From e71087605128c5335da0f717e47b0375fe2958c5 Mon Sep 17 00:00:00 2001 From: gatecat Date: Fri, 28 Mar 2025 09:47:34 +0100 Subject: [PATCH 1/2] Simplify board initialisation and get it back working again --- mcu_soc/chipflow.toml | 1 + mcu_soc/design/steps/board.py | 117 ++++++++++++---------------------- 2 files changed, 43 insertions(+), 75 deletions(-) diff --git a/mcu_soc/chipflow.toml b/mcu_soc/chipflow.toml index 3bddb91..c82200e 100644 --- a/mcu_soc/chipflow.toml +++ b/mcu_soc/chipflow.toml @@ -6,6 +6,7 @@ soc = "design.design:MySoC" [chipflow.steps] sim = "design.steps.sim:MySimStep" +board = "design.steps.board:MyBoardStep" silicon = "chipflow_lib.steps.silicon:SiliconStep" software = "design.steps.software:MySoftwareStep" diff --git a/mcu_soc/design/steps/board.py b/mcu_soc/design/steps/board.py index 2f13e64..784b29e 100644 --- a/mcu_soc/design/steps/board.py +++ b/mcu_soc/design/steps/board.py @@ -4,6 +4,7 @@ from amaranth import * from amaranth.lib import wiring +from amaranth.lib.cdc import ResetSynchronizer from amaranth.lib.wiring import connect, flipped from amaranth.build import Resource, Subsignal, Pins, Attrs @@ -17,84 +18,51 @@ def elaborate(self, platform): m.submodules.soc = soc = MySoC() m.domains += ClockDomain("sync") - m.submodules.clock_reset_provider = platform.providers.ClockResetProvider() - m.submodules.spiflash_provider = spiflash_provider = platform.providers.QSPIFlashProvider() - connect(m, flipped(spiflash_provider.pins), soc.flash) - - m.submodules.led_gpio_provider = led_gpio_provider = platform.providers.LEDGPIOProvider() - connect(m, flipped(led_gpio_provider.pins), soc.gpio_0) - - m.submodules.uart_provider = uart_provider = platform.providers.UARTProvider() - connect(m, flipped(uart_provider.pins), soc.uart_0) - - # Extra IO on headers - platform.add_resources([ - Resource( - "expansion", - 0, - Subsignal("user_spi0_sck", Pins("0+", conn=("gpio", 0), dir='o')), - Subsignal("user_spi0_copi", Pins("0-", conn=("gpio", 0), dir='o')), - Subsignal("user_spi0_cipo", Pins("1+", conn=("gpio", 0), dir='i')), - Subsignal("user_spi0_csn", Pins("1-", conn=("gpio", 0), dir='o')), - - Subsignal("user_spi1_sck", Pins("2+", conn=("gpio", 0), dir='o')), - Subsignal("user_spi1_copi", Pins("2-", conn=("gpio", 0), dir='o')), - Subsignal("user_spi1_cipo", Pins("3+", conn=("gpio", 0), dir='i')), - Subsignal("user_spi1_csn", Pins("3-", conn=("gpio", 0), dir='o')), - - Subsignal("i2c0_sda", Pins("4+", conn=("gpio", 0), dir='io')), - Subsignal("i2c0_scl", Pins("4-", conn=("gpio", 0), dir='io')), - - Subsignal("motor_pwm0_pwm", Pins("5+", conn=("gpio", 0), dir='o')), - Subsignal("motor_pwm0_dir", Pins("5-", conn=("gpio", 0), dir='o')), - Subsignal("motor_pwm0_stop", Pins("6+", conn=("gpio", 0), dir='i'), Attrs(PULLMODE="DOWN")), - - Subsignal("motor_pwm1_pwm", Pins("6-", conn=("gpio", 0), dir='o')), - Subsignal("motor_pwm1_dir", Pins("7+", conn=("gpio", 0), dir='o')), - Subsignal("motor_pwm1_stop", Pins("7-", conn=("gpio", 0), dir='i'), Attrs(PULLMODE="DOWN")), - - Subsignal("uart1_rx", Pins("8+", conn=("gpio", 0), dir='i')), - Subsignal("uart1_tx", Pins("8-", conn=("gpio", 0), dir='o')), - - Subsignal("cpu_jtag_tck", Pins("9+", conn=("gpio", 0), dir='i')), - Subsignal("cpu_jtag_tms", Pins("9-", conn=("gpio", 0), dir='i')), - Subsignal("cpu_jtag_tdi", Pins("10+", conn=("gpio", 0), dir='i')), - Subsignal("cpu_jtag_tdo", Pins("10-", conn=("gpio", 0), dir='o')), - Subsignal("cpu_jtag_trst", Pins("11+", conn=("gpio", 0), dir='i')), - - Attrs(IO_TYPE="LVCMOS33", PULLMODE="UP"), + m.d.comb += ClockSignal("sync").eq(platform.request("clk25").i) + + btn_rst = platform.request("button_pwr") + m.submodules.rst_sync = ResetSynchronizer(arst=btn_rst.i, domain="sync") + + flash = platform.request("spi_flash", dir=dict(cs='-', copi='-', cipo='-', wp='-', hold='-')) + # Flash clock requires a special primitive to access in ECP5 + m.submodules.usrmclk = Instance( + "USRMCLK", + i_USRMCLKI=soc.flash.clk.o, + i_USRMCLKTS=ResetSignal(), # tristate in reset for programmer accesss + a_keep=1, + ) + + # Flash IO buffers + m.submodules += Instance( + "OBZ", + o_O=flash.cs.io, + i_I=soc.flash.csn.o, + i_T=ResetSignal(), + ) + + # Connect flash data pins in order + data_pins = ["copi", "cipo", "wp", "hold"] + for i in range(4): + m.submodules += Instance( + "BB", + io_B=getattr(flash, data_pins[i]).io, + i_I=soc.flash.d.o[i], + i_T=~soc.flash.d.oe[i], + o_O=soc.flash.d.i[i] ) - ]) - - exp = platform.request("expansion") - def _connect_interface(interface, name): - pins = dict() - for member in interface.signature.members: - pin, suffix = member.rsplit("_", 2) - assert suffix in ("o", "i", "oe"), suffix - pins[pin] = getattr(interface, member).width - for pin, width in pins.items(): - for i in range(width): - platform_pin = getattr(exp, f"{name}_{pin}{'' if width == 1 else str(i)}") - if hasattr(interface, f"{pin}_i"): - m.d.comb += getattr(interface, f"{pin}_i")[i].eq(platform_pin.i) - if hasattr(interface, f"{pin}_o"): - m.d.comb += platform_pin.o.eq(getattr(interface, f"{pin}_o")[i]) - if hasattr(interface, f"{pin}_oe"): - m.d.comb += platform_pin.oe.eq(getattr(interface, f"{pin}_oe")[i]) - - _connect_interface(soc.user_spi_0, "user_spi0") - _connect_interface(soc.user_spi_1, "user_spi1") - - _connect_interface(soc.i2c_0, "i2c0") - - _connect_interface(soc.motor_pwm0, "motor_pwm0") - _connect_interface(soc.motor_pwm1, "motor_pwm1") - _connect_interface(soc.uart_1, "uart1") + # Connect LEDs to GPIO0 + for i in range(8): + led = platform.request("led", i) + m.d.comb += led.o.eq(soc.gpio_0.gpio.o[i]) - _connect_interface(soc.cpu_jtag, "cpu_jtag") + # Connect UART0 + uart = platform.request("uart") + m.d.comb += [ + uart.tx.o.eq(soc.uart_0.tx.o), + soc.uart_0.rx.i.eq(uart.rx.i), + ] return m @@ -102,7 +70,6 @@ class MyBoardStep(BoardStep): def __init__(self, config): platform = ULX3S_85F_Platform() - platform.providers = board_ulx3s_providers super().__init__(config, platform) From 9cefe766fe4c11c9a8766f4d1a895c85812d0767 Mon Sep 17 00:00:00 2001 From: Rob Taylor Date: Tue, 20 May 2025 02:09:52 +0100 Subject: [PATCH 2/2] wip: board specification --- mcu_soc/chipflow.toml | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/mcu_soc/chipflow.toml b/mcu_soc/chipflow.toml index c82200e..a6a1936 100644 --- a/mcu_soc/chipflow.toml +++ b/mcu_soc/chipflow.toml @@ -11,10 +11,15 @@ silicon = "chipflow_lib.steps.silicon:SiliconStep" software = "design.steps.software:MySoftwareStep" [chipflow.clocks] -default = 'sys_clk' +default = 'clock_1' [chipflow.resets] -default = 'sys_rst_n' +default = 'reset_1' + +[chipflow.boards.ULX3S] +spi_flash = 'soc.flash' +leds = 'soc.gpio_0' +uart = 'soc.uart_0' [chipflow.silicon] process = "ihp_sg13g2" @@ -22,8 +27,8 @@ package = "pga144" [chipflow.silicon.pads] # System -sys_clk = { type = "clock", loc = "114" } -sys_rst_n = { type = "reset", loc = "115" } +clock_1 = { type = "clock", loc = "114" } +reset_1 = { type = "reset", loc = "115" } [chipflow.silicon.power] dvss0 = { type = "power", loc = "1" }