diff --git a/library/SubcircuitLibrary/LH0004/D.lib b/library/SubcircuitLibrary/LH0004/D.lib new file mode 100644 index 000000000..f53bf3e03 --- /dev/null +++ b/library/SubcircuitLibrary/LH0004/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/LH0004/LH0004-cache.lib b/library/SubcircuitLibrary/LH0004/LH0004-cache.lib new file mode 100644 index 000000000..f970ce61c --- /dev/null +++ b/library/SubcircuitLibrary/LH0004/LH0004-cache.lib @@ -0,0 +1,102 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/LH0004/LH0004.cir b/library/SubcircuitLibrary/LH0004/LH0004.cir new file mode 100644 index 000000000..eb210e8b2 --- /dev/null +++ b/library/SubcircuitLibrary/LH0004/LH0004.cir @@ -0,0 +1,28 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\LH0004\LH0004.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/05/25 11:43:58 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_PNP +Q3 Net-_Q2-Pad3_ Net-_Q1-Pad1_ Net-_Q1-Pad2_ eSim_PNP +R3 Net-_Q1-Pad3_ Net-_Q1-Pad2_ 40K +R1 Net-_Q1-Pad1_ Net-_R1-Pad2_ 600K +Q2 Net-_Q2-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_PNP +Q4 Net-_Q4-Pad1_ Net-_Q4-Pad2_ Net-_Q2-Pad3_ eSim_PNP +R2 Net-_Q2-Pad1_ Net-_Q10-Pad1_ 300K +R4 Net-_Q4-Pad1_ Net-_Q10-Pad1_ 300K +R5 Net-_Q1-Pad3_ Net-_Q6-Pad3_ 50K +Q6 Net-_Q5-Pad1_ Net-_Q5-Pad1_ Net-_Q6-Pad3_ eSim_PNP +Q7 Net-_Q10-Pad2_ Net-_Q5-Pad1_ Net-_Q7-Pad3_ eSim_PNP +R7 Net-_Q1-Pad3_ Net-_Q7-Pad3_ 50K +Q5 Net-_Q5-Pad1_ Net-_Q4-Pad1_ Net-_Q5-Pad3_ eSim_NPN +Q8 Net-_Q10-Pad2_ Net-_Q2-Pad1_ Net-_Q5-Pad3_ eSim_NPN +R6 Net-_Q5-Pad3_ Net-_Q10-Pad1_ 50K +Q9 Net-_Q1-Pad3_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_PNP +U1 Net-_Q2-Pad1_ Net-_Q2-Pad2_ Net-_Q10-Pad1_ Net-_Q4-Pad2_ Net-_Q4-Pad1_ Net-_Q1-Pad1_ Net-_R1-Pad2_ Net-_Q10-Pad3_ Net-_Q1-Pad3_ Net-_Q10-Pad2_ PORT + +.end diff --git a/library/SubcircuitLibrary/LH0004/LH0004.cir.out b/library/SubcircuitLibrary/LH0004/LH0004.cir.out new file mode 100644 index 000000000..d4a9a1404 --- /dev/null +++ b/library/SubcircuitLibrary/LH0004/LH0004.cir.out @@ -0,0 +1,31 @@ +* c:\fossee\esim\library\subcircuitlibrary\lh0004\lh0004.cir + +.include PNP.lib +.include NPN.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2907A +q3 net-_q2-pad3_ net-_q1-pad1_ net-_q1-pad2_ Q2N2907A +r3 net-_q1-pad3_ net-_q1-pad2_ 40k +r1 net-_q1-pad1_ net-_r1-pad2_ 600k +q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2907A +q4 net-_q4-pad1_ net-_q4-pad2_ net-_q2-pad3_ Q2N2907A +r2 net-_q2-pad1_ net-_q10-pad1_ 300k +r4 net-_q4-pad1_ net-_q10-pad1_ 300k +r5 net-_q1-pad3_ net-_q6-pad3_ 50k +q6 net-_q5-pad1_ net-_q5-pad1_ net-_q6-pad3_ Q2N2907A +q7 net-_q10-pad2_ net-_q5-pad1_ net-_q7-pad3_ Q2N2907A +r7 net-_q1-pad3_ net-_q7-pad3_ 50k +q5 net-_q5-pad1_ net-_q4-pad1_ net-_q5-pad3_ Q2N2222 +q8 net-_q10-pad2_ net-_q2-pad1_ net-_q5-pad3_ Q2N2222 +r6 net-_q5-pad3_ net-_q10-pad1_ 50k +q9 net-_q1-pad3_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2907A +* u1 net-_q2-pad1_ net-_q2-pad2_ net-_q10-pad1_ net-_q4-pad2_ net-_q4-pad1_ net-_q1-pad1_ net-_r1-pad2_ net-_q10-pad3_ net-_q1-pad3_ net-_q10-pad2_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/LH0004/LH0004.pro b/library/SubcircuitLibrary/LH0004/LH0004.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/LH0004/LH0004.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/LH0004/LH0004.sch b/library/SubcircuitLibrary/LH0004/LH0004.sch new file mode 100644 index 000000000..c565942ee --- /dev/null +++ b/library/SubcircuitLibrary/LH0004/LH0004.sch @@ -0,0 +1,462 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_PNP Q1 +U 1 1 68412DDE +P 4300 2350 +F 0 "Q1" H 4200 2400 50 0000 R CNN +F 1 "eSim_PNP" H 4250 2500 50 0000 R CNN +F 2 "" H 4500 2450 29 0000 C CNN +F 3 "" H 4300 2350 60 0000 C CNN + 1 4300 2350 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q3 +U 1 1 68412E2C +P 4650 3000 +F 0 "Q3" H 4550 3050 50 0000 R CNN +F 1 "eSim_PNP" H 4600 3150 50 0000 R CNN +F 2 "" H 4850 3100 29 0000 C CNN +F 3 "" H 4650 3000 60 0000 C CNN + 1 4650 3000 + 1 0 0 1 +$EndComp +$Comp +L resistor R3 +U 1 1 68412E7F +P 4700 1950 +F 0 "R3" H 4750 2080 50 0000 C CNN +F 1 "40K" H 4750 1900 50 0000 C CNN +F 2 "" H 4750 1930 30 0000 C CNN +F 3 "" V 4750 2000 30 0000 C CNN + 1 4700 1950 + 0 1 1 0 +$EndComp +$Comp +L resistor R1 +U 1 1 68412FBE +P 4150 3300 +F 0 "R1" H 4200 3430 50 0000 C CNN +F 1 "600K" H 4200 3250 50 0000 C CNN +F 2 "" H 4200 3280 30 0000 C CNN +F 3 "" V 4200 3350 30 0000 C CNN + 1 4150 3300 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q2 +U 1 1 68412FF4 +P 4300 4050 +F 0 "Q2" H 4200 4100 50 0000 R CNN +F 1 "eSim_PNP" H 4250 4200 50 0000 R CNN +F 2 "" H 4500 4150 29 0000 C CNN +F 3 "" H 4300 4050 60 0000 C CNN + 1 4300 4050 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q4 +U 1 1 6841304F +P 5100 4050 +F 0 "Q4" H 5000 4100 50 0000 R CNN +F 1 "eSim_PNP" H 5050 4200 50 0000 R CNN +F 2 "" H 5300 4150 29 0000 C CNN +F 3 "" H 5100 4050 60 0000 C CNN + 1 5100 4050 + -1 0 0 1 +$EndComp +$Comp +L resistor R2 +U 1 1 6841308D +P 4350 4850 +F 0 "R2" H 4400 4980 50 0000 C CNN +F 1 "300K" H 4400 4800 50 0000 C CNN +F 2 "" H 4400 4830 30 0000 C CNN +F 3 "" V 4400 4900 30 0000 C CNN + 1 4350 4850 + 0 1 1 0 +$EndComp +$Comp +L resistor R4 +U 1 1 68413107 +P 4950 4850 +F 0 "R4" H 5000 4980 50 0000 C CNN +F 1 "300K" H 5000 4800 50 0000 C CNN +F 2 "" H 5000 4830 30 0000 C CNN +F 3 "" V 5000 4900 30 0000 C CNN + 1 4950 4850 + 0 1 1 0 +$EndComp +$Comp +L resistor R5 +U 1 1 68413149 +P 5650 2100 +F 0 "R5" H 5700 2230 50 0000 C CNN +F 1 "50K" H 5700 2050 50 0000 C CNN +F 2 "" H 5700 2080 30 0000 C CNN +F 3 "" V 5700 2150 30 0000 C CNN + 1 5650 2100 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q6 +U 1 1 684131C2 +P 5800 3000 +F 0 "Q6" H 5700 3050 50 0000 R CNN +F 1 "eSim_PNP" H 5750 3150 50 0000 R CNN +F 2 "" H 6000 3100 29 0000 C CNN +F 3 "" H 5800 3000 60 0000 C CNN + 1 5800 3000 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q7 +U 1 1 68413204 +P 6400 3000 +F 0 "Q7" H 6300 3050 50 0000 R CNN +F 1 "eSim_PNP" H 6350 3150 50 0000 R CNN +F 2 "" H 6600 3100 29 0000 C CNN +F 3 "" H 6400 3000 60 0000 C CNN + 1 6400 3000 + 1 0 0 1 +$EndComp +$Comp +L resistor R7 +U 1 1 68413253 +P 6450 2100 +F 0 "R7" H 6500 2230 50 0000 C CNN +F 1 "50K" H 6500 2050 50 0000 C CNN +F 2 "" H 6500 2080 30 0000 C CNN +F 3 "" V 6500 2150 30 0000 C CNN + 1 6450 2100 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q5 +U 1 1 68413293 +P 5600 4500 +F 0 "Q5" H 5500 4550 50 0000 R CNN +F 1 "eSim_NPN" H 5550 4650 50 0000 R CNN +F 2 "" H 5800 4600 29 0000 C CNN +F 3 "" H 5600 4500 60 0000 C CNN + 1 5600 4500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q8 +U 1 1 684133A8 +P 6600 4500 +F 0 "Q8" H 6500 4550 50 0000 R CNN +F 1 "eSim_NPN" H 6550 4650 50 0000 R CNN +F 2 "" H 6800 4600 29 0000 C CNN +F 3 "" H 6600 4500 60 0000 C CNN + 1 6600 4500 + -1 0 0 -1 +$EndComp +$Comp +L resistor R6 +U 1 1 684136BF +P 6050 4850 +F 0 "R6" H 6100 4980 50 0000 C CNN +F 1 "50K" H 6100 4800 50 0000 C CNN +F 2 "" H 6100 4830 30 0000 C CNN +F 3 "" V 6100 4900 30 0000 C CNN + 1 6050 4850 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q9 +U 1 1 6841371F +P 7200 2800 +F 0 "Q9" H 7100 2850 50 0000 R CNN +F 1 "eSim_NPN" H 7150 2950 50 0000 R CNN +F 2 "" H 7400 2900 29 0000 C CNN +F 3 "" H 7200 2800 60 0000 C CNN + 1 7200 2800 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q10 +U 1 1 68413DCF +P 7200 3800 +F 0 "Q10" H 7100 3850 50 0000 R CNN +F 1 "eSim_PNP" H 7150 3950 50 0000 R CNN +F 2 "" H 7400 3900 29 0000 C CNN +F 3 "" H 7200 3800 60 0000 C CNN + 1 7200 3800 + 1 0 0 1 +$EndComp +Wire Wire Line + 4500 2350 4750 2350 +Wire Wire Line + 4750 2150 4750 2800 +Connection ~ 4750 2350 +Wire Wire Line + 4200 2550 4200 3200 +Wire Wire Line + 3850 3000 4450 3000 +Connection ~ 4200 3000 +Wire Wire Line + 4400 3850 5000 3850 +Wire Wire Line + 4750 3850 4750 3200 +Connection ~ 4750 3850 +Wire Wire Line + 4400 4250 4400 4750 +Wire Wire Line + 5000 4250 5000 4750 +Wire Wire Line + 4400 5050 4400 5400 +Wire Wire Line + 4400 5400 7550 5400 +Wire Wire Line + 6100 5400 6100 5050 +Wire Wire Line + 5000 5050 5000 5400 +Connection ~ 5000 5400 +Wire Wire Line + 3850 4500 5400 4500 +Connection ~ 5000 4500 +Wire Wire Line + 6500 3200 6500 4300 +Wire Wire Line + 5700 3200 5700 4300 +Wire Wire Line + 5700 3500 6100 3500 +Wire Wire Line + 6100 3500 6100 3000 +Wire Wire Line + 6000 3000 6200 3000 +Connection ~ 5700 3500 +Connection ~ 6100 3000 +Wire Wire Line + 5700 2300 5700 2800 +Wire Wire Line + 6500 2800 6500 2300 +Wire Wire Line + 4200 2150 4200 1550 +Wire Wire Line + 4200 1550 7500 1550 +Wire Wire Line + 7300 1550 7300 2600 +Wire Wire Line + 6500 2000 6500 1550 +Connection ~ 6500 1550 +Wire Wire Line + 5700 2000 5700 1550 +Connection ~ 5700 1550 +Wire Wire Line + 4750 1850 4750 1550 +Connection ~ 4750 1550 +Wire Wire Line + 3850 4300 6900 4300 +Wire Wire Line + 6900 4300 6900 4500 +Wire Wire Line + 6900 4500 6800 4500 +Connection ~ 4400 4300 +Wire Wire Line + 5700 4700 6500 4700 +Wire Wire Line + 6100 4700 6100 4750 +Connection ~ 6100 4700 +Wire Wire Line + 7300 5400 7300 4000 +Connection ~ 6100 5400 +Wire Wire Line + 7300 3000 7300 3600 +Wire Wire Line + 6500 3300 6900 3300 +Wire Wire Line + 6900 2800 7000 2800 +Connection ~ 6500 3300 +$Comp +L PORT U1 +U 6 1 6841456E +P 3600 3000 +F 0 "U1" H 3650 3100 30 0000 C CNN +F 1 "PORT" H 3600 3000 30 0000 C CNN +F 2 "" H 3600 3000 60 0000 C CNN +F 3 "" H 3600 3000 60 0000 C CNN + 6 3600 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 684145EF +P 7800 4100 +F 0 "U1" H 7850 4200 30 0000 C CNN +F 1 "PORT" H 7800 4100 30 0000 C CNN +F 2 "" H 7800 4100 60 0000 C CNN +F 3 "" H 7800 4100 60 0000 C CNN + 10 7800 4100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 9 1 6841462C +P 7750 1550 +F 0 "U1" H 7800 1650 30 0000 C CNN +F 1 "PORT" H 7750 1550 30 0000 C CNN +F 2 "" H 7750 1550 60 0000 C CNN +F 3 "" H 7750 1550 60 0000 C CNN + 9 7750 1550 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 6841466B +P 3600 3750 +F 0 "U1" H 3650 3850 30 0000 C CNN +F 1 "PORT" H 3600 3750 30 0000 C CNN +F 2 "" H 3600 3750 60 0000 C CNN +F 3 "" H 3600 3750 60 0000 C CNN + 4 3600 3750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 684146B0 +P 3600 3600 +F 0 "U1" H 3650 3700 30 0000 C CNN +F 1 "PORT" H 3600 3600 30 0000 C CNN +F 2 "" H 3600 3600 60 0000 C CNN +F 3 "" H 3600 3600 60 0000 C CNN + 7 3600 3600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 684146F3 +P 7800 3250 +F 0 "U1" H 7850 3350 30 0000 C CNN +F 1 "PORT" H 7800 3250 30 0000 C CNN +F 2 "" H 7800 3250 60 0000 C CNN +F 3 "" H 7800 3250 60 0000 C CNN + 8 7800 3250 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 1 1 68414738 +P 3600 4300 +F 0 "U1" H 3650 4400 30 0000 C CNN +F 1 "PORT" H 3600 4300 30 0000 C CNN +F 2 "" H 3600 4300 60 0000 C CNN +F 3 "" H 3600 4300 60 0000 C CNN + 1 3600 4300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 684147D4 +P 3600 4050 +F 0 "U1" H 3650 4150 30 0000 C CNN +F 1 "PORT" H 3600 4050 30 0000 C CNN +F 2 "" H 3600 4050 60 0000 C CNN +F 3 "" H 3600 4050 60 0000 C CNN + 2 3600 4050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 68414829 +P 3600 4500 +F 0 "U1" H 3650 4600 30 0000 C CNN +F 1 "PORT" H 3600 4500 30 0000 C CNN +F 2 "" H 3600 4500 60 0000 C CNN +F 3 "" H 3600 4500 60 0000 C CNN + 5 3600 4500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 68414874 +P 7800 5400 +F 0 "U1" H 7850 5500 30 0000 C CNN +F 1 "PORT" H 7800 5400 30 0000 C CNN +F 2 "" H 7800 5400 60 0000 C CNN +F 3 "" H 7800 5400 60 0000 C CNN + 3 7800 5400 + -1 0 0 1 +$EndComp +Wire Wire Line + 3850 3600 4200 3600 +Wire Wire Line + 4200 3600 4200 3500 +Wire Wire Line + 3850 3750 5400 3750 +Wire Wire Line + 5400 3750 5400 4050 +Wire Wire Line + 5400 4050 5300 4050 +Wire Wire Line + 3850 4050 4100 4050 +Connection ~ 7300 5400 +Connection ~ 6900 3300 +Wire Wire Line + 7300 3250 7550 3250 +Connection ~ 7300 3250 +Connection ~ 7300 1550 +Wire Wire Line + 6900 2800 6900 3800 +Wire Wire Line + 6900 3800 7000 3800 +Wire Wire Line + 7550 4100 6500 4100 +Connection ~ 6500 4100 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/LH0004/LH0004.sub b/library/SubcircuitLibrary/LH0004/LH0004.sub new file mode 100644 index 000000000..910480465 --- /dev/null +++ b/library/SubcircuitLibrary/LH0004/LH0004.sub @@ -0,0 +1,25 @@ +* Subcircuit LH0004 +.subckt LH0004 net-_q2-pad1_ net-_q2-pad2_ net-_q10-pad1_ net-_q4-pad2_ net-_q4-pad1_ net-_q1-pad1_ net-_r1-pad2_ net-_q10-pad3_ net-_q1-pad3_ net-_q10-pad2_ +* c:\fossee\esim\library\subcircuitlibrary\lh0004\lh0004.cir +.include PNP.lib +.include NPN.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2907A +q3 net-_q2-pad3_ net-_q1-pad1_ net-_q1-pad2_ Q2N2907A +r3 net-_q1-pad3_ net-_q1-pad2_ 40k +r1 net-_q1-pad1_ net-_r1-pad2_ 600k +q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2907A +q4 net-_q4-pad1_ net-_q4-pad2_ net-_q2-pad3_ Q2N2907A +r2 net-_q2-pad1_ net-_q10-pad1_ 300k +r4 net-_q4-pad1_ net-_q10-pad1_ 300k +r5 net-_q1-pad3_ net-_q6-pad3_ 50k +q6 net-_q5-pad1_ net-_q5-pad1_ net-_q6-pad3_ Q2N2907A +q7 net-_q10-pad2_ net-_q5-pad1_ net-_q7-pad3_ Q2N2907A +r7 net-_q1-pad3_ net-_q7-pad3_ 50k +q5 net-_q5-pad1_ net-_q4-pad1_ net-_q5-pad3_ Q2N2222 +q8 net-_q10-pad2_ net-_q2-pad1_ net-_q5-pad3_ Q2N2222 +r6 net-_q5-pad3_ net-_q10-pad1_ 50k +q9 net-_q1-pad3_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2907A +* Control Statements + +.ends LH0004 \ No newline at end of file diff --git a/library/SubcircuitLibrary/LH0004/LH0004_Previous_Values.xml b/library/SubcircuitLibrary/LH0004/LH0004_Previous_Values.xml new file mode 100644 index 000000000..4294822a8 --- /dev/null +++ b/library/SubcircuitLibrary/LH0004/LH0004_Previous_Values.xml @@ -0,0 +1 @@ +C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/LH0004/NPN.lib b/library/SubcircuitLibrary/LH0004/NPN.lib new file mode 100644 index 000000000..be5f3073a --- /dev/null +++ b/library/SubcircuitLibrary/LH0004/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/LH0004/PNP.lib b/library/SubcircuitLibrary/LH0004/PNP.lib new file mode 100644 index 000000000..7edda0eab --- /dev/null +++ b/library/SubcircuitLibrary/LH0004/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/LH0004/analysis b/library/SubcircuitLibrary/LH0004/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/LH0004/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/MC10H160/MC10H160-cache.lib b/library/SubcircuitLibrary/MC10H160/MC10H160-cache.lib new file mode 100644 index 000000000..15b9880ea --- /dev/null +++ b/library/SubcircuitLibrary/MC10H160/MC10H160-cache.lib @@ -0,0 +1,64 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_xor +# +DEF d_xor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 39 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/MC10H160/MC10H160.cir b/library/SubcircuitLibrary/MC10H160/MC10H160.cir new file mode 100644 index 000000000..d9a2b7543 --- /dev/null +++ b/library/SubcircuitLibrary/MC10H160/MC10H160.cir @@ -0,0 +1,22 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\MC10H160\MC10H160.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/09/25 12:10:19 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ d_xor +U2 Net-_U10-Pad5_ Net-_U10-Pad6_ Net-_U11-Pad2_ d_xor +U3 Net-_U10-Pad7_ Net-_U10-Pad9_ Net-_U3-Pad3_ d_xor +U4 Net-_U10-Pad10_ Net-_U10-Pad11_ Net-_U4-Pad3_ d_xor +U5 Net-_U10-Pad12_ Net-_U10-Pad13_ Net-_U5-Pad3_ d_xor +U6 Net-_U10-Pad14_ Net-_U10-Pad15_ Net-_U12-Pad2_ d_xor +U7 Net-_U11-Pad3_ Net-_U3-Pad3_ Net-_U7-Pad3_ d_xor +U8 Net-_U4-Pad3_ Net-_U5-Pad3_ Net-_U12-Pad1_ d_xor +U9 Net-_U7-Pad3_ Net-_U12-Pad3_ Net-_U10-Pad2_ d_xor +U10 ? Net-_U10-Pad2_ Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U10-Pad5_ Net-_U10-Pad6_ Net-_U10-Pad7_ ? Net-_U10-Pad9_ Net-_U10-Pad10_ Net-_U10-Pad11_ Net-_U10-Pad12_ Net-_U10-Pad13_ Net-_U10-Pad14_ Net-_U10-Pad15_ ? PORT +U11 Net-_U1-Pad3_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_xor +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ Net-_U12-Pad3_ d_xor + +.end diff --git a/library/SubcircuitLibrary/MC10H160/MC10H160.cir.out b/library/SubcircuitLibrary/MC10H160/MC10H160.cir.out new file mode 100644 index 000000000..942c19916 --- /dev/null +++ b/library/SubcircuitLibrary/MC10H160/MC10H160.cir.out @@ -0,0 +1,56 @@ +* c:\fossee\esim\library\subcircuitlibrary\mc10h160\mc10h160.cir + +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_xor +* u2 net-_u10-pad5_ net-_u10-pad6_ net-_u11-pad2_ d_xor +* u3 net-_u10-pad7_ net-_u10-pad9_ net-_u3-pad3_ d_xor +* u4 net-_u10-pad10_ net-_u10-pad11_ net-_u4-pad3_ d_xor +* u5 net-_u10-pad12_ net-_u10-pad13_ net-_u5-pad3_ d_xor +* u6 net-_u10-pad14_ net-_u10-pad15_ net-_u12-pad2_ d_xor +* u7 net-_u11-pad3_ net-_u3-pad3_ net-_u7-pad3_ d_xor +* u8 net-_u4-pad3_ net-_u5-pad3_ net-_u12-pad1_ d_xor +* u9 net-_u7-pad3_ net-_u12-pad3_ net-_u10-pad2_ d_xor +* u10 ? net-_u10-pad2_ net-_u1-pad1_ net-_u1-pad2_ net-_u10-pad5_ net-_u10-pad6_ net-_u10-pad7_ ? net-_u10-pad9_ net-_u10-pad10_ net-_u10-pad11_ net-_u10-pad12_ net-_u10-pad13_ net-_u10-pad14_ net-_u10-pad15_ ? port +* u11 net-_u1-pad3_ net-_u11-pad2_ net-_u11-pad3_ d_xor +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_xor +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u1 +a2 [net-_u10-pad5_ net-_u10-pad6_ ] net-_u11-pad2_ u2 +a3 [net-_u10-pad7_ net-_u10-pad9_ ] net-_u3-pad3_ u3 +a4 [net-_u10-pad10_ net-_u10-pad11_ ] net-_u4-pad3_ u4 +a5 [net-_u10-pad12_ net-_u10-pad13_ ] net-_u5-pad3_ u5 +a6 [net-_u10-pad14_ net-_u10-pad15_ ] net-_u12-pad2_ u6 +a7 [net-_u11-pad3_ net-_u3-pad3_ ] net-_u7-pad3_ u7 +a8 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u12-pad1_ u8 +a9 [net-_u7-pad3_ net-_u12-pad3_ ] net-_u10-pad2_ u9 +a10 [net-_u1-pad3_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a11 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u1 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u2 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u3 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u4 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u5 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u6 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u7 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u8 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u9 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u11 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u12 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/MC10H160/MC10H160.pro b/library/SubcircuitLibrary/MC10H160/MC10H160.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/MC10H160/MC10H160.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/MC10H160/MC10H160.sch b/library/SubcircuitLibrary/MC10H160/MC10H160.sch new file mode 100644 index 000000000..c84b91d23 --- /dev/null +++ b/library/SubcircuitLibrary/MC10H160/MC10H160.sch @@ -0,0 +1,435 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:MC10H160-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_xor U1 +U 1 1 68467D6D +P 3550 1500 +F 0 "U1" H 3550 1500 60 0000 C CNN +F 1 "d_xor" H 3600 1600 47 0000 C CNN +F 2 "" H 3550 1500 60 0000 C CNN +F 3 "" H 3550 1500 60 0000 C CNN + 1 3550 1500 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U2 +U 1 1 68467DC9 +P 3550 1950 +F 0 "U2" H 3550 1950 60 0000 C CNN +F 1 "d_xor" H 3600 2050 47 0000 C CNN +F 2 "" H 3550 1950 60 0000 C CNN +F 3 "" H 3550 1950 60 0000 C CNN + 1 3550 1950 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U3 +U 1 1 68467DED +P 3550 2400 +F 0 "U3" H 3550 2400 60 0000 C CNN +F 1 "d_xor" H 3600 2500 47 0000 C CNN +F 2 "" H 3550 2400 60 0000 C CNN +F 3 "" H 3550 2400 60 0000 C CNN + 1 3550 2400 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U4 +U 1 1 68467E22 +P 3550 3000 +F 0 "U4" H 3550 3000 60 0000 C CNN +F 1 "d_xor" H 3600 3100 47 0000 C CNN +F 2 "" H 3550 3000 60 0000 C CNN +F 3 "" H 3550 3000 60 0000 C CNN + 1 3550 3000 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U5 +U 1 1 68467E62 +P 3550 3400 +F 0 "U5" H 3550 3400 60 0000 C CNN +F 1 "d_xor" H 3600 3500 47 0000 C CNN +F 2 "" H 3550 3400 60 0000 C CNN +F 3 "" H 3550 3400 60 0000 C CNN + 1 3550 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U6 +U 1 1 68467E95 +P 3550 3800 +F 0 "U6" H 3550 3800 60 0000 C CNN +F 1 "d_xor" H 3600 3900 47 0000 C CNN +F 2 "" H 3550 3800 60 0000 C CNN +F 3 "" H 3550 3800 60 0000 C CNN + 1 3550 3800 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U7 +U 1 1 68467ED1 +P 5650 1900 +F 0 "U7" H 5650 1900 60 0000 C CNN +F 1 "d_xor" H 5700 2000 47 0000 C CNN +F 2 "" H 5650 1900 60 0000 C CNN +F 3 "" H 5650 1900 60 0000 C CNN + 1 5650 1900 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U8 +U 1 1 68467F48 +P 4650 3150 +F 0 "U8" H 4650 3150 60 0000 C CNN +F 1 "d_xor" H 4700 3250 47 0000 C CNN +F 2 "" H 4650 3150 60 0000 C CNN +F 3 "" H 4650 3150 60 0000 C CNN + 1 4650 3150 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U9 +U 1 1 68467FA4 +P 6750 2450 +F 0 "U9" H 6750 2450 60 0000 C CNN +F 1 "d_xor" H 6800 2550 47 0000 C CNN +F 2 "" H 6750 2450 60 0000 C CNN +F 3 "" H 6750 2450 60 0000 C CNN + 1 6750 2450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U10 +U 3 1 68468010 +P 2650 1400 +F 0 "U10" H 2700 1500 30 0000 C CNN +F 1 "PORT" H 2650 1400 30 0000 C CNN +F 2 "" H 2650 1400 60 0000 C CNN +F 3 "" H 2650 1400 60 0000 C CNN + 3 2650 1400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U10 +U 4 1 68468099 +P 2650 1550 +F 0 "U10" H 2700 1650 30 0000 C CNN +F 1 "PORT" H 2650 1550 30 0000 C CNN +F 2 "" H 2650 1550 60 0000 C CNN +F 3 "" H 2650 1550 60 0000 C CNN + 4 2650 1550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U10 +U 5 1 684680C4 +P 2650 1800 +F 0 "U10" H 2700 1900 30 0000 C CNN +F 1 "PORT" H 2650 1800 30 0000 C CNN +F 2 "" H 2650 1800 60 0000 C CNN +F 3 "" H 2650 1800 60 0000 C CNN + 5 2650 1800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U10 +U 6 1 684680F1 +P 2650 1950 +F 0 "U10" H 2700 2050 30 0000 C CNN +F 1 "PORT" H 2650 1950 30 0000 C CNN +F 2 "" H 2650 1950 60 0000 C CNN +F 3 "" H 2650 1950 60 0000 C CNN + 6 2650 1950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U10 +U 14 1 68468120 +P 2650 3650 +F 0 "U10" H 2700 3750 30 0000 C CNN +F 1 "PORT" H 2650 3650 30 0000 C CNN +F 2 "" H 2650 3650 60 0000 C CNN +F 3 "" H 2650 3650 60 0000 C CNN + 14 2650 3650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U10 +U 15 1 68468151 +P 2650 3800 +F 0 "U10" H 2700 3900 30 0000 C CNN +F 1 "PORT" H 2650 3800 30 0000 C CNN +F 2 "" H 2650 3800 60 0000 C CNN +F 3 "" H 2650 3800 60 0000 C CNN + 15 2650 3800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U10 +U 16 1 68468184 +P 6750 1250 +F 0 "U10" H 6800 1350 30 0000 C CNN +F 1 "PORT" H 6750 1250 30 0000 C CNN +F 2 "" H 6750 1250 60 0000 C CNN +F 3 "" H 6750 1250 60 0000 C CNN + 16 6750 1250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U10 +U 7 1 684681B9 +P 2650 2250 +F 0 "U10" H 2700 2350 30 0000 C CNN +F 1 "PORT" H 2650 2250 30 0000 C CNN +F 2 "" H 2650 2250 60 0000 C CNN +F 3 "" H 2650 2250 60 0000 C CNN + 7 2650 2250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U10 +U 8 1 684681F6 +P 6750 1450 +F 0 "U10" H 6800 1550 30 0000 C CNN +F 1 "PORT" H 6750 1450 30 0000 C CNN +F 2 "" H 6750 1450 60 0000 C CNN +F 3 "" H 6750 1450 60 0000 C CNN + 8 6750 1450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U10 +U 1 1 6846822F +P 6750 1650 +F 0 "U10" H 6800 1750 30 0000 C CNN +F 1 "PORT" H 6750 1650 30 0000 C CNN +F 2 "" H 6750 1650 60 0000 C CNN +F 3 "" H 6750 1650 60 0000 C CNN + 1 6750 1650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U10 +U 9 1 68468272 +P 2650 2400 +F 0 "U10" H 2700 2500 30 0000 C CNN +F 1 "PORT" H 2650 2400 30 0000 C CNN +F 2 "" H 2650 2400 60 0000 C CNN +F 3 "" H 2650 2400 60 0000 C CNN + 9 2650 2400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U10 +U 2 1 684682AF +P 7550 2400 +F 0 "U10" H 7600 2500 30 0000 C CNN +F 1 "PORT" H 7550 2400 30 0000 C CNN +F 2 "" H 7550 2400 60 0000 C CNN +F 3 "" H 7550 2400 60 0000 C CNN + 2 7550 2400 + -1 0 0 1 +$EndComp +$Comp +L PORT U10 +U 10 1 684682F6 +P 2650 2900 +F 0 "U10" H 2700 3000 30 0000 C CNN +F 1 "PORT" H 2650 2900 30 0000 C CNN +F 2 "" H 2650 2900 60 0000 C CNN +F 3 "" H 2650 2900 60 0000 C CNN + 10 2650 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U10 +U 11 1 68468339 +P 2650 3050 +F 0 "U10" H 2700 3150 30 0000 C CNN +F 1 "PORT" H 2650 3050 30 0000 C CNN +F 2 "" H 2650 3050 60 0000 C CNN +F 3 "" H 2650 3050 60 0000 C CNN + 11 2650 3050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U10 +U 12 1 6846837C +P 2650 3250 +F 0 "U10" H 2700 3350 30 0000 C CNN +F 1 "PORT" H 2650 3250 30 0000 C CNN +F 2 "" H 2650 3250 60 0000 C CNN +F 3 "" H 2650 3250 60 0000 C CNN + 12 2650 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U10 +U 13 1 684683C1 +P 2650 3400 +F 0 "U10" H 2700 3500 30 0000 C CNN +F 1 "PORT" H 2650 3400 30 0000 C CNN +F 2 "" H 2650 3400 60 0000 C CNN +F 3 "" H 2650 3400 60 0000 C CNN + 13 2650 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U11 +U 1 1 68468695 +P 4650 1700 +F 0 "U11" H 4650 1700 60 0000 C CNN +F 1 "d_xor" H 4700 1800 47 0000 C CNN +F 2 "" H 4650 1700 60 0000 C CNN +F 3 "" H 4650 1700 60 0000 C CNN + 1 4650 1700 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U12 +U 1 1 6846874F +P 5650 3400 +F 0 "U12" H 5650 3400 60 0000 C CNN +F 1 "d_xor" H 5700 3500 47 0000 C CNN +F 2 "" H 5650 3400 60 0000 C CNN +F 3 "" H 5650 3400 60 0000 C CNN + 1 5650 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2900 1400 3100 1400 +Wire Wire Line + 2900 1550 3100 1550 +Wire Wire Line + 3100 1550 3100 1500 +Wire Wire Line + 2900 1800 3100 1800 +Wire Wire Line + 3100 1800 3100 1850 +Wire Wire Line + 2900 1950 3100 1950 +Wire Wire Line + 2900 2250 3100 2250 +Wire Wire Line + 3100 2250 3100 2300 +Wire Wire Line + 2900 2400 3100 2400 +Wire Wire Line + 2900 2900 3100 2900 +Wire Wire Line + 2900 3050 3100 3050 +Wire Wire Line + 3100 3050 3100 3000 +Wire Wire Line + 2900 3250 3100 3250 +Wire Wire Line + 3100 3250 3100 3300 +Wire Wire Line + 2900 3400 3100 3400 +Wire Wire Line + 2900 3650 3100 3650 +Wire Wire Line + 3100 3650 3100 3700 +Wire Wire Line + 2900 3800 3100 3800 +Wire Wire Line + 4000 1450 4200 1450 +Wire Wire Line + 4200 1450 4200 1600 +Wire Wire Line + 4000 1900 4200 1900 +Wire Wire Line + 4200 1900 4200 1700 +Wire Wire Line + 4000 2350 5200 2350 +Wire Wire Line + 5200 2350 5200 1900 +Wire Wire Line + 5100 1650 5200 1650 +Wire Wire Line + 5200 1650 5200 1800 +Wire Wire Line + 6100 1850 6300 1850 +Wire Wire Line + 6300 1850 6300 2350 +Wire Wire Line + 4000 2950 4200 2950 +Wire Wire Line + 4200 2950 4200 3050 +Wire Wire Line + 4000 3350 4200 3350 +Wire Wire Line + 4200 3350 4200 3150 +Wire Wire Line + 4000 3750 5200 3750 +Wire Wire Line + 5200 3750 5200 3400 +Wire Wire Line + 5100 3100 5200 3100 +Wire Wire Line + 5200 3100 5200 3300 +Wire Wire Line + 6100 3350 6300 3350 +Wire Wire Line + 6300 3350 6300 2450 +Wire Wire Line + 7200 2400 7300 2400 +NoConn ~ 7000 1250 +NoConn ~ 7000 1450 +NoConn ~ 7000 1650 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/MC10H160/MC10H160.sub b/library/SubcircuitLibrary/MC10H160/MC10H160.sub new file mode 100644 index 000000000..03e8d26f3 --- /dev/null +++ b/library/SubcircuitLibrary/MC10H160/MC10H160.sub @@ -0,0 +1,50 @@ +* Subcircuit MC10H160 +.subckt MC10H160 ? net-_u10-pad2_ net-_u1-pad1_ net-_u1-pad2_ net-_u10-pad5_ net-_u10-pad6_ net-_u10-pad7_ ? net-_u10-pad9_ net-_u10-pad10_ net-_u10-pad11_ net-_u10-pad12_ net-_u10-pad13_ net-_u10-pad14_ net-_u10-pad15_ ? +* c:\fossee\esim\library\subcircuitlibrary\mc10h160\mc10h160.cir +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_xor +* u2 net-_u10-pad5_ net-_u10-pad6_ net-_u11-pad2_ d_xor +* u3 net-_u10-pad7_ net-_u10-pad9_ net-_u3-pad3_ d_xor +* u4 net-_u10-pad10_ net-_u10-pad11_ net-_u4-pad3_ d_xor +* u5 net-_u10-pad12_ net-_u10-pad13_ net-_u5-pad3_ d_xor +* u6 net-_u10-pad14_ net-_u10-pad15_ net-_u12-pad2_ d_xor +* u7 net-_u11-pad3_ net-_u3-pad3_ net-_u7-pad3_ d_xor +* u8 net-_u4-pad3_ net-_u5-pad3_ net-_u12-pad1_ d_xor +* u9 net-_u7-pad3_ net-_u12-pad3_ net-_u10-pad2_ d_xor +* u11 net-_u1-pad3_ net-_u11-pad2_ net-_u11-pad3_ d_xor +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_xor +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u1 +a2 [net-_u10-pad5_ net-_u10-pad6_ ] net-_u11-pad2_ u2 +a3 [net-_u10-pad7_ net-_u10-pad9_ ] net-_u3-pad3_ u3 +a4 [net-_u10-pad10_ net-_u10-pad11_ ] net-_u4-pad3_ u4 +a5 [net-_u10-pad12_ net-_u10-pad13_ ] net-_u5-pad3_ u5 +a6 [net-_u10-pad14_ net-_u10-pad15_ ] net-_u12-pad2_ u6 +a7 [net-_u11-pad3_ net-_u3-pad3_ ] net-_u7-pad3_ u7 +a8 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u12-pad1_ u8 +a9 [net-_u7-pad3_ net-_u12-pad3_ ] net-_u10-pad2_ u9 +a10 [net-_u1-pad3_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a11 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u1 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u2 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u3 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u4 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u5 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u6 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u7 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u8 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u9 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u11 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u12 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends MC10H160 \ No newline at end of file diff --git a/library/SubcircuitLibrary/MC10H160/MC10H160_Previous_Values.xml b/library/SubcircuitLibrary/MC10H160/MC10H160_Previous_Values.xml new file mode 100644 index 000000000..cb15384cb --- /dev/null +++ b/library/SubcircuitLibrary/MC10H160/MC10H160_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_xord_xord_xord_xord_xord_xord_xord_xord_xord_xord_xor \ No newline at end of file diff --git a/library/SubcircuitLibrary/MC10H160/analysis b/library/SubcircuitLibrary/MC10H160/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/MC10H160/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN7407/D.lib b/library/SubcircuitLibrary/SN7407/D.lib new file mode 100644 index 000000000..f53bf3e03 --- /dev/null +++ b/library/SubcircuitLibrary/SN7407/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/SN7407/NPN.lib b/library/SubcircuitLibrary/SN7407/NPN.lib new file mode 100644 index 000000000..be5f3073a --- /dev/null +++ b/library/SubcircuitLibrary/SN7407/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/SN7407/SN7407-cache.lib b/library/SubcircuitLibrary/SN7407/SN7407-cache.lib new file mode 100644 index 000000000..7e9c6731b --- /dev/null +++ b/library/SubcircuitLibrary/SN7407/SN7407-cache.lib @@ -0,0 +1,107 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN7407/SN7407.cir b/library/SubcircuitLibrary/SN7407/SN7407.cir new file mode 100644 index 000000000..fe735a2cd --- /dev/null +++ b/library/SubcircuitLibrary/SN7407/SN7407.cir @@ -0,0 +1,71 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\SN7407\SN7407.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/06/25 11:06:26 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_D1-Pad2_ eSim_NPN +Q2 Net-_Q2-Pad1_ Net-_Q1-Pad1_ Net-_Q2-Pad3_ eSim_NPN +Q3 Net-_Q3-Pad1_ Net-_Q3-Pad2_ Net-_D1-Pad1_ eSim_NPN +Q4 Net-_Q4-Pad1_ Net-_Q3-Pad1_ Net-_D1-Pad1_ eSim_NPN +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +R1 Net-_R1-Pad1_ Net-_Q1-Pad2_ 6K +R2 Net-_R1-Pad1_ Net-_Q2-Pad1_ 3.4K +R3 Net-_Q2-Pad3_ Net-_Q3-Pad2_ 100 +R4 Net-_Q3-Pad2_ Net-_D1-Pad1_ 1K +R5 Net-_R1-Pad1_ Net-_Q3-Pad1_ 1.6K +Q5 Net-_Q5-Pad1_ Net-_Q5-Pad2_ Net-_D2-Pad2_ eSim_NPN +Q6 Net-_Q6-Pad1_ Net-_Q5-Pad1_ Net-_Q6-Pad3_ eSim_NPN +Q7 Net-_Q7-Pad1_ Net-_Q7-Pad2_ Net-_D1-Pad1_ eSim_NPN +Q8 Net-_Q8-Pad1_ Net-_Q7-Pad1_ Net-_D1-Pad1_ eSim_NPN +D2 Net-_D1-Pad1_ Net-_D2-Pad2_ eSim_Diode +R6 Net-_R1-Pad1_ Net-_Q5-Pad2_ 6K +R7 Net-_R1-Pad1_ Net-_Q6-Pad1_ 3.4K +R8 Net-_Q6-Pad3_ Net-_Q7-Pad2_ 100 +R9 Net-_Q7-Pad2_ Net-_D1-Pad1_ 1K +R10 Net-_R1-Pad1_ Net-_Q7-Pad1_ 1.6K +Q9 Net-_Q11-Pad2_ Net-_Q9-Pad2_ Net-_D3-Pad2_ eSim_NPN +Q11 Net-_Q11-Pad1_ Net-_Q11-Pad2_ Net-_Q11-Pad3_ eSim_NPN +Q13 Net-_Q13-Pad1_ Net-_Q13-Pad2_ Net-_D1-Pad1_ eSim_NPN +Q15 Net-_Q15-Pad1_ Net-_Q13-Pad1_ Net-_D1-Pad1_ eSim_NPN +D3 Net-_D1-Pad1_ Net-_D3-Pad2_ eSim_Diode +R11 Net-_R1-Pad1_ Net-_Q9-Pad2_ 6K +R13 Net-_R1-Pad1_ Net-_Q11-Pad1_ 3.4K +R14 Net-_Q11-Pad3_ Net-_Q13-Pad2_ 100 +R15 Net-_Q13-Pad2_ Net-_D1-Pad1_ 1K +R19 Net-_R1-Pad1_ Net-_Q13-Pad1_ 1.6K +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_D4-Pad2_ eSim_NPN +Q12 Net-_Q12-Pad1_ Net-_Q10-Pad1_ Net-_Q12-Pad3_ eSim_NPN +Q14 Net-_Q14-Pad1_ Net-_Q14-Pad2_ Net-_D1-Pad1_ eSim_NPN +Q16 Net-_Q16-Pad1_ Net-_Q14-Pad1_ Net-_D1-Pad1_ eSim_NPN +D4 Net-_D1-Pad1_ Net-_D4-Pad2_ eSim_Diode +R12 Net-_R1-Pad1_ Net-_Q10-Pad2_ 6K +R16 Net-_R1-Pad1_ Net-_Q12-Pad1_ 3.4K +R17 Net-_Q12-Pad3_ Net-_Q14-Pad2_ 100 +R18 Net-_Q14-Pad2_ Net-_D1-Pad1_ 1K +R20 Net-_R1-Pad1_ Net-_Q14-Pad1_ 1.6K +Q17 Net-_Q17-Pad1_ Net-_Q17-Pad2_ Net-_D5-Pad2_ eSim_NPN +Q19 Net-_Q19-Pad1_ Net-_Q17-Pad1_ Net-_Q19-Pad3_ eSim_NPN +Q21 Net-_Q21-Pad1_ Net-_Q21-Pad2_ Net-_D1-Pad1_ eSim_NPN +Q23 Net-_Q23-Pad1_ Net-_Q21-Pad1_ Net-_D1-Pad1_ eSim_NPN +D5 Net-_D1-Pad1_ Net-_D5-Pad2_ eSim_Diode +R21 Net-_R1-Pad1_ Net-_Q17-Pad2_ 6K +R23 Net-_R1-Pad1_ Net-_Q19-Pad1_ 3.4K +R24 Net-_Q19-Pad3_ Net-_Q21-Pad2_ 100 +R25 Net-_Q21-Pad2_ Net-_D1-Pad1_ 1K +R29 Net-_R1-Pad1_ Net-_Q21-Pad1_ 1.6K +Q18 Net-_Q18-Pad1_ Net-_Q18-Pad2_ Net-_D6-Pad2_ eSim_NPN +Q20 Net-_Q20-Pad1_ Net-_Q18-Pad1_ Net-_Q20-Pad3_ eSim_NPN +Q22 Net-_Q22-Pad1_ Net-_Q22-Pad2_ Net-_D1-Pad1_ eSim_NPN +Q24 Net-_Q24-Pad1_ Net-_Q22-Pad1_ Net-_D1-Pad1_ eSim_NPN +D6 Net-_D1-Pad1_ Net-_D6-Pad2_ eSim_Diode +R22 Net-_R1-Pad1_ Net-_Q18-Pad2_ 6K +R26 Net-_R1-Pad1_ Net-_Q20-Pad1_ 3.4K +R27 Net-_Q20-Pad3_ Net-_Q22-Pad2_ 100 +R28 Net-_Q22-Pad2_ Net-_D1-Pad1_ 1K +R30 Net-_R1-Pad1_ Net-_Q22-Pad1_ 1.6K +U1 Net-_D1-Pad2_ Net-_Q4-Pad1_ Net-_D2-Pad2_ Net-_Q8-Pad1_ Net-_D3-Pad2_ Net-_Q15-Pad1_ Net-_D1-Pad1_ Net-_Q16-Pad1_ Net-_D4-Pad2_ Net-_Q23-Pad1_ Net-_D5-Pad2_ Net-_Q24-Pad1_ Net-_D6-Pad2_ Net-_R1-Pad1_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN7407/SN7407.cir.out b/library/SubcircuitLibrary/SN7407/SN7407.cir.out new file mode 100644 index 000000000..f8d1823e0 --- /dev/null +++ b/library/SubcircuitLibrary/SN7407/SN7407.cir.out @@ -0,0 +1,74 @@ +* c:\fossee\esim\library\subcircuitlibrary\sn7407\sn7407.cir + +.include D.lib +.include NPN.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_d1-pad2_ Q2N2222 +q2 net-_q2-pad1_ net-_q1-pad1_ net-_q2-pad3_ Q2N2222 +q3 net-_q3-pad1_ net-_q3-pad2_ net-_d1-pad1_ Q2N2222 +q4 net-_q4-pad1_ net-_q3-pad1_ net-_d1-pad1_ Q2N2222 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +r1 net-_r1-pad1_ net-_q1-pad2_ 6k +r2 net-_r1-pad1_ net-_q2-pad1_ 3.4k +r3 net-_q2-pad3_ net-_q3-pad2_ 100 +r4 net-_q3-pad2_ net-_d1-pad1_ 1k +r5 net-_r1-pad1_ net-_q3-pad1_ 1.6k +q5 net-_q5-pad1_ net-_q5-pad2_ net-_d2-pad2_ Q2N2222 +q6 net-_q6-pad1_ net-_q5-pad1_ net-_q6-pad3_ Q2N2222 +q7 net-_q7-pad1_ net-_q7-pad2_ net-_d1-pad1_ Q2N2222 +q8 net-_q8-pad1_ net-_q7-pad1_ net-_d1-pad1_ Q2N2222 +d2 net-_d1-pad1_ net-_d2-pad2_ 1N4148 +r6 net-_r1-pad1_ net-_q5-pad2_ 6k +r7 net-_r1-pad1_ net-_q6-pad1_ 3.4k +r8 net-_q6-pad3_ net-_q7-pad2_ 100 +r9 net-_q7-pad2_ net-_d1-pad1_ 1k +r10 net-_r1-pad1_ net-_q7-pad1_ 1.6k +q9 net-_q11-pad2_ net-_q9-pad2_ net-_d3-pad2_ Q2N2222 +q11 net-_q11-pad1_ net-_q11-pad2_ net-_q11-pad3_ Q2N2222 +q13 net-_q13-pad1_ net-_q13-pad2_ net-_d1-pad1_ Q2N2222 +q15 net-_q15-pad1_ net-_q13-pad1_ net-_d1-pad1_ Q2N2222 +d3 net-_d1-pad1_ net-_d3-pad2_ 1N4148 +r11 net-_r1-pad1_ net-_q9-pad2_ 6k +r13 net-_r1-pad1_ net-_q11-pad1_ 3.4k +r14 net-_q11-pad3_ net-_q13-pad2_ 100 +r15 net-_q13-pad2_ net-_d1-pad1_ 1k +r19 net-_r1-pad1_ net-_q13-pad1_ 1.6k +q10 net-_q10-pad1_ net-_q10-pad2_ net-_d4-pad2_ Q2N2222 +q12 net-_q12-pad1_ net-_q10-pad1_ net-_q12-pad3_ Q2N2222 +q14 net-_q14-pad1_ net-_q14-pad2_ net-_d1-pad1_ Q2N2222 +q16 net-_q16-pad1_ net-_q14-pad1_ net-_d1-pad1_ Q2N2222 +d4 net-_d1-pad1_ net-_d4-pad2_ 1N4148 +r12 net-_r1-pad1_ net-_q10-pad2_ 6k +r16 net-_r1-pad1_ net-_q12-pad1_ 3.4k +r17 net-_q12-pad3_ net-_q14-pad2_ 100 +r18 net-_q14-pad2_ net-_d1-pad1_ 1k +r20 net-_r1-pad1_ net-_q14-pad1_ 1.6k +q17 net-_q17-pad1_ net-_q17-pad2_ net-_d5-pad2_ Q2N2222 +q19 net-_q19-pad1_ net-_q17-pad1_ net-_q19-pad3_ Q2N2222 +q21 net-_q21-pad1_ net-_q21-pad2_ net-_d1-pad1_ Q2N2222 +q23 net-_q23-pad1_ net-_q21-pad1_ net-_d1-pad1_ Q2N2222 +d5 net-_d1-pad1_ net-_d5-pad2_ 1N4148 +r21 net-_r1-pad1_ net-_q17-pad2_ 6k +r23 net-_r1-pad1_ net-_q19-pad1_ 3.4k +r24 net-_q19-pad3_ net-_q21-pad2_ 100 +r25 net-_q21-pad2_ net-_d1-pad1_ 1k +r29 net-_r1-pad1_ net-_q21-pad1_ 1.6k +q18 net-_q18-pad1_ net-_q18-pad2_ net-_d6-pad2_ Q2N2222 +q20 net-_q20-pad1_ net-_q18-pad1_ net-_q20-pad3_ Q2N2222 +q22 net-_q22-pad1_ net-_q22-pad2_ net-_d1-pad1_ Q2N2222 +q24 net-_q24-pad1_ net-_q22-pad1_ net-_d1-pad1_ Q2N2222 +d6 net-_d1-pad1_ net-_d6-pad2_ 1N4148 +r22 net-_r1-pad1_ net-_q18-pad2_ 6k +r26 net-_r1-pad1_ net-_q20-pad1_ 3.4k +r27 net-_q20-pad3_ net-_q22-pad2_ 100 +r28 net-_q22-pad2_ net-_d1-pad1_ 1k +r30 net-_r1-pad1_ net-_q22-pad1_ 1.6k +* u1 net-_d1-pad2_ net-_q4-pad1_ net-_d2-pad2_ net-_q8-pad1_ net-_d3-pad2_ net-_q15-pad1_ net-_d1-pad1_ net-_q16-pad1_ net-_d4-pad2_ net-_q23-pad1_ net-_d5-pad2_ net-_q24-pad1_ net-_d6-pad2_ net-_r1-pad1_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN7407/SN7407.pro b/library/SubcircuitLibrary/SN7407/SN7407.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/SN7407/SN7407.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN7407/SN7407.sch b/library/SubcircuitLibrary/SN7407/SN7407.sch new file mode 100644 index 000000000..ce193792e --- /dev/null +++ b/library/SubcircuitLibrary/SN7407/SN7407.sch @@ -0,0 +1,1243 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SN7407-cache +EELAYER 25 0 +EELAYER END +$Descr A3 16535 11693 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q1 +U 1 1 68468E27 +P 2050 3200 +F 0 "Q1" H 1950 3250 50 0000 R CNN +F 1 "eSim_NPN" H 2000 3350 50 0000 R CNN +F 2 "" H 2250 3300 29 0000 C CNN +F 3 "" H 2050 3200 60 0000 C CNN + 1 2050 3200 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 68468E68 +P 2650 3450 +F 0 "Q2" H 2550 3500 50 0000 R CNN +F 1 "eSim_NPN" H 2600 3600 50 0000 R CNN +F 2 "" H 2850 3550 29 0000 C CNN +F 3 "" H 2650 3450 60 0000 C CNN + 1 2650 3450 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 68468EC9 +P 3000 4350 +F 0 "Q3" H 2900 4400 50 0000 R CNN +F 1 "eSim_NPN" H 2950 4500 50 0000 R CNN +F 2 "" H 3200 4450 29 0000 C CNN +F 3 "" H 3000 4350 60 0000 C CNN + 1 3000 4350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q4 +U 1 1 68468F2E +P 3850 4000 +F 0 "Q4" H 3750 4050 50 0000 R CNN +F 1 "eSim_NPN" H 3800 4150 50 0000 R CNN +F 2 "" H 4050 4100 29 0000 C CNN +F 3 "" H 3850 4000 60 0000 C CNN + 1 3850 4000 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D1 +U 1 1 68468F62 +P 1700 3850 +F 0 "D1" H 1700 3950 50 0000 C CNN +F 1 "eSim_Diode" H 1700 3750 50 0000 C CNN +F 2 "" H 1700 3850 60 0000 C CNN +F 3 "" H 1700 3850 60 0000 C CNN + 1 1700 3850 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R1 +U 1 1 68468FE4 +P 2000 2550 +F 0 "R1" H 2050 2680 50 0000 C CNN +F 1 "6K" H 2050 2500 50 0000 C CNN +F 2 "" H 2050 2530 30 0000 C CNN +F 3 "" V 2050 2600 30 0000 C CNN + 1 2000 2550 + 0 1 1 0 +$EndComp +$Comp +L resistor R2 +U 1 1 68469074 +P 2700 2700 +F 0 "R2" H 2750 2830 50 0000 C CNN +F 1 "3.4K" H 2750 2650 50 0000 C CNN +F 2 "" H 2750 2680 30 0000 C CNN +F 3 "" V 2750 2750 30 0000 C CNN + 1 2700 2700 + 0 1 1 0 +$EndComp +$Comp +L resistor R3 +U 1 1 684690C1 +P 2700 3900 +F 0 "R3" H 2750 4030 50 0000 C CNN +F 1 "100" H 2750 3850 50 0000 C CNN +F 2 "" H 2750 3880 30 0000 C CNN +F 3 "" V 2750 3950 30 0000 C CNN + 1 2700 3900 + 0 1 1 0 +$EndComp +$Comp +L resistor R4 +U 1 1 68469109 +P 2700 4600 +F 0 "R4" H 2750 4730 50 0000 C CNN +F 1 "1K" H 2750 4550 50 0000 C CNN +F 2 "" H 2750 4580 30 0000 C CNN +F 3 "" V 2750 4650 30 0000 C CNN + 1 2700 4600 + 0 1 1 0 +$EndComp +$Comp +L resistor R5 +U 1 1 68469152 +P 3400 2850 +F 0 "R5" H 3450 2980 50 0000 C CNN +F 1 "1.6K" H 3450 2800 50 0000 C CNN +F 2 "" H 3450 2830 30 0000 C CNN +F 3 "" V 3450 2900 30 0000 C CNN + 1 3400 2850 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q5 +U 1 1 6864E1C9 +P 2050 6300 +F 0 "Q5" H 1950 6350 50 0000 R CNN +F 1 "eSim_NPN" H 2000 6450 50 0000 R CNN +F 2 "" H 2250 6400 29 0000 C CNN +F 3 "" H 2050 6300 60 0000 C CNN + 1 2050 6300 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q6 +U 1 1 6864E1CF +P 2650 6550 +F 0 "Q6" H 2550 6600 50 0000 R CNN +F 1 "eSim_NPN" H 2600 6700 50 0000 R CNN +F 2 "" H 2850 6650 29 0000 C CNN +F 3 "" H 2650 6550 60 0000 C CNN + 1 2650 6550 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q7 +U 1 1 6864E1D5 +P 3000 7450 +F 0 "Q7" H 2900 7500 50 0000 R CNN +F 1 "eSim_NPN" H 2950 7600 50 0000 R CNN +F 2 "" H 3200 7550 29 0000 C CNN +F 3 "" H 3000 7450 60 0000 C CNN + 1 3000 7450 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q8 +U 1 1 6864E1DB +P 3850 7100 +F 0 "Q8" H 3750 7150 50 0000 R CNN +F 1 "eSim_NPN" H 3800 7250 50 0000 R CNN +F 2 "" H 4050 7200 29 0000 C CNN +F 3 "" H 3850 7100 60 0000 C CNN + 1 3850 7100 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D2 +U 1 1 6864E1E1 +P 1700 6950 +F 0 "D2" H 1700 7050 50 0000 C CNN +F 1 "eSim_Diode" H 1700 6850 50 0000 C CNN +F 2 "" H 1700 6950 60 0000 C CNN +F 3 "" H 1700 6950 60 0000 C CNN + 1 1700 6950 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R6 +U 1 1 6864E1E7 +P 2000 5650 +F 0 "R6" H 2050 5780 50 0000 C CNN +F 1 "6K" H 2050 5600 50 0000 C CNN +F 2 "" H 2050 5630 30 0000 C CNN +F 3 "" V 2050 5700 30 0000 C CNN + 1 2000 5650 + 0 1 1 0 +$EndComp +$Comp +L resistor R7 +U 1 1 6864E1ED +P 2700 5800 +F 0 "R7" H 2750 5930 50 0000 C CNN +F 1 "3.4K" H 2750 5750 50 0000 C CNN +F 2 "" H 2750 5780 30 0000 C CNN +F 3 "" V 2750 5850 30 0000 C CNN + 1 2700 5800 + 0 1 1 0 +$EndComp +$Comp +L resistor R8 +U 1 1 6864E1F3 +P 2700 7000 +F 0 "R8" H 2750 7130 50 0000 C CNN +F 1 "100" H 2750 6950 50 0000 C CNN +F 2 "" H 2750 6980 30 0000 C CNN +F 3 "" V 2750 7050 30 0000 C CNN + 1 2700 7000 + 0 1 1 0 +$EndComp +$Comp +L resistor R9 +U 1 1 6864E1F9 +P 2700 7700 +F 0 "R9" H 2750 7830 50 0000 C CNN +F 1 "1K" H 2750 7650 50 0000 C CNN +F 2 "" H 2750 7680 30 0000 C CNN +F 3 "" V 2750 7750 30 0000 C CNN + 1 2700 7700 + 0 1 1 0 +$EndComp +$Comp +L resistor R10 +U 1 1 6864E1FF +P 3400 5950 +F 0 "R10" H 3450 6080 50 0000 C CNN +F 1 "1.6K" H 3450 5900 50 0000 C CNN +F 2 "" H 3450 5930 30 0000 C CNN +F 3 "" V 3450 6000 30 0000 C CNN + 1 3400 5950 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q9 +U 1 1 6864E579 +P 6300 3200 +F 0 "Q9" H 6200 3250 50 0000 R CNN +F 1 "eSim_NPN" H 6250 3350 50 0000 R CNN +F 2 "" H 6500 3300 29 0000 C CNN +F 3 "" H 6300 3200 60 0000 C CNN + 1 6300 3200 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q11 +U 1 1 6864E57F +P 6900 3450 +F 0 "Q11" H 6800 3500 50 0000 R CNN +F 1 "eSim_NPN" H 6850 3600 50 0000 R CNN +F 2 "" H 7100 3550 29 0000 C CNN +F 3 "" H 6900 3450 60 0000 C CNN + 1 6900 3450 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q13 +U 1 1 6864E585 +P 7250 4350 +F 0 "Q13" H 7150 4400 50 0000 R CNN +F 1 "eSim_NPN" H 7200 4500 50 0000 R CNN +F 2 "" H 7450 4450 29 0000 C CNN +F 3 "" H 7250 4350 60 0000 C CNN + 1 7250 4350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q15 +U 1 1 6864E58B +P 8100 4000 +F 0 "Q15" H 8000 4050 50 0000 R CNN +F 1 "eSim_NPN" H 8050 4150 50 0000 R CNN +F 2 "" H 8300 4100 29 0000 C CNN +F 3 "" H 8100 4000 60 0000 C CNN + 1 8100 4000 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D3 +U 1 1 6864E591 +P 5950 3850 +F 0 "D3" H 5950 3950 50 0000 C CNN +F 1 "eSim_Diode" H 5950 3750 50 0000 C CNN +F 2 "" H 5950 3850 60 0000 C CNN +F 3 "" H 5950 3850 60 0000 C CNN + 1 5950 3850 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R11 +U 1 1 6864E597 +P 6250 2550 +F 0 "R11" H 6300 2680 50 0000 C CNN +F 1 "6K" H 6300 2500 50 0000 C CNN +F 2 "" H 6300 2530 30 0000 C CNN +F 3 "" V 6300 2600 30 0000 C CNN + 1 6250 2550 + 0 1 1 0 +$EndComp +$Comp +L resistor R13 +U 1 1 6864E59D +P 6950 2700 +F 0 "R13" H 7000 2830 50 0000 C CNN +F 1 "3.4K" H 7000 2650 50 0000 C CNN +F 2 "" H 7000 2680 30 0000 C CNN +F 3 "" V 7000 2750 30 0000 C CNN + 1 6950 2700 + 0 1 1 0 +$EndComp +$Comp +L resistor R14 +U 1 1 6864E5A3 +P 6950 3900 +F 0 "R14" H 7000 4030 50 0000 C CNN +F 1 "100" H 7000 3850 50 0000 C CNN +F 2 "" H 7000 3880 30 0000 C CNN +F 3 "" V 7000 3950 30 0000 C CNN + 1 6950 3900 + 0 1 1 0 +$EndComp +$Comp +L resistor R15 +U 1 1 6864E5A9 +P 6950 4600 +F 0 "R15" H 7000 4730 50 0000 C CNN +F 1 "1K" H 7000 4550 50 0000 C CNN +F 2 "" H 7000 4580 30 0000 C CNN +F 3 "" V 7000 4650 30 0000 C CNN + 1 6950 4600 + 0 1 1 0 +$EndComp +$Comp +L resistor R19 +U 1 1 6864E5AF +P 7650 2850 +F 0 "R19" H 7700 2980 50 0000 C CNN +F 1 "1.6K" H 7700 2800 50 0000 C CNN +F 2 "" H 7700 2830 30 0000 C CNN +F 3 "" V 7700 2900 30 0000 C CNN + 1 7650 2850 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q10 +U 1 1 6864E839 +P 6300 6300 +F 0 "Q10" H 6200 6350 50 0000 R CNN +F 1 "eSim_NPN" H 6250 6450 50 0000 R CNN +F 2 "" H 6500 6400 29 0000 C CNN +F 3 "" H 6300 6300 60 0000 C CNN + 1 6300 6300 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q12 +U 1 1 6864E83F +P 6900 6550 +F 0 "Q12" H 6800 6600 50 0000 R CNN +F 1 "eSim_NPN" H 6850 6700 50 0000 R CNN +F 2 "" H 7100 6650 29 0000 C CNN +F 3 "" H 6900 6550 60 0000 C CNN + 1 6900 6550 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q14 +U 1 1 6864E845 +P 7250 7450 +F 0 "Q14" H 7150 7500 50 0000 R CNN +F 1 "eSim_NPN" H 7200 7600 50 0000 R CNN +F 2 "" H 7450 7550 29 0000 C CNN +F 3 "" H 7250 7450 60 0000 C CNN + 1 7250 7450 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q16 +U 1 1 6864E84B +P 8100 7100 +F 0 "Q16" H 8000 7150 50 0000 R CNN +F 1 "eSim_NPN" H 8050 7250 50 0000 R CNN +F 2 "" H 8300 7200 29 0000 C CNN +F 3 "" H 8100 7100 60 0000 C CNN + 1 8100 7100 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D4 +U 1 1 6864E851 +P 5950 6950 +F 0 "D4" H 5950 7050 50 0000 C CNN +F 1 "eSim_Diode" H 5950 6850 50 0000 C CNN +F 2 "" H 5950 6950 60 0000 C CNN +F 3 "" H 5950 6950 60 0000 C CNN + 1 5950 6950 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R12 +U 1 1 6864E857 +P 6250 5650 +F 0 "R12" H 6300 5780 50 0000 C CNN +F 1 "6K" H 6300 5600 50 0000 C CNN +F 2 "" H 6300 5630 30 0000 C CNN +F 3 "" V 6300 5700 30 0000 C CNN + 1 6250 5650 + 0 1 1 0 +$EndComp +$Comp +L resistor R16 +U 1 1 6864E85D +P 6950 5800 +F 0 "R16" H 7000 5930 50 0000 C CNN +F 1 "3.4K" H 7000 5750 50 0000 C CNN +F 2 "" H 7000 5780 30 0000 C CNN +F 3 "" V 7000 5850 30 0000 C CNN + 1 6950 5800 + 0 1 1 0 +$EndComp +$Comp +L resistor R17 +U 1 1 6864E863 +P 6950 7000 +F 0 "R17" H 7000 7130 50 0000 C CNN +F 1 "100" H 7000 6950 50 0000 C CNN +F 2 "" H 7000 6980 30 0000 C CNN +F 3 "" V 7000 7050 30 0000 C CNN + 1 6950 7000 + 0 1 1 0 +$EndComp +$Comp +L resistor R18 +U 1 1 6864E869 +P 6950 7700 +F 0 "R18" H 7000 7830 50 0000 C CNN +F 1 "1K" H 7000 7650 50 0000 C CNN +F 2 "" H 7000 7680 30 0000 C CNN +F 3 "" V 7000 7750 30 0000 C CNN + 1 6950 7700 + 0 1 1 0 +$EndComp +$Comp +L resistor R20 +U 1 1 6864E86F +P 7650 5950 +F 0 "R20" H 7700 6080 50 0000 C CNN +F 1 "1.6K" H 7700 5900 50 0000 C CNN +F 2 "" H 7700 5930 30 0000 C CNN +F 3 "" V 7700 6000 30 0000 C CNN + 1 7650 5950 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q17 +U 1 1 6864EB35 +P 10900 3300 +F 0 "Q17" H 10800 3350 50 0000 R CNN +F 1 "eSim_NPN" H 10850 3450 50 0000 R CNN +F 2 "" H 11100 3400 29 0000 C CNN +F 3 "" H 10900 3300 60 0000 C CNN + 1 10900 3300 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q19 +U 1 1 6864EB3B +P 11500 3550 +F 0 "Q19" H 11400 3600 50 0000 R CNN +F 1 "eSim_NPN" H 11450 3700 50 0000 R CNN +F 2 "" H 11700 3650 29 0000 C CNN +F 3 "" H 11500 3550 60 0000 C CNN + 1 11500 3550 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q21 +U 1 1 6864EB41 +P 11850 4450 +F 0 "Q21" H 11750 4500 50 0000 R CNN +F 1 "eSim_NPN" H 11800 4600 50 0000 R CNN +F 2 "" H 12050 4550 29 0000 C CNN +F 3 "" H 11850 4450 60 0000 C CNN + 1 11850 4450 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q23 +U 1 1 6864EB47 +P 12700 4100 +F 0 "Q23" H 12600 4150 50 0000 R CNN +F 1 "eSim_NPN" H 12650 4250 50 0000 R CNN +F 2 "" H 12900 4200 29 0000 C CNN +F 3 "" H 12700 4100 60 0000 C CNN + 1 12700 4100 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D5 +U 1 1 6864EB4D +P 10550 3950 +F 0 "D5" H 10550 4050 50 0000 C CNN +F 1 "eSim_Diode" H 10550 3850 50 0000 C CNN +F 2 "" H 10550 3950 60 0000 C CNN +F 3 "" H 10550 3950 60 0000 C CNN + 1 10550 3950 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R21 +U 1 1 6864EB53 +P 10850 2650 +F 0 "R21" H 10900 2780 50 0000 C CNN +F 1 "6K" H 10900 2600 50 0000 C CNN +F 2 "" H 10900 2630 30 0000 C CNN +F 3 "" V 10900 2700 30 0000 C CNN + 1 10850 2650 + 0 1 1 0 +$EndComp +$Comp +L resistor R23 +U 1 1 6864EB59 +P 11550 2800 +F 0 "R23" H 11600 2930 50 0000 C CNN +F 1 "3.4K" H 11600 2750 50 0000 C CNN +F 2 "" H 11600 2780 30 0000 C CNN +F 3 "" V 11600 2850 30 0000 C CNN + 1 11550 2800 + 0 1 1 0 +$EndComp +$Comp +L resistor R24 +U 1 1 6864EB5F +P 11550 4000 +F 0 "R24" H 11600 4130 50 0000 C CNN +F 1 "100" H 11600 3950 50 0000 C CNN +F 2 "" H 11600 3980 30 0000 C CNN +F 3 "" V 11600 4050 30 0000 C CNN + 1 11550 4000 + 0 1 1 0 +$EndComp +$Comp +L resistor R25 +U 1 1 6864EB65 +P 11550 4700 +F 0 "R25" H 11600 4830 50 0000 C CNN +F 1 "1K" H 11600 4650 50 0000 C CNN +F 2 "" H 11600 4680 30 0000 C CNN +F 3 "" V 11600 4750 30 0000 C CNN + 1 11550 4700 + 0 1 1 0 +$EndComp +$Comp +L resistor R29 +U 1 1 6864EB6B +P 12250 2950 +F 0 "R29" H 12300 3080 50 0000 C CNN +F 1 "1.6K" H 12300 2900 50 0000 C CNN +F 2 "" H 12300 2930 30 0000 C CNN +F 3 "" V 12300 3000 30 0000 C CNN + 1 12250 2950 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q18 +U 1 1 6864ED19 +P 10900 6350 +F 0 "Q18" H 10800 6400 50 0000 R CNN +F 1 "eSim_NPN" H 10850 6500 50 0000 R CNN +F 2 "" H 11100 6450 29 0000 C CNN +F 3 "" H 10900 6350 60 0000 C CNN + 1 10900 6350 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q20 +U 1 1 6864ED1F +P 11500 6600 +F 0 "Q20" H 11400 6650 50 0000 R CNN +F 1 "eSim_NPN" H 11450 6750 50 0000 R CNN +F 2 "" H 11700 6700 29 0000 C CNN +F 3 "" H 11500 6600 60 0000 C CNN + 1 11500 6600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q22 +U 1 1 6864ED25 +P 11850 7500 +F 0 "Q22" H 11750 7550 50 0000 R CNN +F 1 "eSim_NPN" H 11800 7650 50 0000 R CNN +F 2 "" H 12050 7600 29 0000 C CNN +F 3 "" H 11850 7500 60 0000 C CNN + 1 11850 7500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q24 +U 1 1 6864ED2B +P 12700 7150 +F 0 "Q24" H 12600 7200 50 0000 R CNN +F 1 "eSim_NPN" H 12650 7300 50 0000 R CNN +F 2 "" H 12900 7250 29 0000 C CNN +F 3 "" H 12700 7150 60 0000 C CNN + 1 12700 7150 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D6 +U 1 1 6864ED31 +P 10550 7000 +F 0 "D6" H 10550 7100 50 0000 C CNN +F 1 "eSim_Diode" H 10550 6900 50 0000 C CNN +F 2 "" H 10550 7000 60 0000 C CNN +F 3 "" H 10550 7000 60 0000 C CNN + 1 10550 7000 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R22 +U 1 1 6864ED37 +P 10850 5700 +F 0 "R22" H 10900 5830 50 0000 C CNN +F 1 "6K" H 10900 5650 50 0000 C CNN +F 2 "" H 10900 5680 30 0000 C CNN +F 3 "" V 10900 5750 30 0000 C CNN + 1 10850 5700 + 0 1 1 0 +$EndComp +$Comp +L resistor R26 +U 1 1 6864ED3D +P 11550 5850 +F 0 "R26" H 11600 5980 50 0000 C CNN +F 1 "3.4K" H 11600 5800 50 0000 C CNN +F 2 "" H 11600 5830 30 0000 C CNN +F 3 "" V 11600 5900 30 0000 C CNN + 1 11550 5850 + 0 1 1 0 +$EndComp +$Comp +L resistor R27 +U 1 1 6864ED43 +P 11550 7050 +F 0 "R27" H 11600 7180 50 0000 C CNN +F 1 "100" H 11600 7000 50 0000 C CNN +F 2 "" H 11600 7030 30 0000 C CNN +F 3 "" V 11600 7100 30 0000 C CNN + 1 11550 7050 + 0 1 1 0 +$EndComp +$Comp +L resistor R28 +U 1 1 6864ED49 +P 11550 7750 +F 0 "R28" H 11600 7880 50 0000 C CNN +F 1 "1K" H 11600 7700 50 0000 C CNN +F 2 "" H 11600 7730 30 0000 C CNN +F 3 "" V 11600 7800 30 0000 C CNN + 1 11550 7750 + 0 1 1 0 +$EndComp +$Comp +L resistor R30 +U 1 1 6864ED4F +P 12250 6000 +F 0 "R30" H 12300 6130 50 0000 C CNN +F 1 "1.6K" H 12300 5950 50 0000 C CNN +F 2 "" H 12300 5980 30 0000 C CNN +F 3 "" V 12300 6050 30 0000 C CNN + 1 12250 6000 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 1 1 68654139 +P 1300 3400 +F 0 "U1" H 1350 3500 30 0000 C CNN +F 1 "PORT" H 1300 3400 30 0000 C CNN +F 2 "" H 1300 3400 60 0000 C CNN +F 3 "" H 1300 3400 60 0000 C CNN + 1 1300 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 686541C8 +P 4250 3600 +F 0 "U1" H 4300 3700 30 0000 C CNN +F 1 "PORT" H 4250 3600 30 0000 C CNN +F 2 "" H 4250 3600 60 0000 C CNN +F 3 "" H 4250 3600 60 0000 C CNN + 2 4250 3600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 68654289 +P 1300 6600 +F 0 "U1" H 1350 6700 30 0000 C CNN +F 1 "PORT" H 1300 6600 30 0000 C CNN +F 2 "" H 1300 6600 60 0000 C CNN +F 3 "" H 1300 6600 60 0000 C CNN + 3 1300 6600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 6865431C +P 4250 6650 +F 0 "U1" H 4300 6750 30 0000 C CNN +F 1 "PORT" H 4250 6650 30 0000 C CNN +F 2 "" H 4250 6650 60 0000 C CNN +F 3 "" H 4250 6650 60 0000 C CNN + 4 4250 6650 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 686543D7 +P 5550 3550 +F 0 "U1" H 5600 3650 30 0000 C CNN +F 1 "PORT" H 5550 3550 30 0000 C CNN +F 2 "" H 5550 3550 60 0000 C CNN +F 3 "" H 5550 3550 60 0000 C CNN + 5 5550 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 68654470 +P 8500 3500 +F 0 "U1" H 8550 3600 30 0000 C CNN +F 1 "PORT" H 8500 3500 30 0000 C CNN +F 2 "" H 8500 3500 60 0000 C CNN +F 3 "" H 8500 3500 60 0000 C CNN + 6 8500 3500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 68654509 +P 14800 8600 +F 0 "U1" H 14850 8700 30 0000 C CNN +F 1 "PORT" H 14800 8600 30 0000 C CNN +F 2 "" H 14800 8600 60 0000 C CNN +F 3 "" H 14800 8600 60 0000 C CNN + 7 14800 8600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 686545A4 +P 8500 6650 +F 0 "U1" H 8550 6750 30 0000 C CNN +F 1 "PORT" H 8500 6650 30 0000 C CNN +F 2 "" H 8500 6650 60 0000 C CNN +F 3 "" H 8500 6650 60 0000 C CNN + 8 8500 6650 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 9 1 68654641 +P 5550 6550 +F 0 "U1" H 5600 6650 30 0000 C CNN +F 1 "PORT" H 5550 6550 30 0000 C CNN +F 2 "" H 5550 6550 60 0000 C CNN +F 3 "" H 5550 6550 60 0000 C CNN + 9 5550 6550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 686546F0 +P 13100 3650 +F 0 "U1" H 13150 3750 30 0000 C CNN +F 1 "PORT" H 13100 3650 30 0000 C CNN +F 2 "" H 13100 3650 60 0000 C CNN +F 3 "" H 13100 3650 60 0000 C CNN + 10 13100 3650 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 68654791 +P 10150 3550 +F 0 "U1" H 10200 3650 30 0000 C CNN +F 1 "PORT" H 10150 3550 30 0000 C CNN +F 2 "" H 10150 3550 60 0000 C CNN +F 3 "" H 10150 3550 60 0000 C CNN + 11 10150 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 6865483C +P 13100 6650 +F 0 "U1" H 13150 6750 30 0000 C CNN +F 1 "PORT" H 13100 6650 30 0000 C CNN +F 2 "" H 13100 6650 60 0000 C CNN +F 3 "" H 13100 6650 60 0000 C CNN + 12 13100 6650 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 686548E1 +P 10200 6600 +F 0 "U1" H 10250 6700 30 0000 C CNN +F 1 "PORT" H 10200 6600 30 0000 C CNN +F 2 "" H 10200 6600 60 0000 C CNN +F 3 "" H 10200 6600 60 0000 C CNN + 13 10200 6600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 68654988 +P 14850 2200 +F 0 "U1" H 14900 2300 30 0000 C CNN +F 1 "PORT" H 14850 2200 30 0000 C CNN +F 2 "" H 14850 2200 60 0000 C CNN +F 3 "" H 14850 2200 60 0000 C CNN + 14 14850 2200 + -1 0 0 1 +$EndComp +Wire Wire Line + 1700 3300 1700 3700 +Wire Wire Line + 1700 3300 1850 3300 +Wire Wire Line + 2250 3300 2250 3450 +Wire Wire Line + 2250 3450 2450 3450 +Wire Wire Line + 2750 3650 2750 3800 +Wire Wire Line + 2750 4100 2750 4500 +Wire Wire Line + 2750 4350 2800 4350 +Connection ~ 2750 4350 +Wire Wire Line + 3100 4150 3100 4000 +Wire Wire Line + 3100 4000 3650 4000 +Wire Wire Line + 3450 3050 3450 4000 +Connection ~ 3450 4000 +Wire Wire Line + 2050 2750 2050 3000 +Wire Wire Line + 2750 2900 2750 3250 +Wire Wire Line + 1700 4000 1700 5000 +Wire Wire Line + 1700 5000 5350 5000 +Wire Wire Line + 2750 4800 2750 5000 +Connection ~ 2750 5000 +Wire Wire Line + 3100 4550 3100 5000 +Connection ~ 3100 5000 +Wire Wire Line + 3950 4200 3950 5000 +Connection ~ 3950 5000 +Wire Wire Line + 2050 2450 2050 2300 +Wire Wire Line + 2050 2300 3450 2300 +Wire Wire Line + 3450 2200 3450 2750 +Wire Wire Line + 2750 2300 2750 2600 +Connection ~ 2750 2300 +Wire Wire Line + 1700 6800 1700 6400 +Wire Wire Line + 1700 6400 1850 6400 +Wire Wire Line + 2250 6400 2250 6550 +Wire Wire Line + 2250 6550 2450 6550 +Wire Wire Line + 2750 6750 2750 6900 +Wire Wire Line + 2750 7200 2750 7600 +Wire Wire Line + 2750 7450 2800 7450 +Connection ~ 2750 7450 +Wire Wire Line + 3100 7250 3100 7100 +Wire Wire Line + 3100 7100 3650 7100 +Wire Wire Line + 3450 6150 3450 7100 +Connection ~ 3450 7100 +Wire Wire Line + 2050 5850 2050 6100 +Wire Wire Line + 2750 6000 2750 6350 +Wire Wire Line + 1700 7100 1700 8100 +Wire Wire Line + 1700 8100 5000 8100 +Wire Wire Line + 5000 8100 5000 8600 +Wire Wire Line + 2750 7900 2750 8100 +Connection ~ 2750 8100 +Wire Wire Line + 3100 7650 3100 8100 +Connection ~ 3100 8100 +Wire Wire Line + 3950 7300 3950 8100 +Connection ~ 3950 8100 +Wire Wire Line + 2050 5550 2050 5400 +Wire Wire Line + 2050 5400 5000 5400 +Wire Wire Line + 3450 5400 3450 5850 +Wire Wire Line + 2750 5400 2750 5700 +Connection ~ 2750 5400 +Wire Wire Line + 5950 3300 5950 3700 +Wire Wire Line + 5950 3300 6100 3300 +Wire Wire Line + 6500 3300 6500 3450 +Wire Wire Line + 6500 3450 6700 3450 +Wire Wire Line + 7000 3650 7000 3800 +Wire Wire Line + 7000 4100 7000 4500 +Wire Wire Line + 7000 4350 7050 4350 +Connection ~ 7000 4350 +Wire Wire Line + 7350 4150 7350 4000 +Wire Wire Line + 7350 4000 7900 4000 +Wire Wire Line + 7700 3050 7700 4000 +Connection ~ 7700 4000 +Wire Wire Line + 6300 2750 6300 3000 +Wire Wire Line + 7000 2900 7000 3250 +Wire Wire Line + 5950 4000 5950 5000 +Wire Wire Line + 5950 5000 9850 5000 +Wire Wire Line + 7000 4800 7000 5000 +Connection ~ 7000 5000 +Wire Wire Line + 7350 4550 7350 5000 +Connection ~ 7350 5000 +Wire Wire Line + 8200 4200 8200 5000 +Connection ~ 8200 5000 +Wire Wire Line + 6300 2450 6300 2300 +Wire Wire Line + 6300 2300 8150 2300 +Wire Wire Line + 7700 2300 7700 2750 +Wire Wire Line + 7000 2300 7000 2600 +Connection ~ 7000 2300 +Wire Wire Line + 5950 6400 5950 6800 +Wire Wire Line + 5950 6400 6100 6400 +Wire Wire Line + 6500 6400 6500 6550 +Wire Wire Line + 6500 6550 6700 6550 +Wire Wire Line + 7000 6750 7000 6900 +Wire Wire Line + 7000 7200 7000 7600 +Wire Wire Line + 7000 7450 7050 7450 +Connection ~ 7000 7450 +Wire Wire Line + 7350 7250 7350 7100 +Wire Wire Line + 7350 7100 7900 7100 +Wire Wire Line + 7700 6150 7700 7100 +Connection ~ 7700 7100 +Wire Wire Line + 6300 5850 6300 6100 +Wire Wire Line + 7000 6000 7000 6350 +Wire Wire Line + 5950 7100 5950 8100 +Wire Wire Line + 5950 8100 9250 8100 +Wire Wire Line + 9250 8100 9250 8600 +Wire Wire Line + 7000 7900 7000 8100 +Connection ~ 7000 8100 +Wire Wire Line + 7350 7650 7350 8100 +Connection ~ 7350 8100 +Wire Wire Line + 8200 7300 8200 8100 +Connection ~ 8200 8100 +Wire Wire Line + 6300 5550 6300 5400 +Wire Wire Line + 6300 5400 9500 5400 +Wire Wire Line + 7700 5400 7700 5850 +Wire Wire Line + 7000 5400 7000 5700 +Connection ~ 7000 5400 +Wire Wire Line + 10550 3400 10550 3800 +Wire Wire Line + 10550 3400 10700 3400 +Wire Wire Line + 11100 3400 11100 3550 +Wire Wire Line + 11100 3550 11300 3550 +Wire Wire Line + 11600 3750 11600 3900 +Wire Wire Line + 11600 4200 11600 4600 +Wire Wire Line + 11600 4450 11650 4450 +Connection ~ 11600 4450 +Wire Wire Line + 11950 4250 11950 4100 +Wire Wire Line + 11950 4100 12500 4100 +Wire Wire Line + 12300 3150 12300 4100 +Connection ~ 12300 4100 +Wire Wire Line + 10900 2850 10900 3100 +Wire Wire Line + 11600 3000 11600 3350 +Wire Wire Line + 10550 4100 10550 5100 +Wire Wire Line + 10550 5100 14250 5100 +Wire Wire Line + 11600 4900 11600 5100 +Connection ~ 11600 5100 +Wire Wire Line + 11950 4650 11950 5100 +Connection ~ 11950 5100 +Wire Wire Line + 12800 4300 12800 5100 +Connection ~ 12800 5100 +Wire Wire Line + 10900 2550 10900 2400 +Wire Wire Line + 10900 2400 12800 2400 +Wire Wire Line + 12300 2400 12300 2850 +Wire Wire Line + 11600 2400 11600 2700 +Connection ~ 11600 2400 +Wire Wire Line + 10550 6450 10550 6850 +Wire Wire Line + 10550 6450 10700 6450 +Wire Wire Line + 11100 6450 11100 6600 +Wire Wire Line + 11100 6600 11300 6600 +Wire Wire Line + 11600 6800 11600 6950 +Wire Wire Line + 11600 7250 11600 7650 +Wire Wire Line + 11600 7500 11650 7500 +Connection ~ 11600 7500 +Wire Wire Line + 11950 7300 11950 7150 +Wire Wire Line + 11950 7150 12500 7150 +Wire Wire Line + 12300 6200 12300 7150 +Connection ~ 12300 7150 +Wire Wire Line + 10900 5900 10900 6150 +Wire Wire Line + 11600 6050 11600 6400 +Wire Wire Line + 10550 7150 10550 8150 +Wire Wire Line + 10550 8150 13850 8150 +Wire Wire Line + 13850 8150 13850 8600 +Wire Wire Line + 11600 7950 11600 8150 +Connection ~ 11600 8150 +Wire Wire Line + 11950 7700 11950 8150 +Connection ~ 11950 8150 +Wire Wire Line + 12800 7350 12800 8150 +Connection ~ 12800 8150 +Wire Wire Line + 10900 5600 10900 5450 +Wire Wire Line + 10900 5450 13800 5450 +Wire Wire Line + 12300 5450 12300 5900 +Wire Wire Line + 11600 5450 11600 5750 +Connection ~ 11600 5450 +Wire Wire Line + 5350 5000 5350 8600 +Wire Wire Line + 5000 8600 14550 8600 +Wire Wire Line + 9850 5000 9850 8600 +Connection ~ 9850 8600 +Wire Wire Line + 14250 5100 14250 8600 +Connection ~ 14250 8600 +Connection ~ 13850 8600 +Connection ~ 9250 8600 +Connection ~ 5350 8600 +Wire Wire Line + 5000 5400 5000 2200 +Wire Wire Line + 3450 2200 14600 2200 +Connection ~ 3450 5400 +Wire Wire Line + 12800 2400 12800 2200 +Connection ~ 12800 2200 +Connection ~ 12300 2400 +Wire Wire Line + 8150 2300 8150 2200 +Connection ~ 8150 2200 +Connection ~ 7700 2300 +Connection ~ 5000 2200 +Connection ~ 3450 2300 +Wire Wire Line + 9500 5400 9500 2200 +Connection ~ 9500 2200 +Connection ~ 7700 5400 +Wire Wire Line + 13800 5450 13800 2200 +Connection ~ 13800 2200 +Connection ~ 12300 5450 +Wire Wire Line + 1550 3400 1700 3400 +Connection ~ 1700 3400 +Wire Wire Line + 3950 3800 3950 3600 +Wire Wire Line + 3950 3600 4000 3600 +Wire Wire Line + 3950 6900 3950 6650 +Wire Wire Line + 3950 6650 4000 6650 +Wire Wire Line + 5800 3550 5950 3550 +Connection ~ 5950 3550 +Wire Wire Line + 8200 3800 8200 3500 +Wire Wire Line + 8200 3500 8250 3500 +Wire Wire Line + 5800 6550 5950 6550 +Connection ~ 5950 6550 +Wire Wire Line + 8200 6900 8200 6650 +Wire Wire Line + 8200 6650 8250 6650 +Wire Wire Line + 10400 3550 10550 3550 +Connection ~ 10550 3550 +Wire Wire Line + 12800 3900 12800 3650 +Wire Wire Line + 12800 3650 12850 3650 +Wire Wire Line + 10450 6600 10550 6600 +Connection ~ 10550 6600 +Wire Wire Line + 12800 6950 12800 6650 +Wire Wire Line + 12800 6650 12850 6650 +Wire Wire Line + 1550 6600 1700 6600 +Connection ~ 1700 6600 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN7407/SN7407.sub b/library/SubcircuitLibrary/SN7407/SN7407.sub new file mode 100644 index 000000000..52ea34539 --- /dev/null +++ b/library/SubcircuitLibrary/SN7407/SN7407.sub @@ -0,0 +1,68 @@ +* Subcircuit SN7407 +.subckt SN7407 net-_d1-pad2_ net-_q4-pad1_ net-_d2-pad2_ net-_q8-pad1_ net-_d3-pad2_ net-_q15-pad1_ net-_d1-pad1_ net-_q16-pad1_ net-_d4-pad2_ net-_q23-pad1_ net-_d5-pad2_ net-_q24-pad1_ net-_d6-pad2_ net-_r1-pad1_ +* c:\fossee\esim\library\subcircuitlibrary\sn7407\sn7407.cir +.include D.lib +.include NPN.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_d1-pad2_ Q2N2222 +q2 net-_q2-pad1_ net-_q1-pad1_ net-_q2-pad3_ Q2N2222 +q3 net-_q3-pad1_ net-_q3-pad2_ net-_d1-pad1_ Q2N2222 +q4 net-_q4-pad1_ net-_q3-pad1_ net-_d1-pad1_ Q2N2222 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +r1 net-_r1-pad1_ net-_q1-pad2_ 6k +r2 net-_r1-pad1_ net-_q2-pad1_ 3.4k +r3 net-_q2-pad3_ net-_q3-pad2_ 100 +r4 net-_q3-pad2_ net-_d1-pad1_ 1k +r5 net-_r1-pad1_ net-_q3-pad1_ 1.6k +q5 net-_q5-pad1_ net-_q5-pad2_ net-_d2-pad2_ Q2N2222 +q6 net-_q6-pad1_ net-_q5-pad1_ net-_q6-pad3_ Q2N2222 +q7 net-_q7-pad1_ net-_q7-pad2_ net-_d1-pad1_ Q2N2222 +q8 net-_q8-pad1_ net-_q7-pad1_ net-_d1-pad1_ Q2N2222 +d2 net-_d1-pad1_ net-_d2-pad2_ 1N4148 +r6 net-_r1-pad1_ net-_q5-pad2_ 6k +r7 net-_r1-pad1_ net-_q6-pad1_ 3.4k +r8 net-_q6-pad3_ net-_q7-pad2_ 100 +r9 net-_q7-pad2_ net-_d1-pad1_ 1k +r10 net-_r1-pad1_ net-_q7-pad1_ 1.6k +q9 net-_q11-pad2_ net-_q9-pad2_ net-_d3-pad2_ Q2N2222 +q11 net-_q11-pad1_ net-_q11-pad2_ net-_q11-pad3_ Q2N2222 +q13 net-_q13-pad1_ net-_q13-pad2_ net-_d1-pad1_ Q2N2222 +q15 net-_q15-pad1_ net-_q13-pad1_ net-_d1-pad1_ Q2N2222 +d3 net-_d1-pad1_ net-_d3-pad2_ 1N4148 +r11 net-_r1-pad1_ net-_q9-pad2_ 6k +r13 net-_r1-pad1_ net-_q11-pad1_ 3.4k +r14 net-_q11-pad3_ net-_q13-pad2_ 100 +r15 net-_q13-pad2_ net-_d1-pad1_ 1k +r19 net-_r1-pad1_ net-_q13-pad1_ 1.6k +q10 net-_q10-pad1_ net-_q10-pad2_ net-_d4-pad2_ Q2N2222 +q12 net-_q12-pad1_ net-_q10-pad1_ net-_q12-pad3_ Q2N2222 +q14 net-_q14-pad1_ net-_q14-pad2_ net-_d1-pad1_ Q2N2222 +q16 net-_q16-pad1_ net-_q14-pad1_ net-_d1-pad1_ Q2N2222 +d4 net-_d1-pad1_ net-_d4-pad2_ 1N4148 +r12 net-_r1-pad1_ net-_q10-pad2_ 6k +r16 net-_r1-pad1_ net-_q12-pad1_ 3.4k +r17 net-_q12-pad3_ net-_q14-pad2_ 100 +r18 net-_q14-pad2_ net-_d1-pad1_ 1k +r20 net-_r1-pad1_ net-_q14-pad1_ 1.6k +q17 net-_q17-pad1_ net-_q17-pad2_ net-_d5-pad2_ Q2N2222 +q19 net-_q19-pad1_ net-_q17-pad1_ net-_q19-pad3_ Q2N2222 +q21 net-_q21-pad1_ net-_q21-pad2_ net-_d1-pad1_ Q2N2222 +q23 net-_q23-pad1_ net-_q21-pad1_ net-_d1-pad1_ Q2N2222 +d5 net-_d1-pad1_ net-_d5-pad2_ 1N4148 +r21 net-_r1-pad1_ net-_q17-pad2_ 6k +r23 net-_r1-pad1_ net-_q19-pad1_ 3.4k +r24 net-_q19-pad3_ net-_q21-pad2_ 100 +r25 net-_q21-pad2_ net-_d1-pad1_ 1k +r29 net-_r1-pad1_ net-_q21-pad1_ 1.6k +q18 net-_q18-pad1_ net-_q18-pad2_ net-_d6-pad2_ Q2N2222 +q20 net-_q20-pad1_ net-_q18-pad1_ net-_q20-pad3_ Q2N2222 +q22 net-_q22-pad1_ net-_q22-pad2_ net-_d1-pad1_ Q2N2222 +q24 net-_q24-pad1_ net-_q22-pad1_ net-_d1-pad1_ Q2N2222 +d6 net-_d1-pad1_ net-_d6-pad2_ 1N4148 +r22 net-_r1-pad1_ net-_q18-pad2_ 6k +r26 net-_r1-pad1_ net-_q20-pad1_ 3.4k +r27 net-_q20-pad3_ net-_q22-pad2_ 100 +r28 net-_q22-pad2_ net-_d1-pad1_ 1k +r30 net-_r1-pad1_ net-_q22-pad1_ 1.6k +* Control Statements + +.ends SN7407 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN7407/SN7407_Previous_Values.xml b/library/SubcircuitLibrary/SN7407/SN7407_Previous_Values.xml new file mode 100644 index 000000000..1ade3ec19 --- /dev/null +++ b/library/SubcircuitLibrary/SN7407/SN7407_Previous_Values.xml @@ -0,0 +1 @@ +C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN7407/analysis b/library/SubcircuitLibrary/SN7407/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/SN7407/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74116/SN74116-cache.lib b/library/SubcircuitLibrary/SN74116/SN74116-cache.lib new file mode 100644 index 000000000..af784f684 --- /dev/null +++ b/library/SubcircuitLibrary/SN74116/SN74116-cache.lib @@ -0,0 +1,111 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74116/SN74116.cir b/library/SubcircuitLibrary/SN74116/SN74116.cir new file mode 100644 index 000000000..367c4ea10 --- /dev/null +++ b/library/SubcircuitLibrary/SN74116/SN74116.cir @@ -0,0 +1,127 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\SN74116\SN74116.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/05/25 18:51:59 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 Net-_U3-Pad1_ Net-_U3-Pad2_ d_inverter +U4 Net-_U1-Pad2_ Net-_U2-Pad2_ Net-_U10-Pad1_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ d_inverter +U2 Net-_U2-Pad1_ Net-_U2-Pad2_ d_inverter +U6 Net-_U10-Pad1_ Net-_U14-Pad2_ d_inverter +U14 Net-_U14-Pad1_ Net-_U14-Pad2_ Net-_U14-Pad3_ d_nand +U16 Net-_U10-Pad1_ Net-_U15-Pad2_ Net-_U16-Pad3_ d_and +U15 Net-_U14-Pad1_ Net-_U15-Pad2_ Net-_U15-Pad3_ d_and +U30 Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_U30-Pad3_ d_nor +U36 Net-_U14-Pad3_ Net-_U30-Pad3_ Net-_U36-Pad3_ d_and +U54 Net-_U43-Pad2_ Net-_U44-Pad2_ Net-_U14-Pad1_ d_and +U44 Net-_U36-Pad3_ Net-_U44-Pad2_ d_inverter +U5 Net-_U10-Pad1_ Net-_U11-Pad2_ d_inverter +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_nand +U13 Net-_U10-Pad1_ Net-_U12-Pad2_ Net-_U13-Pad3_ d_and +U12 Net-_U11-Pad1_ Net-_U12-Pad2_ Net-_U12-Pad3_ d_and +U29 Net-_U12-Pad3_ Net-_U13-Pad3_ Net-_U29-Pad3_ d_nor +U35 Net-_U11-Pad3_ Net-_U29-Pad3_ Net-_U35-Pad3_ d_and +U53 Net-_U41-Pad2_ Net-_U42-Pad2_ Net-_U11-Pad1_ d_and +U41 Net-_U3-Pad2_ Net-_U41-Pad2_ d_inverter +U42 Net-_U35-Pad3_ Net-_U42-Pad2_ d_inverter +U9 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter +U23 Net-_U23-Pad1_ Net-_U10-Pad2_ Net-_U23-Pad3_ d_nand +U27 Net-_U10-Pad1_ Net-_U25-Pad2_ Net-_U27-Pad3_ d_and +U25 Net-_U23-Pad1_ Net-_U25-Pad2_ Net-_U25-Pad3_ d_and +U33 Net-_U25-Pad3_ Net-_U27-Pad3_ Net-_U33-Pad3_ d_nor +U39 Net-_U23-Pad3_ Net-_U33-Pad3_ Net-_U39-Pad3_ d_and +U57 Net-_U49-Pad2_ Net-_U51-Pad2_ Net-_U23-Pad1_ d_and +U49 Net-_U3-Pad2_ Net-_U49-Pad2_ d_inverter +U51 Net-_U39-Pad3_ Net-_U51-Pad2_ d_inverter +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter +U24 Net-_U23-Pad1_ Net-_U10-Pad2_ Net-_U23-Pad3_ d_nand +U28 Net-_U10-Pad1_ Net-_U25-Pad2_ Net-_U27-Pad3_ d_and +U26 Net-_U23-Pad1_ Net-_U25-Pad2_ Net-_U25-Pad3_ d_and +U34 Net-_U25-Pad3_ Net-_U27-Pad3_ Net-_U33-Pad3_ d_nor +U40 Net-_U23-Pad3_ Net-_U33-Pad3_ Net-_U39-Pad3_ d_and +U58 Net-_U49-Pad2_ Net-_U51-Pad2_ Net-_U23-Pad1_ d_and +U50 Net-_U3-Pad2_ Net-_U49-Pad2_ d_inverter +U52 Net-_U39-Pad3_ Net-_U51-Pad2_ d_inverter +U7 Net-_U10-Pad1_ Net-_U17-Pad2_ d_inverter +U17 Net-_U17-Pad1_ Net-_U17-Pad2_ Net-_U17-Pad3_ d_nand +U21 Net-_U10-Pad1_ Net-_U19-Pad2_ Net-_U21-Pad3_ d_and +U19 Net-_U17-Pad1_ Net-_U19-Pad2_ Net-_U19-Pad3_ d_and +U31 Net-_U19-Pad3_ Net-_U21-Pad3_ Net-_U31-Pad3_ d_nor +U37 Net-_U17-Pad3_ Net-_U31-Pad3_ Net-_U37-Pad3_ d_and +U55 Net-_U45-Pad2_ Net-_U47-Pad2_ Net-_U17-Pad1_ d_and +U45 Net-_U3-Pad2_ Net-_U45-Pad2_ d_inverter +U47 Net-_U37-Pad3_ Net-_U47-Pad2_ d_inverter +U8 Net-_U10-Pad1_ Net-_U17-Pad2_ d_inverter +U18 Net-_U17-Pad1_ Net-_U17-Pad2_ Net-_U17-Pad3_ d_nand +U22 Net-_U10-Pad1_ Net-_U19-Pad2_ Net-_U21-Pad3_ d_and +U20 Net-_U17-Pad1_ Net-_U19-Pad2_ Net-_U19-Pad3_ d_and +U32 Net-_U19-Pad3_ Net-_U21-Pad3_ Net-_U31-Pad3_ d_nor +U38 Net-_U17-Pad3_ Net-_U31-Pad3_ Net-_U37-Pad3_ d_and +U56 Net-_U45-Pad2_ Net-_U47-Pad2_ Net-_U17-Pad1_ d_and +U46 Net-_U3-Pad2_ Net-_U45-Pad2_ d_inverter +U48 Net-_U37-Pad3_ Net-_U47-Pad2_ d_inverter +U43 Net-_U3-Pad2_ Net-_U43-Pad2_ d_inverter +U62 Net-_U59-Pad13_ Net-_U100-Pad1_ d_inverter +U63 Net-_U60-Pad2_ Net-_U61-Pad2_ Net-_U63-Pad3_ d_and +U60 Net-_U59-Pad14_ Net-_U60-Pad2_ d_inverter +U61 Net-_U59-Pad15_ Net-_U61-Pad2_ d_inverter +U65 Net-_U63-Pad3_ Net-_U65-Pad2_ d_inverter +U73 Net-_U113-Pad3_ Net-_U65-Pad2_ Net-_U73-Pad3_ d_nand +U75 Net-_U63-Pad3_ Net-_U59-Pad16_ Net-_U75-Pad3_ d_and +U74 Net-_U113-Pad3_ Net-_U59-Pad16_ Net-_U74-Pad3_ d_and +U89 Net-_U74-Pad3_ Net-_U75-Pad3_ Net-_U89-Pad3_ d_nor +U95 Net-_U73-Pad3_ Net-_U89-Pad3_ Net-_U103-Pad1_ d_and +U113 Net-_U102-Pad2_ Net-_U103-Pad2_ Net-_U113-Pad3_ d_and +U103 Net-_U103-Pad1_ Net-_U103-Pad2_ d_inverter +U64 Net-_U63-Pad3_ Net-_U64-Pad2_ d_inverter +U70 Net-_U112-Pad3_ Net-_U64-Pad2_ Net-_U70-Pad3_ d_nand +U72 Net-_U63-Pad3_ Net-_U59-Pad18_ Net-_U72-Pad3_ d_and +U71 Net-_U112-Pad3_ Net-_U59-Pad18_ Net-_U71-Pad3_ d_and +U88 Net-_U71-Pad3_ Net-_U72-Pad3_ Net-_U88-Pad3_ d_nor +U94 Net-_U70-Pad3_ Net-_U88-Pad3_ Net-_U101-Pad1_ d_and +U112 Net-_U100-Pad2_ Net-_U101-Pad2_ Net-_U112-Pad3_ d_and +U100 Net-_U100-Pad1_ Net-_U100-Pad2_ d_inverter +U101 Net-_U101-Pad1_ Net-_U101-Pad2_ d_inverter +U68 Net-_U63-Pad3_ Net-_U68-Pad2_ d_inverter +U82 Net-_U116-Pad3_ Net-_U68-Pad2_ Net-_U82-Pad3_ d_nand +U86 Net-_U63-Pad3_ Net-_U59-Pad22_ Net-_U86-Pad3_ d_and +U84 Net-_U116-Pad3_ Net-_U59-Pad22_ Net-_U84-Pad3_ d_and +U92 Net-_U84-Pad3_ Net-_U86-Pad3_ Net-_U92-Pad3_ d_nor +U98 Net-_U82-Pad3_ Net-_U92-Pad3_ Net-_U110-Pad1_ d_and +U116 Net-_U108-Pad2_ Net-_U110-Pad2_ Net-_U116-Pad3_ d_and +U108 Net-_U100-Pad1_ Net-_U108-Pad2_ d_inverter +U110 Net-_U110-Pad1_ Net-_U110-Pad2_ d_inverter +U69 Net-_U63-Pad3_ Net-_U68-Pad2_ d_inverter +U83 Net-_U116-Pad3_ Net-_U68-Pad2_ Net-_U82-Pad3_ d_nand +U87 Net-_U63-Pad3_ Net-_U59-Pad22_ Net-_U86-Pad3_ d_and +U85 Net-_U116-Pad3_ Net-_U59-Pad22_ Net-_U84-Pad3_ d_and +U93 Net-_U84-Pad3_ Net-_U86-Pad3_ Net-_U92-Pad3_ d_nor +U99 Net-_U82-Pad3_ Net-_U92-Pad3_ Net-_U110-Pad1_ d_and +U117 Net-_U108-Pad2_ Net-_U110-Pad2_ Net-_U116-Pad3_ d_and +U109 Net-_U100-Pad1_ Net-_U108-Pad2_ d_inverter +U111 Net-_U110-Pad1_ Net-_U110-Pad2_ d_inverter +U66 Net-_U63-Pad3_ Net-_U66-Pad2_ d_inverter +U76 Net-_U114-Pad3_ Net-_U66-Pad2_ Net-_U76-Pad3_ d_nand +U80 Net-_U63-Pad3_ Net-_U59-Pad20_ Net-_U80-Pad3_ d_and +U78 Net-_U114-Pad3_ Net-_U59-Pad20_ Net-_U78-Pad3_ d_and +U90 Net-_U78-Pad3_ Net-_U80-Pad3_ Net-_U90-Pad3_ d_nor +U96 Net-_U76-Pad3_ Net-_U90-Pad3_ Net-_U106-Pad1_ d_and +U114 Net-_U104-Pad2_ Net-_U106-Pad2_ Net-_U114-Pad3_ d_and +U104 Net-_U100-Pad1_ Net-_U104-Pad2_ d_inverter +U106 Net-_U106-Pad1_ Net-_U106-Pad2_ d_inverter +U67 Net-_U63-Pad3_ Net-_U66-Pad2_ d_inverter +U77 Net-_U114-Pad3_ Net-_U66-Pad2_ Net-_U76-Pad3_ d_nand +U81 Net-_U63-Pad3_ Net-_U59-Pad20_ Net-_U80-Pad3_ d_and +U79 Net-_U114-Pad3_ Net-_U59-Pad20_ Net-_U78-Pad3_ d_and +U91 Net-_U78-Pad3_ Net-_U80-Pad3_ Net-_U90-Pad3_ d_nor +U97 Net-_U76-Pad3_ Net-_U90-Pad3_ Net-_U106-Pad1_ d_and +U115 Net-_U104-Pad2_ Net-_U106-Pad2_ Net-_U114-Pad3_ d_and +U105 Net-_U100-Pad1_ Net-_U104-Pad2_ d_inverter +U107 Net-_U106-Pad1_ Net-_U106-Pad2_ d_inverter +U102 Net-_U100-Pad1_ Net-_U102-Pad2_ d_inverter +U59 Net-_U3-Pad1_ Net-_U1-Pad1_ Net-_U2-Pad1_ Net-_U15-Pad2_ Net-_U14-Pad1_ Net-_U12-Pad2_ Net-_U11-Pad1_ Net-_U19-Pad2_ Net-_U17-Pad1_ Net-_U25-Pad2_ Net-_U23-Pad1_ ? Net-_U59-Pad13_ Net-_U59-Pad14_ Net-_U59-Pad15_ Net-_U59-Pad16_ Net-_U113-Pad3_ Net-_U59-Pad18_ Net-_U112-Pad3_ Net-_U59-Pad20_ Net-_U114-Pad3_ Net-_U59-Pad22_ Net-_U116-Pad3_ ? PORT + +.end diff --git a/library/SubcircuitLibrary/SN74116/SN74116.cir.out b/library/SubcircuitLibrary/SN74116/SN74116.cir.out new file mode 100644 index 000000000..4eb44c919 --- /dev/null +++ b/library/SubcircuitLibrary/SN74116/SN74116.cir.out @@ -0,0 +1,476 @@ +* c:\fossee\esim\library\subcircuitlibrary\sn74116\sn74116.cir + +* u3 net-_u3-pad1_ net-_u3-pad2_ d_inverter +* u4 net-_u1-pad2_ net-_u2-pad2_ net-_u10-pad1_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter +* u2 net-_u2-pad1_ net-_u2-pad2_ d_inverter +* u6 net-_u10-pad1_ net-_u14-pad2_ d_inverter +* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_nand +* u16 net-_u10-pad1_ net-_u15-pad2_ net-_u16-pad3_ d_and +* u15 net-_u14-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_and +* u30 net-_u15-pad3_ net-_u16-pad3_ net-_u30-pad3_ d_nor +* u36 net-_u14-pad3_ net-_u30-pad3_ net-_u36-pad3_ d_and +* u54 net-_u43-pad2_ net-_u44-pad2_ net-_u14-pad1_ d_and +* u44 net-_u36-pad3_ net-_u44-pad2_ d_inverter +* u5 net-_u10-pad1_ net-_u11-pad2_ d_inverter +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_nand +* u13 net-_u10-pad1_ net-_u12-pad2_ net-_u13-pad3_ d_and +* u12 net-_u11-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_and +* u29 net-_u12-pad3_ net-_u13-pad3_ net-_u29-pad3_ d_nor +* u35 net-_u11-pad3_ net-_u29-pad3_ net-_u35-pad3_ d_and +* u53 net-_u41-pad2_ net-_u42-pad2_ net-_u11-pad1_ d_and +* u41 net-_u3-pad2_ net-_u41-pad2_ d_inverter +* u42 net-_u35-pad3_ net-_u42-pad2_ d_inverter +* u9 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u23 net-_u23-pad1_ net-_u10-pad2_ net-_u23-pad3_ d_nand +* u27 net-_u10-pad1_ net-_u25-pad2_ net-_u27-pad3_ d_and +* u25 net-_u23-pad1_ net-_u25-pad2_ net-_u25-pad3_ d_and +* u33 net-_u25-pad3_ net-_u27-pad3_ net-_u33-pad3_ d_nor +* u39 net-_u23-pad3_ net-_u33-pad3_ net-_u39-pad3_ d_and +* u57 net-_u49-pad2_ net-_u51-pad2_ net-_u23-pad1_ d_and +* u49 net-_u3-pad2_ net-_u49-pad2_ d_inverter +* u51 net-_u39-pad3_ net-_u51-pad2_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u24 net-_u23-pad1_ net-_u10-pad2_ net-_u23-pad3_ d_nand +* u28 net-_u10-pad1_ net-_u25-pad2_ net-_u27-pad3_ d_and +* u26 net-_u23-pad1_ net-_u25-pad2_ net-_u25-pad3_ d_and +* u34 net-_u25-pad3_ net-_u27-pad3_ net-_u33-pad3_ d_nor +* u40 net-_u23-pad3_ net-_u33-pad3_ net-_u39-pad3_ d_and +* u58 net-_u49-pad2_ net-_u51-pad2_ net-_u23-pad1_ d_and +* u50 net-_u3-pad2_ net-_u49-pad2_ d_inverter +* u52 net-_u39-pad3_ net-_u51-pad2_ d_inverter +* u7 net-_u10-pad1_ net-_u17-pad2_ d_inverter +* u17 net-_u17-pad1_ net-_u17-pad2_ net-_u17-pad3_ d_nand +* u21 net-_u10-pad1_ net-_u19-pad2_ net-_u21-pad3_ d_and +* u19 net-_u17-pad1_ net-_u19-pad2_ net-_u19-pad3_ d_and +* u31 net-_u19-pad3_ net-_u21-pad3_ net-_u31-pad3_ d_nor +* u37 net-_u17-pad3_ net-_u31-pad3_ net-_u37-pad3_ d_and +* u55 net-_u45-pad2_ net-_u47-pad2_ net-_u17-pad1_ d_and +* u45 net-_u3-pad2_ net-_u45-pad2_ d_inverter +* u47 net-_u37-pad3_ net-_u47-pad2_ d_inverter +* u8 net-_u10-pad1_ net-_u17-pad2_ d_inverter +* u18 net-_u17-pad1_ net-_u17-pad2_ net-_u17-pad3_ d_nand +* u22 net-_u10-pad1_ net-_u19-pad2_ net-_u21-pad3_ d_and +* u20 net-_u17-pad1_ net-_u19-pad2_ net-_u19-pad3_ d_and +* u32 net-_u19-pad3_ net-_u21-pad3_ net-_u31-pad3_ d_nor +* u38 net-_u17-pad3_ net-_u31-pad3_ net-_u37-pad3_ d_and +* u56 net-_u45-pad2_ net-_u47-pad2_ net-_u17-pad1_ d_and +* u46 net-_u3-pad2_ net-_u45-pad2_ d_inverter +* u48 net-_u37-pad3_ net-_u47-pad2_ d_inverter +* u43 net-_u3-pad2_ net-_u43-pad2_ d_inverter +* u62 net-_u59-pad13_ net-_u100-pad1_ d_inverter +* u63 net-_u60-pad2_ net-_u61-pad2_ net-_u63-pad3_ d_and +* u60 net-_u59-pad14_ net-_u60-pad2_ d_inverter +* u61 net-_u59-pad15_ net-_u61-pad2_ d_inverter +* u65 net-_u63-pad3_ net-_u65-pad2_ d_inverter +* u73 net-_u113-pad3_ net-_u65-pad2_ net-_u73-pad3_ d_nand +* u75 net-_u63-pad3_ net-_u59-pad16_ net-_u75-pad3_ d_and +* u74 net-_u113-pad3_ net-_u59-pad16_ net-_u74-pad3_ d_and +* u89 net-_u74-pad3_ net-_u75-pad3_ net-_u89-pad3_ d_nor +* u95 net-_u73-pad3_ net-_u89-pad3_ net-_u103-pad1_ d_and +* u113 net-_u102-pad2_ net-_u103-pad2_ net-_u113-pad3_ d_and +* u103 net-_u103-pad1_ net-_u103-pad2_ d_inverter +* u64 net-_u63-pad3_ net-_u64-pad2_ d_inverter +* u70 net-_u112-pad3_ net-_u64-pad2_ net-_u70-pad3_ d_nand +* u72 net-_u63-pad3_ net-_u59-pad18_ net-_u72-pad3_ d_and +* u71 net-_u112-pad3_ net-_u59-pad18_ net-_u71-pad3_ d_and +* u88 net-_u71-pad3_ net-_u72-pad3_ net-_u88-pad3_ d_nor +* u94 net-_u70-pad3_ net-_u88-pad3_ net-_u101-pad1_ d_and +* u112 net-_u100-pad2_ net-_u101-pad2_ net-_u112-pad3_ d_and +* u100 net-_u100-pad1_ net-_u100-pad2_ d_inverter +* u101 net-_u101-pad1_ net-_u101-pad2_ d_inverter +* u68 net-_u63-pad3_ net-_u68-pad2_ d_inverter +* u82 net-_u116-pad3_ net-_u68-pad2_ net-_u82-pad3_ d_nand +* u86 net-_u63-pad3_ net-_u59-pad22_ net-_u86-pad3_ d_and +* u84 net-_u116-pad3_ net-_u59-pad22_ net-_u84-pad3_ d_and +* u92 net-_u84-pad3_ net-_u86-pad3_ net-_u92-pad3_ d_nor +* u98 net-_u82-pad3_ net-_u92-pad3_ net-_u110-pad1_ d_and +* u116 net-_u108-pad2_ net-_u110-pad2_ net-_u116-pad3_ d_and +* u108 net-_u100-pad1_ net-_u108-pad2_ d_inverter +* u110 net-_u110-pad1_ net-_u110-pad2_ d_inverter +* u69 net-_u63-pad3_ net-_u68-pad2_ d_inverter +* u83 net-_u116-pad3_ net-_u68-pad2_ net-_u82-pad3_ d_nand +* u87 net-_u63-pad3_ net-_u59-pad22_ net-_u86-pad3_ d_and +* u85 net-_u116-pad3_ net-_u59-pad22_ net-_u84-pad3_ d_and +* u93 net-_u84-pad3_ net-_u86-pad3_ net-_u92-pad3_ d_nor +* u99 net-_u82-pad3_ net-_u92-pad3_ net-_u110-pad1_ d_and +* u117 net-_u108-pad2_ net-_u110-pad2_ net-_u116-pad3_ d_and +* u109 net-_u100-pad1_ net-_u108-pad2_ d_inverter +* u111 net-_u110-pad1_ net-_u110-pad2_ d_inverter +* u66 net-_u63-pad3_ net-_u66-pad2_ d_inverter +* u76 net-_u114-pad3_ net-_u66-pad2_ net-_u76-pad3_ d_nand +* u80 net-_u63-pad3_ net-_u59-pad20_ net-_u80-pad3_ d_and +* u78 net-_u114-pad3_ net-_u59-pad20_ net-_u78-pad3_ d_and +* u90 net-_u78-pad3_ net-_u80-pad3_ net-_u90-pad3_ d_nor +* u96 net-_u76-pad3_ net-_u90-pad3_ net-_u106-pad1_ d_and +* u114 net-_u104-pad2_ net-_u106-pad2_ net-_u114-pad3_ d_and +* u104 net-_u100-pad1_ net-_u104-pad2_ d_inverter +* u106 net-_u106-pad1_ net-_u106-pad2_ d_inverter +* u67 net-_u63-pad3_ net-_u66-pad2_ d_inverter +* u77 net-_u114-pad3_ net-_u66-pad2_ net-_u76-pad3_ d_nand +* u81 net-_u63-pad3_ net-_u59-pad20_ net-_u80-pad3_ d_and +* u79 net-_u114-pad3_ net-_u59-pad20_ net-_u78-pad3_ d_and +* u91 net-_u78-pad3_ net-_u80-pad3_ net-_u90-pad3_ d_nor +* u97 net-_u76-pad3_ net-_u90-pad3_ net-_u106-pad1_ d_and +* u115 net-_u104-pad2_ net-_u106-pad2_ net-_u114-pad3_ d_and +* u105 net-_u100-pad1_ net-_u104-pad2_ d_inverter +* u107 net-_u106-pad1_ net-_u106-pad2_ d_inverter +* u102 net-_u100-pad1_ net-_u102-pad2_ d_inverter +* u59 net-_u3-pad1_ net-_u1-pad1_ net-_u2-pad1_ net-_u15-pad2_ net-_u14-pad1_ net-_u12-pad2_ net-_u11-pad1_ net-_u19-pad2_ net-_u17-pad1_ net-_u25-pad2_ net-_u23-pad1_ ? net-_u59-pad13_ net-_u59-pad14_ net-_u59-pad15_ net-_u59-pad16_ net-_u113-pad3_ net-_u59-pad18_ net-_u112-pad3_ net-_u59-pad20_ net-_u114-pad3_ net-_u59-pad22_ net-_u116-pad3_ ? port +a1 net-_u3-pad1_ net-_u3-pad2_ u3 +a2 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u10-pad1_ u4 +a3 net-_u1-pad1_ net-_u1-pad2_ u1 +a4 net-_u2-pad1_ net-_u2-pad2_ u2 +a5 net-_u10-pad1_ net-_u14-pad2_ u6 +a6 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14 +a7 [net-_u10-pad1_ net-_u15-pad2_ ] net-_u16-pad3_ u16 +a8 [net-_u14-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15 +a9 [net-_u15-pad3_ net-_u16-pad3_ ] net-_u30-pad3_ u30 +a10 [net-_u14-pad3_ net-_u30-pad3_ ] net-_u36-pad3_ u36 +a11 [net-_u43-pad2_ net-_u44-pad2_ ] net-_u14-pad1_ u54 +a12 net-_u36-pad3_ net-_u44-pad2_ u44 +a13 net-_u10-pad1_ net-_u11-pad2_ u5 +a14 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a15 [net-_u10-pad1_ net-_u12-pad2_ ] net-_u13-pad3_ u13 +a16 [net-_u11-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +a17 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u29-pad3_ u29 +a18 [net-_u11-pad3_ net-_u29-pad3_ ] net-_u35-pad3_ u35 +a19 [net-_u41-pad2_ net-_u42-pad2_ ] net-_u11-pad1_ u53 +a20 net-_u3-pad2_ net-_u41-pad2_ u41 +a21 net-_u35-pad3_ net-_u42-pad2_ u42 +a22 net-_u10-pad1_ net-_u10-pad2_ u9 +a23 [net-_u23-pad1_ net-_u10-pad2_ ] net-_u23-pad3_ u23 +a24 [net-_u10-pad1_ net-_u25-pad2_ ] net-_u27-pad3_ u27 +a25 [net-_u23-pad1_ net-_u25-pad2_ ] net-_u25-pad3_ u25 +a26 [net-_u25-pad3_ net-_u27-pad3_ ] net-_u33-pad3_ u33 +a27 [net-_u23-pad3_ net-_u33-pad3_ ] net-_u39-pad3_ u39 +a28 [net-_u49-pad2_ net-_u51-pad2_ ] net-_u23-pad1_ u57 +a29 net-_u3-pad2_ net-_u49-pad2_ u49 +a30 net-_u39-pad3_ net-_u51-pad2_ u51 +a31 net-_u10-pad1_ net-_u10-pad2_ u10 +a32 [net-_u23-pad1_ net-_u10-pad2_ ] net-_u23-pad3_ u24 +a33 [net-_u10-pad1_ net-_u25-pad2_ ] net-_u27-pad3_ u28 +a34 [net-_u23-pad1_ net-_u25-pad2_ ] net-_u25-pad3_ u26 +a35 [net-_u25-pad3_ net-_u27-pad3_ ] net-_u33-pad3_ u34 +a36 [net-_u23-pad3_ net-_u33-pad3_ ] net-_u39-pad3_ u40 +a37 [net-_u49-pad2_ net-_u51-pad2_ ] net-_u23-pad1_ u58 +a38 net-_u3-pad2_ net-_u49-pad2_ u50 +a39 net-_u39-pad3_ net-_u51-pad2_ u52 +a40 net-_u10-pad1_ net-_u17-pad2_ u7 +a41 [net-_u17-pad1_ net-_u17-pad2_ ] net-_u17-pad3_ u17 +a42 [net-_u10-pad1_ net-_u19-pad2_ ] net-_u21-pad3_ u21 +a43 [net-_u17-pad1_ net-_u19-pad2_ ] net-_u19-pad3_ u19 +a44 [net-_u19-pad3_ net-_u21-pad3_ ] net-_u31-pad3_ u31 +a45 [net-_u17-pad3_ net-_u31-pad3_ ] net-_u37-pad3_ u37 +a46 [net-_u45-pad2_ net-_u47-pad2_ ] net-_u17-pad1_ u55 +a47 net-_u3-pad2_ net-_u45-pad2_ u45 +a48 net-_u37-pad3_ net-_u47-pad2_ u47 +a49 net-_u10-pad1_ net-_u17-pad2_ u8 +a50 [net-_u17-pad1_ net-_u17-pad2_ ] net-_u17-pad3_ u18 +a51 [net-_u10-pad1_ net-_u19-pad2_ ] net-_u21-pad3_ u22 +a52 [net-_u17-pad1_ net-_u19-pad2_ ] net-_u19-pad3_ u20 +a53 [net-_u19-pad3_ net-_u21-pad3_ ] net-_u31-pad3_ u32 +a54 [net-_u17-pad3_ net-_u31-pad3_ ] net-_u37-pad3_ u38 +a55 [net-_u45-pad2_ net-_u47-pad2_ ] net-_u17-pad1_ u56 +a56 net-_u3-pad2_ net-_u45-pad2_ u46 +a57 net-_u37-pad3_ net-_u47-pad2_ u48 +a58 net-_u3-pad2_ net-_u43-pad2_ u43 +a59 net-_u59-pad13_ net-_u100-pad1_ u62 +a60 [net-_u60-pad2_ net-_u61-pad2_ ] net-_u63-pad3_ u63 +a61 net-_u59-pad14_ net-_u60-pad2_ u60 +a62 net-_u59-pad15_ net-_u61-pad2_ u61 +a63 net-_u63-pad3_ net-_u65-pad2_ u65 +a64 [net-_u113-pad3_ net-_u65-pad2_ ] net-_u73-pad3_ u73 +a65 [net-_u63-pad3_ net-_u59-pad16_ ] net-_u75-pad3_ u75 +a66 [net-_u113-pad3_ net-_u59-pad16_ ] net-_u74-pad3_ u74 +a67 [net-_u74-pad3_ net-_u75-pad3_ ] net-_u89-pad3_ u89 +a68 [net-_u73-pad3_ net-_u89-pad3_ ] net-_u103-pad1_ u95 +a69 [net-_u102-pad2_ net-_u103-pad2_ ] net-_u113-pad3_ u113 +a70 net-_u103-pad1_ net-_u103-pad2_ u103 +a71 net-_u63-pad3_ net-_u64-pad2_ u64 +a72 [net-_u112-pad3_ net-_u64-pad2_ ] net-_u70-pad3_ u70 +a73 [net-_u63-pad3_ net-_u59-pad18_ ] net-_u72-pad3_ u72 +a74 [net-_u112-pad3_ net-_u59-pad18_ ] net-_u71-pad3_ u71 +a75 [net-_u71-pad3_ net-_u72-pad3_ ] net-_u88-pad3_ u88 +a76 [net-_u70-pad3_ net-_u88-pad3_ ] net-_u101-pad1_ u94 +a77 [net-_u100-pad2_ net-_u101-pad2_ ] net-_u112-pad3_ u112 +a78 net-_u100-pad1_ net-_u100-pad2_ u100 +a79 net-_u101-pad1_ net-_u101-pad2_ u101 +a80 net-_u63-pad3_ net-_u68-pad2_ u68 +a81 [net-_u116-pad3_ net-_u68-pad2_ ] net-_u82-pad3_ u82 +a82 [net-_u63-pad3_ net-_u59-pad22_ ] net-_u86-pad3_ u86 +a83 [net-_u116-pad3_ net-_u59-pad22_ ] net-_u84-pad3_ u84 +a84 [net-_u84-pad3_ net-_u86-pad3_ ] net-_u92-pad3_ u92 +a85 [net-_u82-pad3_ net-_u92-pad3_ ] net-_u110-pad1_ u98 +a86 [net-_u108-pad2_ net-_u110-pad2_ ] net-_u116-pad3_ u116 +a87 net-_u100-pad1_ net-_u108-pad2_ u108 +a88 net-_u110-pad1_ net-_u110-pad2_ u110 +a89 net-_u63-pad3_ net-_u68-pad2_ u69 +a90 [net-_u116-pad3_ net-_u68-pad2_ ] net-_u82-pad3_ u83 +a91 [net-_u63-pad3_ net-_u59-pad22_ ] net-_u86-pad3_ u87 +a92 [net-_u116-pad3_ net-_u59-pad22_ ] net-_u84-pad3_ u85 +a93 [net-_u84-pad3_ net-_u86-pad3_ ] net-_u92-pad3_ u93 +a94 [net-_u82-pad3_ net-_u92-pad3_ ] net-_u110-pad1_ u99 +a95 [net-_u108-pad2_ net-_u110-pad2_ ] net-_u116-pad3_ u117 +a96 net-_u100-pad1_ net-_u108-pad2_ u109 +a97 net-_u110-pad1_ net-_u110-pad2_ u111 +a98 net-_u63-pad3_ net-_u66-pad2_ u66 +a99 [net-_u114-pad3_ net-_u66-pad2_ ] net-_u76-pad3_ u76 +a100 [net-_u63-pad3_ net-_u59-pad20_ ] net-_u80-pad3_ u80 +a101 [net-_u114-pad3_ net-_u59-pad20_ ] net-_u78-pad3_ u78 +a102 [net-_u78-pad3_ net-_u80-pad3_ ] net-_u90-pad3_ u90 +a103 [net-_u76-pad3_ net-_u90-pad3_ ] net-_u106-pad1_ u96 +a104 [net-_u104-pad2_ net-_u106-pad2_ ] net-_u114-pad3_ u114 +a105 net-_u100-pad1_ net-_u104-pad2_ u104 +a106 net-_u106-pad1_ net-_u106-pad2_ u106 +a107 net-_u63-pad3_ net-_u66-pad2_ u67 +a108 [net-_u114-pad3_ net-_u66-pad2_ ] net-_u76-pad3_ u77 +a109 [net-_u63-pad3_ net-_u59-pad20_ ] net-_u80-pad3_ u81 +a110 [net-_u114-pad3_ net-_u59-pad20_ ] net-_u78-pad3_ u79 +a111 [net-_u78-pad3_ net-_u80-pad3_ ] net-_u90-pad3_ u91 +a112 [net-_u76-pad3_ net-_u90-pad3_ ] net-_u106-pad1_ u97 +a113 [net-_u104-pad2_ net-_u106-pad2_ ] net-_u114-pad3_ u115 +a114 net-_u100-pad1_ net-_u104-pad2_ u105 +a115 net-_u106-pad1_ net-_u106-pad2_ u107 +a116 net-_u100-pad1_ net-_u102-pad2_ u102 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u14 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u30 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u36 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u54 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u44 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u11 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u29 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u35 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u53 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u41 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u42 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u23 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u27 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u33 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u39 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u57 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u49 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u51 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u24 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u34 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u40 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u58 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u50 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u52 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u17 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u31 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u37 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u55 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u45 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u47 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u18 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u32 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u38 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u56 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u46 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u48 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u43 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u62 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u63 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u60 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u61 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u65 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u73 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u75 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u74 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u89 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u95 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u113 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u103 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u64 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u70 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u72 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u71 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u88 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u94 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u112 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u100 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u101 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u68 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u82 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u86 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u84 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u92 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u98 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u116 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u108 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u110 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u69 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u83 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u87 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u85 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u93 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u99 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u117 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u109 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u111 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u66 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u76 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u80 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u78 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u90 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u96 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u114 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u104 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u106 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u67 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u77 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u81 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u79 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u91 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u97 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u115 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u105 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u107 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u102 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74116/SN74116.pro b/library/SubcircuitLibrary/SN74116/SN74116.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/SN74116/SN74116.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN74116/SN74116.sch b/library/SubcircuitLibrary/SN74116/SN74116.sch new file mode 100644 index 000000000..59063a388 --- /dev/null +++ b/library/SubcircuitLibrary/SN74116/SN74116.sch @@ -0,0 +1,2087 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SN74116-cache +EELAYER 25 0 +EELAYER END +$Descr A2 23386 16535 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_inverter U3 +U 1 1 68690CB4 +P 4100 3850 +F 0 "U3" H 4100 3750 60 0000 C CNN +F 1 "d_inverter" H 4100 4000 60 0000 C CNN +F 2 "" H 4150 3800 60 0000 C CNN +F 3 "" H 4150 3800 60 0000 C CNN + 1 4100 3850 + 1 0 0 -1 +$EndComp +$Comp +L d_and U4 +U 1 1 68690DA8 +P 4250 4400 +F 0 "U4" H 4250 4400 60 0000 C CNN +F 1 "d_and" H 4300 4500 60 0000 C CNN +F 2 "" H 4250 4400 60 0000 C CNN +F 3 "" H 4250 4400 60 0000 C CNN + 1 4250 4400 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U1 +U 1 1 68690E39 +P 3350 4200 +F 0 "U1" H 3350 4100 60 0000 C CNN +F 1 "d_inverter" H 3350 4350 60 0000 C CNN +F 2 "" H 3400 4150 60 0000 C CNN +F 3 "" H 3400 4150 60 0000 C CNN + 1 3350 4200 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 68690E58 +P 3350 4400 +F 0 "U2" H 3350 4300 60 0000 C CNN +F 1 "d_inverter" H 3350 4550 60 0000 C CNN +F 2 "" H 3400 4350 60 0000 C CNN +F 3 "" H 3400 4350 60 0000 C CNN + 1 3350 4400 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 68690EFC +P 5200 4350 +F 0 "U6" H 5200 4250 60 0000 C CNN +F 1 "d_inverter" H 5200 4500 60 0000 C CNN +F 2 "" H 5250 4300 60 0000 C CNN +F 3 "" H 5250 4300 60 0000 C CNN + 1 5200 4350 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U14 +U 1 1 68690F7B +P 6050 4350 +F 0 "U14" H 6050 4350 60 0000 C CNN +F 1 "d_nand" H 6100 4450 60 0000 C CNN +F 2 "" H 6050 4350 60 0000 C CNN +F 3 "" H 6050 4350 60 0000 C CNN + 1 6050 4350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U16 +U 1 1 6869108F +P 6050 5000 +F 0 "U16" H 6050 5000 60 0000 C CNN +F 1 "d_and" H 6100 5100 60 0000 C CNN +F 2 "" H 6050 5000 60 0000 C CNN +F 3 "" H 6050 5000 60 0000 C CNN + 1 6050 5000 + 1 0 0 -1 +$EndComp +$Comp +L d_and U15 +U 1 1 686910CF +P 6050 4700 +F 0 "U15" H 6050 4700 60 0000 C CNN +F 1 "d_and" H 6100 4800 60 0000 C CNN +F 2 "" H 6050 4700 60 0000 C CNN +F 3 "" H 6050 4700 60 0000 C CNN + 1 6050 4700 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U30 +U 1 1 68691206 +P 7050 4850 +F 0 "U30" H 7050 4850 60 0000 C CNN +F 1 "d_nor" H 7100 4950 60 0000 C CNN +F 2 "" H 7050 4850 60 0000 C CNN +F 3 "" H 7050 4850 60 0000 C CNN + 1 7050 4850 + 1 0 0 -1 +$EndComp +$Comp +L d_and U36 +U 1 1 686912C9 +P 8050 4450 +F 0 "U36" H 8050 4450 60 0000 C CNN +F 1 "d_and" H 8100 4550 60 0000 C CNN +F 2 "" H 8050 4450 60 0000 C CNN +F 3 "" H 8050 4450 60 0000 C CNN + 1 8050 4450 + 1 0 0 -1 +$EndComp +$Comp +L d_and U54 +U 1 1 68691AAE +P 9850 4400 +F 0 "U54" H 9850 4400 60 0000 C CNN +F 1 "d_and" H 9900 4500 60 0000 C CNN +F 2 "" H 9850 4400 60 0000 C CNN +F 3 "" H 9850 4400 60 0000 C CNN + 1 9850 4400 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U44 +U 1 1 68691ABA +P 8950 4400 +F 0 "U44" H 8950 4300 60 0000 C CNN +F 1 "d_inverter" H 8950 4550 60 0000 C CNN +F 2 "" H 9000 4350 60 0000 C CNN +F 3 "" H 9000 4350 60 0000 C CNN + 1 8950 4400 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U5 +U 1 1 68692CC3 +P 5150 5650 +F 0 "U5" H 5150 5550 60 0000 C CNN +F 1 "d_inverter" H 5150 5800 60 0000 C CNN +F 2 "" H 5200 5600 60 0000 C CNN +F 3 "" H 5200 5600 60 0000 C CNN + 1 5150 5650 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U11 +U 1 1 68692CC9 +P 6000 5650 +F 0 "U11" H 6000 5650 60 0000 C CNN +F 1 "d_nand" H 6050 5750 60 0000 C CNN +F 2 "" H 6000 5650 60 0000 C CNN +F 3 "" H 6000 5650 60 0000 C CNN + 1 6000 5650 + 1 0 0 -1 +$EndComp +$Comp +L d_and U13 +U 1 1 68692CCF +P 6000 6300 +F 0 "U13" H 6000 6300 60 0000 C CNN +F 1 "d_and" H 6050 6400 60 0000 C CNN +F 2 "" H 6000 6300 60 0000 C CNN +F 3 "" H 6000 6300 60 0000 C CNN + 1 6000 6300 + 1 0 0 -1 +$EndComp +$Comp +L d_and U12 +U 1 1 68692CD5 +P 6000 6000 +F 0 "U12" H 6000 6000 60 0000 C CNN +F 1 "d_and" H 6050 6100 60 0000 C CNN +F 2 "" H 6000 6000 60 0000 C CNN +F 3 "" H 6000 6000 60 0000 C CNN + 1 6000 6000 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U29 +U 1 1 68692CDB +P 7000 6150 +F 0 "U29" H 7000 6150 60 0000 C CNN +F 1 "d_nor" H 7050 6250 60 0000 C CNN +F 2 "" H 7000 6150 60 0000 C CNN +F 3 "" H 7000 6150 60 0000 C CNN + 1 7000 6150 + 1 0 0 -1 +$EndComp +$Comp +L d_and U35 +U 1 1 68692CE1 +P 8000 5750 +F 0 "U35" H 8000 5750 60 0000 C CNN +F 1 "d_and" H 8050 5850 60 0000 C CNN +F 2 "" H 8000 5750 60 0000 C CNN +F 3 "" H 8000 5750 60 0000 C CNN + 1 8000 5750 + 1 0 0 -1 +$EndComp +$Comp +L d_and U53 +U 1 1 68692CE7 +P 9800 5700 +F 0 "U53" H 9800 5700 60 0000 C CNN +F 1 "d_and" H 9850 5800 60 0000 C CNN +F 2 "" H 9800 5700 60 0000 C CNN +F 3 "" H 9800 5700 60 0000 C CNN + 1 9800 5700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U41 +U 1 1 68692CED +P 8900 5500 +F 0 "U41" H 8900 5400 60 0000 C CNN +F 1 "d_inverter" H 8900 5650 60 0000 C CNN +F 2 "" H 8950 5450 60 0000 C CNN +F 3 "" H 8950 5450 60 0000 C CNN + 1 8900 5500 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U42 +U 1 1 68692CF3 +P 8900 5700 +F 0 "U42" H 8900 5600 60 0000 C CNN +F 1 "d_inverter" H 8900 5850 60 0000 C CNN +F 2 "" H 8950 5650 60 0000 C CNN +F 3 "" H 8950 5650 60 0000 C CNN + 1 8900 5700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U9 +U 1 1 68693622 +P 5250 8100 +F 0 "U9" H 5250 8000 60 0000 C CNN +F 1 "d_inverter" H 5250 8250 60 0000 C CNN +F 2 "" H 5300 8050 60 0000 C CNN +F 3 "" H 5300 8050 60 0000 C CNN + 1 5250 8100 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U23 +U 1 1 68693628 +P 6100 8100 +F 0 "U23" H 6100 8100 60 0000 C CNN +F 1 "d_nand" H 6150 8200 60 0000 C CNN +F 2 "" H 6100 8100 60 0000 C CNN +F 3 "" H 6100 8100 60 0000 C CNN + 1 6100 8100 + 1 0 0 -1 +$EndComp +$Comp +L d_and U27 +U 1 1 6869362E +P 6100 8750 +F 0 "U27" H 6100 8750 60 0000 C CNN +F 1 "d_and" H 6150 8850 60 0000 C CNN +F 2 "" H 6100 8750 60 0000 C CNN +F 3 "" H 6100 8750 60 0000 C CNN + 1 6100 8750 + 1 0 0 -1 +$EndComp +$Comp +L d_and U25 +U 1 1 68693634 +P 6100 8450 +F 0 "U25" H 6100 8450 60 0000 C CNN +F 1 "d_and" H 6150 8550 60 0000 C CNN +F 2 "" H 6100 8450 60 0000 C CNN +F 3 "" H 6100 8450 60 0000 C CNN + 1 6100 8450 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U33 +U 1 1 6869363A +P 7100 8600 +F 0 "U33" H 7100 8600 60 0000 C CNN +F 1 "d_nor" H 7150 8700 60 0000 C CNN +F 2 "" H 7100 8600 60 0000 C CNN +F 3 "" H 7100 8600 60 0000 C CNN + 1 7100 8600 + 1 0 0 -1 +$EndComp +$Comp +L d_and U39 +U 1 1 68693640 +P 8100 8200 +F 0 "U39" H 8100 8200 60 0000 C CNN +F 1 "d_and" H 8150 8300 60 0000 C CNN +F 2 "" H 8100 8200 60 0000 C CNN +F 3 "" H 8100 8200 60 0000 C CNN + 1 8100 8200 + 1 0 0 -1 +$EndComp +$Comp +L d_and U57 +U 1 1 68693646 +P 9900 8150 +F 0 "U57" H 9900 8150 60 0000 C CNN +F 1 "d_and" H 9950 8250 60 0000 C CNN +F 2 "" H 9900 8150 60 0000 C CNN +F 3 "" H 9900 8150 60 0000 C CNN + 1 9900 8150 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U49 +U 1 1 6869364C +P 9000 7950 +F 0 "U49" H 9000 7850 60 0000 C CNN +F 1 "d_inverter" H 9000 8100 60 0000 C CNN +F 2 "" H 9050 7900 60 0000 C CNN +F 3 "" H 9050 7900 60 0000 C CNN + 1 9000 7950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U51 +U 1 1 68693652 +P 9000 8150 +F 0 "U51" H 9000 8050 60 0000 C CNN +F 1 "d_inverter" H 9000 8300 60 0000 C CNN +F 2 "" H 9050 8100 60 0000 C CNN +F 3 "" H 9050 8100 60 0000 C CNN + 1 9000 8150 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U10 +U 1 1 68693BE5 +P 5250 8100 +F 0 "U10" H 5250 8000 60 0000 C CNN +F 1 "d_inverter" H 5250 8250 60 0000 C CNN +F 2 "" H 5300 8050 60 0000 C CNN +F 3 "" H 5300 8050 60 0000 C CNN + 1 5250 8100 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U24 +U 1 1 68693BEB +P 6100 8100 +F 0 "U24" H 6100 8100 60 0000 C CNN +F 1 "d_nand" H 6150 8200 60 0000 C CNN +F 2 "" H 6100 8100 60 0000 C CNN +F 3 "" H 6100 8100 60 0000 C CNN + 1 6100 8100 + 1 0 0 -1 +$EndComp +$Comp +L d_and U28 +U 1 1 68693BF1 +P 6100 8750 +F 0 "U28" H 6100 8750 60 0000 C CNN +F 1 "d_and" H 6150 8850 60 0000 C CNN +F 2 "" H 6100 8750 60 0000 C CNN +F 3 "" H 6100 8750 60 0000 C CNN + 1 6100 8750 + 1 0 0 -1 +$EndComp +$Comp +L d_and U26 +U 1 1 68693BF7 +P 6100 8450 +F 0 "U26" H 6100 8450 60 0000 C CNN +F 1 "d_and" H 6150 8550 60 0000 C CNN +F 2 "" H 6100 8450 60 0000 C CNN +F 3 "" H 6100 8450 60 0000 C CNN + 1 6100 8450 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U34 +U 1 1 68693BFD +P 7100 8600 +F 0 "U34" H 7100 8600 60 0000 C CNN +F 1 "d_nor" H 7150 8700 60 0000 C CNN +F 2 "" H 7100 8600 60 0000 C CNN +F 3 "" H 7100 8600 60 0000 C CNN + 1 7100 8600 + 1 0 0 -1 +$EndComp +$Comp +L d_and U40 +U 1 1 68693C03 +P 8100 8200 +F 0 "U40" H 8100 8200 60 0000 C CNN +F 1 "d_and" H 8150 8300 60 0000 C CNN +F 2 "" H 8100 8200 60 0000 C CNN +F 3 "" H 8100 8200 60 0000 C CNN + 1 8100 8200 + 1 0 0 -1 +$EndComp +$Comp +L d_and U58 +U 1 1 68693C09 +P 9900 8150 +F 0 "U58" H 9900 8150 60 0000 C CNN +F 1 "d_and" H 9950 8250 60 0000 C CNN +F 2 "" H 9900 8150 60 0000 C CNN +F 3 "" H 9900 8150 60 0000 C CNN + 1 9900 8150 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U50 +U 1 1 68693C0F +P 9000 7950 +F 0 "U50" H 9000 7850 60 0000 C CNN +F 1 "d_inverter" H 9000 8100 60 0000 C CNN +F 2 "" H 9050 7900 60 0000 C CNN +F 3 "" H 9050 7900 60 0000 C CNN + 1 9000 7950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U52 +U 1 1 68693C15 +P 9000 8150 +F 0 "U52" H 9000 8050 60 0000 C CNN +F 1 "d_inverter" H 9000 8300 60 0000 C CNN +F 2 "" H 9050 8100 60 0000 C CNN +F 3 "" H 9050 8100 60 0000 C CNN + 1 9000 8150 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 686942A3 +P 5200 6900 +F 0 "U7" H 5200 6800 60 0000 C CNN +F 1 "d_inverter" H 5200 7050 60 0000 C CNN +F 2 "" H 5250 6850 60 0000 C CNN +F 3 "" H 5250 6850 60 0000 C CNN + 1 5200 6900 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U17 +U 1 1 686942A9 +P 6050 6900 +F 0 "U17" H 6050 6900 60 0000 C CNN +F 1 "d_nand" H 6100 7000 60 0000 C CNN +F 2 "" H 6050 6900 60 0000 C CNN +F 3 "" H 6050 6900 60 0000 C CNN + 1 6050 6900 + 1 0 0 -1 +$EndComp +$Comp +L d_and U21 +U 1 1 686942AF +P 6050 7550 +F 0 "U21" H 6050 7550 60 0000 C CNN +F 1 "d_and" H 6100 7650 60 0000 C CNN +F 2 "" H 6050 7550 60 0000 C CNN +F 3 "" H 6050 7550 60 0000 C CNN + 1 6050 7550 + 1 0 0 -1 +$EndComp +$Comp +L d_and U19 +U 1 1 686942B5 +P 6050 7250 +F 0 "U19" H 6050 7250 60 0000 C CNN +F 1 "d_and" H 6100 7350 60 0000 C CNN +F 2 "" H 6050 7250 60 0000 C CNN +F 3 "" H 6050 7250 60 0000 C CNN + 1 6050 7250 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U31 +U 1 1 686942BB +P 7050 7400 +F 0 "U31" H 7050 7400 60 0000 C CNN +F 1 "d_nor" H 7100 7500 60 0000 C CNN +F 2 "" H 7050 7400 60 0000 C CNN +F 3 "" H 7050 7400 60 0000 C CNN + 1 7050 7400 + 1 0 0 -1 +$EndComp +$Comp +L d_and U37 +U 1 1 686942C1 +P 8050 7000 +F 0 "U37" H 8050 7000 60 0000 C CNN +F 1 "d_and" H 8100 7100 60 0000 C CNN +F 2 "" H 8050 7000 60 0000 C CNN +F 3 "" H 8050 7000 60 0000 C CNN + 1 8050 7000 + 1 0 0 -1 +$EndComp +$Comp +L d_and U55 +U 1 1 686942C7 +P 9850 6950 +F 0 "U55" H 9850 6950 60 0000 C CNN +F 1 "d_and" H 9900 7050 60 0000 C CNN +F 2 "" H 9850 6950 60 0000 C CNN +F 3 "" H 9850 6950 60 0000 C CNN + 1 9850 6950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U45 +U 1 1 686942CD +P 8950 6750 +F 0 "U45" H 8950 6650 60 0000 C CNN +F 1 "d_inverter" H 8950 6900 60 0000 C CNN +F 2 "" H 9000 6700 60 0000 C CNN +F 3 "" H 9000 6700 60 0000 C CNN + 1 8950 6750 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U47 +U 1 1 686942D3 +P 8950 6950 +F 0 "U47" H 8950 6850 60 0000 C CNN +F 1 "d_inverter" H 8950 7100 60 0000 C CNN +F 2 "" H 9000 6900 60 0000 C CNN +F 3 "" H 9000 6900 60 0000 C CNN + 1 8950 6950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U8 +U 1 1 686942D9 +P 5200 6900 +F 0 "U8" H 5200 6800 60 0000 C CNN +F 1 "d_inverter" H 5200 7050 60 0000 C CNN +F 2 "" H 5250 6850 60 0000 C CNN +F 3 "" H 5250 6850 60 0000 C CNN + 1 5200 6900 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U18 +U 1 1 686942DF +P 6050 6900 +F 0 "U18" H 6050 6900 60 0000 C CNN +F 1 "d_nand" H 6100 7000 60 0000 C CNN +F 2 "" H 6050 6900 60 0000 C CNN +F 3 "" H 6050 6900 60 0000 C CNN + 1 6050 6900 + 1 0 0 -1 +$EndComp +$Comp +L d_and U22 +U 1 1 686942E5 +P 6050 7550 +F 0 "U22" H 6050 7550 60 0000 C CNN +F 1 "d_and" H 6100 7650 60 0000 C CNN +F 2 "" H 6050 7550 60 0000 C CNN +F 3 "" H 6050 7550 60 0000 C CNN + 1 6050 7550 + 1 0 0 -1 +$EndComp +$Comp +L d_and U20 +U 1 1 686942EB +P 6050 7250 +F 0 "U20" H 6050 7250 60 0000 C CNN +F 1 "d_and" H 6100 7350 60 0000 C CNN +F 2 "" H 6050 7250 60 0000 C CNN +F 3 "" H 6050 7250 60 0000 C CNN + 1 6050 7250 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U32 +U 1 1 686942F1 +P 7050 7400 +F 0 "U32" H 7050 7400 60 0000 C CNN +F 1 "d_nor" H 7100 7500 60 0000 C CNN +F 2 "" H 7050 7400 60 0000 C CNN +F 3 "" H 7050 7400 60 0000 C CNN + 1 7050 7400 + 1 0 0 -1 +$EndComp +$Comp +L d_and U38 +U 1 1 686942F7 +P 8050 7000 +F 0 "U38" H 8050 7000 60 0000 C CNN +F 1 "d_and" H 8100 7100 60 0000 C CNN +F 2 "" H 8050 7000 60 0000 C CNN +F 3 "" H 8050 7000 60 0000 C CNN + 1 8050 7000 + 1 0 0 -1 +$EndComp +$Comp +L d_and U56 +U 1 1 686942FD +P 9850 6950 +F 0 "U56" H 9850 6950 60 0000 C CNN +F 1 "d_and" H 9900 7050 60 0000 C CNN +F 2 "" H 9850 6950 60 0000 C CNN +F 3 "" H 9850 6950 60 0000 C CNN + 1 9850 6950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U46 +U 1 1 68694303 +P 8950 6750 +F 0 "U46" H 8950 6650 60 0000 C CNN +F 1 "d_inverter" H 8950 6900 60 0000 C CNN +F 2 "" H 9000 6700 60 0000 C CNN +F 3 "" H 9000 6700 60 0000 C CNN + 1 8950 6750 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U48 +U 1 1 68694309 +P 8950 6950 +F 0 "U48" H 8950 6850 60 0000 C CNN +F 1 "d_inverter" H 8950 7100 60 0000 C CNN +F 2 "" H 9000 6900 60 0000 C CNN +F 3 "" H 9000 6900 60 0000 C CNN + 1 8950 6950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U43 +U 1 1 68691AB4 +P 8950 4200 +F 0 "U43" H 8950 4100 60 0000 C CNN +F 1 "d_inverter" H 8950 4350 60 0000 C CNN +F 2 "" H 9000 4150 60 0000 C CNN +F 3 "" H 9000 4150 60 0000 C CNN + 1 8950 4200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3650 4200 3800 4200 +Wire Wire Line + 3800 4200 3800 4300 +Wire Wire Line + 3650 4400 3800 4400 +Wire Wire Line + 4700 4350 4900 4350 +Wire Wire Line + 5500 4350 5600 4350 +Wire Wire Line + 5600 4250 5500 4250 +Wire Wire Line + 5500 3750 5500 4600 +Wire Wire Line + 5500 4600 5600 4600 +Wire Wire Line + 5600 4700 5500 4700 +Wire Wire Line + 5500 4700 5500 5000 +Wire Wire Line + 3900 5000 5600 5000 +Wire Wire Line + 4800 4350 4800 8650 +Wire Wire Line + 4800 4900 5600 4900 +Connection ~ 4800 4350 +Wire Wire Line + 6500 4650 6600 4650 +Wire Wire Line + 6600 4650 6600 4750 +Wire Wire Line + 6500 4950 6600 4950 +Wire Wire Line + 6600 4950 6600 4850 +Wire Wire Line + 7500 4800 7600 4800 +Wire Wire Line + 7600 4800 7600 4450 +Wire Wire Line + 6500 4300 7600 4300 +Wire Wire Line + 7600 4300 7600 4350 +Wire Wire Line + 8500 4400 8650 4400 +Wire Wire Line + 9250 4400 9400 4400 +Wire Wire Line + 9250 4200 9400 4200 +Wire Wire Line + 9400 4200 9400 4300 +Wire Wire Line + 4400 3850 8650 3850 +Wire Wire Line + 10300 4350 10900 4350 +Wire Wire Line + 10450 4350 10450 3750 +Wire Wire Line + 10450 3750 5500 3750 +Connection ~ 5500 4250 +Connection ~ 5500 5000 +Wire Wire Line + 4800 5650 4850 5650 +Connection ~ 4800 4900 +Wire Wire Line + 5450 5650 5550 5650 +Wire Wire Line + 6450 5600 7550 5600 +Wire Wire Line + 7550 5600 7550 5650 +Wire Wire Line + 5550 5550 5450 5550 +Wire Wire Line + 5450 5250 5450 5900 +Wire Wire Line + 5450 5900 5550 5900 +Wire Wire Line + 5550 6000 5450 6000 +Wire Wire Line + 5450 6000 5450 6300 +Wire Wire Line + 3850 6300 5550 6300 +Wire Wire Line + 6450 5950 6550 5950 +Wire Wire Line + 6550 5950 6550 6050 +Wire Wire Line + 6450 6250 6550 6250 +Wire Wire Line + 6550 6250 6550 6150 +Wire Wire Line + 7450 6100 7550 6100 +Wire Wire Line + 7550 6100 7550 5750 +Wire Wire Line + 8450 5700 8600 5700 +Wire Wire Line + 8650 3850 8650 4000 +Wire Wire Line + 8650 4000 8500 4000 +Wire Wire Line + 8500 4000 8500 7950 +Wire Wire Line + 8500 4200 8650 4200 +Wire Wire Line + 8500 5500 8600 5500 +Connection ~ 8500 4200 +Wire Wire Line + 9200 5500 9350 5500 +Wire Wire Line + 9350 5500 9350 5600 +Wire Wire Line + 9200 5700 9350 5700 +Wire Wire Line + 10250 5650 10900 5650 +Wire Wire Line + 10450 5650 10450 5250 +Wire Wire Line + 10450 5250 5450 5250 +Connection ~ 5450 5550 +Connection ~ 5450 6300 +Wire Wire Line + 4800 6200 5550 6200 +Connection ~ 4800 5650 +Wire Wire Line + 4800 6900 4900 6900 +Connection ~ 4800 6200 +Wire Wire Line + 5500 6900 5600 6900 +Wire Wire Line + 6500 6850 7600 6850 +Wire Wire Line + 7600 6850 7600 6900 +Wire Wire Line + 6500 7200 6600 7200 +Wire Wire Line + 6600 7200 6600 7300 +Wire Wire Line + 6500 7500 6600 7500 +Wire Wire Line + 6600 7500 6600 7400 +Wire Wire Line + 7500 7350 7600 7350 +Wire Wire Line + 7600 7350 7600 7000 +Wire Wire Line + 8500 6950 8650 6950 +Wire Wire Line + 8500 6750 8650 6750 +Connection ~ 8500 5500 +Wire Wire Line + 9400 6750 9400 6850 +Wire Wire Line + 9250 6950 9400 6950 +Wire Wire Line + 9250 6750 9400 6750 +Wire Wire Line + 10300 6900 11000 6900 +Wire Wire Line + 10450 6900 10450 6500 +Wire Wire Line + 10450 6500 5500 6500 +Wire Wire Line + 5500 6500 5500 7150 +Wire Wire Line + 5500 6800 5600 6800 +Wire Wire Line + 5500 7150 5600 7150 +Connection ~ 5500 6800 +Wire Wire Line + 5600 7250 5500 7250 +Wire Wire Line + 5500 7250 5500 7550 +Wire Wire Line + 3850 7550 5600 7550 +Connection ~ 5500 7550 +Wire Wire Line + 4800 7450 5600 7450 +Connection ~ 4800 6900 +Wire Wire Line + 4800 8100 4950 8100 +Connection ~ 4800 7450 +Wire Wire Line + 5550 8100 5650 8100 +Wire Wire Line + 7650 8050 7650 8100 +Wire Wire Line + 6550 8050 7650 8050 +Wire Wire Line + 6550 8400 6650 8400 +Wire Wire Line + 6650 8400 6650 8500 +Wire Wire Line + 6550 8700 6650 8700 +Wire Wire Line + 6650 8700 6650 8600 +Wire Wire Line + 7550 8550 7650 8550 +Wire Wire Line + 7650 8550 7650 8200 +Wire Wire Line + 8550 8150 8700 8150 +Wire Wire Line + 9300 8150 9450 8150 +Wire Wire Line + 9300 7950 9450 7950 +Wire Wire Line + 9450 7950 9450 8050 +Wire Wire Line + 8500 7950 8700 7950 +Connection ~ 8500 6750 +Wire Wire Line + 10350 8100 11050 8100 +Wire Wire Line + 10450 8100 10450 7800 +Wire Wire Line + 10450 7800 5500 7800 +Wire Wire Line + 5500 7800 5500 8350 +Wire Wire Line + 5500 8000 5650 8000 +Wire Wire Line + 5500 8350 5650 8350 +Connection ~ 5500 8000 +Wire Wire Line + 5650 8450 5500 8450 +Wire Wire Line + 5500 8450 5500 8750 +Wire Wire Line + 3850 8750 5650 8750 +Wire Wire Line + 4800 8650 5650 8650 +Connection ~ 4800 8100 +Connection ~ 5500 8750 +Connection ~ 10450 4350 +Connection ~ 10450 5650 +Connection ~ 10450 6900 +Connection ~ 10450 8100 +Wire Wire Line + 2700 4400 3050 4400 +Wire Wire Line + 2700 4200 3050 4200 +Wire Wire Line + 3100 3850 3800 3850 +$Comp +L d_inverter U62 +U 1 1 686ABC95 +P 13450 3750 +F 0 "U62" H 13450 3650 60 0000 C CNN +F 1 "d_inverter" H 13450 3900 60 0000 C CNN +F 2 "" H 13500 3700 60 0000 C CNN +F 3 "" H 13500 3700 60 0000 C CNN + 1 13450 3750 + 1 0 0 -1 +$EndComp +$Comp +L d_and U63 +U 1 1 686ABC9B +P 13600 4300 +F 0 "U63" H 13600 4300 60 0000 C CNN +F 1 "d_and" H 13650 4400 60 0000 C CNN +F 2 "" H 13600 4300 60 0000 C CNN +F 3 "" H 13600 4300 60 0000 C CNN + 1 13600 4300 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U60 +U 1 1 686ABCA1 +P 12700 4100 +F 0 "U60" H 12700 4000 60 0000 C CNN +F 1 "d_inverter" H 12700 4250 60 0000 C CNN +F 2 "" H 12750 4050 60 0000 C CNN +F 3 "" H 12750 4050 60 0000 C CNN + 1 12700 4100 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U61 +U 1 1 686ABCA7 +P 12700 4300 +F 0 "U61" H 12700 4200 60 0000 C CNN +F 1 "d_inverter" H 12700 4450 60 0000 C CNN +F 2 "" H 12750 4250 60 0000 C CNN +F 3 "" H 12750 4250 60 0000 C CNN + 1 12700 4300 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U65 +U 1 1 686ABCAD +P 14550 4250 +F 0 "U65" H 14550 4150 60 0000 C CNN +F 1 "d_inverter" H 14550 4400 60 0000 C CNN +F 2 "" H 14600 4200 60 0000 C CNN +F 3 "" H 14600 4200 60 0000 C CNN + 1 14550 4250 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U73 +U 1 1 686ABCB3 +P 15400 4250 +F 0 "U73" H 15400 4250 60 0000 C CNN +F 1 "d_nand" H 15450 4350 60 0000 C CNN +F 2 "" H 15400 4250 60 0000 C CNN +F 3 "" H 15400 4250 60 0000 C CNN + 1 15400 4250 + 1 0 0 -1 +$EndComp +$Comp +L d_and U75 +U 1 1 686ABCB9 +P 15400 4900 +F 0 "U75" H 15400 4900 60 0000 C CNN +F 1 "d_and" H 15450 5000 60 0000 C CNN +F 2 "" H 15400 4900 60 0000 C CNN +F 3 "" H 15400 4900 60 0000 C CNN + 1 15400 4900 + 1 0 0 -1 +$EndComp +$Comp +L d_and U74 +U 1 1 686ABCBF +P 15400 4600 +F 0 "U74" H 15400 4600 60 0000 C CNN +F 1 "d_and" H 15450 4700 60 0000 C CNN +F 2 "" H 15400 4600 60 0000 C CNN +F 3 "" H 15400 4600 60 0000 C CNN + 1 15400 4600 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U89 +U 1 1 686ABCC5 +P 16400 4750 +F 0 "U89" H 16400 4750 60 0000 C CNN +F 1 "d_nor" H 16450 4850 60 0000 C CNN +F 2 "" H 16400 4750 60 0000 C CNN +F 3 "" H 16400 4750 60 0000 C CNN + 1 16400 4750 + 1 0 0 -1 +$EndComp +$Comp +L d_and U95 +U 1 1 686ABCCB +P 17400 4350 +F 0 "U95" H 17400 4350 60 0000 C CNN +F 1 "d_and" H 17450 4450 60 0000 C CNN +F 2 "" H 17400 4350 60 0000 C CNN +F 3 "" H 17400 4350 60 0000 C CNN + 1 17400 4350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U113 +U 1 1 686ABCD1 +P 19200 4300 +F 0 "U113" H 19200 4300 60 0000 C CNN +F 1 "d_and" H 19250 4400 60 0000 C CNN +F 2 "" H 19200 4300 60 0000 C CNN +F 3 "" H 19200 4300 60 0000 C CNN + 1 19200 4300 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U103 +U 1 1 686ABCD7 +P 18300 4300 +F 0 "U103" H 18300 4200 60 0000 C CNN +F 1 "d_inverter" H 18300 4450 60 0000 C CNN +F 2 "" H 18350 4250 60 0000 C CNN +F 3 "" H 18350 4250 60 0000 C CNN + 1 18300 4300 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U64 +U 1 1 686ABCDD +P 14500 5550 +F 0 "U64" H 14500 5450 60 0000 C CNN +F 1 "d_inverter" H 14500 5700 60 0000 C CNN +F 2 "" H 14550 5500 60 0000 C CNN +F 3 "" H 14550 5500 60 0000 C CNN + 1 14500 5550 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U70 +U 1 1 686ABCE3 +P 15350 5550 +F 0 "U70" H 15350 5550 60 0000 C CNN +F 1 "d_nand" H 15400 5650 60 0000 C CNN +F 2 "" H 15350 5550 60 0000 C CNN +F 3 "" H 15350 5550 60 0000 C CNN + 1 15350 5550 + 1 0 0 -1 +$EndComp +$Comp +L d_and U72 +U 1 1 686ABCE9 +P 15350 6200 +F 0 "U72" H 15350 6200 60 0000 C CNN +F 1 "d_and" H 15400 6300 60 0000 C CNN +F 2 "" H 15350 6200 60 0000 C CNN +F 3 "" H 15350 6200 60 0000 C CNN + 1 15350 6200 + 1 0 0 -1 +$EndComp +$Comp +L d_and U71 +U 1 1 686ABCEF +P 15350 5900 +F 0 "U71" H 15350 5900 60 0000 C CNN +F 1 "d_and" H 15400 6000 60 0000 C CNN +F 2 "" H 15350 5900 60 0000 C CNN +F 3 "" H 15350 5900 60 0000 C CNN + 1 15350 5900 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U88 +U 1 1 686ABCF5 +P 16350 6050 +F 0 "U88" H 16350 6050 60 0000 C CNN +F 1 "d_nor" H 16400 6150 60 0000 C CNN +F 2 "" H 16350 6050 60 0000 C CNN +F 3 "" H 16350 6050 60 0000 C CNN + 1 16350 6050 + 1 0 0 -1 +$EndComp +$Comp +L d_and U94 +U 1 1 686ABCFB +P 17350 5650 +F 0 "U94" H 17350 5650 60 0000 C CNN +F 1 "d_and" H 17400 5750 60 0000 C CNN +F 2 "" H 17350 5650 60 0000 C CNN +F 3 "" H 17350 5650 60 0000 C CNN + 1 17350 5650 + 1 0 0 -1 +$EndComp +$Comp +L d_and U112 +U 1 1 686ABD01 +P 19150 5600 +F 0 "U112" H 19150 5600 60 0000 C CNN +F 1 "d_and" H 19200 5700 60 0000 C CNN +F 2 "" H 19150 5600 60 0000 C CNN +F 3 "" H 19150 5600 60 0000 C CNN + 1 19150 5600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U100 +U 1 1 686ABD07 +P 18250 5400 +F 0 "U100" H 18250 5300 60 0000 C CNN +F 1 "d_inverter" H 18250 5550 60 0000 C CNN +F 2 "" H 18300 5350 60 0000 C CNN +F 3 "" H 18300 5350 60 0000 C CNN + 1 18250 5400 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U101 +U 1 1 686ABD0D +P 18250 5600 +F 0 "U101" H 18250 5500 60 0000 C CNN +F 1 "d_inverter" H 18250 5750 60 0000 C CNN +F 2 "" H 18300 5550 60 0000 C CNN +F 3 "" H 18300 5550 60 0000 C CNN + 1 18250 5600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U68 +U 1 1 686ABD13 +P 14600 8000 +F 0 "U68" H 14600 7900 60 0000 C CNN +F 1 "d_inverter" H 14600 8150 60 0000 C CNN +F 2 "" H 14650 7950 60 0000 C CNN +F 3 "" H 14650 7950 60 0000 C CNN + 1 14600 8000 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U82 +U 1 1 686ABD19 +P 15450 8000 +F 0 "U82" H 15450 8000 60 0000 C CNN +F 1 "d_nand" H 15500 8100 60 0000 C CNN +F 2 "" H 15450 8000 60 0000 C CNN +F 3 "" H 15450 8000 60 0000 C CNN + 1 15450 8000 + 1 0 0 -1 +$EndComp +$Comp +L d_and U86 +U 1 1 686ABD1F +P 15450 8650 +F 0 "U86" H 15450 8650 60 0000 C CNN +F 1 "d_and" H 15500 8750 60 0000 C CNN +F 2 "" H 15450 8650 60 0000 C CNN +F 3 "" H 15450 8650 60 0000 C CNN + 1 15450 8650 + 1 0 0 -1 +$EndComp +$Comp +L d_and U84 +U 1 1 686ABD25 +P 15450 8350 +F 0 "U84" H 15450 8350 60 0000 C CNN +F 1 "d_and" H 15500 8450 60 0000 C CNN +F 2 "" H 15450 8350 60 0000 C CNN +F 3 "" H 15450 8350 60 0000 C CNN + 1 15450 8350 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U92 +U 1 1 686ABD2B +P 16450 8500 +F 0 "U92" H 16450 8500 60 0000 C CNN +F 1 "d_nor" H 16500 8600 60 0000 C CNN +F 2 "" H 16450 8500 60 0000 C CNN +F 3 "" H 16450 8500 60 0000 C CNN + 1 16450 8500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U98 +U 1 1 686ABD31 +P 17450 8100 +F 0 "U98" H 17450 8100 60 0000 C CNN +F 1 "d_and" H 17500 8200 60 0000 C CNN +F 2 "" H 17450 8100 60 0000 C CNN +F 3 "" H 17450 8100 60 0000 C CNN + 1 17450 8100 + 1 0 0 -1 +$EndComp +$Comp +L d_and U116 +U 1 1 686ABD37 +P 19250 8050 +F 0 "U116" H 19250 8050 60 0000 C CNN +F 1 "d_and" H 19300 8150 60 0000 C CNN +F 2 "" H 19250 8050 60 0000 C CNN +F 3 "" H 19250 8050 60 0000 C CNN + 1 19250 8050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U108 +U 1 1 686ABD3D +P 18350 7850 +F 0 "U108" H 18350 7750 60 0000 C CNN +F 1 "d_inverter" H 18350 8000 60 0000 C CNN +F 2 "" H 18400 7800 60 0000 C CNN +F 3 "" H 18400 7800 60 0000 C CNN + 1 18350 7850 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U110 +U 1 1 686ABD43 +P 18350 8050 +F 0 "U110" H 18350 7950 60 0000 C CNN +F 1 "d_inverter" H 18350 8200 60 0000 C CNN +F 2 "" H 18400 8000 60 0000 C CNN +F 3 "" H 18400 8000 60 0000 C CNN + 1 18350 8050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U69 +U 1 1 686ABD49 +P 14600 8000 +F 0 "U69" H 14600 7900 60 0000 C CNN +F 1 "d_inverter" H 14600 8150 60 0000 C CNN +F 2 "" H 14650 7950 60 0000 C CNN +F 3 "" H 14650 7950 60 0000 C CNN + 1 14600 8000 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U83 +U 1 1 686ABD4F +P 15450 8000 +F 0 "U83" H 15450 8000 60 0000 C CNN +F 1 "d_nand" H 15500 8100 60 0000 C CNN +F 2 "" H 15450 8000 60 0000 C CNN +F 3 "" H 15450 8000 60 0000 C CNN + 1 15450 8000 + 1 0 0 -1 +$EndComp +$Comp +L d_and U87 +U 1 1 686ABD55 +P 15450 8650 +F 0 "U87" H 15450 8650 60 0000 C CNN +F 1 "d_and" H 15500 8750 60 0000 C CNN +F 2 "" H 15450 8650 60 0000 C CNN +F 3 "" H 15450 8650 60 0000 C CNN + 1 15450 8650 + 1 0 0 -1 +$EndComp +$Comp +L d_and U85 +U 1 1 686ABD5B +P 15450 8350 +F 0 "U85" H 15450 8350 60 0000 C CNN +F 1 "d_and" H 15500 8450 60 0000 C CNN +F 2 "" H 15450 8350 60 0000 C CNN +F 3 "" H 15450 8350 60 0000 C CNN + 1 15450 8350 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U93 +U 1 1 686ABD61 +P 16450 8500 +F 0 "U93" H 16450 8500 60 0000 C CNN +F 1 "d_nor" H 16500 8600 60 0000 C CNN +F 2 "" H 16450 8500 60 0000 C CNN +F 3 "" H 16450 8500 60 0000 C CNN + 1 16450 8500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U99 +U 1 1 686ABD67 +P 17450 8100 +F 0 "U99" H 17450 8100 60 0000 C CNN +F 1 "d_and" H 17500 8200 60 0000 C CNN +F 2 "" H 17450 8100 60 0000 C CNN +F 3 "" H 17450 8100 60 0000 C CNN + 1 17450 8100 + 1 0 0 -1 +$EndComp +$Comp +L d_and U117 +U 1 1 686ABD6D +P 19250 8050 +F 0 "U117" H 19250 8050 60 0000 C CNN +F 1 "d_and" H 19300 8150 60 0000 C CNN +F 2 "" H 19250 8050 60 0000 C CNN +F 3 "" H 19250 8050 60 0000 C CNN + 1 19250 8050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U109 +U 1 1 686ABD73 +P 18350 7850 +F 0 "U109" H 18350 7750 60 0000 C CNN +F 1 "d_inverter" H 18350 8000 60 0000 C CNN +F 2 "" H 18400 7800 60 0000 C CNN +F 3 "" H 18400 7800 60 0000 C CNN + 1 18350 7850 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U111 +U 1 1 686ABD79 +P 18350 8050 +F 0 "U111" H 18350 7950 60 0000 C CNN +F 1 "d_inverter" H 18350 8200 60 0000 C CNN +F 2 "" H 18400 8000 60 0000 C CNN +F 3 "" H 18400 8000 60 0000 C CNN + 1 18350 8050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U66 +U 1 1 686ABD7F +P 14550 6800 +F 0 "U66" H 14550 6700 60 0000 C CNN +F 1 "d_inverter" H 14550 6950 60 0000 C CNN +F 2 "" H 14600 6750 60 0000 C CNN +F 3 "" H 14600 6750 60 0000 C CNN + 1 14550 6800 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U76 +U 1 1 686ABD85 +P 15400 6800 +F 0 "U76" H 15400 6800 60 0000 C CNN +F 1 "d_nand" H 15450 6900 60 0000 C CNN +F 2 "" H 15400 6800 60 0000 C CNN +F 3 "" H 15400 6800 60 0000 C CNN + 1 15400 6800 + 1 0 0 -1 +$EndComp +$Comp +L d_and U80 +U 1 1 686ABD8B +P 15400 7450 +F 0 "U80" H 15400 7450 60 0000 C CNN +F 1 "d_and" H 15450 7550 60 0000 C CNN +F 2 "" H 15400 7450 60 0000 C CNN +F 3 "" H 15400 7450 60 0000 C CNN + 1 15400 7450 + 1 0 0 -1 +$EndComp +$Comp +L d_and U78 +U 1 1 686ABD91 +P 15400 7150 +F 0 "U78" H 15400 7150 60 0000 C CNN +F 1 "d_and" H 15450 7250 60 0000 C CNN +F 2 "" H 15400 7150 60 0000 C CNN +F 3 "" H 15400 7150 60 0000 C CNN + 1 15400 7150 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U90 +U 1 1 686ABD97 +P 16400 7300 +F 0 "U90" H 16400 7300 60 0000 C CNN +F 1 "d_nor" H 16450 7400 60 0000 C CNN +F 2 "" H 16400 7300 60 0000 C CNN +F 3 "" H 16400 7300 60 0000 C CNN + 1 16400 7300 + 1 0 0 -1 +$EndComp +$Comp +L d_and U96 +U 1 1 686ABD9D +P 17400 6900 +F 0 "U96" H 17400 6900 60 0000 C CNN +F 1 "d_and" H 17450 7000 60 0000 C CNN +F 2 "" H 17400 6900 60 0000 C CNN +F 3 "" H 17400 6900 60 0000 C CNN + 1 17400 6900 + 1 0 0 -1 +$EndComp +$Comp +L d_and U114 +U 1 1 686ABDA3 +P 19200 6850 +F 0 "U114" H 19200 6850 60 0000 C CNN +F 1 "d_and" H 19250 6950 60 0000 C CNN +F 2 "" H 19200 6850 60 0000 C CNN +F 3 "" H 19200 6850 60 0000 C CNN + 1 19200 6850 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U104 +U 1 1 686ABDA9 +P 18300 6650 +F 0 "U104" H 18300 6550 60 0000 C CNN +F 1 "d_inverter" H 18300 6800 60 0000 C CNN +F 2 "" H 18350 6600 60 0000 C CNN +F 3 "" H 18350 6600 60 0000 C CNN + 1 18300 6650 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U106 +U 1 1 686ABDAF +P 18300 6850 +F 0 "U106" H 18300 6750 60 0000 C CNN +F 1 "d_inverter" H 18300 7000 60 0000 C CNN +F 2 "" H 18350 6800 60 0000 C CNN +F 3 "" H 18350 6800 60 0000 C CNN + 1 18300 6850 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U67 +U 1 1 686ABDB5 +P 14550 6800 +F 0 "U67" H 14550 6700 60 0000 C CNN +F 1 "d_inverter" H 14550 6950 60 0000 C CNN +F 2 "" H 14600 6750 60 0000 C CNN +F 3 "" H 14600 6750 60 0000 C CNN + 1 14550 6800 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U77 +U 1 1 686ABDBB +P 15400 6800 +F 0 "U77" H 15400 6800 60 0000 C CNN +F 1 "d_nand" H 15450 6900 60 0000 C CNN +F 2 "" H 15400 6800 60 0000 C CNN +F 3 "" H 15400 6800 60 0000 C CNN + 1 15400 6800 + 1 0 0 -1 +$EndComp +$Comp +L d_and U81 +U 1 1 686ABDC1 +P 15400 7450 +F 0 "U81" H 15400 7450 60 0000 C CNN +F 1 "d_and" H 15450 7550 60 0000 C CNN +F 2 "" H 15400 7450 60 0000 C CNN +F 3 "" H 15400 7450 60 0000 C CNN + 1 15400 7450 + 1 0 0 -1 +$EndComp +$Comp +L d_and U79 +U 1 1 686ABDC7 +P 15400 7150 +F 0 "U79" H 15400 7150 60 0000 C CNN +F 1 "d_and" H 15450 7250 60 0000 C CNN +F 2 "" H 15400 7150 60 0000 C CNN +F 3 "" H 15400 7150 60 0000 C CNN + 1 15400 7150 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U91 +U 1 1 686ABDCD +P 16400 7300 +F 0 "U91" H 16400 7300 60 0000 C CNN +F 1 "d_nor" H 16450 7400 60 0000 C CNN +F 2 "" H 16400 7300 60 0000 C CNN +F 3 "" H 16400 7300 60 0000 C CNN + 1 16400 7300 + 1 0 0 -1 +$EndComp +$Comp +L d_and U97 +U 1 1 686ABDD3 +P 17400 6900 +F 0 "U97" H 17400 6900 60 0000 C CNN +F 1 "d_and" H 17450 7000 60 0000 C CNN +F 2 "" H 17400 6900 60 0000 C CNN +F 3 "" H 17400 6900 60 0000 C CNN + 1 17400 6900 + 1 0 0 -1 +$EndComp +$Comp +L d_and U115 +U 1 1 686ABDD9 +P 19200 6850 +F 0 "U115" H 19200 6850 60 0000 C CNN +F 1 "d_and" H 19250 6950 60 0000 C CNN +F 2 "" H 19200 6850 60 0000 C CNN +F 3 "" H 19200 6850 60 0000 C CNN + 1 19200 6850 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U105 +U 1 1 686ABDDF +P 18300 6650 +F 0 "U105" H 18300 6550 60 0000 C CNN +F 1 "d_inverter" H 18300 6800 60 0000 C CNN +F 2 "" H 18350 6600 60 0000 C CNN +F 3 "" H 18350 6600 60 0000 C CNN + 1 18300 6650 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U107 +U 1 1 686ABDE5 +P 18300 6850 +F 0 "U107" H 18300 6750 60 0000 C CNN +F 1 "d_inverter" H 18300 7000 60 0000 C CNN +F 2 "" H 18350 6800 60 0000 C CNN +F 3 "" H 18350 6800 60 0000 C CNN + 1 18300 6850 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U102 +U 1 1 686ABDEB +P 18300 4100 +F 0 "U102" H 18300 4000 60 0000 C CNN +F 1 "d_inverter" H 18300 4250 60 0000 C CNN +F 2 "" H 18350 4050 60 0000 C CNN +F 3 "" H 18350 4050 60 0000 C CNN + 1 18300 4100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 13000 4100 13150 4100 +Wire Wire Line + 13150 4100 13150 4200 +Wire Wire Line + 13000 4300 13150 4300 +Wire Wire Line + 14050 4250 14250 4250 +Wire Wire Line + 14850 4250 14950 4250 +Wire Wire Line + 14950 4150 14850 4150 +Wire Wire Line + 14850 3650 14850 4500 +Wire Wire Line + 14850 4500 14950 4500 +Wire Wire Line + 14950 4600 14850 4600 +Wire Wire Line + 14850 4600 14850 4900 +Wire Wire Line + 12900 4900 14950 4900 +Wire Wire Line + 14150 4250 14150 8550 +Wire Wire Line + 14150 4800 14950 4800 +Connection ~ 14150 4250 +Wire Wire Line + 15850 4550 15950 4550 +Wire Wire Line + 15950 4550 15950 4650 +Wire Wire Line + 15850 4850 15950 4850 +Wire Wire Line + 15950 4850 15950 4750 +Wire Wire Line + 16850 4700 16950 4700 +Wire Wire Line + 16950 4700 16950 4350 +Wire Wire Line + 15850 4200 16950 4200 +Wire Wire Line + 16950 4200 16950 4250 +Wire Wire Line + 17850 4300 18000 4300 +Wire Wire Line + 18600 4300 18750 4300 +Wire Wire Line + 18600 4100 18750 4100 +Wire Wire Line + 18750 4100 18750 4200 +Wire Wire Line + 13750 3750 18000 3750 +Wire Wire Line + 19650 4250 20400 4250 +Wire Wire Line + 19800 4250 19800 3650 +Wire Wire Line + 19800 3650 14850 3650 +Connection ~ 14850 4150 +Connection ~ 14850 4900 +Wire Wire Line + 14150 5550 14200 5550 +Connection ~ 14150 4800 +Wire Wire Line + 14800 5550 14900 5550 +Wire Wire Line + 15800 5500 16900 5500 +Wire Wire Line + 16900 5500 16900 5550 +Wire Wire Line + 14900 5450 14800 5450 +Wire Wire Line + 14800 5150 14800 5800 +Wire Wire Line + 14800 5800 14900 5800 +Wire Wire Line + 14900 5900 14800 5900 +Wire Wire Line + 14800 5900 14800 6200 +Wire Wire Line + 12850 6200 14900 6200 +Wire Wire Line + 15800 5850 15900 5850 +Wire Wire Line + 15900 5850 15900 5950 +Wire Wire Line + 15800 6150 15900 6150 +Wire Wire Line + 15900 6150 15900 6050 +Wire Wire Line + 16800 6000 16900 6000 +Wire Wire Line + 16900 6000 16900 5650 +Wire Wire Line + 17800 5600 17950 5600 +Wire Wire Line + 18000 3750 18000 3900 +Wire Wire Line + 18000 3900 17850 3900 +Wire Wire Line + 17850 3900 17850 7850 +Wire Wire Line + 17850 4100 18000 4100 +Wire Wire Line + 17850 5400 17950 5400 +Connection ~ 17850 4100 +Wire Wire Line + 18550 5400 18700 5400 +Wire Wire Line + 18700 5400 18700 5500 +Wire Wire Line + 18550 5600 18700 5600 +Wire Wire Line + 19600 5550 20450 5550 +Wire Wire Line + 19800 5550 19800 5150 +Wire Wire Line + 19800 5150 14800 5150 +Connection ~ 14800 5450 +Connection ~ 14800 6200 +Wire Wire Line + 14150 6100 14900 6100 +Connection ~ 14150 5550 +Wire Wire Line + 14150 6800 14250 6800 +Connection ~ 14150 6100 +Wire Wire Line + 14850 6800 14950 6800 +Wire Wire Line + 15850 6750 16950 6750 +Wire Wire Line + 16950 6750 16950 6800 +Wire Wire Line + 15850 7100 15950 7100 +Wire Wire Line + 15950 7100 15950 7200 +Wire Wire Line + 15850 7400 15950 7400 +Wire Wire Line + 15950 7400 15950 7300 +Wire Wire Line + 16850 7250 16950 7250 +Wire Wire Line + 16950 7250 16950 6900 +Wire Wire Line + 17850 6850 18000 6850 +Wire Wire Line + 17850 6650 18000 6650 +Connection ~ 17850 5400 +Wire Wire Line + 18750 6650 18750 6750 +Wire Wire Line + 18600 6850 18750 6850 +Wire Wire Line + 18600 6650 18750 6650 +Wire Wire Line + 19650 6800 20450 6800 +Wire Wire Line + 19800 6800 19800 6400 +Wire Wire Line + 19800 6400 14850 6400 +Wire Wire Line + 14850 6400 14850 7050 +Wire Wire Line + 14850 6700 14950 6700 +Wire Wire Line + 14850 7050 14950 7050 +Connection ~ 14850 6700 +Wire Wire Line + 14950 7150 14850 7150 +Wire Wire Line + 14850 7150 14850 7450 +Wire Wire Line + 12850 7450 14950 7450 +Connection ~ 14850 7450 +Wire Wire Line + 14150 7350 14950 7350 +Connection ~ 14150 6800 +Wire Wire Line + 14150 8000 14300 8000 +Connection ~ 14150 7350 +Wire Wire Line + 14900 8000 15000 8000 +Wire Wire Line + 17000 7950 17000 8000 +Wire Wire Line + 15900 7950 17000 7950 +Wire Wire Line + 15900 8300 16000 8300 +Wire Wire Line + 16000 8300 16000 8400 +Wire Wire Line + 15900 8600 16000 8600 +Wire Wire Line + 16000 8600 16000 8500 +Wire Wire Line + 16900 8450 17000 8450 +Wire Wire Line + 17000 8450 17000 8100 +Wire Wire Line + 17900 8050 18050 8050 +Wire Wire Line + 18650 8050 18800 8050 +Wire Wire Line + 18650 7850 18800 7850 +Wire Wire Line + 18800 7850 18800 7950 +Wire Wire Line + 17850 7850 18050 7850 +Connection ~ 17850 6650 +Wire Wire Line + 19700 8000 20450 8000 +Wire Wire Line + 19800 8000 19800 7700 +Wire Wire Line + 19800 7700 14850 7700 +Wire Wire Line + 14850 7700 14850 8250 +Wire Wire Line + 14850 7900 15000 7900 +Wire Wire Line + 14850 8250 15000 8250 +Connection ~ 14850 7900 +Wire Wire Line + 15000 8350 14850 8350 +Wire Wire Line + 14850 8350 14850 8650 +Wire Wire Line + 12800 8650 15000 8650 +Wire Wire Line + 14150 8550 15000 8550 +Connection ~ 14150 8000 +Connection ~ 14850 8650 +Connection ~ 19800 4250 +Connection ~ 19800 5550 +Connection ~ 19800 6800 +Connection ~ 19800 8000 +Wire Wire Line + 12000 4300 12400 4300 +Wire Wire Line + 12000 4100 12400 4100 +Wire Wire Line + 12400 3750 13150 3750 +$Comp +L PORT U59 +U 1 1 686ABEEC +P 2850 3850 +F 0 "U59" H 2900 3950 30 0000 C CNN +F 1 "PORT" H 2850 3850 30 0000 C CNN +F 2 "" H 2850 3850 60 0000 C CNN +F 3 "" H 2850 3850 60 0000 C CNN + 1 2850 3850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U59 +U 2 1 686AC02D +P 2450 4200 +F 0 "U59" H 2500 4300 30 0000 C CNN +F 1 "PORT" H 2450 4200 30 0000 C CNN +F 2 "" H 2450 4200 60 0000 C CNN +F 3 "" H 2450 4200 60 0000 C CNN + 2 2450 4200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U59 +U 3 1 686AC12E +P 2450 4400 +F 0 "U59" H 2500 4500 30 0000 C CNN +F 1 "PORT" H 2450 4400 30 0000 C CNN +F 2 "" H 2450 4400 60 0000 C CNN +F 3 "" H 2450 4400 60 0000 C CNN + 3 2450 4400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U59 +U 14 1 686AC241 +P 11750 4100 +F 0 "U59" H 11800 4200 30 0000 C CNN +F 1 "PORT" H 11750 4100 30 0000 C CNN +F 2 "" H 11750 4100 60 0000 C CNN +F 3 "" H 11750 4100 60 0000 C CNN + 14 11750 4100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U59 +U 4 1 686AC346 +P 3650 5000 +F 0 "U59" H 3700 5100 30 0000 C CNN +F 1 "PORT" H 3650 5000 30 0000 C CNN +F 2 "" H 3650 5000 60 0000 C CNN +F 3 "" H 3650 5000 60 0000 C CNN + 4 3650 5000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U59 +U 5 1 686AC44D +P 11150 4350 +F 0 "U59" H 11200 4450 30 0000 C CNN +F 1 "PORT" H 11150 4350 30 0000 C CNN +F 2 "" H 11150 4350 60 0000 C CNN +F 3 "" H 11150 4350 60 0000 C CNN + 5 11150 4350 + -1 0 0 1 +$EndComp +$Comp +L PORT U59 +U 6 1 686AC556 +P 3600 6300 +F 0 "U59" H 3650 6400 30 0000 C CNN +F 1 "PORT" H 3600 6300 30 0000 C CNN +F 2 "" H 3600 6300 60 0000 C CNN +F 3 "" H 3600 6300 60 0000 C CNN + 6 3600 6300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U59 +U 7 1 686AC661 +P 11150 5650 +F 0 "U59" H 11200 5750 30 0000 C CNN +F 1 "PORT" H 11150 5650 30 0000 C CNN +F 2 "" H 11150 5650 60 0000 C CNN +F 3 "" H 11150 5650 60 0000 C CNN + 7 11150 5650 + -1 0 0 1 +$EndComp +$Comp +L PORT U59 +U 8 1 686AC76E +P 3600 7550 +F 0 "U59" H 3650 7650 30 0000 C CNN +F 1 "PORT" H 3600 7550 30 0000 C CNN +F 2 "" H 3600 7550 60 0000 C CNN +F 3 "" H 3600 7550 60 0000 C CNN + 8 3600 7550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U59 +U 9 1 686AC87D +P 11250 6900 +F 0 "U59" H 11300 7000 30 0000 C CNN +F 1 "PORT" H 11250 6900 30 0000 C CNN +F 2 "" H 11250 6900 60 0000 C CNN +F 3 "" H 11250 6900 60 0000 C CNN + 9 11250 6900 + -1 0 0 1 +$EndComp +$Comp +L PORT U59 +U 15 1 686AC98E +P 11750 4300 +F 0 "U59" H 11800 4400 30 0000 C CNN +F 1 "PORT" H 11750 4300 30 0000 C CNN +F 2 "" H 11750 4300 60 0000 C CNN +F 3 "" H 11750 4300 60 0000 C CNN + 15 11750 4300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U59 +U 10 1 686ACAA3 +P 3600 8750 +F 0 "U59" H 3650 8850 30 0000 C CNN +F 1 "PORT" H 3600 8750 30 0000 C CNN +F 2 "" H 3600 8750 60 0000 C CNN +F 3 "" H 3600 8750 60 0000 C CNN + 10 3600 8750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U59 +U 16 1 686ACBBE +P 12650 4900 +F 0 "U59" H 12700 5000 30 0000 C CNN +F 1 "PORT" H 12650 4900 30 0000 C CNN +F 2 "" H 12650 4900 60 0000 C CNN +F 3 "" H 12650 4900 60 0000 C CNN + 16 12650 4900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U59 +U 17 1 686ACCD5 +P 20650 4250 +F 0 "U59" H 20700 4350 30 0000 C CNN +F 1 "PORT" H 20650 4250 30 0000 C CNN +F 2 "" H 20650 4250 60 0000 C CNN +F 3 "" H 20650 4250 60 0000 C CNN + 17 20650 4250 + -1 0 0 1 +$EndComp +$Comp +L PORT U59 +U 18 1 686ACDF0 +P 12600 6200 +F 0 "U59" H 12650 6300 30 0000 C CNN +F 1 "PORT" H 12600 6200 30 0000 C CNN +F 2 "" H 12600 6200 60 0000 C CNN +F 3 "" H 12600 6200 60 0000 C CNN + 18 12600 6200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U59 +U 19 1 686ACF0B +P 20700 5550 +F 0 "U59" H 20750 5650 30 0000 C CNN +F 1 "PORT" H 20700 5550 30 0000 C CNN +F 2 "" H 20700 5550 60 0000 C CNN +F 3 "" H 20700 5550 60 0000 C CNN + 19 20700 5550 + -1 0 0 1 +$EndComp +$Comp +L PORT U59 +U 20 1 686AD028 +P 12600 7450 +F 0 "U59" H 12650 7550 30 0000 C CNN +F 1 "PORT" H 12600 7450 30 0000 C CNN +F 2 "" H 12600 7450 60 0000 C CNN +F 3 "" H 12600 7450 60 0000 C CNN + 20 12600 7450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U59 +U 23 1 686AD149 +P 20700 8000 +F 0 "U59" H 20750 8100 30 0000 C CNN +F 1 "PORT" H 20700 8000 30 0000 C CNN +F 2 "" H 20700 8000 60 0000 C CNN +F 3 "" H 20700 8000 60 0000 C CNN + 23 20700 8000 + -1 0 0 1 +$EndComp +$Comp +L PORT U59 +U 11 1 686AD26A +P 11300 8100 +F 0 "U59" H 11350 8200 30 0000 C CNN +F 1 "PORT" H 11300 8100 30 0000 C CNN +F 2 "" H 11300 8100 60 0000 C CNN +F 3 "" H 11300 8100 60 0000 C CNN + 11 11300 8100 + -1 0 0 1 +$EndComp +$Comp +L PORT U59 +U 24 1 686AD38D +P 11800 3450 +F 0 "U59" H 11850 3550 30 0000 C CNN +F 1 "PORT" H 11800 3450 30 0000 C CNN +F 2 "" H 11800 3450 60 0000 C CNN +F 3 "" H 11800 3450 60 0000 C CNN + 24 11800 3450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U59 +U 21 1 686AD4B4 +P 20700 6800 +F 0 "U59" H 20750 6900 30 0000 C CNN +F 1 "PORT" H 20700 6800 30 0000 C CNN +F 2 "" H 20700 6800 60 0000 C CNN +F 3 "" H 20700 6800 60 0000 C CNN + 21 20700 6800 + -1 0 0 1 +$EndComp +$Comp +L PORT U59 +U 12 1 686AD5DB +P 11800 3250 +F 0 "U59" H 11850 3350 30 0000 C CNN +F 1 "PORT" H 11800 3250 30 0000 C CNN +F 2 "" H 11800 3250 60 0000 C CNN +F 3 "" H 11800 3250 60 0000 C CNN + 12 11800 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U59 +U 22 1 686AD704 +P 12550 8650 +F 0 "U59" H 12600 8750 30 0000 C CNN +F 1 "PORT" H 12550 8650 30 0000 C CNN +F 2 "" H 12550 8650 60 0000 C CNN +F 3 "" H 12550 8650 60 0000 C CNN + 22 12550 8650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U59 +U 13 1 686AD82F +P 12150 3750 +F 0 "U59" H 12200 3850 30 0000 C CNN +F 1 "PORT" H 12150 3750 30 0000 C CNN +F 2 "" H 12150 3750 60 0000 C CNN +F 3 "" H 12150 3750 60 0000 C CNN + 13 12150 3750 + 1 0 0 -1 +$EndComp +NoConn ~ 12050 3450 +NoConn ~ 12050 3250 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74116/SN74116.sub b/library/SubcircuitLibrary/SN74116/SN74116.sub new file mode 100644 index 000000000..6580feed4 --- /dev/null +++ b/library/SubcircuitLibrary/SN74116/SN74116.sub @@ -0,0 +1,470 @@ +* Subcircuit SN74116 +.subckt SN74116 net-_u3-pad1_ net-_u1-pad1_ net-_u2-pad1_ net-_u15-pad2_ net-_u14-pad1_ net-_u12-pad2_ net-_u11-pad1_ net-_u19-pad2_ net-_u17-pad1_ net-_u25-pad2_ net-_u23-pad1_ ? net-_u59-pad13_ net-_u59-pad14_ net-_u59-pad15_ net-_u59-pad16_ net-_u113-pad3_ net-_u59-pad18_ net-_u112-pad3_ net-_u59-pad20_ net-_u114-pad3_ net-_u59-pad22_ net-_u116-pad3_ ? +* c:\fossee\esim\library\subcircuitlibrary\sn74116\sn74116.cir +* u3 net-_u3-pad1_ net-_u3-pad2_ d_inverter +* u4 net-_u1-pad2_ net-_u2-pad2_ net-_u10-pad1_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter +* u2 net-_u2-pad1_ net-_u2-pad2_ d_inverter +* u6 net-_u10-pad1_ net-_u14-pad2_ d_inverter +* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_nand +* u16 net-_u10-pad1_ net-_u15-pad2_ net-_u16-pad3_ d_and +* u15 net-_u14-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_and +* u30 net-_u15-pad3_ net-_u16-pad3_ net-_u30-pad3_ d_nor +* u36 net-_u14-pad3_ net-_u30-pad3_ net-_u36-pad3_ d_and +* u54 net-_u43-pad2_ net-_u44-pad2_ net-_u14-pad1_ d_and +* u44 net-_u36-pad3_ net-_u44-pad2_ d_inverter +* u5 net-_u10-pad1_ net-_u11-pad2_ d_inverter +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_nand +* u13 net-_u10-pad1_ net-_u12-pad2_ net-_u13-pad3_ d_and +* u12 net-_u11-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_and +* u29 net-_u12-pad3_ net-_u13-pad3_ net-_u29-pad3_ d_nor +* u35 net-_u11-pad3_ net-_u29-pad3_ net-_u35-pad3_ d_and +* u53 net-_u41-pad2_ net-_u42-pad2_ net-_u11-pad1_ d_and +* u41 net-_u3-pad2_ net-_u41-pad2_ d_inverter +* u42 net-_u35-pad3_ net-_u42-pad2_ d_inverter +* u9 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u23 net-_u23-pad1_ net-_u10-pad2_ net-_u23-pad3_ d_nand +* u27 net-_u10-pad1_ net-_u25-pad2_ net-_u27-pad3_ d_and +* u25 net-_u23-pad1_ net-_u25-pad2_ net-_u25-pad3_ d_and +* u33 net-_u25-pad3_ net-_u27-pad3_ net-_u33-pad3_ d_nor +* u39 net-_u23-pad3_ net-_u33-pad3_ net-_u39-pad3_ d_and +* u57 net-_u49-pad2_ net-_u51-pad2_ net-_u23-pad1_ d_and +* u49 net-_u3-pad2_ net-_u49-pad2_ d_inverter +* u51 net-_u39-pad3_ net-_u51-pad2_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u24 net-_u23-pad1_ net-_u10-pad2_ net-_u23-pad3_ d_nand +* u28 net-_u10-pad1_ net-_u25-pad2_ net-_u27-pad3_ d_and +* u26 net-_u23-pad1_ net-_u25-pad2_ net-_u25-pad3_ d_and +* u34 net-_u25-pad3_ net-_u27-pad3_ net-_u33-pad3_ d_nor +* u40 net-_u23-pad3_ net-_u33-pad3_ net-_u39-pad3_ d_and +* u58 net-_u49-pad2_ net-_u51-pad2_ net-_u23-pad1_ d_and +* u50 net-_u3-pad2_ net-_u49-pad2_ d_inverter +* u52 net-_u39-pad3_ net-_u51-pad2_ d_inverter +* u7 net-_u10-pad1_ net-_u17-pad2_ d_inverter +* u17 net-_u17-pad1_ net-_u17-pad2_ net-_u17-pad3_ d_nand +* u21 net-_u10-pad1_ net-_u19-pad2_ net-_u21-pad3_ d_and +* u19 net-_u17-pad1_ net-_u19-pad2_ net-_u19-pad3_ d_and +* u31 net-_u19-pad3_ net-_u21-pad3_ net-_u31-pad3_ d_nor +* u37 net-_u17-pad3_ net-_u31-pad3_ net-_u37-pad3_ d_and +* u55 net-_u45-pad2_ net-_u47-pad2_ net-_u17-pad1_ d_and +* u45 net-_u3-pad2_ net-_u45-pad2_ d_inverter +* u47 net-_u37-pad3_ net-_u47-pad2_ d_inverter +* u8 net-_u10-pad1_ net-_u17-pad2_ d_inverter +* u18 net-_u17-pad1_ net-_u17-pad2_ net-_u17-pad3_ d_nand +* u22 net-_u10-pad1_ net-_u19-pad2_ net-_u21-pad3_ d_and +* u20 net-_u17-pad1_ net-_u19-pad2_ net-_u19-pad3_ d_and +* u32 net-_u19-pad3_ net-_u21-pad3_ net-_u31-pad3_ d_nor +* u38 net-_u17-pad3_ net-_u31-pad3_ net-_u37-pad3_ d_and +* u56 net-_u45-pad2_ net-_u47-pad2_ net-_u17-pad1_ d_and +* u46 net-_u3-pad2_ net-_u45-pad2_ d_inverter +* u48 net-_u37-pad3_ net-_u47-pad2_ d_inverter +* u43 net-_u3-pad2_ net-_u43-pad2_ d_inverter +* u62 net-_u59-pad13_ net-_u100-pad1_ d_inverter +* u63 net-_u60-pad2_ net-_u61-pad2_ net-_u63-pad3_ d_and +* u60 net-_u59-pad14_ net-_u60-pad2_ d_inverter +* u61 net-_u59-pad15_ net-_u61-pad2_ d_inverter +* u65 net-_u63-pad3_ net-_u65-pad2_ d_inverter +* u73 net-_u113-pad3_ net-_u65-pad2_ net-_u73-pad3_ d_nand +* u75 net-_u63-pad3_ net-_u59-pad16_ net-_u75-pad3_ d_and +* u74 net-_u113-pad3_ net-_u59-pad16_ net-_u74-pad3_ d_and +* u89 net-_u74-pad3_ net-_u75-pad3_ net-_u89-pad3_ d_nor +* u95 net-_u73-pad3_ net-_u89-pad3_ net-_u103-pad1_ d_and +* u113 net-_u102-pad2_ net-_u103-pad2_ net-_u113-pad3_ d_and +* u103 net-_u103-pad1_ net-_u103-pad2_ d_inverter +* u64 net-_u63-pad3_ net-_u64-pad2_ d_inverter +* u70 net-_u112-pad3_ net-_u64-pad2_ net-_u70-pad3_ d_nand +* u72 net-_u63-pad3_ net-_u59-pad18_ net-_u72-pad3_ d_and +* u71 net-_u112-pad3_ net-_u59-pad18_ net-_u71-pad3_ d_and +* u88 net-_u71-pad3_ net-_u72-pad3_ net-_u88-pad3_ d_nor +* u94 net-_u70-pad3_ net-_u88-pad3_ net-_u101-pad1_ d_and +* u112 net-_u100-pad2_ net-_u101-pad2_ net-_u112-pad3_ d_and +* u100 net-_u100-pad1_ net-_u100-pad2_ d_inverter +* u101 net-_u101-pad1_ net-_u101-pad2_ d_inverter +* u68 net-_u63-pad3_ net-_u68-pad2_ d_inverter +* u82 net-_u116-pad3_ net-_u68-pad2_ net-_u82-pad3_ d_nand +* u86 net-_u63-pad3_ net-_u59-pad22_ net-_u86-pad3_ d_and +* u84 net-_u116-pad3_ net-_u59-pad22_ net-_u84-pad3_ d_and +* u92 net-_u84-pad3_ net-_u86-pad3_ net-_u92-pad3_ d_nor +* u98 net-_u82-pad3_ net-_u92-pad3_ net-_u110-pad1_ d_and +* u116 net-_u108-pad2_ net-_u110-pad2_ net-_u116-pad3_ d_and +* u108 net-_u100-pad1_ net-_u108-pad2_ d_inverter +* u110 net-_u110-pad1_ net-_u110-pad2_ d_inverter +* u69 net-_u63-pad3_ net-_u68-pad2_ d_inverter +* u83 net-_u116-pad3_ net-_u68-pad2_ net-_u82-pad3_ d_nand +* u87 net-_u63-pad3_ net-_u59-pad22_ net-_u86-pad3_ d_and +* u85 net-_u116-pad3_ net-_u59-pad22_ net-_u84-pad3_ d_and +* u93 net-_u84-pad3_ net-_u86-pad3_ net-_u92-pad3_ d_nor +* u99 net-_u82-pad3_ net-_u92-pad3_ net-_u110-pad1_ d_and +* u117 net-_u108-pad2_ net-_u110-pad2_ net-_u116-pad3_ d_and +* u109 net-_u100-pad1_ net-_u108-pad2_ d_inverter +* u111 net-_u110-pad1_ net-_u110-pad2_ d_inverter +* u66 net-_u63-pad3_ net-_u66-pad2_ d_inverter +* u76 net-_u114-pad3_ net-_u66-pad2_ net-_u76-pad3_ d_nand +* u80 net-_u63-pad3_ net-_u59-pad20_ net-_u80-pad3_ d_and +* u78 net-_u114-pad3_ net-_u59-pad20_ net-_u78-pad3_ d_and +* u90 net-_u78-pad3_ net-_u80-pad3_ net-_u90-pad3_ d_nor +* u96 net-_u76-pad3_ net-_u90-pad3_ net-_u106-pad1_ d_and +* u114 net-_u104-pad2_ net-_u106-pad2_ net-_u114-pad3_ d_and +* u104 net-_u100-pad1_ net-_u104-pad2_ d_inverter +* u106 net-_u106-pad1_ net-_u106-pad2_ d_inverter +* u67 net-_u63-pad3_ net-_u66-pad2_ d_inverter +* u77 net-_u114-pad3_ net-_u66-pad2_ net-_u76-pad3_ d_nand +* u81 net-_u63-pad3_ net-_u59-pad20_ net-_u80-pad3_ d_and +* u79 net-_u114-pad3_ net-_u59-pad20_ net-_u78-pad3_ d_and +* u91 net-_u78-pad3_ net-_u80-pad3_ net-_u90-pad3_ d_nor +* u97 net-_u76-pad3_ net-_u90-pad3_ net-_u106-pad1_ d_and +* u115 net-_u104-pad2_ net-_u106-pad2_ net-_u114-pad3_ d_and +* u105 net-_u100-pad1_ net-_u104-pad2_ d_inverter +* u107 net-_u106-pad1_ net-_u106-pad2_ d_inverter +* u102 net-_u100-pad1_ net-_u102-pad2_ d_inverter +a1 net-_u3-pad1_ net-_u3-pad2_ u3 +a2 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u10-pad1_ u4 +a3 net-_u1-pad1_ net-_u1-pad2_ u1 +a4 net-_u2-pad1_ net-_u2-pad2_ u2 +a5 net-_u10-pad1_ net-_u14-pad2_ u6 +a6 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14 +a7 [net-_u10-pad1_ net-_u15-pad2_ ] net-_u16-pad3_ u16 +a8 [net-_u14-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15 +a9 [net-_u15-pad3_ net-_u16-pad3_ ] net-_u30-pad3_ u30 +a10 [net-_u14-pad3_ net-_u30-pad3_ ] net-_u36-pad3_ u36 +a11 [net-_u43-pad2_ net-_u44-pad2_ ] net-_u14-pad1_ u54 +a12 net-_u36-pad3_ net-_u44-pad2_ u44 +a13 net-_u10-pad1_ net-_u11-pad2_ u5 +a14 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a15 [net-_u10-pad1_ net-_u12-pad2_ ] net-_u13-pad3_ u13 +a16 [net-_u11-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +a17 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u29-pad3_ u29 +a18 [net-_u11-pad3_ net-_u29-pad3_ ] net-_u35-pad3_ u35 +a19 [net-_u41-pad2_ net-_u42-pad2_ ] net-_u11-pad1_ u53 +a20 net-_u3-pad2_ net-_u41-pad2_ u41 +a21 net-_u35-pad3_ net-_u42-pad2_ u42 +a22 net-_u10-pad1_ net-_u10-pad2_ u9 +a23 [net-_u23-pad1_ net-_u10-pad2_ ] net-_u23-pad3_ u23 +a24 [net-_u10-pad1_ net-_u25-pad2_ ] net-_u27-pad3_ u27 +a25 [net-_u23-pad1_ net-_u25-pad2_ ] net-_u25-pad3_ u25 +a26 [net-_u25-pad3_ net-_u27-pad3_ ] net-_u33-pad3_ u33 +a27 [net-_u23-pad3_ net-_u33-pad3_ ] net-_u39-pad3_ u39 +a28 [net-_u49-pad2_ net-_u51-pad2_ ] net-_u23-pad1_ u57 +a29 net-_u3-pad2_ net-_u49-pad2_ u49 +a30 net-_u39-pad3_ net-_u51-pad2_ u51 +a31 net-_u10-pad1_ net-_u10-pad2_ u10 +a32 [net-_u23-pad1_ net-_u10-pad2_ ] net-_u23-pad3_ u24 +a33 [net-_u10-pad1_ net-_u25-pad2_ ] net-_u27-pad3_ u28 +a34 [net-_u23-pad1_ net-_u25-pad2_ ] net-_u25-pad3_ u26 +a35 [net-_u25-pad3_ net-_u27-pad3_ ] net-_u33-pad3_ u34 +a36 [net-_u23-pad3_ net-_u33-pad3_ ] net-_u39-pad3_ u40 +a37 [net-_u49-pad2_ net-_u51-pad2_ ] net-_u23-pad1_ u58 +a38 net-_u3-pad2_ net-_u49-pad2_ u50 +a39 net-_u39-pad3_ net-_u51-pad2_ u52 +a40 net-_u10-pad1_ net-_u17-pad2_ u7 +a41 [net-_u17-pad1_ net-_u17-pad2_ ] net-_u17-pad3_ u17 +a42 [net-_u10-pad1_ net-_u19-pad2_ ] net-_u21-pad3_ u21 +a43 [net-_u17-pad1_ net-_u19-pad2_ ] net-_u19-pad3_ u19 +a44 [net-_u19-pad3_ net-_u21-pad3_ ] net-_u31-pad3_ u31 +a45 [net-_u17-pad3_ net-_u31-pad3_ ] net-_u37-pad3_ u37 +a46 [net-_u45-pad2_ net-_u47-pad2_ ] net-_u17-pad1_ u55 +a47 net-_u3-pad2_ net-_u45-pad2_ u45 +a48 net-_u37-pad3_ net-_u47-pad2_ u47 +a49 net-_u10-pad1_ net-_u17-pad2_ u8 +a50 [net-_u17-pad1_ net-_u17-pad2_ ] net-_u17-pad3_ u18 +a51 [net-_u10-pad1_ net-_u19-pad2_ ] net-_u21-pad3_ u22 +a52 [net-_u17-pad1_ net-_u19-pad2_ ] net-_u19-pad3_ u20 +a53 [net-_u19-pad3_ net-_u21-pad3_ ] net-_u31-pad3_ u32 +a54 [net-_u17-pad3_ net-_u31-pad3_ ] net-_u37-pad3_ u38 +a55 [net-_u45-pad2_ net-_u47-pad2_ ] net-_u17-pad1_ u56 +a56 net-_u3-pad2_ net-_u45-pad2_ u46 +a57 net-_u37-pad3_ net-_u47-pad2_ u48 +a58 net-_u3-pad2_ net-_u43-pad2_ u43 +a59 net-_u59-pad13_ net-_u100-pad1_ u62 +a60 [net-_u60-pad2_ net-_u61-pad2_ ] net-_u63-pad3_ u63 +a61 net-_u59-pad14_ net-_u60-pad2_ u60 +a62 net-_u59-pad15_ net-_u61-pad2_ u61 +a63 net-_u63-pad3_ net-_u65-pad2_ u65 +a64 [net-_u113-pad3_ net-_u65-pad2_ ] net-_u73-pad3_ u73 +a65 [net-_u63-pad3_ net-_u59-pad16_ ] net-_u75-pad3_ u75 +a66 [net-_u113-pad3_ net-_u59-pad16_ ] net-_u74-pad3_ u74 +a67 [net-_u74-pad3_ net-_u75-pad3_ ] net-_u89-pad3_ u89 +a68 [net-_u73-pad3_ net-_u89-pad3_ ] net-_u103-pad1_ u95 +a69 [net-_u102-pad2_ net-_u103-pad2_ ] net-_u113-pad3_ u113 +a70 net-_u103-pad1_ net-_u103-pad2_ u103 +a71 net-_u63-pad3_ net-_u64-pad2_ u64 +a72 [net-_u112-pad3_ net-_u64-pad2_ ] net-_u70-pad3_ u70 +a73 [net-_u63-pad3_ net-_u59-pad18_ ] net-_u72-pad3_ u72 +a74 [net-_u112-pad3_ net-_u59-pad18_ ] net-_u71-pad3_ u71 +a75 [net-_u71-pad3_ net-_u72-pad3_ ] net-_u88-pad3_ u88 +a76 [net-_u70-pad3_ net-_u88-pad3_ ] net-_u101-pad1_ u94 +a77 [net-_u100-pad2_ net-_u101-pad2_ ] net-_u112-pad3_ u112 +a78 net-_u100-pad1_ net-_u100-pad2_ u100 +a79 net-_u101-pad1_ net-_u101-pad2_ u101 +a80 net-_u63-pad3_ net-_u68-pad2_ u68 +a81 [net-_u116-pad3_ net-_u68-pad2_ ] net-_u82-pad3_ u82 +a82 [net-_u63-pad3_ net-_u59-pad22_ ] net-_u86-pad3_ u86 +a83 [net-_u116-pad3_ net-_u59-pad22_ ] net-_u84-pad3_ u84 +a84 [net-_u84-pad3_ net-_u86-pad3_ ] net-_u92-pad3_ u92 +a85 [net-_u82-pad3_ net-_u92-pad3_ ] net-_u110-pad1_ u98 +a86 [net-_u108-pad2_ net-_u110-pad2_ ] net-_u116-pad3_ u116 +a87 net-_u100-pad1_ net-_u108-pad2_ u108 +a88 net-_u110-pad1_ net-_u110-pad2_ u110 +a89 net-_u63-pad3_ net-_u68-pad2_ u69 +a90 [net-_u116-pad3_ net-_u68-pad2_ ] net-_u82-pad3_ u83 +a91 [net-_u63-pad3_ net-_u59-pad22_ ] net-_u86-pad3_ u87 +a92 [net-_u116-pad3_ net-_u59-pad22_ ] net-_u84-pad3_ u85 +a93 [net-_u84-pad3_ net-_u86-pad3_ ] net-_u92-pad3_ u93 +a94 [net-_u82-pad3_ net-_u92-pad3_ ] net-_u110-pad1_ u99 +a95 [net-_u108-pad2_ net-_u110-pad2_ ] net-_u116-pad3_ u117 +a96 net-_u100-pad1_ net-_u108-pad2_ u109 +a97 net-_u110-pad1_ net-_u110-pad2_ u111 +a98 net-_u63-pad3_ net-_u66-pad2_ u66 +a99 [net-_u114-pad3_ net-_u66-pad2_ ] net-_u76-pad3_ u76 +a100 [net-_u63-pad3_ net-_u59-pad20_ ] net-_u80-pad3_ u80 +a101 [net-_u114-pad3_ net-_u59-pad20_ ] net-_u78-pad3_ u78 +a102 [net-_u78-pad3_ net-_u80-pad3_ ] net-_u90-pad3_ u90 +a103 [net-_u76-pad3_ net-_u90-pad3_ ] net-_u106-pad1_ u96 +a104 [net-_u104-pad2_ net-_u106-pad2_ ] net-_u114-pad3_ u114 +a105 net-_u100-pad1_ net-_u104-pad2_ u104 +a106 net-_u106-pad1_ net-_u106-pad2_ u106 +a107 net-_u63-pad3_ net-_u66-pad2_ u67 +a108 [net-_u114-pad3_ net-_u66-pad2_ ] net-_u76-pad3_ u77 +a109 [net-_u63-pad3_ net-_u59-pad20_ ] net-_u80-pad3_ u81 +a110 [net-_u114-pad3_ net-_u59-pad20_ ] net-_u78-pad3_ u79 +a111 [net-_u78-pad3_ net-_u80-pad3_ ] net-_u90-pad3_ u91 +a112 [net-_u76-pad3_ net-_u90-pad3_ ] net-_u106-pad1_ u97 +a113 [net-_u104-pad2_ net-_u106-pad2_ ] net-_u114-pad3_ u115 +a114 net-_u100-pad1_ net-_u104-pad2_ u105 +a115 net-_u106-pad1_ net-_u106-pad2_ u107 +a116 net-_u100-pad1_ net-_u102-pad2_ u102 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u14 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u30 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u36 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u54 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u44 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u11 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u29 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u35 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u53 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u41 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u42 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u23 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u27 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u33 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u39 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u57 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u49 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u51 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u24 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u34 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u40 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u58 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u50 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u52 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u17 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u31 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u37 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u55 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u45 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u47 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u18 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u32 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u38 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u56 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u46 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u48 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u43 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u62 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u63 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u60 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u61 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u65 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u73 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u75 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u74 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u89 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u95 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u113 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u103 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u64 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u70 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u72 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u71 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u88 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u94 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u112 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u100 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u101 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u68 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u82 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u86 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u84 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u92 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u98 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u116 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u108 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u110 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u69 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u83 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u87 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u85 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u93 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u99 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u117 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u109 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u111 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u66 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u76 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u80 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u78 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u90 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u96 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u114 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u104 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u106 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u67 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u77 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u81 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u79 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u91 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u97 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u115 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u105 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u107 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u102 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SN74116 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74116/SN74116_Previous_Values.xml b/library/SubcircuitLibrary/SN74116/SN74116_Previous_Values.xml new file mode 100644 index 000000000..6f6d32daf --- /dev/null +++ b/library/SubcircuitLibrary/SN74116/SN74116_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_inverterd_andd_inverterd_inverterd_inverterd_nandd_andd_andd_nord_andd_andd_inverterd_inverterd_nandd_andd_andd_nord_andd_andd_inverterd_inverterd_inverterd_nandd_andd_andd_nord_andd_andd_inverterd_inverterd_inverterd_nandd_andd_andd_nord_andd_andd_inverterd_inverterd_inverterd_nandd_andd_andd_nord_andd_andd_inverterd_inverterd_inverterd_nandd_andd_andd_nord_andd_andd_inverterd_inverterd_inverterd_inverterd_andd_inverterd_inverterd_inverterd_nandd_andd_andd_nord_andd_andd_inverterd_inverterd_nandd_andd_andd_nord_andd_andd_inverterd_inverterd_inverterd_nandd_andd_andd_nord_andd_andd_inverterd_inverterd_inverterd_nandd_andd_andd_nord_andd_andd_inverterd_inverterd_inverterd_nandd_andd_andd_nord_andd_andd_inverterd_inverterd_inverterd_nandd_andd_andd_nord_andd_andd_inverterd_inverterd_inverter \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74116/analysis b/library/SubcircuitLibrary/SN74116/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/SN74116/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74182/3_and-cache.lib b/library/SubcircuitLibrary/SN74182/3_and-cache.lib new file mode 100644 index 000000000..af0586415 --- /dev/null +++ b/library/SubcircuitLibrary/SN74182/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74182/3_and.cir b/library/SubcircuitLibrary/SN74182/3_and.cir new file mode 100644 index 000000000..ba296cf01 --- /dev/null +++ b/library/SubcircuitLibrary/SN74182/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74182/3_and.cir.out b/library/SubcircuitLibrary/SN74182/3_and.cir.out new file mode 100644 index 000000000..d7cf79a07 --- /dev/null +++ b/library/SubcircuitLibrary/SN74182/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74182/3_and.pro b/library/SubcircuitLibrary/SN74182/3_and.pro new file mode 100644 index 000000000..00597a5ad --- /dev/null +++ b/library/SubcircuitLibrary/SN74182/3_and.pro @@ -0,0 +1,43 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_User +LibName9=eSim_Sources +LibName10=eSim_Subckt diff --git a/library/SubcircuitLibrary/SN74182/3_and.sch b/library/SubcircuitLibrary/SN74182/3_and.sch new file mode 100644 index 000000000..d6ac89f95 --- /dev/null +++ b/library/SubcircuitLibrary/SN74182/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74182/3_and.sub b/library/SubcircuitLibrary/SN74182/3_and.sub new file mode 100644 index 000000000..3d9120bb6 --- /dev/null +++ b/library/SubcircuitLibrary/SN74182/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74182/3_and_Previous_Values.xml b/library/SubcircuitLibrary/SN74182/3_and_Previous_Values.xml new file mode 100644 index 000000000..abc5faaae --- /dev/null +++ b/library/SubcircuitLibrary/SN74182/3_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74182/4_OR-cache.lib b/library/SubcircuitLibrary/SN74182/4_OR-cache.lib new file mode 100644 index 000000000..155f5e601 --- /dev/null +++ b/library/SubcircuitLibrary/SN74182/4_OR-cache.lib @@ -0,0 +1,63 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74182/4_OR.cir b/library/SubcircuitLibrary/SN74182/4_OR.cir new file mode 100644 index 000000000..b338b7b5f --- /dev/null +++ b/library/SubcircuitLibrary/SN74182/4_OR.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or +U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or +U4 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74182/4_OR.cir.out b/library/SubcircuitLibrary/SN74182/4_OR.cir.out new file mode 100644 index 000000000..adb6b01be --- /dev/null +++ b/library/SubcircuitLibrary/SN74182/4_OR.cir.out @@ -0,0 +1,24 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74182/4_OR.pro b/library/SubcircuitLibrary/SN74182/4_OR.pro new file mode 100644 index 000000000..881563ebd --- /dev/null +++ b/library/SubcircuitLibrary/SN74182/4_OR.pro @@ -0,0 +1,44 @@ +update=06/01/19 12:36:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_User +LibName10=eSim_Sources +LibName11=eSim_Subckt diff --git a/library/SubcircuitLibrary/SN74182/4_OR.sch b/library/SubcircuitLibrary/SN74182/4_OR.sch new file mode 100644 index 000000000..118968656 --- /dev/null +++ b/library/SubcircuitLibrary/SN74182/4_OR.sch @@ -0,0 +1,150 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_or U2 +U 1 1 5C9D00E1 +P 4300 2950 +F 0 "U2" H 4300 2950 60 0000 C CNN +F 1 "d_or" H 4300 3050 60 0000 C CNN +F 2 "" H 4300 2950 60 0000 C CNN +F 3 "" H 4300 2950 60 0000 C CNN + 1 4300 2950 + 1 0 0 -1 +$EndComp +$Comp +L d_or U3 +U 1 1 5C9D011F +P 4300 3350 +F 0 "U3" H 4300 3350 60 0000 C CNN +F 1 "d_or" H 4300 3450 60 0000 C CNN +F 2 "" H 4300 3350 60 0000 C CNN +F 3 "" H 4300 3350 60 0000 C CNN + 1 4300 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_or U4 +U 1 1 5C9D0141 +P 5250 3150 +F 0 "U4" H 5250 3150 60 0000 C CNN +F 1 "d_or" H 5250 3250 60 0000 C CNN +F 2 "" H 5250 3150 60 0000 C CNN +F 3 "" H 5250 3150 60 0000 C CNN + 1 5250 3150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4800 3050 4800 2900 +Wire Wire Line + 4800 2900 4750 2900 +Wire Wire Line + 4800 3150 4800 3300 +Wire Wire Line + 4800 3300 4750 3300 +Wire Wire Line + 3350 2850 3850 2850 +Wire Wire Line + 3850 2950 3600 2950 +Wire Wire Line + 3850 3250 3350 3250 +Wire Wire Line + 3600 2950 3600 3000 +Wire Wire Line + 3600 3000 3350 3000 +Wire Wire Line + 3850 3350 3850 3400 +Wire Wire Line + 3850 3400 3350 3400 +Wire Wire Line + 5700 3100 6200 3100 +$Comp +L PORT U1 +U 1 1 5C9D01F4 +P 3100 2850 +F 0 "U1" H 3150 2950 30 0000 C CNN +F 1 "PORT" H 3100 2850 30 0000 C CNN +F 2 "" H 3100 2850 60 0000 C CNN +F 3 "" H 3100 2850 60 0000 C CNN + 1 3100 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9D022F +P 3100 3000 +F 0 "U1" H 3150 3100 30 0000 C CNN +F 1 "PORT" H 3100 3000 30 0000 C CNN +F 2 "" H 3100 3000 60 0000 C CNN +F 3 "" H 3100 3000 60 0000 C CNN + 2 3100 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9D0271 +P 3100 3250 +F 0 "U1" H 3150 3350 30 0000 C CNN +F 1 "PORT" H 3100 3250 30 0000 C CNN +F 2 "" H 3100 3250 60 0000 C CNN +F 3 "" H 3100 3250 60 0000 C CNN + 3 3100 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9D0299 +P 3100 3400 +F 0 "U1" H 3150 3500 30 0000 C CNN +F 1 "PORT" H 3100 3400 30 0000 C CNN +F 2 "" H 3100 3400 60 0000 C CNN +F 3 "" H 3100 3400 60 0000 C CNN + 4 3100 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9D02C2 +P 6450 3100 +F 0 "U1" H 6500 3200 30 0000 C CNN +F 1 "PORT" H 6450 3100 30 0000 C CNN +F 2 "" H 6450 3100 60 0000 C CNN +F 3 "" H 6450 3100 60 0000 C CNN + 5 6450 3100 + -1 0 0 1 +$EndComp +Text Notes 3450 2850 0 60 ~ 12 +in1 +Text Notes 3450 3000 0 60 ~ 12 +in2 +Text Notes 3450 3250 0 60 ~ 12 +in3 +Text Notes 3450 3400 0 60 ~ 12 +in4 +Text Notes 5800 3100 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74182/4_OR.sub b/library/SubcircuitLibrary/SN74182/4_OR.sub new file mode 100644 index 000000000..d1fd3a241 --- /dev/null +++ b/library/SubcircuitLibrary/SN74182/4_OR.sub @@ -0,0 +1,18 @@ +* Subcircuit 4_OR +.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_OR \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74182/4_OR_Previous_Values.xml b/library/SubcircuitLibrary/SN74182/4_OR_Previous_Values.xml new file mode 100644 index 000000000..0683d9eb6 --- /dev/null +++ b/library/SubcircuitLibrary/SN74182/4_OR_Previous_Values.xml @@ -0,0 +1 @@ +d_ord_ord_ortruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74182/4_and-cache.lib b/library/SubcircuitLibrary/SN74182/4_and-cache.lib new file mode 100644 index 000000000..60f1a83d4 --- /dev/null +++ b/library/SubcircuitLibrary/SN74182/4_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74182/4_and-rescue.lib b/library/SubcircuitLibrary/SN74182/4_and-rescue.lib new file mode 100644 index 000000000..e38330518 --- /dev/null +++ b/library/SubcircuitLibrary/SN74182/4_and-rescue.lib @@ -0,0 +1,22 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74182/4_and.cir b/library/SubcircuitLibrary/SN74182/4_and.cir new file mode 100644 index 000000000..fdf2e1074 --- /dev/null +++ b/library/SubcircuitLibrary/SN74182/4_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and +U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74182/4_and.cir.out b/library/SubcircuitLibrary/SN74182/4_and.cir.out new file mode 100644 index 000000000..f40e5bc62 --- /dev/null +++ b/library/SubcircuitLibrary/SN74182/4_and.cir.out @@ -0,0 +1,18 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74182/4_and.pro b/library/SubcircuitLibrary/SN74182/4_and.pro new file mode 100644 index 000000000..b13a0a825 --- /dev/null +++ b/library/SubcircuitLibrary/SN74182/4_and.pro @@ -0,0 +1,57 @@ +update=Wed Mar 18 19:54:24 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=4_and-rescue +LibName2=texas +LibName3=intel +LibName4=audio +LibName5=interface +LibName6=digital-audio +LibName7=philips +LibName8=display +LibName9=cypress +LibName10=siliconi +LibName11=opto +LibName12=atmel +LibName13=contrib +LibName14=valves +LibName15=eSim_Analog +LibName16=eSim_Devices +LibName17=eSim_Digital +LibName18=eSim_Hybrid +LibName19=eSim_Miscellaneous +LibName20=eSim_Plot +LibName21=eSim_Power +LibName22=eSim_Sources +LibName23=eSim_Subckt +LibName24=eSim_User diff --git a/library/SubcircuitLibrary/SN74182/4_and.sch b/library/SubcircuitLibrary/SN74182/4_and.sch new file mode 100644 index 000000000..f5e8febdc --- /dev/null +++ b/library/SubcircuitLibrary/SN74182/4_and.sch @@ -0,0 +1,151 @@ +EESchema Schematic File Version 2 +LIBS:4_and-rescue +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:4_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and-RESCUE-4_and X1 +U 1 1 5C9A2915 +P 3700 3500 +F 0 "X1" H 4600 3800 60 0000 C CNN +F 1 "3_and" H 4650 4000 60 0000 C CNN +F 2 "" H 3700 3500 60 0000 C CNN +F 3 "" H 3700 3500 60 0000 C CNN + 1 3700 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2940 +P 5450 3400 +F 0 "U2" H 5450 3400 60 0000 C CNN +F 1 "d_and" H 5500 3500 60 0000 C CNN +F 2 "" H 5450 3400 60 0000 C CNN +F 3 "" H 5450 3400 60 0000 C CNN + 1 5450 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 3100 5000 3300 +Wire Wire Line + 4150 3000 4150 2700 +Wire Wire Line + 4150 2700 3200 2700 +Wire Wire Line + 4150 3100 4000 3100 +Wire Wire Line + 4000 3100 4000 3000 +Wire Wire Line + 4000 3000 3200 3000 +Wire Wire Line + 4150 3200 4150 3300 +Wire Wire Line + 4150 3300 3250 3300 +Wire Wire Line + 5000 3400 5000 3550 +Wire Wire Line + 5000 3550 3250 3550 +Wire Wire Line + 5900 3350 6500 3350 +$Comp +L PORT U1 +U 1 1 5C9A29B1 +P 2950 2700 +F 0 "U1" H 3000 2800 30 0000 C CNN +F 1 "PORT" H 2950 2700 30 0000 C CNN +F 2 "" H 2950 2700 60 0000 C CNN +F 3 "" H 2950 2700 60 0000 C CNN + 1 2950 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A29E9 +P 2950 3000 +F 0 "U1" H 3000 3100 30 0000 C CNN +F 1 "PORT" H 2950 3000 30 0000 C CNN +F 2 "" H 2950 3000 60 0000 C CNN +F 3 "" H 2950 3000 60 0000 C CNN + 2 2950 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A2A0D +P 3000 3300 +F 0 "U1" H 3050 3400 30 0000 C CNN +F 1 "PORT" H 3000 3300 30 0000 C CNN +F 2 "" H 3000 3300 60 0000 C CNN +F 3 "" H 3000 3300 60 0000 C CNN + 3 3000 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2A3C +P 3000 3550 +F 0 "U1" H 3050 3650 30 0000 C CNN +F 1 "PORT" H 3000 3550 30 0000 C CNN +F 2 "" H 3000 3550 60 0000 C CNN +F 3 "" H 3000 3550 60 0000 C CNN + 4 3000 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2A68 +P 6750 3350 +F 0 "U1" H 6800 3450 30 0000 C CNN +F 1 "PORT" H 6750 3350 30 0000 C CNN +F 2 "" H 6750 3350 60 0000 C CNN +F 3 "" H 6750 3350 60 0000 C CNN + 5 6750 3350 + -1 0 0 1 +$EndComp +Text Notes 3450 2650 0 60 ~ 12 +in1 +Text Notes 3450 2950 0 60 ~ 12 +in2 +Text Notes 3500 3300 0 60 ~ 12 +in3 +Text Notes 3500 3550 0 60 ~ 12 +in4 +Text Notes 6150 3350 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74182/4_and.sub b/library/SubcircuitLibrary/SN74182/4_and.sub new file mode 100644 index 000000000..8663f37e6 --- /dev/null +++ b/library/SubcircuitLibrary/SN74182/4_and.sub @@ -0,0 +1,12 @@ +* Subcircuit 4_and +.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74182/4_and_Previous_Values.xml b/library/SubcircuitLibrary/SN74182/4_and_Previous_Values.xml new file mode 100644 index 000000000..f2ba0130e --- /dev/null +++ b/library/SubcircuitLibrary/SN74182/4_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andC:\Users\malli\eSim\src\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74182/SN74182.cir b/library/SubcircuitLibrary/SN74182/SN74182.cir new file mode 100644 index 000000000..d02a06377 --- /dev/null +++ b/library/SubcircuitLibrary/SN74182/SN74182.cir @@ -0,0 +1,33 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\SN74182\SN74182.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/07/25 14:25:56 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad6_ Net-_U1-Pad15_ Net-_U1-Pad2_ Net-_U1-Pad4_ Net-_U1-Pad7_ 4_OR +X6 Net-_U1-Pad5_ Net-_U1-Pad14_ Net-_U1-Pad1_ Net-_U1-Pad3_ Net-_X10-Pad1_ 4_and +X2 Net-_U1-Pad15_ Net-_U1-Pad5_ Net-_U1-Pad14_ Net-_X10-Pad3_ 3_and +X7 Net-_U1-Pad2_ Net-_U1-Pad5_ Net-_U1-Pad14_ Net-_U1-Pad1_ Net-_X10-Pad2_ 4_and +U3 Net-_U1-Pad6_ Net-_U1-Pad5_ Net-_U3-Pad3_ d_and +X10 Net-_X10-Pad1_ Net-_X10-Pad2_ Net-_X10-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad10_ 4_OR +X8 Net-_U1-Pad14_ Net-_U1-Pad1_ Net-_U1-Pad3_ Net-_U2-Pad2_ Net-_X11-Pad1_ 4_and +X3 Net-_U1-Pad2_ Net-_U1-Pad14_ Net-_U1-Pad1_ Net-_X11-Pad3_ 3_and +X9 Net-_U1-Pad4_ Net-_U1-Pad14_ Net-_U1-Pad1_ Net-_U1-Pad3_ Net-_X11-Pad2_ 4_and +U4 Net-_U1-Pad15_ Net-_U1-Pad14_ Net-_U4-Pad3_ d_and +X11 Net-_X11-Pad1_ Net-_X11-Pad2_ Net-_X11-Pad3_ Net-_U4-Pad3_ Net-_U11-Pad1_ 4_OR +U11 Net-_U11-Pad1_ Net-_U1-Pad9_ d_inverter +X4 Net-_U1-Pad1_ Net-_U1-Pad3_ Net-_U2-Pad2_ Net-_U8-Pad1_ 3_and +X5 Net-_U1-Pad4_ Net-_U1-Pad1_ Net-_U1-Pad3_ Net-_U8-Pad2_ 3_and +U5 Net-_U1-Pad2_ Net-_U1-Pad1_ Net-_U10-Pad2_ d_and +U8 Net-_U8-Pad1_ Net-_U8-Pad2_ Net-_U10-Pad1_ d_or +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_or +U12 Net-_U10-Pad3_ Net-_U1-Pad11_ d_inverter +U2 Net-_U1-Pad13_ Net-_U2-Pad2_ d_inverter +U6 Net-_U1-Pad3_ Net-_U2-Pad2_ Net-_U6-Pad3_ d_and +U7 Net-_U1-Pad4_ Net-_U1-Pad3_ Net-_U7-Pad3_ d_and +U9 Net-_U6-Pad3_ Net-_U7-Pad3_ Net-_U1-Pad12_ d_nor +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ ? PORT + +.end diff --git a/library/SubcircuitLibrary/SN74182/SN74182.cir.out b/library/SubcircuitLibrary/SN74182/SN74182.cir.out new file mode 100644 index 000000000..e9263b114 --- /dev/null +++ b/library/SubcircuitLibrary/SN74182/SN74182.cir.out @@ -0,0 +1,70 @@ +* c:\fossee\esim\library\subcircuitlibrary\sn74182\sn74182.cir + +.include 4_and.sub +.include 4_OR.sub +.include 3_and.sub +x1 net-_u1-pad6_ net-_u1-pad15_ net-_u1-pad2_ net-_u1-pad4_ net-_u1-pad7_ 4_OR +x6 net-_u1-pad5_ net-_u1-pad14_ net-_u1-pad1_ net-_u1-pad3_ net-_x10-pad1_ 4_and +x2 net-_u1-pad15_ net-_u1-pad5_ net-_u1-pad14_ net-_x10-pad3_ 3_and +x7 net-_u1-pad2_ net-_u1-pad5_ net-_u1-pad14_ net-_u1-pad1_ net-_x10-pad2_ 4_and +* u3 net-_u1-pad6_ net-_u1-pad5_ net-_u3-pad3_ d_and +x10 net-_x10-pad1_ net-_x10-pad2_ net-_x10-pad3_ net-_u3-pad3_ net-_u1-pad10_ 4_OR +x8 net-_u1-pad14_ net-_u1-pad1_ net-_u1-pad3_ net-_u2-pad2_ net-_x11-pad1_ 4_and +x3 net-_u1-pad2_ net-_u1-pad14_ net-_u1-pad1_ net-_x11-pad3_ 3_and +x9 net-_u1-pad4_ net-_u1-pad14_ net-_u1-pad1_ net-_u1-pad3_ net-_x11-pad2_ 4_and +* u4 net-_u1-pad15_ net-_u1-pad14_ net-_u4-pad3_ d_and +x11 net-_x11-pad1_ net-_x11-pad2_ net-_x11-pad3_ net-_u4-pad3_ net-_u11-pad1_ 4_OR +* u11 net-_u11-pad1_ net-_u1-pad9_ d_inverter +x4 net-_u1-pad1_ net-_u1-pad3_ net-_u2-pad2_ net-_u8-pad1_ 3_and +x5 net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad3_ net-_u8-pad2_ 3_and +* u5 net-_u1-pad2_ net-_u1-pad1_ net-_u10-pad2_ d_and +* u8 net-_u8-pad1_ net-_u8-pad2_ net-_u10-pad1_ d_or +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_or +* u12 net-_u10-pad3_ net-_u1-pad11_ d_inverter +* u2 net-_u1-pad13_ net-_u2-pad2_ d_inverter +* u6 net-_u1-pad3_ net-_u2-pad2_ net-_u6-pad3_ d_and +* u7 net-_u1-pad4_ net-_u1-pad3_ net-_u7-pad3_ d_and +* u9 net-_u6-pad3_ net-_u7-pad3_ net-_u1-pad12_ d_nor +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? port +a1 [net-_u1-pad6_ net-_u1-pad5_ ] net-_u3-pad3_ u3 +a2 [net-_u1-pad15_ net-_u1-pad14_ ] net-_u4-pad3_ u4 +a3 net-_u11-pad1_ net-_u1-pad9_ u11 +a4 [net-_u1-pad2_ net-_u1-pad1_ ] net-_u10-pad2_ u5 +a5 [net-_u8-pad1_ net-_u8-pad2_ ] net-_u10-pad1_ u8 +a6 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a7 net-_u10-pad3_ net-_u1-pad11_ u12 +a8 net-_u1-pad13_ net-_u2-pad2_ u2 +a9 [net-_u1-pad3_ net-_u2-pad2_ ] net-_u6-pad3_ u6 +a10 [net-_u1-pad4_ net-_u1-pad3_ ] net-_u7-pad3_ u7 +a11 [net-_u6-pad3_ net-_u7-pad3_ ] net-_u1-pad12_ u9 +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u8 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u10 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u9 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74182/SN74182.pro b/library/SubcircuitLibrary/SN74182/SN74182.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/SN74182/SN74182.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN74182/SN74182.sch b/library/SubcircuitLibrary/SN74182/SN74182.sch new file mode 100644 index 000000000..3fc2a37a9 --- /dev/null +++ b/library/SubcircuitLibrary/SN74182/SN74182.sch @@ -0,0 +1,706 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:Lookahead_carry-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 4_OR X1 +U 1 1 6836CAB2 +P 5100 850 +F 0 "X1" H 5250 750 60 0000 C CNN +F 1 "4_OR" H 5250 950 60 0000 C CNN +F 2 "" H 5100 850 60 0000 C CNN +F 3 "" H 5100 850 60 0000 C CNN + 1 5100 850 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X6 +U 1 1 6836CB1D +P 5950 1300 +F 0 "X6" H 6000 1250 60 0000 C CNN +F 1 "4_and" H 6050 1400 60 0000 C CNN +F 2 "" H 5950 1300 60 0000 C CNN +F 3 "" H 5950 1300 60 0000 C CNN + 1 5950 1300 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X2 +U 1 1 6836CBE8 +P 5900 2350 +F 0 "X2" H 6000 2300 60 0000 C CNN +F 1 "3_and" H 6050 2500 60 0000 C CNN +F 2 "" H 5900 2350 60 0000 C CNN +F 3 "" H 5900 2350 60 0000 C CNN + 1 5900 2350 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X7 +U 1 1 6836CC5D +P 5950 1800 +F 0 "X7" H 6000 1750 60 0000 C CNN +F 1 "4_and" H 6050 1900 60 0000 C CNN +F 2 "" H 5950 1800 60 0000 C CNN +F 3 "" H 5950 1800 60 0000 C CNN + 1 5950 1800 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 6836CC8F +P 6000 2700 +F 0 "U3" H 6000 2700 60 0000 C CNN +F 1 "d_and" H 6050 2800 60 0000 C CNN +F 2 "" H 6000 2700 60 0000 C CNN +F 3 "" H 6000 2700 60 0000 C CNN + 1 6000 2700 + 1 0 0 -1 +$EndComp +$Comp +L 4_OR X10 +U 1 1 6836CCE1 +P 7450 1800 +F 0 "X10" H 7600 1700 60 0000 C CNN +F 1 "4_OR" H 7600 1900 60 0000 C CNN +F 2 "" H 7450 1800 60 0000 C CNN +F 3 "" H 7450 1800 60 0000 C CNN + 1 7450 1800 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X8 +U 1 1 6836D08B +P 5950 3100 +F 0 "X8" H 6000 3050 60 0000 C CNN +F 1 "4_and" H 6050 3200 60 0000 C CNN +F 2 "" H 5950 3100 60 0000 C CNN +F 3 "" H 5950 3100 60 0000 C CNN + 1 5950 3100 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X3 +U 1 1 6836D091 +P 5900 4150 +F 0 "X3" H 6000 4100 60 0000 C CNN +F 1 "3_and" H 6050 4300 60 0000 C CNN +F 2 "" H 5900 4150 60 0000 C CNN +F 3 "" H 5900 4150 60 0000 C CNN + 1 5900 4150 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X9 +U 1 1 6836D097 +P 5950 3600 +F 0 "X9" H 6000 3550 60 0000 C CNN +F 1 "4_and" H 6050 3700 60 0000 C CNN +F 2 "" H 5950 3600 60 0000 C CNN +F 3 "" H 5950 3600 60 0000 C CNN + 1 5950 3600 + 1 0 0 -1 +$EndComp +$Comp +L d_and U4 +U 1 1 6836D09D +P 6000 4500 +F 0 "U4" H 6000 4500 60 0000 C CNN +F 1 "d_and" H 6050 4600 60 0000 C CNN +F 2 "" H 6000 4500 60 0000 C CNN +F 3 "" H 6000 4500 60 0000 C CNN + 1 6000 4500 + 1 0 0 -1 +$EndComp +$Comp +L 4_OR X11 +U 1 1 6836D0A3 +P 7450 3600 +F 0 "X11" H 7600 3500 60 0000 C CNN +F 1 "4_OR" H 7600 3700 60 0000 C CNN +F 2 "" H 7450 3600 60 0000 C CNN +F 3 "" H 7450 3600 60 0000 C CNN + 1 7450 3600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U11 +U 1 1 6836D362 +P 8500 3600 +F 0 "U11" H 8500 3500 60 0000 C CNN +F 1 "d_inverter" H 8500 3750 60 0000 C CNN +F 2 "" H 8550 3550 60 0000 C CNN +F 3 "" H 8550 3550 60 0000 C CNN + 1 8500 3600 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X4 +U 1 1 6836D3B1 +P 5900 4950 +F 0 "X4" H 6000 4900 60 0000 C CNN +F 1 "3_and" H 6050 5100 60 0000 C CNN +F 2 "" H 5900 4950 60 0000 C CNN +F 3 "" H 5900 4950 60 0000 C CNN + 1 5900 4950 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X5 +U 1 1 6836D42F +P 5900 5350 +F 0 "X5" H 6000 5300 60 0000 C CNN +F 1 "3_and" H 6050 5500 60 0000 C CNN +F 2 "" H 5900 5350 60 0000 C CNN +F 3 "" H 5900 5350 60 0000 C CNN + 1 5900 5350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U5 +U 1 1 6836D475 +P 6000 5700 +F 0 "U5" H 6000 5700 60 0000 C CNN +F 1 "d_and" H 6050 5800 60 0000 C CNN +F 2 "" H 6000 5700 60 0000 C CNN +F 3 "" H 6000 5700 60 0000 C CNN + 1 6000 5700 + 1 0 0 -1 +$EndComp +$Comp +L d_or U8 +U 1 1 6836D4DF +P 7150 5150 +F 0 "U8" H 7150 5150 60 0000 C CNN +F 1 "d_or" H 7150 5250 60 0000 C CNN +F 2 "" H 7150 5150 60 0000 C CNN +F 3 "" H 7150 5150 60 0000 C CNN + 1 7150 5150 + 1 0 0 -1 +$EndComp +$Comp +L d_or U10 +U 1 1 6836D53E +P 8050 5300 +F 0 "U10" H 8050 5300 60 0000 C CNN +F 1 "d_or" H 8050 5400 60 0000 C CNN +F 2 "" H 8050 5300 60 0000 C CNN +F 3 "" H 8050 5300 60 0000 C CNN + 1 8050 5300 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U12 +U 1 1 6836D5B9 +P 8950 5250 +F 0 "U12" H 8950 5150 60 0000 C CNN +F 1 "d_inverter" H 8950 5400 60 0000 C CNN +F 2 "" H 9000 5200 60 0000 C CNN +F 3 "" H 9000 5200 60 0000 C CNN + 1 8950 5250 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 6836D63B +P 4250 6950 +F 0 "U2" H 4250 6850 60 0000 C CNN +F 1 "d_inverter" H 4250 7100 60 0000 C CNN +F 2 "" H 4300 6900 60 0000 C CNN +F 3 "" H 4300 6900 60 0000 C CNN + 1 4250 6950 + 1 0 0 -1 +$EndComp +$Comp +L d_and U6 +U 1 1 6836D6CC +P 6000 6050 +F 0 "U6" H 6000 6050 60 0000 C CNN +F 1 "d_and" H 6050 6150 60 0000 C CNN +F 2 "" H 6000 6050 60 0000 C CNN +F 3 "" H 6000 6050 60 0000 C CNN + 1 6000 6050 + 1 0 0 -1 +$EndComp +$Comp +L d_and U7 +U 1 1 6836D726 +P 6000 6400 +F 0 "U7" H 6000 6400 60 0000 C CNN +F 1 "d_and" H 6050 6500 60 0000 C CNN +F 2 "" H 6000 6400 60 0000 C CNN +F 3 "" H 6000 6400 60 0000 C CNN + 1 6000 6400 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U9 +U 1 1 6836D796 +P 7250 6250 +F 0 "U9" H 7250 6250 60 0000 C CNN +F 1 "d_nor" H 7300 6350 60 0000 C CNN +F 2 "" H 7250 6250 60 0000 C CNN +F 3 "" H 7250 6250 60 0000 C CNN + 1 7250 6250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6450 1300 6450 1650 +Wire Wire Line + 6450 1650 7100 1650 +Wire Wire Line + 6500 1800 6500 1750 +Wire Wire Line + 6400 2300 6400 1850 +Wire Wire Line + 6400 1850 7100 1850 +Wire Wire Line + 6450 2650 6550 2650 +Wire Wire Line + 6550 2650 6550 1950 +Wire Wire Line + 6550 1950 7100 1950 +Wire Wire Line + 6450 3100 6450 3450 +Wire Wire Line + 6450 3450 7100 3450 +Wire Wire Line + 6450 3600 6450 3550 +Wire Wire Line + 6450 3550 7100 3550 +Wire Wire Line + 6400 4100 6400 3650 +Wire Wire Line + 6400 3650 7100 3650 +Wire Wire Line + 6450 4450 6450 3750 +Wire Wire Line + 6450 3750 7100 3750 +Wire Wire Line + 8000 3600 8200 3600 +Wire Wire Line + 6400 4900 6400 5050 +Wire Wire Line + 6400 5050 6700 5050 +Wire Wire Line + 6400 5300 6400 5150 +Wire Wire Line + 6400 5150 6700 5150 +Wire Wire Line + 6450 5650 6450 5300 +Wire Wire Line + 7600 5100 7600 5200 +Wire Wire Line + 8500 5250 8650 5250 +Wire Wire Line + 6450 6000 6450 6150 +Wire Wire Line + 6450 6150 6800 6150 +Wire Wire Line + 6450 6350 6450 6250 +Wire Wire Line + 6450 6250 6800 6250 +$Comp +L PORT U1 +U 1 1 6837324D +P 2550 5850 +F 0 "U1" H 2600 5950 30 0000 C CNN +F 1 "PORT" H 2550 5850 30 0000 C CNN +F 2 "" H 2550 5850 60 0000 C CNN +F 3 "" H 2550 5850 60 0000 C CNN + 1 2550 5850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 68373298 +P 2550 5700 +F 0 "U1" H 2600 5800 30 0000 C CNN +F 1 "PORT" H 2550 5700 30 0000 C CNN +F 2 "" H 2550 5700 60 0000 C CNN +F 3 "" H 2550 5700 60 0000 C CNN + 2 2550 5700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2800 2650 5550 2650 +Wire Wire Line + 5550 2650 5550 2700 +Wire Wire Line + 2800 2450 2800 2600 +Wire Wire Line + 2800 2600 5550 2600 +Wire Wire Line + 4000 2600 4000 700 +Wire Wire Line + 4000 700 4750 700 +Connection ~ 4000 2600 +$Comp +L PORT U1 +U 10 1 68375C57 +P 9500 1800 +F 0 "U1" H 9550 1900 30 0000 C CNN +F 1 "PORT" H 9500 1800 30 0000 C CNN +F 2 "" H 9500 1800 60 0000 C CNN +F 3 "" H 9500 1800 60 0000 C CNN + 10 9500 1800 + -1 0 0 1 +$EndComp +Wire Wire Line + 5650 850 9250 850 +Wire Wire Line + 5400 1150 5400 2650 +Wire Wire Line + 5400 1150 5550 1150 +Connection ~ 5400 2650 +Wire Wire Line + 5400 1750 5550 1750 +Connection ~ 5400 1750 +Wire Wire Line + 5400 2300 5550 2300 +Connection ~ 5400 2300 +$Comp +L PORT U1 +U 7 1 6837832B +P 9500 850 +F 0 "U1" H 9550 950 30 0000 C CNN +F 1 "PORT" H 9500 850 30 0000 C CNN +F 2 "" H 9500 850 60 0000 C CNN +F 3 "" H 9500 850 60 0000 C CNN + 7 9500 850 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 68378B12 +P 9500 5250 +F 0 "U1" H 9550 5350 30 0000 C CNN +F 1 "PORT" H 9500 5250 30 0000 C CNN +F 2 "" H 9500 5250 60 0000 C CNN +F 3 "" H 9500 5250 60 0000 C CNN + 11 9500 5250 + -1 0 0 1 +$EndComp +Wire Wire Line + 8000 1800 9250 1800 +$Comp +L PORT U1 +U 12 1 6837A4A8 +P 9500 6200 +F 0 "U1" H 9550 6300 30 0000 C CNN +F 1 "PORT" H 9500 6200 30 0000 C CNN +F 2 "" H 9500 6200 60 0000 C CNN +F 3 "" H 9500 6200 60 0000 C CNN + 12 9500 6200 + -1 0 0 1 +$EndComp +Wire Wire Line + 6450 5300 7600 5300 +$Comp +L PORT U1 +U 13 1 6837A6FA +P 2650 6950 +F 0 "U1" H 2700 7050 30 0000 C CNN +F 1 "PORT" H 2650 6950 30 0000 C CNN +F 2 "" H 2650 6950 60 0000 C CNN +F 3 "" H 2650 6950 60 0000 C CNN + 13 2650 6950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 6837D04B +P 2600 4500 +F 0 "U1" H 2650 4600 30 0000 C CNN +F 1 "PORT" H 2600 4500 30 0000 C CNN +F 2 "" H 2600 4500 60 0000 C CNN +F 3 "" H 2600 4500 60 0000 C CNN + 14 2600 4500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7700 6200 9250 6200 +Wire Wire Line + 5400 6950 4550 6950 +Wire Wire Line + 5400 3250 5400 6950 +Wire Wire Line + 5400 6050 5550 6050 +Wire Wire Line + 5400 5000 5550 5000 +Connection ~ 5400 6050 +Wire Wire Line + 5400 3250 5550 3250 +Connection ~ 5400 5000 +$Comp +L PORT U1 +U 9 1 6837E103 +P 9500 3600 +F 0 "U1" H 9550 3700 30 0000 C CNN +F 1 "PORT" H 9500 3600 30 0000 C CNN +F 2 "" H 9500 3600 60 0000 C CNN +F 3 "" H 9500 3600 60 0000 C CNN + 9 9500 3600 + -1 0 0 1 +$EndComp +Wire Wire Line + 2900 6950 3950 6950 +$Comp +L PORT U1 +U 6 1 6837E252 +P 2550 2450 +F 0 "U1" H 2600 2550 30 0000 C CNN +F 1 "PORT" H 2550 2450 30 0000 C CNN +F 2 "" H 2550 2450 60 0000 C CNN +F 3 "" H 2550 2450 60 0000 C CNN + 6 2550 2450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 6837E2CB +P 2550 2650 +F 0 "U1" H 2600 2750 30 0000 C CNN +F 1 "PORT" H 2550 2650 30 0000 C CNN +F 2 "" H 2550 2650 60 0000 C CNN +F 3 "" H 2550 2650 60 0000 C CNN + 5 2550 2650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2800 6700 5350 6700 +Wire Wire Line + 5350 6700 5350 6400 +Wire Wire Line + 5350 6400 5550 6400 +Wire Wire Line + 2800 6500 5250 6500 +Wire Wire Line + 5250 6500 5250 6300 +Wire Wire Line + 5250 6300 5550 6300 +Wire Wire Line + 4800 1450 4800 6700 +Wire Wire Line + 4800 5950 5550 5950 +Connection ~ 4800 6700 +Wire Wire Line + 4800 5400 5550 5400 +Connection ~ 4800 5950 +Wire Wire Line + 4800 4900 5550 4900 +Connection ~ 4800 5400 +Wire Wire Line + 3300 1000 3300 6500 +Wire Wire Line + 3300 5200 5550 5200 +Connection ~ 3300 6500 +$Comp +L PORT U1 +U 3 1 6837FEF1 +P 2550 6700 +F 0 "U1" H 2600 6800 30 0000 C CNN +F 1 "PORT" H 2550 6700 30 0000 C CNN +F 2 "" H 2550 6700 60 0000 C CNN +F 3 "" H 2550 6700 60 0000 C CNN + 3 2550 6700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 6837FFA2 +P 2550 6500 +F 0 "U1" H 2600 6600 30 0000 C CNN +F 1 "PORT" H 2550 6500 30 0000 C CNN +F 2 "" H 2550 6500 60 0000 C CNN +F 3 "" H 2550 6500 60 0000 C CNN + 4 2550 6500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5200 5850 2800 5850 +Wire Wire Line + 5200 1350 5200 5850 +Wire Wire Line + 5200 5700 5550 5700 +Wire Wire Line + 2800 5650 5550 5650 +Wire Wire Line + 5550 5650 5550 5600 +Wire Wire Line + 5200 5300 5550 5300 +Connection ~ 5200 5700 +Wire Wire Line + 5200 4800 5550 4800 +Connection ~ 5200 5300 +Wire Wire Line + 3300 3450 5550 3450 +Connection ~ 3300 5200 +Wire Wire Line + 3300 1000 4750 1000 +Connection ~ 3300 3450 +Wire Wire Line + 2850 4500 5550 4500 +Wire Wire Line + 2850 4300 2850 4400 +Wire Wire Line + 2850 4400 5550 4400 +Wire Wire Line + 3450 900 3450 5650 +Wire Wire Line + 3450 4000 5550 4000 +Connection ~ 3450 5650 +Wire Wire Line + 3450 1650 5550 1650 +Connection ~ 3450 4000 +Wire Wire Line + 3450 900 4750 900 +Connection ~ 3450 1650 +Wire Wire Line + 3600 800 3600 4400 +Wire Wire Line + 3600 2200 5550 2200 +Connection ~ 3600 4400 +Wire Wire Line + 3600 800 4750 800 +Connection ~ 3600 2200 +Wire Wire Line + 5250 1250 5250 4500 +Wire Wire Line + 5250 4100 5550 4100 +Connection ~ 5250 4500 +Wire Wire Line + 5200 4200 5550 4200 +Connection ~ 5200 4800 +Wire Wire Line + 5200 3650 5550 3650 +Connection ~ 5200 4200 +Wire Wire Line + 5200 3050 5550 3050 +Connection ~ 5200 3650 +Wire Wire Line + 5200 1950 5550 1950 +Connection ~ 5200 3050 +Wire Wire Line + 5200 1350 5550 1350 +Connection ~ 5200 1950 +Wire Wire Line + 5250 3550 5550 3550 +Connection ~ 5250 4100 +Wire Wire Line + 5250 2950 5550 2950 +Connection ~ 5250 3550 +Wire Wire Line + 5250 2400 5550 2400 +Connection ~ 5250 2950 +Wire Wire Line + 5250 1850 5550 1850 +Connection ~ 5250 2400 +Wire Wire Line + 5250 1250 5550 1250 +Connection ~ 5250 1850 +Wire Wire Line + 4800 3750 5550 3750 +Connection ~ 4800 4900 +Wire Wire Line + 4800 3150 5550 3150 +Connection ~ 4800 3750 +Wire Wire Line + 4800 1450 5550 1450 +Connection ~ 4800 3150 +Wire Wire Line + 2800 5650 2800 5700 +$Comp +L PORT U1 +U 8 1 683AA1B3 +P 10500 2350 +F 0 "U1" H 10550 2450 30 0000 C CNN +F 1 "PORT" H 10500 2350 30 0000 C CNN +F 2 "" H 10500 2350 60 0000 C CNN +F 3 "" H 10500 2350 60 0000 C CNN + 8 10500 2350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8800 3600 9250 3600 +$Comp +L PORT U1 +U 16 1 683BD0F1 +P 10500 2700 +F 0 "U1" H 10550 2800 30 0000 C CNN +F 1 "PORT" H 10500 2700 30 0000 C CNN +F 2 "" H 10500 2700 60 0000 C CNN +F 3 "" H 10500 2700 60 0000 C CNN + 16 10500 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 15 1 683BD1F3 +P 2600 4300 +F 0 "U1" H 2650 4400 30 0000 C CNN +F 1 "PORT" H 2600 4300 30 0000 C CNN +F 2 "" H 2600 4300 60 0000 C CNN +F 3 "" H 2600 4300 60 0000 C CNN + 15 2600 4300 + 1 0 0 -1 +$EndComp +NoConn ~ 10750 2350 +NoConn ~ 10750 2700 +Wire Wire Line + 6500 1750 7100 1750 +Wire Wire Line + 6450 1800 6500 1800 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74182/SN74182.sub b/library/SubcircuitLibrary/SN74182/SN74182.sub new file mode 100644 index 000000000..705a68536 --- /dev/null +++ b/library/SubcircuitLibrary/SN74182/SN74182.sub @@ -0,0 +1,64 @@ +* Subcircuit SN74182 +.subckt SN74182 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? +* c:\fossee\esim\library\subcircuitlibrary\sn74182\sn74182.cir +.include 4_and.sub +.include 4_OR.sub +.include 3_and.sub +x1 net-_u1-pad6_ net-_u1-pad15_ net-_u1-pad2_ net-_u1-pad4_ net-_u1-pad7_ 4_OR +x6 net-_u1-pad5_ net-_u1-pad14_ net-_u1-pad1_ net-_u1-pad3_ net-_x10-pad1_ 4_and +x2 net-_u1-pad15_ net-_u1-pad5_ net-_u1-pad14_ net-_x10-pad3_ 3_and +x7 net-_u1-pad2_ net-_u1-pad5_ net-_u1-pad14_ net-_u1-pad1_ net-_x10-pad2_ 4_and +* u3 net-_u1-pad6_ net-_u1-pad5_ net-_u3-pad3_ d_and +x10 net-_x10-pad1_ net-_x10-pad2_ net-_x10-pad3_ net-_u3-pad3_ net-_u1-pad10_ 4_OR +x8 net-_u1-pad14_ net-_u1-pad1_ net-_u1-pad3_ net-_u2-pad2_ net-_x11-pad1_ 4_and +x3 net-_u1-pad2_ net-_u1-pad14_ net-_u1-pad1_ net-_x11-pad3_ 3_and +x9 net-_u1-pad4_ net-_u1-pad14_ net-_u1-pad1_ net-_u1-pad3_ net-_x11-pad2_ 4_and +* u4 net-_u1-pad15_ net-_u1-pad14_ net-_u4-pad3_ d_and +x11 net-_x11-pad1_ net-_x11-pad2_ net-_x11-pad3_ net-_u4-pad3_ net-_u11-pad1_ 4_OR +* u11 net-_u11-pad1_ net-_u1-pad9_ d_inverter +x4 net-_u1-pad1_ net-_u1-pad3_ net-_u2-pad2_ net-_u8-pad1_ 3_and +x5 net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad3_ net-_u8-pad2_ 3_and +* u5 net-_u1-pad2_ net-_u1-pad1_ net-_u10-pad2_ d_and +* u8 net-_u8-pad1_ net-_u8-pad2_ net-_u10-pad1_ d_or +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_or +* u12 net-_u10-pad3_ net-_u1-pad11_ d_inverter +* u2 net-_u1-pad13_ net-_u2-pad2_ d_inverter +* u6 net-_u1-pad3_ net-_u2-pad2_ net-_u6-pad3_ d_and +* u7 net-_u1-pad4_ net-_u1-pad3_ net-_u7-pad3_ d_and +* u9 net-_u6-pad3_ net-_u7-pad3_ net-_u1-pad12_ d_nor +a1 [net-_u1-pad6_ net-_u1-pad5_ ] net-_u3-pad3_ u3 +a2 [net-_u1-pad15_ net-_u1-pad14_ ] net-_u4-pad3_ u4 +a3 net-_u11-pad1_ net-_u1-pad9_ u11 +a4 [net-_u1-pad2_ net-_u1-pad1_ ] net-_u10-pad2_ u5 +a5 [net-_u8-pad1_ net-_u8-pad2_ ] net-_u10-pad1_ u8 +a6 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a7 net-_u10-pad3_ net-_u1-pad11_ u12 +a8 net-_u1-pad13_ net-_u2-pad2_ u2 +a9 [net-_u1-pad3_ net-_u2-pad2_ ] net-_u6-pad3_ u6 +a10 [net-_u1-pad4_ net-_u1-pad3_ ] net-_u7-pad3_ u7 +a11 [net-_u6-pad3_ net-_u7-pad3_ ] net-_u1-pad12_ u9 +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u8 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u10 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u9 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SN74182 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74182/SN74182_Previous_Values.xml b/library/SubcircuitLibrary/SN74182/SN74182_Previous_Values.xml new file mode 100644 index 000000000..233e79324 --- /dev/null +++ b/library/SubcircuitLibrary/SN74182/SN74182_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_andd_andd_inverterd_andd_ord_ord_inverterd_inverterd_andd_andd_norC:\FOSSEE\eSim\library\SubcircuitLibrary\4_ORC:\FOSSEE\eSim\library\SubcircuitLibrary\4_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\4_andC:\FOSSEE\eSim\library\SubcircuitLibrary\4_ORC:\FOSSEE\eSim\library\SubcircuitLibrary\4_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\4_andC:\FOSSEE\eSim\library\SubcircuitLibrary\4_ORC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74182/analysis b/library/SubcircuitLibrary/SN74182/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/SN74182/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74279/3_and-cache.lib b/library/SubcircuitLibrary/SN74279/3_and-cache.lib new file mode 100644 index 000000000..af0586415 --- /dev/null +++ b/library/SubcircuitLibrary/SN74279/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74279/3_and.cir b/library/SubcircuitLibrary/SN74279/3_and.cir new file mode 100644 index 000000000..ba296cf01 --- /dev/null +++ b/library/SubcircuitLibrary/SN74279/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74279/3_and.cir.out b/library/SubcircuitLibrary/SN74279/3_and.cir.out new file mode 100644 index 000000000..d7cf79a07 --- /dev/null +++ b/library/SubcircuitLibrary/SN74279/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74279/3_and.pro b/library/SubcircuitLibrary/SN74279/3_and.pro new file mode 100644 index 000000000..00597a5ad --- /dev/null +++ b/library/SubcircuitLibrary/SN74279/3_and.pro @@ -0,0 +1,43 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_User +LibName9=eSim_Sources +LibName10=eSim_Subckt diff --git a/library/SubcircuitLibrary/SN74279/3_and.sch b/library/SubcircuitLibrary/SN74279/3_and.sch new file mode 100644 index 000000000..d6ac89f95 --- /dev/null +++ b/library/SubcircuitLibrary/SN74279/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74279/3_and.sub b/library/SubcircuitLibrary/SN74279/3_and.sub new file mode 100644 index 000000000..3d9120bb6 --- /dev/null +++ b/library/SubcircuitLibrary/SN74279/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74279/3_and_Previous_Values.xml b/library/SubcircuitLibrary/SN74279/3_and_Previous_Values.xml new file mode 100644 index 000000000..abc5faaae --- /dev/null +++ b/library/SubcircuitLibrary/SN74279/3_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74279/SN74279-cache.lib b/library/SubcircuitLibrary/SN74279/SN74279-cache.lib new file mode 100644 index 000000000..cecf21613 --- /dev/null +++ b/library/SubcircuitLibrary/SN74279/SN74279-cache.lib @@ -0,0 +1,93 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74279/SN74279.cir b/library/SubcircuitLibrary/SN74279/SN74279.cir new file mode 100644 index 000000000..e454794a6 --- /dev/null +++ b/library/SubcircuitLibrary/SN74279/SN74279.cir @@ -0,0 +1,21 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\SN74279\SN74279.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/05/25 18:55:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad4_ Net-_U2-Pad3_ d_nand +X1 Net-_U2-Pad3_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U8-Pad1_ 3_and +U8 Net-_U8-Pad1_ Net-_U1-Pad4_ d_inverter +U3 Net-_U1-Pad5_ Net-_U1-Pad7_ Net-_U3-Pad3_ d_nand +U4 Net-_U3-Pad3_ Net-_U1-Pad6_ Net-_U1-Pad7_ d_nand +U5 Net-_U1-Pad10_ Net-_U1-Pad9_ Net-_U5-Pad3_ d_nand +X2 Net-_U5-Pad3_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U9-Pad1_ 3_and +U9 Net-_U9-Pad1_ Net-_U1-Pad9_ d_inverter +U6 Net-_U1-Pad14_ Net-_U1-Pad13_ Net-_U6-Pad3_ d_nand +U7 Net-_U6-Pad3_ Net-_U1-Pad15_ Net-_U1-Pad13_ d_nand +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ ? PORT + +.end diff --git a/library/SubcircuitLibrary/SN74279/SN74279.cir.out b/library/SubcircuitLibrary/SN74279/SN74279.cir.out new file mode 100644 index 000000000..534e59b45 --- /dev/null +++ b/library/SubcircuitLibrary/SN74279/SN74279.cir.out @@ -0,0 +1,47 @@ +* c:\fossee\esim\library\subcircuitlibrary\sn74279\sn74279.cir + +.include 3_and.sub +* u2 net-_u1-pad1_ net-_u1-pad4_ net-_u2-pad3_ d_nand +x1 net-_u2-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u8-pad1_ 3_and +* u8 net-_u8-pad1_ net-_u1-pad4_ d_inverter +* u3 net-_u1-pad5_ net-_u1-pad7_ net-_u3-pad3_ d_nand +* u4 net-_u3-pad3_ net-_u1-pad6_ net-_u1-pad7_ d_nand +* u5 net-_u1-pad10_ net-_u1-pad9_ net-_u5-pad3_ d_nand +x2 net-_u5-pad3_ net-_u1-pad11_ net-_u1-pad12_ net-_u9-pad1_ 3_and +* u9 net-_u9-pad1_ net-_u1-pad9_ d_inverter +* u6 net-_u1-pad14_ net-_u1-pad13_ net-_u6-pad3_ d_nand +* u7 net-_u6-pad3_ net-_u1-pad15_ net-_u1-pad13_ d_nand +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? port +a1 [net-_u1-pad1_ net-_u1-pad4_ ] net-_u2-pad3_ u2 +a2 net-_u8-pad1_ net-_u1-pad4_ u8 +a3 [net-_u1-pad5_ net-_u1-pad7_ ] net-_u3-pad3_ u3 +a4 [net-_u3-pad3_ net-_u1-pad6_ ] net-_u1-pad7_ u4 +a5 [net-_u1-pad10_ net-_u1-pad9_ ] net-_u5-pad3_ u5 +a6 net-_u9-pad1_ net-_u1-pad9_ u9 +a7 [net-_u1-pad14_ net-_u1-pad13_ ] net-_u6-pad3_ u6 +a8 [net-_u6-pad3_ net-_u1-pad15_ ] net-_u1-pad13_ u7 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u2 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u6 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u7 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74279/SN74279.pro b/library/SubcircuitLibrary/SN74279/SN74279.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/SN74279/SN74279.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN74279/SN74279.sch b/library/SubcircuitLibrary/SN74279/SN74279.sch new file mode 100644 index 000000000..9f5ebe03e --- /dev/null +++ b/library/SubcircuitLibrary/SN74279/SN74279.sch @@ -0,0 +1,440 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_nand U2 +U 1 1 6841981C +P 4200 1250 +F 0 "U2" H 4200 1250 60 0000 C CNN +F 1 "d_nand" H 4250 1350 60 0000 C CNN +F 2 "" H 4200 1250 60 0000 C CNN +F 3 "" H 4200 1250 60 0000 C CNN + 1 4200 1250 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X1 +U 1 1 6841985F +P 4150 1850 +F 0 "X1" H 4250 1800 60 0000 C CNN +F 1 "3_and" H 4300 2000 60 0000 C CNN +F 2 "" H 4150 1850 60 0000 C CNN +F 3 "" H 4150 1850 60 0000 C CNN + 1 4150 1850 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U8 +U 1 1 68419888 +P 5000 1800 +F 0 "U8" H 5000 1700 60 0000 C CNN +F 1 "d_inverter" H 5000 1950 60 0000 C CNN +F 2 "" H 5050 1750 60 0000 C CNN +F 3 "" H 5050 1750 60 0000 C CNN + 1 5000 1800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4650 1800 4700 1800 +Wire Wire Line + 3750 1250 3750 1450 +Wire Wire Line + 3750 1450 5550 1450 +Wire Wire Line + 5550 1450 5550 1800 +Wire Wire Line + 5300 1800 5800 1800 +Wire Wire Line + 3800 1700 3800 1500 +Wire Wire Line + 3800 1500 4850 1500 +Wire Wire Line + 4850 1500 4850 1200 +Wire Wire Line + 4850 1200 4650 1200 +$Comp +L d_nand U3 +U 1 1 684198D9 +P 4250 2500 +F 0 "U3" H 4250 2500 60 0000 C CNN +F 1 "d_nand" H 4300 2600 60 0000 C CNN +F 2 "" H 4250 2500 60 0000 C CNN +F 3 "" H 4250 2500 60 0000 C CNN + 1 4250 2500 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U4 +U 1 1 68419903 +P 4250 3050 +F 0 "U4" H 4250 3050 60 0000 C CNN +F 1 "d_nand" H 4300 3150 60 0000 C CNN +F 2 "" H 4250 3050 60 0000 C CNN +F 3 "" H 4250 3050 60 0000 C CNN + 1 4250 3050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3800 2500 3800 2700 +Wire Wire Line + 3800 2700 5050 2700 +Wire Wire Line + 5050 2700 5050 3000 +Wire Wire Line + 4700 3000 5800 3000 +Wire Wire Line + 3800 2950 3800 2750 +Wire Wire Line + 3800 2750 4850 2750 +Wire Wire Line + 4850 2750 4850 2450 +Wire Wire Line + 4850 2450 4700 2450 +$Comp +L d_nand U5 +U 1 1 68419BA1 +P 4300 3700 +F 0 "U5" H 4300 3700 60 0000 C CNN +F 1 "d_nand" H 4350 3800 60 0000 C CNN +F 2 "" H 4300 3700 60 0000 C CNN +F 3 "" H 4300 3700 60 0000 C CNN + 1 4300 3700 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X2 +U 1 1 68419BA7 +P 4250 4300 +F 0 "X2" H 4350 4250 60 0000 C CNN +F 1 "3_and" H 4400 4450 60 0000 C CNN +F 2 "" H 4250 4300 60 0000 C CNN +F 3 "" H 4250 4300 60 0000 C CNN + 1 4250 4300 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U9 +U 1 1 68419BAD +P 5100 4250 +F 0 "U9" H 5100 4150 60 0000 C CNN +F 1 "d_inverter" H 5100 4400 60 0000 C CNN +F 2 "" H 5150 4200 60 0000 C CNN +F 3 "" H 5150 4200 60 0000 C CNN + 1 5100 4250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4750 4250 4800 4250 +Wire Wire Line + 3850 3700 3850 3900 +Wire Wire Line + 3850 3900 5650 3900 +Wire Wire Line + 5650 3900 5650 4250 +Wire Wire Line + 5400 4250 5850 4250 +Wire Wire Line + 3900 4150 3900 3950 +Wire Wire Line + 3900 3950 4950 3950 +Wire Wire Line + 4950 3950 4950 3650 +Wire Wire Line + 4950 3650 4750 3650 +$Comp +L d_nand U6 +U 1 1 68419CF4 +P 4400 5050 +F 0 "U6" H 4400 5050 60 0000 C CNN +F 1 "d_nand" H 4450 5150 60 0000 C CNN +F 2 "" H 4400 5050 60 0000 C CNN +F 3 "" H 4400 5050 60 0000 C CNN + 1 4400 5050 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U7 +U 1 1 68419CFA +P 4400 5600 +F 0 "U7" H 4400 5600 60 0000 C CNN +F 1 "d_nand" H 4450 5700 60 0000 C CNN +F 2 "" H 4400 5600 60 0000 C CNN +F 3 "" H 4400 5600 60 0000 C CNN + 1 4400 5600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3950 5050 3950 5250 +Wire Wire Line + 3950 5250 5200 5250 +Wire Wire Line + 5200 5250 5200 5550 +Wire Wire Line + 4850 5550 5850 5550 +Wire Wire Line + 3950 5500 3950 5300 +Wire Wire Line + 3950 5300 5000 5300 +Wire Wire Line + 5000 5300 5000 5000 +Wire Wire Line + 5000 5000 4850 5000 +$Comp +L PORT U1 +U 8 1 6841A17E +P 6700 1250 +F 0 "U1" H 6750 1350 30 0000 C CNN +F 1 "PORT" H 6700 1250 30 0000 C CNN +F 2 "" H 6700 1250 60 0000 C CNN +F 3 "" H 6700 1250 60 0000 C CNN + 8 6700 1250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 6841A1E5 +P 3250 4400 +F 0 "U1" H 3300 4500 30 0000 C CNN +F 1 "PORT" H 3250 4400 30 0000 C CNN +F 2 "" H 3250 4400 60 0000 C CNN +F 3 "" H 3250 4400 60 0000 C CNN + 12 3250 4400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 6841A216 +P 6100 5550 +F 0 "U1" H 6150 5650 30 0000 C CNN +F 1 "PORT" H 6100 5550 30 0000 C CNN +F 2 "" H 6100 5550 60 0000 C CNN +F 3 "" H 6100 5550 60 0000 C CNN + 13 6100 5550 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 15 1 6841A245 +P 3250 5600 +F 0 "U1" H 3300 5700 30 0000 C CNN +F 1 "PORT" H 3250 5600 30 0000 C CNN +F 2 "" H 3250 5600 60 0000 C CNN +F 3 "" H 3250 5600 60 0000 C CNN + 15 3250 5600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 6841A276 +P 3200 1800 +F 0 "U1" H 3250 1900 30 0000 C CNN +F 1 "PORT" H 3200 1800 30 0000 C CNN +F 2 "" H 3200 1800 60 0000 C CNN +F 3 "" H 3200 1800 60 0000 C CNN + 2 3200 1800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 6841A2B7 +P 3200 3600 +F 0 "U1" H 3250 3700 30 0000 C CNN +F 1 "PORT" H 3200 3600 30 0000 C CNN +F 2 "" H 3200 3600 60 0000 C CNN +F 3 "" H 3200 3600 60 0000 C CNN + 10 3200 3600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 6841A2F4 +P 3200 1950 +F 0 "U1" H 3250 2050 30 0000 C CNN +F 1 "PORT" H 3200 1950 30 0000 C CNN +F 2 "" H 3200 1950 60 0000 C CNN +F 3 "" H 3200 1950 60 0000 C CNN + 3 3200 1950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 6841A33F +P 6100 4250 +F 0 "U1" H 6150 4350 30 0000 C CNN +F 1 "PORT" H 6100 4250 30 0000 C CNN +F 2 "" H 6100 4250 60 0000 C CNN +F 3 "" H 6100 4250 60 0000 C CNN + 9 6100 4250 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 6841A384 +P 6050 1800 +F 0 "U1" H 6100 1900 30 0000 C CNN +F 1 "PORT" H 6050 1800 30 0000 C CNN +F 2 "" H 6050 1800 60 0000 C CNN +F 3 "" H 6050 1800 60 0000 C CNN + 4 6050 1800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 1 1 6841A3C9 +P 3200 1150 +F 0 "U1" H 3250 1250 30 0000 C CNN +F 1 "PORT" H 3200 1150 30 0000 C CNN +F 2 "" H 3200 1150 60 0000 C CNN +F 3 "" H 3200 1150 60 0000 C CNN + 1 3200 1150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 6841A414 +P 3200 2400 +F 0 "U1" H 3250 2500 30 0000 C CNN +F 1 "PORT" H 3200 2400 30 0000 C CNN +F 2 "" H 3200 2400 60 0000 C CNN +F 3 "" H 3200 2400 60 0000 C CNN + 5 3200 2400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 6841A45D +P 3200 3050 +F 0 "U1" H 3250 3150 30 0000 C CNN +F 1 "PORT" H 3200 3050 30 0000 C CNN +F 2 "" H 3200 3050 60 0000 C CNN +F 3 "" H 3200 3050 60 0000 C CNN + 6 3200 3050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 6841A4A8 +P 6050 3000 +F 0 "U1" H 6100 3100 30 0000 C CNN +F 1 "PORT" H 6050 3000 30 0000 C CNN +F 2 "" H 6050 3000 60 0000 C CNN +F 3 "" H 6050 3000 60 0000 C CNN + 7 6050 3000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 6841A4F7 +P 3250 4950 +F 0 "U1" H 3300 5050 30 0000 C CNN +F 1 "PORT" H 3250 4950 30 0000 C CNN +F 2 "" H 3250 4950 60 0000 C CNN +F 3 "" H 3250 4950 60 0000 C CNN + 14 3250 4950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 6841A53C +P 3250 4250 +F 0 "U1" H 3300 4350 30 0000 C CNN +F 1 "PORT" H 3250 4250 30 0000 C CNN +F 2 "" H 3250 4250 60 0000 C CNN +F 3 "" H 3250 4250 60 0000 C CNN + 11 3250 4250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 16 1 6841A59F +P 6700 1450 +F 0 "U1" H 6750 1550 30 0000 C CNN +F 1 "PORT" H 6700 1450 30 0000 C CNN +F 2 "" H 6700 1450 60 0000 C CNN +F 3 "" H 6700 1450 60 0000 C CNN + 16 6700 1450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3450 1150 3750 1150 +Wire Wire Line + 3450 1800 3800 1800 +Wire Wire Line + 3450 1950 3800 1950 +Wire Wire Line + 3800 1950 3800 1900 +Wire Wire Line + 3450 2400 3800 2400 +Wire Wire Line + 3450 3050 3800 3050 +Wire Wire Line + 3450 3600 3850 3600 +Wire Wire Line + 3500 4250 3900 4250 +Wire Wire Line + 3500 4400 3900 4400 +Wire Wire Line + 3900 4400 3900 4350 +Wire Wire Line + 3500 4950 3950 4950 +Wire Wire Line + 3500 5600 3950 5600 +Connection ~ 5200 5550 +Connection ~ 5650 4250 +Connection ~ 5050 3000 +Connection ~ 5550 1800 +NoConn ~ 6950 1250 +NoConn ~ 6950 1450 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74279/SN74279.sub b/library/SubcircuitLibrary/SN74279/SN74279.sub new file mode 100644 index 000000000..5443375e5 --- /dev/null +++ b/library/SubcircuitLibrary/SN74279/SN74279.sub @@ -0,0 +1,41 @@ +* Subcircuit SN74279 +.subckt SN74279 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? +* c:\fossee\esim\library\subcircuitlibrary\sn74279\sn74279.cir +.include 3_and.sub +* u2 net-_u1-pad1_ net-_u1-pad4_ net-_u2-pad3_ d_nand +x1 net-_u2-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u8-pad1_ 3_and +* u8 net-_u8-pad1_ net-_u1-pad4_ d_inverter +* u3 net-_u1-pad5_ net-_u1-pad7_ net-_u3-pad3_ d_nand +* u4 net-_u3-pad3_ net-_u1-pad6_ net-_u1-pad7_ d_nand +* u5 net-_u1-pad10_ net-_u1-pad9_ net-_u5-pad3_ d_nand +x2 net-_u5-pad3_ net-_u1-pad11_ net-_u1-pad12_ net-_u9-pad1_ 3_and +* u9 net-_u9-pad1_ net-_u1-pad9_ d_inverter +* u6 net-_u1-pad14_ net-_u1-pad13_ net-_u6-pad3_ d_nand +* u7 net-_u6-pad3_ net-_u1-pad15_ net-_u1-pad13_ d_nand +a1 [net-_u1-pad1_ net-_u1-pad4_ ] net-_u2-pad3_ u2 +a2 net-_u8-pad1_ net-_u1-pad4_ u8 +a3 [net-_u1-pad5_ net-_u1-pad7_ ] net-_u3-pad3_ u3 +a4 [net-_u3-pad3_ net-_u1-pad6_ ] net-_u1-pad7_ u4 +a5 [net-_u1-pad10_ net-_u1-pad9_ ] net-_u5-pad3_ u5 +a6 net-_u9-pad1_ net-_u1-pad9_ u9 +a7 [net-_u1-pad14_ net-_u1-pad13_ ] net-_u6-pad3_ u6 +a8 [net-_u6-pad3_ net-_u1-pad15_ ] net-_u1-pad13_ u7 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u2 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u6 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u7 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SN74279 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74279/SN74279_Previous_Values.xml b/library/SubcircuitLibrary/SN74279/SN74279_Previous_Values.xml new file mode 100644 index 000000000..2f2686b12 --- /dev/null +++ b/library/SubcircuitLibrary/SN74279/SN74279_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_nandd_inverterd_nandd_nandd_nandd_inverterd_nandd_nandC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74279/analysis b/library/SubcircuitLibrary/SN74279/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/SN74279/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74H53/3_and-cache.lib b/library/SubcircuitLibrary/SN74H53/3_and-cache.lib new file mode 100644 index 000000000..af0586415 --- /dev/null +++ b/library/SubcircuitLibrary/SN74H53/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74H53/3_and.cir b/library/SubcircuitLibrary/SN74H53/3_and.cir new file mode 100644 index 000000000..ba296cf01 --- /dev/null +++ b/library/SubcircuitLibrary/SN74H53/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74H53/3_and.cir.out b/library/SubcircuitLibrary/SN74H53/3_and.cir.out new file mode 100644 index 000000000..d7cf79a07 --- /dev/null +++ b/library/SubcircuitLibrary/SN74H53/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74H53/3_and.pro b/library/SubcircuitLibrary/SN74H53/3_and.pro new file mode 100644 index 000000000..00597a5ad --- /dev/null +++ b/library/SubcircuitLibrary/SN74H53/3_and.pro @@ -0,0 +1,43 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_User +LibName9=eSim_Sources +LibName10=eSim_Subckt diff --git a/library/SubcircuitLibrary/SN74H53/3_and.sch b/library/SubcircuitLibrary/SN74H53/3_and.sch new file mode 100644 index 000000000..d6ac89f95 --- /dev/null +++ b/library/SubcircuitLibrary/SN74H53/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74H53/3_and.sub b/library/SubcircuitLibrary/SN74H53/3_and.sub new file mode 100644 index 000000000..3d9120bb6 --- /dev/null +++ b/library/SubcircuitLibrary/SN74H53/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74H53/3_and_Previous_Values.xml b/library/SubcircuitLibrary/SN74H53/3_and_Previous_Values.xml new file mode 100644 index 000000000..abc5faaae --- /dev/null +++ b/library/SubcircuitLibrary/SN74H53/3_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74H53/SN74H53-cache.lib b/library/SubcircuitLibrary/SN74H53/SN74H53-cache.lib new file mode 100644 index 000000000..8256d8a65 --- /dev/null +++ b/library/SubcircuitLibrary/SN74H53/SN74H53-cache.lib @@ -0,0 +1,112 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74H53/SN74H53.cir b/library/SubcircuitLibrary/SN74H53/SN74H53.cir new file mode 100644 index 000000000..3d277aadc --- /dev/null +++ b/library/SubcircuitLibrary/SN74H53/SN74H53.cir @@ -0,0 +1,22 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\SN74H53\SN74H53.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/26/25 08:17:09 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad13_ Net-_U2-Pad3_ d_and +U3 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad3_ d_and +U4 Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U4-Pad3_ d_and +X1 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U7-Pad1_ 3_and +U6 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U6-Pad3_ d_or +U7 Net-_U7-Pad1_ Net-_U4-Pad3_ Net-_U7-Pad3_ d_or +U8 Net-_U6-Pad3_ Net-_U7-Pad3_ Net-_U10-Pad1_ d_or +U9 Net-_U1-Pad11_ Net-_U5-Pad2_ Net-_U10-Pad2_ d_or +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_or +U5 Net-_U1-Pad12_ Net-_U5-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ ? Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT +U11 Net-_U10-Pad3_ Net-_U1-Pad8_ d_inverter + +.end diff --git a/library/SubcircuitLibrary/SN74H53/SN74H53.cir.out b/library/SubcircuitLibrary/SN74H53/SN74H53.cir.out new file mode 100644 index 000000000..ec18a34d7 --- /dev/null +++ b/library/SubcircuitLibrary/SN74H53/SN74H53.cir.out @@ -0,0 +1,54 @@ +* c:\fossee\esim\library\subcircuitlibrary\sn74h53\sn74h53.cir + +.include 3_and.sub +* u2 net-_u1-pad1_ net-_u1-pad13_ net-_u2-pad3_ d_and +* u3 net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad3_ d_and +* u4 net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_and +x1 net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u7-pad1_ 3_and +* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u6-pad3_ d_or +* u7 net-_u7-pad1_ net-_u4-pad3_ net-_u7-pad3_ d_or +* u8 net-_u6-pad3_ net-_u7-pad3_ net-_u10-pad1_ d_or +* u9 net-_u1-pad11_ net-_u5-pad2_ net-_u10-pad2_ d_or +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_or +* u5 net-_u1-pad12_ net-_u5-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port +* u11 net-_u10-pad3_ net-_u1-pad8_ d_inverter +a1 [net-_u1-pad1_ net-_u1-pad13_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u3-pad3_ u3 +a3 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4 +a4 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u6-pad3_ u6 +a5 [net-_u7-pad1_ net-_u4-pad3_ ] net-_u7-pad3_ u7 +a6 [net-_u6-pad3_ net-_u7-pad3_ ] net-_u10-pad1_ u8 +a7 [net-_u1-pad11_ net-_u5-pad2_ ] net-_u10-pad2_ u9 +a8 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a9 net-_u1-pad12_ net-_u5-pad2_ u5 +a10 net-_u10-pad3_ net-_u1-pad8_ u11 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u6 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u7 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u8 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u9 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u10 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74H53/SN74H53.pro b/library/SubcircuitLibrary/SN74H53/SN74H53.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/SN74H53/SN74H53.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN74H53/SN74H53.sch b/library/SubcircuitLibrary/SN74H53/SN74H53.sch new file mode 100644 index 000000000..78a53dd2a --- /dev/null +++ b/library/SubcircuitLibrary/SN74H53/SN74H53.sch @@ -0,0 +1,410 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SN74H53-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 685CA412 +P 4150 2200 +F 0 "U2" H 4150 2200 60 0000 C CNN +F 1 "d_and" H 4200 2300 60 0000 C CNN +F 2 "" H 4150 2200 60 0000 C CNN +F 3 "" H 4150 2200 60 0000 C CNN + 1 4150 2200 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 685CA450 +P 4150 2550 +F 0 "U3" H 4150 2550 60 0000 C CNN +F 1 "d_and" H 4200 2650 60 0000 C CNN +F 2 "" H 4150 2550 60 0000 C CNN +F 3 "" H 4150 2550 60 0000 C CNN + 1 4150 2550 + 1 0 0 -1 +$EndComp +$Comp +L d_and U4 +U 1 1 685CA478 +P 4200 3750 +F 0 "U4" H 4200 3750 60 0000 C CNN +F 1 "d_and" H 4250 3850 60 0000 C CNN +F 2 "" H 4200 3750 60 0000 C CNN +F 3 "" H 4200 3750 60 0000 C CNN + 1 4200 3750 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X1 +U 1 1 685CA4B6 +P 4100 3150 +F 0 "X1" H 4200 3100 60 0000 C CNN +F 1 "3_and" H 4250 3300 60 0000 C CNN +F 2 "" H 4100 3150 60 0000 C CNN +F 3 "" H 4100 3150 60 0000 C CNN + 1 4100 3150 + 1 0 0 -1 +$EndComp +$Comp +L d_or U6 +U 1 1 685CA4FB +P 5350 2350 +F 0 "U6" H 5350 2350 60 0000 C CNN +F 1 "d_or" H 5350 2450 60 0000 C CNN +F 2 "" H 5350 2350 60 0000 C CNN +F 3 "" H 5350 2350 60 0000 C CNN + 1 5350 2350 + 1 0 0 -1 +$EndComp +$Comp +L d_or U7 +U 1 1 685CA535 +P 5350 3400 +F 0 "U7" H 5350 3400 60 0000 C CNN +F 1 "d_or" H 5350 3500 60 0000 C CNN +F 2 "" H 5350 3400 60 0000 C CNN +F 3 "" H 5350 3400 60 0000 C CNN + 1 5350 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_or U8 +U 1 1 685CA57B +P 6400 2800 +F 0 "U8" H 6400 2800 60 0000 C CNN +F 1 "d_or" H 6400 2900 60 0000 C CNN +F 2 "" H 6400 2800 60 0000 C CNN +F 3 "" H 6400 2800 60 0000 C CNN + 1 6400 2800 + 1 0 0 -1 +$EndComp +$Comp +L d_or U9 +U 1 1 685CA5C0 +P 6400 4250 +F 0 "U9" H 6400 4250 60 0000 C CNN +F 1 "d_or" H 6400 4350 60 0000 C CNN +F 2 "" H 6400 4250 60 0000 C CNN +F 3 "" H 6400 4250 60 0000 C CNN + 1 6400 4250 + 1 0 0 -1 +$EndComp +$Comp +L d_or U10 +U 1 1 685CA616 +P 7700 3250 +F 0 "U10" H 7700 3250 60 0000 C CNN +F 1 "d_or" H 7700 3350 60 0000 C CNN +F 2 "" H 7700 3250 60 0000 C CNN +F 3 "" H 7700 3250 60 0000 C CNN + 1 7700 3250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4600 2150 4900 2150 +Wire Wire Line + 4900 2150 4900 2250 +Wire Wire Line + 4600 2500 4900 2500 +Wire Wire Line + 4900 2500 4900 2350 +Wire Wire Line + 5800 2300 5900 2300 +Wire Wire Line + 5900 2300 5900 2700 +Wire Wire Line + 5900 2700 5950 2700 +Wire Wire Line + 4600 3100 4900 3100 +Wire Wire Line + 4900 3100 4900 3300 +Wire Wire Line + 4650 3700 4900 3700 +Wire Wire Line + 4900 3700 4900 3400 +Wire Wire Line + 5800 3350 5800 2800 +Wire Wire Line + 5800 2800 5950 2800 +Wire Wire Line + 6850 2750 7250 2750 +Wire Wire Line + 7250 2750 7250 3150 +Wire Wire Line + 6850 4200 7250 4200 +Wire Wire Line + 7250 4200 7250 3250 +$Comp +L d_inverter U5 +U 1 1 685CA710 +P 5250 4450 +F 0 "U5" H 5250 4350 60 0000 C CNN +F 1 "d_inverter" H 5250 4600 60 0000 C CNN +F 2 "" H 5300 4400 60 0000 C CNN +F 3 "" H 5300 4400 60 0000 C CNN + 1 5250 4450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5550 4450 5950 4450 +Wire Wire Line + 5950 4450 5950 4250 +$Comp +L PORT U1 +U 1 1 685CA792 +P 3350 2100 +F 0 "U1" H 3400 2200 30 0000 C CNN +F 1 "PORT" H 3350 2100 30 0000 C CNN +F 2 "" H 3350 2100 60 0000 C CNN +F 3 "" H 3350 2100 60 0000 C CNN + 1 3350 2100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 685CA801 +P 3350 2400 +F 0 "U1" H 3400 2500 30 0000 C CNN +F 1 "PORT" H 3350 2400 30 0000 C CNN +F 2 "" H 3350 2400 60 0000 C CNN +F 3 "" H 3350 2400 60 0000 C CNN + 2 3350 2400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 685CA83A +P 3350 2550 +F 0 "U1" H 3400 2650 30 0000 C CNN +F 1 "PORT" H 3350 2550 30 0000 C CNN +F 2 "" H 3350 2550 60 0000 C CNN +F 3 "" H 3350 2550 60 0000 C CNN + 3 3350 2550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 685CA869 +P 3350 2900 +F 0 "U1" H 3400 3000 30 0000 C CNN +F 1 "PORT" H 3350 2900 30 0000 C CNN +F 2 "" H 3350 2900 60 0000 C CNN +F 3 "" H 3350 2900 60 0000 C CNN + 4 3350 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 685CA89E +P 3350 3100 +F 0 "U1" H 3400 3200 30 0000 C CNN +F 1 "PORT" H 3350 3100 30 0000 C CNN +F 2 "" H 3350 3100 60 0000 C CNN +F 3 "" H 3350 3100 60 0000 C CNN + 5 3350 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 685CA8D1 +P 3350 3300 +F 0 "U1" H 3400 3400 30 0000 C CNN +F 1 "PORT" H 3350 3300 30 0000 C CNN +F 2 "" H 3350 3300 60 0000 C CNN +F 3 "" H 3350 3300 60 0000 C CNN + 6 3350 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 685CA910 +P 7150 2100 +F 0 "U1" H 7200 2200 30 0000 C CNN +F 1 "PORT" H 7150 2100 30 0000 C CNN +F 2 "" H 7150 2100 60 0000 C CNN +F 3 "" H 7150 2100 60 0000 C CNN + 7 7150 2100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 685CA985 +P 9300 3200 +F 0 "U1" H 9350 3300 30 0000 C CNN +F 1 "PORT" H 9300 3200 30 0000 C CNN +F 2 "" H 9300 3200 60 0000 C CNN +F 3 "" H 9300 3200 60 0000 C CNN + 8 9300 3200 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 9 1 685CA9C0 +P 3350 3600 +F 0 "U1" H 3400 3700 30 0000 C CNN +F 1 "PORT" H 3350 3600 30 0000 C CNN +F 2 "" H 3350 3600 60 0000 C CNN +F 3 "" H 3350 3600 60 0000 C CNN + 9 3350 3600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 685CA9FB +P 3350 3800 +F 0 "U1" H 3400 3900 30 0000 C CNN +F 1 "PORT" H 3350 3800 30 0000 C CNN +F 2 "" H 3350 3800 60 0000 C CNN +F 3 "" H 3350 3800 60 0000 C CNN + 10 3350 3800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 685CAA3C +P 3350 4150 +F 0 "U1" H 3400 4250 30 0000 C CNN +F 1 "PORT" H 3350 4150 30 0000 C CNN +F 2 "" H 3350 4150 60 0000 C CNN +F 3 "" H 3350 4150 60 0000 C CNN + 11 3350 4150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 685CAA7D +P 3350 4450 +F 0 "U1" H 3400 4550 30 0000 C CNN +F 1 "PORT" H 3350 4450 30 0000 C CNN +F 2 "" H 3350 4450 60 0000 C CNN +F 3 "" H 3350 4450 60 0000 C CNN + 12 3350 4450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 685CAAC4 +P 3350 2250 +F 0 "U1" H 3400 2350 30 0000 C CNN +F 1 "PORT" H 3350 2250 30 0000 C CNN +F 2 "" H 3350 2250 60 0000 C CNN +F 3 "" H 3350 2250 60 0000 C CNN + 13 3350 2250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 685CAB07 +P 7150 2300 +F 0 "U1" H 7200 2400 30 0000 C CNN +F 1 "PORT" H 7150 2300 30 0000 C CNN +F 2 "" H 7150 2300 60 0000 C CNN +F 3 "" H 7150 2300 60 0000 C CNN + 14 7150 2300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3600 2100 3700 2100 +Wire Wire Line + 3600 2250 3700 2250 +Wire Wire Line + 3700 2250 3700 2200 +Wire Wire Line + 3600 2400 3700 2400 +Wire Wire Line + 3700 2400 3700 2450 +Wire Wire Line + 3600 2550 3700 2550 +Wire Wire Line + 3600 2900 3750 2900 +Wire Wire Line + 3750 2900 3750 3000 +Wire Wire Line + 3600 3100 3750 3100 +Wire Wire Line + 3600 3300 3750 3300 +Wire Wire Line + 3750 3300 3750 3200 +Wire Wire Line + 3600 3600 3750 3600 +Wire Wire Line + 3750 3600 3750 3650 +Wire Wire Line + 3600 3800 3750 3800 +Wire Wire Line + 3750 3800 3750 3750 +Wire Wire Line + 3600 4150 5950 4150 +Wire Wire Line + 3600 4450 4950 4450 +NoConn ~ 7400 2100 +NoConn ~ 7400 2300 +$Comp +L d_inverter U11 +U 1 1 685CDB2C +P 8550 3200 +F 0 "U11" H 8550 3100 60 0000 C CNN +F 1 "d_inverter" H 8550 3350 60 0000 C CNN +F 2 "" H 8600 3150 60 0000 C CNN +F 3 "" H 8600 3150 60 0000 C CNN + 1 8550 3200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8850 3200 9050 3200 +Wire Wire Line + 8250 3200 8150 3200 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74H53/SN74H53.sub b/library/SubcircuitLibrary/SN74H53/SN74H53.sub new file mode 100644 index 000000000..f0445f685 --- /dev/null +++ b/library/SubcircuitLibrary/SN74H53/SN74H53.sub @@ -0,0 +1,48 @@ +* Subcircuit SN74H53 +.subckt SN74H53 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? +* c:\fossee\esim\library\subcircuitlibrary\sn74h53\sn74h53.cir +.include 3_and.sub +* u2 net-_u1-pad1_ net-_u1-pad13_ net-_u2-pad3_ d_and +* u3 net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad3_ d_and +* u4 net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_and +x1 net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u7-pad1_ 3_and +* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u6-pad3_ d_or +* u7 net-_u7-pad1_ net-_u4-pad3_ net-_u7-pad3_ d_or +* u8 net-_u6-pad3_ net-_u7-pad3_ net-_u10-pad1_ d_or +* u9 net-_u1-pad11_ net-_u5-pad2_ net-_u10-pad2_ d_or +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_or +* u5 net-_u1-pad12_ net-_u5-pad2_ d_inverter +* u11 net-_u10-pad3_ net-_u1-pad8_ d_inverter +a1 [net-_u1-pad1_ net-_u1-pad13_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u3-pad3_ u3 +a3 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4 +a4 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u6-pad3_ u6 +a5 [net-_u7-pad1_ net-_u4-pad3_ ] net-_u7-pad3_ u7 +a6 [net-_u6-pad3_ net-_u7-pad3_ ] net-_u10-pad1_ u8 +a7 [net-_u1-pad11_ net-_u5-pad2_ ] net-_u10-pad2_ u9 +a8 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a9 net-_u1-pad12_ net-_u5-pad2_ u5 +a10 net-_u10-pad3_ net-_u1-pad8_ u11 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u6 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u7 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u8 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u9 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u10 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SN74H53 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74H53/SN74H53_Previous_Values.xml b/library/SubcircuitLibrary/SN74H53/SN74H53_Previous_Values.xml new file mode 100644 index 000000000..9c440c9a6 --- /dev/null +++ b/library/SubcircuitLibrary/SN74H53/SN74H53_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andd_andd_ord_ord_ord_ord_ord_inverterd_inverterC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74H53/analysis b/library/SubcircuitLibrary/SN74H53/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/SN74H53/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74H55/3_and-cache.lib b/library/SubcircuitLibrary/SN74H55/3_and-cache.lib new file mode 100644 index 000000000..af0586415 --- /dev/null +++ b/library/SubcircuitLibrary/SN74H55/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74H55/3_and.cir b/library/SubcircuitLibrary/SN74H55/3_and.cir new file mode 100644 index 000000000..ba296cf01 --- /dev/null +++ b/library/SubcircuitLibrary/SN74H55/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74H55/3_and.cir.out b/library/SubcircuitLibrary/SN74H55/3_and.cir.out new file mode 100644 index 000000000..d7cf79a07 --- /dev/null +++ b/library/SubcircuitLibrary/SN74H55/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74H55/3_and.pro b/library/SubcircuitLibrary/SN74H55/3_and.pro new file mode 100644 index 000000000..06813ca78 --- /dev/null +++ b/library/SubcircuitLibrary/SN74H55/3_and.pro @@ -0,0 +1,43 @@ +update=Wed Mar 18 19:54:53 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_Sources +LibName9=eSim_Subckt +LibName10=eSim_User diff --git a/library/SubcircuitLibrary/SN74H55/3_and.sch b/library/SubcircuitLibrary/SN74H55/3_and.sch new file mode 100644 index 000000000..d6ac89f95 --- /dev/null +++ b/library/SubcircuitLibrary/SN74H55/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74H55/3_and.sub b/library/SubcircuitLibrary/SN74H55/3_and.sub new file mode 100644 index 000000000..3d9120bb6 --- /dev/null +++ b/library/SubcircuitLibrary/SN74H55/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74H55/3_and_Previous_Values.xml b/library/SubcircuitLibrary/SN74H55/3_and_Previous_Values.xml new file mode 100644 index 000000000..abc5faaae --- /dev/null +++ b/library/SubcircuitLibrary/SN74H55/3_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74H55/4_OR-cache.lib b/library/SubcircuitLibrary/SN74H55/4_OR-cache.lib new file mode 100644 index 000000000..155f5e601 --- /dev/null +++ b/library/SubcircuitLibrary/SN74H55/4_OR-cache.lib @@ -0,0 +1,63 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74H55/4_OR.cir b/library/SubcircuitLibrary/SN74H55/4_OR.cir new file mode 100644 index 000000000..b338b7b5f --- /dev/null +++ b/library/SubcircuitLibrary/SN74H55/4_OR.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or +U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or +U4 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74H55/4_OR.cir.out b/library/SubcircuitLibrary/SN74H55/4_OR.cir.out new file mode 100644 index 000000000..adb6b01be --- /dev/null +++ b/library/SubcircuitLibrary/SN74H55/4_OR.cir.out @@ -0,0 +1,24 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74H55/4_OR.pro b/library/SubcircuitLibrary/SN74H55/4_OR.pro new file mode 100644 index 000000000..881563ebd --- /dev/null +++ b/library/SubcircuitLibrary/SN74H55/4_OR.pro @@ -0,0 +1,44 @@ +update=06/01/19 12:36:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_User +LibName10=eSim_Sources +LibName11=eSim_Subckt diff --git a/library/SubcircuitLibrary/SN74H55/4_OR.sch b/library/SubcircuitLibrary/SN74H55/4_OR.sch new file mode 100644 index 000000000..118968656 --- /dev/null +++ b/library/SubcircuitLibrary/SN74H55/4_OR.sch @@ -0,0 +1,150 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_or U2 +U 1 1 5C9D00E1 +P 4300 2950 +F 0 "U2" H 4300 2950 60 0000 C CNN +F 1 "d_or" H 4300 3050 60 0000 C CNN +F 2 "" H 4300 2950 60 0000 C CNN +F 3 "" H 4300 2950 60 0000 C CNN + 1 4300 2950 + 1 0 0 -1 +$EndComp +$Comp +L d_or U3 +U 1 1 5C9D011F +P 4300 3350 +F 0 "U3" H 4300 3350 60 0000 C CNN +F 1 "d_or" H 4300 3450 60 0000 C CNN +F 2 "" H 4300 3350 60 0000 C CNN +F 3 "" H 4300 3350 60 0000 C CNN + 1 4300 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_or U4 +U 1 1 5C9D0141 +P 5250 3150 +F 0 "U4" H 5250 3150 60 0000 C CNN +F 1 "d_or" H 5250 3250 60 0000 C CNN +F 2 "" H 5250 3150 60 0000 C CNN +F 3 "" H 5250 3150 60 0000 C CNN + 1 5250 3150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4800 3050 4800 2900 +Wire Wire Line + 4800 2900 4750 2900 +Wire Wire Line + 4800 3150 4800 3300 +Wire Wire Line + 4800 3300 4750 3300 +Wire Wire Line + 3350 2850 3850 2850 +Wire Wire Line + 3850 2950 3600 2950 +Wire Wire Line + 3850 3250 3350 3250 +Wire Wire Line + 3600 2950 3600 3000 +Wire Wire Line + 3600 3000 3350 3000 +Wire Wire Line + 3850 3350 3850 3400 +Wire Wire Line + 3850 3400 3350 3400 +Wire Wire Line + 5700 3100 6200 3100 +$Comp +L PORT U1 +U 1 1 5C9D01F4 +P 3100 2850 +F 0 "U1" H 3150 2950 30 0000 C CNN +F 1 "PORT" H 3100 2850 30 0000 C CNN +F 2 "" H 3100 2850 60 0000 C CNN +F 3 "" H 3100 2850 60 0000 C CNN + 1 3100 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9D022F +P 3100 3000 +F 0 "U1" H 3150 3100 30 0000 C CNN +F 1 "PORT" H 3100 3000 30 0000 C CNN +F 2 "" H 3100 3000 60 0000 C CNN +F 3 "" H 3100 3000 60 0000 C CNN + 2 3100 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9D0271 +P 3100 3250 +F 0 "U1" H 3150 3350 30 0000 C CNN +F 1 "PORT" H 3100 3250 30 0000 C CNN +F 2 "" H 3100 3250 60 0000 C CNN +F 3 "" H 3100 3250 60 0000 C CNN + 3 3100 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9D0299 +P 3100 3400 +F 0 "U1" H 3150 3500 30 0000 C CNN +F 1 "PORT" H 3100 3400 30 0000 C CNN +F 2 "" H 3100 3400 60 0000 C CNN +F 3 "" H 3100 3400 60 0000 C CNN + 4 3100 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9D02C2 +P 6450 3100 +F 0 "U1" H 6500 3200 30 0000 C CNN +F 1 "PORT" H 6450 3100 30 0000 C CNN +F 2 "" H 6450 3100 60 0000 C CNN +F 3 "" H 6450 3100 60 0000 C CNN + 5 6450 3100 + -1 0 0 1 +$EndComp +Text Notes 3450 2850 0 60 ~ 12 +in1 +Text Notes 3450 3000 0 60 ~ 12 +in2 +Text Notes 3450 3250 0 60 ~ 12 +in3 +Text Notes 3450 3400 0 60 ~ 12 +in4 +Text Notes 5800 3100 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74H55/4_OR.sub b/library/SubcircuitLibrary/SN74H55/4_OR.sub new file mode 100644 index 000000000..d1fd3a241 --- /dev/null +++ b/library/SubcircuitLibrary/SN74H55/4_OR.sub @@ -0,0 +1,18 @@ +* Subcircuit 4_OR +.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_OR \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74H55/4_OR_Previous_Values.xml b/library/SubcircuitLibrary/SN74H55/4_OR_Previous_Values.xml new file mode 100644 index 000000000..0683d9eb6 --- /dev/null +++ b/library/SubcircuitLibrary/SN74H55/4_OR_Previous_Values.xml @@ -0,0 +1 @@ +d_ord_ord_ortruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74H55/4_and-cache.lib b/library/SubcircuitLibrary/SN74H55/4_and-cache.lib new file mode 100644 index 000000000..60f1a83d4 --- /dev/null +++ b/library/SubcircuitLibrary/SN74H55/4_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74H55/4_and-rescue.lib b/library/SubcircuitLibrary/SN74H55/4_and-rescue.lib new file mode 100644 index 000000000..e38330518 --- /dev/null +++ b/library/SubcircuitLibrary/SN74H55/4_and-rescue.lib @@ -0,0 +1,22 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74H55/4_and.cir b/library/SubcircuitLibrary/SN74H55/4_and.cir new file mode 100644 index 000000000..fdf2e1074 --- /dev/null +++ b/library/SubcircuitLibrary/SN74H55/4_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and +U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74H55/4_and.cir.out b/library/SubcircuitLibrary/SN74H55/4_and.cir.out new file mode 100644 index 000000000..f40e5bc62 --- /dev/null +++ b/library/SubcircuitLibrary/SN74H55/4_and.cir.out @@ -0,0 +1,18 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74H55/4_and.pro b/library/SubcircuitLibrary/SN74H55/4_and.pro new file mode 100644 index 000000000..b13a0a825 --- /dev/null +++ b/library/SubcircuitLibrary/SN74H55/4_and.pro @@ -0,0 +1,57 @@ +update=Wed Mar 18 19:54:24 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=4_and-rescue +LibName2=texas +LibName3=intel +LibName4=audio +LibName5=interface +LibName6=digital-audio +LibName7=philips +LibName8=display +LibName9=cypress +LibName10=siliconi +LibName11=opto +LibName12=atmel +LibName13=contrib +LibName14=valves +LibName15=eSim_Analog +LibName16=eSim_Devices +LibName17=eSim_Digital +LibName18=eSim_Hybrid +LibName19=eSim_Miscellaneous +LibName20=eSim_Plot +LibName21=eSim_Power +LibName22=eSim_Sources +LibName23=eSim_Subckt +LibName24=eSim_User diff --git a/library/SubcircuitLibrary/SN74H55/4_and.sch b/library/SubcircuitLibrary/SN74H55/4_and.sch new file mode 100644 index 000000000..f5e8febdc --- /dev/null +++ b/library/SubcircuitLibrary/SN74H55/4_and.sch @@ -0,0 +1,151 @@ +EESchema Schematic File Version 2 +LIBS:4_and-rescue +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:4_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and-RESCUE-4_and X1 +U 1 1 5C9A2915 +P 3700 3500 +F 0 "X1" H 4600 3800 60 0000 C CNN +F 1 "3_and" H 4650 4000 60 0000 C CNN +F 2 "" H 3700 3500 60 0000 C CNN +F 3 "" H 3700 3500 60 0000 C CNN + 1 3700 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2940 +P 5450 3400 +F 0 "U2" H 5450 3400 60 0000 C CNN +F 1 "d_and" H 5500 3500 60 0000 C CNN +F 2 "" H 5450 3400 60 0000 C CNN +F 3 "" H 5450 3400 60 0000 C CNN + 1 5450 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 3100 5000 3300 +Wire Wire Line + 4150 3000 4150 2700 +Wire Wire Line + 4150 2700 3200 2700 +Wire Wire Line + 4150 3100 4000 3100 +Wire Wire Line + 4000 3100 4000 3000 +Wire Wire Line + 4000 3000 3200 3000 +Wire Wire Line + 4150 3200 4150 3300 +Wire Wire Line + 4150 3300 3250 3300 +Wire Wire Line + 5000 3400 5000 3550 +Wire Wire Line + 5000 3550 3250 3550 +Wire Wire Line + 5900 3350 6500 3350 +$Comp +L PORT U1 +U 1 1 5C9A29B1 +P 2950 2700 +F 0 "U1" H 3000 2800 30 0000 C CNN +F 1 "PORT" H 2950 2700 30 0000 C CNN +F 2 "" H 2950 2700 60 0000 C CNN +F 3 "" H 2950 2700 60 0000 C CNN + 1 2950 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A29E9 +P 2950 3000 +F 0 "U1" H 3000 3100 30 0000 C CNN +F 1 "PORT" H 2950 3000 30 0000 C CNN +F 2 "" H 2950 3000 60 0000 C CNN +F 3 "" H 2950 3000 60 0000 C CNN + 2 2950 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A2A0D +P 3000 3300 +F 0 "U1" H 3050 3400 30 0000 C CNN +F 1 "PORT" H 3000 3300 30 0000 C CNN +F 2 "" H 3000 3300 60 0000 C CNN +F 3 "" H 3000 3300 60 0000 C CNN + 3 3000 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2A3C +P 3000 3550 +F 0 "U1" H 3050 3650 30 0000 C CNN +F 1 "PORT" H 3000 3550 30 0000 C CNN +F 2 "" H 3000 3550 60 0000 C CNN +F 3 "" H 3000 3550 60 0000 C CNN + 4 3000 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2A68 +P 6750 3350 +F 0 "U1" H 6800 3450 30 0000 C CNN +F 1 "PORT" H 6750 3350 30 0000 C CNN +F 2 "" H 6750 3350 60 0000 C CNN +F 3 "" H 6750 3350 60 0000 C CNN + 5 6750 3350 + -1 0 0 1 +$EndComp +Text Notes 3450 2650 0 60 ~ 12 +in1 +Text Notes 3450 2950 0 60 ~ 12 +in2 +Text Notes 3500 3300 0 60 ~ 12 +in3 +Text Notes 3500 3550 0 60 ~ 12 +in4 +Text Notes 6150 3350 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74H55/4_and.sub b/library/SubcircuitLibrary/SN74H55/4_and.sub new file mode 100644 index 000000000..8663f37e6 --- /dev/null +++ b/library/SubcircuitLibrary/SN74H55/4_and.sub @@ -0,0 +1,12 @@ +* Subcircuit 4_and +.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74H55/4_and_Previous_Values.xml b/library/SubcircuitLibrary/SN74H55/4_and_Previous_Values.xml new file mode 100644 index 000000000..f2ba0130e --- /dev/null +++ b/library/SubcircuitLibrary/SN74H55/4_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andC:\Users\malli\eSim\src\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74H55/SN74H55-cache.lib b/library/SubcircuitLibrary/SN74H55/SN74H55-cache.lib new file mode 100644 index 000000000..4f81c933f --- /dev/null +++ b/library/SubcircuitLibrary/SN74H55/SN74H55-cache.lib @@ -0,0 +1,98 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 4_OR +# +DEF 4_OR X 0 40 Y Y 1 F N +F0 "X" 150 -100 60 H V C CNN +F1 "4_OR" 150 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250 +A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0 +A -30 -99 393 627 146 0 1 0 N 150 250 350 0 +P 2 0 1 0 -200 -250 150 -250 N +P 2 0 1 0 -200 250 150 250 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X in4 4 -350 -150 200 R 50 50 1 1 I +X out 5 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "4_and" 100 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 206 760 -760 0 1 0 N 150 200 150 -200 +P 2 0 1 0 -200 200 150 200 N +P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N +X in1 1 -400 150 200 R 50 50 1 1 I +X in2 2 -400 50 200 R 50 50 1 1 I +X in3 3 -400 -50 200 R 50 50 1 1 I +X in4 4 -400 -150 200 R 50 50 1 1 I +X out 5 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74H55/SN74H55.cir b/library/SubcircuitLibrary/SN74H55/SN74H55.cir new file mode 100644 index 000000000..d96c442f8 --- /dev/null +++ b/library/SubcircuitLibrary/SN74H55/SN74H55.cir @@ -0,0 +1,16 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\SN74H55\SN74H55.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/21/25 12:33:56 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U3-Pad1_ Net-_U3-Pad2_ Net-_U3-Pad3_ Net-_U3-Pad4_ Net-_X1-Pad5_ 4_and +X2 Net-_U3-Pad10_ Net-_U3-Pad11_ Net-_U3-Pad12_ Net-_U3-Pad13_ Net-_X2-Pad5_ 4_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ d_inverter +X3 Net-_X1-Pad5_ Net-_X2-Pad5_ Net-_U1-Pad2_ Net-_U3-Pad5_ Net-_U2-Pad1_ 4_OR +U2 Net-_U2-Pad1_ Net-_U2-Pad2_ d_inverter +U3 Net-_U3-Pad1_ Net-_U3-Pad2_ Net-_U3-Pad3_ Net-_U3-Pad4_ Net-_U3-Pad5_ ? ? Net-_U2-Pad2_ Net-_U1-Pad1_ Net-_U3-Pad10_ Net-_U3-Pad11_ Net-_U3-Pad12_ Net-_U3-Pad13_ ? PORT + +.end diff --git a/library/SubcircuitLibrary/SN74H55/SN74H55.cir.out b/library/SubcircuitLibrary/SN74H55/SN74H55.cir.out new file mode 100644 index 000000000..8f6ce3c98 --- /dev/null +++ b/library/SubcircuitLibrary/SN74H55/SN74H55.cir.out @@ -0,0 +1,25 @@ +* c:\fossee\esim\library\subcircuitlibrary\sn74h55\sn74h55.cir + +.include 4_and.sub +.include 4_OR.sub +x1 net-_u3-pad1_ net-_u3-pad2_ net-_u3-pad3_ net-_u3-pad4_ net-_x1-pad5_ 4_and +x2 net-_u3-pad10_ net-_u3-pad11_ net-_u3-pad12_ net-_u3-pad13_ net-_x2-pad5_ 4_and +* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter +x3 net-_x1-pad5_ net-_x2-pad5_ net-_u1-pad2_ net-_u3-pad5_ net-_u2-pad1_ 4_OR +* u2 net-_u2-pad1_ net-_u2-pad2_ d_inverter +* u3 net-_u3-pad1_ net-_u3-pad2_ net-_u3-pad3_ net-_u3-pad4_ net-_u3-pad5_ ? ? net-_u2-pad2_ net-_u1-pad1_ net-_u3-pad10_ net-_u3-pad11_ net-_u3-pad12_ net-_u3-pad13_ ? port +a1 net-_u1-pad1_ net-_u1-pad2_ u1 +a2 net-_u2-pad1_ net-_u2-pad2_ u2 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74H55/SN74H55.pro b/library/SubcircuitLibrary/SN74H55/SN74H55.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/SN74H55/SN74H55.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN74H55/SN74H55.sch b/library/SubcircuitLibrary/SN74H55/SN74H55.sch new file mode 100644 index 000000000..97032c503 --- /dev/null +++ b/library/SubcircuitLibrary/SN74H55/SN74H55.sch @@ -0,0 +1,321 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SN74H55-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 4_and X1 +U 1 1 68562EC6 +P 3500 2150 +F 0 "X1" H 3550 2100 60 0000 C CNN +F 1 "4_and" H 3600 2250 60 0000 C CNN +F 2 "" H 3500 2150 60 0000 C CNN +F 3 "" H 3500 2150 60 0000 C CNN + 1 3500 2150 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X2 +U 1 1 68562F0C +P 3500 2800 +F 0 "X2" H 3550 2750 60 0000 C CNN +F 1 "4_and" H 3600 2900 60 0000 C CNN +F 2 "" H 3500 2800 60 0000 C CNN +F 3 "" H 3500 2800 60 0000 C CNN + 1 3500 2800 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U1 +U 1 1 68564EC2 +P 4350 3350 +F 0 "U1" H 4350 3250 60 0000 C CNN +F 1 "d_inverter" H 4350 3500 60 0000 C CNN +F 2 "" H 4400 3300 60 0000 C CNN +F 3 "" H 4400 3300 60 0000 C CNN + 1 4350 3350 + 1 0 0 -1 +$EndComp +$Comp +L 4_OR X3 +U 1 1 68564F65 +P 5650 2450 +F 0 "X3" H 5800 2350 60 0000 C CNN +F 1 "4_OR" H 5800 2550 60 0000 C CNN +F 2 "" H 5650 2450 60 0000 C CNN +F 3 "" H 5650 2450 60 0000 C CNN + 1 5650 2450 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 68564FFE +P 6700 2450 +F 0 "U2" H 6700 2350 60 0000 C CNN +F 1 "d_inverter" H 6700 2600 60 0000 C CNN +F 2 "" H 6750 2400 60 0000 C CNN +F 3 "" H 6750 2400 60 0000 C CNN + 1 6700 2450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4000 2150 5300 2150 +Wire Wire Line + 5300 2150 5300 2300 +Wire Wire Line + 4000 2800 4100 2800 +Wire Wire Line + 4100 2800 4100 2400 +Wire Wire Line + 4100 2400 5300 2400 +Wire Wire Line + 4650 3350 4650 2500 +Wire Wire Line + 4650 2500 5300 2500 +Wire Wire Line + 6200 2450 6400 2450 +$Comp +L PORT U3 +U 1 1 68565099 +P 2750 1900 +F 0 "U3" H 2800 2000 30 0000 C CNN +F 1 "PORT" H 2750 1900 30 0000 C CNN +F 2 "" H 2750 1900 60 0000 C CNN +F 3 "" H 2750 1900 60 0000 C CNN + 1 2750 1900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U3 +U 2 1 685650DA +P 2750 2050 +F 0 "U3" H 2800 2150 30 0000 C CNN +F 1 "PORT" H 2750 2050 30 0000 C CNN +F 2 "" H 2750 2050 60 0000 C CNN +F 3 "" H 2750 2050 60 0000 C CNN + 2 2750 2050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U3 +U 3 1 6856510D +P 2750 2200 +F 0 "U3" H 2800 2300 30 0000 C CNN +F 1 "PORT" H 2750 2200 30 0000 C CNN +F 2 "" H 2750 2200 60 0000 C CNN +F 3 "" H 2750 2200 60 0000 C CNN + 3 2750 2200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U3 +U 4 1 68565142 +P 2750 2350 +F 0 "U3" H 2800 2450 30 0000 C CNN +F 1 "PORT" H 2750 2350 30 0000 C CNN +F 2 "" H 2750 2350 60 0000 C CNN +F 3 "" H 2750 2350 60 0000 C CNN + 4 2750 2350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U3 +U 5 1 68565169 +P 2650 3750 +F 0 "U3" H 2700 3850 30 0000 C CNN +F 1 "PORT" H 2650 3750 30 0000 C CNN +F 2 "" H 2650 3750 60 0000 C CNN +F 3 "" H 2650 3750 60 0000 C CNN + 5 2650 3750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U3 +U 6 1 68565192 +P 6200 1400 +F 0 "U3" H 6250 1500 30 0000 C CNN +F 1 "PORT" H 6200 1400 30 0000 C CNN +F 2 "" H 6200 1400 60 0000 C CNN +F 3 "" H 6200 1400 60 0000 C CNN + 6 6200 1400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U3 +U 7 1 685651BD +P 6200 1550 +F 0 "U3" H 6250 1650 30 0000 C CNN +F 1 "PORT" H 6200 1550 30 0000 C CNN +F 2 "" H 6200 1550 60 0000 C CNN +F 3 "" H 6200 1550 60 0000 C CNN + 7 6200 1550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U3 +U 8 1 685651EE +P 7500 2450 +F 0 "U3" H 7550 2550 30 0000 C CNN +F 1 "PORT" H 7500 2450 30 0000 C CNN +F 2 "" H 7500 2450 60 0000 C CNN +F 3 "" H 7500 2450 60 0000 C CNN + 8 7500 2450 + -1 0 0 1 +$EndComp +$Comp +L PORT U3 +U 9 1 6856521D +P 2650 3350 +F 0 "U3" H 2700 3450 30 0000 C CNN +F 1 "PORT" H 2650 3350 30 0000 C CNN +F 2 "" H 2650 3350 60 0000 C CNN +F 3 "" H 2650 3350 60 0000 C CNN + 9 2650 3350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U3 +U 10 1 6856524E +P 2750 2600 +F 0 "U3" H 2800 2700 30 0000 C CNN +F 1 "PORT" H 2750 2600 30 0000 C CNN +F 2 "" H 2750 2600 60 0000 C CNN +F 3 "" H 2750 2600 60 0000 C CNN + 10 2750 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U3 +U 11 1 68565283 +P 2750 2750 +F 0 "U3" H 2800 2850 30 0000 C CNN +F 1 "PORT" H 2750 2750 30 0000 C CNN +F 2 "" H 2750 2750 60 0000 C CNN +F 3 "" H 2750 2750 60 0000 C CNN + 11 2750 2750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U3 +U 12 1 685652B8 +P 2750 2900 +F 0 "U3" H 2800 3000 30 0000 C CNN +F 1 "PORT" H 2750 2900 30 0000 C CNN +F 2 "" H 2750 2900 60 0000 C CNN +F 3 "" H 2750 2900 60 0000 C CNN + 12 2750 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U3 +U 13 1 685652EF +P 2750 3050 +F 0 "U3" H 2800 3150 30 0000 C CNN +F 1 "PORT" H 2750 3050 30 0000 C CNN +F 2 "" H 2750 3050 60 0000 C CNN +F 3 "" H 2750 3050 60 0000 C CNN + 13 2750 3050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U3 +U 14 1 68565328 +P 6200 1750 +F 0 "U3" H 6250 1850 30 0000 C CNN +F 1 "PORT" H 6200 1750 30 0000 C CNN +F 2 "" H 6200 1750 60 0000 C CNN +F 3 "" H 6200 1750 60 0000 C CNN + 14 6200 1750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3000 1900 3100 1900 +Wire Wire Line + 3100 1900 3100 2000 +Wire Wire Line + 3000 2050 3100 2050 +Wire Wire Line + 3100 2050 3100 2100 +Wire Wire Line + 3000 2200 3100 2200 +Wire Wire Line + 3000 2350 3100 2350 +Wire Wire Line + 3100 2350 3100 2300 +Wire Wire Line + 3000 2600 3100 2600 +Wire Wire Line + 3100 2600 3100 2650 +Wire Wire Line + 3000 2750 3100 2750 +Wire Wire Line + 3000 2900 3100 2900 +Wire Wire Line + 3100 2900 3100 2850 +Wire Wire Line + 3000 3050 3100 3050 +Wire Wire Line + 3100 3050 3100 2950 +Wire Wire Line + 2900 3350 4050 3350 +Wire Wire Line + 2900 3750 5300 3750 +Wire Wire Line + 5300 3750 5300 2600 +Wire Wire Line + 7000 2450 7250 2450 +NoConn ~ 6450 1400 +NoConn ~ 6450 1550 +NoConn ~ 6450 1750 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74H55/SN74H55.sub b/library/SubcircuitLibrary/SN74H55/SN74H55.sub new file mode 100644 index 000000000..4ed992ac9 --- /dev/null +++ b/library/SubcircuitLibrary/SN74H55/SN74H55.sub @@ -0,0 +1,19 @@ +* Subcircuit SN74H55 +.subckt SN74H55 net-_u3-pad1_ net-_u3-pad2_ net-_u3-pad3_ net-_u3-pad4_ net-_u3-pad5_ ? ? net-_u2-pad2_ net-_u1-pad1_ net-_u3-pad10_ net-_u3-pad11_ net-_u3-pad12_ net-_u3-pad13_ ? +* c:\fossee\esim\library\subcircuitlibrary\sn74h55\sn74h55.cir +.include 4_and.sub +.include 4_OR.sub +x1 net-_u3-pad1_ net-_u3-pad2_ net-_u3-pad3_ net-_u3-pad4_ net-_x1-pad5_ 4_and +x2 net-_u3-pad10_ net-_u3-pad11_ net-_u3-pad12_ net-_u3-pad13_ net-_x2-pad5_ 4_and +* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter +x3 net-_x1-pad5_ net-_x2-pad5_ net-_u1-pad2_ net-_u3-pad5_ net-_u2-pad1_ 4_OR +* u2 net-_u2-pad1_ net-_u2-pad2_ d_inverter +a1 net-_u1-pad1_ net-_u1-pad2_ u1 +a2 net-_u2-pad1_ net-_u2-pad2_ u2 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SN74H55 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74H55/SN74H55_Previous_Values.xml b/library/SubcircuitLibrary/SN74H55/SN74H55_Previous_Values.xml new file mode 100644 index 000000000..413fe74ed --- /dev/null +++ b/library/SubcircuitLibrary/SN74H55/SN74H55_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_inverterd_inverterC:\FOSSEE\eSim\library\SubcircuitLibrary\4_andC:\FOSSEE\eSim\library\SubcircuitLibrary\4_andC:\FOSSEE\eSim\library\SubcircuitLibrary\4_OR \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74H55/analysis b/library/SubcircuitLibrary/SN74H55/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/SN74H55/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74H60/D.lib b/library/SubcircuitLibrary/SN74H60/D.lib new file mode 100644 index 000000000..f53bf3e03 --- /dev/null +++ b/library/SubcircuitLibrary/SN74H60/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/SN74H60/NPN.lib b/library/SubcircuitLibrary/SN74H60/NPN.lib new file mode 100644 index 000000000..be5f3073a --- /dev/null +++ b/library/SubcircuitLibrary/SN74H60/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/SN74H60/SN74H60-cache.lib b/library/SubcircuitLibrary/SN74H60/SN74H60-cache.lib new file mode 100644 index 000000000..416a996bf --- /dev/null +++ b/library/SubcircuitLibrary/SN74H60/SN74H60-cache.lib @@ -0,0 +1,75 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74H60/SN74H60.cir b/library/SubcircuitLibrary/SN74H60/SN74H60.cir new file mode 100644 index 000000000..b30b7877f --- /dev/null +++ b/library/SubcircuitLibrary/SN74H60/SN74H60.cir @@ -0,0 +1,19 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\SN74H60\SN74H60.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/19/25 15:54:11 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ d_and +U2 Net-_U2-Pad1_ Net-_U2-Pad2_ Net-_U2-Pad3_ d_and +U5 Net-_U1-Pad3_ Net-_U2-Pad3_ Net-_U5-Pad3_ d_and +U3 Net-_U3-Pad1_ Net-_U3-Pad2_ Net-_U3-Pad3_ d_and +U4 Net-_U4-Pad1_ Net-_U4-Pad2_ Net-_U4-Pad3_ d_and +U6 Net-_U3-Pad3_ Net-_U4-Pad3_ Net-_U6-Pad3_ d_and +U7 Net-_U5-Pad3_ Net-_U7-Pad2_ d_inverter +U8 Net-_U6-Pad3_ Net-_U8-Pad2_ d_inverter +U9 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad1_ Net-_U3-Pad1_ Net-_U3-Pad2_ Net-_U4-Pad1_ ? Net-_U4-Pad2_ Net-_U8-Pad2_ Net-_U6-Pad3_ Net-_U5-Pad3_ Net-_U7-Pad2_ Net-_U2-Pad2_ ? PORT + +.end diff --git a/library/SubcircuitLibrary/SN74H60/SN74H60.cir.out b/library/SubcircuitLibrary/SN74H60/SN74H60.cir.out new file mode 100644 index 000000000..fc86579c9 --- /dev/null +++ b/library/SubcircuitLibrary/SN74H60/SN74H60.cir.out @@ -0,0 +1,44 @@ +* c:\fossee\esim\library\subcircuitlibrary\sn74h60\sn74h60.cir + +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_and +* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ d_and +* u5 net-_u1-pad3_ net-_u2-pad3_ net-_u5-pad3_ d_and +* u3 net-_u3-pad1_ net-_u3-pad2_ net-_u3-pad3_ d_and +* u4 net-_u4-pad1_ net-_u4-pad2_ net-_u4-pad3_ d_and +* u6 net-_u3-pad3_ net-_u4-pad3_ net-_u6-pad3_ d_and +* u7 net-_u5-pad3_ net-_u7-pad2_ d_inverter +* u8 net-_u6-pad3_ net-_u8-pad2_ d_inverter +* u9 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad1_ net-_u3-pad1_ net-_u3-pad2_ net-_u4-pad1_ ? net-_u4-pad2_ net-_u8-pad2_ net-_u6-pad3_ net-_u5-pad3_ net-_u7-pad2_ net-_u2-pad2_ ? port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u1 +a2 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u2-pad3_ u2 +a3 [net-_u1-pad3_ net-_u2-pad3_ ] net-_u5-pad3_ u5 +a4 [net-_u3-pad1_ net-_u3-pad2_ ] net-_u3-pad3_ u3 +a5 [net-_u4-pad1_ net-_u4-pad2_ ] net-_u4-pad3_ u4 +a6 [net-_u3-pad3_ net-_u4-pad3_ ] net-_u6-pad3_ u6 +a7 net-_u5-pad3_ net-_u7-pad2_ u7 +a8 net-_u6-pad3_ net-_u8-pad2_ u8 +* Schematic Name: d_and, NgSpice Name: d_and +.model u1 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74H60/SN74H60.pro b/library/SubcircuitLibrary/SN74H60/SN74H60.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/SN74H60/SN74H60.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN74H60/SN74H60.sch b/library/SubcircuitLibrary/SN74H60/SN74H60.sch new file mode 100644 index 000000000..ae70d4fb5 --- /dev/null +++ b/library/SubcircuitLibrary/SN74H60/SN74H60.sch @@ -0,0 +1,361 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SN74H60-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U1 +U 1 1 6853E4C9 +P 3700 2150 +F 0 "U1" H 3700 2150 60 0000 C CNN +F 1 "d_and" H 3750 2250 60 0000 C CNN +F 2 "" H 3700 2150 60 0000 C CNN +F 3 "" H 3700 2150 60 0000 C CNN + 1 3700 2150 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 6853E52B +P 3700 2550 +F 0 "U2" H 3700 2550 60 0000 C CNN +F 1 "d_and" H 3750 2650 60 0000 C CNN +F 2 "" H 3700 2550 60 0000 C CNN +F 3 "" H 3700 2550 60 0000 C CNN + 1 3700 2550 + 1 0 0 -1 +$EndComp +$Comp +L d_and U5 +U 1 1 6853E555 +P 4950 2300 +F 0 "U5" H 4950 2300 60 0000 C CNN +F 1 "d_and" H 5000 2400 60 0000 C CNN +F 2 "" H 4950 2300 60 0000 C CNN +F 3 "" H 4950 2300 60 0000 C CNN + 1 4950 2300 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 6853E5A0 +P 3700 3150 +F 0 "U3" H 3700 3150 60 0000 C CNN +F 1 "d_and" H 3750 3250 60 0000 C CNN +F 2 "" H 3700 3150 60 0000 C CNN +F 3 "" H 3700 3150 60 0000 C CNN + 1 3700 3150 + 1 0 0 -1 +$EndComp +$Comp +L d_and U4 +U 1 1 6853E620 +P 3700 3550 +F 0 "U4" H 3700 3550 60 0000 C CNN +F 1 "d_and" H 3750 3650 60 0000 C CNN +F 2 "" H 3700 3550 60 0000 C CNN +F 3 "" H 3700 3550 60 0000 C CNN + 1 3700 3550 + 1 0 0 -1 +$EndComp +$Comp +L d_and U6 +U 1 1 6853E64F +P 4950 3350 +F 0 "U6" H 4950 3350 60 0000 C CNN +F 1 "d_and" H 5000 3450 60 0000 C CNN +F 2 "" H 4950 3350 60 0000 C CNN +F 3 "" H 4950 3350 60 0000 C CNN + 1 4950 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 6853E855 +P 6050 2000 +F 0 "U7" H 6050 1900 60 0000 C CNN +F 1 "d_inverter" H 6050 2150 60 0000 C CNN +F 2 "" H 6100 1950 60 0000 C CNN +F 3 "" H 6100 1950 60 0000 C CNN + 1 6050 2000 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U8 +U 1 1 6853E88B +P 6050 3050 +F 0 "U8" H 6050 2950 60 0000 C CNN +F 1 "d_inverter" H 6050 3200 60 0000 C CNN +F 2 "" H 6100 3000 60 0000 C CNN +F 3 "" H 6100 3000 60 0000 C CNN + 1 6050 3050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4150 2100 4500 2100 +Wire Wire Line + 4500 2100 4500 2200 +Wire Wire Line + 4150 2500 4500 2500 +Wire Wire Line + 4500 2500 4500 2300 +Wire Wire Line + 4150 3100 4500 3100 +Wire Wire Line + 4500 3100 4500 3250 +Wire Wire Line + 4150 3500 4500 3500 +Wire Wire Line + 4500 3500 4500 3350 +Wire Wire Line + 5400 2250 6800 2250 +Wire Wire Line + 5450 2250 5450 2000 +Wire Wire Line + 5450 2000 5750 2000 +$Comp +L PORT U9 +U 1 1 6853ECEA +P 2850 2050 +F 0 "U9" H 2900 2150 30 0000 C CNN +F 1 "PORT" H 2850 2050 30 0000 C CNN +F 2 "" H 2850 2050 60 0000 C CNN +F 3 "" H 2850 2050 60 0000 C CNN + 1 2850 2050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U9 +U 2 1 6853ED35 +P 2850 2200 +F 0 "U9" H 2900 2300 30 0000 C CNN +F 1 "PORT" H 2850 2200 30 0000 C CNN +F 2 "" H 2850 2200 60 0000 C CNN +F 3 "" H 2850 2200 60 0000 C CNN + 2 2850 2200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U9 +U 6 1 6853ED90 +P 2850 3400 +F 0 "U9" H 2900 3500 30 0000 C CNN +F 1 "PORT" H 2850 3400 30 0000 C CNN +F 2 "" H 2850 3400 60 0000 C CNN +F 3 "" H 2850 3400 60 0000 C CNN + 6 2850 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U9 +U 3 1 6853EDF0 +P 2850 2450 +F 0 "U9" H 2900 2550 30 0000 C CNN +F 1 "PORT" H 2850 2450 30 0000 C CNN +F 2 "" H 2850 2450 60 0000 C CNN +F 3 "" H 2850 2450 60 0000 C CNN + 3 2850 2450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U9 +U 7 1 6853EE21 +P 6800 1350 +F 0 "U9" H 6850 1450 30 0000 C CNN +F 1 "PORT" H 6800 1350 30 0000 C CNN +F 2 "" H 6800 1350 60 0000 C CNN +F 3 "" H 6800 1350 60 0000 C CNN + 7 6800 1350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U9 +U 8 1 6853EE50 +P 2850 3600 +F 0 "U9" H 2900 3700 30 0000 C CNN +F 1 "PORT" H 2850 3600 30 0000 C CNN +F 2 "" H 2850 3600 60 0000 C CNN +F 3 "" H 2850 3600 60 0000 C CNN + 8 2850 3600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U9 +U 9 1 6853EE81 +P 7050 3050 +F 0 "U9" H 7100 3150 30 0000 C CNN +F 1 "PORT" H 7050 3050 30 0000 C CNN +F 2 "" H 7050 3050 60 0000 C CNN +F 3 "" H 7050 3050 60 0000 C CNN + 9 7050 3050 + -1 0 0 1 +$EndComp +$Comp +L PORT U9 +U 4 1 6853EEB8 +P 2850 2950 +F 0 "U9" H 2900 3050 30 0000 C CNN +F 1 "PORT" H 2850 2950 30 0000 C CNN +F 2 "" H 2850 2950 60 0000 C CNN +F 3 "" H 2850 2950 60 0000 C CNN + 4 2850 2950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U9 +U 5 1 6853EF01 +P 2850 3150 +F 0 "U9" H 2900 3250 30 0000 C CNN +F 1 "PORT" H 2850 3150 30 0000 C CNN +F 2 "" H 2850 3150 60 0000 C CNN +F 3 "" H 2850 3150 60 0000 C CNN + 5 2850 3150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U9 +U 10 1 6853EF3C +P 7050 3300 +F 0 "U9" H 7100 3400 30 0000 C CNN +F 1 "PORT" H 7050 3300 30 0000 C CNN +F 2 "" H 7050 3300 60 0000 C CNN +F 3 "" H 7050 3300 60 0000 C CNN + 10 7050 3300 + -1 0 0 1 +$EndComp +$Comp +L PORT U9 +U 11 1 6853EF81 +P 7050 2250 +F 0 "U9" H 7100 2350 30 0000 C CNN +F 1 "PORT" H 7050 2250 30 0000 C CNN +F 2 "" H 7050 2250 60 0000 C CNN +F 3 "" H 7050 2250 60 0000 C CNN + 11 7050 2250 + -1 0 0 1 +$EndComp +$Comp +L PORT U9 +U 12 1 6853EFBC +P 7050 2000 +F 0 "U9" H 7100 2100 30 0000 C CNN +F 1 "PORT" H 7050 2000 30 0000 C CNN +F 2 "" H 7050 2000 60 0000 C CNN +F 3 "" H 7050 2000 60 0000 C CNN + 12 7050 2000 + -1 0 0 1 +$EndComp +$Comp +L PORT U9 +U 13 1 6853EFFD +P 2850 2600 +F 0 "U9" H 2900 2700 30 0000 C CNN +F 1 "PORT" H 2850 2600 30 0000 C CNN +F 2 "" H 2850 2600 60 0000 C CNN +F 3 "" H 2850 2600 60 0000 C CNN + 13 2850 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U9 +U 14 1 6853F046 +P 6800 1550 +F 0 "U9" H 6850 1650 30 0000 C CNN +F 1 "PORT" H 6800 1550 30 0000 C CNN +F 2 "" H 6800 1550 60 0000 C CNN +F 3 "" H 6800 1550 60 0000 C CNN + 14 6800 1550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6350 2000 6800 2000 +Connection ~ 5450 2250 +Wire Wire Line + 5400 3300 6800 3300 +Wire Wire Line + 6350 3050 6800 3050 +Wire Wire Line + 5750 3050 5450 3050 +Wire Wire Line + 5450 3050 5450 3300 +Connection ~ 5450 3300 +Wire Wire Line + 3100 2050 3250 2050 +Wire Wire Line + 3100 2200 3250 2200 +Wire Wire Line + 3250 2200 3250 2150 +Wire Wire Line + 3100 2450 3250 2450 +Wire Wire Line + 3100 2600 3250 2600 +Wire Wire Line + 3250 2600 3250 2550 +Wire Wire Line + 3100 2950 3250 2950 +Wire Wire Line + 3250 2950 3250 3050 +Wire Wire Line + 3100 3150 3250 3150 +Wire Wire Line + 3100 3400 3250 3400 +Wire Wire Line + 3250 3400 3250 3450 +Wire Wire Line + 3100 3600 3250 3600 +Wire Wire Line + 3250 3600 3250 3550 +NoConn ~ 7050 1350 +NoConn ~ 7050 1550 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74H60/SN74H60.sub b/library/SubcircuitLibrary/SN74H60/SN74H60.sub new file mode 100644 index 000000000..39700738f --- /dev/null +++ b/library/SubcircuitLibrary/SN74H60/SN74H60.sub @@ -0,0 +1,38 @@ +* Subcircuit SN74H60 +.subckt SN74H60 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad1_ net-_u3-pad1_ net-_u3-pad2_ net-_u4-pad1_ ? net-_u4-pad2_ net-_u8-pad2_ net-_u6-pad3_ net-_u5-pad3_ net-_u7-pad2_ net-_u2-pad2_ ? +* c:\fossee\esim\library\subcircuitlibrary\sn74h60\sn74h60.cir +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_and +* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ d_and +* u5 net-_u1-pad3_ net-_u2-pad3_ net-_u5-pad3_ d_and +* u3 net-_u3-pad1_ net-_u3-pad2_ net-_u3-pad3_ d_and +* u4 net-_u4-pad1_ net-_u4-pad2_ net-_u4-pad3_ d_and +* u6 net-_u3-pad3_ net-_u4-pad3_ net-_u6-pad3_ d_and +* u7 net-_u5-pad3_ net-_u7-pad2_ d_inverter +* u8 net-_u6-pad3_ net-_u8-pad2_ d_inverter +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u1 +a2 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u2-pad3_ u2 +a3 [net-_u1-pad3_ net-_u2-pad3_ ] net-_u5-pad3_ u5 +a4 [net-_u3-pad1_ net-_u3-pad2_ ] net-_u3-pad3_ u3 +a5 [net-_u4-pad1_ net-_u4-pad2_ ] net-_u4-pad3_ u4 +a6 [net-_u3-pad3_ net-_u4-pad3_ ] net-_u6-pad3_ u6 +a7 net-_u5-pad3_ net-_u7-pad2_ u7 +a8 net-_u6-pad3_ net-_u8-pad2_ u8 +* Schematic Name: d_and, NgSpice Name: d_and +.model u1 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SN74H60 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74H60/SN74H60_Previous_Values.xml b/library/SubcircuitLibrary/SN74H60/SN74H60_Previous_Values.xml new file mode 100644 index 000000000..e7374d7d6 --- /dev/null +++ b/library/SubcircuitLibrary/SN74H60/SN74H60_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andd_andd_andd_andd_andd_inverterd_invertertruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74H60/analysis b/library/SubcircuitLibrary/SN74H60/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/SN74H60/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74H62/3_and-cache.lib b/library/SubcircuitLibrary/SN74H62/3_and-cache.lib new file mode 100644 index 000000000..af0586415 --- /dev/null +++ b/library/SubcircuitLibrary/SN74H62/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74H62/3_and.cir b/library/SubcircuitLibrary/SN74H62/3_and.cir new file mode 100644 index 000000000..ba296cf01 --- /dev/null +++ b/library/SubcircuitLibrary/SN74H62/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74H62/3_and.cir.out b/library/SubcircuitLibrary/SN74H62/3_and.cir.out new file mode 100644 index 000000000..d7cf79a07 --- /dev/null +++ b/library/SubcircuitLibrary/SN74H62/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74H62/3_and.pro b/library/SubcircuitLibrary/SN74H62/3_and.pro new file mode 100644 index 000000000..00597a5ad --- /dev/null +++ b/library/SubcircuitLibrary/SN74H62/3_and.pro @@ -0,0 +1,43 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_User +LibName9=eSim_Sources +LibName10=eSim_Subckt diff --git a/library/SubcircuitLibrary/SN74H62/3_and.sch b/library/SubcircuitLibrary/SN74H62/3_and.sch new file mode 100644 index 000000000..d6ac89f95 --- /dev/null +++ b/library/SubcircuitLibrary/SN74H62/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74H62/3_and.sub b/library/SubcircuitLibrary/SN74H62/3_and.sub new file mode 100644 index 000000000..3d9120bb6 --- /dev/null +++ b/library/SubcircuitLibrary/SN74H62/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74H62/3_and_Previous_Values.xml b/library/SubcircuitLibrary/SN74H62/3_and_Previous_Values.xml new file mode 100644 index 000000000..abc5faaae --- /dev/null +++ b/library/SubcircuitLibrary/SN74H62/3_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74H62/4_OR-cache.lib b/library/SubcircuitLibrary/SN74H62/4_OR-cache.lib new file mode 100644 index 000000000..155f5e601 --- /dev/null +++ b/library/SubcircuitLibrary/SN74H62/4_OR-cache.lib @@ -0,0 +1,63 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74H62/4_OR.cir b/library/SubcircuitLibrary/SN74H62/4_OR.cir new file mode 100644 index 000000000..b338b7b5f --- /dev/null +++ b/library/SubcircuitLibrary/SN74H62/4_OR.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or +U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or +U4 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74H62/4_OR.cir.out b/library/SubcircuitLibrary/SN74H62/4_OR.cir.out new file mode 100644 index 000000000..adb6b01be --- /dev/null +++ b/library/SubcircuitLibrary/SN74H62/4_OR.cir.out @@ -0,0 +1,24 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74H62/4_OR.pro b/library/SubcircuitLibrary/SN74H62/4_OR.pro new file mode 100644 index 000000000..881563ebd --- /dev/null +++ b/library/SubcircuitLibrary/SN74H62/4_OR.pro @@ -0,0 +1,44 @@ +update=06/01/19 12:36:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_User +LibName10=eSim_Sources +LibName11=eSim_Subckt diff --git a/library/SubcircuitLibrary/SN74H62/4_OR.sch b/library/SubcircuitLibrary/SN74H62/4_OR.sch new file mode 100644 index 000000000..118968656 --- /dev/null +++ b/library/SubcircuitLibrary/SN74H62/4_OR.sch @@ -0,0 +1,150 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_or U2 +U 1 1 5C9D00E1 +P 4300 2950 +F 0 "U2" H 4300 2950 60 0000 C CNN +F 1 "d_or" H 4300 3050 60 0000 C CNN +F 2 "" H 4300 2950 60 0000 C CNN +F 3 "" H 4300 2950 60 0000 C CNN + 1 4300 2950 + 1 0 0 -1 +$EndComp +$Comp +L d_or U3 +U 1 1 5C9D011F +P 4300 3350 +F 0 "U3" H 4300 3350 60 0000 C CNN +F 1 "d_or" H 4300 3450 60 0000 C CNN +F 2 "" H 4300 3350 60 0000 C CNN +F 3 "" H 4300 3350 60 0000 C CNN + 1 4300 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_or U4 +U 1 1 5C9D0141 +P 5250 3150 +F 0 "U4" H 5250 3150 60 0000 C CNN +F 1 "d_or" H 5250 3250 60 0000 C CNN +F 2 "" H 5250 3150 60 0000 C CNN +F 3 "" H 5250 3150 60 0000 C CNN + 1 5250 3150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4800 3050 4800 2900 +Wire Wire Line + 4800 2900 4750 2900 +Wire Wire Line + 4800 3150 4800 3300 +Wire Wire Line + 4800 3300 4750 3300 +Wire Wire Line + 3350 2850 3850 2850 +Wire Wire Line + 3850 2950 3600 2950 +Wire Wire Line + 3850 3250 3350 3250 +Wire Wire Line + 3600 2950 3600 3000 +Wire Wire Line + 3600 3000 3350 3000 +Wire Wire Line + 3850 3350 3850 3400 +Wire Wire Line + 3850 3400 3350 3400 +Wire Wire Line + 5700 3100 6200 3100 +$Comp +L PORT U1 +U 1 1 5C9D01F4 +P 3100 2850 +F 0 "U1" H 3150 2950 30 0000 C CNN +F 1 "PORT" H 3100 2850 30 0000 C CNN +F 2 "" H 3100 2850 60 0000 C CNN +F 3 "" H 3100 2850 60 0000 C CNN + 1 3100 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9D022F +P 3100 3000 +F 0 "U1" H 3150 3100 30 0000 C CNN +F 1 "PORT" H 3100 3000 30 0000 C CNN +F 2 "" H 3100 3000 60 0000 C CNN +F 3 "" H 3100 3000 60 0000 C CNN + 2 3100 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9D0271 +P 3100 3250 +F 0 "U1" H 3150 3350 30 0000 C CNN +F 1 "PORT" H 3100 3250 30 0000 C CNN +F 2 "" H 3100 3250 60 0000 C CNN +F 3 "" H 3100 3250 60 0000 C CNN + 3 3100 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9D0299 +P 3100 3400 +F 0 "U1" H 3150 3500 30 0000 C CNN +F 1 "PORT" H 3100 3400 30 0000 C CNN +F 2 "" H 3100 3400 60 0000 C CNN +F 3 "" H 3100 3400 60 0000 C CNN + 4 3100 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9D02C2 +P 6450 3100 +F 0 "U1" H 6500 3200 30 0000 C CNN +F 1 "PORT" H 6450 3100 30 0000 C CNN +F 2 "" H 6450 3100 60 0000 C CNN +F 3 "" H 6450 3100 60 0000 C CNN + 5 6450 3100 + -1 0 0 1 +$EndComp +Text Notes 3450 2850 0 60 ~ 12 +in1 +Text Notes 3450 3000 0 60 ~ 12 +in2 +Text Notes 3450 3250 0 60 ~ 12 +in3 +Text Notes 3450 3400 0 60 ~ 12 +in4 +Text Notes 5800 3100 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74H62/4_OR.sub b/library/SubcircuitLibrary/SN74H62/4_OR.sub new file mode 100644 index 000000000..d1fd3a241 --- /dev/null +++ b/library/SubcircuitLibrary/SN74H62/4_OR.sub @@ -0,0 +1,18 @@ +* Subcircuit 4_OR +.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_OR \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74H62/4_OR_Previous_Values.xml b/library/SubcircuitLibrary/SN74H62/4_OR_Previous_Values.xml new file mode 100644 index 000000000..0683d9eb6 --- /dev/null +++ b/library/SubcircuitLibrary/SN74H62/4_OR_Previous_Values.xml @@ -0,0 +1 @@ +d_ord_ord_ortruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74H62/SN74H62-cache.lib b/library/SubcircuitLibrary/SN74H62/SN74H62-cache.lib new file mode 100644 index 000000000..6bcc31039 --- /dev/null +++ b/library/SubcircuitLibrary/SN74H62/SN74H62-cache.lib @@ -0,0 +1,114 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_OR +# +DEF 4_OR X 0 40 Y Y 1 F N +F0 "X" 150 -100 60 H V C CNN +F1 "4_OR" 150 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250 +A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0 +A -30 -99 393 627 146 0 1 0 N 150 250 350 0 +P 2 0 1 0 -200 -250 150 -250 N +P 2 0 1 0 -200 250 150 250 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X in4 4 -350 -150 200 R 50 50 1 1 I +X out 5 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74H62/SN74H62.cir b/library/SubcircuitLibrary/SN74H62/SN74H62.cir new file mode 100644 index 000000000..40559961b --- /dev/null +++ b/library/SubcircuitLibrary/SN74H62/SN74H62.cir @@ -0,0 +1,17 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\SN74H62\SN74H62.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/10/25 11:11:56 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ d_and +X1 Net-_U3-Pad3_ Net-_U3-Pad4_ Net-_U3-Pad5_ Net-_X1-Pad4_ 3_and +X2 Net-_U3-Pad9_ Net-_U3-Pad10_ Net-_U3-Pad11_ Net-_X2-Pad4_ 3_and +U2 Net-_U2-Pad1_ Net-_U2-Pad2_ Net-_U2-Pad3_ d_and +X3 Net-_U1-Pad3_ Net-_X1-Pad4_ Net-_X2-Pad4_ Net-_U2-Pad3_ Net-_U3-Pad8_ 4_OR +U4 Net-_U3-Pad8_ Net-_U3-Pad6_ d_inverter +U3 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U3-Pad3_ Net-_U3-Pad4_ Net-_U3-Pad5_ Net-_U3-Pad6_ ? Net-_U3-Pad8_ Net-_U3-Pad9_ Net-_U3-Pad10_ Net-_U3-Pad11_ Net-_U2-Pad1_ Net-_U2-Pad2_ ? PORT + +.end diff --git a/library/SubcircuitLibrary/SN74H62/SN74H62.cir.out b/library/SubcircuitLibrary/SN74H62/SN74H62.cir.out new file mode 100644 index 000000000..211568255 --- /dev/null +++ b/library/SubcircuitLibrary/SN74H62/SN74H62.cir.out @@ -0,0 +1,29 @@ +* c:\fossee\esim\library\subcircuitlibrary\sn74h62\sn74h62.cir + +.include 3_and.sub +.include 4_OR.sub +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_and +x1 net-_u3-pad3_ net-_u3-pad4_ net-_u3-pad5_ net-_x1-pad4_ 3_and +x2 net-_u3-pad9_ net-_u3-pad10_ net-_u3-pad11_ net-_x2-pad4_ 3_and +* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ d_and +x3 net-_u1-pad3_ net-_x1-pad4_ net-_x2-pad4_ net-_u2-pad3_ net-_u3-pad8_ 4_OR +* u4 net-_u3-pad8_ net-_u3-pad6_ d_inverter +* u3 net-_u1-pad1_ net-_u1-pad2_ net-_u3-pad3_ net-_u3-pad4_ net-_u3-pad5_ net-_u3-pad6_ ? net-_u3-pad8_ net-_u3-pad9_ net-_u3-pad10_ net-_u3-pad11_ net-_u2-pad1_ net-_u2-pad2_ ? port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u1 +a2 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u2-pad3_ u2 +a3 net-_u3-pad8_ net-_u3-pad6_ u4 +* Schematic Name: d_and, NgSpice Name: d_and +.model u1 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74H62/SN74H62.pro b/library/SubcircuitLibrary/SN74H62/SN74H62.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/SN74H62/SN74H62.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN74H62/SN74H62.sch b/library/SubcircuitLibrary/SN74H62/SN74H62.sch new file mode 100644 index 000000000..8bf0f1f0c --- /dev/null +++ b/library/SubcircuitLibrary/SN74H62/SN74H62.sch @@ -0,0 +1,337 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U1 +U 1 1 6847C3ED +P 4700 2750 +F 0 "U1" H 4700 2750 60 0000 C CNN +F 1 "d_and" H 4750 2850 60 0000 C CNN +F 2 "" H 4700 2750 60 0000 C CNN +F 3 "" H 4700 2750 60 0000 C CNN + 1 4700 2750 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X1 +U 1 1 6847C42C +P 4600 3150 +F 0 "X1" H 4700 3100 60 0000 C CNN +F 1 "3_and" H 4750 3300 60 0000 C CNN +F 2 "" H 4600 3150 60 0000 C CNN +F 3 "" H 4600 3150 60 0000 C CNN + 1 4600 3150 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X2 +U 1 1 6847C45F +P 4600 3550 +F 0 "X2" H 4700 3500 60 0000 C CNN +F 1 "3_and" H 4750 3700 60 0000 C CNN +F 2 "" H 4600 3550 60 0000 C CNN +F 3 "" H 4600 3550 60 0000 C CNN + 1 4600 3550 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 6847C490 +P 4700 3900 +F 0 "U2" H 4700 3900 60 0000 C CNN +F 1 "d_and" H 4750 4000 60 0000 C CNN +F 2 "" H 4700 3900 60 0000 C CNN +F 3 "" H 4700 3900 60 0000 C CNN + 1 4700 3900 + 1 0 0 -1 +$EndComp +$Comp +L 4_OR X3 +U 1 1 6847C4C2 +P 5800 3200 +F 0 "X3" H 5950 3100 60 0000 C CNN +F 1 "4_OR" H 5950 3300 60 0000 C CNN +F 2 "" H 5800 3200 60 0000 C CNN +F 3 "" H 5800 3200 60 0000 C CNN + 1 5800 3200 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 6847C4F1 +P 6950 2850 +F 0 "U4" H 6950 2750 60 0000 C CNN +F 1 "d_inverter" H 6950 3000 60 0000 C CNN +F 2 "" H 7000 2800 60 0000 C CNN +F 3 "" H 7000 2800 60 0000 C CNN + 1 6950 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U3 +U 2 1 6847C51A +P 3800 2800 +F 0 "U3" H 3850 2900 30 0000 C CNN +F 1 "PORT" H 3800 2800 30 0000 C CNN +F 2 "" H 3800 2800 60 0000 C CNN +F 3 "" H 3800 2800 60 0000 C CNN + 2 3800 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U3 +U 3 1 6847C579 +P 3800 2950 +F 0 "U3" H 3850 3050 30 0000 C CNN +F 1 "PORT" H 3800 2950 30 0000 C CNN +F 2 "" H 3800 2950 60 0000 C CNN +F 3 "" H 3800 2950 60 0000 C CNN + 3 3800 2950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U3 +U 1 1 6847C59E +P 3800 2650 +F 0 "U3" H 3850 2750 30 0000 C CNN +F 1 "PORT" H 3800 2650 30 0000 C CNN +F 2 "" H 3800 2650 60 0000 C CNN +F 3 "" H 3800 2650 60 0000 C CNN + 1 3800 2650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U3 +U 4 1 6847C5C7 +P 3800 3100 +F 0 "U3" H 3850 3200 30 0000 C CNN +F 1 "PORT" H 3800 3100 30 0000 C CNN +F 2 "" H 3800 3100 60 0000 C CNN +F 3 "" H 3800 3100 60 0000 C CNN + 4 3800 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U3 +U 5 1 6847C5F0 +P 3800 3250 +F 0 "U3" H 3850 3350 30 0000 C CNN +F 1 "PORT" H 3800 3250 30 0000 C CNN +F 2 "" H 3800 3250 60 0000 C CNN +F 3 "" H 3800 3250 60 0000 C CNN + 5 3800 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U3 +U 6 1 6847C61B +P 7700 2850 +F 0 "U3" H 7750 2950 30 0000 C CNN +F 1 "PORT" H 7700 2850 30 0000 C CNN +F 2 "" H 7700 2850 60 0000 C CNN +F 3 "" H 7700 2850 60 0000 C CNN + 6 7700 2850 + -1 0 0 1 +$EndComp +$Comp +L PORT U3 +U 7 1 6847C648 +P 6000 2450 +F 0 "U3" H 6050 2550 30 0000 C CNN +F 1 "PORT" H 6000 2450 30 0000 C CNN +F 2 "" H 6000 2450 60 0000 C CNN +F 3 "" H 6000 2450 60 0000 C CNN + 7 6000 2450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U3 +U 8 1 6847C677 +P 7700 3200 +F 0 "U3" H 7750 3300 30 0000 C CNN +F 1 "PORT" H 7700 3200 30 0000 C CNN +F 2 "" H 7700 3200 60 0000 C CNN +F 3 "" H 7700 3200 60 0000 C CNN + 8 7700 3200 + -1 0 0 1 +$EndComp +$Comp +L PORT U3 +U 9 1 6847C6A8 +P 3800 3400 +F 0 "U3" H 3850 3500 30 0000 C CNN +F 1 "PORT" H 3800 3400 30 0000 C CNN +F 2 "" H 3800 3400 60 0000 C CNN +F 3 "" H 3800 3400 60 0000 C CNN + 9 3800 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U3 +U 10 1 6847C6DB +P 3800 3550 +F 0 "U3" H 3850 3650 30 0000 C CNN +F 1 "PORT" H 3800 3550 30 0000 C CNN +F 2 "" H 3800 3550 60 0000 C CNN +F 3 "" H 3800 3550 60 0000 C CNN + 10 3800 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U3 +U 11 1 6847C710 +P 3800 3700 +F 0 "U3" H 3850 3800 30 0000 C CNN +F 1 "PORT" H 3800 3700 30 0000 C CNN +F 2 "" H 3800 3700 60 0000 C CNN +F 3 "" H 3800 3700 60 0000 C CNN + 11 3800 3700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U3 +U 12 1 6847C747 +P 3800 3850 +F 0 "U3" H 3850 3950 30 0000 C CNN +F 1 "PORT" H 3800 3850 30 0000 C CNN +F 2 "" H 3800 3850 60 0000 C CNN +F 3 "" H 3800 3850 60 0000 C CNN + 12 3800 3850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U3 +U 13 1 6847C780 +P 3800 4000 +F 0 "U3" H 3850 4100 30 0000 C CNN +F 1 "PORT" H 3800 4000 30 0000 C CNN +F 2 "" H 3800 4000 60 0000 C CNN +F 3 "" H 3800 4000 60 0000 C CNN + 13 3800 4000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U3 +U 14 1 6847C7BB +P 6000 2600 +F 0 "U3" H 6050 2700 30 0000 C CNN +F 1 "PORT" H 6000 2600 30 0000 C CNN +F 2 "" H 6000 2600 60 0000 C CNN +F 3 "" H 6000 2600 60 0000 C CNN + 14 6000 2600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5150 2700 5450 2700 +Wire Wire Line + 5450 2700 5450 3050 +Wire Wire Line + 5100 3100 5450 3100 +Wire Wire Line + 5450 3100 5450 3150 +Wire Wire Line + 5100 3500 5100 3250 +Wire Wire Line + 5100 3250 5450 3250 +Wire Wire Line + 5150 3850 5450 3850 +Wire Wire Line + 5450 3850 5450 3350 +Wire Wire Line + 4050 2650 4250 2650 +Wire Wire Line + 4050 2800 4250 2800 +Wire Wire Line + 4250 2800 4250 2750 +Wire Wire Line + 4050 2950 4250 2950 +Wire Wire Line + 4250 2950 4250 3000 +Wire Wire Line + 4050 3100 4250 3100 +Wire Wire Line + 4050 3250 4250 3250 +Wire Wire Line + 4250 3250 4250 3200 +Wire Wire Line + 4050 3400 4250 3400 +Wire Wire Line + 4050 3550 4250 3550 +Wire Wire Line + 4250 3550 4250 3500 +Wire Wire Line + 4050 3700 4250 3700 +Wire Wire Line + 4250 3700 4250 3600 +Wire Wire Line + 4050 3850 4050 3800 +Wire Wire Line + 4050 3800 4250 3800 +Wire Wire Line + 4050 4000 4250 4000 +Wire Wire Line + 4250 4000 4250 3900 +Wire Wire Line + 6350 3200 7450 3200 +Wire Wire Line + 6650 2850 6550 2850 +Wire Wire Line + 6550 2850 6550 3200 +Connection ~ 6550 3200 +NoConn ~ 6250 2450 +NoConn ~ 6250 2600 +Wire Wire Line + 7250 2850 7450 2850 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74H62/SN74H62.sub b/library/SubcircuitLibrary/SN74H62/SN74H62.sub new file mode 100644 index 000000000..949abe968 --- /dev/null +++ b/library/SubcircuitLibrary/SN74H62/SN74H62.sub @@ -0,0 +1,23 @@ +* Subcircuit SN74H62 +.subckt SN74H62 net-_u1-pad1_ net-_u1-pad2_ net-_u3-pad3_ net-_u3-pad4_ net-_u3-pad5_ net-_u3-pad6_ ? net-_u3-pad8_ net-_u3-pad9_ net-_u3-pad10_ net-_u3-pad11_ net-_u2-pad1_ net-_u2-pad2_ ? +* c:\fossee\esim\library\subcircuitlibrary\sn74h62\sn74h62.cir +.include 3_and.sub +.include 4_OR.sub +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_and +x1 net-_u3-pad3_ net-_u3-pad4_ net-_u3-pad5_ net-_x1-pad4_ 3_and +x2 net-_u3-pad9_ net-_u3-pad10_ net-_u3-pad11_ net-_x2-pad4_ 3_and +* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ d_and +x3 net-_u1-pad3_ net-_x1-pad4_ net-_x2-pad4_ net-_u2-pad3_ net-_u3-pad8_ 4_OR +* u4 net-_u3-pad8_ net-_u3-pad6_ d_inverter +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u1 +a2 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u2-pad3_ u2 +a3 net-_u3-pad8_ net-_u3-pad6_ u4 +* Schematic Name: d_and, NgSpice Name: d_and +.model u1 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SN74H62 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74H62/SN74H62_Previous_Values.xml b/library/SubcircuitLibrary/SN74H62/SN74H62_Previous_Values.xml new file mode 100644 index 000000000..dda622bc6 --- /dev/null +++ b/library/SubcircuitLibrary/SN74H62/SN74H62_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andd_inverterC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\4_ORtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74H62/analysis b/library/SubcircuitLibrary/SN74H62/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/SN74H62/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file