From 1503279908c46296876cf262ae3aeee1a0b50a75 Mon Sep 17 00:00:00 2001 From: Annesha Dey <142687349+AD20047@users.noreply.github.com> Date: Fri, 11 Jul 2025 23:29:58 +0530 Subject: [PATCH 1/9] Instrumentation Amplifier --- library/SubcircuitLibrary/AD623/analysis | 1 + 1 file changed, 1 insertion(+) create mode 100644 library/SubcircuitLibrary/AD623/analysis diff --git a/library/SubcircuitLibrary/AD623/analysis b/library/SubcircuitLibrary/AD623/analysis new file mode 100644 index 000000000..f6e0de997 --- /dev/null +++ b/library/SubcircuitLibrary/AD623/analysis @@ -0,0 +1 @@ +.tran 1e-06 1000e-06 0e-06 From 7155261cf2fe05365592a0b6abac8440cb0dc12b Mon Sep 17 00:00:00 2001 From: Annesha Dey <142687349+AD20047@users.noreply.github.com> Date: Fri, 11 Jul 2025 23:31:46 +0530 Subject: [PATCH 2/9] Instrumentation Amplifier --- library/SubcircuitLibrary/AD623/NPN.lib | 4 + library/SubcircuitLibrary/AD623/PNP.lib | 4 + .../AD623/SC_AD623-cache.lib | 153 ++++++ library/SubcircuitLibrary/AD623/SC_AD623.cir | 30 ++ .../SubcircuitLibrary/AD623/SC_AD623.cir.out | 33 ++ library/SubcircuitLibrary/AD623/SC_AD623.pro | 73 +++ library/SubcircuitLibrary/AD623/SC_AD623.sch | 509 ++++++++++++++++++ library/SubcircuitLibrary/AD623/SC_AD623.sub | 27 + .../AD623/SC_AD623_Previous_Values.xml | 1 + library/SubcircuitLibrary/AD623/npn_1.lib | 29 + library/SubcircuitLibrary/AD623/pnp_1.lib | 29 + 11 files changed, 892 insertions(+) create mode 100644 library/SubcircuitLibrary/AD623/NPN.lib create mode 100644 library/SubcircuitLibrary/AD623/PNP.lib create mode 100644 library/SubcircuitLibrary/AD623/SC_AD623-cache.lib create mode 100644 library/SubcircuitLibrary/AD623/SC_AD623.cir create mode 100644 library/SubcircuitLibrary/AD623/SC_AD623.cir.out create mode 100644 library/SubcircuitLibrary/AD623/SC_AD623.pro create mode 100644 library/SubcircuitLibrary/AD623/SC_AD623.sch create mode 100644 library/SubcircuitLibrary/AD623/SC_AD623.sub create mode 100644 library/SubcircuitLibrary/AD623/SC_AD623_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/AD623/npn_1.lib create mode 100644 library/SubcircuitLibrary/AD623/pnp_1.lib diff --git a/library/SubcircuitLibrary/AD623/NPN.lib b/library/SubcircuitLibrary/AD623/NPN.lib new file mode 100644 index 000000000..7f2f03199 --- /dev/null +++ b/library/SubcircuitLibrary/AD623/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/AD623/PNP.lib b/library/SubcircuitLibrary/AD623/PNP.lib new file mode 100644 index 000000000..0eaa3e257 --- /dev/null +++ b/library/SubcircuitLibrary/AD623/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/AD623/SC_AD623-cache.lib b/library/SubcircuitLibrary/AD623/SC_AD623-cache.lib new file mode 100644 index 000000000..5fcd276fd --- /dev/null +++ b/library/SubcircuitLibrary/AD623/SC_AD623-cache.lib @@ -0,0 +1,153 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# DC +# +DEF DC v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 w +X - 2 0 -450 300 U 50 50 1 1 w +ENDDRAW +ENDDEF +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# dc +# +DEF dc I 0 40 Y Y 1 F N +F0 "I" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +P 2 0 1 0 0 -100 0 -100 N +P 2 0 1 0 0 100 -50 50 N +P 2 0 1 0 0 100 0 -100 N +P 2 0 1 0 0 100 50 50 N +X ~ 1 0 450 300 D 50 50 1 1 P +X ~ 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# lm_741 +# +DEF lm_741 X 0 40 Y Y 1 F N +F0 "X" -200 0 60 H V C CNN +F1 "lm_741" -100 -250 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -350 350 350 0 -350 -350 -350 350 N +X off_null 1 -50 400 200 D 50 38 1 1 I +X inv 2 -550 150 200 R 50 38 1 1 I +X non_inv 3 -550 -100 200 R 50 38 1 1 I +X v_neg 4 -150 -450 200 U 50 38 1 1 I +X off_null 5 50 350 200 D 50 38 1 1 I +X out 6 550 0 200 L 50 38 1 1 O +X v_pos 7 -150 450 200 D 50 38 1 1 I +X NC 8 150 -300 200 U 50 38 1 1 N +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/AD623/SC_AD623.cir b/library/SubcircuitLibrary/AD623/SC_AD623.cir new file mode 100644 index 000000000..bbcfed423 --- /dev/null +++ b/library/SubcircuitLibrary/AD623/SC_AD623.cir @@ -0,0 +1,30 @@ +* C:\FOSSEE2\eSim\library\SubcircuitLibrary\SC_AD623\SC_AD623.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/02/25 19:15:44 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 ? Net-_R2-Pad1_ Net-_I2-Pad1_ Net-_X1-Pad4_ ? Net-_R2-Pad2_ Net-_X1-Pad7_ ? lm_741 +X2 ? Net-_R3-Pad1_ Net-_I1-Pad1_ Net-_X2-Pad4_ ? Net-_R3-Pad2_ Net-_X2-Pad7_ ? lm_741 +X3 ? Net-_R4-Pad2_ Net-_R5-Pad2_ Net-_X3-Pad4_ ? Net-_R6-Pad2_ Net-_X3-Pad7_ ? lm_741 +R2 Net-_R2-Pad1_ Net-_R2-Pad2_ 50k +R4 Net-_R2-Pad2_ Net-_R4-Pad2_ 50k +R6 Net-_R4-Pad2_ Net-_R6-Pad2_ 50k +R7 Net-_R5-Pad2_ Net-_R7-Pad2_ 50k +R5 Net-_R3-Pad2_ Net-_R5-Pad2_ 50k +R3 Net-_R3-Pad1_ Net-_R3-Pad2_ 50k +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_I2-Pad1_ eSim_PNP +Q2 Net-_Q1-Pad1_ Net-_Q2-Pad2_ Net-_I1-Pad1_ eSim_PNP +U1 Net-_R2-Pad1_ Net-_Q1-Pad2_ Net-_Q2-Pad2_ Net-_Q1-Pad1_ Net-_R7-Pad2_ Net-_R6-Pad2_ Net-_I1-Pad2_ Net-_R3-Pad1_ PORT +v2 Net-_X1-Pad7_ GND DC +v5 GND Net-_X3-Pad7_ DC +v4 Net-_X2-Pad7_ GND DC +v3 GND Net-_X2-Pad4_ DC +v6 GND Net-_X3-Pad4_ DC +v1 GND Net-_X1-Pad4_ DC +I2 Net-_I2-Pad1_ Net-_I1-Pad2_ dc +I1 Net-_I1-Pad1_ Net-_I1-Pad2_ dc + +.end diff --git a/library/SubcircuitLibrary/AD623/SC_AD623.cir.out b/library/SubcircuitLibrary/AD623/SC_AD623.cir.out new file mode 100644 index 000000000..3685be682 --- /dev/null +++ b/library/SubcircuitLibrary/AD623/SC_AD623.cir.out @@ -0,0 +1,33 @@ +* c:\fossee2\esim\library\subcircuitlibrary\sc_ad623\sc_ad623.cir + +.include lm_741.sub +.include PNP.lib +x1 ? net-_r2-pad1_ net-_i2-pad1_ net-_x1-pad4_ ? net-_r2-pad2_ net-_x1-pad7_ ? lm_741 +x2 ? net-_r3-pad1_ net-_i1-pad1_ net-_x2-pad4_ ? net-_r3-pad2_ net-_x2-pad7_ ? lm_741 +x3 ? net-_r4-pad2_ net-_r5-pad2_ net-_x3-pad4_ ? net-_r6-pad2_ net-_x3-pad7_ ? lm_741 +r2 net-_r2-pad1_ net-_r2-pad2_ 50k +r4 net-_r2-pad2_ net-_r4-pad2_ 50k +r6 net-_r4-pad2_ net-_r6-pad2_ 50k +r7 net-_r5-pad2_ net-_r7-pad2_ 50k +r5 net-_r3-pad2_ net-_r5-pad2_ 50k +r3 net-_r3-pad1_ net-_r3-pad2_ 50k +q1 net-_q1-pad1_ net-_q1-pad2_ net-_i2-pad1_ Q2N2907A +q2 net-_q1-pad1_ net-_q2-pad2_ net-_i1-pad1_ Q2N2907A +* u1 net-_r2-pad1_ net-_q1-pad2_ net-_q2-pad2_ net-_q1-pad1_ net-_r7-pad2_ net-_r6-pad2_ net-_i1-pad2_ net-_r3-pad1_ port +v2 net-_x1-pad7_ gnd dc 12 +v5 gnd net-_x3-pad7_ dc 12 +v4 net-_x2-pad7_ gnd dc 12 +v3 gnd net-_x2-pad4_ dc 12 +v6 gnd net-_x3-pad4_ dc 12 +v1 gnd net-_x1-pad4_ dc 12 +i2 net-_i2-pad1_ net-_i1-pad2_ dc 50u +i1 net-_i1-pad1_ net-_i1-pad2_ dc 50u +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/AD623/SC_AD623.pro b/library/SubcircuitLibrary/AD623/SC_AD623.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/AD623/SC_AD623.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/AD623/SC_AD623.sch b/library/SubcircuitLibrary/AD623/SC_AD623.sch new file mode 100644 index 000000000..abca5346c --- /dev/null +++ b/library/SubcircuitLibrary/AD623/SC_AD623.sch @@ -0,0 +1,509 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SC_AD623-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L lm_741 X1 +U 1 1 683572C9 +P 5650 2450 +F 0 "X1" H 5450 2450 60 0000 C CNN +F 1 "lm_741" H 5550 2200 60 0000 C CNN +F 2 "" H 5650 2450 60 0000 C CNN +F 3 "" H 5650 2450 60 0000 C CNN + 1 5650 2450 + 1 0 0 -1 +$EndComp +$Comp +L lm_741 X2 +U 1 1 6835732C +P 5700 5550 +F 0 "X2" H 5500 5550 60 0000 C CNN +F 1 "lm_741" H 5600 5300 60 0000 C CNN +F 2 "" H 5700 5550 60 0000 C CNN +F 3 "" H 5700 5550 60 0000 C CNN + 1 5700 5550 + 1 0 0 -1 +$EndComp +$Comp +L lm_741 X3 +U 1 1 6835735D +P 7750 3750 +F 0 "X3" H 7550 3750 60 0000 C CNN +F 1 "lm_741" H 7650 3500 60 0000 C CNN +F 2 "" H 7750 3750 60 0000 C CNN +F 3 "" H 7750 3750 60 0000 C CNN + 1 7750 3750 + 1 0 0 -1 +$EndComp +$Comp +L resistor R2 +U 1 1 683574A1 +P 5550 3150 +F 0 "R2" H 5600 3280 50 0000 C CNN +F 1 "50k" H 5600 3100 50 0000 C CNN +F 2 "" H 5600 3130 30 0000 C CNN +F 3 "" V 5600 3200 30 0000 C CNN + 1 5550 3150 + 1 0 0 -1 +$EndComp +$Comp +L resistor R4 +U 1 1 683574FC +P 6300 3150 +F 0 "R4" H 6350 3280 50 0000 C CNN +F 1 "50k" H 6350 3100 50 0000 C CNN +F 2 "" H 6350 3130 30 0000 C CNN +F 3 "" V 6350 3200 30 0000 C CNN + 1 6300 3150 + 1 0 0 -1 +$EndComp +$Comp +L resistor R6 +U 1 1 6835758A +P 6800 3150 +F 0 "R6" H 6850 3280 50 0000 C CNN +F 1 "50k" H 6850 3100 50 0000 C CNN +F 2 "" H 6850 3130 30 0000 C CNN +F 3 "" V 6850 3200 30 0000 C CNN + 1 6800 3150 + 1 0 0 -1 +$EndComp +$Comp +L resistor R7 +U 1 1 68357687 +P 7600 4550 +F 0 "R7" H 7650 4680 50 0000 C CNN +F 1 "50k" H 7650 4500 50 0000 C CNN +F 2 "" H 7650 4530 30 0000 C CNN +F 3 "" V 7650 4600 30 0000 C CNN + 1 7600 4550 + 1 0 0 -1 +$EndComp +$Comp +L resistor R5 +U 1 1 683576FE +P 6650 4550 +F 0 "R5" H 6700 4680 50 0000 C CNN +F 1 "50k" H 6700 4500 50 0000 C CNN +F 2 "" H 6700 4530 30 0000 C CNN +F 3 "" V 6700 4600 30 0000 C CNN + 1 6650 4550 + 1 0 0 -1 +$EndComp +$Comp +L resistor R3 +U 1 1 68357780 +P 5600 4550 +F 0 "R3" H 5650 4680 50 0000 C CNN +F 1 "50k" H 5650 4500 50 0000 C CNN +F 2 "" H 5650 4530 30 0000 C CNN +F 3 "" V 5650 4600 30 0000 C CNN + 1 5600 4550 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q1 +U 1 1 68357B31 +P 4150 2950 +F 0 "Q1" H 4050 3000 50 0000 R CNN +F 1 "eSim_PNP" H 4100 3100 50 0000 R CNN +F 2 "" H 4350 3050 29 0000 C CNN +F 3 "" H 4150 2950 60 0000 C CNN + 1 4150 2950 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q2 +U 1 1 68357B94 +P 4500 6000 +F 0 "Q2" H 4400 6050 50 0000 R CNN +F 1 "eSim_PNP" H 4450 6150 50 0000 R CNN +F 2 "" H 4700 6100 29 0000 C CNN +F 3 "" H 4500 6000 60 0000 C CNN + 1 4500 6000 + 1 0 0 1 +$EndComp +NoConn ~ 5650 5150 +NoConn ~ 5750 5200 +NoConn ~ 7700 3350 +NoConn ~ 7800 3400 +NoConn ~ 5600 2050 +NoConn ~ 5700 2100 +$Comp +L PORT U1 +U 1 1 683961B4 +P 4450 3300 +F 0 "U1" H 4500 3400 30 0000 C CNN +F 1 "PORT" H 4450 3300 30 0000 C CNN +F 2 "" H 4450 3300 60 0000 C CNN +F 3 "" H 4450 3300 60 0000 C CNN + 1 4450 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 68396217 +P 3700 2950 +F 0 "U1" H 3750 3050 30 0000 C CNN +F 1 "PORT" H 3700 2950 30 0000 C CNN +F 2 "" H 3700 2950 60 0000 C CNN +F 3 "" H 3700 2950 60 0000 C CNN + 2 3700 2950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 6839628E +P 4050 6000 +F 0 "U1" H 4100 6100 30 0000 C CNN +F 1 "PORT" H 4050 6000 30 0000 C CNN +F 2 "" H 4050 6000 60 0000 C CNN +F 3 "" H 4050 6000 60 0000 C CNN + 3 4050 6000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 6839636C +P 4000 3850 +F 0 "U1" H 4050 3950 30 0000 C CNN +F 1 "PORT" H 4000 3850 30 0000 C CNN +F 2 "" H 4000 3850 60 0000 C CNN +F 3 "" H 4000 3850 60 0000 C CNN + 4 4000 3850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 6839655C +P 8050 4500 +F 0 "U1" H 8100 4600 30 0000 C CNN +F 1 "PORT" H 8050 4500 30 0000 C CNN +F 2 "" H 8050 4500 60 0000 C CNN +F 3 "" H 8050 4500 60 0000 C CNN + 5 8050 4500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 68396641 +P 8300 4000 +F 0 "U1" H 8350 4100 30 0000 C CNN +F 1 "PORT" H 8300 4000 30 0000 C CNN +F 2 "" H 8300 4000 60 0000 C CNN +F 3 "" H 8300 4000 60 0000 C CNN + 6 8300 4000 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 7 1 683966F4 +P 4500 1000 +F 0 "U1" H 4550 1100 30 0000 C CNN +F 1 "PORT" H 4500 1000 30 0000 C CNN +F 2 "" H 4500 1000 60 0000 C CNN +F 3 "" H 4500 1000 60 0000 C CNN + 7 4500 1000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 6839679F +P 4400 4100 +F 0 "U1" H 4450 4200 30 0000 C CNN +F 1 "PORT" H 4400 4100 30 0000 C CNN +F 2 "" H 4400 4100 60 0000 C CNN +F 3 "" H 4400 4100 60 0000 C CNN + 8 4400 4100 + 1 0 0 -1 +$EndComp +$Comp +L DC v2 +U 1 1 6839B6BB +P 5500 1550 +F 0 "v2" H 5300 1650 60 0000 C CNN +F 1 "DC" H 5300 1500 60 0000 C CNN +F 2 "R1" H 5200 1550 60 0000 C CNN +F 3 "" H 5500 1550 60 0000 C CNN + 1 5500 1550 + -1 0 0 1 +$EndComp +$Comp +L DC v5 +U 1 1 6839B7C6 +P 7600 2450 +F 0 "v5" H 7400 2550 60 0000 C CNN +F 1 "DC" H 7400 2400 60 0000 C CNN +F 2 "R1" H 7300 2450 60 0000 C CNN +F 3 "" H 7600 2450 60 0000 C CNN + 1 7600 2450 + 1 0 0 -1 +$EndComp +$Comp +L DC v4 +U 1 1 6839BD79 +P 6900 5100 +F 0 "v4" H 6700 5200 60 0000 C CNN +F 1 "DC" H 6700 5050 60 0000 C CNN +F 2 "R1" H 6600 5100 60 0000 C CNN +F 3 "" H 6900 5100 60 0000 C CNN + 1 6900 5100 + 0 -1 -1 0 +$EndComp +$Comp +L DC v3 +U 1 1 6839BE04 +P 5550 6550 +F 0 "v3" H 5350 6650 60 0000 C CNN +F 1 "DC" H 5350 6500 60 0000 C CNN +F 2 "R1" H 5250 6550 60 0000 C CNN +F 3 "" H 5550 6550 60 0000 C CNN + 1 5550 6550 + -1 0 0 1 +$EndComp +$Comp +L DC v6 +U 1 1 6839C0E8 +P 8500 4650 +F 0 "v6" H 8300 4750 60 0000 C CNN +F 1 "DC" H 8300 4600 60 0000 C CNN +F 2 "R1" H 8200 4650 60 0000 C CNN +F 3 "" H 8500 4650 60 0000 C CNN + 1 8500 4650 + -1 0 0 1 +$EndComp +$Comp +L DC v1 +U 1 1 6839C1EB +P 5300 3650 +F 0 "v1" H 5100 3750 60 0000 C CNN +F 1 "DC" H 5100 3600 60 0000 C CNN +F 2 "R1" H 5000 3650 60 0000 C CNN +F 3 "" H 5300 3650 60 0000 C CNN + 1 5300 3650 + -1 0 0 1 +$EndComp +$Comp +L GND #PWR1 +U 1 1 6839C38B +P 5300 4100 +F 0 "#PWR1" H 5300 3850 50 0001 C CNN +F 1 "GND" H 5300 3950 50 0000 C CNN +F 2 "" H 5300 4100 50 0001 C CNN +F 3 "" H 5300 4100 50 0001 C CNN + 1 5300 4100 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR6 +U 1 1 6839C3D1 +P 8500 5100 +F 0 "#PWR6" H 8500 4850 50 0001 C CNN +F 1 "GND" H 8500 4950 50 0000 C CNN +F 2 "" H 8500 5100 50 0001 C CNN +F 3 "" H 8500 5100 50 0001 C CNN + 1 8500 5100 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR3 +U 1 1 6839C417 +P 5550 7000 +F 0 "#PWR3" H 5550 6750 50 0001 C CNN +F 1 "GND" H 5550 6850 50 0000 C CNN +F 2 "" H 5550 7000 50 0001 C CNN +F 3 "" H 5550 7000 50 0001 C CNN + 1 5550 7000 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR4 +U 1 1 6839C4DA +P 7350 5100 +F 0 "#PWR4" H 7350 4850 50 0001 C CNN +F 1 "GND" H 7350 4950 50 0000 C CNN +F 2 "" H 7350 5100 50 0001 C CNN +F 3 "" H 7350 5100 50 0001 C CNN + 1 7350 5100 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR2 +U 1 1 6839CA03 +P 5500 1100 +F 0 "#PWR2" H 5500 850 50 0001 C CNN +F 1 "GND" H 5500 950 50 0000 C CNN +F 2 "" H 5500 1100 50 0001 C CNN +F 3 "" H 5500 1100 50 0001 C CNN + 1 5500 1100 + -1 0 0 1 +$EndComp +$Comp +L GND #PWR5 +U 1 1 6839CA49 +P 7600 2000 +F 0 "#PWR5" H 7600 1750 50 0001 C CNN +F 1 "GND" H 7600 1850 50 0000 C CNN +F 2 "" H 7600 2000 50 0001 C CNN +F 3 "" H 7600 2000 50 0001 C CNN + 1 7600 2000 + -1 0 0 1 +$EndComp +Wire Wire Line + 5550 6000 5550 6100 +Wire Wire Line + 7600 3300 7600 2900 +Wire Wire Line + 4600 6350 4600 6200 +Wire Wire Line + 2850 3150 2850 6350 +Wire Wire Line + 4250 3150 2850 3150 +Wire Wire Line + 3100 4750 4600 4750 +Wire Wire Line + 4250 1000 3100 1650 +Wire Wire Line + 5150 5650 4600 5650 +Connection ~ 5150 4500 +Connection ~ 4750 3100 +Wire Wire Line + 5150 4500 5150 5400 +Wire Wire Line + 4750 4500 5500 4500 +Connection ~ 6250 4500 +Wire Wire Line + 6250 5550 6250 4500 +Wire Wire Line + 5800 4500 6550 4500 +Connection ~ 7200 4500 +Wire Wire Line + 7200 4500 7200 3850 +Wire Wire Line + 6850 4500 7500 4500 +Connection ~ 6600 3100 +Wire Wire Line + 6600 3600 6600 3100 +Wire Wire Line + 7200 3600 6600 3600 +Wire Wire Line + 8300 3100 8300 3750 +Wire Wire Line + 7000 3100 8300 3100 +Wire Wire Line + 6500 3100 6700 3100 +Wire Wire Line + 6200 3100 6200 2450 +Wire Wire Line + 5750 3100 6200 3100 +Wire Wire Line + 4750 3100 5450 3100 +Wire Wire Line + 5100 2300 4750 2300 +Wire Wire Line + 4750 3300 4700 3300 +Wire Wire Line + 4650 4100 4750 4100 +Wire Wire Line + 4750 2300 4750 3300 +Wire Wire Line + 4750 4100 4750 4500 +Connection ~ 4600 5650 +Wire Wire Line + 6450 5100 5550 5100 +Wire Wire Line + 7600 4200 8500 4200 +Wire Wire Line + 5300 3200 5300 2900 +Wire Wire Line + 5300 2900 5500 2900 +Wire Wire Line + 4250 2300 4250 2750 +Wire Wire Line + 4600 4750 4600 5800 +Wire Wire Line + 5100 2550 4250 2550 +Connection ~ 4250 2550 +Wire Wire Line + 4250 3150 4250 3850 +Wire Wire Line + 2850 6350 4600 6350 +$Comp +L dc I2 +U 1 1 683DACBE +P 4250 1850 +F 0 "I2" H 4050 1950 60 0000 C CNN +F 1 "dc" H 4050 1800 60 0000 C CNN +F 2 "R1" H 3950 1850 60 0000 C CNN +F 3 "" H 4250 1850 60 0000 C CNN + 1 4250 1850 + -1 0 0 1 +$EndComp +$Comp +L dc I1 +U 1 1 683DAE8B +P 3100 4300 +F 0 "I1" H 2900 4400 60 0000 C CNN +F 1 "dc" H 2900 4250 60 0000 C CNN +F 2 "R1" H 2800 4300 60 0000 C CNN +F 3 "" H 3100 4300 60 0000 C CNN + 1 3100 4300 + -1 0 0 1 +$EndComp +Wire Wire Line + 4250 1400 4250 1000 +Wire Wire Line + 3100 1650 3100 3850 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/AD623/SC_AD623.sub b/library/SubcircuitLibrary/AD623/SC_AD623.sub new file mode 100644 index 000000000..304fce928 --- /dev/null +++ b/library/SubcircuitLibrary/AD623/SC_AD623.sub @@ -0,0 +1,27 @@ +* Subcircuit SC_AD623 +.subckt SC_AD623 net-_r2-pad1_ net-_q1-pad2_ net-_q2-pad2_ net-_q1-pad1_ net-_r7-pad2_ net-_r6-pad2_ net-_i1-pad2_ net-_r3-pad1_ +* c:\fossee2\esim\library\subcircuitlibrary\sc_ad623\sc_ad623.cir +.include lm_741.sub +.include PNP.lib +x1 ? net-_r2-pad1_ net-_i2-pad1_ net-_x1-pad4_ ? net-_r2-pad2_ net-_x1-pad7_ ? lm_741 +x2 ? net-_r3-pad1_ net-_i1-pad1_ net-_x2-pad4_ ? net-_r3-pad2_ net-_x2-pad7_ ? lm_741 +x3 ? net-_r4-pad2_ net-_r5-pad2_ net-_x3-pad4_ ? net-_r6-pad2_ net-_x3-pad7_ ? lm_741 +r2 net-_r2-pad1_ net-_r2-pad2_ 50k +r4 net-_r2-pad2_ net-_r4-pad2_ 50k +r6 net-_r4-pad2_ net-_r6-pad2_ 50k +r7 net-_r5-pad2_ net-_r7-pad2_ 50k +r5 net-_r3-pad2_ net-_r5-pad2_ 50k +r3 net-_r3-pad1_ net-_r3-pad2_ 50k +q1 net-_q1-pad1_ net-_q1-pad2_ net-_i2-pad1_ Q2N2907A +q2 net-_q1-pad1_ net-_q2-pad2_ net-_i1-pad1_ Q2N2907A +v2 net-_x1-pad7_ gnd dc 12 +v5 gnd net-_x3-pad7_ dc 12 +v4 net-_x2-pad7_ gnd dc 12 +v3 gnd net-_x2-pad4_ dc 12 +v6 gnd net-_x3-pad4_ dc 12 +v1 gnd net-_x1-pad4_ dc 12 +i2 net-_i2-pad1_ net-_i1-pad2_ dc 50u +i1 net-_i1-pad1_ net-_i1-pad2_ dc 50u +* Control Statements + +.ends SC_AD623 \ No newline at end of file diff --git a/library/SubcircuitLibrary/AD623/SC_AD623_Previous_Values.xml b/library/SubcircuitLibrary/AD623/SC_AD623_Previous_Values.xml new file mode 100644 index 000000000..f9d9d25a8 --- /dev/null +++ b/library/SubcircuitLibrary/AD623/SC_AD623_Previous_Values.xml @@ -0,0 +1 @@ +dc12dc12dc12dc12dc12dc12dc12dc12C:\FOSSEE2\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE2\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE2\eSim\library\SubcircuitLibrary\lm_741C:\FOSSEE2\eSim\library\SubcircuitLibrary\lm_741C:\FOSSEE2\eSim\library\SubcircuitLibrary\lm_741truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes010100msmsms \ No newline at end of file diff --git a/library/SubcircuitLibrary/AD623/npn_1.lib b/library/SubcircuitLibrary/AD623/npn_1.lib new file mode 100644 index 000000000..4a863e3e9 --- /dev/null +++ b/library/SubcircuitLibrary/AD623/npn_1.lib @@ -0,0 +1,29 @@ +.model npn_1 NPN( ++ Vtf=1.7 ++ Cjc=0.5p ++ Nc=2 ++ Tr=46.91n ++ Ne=1.307 ++ Cje=0.5p ++ Isc=0 ++ Xtb=1.5 ++ Rb=500 ++ Rc=1 ++ Tf=411.1p ++ Xti=3 ++ Ikr=0 ++ Bf=125 ++ Fc=.5 ++ Ise=14.34f ++ Br=6.092 ++ Ikf=.2847 ++ Mje=.377 ++ Mjc=.3416 ++ Vaf=74.03 ++ Vjc=.75 ++ Vje=.75 ++ Xtf=3 ++ Itf=.6 ++ Is=14.34f ++ Eg=1.11 +) \ No newline at end of file diff --git a/library/SubcircuitLibrary/AD623/pnp_1.lib b/library/SubcircuitLibrary/AD623/pnp_1.lib new file mode 100644 index 000000000..c486429f0 --- /dev/null +++ b/library/SubcircuitLibrary/AD623/pnp_1.lib @@ -0,0 +1,29 @@ +.model pnp_1 PNP( ++ Vtf=1.7 ++ Cjc=1.5p ++ Nc=2 ++ Tr=46.91n ++ Ne=1.307 ++ Cje=0.3p ++ Isc=0 ++ Xtb=1.5 ++ Rb=250 ++ Rc=1 ++ Tf=411.1p ++ Xti=3 ++ Ikr=0 ++ Bf=25 ++ Fc=.5 ++ Ise=14.34f ++ Br=6.092 ++ Ikf=.2847 ++ Mje=.377 ++ Mjc=.3416 ++ Vaf=74.03 ++ Vjc=.75 ++ Vje=.75 ++ Xtf=3 ++ Itf=.6 ++ Is=14.34f ++ Eg=1.11 +) \ No newline at end of file From 1f2cb067f4372a4ab0e195cbde7fbda3d069cf42 Mon Sep 17 00:00:00 2001 From: Annesha Dey <142687349+AD20047@users.noreply.github.com> Date: Fri, 11 Jul 2025 23:33:15 +0530 Subject: [PATCH 3/9] Operational Amplifiers --- library/SubcircuitLibrary/MC33171/analysis | 1 + 1 file changed, 1 insertion(+) create mode 100644 library/SubcircuitLibrary/MC33171/analysis diff --git a/library/SubcircuitLibrary/MC33171/analysis b/library/SubcircuitLibrary/MC33171/analysis new file mode 100644 index 000000000..f6e0de997 --- /dev/null +++ b/library/SubcircuitLibrary/MC33171/analysis @@ -0,0 +1 @@ +.tran 1e-06 1000e-06 0e-06 From 4467516c775d2bfbbce78582e7d270bbe49ed34a Mon Sep 17 00:00:00 2001 From: Annesha Dey <142687349+AD20047@users.noreply.github.com> Date: Fri, 11 Jul 2025 23:34:52 +0530 Subject: [PATCH 4/9] Operational Amplifiers --- library/SubcircuitLibrary/MC33171/D.lib | 2 + library/SubcircuitLibrary/MC33171/NPN.lib | 4 + library/SubcircuitLibrary/MC33171/PNP.lib | 4 + .../MC33171/SC_MC33171-cache.lib | 181 +++++ .../SubcircuitLibrary/MC33171/SC_MC33171.cir | 45 ++ .../MC33171/SC_MC33171.cir.out | 49 ++ .../SubcircuitLibrary/MC33171/SC_MC33171.pro | 73 ++ .../SubcircuitLibrary/MC33171/SC_MC33171.sch | 708 ++++++++++++++++++ .../SubcircuitLibrary/MC33171/SC_MC33171.sub | 43 ++ .../MC33171/SC_MC33171_Previous_Values.xml | 1 + 10 files changed, 1110 insertions(+) create mode 100644 library/SubcircuitLibrary/MC33171/D.lib create mode 100644 library/SubcircuitLibrary/MC33171/NPN.lib create mode 100644 library/SubcircuitLibrary/MC33171/PNP.lib create mode 100644 library/SubcircuitLibrary/MC33171/SC_MC33171-cache.lib create mode 100644 library/SubcircuitLibrary/MC33171/SC_MC33171.cir create mode 100644 library/SubcircuitLibrary/MC33171/SC_MC33171.cir.out create mode 100644 library/SubcircuitLibrary/MC33171/SC_MC33171.pro create mode 100644 library/SubcircuitLibrary/MC33171/SC_MC33171.sch create mode 100644 library/SubcircuitLibrary/MC33171/SC_MC33171.sub create mode 100644 library/SubcircuitLibrary/MC33171/SC_MC33171_Previous_Values.xml diff --git a/library/SubcircuitLibrary/MC33171/D.lib b/library/SubcircuitLibrary/MC33171/D.lib new file mode 100644 index 000000000..f53bf3e03 --- /dev/null +++ b/library/SubcircuitLibrary/MC33171/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/MC33171/NPN.lib b/library/SubcircuitLibrary/MC33171/NPN.lib new file mode 100644 index 000000000..be5f3073a --- /dev/null +++ b/library/SubcircuitLibrary/MC33171/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/MC33171/PNP.lib b/library/SubcircuitLibrary/MC33171/PNP.lib new file mode 100644 index 000000000..7edda0eab --- /dev/null +++ b/library/SubcircuitLibrary/MC33171/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/MC33171/SC_MC33171-cache.lib b/library/SubcircuitLibrary/MC33171/SC_MC33171-cache.lib new file mode 100644 index 000000000..e1f99d5b6 --- /dev/null +++ b/library/SubcircuitLibrary/MC33171/SC_MC33171-cache.lib @@ -0,0 +1,181 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# dc +# +DEF dc I 0 40 Y Y 1 F N +F0 "I" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +P 2 0 1 0 0 -100 0 -100 N +P 2 0 1 0 0 100 -50 50 N +P 2 0 1 0 0 100 0 -100 N +P 2 0 1 0 0 100 50 50 N +X ~ 1 0 450 300 D 50 50 1 1 P +X ~ 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_CP1 +# +DEF eSim_CP1 C 0 10 N N 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_CP1" 25 -100 50 H V L CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +ALIAS capacitor_polarised +$FPLIST + CP_* +$ENDFPLIST +DRAW +A 0 -150 128 1287 513 0 1 20 N -80 -50 80 -50 +P 2 0 1 20 -80 30 80 30 N +P 2 0 1 0 -70 90 -30 90 N +P 2 0 1 0 -50 70 -50 110 N +X ~ 1 0 150 110 D 50 50 1 1 P +X ~ 2 0 -150 130 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/MC33171/SC_MC33171.cir b/library/SubcircuitLibrary/MC33171/SC_MC33171.cir new file mode 100644 index 000000000..157ea0a7b --- /dev/null +++ b/library/SubcircuitLibrary/MC33171/SC_MC33171.cir @@ -0,0 +1,45 @@ +* C:\FOSSEE2\eSim\library\SubcircuitLibrary\SC_MC33171\SC_MC33171.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/07/25 00:42:32 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q1 Net-_I1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_PNP +Q3 Net-_Q3-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_PNP +Q6 Net-_Q6-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_PNP +Q9 Net-_Q11-Pad3_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_PNP +Q12 Net-_Q10-Pad3_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_PNP +Q14 Net-_D2-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_PNP +Q2 Net-_Q10-Pad1_ Net-_I1-Pad1_ Net-_Q1-Pad2_ eSim_PNP +Q4 Net-_Q10-Pad1_ Net-_Q4-Pad2_ Net-_Q3-Pad1_ eSim_PNP +Q5 Net-_D1-Pad1_ Net-_Q3-Pad1_ Net-_C1-Pad2_ eSim_PNP +Q8 Net-_C2-Pad2_ Net-_Q11-Pad3_ Net-_C1-Pad1_ eSim_PNP +Q11 Net-_Q10-Pad1_ Net-_Q11-Pad2_ Net-_Q11-Pad3_ eSim_PNP +Q16 Net-_Q1-Pad3_ Net-_D2-Pad1_ Net-_C2-Pad1_ eSim_NPN +Q18 Net-_D2-Pad1_ Net-_C2-Pad1_ Net-_Q18-Pad3_ eSim_NPN +Q19 Net-_Q19-Pad1_ Net-_C2-Pad1_ Net-_I2-Pad1_ eSim_NPN +Q17 Net-_C2-Pad1_ Net-_Q13-Pad3_ Net-_Q10-Pad1_ eSim_NPN +Q15 Net-_D2-Pad2_ ? Net-_Q10-Pad1_ eSim_NPN +Q13 Net-_D2-Pad1_ Net-_Q10-Pad3_ Net-_Q13-Pad3_ eSim_NPN +Q7 Net-_C2-Pad2_ Net-_D1-Pad1_ Net-_Q7-Pad3_ eSim_NPN +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 0.8p +R1 Net-_Q6-Pad1_ Net-_C1-Pad2_ 10k +R3 Net-_Q6-Pad1_ Net-_C1-Pad1_ 10k +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +R2 Net-_D1-Pad2_ Net-_Q10-Pad1_ 10k +R4 Net-_Q7-Pad3_ Net-_Q10-Pad1_ 10k +D2 Net-_D2-Pad1_ Net-_D2-Pad2_ eSim_Diode +R6 Net-_D2-Pad2_ Net-_C2-Pad1_ 10k +R7 Net-_C2-Pad1_ Net-_Q18-Pad3_ 10k +D3 Net-_C2-Pad1_ Net-_D2-Pad2_ eSim_Diode +R8 Net-_Q19-Pad1_ Net-_Q18-Pad3_ 10k +C2 Net-_C2-Pad1_ Net-_C2-Pad2_ 100u +Q10 Net-_Q10-Pad1_ Net-_C2-Pad2_ Net-_Q10-Pad3_ eSim_PNP +R5 Net-_Q13-Pad3_ Net-_Q10-Pad1_ 10k +U1 Net-_D1-Pad2_ Net-_Q4-Pad2_ Net-_Q11-Pad2_ Net-_Q10-Pad1_ Net-_Q7-Pad3_ Net-_Q18-Pad3_ Net-_Q1-Pad3_ ? PORT +I1 Net-_I1-Pad1_ GND dc +I2 Net-_I2-Pad1_ GND dc + +.end diff --git a/library/SubcircuitLibrary/MC33171/SC_MC33171.cir.out b/library/SubcircuitLibrary/MC33171/SC_MC33171.cir.out new file mode 100644 index 000000000..d1410e372 --- /dev/null +++ b/library/SubcircuitLibrary/MC33171/SC_MC33171.cir.out @@ -0,0 +1,49 @@ +* c:\fossee2\esim\library\subcircuitlibrary\sc_mc33171\sc_mc33171.cir + +.include NPN.lib +.include PNP.lib +.include D.lib +q1 net-_i1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2907A +q3 net-_q3-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2907A +q6 net-_q6-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2907A +q9 net-_q11-pad3_ net-_q1-pad2_ net-_q1-pad3_ Q2N2907A +q12 net-_q10-pad3_ net-_q1-pad2_ net-_q1-pad3_ Q2N2907A +q14 net-_d2-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2907A +q2 net-_q10-pad1_ net-_i1-pad1_ net-_q1-pad2_ Q2N2907A +q4 net-_q10-pad1_ net-_q4-pad2_ net-_q3-pad1_ Q2N2907A +q5 net-_d1-pad1_ net-_q3-pad1_ net-_c1-pad2_ Q2N2907A +q8 net-_c2-pad2_ net-_q11-pad3_ net-_c1-pad1_ Q2N2907A +q11 net-_q10-pad1_ net-_q11-pad2_ net-_q11-pad3_ Q2N2907A +q16 net-_q1-pad3_ net-_d2-pad1_ net-_c2-pad1_ Q2N2222 +q18 net-_d2-pad1_ net-_c2-pad1_ net-_q18-pad3_ Q2N2222 +q19 net-_q19-pad1_ net-_c2-pad1_ net-_i2-pad1_ Q2N2222 +q17 net-_c2-pad1_ net-_q13-pad3_ net-_q10-pad1_ Q2N2222 +q15 net-_d2-pad2_ ? net-_q10-pad1_ Q2N2222 +q13 net-_d2-pad1_ net-_q10-pad3_ net-_q13-pad3_ Q2N2222 +q7 net-_c2-pad2_ net-_d1-pad1_ net-_q7-pad3_ Q2N2222 +c1 net-_c1-pad1_ net-_c1-pad2_ 0.8p +r1 net-_q6-pad1_ net-_c1-pad2_ 10k +r3 net-_q6-pad1_ net-_c1-pad1_ 10k +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +r2 net-_d1-pad2_ net-_q10-pad1_ 10k +r4 net-_q7-pad3_ net-_q10-pad1_ 10k +d2 net-_d2-pad1_ net-_d2-pad2_ 1N4148 +r6 net-_d2-pad2_ net-_c2-pad1_ 10k +r7 net-_c2-pad1_ net-_q18-pad3_ 10k +d3 net-_c2-pad1_ net-_d2-pad2_ 1N4148 +r8 net-_q19-pad1_ net-_q18-pad3_ 10k +c2 net-_c2-pad1_ net-_c2-pad2_ 100u +q10 net-_q10-pad1_ net-_c2-pad2_ net-_q10-pad3_ Q2N2907A +r5 net-_q13-pad3_ net-_q10-pad1_ 10k +* u1 net-_d1-pad2_ net-_q4-pad2_ net-_q11-pad2_ net-_q10-pad1_ net-_q7-pad3_ net-_q18-pad3_ net-_q1-pad3_ ? port +i1 net-_i1-pad1_ gnd dc 500u +i2 net-_i2-pad1_ gnd dc 10p +.tran 1e-06 1000e-06 0e-06 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/MC33171/SC_MC33171.pro b/library/SubcircuitLibrary/MC33171/SC_MC33171.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/MC33171/SC_MC33171.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/MC33171/SC_MC33171.sch b/library/SubcircuitLibrary/MC33171/SC_MC33171.sch new file mode 100644 index 000000000..39babe3be --- /dev/null +++ b/library/SubcircuitLibrary/MC33171/SC_MC33171.sch @@ -0,0 +1,708 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SC_MC33171-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_PNP Q1 +U 1 1 6842EE61 +P 2700 1650 +F 0 "Q1" H 2600 1700 50 0000 R CNN +F 1 "eSim_PNP" H 2650 1800 50 0000 R CNN +F 2 "" H 2900 1750 29 0000 C CNN +F 3 "" H 2700 1650 60 0000 C CNN + 1 2700 1650 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q3 +U 1 1 6842EEA1 +P 3950 1650 +F 0 "Q3" H 3850 1700 50 0000 R CNN +F 1 "eSim_PNP" H 3900 1800 50 0000 R CNN +F 2 "" H 4150 1750 29 0000 C CNN +F 3 "" H 3950 1650 60 0000 C CNN + 1 3950 1650 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q6 +U 1 1 6842EF05 +P 4850 1650 +F 0 "Q6" H 4750 1700 50 0000 R CNN +F 1 "eSim_PNP" H 4800 1800 50 0000 R CNN +F 2 "" H 5050 1750 29 0000 C CNN +F 3 "" H 4850 1650 60 0000 C CNN + 1 4850 1650 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q9 +U 1 1 6842EF55 +P 5850 1650 +F 0 "Q9" H 5750 1700 50 0000 R CNN +F 1 "eSim_PNP" H 5800 1800 50 0000 R CNN +F 2 "" H 6050 1750 29 0000 C CNN +F 3 "" H 5850 1650 60 0000 C CNN + 1 5850 1650 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q12 +U 1 1 6842EFA6 +P 7000 1650 +F 0 "Q12" H 6900 1700 50 0000 R CNN +F 1 "eSim_PNP" H 6950 1800 50 0000 R CNN +F 2 "" H 7200 1750 29 0000 C CNN +F 3 "" H 7000 1650 60 0000 C CNN + 1 7000 1650 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q14 +U 1 1 6842F003 +P 7850 1650 +F 0 "Q14" H 7750 1700 50 0000 R CNN +F 1 "eSim_PNP" H 7800 1800 50 0000 R CNN +F 2 "" H 8050 1750 29 0000 C CNN +F 3 "" H 7850 1650 60 0000 C CNN + 1 7850 1650 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q2 +U 1 1 6842F057 +P 3250 2300 +F 0 "Q2" H 3150 2350 50 0000 R CNN +F 1 "eSim_PNP" H 3200 2450 50 0000 R CNN +F 2 "" H 3450 2400 29 0000 C CNN +F 3 "" H 3250 2300 60 0000 C CNN + 1 3250 2300 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q4 +U 1 1 6842F0B4 +P 3950 3200 +F 0 "Q4" H 3850 3250 50 0000 R CNN +F 1 "eSim_PNP" H 3900 3350 50 0000 R CNN +F 2 "" H 4150 3300 29 0000 C CNN +F 3 "" H 3950 3200 60 0000 C CNN + 1 3950 3200 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q5 +U 1 1 6842F13A +P 4700 3200 +F 0 "Q5" H 4600 3250 50 0000 R CNN +F 1 "eSim_PNP" H 4650 3350 50 0000 R CNN +F 2 "" H 4900 3300 29 0000 C CNN +F 3 "" H 4700 3200 60 0000 C CNN + 1 4700 3200 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q8 +U 1 1 6842F187 +P 5550 3200 +F 0 "Q8" H 5450 3250 50 0000 R CNN +F 1 "eSim_PNP" H 5500 3350 50 0000 R CNN +F 2 "" H 5750 3300 29 0000 C CNN +F 3 "" H 5550 3200 60 0000 C CNN + 1 5550 3200 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q11 +U 1 1 6842F1E6 +P 6500 3200 +F 0 "Q11" H 6400 3250 50 0000 R CNN +F 1 "eSim_PNP" H 6450 3350 50 0000 R CNN +F 2 "" H 6700 3300 29 0000 C CNN +F 3 "" H 6500 3200 60 0000 C CNN + 1 6500 3200 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q16 +U 1 1 6842F241 +P 8800 2000 +F 0 "Q16" H 8700 2050 50 0000 R CNN +F 1 "eSim_NPN" H 8750 2150 50 0000 R CNN +F 2 "" H 9000 2100 29 0000 C CNN +F 3 "" H 8800 2000 60 0000 C CNN + 1 8800 2000 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q18 +U 1 1 6842F29E +P 9600 2250 +F 0 "Q18" H 9500 2300 50 0000 R CNN +F 1 "eSim_NPN" H 9550 2400 50 0000 R CNN +F 2 "" H 9800 2350 29 0000 C CNN +F 3 "" H 9600 2250 60 0000 C CNN + 1 9600 2250 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q19 +U 1 1 6842F2E3 +P 9600 3800 +F 0 "Q19" H 9500 3850 50 0000 R CNN +F 1 "eSim_NPN" H 9550 3950 50 0000 R CNN +F 2 "" H 9800 3900 29 0000 C CNN +F 3 "" H 9600 3800 60 0000 C CNN + 1 9600 3800 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q17 +U 1 1 6842F324 +P 8800 4500 +F 0 "Q17" H 8700 4550 50 0000 R CNN +F 1 "eSim_NPN" H 8750 4650 50 0000 R CNN +F 2 "" H 9000 4600 29 0000 C CNN +F 3 "" H 8800 4500 60 0000 C CNN + 1 8800 4500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q15 +U 1 1 6842F369 +P 7850 4500 +F 0 "Q15" H 7750 4550 50 0000 R CNN +F 1 "eSim_NPN" H 7800 4650 50 0000 R CNN +F 2 "" H 8050 4600 29 0000 C CNN +F 3 "" H 7850 4500 60 0000 C CNN + 1 7850 4500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q13 +U 1 1 6842F3B0 +P 7350 4000 +F 0 "Q13" H 7250 4050 50 0000 R CNN +F 1 "eSim_NPN" H 7300 4150 50 0000 R CNN +F 2 "" H 7550 4100 29 0000 C CNN +F 3 "" H 7350 4000 60 0000 C CNN + 1 7350 4000 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q7 +U 1 1 6842F46E +P 5350 5100 +F 0 "Q7" H 5250 5150 50 0000 R CNN +F 1 "eSim_NPN" H 5300 5250 50 0000 R CNN +F 2 "" H 5550 5200 29 0000 C CNN +F 3 "" H 5350 5100 60 0000 C CNN + 1 5350 5100 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR01 +U 1 1 6842F79A +P 2600 3200 +F 0 "#PWR01" H 2600 2950 50 0001 C CNN +F 1 "GND" H 2600 3050 50 0000 C CNN +F 2 "" H 2600 3200 50 0001 C CNN +F 3 "" H 2600 3200 50 0001 C CNN + 1 2600 3200 + 1 0 0 -1 +$EndComp +$Comp +L capacitor_polarised C1 +U 1 1 6842F8B1 +P 5100 2800 +F 0 "C1" H 5125 2900 50 0000 L CNN +F 1 "0.8p" H 5125 2700 50 0000 L CNN +F 2 "" H 5100 2800 50 0001 C CNN +F 3 "" H 5100 2800 50 0001 C CNN + 1 5100 2800 + 0 1 1 0 +$EndComp +$Comp +L resistor R1 +U 1 1 6842F90A +P 4750 2400 +F 0 "R1" H 4800 2530 50 0000 C CNN +F 1 "10k" H 4800 2350 50 0000 C CNN +F 2 "" H 4800 2380 30 0000 C CNN +F 3 "" V 4800 2450 30 0000 C CNN + 1 4750 2400 + 0 1 1 0 +$EndComp +$Comp +L resistor R3 +U 1 1 6842F96B +P 5400 2400 +F 0 "R3" H 5450 2530 50 0000 C CNN +F 1 "10k" H 5450 2350 50 0000 C CNN +F 2 "" H 5450 2380 30 0000 C CNN +F 3 "" V 5450 2450 30 0000 C CNN + 1 5400 2400 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D1 +U 1 1 68430003 +P 4800 5250 +F 0 "D1" H 4800 5350 50 0000 C CNN +F 1 "eSim_Diode" H 4800 5150 50 0000 C CNN +F 2 "" H 4800 5250 60 0000 C CNN +F 3 "" H 4800 5250 60 0000 C CNN + 1 4800 5250 + 0 1 1 0 +$EndComp +$Comp +L resistor R2 +U 1 1 68430096 +P 4750 5650 +F 0 "R2" H 4800 5780 50 0000 C CNN +F 1 "10k" H 4800 5600 50 0000 C CNN +F 2 "" H 4800 5630 30 0000 C CNN +F 3 "" V 4800 5700 30 0000 C CNN + 1 4750 5650 + 0 1 1 0 +$EndComp +$Comp +L resistor R4 +U 1 1 6843010F +P 5400 5650 +F 0 "R4" H 5450 5780 50 0000 C CNN +F 1 "10k" H 5450 5600 50 0000 C CNN +F 2 "" H 5450 5630 30 0000 C CNN +F 3 "" V 5450 5700 30 0000 C CNN + 1 5400 5650 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D2 +U 1 1 684306B0 +P 7950 2300 +F 0 "D2" H 7950 2400 50 0000 C CNN +F 1 "eSim_Diode" H 7950 2200 50 0000 C CNN +F 2 "" H 7950 2300 60 0000 C CNN +F 3 "" H 7950 2300 60 0000 C CNN + 1 7950 2300 + 0 1 1 0 +$EndComp +$Comp +L resistor R6 +U 1 1 68430735 +P 8350 2700 +F 0 "R6" H 8400 2830 50 0000 C CNN +F 1 "10k" H 8400 2650 50 0000 C CNN +F 2 "" H 8400 2680 30 0000 C CNN +F 3 "" V 8400 2750 30 0000 C CNN + 1 8350 2700 + 1 0 0 -1 +$EndComp +$Comp +L resistor R7 +U 1 1 684307C4 +P 9250 2700 +F 0 "R7" H 9300 2830 50 0000 C CNN +F 1 "10k" H 9300 2650 50 0000 C CNN +F 2 "" H 9300 2680 30 0000 C CNN +F 3 "" V 9300 2750 30 0000 C CNN + 1 9250 2700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D3 +U 1 1 68430869 +P 8450 3150 +F 0 "D3" H 8450 3250 50 0000 C CNN +F 1 "eSim_Diode" H 8450 3050 50 0000 C CNN +F 2 "" H 8450 3150 60 0000 C CNN +F 3 "" H 8450 3150 60 0000 C CNN + 1 8450 3150 + -1 0 0 1 +$EndComp +$Comp +L resistor R8 +U 1 1 684308D6 +P 9750 3150 +F 0 "R8" H 9800 3280 50 0000 C CNN +F 1 "10k" H 9800 3100 50 0000 C CNN +F 2 "" H 9800 3130 30 0000 C CNN +F 3 "" V 9800 3200 30 0000 C CNN + 1 9750 3150 + 0 -1 -1 0 +$EndComp +$Comp +L capacitor_polarised C2 +U 1 1 68430EF1 +P 7750 3800 +F 0 "C2" H 7775 3900 50 0000 L CNN +F 1 "100u" H 7775 3700 50 0000 L CNN +F 2 "" H 7750 3800 50 0001 C CNN +F 3 "" H 7750 3800 50 0001 C CNN + 1 7750 3800 + 0 1 1 0 +$EndComp +Connection ~ 4050 1450 +Connection ~ 4950 1450 +Connection ~ 5750 1450 +Wire Wire Line + 2600 1450 8900 1450 +Connection ~ 6900 1450 +Wire Wire Line + 2900 1650 7650 1650 +Connection ~ 3750 1650 +Connection ~ 4650 1650 +Connection ~ 6050 1650 +Connection ~ 7200 1650 +Wire Wire Line + 3350 2100 3350 1650 +Connection ~ 3350 1650 +Wire Wire Line + 2600 1850 2600 2300 +Wire Wire Line + 2600 2300 3050 2300 +Wire Wire Line + 4050 1850 4050 3000 +Wire Wire Line + 4050 3400 4050 3750 +Wire Wire Line + 4050 3750 6400 3750 +Wire Wire Line + 6400 3750 6400 3400 +Wire Wire Line + 3350 2500 3350 6050 +Wire Wire Line + 3350 4100 5100 4100 +Wire Wire Line + 5100 4100 5100 3750 +Connection ~ 5100 3750 +Wire Wire Line + 4050 2800 4500 2800 +Wire Wire Line + 4500 2800 4500 3200 +Connection ~ 4050 2800 +Wire Wire Line + 4950 1850 4950 2300 +Wire Wire Line + 4800 2300 5450 2300 +Connection ~ 4950 2300 +Wire Wire Line + 4800 2600 4800 3000 +Wire Wire Line + 5450 2600 5450 3000 +Wire Wire Line + 5250 2800 5450 2800 +Connection ~ 5450 2800 +Wire Wire Line + 4950 2800 4800 2800 +Connection ~ 4800 2800 +Wire Wire Line + 5750 1850 5750 3200 +Wire Wire Line + 5750 2800 6400 2800 +Wire Wire Line + 6400 2800 6400 3000 +Connection ~ 5750 2800 +Wire Wire Line + 5450 3400 5450 4900 +Wire Wire Line + 5450 4550 5850 4550 +Connection ~ 5450 4550 +Wire Wire Line + 4800 3400 4800 5100 +Wire Wire Line + 4800 5100 5150 5100 +Wire Wire Line + 4800 5400 4800 5550 +Wire Wire Line + 5450 5300 5450 5550 +Wire Wire Line + 3350 6050 8900 6050 +Wire Wire Line + 4800 6050 4800 5850 +Connection ~ 3350 4100 +Wire Wire Line + 5450 6050 5450 5850 +Connection ~ 4800 6050 +Wire Wire Line + 6150 6050 6150 4750 +Connection ~ 5450 6050 +Wire Wire Line + 6150 4350 6150 4000 +Wire Wire Line + 6150 4000 7150 4000 +Wire Wire Line + 6900 1850 6900 4000 +Connection ~ 6900 4000 +Wire Wire Line + 7450 3800 7450 2000 +Wire Wire Line + 7450 2000 8600 2000 +Wire Wire Line + 7950 1850 7950 2150 +Connection ~ 7950 2000 +Wire Wire Line + 8900 1450 8900 1800 +Connection ~ 7950 1450 +Wire Wire Line + 8550 2000 9700 2000 +Wire Wire Line + 9700 2000 9700 2050 +Connection ~ 8550 2000 +Wire Wire Line + 8900 2200 8900 4300 +Wire Wire Line + 8900 2250 9400 2250 +Wire Wire Line + 7950 2450 7950 4300 +Wire Wire Line + 7950 2650 8250 2650 +Wire Wire Line + 8550 2650 9150 2650 +Connection ~ 8900 2650 +Connection ~ 8900 2250 +Wire Wire Line + 9450 2650 9700 2650 +Wire Wire Line + 9700 2450 9700 2950 +Connection ~ 9700 2650 +Wire Wire Line + 9700 3250 9700 3600 +Wire Wire Line + 7950 3150 8300 3150 +Connection ~ 7950 2650 +Wire Wire Line + 8900 3150 8600 3150 +Wire Wire Line + 7900 3800 9400 3800 +Connection ~ 8900 3150 +Connection ~ 8900 3800 +Wire Wire Line + 7600 3800 5450 3800 +Connection ~ 5450 3800 +$Comp +L eSim_PNP Q10 +U 1 1 684311CA +P 6050 4550 +F 0 "Q10" H 5950 4600 50 0000 R CNN +F 1 "eSim_PNP" H 6000 4700 50 0000 R CNN +F 2 "" H 6250 4650 29 0000 C CNN +F 3 "" H 6050 4550 60 0000 C CNN + 1 6050 4550 + 1 0 0 1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 684317E4 +P 9700 4900 +F 0 "#PWR02" H 9700 4650 50 0001 C CNN +F 1 "GND" H 9700 4750 50 0000 C CNN +F 2 "" H 9700 4900 50 0001 C CNN +F 3 "" H 9700 4900 50 0001 C CNN + 1 9700 4900 + 1 0 0 -1 +$EndComp +$Comp +L resistor R5 +U 1 1 68431884 +P 7400 5200 +F 0 "R5" H 7450 5330 50 0000 C CNN +F 1 "10k" H 7450 5150 50 0000 C CNN +F 2 "" H 7450 5180 30 0000 C CNN +F 3 "" V 7450 5250 30 0000 C CNN + 1 7400 5200 + 0 1 1 0 +$EndComp +Wire Wire Line + 7450 4200 7450 5100 +Wire Wire Line + 7450 4500 8600 4500 +Connection ~ 7450 4500 +Connection ~ 6150 6050 +Wire Wire Line + 7450 5400 7450 6050 +Connection ~ 7450 6050 +Connection ~ 7950 3150 +Wire Wire Line + 7950 4700 7950 6050 +Connection ~ 7950 6050 +Wire Wire Line + 8900 6050 8900 4700 +Wire Wire Line + 8900 3800 8950 3800 +Connection ~ 8950 3800 +$Comp +L PORT U1 +U 1 1 6843233A +P 4500 6450 +F 0 "U1" H 4550 6550 30 0000 C CNN +F 1 "PORT" H 4500 6450 30 0000 C CNN +F 2 "" H 4500 6450 60 0000 C CNN +F 3 "" H 4500 6450 60 0000 C CNN + 1 4500 6450 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 6843243F +P 3500 3200 +F 0 "U1" H 3550 3300 30 0000 C CNN +F 1 "PORT" H 3500 3200 30 0000 C CNN +F 2 "" H 3500 3200 60 0000 C CNN +F 3 "" H 3500 3200 60 0000 C CNN + 2 3500 3200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 6843256E +P 6950 3200 +F 0 "U1" H 7000 3300 30 0000 C CNN +F 1 "PORT" H 6950 3200 30 0000 C CNN +F 2 "" H 6950 3200 60 0000 C CNN +F 3 "" H 6950 3200 60 0000 C CNN + 3 6950 3200 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 6843262F +P 9150 6050 +F 0 "U1" H 9200 6150 30 0000 C CNN +F 1 "PORT" H 9150 6050 30 0000 C CNN +F 2 "" H 9150 6050 60 0000 C CNN +F 3 "" H 9150 6050 60 0000 C CNN + 4 9150 6050 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 684326F4 +P 5200 6450 +F 0 "U1" H 5250 6550 30 0000 C CNN +F 1 "PORT" H 5200 6450 30 0000 C CNN +F 2 "" H 5200 6450 60 0000 C CNN +F 3 "" H 5200 6450 60 0000 C CNN + 5 5200 6450 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 6 1 6843364E +P 9950 2650 +F 0 "U1" H 10000 2750 30 0000 C CNN +F 1 "PORT" H 9950 2650 30 0000 C CNN +F 2 "" H 9950 2650 60 0000 C CNN +F 3 "" H 9950 2650 60 0000 C CNN + 6 9950 2650 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 684336E9 +P 2700 900 +F 0 "U1" H 2750 1000 30 0000 C CNN +F 1 "PORT" H 2700 900 30 0000 C CNN +F 2 "" H 2700 900 60 0000 C CNN +F 3 "" H 2700 900 60 0000 C CNN + 8 2700 900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 684337BC +P 9150 1450 +F 0 "U1" H 9200 1550 30 0000 C CNN +F 1 "PORT" H 9150 1450 30 0000 C CNN +F 2 "" H 9150 1450 60 0000 C CNN +F 3 "" H 9150 1450 60 0000 C CNN + 7 9150 1450 + -1 0 0 1 +$EndComp +Wire Wire Line + 4500 6200 4500 5450 +Wire Wire Line + 4500 5450 4800 5450 +Connection ~ 4800 5450 +Wire Wire Line + 5200 6200 5200 5450 +Wire Wire Line + 5200 5450 5450 5450 +Connection ~ 5450 5450 +NoConn ~ 2950 900 +$Comp +L dc I1 +U 1 1 684318DC +P 2600 2750 +F 0 "I1" H 2400 2850 60 0000 C CNN +F 1 "dc" H 2400 2700 60 0000 C CNN +F 2 "R1" H 2300 2750 60 0000 C CNN +F 3 "" H 2600 2750 60 0000 C CNN + 1 2600 2750 + 1 0 0 -1 +$EndComp +$Comp +L dc I2 +U 1 1 684319C6 +P 9700 4450 +F 0 "I2" H 9500 4550 60 0000 C CNN +F 1 "dc" H 9500 4400 60 0000 C CNN +F 2 "R1" H 9400 4450 60 0000 C CNN +F 3 "" H 9700 4450 60 0000 C CNN + 1 9700 4450 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/MC33171/SC_MC33171.sub b/library/SubcircuitLibrary/MC33171/SC_MC33171.sub new file mode 100644 index 000000000..7d045ceab --- /dev/null +++ b/library/SubcircuitLibrary/MC33171/SC_MC33171.sub @@ -0,0 +1,43 @@ +* Subcircuit SC_MC33171 +.subckt SC_MC33171 net-_d1-pad2_ net-_q4-pad2_ net-_q11-pad2_ net-_q10-pad1_ net-_q7-pad3_ net-_q18-pad3_ net-_q1-pad3_ ? +* c:\fossee2\esim\library\subcircuitlibrary\sc_mc33171\sc_mc33171.cir +.include NPN.lib +.include PNP.lib +.include D.lib +q1 net-_i1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2907A +q3 net-_q3-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2907A +q6 net-_q6-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2907A +q9 net-_q11-pad3_ net-_q1-pad2_ net-_q1-pad3_ Q2N2907A +q12 net-_q10-pad3_ net-_q1-pad2_ net-_q1-pad3_ Q2N2907A +q14 net-_d2-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2907A +q2 net-_q10-pad1_ net-_i1-pad1_ net-_q1-pad2_ Q2N2907A +q4 net-_q10-pad1_ net-_q4-pad2_ net-_q3-pad1_ Q2N2907A +q5 net-_d1-pad1_ net-_q3-pad1_ net-_c1-pad2_ Q2N2907A +q8 net-_c2-pad2_ net-_q11-pad3_ net-_c1-pad1_ Q2N2907A +q11 net-_q10-pad1_ net-_q11-pad2_ net-_q11-pad3_ Q2N2907A +q16 net-_q1-pad3_ net-_d2-pad1_ net-_c2-pad1_ Q2N2222 +q18 net-_d2-pad1_ net-_c2-pad1_ net-_q18-pad3_ Q2N2222 +q19 net-_q19-pad1_ net-_c2-pad1_ net-_i2-pad1_ Q2N2222 +q17 net-_c2-pad1_ net-_q13-pad3_ net-_q10-pad1_ Q2N2222 +q15 net-_d2-pad2_ ? net-_q10-pad1_ Q2N2222 +q13 net-_d2-pad1_ net-_q10-pad3_ net-_q13-pad3_ Q2N2222 +q7 net-_c2-pad2_ net-_d1-pad1_ net-_q7-pad3_ Q2N2222 +c1 net-_c1-pad1_ net-_c1-pad2_ 0.8p +r1 net-_q6-pad1_ net-_c1-pad2_ 10k +r3 net-_q6-pad1_ net-_c1-pad1_ 10k +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +r2 net-_d1-pad2_ net-_q10-pad1_ 10k +r4 net-_q7-pad3_ net-_q10-pad1_ 10k +d2 net-_d2-pad1_ net-_d2-pad2_ 1N4148 +r6 net-_d2-pad2_ net-_c2-pad1_ 10k +r7 net-_c2-pad1_ net-_q18-pad3_ 10k +d3 net-_c2-pad1_ net-_d2-pad2_ 1N4148 +r8 net-_q19-pad1_ net-_q18-pad3_ 10k +c2 net-_c2-pad1_ net-_c2-pad2_ 100u +q10 net-_q10-pad1_ net-_c2-pad2_ net-_q10-pad3_ Q2N2907A +r5 net-_q13-pad3_ net-_q10-pad1_ 10k +i1 net-_i1-pad1_ gnd dc 500u +i2 net-_i2-pad1_ gnd dc 10p +* Control Statements + +.ends SC_MC33171 \ No newline at end of file diff --git a/library/SubcircuitLibrary/MC33171/SC_MC33171_Previous_Values.xml b/library/SubcircuitLibrary/MC33171/SC_MC33171_Previous_Values.xml new file mode 100644 index 000000000..5f074c99d --- /dev/null +++ b/library/SubcircuitLibrary/MC33171/SC_MC33171_Previous_Values.xml @@ -0,0 +1 @@ +dc500udc10psine010m1k00dc5dc0truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes011000ususus \ No newline at end of file From 02ee52b27b04ef2bbc925a72e356f2f86d0eabf9 Mon Sep 17 00:00:00 2001 From: Annesha Dey <142687349+AD20047@users.noreply.github.com> Date: Fri, 11 Jul 2025 23:36:58 +0530 Subject: [PATCH 5/9] MicroPower Comparator --- library/SubcircuitLibrary/TLV1701/analysis | 1 + 1 file changed, 1 insertion(+) create mode 100644 library/SubcircuitLibrary/TLV1701/analysis diff --git a/library/SubcircuitLibrary/TLV1701/analysis b/library/SubcircuitLibrary/TLV1701/analysis new file mode 100644 index 000000000..f6e0de997 --- /dev/null +++ b/library/SubcircuitLibrary/TLV1701/analysis @@ -0,0 +1 @@ +.tran 1e-06 1000e-06 0e-06 From 66d65c0ed89bc47173d1d03528bad83398ec4aa0 Mon Sep 17 00:00:00 2001 From: Annesha Dey <142687349+AD20047@users.noreply.github.com> Date: Fri, 11 Jul 2025 23:39:05 +0530 Subject: [PATCH 6/9] MicroPower Comparator --- library/SubcircuitLibrary/TLV1701/NPN.lib | 4 + library/SubcircuitLibrary/TLV1701/PNP.lib | 4 + .../TLV1701/SC_TLV1701-cache.lib | 123 ++++ .../SubcircuitLibrary/TLV1701/SC_TLV1701.cir | 42 ++ .../TLV1701/SC_TLV1701.cir.out | 45 ++ .../SubcircuitLibrary/TLV1701/SC_TLV1701.pro | 73 +++ .../SubcircuitLibrary/TLV1701/SC_TLV1701.sch | 619 ++++++++++++++++++ .../SubcircuitLibrary/TLV1701/SC_TLV1701.sub | 39 ++ .../TLV1701/SC_TLV1701_Previous_Values.xml | 1 + 9 files changed, 950 insertions(+) create mode 100644 library/SubcircuitLibrary/TLV1701/NPN.lib create mode 100644 library/SubcircuitLibrary/TLV1701/PNP.lib create mode 100644 library/SubcircuitLibrary/TLV1701/SC_TLV1701-cache.lib create mode 100644 library/SubcircuitLibrary/TLV1701/SC_TLV1701.cir create mode 100644 library/SubcircuitLibrary/TLV1701/SC_TLV1701.cir.out create mode 100644 library/SubcircuitLibrary/TLV1701/SC_TLV1701.pro create mode 100644 library/SubcircuitLibrary/TLV1701/SC_TLV1701.sch create mode 100644 library/SubcircuitLibrary/TLV1701/SC_TLV1701.sub create mode 100644 library/SubcircuitLibrary/TLV1701/SC_TLV1701_Previous_Values.xml diff --git a/library/SubcircuitLibrary/TLV1701/NPN.lib b/library/SubcircuitLibrary/TLV1701/NPN.lib new file mode 100644 index 000000000..be5f3073a --- /dev/null +++ b/library/SubcircuitLibrary/TLV1701/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/TLV1701/PNP.lib b/library/SubcircuitLibrary/TLV1701/PNP.lib new file mode 100644 index 000000000..7edda0eab --- /dev/null +++ b/library/SubcircuitLibrary/TLV1701/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/TLV1701/SC_TLV1701-cache.lib b/library/SubcircuitLibrary/TLV1701/SC_TLV1701-cache.lib new file mode 100644 index 000000000..d3e0bea24 --- /dev/null +++ b/library/SubcircuitLibrary/TLV1701/SC_TLV1701-cache.lib @@ -0,0 +1,123 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# dc +# +DEF dc I 0 40 Y Y 1 F N +F0 "I" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +P 2 0 1 0 0 -100 0 -100 N +P 2 0 1 0 0 100 -50 50 N +P 2 0 1 0 0 100 0 -100 N +P 2 0 1 0 0 100 50 50 N +X ~ 1 0 450 300 D 50 50 1 1 P +X ~ 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/TLV1701/SC_TLV1701.cir b/library/SubcircuitLibrary/TLV1701/SC_TLV1701.cir new file mode 100644 index 000000000..d0091375e --- /dev/null +++ b/library/SubcircuitLibrary/TLV1701/SC_TLV1701.cir @@ -0,0 +1,42 @@ +* C:\FOSSEE2\eSim\library\SubcircuitLibrary\SC_TLV1701\SC_TLV1701.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/07/25 13:23:03 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q1 Net-_I2-Pad2_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +Q4 Net-_I2-Pad2_ Net-_Q4-Pad2_ Net-_Q4-Pad3_ eSim_NPN +Q2 Net-_Q12-Pad3_ Net-_I1-Pad2_ Net-_I2-Pad1_ eSim_PNP +Q3 Net-_Q10-Pad3_ Net-_I3-Pad2_ Net-_I2-Pad1_ eSim_PNP +Q5 Net-_I1-Pad1_ Net-_Q1-Pad2_ Net-_Q5-Pad3_ eSim_PNP +Q8 Net-_I1-Pad1_ Net-_Q4-Pad2_ Net-_Q8-Pad3_ eSim_PNP +Q6 Net-_Q11-Pad3_ Net-_I4-Pad1_ Net-_I5-Pad2_ eSim_NPN +Q7 Net-_Q7-Pad1_ Net-_I6-Pad1_ Net-_I5-Pad2_ eSim_NPN +Q9 Net-_Q10-Pad1_ Net-_Q11-Pad2_ Net-_Q7-Pad1_ eSim_PNP +Q11 Net-_Q11-Pad1_ Net-_Q11-Pad2_ Net-_Q11-Pad3_ eSim_PNP +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN +Q12 Net-_Q11-Pad1_ Net-_Q10-Pad2_ Net-_Q12-Pad3_ eSim_NPN +Q13 Net-_I1-Pad1_ Net-_Q11-Pad1_ Net-_I7-Pad1_ eSim_PNP +Q14 Net-_I2-Pad2_ Net-_I7-Pad1_ Net-_I8-Pad2_ eSim_NPN +Q15 Net-_Q15-Pad1_ Net-_I8-Pad2_ Net-_I1-Pad1_ eSim_NPN +R1 Net-_Q1-Pad3_ Net-_I1-Pad2_ 10k +R2 Net-_Q4-Pad3_ Net-_I3-Pad2_ 10k +I2 Net-_I2-Pad1_ Net-_I2-Pad2_ dc +I1 Net-_I1-Pad1_ Net-_I1-Pad2_ dc +I3 Net-_I1-Pad1_ Net-_I3-Pad2_ dc +R3 Net-_I4-Pad1_ Net-_Q5-Pad3_ 10k +R4 Net-_I6-Pad1_ Net-_Q8-Pad3_ 10k +I5 Net-_I1-Pad1_ Net-_I5-Pad2_ dc +R5 Net-_Q10-Pad3_ Net-_I1-Pad1_ 10k +R8 Net-_I1-Pad1_ Net-_Q12-Pad3_ 10k +I8 Net-_I1-Pad1_ Net-_I8-Pad2_ dc +I4 Net-_I4-Pad1_ Net-_I2-Pad2_ dc +I6 Net-_I6-Pad1_ Net-_I2-Pad2_ dc +R6 Net-_Q7-Pad1_ Net-_I2-Pad2_ 10k +R7 Net-_I2-Pad2_ Net-_Q11-Pad3_ 10k +I7 Net-_I7-Pad1_ Net-_I2-Pad2_ dc +U1 Net-_Q1-Pad2_ Net-_I1-Pad1_ Net-_Q4-Pad2_ Net-_Q15-Pad1_ Net-_I2-Pad2_ PORT + +.end diff --git a/library/SubcircuitLibrary/TLV1701/SC_TLV1701.cir.out b/library/SubcircuitLibrary/TLV1701/SC_TLV1701.cir.out new file mode 100644 index 000000000..048dc902e --- /dev/null +++ b/library/SubcircuitLibrary/TLV1701/SC_TLV1701.cir.out @@ -0,0 +1,45 @@ +* c:\fossee2\esim\library\subcircuitlibrary\sc_tlv1701\sc_tlv1701.cir + +.include NPN.lib +.include PNP.lib +q1 net-_i2-pad2_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +q4 net-_i2-pad2_ net-_q4-pad2_ net-_q4-pad3_ Q2N2222 +q2 net-_q12-pad3_ net-_i1-pad2_ net-_i2-pad1_ Q2N2907A +q3 net-_q10-pad3_ net-_i3-pad2_ net-_i2-pad1_ Q2N2907A +q5 net-_i1-pad1_ net-_q1-pad2_ net-_q5-pad3_ Q2N2907A +q8 net-_i1-pad1_ net-_q4-pad2_ net-_q8-pad3_ Q2N2907A +q6 net-_q11-pad3_ net-_i4-pad1_ net-_i5-pad2_ Q2N2222 +q7 net-_q7-pad1_ net-_i6-pad1_ net-_i5-pad2_ Q2N2222 +q9 net-_q10-pad1_ net-_q11-pad2_ net-_q7-pad1_ Q2N2907A +q11 net-_q11-pad1_ net-_q11-pad2_ net-_q11-pad3_ Q2N2907A +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +q12 net-_q11-pad1_ net-_q10-pad2_ net-_q12-pad3_ Q2N2222 +q13 net-_i1-pad1_ net-_q11-pad1_ net-_i7-pad1_ Q2N2907A +q14 net-_i2-pad2_ net-_i7-pad1_ net-_i8-pad2_ Q2N2222 +q15 net-_q15-pad1_ net-_i8-pad2_ net-_i1-pad1_ Q2N2222 +r1 net-_q1-pad3_ net-_i1-pad2_ 10k +r2 net-_q4-pad3_ net-_i3-pad2_ 10k +i2 net-_i2-pad1_ net-_i2-pad2_ dc 55u +i1 net-_i1-pad1_ net-_i1-pad2_ dc 55u +i3 net-_i1-pad1_ net-_i3-pad2_ dc 55u +r3 net-_i4-pad1_ net-_q5-pad3_ 10k +r4 net-_i6-pad1_ net-_q8-pad3_ 10k +i5 net-_i1-pad1_ net-_i5-pad2_ dc 55u +r5 net-_q10-pad3_ net-_i1-pad1_ 10k +r8 net-_i1-pad1_ net-_q12-pad3_ 10k +i8 net-_i1-pad1_ net-_i8-pad2_ dc 55u +i4 net-_i4-pad1_ net-_i2-pad2_ dc 55u +i6 net-_i6-pad1_ net-_i2-pad2_ dc 55u +r6 net-_q7-pad1_ net-_i2-pad2_ 10k +r7 net-_i2-pad2_ net-_q11-pad3_ 10k +i7 net-_i7-pad1_ net-_i2-pad2_ dc 55u +* u1 net-_q1-pad2_ net-_i1-pad1_ net-_q4-pad2_ net-_q15-pad1_ net-_i2-pad2_ port +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/TLV1701/SC_TLV1701.pro b/library/SubcircuitLibrary/TLV1701/SC_TLV1701.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/TLV1701/SC_TLV1701.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/TLV1701/SC_TLV1701.sch b/library/SubcircuitLibrary/TLV1701/SC_TLV1701.sch new file mode 100644 index 000000000..343a6d259 --- /dev/null +++ b/library/SubcircuitLibrary/TLV1701/SC_TLV1701.sch @@ -0,0 +1,619 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SC_TLV1701-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q1 +U 1 1 6843E1AA +P 1500 3050 +F 0 "Q1" H 1400 3100 50 0000 R CNN +F 1 "eSim_NPN" H 1450 3200 50 0000 R CNN +F 2 "" H 1700 3150 29 0000 C CNN +F 3 "" H 1500 3050 60 0000 C CNN + 1 1500 3050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q4 +U 1 1 6843E21B +P 3550 3050 +F 0 "Q4" H 3450 3100 50 0000 R CNN +F 1 "eSim_NPN" H 3500 3200 50 0000 R CNN +F 2 "" H 3750 3150 29 0000 C CNN +F 3 "" H 3550 3050 60 0000 C CNN + 1 3550 3050 + -1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q2 +U 1 1 6843E266 +P 2100 3850 +F 0 "Q2" H 2000 3900 50 0000 R CNN +F 1 "eSim_PNP" H 2050 4000 50 0000 R CNN +F 2 "" H 2300 3950 29 0000 C CNN +F 3 "" H 2100 3850 60 0000 C CNN + 1 2100 3850 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q3 +U 1 1 6843E2D6 +P 3000 3900 +F 0 "Q3" H 2900 3950 50 0000 R CNN +F 1 "eSim_PNP" H 2950 4050 50 0000 R CNN +F 2 "" H 3200 4000 29 0000 C CNN +F 3 "" H 3000 3900 60 0000 C CNN + 1 3000 3900 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q5 +U 1 1 6843E303 +P 4400 4650 +F 0 "Q5" H 4300 4700 50 0000 R CNN +F 1 "eSim_PNP" H 4350 4800 50 0000 R CNN +F 2 "" H 4600 4750 29 0000 C CNN +F 3 "" H 4400 4650 60 0000 C CNN + 1 4400 4650 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q8 +U 1 1 6843E34E +P 6050 4700 +F 0 "Q8" H 5950 4750 50 0000 R CNN +F 1 "eSim_PNP" H 6000 4850 50 0000 R CNN +F 2 "" H 6250 4800 29 0000 C CNN +F 3 "" H 6050 4700 60 0000 C CNN + 1 6050 4700 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q6 +U 1 1 6843E3E2 +P 5050 3750 +F 0 "Q6" H 4950 3800 50 0000 R CNN +F 1 "eSim_NPN" H 5000 3900 50 0000 R CNN +F 2 "" H 5250 3850 29 0000 C CNN +F 3 "" H 5050 3750 60 0000 C CNN + 1 5050 3750 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q7 +U 1 1 6843E45D +P 5700 3750 +F 0 "Q7" H 5600 3800 50 0000 R CNN +F 1 "eSim_NPN" H 5650 3900 50 0000 R CNN +F 2 "" H 5900 3850 29 0000 C CNN +F 3 "" H 5700 3750 60 0000 C CNN + 1 5700 3750 + -1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q9 +U 1 1 6843E4A2 +P 7100 2750 +F 0 "Q9" H 7000 2800 50 0000 R CNN +F 1 "eSim_PNP" H 7050 2900 50 0000 R CNN +F 2 "" H 7300 2850 29 0000 C CNN +F 3 "" H 7100 2750 60 0000 C CNN + 1 7100 2750 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q11 +U 1 1 6843E54D +P 7850 2750 +F 0 "Q11" H 7750 2800 50 0000 R CNN +F 1 "eSim_PNP" H 7800 2900 50 0000 R CNN +F 2 "" H 8050 2850 29 0000 C CNN +F 3 "" H 7850 2750 60 0000 C CNN + 1 7850 2750 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q10 +U 1 1 6843E590 +P 7100 4700 +F 0 "Q10" H 7000 4750 50 0000 R CNN +F 1 "eSim_NPN" H 7050 4850 50 0000 R CNN +F 2 "" H 7300 4800 29 0000 C CNN +F 3 "" H 7100 4700 60 0000 C CNN + 1 7100 4700 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q12 +U 1 1 6843E5E5 +P 7850 4700 +F 0 "Q12" H 7750 4750 50 0000 R CNN +F 1 "eSim_NPN" H 7800 4850 50 0000 R CNN +F 2 "" H 8050 4800 29 0000 C CNN +F 3 "" H 7850 4700 60 0000 C CNN + 1 7850 4700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q13 +U 1 1 6843E62E +P 8550 4000 +F 0 "Q13" H 8450 4050 50 0000 R CNN +F 1 "eSim_PNP" H 8500 4150 50 0000 R CNN +F 2 "" H 8750 4100 29 0000 C CNN +F 3 "" H 8550 4000 60 0000 C CNN + 1 8550 4000 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q14 +U 1 1 6843E671 +P 9150 3250 +F 0 "Q14" H 9050 3300 50 0000 R CNN +F 1 "eSim_NPN" H 9100 3400 50 0000 R CNN +F 2 "" H 9350 3350 29 0000 C CNN +F 3 "" H 9150 3250 60 0000 C CNN + 1 9150 3250 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q15 +U 1 1 6843E6C0 +P 9850 4200 +F 0 "Q15" H 9750 4250 50 0000 R CNN +F 1 "eSim_NPN" H 9800 4350 50 0000 R CNN +F 2 "" H 10050 4300 29 0000 C CNN +F 3 "" H 9850 4200 60 0000 C CNN + 1 9850 4200 + 1 0 0 -1 +$EndComp +$Comp +L resistor R1 +U 1 1 6843E71E +P 1550 3550 +F 0 "R1" H 1600 3680 50 0000 C CNN +F 1 "10k" H 1600 3500 50 0000 C CNN +F 2 "" H 1600 3530 30 0000 C CNN +F 3 "" V 1600 3600 30 0000 C CNN + 1 1550 3550 + 0 1 1 0 +$EndComp +$Comp +L resistor R2 +U 1 1 6843E785 +P 3400 3500 +F 0 "R2" H 3450 3630 50 0000 C CNN +F 1 "10k" H 3450 3450 50 0000 C CNN +F 2 "" H 3450 3480 30 0000 C CNN +F 3 "" V 3450 3550 30 0000 C CNN + 1 3400 3500 + 0 1 1 0 +$EndComp +$Comp +L dc I2 +U 1 1 6843E8AE +P 2600 2150 +F 0 "I2" H 2400 2250 60 0000 C CNN +F 1 "dc" H 2400 2100 60 0000 C CNN +F 2 "R1" H 2300 2150 60 0000 C CNN +F 3 "" H 2600 2150 60 0000 C CNN + 1 2600 2150 + -1 0 0 1 +$EndComp +$Comp +L dc I1 +U 1 1 6843E95D +P 1600 5650 +F 0 "I1" H 1400 5750 60 0000 C CNN +F 1 "dc" H 1400 5600 60 0000 C CNN +F 2 "R1" H 1300 5650 60 0000 C CNN +F 3 "" H 1600 5650 60 0000 C CNN + 1 1600 5650 + -1 0 0 1 +$EndComp +$Comp +L dc I3 +U 1 1 6843E9BA +P 3450 5650 +F 0 "I3" H 3250 5750 60 0000 C CNN +F 1 "dc" H 3250 5600 60 0000 C CNN +F 2 "R1" H 3150 5650 60 0000 C CNN +F 3 "" H 3450 5650 60 0000 C CNN + 1 3450 5650 + -1 0 0 1 +$EndComp +$Comp +L resistor R3 +U 1 1 6843EB7B +P 4450 4150 +F 0 "R3" H 4500 4280 50 0000 C CNN +F 1 "10k" H 4500 4100 50 0000 C CNN +F 2 "" H 4500 4130 30 0000 C CNN +F 3 "" V 4500 4200 30 0000 C CNN + 1 4450 4150 + 0 1 1 0 +$EndComp +$Comp +L resistor R4 +U 1 1 6843EBE6 +P 5900 4200 +F 0 "R4" H 5950 4330 50 0000 C CNN +F 1 "10k" H 5950 4150 50 0000 C CNN +F 2 "" H 5950 4180 30 0000 C CNN +F 3 "" V 5950 4250 30 0000 C CNN + 1 5900 4200 + 0 1 1 0 +$EndComp +$Comp +L dc I5 +U 1 1 6843EC3F +P 5350 5600 +F 0 "I5" H 5150 5700 60 0000 C CNN +F 1 "dc" H 5150 5550 60 0000 C CNN +F 2 "R1" H 5050 5600 60 0000 C CNN +F 3 "" H 5350 5600 60 0000 C CNN + 1 5350 5600 + -1 0 0 1 +$EndComp +$Comp +L resistor R5 +U 1 1 6843ECB2 +P 6950 5550 +F 0 "R5" H 7000 5680 50 0000 C CNN +F 1 "10k" H 7000 5500 50 0000 C CNN +F 2 "" H 7000 5530 30 0000 C CNN +F 3 "" V 7000 5600 30 0000 C CNN + 1 6950 5550 + 0 1 1 0 +$EndComp +$Comp +L resistor R8 +U 1 1 6843ED0D +P 8000 5600 +F 0 "R8" H 8050 5730 50 0000 C CNN +F 1 "10k" H 8050 5550 50 0000 C CNN +F 2 "" H 8050 5580 30 0000 C CNN +F 3 "" V 8050 5650 30 0000 C CNN + 1 8000 5600 + 0 -1 -1 0 +$EndComp +$Comp +L dc I8 +U 1 1 6843ED76 +P 9250 5650 +F 0 "I8" H 9050 5750 60 0000 C CNN +F 1 "dc" H 9050 5600 60 0000 C CNN +F 2 "R1" H 8950 5650 60 0000 C CNN +F 3 "" H 9250 5650 60 0000 C CNN + 1 9250 5650 + -1 0 0 1 +$EndComp +$Comp +L dc I4 +U 1 1 6843EDF9 +P 4500 2400 +F 0 "I4" H 4300 2500 60 0000 C CNN +F 1 "dc" H 4300 2350 60 0000 C CNN +F 2 "R1" H 4200 2400 60 0000 C CNN +F 3 "" H 4500 2400 60 0000 C CNN + 1 4500 2400 + -1 0 0 1 +$EndComp +$Comp +L dc I6 +U 1 1 6843EE62 +P 5950 2350 +F 0 "I6" H 5750 2450 60 0000 C CNN +F 1 "dc" H 5750 2300 60 0000 C CNN +F 2 "R1" H 5650 2350 60 0000 C CNN +F 3 "" H 5950 2350 60 0000 C CNN + 1 5950 2350 + -1 0 0 1 +$EndComp +$Comp +L resistor R6 +U 1 1 6843EEBB +P 7050 2250 +F 0 "R6" H 7100 2380 50 0000 C CNN +F 1 "10k" H 7100 2200 50 0000 C CNN +F 2 "" H 7100 2230 30 0000 C CNN +F 3 "" V 7100 2300 30 0000 C CNN + 1 7050 2250 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R7 +U 1 1 6843EF1A +P 7900 2200 +F 0 "R7" H 7950 2330 50 0000 C CNN +F 1 "10k" H 7950 2150 50 0000 C CNN +F 2 "" H 7950 2180 30 0000 C CNN +F 3 "" V 7950 2250 30 0000 C CNN + 1 7900 2200 + 0 1 1 0 +$EndComp +$Comp +L dc I7 +U 1 1 6843EF77 +P 8650 2650 +F 0 "I7" H 8450 2750 60 0000 C CNN +F 1 "dc" H 8450 2600 60 0000 C CNN +F 2 "R1" H 8350 2650 60 0000 C CNN +F 3 "" H 8650 2650 60 0000 C CNN + 1 8650 2650 + -1 0 0 1 +$EndComp +Wire Wire Line + 1600 3250 1600 3450 +Wire Wire Line + 1600 3750 1600 5200 +Wire Wire Line + 1600 3850 1900 3850 +Wire Wire Line + 3450 3700 3450 5200 +Wire Wire Line + 3450 3900 3200 3900 +Wire Wire Line + 3450 3250 3450 3400 +Wire Wire Line + 2200 3650 2200 3250 +Wire Wire Line + 2200 3250 2900 3250 +Wire Wire Line + 2900 3250 2900 3700 +Wire Wire Line + 2600 2600 2600 3250 +Connection ~ 2600 3250 +Connection ~ 1600 3850 +Connection ~ 3450 3900 +Wire Wire Line + 1600 6100 9950 6100 +Wire Wire Line + 1600 2850 1600 1700 +Wire Wire Line + 1600 1700 9250 1700 +Wire Wire Line + 3450 1700 3450 2850 +Connection ~ 2600 1700 +Wire Wire Line + 4500 1700 4500 1950 +Connection ~ 3450 1700 +Wire Wire Line + 4500 2850 4500 4050 +Wire Wire Line + 4850 3750 4500 3750 +Connection ~ 4500 3750 +Wire Wire Line + 4500 4350 4500 4450 +Wire Wire Line + 4500 6100 4500 4850 +Connection ~ 3450 6100 +Wire Wire Line + 5150 3950 5150 4250 +Wire Wire Line + 5150 4250 5600 4250 +Wire Wire Line + 5600 4250 5600 3950 +Wire Wire Line + 5350 5150 5350 4250 +Connection ~ 5350 4250 +Wire Wire Line + 5350 6100 5350 6050 +Connection ~ 4500 6100 +Wire Wire Line + 5950 1700 5950 1900 +Connection ~ 4500 1700 +Wire Wire Line + 5950 2800 5950 4100 +Wire Wire Line + 5900 3750 5950 3750 +Connection ~ 5950 3750 +Wire Wire Line + 5950 4400 5950 4500 +Wire Wire Line + 5950 6100 5950 4900 +Connection ~ 5350 6100 +Wire Wire Line + 7000 4900 7000 5450 +Wire Wire Line + 7950 4900 7950 5400 +Wire Wire Line + 7000 6100 7000 5750 +Connection ~ 5950 6100 +Wire Wire Line + 7950 6100 7950 5700 +Connection ~ 7000 6100 +Wire Wire Line + 7000 1700 7000 2050 +Connection ~ 5950 1700 +Wire Wire Line + 7950 1700 7950 2100 +Connection ~ 7000 1700 +Wire Wire Line + 7000 2350 7000 2550 +Wire Wire Line + 7950 2400 7950 2550 +Wire Wire Line + 7300 2750 7650 2750 +Wire Wire Line + 7000 4500 7000 2950 +Wire Wire Line + 7950 2950 7950 4500 +Wire Wire Line + 7300 4700 7650 4700 +Wire Wire Line + 8350 4000 7950 4000 +Connection ~ 7950 4000 +Wire Wire Line + 8650 1700 8650 2200 +Connection ~ 7950 1700 +Wire Wire Line + 8650 3800 8650 3100 +Wire Wire Line + 8650 6100 8650 4200 +Connection ~ 7950 6100 +Wire Wire Line + 9250 5200 9250 3450 +Wire Wire Line + 8950 3250 8650 3250 +Connection ~ 8650 3250 +Connection ~ 8650 6100 +Wire Wire Line + 9650 4200 9250 4200 +Connection ~ 9250 4200 +Wire Wire Line + 9950 6100 9950 4400 +Connection ~ 9250 6100 +Wire Wire Line + 9250 1700 9250 3050 +Connection ~ 8650 1700 +Wire Wire Line + 5150 3550 5150 2000 +Wire Wire Line + 5150 2000 7650 2000 +Wire Wire Line + 7650 2000 7650 2500 +Wire Wire Line + 7650 2500 7950 2500 +Connection ~ 7950 2500 +Wire Wire Line + 5600 3550 5600 2900 +Wire Wire Line + 5600 2900 6700 2900 +Wire Wire Line + 6700 2900 6700 2500 +Wire Wire Line + 6700 2500 7000 2500 +Connection ~ 7000 2500 +Wire Wire Line + 2900 4100 2900 5000 +Wire Wire Line + 2900 5000 7000 5000 +Connection ~ 7000 5000 +Wire Wire Line + 2200 4050 2200 5150 +Wire Wire Line + 2200 5150 7950 5150 +Connection ~ 7950 5150 +Wire Wire Line + 1300 3050 1300 4650 +Wire Wire Line + 1300 4650 4200 4650 +Wire Wire Line + 3750 3050 6250 3050 +Wire Wire Line + 6250 3050 6250 4700 +$Comp +L PORT U1 +U 1 1 684430F3 +P 1050 4650 +F 0 "U1" H 1100 4750 30 0000 C CNN +F 1 "PORT" H 1050 4650 30 0000 C CNN +F 2 "" H 1050 4650 60 0000 C CNN +F 3 "" H 1050 4650 60 0000 C CNN + 1 1050 4650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 6844326D +P 6500 3050 +F 0 "U1" H 6550 3150 30 0000 C CNN +F 1 "PORT" H 6500 3050 30 0000 C CNN +F 2 "" H 6500 3050 60 0000 C CNN +F 3 "" H 6500 3050 60 0000 C CNN + 3 6500 3050 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 68443318 +P 9950 3750 +F 0 "U1" H 10000 3850 30 0000 C CNN +F 1 "PORT" H 9950 3750 30 0000 C CNN +F 2 "" H 9950 3750 60 0000 C CNN +F 3 "" H 9950 3750 60 0000 C CNN + 4 9950 3750 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 5 1 684433CD +P 5850 1250 +F 0 "U1" H 5900 1350 30 0000 C CNN +F 1 "PORT" H 5850 1250 30 0000 C CNN +F 2 "" H 5850 1250 60 0000 C CNN +F 3 "" H 5850 1250 60 0000 C CNN + 5 5850 1250 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 68443779 +P 6100 6500 +F 0 "U1" H 6150 6600 30 0000 C CNN +F 1 "PORT" H 6100 6500 30 0000 C CNN +F 2 "" H 6100 6500 60 0000 C CNN +F 3 "" H 6100 6500 60 0000 C CNN + 2 6100 6500 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 6100 6250 6100 6100 +Connection ~ 6100 6100 +Wire Wire Line + 5850 1500 5850 1700 +Connection ~ 5850 1700 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/TLV1701/SC_TLV1701.sub b/library/SubcircuitLibrary/TLV1701/SC_TLV1701.sub new file mode 100644 index 000000000..fab725164 --- /dev/null +++ b/library/SubcircuitLibrary/TLV1701/SC_TLV1701.sub @@ -0,0 +1,39 @@ +* Subcircuit SC_TLV1701 +.subckt SC_TLV1701 net-_q1-pad2_ net-_i1-pad1_ net-_q4-pad2_ net-_q15-pad1_ net-_i2-pad2_ +* c:\fossee2\esim\library\subcircuitlibrary\sc_tlv1701\sc_tlv1701.cir +.include NPN.lib +.include PNP.lib +q1 net-_i2-pad2_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +q4 net-_i2-pad2_ net-_q4-pad2_ net-_q4-pad3_ Q2N2222 +q2 net-_q12-pad3_ net-_i1-pad2_ net-_i2-pad1_ Q2N2907A +q3 net-_q10-pad3_ net-_i3-pad2_ net-_i2-pad1_ Q2N2907A +q5 net-_i1-pad1_ net-_q1-pad2_ net-_q5-pad3_ Q2N2907A +q8 net-_i1-pad1_ net-_q4-pad2_ net-_q8-pad3_ Q2N2907A +q6 net-_q11-pad3_ net-_i4-pad1_ net-_i5-pad2_ Q2N2222 +q7 net-_q7-pad1_ net-_i6-pad1_ net-_i5-pad2_ Q2N2222 +q9 net-_q10-pad1_ net-_q11-pad2_ net-_q7-pad1_ Q2N2907A +q11 net-_q11-pad1_ net-_q11-pad2_ net-_q11-pad3_ Q2N2907A +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +q12 net-_q11-pad1_ net-_q10-pad2_ net-_q12-pad3_ Q2N2222 +q13 net-_i1-pad1_ net-_q11-pad1_ net-_i7-pad1_ Q2N2907A +q14 net-_i2-pad2_ net-_i7-pad1_ net-_i8-pad2_ Q2N2222 +q15 net-_q15-pad1_ net-_i8-pad2_ net-_i1-pad1_ Q2N2222 +r1 net-_q1-pad3_ net-_i1-pad2_ 10k +r2 net-_q4-pad3_ net-_i3-pad2_ 10k +i2 net-_i2-pad1_ net-_i2-pad2_ dc 55u +i1 net-_i1-pad1_ net-_i1-pad2_ dc 55u +i3 net-_i1-pad1_ net-_i3-pad2_ dc 55u +r3 net-_i4-pad1_ net-_q5-pad3_ 10k +r4 net-_i6-pad1_ net-_q8-pad3_ 10k +i5 net-_i1-pad1_ net-_i5-pad2_ dc 55u +r5 net-_q10-pad3_ net-_i1-pad1_ 10k +r8 net-_i1-pad1_ net-_q12-pad3_ 10k +i8 net-_i1-pad1_ net-_i8-pad2_ dc 55u +i4 net-_i4-pad1_ net-_i2-pad2_ dc 55u +i6 net-_i6-pad1_ net-_i2-pad2_ dc 55u +r6 net-_q7-pad1_ net-_i2-pad2_ 10k +r7 net-_i2-pad2_ net-_q11-pad3_ 10k +i7 net-_i7-pad1_ net-_i2-pad2_ dc 55u +* Control Statements + +.ends SC_TLV1701 \ No newline at end of file diff --git a/library/SubcircuitLibrary/TLV1701/SC_TLV1701_Previous_Values.xml b/library/SubcircuitLibrary/TLV1701/SC_TLV1701_Previous_Values.xml new file mode 100644 index 000000000..e3d650818 --- /dev/null +++ b/library/SubcircuitLibrary/TLV1701/SC_TLV1701_Previous_Values.xml @@ -0,0 +1 @@ +dc55udc55udc55udc55udc55udc55udc55udc55uC:\FOSSEE2\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE2\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE2\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE2\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE2\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE2\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE2\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE2\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE2\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE2\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE2\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE2\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE2\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE2\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE2\eSim\library\deviceModelLibrary\Transistor\NPN.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes010100msmsms \ No newline at end of file From 35d14d454b81df8b60c64830caed0067aea42cca Mon Sep 17 00:00:00 2001 From: Annesha Dey <142687349+AD20047@users.noreply.github.com> Date: Fri, 11 Jul 2025 23:40:11 +0530 Subject: [PATCH 7/9] AND-GATED J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR --- library/SubcircuitLibrary/SN7470/analysis | 1 + 1 file changed, 1 insertion(+) create mode 100644 library/SubcircuitLibrary/SN7470/analysis diff --git a/library/SubcircuitLibrary/SN7470/analysis b/library/SubcircuitLibrary/SN7470/analysis new file mode 100644 index 000000000..155ea4753 --- /dev/null +++ b/library/SubcircuitLibrary/SN7470/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-03 From 46b4dddd6febead3a579d959ca1fb9623d988072 Mon Sep 17 00:00:00 2001 From: Annesha Dey <142687349+AD20047@users.noreply.github.com> Date: Fri, 11 Jul 2025 23:42:05 +0530 Subject: [PATCH 8/9] AND-GATED J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS (WITH PRESET AND CLEAR) --- library/SubcircuitLibrary/SN7470/NPN.lib | 4 + .../SN7470/SC_SN7470-cache.lib | 146 ++++ .../SubcircuitLibrary/SN7470/SC_SN7470.cir | 38 + .../SN7470/SC_SN7470.cir.out | 99 +++ .../SubcircuitLibrary/SN7470/SC_SN7470.pro | 73 ++ .../SubcircuitLibrary/SN7470/SC_SN7470.sch | 720 ++++++++++++++++++ .../SubcircuitLibrary/SN7470/SC_SN7470.sub | 93 +++ .../SN7470/SC_SN7470_Previous_Values.xml | 1 + 8 files changed, 1174 insertions(+) create mode 100644 library/SubcircuitLibrary/SN7470/NPN.lib create mode 100644 library/SubcircuitLibrary/SN7470/SC_SN7470-cache.lib create mode 100644 library/SubcircuitLibrary/SN7470/SC_SN7470.cir create mode 100644 library/SubcircuitLibrary/SN7470/SC_SN7470.cir.out create mode 100644 library/SubcircuitLibrary/SN7470/SC_SN7470.pro create mode 100644 library/SubcircuitLibrary/SN7470/SC_SN7470.sch create mode 100644 library/SubcircuitLibrary/SN7470/SC_SN7470.sub create mode 100644 library/SubcircuitLibrary/SN7470/SC_SN7470_Previous_Values.xml diff --git a/library/SubcircuitLibrary/SN7470/NPN.lib b/library/SubcircuitLibrary/SN7470/NPN.lib new file mode 100644 index 000000000..be5f3073a --- /dev/null +++ b/library/SubcircuitLibrary/SN7470/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/SN7470/SC_SN7470-cache.lib b/library/SubcircuitLibrary/SN7470/SC_SN7470-cache.lib new file mode 100644 index 000000000..cfa3c8b96 --- /dev/null +++ b/library/SubcircuitLibrary/SN7470/SC_SN7470-cache.lib @@ -0,0 +1,146 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "4_and" 100 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 206 760 -760 0 1 0 N 150 200 150 -200 +P 2 0 1 0 -200 200 150 200 N +P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N +X in1 1 -400 150 200 R 50 50 1 1 I +X in2 2 -400 50 200 R 50 50 1 1 I +X in3 3 -400 -50 200 R 50 50 1 1 I +X in4 4 -400 -150 200 R 50 50 1 1 I +X out 5 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# dac_bridge_1 +# +DEF dac_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN7470/SC_SN7470.cir b/library/SubcircuitLibrary/SN7470/SC_SN7470.cir new file mode 100644 index 000000000..99786f159 --- /dev/null +++ b/library/SubcircuitLibrary/SN7470/SC_SN7470.cir @@ -0,0 +1,38 @@ +* C:\FOSSEE2\eSim\library\SubcircuitLibrary\SC_SN7470\SC_SN7470.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/06/25 17:08:36 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X4 Net-_U4-Pad1_ Net-_U12-Pad1_ Net-_U1-Pad2_ Net-_U15-Pad1_ 3_and +X2 Net-_U1-Pad13_ Net-_U10-Pad1_ Net-_U15-Pad2_ Net-_U6-Pad1_ 3_and +U15 Net-_U15-Pad1_ Net-_U15-Pad2_ d_inverter +U6 Net-_U6-Pad1_ Net-_U4-Pad1_ d_inverter +X3 Net-_U12-Pad1_ Net-_U7-Pad2_ Net-_U4-Pad1_ Net-_U8-Pad1_ 3_and +X5 Net-_U15-Pad2_ Net-_U16-Pad2_ Net-_U10-Pad1_ Net-_U13-Pad1_ 3_and +U11 Net-_U1-Pad12_ Net-_U11-Pad2_ d_inverter +U4 Net-_U4-Pad1_ Net-_U1-Pad6_ d_inverter +U17 Net-_U15-Pad2_ Net-_U1-Pad8_ d_inverter +X6 Net-_U1-Pad3_ Net-_U1-Pad2_ Net-_U1-Pad6_ Net-_U12-Pad1_ Net-_U18-Pad2_ 4_and +U19 Net-_U19-Pad1_ Net-_U1-Pad4_ Net-_U18-Pad1_ d_and +U20 Net-_U1-Pad5_ Net-_U19-Pad1_ d_inverter +U18 Net-_U18-Pad1_ Net-_U18-Pad2_ Net-_U16-Pad1_ d_and +X1 Net-_U1-Pad10_ Net-_U1-Pad13_ Net-_U1-Pad8_ Net-_U10-Pad1_ Net-_U5-Pad2_ 4_and +U3 Net-_U2-Pad2_ Net-_U1-Pad11_ Net-_U3-Pad3_ d_and +U2 Net-_U1-Pad9_ Net-_U2-Pad2_ d_inverter +U5 Net-_U3-Pad3_ Net-_U5-Pad2_ Net-_U5-Pad3_ d_and +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +Q2 Net-_Q2-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN +U1 ? Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ ? Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT +U7 Net-_U5-Pad3_ Net-_U7-Pad2_ d_inverter +U16 Net-_U16-Pad1_ Net-_U16-Pad2_ d_inverter +U8 Net-_U8-Pad1_ Net-_Q1-Pad2_ dac_bridge_1 +U13 Net-_U13-Pad1_ Net-_Q2-Pad2_ dac_bridge_1 +U9 Net-_U11-Pad2_ Net-_Q1-Pad3_ dac_bridge_1 +U10 Net-_U10-Pad1_ Net-_Q1-Pad1_ dac_bridge_1 +U14 Net-_U11-Pad2_ Net-_Q2-Pad3_ dac_bridge_1 +U12 Net-_U12-Pad1_ Net-_Q2-Pad1_ dac_bridge_1 + +.end diff --git a/library/SubcircuitLibrary/SN7470/SC_SN7470.cir.out b/library/SubcircuitLibrary/SN7470/SC_SN7470.cir.out new file mode 100644 index 000000000..ec8f451ab --- /dev/null +++ b/library/SubcircuitLibrary/SN7470/SC_SN7470.cir.out @@ -0,0 +1,99 @@ +* c:\fossee2\esim\library\subcircuitlibrary\sc_sn7470\sc_sn7470.cir + +.include 3_and.sub +.include 4_and.sub +.include NPN.lib +x4 net-_u4-pad1_ net-_u12-pad1_ net-_u1-pad2_ net-_u15-pad1_ 3_and +x2 net-_u1-pad13_ net-_u10-pad1_ net-_u15-pad2_ net-_u6-pad1_ 3_and +* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter +* u6 net-_u6-pad1_ net-_u4-pad1_ d_inverter +x3 net-_u12-pad1_ net-_u7-pad2_ net-_u4-pad1_ net-_u8-pad1_ 3_and +x5 net-_u15-pad2_ net-_u16-pad2_ net-_u10-pad1_ net-_u13-pad1_ 3_and +* u11 net-_u1-pad12_ net-_u11-pad2_ d_inverter +* u4 net-_u4-pad1_ net-_u1-pad6_ d_inverter +* u17 net-_u15-pad2_ net-_u1-pad8_ d_inverter +x6 net-_u1-pad3_ net-_u1-pad2_ net-_u1-pad6_ net-_u12-pad1_ net-_u18-pad2_ 4_and +* u19 net-_u19-pad1_ net-_u1-pad4_ net-_u18-pad1_ d_and +* u20 net-_u1-pad5_ net-_u19-pad1_ d_inverter +* u18 net-_u18-pad1_ net-_u18-pad2_ net-_u16-pad1_ d_and +x1 net-_u1-pad10_ net-_u1-pad13_ net-_u1-pad8_ net-_u10-pad1_ net-_u5-pad2_ 4_and +* u3 net-_u2-pad2_ net-_u1-pad11_ net-_u3-pad3_ d_and +* u2 net-_u1-pad9_ net-_u2-pad2_ d_inverter +* u5 net-_u3-pad3_ net-_u5-pad2_ net-_u5-pad3_ d_and +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222 +* u1 ? net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port +* u7 net-_u5-pad3_ net-_u7-pad2_ d_inverter +* u16 net-_u16-pad1_ net-_u16-pad2_ d_inverter +* u8 net-_u8-pad1_ net-_q1-pad2_ dac_bridge_1 +* u13 net-_u13-pad1_ net-_q2-pad2_ dac_bridge_1 +* u9 net-_u11-pad2_ net-_q1-pad3_ dac_bridge_1 +* u10 net-_u10-pad1_ net-_q1-pad1_ dac_bridge_1 +* u14 net-_u11-pad2_ net-_q2-pad3_ dac_bridge_1 +* u12 net-_u12-pad1_ net-_q2-pad1_ dac_bridge_1 +a1 net-_u15-pad1_ net-_u15-pad2_ u15 +a2 net-_u6-pad1_ net-_u4-pad1_ u6 +a3 net-_u1-pad12_ net-_u11-pad2_ u11 +a4 net-_u4-pad1_ net-_u1-pad6_ u4 +a5 net-_u15-pad2_ net-_u1-pad8_ u17 +a6 [net-_u19-pad1_ net-_u1-pad4_ ] net-_u18-pad1_ u19 +a7 net-_u1-pad5_ net-_u19-pad1_ u20 +a8 [net-_u18-pad1_ net-_u18-pad2_ ] net-_u16-pad1_ u18 +a9 [net-_u2-pad2_ net-_u1-pad11_ ] net-_u3-pad3_ u3 +a10 net-_u1-pad9_ net-_u2-pad2_ u2 +a11 [net-_u3-pad3_ net-_u5-pad2_ ] net-_u5-pad3_ u5 +a12 net-_u5-pad3_ net-_u7-pad2_ u7 +a13 net-_u16-pad1_ net-_u16-pad2_ u16 +a14 [net-_u8-pad1_ ] [net-_q1-pad2_ ] u8 +a15 [net-_u13-pad1_ ] [net-_q2-pad2_ ] u13 +a16 [net-_u11-pad2_ ] [net-_q1-pad3_ ] u9 +a17 [net-_u10-pad1_ ] [net-_q1-pad1_ ] u10 +a18 [net-_u11-pad2_ ] [net-_q2-pad3_ ] u14 +a19 [net-_u12-pad1_ ] [net-_q2-pad1_ ] u12 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u8 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u13 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u9 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u10 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u14 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u12 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN7470/SC_SN7470.pro b/library/SubcircuitLibrary/SN7470/SC_SN7470.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/SN7470/SC_SN7470.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN7470/SC_SN7470.sch b/library/SubcircuitLibrary/SN7470/SC_SN7470.sch new file mode 100644 index 000000000..0c6d1e026 --- /dev/null +++ b/library/SubcircuitLibrary/SN7470/SC_SN7470.sch @@ -0,0 +1,720 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SC_SN7470-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and X4 +U 1 1 6857B960 +P 6700 1600 +F 0 "X4" H 6800 1550 60 0000 C CNN +F 1 "3_and" H 6850 1750 60 0000 C CNN +F 2 "" H 6700 1600 60 0000 C CNN +F 3 "" H 6700 1600 60 0000 C CNN + 1 6700 1600 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X2 +U 1 1 6857B9A5 +P 4350 1500 +F 0 "X2" H 4450 1450 60 0000 C CNN +F 1 "3_and" H 4500 1650 60 0000 C CNN +F 2 "" H 4350 1500 60 0000 C CNN +F 3 "" H 4350 1500 60 0000 C CNN + 1 4350 1500 + -1 0 0 1 +$EndComp +$Comp +L d_inverter U15 +U 1 1 6857BA26 +P 7500 1550 +F 0 "U15" H 7500 1450 60 0000 C CNN +F 1 "d_inverter" H 7500 1700 60 0000 C CNN +F 2 "" H 7550 1500 60 0000 C CNN +F 3 "" H 7550 1500 60 0000 C CNN + 1 7500 1550 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 6857BBA1 +P 3550 1550 +F 0 "U6" H 3550 1450 60 0000 C CNN +F 1 "d_inverter" H 3550 1700 60 0000 C CNN +F 2 "" H 3600 1500 60 0000 C CNN +F 3 "" H 3600 1500 60 0000 C CNN + 1 3550 1550 + -1 0 0 1 +$EndComp +$Comp +L 3_and X3 +U 1 1 6857BBE4 +P 4350 4250 +F 0 "X3" H 4450 4200 60 0000 C CNN +F 1 "3_and" H 4500 4400 60 0000 C CNN +F 2 "" H 4350 4250 60 0000 C CNN +F 3 "" H 4350 4250 60 0000 C CNN + 1 4350 4250 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X5 +U 1 1 6857BC13 +P 6900 4150 +F 0 "X5" H 7000 4100 60 0000 C CNN +F 1 "3_and" H 7050 4300 60 0000 C CNN +F 2 "" H 6900 4150 60 0000 C CNN +F 3 "" H 6900 4150 60 0000 C CNN + 1 6900 4150 + -1 0 0 1 +$EndComp +$Comp +L d_inverter U11 +U 1 1 6857BC62 +P 5600 5150 +F 0 "U11" H 5600 5050 60 0000 C CNN +F 1 "d_inverter" H 5600 5300 60 0000 C CNN +F 2 "" H 5650 5100 60 0000 C CNN +F 3 "" H 5650 5100 60 0000 C CNN + 1 5600 5150 + 0 -1 -1 0 +$EndComp +$Comp +L d_inverter U4 +U 1 1 6857BCAF +P 2500 1550 +F 0 "U4" H 2500 1450 60 0000 C CNN +F 1 "d_inverter" H 2500 1700 60 0000 C CNN +F 2 "" H 2550 1500 60 0000 C CNN +F 3 "" H 2550 1500 60 0000 C CNN + 1 2500 1550 + -1 0 0 1 +$EndComp +$Comp +L d_inverter U17 +U 1 1 6857BDC2 +P 8550 1550 +F 0 "U17" H 8550 1450 60 0000 C CNN +F 1 "d_inverter" H 8550 1700 60 0000 C CNN +F 2 "" H 8600 1500 60 0000 C CNN +F 3 "" H 8600 1500 60 0000 C CNN + 1 8550 1550 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X6 +U 1 1 6857BE92 +P 9800 3950 +F 0 "X6" H 9850 3900 60 0000 C CNN +F 1 "4_and" H 9900 4050 60 0000 C CNN +F 2 "" H 9800 3950 60 0000 C CNN +F 3 "" H 9800 3950 60 0000 C CNN + 1 9800 3950 + -1 0 0 1 +$EndComp +$Comp +L d_and U19 +U 1 1 6857BECF +P 9750 4500 +F 0 "U19" H 9750 4500 60 0000 C CNN +F 1 "d_and" H 9800 4600 60 0000 C CNN +F 2 "" H 9750 4500 60 0000 C CNN +F 3 "" H 9750 4500 60 0000 C CNN + 1 9750 4500 + -1 0 0 1 +$EndComp +$Comp +L d_inverter U20 +U 1 1 6857BF20 +P 10200 4900 +F 0 "U20" H 10200 4800 60 0000 C CNN +F 1 "d_inverter" H 10200 5050 60 0000 C CNN +F 2 "" H 10250 4850 60 0000 C CNN +F 3 "" H 10250 4850 60 0000 C CNN + 1 10200 4900 + 0 -1 -1 0 +$EndComp +$Comp +L d_and U18 +U 1 1 6857BF81 +P 8700 4150 +F 0 "U18" H 8700 4150 60 0000 C CNN +F 1 "d_and" H 8750 4250 60 0000 C CNN +F 2 "" H 8700 4150 60 0000 C CNN +F 3 "" H 8700 4150 60 0000 C CNN + 1 8700 4150 + -1 0 0 1 +$EndComp +$Comp +L 4_and X1 +U 1 1 6857C773 +P 2150 3950 +F 0 "X1" H 2200 3900 60 0000 C CNN +F 1 "4_and" H 2250 4050 60 0000 C CNN +F 2 "" H 2150 3950 60 0000 C CNN +F 3 "" H 2150 3950 60 0000 C CNN + 1 2150 3950 + 1 0 0 1 +$EndComp +$Comp +L d_and U3 +U 1 1 6857C77A +P 2200 4500 +F 0 "U3" H 2200 4500 60 0000 C CNN +F 1 "d_and" H 2250 4600 60 0000 C CNN +F 2 "" H 2200 4500 60 0000 C CNN +F 3 "" H 2200 4500 60 0000 C CNN + 1 2200 4500 + 1 0 0 1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 6857C781 +P 1750 4900 +F 0 "U2" H 1750 4800 60 0000 C CNN +F 1 "d_inverter" H 1750 5050 60 0000 C CNN +F 2 "" H 1800 4850 60 0000 C CNN +F 3 "" H 1800 4850 60 0000 C CNN + 1 1750 4900 + 0 1 -1 0 +$EndComp +$Comp +L d_and U5 +U 1 1 6857C788 +P 3250 4150 +F 0 "U5" H 3250 4150 60 0000 C CNN +F 1 "d_and" H 3300 4250 60 0000 C CNN +F 2 "" H 3250 4150 60 0000 C CNN +F 3 "" H 3250 4150 60 0000 C CNN + 1 3250 4150 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q1 +U 1 1 6857CC11 +P 5200 4200 +F 0 "Q1" H 5100 4250 50 0000 R CNN +F 1 "eSim_NPN" H 5150 4350 50 0000 R CNN +F 2 "" H 5400 4300 29 0000 C CNN +F 3 "" H 5200 4200 60 0000 C CNN + 1 5200 4200 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 6857CC6A +P 6050 4200 +F 0 "Q2" H 5950 4250 50 0000 R CNN +F 1 "eSim_NPN" H 6000 4350 50 0000 R CNN +F 2 "" H 6250 4300 29 0000 C CNN +F 3 "" H 6050 4200 60 0000 C CNN + 1 6050 4200 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 68584475 +P 2400 5450 +F 0 "U1" H 2450 5550 30 0000 C CNN +F 1 "PORT" H 2400 5450 30 0000 C CNN +F 2 "" H 2400 5450 60 0000 C CNN +F 3 "" H 2400 5450 60 0000 C CNN + 1 2400 5450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 685844CE +P 10900 2300 +F 0 "U1" H 10950 2400 30 0000 C CNN +F 1 "PORT" H 10900 2300 30 0000 C CNN +F 2 "" H 10900 2300 60 0000 C CNN +F 3 "" H 10900 2300 60 0000 C CNN + 2 10900 2300 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 68584593 +P 10450 4100 +F 0 "U1" H 10500 4200 30 0000 C CNN +F 1 "PORT" H 10450 4100 30 0000 C CNN +F 2 "" H 10450 4100 60 0000 C CNN +F 3 "" H 10450 4100 60 0000 C CNN + 3 10450 4100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 685845FA +P 10450 4500 +F 0 "U1" H 10500 4600 30 0000 C CNN +F 1 "PORT" H 10450 4500 30 0000 C CNN +F 2 "" H 10450 4500 60 0000 C CNN +F 3 "" H 10450 4500 60 0000 C CNN + 4 10450 4500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 68584667 +P 10200 5450 +F 0 "U1" H 10250 5550 30 0000 C CNN +F 1 "PORT" H 10200 5450 30 0000 C CNN +F 2 "" H 10200 5450 60 0000 C CNN +F 3 "" H 10200 5450 60 0000 C CNN + 5 10200 5450 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 6 1 68584712 +P 1700 1550 +F 0 "U1" H 1750 1650 30 0000 C CNN +F 1 "PORT" H 1700 1550 30 0000 C CNN +F 2 "" H 1700 1550 60 0000 C CNN +F 3 "" H 1700 1550 60 0000 C CNN + 6 1700 1550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 68584779 +P 2400 5800 +F 0 "U1" H 2450 5900 30 0000 C CNN +F 1 "PORT" H 2400 5800 30 0000 C CNN +F 2 "" H 2400 5800 60 0000 C CNN +F 3 "" H 2400 5800 60 0000 C CNN + 7 2400 5800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 68584826 +P 9600 1550 +F 0 "U1" H 9650 1650 30 0000 C CNN +F 1 "PORT" H 9600 1550 30 0000 C CNN +F 2 "" H 9600 1550 60 0000 C CNN +F 3 "" H 9600 1550 60 0000 C CNN + 8 9600 1550 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 9 1 68584900 +P 1500 5200 +F 0 "U1" H 1550 5300 30 0000 C CNN +F 1 "PORT" H 1500 5200 30 0000 C CNN +F 2 "" H 1500 5200 60 0000 C CNN +F 3 "" H 1500 5200 60 0000 C CNN + 9 1500 5200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 68584999 +P 1500 4100 +F 0 "U1" H 1550 4200 30 0000 C CNN +F 1 "PORT" H 1500 4100 30 0000 C CNN +F 2 "" H 1500 4100 60 0000 C CNN +F 3 "" H 1500 4100 60 0000 C CNN + 10 1500 4100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 68584A0A +P 1500 4500 +F 0 "U1" H 1550 4600 30 0000 C CNN +F 1 "PORT" H 1500 4500 30 0000 C CNN +F 2 "" H 1500 4500 60 0000 C CNN +F 3 "" H 1500 4500 60 0000 C CNN + 11 1500 4500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 68584AA7 +P 5600 5700 +F 0 "U1" H 5650 5800 30 0000 C CNN +F 1 "PORT" H 5600 5700 30 0000 C CNN +F 2 "" H 5600 5700 60 0000 C CNN +F 3 "" H 5600 5700 60 0000 C CNN + 12 5600 5700 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 13 1 68584B43 +P 1400 2100 +F 0 "U1" H 1450 2200 30 0000 C CNN +F 1 "PORT" H 1400 2100 30 0000 C CNN +F 2 "" H 1400 2100 60 0000 C CNN +F 3 "" H 1400 2100 60 0000 C CNN + 13 1400 2100 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 14 1 68584C1C +P 2400 6250 +F 0 "U1" H 2450 6350 30 0000 C CNN +F 1 "PORT" H 2400 6250 30 0000 C CNN +F 2 "" H 2400 6250 60 0000 C CNN +F 3 "" H 2400 6250 60 0000 C CNN + 14 2400 6250 + 1 0 0 -1 +$EndComp +NoConn ~ 2650 5450 +NoConn ~ 2650 5800 +NoConn ~ 2650 6250 +$Comp +L d_inverter U7 +U 1 1 685A556D +P 3850 4800 +F 0 "U7" H 3850 4700 60 0000 C CNN +F 1 "d_inverter" H 3850 4950 60 0000 C CNN +F 2 "" H 3900 4750 60 0000 C CNN +F 3 "" H 3900 4750 60 0000 C CNN + 1 3850 4800 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U16 +U 1 1 685A55DC +P 7950 4200 +F 0 "U16" H 7950 4100 60 0000 C CNN +F 1 "d_inverter" H 7950 4350 60 0000 C CNN +F 2 "" H 8000 4150 60 0000 C CNN +F 3 "" H 8000 4150 60 0000 C CNN + 1 7950 4200 + -1 0 0 1 +$EndComp +$Comp +L dac_bridge_1 U8 +U 1 1 68651899 +P 4500 5450 +F 0 "U8" H 4500 5450 60 0000 C CNN +F 1 "dac_bridge_1" H 4500 5600 60 0000 C CNN +F 2 "" H 4500 5450 60 0000 C CNN +F 3 "" H 4500 5450 60 0000 C CNN + 1 4500 5450 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U13 +U 1 1 6865192E +P 6750 5300 +F 0 "U13" H 6750 5300 60 0000 C CNN +F 1 "dac_bridge_1" H 6750 5450 60 0000 C CNN +F 2 "" H 6750 5300 60 0000 C CNN +F 3 "" H 6750 5300 60 0000 C CNN + 1 6750 5300 + -1 0 0 1 +$EndComp +$Comp +L dac_bridge_1 U9 +U 1 1 686519B5 +P 4500 6050 +F 0 "U9" H 4500 6050 60 0000 C CNN +F 1 "dac_bridge_1" H 4500 6200 60 0000 C CNN +F 2 "" H 4500 6050 60 0000 C CNN +F 3 "" H 4500 6050 60 0000 C CNN + 1 4500 6050 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U10 +U 1 1 68651BE2 +P 4500 6600 +F 0 "U10" H 4500 6600 60 0000 C CNN +F 1 "dac_bridge_1" H 4500 6750 60 0000 C CNN +F 2 "" H 4500 6600 60 0000 C CNN +F 3 "" H 4500 6600 60 0000 C CNN + 1 4500 6600 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U14 +U 1 1 68651C63 +P 6900 6100 +F 0 "U14" H 6900 6100 60 0000 C CNN +F 1 "dac_bridge_1" H 6900 6250 60 0000 C CNN +F 2 "" H 6900 6100 60 0000 C CNN +F 3 "" H 6900 6100 60 0000 C CNN + 1 6900 6100 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U12 +U 1 1 68651CF2 +P 6700 6450 +F 0 "U12" H 6700 6450 60 0000 C CNN +F 1 "dac_bridge_1" H 6700 6600 60 0000 C CNN +F 2 "" H 6700 6450 60 0000 C CNN +F 3 "" H 6700 6450 60 0000 C CNN + 1 6700 6450 + -1 0 0 1 +$EndComp +Wire Wire Line + 3650 4850 6100 4850 +Connection ~ 5600 4850 +Wire Wire Line + 4700 1550 5150 1550 +Wire Wire Line + 6350 1550 6100 1550 +Wire Wire Line + 2650 3950 2800 3950 +Wire Wire Line + 2800 3950 2800 4150 +Wire Wire Line + 2800 4250 2800 4550 +Wire Wire Line + 2800 4550 2650 4550 +Wire Wire Line + 2800 1550 3250 1550 +Wire Wire Line + 9150 4150 9150 3950 +Wire Wire Line + 9150 3950 9300 3950 +Wire Wire Line + 9150 4250 9150 4550 +Wire Wire Line + 9150 4550 9300 4550 +Wire Wire Line + 7800 1550 8250 1550 +Wire Wire Line + 7250 4100 7350 4100 +Wire Wire Line + 7350 4100 7350 3700 +Wire Wire Line + 7350 3700 900 3700 +Wire Wire Line + 4000 4100 4000 3400 +Wire Wire Line + 4000 3400 11050 3400 +Connection ~ 6100 3400 +Wire Wire Line + 5150 3100 1750 3100 +Wire Wire Line + 1750 3100 1750 3800 +Connection ~ 5150 3100 +Wire Wire Line + 1750 3900 1500 3900 +Wire Wire Line + 1500 3900 1500 2500 +Wire Wire Line + 1500 2500 8900 2500 +Wire Wire Line + 10200 3800 10200 3250 +Wire Wire Line + 10200 3250 6100 3250 +Connection ~ 6100 3250 +Wire Wire Line + 10200 3900 10350 3900 +Wire Wire Line + 10350 3900 10350 2800 +Wire Wire Line + 10350 2800 2100 2800 +Wire Wire Line + 4700 1650 4700 2400 +Wire Wire Line + 4700 2400 1400 2400 +Wire Wire Line + 1400 2350 1400 4000 +Wire Wire Line + 1400 4000 1750 4000 +Wire Wire Line + 6350 1650 6350 2300 +Wire Wire Line + 6350 2300 10650 2300 +Wire Wire Line + 10550 2300 10550 4000 +Wire Wire Line + 10550 4000 10200 4000 +Wire Wire Line + 4700 1450 5500 1450 +Wire Wire Line + 5500 1450 5500 950 +Wire Wire Line + 5500 950 7900 950 +Wire Wire Line + 7900 950 7900 1550 +Connection ~ 7900 1550 +Wire Wire Line + 6350 1450 5700 1450 +Wire Wire Line + 5700 1450 5700 850 +Wire Wire Line + 5700 850 3000 850 +Wire Wire Line + 3000 850 3000 1550 +Connection ~ 3000 1550 +Wire Wire Line + 7250 4300 8000 4300 +Wire Wire Line + 8000 4300 8000 1550 +Connection ~ 8000 1550 +Wire Wire Line + 4000 4300 3750 4300 +Wire Wire Line + 3750 4300 3750 2150 +Wire Wire Line + 3750 2150 2850 2150 +Wire Wire Line + 2850 2150 2850 1550 +Connection ~ 2850 1550 +Wire Wire Line + 8850 1550 9350 1550 +Wire Wire Line + 8900 2500 8900 1550 +Connection ~ 8900 1550 +Wire Wire Line + 1950 1550 2200 1550 +Wire Wire Line + 2100 2800 2100 1550 +Connection ~ 2100 1550 +Wire Wire Line + 7650 4200 7250 4200 +Wire Wire Line + 3550 4800 3550 4450 +Wire Wire Line + 3550 4450 3700 4450 +Wire Wire Line + 3700 4450 3700 4200 +Wire Wire Line + 4000 4200 4000 4500 +Wire Wire Line + 4000 4500 4150 4500 +Wire Wire Line + 4150 4500 4150 4800 +Wire Wire Line + 4750 4400 5300 4400 +Wire Wire Line + 5950 4400 7550 4400 +Wire Wire Line + 3500 4000 5300 4000 +Connection ~ 5150 3700 +Wire Wire Line + 3900 5400 3900 5000 +Wire Wire Line + 3900 5000 4850 5000 +Wire Wire Line + 4850 5000 4850 4200 +Wire Wire Line + 5000 4200 5000 5000 +Wire Wire Line + 5000 5000 5050 5000 +Wire Wire Line + 5050 5000 5050 5400 +Wire Wire Line + 6250 4200 6250 5200 +Wire Wire Line + 6250 5200 6200 5200 +Wire Wire Line + 6200 5200 6200 5350 +Wire Wire Line + 6400 4200 6400 5150 +Wire Wire Line + 6400 5150 7350 5150 +Wire Wire Line + 7350 5150 7350 5350 +Wire Wire Line + 4750 4400 4750 5100 +Wire Wire Line + 4750 5100 5150 5100 +Wire Wire Line + 5150 5100 5150 6000 +Wire Wire Line + 5150 6000 5050 6000 +Wire Wire Line + 3650 4850 3650 6000 +Wire Wire Line + 3650 6000 3900 6000 +Wire Wire Line + 5150 1550 5150 3700 +Wire Wire Line + 900 3700 900 6550 +Wire Wire Line + 900 6550 3900 6550 +Wire Wire Line + 3500 6250 5050 6250 +Wire Wire Line + 5050 6250 5050 6550 +Wire Wire Line + 6100 4850 6100 6050 +Wire Wire Line + 6100 6050 6300 6050 +Wire Wire Line + 7550 4400 7550 6050 +Wire Wire Line + 7550 6050 7450 6050 +Wire Wire Line + 6100 1550 6100 3400 +Wire Wire Line + 5700 6500 6150 6500 +Wire Wire Line + 5700 4000 5950 4000 +Wire Wire Line + 11050 3400 11050 6500 +Wire Wire Line + 11050 6500 7300 6500 +Connection ~ 10550 2300 +Connection ~ 1400 2400 +Wire Wire Line + 5700 4000 5700 6500 +Wire Wire Line + 3500 4000 3500 6250 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN7470/SC_SN7470.sub b/library/SubcircuitLibrary/SN7470/SC_SN7470.sub new file mode 100644 index 000000000..111bba9a1 --- /dev/null +++ b/library/SubcircuitLibrary/SN7470/SC_SN7470.sub @@ -0,0 +1,93 @@ +* Subcircuit SC_SN7470 +.subckt SC_SN7470 ? net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? +* c:\fossee2\esim\library\subcircuitlibrary\sc_sn7470\sc_sn7470.cir +.include 3_and.sub +.include 4_and.sub +.include NPN.lib +x4 net-_u4-pad1_ net-_u12-pad1_ net-_u1-pad2_ net-_u15-pad1_ 3_and +x2 net-_u1-pad13_ net-_u10-pad1_ net-_u15-pad2_ net-_u6-pad1_ 3_and +* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter +* u6 net-_u6-pad1_ net-_u4-pad1_ d_inverter +x3 net-_u12-pad1_ net-_u7-pad2_ net-_u4-pad1_ net-_u8-pad1_ 3_and +x5 net-_u15-pad2_ net-_u16-pad2_ net-_u10-pad1_ net-_u13-pad1_ 3_and +* u11 net-_u1-pad12_ net-_u11-pad2_ d_inverter +* u4 net-_u4-pad1_ net-_u1-pad6_ d_inverter +* u17 net-_u15-pad2_ net-_u1-pad8_ d_inverter +x6 net-_u1-pad3_ net-_u1-pad2_ net-_u1-pad6_ net-_u12-pad1_ net-_u18-pad2_ 4_and +* u19 net-_u19-pad1_ net-_u1-pad4_ net-_u18-pad1_ d_and +* u20 net-_u1-pad5_ net-_u19-pad1_ d_inverter +* u18 net-_u18-pad1_ net-_u18-pad2_ net-_u16-pad1_ d_and +x1 net-_u1-pad10_ net-_u1-pad13_ net-_u1-pad8_ net-_u10-pad1_ net-_u5-pad2_ 4_and +* u3 net-_u2-pad2_ net-_u1-pad11_ net-_u3-pad3_ d_and +* u2 net-_u1-pad9_ net-_u2-pad2_ d_inverter +* u5 net-_u3-pad3_ net-_u5-pad2_ net-_u5-pad3_ d_and +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222 +* u7 net-_u5-pad3_ net-_u7-pad2_ d_inverter +* u16 net-_u16-pad1_ net-_u16-pad2_ d_inverter +* u8 net-_u8-pad1_ net-_q1-pad2_ dac_bridge_1 +* u13 net-_u13-pad1_ net-_q2-pad2_ dac_bridge_1 +* u9 net-_u11-pad2_ net-_q1-pad3_ dac_bridge_1 +* u10 net-_u10-pad1_ net-_q1-pad1_ dac_bridge_1 +* u14 net-_u11-pad2_ net-_q2-pad3_ dac_bridge_1 +* u12 net-_u12-pad1_ net-_q2-pad1_ dac_bridge_1 +a1 net-_u15-pad1_ net-_u15-pad2_ u15 +a2 net-_u6-pad1_ net-_u4-pad1_ u6 +a3 net-_u1-pad12_ net-_u11-pad2_ u11 +a4 net-_u4-pad1_ net-_u1-pad6_ u4 +a5 net-_u15-pad2_ net-_u1-pad8_ u17 +a6 [net-_u19-pad1_ net-_u1-pad4_ ] net-_u18-pad1_ u19 +a7 net-_u1-pad5_ net-_u19-pad1_ u20 +a8 [net-_u18-pad1_ net-_u18-pad2_ ] net-_u16-pad1_ u18 +a9 [net-_u2-pad2_ net-_u1-pad11_ ] net-_u3-pad3_ u3 +a10 net-_u1-pad9_ net-_u2-pad2_ u2 +a11 [net-_u3-pad3_ net-_u5-pad2_ ] net-_u5-pad3_ u5 +a12 net-_u5-pad3_ net-_u7-pad2_ u7 +a13 net-_u16-pad1_ net-_u16-pad2_ u16 +a14 [net-_u8-pad1_ ] [net-_q1-pad2_ ] u8 +a15 [net-_u13-pad1_ ] [net-_q2-pad2_ ] u13 +a16 [net-_u11-pad2_ ] [net-_q1-pad3_ ] u9 +a17 [net-_u10-pad1_ ] [net-_q1-pad1_ ] u10 +a18 [net-_u11-pad2_ ] [net-_q2-pad3_ ] u14 +a19 [net-_u12-pad1_ ] [net-_q2-pad1_ ] u12 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u8 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u13 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u9 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u10 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u14 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u12 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Control Statements + +.ends SC_SN7470 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN7470/SC_SN7470_Previous_Values.xml b/library/SubcircuitLibrary/SN7470/SC_SN7470_Previous_Values.xml new file mode 100644 index 000000000..5d56ac333 --- /dev/null +++ b/library/SubcircuitLibrary/SN7470/SC_SN7470_Previous_Values.xml @@ -0,0 +1 @@ +d_inverterd_inverterd_inverterd_inverterd_inverterd_andd_inverterd_andd_andd_inverterd_andd_inverterd_andd_inverterd_andd_inverterd_inverterd_inverterd_andd_inverterd_andd_inverterdac_bridgedac_bridgedac_bridgedac_bridgedac_bridgedac_bridgeC:\FOSSEE2\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE2\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_andC:\FOSSEE2\eSim\library\SubcircuitLibrary\4_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes010100msmsms \ No newline at end of file From ffc7a0bb75fc596237223082d8951b162d005392 Mon Sep 17 00:00:00 2001 From: Annesha Dey <142687349+AD20047@users.noreply.github.com> Date: Fri, 11 Jul 2025 23:50:25 +0530 Subject: [PATCH 9/9] Contains IC symbols --- library/SubcircuitLibrary/eSim_Subckt.lib | 2672 ++++++++++++--------- 1 file changed, 1486 insertions(+), 1186 deletions(-) diff --git a/library/SubcircuitLibrary/eSim_Subckt.lib b/library/SubcircuitLibrary/eSim_Subckt.lib index 56cddf041..d3f839be7 100644 --- a/library/SubcircuitLibrary/eSim_Subckt.lib +++ b/library/SubcircuitLibrary/eSim_Subckt.lib @@ -1,1186 +1,1486 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# 10bitDAC -# -DEF 10bitDAC X 0 40 Y Y 1 F N -F0 "X" 0 50 60 H V C CNN -F1 "10bitDAC" -50 -50 60 H V C CNN -F2 "" 0 50 60 H I C CNN -F3 "" 0 50 60 H I C CNN -DRAW -S -500 500 400 -600 0 1 0 N -X D0 1 -700 -500 200 R 50 50 1 1 I -X D1 2 -700 -400 200 R 50 50 1 1 I -X D2 3 -700 -300 200 R 50 50 1 1 I -X D3 4 -700 -200 200 R 50 50 1 1 I -X D4 5 -700 -100 200 R 50 50 1 1 I -X D5 6 -700 0 200 R 50 50 1 1 I -X D6 7 -700 100 200 R 50 50 1 1 I -X D7 8 -700 200 200 R 50 50 1 1 I -X D8 9 -700 300 200 R 50 50 1 1 I -X D9 10 -700 400 200 R 50 50 1 1 I -X AnalogOut 11 600 350 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# 2BITMUL -# -DEF 2BITMUL X 0 40 Y Y 1 F N -F0 "X" 0 0 60 H V C CNN -F1 "2BITMUL" 0 0 60 H V C CNN -F2 "" 0 0 60 H I C CNN -F3 "" 0 0 60 H I C CNN -DRAW -S -300 400 300 -400 0 1 0 N -X A0 1 -500 300 200 R 50 50 1 1 I -X A1 2 -500 150 200 R 50 50 1 1 I -X B0 3 -500 -50 200 R 50 50 1 1 I -X B1 4 -500 -250 200 R 50 50 1 1 I -X M0 5 500 250 200 L 50 50 1 1 O -X M1 6 500 100 200 L 50 50 1 1 O -X M2 7 500 -50 200 L 50 50 1 1 O -X M3 8 500 -250 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# 3_and -# -DEF 3_and X 0 40 Y Y 1 F N -F0 "X" 100 -50 60 H V C CNN -F1 "3_and" 150 150 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 -P 2 0 1 0 -150 200 200 200 N -P 3 0 1 0 -150 200 -150 -100 200 -100 N -X in1 1 -350 150 200 R 50 50 1 1 I -X in2 2 -350 50 200 R 50 50 1 1 I -X in3 3 -350 -50 200 R 50 50 1 1 I -X out 4 500 50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# 4_OR -# -DEF 4_OR X 0 40 Y Y 1 F N -F0 "X" 150 -100 60 H V C CNN -F1 "4_OR" 150 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250 -A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0 -A -30 -99 393 627 146 0 1 0 N 150 250 350 0 -P 2 0 1 0 -200 -250 150 -250 N -P 2 0 1 0 -200 250 150 250 N -X in1 1 -350 150 200 R 50 50 1 1 I -X in2 2 -350 50 200 R 50 50 1 1 I -X in3 3 -350 -50 200 R 50 50 1 1 I -X in4 4 -350 -150 200 R 50 50 1 1 I -X out 5 550 0 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# 4_and -# -DEF 4_and X 0 40 Y Y 1 F N -F0 "X" 50 -50 60 H V C CNN -F1 "4_and" 100 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 100 0 206 760 -760 0 1 0 N 150 200 150 -200 -P 2 0 1 0 -200 200 150 200 N -P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N -X in1 1 -400 150 200 R 50 50 1 1 I -X in2 2 -400 50 200 R 50 50 1 1 I -X in3 3 -400 -50 200 R 50 50 1 1 I -X in4 4 -400 -150 200 R 50 50 1 1 I -X out 5 500 0 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# 556 -# -DEF 556 X 0 40 Y Y 1 F N -F0 "X" 0 0 60 H V C CNN -F1 "556" 0 0 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -S -300 400 250 -550 0 1 0 N -X dis1 1 -500 150 200 R 50 50 1 1 I -X thr1 2 -500 -150 200 R 50 50 1 1 I -X cv1 3 -150 -750 200 U 50 50 1 1 I -X rst1 4 -200 600 200 D 50 50 1 1 I -X out1 5 -500 0 200 R 50 50 1 1 O -X trig1 6 -500 -300 200 R 50 50 1 1 I -X gnd 7 0 -750 200 U 50 50 1 1 I -X trig2 8 450 -300 200 L 50 50 1 1 I -X out2 9 450 0 200 L 50 50 1 1 O -X rst2 10 100 600 200 D 50 50 1 1 I -X cv2 11 150 -750 200 U 50 50 1 1 I -X thr2 12 450 -150 200 L 50 50 1 1 I -X dis2 13 450 150 200 L 50 50 1 1 I -X vcc 14 -50 600 200 D 50 50 1 1 I -ENDDRAW -ENDDEF -# -# 5_and -# -DEF 5_and X 0 40 Y Y 1 F N -F0 "X" 50 -100 60 H V C CNN -F1 "5_and" 100 150 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 100 0 255 787 -787 0 1 0 N 150 250 150 -250 -P 2 0 1 0 -250 250 150 250 N -P 3 0 1 0 -250 250 -250 -250 150 -250 N -X in1 1 -450 200 200 R 50 50 1 1 I -X in2 2 -450 100 200 R 50 50 1 1 I -X in3 3 -450 0 200 R 50 50 1 1 I -X in4 4 -450 -100 200 R 50 50 1 1 I -X in5 5 -450 -200 200 R 50 50 1 1 I -X out 6 550 0 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# 74HC194 -# -DEF 74HC194 X 0 40 Y Y 1 F N -F0 "X" 50 300 60 H V C CNN -F1 "74HC194" 50 550 60 H V C CNN -F2 "" 50 300 60 H I C CNN -F3 "" 50 300 60 H I C CNN -DRAW -A 0 1350 100 -1799 -1 0 1 0 N -100 1350 100 1350 -S -400 1350 450 -750 0 1 0 N -X MR_bar 1 -600 1200 200 R 50 50 1 1 I -X DSR 2 -600 950 200 R 50 50 1 1 I -X D0 3 -600 700 200 R 50 50 1 1 I -X D1 4 -600 450 200 R 50 50 1 1 I -X D2 5 -600 200 200 R 50 50 1 1 I -X D3 6 -600 -50 200 R 50 50 1 1 I -X DSL 7 -600 -300 200 R 50 50 1 1 I -X GND 8 -600 -550 200 R 50 50 1 1 I -X S0 9 650 -550 200 L 50 50 1 1 I -X S1 10 650 -300 200 L 50 50 1 1 I -X CP 11 650 -50 200 L 50 50 1 1 I -X Q3 12 650 200 200 L 50 50 1 1 O -X Q2 13 650 450 200 L 50 50 1 1 O -X Q1 14 650 700 200 L 50 50 1 1 O -X Q0 15 650 950 200 L 50 50 1 1 O -X VCC 16 650 1200 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# AN1186 -# -DEF AN1186 X 0 40 Y Y 1 F N -F0 "X" 0 -100 60 H V C CNN -F1 "AN1186" -50 400 60 H V C CNN -F2 "" -50 400 60 H I C CNN -F3 "" -50 400 60 H I C CNN -DRAW -S -350 350 250 -350 0 1 0 N -X Clk 1 -550 300 200 R 50 50 1 1 I -X rst 2 -550 200 200 R 50 50 1 1 I -X data_in 3 -550 100 200 R 50 50 1 1 I -X q0 4 -550 0 200 R 50 50 1 1 O -X q1 5 -550 -100 200 R 50 50 1 1 O -X q2 6 -550 -200 200 R 50 50 1 1 O -X Gnd 7 -550 -300 200 R 50 50 1 1 I -X q3 8 450 -300 200 L 50 50 1 1 O -X q4 9 450 -200 200 L 50 50 1 1 O -X q5 10 450 -100 200 L 50 50 1 1 O -X q6 11 450 0 200 L 50 50 1 1 O -X q7 12 450 100 200 L 50 50 1 1 O -X NC 13 450 200 200 L 50 50 1 1 I -X Vcc 14 450 300 200 L 50 50 1 1 I -ENDDRAW -ENDDEF -# -# AN1186_CRC -# -DEF AN1186_CRC U 0 40 Y Y 1 F N -F0 "U" 0 -100 60 H V C CNN -F1 "AN1186_CRC" -50 400 60 H V C CNN -F2 "" -50 400 60 H I C CNN -F3 "" -50 400 60 H I C CNN -DRAW -S -350 350 250 -350 0 1 0 N -X Clk 1 -550 300 200 R 50 50 1 1 I -X rst 2 -550 200 200 R 50 50 1 1 I -X data_in 3 -550 100 200 R 50 50 1 1 I -X q0 4 -550 0 200 R 50 50 1 1 O -X q1 5 -550 -100 200 R 50 50 1 1 O -X q2 6 -550 -200 200 R 50 50 1 1 O -X Gnd 7 -550 -300 200 R 50 50 1 1 I -X q3 8 450 -300 200 L 50 50 1 1 O -X q4 9 450 -200 200 L 50 50 1 1 O -X q5 10 450 -100 200 L 50 50 1 1 O -X q6 11 450 0 200 L 50 50 1 1 O -X q7 12 450 100 200 L 50 50 1 1 O -X NC 13 450 200 200 L 50 50 1 1 I -X Vcc 14 450 300 200 L 50 50 1 1 I -ENDDRAW -ENDDEF -# -# AN1186_CRC_Gen -# -DEF AN1186_CRC_Gen X 0 40 Y Y 1 F N -F0 "X" 0 -100 60 H V C CNN -F1 "AN1186_CRC_Gen" 0 400 60 H V C CNN -F2 "" 0 -100 60 H I C CNN -F3 "" 0 -100 60 H I C CNN -DRAW -S -300 350 250 -400 0 1 0 N -X Clk 1 -500 250 200 R 50 50 1 1 I -X Rst 2 -500 150 200 R 50 50 1 1 I -X Data_in 3 -500 50 200 R 50 50 1 1 I -X q0 4 -500 -50 200 R 50 50 1 1 O -X q1 5 -500 -150 200 R 50 50 1 1 O -X q2 6 -500 -250 200 R 50 50 1 1 O -X Gnd 7 -500 -350 200 R 50 50 1 1 I -X q3 8 450 -350 200 L 50 50 1 1 O -X q4 9 450 -250 200 L 50 50 1 1 O -X q5 10 450 -150 200 L 50 50 1 1 O -X q6 11 450 -50 200 L 50 50 1 1 O -X q7 12 450 50 200 L 50 50 1 1 O -X NC 13 450 150 200 L 50 50 1 1 I -X Vcc 14 450 250 200 L 50 50 1 1 I -ENDDRAW -ENDDEF -# -# Bidirectional_switch -# -DEF Bidirectional_switch X 0 40 Y Y 1 F N -F0 "X" -150 -200 60 H V C CNN -F1 "Bidirectional_switch" 50 0 60 H V C CNN -F2 "" 50 0 60 H I C CNN -F3 "" 50 0 60 H I C CNN -DRAW -P 2 0 1 0 150 -250 500 -250 N -P 3 0 1 0 -400 -250 -100 -250 150 -100 N -X ~ 1 -550 -250 200 R 50 50 1 1 B -X ~ 2 700 -250 200 L 50 50 1 1 B -X ~ 3 -100 -450 200 U 50 50 1 1 B -ENDDRAW -ENDDEF -# -# CBTL02043A -# -DEF CBTL02043A X 0 40 Y Y 1 F N -F0 "X" 1550 750 60 H V C CNN -F1 "CBTL02043A" 1550 850 60 H V C CNN -F2 "" 1550 850 60 H I C CNN -F3 "" 1550 850 60 H I C CNN -DRAW -S 1200 800 1850 -250 0 1 0 N -X Vdd 1 1000 700 200 R 50 50 1 1 I -X XSD 2 1000 600 200 R 50 50 1 1 I -X A0_P 3 1000 500 200 R 50 50 1 1 B -X A0_N 4 1000 400 200 R 50 50 1 1 B -X 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-650 50 200 R 50 50 1 1 I -X Kb 7 -650 -100 200 R 50 50 1 1 I -X VSS 8 -650 -250 200 R 50 50 1 1 I -X Kc 9 600 -250 200 L 50 50 1 1 I -X Ka 10 600 -100 200 L 50 50 1 1 I -X D 11 600 50 200 L 50 50 1 1 I -X C 12 600 200 200 L 50 50 1 1 I -X B 13 600 350 200 L 50 50 1 1 I -X A 14 600 500 200 L 50 50 1 1 I -X Expand 15 600 650 200 L 50 50 1 1 I -X VDD 16 600 800 200 L 50 50 1 1 I -ENDDRAW -ENDDEF -# -# CMOS_NAND -# -DEF CMOS_NAND X 0 40 Y Y 1 F N -F0 "X" -100 -150 60 H V C CNN -F1 "CMOS_NAND" 0 -50 60 H V C CNN -F2 "" 0 0 60 H I C CNN -F3 "" 0 0 60 H I C CNN -DRAW -A 150 -50 381 668 -668 0 1 0 N 300 300 300 -400 -C 550 0 50 0 1 0 N -P 2 0 1 0 -350 300 300 300 N -P 3 0 1 0 -350 300 -350 -400 300 -400 N -X in1 1 -550 250 200 R 50 50 1 1 I -X in2 2 -550 -300 200 R 50 50 1 1 I -X out 3 800 0 279 L 79 79 1 1 I -ENDDRAW -ENDDEF -# -# Clock_pulse_generator -# -DEF Clock_pulse_generator X 0 40 Y Y 1 F N -F0 "X" 0 0 60 H V C CNN -F1 "Clock_pulse_generator" 0 -100 60 H V C CNN -F2 "" 0 0 60 H I C CNN -F3 "" 0 0 60 H I C CNN -DRAW -S -550 200 600 -300 0 1 0 N -X Vdd 1 -750 100 200 R 50 50 1 1 I -X R 2 -750 -50 200 R 50 50 1 1 I -X C 3 -750 -200 200 R 50 50 1 1 I -X Clkout 4 800 0 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# DFF -# -DEF DFF X 0 40 Y Y 1 F N -F0 "X" 0 0 60 H V C CNN -F1 "DFF" 0 100 60 H V C CNN -F2 "" 0 0 60 H I C CNN -F3 "" 0 0 60 H I C CNN -DRAW -S -550 750 550 -500 0 1 0 N -X D 1 -750 550 200 R 50 50 1 1 I -X CLK 2 -750 -250 200 R 50 50 1 1 I -X SET 3 0 950 200 D 50 50 1 1 I -X RESET 4 0 -700 200 U 50 50 1 1 I -X Q 5 750 550 200 L 50 50 1 1 O -X Q_bar 6 750 -250 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# IC-LM3900 -# -DEF IC-LM3900 X 0 40 Y Y 1 F N -F0 "X" 0 -300 60 H V C CNN -F1 "IC-LM3900" 0 -200 60 H V C CNN -F2 "" 0 -200 60 H I C CNN -F3 "" 0 -200 60 H I C CNN -DRAW -A -1200 -100 150 -899 899 0 0 0 N -1200 -250 -1200 50 -T 0 -550 -500 60 0 0 0 + Normal 0 C C -T 0 -550 50 60 0 0 0 + Normal 0 C C -T 0 750 -300 60 0 0 0 + Normal 0 C C -T 0 750 250 60 0 0 0 + Normal 0 C C -T 0 -550 -250 60 0 0 0 - Normal 0 C C -T 0 -550 300 60 0 0 0 - Normal 0 C C -T 0 750 -500 60 0 0 0 - Normal 0 C C -T 0 750 50 60 0 0 0 - Normal 0 C C -T 0 650 -400 60 0 0 0 1 Normal 0 C C -T 0 -450 -400 60 0 0 0 2 Normal 0 C C -T 0 650 150 60 0 0 0 3 Normal 0 C C -T 0 -450 150 60 0 0 0 4 Normal 0 C C -S -1200 750 1150 -1050 0 0 0 N -P 3 0 0 0 -600 -550 -650 -550 -650 -800 N -P 3 0 0 0 -200 -400 50 -400 50 -800 N -P 3 0 0 0 400 -400 350 -400 350 -800 N -P 3 0 0 0 800 0 950 0 950 500 N -P 5 0 0 0 -600 -250 -800 -250 -800 -700 -300 -700 -300 -800 N -P 5 0 0 0 -600 0 -800 0 -800 400 -300 400 -300 500 N -P 5 0 0 0 -600 300 -700 300 -700 450 50 450 50 500 N -P 5 0 0 0 -200 150 150 150 150 450 350 450 350 500 N -P 5 0 0 0 400 150 250 150 250 400 650 400 650 500 N -P 5 0 0 0 800 -550 900 -550 900 -750 650 -750 650 -800 N -P 5 0 0 0 800 -250 950 -250 950 -650 -950 -650 -950 -800 N -P 6 0 0 0 800 300 1000 300 1000 -100 -1000 -100 -1000 500 -650 500 N -C -600 -400 71 0 1 0 N -C -600 150 71 0 1 0 N -C 800 -400 71 0 1 0 N -C 800 150 71 0 1 0 N -P 4 0 1 0 -650 -350 -600 -450 -550 -350 -650 -350 N -P 4 0 1 0 -650 200 -600 100 -550 200 -650 200 N -P 4 0 1 0 -600 -200 -600 -600 -200 -400 -600 -200 N -P 4 0 1 0 -600 350 -600 -50 -200 150 -600 350 N -P 4 0 1 0 800 -600 800 -200 400 -400 800 -600 N -P 4 0 1 0 800 -50 800 350 400 150 800 -50 N -P 4 0 1 0 850 -450 800 -350 750 -450 850 -450 N -P 4 0 1 0 850 100 800 200 750 100 850 100 N -X IN1+ 1 -950 -1250 200 U 50 50 1 1 I -X IN2+ 2 -650 -1250 200 U 50 50 1 1 I -X IN2- 3 -300 -1250 200 U 50 50 1 1 I -X OUT2 4 50 -1250 200 U 50 50 1 1 O -X OUT1 5 350 -1250 200 U 50 50 1 1 O -X IN1- 6 650 -1250 200 U 50 50 1 1 I -X GND 7 950 -1250 200 U 50 50 1 1 I -X IN3- 8 950 950 200 D 50 50 1 1 I -X OUT3 9 650 950 200 D 50 50 1 1 O -X OUT4 10 350 950 200 D 50 50 1 1 O -X IN4- 11 50 950 200 D 50 50 1 1 I -X IN4+ 12 -300 950 200 D 50 50 1 1 I -X IN3+ 13 -650 950 200 D 50 50 1 1 I -X VCC 14 -950 950 200 D 50 50 1 1 I -ENDDRAW -ENDDEF -# -# IC_4002 -# -DEF IC_4002 X 0 40 Y Y 1 F N -F0 "X" 0 150 60 H V C CNN -F1 "IC_4002" 0 0 60 H V C CNN -F2 "" 50 -150 60 H V C CNN -F3 "" 50 -150 60 H V C CNN -DRAW -S -250 350 250 -400 0 1 0 N -X 1Y 1 -450 250 200 R 50 50 1 1 O -X 1A 2 -450 150 200 R 50 50 1 1 I -X 1B 3 -450 50 200 R 50 50 1 1 I -X 1C 4 -450 -50 200 R 50 50 1 1 I -X 1D 5 -450 -150 200 R 50 50 1 1 I -X NC 6 -450 -250 200 R 50 50 1 1 I -X GND 7 -450 -350 200 R 50 50 1 1 I -X NC 8 450 -350 200 L 50 50 1 1 I -X 2A 9 450 -250 200 L 50 50 1 1 I -X 2B 10 450 -150 200 L 50 50 1 1 I -X 2C 11 450 -50 200 L 50 50 1 1 I -X 2D 12 450 50 200 L 50 50 1 1 I -X 2Y 13 450 150 200 L 50 50 1 1 O -X VCC 14 450 250 200 L 50 50 1 1 I -ENDDRAW -ENDDEF -# -# IC_4012 -# -DEF IC_4012 X 0 40 Y Y 1 F N -F0 "X" 0 0 60 H V C CNN -F1 "IC_4012" 0 200 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -S -300 400 350 -400 0 1 0 N -X Q1 1 -500 300 200 R 50 50 1 1 O -X A1 2 -500 200 200 R 50 50 1 1 I -X B1 3 -500 100 200 R 50 50 1 1 I -X C1 4 -500 0 200 R 50 50 1 1 I -X D1 5 -500 -100 200 R 50 50 1 1 I -X NC 6 -500 -200 200 R 50 50 1 1 N -X VSS 7 -500 -300 200 R 50 50 1 1 I -X NC 8 550 -300 200 L 50 50 1 1 N -X A2 9 550 -200 200 L 50 50 1 1 I -X B2 10 550 -100 200 L 50 50 1 1 I -X C2 11 550 0 200 L 50 50 1 1 I -X D2 12 550 100 200 L 50 50 1 1 I -X Q2 13 550 200 200 L 50 50 1 1 O -X VDD 14 550 300 200 L 50 50 1 1 I -ENDDRAW -ENDDEF -# -# IC_4017 -# -DEF IC_4017 X 0 40 Y Y 1 F N -F0 "X" 0 0 60 H V C CNN -F1 "IC_4017" 0 0 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -S -350 850 400 -850 0 1 0 N -X 1 1 600 650 200 L 50 50 1 1 O -X 2 2 600 500 200 L 50 50 1 1 O -X 3 3 600 350 200 L 50 50 1 1 O -X 4 4 600 200 200 L 50 50 1 1 O -X 5 5 600 50 200 L 50 50 1 1 O -X 6 6 600 -100 200 L 50 50 1 1 O -X 7 7 600 -250 200 L 50 50 1 1 O -X 8 8 600 -400 200 L 50 50 1 1 O -X 9 9 600 -600 200 L 50 50 1 1 O -X 10 10 600 -750 200 L 50 50 1 1 O -X RST 11 -550 -400 200 R 50 50 1 1 I -X CLK 12 -550 350 200 R 50 50 1 1 I -ENDDRAW -ENDDEF -# -# IC_4023 -# -DEF IC_4023 X 0 40 Y Y 1 F N -F0 "X" 0 -100 60 H V C CNN -F1 "IC_4023" 0 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -S -300 450 300 -450 0 1 0 N -X A1 1 -500 300 200 R 50 50 1 1 I -X B1 2 -500 200 200 R 50 50 1 1 I -X A2 3 -500 100 200 R 50 50 1 1 I -X B2 4 -500 0 200 R 50 50 1 1 I -X C2 5 -500 -100 200 R 50 50 1 1 I -X Q2 6 -500 -200 200 R 50 50 1 1 O -X Vss 7 -500 -300 200 R 50 50 1 1 I -X C1 8 500 -300 200 L 50 50 1 1 I -X Q1 9 500 -200 200 L 50 50 1 1 O -X Q3 10 500 -100 200 L 50 50 1 1 O -X C3 11 500 0 200 L 50 50 1 1 I -X B3 12 500 100 200 L 50 50 1 1 I -X A3 13 500 200 200 L 50 50 1 1 I -X Vdd 14 500 300 200 L 50 50 1 1 I -ENDDRAW -ENDDEF -# -# IC_4028 -# -DEF IC_4028 X 0 40 Y Y 1 F N -F0 "X" 0 -100 60 H V C CNN -F1 "IC_4028" 0 50 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -S -300 450 300 -450 0 1 0 N -X Q4 1 -500 350 200 R 50 50 1 1 O -X Q2 2 -500 250 200 R 50 50 1 1 O -X Q0 3 -500 150 200 R 50 50 1 1 O -X Q7 4 -500 50 200 R 50 50 1 1 O -X Q9 5 -500 -50 200 R 50 50 1 1 O -X Q5 6 -500 -150 200 R 50 50 1 1 O -X Q6 7 -500 -250 200 R 50 50 1 1 O -X Vss 8 -500 -350 200 R 50 50 1 1 I -X Q8 9 500 -350 200 L 50 50 1 1 O -X A0 10 500 -250 200 L 50 50 1 1 I -X A3 11 500 -150 200 L 50 50 1 1 I -X A2 12 500 -50 200 L 50 50 1 1 I -X A1 13 500 50 200 L 50 50 1 1 I -X Q1 14 500 150 200 L 50 50 1 1 O -X Q3 15 500 250 200 L 50 50 1 1 O -X Vdd 16 500 350 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# IC_4073 -# -DEF IC_4073 X 0 40 Y Y 1 F N -F0 "X" 0 -100 60 H V C CNN -F1 "IC_4073" 0 50 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -S -300 400 300 -400 0 1 0 N -X A1 1 -500 300 200 R 50 50 1 1 I -X B1 2 -500 200 200 R 50 50 1 1 I -X A2 3 -500 100 200 R 50 50 1 1 I -X B2 4 -500 0 200 R 50 50 1 1 I -X C2 5 -500 -100 200 R 50 50 1 1 I -X Q2 6 -500 -200 200 R 50 50 1 1 O -X Vss 7 -500 -300 200 R 50 50 1 1 I -X C1 8 500 -300 200 L 50 50 1 1 I -X Q1 9 500 -200 200 L 50 50 1 1 O -X Q3 10 500 -100 200 L 50 50 1 1 O -X A3 11 500 0 200 L 50 50 1 1 I -X B3 12 500 100 200 L 50 50 1 1 I -X C3 13 500 200 200 L 50 50 1 1 I -X Vdd 14 500 300 200 L 50 50 1 1 I -ENDDRAW -ENDDEF -# -# IC_74153 -# -DEF IC_74153 X 0 40 Y Y 1 F N -F0 "X" 100 50 60 H V C CNN -F1 "IC_74153" 100 150 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -T 0 100 -200 60 0 0 0 4:1 Normal 0 C C -T 0 100 -100 60 0 0 0 DUAL Normal 0 C C -T 0 100 -300 60 0 0 0 MUX Normal 0 C C -S -200 500 350 -550 0 1 0 N -X a0 1 -400 350 200 R 50 50 1 1 I -X a1 2 -400 250 200 R 50 50 1 1 I -X a2 3 -400 150 200 R 50 50 1 1 I -X a3 4 -400 50 200 R 50 50 1 1 I -X EA 5 0 700 200 D 50 50 1 1 I I -X b0 6 -400 -150 200 R 50 50 1 1 I -X b1 7 -400 -250 200 R 50 50 1 1 I -X b2 8 -400 -350 200 R 50 50 1 1 I -X b3 9 -400 -450 200 R 50 50 1 1 I -X EB 10 200 700 200 D 50 50 1 1 I I -X s1 11 50 -750 200 U 50 50 1 1 I -X s0 12 150 -750 200 U 50 50 1 1 I -X ya 13 550 250 200 L 50 50 1 1 O -X yb 14 550 -300 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# IC_74154 -# -DEF IC_74154 X 0 40 Y Y 1 F N -F0 "X" 0 -200 60 H V C CNN -F1 "IC_74154" 50 -50 60 H V C CNN -F2 "" 0 50 60 H V C CNN -F3 "" 0 50 60 H V C CNN -DRAW -T 0 0 400 60 0 0 0 4:16~ Normal 0 C C -T 0 0 250 60 0 0 0 decoder Normal 0 C C -S -350 700 400 -700 0 0 0 N -X ~Y0 1 -550 550 200 R 50 50 1 1 O I -X ~Y1 2 -550 450 200 R 50 50 1 1 O I -X ~Y2 3 -550 350 200 R 50 50 1 1 O I -X ~Y3 4 -550 250 200 R 50 50 1 1 O I -X ~Y4 5 -550 150 200 R 50 50 1 1 O I -X ~Y5 6 -550 50 200 R 50 50 1 1 O I -X ~Y6 7 -550 -50 200 R 50 50 1 1 O I -X ~Y7 8 -550 -150 200 R 50 50 1 1 O I -X ~Y8 9 -550 -250 200 R 50 50 1 1 O I -X ~Y9 10 -550 -350 200 R 50 50 1 1 O I -X A3 20 600 150 200 L 50 50 1 1 I -X ~Y10 11 -550 -450 200 R 50 50 1 1 O I -X A2 21 600 250 200 L 50 50 1 1 I -X GND 12 -550 -550 200 R 50 50 1 1 I -X A1 22 600 350 200 L 50 50 1 1 I -X ~Y11 13 600 -550 200 L 50 50 1 1 O I -X A0 23 600 450 200 L 50 50 1 1 I -X ~Y12 14 600 -450 200 L 50 50 1 1 O I -X Vcc 24 600 550 200 L 50 50 1 1 I -X ~Y13 15 600 -350 200 L 50 50 1 1 O I -X ~Y14 16 600 -250 200 L 50 50 1 1 O I -X ~Y15 17 600 -150 200 L 50 50 1 1 O I -X ~E0 18 600 -50 200 L 50 50 1 1 I I -X ~E1 19 600 50 200 L 50 50 1 1 I I -ENDDRAW -ENDDEF -# -# IC_74157 -# -DEF IC_74157 X 0 40 Y Y 1 F N -F0 "X" 50 -50 60 H V C CNN -F1 "IC_74157" 50 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -T 0 50 -300 60 0 0 0 2:1 Normal 0 C C -T 0 50 -400 60 0 0 0 MUX Normal 0 C C -T 0 50 -200 60 0 0 0 QUAD Normal 0 C C -S -350 550 400 -650 0 1 0 N -X a0 1 -550 450 200 R 50 50 1 1 I -X a1 2 -550 300 200 R 50 50 1 1 I -X b0 3 -550 200 200 R 50 50 1 1 I -X b1 4 -550 100 200 R 50 50 1 1 I -X c0 5 -550 0 200 R 50 50 1 1 I -X c1 6 -550 -100 200 R 50 50 1 1 I -X d0 7 -550 -200 200 R 50 50 1 1 I -X d1 8 -550 -300 200 R 50 50 1 1 I -X EN 9 -550 -550 200 R 50 50 1 1 I I -X S 10 -550 -450 200 R 50 50 1 1 I -X Yd 11 600 0 200 L 50 50 1 1 O -X Ya 12 600 300 200 L 50 50 1 1 O -X Yb 13 600 200 200 L 50 50 1 1 O -X Yc 14 600 100 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# IC_7485 -# -DEF IC_7485 X 0 40 Y Y 1 F N -F0 "X" -50 -100 60 H V C CNN -F1 "IC_7485" -50 50 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -T 0 0 550 60 0 0 0 4~BIT~comparator Normal 0 C C -S -350 450 400 -400 0 1 0 N -X AB(in) 3 600 -300 200 L 50 50 1 1 I -X A3 4 -550 100 200 R 50 50 1 1 I -X B3 5 -550 -350 200 R 50 50 1 1 I -X A2 6 -550 200 200 R 50 50 1 1 I -X B2 7 -550 -250 200 R 50 50 1 1 I -X A1 8 -550 300 200 R 50 50 1 1 I -X B1 9 -550 -150 200 R 50 50 1 1 I -X A0 10 -550 400 200 R 50 50 1 1 I -X B0 11 -550 -50 200 R 50 50 1 1 I -X A>B(out) 12 600 350 200 L 50 50 1 1 O -X A=B(out) 13 600 250 200 L 50 50 1 1 O -X AB(in) 3 600 -300 200 L 50 50 1 1 I +X A3 4 -550 100 200 R 50 50 1 1 I +X B3 5 -550 -350 200 R 50 50 1 1 I +X A2 6 -550 200 200 R 50 50 1 1 I +X B2 7 -550 -250 200 R 50 50 1 1 I +X A1 8 -550 300 200 R 50 50 1 1 I +X B1 9 -550 -150 200 R 50 50 1 1 I +X A0 10 -550 400 200 R 50 50 1 1 I +X B0 11 -550 -50 200 R 50 50 1 1 I +X A>B(out) 12 600 350 200 L 50 50 1 1 O +X A=B(out) 13 600 250 200 L 50 50 1 1 O +X A