From b11e227ec99685f76063e2708218d49daf0ccb7a Mon Sep 17 00:00:00 2001 From: Gurce Isikyildiz Date: Fri, 21 Feb 2025 02:44:41 +0000 Subject: [PATCH 01/11] (#844) attempt to get 'r' uart mon command to show current megabyte --- .jenkinsfile | 16 +++++++--------- src/monitor/monitor.a65 | 7 ++++--- src/verilog/monitor_top.v | 11 +++++++---- 3 files changed, 18 insertions(+), 16 deletions(-) diff --git a/.jenkinsfile b/.jenkinsfile index 12ea41c1f..2d17a66b5 100644 --- a/.jenkinsfile +++ b/.jenkinsfile @@ -29,7 +29,7 @@ pipeline { sh 'make flasher_files' } } - stage('Build MEGA65R6') { + /*stage('Build MEGA65R6') { steps { catchError(buildResult: 'SUCCESS', stageResult: 'FAILURE', catchInterruptions: false) { sh 'make bin/mega65r6.bit' @@ -37,7 +37,7 @@ pipeline { sh 'release-build/build-release.sh mega65r5_6 JENKINSGEN' } } - } + }*/ /* // mega65r5 is essentially the same as mega65r6, and the r6 build will also package as r5 stage('Build MEGA65R5') { @@ -49,14 +49,14 @@ pipeline { } } */ - stage('Build MEGA65R4') { + /*stage('Build MEGA65R4') { steps { catchError(buildResult: 'SUCCESS', stageResult: 'FAILURE', catchInterruptions: false) { sh 'make bin/mega65r4.bit' sh 'release-build/build-release.sh mega65r4 JENKINSGEN' } } - } + }*/ stage('Build MEGA65R3') { steps { catchError(buildResult: 'SUCCESS', stageResult: 'FAILURE', catchInterruptions: false) { @@ -65,7 +65,7 @@ pipeline { } } } - stage('Build MEGA65R2') { + /*stage('Build MEGA65R2') { steps { catchError(buildResult: 'SUCCESS', stageResult: 'FAILURE', catchInterruptions: false) { sh 'make bin/mega65r2.bit' @@ -80,16 +80,14 @@ pipeline { sh 'release-build/build-release.sh nexys4ddr-widget JENKINSGEN' } } - } + }*/ stage('Set build result') { steps { script { def files = findFiles(glob: 'release-build/pkg/*.7z') // number of total architectures needs to be changed in next line, // if we add or subtract build targets! - if (files.length < 3) { - currentBuild.result = 'UNSTABLE' - } else if (files.length == 0) { + if (files.length == 0) { currentBuild.result = 'FAILURE' } } diff --git a/src/monitor/monitor.a65 b/src/monitor/monitor.a65 index 65deb2c1b..d13ecb8c5 100644 --- a/src/monitor/monitor.a65 +++ b/src/monitor/monitor.a65 @@ -61,7 +61,8 @@ .alias monitor_Arg2 $8014 .alias monitor_Instruction $8015 .alias monitor_roms $8016 - .alias monitor_Unused1 $8017 + .alias monitor_MapHiMb $8017 + .alias monitor_MapLoMb $8018 .alias hist_read_lo $9000 .alias hist_read_hi $9001 @@ -1830,7 +1831,7 @@ state_msg: .byte 13,10,"uS Address Rd",13,10,0 history_msg: - .byte 13,10,"PC A X Y Z B SP MAPH MAPL LAST-OP In " + .byte 13,10,"PC A X Y Z B SP MAPH:MB MAPL:MB LAST-OP In " .byte "P P-FLAGS RGP uS IO ws h RECA8LHC",13,10,0 history_fmt: @@ -1845,7 +1846,7 @@ history_fmt: ; $26 - ROM enables ; $27 - print five spaces ; High bit set implies printing a space first. - .byte $06,$05,$81,$82,$83,$84,$8a,$8c,$0b,$90,$11,$8d,$0e,$80+$21,$15,$27 + .byte $06,$05,$81,$82,$83,$84,$8a,$8c,$0b,$90,$11,$97,$8d,$0e,$98,$80+$21,$15,$27 .byte $80+$00,$80+$23,$80+$24,$88,$80+$22,$89,$80+$25,$00+$26,$20 bad_bitrate_msg: diff --git a/src/verilog/monitor_top.v b/src/verilog/monitor_top.v index 780324b6d..bdf462d2d 100644 --- a/src/verilog/monitor_top.v +++ b/src/verilog/monitor_top.v @@ -65,6 +65,8 @@ input [7:0] monitor_char, input monitor_char_toggle, output wire monitor_char_busy, + input [7:0] monitor_map_low_mb, + input [7:0] monitor_map_hi_mb, output wire [27:0] monitor_mem_address, input [7:0] monitor_mem_rdata, @@ -111,8 +113,9 @@ assign history_wdata[167:160] = monitor_arg2; assign history_wdata[175:168] = monitor_instruction; assign history_wdata[183:176] = monitor_roms; - assign history_wdata[191:184] = 8'h00; - + assign history_wdata[191:184] = monitor_map_hi_mb + assign history_wdata[199:192] = monitor_map_lo_mb + wire [9:0] history_write_index; wire [7:0] history_rdata_lo; @@ -157,10 +160,10 @@ .clkA(clock),.weA(history_write),.enaA(1), .addrA(history_write_index),.diA(history_wdata[127:0]), .clkB(clock),.enaB(1),.addrB(history_read_address_lo),.doB(history_rdata_lo)); - asym_ram_sdp #(.WIDTHA(64),.SIZEA(1024),.ADDRWIDTHA(10), .WIDTHB(8),.SIZEB(8192),.ADDRWIDTHB(13)) + asym_ram_sdp #(.WIDTHA(72),.SIZEA(1024),.ADDRWIDTHA(10), .WIDTHB(8),.SIZEB(8192),.ADDRWIDTHB(13)) historyram1( .clkA(clock),.weA(history_write),.enaA(1), - .addrA(history_write_index),.diA(history_wdata[191:128]), + .addrA(history_write_index),.diA(history_wdata[199:128]), .clkB(clock),.enaB(1),.addrB(history_read_address_hi),.doB(history_rdata_hi)); // Recent CPU State RAM is relatively small, only 64 bits wide by 16 entires deep used to store all the states (and addresses) From 269c3a7bbe8299f5923bd9d7c8f67c6c8df8b9cd Mon Sep 17 00:00:00 2001 From: Gurce Isikyildiz Date: Fri, 21 Feb 2025 02:47:54 +0000 Subject: [PATCH 02/11] (#844) fixed typo --- src/verilog/monitor_top.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/verilog/monitor_top.v b/src/verilog/monitor_top.v index bdf462d2d..0f09e785e 100644 --- a/src/verilog/monitor_top.v +++ b/src/verilog/monitor_top.v @@ -113,8 +113,8 @@ assign history_wdata[167:160] = monitor_arg2; assign history_wdata[175:168] = monitor_instruction; assign history_wdata[183:176] = monitor_roms; - assign history_wdata[191:184] = monitor_map_hi_mb - assign history_wdata[199:192] = monitor_map_lo_mb + assign history_wdata[191:184] = monitor_map_hi_mb; + assign history_wdata[199:192] = monitor_map_lo_mb; wire [9:0] history_write_index; From ea5689f05c5838918f1e274ec95c816234fce447 Mon Sep 17 00:00:00 2001 From: Gurce Isikyildiz Date: Fri, 21 Feb 2025 02:50:13 +0000 Subject: [PATCH 03/11] (#844) fixed another typo --- src/verilog/monitor_top.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/verilog/monitor_top.v b/src/verilog/monitor_top.v index 0f09e785e..112bbf735 100644 --- a/src/verilog/monitor_top.v +++ b/src/verilog/monitor_top.v @@ -65,7 +65,7 @@ input [7:0] monitor_char, input monitor_char_toggle, output wire monitor_char_busy, - input [7:0] monitor_map_low_mb, + input [7:0] monitor_map_lo_mb, input [7:0] monitor_map_hi_mb, output wire [27:0] monitor_mem_address, From 740b9e597911a1a3af9db33b9e53ccf905b8de16 Mon Sep 17 00:00:00 2001 From: Gurce Isikyildiz Date: Fri, 21 Feb 2025 02:52:24 +0000 Subject: [PATCH 04/11] (#844) fixed yet another typo --- src/verilog/monitor_top.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/verilog/monitor_top.v b/src/verilog/monitor_top.v index 112bbf735..026d746a4 100644 --- a/src/verilog/monitor_top.v +++ b/src/verilog/monitor_top.v @@ -82,7 +82,7 @@ output wire monitor_mem_trace_toggle ); - wire [191:0] history_wdata; + wire [199:0] history_wdata; // 16 byte wide section assign history_wdata[7:0] = monitor_p; From 5d38228bf9d13bb55812ad486b0ce5757af169f0 Mon Sep 17 00:00:00 2001 From: Gurce Isikyildiz Date: Fri, 21 Feb 2025 03:46:37 +0000 Subject: [PATCH 05/11] (#844) tried reducing the trace depth to save on ram --- src/verilog/monitor_top.v | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/verilog/monitor_top.v b/src/verilog/monitor_top.v index 026d746a4..b6214e609 100644 --- a/src/verilog/monitor_top.v +++ b/src/verilog/monitor_top.v @@ -150,17 +150,17 @@ assign history_read_address_lo = { history_read_index, cpu_address_next[3:0]}; assign history_read_address_hi = { history_read_index, cpu_address_next[2:0]}; - // Conceptually the history RAM is a dual ported 1024x24 byte RAM, broken up into - // a 1Kx16B and a 1Kx8B. From the write side, the write width for RAM 0 is - // 128 bits, and write width for RAM1 is 64 bits. The write side address width is 10 bits for both. - // For the read side, RAM 0 is a 16Kx8b, and RAM 1 is a 8Kx8b. The read side is mapped + // Conceptually the history RAM is a dual ported 512 byte RAM, broken up into + // a 512Bx16B and a 512Bx9B. From the write side, the write width for RAM 0 is + // 128 bits, and write width for RAM1 is 72 bits. The write side address width is 9 bits for both. + // For the read side, RAM 0 is a 8Kx8b, and RAM 1 is a 8Kx8b. The read side is mapped // into the 6502's address space via 16 and 8 byte windows. - asym_ram_sdp #(.WIDTHA(128),.SIZEA(1024),.ADDRWIDTHA(10), .WIDTHB(8),.SIZEB(16384),.ADDRWIDTHB(14)) + asym_ram_sdp #(.WIDTHA(128),.SIZEA(512),.ADDRWIDTHA(9), .WIDTHB(8),.SIZEB(8192),.ADDRWIDTHB(14)) historyram0( .clkA(clock),.weA(history_write),.enaA(1), .addrA(history_write_index),.diA(history_wdata[127:0]), .clkB(clock),.enaB(1),.addrB(history_read_address_lo),.doB(history_rdata_lo)); - asym_ram_sdp #(.WIDTHA(72),.SIZEA(1024),.ADDRWIDTHA(10), .WIDTHB(8),.SIZEB(8192),.ADDRWIDTHB(13)) + asym_ram_sdp #(.WIDTHA(72),.SIZEA(512),.ADDRWIDTHA(9), .WIDTHB(8),.SIZEB(4608),.ADDRWIDTHB(13)) historyram1( .clkA(clock),.weA(history_write),.enaA(1), .addrA(history_write_index),.diA(history_wdata[199:128]), From 6e4e164149d84097a0d451b4d146e085f8003f37 Mon Sep 17 00:00:00 2001 From: Gurce Isikyildiz Date: Fri, 21 Feb 2025 07:33:39 +0000 Subject: [PATCH 06/11] (#844) forgot to route new signals in --- src/vhdl/gs4510.vhdl | 4 ++++ src/vhdl/machine.vhdl | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/src/vhdl/gs4510.vhdl b/src/vhdl/gs4510.vhdl index 8376969e9..65f2e5083 100755 --- a/src/vhdl/gs4510.vhdl +++ b/src/vhdl/gs4510.vhdl @@ -160,6 +160,8 @@ entity gs4510 is monitor_map_offset_high : out unsigned(11 downto 0); monitor_map_enables_low : out unsigned(3 downto 0); monitor_map_enables_high : out unsigned(3 downto 0); + monitor_map_lo_mb : out unsigned(7 downto 0); + monitor_map_hi_mb : out unsigned(7 downto 0); monitor_interrupt_inhibit : out std_logic; monitor_memory_access_address : out unsigned(31 downto 0); monitor_cpuport : out unsigned(2 downto 0); @@ -9157,6 +9159,8 @@ begin monitor_map_offset_high <= reg_offset_high; monitor_map_enables_low <= unsigned(reg_map_low); monitor_map_enables_high <= unsigned(reg_map_high); + monitor_map_lo_mb <= unsigned(reg_mb_low); + monitor_map_hi_mb <= unsigned(reg_mb_high); -- alternate (new) combinatorial core memory address generation. process (state,reg_pc,vector,reg_t,hypervisor_mode,monitor_mem_attention_request_drive,monitor_mem_address_drive, diff --git a/src/vhdl/machine.vhdl b/src/vhdl/machine.vhdl index f3d169e9a..4fecdf1b2 100644 --- a/src/vhdl/machine.vhdl +++ b/src/vhdl/machine.vhdl @@ -1210,6 +1210,8 @@ begin monitor_map_offset_high => monitor_map_offset_high, monitor_map_enables_low => monitor_map_enables_low, monitor_map_enables_high => monitor_map_enables_high, + monitor_map_lo_mb => monitor_map_lo_mb, + monitor_map_hi_mb => monitor_map_hi_mb, monitor_memory_access_address => monitor_memory_access_address, monitor_mem_address => monitor_mem_address, @@ -2048,6 +2050,8 @@ begin monitor_map_offset_high => monitor_map_offset_high, monitor_map_enables_low => monitor_map_enables_low, monitor_map_enables_high => monitor_map_enables_high, + monitor_map_lo_mb => monitor_map_lo_mb, + monitor_map_hi_mb => monitor_map_hi_mb, monitor_memory_access_address => monitor_memory_access_address, monitor_mem_address => monitor_mem_address, monitor_mem_rdata => monitor_mem_rdata, From cc74f9bb7e7e2748f87b288a9803596a696e038f Mon Sep 17 00:00:00 2001 From: Gurce Isikyildiz Date: Fri, 21 Feb 2025 11:02:04 +0000 Subject: [PATCH 07/11] (#844) forgot a part of routing the signal through --- src/vhdl/machine.vhdl | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/vhdl/machine.vhdl b/src/vhdl/machine.vhdl index 4fecdf1b2..e508a16b5 100644 --- a/src/vhdl/machine.vhdl +++ b/src/vhdl/machine.vhdl @@ -630,6 +630,8 @@ architecture Behavioral of machine is signal monitor_map_offset_high : unsigned(11 downto 0); signal monitor_map_enables_low : unsigned(3 downto 0); signal monitor_map_enables_high : unsigned(3 downto 0); + signal monitor_map_lo_mb : unsigned(7 downto 0); + signal monitor_map_hi_mb : unsigned(7 downto 0); signal monitor_mem_read : std_logic; signal monitor_mem_write : std_logic; signal monitor_mem_setpc : std_logic; From 9fcea47cdbf829e144e843c104dedcaf3b6acd14 Mon Sep 17 00:00:00 2001 From: Gurce Isikyildiz Date: Fri, 21 Feb 2025 11:18:46 +0000 Subject: [PATCH 08/11] (#844) forgot another part --- src/vhdl/machine.vhdl | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/vhdl/machine.vhdl b/src/vhdl/machine.vhdl index e508a16b5..a59982787 100644 --- a/src/vhdl/machine.vhdl +++ b/src/vhdl/machine.vhdl @@ -486,6 +486,8 @@ architecture Behavioral of machine is monitor_map_offset_high : in unsigned(11 downto 0); monitor_map_enables_low : in unsigned(3 downto 0); monitor_map_enables_high : in unsigned(3 downto 0); + monitor_map_lo_mb : in unsigned(7 downto 0); + monitor_map_hi_mb : in unsigned(7 downto 0); monitor_interrupt_inhibit : in std_logic; monitor_char : in unsigned(7 downto 0); From eecb4b7b595ff6d9826907226bbb19d37b5df809 Mon Sep 17 00:00:00 2001 From: Gurce Isikyildiz Date: Fri, 21 Feb 2025 13:49:14 +0000 Subject: [PATCH 09/11] (#844) tried fixing some other issues --- src/verilog/monitor_bus.v | 2 +- src/verilog/monitor_top.v | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/verilog/monitor_bus.v b/src/verilog/monitor_bus.v index 210ec30b3..213085925 100644 --- a/src/verilog/monitor_bus.v +++ b/src/verilog/monitor_bus.v @@ -23,7 +23,7 @@ begin 16'b0000000z_zzzzzzzz: begin read_select = 1; ram_write = cpu_write; end // $0000-$01ff - RAM (zero page + stack) 16'b0111zzzz_zzzzzzzz: read_select = 5; // $7000-$7fff - CPU State 16'b1000zzzz_zzz0zzzz: read_select = 2; // $8000-$800f - History Lo - 16'b1000zzzz_zzz10zzz: read_select = 3; // $8010-$8017 - History Hi + 16'b1000zzzz_zzz1zzzz: read_select = 3; // $8010-$801f - History Hi 16'b1001zzzz_zzzzzzzz: begin read_select = 4; ctrl_write = cpu_write; ctrl_read = ~cpu_write; end // $9000-$9000 - Monitor Ctrl 16'b1111zzzz_zzzzzzzz: read_select = 1; // $f000-$ffff - Monitor "ROM" default : read_select = 0; // Nothing? diff --git a/src/verilog/monitor_top.v b/src/verilog/monitor_top.v index b6214e609..5c1ff091f 100644 --- a/src/verilog/monitor_top.v +++ b/src/verilog/monitor_top.v @@ -105,7 +105,7 @@ assign history_wdata[126] = monitor_request_reflected; assign history_wdata[127] = monitor_interrupt_inhibit; - // 8 byte wide section, 2 unused bytes at top + // 9 byte wide section assign history_wdata[135:128] = { monitor_map_enables_high, monitor_map_offset_high[11:8] }; assign history_wdata[143:136] = monitor_map_offset_high[7:0]; assign history_wdata[151:144] = monitor_opcode; @@ -121,7 +121,7 @@ wire [7:0] history_rdata_lo; wire [7:0] history_rdata_hi; - wire [13:0] history_read_address_lo; + wire [12:0] history_read_address_lo; wire [12:0] history_read_address_hi; wire [9:0] history_read_index; @@ -155,7 +155,7 @@ // 128 bits, and write width for RAM1 is 72 bits. The write side address width is 9 bits for both. // For the read side, RAM 0 is a 8Kx8b, and RAM 1 is a 8Kx8b. The read side is mapped // into the 6502's address space via 16 and 8 byte windows. - asym_ram_sdp #(.WIDTHA(128),.SIZEA(512),.ADDRWIDTHA(9), .WIDTHB(8),.SIZEB(8192),.ADDRWIDTHB(14)) + asym_ram_sdp #(.WIDTHA(128),.SIZEA(512),.ADDRWIDTHA(9), .WIDTHB(8),.SIZEB(8192),.ADDRWIDTHB(13)) historyram0( .clkA(clock),.weA(history_write),.enaA(1), .addrA(history_write_index),.diA(history_wdata[127:0]), From ed8bd7f0c52fe66177689f64e4399225ff3e6fb0 Mon Sep 17 00:00:00 2001 From: Gurce Isikyildiz Date: Sat, 22 Feb 2025 13:42:06 +0000 Subject: [PATCH 10/11] (#844) rework two historyrams into one ram that 32 bytes per trace and is 512 deep --- src/monitor/monitor.a65 | 28 ++++++++++++------------- src/verilog/monitor_bus.v | 8 +++----- src/verilog/monitor_ctrl.v | 8 ++++---- src/verilog/monitor_top.v | 42 +++++++++++++++----------------------- 4 files changed, 38 insertions(+), 48 deletions(-) diff --git a/src/monitor/monitor.a65 b/src/monitor/monitor.a65 index d13ecb8c5..248dc6304 100644 --- a/src/monitor/monitor.a65 +++ b/src/monitor/monitor.a65 @@ -64,10 +64,10 @@ .alias monitor_MapHiMb $8017 .alias monitor_MapLoMb $8018 - .alias hist_read_lo $9000 - .alias hist_read_hi $9001 - .alias hist_write_lo $9002 - .alias hist_write_hi $9003 + .alias hist_read_idx_lo $9000 + .alias hist_read_idx_hi $9001 + .alias hist_write_idx_lo $9002 + .alias hist_write_idx_hi $9003 .alias mon_trace $9004 .alias mon_trace_step $9005 .alias flag_mask_lo $9006 @@ -410,8 +410,8 @@ backspace: ; ------------------------------------- empty_command: lda #0 ; reset history index - sta hist_write_lo - sta hist_write_hi + sta hist_write_idx_lo + sta hist_write_idx_hi lda mon_trace ora #trace_hist_en ; also record history sta mon_trace @@ -985,8 +985,8 @@ trace_cmd: * jmp next_command trace_hist: - stz hist_write_lo - stz hist_write_hi + stz hist_write_idx_lo + stz hist_write_idx_hi bra do_trace trace_cont: @@ -1147,9 +1147,9 @@ history_cmd: lda hex_value+1 cmp #3 bcs bad_index - sta hist_read_hi + sta hist_read_idx_hi lda hex_value+0 - sta hist_read_lo + sta hist_read_idx_lo jsr print_history jmp next_command @@ -1172,10 +1172,10 @@ _lp: dex ; Set history read and write indices to max hardware index. Controller will drop unimplemented bits. lda #$ff - sta hist_write_lo - sta hist_write_hi - sta hist_read_lo - sta hist_read_hi + sta hist_write_idx_lo + sta hist_write_idx_hi + sta hist_read_idx_lo + sta hist_read_idx_hi lda mon_trace ora #trace_hist_en sta mon_trace ; This should enable history writes, which should diff --git a/src/verilog/monitor_bus.v b/src/verilog/monitor_bus.v index 213085925..1d5d4f602 100644 --- a/src/verilog/monitor_bus.v +++ b/src/verilog/monitor_bus.v @@ -5,7 +5,7 @@ `define MARK_DEBUG `endif -module monitor_bus(input clk, input [15:0] cpu_address, input cpu_write, input [7:0] history_lo, input [7:0] history_hi, input [7:0] mem, input [7:0] ctrl, +module monitor_bus(input clk, input [15:0] cpu_address, input cpu_write, input [7:0] history, input [7:0] mem, input [7:0] ctrl, input [7:0] cpu_state, `MARK_DEBUG output reg ram_write, `MARK_DEBUG output reg ctrl_write, `MARK_DEBUG output reg ctrl_read, output reg [7:0] read_data); @@ -22,8 +22,7 @@ begin casez(cpu_address[15:0]) 16'b0000000z_zzzzzzzz: begin read_select = 1; ram_write = cpu_write; end // $0000-$01ff - RAM (zero page + stack) 16'b0111zzzz_zzzzzzzz: read_select = 5; // $7000-$7fff - CPU State - 16'b1000zzzz_zzz0zzzz: read_select = 2; // $8000-$800f - History Lo - 16'b1000zzzz_zzz1zzzz: read_select = 3; // $8010-$801f - History Hi + 16'b1000zzzz_zzzzzzzz: read_select = 2; // $8000-$8fff - History 16'b1001zzzz_zzzzzzzz: begin read_select = 4; ctrl_write = cpu_write; ctrl_read = ~cpu_write; end // $9000-$9000 - Monitor Ctrl 16'b1111zzzz_zzzzzzzz: read_select = 1; // $f000-$ffff - Monitor "ROM" default : read_select = 0; // Nothing? @@ -43,8 +42,7 @@ begin case(read_select_reg) // synthesis full_case parallel_case 0: read_data = 8'h00; 1: read_data = mem; - 2: read_data = history_lo; - 3: read_data = history_hi; + 2: read_data = history; 4: read_data = ctrl; 5: read_data = cpu_state; endcase; diff --git a/src/verilog/monitor_ctrl.v b/src/verilog/monitor_ctrl.v index 7eeb6fa4b..be7dfc28f 100644 --- a/src/verilog/monitor_ctrl.v +++ b/src/verilog/monitor_ctrl.v @@ -53,7 +53,7 @@ module monitor_ctrl(input clk, input reset, output reg reset_out, `MARK_DEBUG input write, `MARK_DEBUG input read, `MARK_DEBUG input [4:0] address, `MARK_DEBUG input [7:0] di, output reg [7:0] do, - output reg [9:0] history_write_index, output wire history_write, output reg [9:0] history_read_index, + output reg [8:0] history_write_index, output wire history_write, output reg [8:0] history_read_index, /* CPU Memory Interface */ output wire [27:0] mem_address, @@ -273,7 +273,7 @@ begin if(address == `MON_READ_IDX_LO) history_read_index[7:0] <= di; if(address == `MON_READ_IDX_HI) - history_read_index[9:8] <= di[1:0]; + history_read_index[8] <= di[0]; end end @@ -317,7 +317,7 @@ begin end if(address == `MON_WRITE_IDX_HI) begin - history_write_index[9:8] <= di[1:0]; + history_write_index[8] <= di[0]; mem_trace_reg[2] <= 0; end if(address == `MON_UART_STATUS) @@ -371,7 +371,7 @@ begin else if(history_write == 1) begin // record history continuously until full. The last slot is reserved for capturing current state. - if(history_write_index < 1022) + if(history_write_index < 510) history_write_index <= history_write_index + 1; else if(history_write_continuous) history_write_index <= 0; // Wrap around to 0 diff --git a/src/verilog/monitor_top.v b/src/verilog/monitor_top.v index 5c1ff091f..a6f7b9b7b 100644 --- a/src/verilog/monitor_top.v +++ b/src/verilog/monitor_top.v @@ -82,7 +82,7 @@ output wire monitor_mem_trace_toggle ); - wire [199:0] history_wdata; + wire [255:0] history_wdata; // 16 byte wide section assign history_wdata[7:0] = monitor_p; @@ -115,16 +115,15 @@ assign history_wdata[183:176] = monitor_roms; assign history_wdata[191:184] = monitor_map_hi_mb; assign history_wdata[199:192] = monitor_map_lo_mb; + assign history_wdata[255:200] = 56'h00; - wire [9:0] history_write_index; + wire [8:0] history_write_index; - wire [7:0] history_rdata_lo; - wire [7:0] history_rdata_hi; + wire [7:0] history_rdata; - wire [12:0] history_read_address_lo; - wire [12:0] history_read_address_hi; + wire [13:0] history_read_address; - wire [9:0] history_read_index; + wire [8:0] history_read_index; `MARK_DEBUG wire [15:0] cpu_address_next; `MARK_DEBUG wire [7:0] cpu_di; @@ -147,26 +146,19 @@ assign reset_internal = ~reset; assign reset_out = ~reset_out_internal; - assign history_read_address_lo = { history_read_index, cpu_address_next[3:0]}; - assign history_read_address_hi = { history_read_index, cpu_address_next[2:0]}; - - // Conceptually the history RAM is a dual ported 512 byte RAM, broken up into - // a 512Bx16B and a 512Bx9B. From the write side, the write width for RAM 0 is - // 128 bits, and write width for RAM1 is 72 bits. The write side address width is 9 bits for both. - // For the read side, RAM 0 is a 8Kx8b, and RAM 1 is a 8Kx8b. The read side is mapped - // into the 6502's address space via 16 and 8 byte windows. - asym_ram_sdp #(.WIDTHA(128),.SIZEA(512),.ADDRWIDTHA(9), .WIDTHB(8),.SIZEB(8192),.ADDRWIDTHB(13)) + assign history_read_address = { history_read_index, cpu_address_next[4:0]}; + + // The history RAM is a dual ported 512Bx32B byte RAM. + // From the write side, the write width is 256 bits. The write side address width is 9 bits. + // For the read side, RAM is a 16Kx1B. The read side is mapped + // into the 6502's address space via 32 byte windows. + asym_ram_sdp #(.WIDTHA(256),.SIZEA(512),.ADDRWIDTHA(9), .WIDTHB(8),.SIZEB(16384),.ADDRWIDTHB(14)) historyram0( .clkA(clock),.weA(history_write),.enaA(1), - .addrA(history_write_index),.diA(history_wdata[127:0]), - .clkB(clock),.enaB(1),.addrB(history_read_address_lo),.doB(history_rdata_lo)); - asym_ram_sdp #(.WIDTHA(72),.SIZEA(512),.ADDRWIDTHA(9), .WIDTHB(8),.SIZEB(4608),.ADDRWIDTHB(13)) - historyram1( - .clkA(clock),.weA(history_write),.enaA(1), - .addrA(history_write_index),.diA(history_wdata[199:128]), - .clkB(clock),.enaB(1),.addrB(history_read_address_hi),.doB(history_rdata_hi)); + .addrA(history_write_index),.diA(history_wdata), + .clkB(clock),.enaB(1),.addrB(history_read_address),.doB(history_rdata)); - // Recent CPU State RAM is relatively small, only 64 bits wide by 16 entires deep used to store all the states (and addresses) + // Recent CPU State RAM is relatively small, only 64 bits wide by 16 entries deep used to store all the states (and addresses) // of the most recent instruction execution. The output is directly mapped into 128 bytes of CPU // address space rather than using a read index register. asym_ram_sdp #(.WIDTHA(64),.SIZEA(16),.ADDRWIDTHA(4), .WIDTHB(8),.SIZEB(128),.ADDRWIDTHB(7)) @@ -212,7 +204,7 @@ .bit_rate_divisor(bit_rate_divisor),.rx(rx),.tx(tx),.activity(activity)); monitor_bus monitorbus(.clk(clock), .cpu_address(cpu_address_next), .cpu_write(cpu_write_next), - .history_lo(history_rdata_lo), .history_hi(history_rdata_hi), .cpu_state(cpu_state_rdata), + .history(history_rdata), .cpu_state(cpu_state_rdata), .mem(ram_do), .ctrl(monitor_do), .ram_write(ram_write), .ctrl_write(ctrl_write), .ctrl_read(ctrl_read), .read_data(cpu_di)); From f3f4b676681e368b3f447b5daf041e1bb42d98bd Mon Sep 17 00:00:00 2001 From: Gurce Isikyildiz Date: Sun, 23 Feb 2025 10:47:35 +0000 Subject: [PATCH 11/11] build R6 too --- .jenkinsfile | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/.jenkinsfile b/.jenkinsfile index 2d17a66b5..29abfc892 100644 --- a/.jenkinsfile +++ b/.jenkinsfile @@ -29,7 +29,7 @@ pipeline { sh 'make flasher_files' } } - /*stage('Build MEGA65R6') { + stage('Build MEGA65R6') { steps { catchError(buildResult: 'SUCCESS', stageResult: 'FAILURE', catchInterruptions: false) { sh 'make bin/mega65r6.bit' @@ -37,7 +37,7 @@ pipeline { sh 'release-build/build-release.sh mega65r5_6 JENKINSGEN' } } - }*/ + } /* // mega65r5 is essentially the same as mega65r6, and the r6 build will also package as r5 stage('Build MEGA65R5') { @@ -87,7 +87,9 @@ pipeline { def files = findFiles(glob: 'release-build/pkg/*.7z') // number of total architectures needs to be changed in next line, // if we add or subtract build targets! - if (files.length == 0) { + if (files.length < 2) { + currentBuild.result = 'UNSTABLE' + } else if (files.length == 0) { currentBuild.result = 'FAILURE' } }