implement slt and sltu

Author: outercloudstudio

documentation/Modules/Hart.md

@@ -24,8 +24,8 @@ Currently only the `LW` instruction uses stage 2, since in stage 1 `LW` requests
 - [x] ADD
 - [x] SUB
 - [x] SLL
-- [ ] SLT
-- [ ] SLTU
+- [x] SLT
+- [x] SLTU
 - [ ] XOR
 - [ ] SRL
 - [ ] SRA

src/main/scala/RISCV/Main.scala

@@ -322,6 +322,46 @@ class Main() extends Module {
 
                     printf("[SLL] Rs1: %d Rs2: %d Rd: %d\n", decoder.io.rs1, decoder.io.rs2, decoder.io.rd);
                 }
+
+                // SLT
+                is("b010_0110011".U) { 
+                    registers.io.read_address_a := decoder.io.rs1;
+                    registers.io.read_address_b := decoder.io.rs2;
+
+                    registers.io.write_address := decoder.io.rd;
+                    registers.io.write_enable := true.B;
+                    
+                    when(registers.io.out_a.asSInt < registers.io.out_b.asSInt) {
+                        registers.io.in := 1.U;
+                    }.otherwise {
+                        registers.io.in := 0.U;
+                    }
+
+                    program_pointer := program_pointer + 1.U;
+                    stage := 0.U;
+
+                    printf("[SLT] Rs1: %d Rs2: %d Rd: %d\n", decoder.io.rs1, decoder.io.rs2, decoder.io.rd);
+                }
+
+                // SLTU
+                is("b011_0110011".U) { 
+                    registers.io.read_address_a := decoder.io.rs1;
+                    registers.io.read_address_b := decoder.io.rs2;
+
+                    registers.io.write_address := decoder.io.rd;
+                    registers.io.write_enable := true.B;
+                    
+                    when(registers.io.out_a < registers.io.out_b) {
+                        registers.io.in := 1.U;
+                    }.otherwise {
+                        registers.io.in := 0.U;
+                    }
+
+                    program_pointer := program_pointer + 1.U;
+                    stage := 0.U;
+
+                    printf("[SLTU] Rs1: %d Rs2: %d Rd: %d\n", decoder.io.rs1, decoder.io.rs2, decoder.io.rd);
+                }
             }
         }
 

src/test/scala/RISCV/MainSpec.scala

@@ -32,6 +32,12 @@ class MainSpec extends AnyFreeSpec with Matchers with ChiselSim {
 
       dut.clock.step(1);
 
+      dut.io.debug_write.poke(true.B);
+      dut.io.debug_write_data.poke("b0000000_00001_00010_011_00010_0110011".U(32.W));
+      dut.io.debug_write_addressess.poke(4.U);
+
+      dut.clock.step(1);
+
       dut.io.debug_write.poke(false.B);
       dut.io.execute.poke(true.B);
 
@@ -46,6 +52,8 @@ class MainSpec extends AnyFreeSpec with Matchers with ChiselSim {
       dut.clock.step(1);
       dut.clock.step(1);
       dut.clock.step(1);
+      dut.clock.step(1);
+      dut.clock.step(1);
     }
   }
 }