Write documentation for Hart

outercloudstudio · outercloudstudio · commit ab40a1cfb494 · 2025-12-12T12:58:52.000-05:00
diff --git a/documentation/.obsidian/workspace.json b/documentation/.obsidian/workspace.json
diff --git a/documentation/Modules/Hart.md b/documentation/Modules/Hart.md
@@ -0,0 +1,10 @@
+## Overview
+The Hart is the "hardware execution unit". This is the complex stuff comes together to actually execute the instructions. Right now it's stored in the `main.scala` file but we'll probably want to move it over to `hart.scala` later.
+## Instruction Staging
+Right now for simplicity, we're not doing anything too complex with how we're loading instructions. The way it works currently is a simple stage counter.
+### Stage 0
+The instruction at the program pointer is requested from memory.
+### Stage 1
+The instruction is available from memory and the decoder is now emitting the decoded instruction. We store the decoded instructions in buffers for access in later stages. Most instructions can simply execute in this stage and then set the stage counter back to 0 and increase the program pointer.
+## Stage 2
+Currently only the `LW` instruction uses stage 2, since in stage 1 `LW` requests the info from memory and then in stage 2 it takes the value from memory and writes it to the register.
diff --git a/documentation/README.md b/documentation/README.md
@@ -1,3 +1,4 @@
 Welcome to the documentation for our RISC-V procesor!
 ## Modules
 - [[Decoder]]
+- [[Hart]]
