Merge branch 'main' of https://github.com/MIT-OpenCompute/RISC-V

Author: Turtlely

.gitignore

@@ -346,4 +346,7 @@ hs_err_pid*
 .bloop/
 
 # Emitted Verilog
-generated/
+generated/
+
+documentation/.obsidian/workspace.json
+documentation/.obsidian/appearance.json

README.md

@@ -97,7 +97,7 @@ class MainTemplateSpec extends AnyFreeSpec with Matchers with ChiselSim {
     simulate(new Main()) { dut =>
       // 1. Initialize registers (example: write value to x1)
       dut.io.write_enable.poke(true.B)
-      dut.io.write_addr.poke(1.U)
+      dut.io.write_address.poke(1.U)
       dut.io.in.poke(42.U)
       dut.clock.step(1)
       dut.io.write_enable.poke(false.B)
@@ -111,8 +111,8 @@ class MainTemplateSpec extends AnyFreeSpec with Matchers with ChiselSim {
 
       // 4. Read back a register value to verify the result
       //    Always use the C port of the register file for reading.
-      dut.io.read_addr_C.poke(1.U)   // Which register to read
-      dut.io.out_C.expect(42.U)      // Expected result (example)
+      dut.io.read_address_c.poke(1.U)   // Which register to read
+      dut.io.out_c.expect(42.U)      // Expected result (example)
     }
   }
 }

src/test/scala/RISCV/ALUSpec.scala disabled-tests/ALUSpec.scalasrc/test/scala/RISCV/ALUSpec.scala renamed to disabled-tests/ALUSpec.scala

@@ -12,79 +12,79 @@ class RegistersSpec extends AnyFreeSpec with Matchers with ChiselSim {
     simulate(new Registers()) { dut =>
       // Write to x1
       dut.io.write_enable.poke(true.B)
-      dut.io.write_addr.poke(1.U)
+      dut.io.write_address.poke(1.U)
       dut.io.in.poke(123.U(32.W))
       dut.clock.step(1)
 
       // Write to x2
-      dut.io.write_addr.poke(2.U)
+      dut.io.write_address.poke(2.U)
       dut.io.in.poke(456.U(32.W))
       dut.clock.step(1)
 
       // Read both registers
-      dut.io.read_addr_A.poke(1.U)
-      dut.io.read_addr_B.poke(2.U)
-      dut.io.out_A.expect(123.U(32.W))
-      dut.io.out_B.expect(456.U(32.W))
+      dut.io.read_address_a.poke(1.U)
+      dut.io.read_address_b.poke(2.U)
+      dut.io.out_a.expect(123.U(32.W))
+      dut.io.out_b.expect(456.U(32.W))
     }
   }
 
   "register x0 should always read as 0 and ignore writes" in {
     simulate(new Registers()) { dut =>
       // Attempt to write to x0
       dut.io.write_enable.poke(true.B)
-      dut.io.write_addr.poke(0.U)
+      dut.io.write_address.poke(0.U)
       dut.io.in.poke(999.U(32.W))
       dut.clock.step(1)
 
       // Read back x0
-      dut.io.read_addr_A.poke(0.U)
-      dut.io.read_addr_B.poke(0.U)
-      dut.io.out_A.expect(0.U(32.W))
-      dut.io.out_B.expect(0.U(32.W))
+      dut.io.read_address_a.poke(0.U)
+      dut.io.read_address_b.poke(0.U)
+      dut.io.out_a.expect(0.U(32.W))
+      dut.io.out_b.expect(0.U(32.W))
     }
   }
 
   "registers should update only when write_enable is true" in {
     simulate(new Registers()) { dut =>
       // Disable writing
       dut.io.write_enable.poke(false.B)
-      dut.io.write_addr.poke(3.U)
+      dut.io.write_address.poke(3.U)
       dut.io.in.poke(111.U(32.W))
       dut.clock.step(1)
 
       // Read back should still be 0
-      dut.io.read_addr_A.poke(3.U)
-      dut.io.out_A.expect(0.U(32.W))
+      dut.io.read_address_a.poke(3.U)
+      dut.io.out_a.expect(0.U(32.W))
     }
   }
 
   "registers should correctly handle multiple writes and reads" in {
     simulate(new Registers()) { dut =>
       // Write multiple registers
       dut.io.write_enable.poke(true.B)
-      dut.io.write_addr.poke(4.U)
+      dut.io.write_address.poke(4.U)
       dut.io.in.poke(10.U(32.W))
       dut.clock.step(1)
 
-      dut.io.write_addr.poke(5.U)
+      dut.io.write_address.poke(5.U)
       dut.io.in.poke(20.U(32.W))
       dut.clock.step(1)
 
-      dut.io.write_addr.poke(6.U)
+      dut.io.write_address.poke(6.U)
       dut.io.in.poke(30.U(32.W))
       dut.clock.step(1)
 
       // Read them back
-      dut.io.read_addr_A.poke(4.U)
-      dut.io.read_addr_B.poke(5.U)
-      dut.io.out_A.expect(10.U(32.W))
-      dut.io.out_B.expect(20.U(32.W))
+      dut.io.read_address_a.poke(4.U)
+      dut.io.read_address_b.poke(5.U)
+      dut.io.out_a.expect(10.U(32.W))
+      dut.io.out_b.expect(20.U(32.W))
 
-      dut.io.read_addr_A.poke(6.U)
-      dut.io.read_addr_B.poke(4.U)
-      dut.io.out_A.expect(30.U(32.W))
-      dut.io.out_B.expect(10.U(32.W))
+      dut.io.read_address_a.poke(6.U)
+      dut.io.read_address_b.poke(4.U)
+      dut.io.out_a.expect(30.U(32.W))
+      dut.io.out_b.expect(10.U(32.W))
     }
   }
 }

src/test/scala/RISCV/DecoderSpec.scala disabled-tests/DecoderSpec.scalasrc/test/scala/RISCV/DecoderSpec.scala renamed to disabled-tests/DecoderSpec.scala

@@ -0,0 +1,64 @@
+## Overview
+The Hart is the "hardware execution unit". This is the complex stuff comes together to actually execute the instructions. Right now it's stored in the `main.scala` file but we'll probably want to move it over to `hart.scala` later.
+## Instruction Staging
+Right now for simplicity, we're not doing anything too complex with how we're loading instructions. The way it works currently is a simple stage counter.
+### Stage 0
+The instruction at the program pointer is requested from memory.
+### Stage 1
+The instruction is available from memory and the decoder is now emitting the decoded instruction. We store the decoded instructions in buffers for access in later stages. Most instructions can simply execute in this stage and then set the stage counter back to 0 and increase the program pointer.
+## Stage 2
+Currently only the `LW` instruction uses stage 2, since in stage 1 `LW` requests the info from memory and then in stage 2 it takes the value from memory and writes it to the register.
+## Implemented Instructions
+### Main Integer Instructions
+- [x] LUI
+- [x] AUIPC
+- [x] ADDI
+- [x] SLTI
+- [x] SLTIU
+- [x] XORI
+- [x] ORI
+- [x] ANDI
+- [ ] SLLI
+- [ ] SRLI
+- [ ] SRAI
+- [x] ADD
+- [x] SUB
+- [ ] SLL
+- [ ] SLT
+- [ ] SLTU
+- [ ] XOR
+- [ ] SRL
+- [ ] SRA
+- [ ] OR
+- [ ] AND
+- [ ] LB
+- [ ] LH
+- [x] LW
+- [ ] LBU
+- [ ] LHU
+- [ ] SB
+- [ ] SH
+- [x] SW
+- [ ] JAL
+- [ ] JALR
+- [ ] BEQ
+- [ ] BNE
+- [ ] BLT
+- [ ] BGE
+- [ ] BLTU
+- [ ] BGEU
+### Other Integer Instructions
+- [ ] FENCE
+- [ ] FENCEI
+- [ ] ECALL
+- [ ] EBREAK
+- [ ] SRET
+- [ ] MRET
+- [ ] WFI
+- [ ] SFENCEVMA
+- [ ] CSRRW
+- [ ] CSRRS
+- [ ] CSRRC
+- [ ] CSRRWI
+- [ ] CSRRSI
+- [ ] CSRRCI

src/test/scala/RISCV/RegistersSpec.scala disabled-tests/RegistersSpec.scalasrc/test/scala/RISCV/RegistersSpec.scala renamed to disabled-tests/RegistersSpec.scala

@@ -1,3 +1,4 @@
 Welcome to the documentation for our RISC-V procesor!
 ## Modules
 - [[Decoder]]
+- [[Hart]]