【Bug】APLIC: setipnum/clripnum/setienum/clrienum do not strictly constrain writes to source numbers

[oChunCai]

Violated specification

setipnum/clripnum/setienum/clrienum have same constrain.

code

ChiselAIA/src/main/scala/APLIC.scala

Description

According to my understanding, The current implementation truncates the 32-bit write data to the lowest aplicIntSrcWidth bits to form the source index.

As a result, writes with values outside the legal source number range (which should be ignored) are instead alias-mapped to a different valid source number due to truncation, causing erroneous interrupt behavior.

Specifically, after source 1 has been configured as active, writing an out-of-range value 129 (0x81) to the setipnum register should be ignored according to the specification.

However, in the current XiangShan implementation, this write results in execution of ips.wBitUI(1, true.B), setting interrupt-pending for source 1.

So I think the code should probably add an in-range check to these two register writes, and only allow entering wBitUI() when the written 32-bit value falls within [1, intSrcNum-1]