From 24d54cbf6bdf40e4d6b80aeeee1b78b0e26572a6 Mon Sep 17 00:00:00 2001
From: shenlin <shen.lin1@zte.com.cn>
Date: Thu, 5 Feb 2026 14:18:03 +0800
Subject: [PATCH] perf vendor events riscv: fix lrw core PMU event mapping

driver inclusion
category: bugfix
Link: https://github.com/RVCK-Project/rvck/issues/216

--------------------------------

The lrw core PMU event definitions contained incorrect and unsupported
mappings, which caused perf to expose events that either did not work
or did not correspond to the hardware behavior.

- Removing unsupported events
- Correcting event names and codes
- Ensuring EventName, EventCode, and BriefDescription are consistent
  with the lrw core PMU specification

This fix improves the accuracy of perf event reporting on lrw core.

Signed-off-by: shenlin <shen.lin1@zte.com.cn>
Signed-off-by: liuqingtao <liu.qingtao2@zte.com.cn>
---
 .../arch/riscv/lrw/lrw-core/branch.json       | 15 ------------
 .../arch/riscv/lrw/lrw-core/general_cpu.json  |  5 ----
 .../arch/riscv/lrw/lrw-core/l3cache.json      | 24 +++++++++----------
 3 files changed, 12 insertions(+), 32 deletions(-)

diff --git a/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/branch.json b/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/branch.json
index 53ab39430e1ee..d35a9214d85f1 100644
--- a/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/branch.json
+++ b/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/branch.json
@@ -49,21 +49,6 @@
         "EventCode": "0x00020009",
         "BriefDescription": "Fetch queue empty"
     },
-    {
-        "EventName": "FETCH_MCACHE_INVALIDATE",
-        "EventCode": "0x00040009",
-        "BriefDescription": "Fetch mopcache invalidate"
-    },
-    {
-        "EventName": "FETCH_MCACHE_ICACHE_SWITCH",
-        "EventCode": "0x00080009",
-        "BriefDescription": "Fetch mopcache instruction cache switch"
-    },
-    {
-        "EventName": "FETCH_MCACHE_ICACHE_SWITCH_PENALTY",
-        "EventCode": "0x00100009",
-        "BriefDescription": "Fetch mopcache instruction cache switch penalty"
-    },
     {
         "EventName": "BR_PRED_BTB_RGN_UPDATE_NREADY",
         "EventCode": "0x00200009",
diff --git a/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/general_cpu.json b/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/general_cpu.json
index 51b01e841bd2c..df01332d6cc1a 100644
--- a/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/general_cpu.json
+++ b/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/general_cpu.json
@@ -1,9 +1,4 @@
 [
-    {
-        "EventName": "CID_WRITE_RETIRED",
-        "EventCode": "0x0000020b",
-        "BriefDescription": "CONTEXTIDR register write"
-    },
     {
         "EventName": "CPU_CYCLES",
         "EventCode": "0x0000040b",
diff --git a/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/l3cache.json b/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/l3cache.json
index b8262dc4eb0a5..a76e53da92961 100644
--- a/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/l3cache.json
+++ b/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/l3cache.json
@@ -1,32 +1,32 @@
 [
     {
-        "EventName": "L3_CACHE_ALLOCATE",
+        "EventName": "LL_CACHE_MISS_RD",
         "EventCode": "0x00000104",
-        "BriefDescription": "Attributable L 3 data cache allocation without refill"
+        "BriefDescription": "Last level cache miss, read"
     },
     {
-        "EventName": "L3_CACHE_REFILL",
+        "EventName": "LL_CACHE_RD",
         "EventCode": "0x00000204",
-        "BriefDescription": "Attributable L3 unified cache refill"
+        "BriefDescription": "Last level cache access, read"
     },
     {
-        "EventName": "L3_CACHE",
+        "EventName": "L3_CACHE_REFILL",
         "EventCode": "0x00000404",
-        "BriefDescription": "Attributable Level 3 unified cache access"
+        "BriefDescription": "Attributable L3 unified cache refill"
     },
     {
-        "EventName": "LL_CACHE_RD",
+        "EventName": "L3_CACHE_RD",
         "EventCode": "0x00000804",
-        "BriefDescription": "Last level cache access, read"
+        "BriefDescription": "L3 cache read"
     },
     {
-        "EventName": "LL_CACHE_MISS_RD",
+        "EventName": "L3_CACHE_ALLOCATE",
         "EventCode": "0x00001004",
-        "BriefDescription": "Last level cache miss, read"
+        "BriefDescription": "Attributable L3 data cache allocation without refill"
     },
     {
-        "EventName": "L3_CACHE_RD",
+        "EventName": "L3_CACHE",
         "EventCode": "0x00002004",
-        "BriefDescription": "L3 cache read"
+        "BriefDescription": "Attributable Level 3 unified cache access"
     }
 ]
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