From dc744b8d77b0da32f5f5a7c869d6244df525df2c Mon Sep 17 00:00:00 2001 From: Marco Celia Date: Mon, 3 Oct 2016 17:00:57 +0200 Subject: [PATCH 01/21] doxygen generated --- Doxyfile | 2427 +++++++++++++++++ html/_formulas.tex | 17 + html/annotated.html | 385 +++ html/arrowdown.png | Bin 0 -> 246 bytes html/arrowright.png | Bin 0 -> 229 bytes html/bc_s.png | Bin 0 -> 676 bytes html/bdwn.png | Bin 0 -> 147 bytes html/classes.html | 191 ++ html/closed.png | Bin 0 -> 132 bytes html/d0/d02/classRTSim_1_1ThreEvt.html | 168 ++ ...classRTSim_1_1SignalInstr__coll__graph.dot | 49 + ...classRTSim_1_1SignalInstr__coll__graph.md5 | 1 + html/d0/d0a/classCatch_1_1ScopedMessage.html | 129 + .../d0/d1a/classRTSim_1_1CPU__coll__graph.dot | 8 + .../d0/d1a/classRTSim_1_1CPU__coll__graph.md5 | 1 + .../classRTSim_1_1TaskEvt__coll__graph.dot | 44 + .../classRTSim_1_1TaskEvt__coll__graph.md5 | 1 + html/d0/d1b/classCatch_1_1StreamBufImpl.html | 119 + ...tch_1_1ValuesGenerator__inherit__graph.dot | 8 + ...tch_1_1ValuesGenerator__inherit__graph.md5 | 1 + html/d0/d27/classRTSim_1_1Interrupt.html | 247 ++ html/d0/d27/taskexc_8hpp_source.html | 109 + html/d0/d2f/classRTSim_1_1TraceTaskEvent.html | 286 ++ html/d0/d38/classRTSim_1_1DispatchEvt.html | 148 + ...assRTSim_1_1ResManager__inherit__graph.dot | 14 + ...assRTSim_1_1ResManager__inherit__graph.md5 | 1 + html/d0/d39/classRTSim_1_1AbsResManager.html | 264 ++ .../classRTSim_1_1ConstCTGen__coll__graph.dot | 30 + .../classRTSim_1_1ConstCTGen__coll__graph.md5 | 1 + ...TSim_1_1KernAlreadySet__inherit__graph.dot | 8 + ...TSim_1_1KernAlreadySet__inherit__graph.md5 | 1 + html/d0/d43/classRTSim_1_1EDFScheduler.html | 360 +++ ...1_1TraceDlinePostEvent__inherit__graph.dot | 10 + ...1_1TraceDlinePostEvent__inherit__graph.md5 | 1 + html/d0/d5b/classRTSim_1_1SchedEvt.html | 162 ++ ...1_1Impl_1_1MatcherImpl__inherit__graph.dot | 14 + ...1_1Impl_1_1MatcherImpl__inherit__graph.md5 | 1 + ...ssRTSim_1_1SporadicServer__coll__graph.dot | 30 + ...ssRTSim_1_1SporadicServer__coll__graph.md5 | 1 + html/d0/d76/classRTSim_1_1AVRTask.html | 463 ++++ ...sRTSim_1_1SuperCBS_1_1ChangeBudgetEvt.html | 137 + ...sRTSim_1_1UtilizationStat__coll__graph.dot | 8 + ...sRTSim_1_1UtilizationStat__coll__graph.md5 | 1 + html/d0/d82/structCatch_1_1ShowDurations.html | 118 + ...classRTSim_1_1SuperCBS__inherit__graph.dot | 10 + ...classRTSim_1_1SuperCBS__inherit__graph.md5 | 1 + ...assRTSim_1_1TraceEvent__inherit__graph.dot | 33 + ...assRTSim_1_1TraceEvent__inherit__graph.md5 | 1 + .../classRTSim_1_1SuperCBS__coll__graph.dot | 10 + .../classRTSim_1_1SuperCBS__coll__graph.md5 | 1 + html/d0/d94/classRTSim_1_1TraceWaitEvent.html | 290 ++ html/d0/d95/classRTSim_1_1SporadicDTGen.html | 203 ++ html/d0/d97/structCatch_1_1FalseType.html | 130 + html/d0/d9a/capacitytimer_8hpp_source.html | 104 + html/d0/da3/structStats.html | 134 + ...ssRTSim_1_1TraceNameEvent__coll__graph.dot | 12 + ...ssRTSim_1_1TraceNameEvent__coll__graph.md5 | 1 + ...RTSim_1_1SporadicDTGen__inherit__graph.dot | 12 + ...RTSim_1_1SporadicDTGen__inherit__graph.md5 | 1 + ...structCatch_1_1IConfig__inherit__graph.dot | 14 + ...structCatch_1_1IConfig__inherit__graph.md5 | 1 + ...hers_1_1Impl_1_1StdString_1_1EndsWith.html | 166 ++ ...assRTSim_1_1ConstCTGen__inherit__graph.dot | 10 + ...assRTSim_1_1ConstCTGen__inherit__graph.md5 | 1 + html/d0/de3/classRTSim_1_1SchedRTA.html | 281 ++ ...Catch_1_1StreamBufBase__inherit__graph.dot | 10 + ...Catch_1_1StreamBufBase__inherit__graph.md5 | 1 + ...RTSim_1_1TardinessStat__inherit__graph.dot | 8 + ...RTSim_1_1TardinessStat__inherit__graph.md5 | 1 + ...1_1FPScheduler_1_1FPModel__coll__graph.dot | 12 + ...1_1FPScheduler_1_1FPModel__coll__graph.md5 | 1 + ...lassRTSim_1_1OffsetGen__inherit__graph.dot | 12 + ...lassRTSim_1_1OffsetGen__inherit__graph.md5 | 1 + ...Catch_1_1BetweenGenerator__coll__graph.dot | 8 + ...Catch_1_1BetweenGenerator__coll__graph.md5 | 1 + ...assRTSim_1_1SchedPoint__inherit__graph.dot | 10 + ...assRTSim_1_1SchedPoint__inherit__graph.md5 | 1 + ...classRTSim_1_1Resource__inherit__graph.dot | 8 + ...classRTSim_1_1Resource__inherit__graph.md5 | 1 + .../d1/d09/classCatch_1_1AssertionResult.html | 168 ++ .../structCatch_1_1IShared__coll__graph.dot | 8 + .../structCatch_1_1IShared__coll__graph.md5 | 1 + .../classCatch_1_1Config__inherit__graph.dot | 14 + .../classCatch_1_1Config__inherit__graph.md5 | 1 + html/d1/d19/jtrace_8hpp_source.html | 105 + html/d1/d1d/classRTSim_1_1ArrEvt.html | 162 ++ .../d25/classRTSim_1_1DTGen__coll__graph.dot | 28 + .../d25/classRTSim_1_1DTGen__coll__graph.md5 | 1 + html/d1/d27/classCatch_1_1TagParser.html | 135 + html/d1/d28/classRTSim_1_1InstrExc.html | 132 + .../classRTSim_1_1ThreEvt__inherit__graph.dot | 10 + .../classRTSim_1_1ThreEvt__inherit__graph.md5 | 1 + ...ssRTSim_1_1FPScheduler__inherit__graph.dot | 12 + ...ssRTSim_1_1FPScheduler__inherit__graph.md5 | 1 + .../d43/classRTSim_1_1FeedbackTestModule.html | 162 ++ .../structCatch_1_1IGeneratorsForTest.html | 119 + html/d1/d4d/classRTSim_1_1TextTrace.html | 142 + ...ssRTSim_1_1GrubSupervisor__coll__graph.dot | 8 + ...ssRTSim_1_1GrubSupervisor__coll__graph.md5 | 1 + ...1_1FeedbackModuleARSim__inherit__graph.dot | 10 + ...1_1FeedbackModuleARSim__inherit__graph.md5 | 1 + ...RTSim_1_1PollingServer__inherit__graph.dot | 16 + ...RTSim_1_1PollingServer__inherit__graph.md5 | 1 + .../d1/d55/structCatch_1_1TestGroupStats.html | 138 + html/d1/d64/classRTSim_1_1MissPercentage.html | 138 + .../classRTSim_1_1BeginDispatchMultiEvt.html | 139 + ...ch_1_1Matchers_1_1Impl_1_1MatcherImpl.html | 153 ++ ...lassRTSim_1_1UniformCTGen__coll__graph.dot | 30 + ...lassRTSim_1_1UniformCTGen__coll__graph.md5 | 1 + ...m_1_1TaskAlreadyExecuting__coll__graph.dot | 8 + ...m_1_1TaskAlreadyExecuting__coll__graph.md5 | 1 + html/d1/d8c/classRTSim_1_1ConstIATGen.html | 247 ++ .../classRTSim_1_1EndDispatchMultiEvt.html | 145 + .../classRTSim_1_1KillEvt__coll__graph.dot | 44 + .../classRTSim_1_1KillEvt__coll__graph.md5 | 1 + ...ssCatch_1_1MethodTestCase__coll__graph.dot | 14 + ...ssCatch_1_1MethodTestCase__coll__graph.md5 | 1 + ...veReporterBase_1_1Node__inherit__graph.dot | 12 + ...veReporterBase_1_1Node__inherit__graph.md5 | 1 + ...ssRTSim_1_1DlineSetEvt__inherit__graph.dot | 10 + ...ssRTSim_1_1DlineSetEvt__inherit__graph.md5 | 1 + html/d1/db1/classRTSim_1_1IATGen.html | 191 ++ ...classRTSim_1_1TaskStatExc__coll__graph.dot | 8 + ...classRTSim_1_1TaskStatExc__coll__graph.md5 | 1 + ...tdString_1_1StartsWith__inherit__graph.dot | 16 + ...tdString_1_1StartsWith__inherit__graph.md5 | 1 + .../classRTSim_1_1GrubExc__coll__graph.dot | 10 + .../classRTSim_1_1GrubExc__coll__graph.md5 | 1 + html/d1/dc1/structCatch_1_1IShared.html | 131 + ...lassRTSim_1_1MissCount__inherit__graph.dot | 8 + ...lassRTSim_1_1MissCount__inherit__graph.md5 | 1 + .../classRTSim_1_1RTSchedExc__coll__graph.dot | 9 + .../classRTSim_1_1RTSchedExc__coll__graph.md5 | 1 + ...lassRTSim_1_1SignalEvt__inherit__graph.dot | 10 + ...lassRTSim_1_1SignalEvt__inherit__graph.md5 | 1 + ...assRTSim_1_1TardinessStat__coll__graph.dot | 8 + ...assRTSim_1_1TardinessStat__coll__graph.md5 | 1 + html/d1/ddb/bwi_8hpp_source.html | 108 + ...ctCatch_1_1StringMaker__inherit__graph.dot | 8 + ...ctCatch_1_1StringMaker__inherit__graph.md5 | 1 + .../structRTSim_1_1SchedPoint_1_1points.html | 116 + ...sRTSim_1_1SchedPoint_1_1SchedPointExc.html | 128 + html/d1/dfa/classRTSim_1_1MinIATGen.html | 264 ++ .../classRTSim_1_1RTModel__inherit__graph.dot | 8 + .../classRTSim_1_1RTModel__inherit__graph.md5 | 1 + html/d2/d01/structCatch_1_1Totals.html | 138 + .../classRTSim_1_1InstrExc__coll__graph.dot | 8 + .../classRTSim_1_1InstrExc__coll__graph.md5 | 1 + ...classRTSim_1_1RMScheduler__coll__graph.dot | 19 + ...classRTSim_1_1RMScheduler__coll__graph.md5 | 1 + ...im_1_1TaskNotExecuting__inherit__graph.dot | 8 + ...im_1_1TaskNotExecuting__inherit__graph.md5 | 1 + html/d2/d11/structCatch_1_1IRegistryHub.html | 122 + html/d2/d1b/classRTSim_1_1UniformCTGen.html | 238 ++ html/d2/d2a/classRTSim_1_1FixedInstr.html | 227 ++ ...atch_1_1MethodTestCase__inherit__graph.dot | 14 + ...atch_1_1MethodTestCase__inherit__graph.md5 | 1 + ...assRTSim_1_1FixedInstr__inherit__graph.dot | 12 + ...assRTSim_1_1FixedInstr__inherit__graph.md5 | 1 + html/d2/d3a/fcfsresmanager_8hpp_source.html | 107 + .../structCatch_1_1Totals__coll__graph.dot | 8 + .../structCatch_1_1Totals__coll__graph.md5 | 1 + .../d2/d40/classCatch_1_1ValuesGenerator.html | 134 + ...lassRTSim_1_1PeriodicTask__coll__graph.dot | 46 + ...lassRTSim_1_1PeriodicTask__coll__graph.md5 | 1 + ...TSim_1_1PreemptionStat__inherit__graph.dot | 8 + ...TSim_1_1PreemptionStat__inherit__graph.md5 | 1 + ...ssRTSim_1_1EndDispatchEvt__coll__graph.dot | 40 + ...ssRTSim_1_1EndDispatchEvt__coll__graph.md5 | 1 + html/d2/d54/structCatch_1_1pluralise.html | 133 + .../classRTSim_1_1AbsTask__inherit__graph.dot | 25 + .../classRTSim_1_1AbsTask__inherit__graph.md5 | 1 + html/d2/d56/group__tasks.html | 212 ++ ...RTSim_1_1ConsumedPower__inherit__graph.dot | 10 + ...RTSim_1_1ConsumedPower__inherit__graph.md5 | 1 + .../structCatch_1_1IMutableRegistryHub.html | 122 + .../classRTSim_1_1TaskAlreadyExecuting.html | 119 + ...classRTSim_1_1RTKernelExc__coll__graph.dot | 8 + ...classRTSim_1_1RTKernelExc__coll__graph.md5 | 1 + html/d2/d70/classRTSim_1_1BWI.html | 178 ++ html/d2/d71/structCatch_1_1AssertionInfo.html | 138 + html/d2/d7c/classCatch_1_1TagExtracter.html | 142 + .../d7e/classRTSim_1_1BWI__inherit__graph.dot | 10 + .../d7e/classRTSim_1_1BWI__inherit__graph.md5 | 1 + .../d2/d7e/structCatch_1_1MessageBuilder.html | 136 + html/d2/d7f/classRTSim_1_1JSONTrace.html | 152 ++ ...sCatch_1_1AssertionResult__coll__graph.dot | 12 + ...sCatch_1_1AssertionResult__coll__graph.md5 | 1 + ...assRTSim_1_1TraceArrEvent__coll__graph.dot | 12 + ...assRTSim_1_1TraceArrEvent__coll__graph.md5 | 1 + html/d2/d94/rtload_8hpp_source.html | 110 + html/d2/d95/classRTSim_1_1TaskEvt.html | 154 ++ .../d2/da3/classRTSim_1_1UtilizationStat.html | 141 + .../da4/classCatch_1_1Detail_1_1Approx.html | 154 ++ ...classRTSim_1_1MinCTGen__inherit__graph.dot | 12 + ...classRTSim_1_1MinCTGen__inherit__graph.md5 | 1 + ...assRTSim_1_1ConsumedPower__coll__graph.dot | 17 + ...assRTSim_1_1ConsumedPower__coll__graph.md5 | 1 + ...uctCatch_1_1Detail_1_1StringMakerBase.html | 117 + ...1Impl_1_1Generic_1_1AllOf__coll__graph.dot | 16 + ...1Impl_1_1Generic_1_1AllOf__coll__graph.md5 | 1 + html/d2/db7/classRTSim_1_1ModeOutOfIndex.html | 128 + .../db9/classRTSim_1_1TaskAlreadyActive.html | 119 + html/d2/dc0/structCatch_1_1StringMaker.html | 127 + .../dc5/structCatch_1_1IReporterRegistry.html | 126 + html/d2/dc7/namespaceRTSim.html | 588 ++++ .../classRTSim_1_1TracePowerConsumption.html | 173 ++ html/d2/de1/classRTSim_1_1SavedPower.html | 152 ++ html/d2/de6/classCatch_1_1ExpressionLhs.html | 173 ++ ...1Impl_1_1Generic_1_1AnyOf__coll__graph.dot | 16 + ...1Impl_1_1Generic_1_1AnyOf__coll__graph.md5 | 1 + html/d2/df3/classRTSim_1_1CBServer.html | 486 ++++ html/d2/df9/classRTSim_1_1TraceEvent.html | 334 +++ html/d2/dfc/classRTSim_1_1ThreInstr.html | 428 +++ ...lassRTSim_1_1Interrupt__inherit__graph.dot | 8 + ...lassRTSim_1_1Interrupt__inherit__graph.md5 | 1 + ...tructCatch_1_1IContext__inherit__graph.dot | 8 + ...tructCatch_1_1IContext__inherit__graph.md5 | 1 + html/d3/d04/classRTSim_1_1AbsRTTask.html | 253 ++ ..._1_1StreamingReporterBase__coll__graph.dot | 29 + ..._1_1StreamingReporterBase__coll__graph.md5 | 1 + ...assRTSim_1_1PollingServer__coll__graph.dot | 30 + ...assRTSim_1_1PollingServer__coll__graph.md5 | 1 + .../structCatch_1_1IConfig__coll__graph.dot | 10 + .../structCatch_1_1IConfig__coll__graph.md5 | 1 + ..._1_1TraceDlineSetEvent__inherit__graph.dot | 10 + ..._1_1TraceDlineSetEvent__inherit__graph.md5 | 1 + .../classRTSim_1_1EndEvt__inherit__graph.dot | 10 + .../classRTSim_1_1EndEvt__inherit__graph.md5 | 1 + .../classRTSim_1_1FixedInstr__coll__graph.dot | 54 + .../classRTSim_1_1FixedInstr__coll__graph.md5 | 1 + html/d3/d26/absresmanager_8hpp_source.html | 108 + html/d3/d2b/classRTSim_1_1EndInstrEvt.html | 139 + ...classRTSim_1_1SparePot_1_1SparePotExc.html | 128 + ..._1GlobalPreemptionStat__inherit__graph.dot | 8 + ..._1GlobalPreemptionStat__inherit__graph.md5 | 1 + ...tch_1_1IStreamingReporter__coll__graph.dot | 10 + ...tch_1_1IStreamingReporter__coll__graph.md5 | 1 + ...m_1_1GlobalPreemptionStat__coll__graph.dot | 8 + ...m_1_1GlobalPreemptionStat__coll__graph.md5 | 1 + ...TSim_1_1GrubSupervisor__inherit__graph.dot | 8 + ...TSim_1_1GrubSupervisor__inherit__graph.md5 | 1 + ...lassCatch_1_1TagParser__inherit__graph.dot | 10 + ...lassCatch_1_1TagParser__inherit__graph.md5 | 1 + html/d3/d66/classRTSim_1_1UniformIATGen.html | 265 ++ html/d3/d67/classRTSim_1_1FakeArrEvt.html | 162 ++ .../classRTSim_1_1ExecInstr__coll__graph.dot | 52 + .../classRTSim_1_1ExecInstr__coll__graph.md5 | 1 + .../d73/classRTSim_1_1WrongParameterSize.html | 128 + ...01T2_00_01IsGreaterThanOrEqualTo_01_4.html | 116 + .../classRTSim_1_1EmptyTask__coll__graph.dot | 8 + .../classRTSim_1_1EmptyTask__coll__graph.md5 | 1 + html/d3/d85/classRTSim_1_1EmptyTask.html | 119 + ...RandomRTTaskSetFactory__inherit__graph.dot | 8 + ...RandomRTTaskSetFactory__inherit__graph.md5 | 1 + html/d3/d94/classRTSim_1_1TaskNotActive.html | 128 + html/d3/d9c/classRTSim_1_1Desc.html | 129 + .../db5/classRTSim_1_1Server__coll__graph.dot | 28 + .../db5/classRTSim_1_1Server__coll__graph.md5 | 1 + .../classRTSim_1_1ServerExc__coll__graph.dot | 8 + .../classRTSim_1_1ServerExc__coll__graph.md5 | 1 + ...Point_1_1SchedPointExc__inherit__graph.dot | 8 + ...Point_1_1SchedPointExc__inherit__graph.md5 | 1 + html/d3/dbc/classRTSim_1_1TaskModel.html | 409 +++ html/d3/dbd/classRTSim_1_1ConsumedPower.html | 148 + ...classRTSim_1_1AbstractGen__coll__graph.dot | 30 + ...classRTSim_1_1AbstractGen__coll__graph.md5 | 1 + .../classRTSim_1_1GlobalPreemptionStat.html | 144 + .../structCatch_1_1Detail_1_1BorgType.html | 117 + html/d3/de3/mrtkernel_8hpp_source.html | 119 + html/d3/de7/rttask_8hpp_source.html | 106 + html/d3/deb/classRTSim_1_1NoSuchInstr.html | 119 + html/d3/df1/classRTSim_1_1PreemptionStat.html | 149 + .../classRTSim_1_1SchedInstr__coll__graph.dot | 49 + .../classRTSim_1_1SchedInstr__coll__graph.md5 | 1 + ...im_1_1DlineEquPeriodDTGen__coll__graph.dot | 31 + ...im_1_1DlineEquPeriodDTGen__coll__graph.md5 | 1 + html/d4/d00/classRTSim_1_1MissCount.html | 138 + html/d4/d17/structCatch_1_1IContext.html | 134 + html/d4/d18/sparepot_8hpp_source.html | 110 + ...m_1_1uniformCPUFactory__inherit__graph.dot | 8 + ...m_1_1uniformCPUFactory__inherit__graph.md5 | 1 + ...classRTSim_1_1RTKernel__inherit__graph.dot | 12 + ...classRTSim_1_1RTKernel__inherit__graph.md5 | 1 + html/d4/d2e/classRTSim_1_1PeriodicTask.html | 391 +++ .../structCatch_1_1TestFailureException.html | 107 + ...TSim_1_1TraceWaitEvent__inherit__graph.dot | 10 + ...TSim_1_1TraceWaitEvent__inherit__graph.md5 | 1 + .../d45/classRTSim_1_1IATGen__coll__graph.dot | 28 + .../d45/classRTSim_1_1IATGen__coll__graph.md5 | 1 + ...assRTSim_1_1CapacityTimer__coll__graph.dot | 8 + ...assRTSim_1_1CapacityTimer__coll__graph.md5 | 1 + .../classRTSim_1_1Instr__inherit__graph.dot | 23 + .../classRTSim_1_1Instr__inherit__graph.md5 | 1 + ...assRTSim_1_1FakeArrEvt__inherit__graph.dot | 10 + ...assRTSim_1_1FakeArrEvt__inherit__graph.md5 | 1 + html/d4/d61/classRTSim_1_1GrubSupervisor.html | 157 ++ html/d4/d63/classCatch_1_1Stream.html | 126 + html/d4/d68/classRTSim_1_1Timer.html | 154 ++ html/d4/d6b/classRTSim_1_1JavaTrace.html | 183 ++ html/d4/d7e/structCatch_1_1SectionInfo.html | 135 + ...TSim_1_1TaskAlreadyActive__coll__graph.dot | 8 + ...TSim_1_1TaskAlreadyActive__coll__graph.md5 | 1 + html/d4/d90/classRTSim_1_1absCPUFactory.html | 153 ++ html/d4/d98/classRTSim_1_1MinCTGen.html | 237 ++ ...1_1AbstractFeedbackModule__coll__graph.dot | 44 + ...1_1AbstractFeedbackModule__coll__graph.md5 | 1 + ...lassRTSim_1_1AbsKernel__inherit__graph.dot | 21 + ...lassRTSim_1_1AbsKernel__inherit__graph.md5 | 1 + ...lassRTSim_1_1AbsRTTask__inherit__graph.dot | 25 + ...lassRTSim_1_1AbsRTTask__inherit__graph.md5 | 1 + .../classRTSim_1_1Interrupt__coll__graph.dot | 8 + .../classRTSim_1_1Interrupt__coll__graph.md5 | 1 + html/d4/dc4/classRTSim_1_1SignalInstr.html | 440 +++ .../classRTSim_1_1WaitEvt__coll__graph.dot | 52 + .../classRTSim_1_1WaitEvt__coll__graph.md5 | 1 + ...Catch_1_1StreamBufImpl__inherit__graph.dot | 10 + ...Catch_1_1StreamBufImpl__inherit__graph.md5 | 1 + html/d4/dde/classRTSim_1_1CapacityTimer.html | 175 ++ html/d4/de1/classRTSim_1_1Server.html | 1299 +++++++++ ...uctCatch_1_1IGenerator__inherit__graph.dot | 10 + ...uctCatch_1_1IGenerator__inherit__graph.md5 | 1 + .../d4/dec/structCatch_1_1IGeneratorInfo.html | 119 + html/d4/dfb/feedbacktest_8hpp_source.html | 107 + ...TSim_1_1SporadicServer__inherit__graph.dot | 16 + ...TSim_1_1SporadicServer__inherit__graph.md5 | 1 + html/d5/d02/taskevt_8hpp_source.html | 113 + html/d5/d05/classRTSim_1_1ConstCTGen.html | 186 ++ .../classRTSim_1_1EDFModel__coll__graph.dot | 12 + .../classRTSim_1_1EDFModel__coll__graph.md5 | 1 + ...im_1_1TraceDlineMissEvent__coll__graph.dot | 12 + ...im_1_1TraceDlineMissEvent__coll__graph.md5 | 1 + ...m_1_1FinishingTimeStat__inherit__graph.dot | 8 + ...m_1_1FinishingTimeStat__inherit__graph.md5 | 1 + html/d5/d13/classRTSim_1_1SparePot.html | 365 +++ ...lassRTSim_1_1WaitInstr__inherit__graph.dot | 10 + ...lassRTSim_1_1WaitInstr__inherit__graph.md5 | 1 + ...RTSim_1_1FIFOScheduler__inherit__graph.dot | 10 + ...RTSim_1_1FIFOScheduler__inherit__graph.md5 | 1 + ...or_3_01T1_00_01T2_00_01IsEqualTo_01_4.html | 116 + .../classRTSim_1_1SparePot__coll__graph.dot | 10 + .../classRTSim_1_1SparePot__coll__graph.md5 | 1 + ...assRTSim_1_1TaskModel_1_1TaskModelCmp.html | 117 + ...ch_1_1TagExpressionParser__coll__graph.dot | 8 + ...ch_1_1TagExpressionParser__coll__graph.md5 | 1 + html/d5/d30/texttrace_8hpp_source.html | 112 + ...im_1_1BeginDispatchEvt__inherit__graph.dot | 10 + ...im_1_1BeginDispatchEvt__inherit__graph.md5 | 1 + html/d5/d3f/classRTSim_1_1TaskStatExc.html | 128 + html/d5/d42/classRTSim_1_1KillEvt.html | 169 ++ ...ssRTSim_1_1DispatchEvt__inherit__graph.dot | 10 + ...ssRTSim_1_1DispatchEvt__inherit__graph.md5 | 1 + ...classRTSim_1_1NoSuchInstr__coll__graph.dot | 8 + ...classRTSim_1_1NoSuchInstr__coll__graph.md5 | 1 + ...lassRTSim_1_1Scheduler__inherit__graph.dot | 18 + ...lassRTSim_1_1Scheduler__inherit__graph.md5 | 1 + ...uctCatch_1_1AssertionInfo__coll__graph.dot | 8 + ...uctCatch_1_1AssertionInfo__coll__graph.md5 | 1 + ...RTSim_1_1TaskNotExecuting__coll__graph.dot | 8 + ...RTSim_1_1TaskNotExecuting__coll__graph.md5 | 1 + html/d5/d62/classRTSim_1_1OffsetGen.html | 180 ++ ...assRTSim_1_1UniformIATGen__coll__graph.dot | 30 + ...assRTSim_1_1UniformIATGen__coll__graph.md5 | 1 + .../classRTSim_1_1DeschedEvt__coll__graph.dot | 44 + .../classRTSim_1_1DeschedEvt__coll__graph.md5 | 1 + ...ssRTSim_1_1SignalInstr__inherit__graph.dot | 10 + ...ssRTSim_1_1SignalInstr__inherit__graph.md5 | 1 + html/d5/d7c/tracepower_8hpp_source.html | 106 + ...TSim_1_1SchedPoint_1_1ChangeBudgetEvt.html | 137 + .../classRTSim_1_1CTGen__inherit__graph.dot | 16 + .../classRTSim_1_1CTGen__inherit__graph.md5 | 1 + html/d5/d8c/structCatch_1_1ResultWas.html | 129 + ..._1NotImplementedException__coll__graph.dot | 8 + ..._1NotImplementedException__coll__graph.md5 | 1 + .../classRTSim_1_1CBServer__coll__graph.dot | 30 + .../classRTSim_1_1CBServer__coll__graph.md5 | 1 + html/d5/d94/structCatch_1_1NameAndDesc.html | 126 + html/d5/d99/classRTSim_1_1Supervisor.html | 129 + html/d5/da2/schedrta_8hpp_source.html | 109 + ...ssRTSim_1_1FCFSResManager__coll__graph.dot | 22 + ...ssRTSim_1_1FCFSResManager__coll__graph.md5 | 1 + .../classCatch_1_1Option__inherit__graph.dot | 8 + .../classCatch_1_1Option__inherit__graph.md5 | 1 + html/d5/dbb/classCatch_1_1TestCaseFilter.html | 122 + .../d5/dc3/classCatch_1_1TestCaseFilters.html | 128 + html/d5/dc7/resource_8hpp_source.html | 105 + ...1BeginDispatchMultiEvt__inherit__graph.dot | 8 + ...1BeginDispatchMultiEvt__inherit__graph.md5 | 1 + ...m_1_1TraceDeschedEvent__inherit__graph.dot | 12 + ...m_1_1TraceDeschedEvent__inherit__graph.md5 | 1 + ...sCatch_1_1ValuesGenerator__coll__graph.dot | 8 + ...sCatch_1_1ValuesGenerator__coll__graph.md5 | 1 + .../structCatch_1_1LazyStat__coll__graph.dot | 8 + .../structCatch_1_1LazyStat__coll__graph.md5 | 1 + ...assCatch_1_1ScopedMessage__coll__graph.dot | 10 + ...assCatch_1_1ScopedMessage__coll__graph.md5 | 1 + ...1_1RandomRTTaskSetFactory__coll__graph.dot | 32 + ...1_1RandomRTTaskSetFactory__coll__graph.md5 | 1 + html/d5/dec/rtsched_8hpp_source.html | 123 + .../structCatch_1_1IStreamingReporter.html | 168 ++ ..._1_1BeginDispatchMultiEvt__coll__graph.dot | 8 + ..._1_1BeginDispatchMultiEvt__coll__graph.md5 | 1 + ...structCatch_1_1IShared__inherit__graph.dot | 69 + ...structCatch_1_1IShared__inherit__graph.md5 | 1 + .../structCatch_1_1IReporter__coll__graph.dot | 10 + .../structCatch_1_1IReporter__coll__graph.md5 | 1 + html/d6/d0e/structCatch_1_1IRunner.html | 107 + .../classRTSim_1_1TraceDlineMissEvent.html | 226 ++ ...1TracePowerConsumption__inherit__graph.dot | 14 + ...1TracePowerConsumption__inherit__graph.md5 | 1 + ...ctCatch_1_1AssertionStats__coll__graph.dot | 18 + ...ctCatch_1_1AssertionStats__coll__graph.md5 | 1 + ...tch_1_1IMutableContext__inherit__graph.dot | 8 + ...tch_1_1IMutableContext__inherit__graph.md5 | 1 + html/d6/d22/classRTSim_1_1CTGen.html | 185 ++ html/d6/d24/classRTSim_1_1RRScheduler.html | 459 ++++ ...1StdString_1_1EndsWith__inherit__graph.dot | 16 + ...1StdString_1_1EndsWith__inherit__graph.md5 | 1 + html/d6/d27/structCatch_1_1TestRunStats.html | 138 + ...ructCatch_1_1ITestCase__inherit__graph.dot | 14 + ...ructCatch_1_1ITestCase__inherit__graph.md5 | 1 + ...tCatch_1_1StringMaker_3_01T_01_5_01_4.html | 117 + ...classRTSim_1_1DispatchEvt__coll__graph.dot | 42 + ...classRTSim_1_1DispatchEvt__coll__graph.md5 | 1 + ..._1_1StdString_1_1Contains__coll__graph.dot | 16 + ..._1_1StdString_1_1Contains__coll__graph.md5 | 1 + html/d6/d46/classRTSim_1_1TardinessStat.html | 141 + ...TSim_1_1FinishingTimeStat__coll__graph.dot | 8 + ...TSim_1_1FinishingTimeStat__coll__graph.md5 | 1 + .../classRTSim_1_1MissCount__coll__graph.dot | 8 + .../classRTSim_1_1MissCount__coll__graph.md5 | 1 + ...ssRTSim_1_1KernAlreadySet__coll__graph.dot | 8 + ...ssRTSim_1_1KernAlreadySet__coll__graph.md5 | 1 + .../classRTSim_1_1SchedRTA__coll__graph.dot | 10 + .../classRTSim_1_1SchedRTA__coll__graph.md5 | 1 + html/d6/d6d/classCatch_1_1TagSet.html | 122 + ..._1_1WrongParameterSize__inherit__graph.dot | 8 + ..._1_1WrongParameterSize__inherit__graph.md5 | 1 + .../d6/d6e/structCatch_1_1IResultCapture.html | 140 + html/d6/d78/pollingserver_8hpp_source.html | 117 + .../d7c/classRTSim_1_1Timer__coll__graph.dot | 8 + .../d7c/classRTSim_1_1Timer__coll__graph.md5 | 1 + ..._1StdString_1_1StartsWith__coll__graph.dot | 16 + ..._1StdString_1_1StartsWith__coll__graph.md5 | 1 + ...orTraits_3_01IsLessThanOrEqualTo_01_4.html | 116 + html/d6/d8d/classRTSim_1_1SuspendInstr.html | 386 +++ .../d8f/classRTSim_1_1BeginDispatchEvt.html | 149 + html/d6/d90/classSystem__coll__graph.dot | 103 + html/d6/d90/classSystem__coll__graph.md5 | 1 + .../d99/classCatch_1_1CompositeGenerator.html | 131 + html/d6/d9d/classRTSim_1_1Scheduler.html | 1154 ++++++++ .../classRTSim_1_1RandomRTTaskSetFactory.html | 377 +++ .../classRTSim_1_1SchedIEvt__coll__graph.dot | 52 + .../classRTSim_1_1SchedIEvt__coll__graph.md5 | 1 + ...lassCatch_1_1TagExtracter__coll__graph.dot | 8 + ...lassCatch_1_1TagExtracter__coll__graph.md5 | 1 + .../classRTSim_1_1ArrEvt__inherit__graph.dot | 10 + .../classRTSim_1_1ArrEvt__inherit__graph.md5 | 1 + ...classRTSim_1_1SchedEvt__inherit__graph.dot | 10 + ...classRTSim_1_1SchedEvt__inherit__graph.md5 | 1 + html/d6/dc4/structStats__coll__graph.dot | 18 + html/d6/dc4/structStats__coll__graph.md5 | 1 + .../classRTSim_1_1Timer__inherit__graph.dot | 12 + .../classRTSim_1_1Timer__inherit__graph.md5 | 1 + html/d6/dc8/abstask_8hpp_source.html | 109 + .../dc8/structCatch_1_1ITestCaseRegistry.html | 119 + ...1Matchers_1_1Impl_1_1Generic_1_1AnyOf.html | 159 ++ ...ssRTSim_1_1TraceWaitEvent__coll__graph.dot | 12 + ...ssRTSim_1_1TraceWaitEvent__coll__graph.md5 | 1 + ...assCatch_1_1StreamBufBase__coll__graph.dot | 8 + ...assCatch_1_1StreamBufBase__coll__graph.md5 | 1 + ...porterBase_1_1SectionNode__coll__graph.dot | 20 + ...porterBase_1_1SectionNode__coll__graph.md5 | 1 + ...TSim_1_1TraceDeschedEvent__coll__graph.dot | 14 + ...TSim_1_1TraceDeschedEvent__coll__graph.md5 | 1 + html/d6/de8/scheduler_8hpp_source.html | 121 + html/d6/de9/schedpoints_8hpp_source.html | 109 + html/d6/deb/feedbackarsim_8hpp_source.html | 107 + .../classRTSim_1_1Resource__coll__graph.dot | 12 + .../classRTSim_1_1Resource__coll__graph.md5 | 1 + html/d6/df4/classCatch_1_1TestCase.html | 196 ++ ...parePot_1_1server__struct__coll__graph.dot | 32 + ...parePot_1_1server__struct__coll__graph.md5 | 1 + ...arePot_1_1ChangeBudgetEvt__coll__graph.dot | 8 + ...arePot_1_1ChangeBudgetEvt__coll__graph.md5 | 1 + ...ndomTaskSetFactory_1_1Exc__coll__graph.dot | 8 + ...ndomTaskSetFactory_1_1Exc__coll__graph.md5 | 1 + ...1_1TraceDlineMissEvent__inherit__graph.dot | 10 + ...1_1TraceDlineMissEvent__inherit__graph.md5 | 1 + .../d15/classRTSim_1_1TraceDeschedEvent.html | 237 ++ .../d1a/classRTSim_1_1TraceDlineSetEvent.html | 317 +++ .../d29/classRTSim_1_1EndEvt__coll__graph.dot | 44 + .../d29/classRTSim_1_1EndEvt__coll__graph.md5 | 1 + .../classCatch_1_1TagExpressionParser.html | 135 + html/d7/d37/structCatch_1_1MessageInfo.html | 147 + ...1_1CumulativeReporterBase__coll__graph.dot | 19 + ...1_1CumulativeReporterBase__coll__graph.md5 | 1 + ...tail_1_1StringMakerBase_3_01true_01_4.html | 117 + html/d7/d3d/classRTSim_1_1TraceArrEvent.html | 226 ++ html/d7/d3d/structCatch_1_1GroupInfo.html | 129 + .../d43/classRTSim_1_1TraceSignalEvent.html | 290 ++ html/d7/d43/waitinstr_8hpp_source.html | 122 + ..._1SparePot_1_1SparePotExc__coll__graph.dot | 8 + ..._1SparePot_1_1SparePotExc__coll__graph.md5 | 1 + html/d7/d58/classRTSim_1_1TraceNameEvent.html | 264 ++ .../classRTSim_1_1DTGen__inherit__graph.dot | 18 + .../classRTSim_1_1DTGen__inherit__graph.md5 | 1 + html/d7/d67/classRTSim_1_1MaxIATGen.html | 264 ++ html/d7/d69/classRTSim_1_1SchedPoint.html | 320 +++ ...im_1_1FeedbackModuleARSim__coll__graph.dot | 46 + ...im_1_1FeedbackModuleARSim__coll__graph.md5 | 1 + ...ctCatch_1_1TestGroupStats__coll__graph.dot | 12 + ...ctCatch_1_1TestGroupStats__coll__graph.md5 | 1 + ...Sim_1_1UtilizationStat__inherit__graph.dot | 8 + ...Sim_1_1UtilizationStat__inherit__graph.md5 | 1 + ...Catch_1_1IExceptionTranslatorRegistry.html | 116 + html/d7/d91/structCatch_1_1SharedImpl.html | 138 + ...ructCatch_1_1SectionStats__coll__graph.dot | 12 + ...ructCatch_1_1SectionStats__coll__graph.md5 | 1 + ...1_1RRScheduler_1_1RRModel__coll__graph.dot | 12 + ...1_1RRScheduler_1_1RRModel__coll__graph.md5 | 1 + ...1StdString_1_1Contains__inherit__graph.dot | 16 + ...1StdString_1_1Contains__inherit__graph.md5 | 1 + ...CumulativeReporterBase_1_1SectionNode.html | 174 ++ .../structCatch_1_1ReporterPreferences.html | 116 + ...classRTSim_1_1EDFModel__inherit__graph.dot | 8 + ...classRTSim_1_1EDFModel__inherit__graph.md5 | 1 + html/d7/dc7/classCatch_1_1Option.html | 161 ++ html/d7/dca/rmsched_8hpp_source.html | 111 + ...ssRTSim_1_1ConstIATGen__inherit__graph.dot | 10 + ...ssRTSim_1_1ConstIATGen__inherit__graph.md5 | 1 + ...assRTSim_1_1RRScheduler_1_1RRSchedExc.html | 128 + ...classRTSim_1_1RandomDTGen__coll__graph.dot | 31 + ...classRTSim_1_1RandomDTGen__coll__graph.md5 | 1 + .../structCatch_1_1AssertionResultData.html | 122 + ...ructCatch_1_1IReporter__inherit__graph.dot | 10 + ...ructCatch_1_1IReporter__inherit__graph.md5 | 1 + ..._1_1IStreamingReporter__inherit__graph.dot | 16 + ..._1_1IStreamingReporter__inherit__graph.md5 | 1 + ...pl_1_1Generic_1_1AllOf__inherit__graph.dot | 16 + ...pl_1_1Generic_1_1AllOf__inherit__graph.md5 | 1 + ...Catch_1_1ExceptionTranslatorRegistrar.html | 118 + html/d7/dfe/classCatch_1_1TagExpression.html | 123 + ...1_1StdString_1_1Equals__inherit__graph.dot | 16 + ...1_1StdString_1_1Equals__inherit__graph.md5 | 1 + .../classRTSim_1_1MinCTGen__coll__graph.dot | 32 + .../classRTSim_1_1MinCTGen__coll__graph.md5 | 1 + html/d8/d11/json__trace_8hpp_source.html | 109 + ...classRTSim_1_1DlineSetEvt__coll__graph.dot | 46 + ...classRTSim_1_1DlineSetEvt__coll__graph.md5 | 1 + ...assCatch_1_1StreamBufImpl__coll__graph.dot | 10 + ...assCatch_1_1StreamBufImpl__coll__graph.md5 | 1 + html/d8/d1e/classRTSim_1_1SporadicServer.html | 469 ++++ ...Sim_1_1WrongParameterSize__coll__graph.dot | 8 + ...Sim_1_1WrongParameterSize__coll__graph.md5 | 1 + ...1_1SchedRTA_1_1ServerInfo__coll__graph.dot | 30 + ...1_1SchedRTA_1_1ServerInfo__coll__graph.md5 | 1 + ...pl_1_1Generic_1_1AnyOf__inherit__graph.dot | 16 + ...pl_1_1Generic_1_1AnyOf__inherit__graph.md5 | 1 + html/d8/d3a/classRTSim_1_1Resource.html | 182 ++ html/d8/d44/classCatch_1_1Timer.html | 125 + html/d8/d44/classRTSim_1_1FCFSResManager.html | 197 ++ .../d44/classRTSim_1_1Instr__coll__graph.dot | 47 + .../d44/classRTSim_1_1Instr__coll__graph.md5 | 1 + html/d8/d4c/rrsched_8hpp_source.html | 112 + ...ructCatch_1_1TestRunStats__coll__graph.dot | 12 + ...ructCatch_1_1TestRunStats__coll__graph.md5 | 1 + html/d8/d59/structRTSim_1_1cpulevel.html | 125 + ...assRTSim_1_1SporadicDTGen__coll__graph.dot | 31 + ...assRTSim_1_1SporadicDTGen__coll__graph.md5 | 1 + html/d8/d60/kernevt_8hpp_source.html | 107 + .../d62/structCatch_1_1ResultDisposition.html | 119 + ...otImplementedException__inherit__graph.dot | 8 + ...otImplementedException__inherit__graph.md5 | 1 + html/d8/d7e/classRTSim_1_1DeadEvt.html | 178 ++ ...pl_1_1StdString_1_1Equals__coll__graph.dot | 16 + ...pl_1_1StdString_1_1Equals__coll__graph.md5 | 1 + ...lassRTSim_1_1TaskModel__inherit__graph.dot | 15 + ...lassRTSim_1_1TaskModel__inherit__graph.md5 | 1 + ...terBase_1_1SectionNode__inherit__graph.dot | 12 + ...terBase_1_1SectionNode__inherit__graph.md5 | 1 + ...classRTSim_1_1ConstIATGen__coll__graph.dot | 30 + ...classRTSim_1_1ConstIATGen__coll__graph.md5 | 1 + ...RTSim_1_1BeginDispatchEvt__coll__graph.dot | 40 + ...RTSim_1_1BeginDispatchEvt__coll__graph.md5 | 1 + html/d8/da0/classRTSim_1_1TraceEndEvent.html | 237 ++ html/d8/da1/task_8hpp_source.html | 166 ++ ...RTSim_1_1TraceArrEvent__inherit__graph.dot | 10 + ...RTSim_1_1TraceArrEvent__inherit__graph.md5 | 1 + html/d8/db0/classRTSim_1_1Task.html | 1633 +++++++++++ ...FPScheduler_1_1FPModel__inherit__graph.dot | 8 + ...FPScheduler_1_1FPModel__inherit__graph.md5 | 1 + ...RTSim_1_1absCPUFactory__inherit__graph.dot | 8 + ...RTSim_1_1absCPUFactory__inherit__graph.md5 | 1 + .../classRTSim_1_1FeedbackModuleARSim.html | 306 +++ ...1_1OperatorTraits_3_01IsLessThan_01_4.html | 116 + ...TSim_1_1EndDispatchEvt__inherit__graph.dot | 10 + ...TSim_1_1EndDispatchEvt__inherit__graph.md5 | 1 + ...ructCatch_1_1TestCaseInfo__coll__graph.dot | 8 + ...ructCatch_1_1TestCaseInfo__coll__graph.md5 | 1 + html/d8/df1/feedback_8hpp_source.html | 105 + ...lassRTSim_1_1ThreInstr__inherit__graph.dot | 10 + ...lassRTSim_1_1ThreInstr__inherit__graph.md5 | 1 + ...lassRTSim_1_1ServerExc__inherit__graph.dot | 10 + ...lassRTSim_1_1ServerExc__inherit__graph.md5 | 1 + html/d8/dfd/threinstr_8hpp_source.html | 115 + ...CumulativeReporterBase__inherit__graph.dot | 14 + ...CumulativeReporterBase__inherit__graph.md5 | 1 + ...RRScheduler_1_1RRSchedExc__coll__graph.dot | 8 + ...RRScheduler_1_1RRSchedExc__coll__graph.md5 | 1 + ...mTaskSetFactory_1_1Exc__inherit__graph.dot | 8 + ...mTaskSetFactory_1_1Exc__inherit__graph.md5 | 1 + html/d9/d11/classRTSim_1_1TraceCPUEvent.html | 290 ++ html/d9/d14/classCatch_1_1StreamBufBase.html | 119 + .../d9/d1c/classRTSim_1_1RandomOffsetGen.html | 190 ++ html/d9/d24/classRTSim_1_1RTModel.html | 504 ++++ .../namespaceRTSim_1_1____sched__stub.html | 104 + ...ch_1_1BetweenGenerator__inherit__graph.dot | 8 + ...ch_1_1BetweenGenerator__inherit__graph.md5 | 1 + ...ers_1_1Impl_1_1Matcher__inherit__graph.dot | 23 + ...ers_1_1Impl_1_1Matcher__inherit__graph.md5 | 1 + html/d9/d29/exeinstr_8hpp_source.html | 117 + .../classRTSim_1_1FPScheduler_1_1FPModel.html | 257 ++ ...assRTSim_1_1Supervisor__inherit__graph.dot | 14 + ...assRTSim_1_1Supervisor__inherit__graph.md5 | 1 + ...im_1_1EndDispatchMultiEvt__coll__graph.dot | 8 + ...im_1_1EndDispatchMultiEvt__coll__graph.md5 | 1 + ...RTSim_1_1TraceCPUEvent__inherit__graph.dot | 16 + ...RTSim_1_1TraceCPUEvent__inherit__graph.md5 | 1 + .../classRTSim_1_1SchedEvt__coll__graph.dot | 44 + .../classRTSim_1_1SchedEvt__coll__graph.md5 | 1 + html/d9/d31/fpsched_8hpp_source.html | 114 + ...uctCatch_1_1SharedImpl__inherit__graph.dot | 8 + ...uctCatch_1_1SharedImpl__inherit__graph.md5 | 1 + .../classRTSim_1_1GrubExc__inherit__graph.dot | 10 + .../classRTSim_1_1GrubExc__inherit__graph.md5 | 1 + .../structCatch_1_1ITestCase__coll__graph.dot | 10 + .../structCatch_1_1ITestCase__coll__graph.md5 | 1 + ...lassRTSim_1_1MinIATGen__inherit__graph.dot | 12 + ...lassRTSim_1_1MinIATGen__inherit__graph.md5 | 1 + ...rs_1_1Impl_1_1StdString_1_1StartsWith.html | 166 ++ ...assRTSim_1_1FIFOScheduler__coll__graph.dot | 17 + ...assRTSim_1_1FIFOScheduler__coll__graph.md5 | 1 + .../classRTSim_1_1SchedPoint__coll__graph.dot | 10 + .../classRTSim_1_1SchedPoint__coll__graph.md5 | 1 + ...TSim_1_1TraceIdleEvent__inherit__graph.dot | 10 + ...TSim_1_1TraceIdleEvent__inherit__graph.md5 | 1 + ...hers_1_1Impl_1_1StdString_1_1Contains.html | 166 ++ .../classCatch_1_1TestCase__coll__graph.dot | 10 + .../classCatch_1_1TestCase__coll__graph.md5 | 1 + html/d9/d6f/grubserver_8hpp_source.html | 110 + ...ssRTSim_1_1ModeOutOfIndex__coll__graph.dot | 8 + ...ssRTSim_1_1ModeOutOfIndex__coll__graph.md5 | 1 + ...1Matchers_1_1Impl_1_1Generic_1_1AllOf.html | 159 ++ ...ssRTSim_1_1RRScheduler__inherit__graph.dot | 10 + ...ssRTSim_1_1RRScheduler__inherit__graph.md5 | 1 + ..._1_1OperatorTraits_3_01IsEqualTo_01_4.html | 116 + .../structCatch_1_1IExceptionTranslator.html | 116 + ..._1_1StdString_1_1EndsWith__coll__graph.dot | 16 + ..._1_1StdString_1_1EndsWith__coll__graph.md5 | 1 + html/d9/d9c/instr_8hpp_source.html | 110 + html/d9/da4/fifosched_8hpp_source.html | 111 + ...sRTSim_1_1SparePot_1_1ChangeBudgetEvt.html | 137 + ...ssRTSim_1_1TraceIdleEvent__coll__graph.dot | 12 + ...ssRTSim_1_1TraceIdleEvent__coll__graph.md5 | 1 + .../classRTSim_1_1AbsRTTask__coll__graph.dot | 8 + .../classRTSim_1_1AbsRTTask__coll__graph.md5 | 1 + .../db1/structCatch_1_1IfFilterMatches.html | 118 + .../classCatch_1_1Internal_1_1Evaluator.html | 107 + ...classCatch_1_1NotImplementedException.html | 131 + ..._1TaskAlreadyExecuting__inherit__graph.dot | 8 + ..._1TaskAlreadyExecuting__inherit__graph.md5 | 1 + html/d9/db9/classRTSim_1_1KernAlreadySet.html | 119 + ...assRTSim_1_1SavedPower__inherit__graph.dot | 10 + ...assRTSim_1_1SavedPower__inherit__graph.md5 | 1 + .../classRTSim_1_1AbstractFeedbackModule.html | 152 ++ html/d9/ddd/classRTSim_1_1EndEvt.html | 169 ++ html/d9/de1/catch_8hpp_source.html | 206 ++ ...ssCatch_1_1NonCopyable__inherit__graph.dot | 69 + ...ssCatch_1_1NonCopyable__inherit__graph.md5 | 1 + ...m_1_1TaskAlreadyActive__inherit__graph.dot | 8 + ...m_1_1TaskAlreadyActive__inherit__graph.md5 | 1 + html/d9/df6/classRTSim_1_1DTGen.html | 183 ++ html/da/d06/classRTSim_1_1SuperCBS.html | 291 ++ .../da/d0b/classRTSim_1_1BWI__coll__graph.dot | 22 + .../da/d0b/classRTSim_1_1BWI__coll__graph.md5 | 1 + ...classRTSim_1_1InstrExc__inherit__graph.dot | 8 + ...classRTSim_1_1InstrExc__inherit__graph.md5 | 1 + html/da/d10/classCatch_1_1Section.html | 119 + ...TSim_1_1MissPercentage__inherit__graph.dot | 8 + ...TSim_1_1MissPercentage__inherit__graph.md5 | 1 + html/da/d14/classCatch_1_1Tag.html | 125 + .../d14/classRTSim_1_1CPU__inherit__graph.dot | 8 + .../d14/classRTSim_1_1CPU__inherit__graph.md5 | 1 + ...tchers_1_1Impl_1_1StdString_1_1Equals.html | 166 ++ html/da/d19/classRTSim_1_1PeriodicTimer.html | 158 ++ html/da/d24/classRTSim_1_1RandomDTGen.html | 193 ++ html/da/d27/classRTSim_1_1RTSchedExc.html | 132 + ..._01T1_00_01T2_00_01IsGreaterThan_01_4.html | 116 + ...r_3_01T1_00_01T2_00_01IsLessThan_01_4.html | 116 + html/da/d3e/classRTSim_1_1RTKernel.html | 1016 +++++++ ...sRTSim_1_1UniformCTGen__inherit__graph.dot | 14 + ...sRTSim_1_1UniformCTGen__inherit__graph.md5 | 1 + .../classRTSim_1_1MRTKernel__coll__graph.dot | 44 + .../classRTSim_1_1MRTKernel__coll__graph.md5 | 1 + html/da/d6a/AVRTask_8hpp_source.html | 111 + html/da/d6b/classRTSim_1_1FIFOScheduler.html | 361 +++ ...Sim_1_1RandomOffsetGen__inherit__graph.dot | 12 + ...Sim_1_1RandomOffsetGen__inherit__graph.md5 | 1 + ...Catch_1_1Detail_1_1IsStreamInsertable.html | 126 + html/da/d76/structCatch_1_1IReporter.html | 171 ++ .../classRTSim_1_1Server__inherit__graph.dot | 22 + .../classRTSim_1_1Server__inherit__graph.md5 | 1 + html/da/d8a/structCatch_1_1TestRunInfo.html | 123 + ...raits_3_01IsGreaterThanOrEqualTo_01_4.html | 116 + ...CBS_1_1ChangeBudgetEvt__inherit__graph.dot | 8 + ...CBS_1_1ChangeBudgetEvt__inherit__graph.md5 | 1 + ...lassRTSim_1_1EDFScheduler__coll__graph.dot | 17 + ...lassRTSim_1_1EDFScheduler__coll__graph.md5 | 1 + html/da/da7/classRTSim_1_1EDFModel.html | 237 ++ .../classRTSim_1_1MaxIATGen__coll__graph.dot | 32 + .../classRTSim_1_1MaxIATGen__coll__graph.md5 | 1 + html/da/dba/cbserver_8hpp_source.html | 108 + .../classRTSim_1_1KernelEvt__coll__graph.dot | 40 + .../classRTSim_1_1KernelEvt__coll__graph.md5 | 1 + ...sRTSim_1_1EDFScheduler__inherit__graph.dot | 10 + ...sRTSim_1_1EDFScheduler__inherit__graph.md5 | 1 + ...uperCBS_1_1SuperCBSExc__inherit__graph.dot | 8 + ...uperCBS_1_1SuperCBSExc__inherit__graph.md5 | 1 + html/da/dcb/structCatch_1_1TrueType.html | 130 + ...assRTSim_1_1TraceEndEvent__coll__graph.dot | 14 + ...assRTSim_1_1TraceEndEvent__coll__graph.md5 | 1 + html/da/dd3/classRTSim_1_1SignalEvt.html | 168 ++ ...sRTSim_1_1PeriodicTask__inherit__graph.dot | 14 + ...sRTSim_1_1PeriodicTask__inherit__graph.md5 | 1 + ...classRTSim_1_1SchedRTA__inherit__graph.dot | 10 + ...classRTSim_1_1SchedRTA__inherit__graph.md5 | 1 + ..._1SuperCBS_1_1SuperCBSExc__coll__graph.dot | 8 + ..._1SuperCBS_1_1SuperCBSExc__coll__graph.md5 | 1 + ...sRTSim_1_1RandomTaskSetFactory_1_1Exc.html | 200 ++ html/da/dff/structCatch_1_1LazyStat.html | 181 ++ html/db/d01/classRTSim_1_1WaitEvt.html | 168 ++ ...int_1_1ChangeBudgetEvt__inherit__graph.dot | 8 + ...int_1_1ChangeBudgetEvt__inherit__graph.md5 | 1 + ...RRScheduler_1_1RRModel__inherit__graph.dot | 8 + ...RRScheduler_1_1RRModel__inherit__graph.md5 | 1 + .../db/d06/structCatch_1_1ReporterConfig.html | 125 + html/db/d0a/classRTSim_1_1RMScheduler.html | 364 +++ .../classRTSim_1_1ThreEvt__coll__graph.dot | 52 + .../classRTSim_1_1ThreEvt__coll__graph.md5 | 1 + ...hedPoint_1_1SchedPointExc__coll__graph.dot | 8 + ...hedPoint_1_1SchedPointExc__coll__graph.md5 | 1 + .../classRTSim_1_1RRScheduler_1_1RRModel.html | 302 ++ ...ssRTSim_1_1NoSuchInstr__inherit__graph.dot | 8 + ...ssRTSim_1_1NoSuchInstr__inherit__graph.md5 | 1 + html/db/d38/classRTSim_1_1VirtualTrace.html | 123 + ...assRTSim_1_1SchedInstr__inherit__graph.dot | 10 + ...assRTSim_1_1SchedInstr__inherit__graph.md5 | 1 + .../classRTSim_1_1RTModel__coll__graph.dot | 13 + .../classRTSim_1_1RTModel__coll__graph.md5 | 1 + ...lassRTSim_1_1LatenessStat__coll__graph.dot | 8 + ...lassRTSim_1_1LatenessStat__coll__graph.md5 | 1 + html/db/d71/classRTSim_1_1DeschedEvt.html | 162 ++ .../d7b/classCatch_1_1BetweenGenerator.html | 134 + ...tructCatch_1_1LazyStat__inherit__graph.dot | 8 + ...tructCatch_1_1LazyStat__inherit__graph.md5 | 1 + html/db/d7f/classRTSim_1_1ServerExc.html | 128 + ...im_1_1TraceSignalEvent__inherit__graph.dot | 10 + ...im_1_1TraceSignalEvent__inherit__graph.md5 | 1 + .../d8e/classRTSim_1_1CTGen__coll__graph.dot | 28 + .../d8e/classRTSim_1_1CTGen__coll__graph.md5 | 1 + html/db/d95/classRTSim_1_1MRTKernel.html | 872 ++++++ html/db/da4/classRTSim_1_1ExecInstr.html | 501 ++++ html/db/dae/structCatch_1_1IGenerator.html | 125 + .../classRTSim_1_1DlineEquPeriodDTGen.html | 187 ++ .../classRTSim_1_1Grub__inherit__graph.dot | 16 + .../classRTSim_1_1Grub__inherit__graph.md5 | 1 + html/db/dc8/structCatch_1_1Verbosity.html | 118 + ...sRTSim_1_1LatenessStat__inherit__graph.dot | 8 + ...sRTSim_1_1LatenessStat__inherit__graph.md5 | 1 + ..._1_1FeedbackTestModule__inherit__graph.dot | 10 + ..._1_1FeedbackTestModule__inherit__graph.md5 | 1 + .../db/dcf/structCatch_1_1AssertionStats.html | 135 + .../dd3/classRTSim_1_1ArrEvt__coll__graph.dot | 44 + .../dd3/classRTSim_1_1ArrEvt__coll__graph.md5 | 1 + .../ddf/structCatch_1_1IReporterFactory.html | 119 + html/db/dee/abskernel_8hpp_source.html | 115 + ...ssRTSim_1_1EndInstrEvt__inherit__graph.dot | 8 + ...ssRTSim_1_1EndInstrEvt__inherit__graph.md5 | 1 + ...sRTSim_1_1SuspendInstr__inherit__graph.dot | 10 + ...sRTSim_1_1SuspendInstr__inherit__graph.md5 | 1 + ...TSim_1_1TraceTaskEvent__inherit__graph.dot | 33 + ...TSim_1_1TraceTaskEvent__inherit__graph.md5 | 1 + ...lassRTSim_1_1ExecInstr__inherit__graph.dot | 12 + ...lassRTSim_1_1ExecInstr__inherit__graph.md5 | 1 + ...assRTSim_1_1PIRManager__inherit__graph.dot | 10 + ...assRTSim_1_1PIRManager__inherit__graph.md5 | 1 + ...structCatch_1_1SharedImpl__coll__graph.dot | 8 + ...structCatch_1_1SharedImpl__coll__graph.md5 | 1 + ...classRTSim_1_1RRScheduler__coll__graph.dot | 17 + ...classRTSim_1_1RRScheduler__coll__graph.md5 | 1 + .../d02/classRTSim_1_1Task__coll__graph.dot | 44 + .../d02/classRTSim_1_1Task__coll__graph.md5 | 1 + ...Sim_1_1TraceDlineSetEvent__coll__graph.dot | 12 + ...Sim_1_1TraceDlineSetEvent__coll__graph.md5 | 1 + .../classRTSim_1_1FakeArrEvt__coll__graph.dot | 44 + .../classRTSim_1_1FakeArrEvt__coll__graph.md5 | 1 + .../classRTSim_1_1ThreInstr__coll__graph.dot | 49 + .../classRTSim_1_1ThreInstr__coll__graph.md5 | 1 + ...RTSim_1_1TraceSignalEvent__coll__graph.dot | 12 + ...RTSim_1_1TraceSignalEvent__coll__graph.md5 | 1 + html/dc/d11/structCatch_1_1SectionStats.html | 138 + .../classRTSim_1_1KillEvt__inherit__graph.dot | 10 + .../classRTSim_1_1KillEvt__inherit__graph.md5 | 1 + html/dc/d17/classRTSim_1_1SchedInstr.html | 428 +++ html/dc/d1c/classCatch_1_1NonCopyable.html | 113 + ...1_1EndDispatchMultiEvt__inherit__graph.dot | 8 + ...1_1EndDispatchMultiEvt__inherit__graph.md5 | 1 + ...TSim_1_1TraceNameEvent__inherit__graph.dot | 10 + ...TSim_1_1TraceNameEvent__inherit__graph.md5 | 1 + ...ssRTSim_1_1RTKernelExc__inherit__graph.dot | 8 + ...ssRTSim_1_1RTKernelExc__inherit__graph.md5 | 1 + .../dc/d2b/structCatch_1_1SourceLineInfo.html | 135 + html/dc/d2f/taskstat_8hpp_source.html | 127 + ...RTSim_1_1UniformIATGen__inherit__graph.dot | 14 + ...RTSim_1_1UniformIATGen__inherit__graph.md5 | 1 + .../d33/structCatch_1_1OutputDebugWriter.html | 116 + html/dc/d36/classRTSim_1_1ResManager.html | 353 +++ .../d3d/namespaceRTSim_1_1____task__stub.html | 104 + .../dc/d4e/classRTSim_1_1TraceSchedEvent.html | 237 ++ ...sRTSim_1_1TraceSchedEvent__coll__graph.dot | 14 + ...sRTSim_1_1TraceSchedEvent__coll__graph.md5 | 1 + ...lassRTSim_1_1MaxIATGen__inherit__graph.dot | 12 + ...lassRTSim_1_1MaxIATGen__inherit__graph.md5 | 1 + ...classCatch_1_1ExpressionResultBuilder.html | 159 ++ html/dc/d59/structCatch_1_1AutoReg.html | 123 + ...assRTSim_1_1TaskNotActive__coll__graph.dot | 8 + ...assRTSim_1_1TaskNotActive__coll__graph.md5 | 1 + ...tCatch_1_1IMutableContext__coll__graph.dot | 8 + ...tCatch_1_1IMutableContext__coll__graph.md5 | 1 + html/dc/d5e/classRTSim_1_1WaitInstr.html | 440 +++ .../classRTSim_1_1RandomTaskSetFactory.html | 361 +++ .../classRTSim_1_1MinIATGen__coll__graph.dot | 32 + .../classRTSim_1_1MinIATGen__coll__graph.md5 | 1 + ...00_01T2_00_01IsLessThanOrEqualTo_01_4.html | 116 + html/dc/d72/classCatch_1_1Config.html | 202 ++ ...sCatch_1_1TagExtracter__inherit__graph.dot | 8 + ...sCatch_1_1TagExtracter__inherit__graph.md5 | 1 + ...tructCatch_1_1SectionInfo__coll__graph.dot | 8 + ...tructCatch_1_1SectionInfo__coll__graph.md5 | 1 + ...tCatch_1_1Matchers_1_1Impl_1_1Matcher.html | 155 ++ html/dc/d89/classCatch_1_1MethodTestCase.html | 145 + ...1_1TagExpressionParser__inherit__graph.dot | 8 + ...1_1TagExpressionParser__inherit__graph.md5 | 1 + .../classRTSim_1_1AVRTask__inherit__graph.dot | 14 + .../classRTSim_1_1AVRTask__inherit__graph.md5 | 1 + .../classRTSim_1_1PIRManager__coll__graph.dot | 22 + .../classRTSim_1_1PIRManager__coll__graph.md5 | 1 + html/dc/dbb/classRTSim_1_1Grub.html | 476 ++++ ...ctCatch_1_1MessageBuilder__coll__graph.dot | 10 + ...ctCatch_1_1MessageBuilder__coll__graph.md5 | 1 + .../dc9/structCatch_1_1IMutableContext.html | 150 + ...structCatch_1_1CumulativeReporterBase.html | 241 ++ html/dc/de3/edfsched_8hpp_source.html | 111 + html/dc/de5/classRTSim_1_1LatenessStat.html | 141 + ...OperatorTraits_3_01IsGreaterThan_01_4.html | 116 + .../classRTSim_1_1Task__inherit__graph.dot | 16 + .../classRTSim_1_1Task__inherit__graph.md5 | 1 + ...ctCatch_1_1Internal_1_1OperatorTraits.html | 116 + html/dc/df6/classCatch_1_1Ptr.html | 149 + .../classRTSim_1_1DeadEvt__inherit__graph.dot | 10 + .../classRTSim_1_1DeadEvt__inherit__graph.md5 | 1 + html/dd/d0d/classMySim.html | 168 ++ ...TSim_1_1uniformCPUFactory__coll__graph.dot | 8 + ...TSim_1_1uniformCPUFactory__coll__graph.md5 | 1 + ...1StreamingReporterBase__inherit__graph.dot | 14 + ...1StreamingReporterBase__inherit__graph.md5 | 1 + ...lassRTSim_1_1EmptyTask__inherit__graph.dot | 8 + ...lassRTSim_1_1EmptyTask__inherit__graph.md5 | 1 + html/dd/d1b/classRTSim_1_1Instr.html | 428 +++ .../d1f/classRTSim_1_1TaskNotExecuting.html | 128 + ...lassRTSim_1_1KernelEvt__inherit__graph.dot | 14 + ...lassRTSim_1_1KernelEvt__inherit__graph.md5 | 1 + ...Pot_1_1ChangeBudgetEvt__inherit__graph.dot | 8 + ...Pot_1_1ChangeBudgetEvt__inherit__graph.md5 | 1 + html/dd/d2d/classSystem.html | 181 ++ ...parePot_1_1SparePotExc__inherit__graph.dot | 8 + ...parePot_1_1SparePotExc__inherit__graph.md5 | 1 + html/dd/d34/classRTSim_1_1SchedIEvt.html | 168 ++ ...classRTSim_1_1FPScheduler__coll__graph.dot | 17 + ...classRTSim_1_1FPScheduler__coll__graph.md5 | 1 + ...classRTSim_1_1CBServer__inherit__graph.dot | 16 + ...classRTSim_1_1CBServer__inherit__graph.md5 | 1 + html/dd/d3e/classMySim__coll__graph.dot | 61 + html/dd/d3e/classMySim__coll__graph.md5 | 1 + ...sRTSim_1_1RandomOffsetGen__coll__graph.dot | 31 + ...sRTSim_1_1RandomOffsetGen__coll__graph.md5 | 1 + .../classRTSim_1_1AVRTask__coll__graph.dot | 46 + .../classRTSim_1_1AVRTask__coll__graph.md5 | 1 + ...classCatch_1_1TestCase__inherit__graph.dot | 8 + ...classCatch_1_1TestCase__inherit__graph.md5 | 1 + ...cheduler_1_1RRSchedExc__inherit__graph.dot | 8 + ...cheduler_1_1RRSchedExc__inherit__graph.md5 | 1 + .../classRTSim_1_1Scheduler__coll__graph.dot | 15 + .../classRTSim_1_1Scheduler__coll__graph.md5 | 1 + ...assRTSim_1_1DeschedEvt__inherit__graph.dot | 10 + ...assRTSim_1_1DeschedEvt__inherit__graph.md5 | 1 + html/dd/d60/classRTSim_1_1KernelEvt.html | 141 + ...perCBS_1_1ChangeBudgetEvt__coll__graph.dot | 8 + ...perCBS_1_1ChangeBudgetEvt__coll__graph.md5 | 1 + html/dd/d72/classRTSim_1_1DlineSetEvt.html | 167 ++ html/dd/d73/classRTSim_1_1MaxCTGen.html | 237 ++ ...RTSim_1_1TraceEndEvent__inherit__graph.dot | 12 + ...RTSim_1_1TraceEndEvent__inherit__graph.md5 | 1 + ...tch_1_1CumulativeReporterBase_1_1Node.html | 156 ++ .../d7a/classRTSim_1_1FinishingTimeStat.html | 141 + .../classRTSim_1_1RTModel_1_1RTModelCmp.html | 120 + .../classRTSim_1_1MaxCTGen__coll__graph.dot | 32 + .../classRTSim_1_1MaxCTGen__coll__graph.md5 | 1 + html/dd/d94/supercbs_8hpp_source.html | 108 + .../classRTSim_1_1OffsetGen__coll__graph.dot | 28 + .../classRTSim_1_1OffsetGen__coll__graph.md5 | 1 + .../classRTSim_1_1WaitInstr__coll__graph.dot | 49 + .../classRTSim_1_1WaitInstr__coll__graph.md5 | 1 + html/dd/da8/structCatch_1_1ResultAction.html | 119 + html/dd/da9/classRTSim_1_1PIRManager.html | 292 ++ html/dd/da9/classRTSim_1_1RTKernelExc.html | 132 + ...assRTSim_1_1PeriodicTimer__coll__graph.dot | 10 + ...assRTSim_1_1PeriodicTimer__coll__graph.md5 | 1 + ..._1RandomTaskSetFactory__inherit__graph.dot | 8 + ..._1RandomTaskSetFactory__inherit__graph.md5 | 1 + ...ativeReporterBase_1_1Node__coll__graph.dot | 12 + ...ativeReporterBase_1_1Node__coll__graph.md5 | 1 + ...TSim_1_1ModeOutOfIndex__inherit__graph.dot | 8 + ...TSim_1_1ModeOutOfIndex__inherit__graph.md5 | 1 + html/dd/dc7/structCatch_1_1ConfigData.html | 161 ++ ...ctRTSim_1_1SparePot_1_1server__struct.html | 128 + ...ssRTSim_1_1TaskStatExc__inherit__graph.dot | 8 + ...ssRTSim_1_1TaskStatExc__inherit__graph.md5 | 1 + ...ssRTSim_1_1TraceTaskEvent__coll__graph.dot | 10 + ...ssRTSim_1_1TraceTaskEvent__coll__graph.md5 | 1 + ...ssRTSim_1_1RandomDTGen__inherit__graph.dot | 12 + ...ssRTSim_1_1RandomDTGen__inherit__graph.md5 | 1 + .../namespaceRTSim_1_1____instr__stub.html | 104 + .../classRTSim_1_1IATGen__inherit__graph.dot | 16 + .../classRTSim_1_1IATGen__inherit__graph.md5 | 1 + ...tructCatch_1_1MessageInfo__coll__graph.dot | 8 + ...tructCatch_1_1MessageInfo__coll__graph.md5 | 1 + .../df2/classCatch_1_1Config__coll__graph.dot | 14 + .../df2/classCatch_1_1Config__coll__graph.md5 | 1 + ...lassRTSim_1_1JavaTrace__inherit__graph.dot | 8 + ...lassRTSim_1_1JavaTrace__inherit__graph.md5 | 1 + ...classRTSim_1_1EndInstrEvt__coll__graph.dot | 8 + ...classRTSim_1_1EndInstrEvt__coll__graph.md5 | 1 + .../structCatch_1_1StreamingReporterBase.html | 198 ++ ...classRTSim_1_1SparePot__inherit__graph.dot | 10 + ...classRTSim_1_1SparePot__inherit__graph.md5 | 1 + .../classRTSim_1_1DeadEvt__coll__graph.dot | 44 + .../classRTSim_1_1DeadEvt__coll__graph.md5 | 1 + ...Sim_1_1TraceSchedEvent__inherit__graph.dot | 12 + ...Sim_1_1TraceSchedEvent__inherit__graph.md5 | 1 + ...im_1_1TraceDlinePostEvent__coll__graph.dot | 12 + ...im_1_1TraceDlinePostEvent__coll__graph.md5 | 1 + .../classRTSim_1_1ResManager__coll__graph.dot | 20 + .../classRTSim_1_1ResManager__coll__graph.md5 | 1 + html/de/d28/resmanager_8hpp_source.html | 109 + ...assRTSim_1_1RTSchedExc__inherit__graph.dot | 9 + ...assRTSim_1_1RTSchedExc__inherit__graph.md5 | 1 + .../classRTSim_1_1WaitEvt__inherit__graph.dot | 10 + .../classRTSim_1_1WaitEvt__inherit__graph.md5 | 1 + .../classRTSim_1_1SignalEvt__coll__graph.dot | 52 + .../classRTSim_1_1SignalEvt__coll__graph.md5 | 1 + ...tchers_1_1Impl_1_1Matcher__coll__graph.dot | 12 + ...tchers_1_1Impl_1_1Matcher__coll__graph.md5 | 1 + .../classRTSim_1_1TaskEvt__inherit__graph.dot | 33 + .../classRTSim_1_1TaskEvt__inherit__graph.md5 | 1 + .../classRTSim_1_1TaskModel__coll__graph.dot | 10 + .../classRTSim_1_1TaskModel__coll__graph.md5 | 1 + ...vector_3_01T_00_01Allocator_01_4_01_4.html | 116 + html/de/d5e/sporadicserver_8hpp_source.html | 108 + html/de/d5f/classRTSim_1_1AbsTask.html | 303 ++ html/de/d5f/piresman_8hpp_source.html | 107 + html/de/d62/structCatch_1_1TestCaseInfo.html | 156 ++ ...ssRTSim_1_1MissPercentage__coll__graph.dot | 8 + ...ssRTSim_1_1MissPercentage__coll__graph.md5 | 1 + ...assRTSim_1_1TraceCPUEvent__coll__graph.dot | 12 + ...assRTSim_1_1TraceCPUEvent__coll__graph.md5 | 1 + .../classRTSim_1_1TraceDlinePostEvent.html | 323 +++ html/de/d7f/classRTSim_1_1AbsKernel.html | 413 +++ ...RTSim_1_1CapacityTimer__inherit__graph.dot | 8 + ...RTSim_1_1CapacityTimer__inherit__graph.md5 | 1 + ...uctCatch_1_1TestCaseStats__coll__graph.dot | 14 + ...uctCatch_1_1TestCaseStats__coll__graph.md5 | 1 + html/de/d8c/structCatch_1_1ITestCase.html | 135 + ...Sim_1_1FeedbackTestModule__coll__graph.dot | 46 + ...Sim_1_1FeedbackTestModule__coll__graph.md5 | 1 + ...lassRTSim_1_1MRTKernel__inherit__graph.dot | 12 + ...lassRTSim_1_1MRTKernel__inherit__graph.md5 | 1 + html/de/d98/classRTSim_1_1CPU.html | 254 ++ ...classRTSim_1_1MaxCTGen__inherit__graph.dot | 12 + ...classRTSim_1_1MaxCTGen__inherit__graph.md5 | 1 + ...tructCatch_1_1StringMaker__coll__graph.dot | 8 + ...tructCatch_1_1StringMaker__coll__graph.md5 | 1 + ...1OperatorTraits_3_01IsNotEqualTo_01_4.html | 116 + html/de/db0/structCatch_1_1Counts.html | 132 + .../classRTSim_1_1JavaTrace__coll__graph.dot | 8 + .../classRTSim_1_1JavaTrace__coll__graph.md5 | 1 + html/de/db6/classRTSim_1_1TraceIdleEvent.html | 226 ++ ...ssRTSim_1_1RMScheduler__inherit__graph.dot | 12 + ...ssRTSim_1_1RMScheduler__inherit__graph.md5 | 1 + ...dPoint_1_1ChangeBudgetEvt__coll__graph.dot | 8 + ...dPoint_1_1ChangeBudgetEvt__coll__graph.md5 | 1 + html/de/dc9/classRTSim_1_1GrubExc.html | 132 + html/de/dc9/traceevent_8hpp_source.html | 118 + html/de/dcf/structCatch_1_1WarnAbout.html | 117 + ...rs_1_1Impl_1_1MatcherImpl__coll__graph.dot | 14 + ...rs_1_1Impl_1_1MatcherImpl__coll__graph.md5 | 1 + ...ssRTSim_1_1PreemptionStat__coll__graph.dot | 8 + ...ssRTSim_1_1PreemptionStat__coll__graph.md5 | 1 + ...3_01T1_00_01T2_00_01IsNotEqualTo_01_4.html | 116 + ..._1_1TracePowerConsumption__coll__graph.dot | 14 + ..._1_1TracePowerConsumption__coll__graph.md5 | 1 + ...classRTSim_1_1SuperCBS_1_1SuperCBSExc.html | 128 + ...1_1DlineEquPeriodDTGen__inherit__graph.dot | 12 + ...1_1DlineEquPeriodDTGen__inherit__graph.md5 | 1 + html/df/d05/timer_8hpp_source.html | 104 + html/df/d0a/server_8hpp_source.html | 123 + ...AbstractFeedbackModule__inherit__graph.dot | 12 + ...AbstractFeedbackModule__inherit__graph.md5 | 1 + ...lassRTSim_1_1SchedIEvt__inherit__graph.dot | 10 + ...lassRTSim_1_1SchedIEvt__inherit__graph.md5 | 1 + html/df/d1d/classCatch_1_1SafeBool.html | 123 + ...tCatch_1_1TestCaseInfo__inherit__graph.dot | 8 + ...tCatch_1_1TestCaseInfo__inherit__graph.md5 | 1 + ...RTSim_1_1TaskNotActive__inherit__graph.dot | 8 + ...RTSim_1_1TaskNotActive__inherit__graph.md5 | 1 + .../d33/classRTSim_1_1Grub__coll__graph.dot | 30 + .../d33/classRTSim_1_1Grub__coll__graph.md5 | 1 + .../classCatch_1_1ExpressionDecomposer.html | 120 + html/df/d39/classRTSim_1_1EndDispatchEvt.html | 149 + .../classRTSim_1_1SavedPower__coll__graph.dot | 19 + .../classRTSim_1_1SavedPower__coll__graph.md5 | 1 + .../classRTSim_1_1RTKernel__coll__graph.dot | 40 + .../classRTSim_1_1RTKernel__coll__graph.md5 | 1 + html/df/d47/classRTSim_1_1FPScheduler.html | 427 +++ ...TSim_1_1FCFSResManager__inherit__graph.dot | 10 + ...TSim_1_1FCFSResManager__inherit__graph.md5 | 1 + html/df/d4f/reginstr_8hpp_source.html | 102 + html/df/d54/sim__structs_8hpp_source.html | 119 + ...RTSim_1_1PeriodicTimer__inherit__graph.dot | 12 + ...RTSim_1_1PeriodicTimer__inherit__graph.md5 | 1 + html/df/d6a/supervisor_8hpp_source.html | 105 + html/df/d72/load_8hpp_source.html | 131 + ...structRTSim_1_1SchedRTA_1_1ServerInfo.html | 138 + html/df/d97/interrupt_8hpp_source.html | 113 + html/df/da6/classRTSim_1_1AbstractGen.html | 154 ++ html/df/db0/suspend__instr_8hpp_source.html | 113 + .../db4/classRTSim_1_1uniformCPUFactory.html | 139 + ...m_1_1RandomTaskSetFactory__coll__graph.dot | 28 + ...m_1_1RandomTaskSetFactory__coll__graph.md5 | 1 + html/df/db8/kernel_8hpp_source.html | 124 + html/df/dbe/cpu_8hpp_source.html | 114 + ...lassRTSim_1_1SuspendInstr__coll__graph.dot | 49 + ...lassRTSim_1_1SuspendInstr__coll__graph.md5 | 1 + html/df/ddb/structCatch_1_1TestCaseStats.html | 141 + html/df/ddf/structCatch_1_1IConfig.html | 156 ++ html/df/ded/classRTSim_1_1PollingServer.html | 454 +++ html/df/dfb/schedinstr_8hpp_source.html | 115 + .../dir_13e138d54eb8818da29c3992edef070a.html | 105 + .../dir_2c1ec4cfaf5ed43ec260b4f91f837847.html | 105 + .../dir_3c5a7878238957e7a9a8834f0b838f8b.html | 105 + .../dir_3c5cc845447c19ce6ee25ef55a49cd4c.html | 105 + .../dir_3f9cfe9044a0c61e52ec878e2326b5b3.html | 105 + .../dir_4fef79e7177ba769987a8da36c892c5f.html | 105 + .../dir_55415680715be69f92249950f105c664.html | 105 + .../dir_63772b626f2709090f0bdca0f40827b4.html | 108 + .../dir_68267d1309a1af8e8297ef4c3efbcdba.html | 105 + .../dir_894d12cf7c955c04db6300346317721c.html | 105 + .../dir_a41afb44cd77021f04ef0298981be91e.html | 105 + .../dir_a573004c1aa1ac4f8bc48460229ea7de.html | 105 + .../dir_d28a4824dc47e487b107a5db32ef43c4.html | 105 + .../dir_d5f87438f5d8e96cf3117079ff5b9178.html | 105 + html/doc.png | Bin 0 -> 746 bytes html/doxygen.css | 1475 ++++++++++ html/doxygen.png | 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.../d0/d1a/classRTSim_1_1CPU__coll__graph.dot | 8 + .../d0/d1a/classRTSim_1_1CPU__coll__graph.md5 | 1 + .../classRTSim_1_1TaskEvt__coll__graph.dot | 44 + .../classRTSim_1_1TaskEvt__coll__graph.md5 | 1 + latex/d0/d1b/classCatch_1_1StreamBufImpl.tex | 15 + ...tch_1_1ValuesGenerator__inherit__graph.dot | 8 + ...tch_1_1ValuesGenerator__inherit__graph.md5 | 1 + latex/d0/d27/classRTSim_1_1Interrupt.tex | 105 + latex/d0/d2f/classRTSim_1_1TraceTaskEvent.tex | 87 + latex/d0/d38/classRTSim_1_1DispatchEvt.tex | 25 + ...assRTSim_1_1ResManager__inherit__graph.dot | 14 + ...assRTSim_1_1ResManager__inherit__graph.md5 | 1 + latex/d0/d39/classRTSim_1_1AbsResManager.tex | 70 + .../classRTSim_1_1ConstCTGen__coll__graph.dot | 30 + .../classRTSim_1_1ConstCTGen__coll__graph.md5 | 1 + ...TSim_1_1KernAlreadySet__inherit__graph.dot | 8 + ...TSim_1_1KernAlreadySet__inherit__graph.md5 | 1 + latex/d0/d43/classRTSim_1_1EDFScheduler.tex | 72 + ...1_1TraceDlinePostEvent__inherit__graph.dot | 10 + ...1_1TraceDlinePostEvent__inherit__graph.md5 | 1 + latex/d0/d5b/classRTSim_1_1SchedEvt.tex | 31 + ...1_1Impl_1_1MatcherImpl__inherit__graph.dot | 14 + ...1_1Impl_1_1MatcherImpl__inherit__graph.md5 | 1 + ...ssRTSim_1_1SporadicServer__coll__graph.dot | 30 + ...ssRTSim_1_1SporadicServer__coll__graph.md5 | 1 + latex/d0/d76/classRTSim_1_1AVRTask.tex | 124 + ...ssRTSim_1_1SuperCBS_1_1ChangeBudgetEvt.tex | 30 + ...sRTSim_1_1UtilizationStat__coll__graph.dot | 8 + ...sRTSim_1_1UtilizationStat__coll__graph.md5 | 1 + latex/d0/d82/structCatch_1_1ShowDurations.tex | 16 + ...classRTSim_1_1SuperCBS__inherit__graph.dot | 10 + ...classRTSim_1_1SuperCBS__inherit__graph.md5 | 1 + ...assRTSim_1_1TraceEvent__inherit__graph.dot | 33 + ...assRTSim_1_1TraceEvent__inherit__graph.md5 | 1 + .../classRTSim_1_1SuperCBS__coll__graph.dot | 10 + .../classRTSim_1_1SuperCBS__coll__graph.md5 | 1 + latex/d0/d94/classRTSim_1_1TraceWaitEvent.tex | 73 + latex/d0/d95/classRTSim_1_1SporadicDTGen.tex | 50 + latex/d0/d97/structCatch_1_1FalseType.tex | 25 + latex/d0/da3/structStats.tex | 32 + ...ssRTSim_1_1TraceNameEvent__coll__graph.dot | 12 + ...ssRTSim_1_1TraceNameEvent__coll__graph.md5 | 1 + ...RTSim_1_1SporadicDTGen__inherit__graph.dot | 12 + ...RTSim_1_1SporadicDTGen__inherit__graph.md5 | 1 + ...structCatch_1_1IConfig__inherit__graph.dot | 14 + ...structCatch_1_1IConfig__inherit__graph.md5 | 1 + ...chers_1_1Impl_1_1StdString_1_1EndsWith.tex | 37 + ...assRTSim_1_1ConstCTGen__inherit__graph.dot | 10 + ...assRTSim_1_1ConstCTGen__inherit__graph.md5 | 1 + latex/d0/de3/classRTSim_1_1SchedRTA.tex | 138 + ...Catch_1_1StreamBufBase__inherit__graph.dot | 10 + ...Catch_1_1StreamBufBase__inherit__graph.md5 | 1 + ...RTSim_1_1TardinessStat__inherit__graph.dot | 8 + ...RTSim_1_1TardinessStat__inherit__graph.md5 | 1 + ...1_1FPScheduler_1_1FPModel__coll__graph.dot | 12 + ...1_1FPScheduler_1_1FPModel__coll__graph.md5 | 1 + ...lassRTSim_1_1OffsetGen__inherit__graph.dot | 12 + ...lassRTSim_1_1OffsetGen__inherit__graph.md5 | 1 + ...Catch_1_1BetweenGenerator__coll__graph.dot | 8 + ...Catch_1_1BetweenGenerator__coll__graph.md5 | 1 + ...assRTSim_1_1SchedPoint__inherit__graph.dot | 10 + ...assRTSim_1_1SchedPoint__inherit__graph.md5 | 1 + ...classRTSim_1_1Resource__inherit__graph.dot | 8 + ...classRTSim_1_1Resource__inherit__graph.md5 | 1 + .../d1/d09/classCatch_1_1AssertionResult.tex | 62 + .../structCatch_1_1IShared__coll__graph.dot | 8 + .../structCatch_1_1IShared__coll__graph.md5 | 1 + .../classCatch_1_1Config__inherit__graph.dot | 14 + .../classCatch_1_1Config__inherit__graph.md5 | 1 + latex/d1/d1d/classRTSim_1_1ArrEvt.tex | 31 + .../d25/classRTSim_1_1DTGen__coll__graph.dot | 28 + .../d25/classRTSim_1_1DTGen__coll__graph.md5 | 1 + latex/d1/d27/classCatch_1_1TagParser.tex | 29 + latex/d1/d28/classRTSim_1_1InstrExc.tex | 28 + .../classRTSim_1_1ThreEvt__inherit__graph.dot | 10 + .../classRTSim_1_1ThreEvt__inherit__graph.md5 | 1 + ...ssRTSim_1_1FPScheduler__inherit__graph.dot | 12 + ...ssRTSim_1_1FPScheduler__inherit__graph.md5 | 1 + .../d43/classRTSim_1_1FeedbackTestModule.tex | 45 + .../d47/structCatch_1_1IGeneratorsForTest.tex | 16 + latex/d1/d4d/classRTSim_1_1TextTrace.tex | 38 + ...ssRTSim_1_1GrubSupervisor__coll__graph.dot | 8 + ...ssRTSim_1_1GrubSupervisor__coll__graph.md5 | 1 + ...1_1FeedbackModuleARSim__inherit__graph.dot | 10 + ...1_1FeedbackModuleARSim__inherit__graph.md5 | 1 + ...RTSim_1_1PollingServer__inherit__graph.dot | 16 + ...RTSim_1_1PollingServer__inherit__graph.md5 | 1 + .../d1/d55/structCatch_1_1TestGroupStats.tex | 32 + latex/d1/d64/classRTSim_1_1MissPercentage.tex | 34 + .../classRTSim_1_1BeginDispatchMultiEvt.tex | 35 + ...tch_1_1Matchers_1_1Impl_1_1MatcherImpl.tex | 22 + ...lassRTSim_1_1UniformCTGen__coll__graph.dot | 30 + ...lassRTSim_1_1UniformCTGen__coll__graph.md5 | 1 + ...m_1_1TaskAlreadyExecuting__coll__graph.dot | 8 + ...m_1_1TaskAlreadyExecuting__coll__graph.md5 | 1 + latex/d1/d8c/classRTSim_1_1ConstIATGen.tex | 56 + .../d8e/classRTSim_1_1EndDispatchMultiEvt.tex | 41 + .../classRTSim_1_1KillEvt__coll__graph.dot | 44 + .../classRTSim_1_1KillEvt__coll__graph.md5 | 1 + ...ssCatch_1_1MethodTestCase__coll__graph.dot | 14 + ...ssCatch_1_1MethodTestCase__coll__graph.md5 | 1 + ...veReporterBase_1_1Node__inherit__graph.dot | 12 + ...veReporterBase_1_1Node__inherit__graph.md5 | 1 + ...ssRTSim_1_1DlineSetEvt__inherit__graph.dot | 10 + ...ssRTSim_1_1DlineSetEvt__inherit__graph.md5 | 1 + latex/d1/db1/classRTSim_1_1IATGen.tex | 71 + ...classRTSim_1_1TaskStatExc__coll__graph.dot | 8 + ...classRTSim_1_1TaskStatExc__coll__graph.md5 | 1 + ...tdString_1_1StartsWith__inherit__graph.dot | 16 + ...tdString_1_1StartsWith__inherit__graph.md5 | 1 + .../classRTSim_1_1GrubExc__coll__graph.dot | 10 + .../classRTSim_1_1GrubExc__coll__graph.md5 | 1 + latex/d1/dc1/structCatch_1_1IShared.tex | 24 + ...lassRTSim_1_1MissCount__inherit__graph.dot | 8 + ...lassRTSim_1_1MissCount__inherit__graph.md5 | 1 + .../classRTSim_1_1RTSchedExc__coll__graph.dot | 9 + .../classRTSim_1_1RTSchedExc__coll__graph.md5 | 1 + ...lassRTSim_1_1SignalEvt__inherit__graph.dot | 10 + ...lassRTSim_1_1SignalEvt__inherit__graph.md5 | 1 + ...assRTSim_1_1TardinessStat__coll__graph.dot | 8 + ...assRTSim_1_1TardinessStat__coll__graph.md5 | 1 + ...ctCatch_1_1StringMaker__inherit__graph.dot | 8 + ...ctCatch_1_1StringMaker__inherit__graph.md5 | 1 + .../structRTSim_1_1SchedPoint_1_1points.tex | 13 + ...ssRTSim_1_1SchedPoint_1_1SchedPointExc.tex | 21 + latex/d1/dfa/classRTSim_1_1MinIATGen.tex | 58 + .../classRTSim_1_1RTModel__inherit__graph.dot | 8 + .../classRTSim_1_1RTModel__inherit__graph.md5 | 1 + latex/d2/d01/structCatch_1_1Totals.tex | 32 + .../classRTSim_1_1InstrExc__coll__graph.dot | 8 + .../classRTSim_1_1InstrExc__coll__graph.md5 | 1 + ...classRTSim_1_1RMScheduler__coll__graph.dot | 19 + ...classRTSim_1_1RMScheduler__coll__graph.md5 | 1 + ...im_1_1TaskNotExecuting__inherit__graph.dot | 8 + ...im_1_1TaskNotExecuting__inherit__graph.md5 | 1 + latex/d2/d11/structCatch_1_1IRegistryHub.tex | 19 + latex/d2/d1b/classRTSim_1_1UniformCTGen.tex | 67 + latex/d2/d2a/classRTSim_1_1FixedInstr.tex | 45 + ...atch_1_1MethodTestCase__inherit__graph.dot | 14 + ...atch_1_1MethodTestCase__inherit__graph.md5 | 1 + ...assRTSim_1_1FixedInstr__inherit__graph.dot | 12 + ...assRTSim_1_1FixedInstr__inherit__graph.md5 | 1 + .../structCatch_1_1Totals__coll__graph.dot | 8 + .../structCatch_1_1Totals__coll__graph.md5 | 1 + .../d2/d40/classCatch_1_1ValuesGenerator.tex | 27 + ...lassRTSim_1_1PeriodicTask__coll__graph.dot | 46 + ...lassRTSim_1_1PeriodicTask__coll__graph.md5 | 1 + ...TSim_1_1PreemptionStat__inherit__graph.dot | 8 + ...TSim_1_1PreemptionStat__inherit__graph.md5 | 1 + ...ssRTSim_1_1EndDispatchEvt__coll__graph.dot | 40 + ...ssRTSim_1_1EndDispatchEvt__coll__graph.md5 | 1 + latex/d2/d54/structCatch_1_1pluralise.tex | 28 + .../classRTSim_1_1AbsTask__inherit__graph.dot | 25 + .../classRTSim_1_1AbsTask__inherit__graph.md5 | 1 + latex/d2/d56/group__tasks.tex | 119 + ...RTSim_1_1ConsumedPower__inherit__graph.dot | 10 + ...RTSim_1_1ConsumedPower__inherit__graph.md5 | 1 + .../structCatch_1_1IMutableRegistryHub.tex | 19 + .../classRTSim_1_1TaskAlreadyExecuting.tex | 15 + ...classRTSim_1_1RTKernelExc__coll__graph.dot | 8 + ...classRTSim_1_1RTKernelExc__coll__graph.md5 | 1 + latex/d2/d70/classRTSim_1_1BWI.tex | 46 + latex/d2/d71/structCatch_1_1AssertionInfo.tex | 32 + latex/d2/d7c/classCatch_1_1TagExtracter.tex | 25 + .../d7e/classRTSim_1_1BWI__inherit__graph.dot | 10 + .../d7e/classRTSim_1_1BWI__inherit__graph.md5 | 1 + .../d2/d7e/structCatch_1_1MessageBuilder.tex | 29 + latex/d2/d7f/classRTSim_1_1JSONTrace.tex | 47 + ...sCatch_1_1AssertionResult__coll__graph.dot | 12 + ...sCatch_1_1AssertionResult__coll__graph.md5 | 1 + ...assRTSim_1_1TraceArrEvent__coll__graph.dot | 12 + ...assRTSim_1_1TraceArrEvent__coll__graph.md5 | 1 + latex/d2/d95/classRTSim_1_1TaskEvt.tex | 42 + .../d2/da3/classRTSim_1_1UtilizationStat.tex | 37 + .../d2/da4/classCatch_1_1Detail_1_1Approx.tex | 49 + ...classRTSim_1_1MinCTGen__inherit__graph.dot | 12 + ...classRTSim_1_1MinCTGen__inherit__graph.md5 | 1 + ...assRTSim_1_1ConsumedPower__coll__graph.dot | 17 + ...assRTSim_1_1ConsumedPower__coll__graph.md5 | 1 + ...ructCatch_1_1Detail_1_1StringMakerBase.tex | 13 + ...1Impl_1_1Generic_1_1AllOf__coll__graph.dot | 16 + ...1Impl_1_1Generic_1_1AllOf__coll__graph.md5 | 1 + latex/d2/db7/classRTSim_1_1ModeOutOfIndex.tex | 21 + .../db9/classRTSim_1_1TaskAlreadyActive.tex | 15 + latex/d2/dc0/structCatch_1_1StringMaker.tex | 16 + .../dc5/structCatch_1_1IReporterRegistry.tex | 22 + latex/d2/dc7/namespaceRTSim.tex | 437 +++ .../classRTSim_1_1TracePowerConsumption.tex | 39 + latex/d2/de1/classRTSim_1_1SavedPower.tex | 35 + latex/d2/de6/classCatch_1_1ExpressionLhs.tex | 58 + ...1Impl_1_1Generic_1_1AnyOf__coll__graph.dot | 16 + ...1Impl_1_1Generic_1_1AnyOf__coll__graph.md5 | 1 + latex/d2/df3/classRTSim_1_1CBServer.tex | 156 ++ latex/d2/df9/classRTSim_1_1TraceEvent.tex | 155 ++ latex/d2/dfc/classRTSim_1_1ThreInstr.tex | 175 ++ ...lassRTSim_1_1Interrupt__inherit__graph.dot | 8 + ...lassRTSim_1_1Interrupt__inherit__graph.md5 | 1 + ...tructCatch_1_1IContext__inherit__graph.dot | 8 + ...tructCatch_1_1IContext__inherit__graph.md5 | 1 + latex/d3/d04/classRTSim_1_1AbsRTTask.tex | 67 + ..._1_1StreamingReporterBase__coll__graph.dot | 29 + ..._1_1StreamingReporterBase__coll__graph.md5 | 1 + ...assRTSim_1_1PollingServer__coll__graph.dot | 30 + ...assRTSim_1_1PollingServer__coll__graph.md5 | 1 + .../structCatch_1_1IConfig__coll__graph.dot | 10 + .../structCatch_1_1IConfig__coll__graph.md5 | 1 + ..._1_1TraceDlineSetEvent__inherit__graph.dot | 10 + ..._1_1TraceDlineSetEvent__inherit__graph.md5 | 1 + .../classRTSim_1_1EndEvt__inherit__graph.dot | 10 + .../classRTSim_1_1EndEvt__inherit__graph.md5 | 1 + .../classRTSim_1_1FixedInstr__coll__graph.dot | 54 + .../classRTSim_1_1FixedInstr__coll__graph.md5 | 1 + latex/d3/d2b/classRTSim_1_1EndInstrEvt.tex | 35 + .../classRTSim_1_1SparePot_1_1SparePotExc.tex | 21 + ..._1GlobalPreemptionStat__inherit__graph.dot | 8 + ..._1GlobalPreemptionStat__inherit__graph.md5 | 1 + ...tch_1_1IStreamingReporter__coll__graph.dot | 10 + ...tch_1_1IStreamingReporter__coll__graph.md5 | 1 + ...m_1_1GlobalPreemptionStat__coll__graph.dot | 8 + ...m_1_1GlobalPreemptionStat__coll__graph.md5 | 1 + ...TSim_1_1GrubSupervisor__inherit__graph.dot | 8 + ...TSim_1_1GrubSupervisor__inherit__graph.md5 | 1 + ...lassCatch_1_1TagParser__inherit__graph.dot | 10 + ...lassCatch_1_1TagParser__inherit__graph.md5 | 1 + latex/d3/d66/classRTSim_1_1UniformIATGen.tex | 76 + latex/d3/d67/classRTSim_1_1FakeArrEvt.tex | 31 + .../classRTSim_1_1ExecInstr__coll__graph.dot | 52 + .../classRTSim_1_1ExecInstr__coll__graph.md5 | 1 + .../d73/classRTSim_1_1WrongParameterSize.tex | 21 + ..._01T2_00_01IsGreaterThanOrEqualTo_01_4.tex | 13 + .../classRTSim_1_1EmptyTask__coll__graph.dot | 8 + .../classRTSim_1_1EmptyTask__coll__graph.md5 | 1 + latex/d3/d85/classRTSim_1_1EmptyTask.tex | 15 + ...RandomRTTaskSetFactory__inherit__graph.dot | 8 + ...RandomRTTaskSetFactory__inherit__graph.md5 | 1 + latex/d3/d94/classRTSim_1_1TaskNotActive.tex | 21 + latex/d3/d9c/classRTSim_1_1Desc.tex | 25 + .../db5/classRTSim_1_1Server__coll__graph.dot | 28 + .../db5/classRTSim_1_1Server__coll__graph.md5 | 1 + .../classRTSim_1_1ServerExc__coll__graph.dot | 8 + .../classRTSim_1_1ServerExc__coll__graph.md5 | 1 + ...Point_1_1SchedPointExc__inherit__graph.dot | 8 + ...Point_1_1SchedPointExc__inherit__graph.md5 | 1 + latex/d3/dbc/classRTSim_1_1TaskModel.tex | 163 ++ latex/d3/dbd/classRTSim_1_1ConsumedPower.tex | 43 + ...classRTSim_1_1AbstractGen__coll__graph.dot | 30 + ...classRTSim_1_1AbstractGen__coll__graph.md5 | 1 + .../classRTSim_1_1GlobalPreemptionStat.tex | 40 + .../ddf/structCatch_1_1Detail_1_1BorgType.tex | 13 + latex/d3/deb/classRTSim_1_1NoSuchInstr.tex | 15 + latex/d3/df1/classRTSim_1_1PreemptionStat.tex | 47 + .../classRTSim_1_1SchedInstr__coll__graph.dot | 49 + .../classRTSim_1_1SchedInstr__coll__graph.md5 | 1 + ...im_1_1DlineEquPeriodDTGen__coll__graph.dot | 31 + ...im_1_1DlineEquPeriodDTGen__coll__graph.md5 | 1 + latex/d4/d00/classRTSim_1_1MissCount.tex | 34 + latex/d4/d17/structCatch_1_1IContext.tex | 29 + ...m_1_1uniformCPUFactory__inherit__graph.dot | 8 + ...m_1_1uniformCPUFactory__inherit__graph.md5 | 1 + ...classRTSim_1_1RTKernel__inherit__graph.dot | 12 + ...classRTSim_1_1RTKernel__inherit__graph.md5 | 1 + latex/d4/d2e/classRTSim_1_1PeriodicTask.tex | 72 + .../structCatch_1_1TestFailureException.tex | 7 + ...TSim_1_1TraceWaitEvent__inherit__graph.dot | 10 + ...TSim_1_1TraceWaitEvent__inherit__graph.md5 | 1 + .../d45/classRTSim_1_1IATGen__coll__graph.dot | 28 + .../d45/classRTSim_1_1IATGen__coll__graph.md5 | 1 + ...assRTSim_1_1CapacityTimer__coll__graph.dot | 8 + ...assRTSim_1_1CapacityTimer__coll__graph.md5 | 1 + .../classRTSim_1_1Instr__inherit__graph.dot | 23 + .../classRTSim_1_1Instr__inherit__graph.md5 | 1 + ...assRTSim_1_1FakeArrEvt__inherit__graph.dot | 10 + ...assRTSim_1_1FakeArrEvt__inherit__graph.md5 | 1 + latex/d4/d61/classRTSim_1_1GrubSupervisor.tex | 53 + latex/d4/d63/classCatch_1_1Stream.tex | 22 + latex/d4/d68/classRTSim_1_1Timer.tex | 46 + latex/d4/d6b/classRTSim_1_1JavaTrace.tex | 73 + latex/d4/d7e/structCatch_1_1SectionInfo.tex | 29 + ...TSim_1_1TaskAlreadyActive__coll__graph.dot | 8 + ...TSim_1_1TaskAlreadyActive__coll__graph.md5 | 1 + latex/d4/d90/classRTSim_1_1absCPUFactory.tex | 36 + latex/d4/d98/classRTSim_1_1MinCTGen.tex | 49 + ...1_1AbstractFeedbackModule__coll__graph.dot | 44 + ...1_1AbstractFeedbackModule__coll__graph.md5 | 1 + ...lassRTSim_1_1AbsKernel__inherit__graph.dot | 21 + ...lassRTSim_1_1AbsKernel__inherit__graph.md5 | 1 + ...lassRTSim_1_1AbsRTTask__inherit__graph.dot | 25 + ...lassRTSim_1_1AbsRTTask__inherit__graph.md5 | 1 + .../classRTSim_1_1Interrupt__coll__graph.dot | 8 + .../classRTSim_1_1Interrupt__coll__graph.md5 | 1 + latex/d4/dc4/classRTSim_1_1SignalInstr.tex | 182 ++ .../classRTSim_1_1WaitEvt__coll__graph.dot | 52 + .../classRTSim_1_1WaitEvt__coll__graph.md5 | 1 + ...Catch_1_1StreamBufImpl__inherit__graph.dot | 10 + ...Catch_1_1StreamBufImpl__inherit__graph.md5 | 1 + latex/d4/dde/classRTSim_1_1CapacityTimer.tex | 60 + latex/d4/de1/classRTSim_1_1Server.tex | 627 +++++ ...uctCatch_1_1IGenerator__inherit__graph.dot | 10 + ...uctCatch_1_1IGenerator__inherit__graph.md5 | 1 + .../d4/dec/structCatch_1_1IGeneratorInfo.tex | 16 + ...TSim_1_1SporadicServer__inherit__graph.dot | 16 + ...TSim_1_1SporadicServer__inherit__graph.md5 | 1 + latex/d5/d05/classRTSim_1_1ConstCTGen.tex | 36 + .../classRTSim_1_1EDFModel__coll__graph.dot | 12 + .../classRTSim_1_1EDFModel__coll__graph.md5 | 1 + ...im_1_1TraceDlineMissEvent__coll__graph.dot | 12 + ...im_1_1TraceDlineMissEvent__coll__graph.md5 | 1 + ...m_1_1FinishingTimeStat__inherit__graph.dot | 8 + ...m_1_1FinishingTimeStat__inherit__graph.md5 | 1 + latex/d5/d13/classRTSim_1_1SparePot.tex | 166 ++ ...lassRTSim_1_1WaitInstr__inherit__graph.dot | 10 + ...lassRTSim_1_1WaitInstr__inherit__graph.md5 | 1 + ...RTSim_1_1FIFOScheduler__inherit__graph.dot | 10 + ...RTSim_1_1FIFOScheduler__inherit__graph.md5 | 1 + ...tor_3_01T1_00_01T2_00_01IsEqualTo_01_4.tex | 13 + .../classRTSim_1_1SparePot__coll__graph.dot | 10 + .../classRTSim_1_1SparePot__coll__graph.md5 | 1 + ...lassRTSim_1_1TaskModel_1_1TaskModelCmp.tex | 14 + ...ch_1_1TagExpressionParser__coll__graph.dot | 8 + ...ch_1_1TagExpressionParser__coll__graph.md5 | 1 + ...im_1_1BeginDispatchEvt__inherit__graph.dot | 10 + ...im_1_1BeginDispatchEvt__inherit__graph.md5 | 1 + latex/d5/d3f/classRTSim_1_1TaskStatExc.tex | 21 + latex/d5/d42/classRTSim_1_1KillEvt.tex | 36 + ...ssRTSim_1_1DispatchEvt__inherit__graph.dot | 10 + ...ssRTSim_1_1DispatchEvt__inherit__graph.md5 | 1 + ...classRTSim_1_1NoSuchInstr__coll__graph.dot | 8 + ...classRTSim_1_1NoSuchInstr__coll__graph.md5 | 1 + ...lassRTSim_1_1Scheduler__inherit__graph.dot | 18 + ...lassRTSim_1_1Scheduler__inherit__graph.md5 | 1 + ...uctCatch_1_1AssertionInfo__coll__graph.dot | 8 + ...uctCatch_1_1AssertionInfo__coll__graph.md5 | 1 + ...RTSim_1_1TaskNotExecuting__coll__graph.dot | 8 + ...RTSim_1_1TaskNotExecuting__coll__graph.md5 | 1 + latex/d5/d62/classRTSim_1_1OffsetGen.tex | 58 + ...assRTSim_1_1UniformIATGen__coll__graph.dot | 30 + ...assRTSim_1_1UniformIATGen__coll__graph.md5 | 1 + .../classRTSim_1_1DeschedEvt__coll__graph.dot | 44 + .../classRTSim_1_1DeschedEvt__coll__graph.md5 | 1 + ...ssRTSim_1_1SignalInstr__inherit__graph.dot | 10 + ...ssRTSim_1_1SignalInstr__inherit__graph.md5 | 1 + ...RTSim_1_1SchedPoint_1_1ChangeBudgetEvt.tex | 30 + .../classRTSim_1_1CTGen__inherit__graph.dot | 16 + .../classRTSim_1_1CTGen__inherit__graph.md5 | 1 + latex/d5/d8c/structCatch_1_1ResultWas.tex | 26 + ..._1NotImplementedException__coll__graph.dot | 8 + ..._1NotImplementedException__coll__graph.md5 | 1 + .../classRTSim_1_1CBServer__coll__graph.dot | 30 + .../classRTSim_1_1CBServer__coll__graph.md5 | 1 + latex/d5/d94/structCatch_1_1NameAndDesc.tex | 22 + latex/d5/d99/classRTSim_1_1Supervisor.tex | 27 + ...ssRTSim_1_1FCFSResManager__coll__graph.dot | 22 + ...ssRTSim_1_1FCFSResManager__coll__graph.md5 | 1 + .../classCatch_1_1Option__inherit__graph.dot | 8 + .../classCatch_1_1Option__inherit__graph.md5 | 1 + latex/d5/dbb/classCatch_1_1TestCaseFilter.tex | 19 + .../d5/dc3/classCatch_1_1TestCaseFilters.tex | 25 + ...1BeginDispatchMultiEvt__inherit__graph.dot | 8 + ...1BeginDispatchMultiEvt__inherit__graph.md5 | 1 + ...m_1_1TraceDeschedEvent__inherit__graph.dot | 12 + ...m_1_1TraceDeschedEvent__inherit__graph.md5 | 1 + ...sCatch_1_1ValuesGenerator__coll__graph.dot | 8 + ...sCatch_1_1ValuesGenerator__coll__graph.md5 | 1 + .../structCatch_1_1LazyStat__coll__graph.dot | 8 + .../structCatch_1_1LazyStat__coll__graph.md5 | 1 + ...assCatch_1_1ScopedMessage__coll__graph.dot | 10 + ...assCatch_1_1ScopedMessage__coll__graph.md5 | 1 + ...1_1RandomRTTaskSetFactory__coll__graph.dot | 32 + ...1_1RandomRTTaskSetFactory__coll__graph.md5 | 1 + .../dee/structCatch_1_1IStreamingReporter.tex | 54 + ..._1_1BeginDispatchMultiEvt__coll__graph.dot | 8 + ..._1_1BeginDispatchMultiEvt__coll__graph.md5 | 1 + ...structCatch_1_1IShared__inherit__graph.dot | 69 + ...structCatch_1_1IShared__inherit__graph.md5 | 1 + .../structCatch_1_1IReporter__coll__graph.dot | 10 + .../structCatch_1_1IReporter__coll__graph.md5 | 1 + latex/d6/d0e/structCatch_1_1IRunner.tex | 7 + .../d13/classRTSim_1_1TraceDlineMissEvent.tex | 22 + ...1TracePowerConsumption__inherit__graph.dot | 14 + ...1TracePowerConsumption__inherit__graph.md5 | 1 + ...ctCatch_1_1AssertionStats__coll__graph.dot | 18 + ...ctCatch_1_1AssertionStats__coll__graph.md5 | 1 + ...tch_1_1IMutableContext__inherit__graph.dot | 8 + ...tch_1_1IMutableContext__inherit__graph.md5 | 1 + latex/d6/d22/classRTSim_1_1CTGen.tex | 62 + latex/d6/d24/classRTSim_1_1RRScheduler.tex | 126 + ...1StdString_1_1EndsWith__inherit__graph.dot | 16 + ...1StdString_1_1EndsWith__inherit__graph.md5 | 1 + latex/d6/d27/structCatch_1_1TestRunStats.tex | 32 + ...ructCatch_1_1ITestCase__inherit__graph.dot | 14 + ...ructCatch_1_1ITestCase__inherit__graph.md5 | 1 + ...ctCatch_1_1StringMaker_3_01T_01_5_01_4.tex | 13 + ...classRTSim_1_1DispatchEvt__coll__graph.dot | 42 + ...classRTSim_1_1DispatchEvt__coll__graph.md5 | 1 + ..._1_1StdString_1_1Contains__coll__graph.dot | 16 + ..._1_1StdString_1_1Contains__coll__graph.md5 | 1 + latex/d6/d46/classRTSim_1_1TardinessStat.tex | 37 + ...TSim_1_1FinishingTimeStat__coll__graph.dot | 8 + ...TSim_1_1FinishingTimeStat__coll__graph.md5 | 1 + .../classRTSim_1_1MissCount__coll__graph.dot | 8 + .../classRTSim_1_1MissCount__coll__graph.md5 | 1 + ...ssRTSim_1_1KernAlreadySet__coll__graph.dot | 8 + ...ssRTSim_1_1KernAlreadySet__coll__graph.md5 | 1 + .../classRTSim_1_1SchedRTA__coll__graph.dot | 10 + .../classRTSim_1_1SchedRTA__coll__graph.md5 | 1 + latex/d6/d6d/classCatch_1_1TagSet.tex | 19 + ..._1_1WrongParameterSize__inherit__graph.dot | 8 + ..._1_1WrongParameterSize__inherit__graph.md5 | 1 + .../d6/d6e/structCatch_1_1IResultCapture.tex | 37 + .../d7c/classRTSim_1_1Timer__coll__graph.dot | 8 + .../d7c/classRTSim_1_1Timer__coll__graph.md5 | 1 + ..._1StdString_1_1StartsWith__coll__graph.dot | 16 + ..._1StdString_1_1StartsWith__coll__graph.md5 | 1 + ...torTraits_3_01IsLessThanOrEqualTo_01_4.tex | 13 + latex/d6/d8d/classRTSim_1_1SuspendInstr.tex | 143 + .../d6/d8f/classRTSim_1_1BeginDispatchEvt.tex | 26 + latex/d6/d90/classSystem__coll__graph.dot | 103 + latex/d6/d90/classSystem__coll__graph.md5 | 1 + .../d99/classCatch_1_1CompositeGenerator.tex | 28 + latex/d6/d9d/classRTSim_1_1Scheduler.tex | 439 +++ .../classRTSim_1_1RandomRTTaskSetFactory.tex | 108 + .../classRTSim_1_1SchedIEvt__coll__graph.dot | 52 + .../classRTSim_1_1SchedIEvt__coll__graph.md5 | 1 + ...lassCatch_1_1TagExtracter__coll__graph.dot | 8 + ...lassCatch_1_1TagExtracter__coll__graph.md5 | 1 + .../classRTSim_1_1ArrEvt__inherit__graph.dot | 10 + .../classRTSim_1_1ArrEvt__inherit__graph.md5 | 1 + ...classRTSim_1_1SchedEvt__inherit__graph.dot | 10 + ...classRTSim_1_1SchedEvt__inherit__graph.md5 | 1 + latex/d6/dc4/structStats__coll__graph.dot | 18 + latex/d6/dc4/structStats__coll__graph.md5 | 1 + .../classRTSim_1_1Timer__inherit__graph.dot | 12 + .../classRTSim_1_1Timer__inherit__graph.md5 | 1 + .../dc8/structCatch_1_1ITestCaseRegistry.tex | 16 + ..._1Matchers_1_1Impl_1_1Generic_1_1AnyOf.tex | 31 + ...ssRTSim_1_1TraceWaitEvent__coll__graph.dot | 12 + ...ssRTSim_1_1TraceWaitEvent__coll__graph.md5 | 1 + ...assCatch_1_1StreamBufBase__coll__graph.dot | 8 + ...assCatch_1_1StreamBufBase__coll__graph.md5 | 1 + ...porterBase_1_1SectionNode__coll__graph.dot | 20 + ...porterBase_1_1SectionNode__coll__graph.md5 | 1 + ...TSim_1_1TraceDeschedEvent__coll__graph.dot | 14 + ...TSim_1_1TraceDeschedEvent__coll__graph.md5 | 1 + .../classRTSim_1_1Resource__coll__graph.dot | 12 + .../classRTSim_1_1Resource__coll__graph.md5 | 1 + latex/d6/df4/classCatch_1_1TestCase.tex | 58 + ...parePot_1_1server__struct__coll__graph.dot | 32 + ...parePot_1_1server__struct__coll__graph.md5 | 1 + ...arePot_1_1ChangeBudgetEvt__coll__graph.dot | 8 + ...arePot_1_1ChangeBudgetEvt__coll__graph.md5 | 1 + ...ndomTaskSetFactory_1_1Exc__coll__graph.dot | 8 + ...ndomTaskSetFactory_1_1Exc__coll__graph.md5 | 1 + ...1_1TraceDlineMissEvent__inherit__graph.dot | 10 + ...1_1TraceDlineMissEvent__inherit__graph.md5 | 1 + .../d15/classRTSim_1_1TraceDeschedEvent.tex | 22 + .../d1a/classRTSim_1_1TraceDlineSetEvent.tex | 86 + .../d29/classRTSim_1_1EndEvt__coll__graph.dot | 44 + .../d29/classRTSim_1_1EndEvt__coll__graph.md5 | 1 + .../d2c/classCatch_1_1TagExpressionParser.tex | 22 + latex/d7/d37/structCatch_1_1MessageInfo.tex | 41 + ...1_1CumulativeReporterBase__coll__graph.dot | 19 + ...1_1CumulativeReporterBase__coll__graph.md5 | 1 + ...etail_1_1StringMakerBase_3_01true_01_4.tex | 13 + latex/d7/d3d/classRTSim_1_1TraceArrEvent.tex | 22 + latex/d7/d3d/structCatch_1_1GroupInfo.tex | 25 + .../d7/d43/classRTSim_1_1TraceSignalEvent.tex | 73 + ..._1SparePot_1_1SparePotExc__coll__graph.dot | 8 + ..._1SparePot_1_1SparePotExc__coll__graph.md5 | 1 + latex/d7/d58/classRTSim_1_1TraceNameEvent.tex | 60 + .../classRTSim_1_1DTGen__inherit__graph.dot | 18 + .../classRTSim_1_1DTGen__inherit__graph.md5 | 1 + latex/d7/d67/classRTSim_1_1MaxIATGen.tex | 58 + latex/d7/d69/classRTSim_1_1SchedPoint.tex | 177 ++ ...im_1_1FeedbackModuleARSim__coll__graph.dot | 46 + ...im_1_1FeedbackModuleARSim__coll__graph.md5 | 1 + ...ctCatch_1_1TestGroupStats__coll__graph.dot | 12 + ...ctCatch_1_1TestGroupStats__coll__graph.md5 | 1 + ...Sim_1_1UtilizationStat__inherit__graph.dot | 8 + ...Sim_1_1UtilizationStat__inherit__graph.md5 | 1 + ...tCatch_1_1IExceptionTranslatorRegistry.tex | 13 + latex/d7/d91/structCatch_1_1SharedImpl.tex | 30 + ...ructCatch_1_1SectionStats__coll__graph.dot | 12 + ...ructCatch_1_1SectionStats__coll__graph.md5 | 1 + ...1_1RRScheduler_1_1RRModel__coll__graph.dot | 12 + ...1_1RRScheduler_1_1RRModel__coll__graph.md5 | 1 + ...1StdString_1_1Contains__inherit__graph.dot | 16 + ...1StdString_1_1Contains__inherit__graph.md5 | 1 + ...1CumulativeReporterBase_1_1SectionNode.tex | 54 + .../structCatch_1_1ReporterPreferences.tex | 13 + ...classRTSim_1_1EDFModel__inherit__graph.dot | 8 + ...classRTSim_1_1EDFModel__inherit__graph.md5 | 1 + latex/d7/dc7/classCatch_1_1Option.tex | 56 + ...ssRTSim_1_1ConstIATGen__inherit__graph.dot | 10 + ...ssRTSim_1_1ConstIATGen__inherit__graph.md5 | 1 + ...lassRTSim_1_1RRScheduler_1_1RRSchedExc.tex | 21 + ...classRTSim_1_1RandomDTGen__coll__graph.dot | 31 + ...classRTSim_1_1RandomDTGen__coll__graph.md5 | 1 + .../structCatch_1_1AssertionResultData.tex | 19 + ...ructCatch_1_1IReporter__inherit__graph.dot | 10 + ...ructCatch_1_1IReporter__inherit__graph.md5 | 1 + ..._1_1IStreamingReporter__inherit__graph.dot | 16 + ..._1_1IStreamingReporter__inherit__graph.md5 | 1 + ...pl_1_1Generic_1_1AllOf__inherit__graph.dot | 16 + ...pl_1_1Generic_1_1AllOf__inherit__graph.md5 | 1 + ...sCatch_1_1ExceptionTranslatorRegistrar.tex | 13 + latex/d7/dfe/classCatch_1_1TagExpression.tex | 19 + ...1_1StdString_1_1Equals__inherit__graph.dot | 16 + ...1_1StdString_1_1Equals__inherit__graph.md5 | 1 + .../classRTSim_1_1MinCTGen__coll__graph.dot | 32 + .../classRTSim_1_1MinCTGen__coll__graph.md5 | 1 + ...classRTSim_1_1DlineSetEvt__coll__graph.dot | 46 + ...classRTSim_1_1DlineSetEvt__coll__graph.md5 | 1 + ...assCatch_1_1StreamBufImpl__coll__graph.dot | 10 + ...assCatch_1_1StreamBufImpl__coll__graph.md5 | 1 + latex/d8/d1e/classRTSim_1_1SporadicServer.tex | 139 + ...Sim_1_1WrongParameterSize__coll__graph.dot | 8 + ...Sim_1_1WrongParameterSize__coll__graph.md5 | 1 + ...1_1SchedRTA_1_1ServerInfo__coll__graph.dot | 30 + ...1_1SchedRTA_1_1ServerInfo__coll__graph.md5 | 1 + ...pl_1_1Generic_1_1AnyOf__inherit__graph.dot | 16 + ...pl_1_1Generic_1_1AnyOf__inherit__graph.md5 | 1 + latex/d8/d3a/classRTSim_1_1Resource.tex | 73 + latex/d8/d44/classCatch_1_1Timer.tex | 22 + latex/d8/d44/classRTSim_1_1FCFSResManager.tex | 61 + .../d44/classRTSim_1_1Instr__coll__graph.dot | 47 + .../d44/classRTSim_1_1Instr__coll__graph.md5 | 1 + ...ructCatch_1_1TestRunStats__coll__graph.dot | 12 + ...ructCatch_1_1TestRunStats__coll__graph.md5 | 1 + latex/d8/d59/structRTSim_1_1cpulevel.tex | 19 + ...assRTSim_1_1SporadicDTGen__coll__graph.dot | 31 + ...assRTSim_1_1SporadicDTGen__coll__graph.md5 | 1 + .../d62/structCatch_1_1ResultDisposition.tex | 17 + ...otImplementedException__inherit__graph.dot | 8 + ...otImplementedException__inherit__graph.md5 | 1 + latex/d8/d7e/classRTSim_1_1DeadEvt.tex | 39 + ...pl_1_1StdString_1_1Equals__coll__graph.dot | 16 + ...pl_1_1StdString_1_1Equals__coll__graph.md5 | 1 + ...lassRTSim_1_1TaskModel__inherit__graph.dot | 15 + ...lassRTSim_1_1TaskModel__inherit__graph.md5 | 1 + ...terBase_1_1SectionNode__inherit__graph.dot | 12 + ...terBase_1_1SectionNode__inherit__graph.md5 | 1 + ...classRTSim_1_1ConstIATGen__coll__graph.dot | 30 + ...classRTSim_1_1ConstIATGen__coll__graph.md5 | 1 + ...RTSim_1_1BeginDispatchEvt__coll__graph.dot | 40 + ...RTSim_1_1BeginDispatchEvt__coll__graph.md5 | 1 + latex/d8/da0/classRTSim_1_1TraceEndEvent.tex | 22 + ...RTSim_1_1TraceArrEvent__inherit__graph.dot | 10 + ...RTSim_1_1TraceArrEvent__inherit__graph.md5 | 1 + latex/d8/db0/classRTSim_1_1Task.tex | 819 ++++++ ...FPScheduler_1_1FPModel__inherit__graph.dot | 8 + ...FPScheduler_1_1FPModel__inherit__graph.md5 | 1 + ...RTSim_1_1absCPUFactory__inherit__graph.dot | 8 + ...RTSim_1_1absCPUFactory__inherit__graph.md5 | 1 + .../dbd/classRTSim_1_1FeedbackModuleARSim.tex | 115 + ..._1_1OperatorTraits_3_01IsLessThan_01_4.tex | 13 + ...TSim_1_1EndDispatchEvt__inherit__graph.dot | 10 + ...TSim_1_1EndDispatchEvt__inherit__graph.md5 | 1 + ...ructCatch_1_1TestCaseInfo__coll__graph.dot | 8 + ...ructCatch_1_1TestCaseInfo__coll__graph.md5 | 1 + ...lassRTSim_1_1ThreInstr__inherit__graph.dot | 10 + ...lassRTSim_1_1ThreInstr__inherit__graph.md5 | 1 + ...lassRTSim_1_1ServerExc__inherit__graph.dot | 10 + ...lassRTSim_1_1ServerExc__inherit__graph.md5 | 1 + ...CumulativeReporterBase__inherit__graph.dot | 14 + ...CumulativeReporterBase__inherit__graph.md5 | 1 + ...RRScheduler_1_1RRSchedExc__coll__graph.dot | 8 + ...RRScheduler_1_1RRSchedExc__coll__graph.md5 | 1 + ...mTaskSetFactory_1_1Exc__inherit__graph.dot | 8 + ...mTaskSetFactory_1_1Exc__inherit__graph.md5 | 1 + latex/d9/d11/classRTSim_1_1TraceCPUEvent.tex | 70 + latex/d9/d14/classCatch_1_1StreamBufBase.tex | 15 + .../d9/d1c/classRTSim_1_1RandomOffsetGen.tex | 41 + latex/d9/d24/classRTSim_1_1RTModel.tex | 184 ++ .../d24/namespaceRTSim_1_1____sched__stub.tex | 8 + ...ch_1_1BetweenGenerator__inherit__graph.dot | 8 + ...ch_1_1BetweenGenerator__inherit__graph.md5 | 1 + ...ers_1_1Impl_1_1Matcher__inherit__graph.dot | 23 + ...ers_1_1Impl_1_1Matcher__inherit__graph.md5 | 1 + .../classRTSim_1_1FPScheduler_1_1FPModel.tex | 67 + ...assRTSim_1_1Supervisor__inherit__graph.dot | 14 + ...assRTSim_1_1Supervisor__inherit__graph.md5 | 1 + ...im_1_1EndDispatchMultiEvt__coll__graph.dot | 8 + ...im_1_1EndDispatchMultiEvt__coll__graph.md5 | 1 + ...RTSim_1_1TraceCPUEvent__inherit__graph.dot | 16 + ...RTSim_1_1TraceCPUEvent__inherit__graph.md5 | 1 + .../classRTSim_1_1SchedEvt__coll__graph.dot | 44 + .../classRTSim_1_1SchedEvt__coll__graph.md5 | 1 + ...uctCatch_1_1SharedImpl__inherit__graph.dot | 8 + ...uctCatch_1_1SharedImpl__inherit__graph.md5 | 1 + .../classRTSim_1_1GrubExc__inherit__graph.dot | 10 + .../classRTSim_1_1GrubExc__inherit__graph.md5 | 1 + .../structCatch_1_1ITestCase__coll__graph.dot | 10 + .../structCatch_1_1ITestCase__coll__graph.md5 | 1 + ...lassRTSim_1_1MinIATGen__inherit__graph.dot | 12 + ...lassRTSim_1_1MinIATGen__inherit__graph.md5 | 1 + ...ers_1_1Impl_1_1StdString_1_1StartsWith.tex | 37 + ...assRTSim_1_1FIFOScheduler__coll__graph.dot | 17 + ...assRTSim_1_1FIFOScheduler__coll__graph.md5 | 1 + .../classRTSim_1_1SchedPoint__coll__graph.dot | 10 + .../classRTSim_1_1SchedPoint__coll__graph.md5 | 1 + ...TSim_1_1TraceIdleEvent__inherit__graph.dot | 10 + ...TSim_1_1TraceIdleEvent__inherit__graph.md5 | 1 + ...chers_1_1Impl_1_1StdString_1_1Contains.tex | 37 + .../classCatch_1_1TestCase__coll__graph.dot | 10 + .../classCatch_1_1TestCase__coll__graph.md5 | 1 + ...ssRTSim_1_1ModeOutOfIndex__coll__graph.dot | 8 + ...ssRTSim_1_1ModeOutOfIndex__coll__graph.md5 | 1 + ..._1Matchers_1_1Impl_1_1Generic_1_1AllOf.tex | 31 + ...ssRTSim_1_1RRScheduler__inherit__graph.dot | 10 + ...ssRTSim_1_1RRScheduler__inherit__graph.md5 | 1 + ...l_1_1OperatorTraits_3_01IsEqualTo_01_4.tex | 13 + .../structCatch_1_1IExceptionTranslator.tex | 13 + ..._1_1StdString_1_1EndsWith__coll__graph.dot | 16 + ..._1_1StdString_1_1EndsWith__coll__graph.md5 | 1 + ...ssRTSim_1_1SparePot_1_1ChangeBudgetEvt.tex | 30 + ...ssRTSim_1_1TraceIdleEvent__coll__graph.dot | 12 + ...ssRTSim_1_1TraceIdleEvent__coll__graph.md5 | 1 + .../classRTSim_1_1AbsRTTask__coll__graph.dot | 8 + .../classRTSim_1_1AbsRTTask__coll__graph.md5 | 1 + .../d9/db1/structCatch_1_1IfFilterMatches.tex | 16 + .../classCatch_1_1Internal_1_1Evaluator.tex | 7 + .../classCatch_1_1NotImplementedException.tex | 24 + ..._1TaskAlreadyExecuting__inherit__graph.dot | 8 + ..._1TaskAlreadyExecuting__inherit__graph.md5 | 1 + latex/d9/db9/classRTSim_1_1KernAlreadySet.tex | 15 + ...assRTSim_1_1SavedPower__inherit__graph.dot | 10 + ...assRTSim_1_1SavedPower__inherit__graph.md5 | 1 + .../classRTSim_1_1AbstractFeedbackModule.tex | 47 + latex/d9/ddd/classRTSim_1_1EndEvt.tex | 36 + ...ssCatch_1_1NonCopyable__inherit__graph.dot | 69 + ...ssCatch_1_1NonCopyable__inherit__graph.md5 | 1 + ...m_1_1TaskAlreadyActive__inherit__graph.dot | 8 + ...m_1_1TaskAlreadyActive__inherit__graph.md5 | 1 + latex/d9/df6/classRTSim_1_1DTGen.tex | 61 + latex/da/d06/classRTSim_1_1SuperCBS.tex | 148 + .../da/d0b/classRTSim_1_1BWI__coll__graph.dot | 22 + .../da/d0b/classRTSim_1_1BWI__coll__graph.md5 | 1 + ...classRTSim_1_1InstrExc__inherit__graph.dot | 8 + ...classRTSim_1_1InstrExc__inherit__graph.md5 | 1 + latex/da/d10/classCatch_1_1Section.tex | 16 + ...TSim_1_1MissPercentage__inherit__graph.dot | 8 + ...TSim_1_1MissPercentage__inherit__graph.md5 | 1 + latex/da/d14/classCatch_1_1Tag.tex | 22 + .../d14/classRTSim_1_1CPU__inherit__graph.dot | 8 + .../d14/classRTSim_1_1CPU__inherit__graph.md5 | 1 + ...atchers_1_1Impl_1_1StdString_1_1Equals.tex | 37 + latex/da/d19/classRTSim_1_1PeriodicTimer.tex | 29 + latex/da/d24/classRTSim_1_1RandomDTGen.tex | 41 + latex/da/d27/classRTSim_1_1RTSchedExc.tex | 25 + ...3_01T1_00_01T2_00_01IsGreaterThan_01_4.tex | 13 + ...or_3_01T1_00_01T2_00_01IsLessThan_01_4.tex | 13 + latex/da/d3e/classRTSim_1_1RTKernel.tex | 475 ++++ ...sRTSim_1_1UniformCTGen__inherit__graph.dot | 14 + ...sRTSim_1_1UniformCTGen__inherit__graph.md5 | 1 + .../classRTSim_1_1MRTKernel__coll__graph.dot | 44 + .../classRTSim_1_1MRTKernel__coll__graph.md5 | 1 + latex/da/d6b/classRTSim_1_1FIFOScheduler.tex | 72 + ...Sim_1_1RandomOffsetGen__inherit__graph.dot | 12 + ...Sim_1_1RandomOffsetGen__inherit__graph.md5 | 1 + ...tCatch_1_1Detail_1_1IsStreamInsertable.tex | 23 + latex/da/d76/structCatch_1_1IReporter.tex | 57 + .../classRTSim_1_1Server__inherit__graph.dot | 22 + .../classRTSim_1_1Server__inherit__graph.md5 | 1 + latex/da/d8a/structCatch_1_1TestRunInfo.tex | 19 + ...Traits_3_01IsGreaterThanOrEqualTo_01_4.tex | 13 + ...CBS_1_1ChangeBudgetEvt__inherit__graph.dot | 8 + ...CBS_1_1ChangeBudgetEvt__inherit__graph.md5 | 1 + ...lassRTSim_1_1EDFScheduler__coll__graph.dot | 17 + ...lassRTSim_1_1EDFScheduler__coll__graph.md5 | 1 + latex/da/da7/classRTSim_1_1EDFModel.tex | 66 + .../classRTSim_1_1MaxIATGen__coll__graph.dot | 32 + .../classRTSim_1_1MaxIATGen__coll__graph.md5 | 1 + .../classRTSim_1_1KernelEvt__coll__graph.dot | 40 + .../classRTSim_1_1KernelEvt__coll__graph.md5 | 1 + ...sRTSim_1_1EDFScheduler__inherit__graph.dot | 10 + ...sRTSim_1_1EDFScheduler__inherit__graph.md5 | 1 + ...uperCBS_1_1SuperCBSExc__inherit__graph.dot | 8 + ...uperCBS_1_1SuperCBSExc__inherit__graph.md5 | 1 + latex/da/dcb/structCatch_1_1TrueType.tex | 25 + ...assRTSim_1_1TraceEndEvent__coll__graph.dot | 14 + ...assRTSim_1_1TraceEndEvent__coll__graph.md5 | 1 + latex/da/dd3/classRTSim_1_1SignalEvt.tex | 40 + ...sRTSim_1_1PeriodicTask__inherit__graph.dot | 14 + ...sRTSim_1_1PeriodicTask__inherit__graph.md5 | 1 + ...classRTSim_1_1SchedRTA__inherit__graph.dot | 10 + ...classRTSim_1_1SchedRTA__inherit__graph.md5 | 1 + ..._1SuperCBS_1_1SuperCBSExc__coll__graph.dot | 8 + ..._1SuperCBS_1_1SuperCBSExc__coll__graph.md5 | 1 + ...ssRTSim_1_1RandomTaskSetFactory_1_1Exc.tex | 58 + latex/da/dff/structCatch_1_1LazyStat.tex | 30 + latex/db/d01/classRTSim_1_1WaitEvt.tex | 40 + ...int_1_1ChangeBudgetEvt__inherit__graph.dot | 8 + ...int_1_1ChangeBudgetEvt__inherit__graph.md5 | 1 + ...RRScheduler_1_1RRModel__inherit__graph.dot | 8 + ...RRScheduler_1_1RRModel__inherit__graph.md5 | 1 + .../db/d06/structCatch_1_1ReporterConfig.tex | 22 + latex/db/d0a/classRTSim_1_1RMScheduler.tex | 68 + .../classRTSim_1_1ThreEvt__coll__graph.dot | 52 + .../classRTSim_1_1ThreEvt__coll__graph.md5 | 1 + ...hedPoint_1_1SchedPointExc__coll__graph.dot | 8 + ...hedPoint_1_1SchedPointExc__coll__graph.md5 | 1 + .../classRTSim_1_1RRScheduler_1_1RRModel.tex | 84 + ...ssRTSim_1_1NoSuchInstr__inherit__graph.dot | 8 + ...ssRTSim_1_1NoSuchInstr__inherit__graph.md5 | 1 + latex/db/d38/classRTSim_1_1VirtualTrace.tex | 20 + ...assRTSim_1_1SchedInstr__inherit__graph.dot | 10 + ...assRTSim_1_1SchedInstr__inherit__graph.md5 | 1 + .../classRTSim_1_1RTModel__coll__graph.dot | 13 + .../classRTSim_1_1RTModel__coll__graph.md5 | 1 + ...lassRTSim_1_1LatenessStat__coll__graph.dot | 8 + ...lassRTSim_1_1LatenessStat__coll__graph.md5 | 1 + latex/db/d71/classRTSim_1_1DeschedEvt.tex | 31 + .../db/d7b/classCatch_1_1BetweenGenerator.tex | 27 + ...tructCatch_1_1LazyStat__inherit__graph.dot | 8 + ...tructCatch_1_1LazyStat__inherit__graph.md5 | 1 + latex/db/d7f/classRTSim_1_1ServerExc.tex | 21 + ...im_1_1TraceSignalEvent__inherit__graph.dot | 10 + ...im_1_1TraceSignalEvent__inherit__graph.md5 | 1 + .../d8e/classRTSim_1_1CTGen__coll__graph.dot | 28 + .../d8e/classRTSim_1_1CTGen__coll__graph.md5 | 1 + latex/db/d95/classRTSim_1_1MRTKernel.tex | 345 +++ latex/db/da4/classRTSim_1_1ExecInstr.tex | 221 ++ latex/db/dae/structCatch_1_1IGenerator.tex | 20 + .../db8/classRTSim_1_1DlineEquPeriodDTGen.tex | 35 + .../classRTSim_1_1Grub__inherit__graph.dot | 16 + .../classRTSim_1_1Grub__inherit__graph.md5 | 1 + latex/db/dc8/structCatch_1_1Verbosity.tex | 16 + ...sRTSim_1_1LatenessStat__inherit__graph.dot | 8 + ...sRTSim_1_1LatenessStat__inherit__graph.md5 | 1 + ..._1_1FeedbackTestModule__inherit__graph.dot | 10 + ..._1_1FeedbackTestModule__inherit__graph.md5 | 1 + .../db/dcf/structCatch_1_1AssertionStats.tex | 29 + .../dd3/classRTSim_1_1ArrEvt__coll__graph.dot | 44 + .../dd3/classRTSim_1_1ArrEvt__coll__graph.md5 | 1 + .../ddf/structCatch_1_1IReporterFactory.tex | 16 + ...ssRTSim_1_1EndInstrEvt__inherit__graph.dot | 8 + ...ssRTSim_1_1EndInstrEvt__inherit__graph.md5 | 1 + ...sRTSim_1_1SuspendInstr__inherit__graph.dot | 10 + ...sRTSim_1_1SuspendInstr__inherit__graph.md5 | 1 + ...TSim_1_1TraceTaskEvent__inherit__graph.dot | 33 + ...TSim_1_1TraceTaskEvent__inherit__graph.md5 | 1 + ...lassRTSim_1_1ExecInstr__inherit__graph.dot | 12 + ...lassRTSim_1_1ExecInstr__inherit__graph.md5 | 1 + ...assRTSim_1_1PIRManager__inherit__graph.dot | 10 + ...assRTSim_1_1PIRManager__inherit__graph.md5 | 1 + ...structCatch_1_1SharedImpl__coll__graph.dot | 8 + ...structCatch_1_1SharedImpl__coll__graph.md5 | 1 + ...classRTSim_1_1RRScheduler__coll__graph.dot | 17 + ...classRTSim_1_1RRScheduler__coll__graph.md5 | 1 + .../d02/classRTSim_1_1Task__coll__graph.dot | 44 + .../d02/classRTSim_1_1Task__coll__graph.md5 | 1 + ...Sim_1_1TraceDlineSetEvent__coll__graph.dot | 12 + ...Sim_1_1TraceDlineSetEvent__coll__graph.md5 | 1 + .../classRTSim_1_1FakeArrEvt__coll__graph.dot | 44 + .../classRTSim_1_1FakeArrEvt__coll__graph.md5 | 1 + .../classRTSim_1_1ThreInstr__coll__graph.dot | 49 + .../classRTSim_1_1ThreInstr__coll__graph.md5 | 1 + ...RTSim_1_1TraceSignalEvent__coll__graph.dot | 12 + ...RTSim_1_1TraceSignalEvent__coll__graph.md5 | 1 + latex/dc/d11/structCatch_1_1SectionStats.tex | 32 + .../classRTSim_1_1KillEvt__inherit__graph.dot | 10 + .../classRTSim_1_1KillEvt__inherit__graph.md5 | 1 + latex/dc/d17/classRTSim_1_1SchedInstr.tex | 175 ++ latex/dc/d1c/classCatch_1_1NonCopyable.tex | 11 + ...1_1EndDispatchMultiEvt__inherit__graph.dot | 8 + ...1_1EndDispatchMultiEvt__inherit__graph.md5 | 1 + ...TSim_1_1TraceNameEvent__inherit__graph.dot | 10 + ...TSim_1_1TraceNameEvent__inherit__graph.md5 | 1 + ...ssRTSim_1_1RTKernelExc__inherit__graph.dot | 8 + ...ssRTSim_1_1RTKernelExc__inherit__graph.md5 | 1 + .../dc/d2b/structCatch_1_1SourceLineInfo.tex | 31 + ...RTSim_1_1UniformIATGen__inherit__graph.dot | 14 + ...RTSim_1_1UniformIATGen__inherit__graph.md5 | 1 + .../d33/structCatch_1_1OutputDebugWriter.tex | 13 + latex/dc/d36/classRTSim_1_1ResManager.tex | 163 ++ .../d3d/namespaceRTSim_1_1____task__stub.tex | 6 + .../dc/d4e/classRTSim_1_1TraceSchedEvent.tex | 22 + ...sRTSim_1_1TraceSchedEvent__coll__graph.dot | 14 + ...sRTSim_1_1TraceSchedEvent__coll__graph.md5 | 1 + ...lassRTSim_1_1MaxIATGen__inherit__graph.dot | 12 + ...lassRTSim_1_1MaxIATGen__inherit__graph.md5 | 1 + .../classCatch_1_1ExpressionResultBuilder.tex | 52 + latex/dc/d59/structCatch_1_1AutoReg.tex | 19 + ...assRTSim_1_1TaskNotActive__coll__graph.dot | 8 + ...assRTSim_1_1TaskNotActive__coll__graph.md5 | 1 + ...tCatch_1_1IMutableContext__coll__graph.dot | 8 + ...tCatch_1_1IMutableContext__coll__graph.md5 | 1 + latex/dc/d5e/classRTSim_1_1WaitInstr.tex | 182 ++ .../classRTSim_1_1RandomTaskSetFactory.tex | 212 ++ .../classRTSim_1_1MinIATGen__coll__graph.dot | 32 + .../classRTSim_1_1MinIATGen__coll__graph.md5 | 1 + ..._00_01T2_00_01IsLessThanOrEqualTo_01_4.tex | 13 + latex/dc/d72/classCatch_1_1Config.tex | 82 + ...sCatch_1_1TagExtracter__inherit__graph.dot | 8 + ...sCatch_1_1TagExtracter__inherit__graph.md5 | 1 + ...tructCatch_1_1SectionInfo__coll__graph.dot | 8 + ...tructCatch_1_1SectionInfo__coll__graph.md5 | 1 + ...ctCatch_1_1Matchers_1_1Impl_1_1Matcher.tex | 34 + latex/dc/d89/classCatch_1_1MethodTestCase.tex | 25 + ...1_1TagExpressionParser__inherit__graph.dot | 8 + ...1_1TagExpressionParser__inherit__graph.md5 | 1 + .../classRTSim_1_1AVRTask__inherit__graph.dot | 14 + .../classRTSim_1_1AVRTask__inherit__graph.md5 | 1 + .../classRTSim_1_1PIRManager__coll__graph.dot | 22 + .../classRTSim_1_1PIRManager__coll__graph.md5 | 1 + latex/dc/dbb/classRTSim_1_1Grub.tex | 145 + ...ctCatch_1_1MessageBuilder__coll__graph.dot | 10 + ...ctCatch_1_1MessageBuilder__coll__graph.md5 | 1 + .../dc/dc9/structCatch_1_1IMutableContext.tex | 27 + .../structCatch_1_1CumulativeReporterBase.tex | 112 + latex/dc/de5/classRTSim_1_1LatenessStat.tex | 37 + ...1OperatorTraits_3_01IsGreaterThan_01_4.tex | 13 + .../classRTSim_1_1Task__inherit__graph.dot | 16 + .../classRTSim_1_1Task__inherit__graph.md5 | 1 + ...uctCatch_1_1Internal_1_1OperatorTraits.tex | 13 + latex/dc/df6/classCatch_1_1Ptr.tex | 46 + .../classRTSim_1_1DeadEvt__inherit__graph.dot | 10 + .../classRTSim_1_1DeadEvt__inherit__graph.md5 | 1 + latex/dd/d0d/classMySim.tex | 5 + latex/dd/d0d/classMySim.tex.tmp | 65 + ...TSim_1_1uniformCPUFactory__coll__graph.dot | 8 + ...TSim_1_1uniformCPUFactory__coll__graph.md5 | 1 + ...1StreamingReporterBase__inherit__graph.dot | 14 + ...1StreamingReporterBase__inherit__graph.md5 | 1 + ...lassRTSim_1_1EmptyTask__inherit__graph.dot | 8 + ...lassRTSim_1_1EmptyTask__inherit__graph.md5 | 1 + latex/dd/d1b/classRTSim_1_1Instr.tex | 179 ++ .../dd/d1f/classRTSim_1_1TaskNotExecuting.tex | 21 + ...lassRTSim_1_1KernelEvt__inherit__graph.dot | 14 + ...lassRTSim_1_1KernelEvt__inherit__graph.md5 | 1 + ...Pot_1_1ChangeBudgetEvt__inherit__graph.dot | 8 + ...Pot_1_1ChangeBudgetEvt__inherit__graph.md5 | 1 + latex/dd/d2d/classSystem.tex | 79 + ...parePot_1_1SparePotExc__inherit__graph.dot | 8 + ...parePot_1_1SparePotExc__inherit__graph.md5 | 1 + latex/dd/d34/classRTSim_1_1SchedIEvt.tex | 40 + ...classRTSim_1_1FPScheduler__coll__graph.dot | 17 + ...classRTSim_1_1FPScheduler__coll__graph.md5 | 1 + ...classRTSim_1_1CBServer__inherit__graph.dot | 16 + ...classRTSim_1_1CBServer__inherit__graph.md5 | 1 + latex/dd/d3e/classMySim__coll__graph.dot | 61 + latex/dd/d3e/classMySim__coll__graph.md5 | 1 + ...sRTSim_1_1RandomOffsetGen__coll__graph.dot | 31 + ...sRTSim_1_1RandomOffsetGen__coll__graph.md5 | 1 + .../classRTSim_1_1AVRTask__coll__graph.dot | 46 + .../classRTSim_1_1AVRTask__coll__graph.md5 | 1 + ...classCatch_1_1TestCase__inherit__graph.dot | 8 + ...classCatch_1_1TestCase__inherit__graph.md5 | 1 + ...cheduler_1_1RRSchedExc__inherit__graph.dot | 8 + ...cheduler_1_1RRSchedExc__inherit__graph.md5 | 1 + .../classRTSim_1_1Scheduler__coll__graph.dot | 15 + .../classRTSim_1_1Scheduler__coll__graph.md5 | 1 + ...assRTSim_1_1DeschedEvt__inherit__graph.dot | 10 + ...assRTSim_1_1DeschedEvt__inherit__graph.md5 | 1 + latex/dd/d60/classRTSim_1_1KernelEvt.tex | 33 + ...perCBS_1_1ChangeBudgetEvt__coll__graph.dot | 8 + ...perCBS_1_1ChangeBudgetEvt__coll__graph.md5 | 1 + latex/dd/d72/classRTSim_1_1DlineSetEvt.tex | 31 + latex/dd/d73/classRTSim_1_1MaxCTGen.tex | 49 + ...RTSim_1_1TraceEndEvent__inherit__graph.dot | 12 + ...RTSim_1_1TraceEndEvent__inherit__graph.md5 | 1 + ...atch_1_1CumulativeReporterBase_1_1Node.tex | 36 + .../d7a/classRTSim_1_1FinishingTimeStat.tex | 37 + .../classRTSim_1_1RTModel_1_1RTModelCmp.tex | 20 + .../classRTSim_1_1MaxCTGen__coll__graph.dot | 32 + .../classRTSim_1_1MaxCTGen__coll__graph.md5 | 1 + .../classRTSim_1_1OffsetGen__coll__graph.dot | 28 + .../classRTSim_1_1OffsetGen__coll__graph.md5 | 1 + .../classRTSim_1_1WaitInstr__coll__graph.dot | 49 + .../classRTSim_1_1WaitInstr__coll__graph.md5 | 1 + latex/dd/da8/structCatch_1_1ResultAction.tex | 17 + latex/dd/da9/classRTSim_1_1PIRManager.tex | 89 + latex/dd/da9/classRTSim_1_1RTKernelExc.tex | 28 + ...assRTSim_1_1PeriodicTimer__coll__graph.dot | 10 + ...assRTSim_1_1PeriodicTimer__coll__graph.md5 | 1 + ..._1RandomTaskSetFactory__inherit__graph.dot | 8 + ..._1RandomTaskSetFactory__inherit__graph.md5 | 1 + ...ativeReporterBase_1_1Node__coll__graph.dot | 12 + ...ativeReporterBase_1_1Node__coll__graph.md5 | 1 + ...TSim_1_1ModeOutOfIndex__inherit__graph.dot | 8 + ...TSim_1_1ModeOutOfIndex__inherit__graph.md5 | 1 + latex/dd/dc7/structCatch_1_1ConfigData.tex | 58 + ...uctRTSim_1_1SparePot_1_1server__struct.tex | 23 + ...ssRTSim_1_1TaskStatExc__inherit__graph.dot | 8 + ...ssRTSim_1_1TaskStatExc__inherit__graph.md5 | 1 + ...ssRTSim_1_1TraceTaskEvent__coll__graph.dot | 10 + ...ssRTSim_1_1TraceTaskEvent__coll__graph.md5 | 1 + ...ssRTSim_1_1RandomDTGen__inherit__graph.dot | 12 + ...ssRTSim_1_1RandomDTGen__inherit__graph.md5 | 1 + .../dda/namespaceRTSim_1_1____instr__stub.tex | 8 + .../classRTSim_1_1IATGen__inherit__graph.dot | 16 + .../classRTSim_1_1IATGen__inherit__graph.md5 | 1 + ...tructCatch_1_1MessageInfo__coll__graph.dot | 8 + ...tructCatch_1_1MessageInfo__coll__graph.md5 | 1 + .../df2/classCatch_1_1Config__coll__graph.dot | 14 + .../df2/classCatch_1_1Config__coll__graph.md5 | 1 + ...lassRTSim_1_1JavaTrace__inherit__graph.dot | 8 + ...lassRTSim_1_1JavaTrace__inherit__graph.md5 | 1 + ...classRTSim_1_1EndInstrEvt__coll__graph.dot | 8 + ...classRTSim_1_1EndInstrEvt__coll__graph.md5 | 1 + .../structCatch_1_1StreamingReporterBase.tex | 69 + ...classRTSim_1_1SparePot__inherit__graph.dot | 10 + ...classRTSim_1_1SparePot__inherit__graph.md5 | 1 + .../classRTSim_1_1DeadEvt__coll__graph.dot | 44 + .../classRTSim_1_1DeadEvt__coll__graph.md5 | 1 + ...Sim_1_1TraceSchedEvent__inherit__graph.dot | 12 + ...Sim_1_1TraceSchedEvent__inherit__graph.md5 | 1 + ...im_1_1TraceDlinePostEvent__coll__graph.dot | 12 + ...im_1_1TraceDlinePostEvent__coll__graph.md5 | 1 + .../classRTSim_1_1ResManager__coll__graph.dot | 20 + .../classRTSim_1_1ResManager__coll__graph.md5 | 1 + ...assRTSim_1_1RTSchedExc__inherit__graph.dot | 9 + ...assRTSim_1_1RTSchedExc__inherit__graph.md5 | 1 + .../classRTSim_1_1WaitEvt__inherit__graph.dot | 10 + .../classRTSim_1_1WaitEvt__inherit__graph.md5 | 1 + .../classRTSim_1_1SignalEvt__coll__graph.dot | 52 + .../classRTSim_1_1SignalEvt__coll__graph.md5 | 1 + ...tchers_1_1Impl_1_1Matcher__coll__graph.dot | 12 + ...tchers_1_1Impl_1_1Matcher__coll__graph.md5 | 1 + .../classRTSim_1_1TaskEvt__inherit__graph.dot | 33 + .../classRTSim_1_1TaskEvt__inherit__graph.md5 | 1 + .../classRTSim_1_1TaskModel__coll__graph.dot | 10 + .../classRTSim_1_1TaskModel__coll__graph.md5 | 1 + ...1vector_3_01T_00_01Allocator_01_4_01_4.tex | 13 + latex/de/d5f/classRTSim_1_1AbsTask.tex | 112 + latex/de/d62/structCatch_1_1TestCaseInfo.tex | 48 + ...ssRTSim_1_1MissPercentage__coll__graph.dot | 8 + ...ssRTSim_1_1MissPercentage__coll__graph.md5 | 1 + ...assRTSim_1_1TraceCPUEvent__coll__graph.dot | 12 + ...assRTSim_1_1TraceCPUEvent__coll__graph.md5 | 1 + .../d79/classRTSim_1_1TraceDlinePostEvent.tex | 92 + latex/de/d7f/classRTSim_1_1AbsKernel.tex | 156 ++ ...RTSim_1_1CapacityTimer__inherit__graph.dot | 8 + ...RTSim_1_1CapacityTimer__inherit__graph.md5 | 1 + ...uctCatch_1_1TestCaseStats__coll__graph.dot | 14 + ...uctCatch_1_1TestCaseStats__coll__graph.md5 | 1 + latex/de/d8c/structCatch_1_1ITestCase.tex | 21 + ...Sim_1_1FeedbackTestModule__coll__graph.dot | 46 + ...Sim_1_1FeedbackTestModule__coll__graph.md5 | 1 + ...lassRTSim_1_1MRTKernel__inherit__graph.dot | 12 + ...lassRTSim_1_1MRTKernel__inherit__graph.md5 | 1 + latex/de/d98/classRTSim_1_1CPU.tex | 92 + ...classRTSim_1_1MaxCTGen__inherit__graph.dot | 12 + ...classRTSim_1_1MaxCTGen__inherit__graph.md5 | 1 + ...tructCatch_1_1StringMaker__coll__graph.dot | 8 + ...tructCatch_1_1StringMaker__coll__graph.md5 | 1 + ..._1OperatorTraits_3_01IsNotEqualTo_01_4.tex | 13 + latex/de/db0/structCatch_1_1Counts.tex | 28 + .../classRTSim_1_1JavaTrace__coll__graph.dot | 8 + .../classRTSim_1_1JavaTrace__coll__graph.md5 | 1 + latex/de/db6/classRTSim_1_1TraceIdleEvent.tex | 22 + ...ssRTSim_1_1RMScheduler__inherit__graph.dot | 12 + ...ssRTSim_1_1RMScheduler__inherit__graph.md5 | 1 + ...dPoint_1_1ChangeBudgetEvt__coll__graph.dot | 8 + ...dPoint_1_1ChangeBudgetEvt__coll__graph.md5 | 1 + latex/de/dc9/classRTSim_1_1GrubExc.tex | 21 + latex/de/dcf/structCatch_1_1WarnAbout.tex | 15 + ...rs_1_1Impl_1_1MatcherImpl__coll__graph.dot | 14 + ...rs_1_1Impl_1_1MatcherImpl__coll__graph.md5 | 1 + ...ssRTSim_1_1PreemptionStat__coll__graph.dot | 8 + ...ssRTSim_1_1PreemptionStat__coll__graph.md5 | 1 + ..._3_01T1_00_01T2_00_01IsNotEqualTo_01_4.tex | 13 + ..._1_1TracePowerConsumption__coll__graph.dot | 14 + ..._1_1TracePowerConsumption__coll__graph.md5 | 1 + .../classRTSim_1_1SuperCBS_1_1SuperCBSExc.tex | 21 + ...1_1DlineEquPeriodDTGen__inherit__graph.dot | 12 + ...1_1DlineEquPeriodDTGen__inherit__graph.md5 | 1 + ...AbstractFeedbackModule__inherit__graph.dot | 12 + ...AbstractFeedbackModule__inherit__graph.md5 | 1 + ...lassRTSim_1_1SchedIEvt__inherit__graph.dot | 10 + ...lassRTSim_1_1SchedIEvt__inherit__graph.md5 | 1 + latex/df/d1d/classCatch_1_1SafeBool.tex | 19 + ...tCatch_1_1TestCaseInfo__inherit__graph.dot | 8 + ...tCatch_1_1TestCaseInfo__inherit__graph.md5 | 1 + ...RTSim_1_1TaskNotActive__inherit__graph.dot | 8 + ...RTSim_1_1TaskNotActive__inherit__graph.md5 | 1 + .../d33/classRTSim_1_1Grub__coll__graph.dot | 30 + .../d33/classRTSim_1_1Grub__coll__graph.md5 | 1 + .../classCatch_1_1ExpressionDecomposer.tex | 16 + latex/df/d39/classRTSim_1_1EndDispatchEvt.tex | 26 + .../classRTSim_1_1SavedPower__coll__graph.dot | 19 + .../classRTSim_1_1SavedPower__coll__graph.md5 | 1 + .../classRTSim_1_1RTKernel__coll__graph.dot | 40 + .../classRTSim_1_1RTKernel__coll__graph.md5 | 1 + latex/df/d47/classRTSim_1_1FPScheduler.tex | 113 + ...TSim_1_1FCFSResManager__inherit__graph.dot | 10 + ...TSim_1_1FCFSResManager__inherit__graph.md5 | 1 + ...RTSim_1_1PeriodicTimer__inherit__graph.dot | 12 + ...RTSim_1_1PeriodicTimer__inherit__graph.md5 | 1 + .../structRTSim_1_1SchedRTA_1_1ServerInfo.tex | 32 + latex/df/da6/classRTSim_1_1AbstractGen.tex | 51 + .../db4/classRTSim_1_1uniformCPUFactory.tex | 32 + ...m_1_1RandomTaskSetFactory__coll__graph.dot | 28 + ...m_1_1RandomTaskSetFactory__coll__graph.md5 | 1 + ...lassRTSim_1_1SuspendInstr__coll__graph.dot | 49 + ...lassRTSim_1_1SuspendInstr__coll__graph.md5 | 1 + latex/df/ddb/structCatch_1_1TestCaseStats.tex | 35 + latex/df/ddf/structCatch_1_1IConfig.tex | 42 + latex/df/ded/classRTSim_1_1PollingServer.tex | 126 + .../dir_13e138d54eb8818da29c3992edef070a.tex | 5 + .../dir_2c1ec4cfaf5ed43ec260b4f91f837847.tex | 5 + .../dir_3c5a7878238957e7a9a8834f0b838f8b.tex | 5 + .../dir_3c5cc845447c19ce6ee25ef55a49cd4c.tex | 5 + .../dir_3f9cfe9044a0c61e52ec878e2326b5b3.tex | 5 + .../dir_4fef79e7177ba769987a8da36c892c5f.tex | 5 + .../dir_55415680715be69f92249950f105c664.tex | 5 + .../dir_63772b626f2709090f0bdca0f40827b4.tex | 8 + .../dir_68267d1309a1af8e8297ef4c3efbcdba.tex | 5 + .../dir_894d12cf7c955c04db6300346317721c.tex | 5 + .../dir_a41afb44cd77021f04ef0298981be91e.tex | 5 + .../dir_a573004c1aa1ac4f8bc48460229ea7de.tex | 5 + .../dir_d28a4824dc47e487b107a5db32ef43c4.tex | 5 + .../dir_d5f87438f5d8e96cf3117079ff5b9178.tex | 5 + latex/doxygen.sty | 477 ++++ latex/hierarchy.tex | 467 ++++ latex/md_README.tex | 150 + latex/modules.tex | 4 + latex/namespaces.tex | 7 + latex/refman.tex | 447 +++ latex/todo.tex | 77 + 2621 files changed, 115926 insertions(+) create mode 100644 Doxyfile create mode 100644 html/_formulas.tex create mode 100644 html/annotated.html create mode 100644 html/arrowdown.png create mode 100644 html/arrowright.png create mode 100644 html/bc_s.png create mode 100644 html/bdwn.png create mode 100644 html/classes.html create mode 100644 html/closed.png create mode 100644 html/d0/d02/classRTSim_1_1ThreEvt.html create mode 100644 html/d0/d03/classRTSim_1_1SignalInstr__coll__graph.dot create mode 100644 html/d0/d03/classRTSim_1_1SignalInstr__coll__graph.md5 create mode 100644 html/d0/d0a/classCatch_1_1ScopedMessage.html create mode 100644 html/d0/d1a/classRTSim_1_1CPU__coll__graph.dot create mode 100644 html/d0/d1a/classRTSim_1_1CPU__coll__graph.md5 create mode 100644 html/d0/d1a/classRTSim_1_1TaskEvt__coll__graph.dot create mode 100644 html/d0/d1a/classRTSim_1_1TaskEvt__coll__graph.md5 create mode 100644 html/d0/d1b/classCatch_1_1StreamBufImpl.html create mode 100644 html/d0/d23/classCatch_1_1ValuesGenerator__inherit__graph.dot create mode 100644 html/d0/d23/classCatch_1_1ValuesGenerator__inherit__graph.md5 create mode 100644 html/d0/d27/classRTSim_1_1Interrupt.html create mode 100644 html/d0/d27/taskexc_8hpp_source.html create mode 100644 html/d0/d2f/classRTSim_1_1TraceTaskEvent.html create mode 100644 html/d0/d38/classRTSim_1_1DispatchEvt.html create mode 100644 html/d0/d38/classRTSim_1_1ResManager__inherit__graph.dot create mode 100644 html/d0/d38/classRTSim_1_1ResManager__inherit__graph.md5 create mode 100644 html/d0/d39/classRTSim_1_1AbsResManager.html create mode 100644 html/d0/d3f/classRTSim_1_1ConstCTGen__coll__graph.dot create mode 100644 html/d0/d3f/classRTSim_1_1ConstCTGen__coll__graph.md5 create mode 100644 html/d0/d40/classRTSim_1_1KernAlreadySet__inherit__graph.dot create mode 100644 html/d0/d40/classRTSim_1_1KernAlreadySet__inherit__graph.md5 create mode 100644 html/d0/d43/classRTSim_1_1EDFScheduler.html create mode 100644 html/d0/d48/classRTSim_1_1TraceDlinePostEvent__inherit__graph.dot create mode 100644 html/d0/d48/classRTSim_1_1TraceDlinePostEvent__inherit__graph.md5 create mode 100644 html/d0/d5b/classRTSim_1_1SchedEvt.html create mode 100644 html/d0/d6e/structCatch_1_1Matchers_1_1Impl_1_1MatcherImpl__inherit__graph.dot create mode 100644 html/d0/d6e/structCatch_1_1Matchers_1_1Impl_1_1MatcherImpl__inherit__graph.md5 create mode 100644 html/d0/d72/classRTSim_1_1SporadicServer__coll__graph.dot create mode 100644 html/d0/d72/classRTSim_1_1SporadicServer__coll__graph.md5 create mode 100644 html/d0/d76/classRTSim_1_1AVRTask.html create mode 100644 html/d0/d7d/classRTSim_1_1SuperCBS_1_1ChangeBudgetEvt.html create mode 100644 html/d0/d81/classRTSim_1_1UtilizationStat__coll__graph.dot create mode 100644 html/d0/d81/classRTSim_1_1UtilizationStat__coll__graph.md5 create mode 100644 html/d0/d82/structCatch_1_1ShowDurations.html create mode 100644 html/d0/d83/classRTSim_1_1SuperCBS__inherit__graph.dot create mode 100644 html/d0/d83/classRTSim_1_1SuperCBS__inherit__graph.md5 create mode 100644 html/d0/d92/classRTSim_1_1TraceEvent__inherit__graph.dot create mode 100644 html/d0/d92/classRTSim_1_1TraceEvent__inherit__graph.md5 create mode 100644 html/d0/d94/classRTSim_1_1SuperCBS__coll__graph.dot create mode 100644 html/d0/d94/classRTSim_1_1SuperCBS__coll__graph.md5 create mode 100644 html/d0/d94/classRTSim_1_1TraceWaitEvent.html create mode 100644 html/d0/d95/classRTSim_1_1SporadicDTGen.html create mode 100644 html/d0/d97/structCatch_1_1FalseType.html create mode 100644 html/d0/d9a/capacitytimer_8hpp_source.html create mode 100644 html/d0/da3/structStats.html create mode 100644 html/d0/da7/classRTSim_1_1TraceNameEvent__coll__graph.dot create mode 100644 html/d0/da7/classRTSim_1_1TraceNameEvent__coll__graph.md5 create mode 100644 html/d0/db4/classRTSim_1_1SporadicDTGen__inherit__graph.dot create mode 100644 html/d0/db4/classRTSim_1_1SporadicDTGen__inherit__graph.md5 create mode 100644 html/d0/dcc/structCatch_1_1IConfig__inherit__graph.dot create mode 100644 html/d0/dcc/structCatch_1_1IConfig__inherit__graph.md5 create mode 100644 html/d0/ddc/structCatch_1_1Matchers_1_1Impl_1_1StdString_1_1EndsWith.html create mode 100644 html/d0/dde/classRTSim_1_1ConstCTGen__inherit__graph.dot create mode 100644 html/d0/dde/classRTSim_1_1ConstCTGen__inherit__graph.md5 create mode 100644 html/d0/de3/classRTSim_1_1SchedRTA.html create mode 100644 html/d0/de4/classCatch_1_1StreamBufBase__inherit__graph.dot create mode 100644 html/d0/de4/classCatch_1_1StreamBufBase__inherit__graph.md5 create mode 100644 html/d0/def/classRTSim_1_1TardinessStat__inherit__graph.dot create mode 100644 html/d0/def/classRTSim_1_1TardinessStat__inherit__graph.md5 create mode 100644 html/d0/df5/classRTSim_1_1FPScheduler_1_1FPModel__coll__graph.dot create mode 100644 html/d0/df5/classRTSim_1_1FPScheduler_1_1FPModel__coll__graph.md5 create mode 100644 html/d0/df5/classRTSim_1_1OffsetGen__inherit__graph.dot create mode 100644 html/d0/df5/classRTSim_1_1OffsetGen__inherit__graph.md5 create mode 100644 html/d0/dfa/classCatch_1_1BetweenGenerator__coll__graph.dot create mode 100644 html/d0/dfa/classCatch_1_1BetweenGenerator__coll__graph.md5 create mode 100644 html/d0/dfd/classRTSim_1_1SchedPoint__inherit__graph.dot create mode 100644 html/d0/dfd/classRTSim_1_1SchedPoint__inherit__graph.md5 create mode 100644 html/d1/d02/classRTSim_1_1Resource__inherit__graph.dot create mode 100644 html/d1/d02/classRTSim_1_1Resource__inherit__graph.md5 create mode 100644 html/d1/d09/classCatch_1_1AssertionResult.html create mode 100644 html/d1/d0e/structCatch_1_1IShared__coll__graph.dot create mode 100644 html/d1/d0e/structCatch_1_1IShared__coll__graph.md5 create mode 100644 html/d1/d15/classCatch_1_1Config__inherit__graph.dot create mode 100644 html/d1/d15/classCatch_1_1Config__inherit__graph.md5 create mode 100644 html/d1/d19/jtrace_8hpp_source.html create mode 100644 html/d1/d1d/classRTSim_1_1ArrEvt.html create mode 100644 html/d1/d25/classRTSim_1_1DTGen__coll__graph.dot create mode 100644 html/d1/d25/classRTSim_1_1DTGen__coll__graph.md5 create mode 100644 html/d1/d27/classCatch_1_1TagParser.html create mode 100644 html/d1/d28/classRTSim_1_1InstrExc.html create mode 100644 html/d1/d33/classRTSim_1_1ThreEvt__inherit__graph.dot create mode 100644 html/d1/d33/classRTSim_1_1ThreEvt__inherit__graph.md5 create mode 100644 html/d1/d36/classRTSim_1_1FPScheduler__inherit__graph.dot create mode 100644 html/d1/d36/classRTSim_1_1FPScheduler__inherit__graph.md5 create mode 100644 html/d1/d43/classRTSim_1_1FeedbackTestModule.html create mode 100644 html/d1/d47/structCatch_1_1IGeneratorsForTest.html create mode 100644 html/d1/d4d/classRTSim_1_1TextTrace.html create mode 100644 html/d1/d4f/classRTSim_1_1GrubSupervisor__coll__graph.dot create mode 100644 html/d1/d4f/classRTSim_1_1GrubSupervisor__coll__graph.md5 create mode 100644 html/d1/d52/classRTSim_1_1FeedbackModuleARSim__inherit__graph.dot create mode 100644 html/d1/d52/classRTSim_1_1FeedbackModuleARSim__inherit__graph.md5 create mode 100644 html/d1/d55/classRTSim_1_1PollingServer__inherit__graph.dot create mode 100644 html/d1/d55/classRTSim_1_1PollingServer__inherit__graph.md5 create mode 100644 html/d1/d55/structCatch_1_1TestGroupStats.html create mode 100644 html/d1/d64/classRTSim_1_1MissPercentage.html create mode 100644 html/d1/d6d/classRTSim_1_1BeginDispatchMultiEvt.html create mode 100644 html/d1/d6e/structCatch_1_1Matchers_1_1Impl_1_1MatcherImpl.html create mode 100644 html/d1/d88/classRTSim_1_1UniformCTGen__coll__graph.dot create mode 100644 html/d1/d88/classRTSim_1_1UniformCTGen__coll__graph.md5 create mode 100644 html/d1/d8a/classRTSim_1_1TaskAlreadyExecuting__coll__graph.dot create mode 100644 html/d1/d8a/classRTSim_1_1TaskAlreadyExecuting__coll__graph.md5 create mode 100644 html/d1/d8c/classRTSim_1_1ConstIATGen.html create mode 100644 html/d1/d8e/classRTSim_1_1EndDispatchMultiEvt.html create mode 100644 html/d1/d8e/classRTSim_1_1KillEvt__coll__graph.dot create mode 100644 html/d1/d8e/classRTSim_1_1KillEvt__coll__graph.md5 create mode 100644 html/d1/d91/classCatch_1_1MethodTestCase__coll__graph.dot create mode 100644 html/d1/d91/classCatch_1_1MethodTestCase__coll__graph.md5 create mode 100644 html/d1/d96/structCatch_1_1CumulativeReporterBase_1_1Node__inherit__graph.dot create mode 100644 html/d1/d96/structCatch_1_1CumulativeReporterBase_1_1Node__inherit__graph.md5 create mode 100644 html/d1/d9d/classRTSim_1_1DlineSetEvt__inherit__graph.dot create mode 100644 html/d1/d9d/classRTSim_1_1DlineSetEvt__inherit__graph.md5 create mode 100644 html/d1/db1/classRTSim_1_1IATGen.html create mode 100644 html/d1/dbb/classRTSim_1_1TaskStatExc__coll__graph.dot create mode 100644 html/d1/dbb/classRTSim_1_1TaskStatExc__coll__graph.md5 create mode 100644 html/d1/dbb/structCatch_1_1Matchers_1_1Impl_1_1StdString_1_1StartsWith__inherit__graph.dot create mode 100644 html/d1/dbb/structCatch_1_1Matchers_1_1Impl_1_1StdString_1_1StartsWith__inherit__graph.md5 create mode 100644 html/d1/dbf/classRTSim_1_1GrubExc__coll__graph.dot create mode 100644 html/d1/dbf/classRTSim_1_1GrubExc__coll__graph.md5 create mode 100644 html/d1/dc1/structCatch_1_1IShared.html create mode 100644 html/d1/dc8/classRTSim_1_1MissCount__inherit__graph.dot create mode 100644 html/d1/dc8/classRTSim_1_1MissCount__inherit__graph.md5 create mode 100644 html/d1/dd2/classRTSim_1_1RTSchedExc__coll__graph.dot create mode 100644 html/d1/dd2/classRTSim_1_1RTSchedExc__coll__graph.md5 create mode 100644 html/d1/dd4/classRTSim_1_1SignalEvt__inherit__graph.dot create mode 100644 html/d1/dd4/classRTSim_1_1SignalEvt__inherit__graph.md5 create mode 100644 html/d1/dd8/classRTSim_1_1TardinessStat__coll__graph.dot create mode 100644 html/d1/dd8/classRTSim_1_1TardinessStat__coll__graph.md5 create mode 100644 html/d1/ddb/bwi_8hpp_source.html create mode 100644 html/d1/ddd/structCatch_1_1StringMaker__inherit__graph.dot create mode 100644 html/d1/ddd/structCatch_1_1StringMaker__inherit__graph.md5 create mode 100644 html/d1/de8/structRTSim_1_1SchedPoint_1_1points.html create mode 100644 html/d1/df2/classRTSim_1_1SchedPoint_1_1SchedPointExc.html create mode 100644 html/d1/dfa/classRTSim_1_1MinIATGen.html create mode 100644 html/d1/dff/classRTSim_1_1RTModel__inherit__graph.dot create mode 100644 html/d1/dff/classRTSim_1_1RTModel__inherit__graph.md5 create mode 100644 html/d2/d01/structCatch_1_1Totals.html create mode 100644 html/d2/d06/classRTSim_1_1InstrExc__coll__graph.dot create mode 100644 html/d2/d06/classRTSim_1_1InstrExc__coll__graph.md5 create mode 100644 html/d2/d09/classRTSim_1_1RMScheduler__coll__graph.dot create mode 100644 html/d2/d09/classRTSim_1_1RMScheduler__coll__graph.md5 create mode 100644 html/d2/d0f/classRTSim_1_1TaskNotExecuting__inherit__graph.dot create mode 100644 html/d2/d0f/classRTSim_1_1TaskNotExecuting__inherit__graph.md5 create mode 100644 html/d2/d11/structCatch_1_1IRegistryHub.html create mode 100644 html/d2/d1b/classRTSim_1_1UniformCTGen.html create mode 100644 html/d2/d2a/classRTSim_1_1FixedInstr.html create mode 100644 html/d2/d2f/classCatch_1_1MethodTestCase__inherit__graph.dot create mode 100644 html/d2/d2f/classCatch_1_1MethodTestCase__inherit__graph.md5 create mode 100644 html/d2/d38/classRTSim_1_1FixedInstr__inherit__graph.dot create mode 100644 html/d2/d38/classRTSim_1_1FixedInstr__inherit__graph.md5 create mode 100644 html/d2/d3a/fcfsresmanager_8hpp_source.html create mode 100644 html/d2/d3c/structCatch_1_1Totals__coll__graph.dot create mode 100644 html/d2/d3c/structCatch_1_1Totals__coll__graph.md5 create mode 100644 html/d2/d40/classCatch_1_1ValuesGenerator.html create mode 100644 html/d2/d46/classRTSim_1_1PeriodicTask__coll__graph.dot create mode 100644 html/d2/d46/classRTSim_1_1PeriodicTask__coll__graph.md5 create mode 100644 html/d2/d4c/classRTSim_1_1PreemptionStat__inherit__graph.dot create mode 100644 html/d2/d4c/classRTSim_1_1PreemptionStat__inherit__graph.md5 create mode 100644 html/d2/d4e/classRTSim_1_1EndDispatchEvt__coll__graph.dot create mode 100644 html/d2/d4e/classRTSim_1_1EndDispatchEvt__coll__graph.md5 create mode 100644 html/d2/d54/structCatch_1_1pluralise.html create mode 100644 html/d2/d55/classRTSim_1_1AbsTask__inherit__graph.dot create mode 100644 html/d2/d55/classRTSim_1_1AbsTask__inherit__graph.md5 create mode 100644 html/d2/d56/group__tasks.html create mode 100644 html/d2/d5b/classRTSim_1_1ConsumedPower__inherit__graph.dot create mode 100644 html/d2/d5b/classRTSim_1_1ConsumedPower__inherit__graph.md5 create mode 100644 html/d2/d60/structCatch_1_1IMutableRegistryHub.html create mode 100644 html/d2/d67/classRTSim_1_1TaskAlreadyExecuting.html create mode 100644 html/d2/d6c/classRTSim_1_1RTKernelExc__coll__graph.dot create mode 100644 html/d2/d6c/classRTSim_1_1RTKernelExc__coll__graph.md5 create mode 100644 html/d2/d70/classRTSim_1_1BWI.html create mode 100644 html/d2/d71/structCatch_1_1AssertionInfo.html create mode 100644 html/d2/d7c/classCatch_1_1TagExtracter.html create mode 100644 html/d2/d7e/classRTSim_1_1BWI__inherit__graph.dot create mode 100644 html/d2/d7e/classRTSim_1_1BWI__inherit__graph.md5 create mode 100644 html/d2/d7e/structCatch_1_1MessageBuilder.html create mode 100644 html/d2/d7f/classRTSim_1_1JSONTrace.html create mode 100644 html/d2/d82/classCatch_1_1AssertionResult__coll__graph.dot create mode 100644 html/d2/d82/classCatch_1_1AssertionResult__coll__graph.md5 create mode 100644 html/d2/d8d/classRTSim_1_1TraceArrEvent__coll__graph.dot create mode 100644 html/d2/d8d/classRTSim_1_1TraceArrEvent__coll__graph.md5 create mode 100644 html/d2/d94/rtload_8hpp_source.html create mode 100644 html/d2/d95/classRTSim_1_1TaskEvt.html create mode 100644 html/d2/da3/classRTSim_1_1UtilizationStat.html create mode 100644 html/d2/da4/classCatch_1_1Detail_1_1Approx.html create mode 100644 html/d2/da4/classRTSim_1_1MinCTGen__inherit__graph.dot create mode 100644 html/d2/da4/classRTSim_1_1MinCTGen__inherit__graph.md5 create mode 100644 html/d2/da7/classRTSim_1_1ConsumedPower__coll__graph.dot create mode 100644 html/d2/da7/classRTSim_1_1ConsumedPower__coll__graph.md5 create mode 100644 html/d2/db2/structCatch_1_1Detail_1_1StringMakerBase.html create mode 100644 html/d2/db7/classCatch_1_1Matchers_1_1Impl_1_1Generic_1_1AllOf__coll__graph.dot create mode 100644 html/d2/db7/classCatch_1_1Matchers_1_1Impl_1_1Generic_1_1AllOf__coll__graph.md5 create mode 100644 html/d2/db7/classRTSim_1_1ModeOutOfIndex.html create mode 100644 html/d2/db9/classRTSim_1_1TaskAlreadyActive.html create mode 100644 html/d2/dc0/structCatch_1_1StringMaker.html create mode 100644 html/d2/dc5/structCatch_1_1IReporterRegistry.html create mode 100644 html/d2/dc7/namespaceRTSim.html create mode 100644 html/d2/dc8/classRTSim_1_1TracePowerConsumption.html create mode 100644 html/d2/de1/classRTSim_1_1SavedPower.html create mode 100644 html/d2/de6/classCatch_1_1ExpressionLhs.html create mode 100644 html/d2/dec/classCatch_1_1Matchers_1_1Impl_1_1Generic_1_1AnyOf__coll__graph.dot create mode 100644 html/d2/dec/classCatch_1_1Matchers_1_1Impl_1_1Generic_1_1AnyOf__coll__graph.md5 create mode 100644 html/d2/df3/classRTSim_1_1CBServer.html create mode 100644 html/d2/df9/classRTSim_1_1TraceEvent.html create mode 100644 html/d2/dfc/classRTSim_1_1ThreInstr.html create mode 100644 html/d3/d00/classRTSim_1_1Interrupt__inherit__graph.dot create mode 100644 html/d3/d00/classRTSim_1_1Interrupt__inherit__graph.md5 create mode 100644 html/d3/d03/structCatch_1_1IContext__inherit__graph.dot create mode 100644 html/d3/d03/structCatch_1_1IContext__inherit__graph.md5 create mode 100644 html/d3/d04/classRTSim_1_1AbsRTTask.html create mode 100644 html/d3/d08/structCatch_1_1StreamingReporterBase__coll__graph.dot create mode 100644 html/d3/d08/structCatch_1_1StreamingReporterBase__coll__graph.md5 create mode 100644 html/d3/d14/classRTSim_1_1PollingServer__coll__graph.dot create mode 100644 html/d3/d14/classRTSim_1_1PollingServer__coll__graph.md5 create mode 100644 html/d3/d14/structCatch_1_1IConfig__coll__graph.dot create mode 100644 html/d3/d14/structCatch_1_1IConfig__coll__graph.md5 create mode 100644 html/d3/d16/classRTSim_1_1TraceDlineSetEvent__inherit__graph.dot create mode 100644 html/d3/d16/classRTSim_1_1TraceDlineSetEvent__inherit__graph.md5 create mode 100644 html/d3/d17/classRTSim_1_1EndEvt__inherit__graph.dot create mode 100644 html/d3/d17/classRTSim_1_1EndEvt__inherit__graph.md5 create mode 100644 html/d3/d21/classRTSim_1_1FixedInstr__coll__graph.dot create mode 100644 html/d3/d21/classRTSim_1_1FixedInstr__coll__graph.md5 create mode 100644 html/d3/d26/absresmanager_8hpp_source.html create mode 100644 html/d3/d2b/classRTSim_1_1EndInstrEvt.html create mode 100644 html/d3/d2e/classRTSim_1_1SparePot_1_1SparePotExc.html create mode 100644 html/d3/d38/classRTSim_1_1GlobalPreemptionStat__inherit__graph.dot create mode 100644 html/d3/d38/classRTSim_1_1GlobalPreemptionStat__inherit__graph.md5 create mode 100644 html/d3/d43/structCatch_1_1IStreamingReporter__coll__graph.dot create mode 100644 html/d3/d43/structCatch_1_1IStreamingReporter__coll__graph.md5 create mode 100644 html/d3/d51/classRTSim_1_1GlobalPreemptionStat__coll__graph.dot create mode 100644 html/d3/d51/classRTSim_1_1GlobalPreemptionStat__coll__graph.md5 create mode 100644 html/d3/d54/classRTSim_1_1GrubSupervisor__inherit__graph.dot create mode 100644 html/d3/d54/classRTSim_1_1GrubSupervisor__inherit__graph.md5 create mode 100644 html/d3/d60/classCatch_1_1TagParser__inherit__graph.dot create mode 100644 html/d3/d60/classCatch_1_1TagParser__inherit__graph.md5 create mode 100644 html/d3/d66/classRTSim_1_1UniformIATGen.html create mode 100644 html/d3/d67/classRTSim_1_1FakeArrEvt.html create mode 100644 html/d3/d71/classRTSim_1_1ExecInstr__coll__graph.dot create mode 100644 html/d3/d71/classRTSim_1_1ExecInstr__coll__graph.md5 create mode 100644 html/d3/d73/classRTSim_1_1WrongParameterSize.html create mode 100644 html/d3/d7b/structCatch_1_1Internal_1_1Evaluator_3_01T1_00_01T2_00_01IsGreaterThanOrEqualTo_01_4.html create mode 100644 html/d3/d84/classRTSim_1_1EmptyTask__coll__graph.dot create mode 100644 html/d3/d84/classRTSim_1_1EmptyTask__coll__graph.md5 create mode 100644 html/d3/d85/classRTSim_1_1EmptyTask.html create mode 100644 html/d3/d94/classRTSim_1_1RandomRTTaskSetFactory__inherit__graph.dot create mode 100644 html/d3/d94/classRTSim_1_1RandomRTTaskSetFactory__inherit__graph.md5 create mode 100644 html/d3/d94/classRTSim_1_1TaskNotActive.html create mode 100644 html/d3/d9c/classRTSim_1_1Desc.html create mode 100644 html/d3/db5/classRTSim_1_1Server__coll__graph.dot create mode 100644 html/d3/db5/classRTSim_1_1Server__coll__graph.md5 create mode 100644 html/d3/db9/classRTSim_1_1ServerExc__coll__graph.dot create mode 100644 html/d3/db9/classRTSim_1_1ServerExc__coll__graph.md5 create mode 100644 html/d3/dbb/classRTSim_1_1SchedPoint_1_1SchedPointExc__inherit__graph.dot create mode 100644 html/d3/dbb/classRTSim_1_1SchedPoint_1_1SchedPointExc__inherit__graph.md5 create mode 100644 html/d3/dbc/classRTSim_1_1TaskModel.html create mode 100644 html/d3/dbd/classRTSim_1_1ConsumedPower.html create mode 100644 html/d3/dc9/classRTSim_1_1AbstractGen__coll__graph.dot create mode 100644 html/d3/dc9/classRTSim_1_1AbstractGen__coll__graph.md5 create mode 100644 html/d3/dd3/classRTSim_1_1GlobalPreemptionStat.html create mode 100644 html/d3/ddf/structCatch_1_1Detail_1_1BorgType.html create mode 100644 html/d3/de3/mrtkernel_8hpp_source.html create mode 100644 html/d3/de7/rttask_8hpp_source.html create mode 100644 html/d3/deb/classRTSim_1_1NoSuchInstr.html create mode 100644 html/d3/df1/classRTSim_1_1PreemptionStat.html create mode 100644 html/d3/df3/classRTSim_1_1SchedInstr__coll__graph.dot create mode 100644 html/d3/df3/classRTSim_1_1SchedInstr__coll__graph.md5 create mode 100644 html/d3/dfc/classRTSim_1_1DlineEquPeriodDTGen__coll__graph.dot create mode 100644 html/d3/dfc/classRTSim_1_1DlineEquPeriodDTGen__coll__graph.md5 create mode 100644 html/d4/d00/classRTSim_1_1MissCount.html create mode 100644 html/d4/d17/structCatch_1_1IContext.html create mode 100644 html/d4/d18/sparepot_8hpp_source.html create mode 100644 html/d4/d24/classRTSim_1_1uniformCPUFactory__inherit__graph.dot create mode 100644 html/d4/d24/classRTSim_1_1uniformCPUFactory__inherit__graph.md5 create mode 100644 html/d4/d2b/classRTSim_1_1RTKernel__inherit__graph.dot create mode 100644 html/d4/d2b/classRTSim_1_1RTKernel__inherit__graph.md5 create mode 100644 html/d4/d2e/classRTSim_1_1PeriodicTask.html create mode 100644 html/d4/d31/structCatch_1_1TestFailureException.html create mode 100644 html/d4/d34/classRTSim_1_1TraceWaitEvent__inherit__graph.dot create mode 100644 html/d4/d34/classRTSim_1_1TraceWaitEvent__inherit__graph.md5 create mode 100644 html/d4/d45/classRTSim_1_1IATGen__coll__graph.dot create mode 100644 html/d4/d45/classRTSim_1_1IATGen__coll__graph.md5 create mode 100644 html/d4/d48/classRTSim_1_1CapacityTimer__coll__graph.dot create mode 100644 html/d4/d48/classRTSim_1_1CapacityTimer__coll__graph.md5 create mode 100644 html/d4/d4d/classRTSim_1_1Instr__inherit__graph.dot create mode 100644 html/d4/d4d/classRTSim_1_1Instr__inherit__graph.md5 create mode 100644 html/d4/d57/classRTSim_1_1FakeArrEvt__inherit__graph.dot create mode 100644 html/d4/d57/classRTSim_1_1FakeArrEvt__inherit__graph.md5 create mode 100644 html/d4/d61/classRTSim_1_1GrubSupervisor.html create mode 100644 html/d4/d63/classCatch_1_1Stream.html create mode 100644 html/d4/d68/classRTSim_1_1Timer.html create mode 100644 html/d4/d6b/classRTSim_1_1JavaTrace.html create mode 100644 html/d4/d7e/structCatch_1_1SectionInfo.html create mode 100644 html/d4/d84/classRTSim_1_1TaskAlreadyActive__coll__graph.dot create mode 100644 html/d4/d84/classRTSim_1_1TaskAlreadyActive__coll__graph.md5 create mode 100644 html/d4/d90/classRTSim_1_1absCPUFactory.html create mode 100644 html/d4/d98/classRTSim_1_1MinCTGen.html create mode 100644 html/d4/da7/classRTSim_1_1AbstractFeedbackModule__coll__graph.dot create mode 100644 html/d4/da7/classRTSim_1_1AbstractFeedbackModule__coll__graph.md5 create mode 100644 html/d4/db3/classRTSim_1_1AbsKernel__inherit__graph.dot create mode 100644 html/d4/db3/classRTSim_1_1AbsKernel__inherit__graph.md5 create mode 100644 html/d4/dba/classRTSim_1_1AbsRTTask__inherit__graph.dot create mode 100644 html/d4/dba/classRTSim_1_1AbsRTTask__inherit__graph.md5 create mode 100644 html/d4/dc3/classRTSim_1_1Interrupt__coll__graph.dot create mode 100644 html/d4/dc3/classRTSim_1_1Interrupt__coll__graph.md5 create mode 100644 html/d4/dc4/classRTSim_1_1SignalInstr.html create mode 100644 html/d4/dcf/classRTSim_1_1WaitEvt__coll__graph.dot create mode 100644 html/d4/dcf/classRTSim_1_1WaitEvt__coll__graph.md5 create mode 100644 html/d4/dd2/classCatch_1_1StreamBufImpl__inherit__graph.dot create mode 100644 html/d4/dd2/classCatch_1_1StreamBufImpl__inherit__graph.md5 create mode 100644 html/d4/dde/classRTSim_1_1CapacityTimer.html create mode 100644 html/d4/de1/classRTSim_1_1Server.html create mode 100644 html/d4/de6/structCatch_1_1IGenerator__inherit__graph.dot create mode 100644 html/d4/de6/structCatch_1_1IGenerator__inherit__graph.md5 create mode 100644 html/d4/dec/structCatch_1_1IGeneratorInfo.html create mode 100644 html/d4/dfb/feedbacktest_8hpp_source.html create mode 100644 html/d4/dfd/classRTSim_1_1SporadicServer__inherit__graph.dot create mode 100644 html/d4/dfd/classRTSim_1_1SporadicServer__inherit__graph.md5 create mode 100644 html/d5/d02/taskevt_8hpp_source.html create mode 100644 html/d5/d05/classRTSim_1_1ConstCTGen.html create mode 100644 html/d5/d07/classRTSim_1_1EDFModel__coll__graph.dot create mode 100644 html/d5/d07/classRTSim_1_1EDFModel__coll__graph.md5 create mode 100644 html/d5/d09/classRTSim_1_1TraceDlineMissEvent__coll__graph.dot create mode 100644 html/d5/d09/classRTSim_1_1TraceDlineMissEvent__coll__graph.md5 create mode 100644 html/d5/d0e/classRTSim_1_1FinishingTimeStat__inherit__graph.dot create mode 100644 html/d5/d0e/classRTSim_1_1FinishingTimeStat__inherit__graph.md5 create mode 100644 html/d5/d13/classRTSim_1_1SparePot.html create mode 100644 html/d5/d16/classRTSim_1_1WaitInstr__inherit__graph.dot create mode 100644 html/d5/d16/classRTSim_1_1WaitInstr__inherit__graph.md5 create mode 100644 html/d5/d1b/classRTSim_1_1FIFOScheduler__inherit__graph.dot create mode 100644 html/d5/d1b/classRTSim_1_1FIFOScheduler__inherit__graph.md5 create mode 100644 html/d5/d1d/structCatch_1_1Internal_1_1Evaluator_3_01T1_00_01T2_00_01IsEqualTo_01_4.html create mode 100644 html/d5/d1e/classRTSim_1_1SparePot__coll__graph.dot create mode 100644 html/d5/d1e/classRTSim_1_1SparePot__coll__graph.md5 create mode 100644 html/d5/d2f/classRTSim_1_1TaskModel_1_1TaskModelCmp.html create mode 100644 html/d5/d30/classCatch_1_1TagExpressionParser__coll__graph.dot create mode 100644 html/d5/d30/classCatch_1_1TagExpressionParser__coll__graph.md5 create mode 100644 html/d5/d30/texttrace_8hpp_source.html create mode 100644 html/d5/d38/classRTSim_1_1BeginDispatchEvt__inherit__graph.dot create mode 100644 html/d5/d38/classRTSim_1_1BeginDispatchEvt__inherit__graph.md5 create mode 100644 html/d5/d3f/classRTSim_1_1TaskStatExc.html create mode 100644 html/d5/d42/classRTSim_1_1KillEvt.html create mode 100644 html/d5/d44/classRTSim_1_1DispatchEvt__inherit__graph.dot create mode 100644 html/d5/d44/classRTSim_1_1DispatchEvt__inherit__graph.md5 create mode 100644 html/d5/d49/classRTSim_1_1NoSuchInstr__coll__graph.dot create mode 100644 html/d5/d49/classRTSim_1_1NoSuchInstr__coll__graph.md5 create mode 100644 html/d5/d51/classRTSim_1_1Scheduler__inherit__graph.dot create mode 100644 html/d5/d51/classRTSim_1_1Scheduler__inherit__graph.md5 create mode 100644 html/d5/d51/structCatch_1_1AssertionInfo__coll__graph.dot create mode 100644 html/d5/d51/structCatch_1_1AssertionInfo__coll__graph.md5 create mode 100644 html/d5/d5a/classRTSim_1_1TaskNotExecuting__coll__graph.dot create mode 100644 html/d5/d5a/classRTSim_1_1TaskNotExecuting__coll__graph.md5 create mode 100644 html/d5/d62/classRTSim_1_1OffsetGen.html create mode 100644 html/d5/d67/classRTSim_1_1UniformIATGen__coll__graph.dot create mode 100644 html/d5/d67/classRTSim_1_1UniformIATGen__coll__graph.md5 create mode 100644 html/d5/d6e/classRTSim_1_1DeschedEvt__coll__graph.dot create mode 100644 html/d5/d6e/classRTSim_1_1DeschedEvt__coll__graph.md5 create mode 100644 html/d5/d7b/classRTSim_1_1SignalInstr__inherit__graph.dot create mode 100644 html/d5/d7b/classRTSim_1_1SignalInstr__inherit__graph.md5 create mode 100644 html/d5/d7c/tracepower_8hpp_source.html create mode 100644 html/d5/d7d/classRTSim_1_1SchedPoint_1_1ChangeBudgetEvt.html create mode 100644 html/d5/d82/classRTSim_1_1CTGen__inherit__graph.dot create mode 100644 html/d5/d82/classRTSim_1_1CTGen__inherit__graph.md5 create mode 100644 html/d5/d8c/structCatch_1_1ResultWas.html create mode 100644 html/d5/d90/classCatch_1_1NotImplementedException__coll__graph.dot create mode 100644 html/d5/d90/classCatch_1_1NotImplementedException__coll__graph.md5 create mode 100644 html/d5/d90/classRTSim_1_1CBServer__coll__graph.dot create mode 100644 html/d5/d90/classRTSim_1_1CBServer__coll__graph.md5 create mode 100644 html/d5/d94/structCatch_1_1NameAndDesc.html create mode 100644 html/d5/d99/classRTSim_1_1Supervisor.html create mode 100644 html/d5/da2/schedrta_8hpp_source.html create mode 100644 html/d5/dae/classRTSim_1_1FCFSResManager__coll__graph.dot create mode 100644 html/d5/dae/classRTSim_1_1FCFSResManager__coll__graph.md5 create mode 100644 html/d5/dba/classCatch_1_1Option__inherit__graph.dot create mode 100644 html/d5/dba/classCatch_1_1Option__inherit__graph.md5 create mode 100644 html/d5/dbb/classCatch_1_1TestCaseFilter.html create mode 100644 html/d5/dc3/classCatch_1_1TestCaseFilters.html create mode 100644 html/d5/dc7/resource_8hpp_source.html create mode 100644 html/d5/dca/classRTSim_1_1BeginDispatchMultiEvt__inherit__graph.dot create mode 100644 html/d5/dca/classRTSim_1_1BeginDispatchMultiEvt__inherit__graph.md5 create mode 100644 html/d5/dd4/classRTSim_1_1TraceDeschedEvent__inherit__graph.dot create mode 100644 html/d5/dd4/classRTSim_1_1TraceDeschedEvent__inherit__graph.md5 create mode 100644 html/d5/dd6/classCatch_1_1ValuesGenerator__coll__graph.dot create mode 100644 html/d5/dd6/classCatch_1_1ValuesGenerator__coll__graph.md5 create mode 100644 html/d5/de2/structCatch_1_1LazyStat__coll__graph.dot create mode 100644 html/d5/de2/structCatch_1_1LazyStat__coll__graph.md5 create mode 100644 html/d5/de5/classCatch_1_1ScopedMessage__coll__graph.dot create mode 100644 html/d5/de5/classCatch_1_1ScopedMessage__coll__graph.md5 create mode 100644 html/d5/dec/classRTSim_1_1RandomRTTaskSetFactory__coll__graph.dot create mode 100644 html/d5/dec/classRTSim_1_1RandomRTTaskSetFactory__coll__graph.md5 create mode 100644 html/d5/dec/rtsched_8hpp_source.html create mode 100644 html/d5/dee/structCatch_1_1IStreamingReporter.html create mode 100644 html/d5/df7/classRTSim_1_1BeginDispatchMultiEvt__coll__graph.dot create mode 100644 html/d5/df7/classRTSim_1_1BeginDispatchMultiEvt__coll__graph.md5 create mode 100644 html/d5/df7/structCatch_1_1IShared__inherit__graph.dot create mode 100644 html/d5/df7/structCatch_1_1IShared__inherit__graph.md5 create mode 100644 html/d5/dfc/structCatch_1_1IReporter__coll__graph.dot create mode 100644 html/d5/dfc/structCatch_1_1IReporter__coll__graph.md5 create mode 100644 html/d6/d0e/structCatch_1_1IRunner.html create mode 100644 html/d6/d13/classRTSim_1_1TraceDlineMissEvent.html create mode 100644 html/d6/d17/classRTSim_1_1TracePowerConsumption__inherit__graph.dot create mode 100644 html/d6/d17/classRTSim_1_1TracePowerConsumption__inherit__graph.md5 create mode 100644 html/d6/d1b/structCatch_1_1AssertionStats__coll__graph.dot create mode 100644 html/d6/d1b/structCatch_1_1AssertionStats__coll__graph.md5 create mode 100644 html/d6/d1f/structCatch_1_1IMutableContext__inherit__graph.dot create mode 100644 html/d6/d1f/structCatch_1_1IMutableContext__inherit__graph.md5 create mode 100644 html/d6/d22/classRTSim_1_1CTGen.html create mode 100644 html/d6/d24/classRTSim_1_1RRScheduler.html create mode 100644 html/d6/d25/structCatch_1_1Matchers_1_1Impl_1_1StdString_1_1EndsWith__inherit__graph.dot create mode 100644 html/d6/d25/structCatch_1_1Matchers_1_1Impl_1_1StdString_1_1EndsWith__inherit__graph.md5 create mode 100644 html/d6/d27/structCatch_1_1TestRunStats.html create mode 100644 html/d6/d38/structCatch_1_1ITestCase__inherit__graph.dot create mode 100644 html/d6/d38/structCatch_1_1ITestCase__inherit__graph.md5 create mode 100644 html/d6/d38/structCatch_1_1StringMaker_3_01T_01_5_01_4.html create mode 100644 html/d6/d40/classRTSim_1_1DispatchEvt__coll__graph.dot create mode 100644 html/d6/d40/classRTSim_1_1DispatchEvt__coll__graph.md5 create mode 100644 html/d6/d45/structCatch_1_1Matchers_1_1Impl_1_1StdString_1_1Contains__coll__graph.dot create mode 100644 html/d6/d45/structCatch_1_1Matchers_1_1Impl_1_1StdString_1_1Contains__coll__graph.md5 create mode 100644 html/d6/d46/classRTSim_1_1TardinessStat.html create mode 100644 html/d6/d48/classRTSim_1_1FinishingTimeStat__coll__graph.dot create mode 100644 html/d6/d48/classRTSim_1_1FinishingTimeStat__coll__graph.md5 create mode 100644 html/d6/d51/classRTSim_1_1MissCount__coll__graph.dot create mode 100644 html/d6/d51/classRTSim_1_1MissCount__coll__graph.md5 create mode 100644 html/d6/d60/classRTSim_1_1KernAlreadySet__coll__graph.dot create mode 100644 html/d6/d60/classRTSim_1_1KernAlreadySet__coll__graph.md5 create mode 100644 html/d6/d6a/classRTSim_1_1SchedRTA__coll__graph.dot create mode 100644 html/d6/d6a/classRTSim_1_1SchedRTA__coll__graph.md5 create mode 100644 html/d6/d6d/classCatch_1_1TagSet.html create mode 100644 html/d6/d6d/classRTSim_1_1WrongParameterSize__inherit__graph.dot create mode 100644 html/d6/d6d/classRTSim_1_1WrongParameterSize__inherit__graph.md5 create mode 100644 html/d6/d6e/structCatch_1_1IResultCapture.html create mode 100644 html/d6/d78/pollingserver_8hpp_source.html create mode 100644 html/d6/d7c/classRTSim_1_1Timer__coll__graph.dot create mode 100644 html/d6/d7c/classRTSim_1_1Timer__coll__graph.md5 create mode 100644 html/d6/d85/structCatch_1_1Matchers_1_1Impl_1_1StdString_1_1StartsWith__coll__graph.dot create mode 100644 html/d6/d85/structCatch_1_1Matchers_1_1Impl_1_1StdString_1_1StartsWith__coll__graph.md5 create mode 100644 html/d6/d8a/structCatch_1_1Internal_1_1OperatorTraits_3_01IsLessThanOrEqualTo_01_4.html create mode 100644 html/d6/d8d/classRTSim_1_1SuspendInstr.html create mode 100644 html/d6/d8f/classRTSim_1_1BeginDispatchEvt.html create mode 100644 html/d6/d90/classSystem__coll__graph.dot create mode 100644 html/d6/d90/classSystem__coll__graph.md5 create mode 100644 html/d6/d99/classCatch_1_1CompositeGenerator.html create mode 100644 html/d6/d9d/classRTSim_1_1Scheduler.html create mode 100644 html/d6/da9/classRTSim_1_1RandomRTTaskSetFactory.html create mode 100644 html/d6/dab/classRTSim_1_1SchedIEvt__coll__graph.dot create mode 100644 html/d6/dab/classRTSim_1_1SchedIEvt__coll__graph.md5 create mode 100644 html/d6/dac/classCatch_1_1TagExtracter__coll__graph.dot create mode 100644 html/d6/dac/classCatch_1_1TagExtracter__coll__graph.md5 create mode 100644 html/d6/db2/classRTSim_1_1ArrEvt__inherit__graph.dot create mode 100644 html/d6/db2/classRTSim_1_1ArrEvt__inherit__graph.md5 create mode 100644 html/d6/db2/classRTSim_1_1SchedEvt__inherit__graph.dot create mode 100644 html/d6/db2/classRTSim_1_1SchedEvt__inherit__graph.md5 create mode 100644 html/d6/dc4/structStats__coll__graph.dot create mode 100644 html/d6/dc4/structStats__coll__graph.md5 create mode 100644 html/d6/dc5/classRTSim_1_1Timer__inherit__graph.dot create mode 100644 html/d6/dc5/classRTSim_1_1Timer__inherit__graph.md5 create mode 100644 html/d6/dc8/abstask_8hpp_source.html create mode 100644 html/d6/dc8/structCatch_1_1ITestCaseRegistry.html create mode 100644 html/d6/dcd/classCatch_1_1Matchers_1_1Impl_1_1Generic_1_1AnyOf.html create mode 100644 html/d6/dd4/classRTSim_1_1TraceWaitEvent__coll__graph.dot create mode 100644 html/d6/dd4/classRTSim_1_1TraceWaitEvent__coll__graph.md5 create mode 100644 html/d6/ddb/classCatch_1_1StreamBufBase__coll__graph.dot create mode 100644 html/d6/ddb/classCatch_1_1StreamBufBase__coll__graph.md5 create mode 100644 html/d6/ddb/structCatch_1_1CumulativeReporterBase_1_1SectionNode__coll__graph.dot create mode 100644 html/d6/ddb/structCatch_1_1CumulativeReporterBase_1_1SectionNode__coll__graph.md5 create mode 100644 html/d6/ddc/classRTSim_1_1TraceDeschedEvent__coll__graph.dot create mode 100644 html/d6/ddc/classRTSim_1_1TraceDeschedEvent__coll__graph.md5 create mode 100644 html/d6/de8/scheduler_8hpp_source.html create mode 100644 html/d6/de9/schedpoints_8hpp_source.html create mode 100644 html/d6/deb/feedbackarsim_8hpp_source.html create mode 100644 html/d6/df1/classRTSim_1_1Resource__coll__graph.dot create mode 100644 html/d6/df1/classRTSim_1_1Resource__coll__graph.md5 create mode 100644 html/d6/df4/classCatch_1_1TestCase.html create mode 100644 html/d6/df4/structRTSim_1_1SparePot_1_1server__struct__coll__graph.dot create mode 100644 html/d6/df4/structRTSim_1_1SparePot_1_1server__struct__coll__graph.md5 create mode 100644 html/d7/d04/classRTSim_1_1SparePot_1_1ChangeBudgetEvt__coll__graph.dot create mode 100644 html/d7/d04/classRTSim_1_1SparePot_1_1ChangeBudgetEvt__coll__graph.md5 create mode 100644 html/d7/d07/classRTSim_1_1RandomTaskSetFactory_1_1Exc__coll__graph.dot create mode 100644 html/d7/d07/classRTSim_1_1RandomTaskSetFactory_1_1Exc__coll__graph.md5 create mode 100644 html/d7/d14/classRTSim_1_1TraceDlineMissEvent__inherit__graph.dot create mode 100644 html/d7/d14/classRTSim_1_1TraceDlineMissEvent__inherit__graph.md5 create mode 100644 html/d7/d15/classRTSim_1_1TraceDeschedEvent.html create mode 100644 html/d7/d1a/classRTSim_1_1TraceDlineSetEvent.html create mode 100644 html/d7/d29/classRTSim_1_1EndEvt__coll__graph.dot create mode 100644 html/d7/d29/classRTSim_1_1EndEvt__coll__graph.md5 create mode 100644 html/d7/d2c/classCatch_1_1TagExpressionParser.html create mode 100644 html/d7/d37/structCatch_1_1MessageInfo.html create mode 100644 html/d7/d38/structCatch_1_1CumulativeReporterBase__coll__graph.dot create mode 100644 html/d7/d38/structCatch_1_1CumulativeReporterBase__coll__graph.md5 create mode 100644 html/d7/d3c/structCatch_1_1Detail_1_1StringMakerBase_3_01true_01_4.html create mode 100644 html/d7/d3d/classRTSim_1_1TraceArrEvent.html create mode 100644 html/d7/d3d/structCatch_1_1GroupInfo.html create mode 100644 html/d7/d43/classRTSim_1_1TraceSignalEvent.html create mode 100644 html/d7/d43/waitinstr_8hpp_source.html create mode 100644 html/d7/d49/classRTSim_1_1SparePot_1_1SparePotExc__coll__graph.dot create mode 100644 html/d7/d49/classRTSim_1_1SparePot_1_1SparePotExc__coll__graph.md5 create mode 100644 html/d7/d58/classRTSim_1_1TraceNameEvent.html create mode 100644 html/d7/d5e/classRTSim_1_1DTGen__inherit__graph.dot create mode 100644 html/d7/d5e/classRTSim_1_1DTGen__inherit__graph.md5 create mode 100644 html/d7/d67/classRTSim_1_1MaxIATGen.html create mode 100644 html/d7/d69/classRTSim_1_1SchedPoint.html create mode 100644 html/d7/d76/classRTSim_1_1FeedbackModuleARSim__coll__graph.dot create mode 100644 html/d7/d76/classRTSim_1_1FeedbackModuleARSim__coll__graph.md5 create mode 100644 html/d7/d82/structCatch_1_1TestGroupStats__coll__graph.dot create mode 100644 html/d7/d82/structCatch_1_1TestGroupStats__coll__graph.md5 create mode 100644 html/d7/d83/classRTSim_1_1UtilizationStat__inherit__graph.dot create mode 100644 html/d7/d83/classRTSim_1_1UtilizationStat__inherit__graph.md5 create mode 100644 html/d7/d91/structCatch_1_1IExceptionTranslatorRegistry.html create mode 100644 html/d7/d91/structCatch_1_1SharedImpl.html create mode 100644 html/d7/d98/structCatch_1_1SectionStats__coll__graph.dot create mode 100644 html/d7/d98/structCatch_1_1SectionStats__coll__graph.md5 create mode 100644 html/d7/d9c/classRTSim_1_1RRScheduler_1_1RRModel__coll__graph.dot create mode 100644 html/d7/d9c/classRTSim_1_1RRScheduler_1_1RRModel__coll__graph.md5 create mode 100644 html/d7/da2/structCatch_1_1Matchers_1_1Impl_1_1StdString_1_1Contains__inherit__graph.dot create mode 100644 html/d7/da2/structCatch_1_1Matchers_1_1Impl_1_1StdString_1_1Contains__inherit__graph.md5 create mode 100644 html/d7/da4/structCatch_1_1CumulativeReporterBase_1_1SectionNode.html create mode 100644 html/d7/dad/structCatch_1_1ReporterPreferences.html create mode 100644 html/d7/dc0/classRTSim_1_1EDFModel__inherit__graph.dot create mode 100644 html/d7/dc0/classRTSim_1_1EDFModel__inherit__graph.md5 create mode 100644 html/d7/dc7/classCatch_1_1Option.html create mode 100644 html/d7/dca/rmsched_8hpp_source.html create mode 100644 html/d7/dcf/classRTSim_1_1ConstIATGen__inherit__graph.dot create mode 100644 html/d7/dcf/classRTSim_1_1ConstIATGen__inherit__graph.md5 create mode 100644 html/d7/dd1/classRTSim_1_1RRScheduler_1_1RRSchedExc.html create mode 100644 html/d7/dda/classRTSim_1_1RandomDTGen__coll__graph.dot create mode 100644 html/d7/dda/classRTSim_1_1RandomDTGen__coll__graph.md5 create mode 100644 html/d7/ddc/structCatch_1_1AssertionResultData.html create mode 100644 html/d7/ddc/structCatch_1_1IReporter__inherit__graph.dot create mode 100644 html/d7/ddc/structCatch_1_1IReporter__inherit__graph.md5 create mode 100644 html/d7/de7/structCatch_1_1IStreamingReporter__inherit__graph.dot create mode 100644 html/d7/de7/structCatch_1_1IStreamingReporter__inherit__graph.md5 create mode 100644 html/d7/df3/classCatch_1_1Matchers_1_1Impl_1_1Generic_1_1AllOf__inherit__graph.dot create mode 100644 html/d7/df3/classCatch_1_1Matchers_1_1Impl_1_1Generic_1_1AllOf__inherit__graph.md5 create mode 100644 html/d7/dfd/classCatch_1_1ExceptionTranslatorRegistrar.html create mode 100644 html/d7/dfe/classCatch_1_1TagExpression.html create mode 100644 html/d7/dff/structCatch_1_1Matchers_1_1Impl_1_1StdString_1_1Equals__inherit__graph.dot create mode 100644 html/d7/dff/structCatch_1_1Matchers_1_1Impl_1_1StdString_1_1Equals__inherit__graph.md5 create mode 100644 html/d8/d0b/classRTSim_1_1MinCTGen__coll__graph.dot create mode 100644 html/d8/d0b/classRTSim_1_1MinCTGen__coll__graph.md5 create mode 100644 html/d8/d11/json__trace_8hpp_source.html create mode 100644 html/d8/d12/classRTSim_1_1DlineSetEvt__coll__graph.dot create mode 100644 html/d8/d12/classRTSim_1_1DlineSetEvt__coll__graph.md5 create mode 100644 html/d8/d18/classCatch_1_1StreamBufImpl__coll__graph.dot create mode 100644 html/d8/d18/classCatch_1_1StreamBufImpl__coll__graph.md5 create mode 100644 html/d8/d1e/classRTSim_1_1SporadicServer.html create mode 100644 html/d8/d20/classRTSim_1_1WrongParameterSize__coll__graph.dot create mode 100644 html/d8/d20/classRTSim_1_1WrongParameterSize__coll__graph.md5 create mode 100644 html/d8/d30/structRTSim_1_1SchedRTA_1_1ServerInfo__coll__graph.dot create mode 100644 html/d8/d30/structRTSim_1_1SchedRTA_1_1ServerInfo__coll__graph.md5 create mode 100644 html/d8/d38/classCatch_1_1Matchers_1_1Impl_1_1Generic_1_1AnyOf__inherit__graph.dot create mode 100644 html/d8/d38/classCatch_1_1Matchers_1_1Impl_1_1Generic_1_1AnyOf__inherit__graph.md5 create mode 100644 html/d8/d3a/classRTSim_1_1Resource.html create mode 100644 html/d8/d44/classCatch_1_1Timer.html create mode 100644 html/d8/d44/classRTSim_1_1FCFSResManager.html create mode 100644 html/d8/d44/classRTSim_1_1Instr__coll__graph.dot create mode 100644 html/d8/d44/classRTSim_1_1Instr__coll__graph.md5 create mode 100644 html/d8/d4c/rrsched_8hpp_source.html create mode 100644 html/d8/d57/structCatch_1_1TestRunStats__coll__graph.dot create mode 100644 html/d8/d57/structCatch_1_1TestRunStats__coll__graph.md5 create mode 100644 html/d8/d59/structRTSim_1_1cpulevel.html create mode 100644 html/d8/d5b/classRTSim_1_1SporadicDTGen__coll__graph.dot create mode 100644 html/d8/d5b/classRTSim_1_1SporadicDTGen__coll__graph.md5 create mode 100644 html/d8/d60/kernevt_8hpp_source.html create mode 100644 html/d8/d62/structCatch_1_1ResultDisposition.html create mode 100644 html/d8/d7e/classCatch_1_1NotImplementedException__inherit__graph.dot create mode 100644 html/d8/d7e/classCatch_1_1NotImplementedException__inherit__graph.md5 create mode 100644 html/d8/d7e/classRTSim_1_1DeadEvt.html create mode 100644 html/d8/d82/structCatch_1_1Matchers_1_1Impl_1_1StdString_1_1Equals__coll__graph.dot create mode 100644 html/d8/d82/structCatch_1_1Matchers_1_1Impl_1_1StdString_1_1Equals__coll__graph.md5 create mode 100644 html/d8/d86/classRTSim_1_1TaskModel__inherit__graph.dot create mode 100644 html/d8/d86/classRTSim_1_1TaskModel__inherit__graph.md5 create mode 100644 html/d8/d8d/structCatch_1_1CumulativeReporterBase_1_1SectionNode__inherit__graph.dot create mode 100644 html/d8/d8d/structCatch_1_1CumulativeReporterBase_1_1SectionNode__inherit__graph.md5 create mode 100644 html/d8/d95/classRTSim_1_1ConstIATGen__coll__graph.dot create mode 100644 html/d8/d95/classRTSim_1_1ConstIATGen__coll__graph.md5 create mode 100644 html/d8/d99/classRTSim_1_1BeginDispatchEvt__coll__graph.dot create mode 100644 html/d8/d99/classRTSim_1_1BeginDispatchEvt__coll__graph.md5 create mode 100644 html/d8/da0/classRTSim_1_1TraceEndEvent.html create mode 100644 html/d8/da1/task_8hpp_source.html create mode 100644 html/d8/da2/classRTSim_1_1TraceArrEvent__inherit__graph.dot create mode 100644 html/d8/da2/classRTSim_1_1TraceArrEvent__inherit__graph.md5 create mode 100644 html/d8/db0/classRTSim_1_1Task.html create mode 100644 html/d8/db2/classRTSim_1_1FPScheduler_1_1FPModel__inherit__graph.dot create mode 100644 html/d8/db2/classRTSim_1_1FPScheduler_1_1FPModel__inherit__graph.md5 create mode 100644 html/d8/db5/classRTSim_1_1absCPUFactory__inherit__graph.dot create mode 100644 html/d8/db5/classRTSim_1_1absCPUFactory__inherit__graph.md5 create mode 100644 html/d8/dbd/classRTSim_1_1FeedbackModuleARSim.html create mode 100644 html/d8/dc7/structCatch_1_1Internal_1_1OperatorTraits_3_01IsLessThan_01_4.html create mode 100644 html/d8/dcd/classRTSim_1_1EndDispatchEvt__inherit__graph.dot create mode 100644 html/d8/dcd/classRTSim_1_1EndDispatchEvt__inherit__graph.md5 create mode 100644 html/d8/ddf/structCatch_1_1TestCaseInfo__coll__graph.dot create mode 100644 html/d8/ddf/structCatch_1_1TestCaseInfo__coll__graph.md5 create mode 100644 html/d8/df1/feedback_8hpp_source.html create mode 100644 html/d8/dfa/classRTSim_1_1ThreInstr__inherit__graph.dot create mode 100644 html/d8/dfa/classRTSim_1_1ThreInstr__inherit__graph.md5 create mode 100644 html/d8/dfb/classRTSim_1_1ServerExc__inherit__graph.dot create mode 100644 html/d8/dfb/classRTSim_1_1ServerExc__inherit__graph.md5 create mode 100644 html/d8/dfd/threinstr_8hpp_source.html create mode 100644 html/d9/d00/structCatch_1_1CumulativeReporterBase__inherit__graph.dot create mode 100644 html/d9/d00/structCatch_1_1CumulativeReporterBase__inherit__graph.md5 create mode 100644 html/d9/d01/classRTSim_1_1RRScheduler_1_1RRSchedExc__coll__graph.dot create mode 100644 html/d9/d01/classRTSim_1_1RRScheduler_1_1RRSchedExc__coll__graph.md5 create mode 100644 html/d9/d10/classRTSim_1_1RandomTaskSetFactory_1_1Exc__inherit__graph.dot create mode 100644 html/d9/d10/classRTSim_1_1RandomTaskSetFactory_1_1Exc__inherit__graph.md5 create mode 100644 html/d9/d11/classRTSim_1_1TraceCPUEvent.html create mode 100644 html/d9/d14/classCatch_1_1StreamBufBase.html create mode 100644 html/d9/d1c/classRTSim_1_1RandomOffsetGen.html create mode 100644 html/d9/d24/classRTSim_1_1RTModel.html create mode 100644 html/d9/d24/namespaceRTSim_1_1____sched__stub.html create mode 100644 html/d9/d25/classCatch_1_1BetweenGenerator__inherit__graph.dot create mode 100644 html/d9/d25/classCatch_1_1BetweenGenerator__inherit__graph.md5 create mode 100644 html/d9/d25/structCatch_1_1Matchers_1_1Impl_1_1Matcher__inherit__graph.dot create mode 100644 html/d9/d25/structCatch_1_1Matchers_1_1Impl_1_1Matcher__inherit__graph.md5 create mode 100644 html/d9/d29/exeinstr_8hpp_source.html create mode 100644 html/d9/d2a/classRTSim_1_1FPScheduler_1_1FPModel.html create mode 100644 html/d9/d2b/classRTSim_1_1Supervisor__inherit__graph.dot create mode 100644 html/d9/d2b/classRTSim_1_1Supervisor__inherit__graph.md5 create mode 100644 html/d9/d2d/classRTSim_1_1EndDispatchMultiEvt__coll__graph.dot create mode 100644 html/d9/d2d/classRTSim_1_1EndDispatchMultiEvt__coll__graph.md5 create mode 100644 html/d9/d2d/classRTSim_1_1TraceCPUEvent__inherit__graph.dot create mode 100644 html/d9/d2d/classRTSim_1_1TraceCPUEvent__inherit__graph.md5 create mode 100644 html/d9/d30/classRTSim_1_1SchedEvt__coll__graph.dot create mode 100644 html/d9/d30/classRTSim_1_1SchedEvt__coll__graph.md5 create mode 100644 html/d9/d31/fpsched_8hpp_source.html create mode 100644 html/d9/d36/structCatch_1_1SharedImpl__inherit__graph.dot create mode 100644 html/d9/d36/structCatch_1_1SharedImpl__inherit__graph.md5 create mode 100644 html/d9/d3b/classRTSim_1_1GrubExc__inherit__graph.dot create mode 100644 html/d9/d3b/classRTSim_1_1GrubExc__inherit__graph.md5 create mode 100644 html/d9/d47/structCatch_1_1ITestCase__coll__graph.dot create mode 100644 html/d9/d47/structCatch_1_1ITestCase__coll__graph.md5 create mode 100644 html/d9/d4c/classRTSim_1_1MinIATGen__inherit__graph.dot create mode 100644 html/d9/d4c/classRTSim_1_1MinIATGen__inherit__graph.md5 create mode 100644 html/d9/d4d/structCatch_1_1Matchers_1_1Impl_1_1StdString_1_1StartsWith.html create mode 100644 html/d9/d50/classRTSim_1_1FIFOScheduler__coll__graph.dot create mode 100644 html/d9/d50/classRTSim_1_1FIFOScheduler__coll__graph.md5 create mode 100644 html/d9/d50/classRTSim_1_1SchedPoint__coll__graph.dot create mode 100644 html/d9/d50/classRTSim_1_1SchedPoint__coll__graph.md5 create mode 100644 html/d9/d57/classRTSim_1_1TraceIdleEvent__inherit__graph.dot create mode 100644 html/d9/d57/classRTSim_1_1TraceIdleEvent__inherit__graph.md5 create mode 100644 html/d9/d57/structCatch_1_1Matchers_1_1Impl_1_1StdString_1_1Contains.html create mode 100644 html/d9/d60/classCatch_1_1TestCase__coll__graph.dot create mode 100644 html/d9/d60/classCatch_1_1TestCase__coll__graph.md5 create mode 100644 html/d9/d6f/grubserver_8hpp_source.html create mode 100644 html/d9/d74/classRTSim_1_1ModeOutOfIndex__coll__graph.dot create mode 100644 html/d9/d74/classRTSim_1_1ModeOutOfIndex__coll__graph.md5 create mode 100644 html/d9/d76/classCatch_1_1Matchers_1_1Impl_1_1Generic_1_1AllOf.html create mode 100644 html/d9/d77/classRTSim_1_1RRScheduler__inherit__graph.dot create mode 100644 html/d9/d77/classRTSim_1_1RRScheduler__inherit__graph.md5 create mode 100644 html/d9/d7e/structCatch_1_1Internal_1_1OperatorTraits_3_01IsEqualTo_01_4.html create mode 100644 html/d9/d8c/structCatch_1_1IExceptionTranslator.html create mode 100644 html/d9/d8f/structCatch_1_1Matchers_1_1Impl_1_1StdString_1_1EndsWith__coll__graph.dot create mode 100644 html/d9/d8f/structCatch_1_1Matchers_1_1Impl_1_1StdString_1_1EndsWith__coll__graph.md5 create mode 100644 html/d9/d9c/instr_8hpp_source.html create mode 100644 html/d9/da4/fifosched_8hpp_source.html create mode 100644 html/d9/daa/classRTSim_1_1SparePot_1_1ChangeBudgetEvt.html create mode 100644 html/d9/daa/classRTSim_1_1TraceIdleEvent__coll__graph.dot create mode 100644 html/d9/daa/classRTSim_1_1TraceIdleEvent__coll__graph.md5 create mode 100644 html/d9/dae/classRTSim_1_1AbsRTTask__coll__graph.dot create mode 100644 html/d9/dae/classRTSim_1_1AbsRTTask__coll__graph.md5 create mode 100644 html/d9/db1/structCatch_1_1IfFilterMatches.html create mode 100644 html/d9/db5/classCatch_1_1Internal_1_1Evaluator.html create mode 100644 html/d9/db7/classCatch_1_1NotImplementedException.html create mode 100644 html/d9/db7/classRTSim_1_1TaskAlreadyExecuting__inherit__graph.dot create mode 100644 html/d9/db7/classRTSim_1_1TaskAlreadyExecuting__inherit__graph.md5 create mode 100644 html/d9/db9/classRTSim_1_1KernAlreadySet.html create mode 100644 html/d9/dc1/classRTSim_1_1SavedPower__inherit__graph.dot create mode 100644 html/d9/dc1/classRTSim_1_1SavedPower__inherit__graph.md5 create mode 100644 html/d9/dd6/classRTSim_1_1AbstractFeedbackModule.html create mode 100644 html/d9/ddd/classRTSim_1_1EndEvt.html create mode 100644 html/d9/de1/catch_8hpp_source.html create mode 100644 html/d9/de5/classCatch_1_1NonCopyable__inherit__graph.dot create mode 100644 html/d9/de5/classCatch_1_1NonCopyable__inherit__graph.md5 create mode 100644 html/d9/df1/classRTSim_1_1TaskAlreadyActive__inherit__graph.dot create mode 100644 html/d9/df1/classRTSim_1_1TaskAlreadyActive__inherit__graph.md5 create mode 100644 html/d9/df6/classRTSim_1_1DTGen.html create mode 100644 html/da/d06/classRTSim_1_1SuperCBS.html create mode 100644 html/da/d0b/classRTSim_1_1BWI__coll__graph.dot create mode 100644 html/da/d0b/classRTSim_1_1BWI__coll__graph.md5 create mode 100644 html/da/d0c/classRTSim_1_1InstrExc__inherit__graph.dot create mode 100644 html/da/d0c/classRTSim_1_1InstrExc__inherit__graph.md5 create mode 100644 html/da/d10/classCatch_1_1Section.html create mode 100644 html/da/d10/classRTSim_1_1MissPercentage__inherit__graph.dot create mode 100644 html/da/d10/classRTSim_1_1MissPercentage__inherit__graph.md5 create mode 100644 html/da/d14/classCatch_1_1Tag.html create mode 100644 html/da/d14/classRTSim_1_1CPU__inherit__graph.dot create mode 100644 html/da/d14/classRTSim_1_1CPU__inherit__graph.md5 create mode 100644 html/da/d14/structCatch_1_1Matchers_1_1Impl_1_1StdString_1_1Equals.html create mode 100644 html/da/d19/classRTSim_1_1PeriodicTimer.html create mode 100644 html/da/d24/classRTSim_1_1RandomDTGen.html create mode 100644 html/da/d27/classRTSim_1_1RTSchedExc.html create mode 100644 html/da/d3b/structCatch_1_1Internal_1_1Evaluator_3_01T1_00_01T2_00_01IsGreaterThan_01_4.html create mode 100644 html/da/d3c/structCatch_1_1Internal_1_1Evaluator_3_01T1_00_01T2_00_01IsLessThan_01_4.html create mode 100644 html/da/d3e/classRTSim_1_1RTKernel.html create mode 100644 html/da/d4b/classRTSim_1_1UniformCTGen__inherit__graph.dot create mode 100644 html/da/d4b/classRTSim_1_1UniformCTGen__inherit__graph.md5 create mode 100644 html/da/d5b/classRTSim_1_1MRTKernel__coll__graph.dot create mode 100644 html/da/d5b/classRTSim_1_1MRTKernel__coll__graph.md5 create mode 100644 html/da/d6a/AVRTask_8hpp_source.html create mode 100644 html/da/d6b/classRTSim_1_1FIFOScheduler.html create mode 100644 html/da/d6e/classRTSim_1_1RandomOffsetGen__inherit__graph.dot create mode 100644 html/da/d6e/classRTSim_1_1RandomOffsetGen__inherit__graph.md5 create mode 100644 html/da/d6f/structCatch_1_1Detail_1_1IsStreamInsertable.html create mode 100644 html/da/d76/structCatch_1_1IReporter.html create mode 100644 html/da/d80/classRTSim_1_1Server__inherit__graph.dot create mode 100644 html/da/d80/classRTSim_1_1Server__inherit__graph.md5 create mode 100644 html/da/d8a/structCatch_1_1TestRunInfo.html create mode 100644 html/da/d8b/structCatch_1_1Internal_1_1OperatorTraits_3_01IsGreaterThanOrEqualTo_01_4.html create mode 100644 html/da/d9f/classRTSim_1_1SuperCBS_1_1ChangeBudgetEvt__inherit__graph.dot create mode 100644 html/da/d9f/classRTSim_1_1SuperCBS_1_1ChangeBudgetEvt__inherit__graph.md5 create mode 100644 html/da/da4/classRTSim_1_1EDFScheduler__coll__graph.dot create mode 100644 html/da/da4/classRTSim_1_1EDFScheduler__coll__graph.md5 create mode 100644 html/da/da7/classRTSim_1_1EDFModel.html create mode 100644 html/da/dae/classRTSim_1_1MaxIATGen__coll__graph.dot create mode 100644 html/da/dae/classRTSim_1_1MaxIATGen__coll__graph.md5 create mode 100644 html/da/dba/cbserver_8hpp_source.html create mode 100644 html/da/dba/classRTSim_1_1KernelEvt__coll__graph.dot create mode 100644 html/da/dba/classRTSim_1_1KernelEvt__coll__graph.md5 create mode 100644 html/da/dc7/classRTSim_1_1EDFScheduler__inherit__graph.dot create mode 100644 html/da/dc7/classRTSim_1_1EDFScheduler__inherit__graph.md5 create mode 100644 html/da/dcb/classRTSim_1_1SuperCBS_1_1SuperCBSExc__inherit__graph.dot create mode 100644 html/da/dcb/classRTSim_1_1SuperCBS_1_1SuperCBSExc__inherit__graph.md5 create mode 100644 html/da/dcb/structCatch_1_1TrueType.html create mode 100644 html/da/dd2/classRTSim_1_1TraceEndEvent__coll__graph.dot create mode 100644 html/da/dd2/classRTSim_1_1TraceEndEvent__coll__graph.md5 create mode 100644 html/da/dd3/classRTSim_1_1SignalEvt.html create mode 100644 html/da/dd7/classRTSim_1_1PeriodicTask__inherit__graph.dot create mode 100644 html/da/dd7/classRTSim_1_1PeriodicTask__inherit__graph.md5 create mode 100644 html/da/dda/classRTSim_1_1SchedRTA__inherit__graph.dot create mode 100644 html/da/dda/classRTSim_1_1SchedRTA__inherit__graph.md5 create mode 100644 html/da/dda/classRTSim_1_1SuperCBS_1_1SuperCBSExc__coll__graph.dot create mode 100644 html/da/dda/classRTSim_1_1SuperCBS_1_1SuperCBSExc__coll__graph.md5 create mode 100644 html/da/deb/classRTSim_1_1RandomTaskSetFactory_1_1Exc.html create mode 100644 html/da/dff/structCatch_1_1LazyStat.html create mode 100644 html/db/d01/classRTSim_1_1WaitEvt.html create mode 100644 html/db/d04/classRTSim_1_1SchedPoint_1_1ChangeBudgetEvt__inherit__graph.dot create mode 100644 html/db/d04/classRTSim_1_1SchedPoint_1_1ChangeBudgetEvt__inherit__graph.md5 create mode 100644 html/db/d06/classRTSim_1_1RRScheduler_1_1RRModel__inherit__graph.dot create mode 100644 html/db/d06/classRTSim_1_1RRScheduler_1_1RRModel__inherit__graph.md5 create mode 100644 html/db/d06/structCatch_1_1ReporterConfig.html create mode 100644 html/db/d0a/classRTSim_1_1RMScheduler.html create mode 100644 html/db/d0d/classRTSim_1_1ThreEvt__coll__graph.dot create mode 100644 html/db/d0d/classRTSim_1_1ThreEvt__coll__graph.md5 create mode 100644 html/db/d18/classRTSim_1_1SchedPoint_1_1SchedPointExc__coll__graph.dot create mode 100644 html/db/d18/classRTSim_1_1SchedPoint_1_1SchedPointExc__coll__graph.md5 create mode 100644 html/db/d19/classRTSim_1_1RRScheduler_1_1RRModel.html create mode 100644 html/db/d30/classRTSim_1_1NoSuchInstr__inherit__graph.dot create mode 100644 html/db/d30/classRTSim_1_1NoSuchInstr__inherit__graph.md5 create mode 100644 html/db/d38/classRTSim_1_1VirtualTrace.html create mode 100644 html/db/d41/classRTSim_1_1SchedInstr__inherit__graph.dot create mode 100644 html/db/d41/classRTSim_1_1SchedInstr__inherit__graph.md5 create mode 100644 html/db/d4e/classRTSim_1_1RTModel__coll__graph.dot create mode 100644 html/db/d4e/classRTSim_1_1RTModel__coll__graph.md5 create mode 100644 html/db/d6a/classRTSim_1_1LatenessStat__coll__graph.dot create mode 100644 html/db/d6a/classRTSim_1_1LatenessStat__coll__graph.md5 create mode 100644 html/db/d71/classRTSim_1_1DeschedEvt.html create mode 100644 html/db/d7b/classCatch_1_1BetweenGenerator.html create mode 100644 html/db/d7e/structCatch_1_1LazyStat__inherit__graph.dot create mode 100644 html/db/d7e/structCatch_1_1LazyStat__inherit__graph.md5 create mode 100644 html/db/d7f/classRTSim_1_1ServerExc.html create mode 100644 html/db/d83/classRTSim_1_1TraceSignalEvent__inherit__graph.dot create mode 100644 html/db/d83/classRTSim_1_1TraceSignalEvent__inherit__graph.md5 create mode 100644 html/db/d8e/classRTSim_1_1CTGen__coll__graph.dot create mode 100644 html/db/d8e/classRTSim_1_1CTGen__coll__graph.md5 create mode 100644 html/db/d95/classRTSim_1_1MRTKernel.html create mode 100644 html/db/da4/classRTSim_1_1ExecInstr.html create mode 100644 html/db/dae/structCatch_1_1IGenerator.html create mode 100644 html/db/db8/classRTSim_1_1DlineEquPeriodDTGen.html create mode 100644 html/db/dbe/classRTSim_1_1Grub__inherit__graph.dot create mode 100644 html/db/dbe/classRTSim_1_1Grub__inherit__graph.md5 create mode 100644 html/db/dc8/structCatch_1_1Verbosity.html create mode 100644 html/db/dca/classRTSim_1_1LatenessStat__inherit__graph.dot create mode 100644 html/db/dca/classRTSim_1_1LatenessStat__inherit__graph.md5 create mode 100644 html/db/dcf/classRTSim_1_1FeedbackTestModule__inherit__graph.dot create mode 100644 html/db/dcf/classRTSim_1_1FeedbackTestModule__inherit__graph.md5 create mode 100644 html/db/dcf/structCatch_1_1AssertionStats.html create mode 100644 html/db/dd3/classRTSim_1_1ArrEvt__coll__graph.dot create mode 100644 html/db/dd3/classRTSim_1_1ArrEvt__coll__graph.md5 create mode 100644 html/db/ddf/structCatch_1_1IReporterFactory.html create mode 100644 html/db/dee/abskernel_8hpp_source.html create mode 100644 html/db/dee/classRTSim_1_1EndInstrEvt__inherit__graph.dot create mode 100644 html/db/dee/classRTSim_1_1EndInstrEvt__inherit__graph.md5 create mode 100644 html/db/dee/classRTSim_1_1SuspendInstr__inherit__graph.dot create mode 100644 html/db/dee/classRTSim_1_1SuspendInstr__inherit__graph.md5 create mode 100644 html/db/df5/classRTSim_1_1TraceTaskEvent__inherit__graph.dot create mode 100644 html/db/df5/classRTSim_1_1TraceTaskEvent__inherit__graph.md5 create mode 100644 html/db/dfe/classRTSim_1_1ExecInstr__inherit__graph.dot create mode 100644 html/db/dfe/classRTSim_1_1ExecInstr__inherit__graph.md5 create mode 100644 html/db/dfe/classRTSim_1_1PIRManager__inherit__graph.dot create mode 100644 html/db/dfe/classRTSim_1_1PIRManager__inherit__graph.md5 create mode 100644 html/dc/d00/structCatch_1_1SharedImpl__coll__graph.dot create mode 100644 html/dc/d00/structCatch_1_1SharedImpl__coll__graph.md5 create mode 100644 html/dc/d01/classRTSim_1_1RRScheduler__coll__graph.dot create mode 100644 html/dc/d01/classRTSim_1_1RRScheduler__coll__graph.md5 create mode 100644 html/dc/d02/classRTSim_1_1Task__coll__graph.dot create mode 100644 html/dc/d02/classRTSim_1_1Task__coll__graph.md5 create mode 100644 html/dc/d08/classRTSim_1_1TraceDlineSetEvent__coll__graph.dot create mode 100644 html/dc/d08/classRTSim_1_1TraceDlineSetEvent__coll__graph.md5 create mode 100644 html/dc/d0a/classRTSim_1_1FakeArrEvt__coll__graph.dot create mode 100644 html/dc/d0a/classRTSim_1_1FakeArrEvt__coll__graph.md5 create mode 100644 html/dc/d0f/classRTSim_1_1ThreInstr__coll__graph.dot create mode 100644 html/dc/d0f/classRTSim_1_1ThreInstr__coll__graph.md5 create mode 100644 html/dc/d11/classRTSim_1_1TraceSignalEvent__coll__graph.dot create mode 100644 html/dc/d11/classRTSim_1_1TraceSignalEvent__coll__graph.md5 create mode 100644 html/dc/d11/structCatch_1_1SectionStats.html create mode 100644 html/dc/d17/classRTSim_1_1KillEvt__inherit__graph.dot create mode 100644 html/dc/d17/classRTSim_1_1KillEvt__inherit__graph.md5 create mode 100644 html/dc/d17/classRTSim_1_1SchedInstr.html create mode 100644 html/dc/d1c/classCatch_1_1NonCopyable.html create mode 100644 html/dc/d1e/classRTSim_1_1EndDispatchMultiEvt__inherit__graph.dot create mode 100644 html/dc/d1e/classRTSim_1_1EndDispatchMultiEvt__inherit__graph.md5 create mode 100644 html/dc/d24/classRTSim_1_1TraceNameEvent__inherit__graph.dot create mode 100644 html/dc/d24/classRTSim_1_1TraceNameEvent__inherit__graph.md5 create mode 100644 html/dc/d28/classRTSim_1_1RTKernelExc__inherit__graph.dot create mode 100644 html/dc/d28/classRTSim_1_1RTKernelExc__inherit__graph.md5 create mode 100644 html/dc/d2b/structCatch_1_1SourceLineInfo.html create mode 100644 html/dc/d2f/taskstat_8hpp_source.html create mode 100644 html/dc/d33/classRTSim_1_1UniformIATGen__inherit__graph.dot create mode 100644 html/dc/d33/classRTSim_1_1UniformIATGen__inherit__graph.md5 create mode 100644 html/dc/d33/structCatch_1_1OutputDebugWriter.html create mode 100644 html/dc/d36/classRTSim_1_1ResManager.html create mode 100644 html/dc/d3d/namespaceRTSim_1_1____task__stub.html create mode 100644 html/dc/d4e/classRTSim_1_1TraceSchedEvent.html create mode 100644 html/dc/d54/classRTSim_1_1TraceSchedEvent__coll__graph.dot create mode 100644 html/dc/d54/classRTSim_1_1TraceSchedEvent__coll__graph.md5 create mode 100644 html/dc/d56/classRTSim_1_1MaxIATGen__inherit__graph.dot create mode 100644 html/dc/d56/classRTSim_1_1MaxIATGen__inherit__graph.md5 create mode 100644 html/dc/d58/classCatch_1_1ExpressionResultBuilder.html create mode 100644 html/dc/d59/structCatch_1_1AutoReg.html create mode 100644 html/dc/d5b/classRTSim_1_1TaskNotActive__coll__graph.dot create mode 100644 html/dc/d5b/classRTSim_1_1TaskNotActive__coll__graph.md5 create mode 100644 html/dc/d5c/structCatch_1_1IMutableContext__coll__graph.dot create mode 100644 html/dc/d5c/structCatch_1_1IMutableContext__coll__graph.md5 create mode 100644 html/dc/d5e/classRTSim_1_1WaitInstr.html create mode 100644 html/dc/d61/classRTSim_1_1RandomTaskSetFactory.html create mode 100644 html/dc/d68/classRTSim_1_1MinIATGen__coll__graph.dot create mode 100644 html/dc/d68/classRTSim_1_1MinIATGen__coll__graph.md5 create mode 100644 html/dc/d6d/structCatch_1_1Internal_1_1Evaluator_3_01T1_00_01T2_00_01IsLessThanOrEqualTo_01_4.html create mode 100644 html/dc/d72/classCatch_1_1Config.html create mode 100644 html/dc/d72/classCatch_1_1TagExtracter__inherit__graph.dot create mode 100644 html/dc/d72/classCatch_1_1TagExtracter__inherit__graph.md5 create mode 100644 html/dc/d7e/structCatch_1_1SectionInfo__coll__graph.dot create mode 100644 html/dc/d7e/structCatch_1_1SectionInfo__coll__graph.md5 create mode 100644 html/dc/d87/structCatch_1_1Matchers_1_1Impl_1_1Matcher.html create mode 100644 html/dc/d89/classCatch_1_1MethodTestCase.html create mode 100644 html/dc/d92/classCatch_1_1TagExpressionParser__inherit__graph.dot create mode 100644 html/dc/d92/classCatch_1_1TagExpressionParser__inherit__graph.md5 create mode 100644 html/dc/daf/classRTSim_1_1AVRTask__inherit__graph.dot create mode 100644 html/dc/daf/classRTSim_1_1AVRTask__inherit__graph.md5 create mode 100644 html/dc/db2/classRTSim_1_1PIRManager__coll__graph.dot create mode 100644 html/dc/db2/classRTSim_1_1PIRManager__coll__graph.md5 create mode 100644 html/dc/dbb/classRTSim_1_1Grub.html create mode 100644 html/dc/dc5/structCatch_1_1MessageBuilder__coll__graph.dot create mode 100644 html/dc/dc5/structCatch_1_1MessageBuilder__coll__graph.md5 create mode 100644 html/dc/dc9/structCatch_1_1IMutableContext.html create mode 100644 html/dc/de0/structCatch_1_1CumulativeReporterBase.html create mode 100644 html/dc/de3/edfsched_8hpp_source.html create mode 100644 html/dc/de5/classRTSim_1_1LatenessStat.html create mode 100644 html/dc/dec/structCatch_1_1Internal_1_1OperatorTraits_3_01IsGreaterThan_01_4.html create mode 100644 html/dc/ded/classRTSim_1_1Task__inherit__graph.dot create mode 100644 html/dc/ded/classRTSim_1_1Task__inherit__graph.md5 create mode 100644 html/dc/dee/structCatch_1_1Internal_1_1OperatorTraits.html create mode 100644 html/dc/df6/classCatch_1_1Ptr.html create mode 100644 html/dd/d05/classRTSim_1_1DeadEvt__inherit__graph.dot create mode 100644 html/dd/d05/classRTSim_1_1DeadEvt__inherit__graph.md5 create mode 100644 html/dd/d0d/classMySim.html create mode 100644 html/dd/d13/classRTSim_1_1uniformCPUFactory__coll__graph.dot create mode 100644 html/dd/d13/classRTSim_1_1uniformCPUFactory__coll__graph.md5 create mode 100644 html/dd/d13/structCatch_1_1StreamingReporterBase__inherit__graph.dot create mode 100644 html/dd/d13/structCatch_1_1StreamingReporterBase__inherit__graph.md5 create mode 100644 html/dd/d17/classRTSim_1_1EmptyTask__inherit__graph.dot create mode 100644 html/dd/d17/classRTSim_1_1EmptyTask__inherit__graph.md5 create mode 100644 html/dd/d1b/classRTSim_1_1Instr.html create mode 100644 html/dd/d1f/classRTSim_1_1TaskNotExecuting.html create mode 100644 html/dd/d25/classRTSim_1_1KernelEvt__inherit__graph.dot create mode 100644 html/dd/d25/classRTSim_1_1KernelEvt__inherit__graph.md5 create mode 100644 html/dd/d25/classRTSim_1_1SparePot_1_1ChangeBudgetEvt__inherit__graph.dot create mode 100644 html/dd/d25/classRTSim_1_1SparePot_1_1ChangeBudgetEvt__inherit__graph.md5 create mode 100644 html/dd/d2d/classSystem.html create mode 100644 html/dd/d31/classRTSim_1_1SparePot_1_1SparePotExc__inherit__graph.dot create mode 100644 html/dd/d31/classRTSim_1_1SparePot_1_1SparePotExc__inherit__graph.md5 create mode 100644 html/dd/d34/classRTSim_1_1SchedIEvt.html create mode 100644 html/dd/d37/classRTSim_1_1FPScheduler__coll__graph.dot create mode 100644 html/dd/d37/classRTSim_1_1FPScheduler__coll__graph.md5 create mode 100644 html/dd/d38/classRTSim_1_1CBServer__inherit__graph.dot create mode 100644 html/dd/d38/classRTSim_1_1CBServer__inherit__graph.md5 create mode 100644 html/dd/d3e/classMySim__coll__graph.dot create mode 100644 html/dd/d3e/classMySim__coll__graph.md5 create mode 100644 html/dd/d3f/classRTSim_1_1RandomOffsetGen__coll__graph.dot create mode 100644 html/dd/d3f/classRTSim_1_1RandomOffsetGen__coll__graph.md5 create mode 100644 html/dd/d40/classRTSim_1_1AVRTask__coll__graph.dot create mode 100644 html/dd/d40/classRTSim_1_1AVRTask__coll__graph.md5 create mode 100644 html/dd/d43/classCatch_1_1TestCase__inherit__graph.dot create mode 100644 html/dd/d43/classCatch_1_1TestCase__inherit__graph.md5 create mode 100644 html/dd/d49/classRTSim_1_1RRScheduler_1_1RRSchedExc__inherit__graph.dot create mode 100644 html/dd/d49/classRTSim_1_1RRScheduler_1_1RRSchedExc__inherit__graph.md5 create mode 100644 html/dd/d4b/classRTSim_1_1Scheduler__coll__graph.dot create mode 100644 html/dd/d4b/classRTSim_1_1Scheduler__coll__graph.md5 create mode 100644 html/dd/d4d/classRTSim_1_1DeschedEvt__inherit__graph.dot create mode 100644 html/dd/d4d/classRTSim_1_1DeschedEvt__inherit__graph.md5 create mode 100644 html/dd/d60/classRTSim_1_1KernelEvt.html create mode 100644 html/dd/d70/classRTSim_1_1SuperCBS_1_1ChangeBudgetEvt__coll__graph.dot create mode 100644 html/dd/d70/classRTSim_1_1SuperCBS_1_1ChangeBudgetEvt__coll__graph.md5 create mode 100644 html/dd/d72/classRTSim_1_1DlineSetEvt.html create mode 100644 html/dd/d73/classRTSim_1_1MaxCTGen.html create mode 100644 html/dd/d74/classRTSim_1_1TraceEndEvent__inherit__graph.dot create mode 100644 html/dd/d74/classRTSim_1_1TraceEndEvent__inherit__graph.md5 create mode 100644 html/dd/d79/structCatch_1_1CumulativeReporterBase_1_1Node.html create mode 100644 html/dd/d7a/classRTSim_1_1FinishingTimeStat.html create mode 100644 html/dd/d8a/classRTSim_1_1RTModel_1_1RTModelCmp.html create mode 100644 html/dd/d90/classRTSim_1_1MaxCTGen__coll__graph.dot create mode 100644 html/dd/d90/classRTSim_1_1MaxCTGen__coll__graph.md5 create mode 100644 html/dd/d94/supercbs_8hpp_source.html create mode 100644 html/dd/d95/classRTSim_1_1OffsetGen__coll__graph.dot create mode 100644 html/dd/d95/classRTSim_1_1OffsetGen__coll__graph.md5 create mode 100644 html/dd/da7/classRTSim_1_1WaitInstr__coll__graph.dot create mode 100644 html/dd/da7/classRTSim_1_1WaitInstr__coll__graph.md5 create mode 100644 html/dd/da8/structCatch_1_1ResultAction.html create mode 100644 html/dd/da9/classRTSim_1_1PIRManager.html create mode 100644 html/dd/da9/classRTSim_1_1RTKernelExc.html create mode 100644 html/dd/dac/classRTSim_1_1PeriodicTimer__coll__graph.dot create mode 100644 html/dd/dac/classRTSim_1_1PeriodicTimer__coll__graph.md5 create mode 100644 html/dd/dad/classRTSim_1_1RandomTaskSetFactory__inherit__graph.dot create mode 100644 html/dd/dad/classRTSim_1_1RandomTaskSetFactory__inherit__graph.md5 create mode 100644 html/dd/dc2/structCatch_1_1CumulativeReporterBase_1_1Node__coll__graph.dot create mode 100644 html/dd/dc2/structCatch_1_1CumulativeReporterBase_1_1Node__coll__graph.md5 create mode 100644 html/dd/dc5/classRTSim_1_1ModeOutOfIndex__inherit__graph.dot create mode 100644 html/dd/dc5/classRTSim_1_1ModeOutOfIndex__inherit__graph.md5 create mode 100644 html/dd/dc7/structCatch_1_1ConfigData.html create mode 100644 html/dd/dcb/structRTSim_1_1SparePot_1_1server__struct.html create mode 100644 html/dd/dce/classRTSim_1_1TaskStatExc__inherit__graph.dot create mode 100644 html/dd/dce/classRTSim_1_1TaskStatExc__inherit__graph.md5 create mode 100644 html/dd/dd3/classRTSim_1_1TraceTaskEvent__coll__graph.dot create mode 100644 html/dd/dd3/classRTSim_1_1TraceTaskEvent__coll__graph.md5 create mode 100644 html/dd/dd4/classRTSim_1_1RandomDTGen__inherit__graph.dot create mode 100644 html/dd/dd4/classRTSim_1_1RandomDTGen__inherit__graph.md5 create mode 100644 html/dd/dda/namespaceRTSim_1_1____instr__stub.html create mode 100644 html/dd/de2/classRTSim_1_1IATGen__inherit__graph.dot create mode 100644 html/dd/de2/classRTSim_1_1IATGen__inherit__graph.md5 create mode 100644 html/dd/dee/structCatch_1_1MessageInfo__coll__graph.dot create mode 100644 html/dd/dee/structCatch_1_1MessageInfo__coll__graph.md5 create mode 100644 html/dd/df2/classCatch_1_1Config__coll__graph.dot create mode 100644 html/dd/df2/classCatch_1_1Config__coll__graph.md5 create mode 100644 html/dd/df4/classRTSim_1_1JavaTrace__inherit__graph.dot create mode 100644 html/dd/df4/classRTSim_1_1JavaTrace__inherit__graph.md5 create mode 100644 html/de/d05/classRTSim_1_1EndInstrEvt__coll__graph.dot create mode 100644 html/de/d05/classRTSim_1_1EndInstrEvt__coll__graph.md5 create mode 100644 html/de/d08/structCatch_1_1StreamingReporterBase.html create mode 100644 html/de/d0d/classRTSim_1_1SparePot__inherit__graph.dot create mode 100644 html/de/d0d/classRTSim_1_1SparePot__inherit__graph.md5 create mode 100644 html/de/d10/classRTSim_1_1DeadEvt__coll__graph.dot create mode 100644 html/de/d10/classRTSim_1_1DeadEvt__coll__graph.md5 create mode 100644 html/de/d13/classRTSim_1_1TraceSchedEvent__inherit__graph.dot create mode 100644 html/de/d13/classRTSim_1_1TraceSchedEvent__inherit__graph.md5 create mode 100644 html/de/d14/classRTSim_1_1TraceDlinePostEvent__coll__graph.dot create mode 100644 html/de/d14/classRTSim_1_1TraceDlinePostEvent__coll__graph.md5 create mode 100644 html/de/d1b/classRTSim_1_1ResManager__coll__graph.dot create mode 100644 html/de/d1b/classRTSim_1_1ResManager__coll__graph.md5 create mode 100644 html/de/d28/resmanager_8hpp_source.html create mode 100644 html/de/d29/classRTSim_1_1RTSchedExc__inherit__graph.dot create mode 100644 html/de/d29/classRTSim_1_1RTSchedExc__inherit__graph.md5 create mode 100644 html/de/d29/classRTSim_1_1WaitEvt__inherit__graph.dot create mode 100644 html/de/d29/classRTSim_1_1WaitEvt__inherit__graph.md5 create mode 100644 html/de/d2d/classRTSim_1_1SignalEvt__coll__graph.dot create mode 100644 html/de/d2d/classRTSim_1_1SignalEvt__coll__graph.md5 create mode 100644 html/de/d30/structCatch_1_1Matchers_1_1Impl_1_1Matcher__coll__graph.dot create mode 100644 html/de/d30/structCatch_1_1Matchers_1_1Impl_1_1Matcher__coll__graph.md5 create mode 100644 html/de/d4d/classRTSim_1_1TaskEvt__inherit__graph.dot create mode 100644 html/de/d4d/classRTSim_1_1TaskEvt__inherit__graph.md5 create mode 100644 html/de/d4d/classRTSim_1_1TaskModel__coll__graph.dot create mode 100644 html/de/d4d/classRTSim_1_1TaskModel__coll__graph.md5 create mode 100644 html/de/d58/structCatch_1_1StringMaker_3_01std_1_1vector_3_01T_00_01Allocator_01_4_01_4.html create mode 100644 html/de/d5e/sporadicserver_8hpp_source.html create mode 100644 html/de/d5f/classRTSim_1_1AbsTask.html create mode 100644 html/de/d5f/piresman_8hpp_source.html create mode 100644 html/de/d62/structCatch_1_1TestCaseInfo.html create mode 100644 html/de/d63/classRTSim_1_1MissPercentage__coll__graph.dot create mode 100644 html/de/d63/classRTSim_1_1MissPercentage__coll__graph.md5 create mode 100644 html/de/d70/classRTSim_1_1TraceCPUEvent__coll__graph.dot create mode 100644 html/de/d70/classRTSim_1_1TraceCPUEvent__coll__graph.md5 create mode 100644 html/de/d79/classRTSim_1_1TraceDlinePostEvent.html create mode 100644 html/de/d7f/classRTSim_1_1AbsKernel.html create mode 100644 html/de/d85/classRTSim_1_1CapacityTimer__inherit__graph.dot create mode 100644 html/de/d85/classRTSim_1_1CapacityTimer__inherit__graph.md5 create mode 100644 html/de/d8b/structCatch_1_1TestCaseStats__coll__graph.dot create mode 100644 html/de/d8b/structCatch_1_1TestCaseStats__coll__graph.md5 create mode 100644 html/de/d8c/structCatch_1_1ITestCase.html create mode 100644 html/de/d93/classRTSim_1_1FeedbackTestModule__coll__graph.dot create mode 100644 html/de/d93/classRTSim_1_1FeedbackTestModule__coll__graph.md5 create mode 100644 html/de/d93/classRTSim_1_1MRTKernel__inherit__graph.dot create mode 100644 html/de/d93/classRTSim_1_1MRTKernel__inherit__graph.md5 create mode 100644 html/de/d98/classRTSim_1_1CPU.html create mode 100644 html/de/da4/classRTSim_1_1MaxCTGen__inherit__graph.dot create mode 100644 html/de/da4/classRTSim_1_1MaxCTGen__inherit__graph.md5 create mode 100644 html/de/da5/structCatch_1_1StringMaker__coll__graph.dot create mode 100644 html/de/da5/structCatch_1_1StringMaker__coll__graph.md5 create mode 100644 html/de/dac/structCatch_1_1Internal_1_1OperatorTraits_3_01IsNotEqualTo_01_4.html create mode 100644 html/de/db0/structCatch_1_1Counts.html create mode 100644 html/de/db6/classRTSim_1_1JavaTrace__coll__graph.dot create mode 100644 html/de/db6/classRTSim_1_1JavaTrace__coll__graph.md5 create mode 100644 html/de/db6/classRTSim_1_1TraceIdleEvent.html create mode 100644 html/de/dbc/classRTSim_1_1RMScheduler__inherit__graph.dot create mode 100644 html/de/dbc/classRTSim_1_1RMScheduler__inherit__graph.md5 create mode 100644 html/de/dc5/classRTSim_1_1SchedPoint_1_1ChangeBudgetEvt__coll__graph.dot create mode 100644 html/de/dc5/classRTSim_1_1SchedPoint_1_1ChangeBudgetEvt__coll__graph.md5 create mode 100644 html/de/dc9/classRTSim_1_1GrubExc.html create mode 100644 html/de/dc9/traceevent_8hpp_source.html create mode 100644 html/de/dcf/structCatch_1_1WarnAbout.html create mode 100644 html/de/dd4/structCatch_1_1Matchers_1_1Impl_1_1MatcherImpl__coll__graph.dot create mode 100644 html/de/dd4/structCatch_1_1Matchers_1_1Impl_1_1MatcherImpl__coll__graph.md5 create mode 100644 html/de/ddc/classRTSim_1_1PreemptionStat__coll__graph.dot create mode 100644 html/de/ddc/classRTSim_1_1PreemptionStat__coll__graph.md5 create mode 100644 html/de/de6/structCatch_1_1Internal_1_1Evaluator_3_01T1_00_01T2_00_01IsNotEqualTo_01_4.html create mode 100644 html/de/de7/classRTSim_1_1TracePowerConsumption__coll__graph.dot create mode 100644 html/de/de7/classRTSim_1_1TracePowerConsumption__coll__graph.md5 create mode 100644 html/de/df3/classRTSim_1_1SuperCBS_1_1SuperCBSExc.html create mode 100644 html/df/d05/classRTSim_1_1DlineEquPeriodDTGen__inherit__graph.dot create mode 100644 html/df/d05/classRTSim_1_1DlineEquPeriodDTGen__inherit__graph.md5 create mode 100644 html/df/d05/timer_8hpp_source.html create mode 100644 html/df/d0a/server_8hpp_source.html create mode 100644 html/df/d15/classRTSim_1_1AbstractFeedbackModule__inherit__graph.dot create mode 100644 html/df/d15/classRTSim_1_1AbstractFeedbackModule__inherit__graph.md5 create mode 100644 html/df/d1b/classRTSim_1_1SchedIEvt__inherit__graph.dot create mode 100644 html/df/d1b/classRTSim_1_1SchedIEvt__inherit__graph.md5 create mode 100644 html/df/d1d/classCatch_1_1SafeBool.html create mode 100644 html/df/d29/structCatch_1_1TestCaseInfo__inherit__graph.dot create mode 100644 html/df/d29/structCatch_1_1TestCaseInfo__inherit__graph.md5 create mode 100644 html/df/d2c/classRTSim_1_1TaskNotActive__inherit__graph.dot create mode 100644 html/df/d2c/classRTSim_1_1TaskNotActive__inherit__graph.md5 create mode 100644 html/df/d33/classRTSim_1_1Grub__coll__graph.dot create mode 100644 html/df/d33/classRTSim_1_1Grub__coll__graph.md5 create mode 100644 html/df/d38/classCatch_1_1ExpressionDecomposer.html create mode 100644 html/df/d39/classRTSim_1_1EndDispatchEvt.html create mode 100644 html/df/d43/classRTSim_1_1SavedPower__coll__graph.dot create mode 100644 html/df/d43/classRTSim_1_1SavedPower__coll__graph.md5 create mode 100644 html/df/d44/classRTSim_1_1RTKernel__coll__graph.dot create mode 100644 html/df/d44/classRTSim_1_1RTKernel__coll__graph.md5 create mode 100644 html/df/d47/classRTSim_1_1FPScheduler.html create mode 100644 html/df/d4f/classRTSim_1_1FCFSResManager__inherit__graph.dot create mode 100644 html/df/d4f/classRTSim_1_1FCFSResManager__inherit__graph.md5 create mode 100644 html/df/d4f/reginstr_8hpp_source.html create mode 100644 html/df/d54/sim__structs_8hpp_source.html create mode 100644 html/df/d58/classRTSim_1_1PeriodicTimer__inherit__graph.dot create mode 100644 html/df/d58/classRTSim_1_1PeriodicTimer__inherit__graph.md5 create mode 100644 html/df/d6a/supervisor_8hpp_source.html create mode 100644 html/df/d72/load_8hpp_source.html create mode 100644 html/df/d7b/structRTSim_1_1SchedRTA_1_1ServerInfo.html create mode 100644 html/df/d97/interrupt_8hpp_source.html create mode 100644 html/df/da6/classRTSim_1_1AbstractGen.html create mode 100644 html/df/db0/suspend__instr_8hpp_source.html create mode 100644 html/df/db4/classRTSim_1_1uniformCPUFactory.html create mode 100644 html/df/db6/classRTSim_1_1RandomTaskSetFactory__coll__graph.dot create mode 100644 html/df/db6/classRTSim_1_1RandomTaskSetFactory__coll__graph.md5 create mode 100644 html/df/db8/kernel_8hpp_source.html create mode 100644 html/df/dbe/cpu_8hpp_source.html create mode 100644 html/df/dc7/classRTSim_1_1SuspendInstr__coll__graph.dot create mode 100644 html/df/dc7/classRTSim_1_1SuspendInstr__coll__graph.md5 create mode 100644 html/df/ddb/structCatch_1_1TestCaseStats.html create mode 100644 html/df/ddf/structCatch_1_1IConfig.html create mode 100644 html/df/ded/classRTSim_1_1PollingServer.html create mode 100644 html/df/dfb/schedinstr_8hpp_source.html create mode 100644 html/dir_13e138d54eb8818da29c3992edef070a.html create mode 100644 html/dir_2c1ec4cfaf5ed43ec260b4f91f837847.html create mode 100644 html/dir_3c5a7878238957e7a9a8834f0b838f8b.html create mode 100644 html/dir_3c5cc845447c19ce6ee25ef55a49cd4c.html create mode 100644 html/dir_3f9cfe9044a0c61e52ec878e2326b5b3.html create mode 100644 html/dir_4fef79e7177ba769987a8da36c892c5f.html create mode 100644 html/dir_55415680715be69f92249950f105c664.html create mode 100644 html/dir_63772b626f2709090f0bdca0f40827b4.html create mode 100644 html/dir_68267d1309a1af8e8297ef4c3efbcdba.html create mode 100644 html/dir_894d12cf7c955c04db6300346317721c.html create mode 100644 html/dir_a41afb44cd77021f04ef0298981be91e.html create mode 100644 html/dir_a573004c1aa1ac4f8bc48460229ea7de.html create mode 100644 html/dir_d28a4824dc47e487b107a5db32ef43c4.html create mode 100644 html/dir_d5f87438f5d8e96cf3117079ff5b9178.html create mode 100644 html/doc.png create mode 100644 html/doxygen.css create mode 100644 html/doxygen.png create mode 100644 html/dynsections.js create mode 100644 html/files.html create mode 100644 html/folderclosed.png create mode 100644 html/folderopen.png create mode 100644 html/functions.html create mode 100644 html/functions_0x7e.html create mode 100644 html/functions_a.html create mode 100644 html/functions_b.html create mode 100644 html/functions_c.html create mode 100644 html/functions_d.html create mode 100644 html/functions_e.html create mode 100644 html/functions_f.html create mode 100644 html/functions_func.html create mode 100644 html/functions_func_0x7e.html create mode 100644 html/functions_func_b.html create mode 100644 html/functions_func_c.html create mode 100644 html/functions_func_d.html create mode 100644 html/functions_func_e.html create mode 100644 html/functions_func_f.html create mode 100644 html/functions_func_g.html create mode 100644 html/functions_func_h.html create mode 100644 html/functions_func_i.html create mode 100644 html/functions_func_k.html create mode 100644 html/functions_func_l.html create mode 100644 html/functions_func_m.html create mode 100644 html/functions_func_n.html create mode 100644 html/functions_func_o.html create mode 100644 html/functions_func_p.html create mode 100644 html/functions_func_r.html create mode 100644 html/functions_func_s.html create mode 100644 html/functions_func_t.html create mode 100644 html/functions_func_u.html create mode 100644 html/functions_func_w.html create mode 100644 html/functions_g.html create mode 100644 html/functions_h.html create mode 100644 html/functions_i.html create mode 100644 html/functions_k.html create mode 100644 html/functions_l.html create mode 100644 html/functions_m.html create mode 100644 html/functions_n.html create mode 100644 html/functions_o.html create mode 100644 html/functions_p.html create mode 100644 html/functions_r.html create mode 100644 html/functions_rela.html create mode 100644 html/functions_s.html create mode 100644 html/functions_t.html create mode 100644 html/functions_u.html create mode 100644 html/functions_v.html create mode 100644 html/functions_vars.html create mode 100644 html/functions_w.html create mode 100644 html/graph_legend.dot create mode 100644 html/graph_legend.html create mode 100644 html/graph_legend.md5 create mode 100644 html/hierarchy.html create mode 100644 html/index.html create mode 100644 html/inherit_graph_0.dot create mode 100644 html/inherit_graph_0.md5 create mode 100644 html/inherit_graph_1.dot create mode 100644 html/inherit_graph_1.md5 create mode 100644 html/inherit_graph_10.dot create mode 100644 html/inherit_graph_10.md5 create mode 100644 html/inherit_graph_100.dot create mode 100644 html/inherit_graph_100.md5 create mode 100644 html/inherit_graph_101.dot create mode 100644 html/inherit_graph_101.md5 create mode 100644 html/inherit_graph_102.dot create mode 100644 html/inherit_graph_102.md5 create mode 100644 html/inherit_graph_103.dot create mode 100644 html/inherit_graph_103.md5 create mode 100644 html/inherit_graph_104.dot create mode 100644 html/inherit_graph_104.md5 create mode 100644 html/inherit_graph_105.dot create mode 100644 html/inherit_graph_105.md5 create mode 100644 html/inherit_graph_106.dot create mode 100644 html/inherit_graph_106.md5 create mode 100644 html/inherit_graph_107.dot create mode 100644 html/inherit_graph_107.md5 create mode 100644 html/inherit_graph_108.dot create mode 100644 html/inherit_graph_108.md5 create mode 100644 html/inherit_graph_109.dot create mode 100644 html/inherit_graph_109.md5 create mode 100644 html/inherit_graph_11.dot create mode 100644 html/inherit_graph_11.md5 create mode 100644 html/inherit_graph_110.dot create mode 100644 html/inherit_graph_110.md5 create mode 100644 html/inherit_graph_111.dot create mode 100644 html/inherit_graph_111.md5 create mode 100644 html/inherit_graph_112.dot create mode 100644 html/inherit_graph_112.md5 create mode 100644 html/inherit_graph_113.dot create mode 100644 html/inherit_graph_113.md5 create mode 100644 html/inherit_graph_114.dot create mode 100644 html/inherit_graph_114.md5 create mode 100644 html/inherit_graph_115.dot create mode 100644 html/inherit_graph_115.md5 create mode 100644 html/inherit_graph_116.dot create mode 100644 html/inherit_graph_116.md5 create mode 100644 html/inherit_graph_117.dot create mode 100644 html/inherit_graph_117.md5 create mode 100644 html/inherit_graph_118.dot create mode 100644 html/inherit_graph_118.md5 create mode 100644 html/inherit_graph_119.dot create mode 100644 html/inherit_graph_119.md5 create mode 100644 html/inherit_graph_12.dot create mode 100644 html/inherit_graph_12.md5 create mode 100644 html/inherit_graph_120.dot create mode 100644 html/inherit_graph_120.md5 create mode 100644 html/inherit_graph_121.dot create mode 100644 html/inherit_graph_121.md5 create mode 100644 html/inherit_graph_122.dot create mode 100644 html/inherit_graph_122.md5 create mode 100644 html/inherit_graph_123.dot create mode 100644 html/inherit_graph_123.md5 create mode 100644 html/inherit_graph_124.dot create mode 100644 html/inherit_graph_124.md5 create mode 100644 html/inherit_graph_125.dot create mode 100644 html/inherit_graph_125.md5 create mode 100644 html/inherit_graph_126.dot create mode 100644 html/inherit_graph_126.md5 create mode 100644 html/inherit_graph_127.dot create mode 100644 html/inherit_graph_127.md5 create mode 100644 html/inherit_graph_13.dot create mode 100644 html/inherit_graph_13.md5 create mode 100644 html/inherit_graph_14.dot create mode 100644 html/inherit_graph_14.md5 create mode 100644 html/inherit_graph_15.dot create mode 100644 html/inherit_graph_15.md5 create mode 100644 html/inherit_graph_16.dot create mode 100644 html/inherit_graph_16.md5 create mode 100644 html/inherit_graph_17.dot create mode 100644 html/inherit_graph_17.md5 create mode 100644 html/inherit_graph_18.dot create mode 100644 html/inherit_graph_18.md5 create mode 100644 html/inherit_graph_19.dot create mode 100644 html/inherit_graph_19.md5 create mode 100644 html/inherit_graph_2.dot create mode 100644 html/inherit_graph_2.md5 create mode 100644 html/inherit_graph_20.dot create mode 100644 html/inherit_graph_20.md5 create mode 100644 html/inherit_graph_21.dot create mode 100644 html/inherit_graph_21.md5 create mode 100644 html/inherit_graph_22.dot create mode 100644 html/inherit_graph_22.md5 create mode 100644 html/inherit_graph_23.dot create mode 100644 html/inherit_graph_23.md5 create mode 100644 html/inherit_graph_24.dot create mode 100644 html/inherit_graph_24.md5 create mode 100644 html/inherit_graph_25.dot create mode 100644 html/inherit_graph_25.md5 create mode 100644 html/inherit_graph_26.dot create mode 100644 html/inherit_graph_26.md5 create mode 100644 html/inherit_graph_27.dot create mode 100644 html/inherit_graph_27.md5 create mode 100644 html/inherit_graph_28.dot create mode 100644 html/inherit_graph_28.md5 create mode 100644 html/inherit_graph_29.dot create mode 100644 html/inherit_graph_29.md5 create mode 100644 html/inherit_graph_3.dot create mode 100644 html/inherit_graph_3.md5 create mode 100644 html/inherit_graph_30.dot create mode 100644 html/inherit_graph_30.md5 create mode 100644 html/inherit_graph_31.dot create mode 100644 html/inherit_graph_31.md5 create mode 100644 html/inherit_graph_32.dot create mode 100644 html/inherit_graph_32.md5 create mode 100644 html/inherit_graph_33.dot create mode 100644 html/inherit_graph_33.md5 create mode 100644 html/inherit_graph_34.dot create mode 100644 html/inherit_graph_34.md5 create mode 100644 html/inherit_graph_35.dot create mode 100644 html/inherit_graph_35.md5 create mode 100644 html/inherit_graph_36.dot create mode 100644 html/inherit_graph_36.md5 create mode 100644 html/inherit_graph_37.dot create mode 100644 html/inherit_graph_37.md5 create mode 100644 html/inherit_graph_38.dot create mode 100644 html/inherit_graph_38.md5 create mode 100644 html/inherit_graph_39.dot create mode 100644 html/inherit_graph_39.md5 create mode 100644 html/inherit_graph_4.dot create mode 100644 html/inherit_graph_4.md5 create mode 100644 html/inherit_graph_40.dot create mode 100644 html/inherit_graph_40.md5 create mode 100644 html/inherit_graph_41.dot create mode 100644 html/inherit_graph_41.md5 create mode 100644 html/inherit_graph_42.dot create mode 100644 html/inherit_graph_42.md5 create mode 100644 html/inherit_graph_43.dot create mode 100644 html/inherit_graph_43.md5 create mode 100644 html/inherit_graph_44.dot create mode 100644 html/inherit_graph_44.md5 create mode 100644 html/inherit_graph_45.dot create mode 100644 html/inherit_graph_45.md5 create mode 100644 html/inherit_graph_46.dot create mode 100644 html/inherit_graph_46.md5 create mode 100644 html/inherit_graph_47.dot create mode 100644 html/inherit_graph_47.md5 create mode 100644 html/inherit_graph_48.dot create mode 100644 html/inherit_graph_48.md5 create mode 100644 html/inherit_graph_49.dot create mode 100644 html/inherit_graph_49.md5 create mode 100644 html/inherit_graph_5.dot create mode 100644 html/inherit_graph_5.md5 create mode 100644 html/inherit_graph_50.dot create mode 100644 html/inherit_graph_50.md5 create mode 100644 html/inherit_graph_51.dot create mode 100644 html/inherit_graph_51.md5 create mode 100644 html/inherit_graph_52.dot create mode 100644 html/inherit_graph_52.md5 create mode 100644 html/inherit_graph_53.dot create mode 100644 html/inherit_graph_53.md5 create mode 100644 html/inherit_graph_54.dot create mode 100644 html/inherit_graph_54.md5 create mode 100644 html/inherit_graph_55.dot create mode 100644 html/inherit_graph_55.md5 create mode 100644 html/inherit_graph_56.dot create mode 100644 html/inherit_graph_56.md5 create mode 100644 html/inherit_graph_57.dot create mode 100644 html/inherit_graph_57.md5 create mode 100644 html/inherit_graph_58.dot create mode 100644 html/inherit_graph_58.md5 create mode 100644 html/inherit_graph_59.dot create mode 100644 html/inherit_graph_59.md5 create mode 100644 html/inherit_graph_6.dot create mode 100644 html/inherit_graph_6.md5 create mode 100644 html/inherit_graph_60.dot create mode 100644 html/inherit_graph_60.md5 create mode 100644 html/inherit_graph_61.dot create mode 100644 html/inherit_graph_61.md5 create mode 100644 html/inherit_graph_62.dot create mode 100644 html/inherit_graph_62.md5 create mode 100644 html/inherit_graph_63.dot create mode 100644 html/inherit_graph_63.md5 create mode 100644 html/inherit_graph_64.dot create mode 100644 html/inherit_graph_64.md5 create mode 100644 html/inherit_graph_65.dot create mode 100644 html/inherit_graph_65.md5 create mode 100644 html/inherit_graph_66.dot create mode 100644 html/inherit_graph_66.md5 create mode 100644 html/inherit_graph_67.dot create mode 100644 html/inherit_graph_67.md5 create mode 100644 html/inherit_graph_68.dot create mode 100644 html/inherit_graph_68.md5 create mode 100644 html/inherit_graph_69.dot create mode 100644 html/inherit_graph_69.md5 create mode 100644 html/inherit_graph_7.dot create mode 100644 html/inherit_graph_7.md5 create mode 100644 html/inherit_graph_70.dot create mode 100644 html/inherit_graph_70.md5 create mode 100644 html/inherit_graph_71.dot create mode 100644 html/inherit_graph_71.md5 create mode 100644 html/inherit_graph_72.dot create mode 100644 html/inherit_graph_72.md5 create mode 100644 html/inherit_graph_73.dot create mode 100644 html/inherit_graph_73.md5 create mode 100644 html/inherit_graph_74.dot create mode 100644 html/inherit_graph_74.md5 create mode 100644 html/inherit_graph_75.dot create mode 100644 html/inherit_graph_75.md5 create mode 100644 html/inherit_graph_76.dot create mode 100644 html/inherit_graph_76.md5 create mode 100644 html/inherit_graph_77.dot create mode 100644 html/inherit_graph_77.md5 create mode 100644 html/inherit_graph_78.dot create mode 100644 html/inherit_graph_78.md5 create mode 100644 html/inherit_graph_79.dot create mode 100644 html/inherit_graph_79.md5 create mode 100644 html/inherit_graph_8.dot create mode 100644 html/inherit_graph_8.md5 create mode 100644 html/inherit_graph_80.dot create mode 100644 html/inherit_graph_80.md5 create mode 100644 html/inherit_graph_81.dot create mode 100644 html/inherit_graph_81.md5 create mode 100644 html/inherit_graph_82.dot create mode 100644 html/inherit_graph_82.md5 create mode 100644 html/inherit_graph_83.dot create mode 100644 html/inherit_graph_83.md5 create mode 100644 html/inherit_graph_84.dot create mode 100644 html/inherit_graph_84.md5 create mode 100644 html/inherit_graph_85.dot create mode 100644 html/inherit_graph_85.md5 create mode 100644 html/inherit_graph_86.dot create mode 100644 html/inherit_graph_86.md5 create mode 100644 html/inherit_graph_87.dot create mode 100644 html/inherit_graph_87.md5 create mode 100644 html/inherit_graph_88.dot create mode 100644 html/inherit_graph_88.md5 create mode 100644 html/inherit_graph_89.dot create mode 100644 html/inherit_graph_89.md5 create mode 100644 html/inherit_graph_9.dot create mode 100644 html/inherit_graph_9.md5 create mode 100644 html/inherit_graph_90.dot create mode 100644 html/inherit_graph_90.md5 create mode 100644 html/inherit_graph_91.dot create mode 100644 html/inherit_graph_91.md5 create mode 100644 html/inherit_graph_92.dot create mode 100644 html/inherit_graph_92.md5 create mode 100644 html/inherit_graph_93.dot create mode 100644 html/inherit_graph_93.md5 create mode 100644 html/inherit_graph_94.dot create mode 100644 html/inherit_graph_94.md5 create mode 100644 html/inherit_graph_95.dot create mode 100644 html/inherit_graph_95.md5 create mode 100644 html/inherit_graph_96.dot create mode 100644 html/inherit_graph_96.md5 create mode 100644 html/inherit_graph_97.dot create mode 100644 html/inherit_graph_97.md5 create mode 100644 html/inherit_graph_98.dot create mode 100644 html/inherit_graph_98.md5 create mode 100644 html/inherit_graph_99.dot create mode 100644 html/inherit_graph_99.md5 create mode 100644 html/inherits.html create mode 100644 html/jquery.js create mode 100644 html/md_README.html create mode 100644 html/modules.html create mode 100644 html/namespacemembers.html create mode 100644 html/namespacemembers_enum.html create mode 100644 html/namespacemembers_func.html create mode 100644 html/namespaces.html create mode 100644 html/nav_f.png create mode 100644 html/nav_g.png create mode 100644 html/nav_h.png create mode 100644 html/open.png create mode 100644 html/pages.html create mode 100644 html/search/all_0.html create mode 100644 html/search/all_0.js create mode 100644 html/search/all_1.html create mode 100644 html/search/all_1.js create mode 100644 html/search/all_10.html create mode 100644 html/search/all_10.js create mode 100644 html/search/all_11.html create mode 100644 html/search/all_11.js create mode 100644 html/search/all_12.html create mode 100644 html/search/all_12.js create mode 100644 html/search/all_13.html create mode 100644 html/search/all_13.js create mode 100644 html/search/all_14.html create mode 100644 html/search/all_14.js create mode 100644 html/search/all_15.html create mode 100644 html/search/all_15.js create mode 100644 html/search/all_16.html create mode 100644 html/search/all_16.js create mode 100644 html/search/all_17.html create mode 100644 html/search/all_17.js create mode 100644 html/search/all_2.html create mode 100644 html/search/all_2.js create mode 100644 html/search/all_3.html create mode 100644 html/search/all_3.js create mode 100644 html/search/all_4.html create mode 100644 html/search/all_4.js create mode 100644 html/search/all_5.html create mode 100644 html/search/all_5.js create mode 100644 html/search/all_6.html create mode 100644 html/search/all_6.js create mode 100644 html/search/all_7.html create mode 100644 html/search/all_7.js create mode 100644 html/search/all_8.html create mode 100644 html/search/all_8.js create mode 100644 html/search/all_9.html create mode 100644 html/search/all_9.js create mode 100644 html/search/all_a.html create mode 100644 html/search/all_a.js create mode 100644 html/search/all_b.html create mode 100644 html/search/all_b.js create mode 100644 html/search/all_c.html create mode 100644 html/search/all_c.js create mode 100644 html/search/all_d.html create mode 100644 html/search/all_d.js create mode 100644 html/search/all_e.html create mode 100644 html/search/all_e.js create mode 100644 html/search/all_f.html create mode 100644 html/search/all_f.js create mode 100644 html/search/classes_0.html create mode 100644 html/search/classes_0.js create mode 100644 html/search/classes_1.html create mode 100644 html/search/classes_1.js create mode 100644 html/search/classes_10.html create mode 100644 html/search/classes_10.js create mode 100644 html/search/classes_11.html create mode 100644 html/search/classes_11.js create mode 100644 html/search/classes_12.html create mode 100644 html/search/classes_12.js create mode 100644 html/search/classes_13.html create mode 100644 html/search/classes_13.js create mode 100644 html/search/classes_14.html create mode 100644 html/search/classes_14.js create mode 100644 html/search/classes_2.html create mode 100644 html/search/classes_2.js create mode 100644 html/search/classes_3.html create mode 100644 html/search/classes_3.js create mode 100644 html/search/classes_4.html create mode 100644 html/search/classes_4.js create mode 100644 html/search/classes_5.html create mode 100644 html/search/classes_5.js create mode 100644 html/search/classes_6.html create mode 100644 html/search/classes_6.js create mode 100644 html/search/classes_7.html create mode 100644 html/search/classes_7.js create mode 100644 html/search/classes_8.html create mode 100644 html/search/classes_8.js create mode 100644 html/search/classes_9.html create mode 100644 html/search/classes_9.js create mode 100644 html/search/classes_a.html create mode 100644 html/search/classes_a.js create mode 100644 html/search/classes_b.html create mode 100644 html/search/classes_b.js create mode 100644 html/search/classes_c.html create mode 100644 html/search/classes_c.js create mode 100644 html/search/classes_d.html create mode 100644 html/search/classes_d.js create mode 100644 html/search/classes_e.html create mode 100644 html/search/classes_e.js create mode 100644 html/search/classes_f.html create mode 100644 html/search/classes_f.js create mode 100644 html/search/close.png create mode 100644 html/search/enums_0.html create mode 100644 html/search/enums_0.js create mode 100644 html/search/functions_0.html create mode 100644 html/search/functions_0.js create mode 100644 html/search/functions_1.html create mode 100644 html/search/functions_1.js create mode 100644 html/search/functions_10.html create mode 100644 html/search/functions_10.js create mode 100644 html/search/functions_11.html create mode 100644 html/search/functions_11.js create mode 100644 html/search/functions_12.html create mode 100644 html/search/functions_12.js create mode 100644 html/search/functions_13.html create mode 100644 html/search/functions_13.js create mode 100644 html/search/functions_14.html create mode 100644 html/search/functions_14.js create mode 100644 html/search/functions_2.html create mode 100644 html/search/functions_2.js create mode 100644 html/search/functions_3.html create mode 100644 html/search/functions_3.js create mode 100644 html/search/functions_4.html create mode 100644 html/search/functions_4.js create mode 100644 html/search/functions_5.html create mode 100644 html/search/functions_5.js create mode 100644 html/search/functions_6.html create mode 100644 html/search/functions_6.js create mode 100644 html/search/functions_7.html create mode 100644 html/search/functions_7.js create mode 100644 html/search/functions_8.html create mode 100644 html/search/functions_8.js create mode 100644 html/search/functions_9.html create mode 100644 html/search/functions_9.js create mode 100644 html/search/functions_a.html create mode 100644 html/search/functions_a.js create mode 100644 html/search/functions_b.html create mode 100644 html/search/functions_b.js create mode 100644 html/search/functions_c.html create mode 100644 html/search/functions_c.js create mode 100644 html/search/functions_d.html create mode 100644 html/search/functions_d.js create mode 100644 html/search/functions_e.html create mode 100644 html/search/functions_e.js create mode 100644 html/search/functions_f.html create mode 100644 html/search/functions_f.js create mode 100644 html/search/groups_0.html create mode 100644 html/search/groups_0.js create mode 100644 html/search/mag_sel.png create mode 100644 html/search/namespaces_0.html create mode 100644 html/search/namespaces_0.js create mode 100644 html/search/nomatches.html create mode 100644 html/search/pages_0.html create mode 100644 html/search/pages_0.js create mode 100644 html/search/pages_1.html create mode 100644 html/search/pages_1.js create mode 100644 html/search/related_0.html create mode 100644 html/search/related_0.js create mode 100644 html/search/search.css create mode 100644 html/search/search.js create mode 100644 html/search/search_l.png create mode 100644 html/search/search_m.png create mode 100644 html/search/search_r.png create mode 100644 html/search/searchdata.js create mode 100644 html/search/variables_0.html create mode 100644 html/search/variables_0.js create mode 100644 html/search/variables_1.html create mode 100644 html/search/variables_1.js create mode 100644 html/search/variables_2.html create mode 100644 html/search/variables_2.js create mode 100644 html/search/variables_3.html create mode 100644 html/search/variables_3.js create mode 100644 html/search/variables_4.html create mode 100644 html/search/variables_4.js create mode 100644 html/search/variables_5.html create mode 100644 html/search/variables_5.js create mode 100644 html/search/variables_6.html create mode 100644 html/search/variables_6.js create mode 100644 html/search/variables_7.html create mode 100644 html/search/variables_7.js create mode 100644 html/search/variables_8.html create mode 100644 html/search/variables_8.js create mode 100644 html/search/variables_9.html create mode 100644 html/search/variables_9.js create mode 100644 html/search/variables_a.html create mode 100644 html/search/variables_a.js create mode 100644 html/search/variables_b.html create mode 100644 html/search/variables_b.js create mode 100644 html/splitbar.png create mode 100644 html/sync_off.png create mode 100644 html/sync_on.png create mode 100644 html/tab_a.png create mode 100644 html/tab_b.png create mode 100644 html/tab_h.png create mode 100644 html/tab_s.png create mode 100644 html/tabs.css create mode 100644 html/todo.html create mode 100644 latex/Makefile create mode 100644 latex/annotated.tex create mode 100644 latex/d0/d02/classRTSim_1_1ThreEvt.tex create mode 100644 latex/d0/d03/classRTSim_1_1SignalInstr__coll__graph.dot create mode 100644 latex/d0/d03/classRTSim_1_1SignalInstr__coll__graph.md5 create mode 100644 latex/d0/d0a/classCatch_1_1ScopedMessage.tex create mode 100644 latex/d0/d1a/classRTSim_1_1CPU__coll__graph.dot create mode 100644 latex/d0/d1a/classRTSim_1_1CPU__coll__graph.md5 create mode 100644 latex/d0/d1a/classRTSim_1_1TaskEvt__coll__graph.dot create mode 100644 latex/d0/d1a/classRTSim_1_1TaskEvt__coll__graph.md5 create mode 100644 latex/d0/d1b/classCatch_1_1StreamBufImpl.tex create mode 100644 latex/d0/d23/classCatch_1_1ValuesGenerator__inherit__graph.dot create mode 100644 latex/d0/d23/classCatch_1_1ValuesGenerator__inherit__graph.md5 create mode 100644 latex/d0/d27/classRTSim_1_1Interrupt.tex create mode 100644 latex/d0/d2f/classRTSim_1_1TraceTaskEvent.tex create mode 100644 latex/d0/d38/classRTSim_1_1DispatchEvt.tex create mode 100644 latex/d0/d38/classRTSim_1_1ResManager__inherit__graph.dot create mode 100644 latex/d0/d38/classRTSim_1_1ResManager__inherit__graph.md5 create mode 100644 latex/d0/d39/classRTSim_1_1AbsResManager.tex create mode 100644 latex/d0/d3f/classRTSim_1_1ConstCTGen__coll__graph.dot create mode 100644 latex/d0/d3f/classRTSim_1_1ConstCTGen__coll__graph.md5 create mode 100644 latex/d0/d40/classRTSim_1_1KernAlreadySet__inherit__graph.dot create mode 100644 latex/d0/d40/classRTSim_1_1KernAlreadySet__inherit__graph.md5 create mode 100644 latex/d0/d43/classRTSim_1_1EDFScheduler.tex create mode 100644 latex/d0/d48/classRTSim_1_1TraceDlinePostEvent__inherit__graph.dot create mode 100644 latex/d0/d48/classRTSim_1_1TraceDlinePostEvent__inherit__graph.md5 create mode 100644 latex/d0/d5b/classRTSim_1_1SchedEvt.tex create mode 100644 latex/d0/d6e/structCatch_1_1Matchers_1_1Impl_1_1MatcherImpl__inherit__graph.dot create mode 100644 latex/d0/d6e/structCatch_1_1Matchers_1_1Impl_1_1MatcherImpl__inherit__graph.md5 create mode 100644 latex/d0/d72/classRTSim_1_1SporadicServer__coll__graph.dot create mode 100644 latex/d0/d72/classRTSim_1_1SporadicServer__coll__graph.md5 create mode 100644 latex/d0/d76/classRTSim_1_1AVRTask.tex create mode 100644 latex/d0/d7d/classRTSim_1_1SuperCBS_1_1ChangeBudgetEvt.tex create mode 100644 latex/d0/d81/classRTSim_1_1UtilizationStat__coll__graph.dot create mode 100644 latex/d0/d81/classRTSim_1_1UtilizationStat__coll__graph.md5 create mode 100644 latex/d0/d82/structCatch_1_1ShowDurations.tex create mode 100644 latex/d0/d83/classRTSim_1_1SuperCBS__inherit__graph.dot create mode 100644 latex/d0/d83/classRTSim_1_1SuperCBS__inherit__graph.md5 create mode 100644 latex/d0/d92/classRTSim_1_1TraceEvent__inherit__graph.dot create mode 100644 latex/d0/d92/classRTSim_1_1TraceEvent__inherit__graph.md5 create mode 100644 latex/d0/d94/classRTSim_1_1SuperCBS__coll__graph.dot create mode 100644 latex/d0/d94/classRTSim_1_1SuperCBS__coll__graph.md5 create mode 100644 latex/d0/d94/classRTSim_1_1TraceWaitEvent.tex create mode 100644 latex/d0/d95/classRTSim_1_1SporadicDTGen.tex create mode 100644 latex/d0/d97/structCatch_1_1FalseType.tex create mode 100644 latex/d0/da3/structStats.tex create mode 100644 latex/d0/da7/classRTSim_1_1TraceNameEvent__coll__graph.dot create mode 100644 latex/d0/da7/classRTSim_1_1TraceNameEvent__coll__graph.md5 create mode 100644 latex/d0/db4/classRTSim_1_1SporadicDTGen__inherit__graph.dot create mode 100644 latex/d0/db4/classRTSim_1_1SporadicDTGen__inherit__graph.md5 create mode 100644 latex/d0/dcc/structCatch_1_1IConfig__inherit__graph.dot create mode 100644 latex/d0/dcc/structCatch_1_1IConfig__inherit__graph.md5 create mode 100644 latex/d0/ddc/structCatch_1_1Matchers_1_1Impl_1_1StdString_1_1EndsWith.tex create mode 100644 latex/d0/dde/classRTSim_1_1ConstCTGen__inherit__graph.dot create mode 100644 latex/d0/dde/classRTSim_1_1ConstCTGen__inherit__graph.md5 create mode 100644 latex/d0/de3/classRTSim_1_1SchedRTA.tex create mode 100644 latex/d0/de4/classCatch_1_1StreamBufBase__inherit__graph.dot create mode 100644 latex/d0/de4/classCatch_1_1StreamBufBase__inherit__graph.md5 create mode 100644 latex/d0/def/classRTSim_1_1TardinessStat__inherit__graph.dot create mode 100644 latex/d0/def/classRTSim_1_1TardinessStat__inherit__graph.md5 create mode 100644 latex/d0/df5/classRTSim_1_1FPScheduler_1_1FPModel__coll__graph.dot create mode 100644 latex/d0/df5/classRTSim_1_1FPScheduler_1_1FPModel__coll__graph.md5 create mode 100644 latex/d0/df5/classRTSim_1_1OffsetGen__inherit__graph.dot create mode 100644 latex/d0/df5/classRTSim_1_1OffsetGen__inherit__graph.md5 create mode 100644 latex/d0/dfa/classCatch_1_1BetweenGenerator__coll__graph.dot create mode 100644 latex/d0/dfa/classCatch_1_1BetweenGenerator__coll__graph.md5 create mode 100644 latex/d0/dfd/classRTSim_1_1SchedPoint__inherit__graph.dot create mode 100644 latex/d0/dfd/classRTSim_1_1SchedPoint__inherit__graph.md5 create mode 100644 latex/d1/d02/classRTSim_1_1Resource__inherit__graph.dot create mode 100644 latex/d1/d02/classRTSim_1_1Resource__inherit__graph.md5 create mode 100644 latex/d1/d09/classCatch_1_1AssertionResult.tex create mode 100644 latex/d1/d0e/structCatch_1_1IShared__coll__graph.dot create mode 100644 latex/d1/d0e/structCatch_1_1IShared__coll__graph.md5 create mode 100644 latex/d1/d15/classCatch_1_1Config__inherit__graph.dot create mode 100644 latex/d1/d15/classCatch_1_1Config__inherit__graph.md5 create mode 100644 latex/d1/d1d/classRTSim_1_1ArrEvt.tex create mode 100644 latex/d1/d25/classRTSim_1_1DTGen__coll__graph.dot create mode 100644 latex/d1/d25/classRTSim_1_1DTGen__coll__graph.md5 create mode 100644 latex/d1/d27/classCatch_1_1TagParser.tex create mode 100644 latex/d1/d28/classRTSim_1_1InstrExc.tex create mode 100644 latex/d1/d33/classRTSim_1_1ThreEvt__inherit__graph.dot create mode 100644 latex/d1/d33/classRTSim_1_1ThreEvt__inherit__graph.md5 create mode 100644 latex/d1/d36/classRTSim_1_1FPScheduler__inherit__graph.dot create mode 100644 latex/d1/d36/classRTSim_1_1FPScheduler__inherit__graph.md5 create mode 100644 latex/d1/d43/classRTSim_1_1FeedbackTestModule.tex create mode 100644 latex/d1/d47/structCatch_1_1IGeneratorsForTest.tex create mode 100644 latex/d1/d4d/classRTSim_1_1TextTrace.tex create mode 100644 latex/d1/d4f/classRTSim_1_1GrubSupervisor__coll__graph.dot create mode 100644 latex/d1/d4f/classRTSim_1_1GrubSupervisor__coll__graph.md5 create mode 100644 latex/d1/d52/classRTSim_1_1FeedbackModuleARSim__inherit__graph.dot create mode 100644 latex/d1/d52/classRTSim_1_1FeedbackModuleARSim__inherit__graph.md5 create mode 100644 latex/d1/d55/classRTSim_1_1PollingServer__inherit__graph.dot create mode 100644 latex/d1/d55/classRTSim_1_1PollingServer__inherit__graph.md5 create mode 100644 latex/d1/d55/structCatch_1_1TestGroupStats.tex create mode 100644 latex/d1/d64/classRTSim_1_1MissPercentage.tex create mode 100644 latex/d1/d6d/classRTSim_1_1BeginDispatchMultiEvt.tex create mode 100644 latex/d1/d6e/structCatch_1_1Matchers_1_1Impl_1_1MatcherImpl.tex create mode 100644 latex/d1/d88/classRTSim_1_1UniformCTGen__coll__graph.dot create mode 100644 latex/d1/d88/classRTSim_1_1UniformCTGen__coll__graph.md5 create mode 100644 latex/d1/d8a/classRTSim_1_1TaskAlreadyExecuting__coll__graph.dot create mode 100644 latex/d1/d8a/classRTSim_1_1TaskAlreadyExecuting__coll__graph.md5 create mode 100644 latex/d1/d8c/classRTSim_1_1ConstIATGen.tex create mode 100644 latex/d1/d8e/classRTSim_1_1EndDispatchMultiEvt.tex create mode 100644 latex/d1/d8e/classRTSim_1_1KillEvt__coll__graph.dot create mode 100644 latex/d1/d8e/classRTSim_1_1KillEvt__coll__graph.md5 create mode 100644 latex/d1/d91/classCatch_1_1MethodTestCase__coll__graph.dot create mode 100644 latex/d1/d91/classCatch_1_1MethodTestCase__coll__graph.md5 create mode 100644 latex/d1/d96/structCatch_1_1CumulativeReporterBase_1_1Node__inherit__graph.dot create mode 100644 latex/d1/d96/structCatch_1_1CumulativeReporterBase_1_1Node__inherit__graph.md5 create mode 100644 latex/d1/d9d/classRTSim_1_1DlineSetEvt__inherit__graph.dot create mode 100644 latex/d1/d9d/classRTSim_1_1DlineSetEvt__inherit__graph.md5 create mode 100644 latex/d1/db1/classRTSim_1_1IATGen.tex create mode 100644 latex/d1/dbb/classRTSim_1_1TaskStatExc__coll__graph.dot create mode 100644 latex/d1/dbb/classRTSim_1_1TaskStatExc__coll__graph.md5 create mode 100644 latex/d1/dbb/structCatch_1_1Matchers_1_1Impl_1_1StdString_1_1StartsWith__inherit__graph.dot create mode 100644 latex/d1/dbb/structCatch_1_1Matchers_1_1Impl_1_1StdString_1_1StartsWith__inherit__graph.md5 create mode 100644 latex/d1/dbf/classRTSim_1_1GrubExc__coll__graph.dot create mode 100644 latex/d1/dbf/classRTSim_1_1GrubExc__coll__graph.md5 create mode 100644 latex/d1/dc1/structCatch_1_1IShared.tex create mode 100644 latex/d1/dc8/classRTSim_1_1MissCount__inherit__graph.dot create mode 100644 latex/d1/dc8/classRTSim_1_1MissCount__inherit__graph.md5 create mode 100644 latex/d1/dd2/classRTSim_1_1RTSchedExc__coll__graph.dot create mode 100644 latex/d1/dd2/classRTSim_1_1RTSchedExc__coll__graph.md5 create mode 100644 latex/d1/dd4/classRTSim_1_1SignalEvt__inherit__graph.dot create mode 100644 latex/d1/dd4/classRTSim_1_1SignalEvt__inherit__graph.md5 create mode 100644 latex/d1/dd8/classRTSim_1_1TardinessStat__coll__graph.dot create mode 100644 latex/d1/dd8/classRTSim_1_1TardinessStat__coll__graph.md5 create mode 100644 latex/d1/ddd/structCatch_1_1StringMaker__inherit__graph.dot create mode 100644 latex/d1/ddd/structCatch_1_1StringMaker__inherit__graph.md5 create mode 100644 latex/d1/de8/structRTSim_1_1SchedPoint_1_1points.tex create mode 100644 latex/d1/df2/classRTSim_1_1SchedPoint_1_1SchedPointExc.tex create mode 100644 latex/d1/dfa/classRTSim_1_1MinIATGen.tex create mode 100644 latex/d1/dff/classRTSim_1_1RTModel__inherit__graph.dot create mode 100644 latex/d1/dff/classRTSim_1_1RTModel__inherit__graph.md5 create mode 100644 latex/d2/d01/structCatch_1_1Totals.tex create mode 100644 latex/d2/d06/classRTSim_1_1InstrExc__coll__graph.dot create mode 100644 latex/d2/d06/classRTSim_1_1InstrExc__coll__graph.md5 create mode 100644 latex/d2/d09/classRTSim_1_1RMScheduler__coll__graph.dot create mode 100644 latex/d2/d09/classRTSim_1_1RMScheduler__coll__graph.md5 create mode 100644 latex/d2/d0f/classRTSim_1_1TaskNotExecuting__inherit__graph.dot create mode 100644 latex/d2/d0f/classRTSim_1_1TaskNotExecuting__inherit__graph.md5 create mode 100644 latex/d2/d11/structCatch_1_1IRegistryHub.tex create mode 100644 latex/d2/d1b/classRTSim_1_1UniformCTGen.tex create mode 100644 latex/d2/d2a/classRTSim_1_1FixedInstr.tex create mode 100644 latex/d2/d2f/classCatch_1_1MethodTestCase__inherit__graph.dot create mode 100644 latex/d2/d2f/classCatch_1_1MethodTestCase__inherit__graph.md5 create mode 100644 latex/d2/d38/classRTSim_1_1FixedInstr__inherit__graph.dot create mode 100644 latex/d2/d38/classRTSim_1_1FixedInstr__inherit__graph.md5 create mode 100644 latex/d2/d3c/structCatch_1_1Totals__coll__graph.dot create mode 100644 latex/d2/d3c/structCatch_1_1Totals__coll__graph.md5 create mode 100644 latex/d2/d40/classCatch_1_1ValuesGenerator.tex create mode 100644 latex/d2/d46/classRTSim_1_1PeriodicTask__coll__graph.dot create mode 100644 latex/d2/d46/classRTSim_1_1PeriodicTask__coll__graph.md5 create mode 100644 latex/d2/d4c/classRTSim_1_1PreemptionStat__inherit__graph.dot create mode 100644 latex/d2/d4c/classRTSim_1_1PreemptionStat__inherit__graph.md5 create mode 100644 latex/d2/d4e/classRTSim_1_1EndDispatchEvt__coll__graph.dot create mode 100644 latex/d2/d4e/classRTSim_1_1EndDispatchEvt__coll__graph.md5 create mode 100644 latex/d2/d54/structCatch_1_1pluralise.tex create mode 100644 latex/d2/d55/classRTSim_1_1AbsTask__inherit__graph.dot create mode 100644 latex/d2/d55/classRTSim_1_1AbsTask__inherit__graph.md5 create mode 100644 latex/d2/d56/group__tasks.tex create mode 100644 latex/d2/d5b/classRTSim_1_1ConsumedPower__inherit__graph.dot create mode 100644 latex/d2/d5b/classRTSim_1_1ConsumedPower__inherit__graph.md5 create mode 100644 latex/d2/d60/structCatch_1_1IMutableRegistryHub.tex create mode 100644 latex/d2/d67/classRTSim_1_1TaskAlreadyExecuting.tex create mode 100644 latex/d2/d6c/classRTSim_1_1RTKernelExc__coll__graph.dot create mode 100644 latex/d2/d6c/classRTSim_1_1RTKernelExc__coll__graph.md5 create mode 100644 latex/d2/d70/classRTSim_1_1BWI.tex create mode 100644 latex/d2/d71/structCatch_1_1AssertionInfo.tex create mode 100644 latex/d2/d7c/classCatch_1_1TagExtracter.tex create mode 100644 latex/d2/d7e/classRTSim_1_1BWI__inherit__graph.dot create mode 100644 latex/d2/d7e/classRTSim_1_1BWI__inherit__graph.md5 create mode 100644 latex/d2/d7e/structCatch_1_1MessageBuilder.tex create mode 100644 latex/d2/d7f/classRTSim_1_1JSONTrace.tex create mode 100644 latex/d2/d82/classCatch_1_1AssertionResult__coll__graph.dot create mode 100644 latex/d2/d82/classCatch_1_1AssertionResult__coll__graph.md5 create mode 100644 latex/d2/d8d/classRTSim_1_1TraceArrEvent__coll__graph.dot create mode 100644 latex/d2/d8d/classRTSim_1_1TraceArrEvent__coll__graph.md5 create mode 100644 latex/d2/d95/classRTSim_1_1TaskEvt.tex create mode 100644 latex/d2/da3/classRTSim_1_1UtilizationStat.tex create mode 100644 latex/d2/da4/classCatch_1_1Detail_1_1Approx.tex create mode 100644 latex/d2/da4/classRTSim_1_1MinCTGen__inherit__graph.dot create mode 100644 latex/d2/da4/classRTSim_1_1MinCTGen__inherit__graph.md5 create mode 100644 latex/d2/da7/classRTSim_1_1ConsumedPower__coll__graph.dot create mode 100644 latex/d2/da7/classRTSim_1_1ConsumedPower__coll__graph.md5 create mode 100644 latex/d2/db2/structCatch_1_1Detail_1_1StringMakerBase.tex create mode 100644 latex/d2/db7/classCatch_1_1Matchers_1_1Impl_1_1Generic_1_1AllOf__coll__graph.dot create mode 100644 latex/d2/db7/classCatch_1_1Matchers_1_1Impl_1_1Generic_1_1AllOf__coll__graph.md5 create mode 100644 latex/d2/db7/classRTSim_1_1ModeOutOfIndex.tex create mode 100644 latex/d2/db9/classRTSim_1_1TaskAlreadyActive.tex create mode 100644 latex/d2/dc0/structCatch_1_1StringMaker.tex create mode 100644 latex/d2/dc5/structCatch_1_1IReporterRegistry.tex create mode 100644 latex/d2/dc7/namespaceRTSim.tex create mode 100644 latex/d2/dc8/classRTSim_1_1TracePowerConsumption.tex create mode 100644 latex/d2/de1/classRTSim_1_1SavedPower.tex create mode 100644 latex/d2/de6/classCatch_1_1ExpressionLhs.tex create mode 100644 latex/d2/dec/classCatch_1_1Matchers_1_1Impl_1_1Generic_1_1AnyOf__coll__graph.dot create mode 100644 latex/d2/dec/classCatch_1_1Matchers_1_1Impl_1_1Generic_1_1AnyOf__coll__graph.md5 create mode 100644 latex/d2/df3/classRTSim_1_1CBServer.tex create mode 100644 latex/d2/df9/classRTSim_1_1TraceEvent.tex create mode 100644 latex/d2/dfc/classRTSim_1_1ThreInstr.tex create mode 100644 latex/d3/d00/classRTSim_1_1Interrupt__inherit__graph.dot create mode 100644 latex/d3/d00/classRTSim_1_1Interrupt__inherit__graph.md5 create mode 100644 latex/d3/d03/structCatch_1_1IContext__inherit__graph.dot create mode 100644 latex/d3/d03/structCatch_1_1IContext__inherit__graph.md5 create mode 100644 latex/d3/d04/classRTSim_1_1AbsRTTask.tex create mode 100644 latex/d3/d08/structCatch_1_1StreamingReporterBase__coll__graph.dot create mode 100644 latex/d3/d08/structCatch_1_1StreamingReporterBase__coll__graph.md5 create mode 100644 latex/d3/d14/classRTSim_1_1PollingServer__coll__graph.dot create mode 100644 latex/d3/d14/classRTSim_1_1PollingServer__coll__graph.md5 create mode 100644 latex/d3/d14/structCatch_1_1IConfig__coll__graph.dot create mode 100644 latex/d3/d14/structCatch_1_1IConfig__coll__graph.md5 create mode 100644 latex/d3/d16/classRTSim_1_1TraceDlineSetEvent__inherit__graph.dot create mode 100644 latex/d3/d16/classRTSim_1_1TraceDlineSetEvent__inherit__graph.md5 create mode 100644 latex/d3/d17/classRTSim_1_1EndEvt__inherit__graph.dot create mode 100644 latex/d3/d17/classRTSim_1_1EndEvt__inherit__graph.md5 create mode 100644 latex/d3/d21/classRTSim_1_1FixedInstr__coll__graph.dot create mode 100644 latex/d3/d21/classRTSim_1_1FixedInstr__coll__graph.md5 create mode 100644 latex/d3/d2b/classRTSim_1_1EndInstrEvt.tex create mode 100644 latex/d3/d2e/classRTSim_1_1SparePot_1_1SparePotExc.tex create mode 100644 latex/d3/d38/classRTSim_1_1GlobalPreemptionStat__inherit__graph.dot create mode 100644 latex/d3/d38/classRTSim_1_1GlobalPreemptionStat__inherit__graph.md5 create mode 100644 latex/d3/d43/structCatch_1_1IStreamingReporter__coll__graph.dot create mode 100644 latex/d3/d43/structCatch_1_1IStreamingReporter__coll__graph.md5 create mode 100644 latex/d3/d51/classRTSim_1_1GlobalPreemptionStat__coll__graph.dot create mode 100644 latex/d3/d51/classRTSim_1_1GlobalPreemptionStat__coll__graph.md5 create mode 100644 latex/d3/d54/classRTSim_1_1GrubSupervisor__inherit__graph.dot create mode 100644 latex/d3/d54/classRTSim_1_1GrubSupervisor__inherit__graph.md5 create mode 100644 latex/d3/d60/classCatch_1_1TagParser__inherit__graph.dot create mode 100644 latex/d3/d60/classCatch_1_1TagParser__inherit__graph.md5 create mode 100644 latex/d3/d66/classRTSim_1_1UniformIATGen.tex create mode 100644 latex/d3/d67/classRTSim_1_1FakeArrEvt.tex create mode 100644 latex/d3/d71/classRTSim_1_1ExecInstr__coll__graph.dot create mode 100644 latex/d3/d71/classRTSim_1_1ExecInstr__coll__graph.md5 create mode 100644 latex/d3/d73/classRTSim_1_1WrongParameterSize.tex create mode 100644 latex/d3/d7b/structCatch_1_1Internal_1_1Evaluator_3_01T1_00_01T2_00_01IsGreaterThanOrEqualTo_01_4.tex create mode 100644 latex/d3/d84/classRTSim_1_1EmptyTask__coll__graph.dot create mode 100644 latex/d3/d84/classRTSim_1_1EmptyTask__coll__graph.md5 create mode 100644 latex/d3/d85/classRTSim_1_1EmptyTask.tex create mode 100644 latex/d3/d94/classRTSim_1_1RandomRTTaskSetFactory__inherit__graph.dot create mode 100644 latex/d3/d94/classRTSim_1_1RandomRTTaskSetFactory__inherit__graph.md5 create mode 100644 latex/d3/d94/classRTSim_1_1TaskNotActive.tex create mode 100644 latex/d3/d9c/classRTSim_1_1Desc.tex create mode 100644 latex/d3/db5/classRTSim_1_1Server__coll__graph.dot create mode 100644 latex/d3/db5/classRTSim_1_1Server__coll__graph.md5 create mode 100644 latex/d3/db9/classRTSim_1_1ServerExc__coll__graph.dot create mode 100644 latex/d3/db9/classRTSim_1_1ServerExc__coll__graph.md5 create mode 100644 latex/d3/dbb/classRTSim_1_1SchedPoint_1_1SchedPointExc__inherit__graph.dot create mode 100644 latex/d3/dbb/classRTSim_1_1SchedPoint_1_1SchedPointExc__inherit__graph.md5 create mode 100644 latex/d3/dbc/classRTSim_1_1TaskModel.tex create mode 100644 latex/d3/dbd/classRTSim_1_1ConsumedPower.tex create mode 100644 latex/d3/dc9/classRTSim_1_1AbstractGen__coll__graph.dot create mode 100644 latex/d3/dc9/classRTSim_1_1AbstractGen__coll__graph.md5 create mode 100644 latex/d3/dd3/classRTSim_1_1GlobalPreemptionStat.tex create mode 100644 latex/d3/ddf/structCatch_1_1Detail_1_1BorgType.tex create mode 100644 latex/d3/deb/classRTSim_1_1NoSuchInstr.tex create mode 100644 latex/d3/df1/classRTSim_1_1PreemptionStat.tex create mode 100644 latex/d3/df3/classRTSim_1_1SchedInstr__coll__graph.dot create mode 100644 latex/d3/df3/classRTSim_1_1SchedInstr__coll__graph.md5 create mode 100644 latex/d3/dfc/classRTSim_1_1DlineEquPeriodDTGen__coll__graph.dot create mode 100644 latex/d3/dfc/classRTSim_1_1DlineEquPeriodDTGen__coll__graph.md5 create mode 100644 latex/d4/d00/classRTSim_1_1MissCount.tex create mode 100644 latex/d4/d17/structCatch_1_1IContext.tex create mode 100644 latex/d4/d24/classRTSim_1_1uniformCPUFactory__inherit__graph.dot create mode 100644 latex/d4/d24/classRTSim_1_1uniformCPUFactory__inherit__graph.md5 create mode 100644 latex/d4/d2b/classRTSim_1_1RTKernel__inherit__graph.dot create mode 100644 latex/d4/d2b/classRTSim_1_1RTKernel__inherit__graph.md5 create mode 100644 latex/d4/d2e/classRTSim_1_1PeriodicTask.tex create mode 100644 latex/d4/d31/structCatch_1_1TestFailureException.tex create mode 100644 latex/d4/d34/classRTSim_1_1TraceWaitEvent__inherit__graph.dot create mode 100644 latex/d4/d34/classRTSim_1_1TraceWaitEvent__inherit__graph.md5 create mode 100644 latex/d4/d45/classRTSim_1_1IATGen__coll__graph.dot create mode 100644 latex/d4/d45/classRTSim_1_1IATGen__coll__graph.md5 create mode 100644 latex/d4/d48/classRTSim_1_1CapacityTimer__coll__graph.dot create mode 100644 latex/d4/d48/classRTSim_1_1CapacityTimer__coll__graph.md5 create mode 100644 latex/d4/d4d/classRTSim_1_1Instr__inherit__graph.dot create mode 100644 latex/d4/d4d/classRTSim_1_1Instr__inherit__graph.md5 create mode 100644 latex/d4/d57/classRTSim_1_1FakeArrEvt__inherit__graph.dot create mode 100644 latex/d4/d57/classRTSim_1_1FakeArrEvt__inherit__graph.md5 create mode 100644 latex/d4/d61/classRTSim_1_1GrubSupervisor.tex create mode 100644 latex/d4/d63/classCatch_1_1Stream.tex create mode 100644 latex/d4/d68/classRTSim_1_1Timer.tex create mode 100644 latex/d4/d6b/classRTSim_1_1JavaTrace.tex create mode 100644 latex/d4/d7e/structCatch_1_1SectionInfo.tex create mode 100644 latex/d4/d84/classRTSim_1_1TaskAlreadyActive__coll__graph.dot create mode 100644 latex/d4/d84/classRTSim_1_1TaskAlreadyActive__coll__graph.md5 create mode 100644 latex/d4/d90/classRTSim_1_1absCPUFactory.tex create mode 100644 latex/d4/d98/classRTSim_1_1MinCTGen.tex create mode 100644 latex/d4/da7/classRTSim_1_1AbstractFeedbackModule__coll__graph.dot create mode 100644 latex/d4/da7/classRTSim_1_1AbstractFeedbackModule__coll__graph.md5 create mode 100644 latex/d4/db3/classRTSim_1_1AbsKernel__inherit__graph.dot create mode 100644 latex/d4/db3/classRTSim_1_1AbsKernel__inherit__graph.md5 create mode 100644 latex/d4/dba/classRTSim_1_1AbsRTTask__inherit__graph.dot create mode 100644 latex/d4/dba/classRTSim_1_1AbsRTTask__inherit__graph.md5 create mode 100644 latex/d4/dc3/classRTSim_1_1Interrupt__coll__graph.dot create mode 100644 latex/d4/dc3/classRTSim_1_1Interrupt__coll__graph.md5 create mode 100644 latex/d4/dc4/classRTSim_1_1SignalInstr.tex create mode 100644 latex/d4/dcf/classRTSim_1_1WaitEvt__coll__graph.dot create mode 100644 latex/d4/dcf/classRTSim_1_1WaitEvt__coll__graph.md5 create mode 100644 latex/d4/dd2/classCatch_1_1StreamBufImpl__inherit__graph.dot create mode 100644 latex/d4/dd2/classCatch_1_1StreamBufImpl__inherit__graph.md5 create mode 100644 latex/d4/dde/classRTSim_1_1CapacityTimer.tex create mode 100644 latex/d4/de1/classRTSim_1_1Server.tex create mode 100644 latex/d4/de6/structCatch_1_1IGenerator__inherit__graph.dot create mode 100644 latex/d4/de6/structCatch_1_1IGenerator__inherit__graph.md5 create mode 100644 latex/d4/dec/structCatch_1_1IGeneratorInfo.tex create mode 100644 latex/d4/dfd/classRTSim_1_1SporadicServer__inherit__graph.dot create mode 100644 latex/d4/dfd/classRTSim_1_1SporadicServer__inherit__graph.md5 create mode 100644 latex/d5/d05/classRTSim_1_1ConstCTGen.tex create mode 100644 latex/d5/d07/classRTSim_1_1EDFModel__coll__graph.dot create mode 100644 latex/d5/d07/classRTSim_1_1EDFModel__coll__graph.md5 create mode 100644 latex/d5/d09/classRTSim_1_1TraceDlineMissEvent__coll__graph.dot create mode 100644 latex/d5/d09/classRTSim_1_1TraceDlineMissEvent__coll__graph.md5 create mode 100644 latex/d5/d0e/classRTSim_1_1FinishingTimeStat__inherit__graph.dot create mode 100644 latex/d5/d0e/classRTSim_1_1FinishingTimeStat__inherit__graph.md5 create mode 100644 latex/d5/d13/classRTSim_1_1SparePot.tex create mode 100644 latex/d5/d16/classRTSim_1_1WaitInstr__inherit__graph.dot create mode 100644 latex/d5/d16/classRTSim_1_1WaitInstr__inherit__graph.md5 create mode 100644 latex/d5/d1b/classRTSim_1_1FIFOScheduler__inherit__graph.dot create mode 100644 latex/d5/d1b/classRTSim_1_1FIFOScheduler__inherit__graph.md5 create mode 100644 latex/d5/d1d/structCatch_1_1Internal_1_1Evaluator_3_01T1_00_01T2_00_01IsEqualTo_01_4.tex create mode 100644 latex/d5/d1e/classRTSim_1_1SparePot__coll__graph.dot create mode 100644 latex/d5/d1e/classRTSim_1_1SparePot__coll__graph.md5 create mode 100644 latex/d5/d2f/classRTSim_1_1TaskModel_1_1TaskModelCmp.tex create mode 100644 latex/d5/d30/classCatch_1_1TagExpressionParser__coll__graph.dot create mode 100644 latex/d5/d30/classCatch_1_1TagExpressionParser__coll__graph.md5 create mode 100644 latex/d5/d38/classRTSim_1_1BeginDispatchEvt__inherit__graph.dot create mode 100644 latex/d5/d38/classRTSim_1_1BeginDispatchEvt__inherit__graph.md5 create mode 100644 latex/d5/d3f/classRTSim_1_1TaskStatExc.tex create mode 100644 latex/d5/d42/classRTSim_1_1KillEvt.tex create mode 100644 latex/d5/d44/classRTSim_1_1DispatchEvt__inherit__graph.dot create mode 100644 latex/d5/d44/classRTSim_1_1DispatchEvt__inherit__graph.md5 create mode 100644 latex/d5/d49/classRTSim_1_1NoSuchInstr__coll__graph.dot create mode 100644 latex/d5/d49/classRTSim_1_1NoSuchInstr__coll__graph.md5 create mode 100644 latex/d5/d51/classRTSim_1_1Scheduler__inherit__graph.dot create mode 100644 latex/d5/d51/classRTSim_1_1Scheduler__inherit__graph.md5 create mode 100644 latex/d5/d51/structCatch_1_1AssertionInfo__coll__graph.dot create mode 100644 latex/d5/d51/structCatch_1_1AssertionInfo__coll__graph.md5 create mode 100644 latex/d5/d5a/classRTSim_1_1TaskNotExecuting__coll__graph.dot create mode 100644 latex/d5/d5a/classRTSim_1_1TaskNotExecuting__coll__graph.md5 create mode 100644 latex/d5/d62/classRTSim_1_1OffsetGen.tex create mode 100644 latex/d5/d67/classRTSim_1_1UniformIATGen__coll__graph.dot create mode 100644 latex/d5/d67/classRTSim_1_1UniformIATGen__coll__graph.md5 create mode 100644 latex/d5/d6e/classRTSim_1_1DeschedEvt__coll__graph.dot create mode 100644 latex/d5/d6e/classRTSim_1_1DeschedEvt__coll__graph.md5 create mode 100644 latex/d5/d7b/classRTSim_1_1SignalInstr__inherit__graph.dot create mode 100644 latex/d5/d7b/classRTSim_1_1SignalInstr__inherit__graph.md5 create mode 100644 latex/d5/d7d/classRTSim_1_1SchedPoint_1_1ChangeBudgetEvt.tex create mode 100644 latex/d5/d82/classRTSim_1_1CTGen__inherit__graph.dot create mode 100644 latex/d5/d82/classRTSim_1_1CTGen__inherit__graph.md5 create mode 100644 latex/d5/d8c/structCatch_1_1ResultWas.tex create mode 100644 latex/d5/d90/classCatch_1_1NotImplementedException__coll__graph.dot create mode 100644 latex/d5/d90/classCatch_1_1NotImplementedException__coll__graph.md5 create mode 100644 latex/d5/d90/classRTSim_1_1CBServer__coll__graph.dot create mode 100644 latex/d5/d90/classRTSim_1_1CBServer__coll__graph.md5 create mode 100644 latex/d5/d94/structCatch_1_1NameAndDesc.tex create mode 100644 latex/d5/d99/classRTSim_1_1Supervisor.tex create mode 100644 latex/d5/dae/classRTSim_1_1FCFSResManager__coll__graph.dot create mode 100644 latex/d5/dae/classRTSim_1_1FCFSResManager__coll__graph.md5 create mode 100644 latex/d5/dba/classCatch_1_1Option__inherit__graph.dot create mode 100644 latex/d5/dba/classCatch_1_1Option__inherit__graph.md5 create mode 100644 latex/d5/dbb/classCatch_1_1TestCaseFilter.tex create mode 100644 latex/d5/dc3/classCatch_1_1TestCaseFilters.tex create mode 100644 latex/d5/dca/classRTSim_1_1BeginDispatchMultiEvt__inherit__graph.dot create mode 100644 latex/d5/dca/classRTSim_1_1BeginDispatchMultiEvt__inherit__graph.md5 create mode 100644 latex/d5/dd4/classRTSim_1_1TraceDeschedEvent__inherit__graph.dot create mode 100644 latex/d5/dd4/classRTSim_1_1TraceDeschedEvent__inherit__graph.md5 create mode 100644 latex/d5/dd6/classCatch_1_1ValuesGenerator__coll__graph.dot create mode 100644 latex/d5/dd6/classCatch_1_1ValuesGenerator__coll__graph.md5 create mode 100644 latex/d5/de2/structCatch_1_1LazyStat__coll__graph.dot create mode 100644 latex/d5/de2/structCatch_1_1LazyStat__coll__graph.md5 create mode 100644 latex/d5/de5/classCatch_1_1ScopedMessage__coll__graph.dot create mode 100644 latex/d5/de5/classCatch_1_1ScopedMessage__coll__graph.md5 create mode 100644 latex/d5/dec/classRTSim_1_1RandomRTTaskSetFactory__coll__graph.dot create mode 100644 latex/d5/dec/classRTSim_1_1RandomRTTaskSetFactory__coll__graph.md5 create mode 100644 latex/d5/dee/structCatch_1_1IStreamingReporter.tex create mode 100644 latex/d5/df7/classRTSim_1_1BeginDispatchMultiEvt__coll__graph.dot create mode 100644 latex/d5/df7/classRTSim_1_1BeginDispatchMultiEvt__coll__graph.md5 create mode 100644 latex/d5/df7/structCatch_1_1IShared__inherit__graph.dot create mode 100644 latex/d5/df7/structCatch_1_1IShared__inherit__graph.md5 create mode 100644 latex/d5/dfc/structCatch_1_1IReporter__coll__graph.dot create mode 100644 latex/d5/dfc/structCatch_1_1IReporter__coll__graph.md5 create mode 100644 latex/d6/d0e/structCatch_1_1IRunner.tex create mode 100644 latex/d6/d13/classRTSim_1_1TraceDlineMissEvent.tex create mode 100644 latex/d6/d17/classRTSim_1_1TracePowerConsumption__inherit__graph.dot create mode 100644 latex/d6/d17/classRTSim_1_1TracePowerConsumption__inherit__graph.md5 create mode 100644 latex/d6/d1b/structCatch_1_1AssertionStats__coll__graph.dot create mode 100644 latex/d6/d1b/structCatch_1_1AssertionStats__coll__graph.md5 create mode 100644 latex/d6/d1f/structCatch_1_1IMutableContext__inherit__graph.dot create mode 100644 latex/d6/d1f/structCatch_1_1IMutableContext__inherit__graph.md5 create mode 100644 latex/d6/d22/classRTSim_1_1CTGen.tex create mode 100644 latex/d6/d24/classRTSim_1_1RRScheduler.tex create mode 100644 latex/d6/d25/structCatch_1_1Matchers_1_1Impl_1_1StdString_1_1EndsWith__inherit__graph.dot create mode 100644 latex/d6/d25/structCatch_1_1Matchers_1_1Impl_1_1StdString_1_1EndsWith__inherit__graph.md5 create mode 100644 latex/d6/d27/structCatch_1_1TestRunStats.tex create mode 100644 latex/d6/d38/structCatch_1_1ITestCase__inherit__graph.dot create mode 100644 latex/d6/d38/structCatch_1_1ITestCase__inherit__graph.md5 create mode 100644 latex/d6/d38/structCatch_1_1StringMaker_3_01T_01_5_01_4.tex create mode 100644 latex/d6/d40/classRTSim_1_1DispatchEvt__coll__graph.dot create mode 100644 latex/d6/d40/classRTSim_1_1DispatchEvt__coll__graph.md5 create mode 100644 latex/d6/d45/structCatch_1_1Matchers_1_1Impl_1_1StdString_1_1Contains__coll__graph.dot create mode 100644 latex/d6/d45/structCatch_1_1Matchers_1_1Impl_1_1StdString_1_1Contains__coll__graph.md5 create mode 100644 latex/d6/d46/classRTSim_1_1TardinessStat.tex create mode 100644 latex/d6/d48/classRTSim_1_1FinishingTimeStat__coll__graph.dot create mode 100644 latex/d6/d48/classRTSim_1_1FinishingTimeStat__coll__graph.md5 create mode 100644 latex/d6/d51/classRTSim_1_1MissCount__coll__graph.dot create mode 100644 latex/d6/d51/classRTSim_1_1MissCount__coll__graph.md5 create mode 100644 latex/d6/d60/classRTSim_1_1KernAlreadySet__coll__graph.dot create mode 100644 latex/d6/d60/classRTSim_1_1KernAlreadySet__coll__graph.md5 create mode 100644 latex/d6/d6a/classRTSim_1_1SchedRTA__coll__graph.dot create mode 100644 latex/d6/d6a/classRTSim_1_1SchedRTA__coll__graph.md5 create mode 100644 latex/d6/d6d/classCatch_1_1TagSet.tex create mode 100644 latex/d6/d6d/classRTSim_1_1WrongParameterSize__inherit__graph.dot create mode 100644 latex/d6/d6d/classRTSim_1_1WrongParameterSize__inherit__graph.md5 create mode 100644 latex/d6/d6e/structCatch_1_1IResultCapture.tex create mode 100644 latex/d6/d7c/classRTSim_1_1Timer__coll__graph.dot create mode 100644 latex/d6/d7c/classRTSim_1_1Timer__coll__graph.md5 create mode 100644 latex/d6/d85/structCatch_1_1Matchers_1_1Impl_1_1StdString_1_1StartsWith__coll__graph.dot create mode 100644 latex/d6/d85/structCatch_1_1Matchers_1_1Impl_1_1StdString_1_1StartsWith__coll__graph.md5 create mode 100644 latex/d6/d8a/structCatch_1_1Internal_1_1OperatorTraits_3_01IsLessThanOrEqualTo_01_4.tex create mode 100644 latex/d6/d8d/classRTSim_1_1SuspendInstr.tex create mode 100644 latex/d6/d8f/classRTSim_1_1BeginDispatchEvt.tex create mode 100644 latex/d6/d90/classSystem__coll__graph.dot create mode 100644 latex/d6/d90/classSystem__coll__graph.md5 create mode 100644 latex/d6/d99/classCatch_1_1CompositeGenerator.tex create mode 100644 latex/d6/d9d/classRTSim_1_1Scheduler.tex create mode 100644 latex/d6/da9/classRTSim_1_1RandomRTTaskSetFactory.tex create mode 100644 latex/d6/dab/classRTSim_1_1SchedIEvt__coll__graph.dot create mode 100644 latex/d6/dab/classRTSim_1_1SchedIEvt__coll__graph.md5 create mode 100644 latex/d6/dac/classCatch_1_1TagExtracter__coll__graph.dot create mode 100644 latex/d6/dac/classCatch_1_1TagExtracter__coll__graph.md5 create mode 100644 latex/d6/db2/classRTSim_1_1ArrEvt__inherit__graph.dot create mode 100644 latex/d6/db2/classRTSim_1_1ArrEvt__inherit__graph.md5 create mode 100644 latex/d6/db2/classRTSim_1_1SchedEvt__inherit__graph.dot create mode 100644 latex/d6/db2/classRTSim_1_1SchedEvt__inherit__graph.md5 create mode 100644 latex/d6/dc4/structStats__coll__graph.dot create mode 100644 latex/d6/dc4/structStats__coll__graph.md5 create mode 100644 latex/d6/dc5/classRTSim_1_1Timer__inherit__graph.dot create mode 100644 latex/d6/dc5/classRTSim_1_1Timer__inherit__graph.md5 create mode 100644 latex/d6/dc8/structCatch_1_1ITestCaseRegistry.tex create mode 100644 latex/d6/dcd/classCatch_1_1Matchers_1_1Impl_1_1Generic_1_1AnyOf.tex create mode 100644 latex/d6/dd4/classRTSim_1_1TraceWaitEvent__coll__graph.dot create mode 100644 latex/d6/dd4/classRTSim_1_1TraceWaitEvent__coll__graph.md5 create mode 100644 latex/d6/ddb/classCatch_1_1StreamBufBase__coll__graph.dot create mode 100644 latex/d6/ddb/classCatch_1_1StreamBufBase__coll__graph.md5 create mode 100644 latex/d6/ddb/structCatch_1_1CumulativeReporterBase_1_1SectionNode__coll__graph.dot create mode 100644 latex/d6/ddb/structCatch_1_1CumulativeReporterBase_1_1SectionNode__coll__graph.md5 create mode 100644 latex/d6/ddc/classRTSim_1_1TraceDeschedEvent__coll__graph.dot create mode 100644 latex/d6/ddc/classRTSim_1_1TraceDeschedEvent__coll__graph.md5 create mode 100644 latex/d6/df1/classRTSim_1_1Resource__coll__graph.dot create mode 100644 latex/d6/df1/classRTSim_1_1Resource__coll__graph.md5 create mode 100644 latex/d6/df4/classCatch_1_1TestCase.tex create mode 100644 latex/d6/df4/structRTSim_1_1SparePot_1_1server__struct__coll__graph.dot create mode 100644 latex/d6/df4/structRTSim_1_1SparePot_1_1server__struct__coll__graph.md5 create mode 100644 latex/d7/d04/classRTSim_1_1SparePot_1_1ChangeBudgetEvt__coll__graph.dot create mode 100644 latex/d7/d04/classRTSim_1_1SparePot_1_1ChangeBudgetEvt__coll__graph.md5 create mode 100644 latex/d7/d07/classRTSim_1_1RandomTaskSetFactory_1_1Exc__coll__graph.dot create mode 100644 latex/d7/d07/classRTSim_1_1RandomTaskSetFactory_1_1Exc__coll__graph.md5 create mode 100644 latex/d7/d14/classRTSim_1_1TraceDlineMissEvent__inherit__graph.dot create mode 100644 latex/d7/d14/classRTSim_1_1TraceDlineMissEvent__inherit__graph.md5 create mode 100644 latex/d7/d15/classRTSim_1_1TraceDeschedEvent.tex create mode 100644 latex/d7/d1a/classRTSim_1_1TraceDlineSetEvent.tex create mode 100644 latex/d7/d29/classRTSim_1_1EndEvt__coll__graph.dot create mode 100644 latex/d7/d29/classRTSim_1_1EndEvt__coll__graph.md5 create mode 100644 latex/d7/d2c/classCatch_1_1TagExpressionParser.tex create mode 100644 latex/d7/d37/structCatch_1_1MessageInfo.tex create mode 100644 latex/d7/d38/structCatch_1_1CumulativeReporterBase__coll__graph.dot create mode 100644 latex/d7/d38/structCatch_1_1CumulativeReporterBase__coll__graph.md5 create mode 100644 latex/d7/d3c/structCatch_1_1Detail_1_1StringMakerBase_3_01true_01_4.tex create mode 100644 latex/d7/d3d/classRTSim_1_1TraceArrEvent.tex create mode 100644 latex/d7/d3d/structCatch_1_1GroupInfo.tex create mode 100644 latex/d7/d43/classRTSim_1_1TraceSignalEvent.tex create mode 100644 latex/d7/d49/classRTSim_1_1SparePot_1_1SparePotExc__coll__graph.dot create mode 100644 latex/d7/d49/classRTSim_1_1SparePot_1_1SparePotExc__coll__graph.md5 create mode 100644 latex/d7/d58/classRTSim_1_1TraceNameEvent.tex create mode 100644 latex/d7/d5e/classRTSim_1_1DTGen__inherit__graph.dot create mode 100644 latex/d7/d5e/classRTSim_1_1DTGen__inherit__graph.md5 create mode 100644 latex/d7/d67/classRTSim_1_1MaxIATGen.tex create mode 100644 latex/d7/d69/classRTSim_1_1SchedPoint.tex create mode 100644 latex/d7/d76/classRTSim_1_1FeedbackModuleARSim__coll__graph.dot create mode 100644 latex/d7/d76/classRTSim_1_1FeedbackModuleARSim__coll__graph.md5 create mode 100644 latex/d7/d82/structCatch_1_1TestGroupStats__coll__graph.dot create mode 100644 latex/d7/d82/structCatch_1_1TestGroupStats__coll__graph.md5 create mode 100644 latex/d7/d83/classRTSim_1_1UtilizationStat__inherit__graph.dot create mode 100644 latex/d7/d83/classRTSim_1_1UtilizationStat__inherit__graph.md5 create mode 100644 latex/d7/d91/structCatch_1_1IExceptionTranslatorRegistry.tex create mode 100644 latex/d7/d91/structCatch_1_1SharedImpl.tex create mode 100644 latex/d7/d98/structCatch_1_1SectionStats__coll__graph.dot create mode 100644 latex/d7/d98/structCatch_1_1SectionStats__coll__graph.md5 create mode 100644 latex/d7/d9c/classRTSim_1_1RRScheduler_1_1RRModel__coll__graph.dot create mode 100644 latex/d7/d9c/classRTSim_1_1RRScheduler_1_1RRModel__coll__graph.md5 create mode 100644 latex/d7/da2/structCatch_1_1Matchers_1_1Impl_1_1StdString_1_1Contains__inherit__graph.dot create mode 100644 latex/d7/da2/structCatch_1_1Matchers_1_1Impl_1_1StdString_1_1Contains__inherit__graph.md5 create mode 100644 latex/d7/da4/structCatch_1_1CumulativeReporterBase_1_1SectionNode.tex create mode 100644 latex/d7/dad/structCatch_1_1ReporterPreferences.tex create mode 100644 latex/d7/dc0/classRTSim_1_1EDFModel__inherit__graph.dot create mode 100644 latex/d7/dc0/classRTSim_1_1EDFModel__inherit__graph.md5 create mode 100644 latex/d7/dc7/classCatch_1_1Option.tex create mode 100644 latex/d7/dcf/classRTSim_1_1ConstIATGen__inherit__graph.dot create mode 100644 latex/d7/dcf/classRTSim_1_1ConstIATGen__inherit__graph.md5 create mode 100644 latex/d7/dd1/classRTSim_1_1RRScheduler_1_1RRSchedExc.tex create mode 100644 latex/d7/dda/classRTSim_1_1RandomDTGen__coll__graph.dot create mode 100644 latex/d7/dda/classRTSim_1_1RandomDTGen__coll__graph.md5 create mode 100644 latex/d7/ddc/structCatch_1_1AssertionResultData.tex create mode 100644 latex/d7/ddc/structCatch_1_1IReporter__inherit__graph.dot create mode 100644 latex/d7/ddc/structCatch_1_1IReporter__inherit__graph.md5 create mode 100644 latex/d7/de7/structCatch_1_1IStreamingReporter__inherit__graph.dot create mode 100644 latex/d7/de7/structCatch_1_1IStreamingReporter__inherit__graph.md5 create mode 100644 latex/d7/df3/classCatch_1_1Matchers_1_1Impl_1_1Generic_1_1AllOf__inherit__graph.dot create mode 100644 latex/d7/df3/classCatch_1_1Matchers_1_1Impl_1_1Generic_1_1AllOf__inherit__graph.md5 create mode 100644 latex/d7/dfd/classCatch_1_1ExceptionTranslatorRegistrar.tex create mode 100644 latex/d7/dfe/classCatch_1_1TagExpression.tex create mode 100644 latex/d7/dff/structCatch_1_1Matchers_1_1Impl_1_1StdString_1_1Equals__inherit__graph.dot create mode 100644 latex/d7/dff/structCatch_1_1Matchers_1_1Impl_1_1StdString_1_1Equals__inherit__graph.md5 create mode 100644 latex/d8/d0b/classRTSim_1_1MinCTGen__coll__graph.dot create mode 100644 latex/d8/d0b/classRTSim_1_1MinCTGen__coll__graph.md5 create mode 100644 latex/d8/d12/classRTSim_1_1DlineSetEvt__coll__graph.dot create mode 100644 latex/d8/d12/classRTSim_1_1DlineSetEvt__coll__graph.md5 create mode 100644 latex/d8/d18/classCatch_1_1StreamBufImpl__coll__graph.dot create mode 100644 latex/d8/d18/classCatch_1_1StreamBufImpl__coll__graph.md5 create mode 100644 latex/d8/d1e/classRTSim_1_1SporadicServer.tex create mode 100644 latex/d8/d20/classRTSim_1_1WrongParameterSize__coll__graph.dot create mode 100644 latex/d8/d20/classRTSim_1_1WrongParameterSize__coll__graph.md5 create mode 100644 latex/d8/d30/structRTSim_1_1SchedRTA_1_1ServerInfo__coll__graph.dot create mode 100644 latex/d8/d30/structRTSim_1_1SchedRTA_1_1ServerInfo__coll__graph.md5 create mode 100644 latex/d8/d38/classCatch_1_1Matchers_1_1Impl_1_1Generic_1_1AnyOf__inherit__graph.dot create mode 100644 latex/d8/d38/classCatch_1_1Matchers_1_1Impl_1_1Generic_1_1AnyOf__inherit__graph.md5 create mode 100644 latex/d8/d3a/classRTSim_1_1Resource.tex create mode 100644 latex/d8/d44/classCatch_1_1Timer.tex create mode 100644 latex/d8/d44/classRTSim_1_1FCFSResManager.tex create mode 100644 latex/d8/d44/classRTSim_1_1Instr__coll__graph.dot create mode 100644 latex/d8/d44/classRTSim_1_1Instr__coll__graph.md5 create mode 100644 latex/d8/d57/structCatch_1_1TestRunStats__coll__graph.dot create mode 100644 latex/d8/d57/structCatch_1_1TestRunStats__coll__graph.md5 create mode 100644 latex/d8/d59/structRTSim_1_1cpulevel.tex create mode 100644 latex/d8/d5b/classRTSim_1_1SporadicDTGen__coll__graph.dot create mode 100644 latex/d8/d5b/classRTSim_1_1SporadicDTGen__coll__graph.md5 create mode 100644 latex/d8/d62/structCatch_1_1ResultDisposition.tex create mode 100644 latex/d8/d7e/classCatch_1_1NotImplementedException__inherit__graph.dot create mode 100644 latex/d8/d7e/classCatch_1_1NotImplementedException__inherit__graph.md5 create mode 100644 latex/d8/d7e/classRTSim_1_1DeadEvt.tex create mode 100644 latex/d8/d82/structCatch_1_1Matchers_1_1Impl_1_1StdString_1_1Equals__coll__graph.dot create mode 100644 latex/d8/d82/structCatch_1_1Matchers_1_1Impl_1_1StdString_1_1Equals__coll__graph.md5 create mode 100644 latex/d8/d86/classRTSim_1_1TaskModel__inherit__graph.dot create mode 100644 latex/d8/d86/classRTSim_1_1TaskModel__inherit__graph.md5 create mode 100644 latex/d8/d8d/structCatch_1_1CumulativeReporterBase_1_1SectionNode__inherit__graph.dot create mode 100644 latex/d8/d8d/structCatch_1_1CumulativeReporterBase_1_1SectionNode__inherit__graph.md5 create mode 100644 latex/d8/d95/classRTSim_1_1ConstIATGen__coll__graph.dot create mode 100644 latex/d8/d95/classRTSim_1_1ConstIATGen__coll__graph.md5 create mode 100644 latex/d8/d99/classRTSim_1_1BeginDispatchEvt__coll__graph.dot create mode 100644 latex/d8/d99/classRTSim_1_1BeginDispatchEvt__coll__graph.md5 create mode 100644 latex/d8/da0/classRTSim_1_1TraceEndEvent.tex create mode 100644 latex/d8/da2/classRTSim_1_1TraceArrEvent__inherit__graph.dot create mode 100644 latex/d8/da2/classRTSim_1_1TraceArrEvent__inherit__graph.md5 create mode 100644 latex/d8/db0/classRTSim_1_1Task.tex create mode 100644 latex/d8/db2/classRTSim_1_1FPScheduler_1_1FPModel__inherit__graph.dot create mode 100644 latex/d8/db2/classRTSim_1_1FPScheduler_1_1FPModel__inherit__graph.md5 create mode 100644 latex/d8/db5/classRTSim_1_1absCPUFactory__inherit__graph.dot create mode 100644 latex/d8/db5/classRTSim_1_1absCPUFactory__inherit__graph.md5 create mode 100644 latex/d8/dbd/classRTSim_1_1FeedbackModuleARSim.tex create mode 100644 latex/d8/dc7/structCatch_1_1Internal_1_1OperatorTraits_3_01IsLessThan_01_4.tex create mode 100644 latex/d8/dcd/classRTSim_1_1EndDispatchEvt__inherit__graph.dot create mode 100644 latex/d8/dcd/classRTSim_1_1EndDispatchEvt__inherit__graph.md5 create mode 100644 latex/d8/ddf/structCatch_1_1TestCaseInfo__coll__graph.dot create mode 100644 latex/d8/ddf/structCatch_1_1TestCaseInfo__coll__graph.md5 create mode 100644 latex/d8/dfa/classRTSim_1_1ThreInstr__inherit__graph.dot create mode 100644 latex/d8/dfa/classRTSim_1_1ThreInstr__inherit__graph.md5 create mode 100644 latex/d8/dfb/classRTSim_1_1ServerExc__inherit__graph.dot create mode 100644 latex/d8/dfb/classRTSim_1_1ServerExc__inherit__graph.md5 create mode 100644 latex/d9/d00/structCatch_1_1CumulativeReporterBase__inherit__graph.dot create mode 100644 latex/d9/d00/structCatch_1_1CumulativeReporterBase__inherit__graph.md5 create mode 100644 latex/d9/d01/classRTSim_1_1RRScheduler_1_1RRSchedExc__coll__graph.dot create mode 100644 latex/d9/d01/classRTSim_1_1RRScheduler_1_1RRSchedExc__coll__graph.md5 create mode 100644 latex/d9/d10/classRTSim_1_1RandomTaskSetFactory_1_1Exc__inherit__graph.dot create mode 100644 latex/d9/d10/classRTSim_1_1RandomTaskSetFactory_1_1Exc__inherit__graph.md5 create mode 100644 latex/d9/d11/classRTSim_1_1TraceCPUEvent.tex create mode 100644 latex/d9/d14/classCatch_1_1StreamBufBase.tex create mode 100644 latex/d9/d1c/classRTSim_1_1RandomOffsetGen.tex create mode 100644 latex/d9/d24/classRTSim_1_1RTModel.tex create mode 100644 latex/d9/d24/namespaceRTSim_1_1____sched__stub.tex create mode 100644 latex/d9/d25/classCatch_1_1BetweenGenerator__inherit__graph.dot create mode 100644 latex/d9/d25/classCatch_1_1BetweenGenerator__inherit__graph.md5 create mode 100644 latex/d9/d25/structCatch_1_1Matchers_1_1Impl_1_1Matcher__inherit__graph.dot create mode 100644 latex/d9/d25/structCatch_1_1Matchers_1_1Impl_1_1Matcher__inherit__graph.md5 create mode 100644 latex/d9/d2a/classRTSim_1_1FPScheduler_1_1FPModel.tex create mode 100644 latex/d9/d2b/classRTSim_1_1Supervisor__inherit__graph.dot create mode 100644 latex/d9/d2b/classRTSim_1_1Supervisor__inherit__graph.md5 create mode 100644 latex/d9/d2d/classRTSim_1_1EndDispatchMultiEvt__coll__graph.dot create mode 100644 latex/d9/d2d/classRTSim_1_1EndDispatchMultiEvt__coll__graph.md5 create mode 100644 latex/d9/d2d/classRTSim_1_1TraceCPUEvent__inherit__graph.dot create mode 100644 latex/d9/d2d/classRTSim_1_1TraceCPUEvent__inherit__graph.md5 create mode 100644 latex/d9/d30/classRTSim_1_1SchedEvt__coll__graph.dot create mode 100644 latex/d9/d30/classRTSim_1_1SchedEvt__coll__graph.md5 create mode 100644 latex/d9/d36/structCatch_1_1SharedImpl__inherit__graph.dot create mode 100644 latex/d9/d36/structCatch_1_1SharedImpl__inherit__graph.md5 create mode 100644 latex/d9/d3b/classRTSim_1_1GrubExc__inherit__graph.dot create mode 100644 latex/d9/d3b/classRTSim_1_1GrubExc__inherit__graph.md5 create mode 100644 latex/d9/d47/structCatch_1_1ITestCase__coll__graph.dot create mode 100644 latex/d9/d47/structCatch_1_1ITestCase__coll__graph.md5 create mode 100644 latex/d9/d4c/classRTSim_1_1MinIATGen__inherit__graph.dot create mode 100644 latex/d9/d4c/classRTSim_1_1MinIATGen__inherit__graph.md5 create mode 100644 latex/d9/d4d/structCatch_1_1Matchers_1_1Impl_1_1StdString_1_1StartsWith.tex create mode 100644 latex/d9/d50/classRTSim_1_1FIFOScheduler__coll__graph.dot create mode 100644 latex/d9/d50/classRTSim_1_1FIFOScheduler__coll__graph.md5 create mode 100644 latex/d9/d50/classRTSim_1_1SchedPoint__coll__graph.dot create mode 100644 latex/d9/d50/classRTSim_1_1SchedPoint__coll__graph.md5 create mode 100644 latex/d9/d57/classRTSim_1_1TraceIdleEvent__inherit__graph.dot create mode 100644 latex/d9/d57/classRTSim_1_1TraceIdleEvent__inherit__graph.md5 create mode 100644 latex/d9/d57/structCatch_1_1Matchers_1_1Impl_1_1StdString_1_1Contains.tex create mode 100644 latex/d9/d60/classCatch_1_1TestCase__coll__graph.dot create mode 100644 latex/d9/d60/classCatch_1_1TestCase__coll__graph.md5 create mode 100644 latex/d9/d74/classRTSim_1_1ModeOutOfIndex__coll__graph.dot create mode 100644 latex/d9/d74/classRTSim_1_1ModeOutOfIndex__coll__graph.md5 create mode 100644 latex/d9/d76/classCatch_1_1Matchers_1_1Impl_1_1Generic_1_1AllOf.tex create mode 100644 latex/d9/d77/classRTSim_1_1RRScheduler__inherit__graph.dot create mode 100644 latex/d9/d77/classRTSim_1_1RRScheduler__inherit__graph.md5 create mode 100644 latex/d9/d7e/structCatch_1_1Internal_1_1OperatorTraits_3_01IsEqualTo_01_4.tex create mode 100644 latex/d9/d8c/structCatch_1_1IExceptionTranslator.tex create mode 100644 latex/d9/d8f/structCatch_1_1Matchers_1_1Impl_1_1StdString_1_1EndsWith__coll__graph.dot create mode 100644 latex/d9/d8f/structCatch_1_1Matchers_1_1Impl_1_1StdString_1_1EndsWith__coll__graph.md5 create mode 100644 latex/d9/daa/classRTSim_1_1SparePot_1_1ChangeBudgetEvt.tex create mode 100644 latex/d9/daa/classRTSim_1_1TraceIdleEvent__coll__graph.dot create mode 100644 latex/d9/daa/classRTSim_1_1TraceIdleEvent__coll__graph.md5 create mode 100644 latex/d9/dae/classRTSim_1_1AbsRTTask__coll__graph.dot create mode 100644 latex/d9/dae/classRTSim_1_1AbsRTTask__coll__graph.md5 create mode 100644 latex/d9/db1/structCatch_1_1IfFilterMatches.tex create mode 100644 latex/d9/db5/classCatch_1_1Internal_1_1Evaluator.tex create mode 100644 latex/d9/db7/classCatch_1_1NotImplementedException.tex create mode 100644 latex/d9/db7/classRTSim_1_1TaskAlreadyExecuting__inherit__graph.dot create mode 100644 latex/d9/db7/classRTSim_1_1TaskAlreadyExecuting__inherit__graph.md5 create mode 100644 latex/d9/db9/classRTSim_1_1KernAlreadySet.tex create mode 100644 latex/d9/dc1/classRTSim_1_1SavedPower__inherit__graph.dot create mode 100644 latex/d9/dc1/classRTSim_1_1SavedPower__inherit__graph.md5 create mode 100644 latex/d9/dd6/classRTSim_1_1AbstractFeedbackModule.tex create mode 100644 latex/d9/ddd/classRTSim_1_1EndEvt.tex create mode 100644 latex/d9/de5/classCatch_1_1NonCopyable__inherit__graph.dot create mode 100644 latex/d9/de5/classCatch_1_1NonCopyable__inherit__graph.md5 create mode 100644 latex/d9/df1/classRTSim_1_1TaskAlreadyActive__inherit__graph.dot create mode 100644 latex/d9/df1/classRTSim_1_1TaskAlreadyActive__inherit__graph.md5 create mode 100644 latex/d9/df6/classRTSim_1_1DTGen.tex create mode 100644 latex/da/d06/classRTSim_1_1SuperCBS.tex create mode 100644 latex/da/d0b/classRTSim_1_1BWI__coll__graph.dot create mode 100644 latex/da/d0b/classRTSim_1_1BWI__coll__graph.md5 create mode 100644 latex/da/d0c/classRTSim_1_1InstrExc__inherit__graph.dot create mode 100644 latex/da/d0c/classRTSim_1_1InstrExc__inherit__graph.md5 create mode 100644 latex/da/d10/classCatch_1_1Section.tex create mode 100644 latex/da/d10/classRTSim_1_1MissPercentage__inherit__graph.dot create mode 100644 latex/da/d10/classRTSim_1_1MissPercentage__inherit__graph.md5 create mode 100644 latex/da/d14/classCatch_1_1Tag.tex create mode 100644 latex/da/d14/classRTSim_1_1CPU__inherit__graph.dot create mode 100644 latex/da/d14/classRTSim_1_1CPU__inherit__graph.md5 create mode 100644 latex/da/d14/structCatch_1_1Matchers_1_1Impl_1_1StdString_1_1Equals.tex create mode 100644 latex/da/d19/classRTSim_1_1PeriodicTimer.tex create mode 100644 latex/da/d24/classRTSim_1_1RandomDTGen.tex create mode 100644 latex/da/d27/classRTSim_1_1RTSchedExc.tex create mode 100644 latex/da/d3b/structCatch_1_1Internal_1_1Evaluator_3_01T1_00_01T2_00_01IsGreaterThan_01_4.tex create mode 100644 latex/da/d3c/structCatch_1_1Internal_1_1Evaluator_3_01T1_00_01T2_00_01IsLessThan_01_4.tex create mode 100644 latex/da/d3e/classRTSim_1_1RTKernel.tex create mode 100644 latex/da/d4b/classRTSim_1_1UniformCTGen__inherit__graph.dot create mode 100644 latex/da/d4b/classRTSim_1_1UniformCTGen__inherit__graph.md5 create mode 100644 latex/da/d5b/classRTSim_1_1MRTKernel__coll__graph.dot create mode 100644 latex/da/d5b/classRTSim_1_1MRTKernel__coll__graph.md5 create mode 100644 latex/da/d6b/classRTSim_1_1FIFOScheduler.tex create mode 100644 latex/da/d6e/classRTSim_1_1RandomOffsetGen__inherit__graph.dot create mode 100644 latex/da/d6e/classRTSim_1_1RandomOffsetGen__inherit__graph.md5 create mode 100644 latex/da/d6f/structCatch_1_1Detail_1_1IsStreamInsertable.tex create mode 100644 latex/da/d76/structCatch_1_1IReporter.tex create mode 100644 latex/da/d80/classRTSim_1_1Server__inherit__graph.dot create mode 100644 latex/da/d80/classRTSim_1_1Server__inherit__graph.md5 create mode 100644 latex/da/d8a/structCatch_1_1TestRunInfo.tex create mode 100644 latex/da/d8b/structCatch_1_1Internal_1_1OperatorTraits_3_01IsGreaterThanOrEqualTo_01_4.tex create mode 100644 latex/da/d9f/classRTSim_1_1SuperCBS_1_1ChangeBudgetEvt__inherit__graph.dot create mode 100644 latex/da/d9f/classRTSim_1_1SuperCBS_1_1ChangeBudgetEvt__inherit__graph.md5 create mode 100644 latex/da/da4/classRTSim_1_1EDFScheduler__coll__graph.dot create mode 100644 latex/da/da4/classRTSim_1_1EDFScheduler__coll__graph.md5 create mode 100644 latex/da/da7/classRTSim_1_1EDFModel.tex create mode 100644 latex/da/dae/classRTSim_1_1MaxIATGen__coll__graph.dot create mode 100644 latex/da/dae/classRTSim_1_1MaxIATGen__coll__graph.md5 create mode 100644 latex/da/dba/classRTSim_1_1KernelEvt__coll__graph.dot create mode 100644 latex/da/dba/classRTSim_1_1KernelEvt__coll__graph.md5 create mode 100644 latex/da/dc7/classRTSim_1_1EDFScheduler__inherit__graph.dot create mode 100644 latex/da/dc7/classRTSim_1_1EDFScheduler__inherit__graph.md5 create mode 100644 latex/da/dcb/classRTSim_1_1SuperCBS_1_1SuperCBSExc__inherit__graph.dot create mode 100644 latex/da/dcb/classRTSim_1_1SuperCBS_1_1SuperCBSExc__inherit__graph.md5 create mode 100644 latex/da/dcb/structCatch_1_1TrueType.tex create mode 100644 latex/da/dd2/classRTSim_1_1TraceEndEvent__coll__graph.dot create mode 100644 latex/da/dd2/classRTSim_1_1TraceEndEvent__coll__graph.md5 create mode 100644 latex/da/dd3/classRTSim_1_1SignalEvt.tex create mode 100644 latex/da/dd7/classRTSim_1_1PeriodicTask__inherit__graph.dot create mode 100644 latex/da/dd7/classRTSim_1_1PeriodicTask__inherit__graph.md5 create mode 100644 latex/da/dda/classRTSim_1_1SchedRTA__inherit__graph.dot create mode 100644 latex/da/dda/classRTSim_1_1SchedRTA__inherit__graph.md5 create mode 100644 latex/da/dda/classRTSim_1_1SuperCBS_1_1SuperCBSExc__coll__graph.dot create mode 100644 latex/da/dda/classRTSim_1_1SuperCBS_1_1SuperCBSExc__coll__graph.md5 create mode 100644 latex/da/deb/classRTSim_1_1RandomTaskSetFactory_1_1Exc.tex create mode 100644 latex/da/dff/structCatch_1_1LazyStat.tex create mode 100644 latex/db/d01/classRTSim_1_1WaitEvt.tex create mode 100644 latex/db/d04/classRTSim_1_1SchedPoint_1_1ChangeBudgetEvt__inherit__graph.dot create mode 100644 latex/db/d04/classRTSim_1_1SchedPoint_1_1ChangeBudgetEvt__inherit__graph.md5 create mode 100644 latex/db/d06/classRTSim_1_1RRScheduler_1_1RRModel__inherit__graph.dot create mode 100644 latex/db/d06/classRTSim_1_1RRScheduler_1_1RRModel__inherit__graph.md5 create mode 100644 latex/db/d06/structCatch_1_1ReporterConfig.tex create mode 100644 latex/db/d0a/classRTSim_1_1RMScheduler.tex create mode 100644 latex/db/d0d/classRTSim_1_1ThreEvt__coll__graph.dot create mode 100644 latex/db/d0d/classRTSim_1_1ThreEvt__coll__graph.md5 create mode 100644 latex/db/d18/classRTSim_1_1SchedPoint_1_1SchedPointExc__coll__graph.dot create mode 100644 latex/db/d18/classRTSim_1_1SchedPoint_1_1SchedPointExc__coll__graph.md5 create mode 100644 latex/db/d19/classRTSim_1_1RRScheduler_1_1RRModel.tex create mode 100644 latex/db/d30/classRTSim_1_1NoSuchInstr__inherit__graph.dot create mode 100644 latex/db/d30/classRTSim_1_1NoSuchInstr__inherit__graph.md5 create mode 100644 latex/db/d38/classRTSim_1_1VirtualTrace.tex create mode 100644 latex/db/d41/classRTSim_1_1SchedInstr__inherit__graph.dot create mode 100644 latex/db/d41/classRTSim_1_1SchedInstr__inherit__graph.md5 create mode 100644 latex/db/d4e/classRTSim_1_1RTModel__coll__graph.dot create mode 100644 latex/db/d4e/classRTSim_1_1RTModel__coll__graph.md5 create mode 100644 latex/db/d6a/classRTSim_1_1LatenessStat__coll__graph.dot create mode 100644 latex/db/d6a/classRTSim_1_1LatenessStat__coll__graph.md5 create mode 100644 latex/db/d71/classRTSim_1_1DeschedEvt.tex create mode 100644 latex/db/d7b/classCatch_1_1BetweenGenerator.tex create mode 100644 latex/db/d7e/structCatch_1_1LazyStat__inherit__graph.dot create mode 100644 latex/db/d7e/structCatch_1_1LazyStat__inherit__graph.md5 create mode 100644 latex/db/d7f/classRTSim_1_1ServerExc.tex create mode 100644 latex/db/d83/classRTSim_1_1TraceSignalEvent__inherit__graph.dot create mode 100644 latex/db/d83/classRTSim_1_1TraceSignalEvent__inherit__graph.md5 create mode 100644 latex/db/d8e/classRTSim_1_1CTGen__coll__graph.dot create mode 100644 latex/db/d8e/classRTSim_1_1CTGen__coll__graph.md5 create mode 100644 latex/db/d95/classRTSim_1_1MRTKernel.tex create mode 100644 latex/db/da4/classRTSim_1_1ExecInstr.tex create mode 100644 latex/db/dae/structCatch_1_1IGenerator.tex create mode 100644 latex/db/db8/classRTSim_1_1DlineEquPeriodDTGen.tex create mode 100644 latex/db/dbe/classRTSim_1_1Grub__inherit__graph.dot create mode 100644 latex/db/dbe/classRTSim_1_1Grub__inherit__graph.md5 create mode 100644 latex/db/dc8/structCatch_1_1Verbosity.tex create mode 100644 latex/db/dca/classRTSim_1_1LatenessStat__inherit__graph.dot create mode 100644 latex/db/dca/classRTSim_1_1LatenessStat__inherit__graph.md5 create mode 100644 latex/db/dcf/classRTSim_1_1FeedbackTestModule__inherit__graph.dot create mode 100644 latex/db/dcf/classRTSim_1_1FeedbackTestModule__inherit__graph.md5 create mode 100644 latex/db/dcf/structCatch_1_1AssertionStats.tex create mode 100644 latex/db/dd3/classRTSim_1_1ArrEvt__coll__graph.dot create mode 100644 latex/db/dd3/classRTSim_1_1ArrEvt__coll__graph.md5 create mode 100644 latex/db/ddf/structCatch_1_1IReporterFactory.tex create mode 100644 latex/db/dee/classRTSim_1_1EndInstrEvt__inherit__graph.dot create mode 100644 latex/db/dee/classRTSim_1_1EndInstrEvt__inherit__graph.md5 create mode 100644 latex/db/dee/classRTSim_1_1SuspendInstr__inherit__graph.dot create mode 100644 latex/db/dee/classRTSim_1_1SuspendInstr__inherit__graph.md5 create mode 100644 latex/db/df5/classRTSim_1_1TraceTaskEvent__inherit__graph.dot create mode 100644 latex/db/df5/classRTSim_1_1TraceTaskEvent__inherit__graph.md5 create mode 100644 latex/db/dfe/classRTSim_1_1ExecInstr__inherit__graph.dot create mode 100644 latex/db/dfe/classRTSim_1_1ExecInstr__inherit__graph.md5 create mode 100644 latex/db/dfe/classRTSim_1_1PIRManager__inherit__graph.dot create mode 100644 latex/db/dfe/classRTSim_1_1PIRManager__inherit__graph.md5 create mode 100644 latex/dc/d00/structCatch_1_1SharedImpl__coll__graph.dot create mode 100644 latex/dc/d00/structCatch_1_1SharedImpl__coll__graph.md5 create mode 100644 latex/dc/d01/classRTSim_1_1RRScheduler__coll__graph.dot create mode 100644 latex/dc/d01/classRTSim_1_1RRScheduler__coll__graph.md5 create mode 100644 latex/dc/d02/classRTSim_1_1Task__coll__graph.dot create mode 100644 latex/dc/d02/classRTSim_1_1Task__coll__graph.md5 create mode 100644 latex/dc/d08/classRTSim_1_1TraceDlineSetEvent__coll__graph.dot create mode 100644 latex/dc/d08/classRTSim_1_1TraceDlineSetEvent__coll__graph.md5 create mode 100644 latex/dc/d0a/classRTSim_1_1FakeArrEvt__coll__graph.dot create mode 100644 latex/dc/d0a/classRTSim_1_1FakeArrEvt__coll__graph.md5 create mode 100644 latex/dc/d0f/classRTSim_1_1ThreInstr__coll__graph.dot create mode 100644 latex/dc/d0f/classRTSim_1_1ThreInstr__coll__graph.md5 create mode 100644 latex/dc/d11/classRTSim_1_1TraceSignalEvent__coll__graph.dot create mode 100644 latex/dc/d11/classRTSim_1_1TraceSignalEvent__coll__graph.md5 create mode 100644 latex/dc/d11/structCatch_1_1SectionStats.tex create mode 100644 latex/dc/d17/classRTSim_1_1KillEvt__inherit__graph.dot create mode 100644 latex/dc/d17/classRTSim_1_1KillEvt__inherit__graph.md5 create mode 100644 latex/dc/d17/classRTSim_1_1SchedInstr.tex create mode 100644 latex/dc/d1c/classCatch_1_1NonCopyable.tex create mode 100644 latex/dc/d1e/classRTSim_1_1EndDispatchMultiEvt__inherit__graph.dot create mode 100644 latex/dc/d1e/classRTSim_1_1EndDispatchMultiEvt__inherit__graph.md5 create mode 100644 latex/dc/d24/classRTSim_1_1TraceNameEvent__inherit__graph.dot create mode 100644 latex/dc/d24/classRTSim_1_1TraceNameEvent__inherit__graph.md5 create mode 100644 latex/dc/d28/classRTSim_1_1RTKernelExc__inherit__graph.dot create mode 100644 latex/dc/d28/classRTSim_1_1RTKernelExc__inherit__graph.md5 create mode 100644 latex/dc/d2b/structCatch_1_1SourceLineInfo.tex create mode 100644 latex/dc/d33/classRTSim_1_1UniformIATGen__inherit__graph.dot create mode 100644 latex/dc/d33/classRTSim_1_1UniformIATGen__inherit__graph.md5 create mode 100644 latex/dc/d33/structCatch_1_1OutputDebugWriter.tex create mode 100644 latex/dc/d36/classRTSim_1_1ResManager.tex create mode 100644 latex/dc/d3d/namespaceRTSim_1_1____task__stub.tex create mode 100644 latex/dc/d4e/classRTSim_1_1TraceSchedEvent.tex create mode 100644 latex/dc/d54/classRTSim_1_1TraceSchedEvent__coll__graph.dot create mode 100644 latex/dc/d54/classRTSim_1_1TraceSchedEvent__coll__graph.md5 create mode 100644 latex/dc/d56/classRTSim_1_1MaxIATGen__inherit__graph.dot create mode 100644 latex/dc/d56/classRTSim_1_1MaxIATGen__inherit__graph.md5 create mode 100644 latex/dc/d58/classCatch_1_1ExpressionResultBuilder.tex create mode 100644 latex/dc/d59/structCatch_1_1AutoReg.tex create mode 100644 latex/dc/d5b/classRTSim_1_1TaskNotActive__coll__graph.dot create mode 100644 latex/dc/d5b/classRTSim_1_1TaskNotActive__coll__graph.md5 create mode 100644 latex/dc/d5c/structCatch_1_1IMutableContext__coll__graph.dot create mode 100644 latex/dc/d5c/structCatch_1_1IMutableContext__coll__graph.md5 create mode 100644 latex/dc/d5e/classRTSim_1_1WaitInstr.tex create mode 100644 latex/dc/d61/classRTSim_1_1RandomTaskSetFactory.tex create mode 100644 latex/dc/d68/classRTSim_1_1MinIATGen__coll__graph.dot create mode 100644 latex/dc/d68/classRTSim_1_1MinIATGen__coll__graph.md5 create mode 100644 latex/dc/d6d/structCatch_1_1Internal_1_1Evaluator_3_01T1_00_01T2_00_01IsLessThanOrEqualTo_01_4.tex create mode 100644 latex/dc/d72/classCatch_1_1Config.tex create mode 100644 latex/dc/d72/classCatch_1_1TagExtracter__inherit__graph.dot create mode 100644 latex/dc/d72/classCatch_1_1TagExtracter__inherit__graph.md5 create mode 100644 latex/dc/d7e/structCatch_1_1SectionInfo__coll__graph.dot create mode 100644 latex/dc/d7e/structCatch_1_1SectionInfo__coll__graph.md5 create mode 100644 latex/dc/d87/structCatch_1_1Matchers_1_1Impl_1_1Matcher.tex create mode 100644 latex/dc/d89/classCatch_1_1MethodTestCase.tex create mode 100644 latex/dc/d92/classCatch_1_1TagExpressionParser__inherit__graph.dot create mode 100644 latex/dc/d92/classCatch_1_1TagExpressionParser__inherit__graph.md5 create mode 100644 latex/dc/daf/classRTSim_1_1AVRTask__inherit__graph.dot create mode 100644 latex/dc/daf/classRTSim_1_1AVRTask__inherit__graph.md5 create mode 100644 latex/dc/db2/classRTSim_1_1PIRManager__coll__graph.dot create mode 100644 latex/dc/db2/classRTSim_1_1PIRManager__coll__graph.md5 create mode 100644 latex/dc/dbb/classRTSim_1_1Grub.tex create mode 100644 latex/dc/dc5/structCatch_1_1MessageBuilder__coll__graph.dot create mode 100644 latex/dc/dc5/structCatch_1_1MessageBuilder__coll__graph.md5 create mode 100644 latex/dc/dc9/structCatch_1_1IMutableContext.tex create mode 100644 latex/dc/de0/structCatch_1_1CumulativeReporterBase.tex create mode 100644 latex/dc/de5/classRTSim_1_1LatenessStat.tex create mode 100644 latex/dc/dec/structCatch_1_1Internal_1_1OperatorTraits_3_01IsGreaterThan_01_4.tex create mode 100644 latex/dc/ded/classRTSim_1_1Task__inherit__graph.dot create mode 100644 latex/dc/ded/classRTSim_1_1Task__inherit__graph.md5 create mode 100644 latex/dc/dee/structCatch_1_1Internal_1_1OperatorTraits.tex create mode 100644 latex/dc/df6/classCatch_1_1Ptr.tex create mode 100644 latex/dd/d05/classRTSim_1_1DeadEvt__inherit__graph.dot create mode 100644 latex/dd/d05/classRTSim_1_1DeadEvt__inherit__graph.md5 create mode 100644 latex/dd/d0d/classMySim.tex create mode 100644 latex/dd/d0d/classMySim.tex.tmp create mode 100644 latex/dd/d13/classRTSim_1_1uniformCPUFactory__coll__graph.dot create mode 100644 latex/dd/d13/classRTSim_1_1uniformCPUFactory__coll__graph.md5 create mode 100644 latex/dd/d13/structCatch_1_1StreamingReporterBase__inherit__graph.dot create mode 100644 latex/dd/d13/structCatch_1_1StreamingReporterBase__inherit__graph.md5 create mode 100644 latex/dd/d17/classRTSim_1_1EmptyTask__inherit__graph.dot create mode 100644 latex/dd/d17/classRTSim_1_1EmptyTask__inherit__graph.md5 create mode 100644 latex/dd/d1b/classRTSim_1_1Instr.tex create mode 100644 latex/dd/d1f/classRTSim_1_1TaskNotExecuting.tex create mode 100644 latex/dd/d25/classRTSim_1_1KernelEvt__inherit__graph.dot create mode 100644 latex/dd/d25/classRTSim_1_1KernelEvt__inherit__graph.md5 create mode 100644 latex/dd/d25/classRTSim_1_1SparePot_1_1ChangeBudgetEvt__inherit__graph.dot create mode 100644 latex/dd/d25/classRTSim_1_1SparePot_1_1ChangeBudgetEvt__inherit__graph.md5 create mode 100644 latex/dd/d2d/classSystem.tex create mode 100644 latex/dd/d31/classRTSim_1_1SparePot_1_1SparePotExc__inherit__graph.dot create mode 100644 latex/dd/d31/classRTSim_1_1SparePot_1_1SparePotExc__inherit__graph.md5 create mode 100644 latex/dd/d34/classRTSim_1_1SchedIEvt.tex create mode 100644 latex/dd/d37/classRTSim_1_1FPScheduler__coll__graph.dot create mode 100644 latex/dd/d37/classRTSim_1_1FPScheduler__coll__graph.md5 create mode 100644 latex/dd/d38/classRTSim_1_1CBServer__inherit__graph.dot create mode 100644 latex/dd/d38/classRTSim_1_1CBServer__inherit__graph.md5 create mode 100644 latex/dd/d3e/classMySim__coll__graph.dot create mode 100644 latex/dd/d3e/classMySim__coll__graph.md5 create mode 100644 latex/dd/d3f/classRTSim_1_1RandomOffsetGen__coll__graph.dot create mode 100644 latex/dd/d3f/classRTSim_1_1RandomOffsetGen__coll__graph.md5 create mode 100644 latex/dd/d40/classRTSim_1_1AVRTask__coll__graph.dot create mode 100644 latex/dd/d40/classRTSim_1_1AVRTask__coll__graph.md5 create mode 100644 latex/dd/d43/classCatch_1_1TestCase__inherit__graph.dot create mode 100644 latex/dd/d43/classCatch_1_1TestCase__inherit__graph.md5 create mode 100644 latex/dd/d49/classRTSim_1_1RRScheduler_1_1RRSchedExc__inherit__graph.dot create mode 100644 latex/dd/d49/classRTSim_1_1RRScheduler_1_1RRSchedExc__inherit__graph.md5 create mode 100644 latex/dd/d4b/classRTSim_1_1Scheduler__coll__graph.dot create mode 100644 latex/dd/d4b/classRTSim_1_1Scheduler__coll__graph.md5 create mode 100644 latex/dd/d4d/classRTSim_1_1DeschedEvt__inherit__graph.dot create mode 100644 latex/dd/d4d/classRTSim_1_1DeschedEvt__inherit__graph.md5 create mode 100644 latex/dd/d60/classRTSim_1_1KernelEvt.tex create mode 100644 latex/dd/d70/classRTSim_1_1SuperCBS_1_1ChangeBudgetEvt__coll__graph.dot create mode 100644 latex/dd/d70/classRTSim_1_1SuperCBS_1_1ChangeBudgetEvt__coll__graph.md5 create mode 100644 latex/dd/d72/classRTSim_1_1DlineSetEvt.tex create mode 100644 latex/dd/d73/classRTSim_1_1MaxCTGen.tex create mode 100644 latex/dd/d74/classRTSim_1_1TraceEndEvent__inherit__graph.dot create mode 100644 latex/dd/d74/classRTSim_1_1TraceEndEvent__inherit__graph.md5 create mode 100644 latex/dd/d79/structCatch_1_1CumulativeReporterBase_1_1Node.tex create mode 100644 latex/dd/d7a/classRTSim_1_1FinishingTimeStat.tex create mode 100644 latex/dd/d8a/classRTSim_1_1RTModel_1_1RTModelCmp.tex create mode 100644 latex/dd/d90/classRTSim_1_1MaxCTGen__coll__graph.dot create mode 100644 latex/dd/d90/classRTSim_1_1MaxCTGen__coll__graph.md5 create mode 100644 latex/dd/d95/classRTSim_1_1OffsetGen__coll__graph.dot create mode 100644 latex/dd/d95/classRTSim_1_1OffsetGen__coll__graph.md5 create mode 100644 latex/dd/da7/classRTSim_1_1WaitInstr__coll__graph.dot create mode 100644 latex/dd/da7/classRTSim_1_1WaitInstr__coll__graph.md5 create mode 100644 latex/dd/da8/structCatch_1_1ResultAction.tex create mode 100644 latex/dd/da9/classRTSim_1_1PIRManager.tex create mode 100644 latex/dd/da9/classRTSim_1_1RTKernelExc.tex create mode 100644 latex/dd/dac/classRTSim_1_1PeriodicTimer__coll__graph.dot create mode 100644 latex/dd/dac/classRTSim_1_1PeriodicTimer__coll__graph.md5 create mode 100644 latex/dd/dad/classRTSim_1_1RandomTaskSetFactory__inherit__graph.dot create mode 100644 latex/dd/dad/classRTSim_1_1RandomTaskSetFactory__inherit__graph.md5 create mode 100644 latex/dd/dc2/structCatch_1_1CumulativeReporterBase_1_1Node__coll__graph.dot create mode 100644 latex/dd/dc2/structCatch_1_1CumulativeReporterBase_1_1Node__coll__graph.md5 create mode 100644 latex/dd/dc5/classRTSim_1_1ModeOutOfIndex__inherit__graph.dot create mode 100644 latex/dd/dc5/classRTSim_1_1ModeOutOfIndex__inherit__graph.md5 create mode 100644 latex/dd/dc7/structCatch_1_1ConfigData.tex create mode 100644 latex/dd/dcb/structRTSim_1_1SparePot_1_1server__struct.tex create mode 100644 latex/dd/dce/classRTSim_1_1TaskStatExc__inherit__graph.dot create mode 100644 latex/dd/dce/classRTSim_1_1TaskStatExc__inherit__graph.md5 create mode 100644 latex/dd/dd3/classRTSim_1_1TraceTaskEvent__coll__graph.dot create mode 100644 latex/dd/dd3/classRTSim_1_1TraceTaskEvent__coll__graph.md5 create mode 100644 latex/dd/dd4/classRTSim_1_1RandomDTGen__inherit__graph.dot create mode 100644 latex/dd/dd4/classRTSim_1_1RandomDTGen__inherit__graph.md5 create mode 100644 latex/dd/dda/namespaceRTSim_1_1____instr__stub.tex create mode 100644 latex/dd/de2/classRTSim_1_1IATGen__inherit__graph.dot create mode 100644 latex/dd/de2/classRTSim_1_1IATGen__inherit__graph.md5 create mode 100644 latex/dd/dee/structCatch_1_1MessageInfo__coll__graph.dot create mode 100644 latex/dd/dee/structCatch_1_1MessageInfo__coll__graph.md5 create mode 100644 latex/dd/df2/classCatch_1_1Config__coll__graph.dot create mode 100644 latex/dd/df2/classCatch_1_1Config__coll__graph.md5 create mode 100644 latex/dd/df4/classRTSim_1_1JavaTrace__inherit__graph.dot create mode 100644 latex/dd/df4/classRTSim_1_1JavaTrace__inherit__graph.md5 create mode 100644 latex/de/d05/classRTSim_1_1EndInstrEvt__coll__graph.dot create mode 100644 latex/de/d05/classRTSim_1_1EndInstrEvt__coll__graph.md5 create mode 100644 latex/de/d08/structCatch_1_1StreamingReporterBase.tex create mode 100644 latex/de/d0d/classRTSim_1_1SparePot__inherit__graph.dot create mode 100644 latex/de/d0d/classRTSim_1_1SparePot__inherit__graph.md5 create mode 100644 latex/de/d10/classRTSim_1_1DeadEvt__coll__graph.dot create mode 100644 latex/de/d10/classRTSim_1_1DeadEvt__coll__graph.md5 create mode 100644 latex/de/d13/classRTSim_1_1TraceSchedEvent__inherit__graph.dot create mode 100644 latex/de/d13/classRTSim_1_1TraceSchedEvent__inherit__graph.md5 create mode 100644 latex/de/d14/classRTSim_1_1TraceDlinePostEvent__coll__graph.dot create mode 100644 latex/de/d14/classRTSim_1_1TraceDlinePostEvent__coll__graph.md5 create mode 100644 latex/de/d1b/classRTSim_1_1ResManager__coll__graph.dot create mode 100644 latex/de/d1b/classRTSim_1_1ResManager__coll__graph.md5 create mode 100644 latex/de/d29/classRTSim_1_1RTSchedExc__inherit__graph.dot create mode 100644 latex/de/d29/classRTSim_1_1RTSchedExc__inherit__graph.md5 create mode 100644 latex/de/d29/classRTSim_1_1WaitEvt__inherit__graph.dot create mode 100644 latex/de/d29/classRTSim_1_1WaitEvt__inherit__graph.md5 create mode 100644 latex/de/d2d/classRTSim_1_1SignalEvt__coll__graph.dot create mode 100644 latex/de/d2d/classRTSim_1_1SignalEvt__coll__graph.md5 create mode 100644 latex/de/d30/structCatch_1_1Matchers_1_1Impl_1_1Matcher__coll__graph.dot create mode 100644 latex/de/d30/structCatch_1_1Matchers_1_1Impl_1_1Matcher__coll__graph.md5 create mode 100644 latex/de/d4d/classRTSim_1_1TaskEvt__inherit__graph.dot create mode 100644 latex/de/d4d/classRTSim_1_1TaskEvt__inherit__graph.md5 create mode 100644 latex/de/d4d/classRTSim_1_1TaskModel__coll__graph.dot create mode 100644 latex/de/d4d/classRTSim_1_1TaskModel__coll__graph.md5 create mode 100644 latex/de/d58/structCatch_1_1StringMaker_3_01std_1_1vector_3_01T_00_01Allocator_01_4_01_4.tex create mode 100644 latex/de/d5f/classRTSim_1_1AbsTask.tex create mode 100644 latex/de/d62/structCatch_1_1TestCaseInfo.tex create mode 100644 latex/de/d63/classRTSim_1_1MissPercentage__coll__graph.dot create mode 100644 latex/de/d63/classRTSim_1_1MissPercentage__coll__graph.md5 create mode 100644 latex/de/d70/classRTSim_1_1TraceCPUEvent__coll__graph.dot create mode 100644 latex/de/d70/classRTSim_1_1TraceCPUEvent__coll__graph.md5 create mode 100644 latex/de/d79/classRTSim_1_1TraceDlinePostEvent.tex create mode 100644 latex/de/d7f/classRTSim_1_1AbsKernel.tex create mode 100644 latex/de/d85/classRTSim_1_1CapacityTimer__inherit__graph.dot create mode 100644 latex/de/d85/classRTSim_1_1CapacityTimer__inherit__graph.md5 create mode 100644 latex/de/d8b/structCatch_1_1TestCaseStats__coll__graph.dot create mode 100644 latex/de/d8b/structCatch_1_1TestCaseStats__coll__graph.md5 create mode 100644 latex/de/d8c/structCatch_1_1ITestCase.tex create mode 100644 latex/de/d93/classRTSim_1_1FeedbackTestModule__coll__graph.dot create mode 100644 latex/de/d93/classRTSim_1_1FeedbackTestModule__coll__graph.md5 create mode 100644 latex/de/d93/classRTSim_1_1MRTKernel__inherit__graph.dot create mode 100644 latex/de/d93/classRTSim_1_1MRTKernel__inherit__graph.md5 create mode 100644 latex/de/d98/classRTSim_1_1CPU.tex create mode 100644 latex/de/da4/classRTSim_1_1MaxCTGen__inherit__graph.dot create mode 100644 latex/de/da4/classRTSim_1_1MaxCTGen__inherit__graph.md5 create mode 100644 latex/de/da5/structCatch_1_1StringMaker__coll__graph.dot create mode 100644 latex/de/da5/structCatch_1_1StringMaker__coll__graph.md5 create mode 100644 latex/de/dac/structCatch_1_1Internal_1_1OperatorTraits_3_01IsNotEqualTo_01_4.tex create mode 100644 latex/de/db0/structCatch_1_1Counts.tex create mode 100644 latex/de/db6/classRTSim_1_1JavaTrace__coll__graph.dot create mode 100644 latex/de/db6/classRTSim_1_1JavaTrace__coll__graph.md5 create mode 100644 latex/de/db6/classRTSim_1_1TraceIdleEvent.tex create mode 100644 latex/de/dbc/classRTSim_1_1RMScheduler__inherit__graph.dot create mode 100644 latex/de/dbc/classRTSim_1_1RMScheduler__inherit__graph.md5 create mode 100644 latex/de/dc5/classRTSim_1_1SchedPoint_1_1ChangeBudgetEvt__coll__graph.dot create mode 100644 latex/de/dc5/classRTSim_1_1SchedPoint_1_1ChangeBudgetEvt__coll__graph.md5 create mode 100644 latex/de/dc9/classRTSim_1_1GrubExc.tex create mode 100644 latex/de/dcf/structCatch_1_1WarnAbout.tex create mode 100644 latex/de/dd4/structCatch_1_1Matchers_1_1Impl_1_1MatcherImpl__coll__graph.dot create mode 100644 latex/de/dd4/structCatch_1_1Matchers_1_1Impl_1_1MatcherImpl__coll__graph.md5 create mode 100644 latex/de/ddc/classRTSim_1_1PreemptionStat__coll__graph.dot create mode 100644 latex/de/ddc/classRTSim_1_1PreemptionStat__coll__graph.md5 create mode 100644 latex/de/de6/structCatch_1_1Internal_1_1Evaluator_3_01T1_00_01T2_00_01IsNotEqualTo_01_4.tex create mode 100644 latex/de/de7/classRTSim_1_1TracePowerConsumption__coll__graph.dot create mode 100644 latex/de/de7/classRTSim_1_1TracePowerConsumption__coll__graph.md5 create mode 100644 latex/de/df3/classRTSim_1_1SuperCBS_1_1SuperCBSExc.tex create mode 100644 latex/df/d05/classRTSim_1_1DlineEquPeriodDTGen__inherit__graph.dot create mode 100644 latex/df/d05/classRTSim_1_1DlineEquPeriodDTGen__inherit__graph.md5 create mode 100644 latex/df/d15/classRTSim_1_1AbstractFeedbackModule__inherit__graph.dot create mode 100644 latex/df/d15/classRTSim_1_1AbstractFeedbackModule__inherit__graph.md5 create mode 100644 latex/df/d1b/classRTSim_1_1SchedIEvt__inherit__graph.dot create mode 100644 latex/df/d1b/classRTSim_1_1SchedIEvt__inherit__graph.md5 create mode 100644 latex/df/d1d/classCatch_1_1SafeBool.tex create mode 100644 latex/df/d29/structCatch_1_1TestCaseInfo__inherit__graph.dot create mode 100644 latex/df/d29/structCatch_1_1TestCaseInfo__inherit__graph.md5 create mode 100644 latex/df/d2c/classRTSim_1_1TaskNotActive__inherit__graph.dot create mode 100644 latex/df/d2c/classRTSim_1_1TaskNotActive__inherit__graph.md5 create mode 100644 latex/df/d33/classRTSim_1_1Grub__coll__graph.dot create mode 100644 latex/df/d33/classRTSim_1_1Grub__coll__graph.md5 create mode 100644 latex/df/d38/classCatch_1_1ExpressionDecomposer.tex create mode 100644 latex/df/d39/classRTSim_1_1EndDispatchEvt.tex create mode 100644 latex/df/d43/classRTSim_1_1SavedPower__coll__graph.dot create mode 100644 latex/df/d43/classRTSim_1_1SavedPower__coll__graph.md5 create mode 100644 latex/df/d44/classRTSim_1_1RTKernel__coll__graph.dot create mode 100644 latex/df/d44/classRTSim_1_1RTKernel__coll__graph.md5 create mode 100644 latex/df/d47/classRTSim_1_1FPScheduler.tex create mode 100644 latex/df/d4f/classRTSim_1_1FCFSResManager__inherit__graph.dot create mode 100644 latex/df/d4f/classRTSim_1_1FCFSResManager__inherit__graph.md5 create mode 100644 latex/df/d58/classRTSim_1_1PeriodicTimer__inherit__graph.dot create mode 100644 latex/df/d58/classRTSim_1_1PeriodicTimer__inherit__graph.md5 create mode 100644 latex/df/d7b/structRTSim_1_1SchedRTA_1_1ServerInfo.tex create mode 100644 latex/df/da6/classRTSim_1_1AbstractGen.tex create mode 100644 latex/df/db4/classRTSim_1_1uniformCPUFactory.tex create mode 100644 latex/df/db6/classRTSim_1_1RandomTaskSetFactory__coll__graph.dot create mode 100644 latex/df/db6/classRTSim_1_1RandomTaskSetFactory__coll__graph.md5 create mode 100644 latex/df/dc7/classRTSim_1_1SuspendInstr__coll__graph.dot create mode 100644 latex/df/dc7/classRTSim_1_1SuspendInstr__coll__graph.md5 create mode 100644 latex/df/ddb/structCatch_1_1TestCaseStats.tex create mode 100644 latex/df/ddf/structCatch_1_1IConfig.tex create mode 100644 latex/df/ded/classRTSim_1_1PollingServer.tex create mode 100644 latex/dir_13e138d54eb8818da29c3992edef070a.tex create mode 100644 latex/dir_2c1ec4cfaf5ed43ec260b4f91f837847.tex create mode 100644 latex/dir_3c5a7878238957e7a9a8834f0b838f8b.tex create mode 100644 latex/dir_3c5cc845447c19ce6ee25ef55a49cd4c.tex create mode 100644 latex/dir_3f9cfe9044a0c61e52ec878e2326b5b3.tex create mode 100644 latex/dir_4fef79e7177ba769987a8da36c892c5f.tex create mode 100644 latex/dir_55415680715be69f92249950f105c664.tex create mode 100644 latex/dir_63772b626f2709090f0bdca0f40827b4.tex create mode 100644 latex/dir_68267d1309a1af8e8297ef4c3efbcdba.tex create mode 100644 latex/dir_894d12cf7c955c04db6300346317721c.tex create mode 100644 latex/dir_a41afb44cd77021f04ef0298981be91e.tex create mode 100644 latex/dir_a573004c1aa1ac4f8bc48460229ea7de.tex create mode 100644 latex/dir_d28a4824dc47e487b107a5db32ef43c4.tex create mode 100644 latex/dir_d5f87438f5d8e96cf3117079ff5b9178.tex create mode 100644 latex/doxygen.sty create mode 100644 latex/hierarchy.tex create mode 100644 latex/md_README.tex create mode 100644 latex/modules.tex create mode 100644 latex/namespaces.tex create mode 100644 latex/refman.tex create mode 100644 latex/todo.tex diff --git a/Doxyfile b/Doxyfile new file mode 100644 index 0000000..5ab3dad --- /dev/null +++ b/Doxyfile @@ -0,0 +1,2427 @@ +# Doxyfile 1.8.11 + +# This file describes the settings to be used by the documentation system +# doxygen (www.doxygen.org) for a project. +# +# All text after a double hash (##) is considered a comment and is placed in +# front of the TAG it is preceding. +# +# All text after a single hash (#) is considered a comment and will be ignored. +# The format is: +# TAG = value [value, ...] +# For lists, items can also be appended using: +# TAG += value [value, ...] +# Values that contain spaces should be placed between quotes (\" \"). + +#--------------------------------------------------------------------------- +# Project related configuration options +#--------------------------------------------------------------------------- + +# This tag specifies the encoding used for all characters in the config file +# that follow. The default is UTF-8 which is also the encoding used for all text +# before the first occurrence of this tag. Doxygen uses libiconv (or the iconv +# built into libc) for the transcoding. See http://www.gnu.org/software/libiconv +# for the list of possible encodings. +# The default value is: UTF-8. + +DOXYFILE_ENCODING = UTF-8 + +# The PROJECT_NAME tag is a single word (or a sequence of words surrounded by +# double-quotes, unless you are using Doxywizard) that should identify the +# project for which the documentation is generated. This name is used in the +# title of most generated pages and in a few other places. +# The default value is: My Project. + +PROJECT_NAME = "RTLibDoc" + +# The PROJECT_NUMBER tag can be used to enter a project or revision number. This +# could be handy for archiving the generated documentation or if some version +# control system is used. + +PROJECT_NUMBER = + +# Using the PROJECT_BRIEF tag one can provide an optional one line description +# for a project that appears at the top of each page and should give viewer a +# quick idea about the purpose of the project. Keep the description short. + +PROJECT_BRIEF = + +# With the PROJECT_LOGO tag one can specify a logo or an icon that is included +# in the documentation. The maximum height of the logo should not exceed 55 +# pixels and the maximum width should not exceed 200 pixels. Doxygen will copy +# the logo to the output directory. + +PROJECT_LOGO = + +# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) path +# into which the generated documentation will be written. If a relative path is +# entered, it will be relative to the location where doxygen was started. If +# left blank the current directory will be used. + +OUTPUT_DIRECTORY = + +# If the CREATE_SUBDIRS tag is set to YES then doxygen will create 4096 sub- +# directories (in 2 levels) under the output directory of each output format and +# will distribute the generated files over these directories. Enabling this +# option can be useful when feeding doxygen a huge amount of source files, where +# putting all generated files in the same directory would otherwise causes +# performance problems for the file system. +# The default value is: NO. + +CREATE_SUBDIRS = YES + +# If the ALLOW_UNICODE_NAMES tag is set to YES, doxygen will allow non-ASCII +# characters to appear in the names of generated files. If set to NO, non-ASCII +# characters will be escaped, for example _xE3_x81_x84 will be used for Unicode +# U+3044. +# The default value is: NO. + +ALLOW_UNICODE_NAMES = NO + +# The OUTPUT_LANGUAGE tag is used to specify the language in which all +# documentation generated by doxygen is written. Doxygen will use this +# information to generate all constant output in the proper language. +# Possible values are: Afrikaans, Arabic, Armenian, Brazilian, Catalan, Chinese, +# Chinese-Traditional, Croatian, Czech, Danish, Dutch, English (United States), +# Esperanto, Farsi (Persian), Finnish, French, German, Greek, Hungarian, +# Indonesian, Italian, Japanese, Japanese-en (Japanese with English messages), +# Korean, Korean-en (Korean with English messages), Latvian, Lithuanian, +# Macedonian, Norwegian, Persian (Farsi), Polish, Portuguese, Romanian, Russian, +# Serbian, Serbian-Cyrillic, Slovak, Slovene, Spanish, Swedish, Turkish, +# Ukrainian and Vietnamese. +# The default value is: English. + +OUTPUT_LANGUAGE = English + +# If the BRIEF_MEMBER_DESC tag is set to YES, doxygen will include brief member +# descriptions after the members that are listed in the file and class +# documentation (similar to Javadoc). Set to NO to disable this. +# The default value is: YES. + +BRIEF_MEMBER_DESC = YES + +# If the REPEAT_BRIEF tag is set to YES, doxygen will prepend the brief +# description of a member or function before the detailed description +# +# Note: If both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the +# brief descriptions will be completely suppressed. +# The default value is: YES. + +REPEAT_BRIEF = YES + +# This tag implements a quasi-intelligent brief description abbreviator that is +# used to form the text in various listings. Each string in this list, if found +# as the leading text of the brief description, will be stripped from the text +# and the result, after processing the whole list, is used as the annotated +# text. Otherwise, the brief description is used as-is. If left blank, the +# following values are used ($name is automatically replaced with the name of +# the entity):The $name class, The $name widget, The $name file, is, provides, +# specifies, contains, represents, a, an and the. + +ABBREVIATE_BRIEF = + +# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then +# doxygen will generate a detailed section even if there is only a brief +# description. +# The default value is: NO. + +ALWAYS_DETAILED_SEC = NO + +# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all +# inherited members of a class in the documentation of that class as if those +# members were ordinary class members. Constructors, destructors and assignment +# operators of the base classes will not be shown. +# The default value is: NO. + +INLINE_INHERITED_MEMB = NO + +# If the FULL_PATH_NAMES tag is set to YES, doxygen will prepend the full path +# before files name in the file list and in the header files. If set to NO the +# shortest path that makes the file name unique will be used +# The default value is: YES. + +FULL_PATH_NAMES = YES + +# The STRIP_FROM_PATH tag can be used to strip a user-defined part of the path. +# Stripping is only done if one of the specified strings matches the left-hand +# part of the path. The tag can be used to show relative paths in the file list. +# If left blank the directory from which doxygen is run is used as the path to +# strip. +# +# Note that you can specify absolute paths here, but also relative paths, which +# will be relative from the directory where doxygen is started. +# This tag requires that the tag FULL_PATH_NAMES is set to YES. + +STRIP_FROM_PATH = + +# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of the +# path mentioned in the documentation of a class, which tells the reader which +# header file to include in order to use a class. If left blank only the name of +# the header file containing the class definition is used. Otherwise one should +# specify the list of include paths that are normally passed to the compiler +# using the -I flag. + +STRIP_FROM_INC_PATH = + +# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter (but +# less readable) file names. This can be useful is your file systems doesn't +# support long names like on DOS, Mac, or CD-ROM. +# The default value is: NO. + +SHORT_NAMES = NO + +# If the JAVADOC_AUTOBRIEF tag is set to YES then doxygen will interpret the +# first line (until the first dot) of a Javadoc-style comment as the brief +# description. If set to NO, the Javadoc-style will behave just like regular Qt- +# style comments (thus requiring an explicit @brief command for a brief +# description.) +# The default value is: NO. + +JAVADOC_AUTOBRIEF = NO + +# If the QT_AUTOBRIEF tag is set to YES then doxygen will interpret the first +# line (until the first dot) of a Qt-style comment as the brief description. If +# set to NO, the Qt-style will behave just like regular Qt-style comments (thus +# requiring an explicit \brief command for a brief description.) +# The default value is: NO. + +QT_AUTOBRIEF = NO + +# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make doxygen treat a +# multi-line C++ special comment block (i.e. a block of //! or /// comments) as +# a brief description. This used to be the default behavior. The new default is +# to treat a multi-line C++ comment block as a detailed description. Set this +# tag to YES if you prefer the old behavior instead. +# +# Note that setting this tag to YES also means that rational rose comments are +# not recognized any more. +# The default value is: NO. + +MULTILINE_CPP_IS_BRIEF = NO + +# If the INHERIT_DOCS tag is set to YES then an undocumented member inherits the +# documentation from any documented member that it re-implements. +# The default value is: YES. + +INHERIT_DOCS = YES + +# If the SEPARATE_MEMBER_PAGES tag is set to YES then doxygen will produce a new +# page for each member. If set to NO, the documentation of a member will be part +# of the file/class/namespace that contains it. +# The default value is: NO. + +SEPARATE_MEMBER_PAGES = NO + +# The TAB_SIZE tag can be used to set the number of spaces in a tab. Doxygen +# uses this value to replace tabs by spaces in code fragments. +# Minimum value: 1, maximum value: 16, default value: 4. + +TAB_SIZE = 4 + +# This tag can be used to specify a number of aliases that act as commands in +# the documentation. An alias has the form: +# name=value +# For example adding +# "sideeffect=@par Side Effects:\n" +# will allow you to put the command \sideeffect (or @sideeffect) in the +# documentation, which will result in a user-defined paragraph with heading +# "Side Effects:". You can put \n's in the value part of an alias to insert +# newlines. + +ALIASES = + +# This tag can be used to specify a number of word-keyword mappings (TCL only). +# A mapping has the form "name=value". For example adding "class=itcl::class" +# will allow you to use the command class in the itcl::class meaning. + +TCL_SUBST = + +# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C sources +# only. Doxygen will then generate output that is more tailored for C. For +# instance, some of the names that are used will be different. The list of all +# members will be omitted, etc. +# The default value is: NO. + +OPTIMIZE_OUTPUT_FOR_C = YES + +# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java or +# Python sources only. Doxygen will then generate output that is more tailored +# for that language. For instance, namespaces will be presented as packages, +# qualified scopes will look different, etc. +# The default value is: NO. + +OPTIMIZE_OUTPUT_JAVA = NO + +# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran +# sources. Doxygen will then generate output that is tailored for Fortran. +# The default value is: NO. + +OPTIMIZE_FOR_FORTRAN = NO + +# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL +# sources. Doxygen will then generate output that is tailored for VHDL. +# The default value is: NO. + +OPTIMIZE_OUTPUT_VHDL = NO + +# Doxygen selects the parser to use depending on the extension of the files it +# parses. With this tag you can assign which parser to use for a given +# extension. Doxygen has a built-in mapping, but you can override or extend it +# using this tag. The format is ext=language, where ext is a file extension, and +# language is one of the parsers supported by doxygen: IDL, Java, Javascript, +# C#, C, C++, D, PHP, Objective-C, Python, Fortran (fixed format Fortran: +# FortranFixed, free formatted Fortran: FortranFree, unknown formatted Fortran: +# Fortran. In the later case the parser tries to guess whether the code is fixed +# or free formatted code, this is the default for Fortran type files), VHDL. For +# instance to make doxygen treat .inc files as Fortran files (default is PHP), +# and .f files as C (default is Fortran), use: inc=Fortran f=C. +# +# Note: For files without extension you can use no_extension as a placeholder. +# +# Note that for custom extensions you also need to set FILE_PATTERNS otherwise +# the files are not read by doxygen. + +EXTENSION_MAPPING = + +# If the MARKDOWN_SUPPORT tag is enabled then doxygen pre-processes all comments +# according to the Markdown format, which allows for more readable +# documentation. See http://daringfireball.net/projects/markdown/ for details. +# The output of markdown processing is further processed by doxygen, so you can +# mix doxygen, HTML, and XML commands with Markdown formatting. Disable only in +# case of backward compatibilities issues. +# The default value is: YES. + +MARKDOWN_SUPPORT = YES + +# When enabled doxygen tries to link words that correspond to documented +# classes, or namespaces to their corresponding documentation. Such a link can +# be prevented in individual cases by putting a % sign in front of the word or +# globally by setting AUTOLINK_SUPPORT to NO. +# The default value is: YES. + +AUTOLINK_SUPPORT = YES + +# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want +# to include (a tag file for) the STL sources as input, then you should set this +# tag to YES in order to let doxygen match functions declarations and +# definitions whose arguments contain STL classes (e.g. func(std::string); +# versus func(std::string) {}). This also make the inheritance and collaboration +# diagrams that involve STL classes more complete and accurate. +# The default value is: NO. + +BUILTIN_STL_SUPPORT = NO + +# If you use Microsoft's C++/CLI language, you should set this option to YES to +# enable parsing support. +# The default value is: NO. + +CPP_CLI_SUPPORT = NO + +# Set the SIP_SUPPORT tag to YES if your project consists of sip (see: +# http://www.riverbankcomputing.co.uk/software/sip/intro) sources only. Doxygen +# will parse them like normal C++ but will assume all classes use public instead +# of private inheritance when no explicit protection keyword is present. +# The default value is: NO. + +SIP_SUPPORT = NO + +# For Microsoft's IDL there are propget and propput attributes to indicate +# getter and setter methods for a property. Setting this option to YES will make +# doxygen to replace the get and set methods by a property in the documentation. +# This will only work if the methods are indeed getting or setting a simple +# type. If this is not the case, or you want to show the methods anyway, you +# should set this option to NO. +# The default value is: YES. + +IDL_PROPERTY_SUPPORT = YES + +# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC +# tag is set to YES then doxygen will reuse the documentation of the first +# member in the group (if any) for the other members of the group. By default +# all members of a group must be documented explicitly. +# The default value is: NO. + +DISTRIBUTE_GROUP_DOC = NO + +# If one adds a struct or class to a group and this option is enabled, then also +# any nested class or struct is added to the same group. By default this option +# is disabled and one has to add nested compounds explicitly via \ingroup. +# The default value is: NO. + +GROUP_NESTED_COMPOUNDS = NO + +# Set the SUBGROUPING tag to YES to allow class member groups of the same type +# (for instance a group of public functions) to be put as a subgroup of that +# type (e.g. under the Public Functions section). Set it to NO to prevent +# subgrouping. Alternatively, this can be done per class using the +# \nosubgrouping command. +# The default value is: YES. + +SUBGROUPING = YES + +# When the INLINE_GROUPED_CLASSES tag is set to YES, classes, structs and unions +# are shown inside the group in which they are included (e.g. using \ingroup) +# instead of on a separate page (for HTML and Man pages) or section (for LaTeX +# and RTF). +# +# Note that this feature does not work in combination with +# SEPARATE_MEMBER_PAGES. +# The default value is: NO. + +INLINE_GROUPED_CLASSES = NO + +# When the INLINE_SIMPLE_STRUCTS tag is set to YES, structs, classes, and unions +# with only public data fields or simple typedef fields will be shown inline in +# the documentation of the scope in which they are defined (i.e. file, +# namespace, or group documentation), provided this scope is documented. If set +# to NO, structs, classes, and unions are shown on a separate page (for HTML and +# Man pages) or section (for LaTeX and RTF). +# The default value is: NO. + +INLINE_SIMPLE_STRUCTS = NO + +# When TYPEDEF_HIDES_STRUCT tag is enabled, a typedef of a struct, union, or +# enum is documented as struct, union, or enum with the name of the typedef. So +# typedef struct TypeS {} TypeT, will appear in the documentation as a struct +# with name TypeT. When disabled the typedef will appear as a member of a file, +# namespace, or class. And the struct will be named TypeS. This can typically be +# useful for C code in case the coding convention dictates that all compound +# types are typedef'ed and only the typedef is referenced, never the tag name. +# The default value is: NO. + +TYPEDEF_HIDES_STRUCT = NO + +# The size of the symbol lookup cache can be set using LOOKUP_CACHE_SIZE. This +# cache is used to resolve symbols given their name and scope. Since this can be +# an expensive process and often the same symbol appears multiple times in the +# code, doxygen keeps a cache of pre-resolved symbols. If the cache is too small +# doxygen will become slower. If the cache is too large, memory is wasted. The +# cache size is given by this formula: 2^(16+LOOKUP_CACHE_SIZE). The valid range +# is 0..9, the default is 0, corresponding to a cache size of 2^16=65536 +# symbols. At the end of a run doxygen will report the cache usage and suggest +# the optimal cache size from a speed point of view. +# Minimum value: 0, maximum value: 9, default value: 0. + +LOOKUP_CACHE_SIZE = 0 + +#--------------------------------------------------------------------------- +# Build related configuration options +#--------------------------------------------------------------------------- + +# If the EXTRACT_ALL tag is set to YES, doxygen will assume all entities in +# documentation are documented, even if no documentation was available. Private +# class members and static file members will be hidden unless the +# EXTRACT_PRIVATE respectively EXTRACT_STATIC tags are set to YES. +# Note: This will also disable the warnings about undocumented members that are +# normally produced when WARNINGS is set to YES. +# The default value is: NO. + +EXTRACT_ALL = NO + +# If the EXTRACT_PRIVATE tag is set to YES, all private members of a class will +# be included in the documentation. +# The default value is: NO. + +EXTRACT_PRIVATE = NO + +# If the EXTRACT_PACKAGE tag is set to YES, all members with package or internal +# scope will be included in the documentation. +# The default value is: NO. + +EXTRACT_PACKAGE = NO + +# If the EXTRACT_STATIC tag is set to YES, all static members of a file will be +# included in the documentation. +# The default value is: NO. + +EXTRACT_STATIC = NO + +# If the EXTRACT_LOCAL_CLASSES tag is set to YES, classes (and structs) defined +# locally in source files will be included in the documentation. If set to NO, +# only classes defined in header files are included. Does not have any effect +# for Java sources. +# The default value is: YES. + +EXTRACT_LOCAL_CLASSES = YES + +# This flag is only useful for Objective-C code. If set to YES, local methods, +# which are defined in the implementation section but not in the interface are +# included in the documentation. If set to NO, only methods in the interface are +# included. +# The default value is: NO. + +EXTRACT_LOCAL_METHODS = NO + +# If this flag is set to YES, the members of anonymous namespaces will be +# extracted and appear in the documentation as a namespace called +# 'anonymous_namespace{file}', where file will be replaced with the base name of +# the file that contains the anonymous namespace. By default anonymous namespace +# are hidden. +# The default value is: NO. + +EXTRACT_ANON_NSPACES = NO + +# If the HIDE_UNDOC_MEMBERS tag is set to YES, doxygen will hide all +# undocumented members inside documented classes or files. If set to NO these +# members will be included in the various overviews, but no documentation +# section is generated. This option has no effect if EXTRACT_ALL is enabled. +# The default value is: NO. + +HIDE_UNDOC_MEMBERS = NO + +# If the HIDE_UNDOC_CLASSES tag is set to YES, doxygen will hide all +# undocumented classes that are normally visible in the class hierarchy. If set +# to NO, these classes will be included in the various overviews. This option +# has no effect if EXTRACT_ALL is enabled. +# The default value is: NO. + +HIDE_UNDOC_CLASSES = NO + +# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, doxygen will hide all friend +# (class|struct|union) declarations. If set to NO, these declarations will be +# included in the documentation. +# The default value is: NO. + +HIDE_FRIEND_COMPOUNDS = NO + +# If the HIDE_IN_BODY_DOCS tag is set to YES, doxygen will hide any +# documentation blocks found inside the body of a function. If set to NO, these +# blocks will be appended to the function's detailed documentation block. +# The default value is: NO. + +HIDE_IN_BODY_DOCS = NO + +# The INTERNAL_DOCS tag determines if documentation that is typed after a +# \internal command is included. If the tag is set to NO then the documentation +# will be excluded. Set it to YES to include the internal documentation. +# The default value is: NO. + +INTERNAL_DOCS = NO + +# If the CASE_SENSE_NAMES tag is set to NO then doxygen will only generate file +# names in lower-case letters. If set to YES, upper-case letters are also +# allowed. This is useful if you have classes or files whose names only differ +# in case and if your file system supports case sensitive file names. Windows +# and Mac users are advised to set this option to NO. +# The default value is: system dependent. + +CASE_SENSE_NAMES = YES + +# If the HIDE_SCOPE_NAMES tag is set to NO then doxygen will show members with +# their full class and namespace scopes in the documentation. If set to YES, the +# scope will be hidden. +# The default value is: NO. + +HIDE_SCOPE_NAMES = NO + +# If the HIDE_COMPOUND_REFERENCE tag is set to NO (default) then doxygen will +# append additional text to a page's title, such as Class Reference. If set to +# YES the compound reference will be hidden. +# The default value is: NO. + +HIDE_COMPOUND_REFERENCE= NO + +# If the SHOW_INCLUDE_FILES tag is set to YES then doxygen will put a list of +# the files that are included by a file in the documentation of that file. +# The default value is: YES. + +SHOW_INCLUDE_FILES = YES + +# If the SHOW_GROUPED_MEMB_INC tag is set to YES then Doxygen will add for each +# grouped member an include statement to the documentation, telling the reader +# which file to include in order to use the member. +# The default value is: NO. + +SHOW_GROUPED_MEMB_INC = NO + +# If the FORCE_LOCAL_INCLUDES tag is set to YES then doxygen will list include +# files with double quotes in the documentation rather than with sharp brackets. +# The default value is: NO. + +FORCE_LOCAL_INCLUDES = NO + +# If the INLINE_INFO tag is set to YES then a tag [inline] is inserted in the +# documentation for inline members. +# The default value is: YES. + +INLINE_INFO = YES + +# If the SORT_MEMBER_DOCS tag is set to YES then doxygen will sort the +# (detailed) documentation of file and class members alphabetically by member +# name. If set to NO, the members will appear in declaration order. +# The default value is: YES. + +SORT_MEMBER_DOCS = YES + +# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the brief +# descriptions of file, namespace and class members alphabetically by member +# name. If set to NO, the members will appear in declaration order. Note that +# this will also influence the order of the classes in the class list. +# The default value is: NO. + +SORT_BRIEF_DOCS = NO + +# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen will sort the +# (brief and detailed) documentation of class members so that constructors and +# destructors are listed first. If set to NO the constructors will appear in the +# respective orders defined by SORT_BRIEF_DOCS and SORT_MEMBER_DOCS. +# Note: If SORT_BRIEF_DOCS is set to NO this option is ignored for sorting brief +# member documentation. +# Note: If SORT_MEMBER_DOCS is set to NO this option is ignored for sorting +# detailed member documentation. +# The default value is: NO. + +SORT_MEMBERS_CTORS_1ST = NO + +# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the hierarchy +# of group names into alphabetical order. If set to NO the group names will +# appear in their defined order. +# The default value is: NO. + +SORT_GROUP_NAMES = NO + +# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be sorted by +# fully-qualified names, including namespaces. If set to NO, the class list will +# be sorted only by class name, not including the namespace part. +# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. +# Note: This option applies only to the class list, not to the alphabetical +# list. +# The default value is: NO. + +SORT_BY_SCOPE_NAME = NO + +# If the STRICT_PROTO_MATCHING option is enabled and doxygen fails to do proper +# type resolution of all parameters of a function it will reject a match between +# the prototype and the implementation of a member function even if there is +# only one candidate or it is obvious which candidate to choose by doing a +# simple string match. By disabling STRICT_PROTO_MATCHING doxygen will still +# accept a match between prototype and implementation in such cases. +# The default value is: NO. + +STRICT_PROTO_MATCHING = NO + +# The GENERATE_TODOLIST tag can be used to enable (YES) or disable (NO) the todo +# list. This list is created by putting \todo commands in the documentation. +# The default value is: YES. + +GENERATE_TODOLIST = YES + +# The GENERATE_TESTLIST tag can be used to enable (YES) or disable (NO) the test +# list. This list is created by putting \test commands in the documentation. +# The default value is: YES. + +GENERATE_TESTLIST = YES + +# The GENERATE_BUGLIST tag can be used to enable (YES) or disable (NO) the bug +# list. This list is created by putting \bug commands in the documentation. +# The default value is: YES. + +GENERATE_BUGLIST = YES + +# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or disable (NO) +# the deprecated list. This list is created by putting \deprecated commands in +# the documentation. +# The default value is: YES. + +GENERATE_DEPRECATEDLIST= YES + +# The ENABLED_SECTIONS tag can be used to enable conditional documentation +# sections, marked by \if ... \endif and \cond +# ... \endcond blocks. + +ENABLED_SECTIONS = + +# The MAX_INITIALIZER_LINES tag determines the maximum number of lines that the +# initial value of a variable or macro / define can have for it to appear in the +# documentation. If the initializer consists of more lines than specified here +# it will be hidden. Use a value of 0 to hide initializers completely. The +# appearance of the value of individual variables and macros / defines can be +# controlled using \showinitializer or \hideinitializer command in the +# documentation regardless of this setting. +# Minimum value: 0, maximum value: 10000, default value: 30. + +MAX_INITIALIZER_LINES = 30 + +# Set the SHOW_USED_FILES tag to NO to disable the list of files generated at +# the bottom of the documentation of classes and structs. If set to YES, the +# list will mention the files that were used to generate the documentation. +# The default value is: YES. + +SHOW_USED_FILES = YES + +# Set the SHOW_FILES tag to NO to disable the generation of the Files page. This +# will remove the Files entry from the Quick Index and from the Folder Tree View +# (if specified). +# The default value is: YES. + +SHOW_FILES = YES + +# Set the SHOW_NAMESPACES tag to NO to disable the generation of the Namespaces +# page. This will remove the Namespaces entry from the Quick Index and from the +# Folder Tree View (if specified). +# The default value is: YES. + +SHOW_NAMESPACES = YES + +# The FILE_VERSION_FILTER tag can be used to specify a program or script that +# doxygen should invoke to get the current version for each file (typically from +# the version control system). Doxygen will invoke the program by executing (via +# popen()) the command command input-file, where command is the value of the +# FILE_VERSION_FILTER tag, and input-file is the name of an input file provided +# by doxygen. Whatever the program writes to standard output is used as the file +# version. For an example see the documentation. + +FILE_VERSION_FILTER = + +# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed +# by doxygen. The layout file controls the global structure of the generated +# output files in an output format independent way. To create the layout file +# that represents doxygen's defaults, run doxygen with the -l option. You can +# optionally specify a file name after the option, if omitted DoxygenLayout.xml +# will be used as the name of the layout file. +# +# Note that if you run doxygen from a directory containing a file called +# DoxygenLayout.xml, doxygen will parse it automatically even if the LAYOUT_FILE +# tag is left empty. + +LAYOUT_FILE = + +# The CITE_BIB_FILES tag can be used to specify one or more bib files containing +# the reference definitions. This must be a list of .bib files. The .bib +# extension is automatically appended if omitted. This requires the bibtex tool +# to be installed. See also http://en.wikipedia.org/wiki/BibTeX for more info. +# For LaTeX the style of the bibliography can be controlled using +# LATEX_BIB_STYLE. To use this feature you need bibtex and perl available in the +# search path. See also \cite for info how to create references. + +CITE_BIB_FILES = + +#--------------------------------------------------------------------------- +# Configuration options related to warning and progress messages +#--------------------------------------------------------------------------- + +# The QUIET tag can be used to turn on/off the messages that are generated to +# standard output by doxygen. If QUIET is set to YES this implies that the +# messages are off. +# The default value is: NO. + +QUIET = NO + +# The WARNINGS tag can be used to turn on/off the warning messages that are +# generated to standard error (stderr) by doxygen. If WARNINGS is set to YES +# this implies that the warnings are on. +# +# Tip: Turn warnings on while writing the documentation. +# The default value is: YES. + +WARNINGS = YES + +# If the WARN_IF_UNDOCUMENTED tag is set to YES then doxygen will generate +# warnings for undocumented members. If EXTRACT_ALL is set to YES then this flag +# will automatically be disabled. +# The default value is: YES. + +WARN_IF_UNDOCUMENTED = YES + +# If the WARN_IF_DOC_ERROR tag is set to YES, doxygen will generate warnings for +# potential errors in the documentation, such as not documenting some parameters +# in a documented function, or documenting parameters that don't exist or using +# markup commands wrongly. +# The default value is: YES. + +WARN_IF_DOC_ERROR = YES + +# This WARN_NO_PARAMDOC option can be enabled to get warnings for functions that +# are documented, but have no documentation for their parameters or return +# value. If set to NO, doxygen will only warn about wrong or incomplete +# parameter documentation, but not about the absence of documentation. +# The default value is: NO. + +WARN_NO_PARAMDOC = NO + +# If the WARN_AS_ERROR tag is set to YES then doxygen will immediately stop when +# a warning is encountered. +# The default value is: NO. + +WARN_AS_ERROR = NO + +# The WARN_FORMAT tag determines the format of the warning messages that doxygen +# can produce. The string should contain the $file, $line, and $text tags, which +# will be replaced by the file and line number from which the warning originated +# and the warning text. Optionally the format may contain $version, which will +# be replaced by the version of the file (if it could be obtained via +# FILE_VERSION_FILTER) +# The default value is: $file:$line: $text. + +WARN_FORMAT = "$file:$line: $text" + +# The WARN_LOGFILE tag can be used to specify a file to which warning and error +# messages should be written. If left blank the output is written to standard +# error (stderr). + +WARN_LOGFILE = + +#--------------------------------------------------------------------------- +# Configuration options related to the input files +#--------------------------------------------------------------------------- + +# The INPUT tag is used to specify the files and/or directories that contain +# documented source files. You may enter file names like myfile.cpp or +# directories like /usr/src/myproject. Separate the files or directories with +# spaces. See also FILE_PATTERNS and EXTENSION_MAPPING +# Note: If this tag is empty the current directory is searched. + +INPUT = + +# This tag can be used to specify the character encoding of the source files +# that doxygen parses. Internally doxygen uses the UTF-8 encoding. Doxygen uses +# libiconv (or the iconv built into libc) for the transcoding. See the libiconv +# documentation (see: http://www.gnu.org/software/libiconv) for the list of +# possible encodings. +# The default value is: UTF-8. + +INPUT_ENCODING = UTF-8 + +# If the value of the INPUT tag contains directories, you can use the +# FILE_PATTERNS tag to specify one or more wildcard patterns (like *.cpp and +# *.h) to filter out the source-files in the directories. +# +# Note that for custom extensions or not directly supported extensions you also +# need to set EXTENSION_MAPPING for the extension otherwise the files are not +# read by doxygen. +# +# If left blank the following patterns are tested:*.c, *.cc, *.cxx, *.cpp, +# *.c++, *.java, *.ii, *.ixx, *.ipp, *.i++, *.inl, *.idl, *.ddl, *.odl, *.h, +# *.hh, *.hxx, *.hpp, *.h++, *.cs, *.d, *.php, *.php4, *.php5, *.phtml, *.inc, +# *.m, *.markdown, *.md, *.mm, *.dox, *.py, *.pyw, *.f90, *.f, *.for, *.tcl, +# *.vhd, *.vhdl, *.ucf, *.qsf, *.as and *.js. + +FILE_PATTERNS = + +# The RECURSIVE tag can be used to specify whether or not subdirectories should +# be searched for input files as well. +# The default value is: NO. + +RECURSIVE = YES + +# The EXCLUDE tag can be used to specify files and/or directories that should be +# excluded from the INPUT source files. This way you can easily exclude a +# subdirectory from a directory tree whose root is specified with the INPUT tag. +# +# Note that relative paths are relative to the directory from which doxygen is +# run. + +EXCLUDE = + +# The EXCLUDE_SYMLINKS tag can be used to select whether or not files or +# directories that are symbolic links (a Unix file system feature) are excluded +# from the input. +# The default value is: NO. + +EXCLUDE_SYMLINKS = NO + +# If the value of the INPUT tag contains directories, you can use the +# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude +# certain files from those directories. +# +# Note that the wildcards are matched against the file with absolute path, so to +# exclude all test directories for example use the pattern */test/* + +EXCLUDE_PATTERNS = + +# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names +# (namespaces, classes, functions, etc.) that should be excluded from the +# output. The symbol name can be a fully qualified name, a word, or if the +# wildcard * is used, a substring. Examples: ANamespace, AClass, +# AClass::ANamespace, ANamespace::*Test +# +# Note that the wildcards are matched against the file with absolute path, so to +# exclude all test directories use the pattern */test/* + +EXCLUDE_SYMBOLS = + +# The EXAMPLE_PATH tag can be used to specify one or more files or directories +# that contain example code fragments that are included (see the \include +# command). + +EXAMPLE_PATH = + +# If the value of the EXAMPLE_PATH tag contains directories, you can use the +# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp and +# *.h) to filter out the source-files in the directories. If left blank all +# files are included. + +EXAMPLE_PATTERNS = + +# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be +# searched for input files to be used with the \include or \dontinclude commands +# irrespective of the value of the RECURSIVE tag. +# The default value is: NO. + +EXAMPLE_RECURSIVE = NO + +# The IMAGE_PATH tag can be used to specify one or more files or directories +# that contain images that are to be included in the documentation (see the +# \image command). + +IMAGE_PATH = + +# The INPUT_FILTER tag can be used to specify a program that doxygen should +# invoke to filter for each input file. Doxygen will invoke the filter program +# by executing (via popen()) the command: +# +# +# +# where is the value of the INPUT_FILTER tag, and is the +# name of an input file. Doxygen will then use the output that the filter +# program writes to standard output. If FILTER_PATTERNS is specified, this tag +# will be ignored. +# +# Note that the filter must not add or remove lines; it is applied before the +# code is scanned, but not when the output code is generated. If lines are added +# or removed, the anchors will not be placed correctly. +# +# Note that for custom extensions or not directly supported extensions you also +# need to set EXTENSION_MAPPING for the extension otherwise the files are not +# properly processed by doxygen. + +INPUT_FILTER = + +# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern +# basis. Doxygen will compare the file name with each pattern and apply the +# filter if there is a match. The filters are a list of the form: pattern=filter +# (like *.cpp=my_cpp_filter). See INPUT_FILTER for further information on how +# filters are used. If the FILTER_PATTERNS tag is empty or if none of the +# patterns match the file name, INPUT_FILTER is applied. +# +# Note that for custom extensions or not directly supported extensions you also +# need to set EXTENSION_MAPPING for the extension otherwise the files are not +# properly processed by doxygen. + +FILTER_PATTERNS = + +# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using +# INPUT_FILTER) will also be used to filter the input files that are used for +# producing the source files to browse (i.e. when SOURCE_BROWSER is set to YES). +# The default value is: NO. + +FILTER_SOURCE_FILES = NO + +# The FILTER_SOURCE_PATTERNS tag can be used to specify source filters per file +# pattern. A pattern will override the setting for FILTER_PATTERN (if any) and +# it is also possible to disable source filtering for a specific pattern using +# *.ext= (so without naming a filter). +# This tag requires that the tag FILTER_SOURCE_FILES is set to YES. + +FILTER_SOURCE_PATTERNS = + +# If the USE_MDFILE_AS_MAINPAGE tag refers to the name of a markdown file that +# is part of the input, its contents will be placed on the main page +# (index.html). This can be useful if you have a project on for instance GitHub +# and want to reuse the introduction page also for the doxygen output. + +USE_MDFILE_AS_MAINPAGE = + +#--------------------------------------------------------------------------- +# Configuration options related to source browsing +#--------------------------------------------------------------------------- + +# If the SOURCE_BROWSER tag is set to YES then a list of source files will be +# generated. Documented entities will be cross-referenced with these sources. +# +# Note: To get rid of all source code in the generated output, make sure that +# also VERBATIM_HEADERS is set to NO. +# The default value is: NO. + +SOURCE_BROWSER = NO + +# Setting the INLINE_SOURCES tag to YES will include the body of functions, +# classes and enums directly into the documentation. +# The default value is: NO. + +INLINE_SOURCES = NO + +# Setting the STRIP_CODE_COMMENTS tag to YES will instruct doxygen to hide any +# special comment blocks from generated source code fragments. Normal C, C++ and +# Fortran comments will always remain visible. +# The default value is: YES. + +STRIP_CODE_COMMENTS = YES + +# If the REFERENCED_BY_RELATION tag is set to YES then for each documented +# function all documented functions referencing it will be listed. +# The default value is: NO. + +REFERENCED_BY_RELATION = NO + +# If the REFERENCES_RELATION tag is set to YES then for each documented function +# all documented entities called/used by that function will be listed. +# The default value is: NO. + +REFERENCES_RELATION = NO + +# If the REFERENCES_LINK_SOURCE tag is set to YES and SOURCE_BROWSER tag is set +# to YES then the hyperlinks from functions in REFERENCES_RELATION and +# REFERENCED_BY_RELATION lists will link to the source code. Otherwise they will +# link to the documentation. +# The default value is: YES. + +REFERENCES_LINK_SOURCE = YES + +# If SOURCE_TOOLTIPS is enabled (the default) then hovering a hyperlink in the +# source code will show a tooltip with additional information such as prototype, +# brief description and links to the definition and documentation. Since this +# will make the HTML file larger and loading of large files a bit slower, you +# can opt to disable this feature. +# The default value is: YES. +# This tag requires that the tag SOURCE_BROWSER is set to YES. + +SOURCE_TOOLTIPS = YES + +# If the USE_HTAGS tag is set to YES then the references to source code will +# point to the HTML generated by the htags(1) tool instead of doxygen built-in +# source browser. The htags tool is part of GNU's global source tagging system +# (see http://www.gnu.org/software/global/global.html). You will need version +# 4.8.6 or higher. +# +# To use it do the following: +# - Install the latest version of global +# - Enable SOURCE_BROWSER and USE_HTAGS in the config file +# - Make sure the INPUT points to the root of the source tree +# - Run doxygen as normal +# +# Doxygen will invoke htags (and that will in turn invoke gtags), so these +# tools must be available from the command line (i.e. in the search path). +# +# The result: instead of the source browser generated by doxygen, the links to +# source code will now point to the output of htags. +# The default value is: NO. +# This tag requires that the tag SOURCE_BROWSER is set to YES. + +USE_HTAGS = NO + +# If the VERBATIM_HEADERS tag is set the YES then doxygen will generate a +# verbatim copy of the header file for each class for which an include is +# specified. Set to NO to disable this. +# See also: Section \class. +# The default value is: YES. + +VERBATIM_HEADERS = YES + +# If the CLANG_ASSISTED_PARSING tag is set to YES then doxygen will use the +# clang parser (see: http://clang.llvm.org/) for more accurate parsing at the +# cost of reduced performance. This can be particularly helpful with template +# rich C++ code for which doxygen's built-in parser lacks the necessary type +# information. +# Note: The availability of this option depends on whether or not doxygen was +# generated with the -Duse-libclang=ON option for CMake. +# The default value is: NO. + +CLANG_ASSISTED_PARSING = NO + +# If clang assisted parsing is enabled you can provide the compiler with command +# line options that you would normally use when invoking the compiler. Note that +# the include paths will already be set by doxygen for the files and directories +# specified with INPUT and INCLUDE_PATH. +# This tag requires that the tag CLANG_ASSISTED_PARSING is set to YES. + +CLANG_OPTIONS = + +#--------------------------------------------------------------------------- +# Configuration options related to the alphabetical class index +#--------------------------------------------------------------------------- + +# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index of all +# compounds will be generated. Enable this if the project contains a lot of +# classes, structs, unions or interfaces. +# The default value is: YES. + +ALPHABETICAL_INDEX = YES + +# The COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns in +# which the alphabetical index list will be split. +# Minimum value: 1, maximum value: 20, default value: 5. +# This tag requires that the tag ALPHABETICAL_INDEX is set to YES. + +COLS_IN_ALPHA_INDEX = 5 + +# In case all classes in a project start with a common prefix, all classes will +# be put under the same header in the alphabetical index. The IGNORE_PREFIX tag +# can be used to specify a prefix (or a list of prefixes) that should be ignored +# while generating the index headers. +# This tag requires that the tag ALPHABETICAL_INDEX is set to YES. + +IGNORE_PREFIX = + +#--------------------------------------------------------------------------- +# Configuration options related to the HTML output +#--------------------------------------------------------------------------- + +# If the GENERATE_HTML tag is set to YES, doxygen will generate HTML output +# The default value is: YES. + +GENERATE_HTML = YES + +# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. If a +# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of +# it. +# The default directory is: html. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_OUTPUT = html + +# The HTML_FILE_EXTENSION tag can be used to specify the file extension for each +# generated HTML page (for example: .htm, .php, .asp). +# The default value is: .html. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_FILE_EXTENSION = .html + +# The HTML_HEADER tag can be used to specify a user-defined HTML header file for +# each generated HTML page. If the tag is left blank doxygen will generate a +# standard header. +# +# To get valid HTML the header file that includes any scripts and style sheets +# that doxygen needs, which is dependent on the configuration options used (e.g. +# the setting GENERATE_TREEVIEW). It is highly recommended to start with a +# default header using +# doxygen -w html new_header.html new_footer.html new_stylesheet.css +# YourConfigFile +# and then modify the file new_header.html. See also section "Doxygen usage" +# for information on how to generate the default header that doxygen normally +# uses. +# Note: The header is subject to change so you typically have to regenerate the +# default header when upgrading to a newer version of doxygen. For a description +# of the possible markers and block names see the documentation. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_HEADER = + +# The HTML_FOOTER tag can be used to specify a user-defined HTML footer for each +# generated HTML page. If the tag is left blank doxygen will generate a standard +# footer. See HTML_HEADER for more information on how to generate a default +# footer and what special commands can be used inside the footer. See also +# section "Doxygen usage" for information on how to generate the default footer +# that doxygen normally uses. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_FOOTER = + +# The HTML_STYLESHEET tag can be used to specify a user-defined cascading style +# sheet that is used by each HTML page. It can be used to fine-tune the look of +# the HTML output. If left blank doxygen will generate a default style sheet. +# See also section "Doxygen usage" for information on how to generate the style +# sheet that doxygen normally uses. +# Note: It is recommended to use HTML_EXTRA_STYLESHEET instead of this tag, as +# it is more robust and this tag (HTML_STYLESHEET) will in the future become +# obsolete. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_STYLESHEET = + +# The HTML_EXTRA_STYLESHEET tag can be used to specify additional user-defined +# cascading style sheets that are included after the standard style sheets +# created by doxygen. Using this option one can overrule certain style aspects. +# This is preferred over using HTML_STYLESHEET since it does not replace the +# standard style sheet and is therefore more robust against future updates. +# Doxygen will copy the style sheet files to the output directory. +# Note: The order of the extra style sheet files is of importance (e.g. the last +# style sheet in the list overrules the setting of the previous ones in the +# list). For an example see the documentation. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_EXTRA_STYLESHEET = + +# The HTML_EXTRA_FILES tag can be used to specify one or more extra images or +# other source files which should be copied to the HTML output directory. Note +# that these files will be copied to the base HTML output directory. Use the +# $relpath^ marker in the HTML_HEADER and/or HTML_FOOTER files to load these +# files. In the HTML_STYLESHEET file, use the file name only. Also note that the +# files will be copied as-is; there are no commands or markers available. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_EXTRA_FILES = + +# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. Doxygen +# will adjust the colors in the style sheet and background images according to +# this color. Hue is specified as an angle on a colorwheel, see +# http://en.wikipedia.org/wiki/Hue for more information. For instance the value +# 0 represents red, 60 is yellow, 120 is green, 180 is cyan, 240 is blue, 300 +# purple, and 360 is red again. +# Minimum value: 0, maximum value: 359, default value: 220. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_COLORSTYLE_HUE = 220 + +# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of the colors +# in the HTML output. For a value of 0 the output will use grayscales only. A +# value of 255 will produce the most vivid colors. +# Minimum value: 0, maximum value: 255, default value: 100. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_COLORSTYLE_SAT = 100 + +# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to the +# luminance component of the colors in the HTML output. Values below 100 +# gradually make the output lighter, whereas values above 100 make the output +# darker. The value divided by 100 is the actual gamma applied, so 80 represents +# a gamma of 0.8, The value 220 represents a gamma of 2.2, and 100 does not +# change the gamma. +# Minimum value: 40, maximum value: 240, default value: 80. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_COLORSTYLE_GAMMA = 80 + +# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML +# page will contain the date and time when the page was generated. Setting this +# to YES can help to show when doxygen was last run and thus if the +# documentation is up to date. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_TIMESTAMP = NO + +# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML +# documentation will contain sections that can be hidden and shown after the +# page has loaded. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_DYNAMIC_SECTIONS = NO + +# With HTML_INDEX_NUM_ENTRIES one can control the preferred number of entries +# shown in the various tree structured indices initially; the user can expand +# and collapse entries dynamically later on. Doxygen will expand the tree to +# such a level that at most the specified number of entries are visible (unless +# a fully collapsed tree already exceeds this amount). So setting the number of +# entries 1 will produce a full collapsed tree by default. 0 is a special value +# representing an infinite number of entries and will result in a full expanded +# tree by default. +# Minimum value: 0, maximum value: 9999, default value: 100. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_INDEX_NUM_ENTRIES = 100 + +# If the GENERATE_DOCSET tag is set to YES, additional index files will be +# generated that can be used as input for Apple's Xcode 3 integrated development +# environment (see: http://developer.apple.com/tools/xcode/), introduced with +# OSX 10.5 (Leopard). To create a documentation set, doxygen will generate a +# Makefile in the HTML output directory. Running make will produce the docset in +# that directory and running make install will install the docset in +# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find it at +# startup. See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html +# for more information. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +GENERATE_DOCSET = NO + +# This tag determines the name of the docset feed. A documentation feed provides +# an umbrella under which multiple documentation sets from a single provider +# (such as a company or product suite) can be grouped. +# The default value is: Doxygen generated docs. +# This tag requires that the tag GENERATE_DOCSET is set to YES. + +DOCSET_FEEDNAME = "Doxygen generated docs" + +# This tag specifies a string that should uniquely identify the documentation +# set bundle. This should be a reverse domain-name style string, e.g. +# com.mycompany.MyDocSet. Doxygen will append .docset to the name. +# The default value is: org.doxygen.Project. +# This tag requires that the tag GENERATE_DOCSET is set to YES. + +DOCSET_BUNDLE_ID = org.doxygen.Project + +# The DOCSET_PUBLISHER_ID tag specifies a string that should uniquely identify +# the documentation publisher. This should be a reverse domain-name style +# string, e.g. com.mycompany.MyDocSet.documentation. +# The default value is: org.doxygen.Publisher. +# This tag requires that the tag GENERATE_DOCSET is set to YES. + +DOCSET_PUBLISHER_ID = org.doxygen.Publisher + +# The DOCSET_PUBLISHER_NAME tag identifies the documentation publisher. +# The default value is: Publisher. +# This tag requires that the tag GENERATE_DOCSET is set to YES. + +DOCSET_PUBLISHER_NAME = Publisher + +# If the GENERATE_HTMLHELP tag is set to YES then doxygen generates three +# additional HTML index files: index.hhp, index.hhc, and index.hhk. The +# index.hhp is a project file that can be read by Microsoft's HTML Help Workshop +# (see: http://www.microsoft.com/en-us/download/details.aspx?id=21138) on +# Windows. +# +# The HTML Help Workshop contains a compiler that can convert all HTML output +# generated by doxygen into a single compiled HTML file (.chm). Compiled HTML +# files are now used as the Windows 98 help format, and will replace the old +# Windows help format (.hlp) on all Windows platforms in the future. Compressed +# HTML files also contain an index, a table of contents, and you can search for +# words in the documentation. The HTML workshop also contains a viewer for +# compressed HTML files. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +GENERATE_HTMLHELP = NO + +# The CHM_FILE tag can be used to specify the file name of the resulting .chm +# file. You can add a path in front of the file if the result should not be +# written to the html output directory. +# This tag requires that the tag GENERATE_HTMLHELP is set to YES. + +CHM_FILE = + +# The HHC_LOCATION tag can be used to specify the location (absolute path +# including file name) of the HTML help compiler (hhc.exe). If non-empty, +# doxygen will try to run the HTML help compiler on the generated index.hhp. +# The file has to be specified with full path. +# This tag requires that the tag GENERATE_HTMLHELP is set to YES. + +HHC_LOCATION = + +# The GENERATE_CHI flag controls if a separate .chi index file is generated +# (YES) or that it should be included in the master .chm file (NO). +# The default value is: NO. +# This tag requires that the tag GENERATE_HTMLHELP is set to YES. + +GENERATE_CHI = NO + +# The CHM_INDEX_ENCODING is used to encode HtmlHelp index (hhk), content (hhc) +# and project file content. +# This tag requires that the tag GENERATE_HTMLHELP is set to YES. + +CHM_INDEX_ENCODING = + +# The BINARY_TOC flag controls whether a binary table of contents is generated +# (YES) or a normal table of contents (NO) in the .chm file. Furthermore it +# enables the Previous and Next buttons. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTMLHELP is set to YES. + +BINARY_TOC = NO + +# The TOC_EXPAND flag can be set to YES to add extra items for group members to +# the table of contents of the HTML help documentation and to the tree view. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTMLHELP is set to YES. + +TOC_EXPAND = NO + +# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and +# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated that +# can be used as input for Qt's qhelpgenerator to generate a Qt Compressed Help +# (.qch) of the generated HTML documentation. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +GENERATE_QHP = NO + +# If the QHG_LOCATION tag is specified, the QCH_FILE tag can be used to specify +# the file name of the resulting .qch file. The path specified is relative to +# the HTML output folder. +# This tag requires that the tag GENERATE_QHP is set to YES. + +QCH_FILE = + +# The QHP_NAMESPACE tag specifies the namespace to use when generating Qt Help +# Project output. For more information please see Qt Help Project / Namespace +# (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#namespace). +# The default value is: org.doxygen.Project. +# This tag requires that the tag GENERATE_QHP is set to YES. + +QHP_NAMESPACE = org.doxygen.Project + +# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating Qt +# Help Project output. For more information please see Qt Help Project / Virtual +# Folders (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#virtual- +# folders). +# The default value is: doc. +# This tag requires that the tag GENERATE_QHP is set to YES. + +QHP_VIRTUAL_FOLDER = doc + +# If the QHP_CUST_FILTER_NAME tag is set, it specifies the name of a custom +# filter to add. For more information please see Qt Help Project / Custom +# Filters (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#custom- +# filters). +# This tag requires that the tag GENERATE_QHP is set to YES. + +QHP_CUST_FILTER_NAME = + +# The QHP_CUST_FILTER_ATTRS tag specifies the list of the attributes of the +# custom filter to add. For more information please see Qt Help Project / Custom +# Filters (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#custom- +# filters). +# This tag requires that the tag GENERATE_QHP is set to YES. + +QHP_CUST_FILTER_ATTRS = + +# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this +# project's filter section matches. Qt Help Project / Filter Attributes (see: +# http://qt-project.org/doc/qt-4.8/qthelpproject.html#filter-attributes). +# This tag requires that the tag GENERATE_QHP is set to YES. + +QHP_SECT_FILTER_ATTRS = + +# The QHG_LOCATION tag can be used to specify the location of Qt's +# qhelpgenerator. If non-empty doxygen will try to run qhelpgenerator on the +# generated .qhp file. +# This tag requires that the tag GENERATE_QHP is set to YES. + +QHG_LOCATION = + +# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files will be +# generated, together with the HTML files, they form an Eclipse help plugin. To +# install this plugin and make it available under the help contents menu in +# Eclipse, the contents of the directory containing the HTML and XML files needs +# to be copied into the plugins directory of eclipse. The name of the directory +# within the plugins directory should be the same as the ECLIPSE_DOC_ID value. +# After copying Eclipse needs to be restarted before the help appears. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +GENERATE_ECLIPSEHELP = NO + +# A unique identifier for the Eclipse help plugin. When installing the plugin +# the directory name containing the HTML and XML files should also have this +# name. Each documentation set should have its own identifier. +# The default value is: org.doxygen.Project. +# This tag requires that the tag GENERATE_ECLIPSEHELP is set to YES. + +ECLIPSE_DOC_ID = org.doxygen.Project + +# If you want full control over the layout of the generated HTML pages it might +# be necessary to disable the index and replace it with your own. The +# DISABLE_INDEX tag can be used to turn on/off the condensed index (tabs) at top +# of each HTML page. A value of NO enables the index and the value YES disables +# it. Since the tabs in the index contain the same information as the navigation +# tree, you can set this option to YES if you also set GENERATE_TREEVIEW to YES. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +DISABLE_INDEX = NO + +# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index +# structure should be generated to display hierarchical information. If the tag +# value is set to YES, a side panel will be generated containing a tree-like +# index structure (just like the one that is generated for HTML Help). For this +# to work a browser that supports JavaScript, DHTML, CSS and frames is required +# (i.e. any modern browser). Windows users are probably better off using the +# HTML help feature. Via custom style sheets (see HTML_EXTRA_STYLESHEET) one can +# further fine-tune the look of the index. As an example, the default style +# sheet generated by doxygen has an example that shows how to put an image at +# the root of the tree instead of the PROJECT_NAME. Since the tree basically has +# the same information as the tab index, you could consider setting +# DISABLE_INDEX to YES when enabling this option. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +GENERATE_TREEVIEW = NO + +# The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values that +# doxygen will group on one line in the generated HTML documentation. +# +# Note that a value of 0 will completely suppress the enum values from appearing +# in the overview section. +# Minimum value: 0, maximum value: 20, default value: 4. +# This tag requires that the tag GENERATE_HTML is set to YES. + +ENUM_VALUES_PER_LINE = 4 + +# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be used +# to set the initial width (in pixels) of the frame in which the tree is shown. +# Minimum value: 0, maximum value: 1500, default value: 250. +# This tag requires that the tag GENERATE_HTML is set to YES. + +TREEVIEW_WIDTH = 250 + +# If the EXT_LINKS_IN_WINDOW option is set to YES, doxygen will open links to +# external symbols imported via tag files in a separate window. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +EXT_LINKS_IN_WINDOW = NO + +# Use this tag to change the font size of LaTeX formulas included as images in +# the HTML documentation. When you change the font size after a successful +# doxygen run you need to manually remove any form_*.png images from the HTML +# output directory to force them to be regenerated. +# Minimum value: 8, maximum value: 50, default value: 10. +# This tag requires that the tag GENERATE_HTML is set to YES. + +FORMULA_FONTSIZE = 10 + +# Use the FORMULA_TRANPARENT tag to determine whether or not the images +# generated for formulas are transparent PNGs. Transparent PNGs are not +# supported properly for IE 6.0, but are supported on all modern browsers. +# +# Note that when changing this option you need to delete any form_*.png files in +# the HTML output directory before the changes have effect. +# The default value is: YES. +# This tag requires that the tag GENERATE_HTML is set to YES. + +FORMULA_TRANSPARENT = YES + +# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see +# http://www.mathjax.org) which uses client side Javascript for the rendering +# instead of using pre-rendered bitmaps. Use this if you do not have LaTeX +# installed or if you want to formulas look prettier in the HTML output. When +# enabled you may also need to install MathJax separately and configure the path +# to it using the MATHJAX_RELPATH option. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +USE_MATHJAX = NO + +# When MathJax is enabled you can set the default output format to be used for +# the MathJax output. See the MathJax site (see: +# http://docs.mathjax.org/en/latest/output.html) for more details. +# Possible values are: HTML-CSS (which is slower, but has the best +# compatibility), NativeMML (i.e. MathML) and SVG. +# The default value is: HTML-CSS. +# This tag requires that the tag USE_MATHJAX is set to YES. + +MATHJAX_FORMAT = HTML-CSS + +# When MathJax is enabled you need to specify the location relative to the HTML +# output directory using the MATHJAX_RELPATH option. The destination directory +# should contain the MathJax.js script. For instance, if the mathjax directory +# is located at the same level as the HTML output directory, then +# MATHJAX_RELPATH should be ../mathjax. The default value points to the MathJax +# Content Delivery Network so you can quickly see the result without installing +# MathJax. However, it is strongly recommended to install a local copy of +# MathJax from http://www.mathjax.org before deployment. +# The default value is: http://cdn.mathjax.org/mathjax/latest. +# This tag requires that the tag USE_MATHJAX is set to YES. + +MATHJAX_RELPATH = http://cdn.mathjax.org/mathjax/latest + +# The MATHJAX_EXTENSIONS tag can be used to specify one or more MathJax +# extension names that should be enabled during MathJax rendering. For example +# MATHJAX_EXTENSIONS = TeX/AMSmath TeX/AMSsymbols +# This tag requires that the tag USE_MATHJAX is set to YES. + +MATHJAX_EXTENSIONS = + +# The MATHJAX_CODEFILE tag can be used to specify a file with javascript pieces +# of code that will be used on startup of the MathJax code. See the MathJax site +# (see: http://docs.mathjax.org/en/latest/output.html) for more details. For an +# example see the documentation. +# This tag requires that the tag USE_MATHJAX is set to YES. + +MATHJAX_CODEFILE = + +# When the SEARCHENGINE tag is enabled doxygen will generate a search box for +# the HTML output. The underlying search engine uses javascript and DHTML and +# should work on any modern browser. Note that when using HTML help +# (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets (GENERATE_DOCSET) +# there is already a search function so this one should typically be disabled. +# For large projects the javascript based search engine can be slow, then +# enabling SERVER_BASED_SEARCH may provide a better solution. It is possible to +# search using the keyboard; to jump to the search box use + S +# (what the is depends on the OS and browser, but it is typically +# , /