From fdffd95cec21d0fa9fd71d0ec9b55ca2550131cf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C3=A9r=C3=B4me=20Pouiller?= Date: Fri, 5 Jul 2024 16:59:52 +0200 Subject: [PATCH 01/62] modules: hal_silabs: introduce WiSeConnect SDK Origin: Silicon Labs WiSeConnect SDK License: MSLA URL: https://github.com/siliconlabs/wiseconnect commit: e97a0ed00ddda347a8a39e8276f470e1c5fea469 Purpose: Add basic support for SiWx917 --- .../silabs/si91x/mcu/core/chip/inc/RS1xxxx.h | 14081 ++++++++++++++ .../si91x/mcu/core/chip/inc/base_types.h | 127 + .../si91x/mcu/core/chip/inc/data_types.h | 78 + .../si91x/mcu/core/chip/inc/rsi_ccp_common.h | 23 + .../si91x/mcu/core/chip/inc/rsi_error.h | 258 + .../si91x/mcu/core/chip/inc/rsi_ps_ram_func.h | 26 + .../mcu/core/chip/inc/rsi_system_config.h | 104 + .../si91x/mcu/core/chip/inc/si91x_device.h | 16007 ++++++++++++++++ .../si91x/mcu/core/chip/inc/system_si91x.h | 298 + .../chip/src/iPMU_prog/iPMU_dotc/ipmu_apis.c | 902 + .../iPMU_dotc/rsi_system_config_917.c | 500 + .../si91x/mcu/core/chip/src/system_si91x.c | 250 + .../mcu/core/config/rsi_ccp_user_config.h | 64 + .../CMSIS/Driver/Include/Driver_Common.h | 72 + .../CMSIS/Driver/Include/Driver_I2C.h | 208 + .../CMSIS/Driver/Include/Driver_SAI.h | 298 + .../CMSIS/Driver/Include/Driver_SPI.h | 238 + .../CMSIS/Driver/Include/Driver_USART.h | 330 + .../si91x/mcu/drivers/cmsis_driver/GSPI.h | 164 + .../si91x/mcu/drivers/cmsis_driver/I2C.h | 299 + .../si91x/mcu/drivers/cmsis_driver/SAI.h | 254 + .../si91x/mcu/drivers/cmsis_driver/SPI.h | 406 + .../si91x/mcu/drivers/cmsis_driver/UDMA.h | 92 + .../si91x/mcu/drivers/cmsis_driver/USART.h | 276 + .../cmsis_driver/config/RTE_Device_917.h | 3408 ++++ .../drivers/peripheral_drivers/inc/rsi_crc.h | 89 + .../drivers/peripheral_drivers/inc/rsi_ct.h | 1076 ++ .../peripheral_drivers/inc/rsi_efuse.h | 120 + .../peripheral_drivers/inc/rsi_egpio.h | 308 + .../peripheral_drivers/inc/rsi_gpdma.h | 490 + .../drivers/peripheral_drivers/inc/rsi_pwm.h | 965 + .../drivers/peripheral_drivers/inc/rsi_qspi.h | 678 + .../peripheral_drivers/inc/rsi_qspi_proto.h | 674 + .../drivers/peripheral_drivers/inc/rsi_rng.h | 43 + .../peripheral_drivers/inc/rsi_timers.h | 357 + .../drivers/peripheral_drivers/inc/rsi_udma.h | 567 + .../peripheral_drivers/inc/rsi_udma_wrapper.h | 79 + .../mcu/drivers/rom_driver/inc/rsi_packing.h | 27 + .../mcu/drivers/rom_driver/inc/rsi_rom_clks.h | 1675 ++ .../drivers/rom_driver/inc/rsi_rom_egpio.h | 1201 ++ .../rom_driver/inc/rsi_rom_table_si91x.h | 1100 ++ .../rom_driver/inc/rsi_rom_ulpss_clk.h | 667 + .../mcu/drivers/systemlevel/inc/rsi_ipmu.h | 817 + .../mcu/drivers/systemlevel/inc/rsi_pll.h | 841 + .../drivers/systemlevel/inc/rsi_power_save.h | 1697 ++ .../systemlevel/inc/rsi_processor_sensor.h | 51 + .../mcu/drivers/systemlevel/inc/rsi_reg_spi.h | 88 + .../drivers/systemlevel/inc/rsi_retention.h | 313 + .../drivers/systemlevel/inc/rsi_temp_sensor.h | 69 + .../drivers/systemlevel/inc/rsi_time_period.h | 68 + .../drivers/systemlevel/inc/rsi_ulpss_clk.h | 347 + .../mcu/drivers/systemlevel/inc/rsi_wwdt.h | 208 + .../mcu/drivers/systemlevel/src/rsi_ipmu.c | 1661 ++ .../mcu/drivers/systemlevel/src/rsi_pll.c | 3415 ++++ .../drivers/systemlevel/src/rsi_ulpss_clk.c | 1180 ++ 55 files changed, 59634 insertions(+) create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/RS1xxxx.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/base_types.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/data_types.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/rsi_ccp_common.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/rsi_error.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/rsi_ps_ram_func.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/rsi_system_config.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/si91x_device.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/system_si91x.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/core/chip/src/iPMU_prog/iPMU_dotc/ipmu_apis.c create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/core/chip/src/iPMU_prog/iPMU_dotc/rsi_system_config_917.c create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/core/chip/src/system_si91x.c create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/core/config/rsi_ccp_user_config.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_Common.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_I2C.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_SAI.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_SPI.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_USART.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/GSPI.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/I2C.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/SAI.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/SPI.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/UDMA.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/USART.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/config/RTE_Device_917.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_crc.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_ct.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_efuse.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_egpio.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_gpdma.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_pwm.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_qspi.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_qspi_proto.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_rng.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_timers.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_udma.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_udma_wrapper.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_packing.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_clks.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_egpio.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_table_si91x.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_ulpss_clk.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_ipmu.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_pll.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_power_save.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_processor_sensor.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_reg_spi.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_retention.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_temp_sensor.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_time_period.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_ulpss_clk.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_wwdt.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_ipmu.c create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_pll.c create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_ulpss_clk.c diff --git a/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/RS1xxxx.h b/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/RS1xxxx.h new file mode 100644 index 000000000..58a2efc71 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/RS1xxxx.h @@ -0,0 +1,14081 @@ +/******************************************************************************* +* @file RS1xxxx.h +* @brief +******************************************************************************* +* # License +* Copyright 2020 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +/** @addtogroup Redpine Signals Inc. + * @{ + */ + +/** @addtogroup RS1xxxx + * @{ + */ + +#ifndef __RS1XXXX_H__ +#define __RS1XXXX_H__ + +#include "base_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* ------------------------- Interrupt Number Definition ------------------------ */ + +typedef enum { + /* ------------------- Cortex-M4 Processor Exceptions Numbers ------------------- */ + Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ + PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ + SysTick_IRQn = -1, /*!< 15 System Tick Timer */ + /* --------------------- RS1xxxx Specific Interrupt Numbers --------------------- */ + VAD_INTR_PING_IRQn = 0, /*!< VAD ping interrupt */ + VAD_INTR_PONG_IRQn = 1, /*!< VAD pong interrupt */ + TIMER0_IRQn = 2, /*!< 1 TIMER0 */ + TIMER1_IRQn = 3, /*!< 2 TIMER1 */ + TIMER2_IRQn = 4, /*!< 3 TIMER2 */ + TIMER3_IRQn = 5, + CAP_SENSOR_IRQn = 6, + COMP2_IRQn = 7, /*!< 7 COMP2 */ + COMP1_IRQn = 8, /*!< 8 COMP1 */ + UDMA1_IRQn = 10, /*!< 10 UDMA1 */ + ADC_IRQn = 11, /*!< 10 UDMA1 */ + ULPSS_UART_IRQn = 12, /*!< 12 ULPSS USART/UART */ + I2C2_IRQn = 13, /*!< 13 I2C2 */ + I2S1_IRQn = 14, /*!< 14 I2S2 */ + IR_DECODER_IRQ = 15, + SSI2_IRQn = 16, /*!< 14 SSI2 */ + FIM_IRQn = 17, + ULP_EGPIO_PIN_IRQn = 18, + ULP_EGPIO_GROUP_IRQn = 19, + NPSS_TO_MCU_WDT_INTR_IRQn = 20, /*!< 20 WDT interrupt */ + NPSS_TO_MCU_GPIO_INTR_IRQn = 21, + NPSS_TO_MCU_CMP_RF_WKP_INTR_IRQn = 22, + NPSS_TO_MCU_BOD_INTR_IRQn = 23, + NPSS_TO_MCU_BUTTON_INTR_IRQn = 24, + NPSS_TO_MCU_SDC_INTR_IRQn = 25, + NPSS_TO_MCU_WIRELESS_INTR_IRQn = 26, + NPSS_MCU_INTR_IRQn = 27, + MCU_CAL_ALARM_IRQn = 28, /*!< Alarm interrupt */ + MCU_CAL_RTC_IRQn = 29, /*!< Alarm interrupt */ + GPDMA_IRQn = 31, /*!< 31 RPDMA */ + UDMA0_IRQn = 33, /*!< 33 UDMA0 */ + CT_IRQn = 34, /*!< 34 CT */ + HIF0_IRQn = 35, /*!< 35 HIF0 */ + HIF1_IRQn = 36, /*!< 36 HIF1 */ + SIO_IRQn = 37, /*!< 37 SIO */ + USART0_IRQn = 38, /*!< 38 USART0 */ + UART1_IRQn = 39, /*!< 39 USART1 */ + EGPIO_WAKEUP_IRQn = 41, /*!< 41 EGPIO_WAKEUP */ + I2C0_IRQn = 42, /*!< 42 I2C0 */ + SSI1_IRQn = 44, /*!< 44 SSI1 */ + GSPI0_IRQn = 46, /*!< 46 GSPI0 */ + SSI0_IRQn = 47, /*!< 47 SSI0 */ + MCPWM_IRQn = 48, /*!< 48 MCPWM */ + QEI_IRQn = 49, /*!< 23 QEI */ + EGPIO_GROUP_0_IRQn = 50, /*!< 50 EGPIO_GROUP_0 */ + EGPIO_GROUP_1_IRQn = 51, /*!< 51 EGPIO_GROUP_1 */ + EGPIO_PIN_0_IRQn = 52, /*!< 52 EGPIO_PIN_0 */ + EGPIO_PIN_1_IRQn = 53, /*!< 53 EGPIO_PIN_1 */ + EGPIO_PIN_2_IRQn = 54, /*!< 54 EGPIO_PIN_2 */ + EGPIO_PIN_3_IRQn = 55, /*!< 55 EGPIO_PIN_3 */ + EGPIO_PIN_4_IRQn = 56, /*!< 56 EGPIO_PIN_4 */ + EGPIO_PIN_5_IRQn = 57, /*!< 57 EGPIO_PIN_5 */ + EGPIO_PIN_6_IRQn = 58, /*!< 58 EGPIO_PIN_6 */ + EGPIO_PIN_7_IRQn = 59, /*!< 59 EGPIO_PIN_7 */ + QSPI_IRQn = 60, /*!< 60 QSPI */ + I2C1_IRQn = 61, /*!< 61 I2C1 */ + ETHERNET_IRQn = 62, /*!< 62 ETHERNET */ + ETHERNET_PMT_IRQn = 63, /*!< 63 ETHERNET PMT */ + I2S0_IRQn = 64, + CAN1_IRQn = 66, /*!< 67 CAN1 */ + SDMEM_IRQn = 68, /*!< 68 SDMEM interrput */ + PLL_CLOCK_IRQn = 69, /*!< 69 PLL CLOCK INTERRUOT */ + CCI_IRQn = 71, /*!< 71 CCI */ + USB_IRQn = 73, /*!< 73 USB */ + TASS_P2P_IRQn = 74 /*!< TA to M4 Interrupt */ +} IRQn_Type; + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +/* ----------------Configuration of the Cortex-M4 Processor and Core Peripherals---------------- */ +#define __CM4_REV 0x0100 /*!< Cortex-M4 Core Revision */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */ +#include "system_si91x.h" /*!< Si91x System */ + +/* ================================================================================ */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================ */ + +/** @addtogroup Device_Peripheral_Registers + * @{ + */ + +/* ------------------- Start of section using anonymous unions ------------------ */ +#if defined(__CC_ARM) +#pragma push +#pragma anon_unions +#elif defined(__ICCARM__) +#pragma language = extended +#elif defined(__GNUC__) +/* anonymous unions are enabled by default */ +#elif defined(__TMS470__) +/* anonymous unions are enabled by default */ +#elif defined(__TASKING__) +#pragma warning 586 +#else +#warning Not supported compiler type +#endif + +/* =========================================================================================================================== */ +/* ================ GPDMA_C ================ */ +/* =========================================================================================================================== */ + +/** + * @brief GPDMA_C_CHANNEL_CONFIG [CHANNEL_CONFIG] ([0..7]) + */ +typedef struct { + union { + __IOM uint32_t LINK_LIST_PTR_REGS; /*!< (@ 0x00000000) Link List Register for channel 0 to 7 */ + + struct { + __IOM uint32_t LINK_LIST_PTR_REG_CHNL : 32; /*!< [31..0] This is the address of the memory location from which + we get our next descriptor */ + } LINK_LIST_PTR_REGS_b; + }; + + union { + __IOM uint32_t SRC_ADDR_REG_CHNL; /*!< (@ 0x00000004) Source Address Register for channel 0 to 7 */ + + struct { + __IOM uint32_t SRC_ADDR : 32; /*!< [31..0] This is the address of the memory location from which + we get our next descriptor */ + } SRC_ADDR_REG_CHNL_b; + }; + + union { + __IOM uint32_t DEST_ADDR_REG_CHNL; /*!< (@ 0x00000008) Source Address Register for channel 0 to 7 */ + + struct { + __IOM uint32_t DEST_ADDR : 32; /*!< [31..0] This is the destination address to whih the data is + sent */ + } DEST_ADDR_REG_CHNL_b; + }; + + union { + __IOM uint32_t + CHANNEL_CTRL_REG_CHNL; /*!< (@ 0x0000000C) Channel Control Register for channel 0 to 7 */ + + struct { + __IOM uint32_t DMA_BLK_SIZE : 12; /*!< [11..0] This is data to be transmitted. Loaded at the beginning + of the DMA transfer and decremented at every dma transaction. */ + __IOM uint32_t TRNS_TYPE : 2; /*!< [13..12] DMA transfer type */ + __IOM uint32_t + DMA_FLOW_CTRL : 2; /*!< [15..14] DMA flow control */ + __IOM uint32_t + MSTR_IF_FETCH_SEL : 1; /*!< [16..16] This selects the MASTER IF from which data to be fetched */ + __IOM uint32_t + MSTR_IF_SEND_SEL : 1; /*!< [17..17] This selects the MASTER IF from which data to be sent */ + __IOM uint32_t + DEST_DATA_WIDTH : 2; /*!< [19..18] Data transfer to destination. */ + __IOM uint32_t + SRC_DATA_WIDTH : 2; /*!< [21..20] Data transfer from source. */ + __IOM uint32_t SRC_ALIGN : 1; /*!< [22..22] Reserved.Value set to 0 We do not do any singles. + We just do burst, save first 3 bytes in to residue buffer + in one cycle, In the next cycle send 4 bytes to fifo, + save 3 bytes in to residue. This continues on. */ + __IOM uint32_t LINK_LIST_ON : 1; /*!< [23..23] This mode is set, when we do link listed operation */ + __IOM uint32_t + LINK_LIST_MSTR_SEL : 1; /*!< [24..24] This mode is set, when we do link listed operation */ + __IOM uint32_t + SRC_ADDR_CONTIGUOUS : 1; /*!< [25..25] Indicates Address is contiguous from previous */ + __IOM uint32_t + DEST_ADDR_CONTIGUOUS : 1; /*!< [26..26] Indicates Address is contiguous from previous */ + __IOM uint32_t RETRY_ON_ERROR : 1; /*!< [27..27] When this bit is set, if we recieve HRESPERR, We will + retry the DMA for that channel. */ + __IOM uint32_t LINK_INTERRUPT : 1; /*!< [28..28] This bit is set in link list descriptor.Hard ware will + send an interrupt when the DMA transfer is done for the + corresponding link list address */ + __IOM uint32_t SRC_FIFO_MODE : 1; /*!< [29..29] If set to 1; source address will not be incremented(means + fifo mode for source) */ + __IOM uint32_t DEST_FIFO_MODE : 1; /*!< [30..30] If set to 1; destination address will not be incremented(means + fifo mode for destination) */ + __IM uint32_t RESERVED1 : 1; /*!< [31..31] Reserved1 */ + } CHANNEL_CTRL_REG_CHNL_b; + }; + + union { + __IOM uint32_t + MISC_CHANNEL_CTRL_REG_CHNL; /*!< (@ 0x00000010) Misc Channel Control Register for channel 0 */ + + struct { + __IOM uint32_t + AHB_BURST_SIZE : 3; /*!< [2..0] Burst size */ + __IOM uint32_t DEST_DATA_BURST : 6; /*!< [8..3] Burst writes in beats to destination.(000000-64 beats + .....111111-63 beats) */ + __IOM uint32_t SRC_DATA_BURST : 6; /*!< [14..9] Burst writes in beats from source(000000-64 beats .....111111-63 + beats) */ + __IOM uint32_t DEST_CHNL_ID : 6; /*!< [20..15] This is the destination channel Id to which the data + is sent. Must be set up prior to DMA_CHANNEL_ENABLE */ + __IOM uint32_t SRC_CHNL_ID : 6; /*!< [26..21] This is the source channel Id, from which the data + is fetched. must be set up prior to DMA_CHANNEL_ENABLE */ + __IOM uint32_t DMA_PROT : 3; /*!< [29..27] Protection level to go with the data. It will be concatenated + with 1 b1 as there will be no opcode fetching and directly + assign to hprot in AHB interface */ + __IOM uint32_t + MEM_FILL_ENABLE : 1; /*!< [30..30] Enable for memory filling with either 1s or 0s. */ + __IOM uint32_t MEM_ONE_FILL : 1; /*!< [31..31] Select for memory filling with either 1s or 0s. */ + } MISC_CHANNEL_CTRL_REG_CHNL_b; + }; + + union { + __IOM uint32_t FIFO_CONFIG_REGS; /*!< (@ 0x00000014) FIFO Configuration Register for channel 1 */ + + struct { + __IOM uint32_t + FIFO_STRT_ADDR : 6; /*!< [5..0] Starting row address of channel */ + __IOM uint32_t FIFO_SIZE : 6; /*!< [11..6] Channel size */ + __IM uint32_t RESERVED1 : 20; /*!< [31..12] Reserved1 */ + } FIFO_CONFIG_REGS_b; + }; + + union { + __IOM uint32_t PRIORITY_CHNL_REGS; /*!< (@ 0x00000018) Priority Register for channel 0 to 7 */ + + struct { + __IOM uint32_t PRIORITY_CH : 2; /*!< [1..0] Set a value between 2 b00 to 2 b11. The channel having + highest number is the highest priority channel. */ + __IM uint32_t RESERVED1 : 30; /*!< [31..2] Reserved1 */ + } PRIORITY_CHNL_REGS_b; + }; + __IM uint32_t RESERVED[57]; +} GPDMA_C_CHANNEL_CONFIG_Type; /*!< Size = 256 (0x100) */ + +/** + * @brief GPDMA_G_GLOBAL [GLOBAL] (GLOBAL) + */ +typedef struct { + union { + __IOM uint32_t INTERRUPT_REG; /*!< (@ 0x00000000) Interrupt Register */ + + struct { + __IOM uint32_t + GPDMAC_INT_STAT : 8; /*!< [7..0] Interrupt Status */ + __IM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + } INTERRUPT_REG_b; + }; + + union { + __IOM uint32_t INTERRUPT_MASK_REG; /*!< (@ 0x00000004) Interrupt Mask Register */ + + struct { + __IOM uint32_t RESERVED1 : 8; /*!< [7..0] reserved1 */ + __IOM uint32_t LINK_LIST_FETCH_MASK : 8; /*!< [15..8] Linked list fetch done interrupt bit mask control. By + default, descriptor fetch done interrupt is masked. */ + __IOM uint32_t + TFR_DONE_MASK : 8; /*!< [23..16] Transfer done interrupt bit mask control. */ + __IOM uint32_t RESERVED2 : 8; /*!< [31..24] reserved2 */ + } INTERRUPT_MASK_REG_b; + }; + + union { + __IOM uint32_t INTERRUPT_STAT_REG; /*!< (@ 0x00000008) Interrupt status register */ + + struct { + __IOM uint32_t HRESP_ERR0 : 1; /*!< [0..0] DMA error bit */ + __IOM uint32_t LINK_LIST_FETCH_DONE0 : 1; /*!< [1..1] This bit indicates the status of linked list descriptor + fetch done for channel 0 */ + __IOM uint32_t TFR_DONE0 : 1; /*!< [2..2] This bit indicates the status of DMA transfer done interrupt + for channel 0 */ + __IOM uint32_t GPDMAC_ERR0 : 1; /*!< [3..3] transfer size or burst size or h size mismatch error */ + __IOM uint32_t HRESP_ERR1 : 1; /*!< [4..4] HRESP error bit */ + __IOM uint32_t LINK_LIST_FETCH_DONE1 : 1; /*!< [5..5] This bit indicates the status of linked list descriptor + fetch done for channel 1 */ + __IOM uint32_t TFR_DONE1 : 1; /*!< [6..6] This bit indicates the status of DMA transfer done interrupt + for channel 1. */ + __IOM uint32_t GPDMAC_ERR1 : 1; /*!< [7..7] transfer size or burst size or h size mismatch error */ + __IOM uint32_t HRESP_ERR2 : 1; /*!< [8..8] HRESP error bit */ + __IOM uint32_t LINK_LIST_FETCH_DONE2 : 1; /*!< [9..9] This bit indicates the status of linked list descriptor + fetch done for channel 2. */ + __IOM uint32_t TFR_DONE2 : 1; /*!< [10..10] This bit indicates the status of DMA transfer done + interrupt for channel 2. */ + __IOM uint32_t GPDMAC_ERR2 : 1; /*!< [11..11] transfer size or burst size or h size mismatch error */ + __IOM uint32_t HRESP_ERR3 : 1; /*!< [12..12] HRESP error bit */ + __IOM uint32_t LINK_LIST_FETCH_DONE3 : 1; /*!< [13..13] This bit indicates the status of linked list descriptor + fetch done for channel 3. */ + __IOM uint32_t TFR_DONE3 : 1; /*!< [14..14] This bit indicates the status of DMA transfer done + interrupt for channel 3. */ + __IOM uint32_t GPDMAC_ERR3 : 1; /*!< [15..15] transfer size or burst size or h size mismatch error */ + __IOM uint32_t HRESP_ERR4 : 1; /*!< [16..16] HRESP error bit */ + __IOM uint32_t LINK_LIST_FETCH_DONE4 : 1; /*!< [17..17] This bit indicates the status of linked list descriptor + fetch done for channel 4. */ + __IOM uint32_t TFR_DONE4 : 1; /*!< [18..18] This bit indicates the status of DMA transfer done + interrupt for channel 4. */ + __IOM uint32_t GPDMAC_ERR4 : 1; /*!< [19..19] transfer size or burst size or h size mismatch error */ + __IOM uint32_t HRESP_ERR5 : 1; /*!< [20..20] HRESP error bit */ + __IOM uint32_t LINK_LIST_FETCH_DONE5 : 1; /*!< [21..21] This bit indicates the status of linked list descriptor + fetch done for channel 5. */ + __IOM uint32_t TFR_DONE5 : 1; /*!< [22..22] This bit indicates the status of DMA transfer done + interrupt for channel 5. */ + __IOM uint32_t GPDMAC_ERR5 : 1; /*!< [23..23] transfer size or burst size or h size mismatch error */ + __IM uint32_t HRESP_ERR6 : 1; /*!< [24..24] HRESP error bit */ + __IOM uint32_t LINK_LIST_FETCH_DONE6 : 1; /*!< [25..25] This bit indicates the status of linked list descriptor + fetch done for channel 6. */ + __IOM uint32_t TFR_DONE6 : 1; /*!< [26..26] This bit indicates the status of DMA transfer done + interrupt for channel 6. */ + __IOM uint32_t GPDMAC_ERR6 : 1; /*!< [27..27] transfer size or burst size or h size mismatch error */ + __IOM uint32_t HRESP_ERR7 : 1; /*!< [28..28] HRESP error bit */ + __IOM uint32_t LINK_LIST_FETCH_DONE7 : 1; /*!< [29..29] This bit indicates the status of linked list descriptor + fetch done for channel 7. */ + __IOM uint32_t TFR_DONE7 : 1; /*!< [30..30] This bit indicates the status of DMA transfer done + interrupt for channel 7. */ + __IOM uint32_t GPDMAC_ERR7 : 1; /*!< [31..31] transfer size or burst size or h size mismatch error */ + } INTERRUPT_STAT_REG_b; + }; + + union { + __IOM uint32_t + DMA_CHNL_ENABLE_REG; /*!< (@ 0x0000000C) This register used for enable DMA channel */ + + struct { + __IOM uint32_t CH_ENB : 8; /*!< [7..0] CWhen a bit is set to one, it indicates, corresponding + channel is enabled for dma operation */ + __IM uint32_t RESERVED1 : 24; /*!< [31..8] Reserved1 */ + } DMA_CHNL_ENABLE_REG_b; + }; + + union { + __IOM uint32_t + DMA_CHNL_SQUASH_REG; /*!< (@ 0x00000010) This register used for enable DMA channel squash */ + + struct { + __IOM uint32_t CH_DIS : 8; /*!< [7..0] CPU Will be masked to write zeros, CPU is allowed write + 1 only */ + __IM uint32_t RESERVED1 : 24; /*!< [31..8] Reserved1 */ + } DMA_CHNL_SQUASH_REG_b; + }; + + union { + __IOM uint32_t DMA_CHNL_LOCK_REG; /*!< (@ 0x00000014) This register used for enable DMA channel squash */ + + struct { + __IOM uint32_t CHNL_LOCK : 8; /*!< [7..0] When set entire DMA block transfer is done, before other + DMA request is serviced */ + __IM uint32_t RESERVED1 : 24; /*!< [31..8] Reserved1 */ + } DMA_CHNL_LOCK_REG_b; + }; +} GPDMA_G_GLOBAL_Type; /*!< Size = 24 (0x18) */ + +/* =========================================================================================================================== */ +/* ================ GPDMA_C ================ */ +/* =========================================================================================================================== */ + +/** + * @brief GPDMAC (dma controller) is an AMBA complaint peripheral unit supports 8-channels (GPDMA_C) + */ + +typedef struct { /*!< (@ 0x21081004) GPDMA_C Structure */ + __IOM GPDMA_C_CHANNEL_CONFIG_Type + CHANNEL_CONFIG[8]; /*!< (@ 0x00000000) [0..7] */ +} GPDMA_C_Type; /*!< Size = 2048 (0x800) */ + +/* =========================================================================================================================== */ +/* ================ GPDMA_G ================ */ +/* =========================================================================================================================== */ + +/** + * @brief GPDMA is an AMBA complaint peripheral unit supports 8-channels (GPDMA_G) + */ + +typedef struct { /*!< (@ 0x21080000) GPDMA_G Structure */ + __IM uint32_t RESERVED[1057]; + __IOM GPDMA_G_GLOBAL_Type GLOBAL; /*!< (@ 0x00001084) GLOBAL */ +} GPDMA_G_Type; /*!< Size = 4252 (0x109c) */ + +/** + * @brief TIMERS_MATCH_CTRL [MATCH_CTRL] ([0..3]) + */ +typedef struct { + union { + __IOM uint32_t MCUULP_TMR_MATCH; /*!< (@ 0x00000000) Timer Match Register */ + + struct { + __IOM uint32_t TMR_MATCH : 32; /*!< (@ 0x00000000) This bits are used to program the lower significant + 16-bits of timer time out value in millisecond + or number of system clocks */ + } MCUULP_TMR_MATCH_b; + }; + + union { + __IOM uint32_t MCUULP_TMR_CNTRL; /*!< (@ 0x00000004) Timer Control Register */ + + struct { + __OM uint32_t TMR_START : 1; /*!< (@ 0x00000000) This Bit are Used to start the timer timer gets + reset upon setting this bit */ + __OM uint32_t TMR_INTR_CLR : 1; /*!< (@ 0x00000001) This Bit are Used to clear the timer */ + __IOM uint32_t + TMR_INTR_ENABLE : 1; /*!< (@ 0x00000002) This Bit are Used to enable the time out interrupt */ + __IOM uint32_t TMR_TYPE : 2; /*!< (@ 0x00000003) This Bit are Used to select the type of timer */ + __IOM uint32_t TMR_MODE : 1; /*!< (@ 0x00000005) This Bit are Used to select the mode working + of timer */ + __OM uint32_t TMR_STOP : 1; /*!< (@ 0x00000006) This Bit are Used to stop the timer */ + __IOM uint32_t COUNTER_UP : 1; /*!< (@ 0x00000007) For reading/tracking counter in up counting this + bit has to be set */ + __IOM uint32_t RESERVED1 : 24; /*!< (@ 0x00000008) reserved1 */ + } MCUULP_TMR_CNTRL_b; + }; +} TIMERS_MATCH_CTRL_Type; + +/** + * @brief EGPIO_PIN_CONFIG [PIN_CONFIG] ([0..79]) + */ +typedef struct { + union { + __IOM uint32_t GPIO_CONFIG_REG; /*!< (@ 0x00000000) GPIO Configuration Register */ + + struct { + __IOM uint32_t DIRECTION : 1; /*!< (@ 0x00000000) Direction of the GPIO pin */ + __IOM uint32_t PORTMASK : 1; /*!< (@ 0x00000001) Port mask value */ + __IOM uint32_t MODE : 4; /*!< (@ 0x00000002) GPIO Pin Mode Used for GPIO Pin Muxing */ + __IOM uint32_t RESERVED1 : 2; /*!< (@ 0x00000006) Reserved1 */ + __IOM uint32_t + GROUP_INTERRUPT1_ENABLE : 1; /*!< (@ 0x00000008) When set, the corresponding GPIO is pin is selected + for group intr 1 generation */ + __IOM uint32_t + GROUP_INTERRUPT1_POLARITY : 1; /*!< (@ 0x00000009) Decides the active value of the pin to be considered + for group interrupt 1 generation */ + __IOM uint32_t + GROUP_INTERRUPT2_ENABLE : 1; /*!< (@ 0x0000000A) When set, the corresponding GPIO is pin is selected + for group intr 2 generation */ + __IOM uint32_t + GROUP_INTERRUPT2_POLARITY : 1; /*!< (@ 0x0000000B) Decides the active value of the pin to be considered + for group interrupt 2 generation */ + __IOM uint32_t RESERVED2 : 4; /*!< (@ 0x0000000C) Reserved2 */ + __IOM uint32_t RESERVED3 : 16; /*!< (@ 0x00000010) Reserved3 */ + } GPIO_CONFIG_REG_b; + }; + + union { + __IOM uint32_t BIT_LOAD_REG; /*!< (@ 0x00000004) Bit Load */ + + struct { + __IOM uint32_t BIT_LOAD : 1; /*!< (@ 0x00000000) Loads 0th bit on to the pin on write. And reads + the value on pin on read into 0th bit */ + __IOM uint32_t RESERVED1 : 31; /*!< (@ 0x00000001) Reserved1 */ + } BIT_LOAD_REG_b; + }; + + union { + __IOM uint32_t WORD_LOAD_REG; /*!< (@ 0x00000008) Word Load */ + + struct { + __IOM uint32_t WORD_LOAD : 16; /*!< (@ 0x00000000) Loads 1 on the pin when any of the bit in load + value is 1. On read pass the bit status + into all bits. */ + __IOM uint32_t RESERVED1 : 16; /*!< (@ 0x00000010) Reserved1 */ + } WORD_LOAD_REG_b; + }; + __IM uint32_t RESERVED; +} EGPIO_PIN_CONFIG_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief EGPIO_PORT_CONFIG [PORT_CONFIG] ([0..5]) + */ +typedef struct { + union { + __IOM uint32_t PORT_LOAD_REG; /*!< (@ 0x00000000) Port Load */ + + struct { + __IOM uint32_t PORT_LOAD : 16; /*!< (@ 0x00000000) Loads the value on to pin on write. And reads + the value of load register on read */ + __IM uint32_t RES : 16; /*!< (@ 0x00000010) RES */ + } PORT_LOAD_REG_b; + }; + + union { + __OM uint32_t PORT_SET_REG; /*!< (@ 0x00000004) Port Set Register */ + + struct { + __OM uint32_t PORT_SET : 16; /*!< (@ 0x00000000) Sets the pin when corresponding bit is high. + Writing zero has no effect. */ + __OM uint32_t RESERVED1 : 16; /*!< (@ 0x00000010) Reserved1 */ + } PORT_SET_REG_b; + }; + + union { + __OM uint32_t PORT_CLEAR_REG; /*!< (@ 0x00000008) Port Clear Register */ + + struct { + __OM uint32_t PORT_CLEAR : 16; /*!< (@ 0x00000000) Clears the pin when corresponding bit is high. + Writing zero has no effect. */ + __OM uint32_t RESERVED1 : 16; /*!< (@ 0x00000010) Reserved1 */ + } PORT_CLEAR_REG_b; + }; + + union { + __OM uint32_t + PORT_MASKED_LOAD_REG; /*!< (@ 0x0000000C) Port Masked Load Register */ + + struct { + __OM uint32_t PORT_MASKED_LOAD : 16; /*!< (@ 0x00000000) Only loads into pins which are not masked. On + read, pass only status unmasked pins */ + __OM uint32_t RESERVED1 : 16; /*!< (@ 0x00000010) Reserved1 */ + } PORT_MASKED_LOAD_REG_b; + }; + + union { + __OM uint32_t PORT_TOGGLE_REG; /*!< (@ 0x00000010) Port Toggle Register */ + + struct { + __OM uint32_t PORT_TOGGLE : 16; /*!< (@ 0x00000000) Toggles the pin when corresponding bit is high. + Writing zero has not effect. */ + __OM uint32_t RESERVED1 : 16; /*!< (@ 0x00000010) Reserved1 */ + } PORT_TOGGLE_REG_b; + }; + + union { + __IM uint32_t PORT_READ_REG; /*!< (@ 0x00000014) Port Read Register */ + + struct { + __IM uint32_t PORT_READ : 16; /*!< (@ 0x00000000) Reads the value on GPIO pins irrespective of + the pin mode. */ + __IM uint32_t RESERVED1 : 16; /*!< (@ 0x00000010) Reserved1 */ + } PORT_READ_REG_b; + }; + __IM uint32_t RESERVED[2]; +} EGPIO_PORT_CONFIG_Type; /*!< Size = 32 (0x20) */ + +/** + * @brief EGPIO_INTR [INTR] ([0..5]) + */ +typedef struct { + union { + __IOM uint32_t GPIO_INTR_CTRL; /*!< (@ 0x00000000) GPIO Interrupt Control Register */ + + struct { + __IOM uint32_t LEVEL_HIGH_ENABLE : 1; /*!< (@ 0x00000000) enables interrupt generation when pin level is + 1 */ + __IOM uint32_t LEVEL_LOW_ENABLE : 1; /*!< (@ 0x00000001) enables interrupt generation when pin level is + 0 */ + __IOM uint32_t RISE_EDGE_ENABLE : 1; /*!< (@ 0x00000002) enables interrupt generation when rising edge + is detected on pin */ + __IOM uint32_t FALL_EDGE_ENABLE : 1; /*!< (@ 0x00000003) enables interrupt generation when Falling edge + is detected on pin */ + __IOM uint32_t MASK : 1; /*!< (@ 0x00000004) Masks the interrupt. Interrupt will still be + seen in status register when enabled */ + __IOM uint32_t RESERVED1 : 3; /*!< (@ 0x00000005) Reserved1 */ + __IOM uint32_t PIN_NUMBER : 4; /*!< (@ 0x00000008) GPIO Pin to be chosen for interrupt generation */ + __IOM uint32_t PORT_NUMBER : 2; /*!< (@ 0x0000000C) GPIO Port to be chosen for interrupt generation */ + __IOM uint32_t RESERVED2 : 18; /*!< (@ 0x0000000E) Reserved2 */ + } GPIO_INTR_CTRL_b; + }; + + union { + __IOM uint32_t GPIO_INTR_STATUS; /*!< (@ 0x00000004) GPIO Interrupt Status Register */ + + struct { + __IOM uint32_t + INTERRUPT_STATUS : 1; /*!< (@ 0x00000000) Gets set when interrupt is enabled and occurs. */ + __IOM uint32_t + RISE_EDGE_STATUS : 1; /*!< (@ 0x00000001) Gets set when rise edge is enabled and occurs. */ + __IOM uint32_t + FALL_EDGE_STATUS : 1; /*!< (@ 0x00000002) Gets set when Fall edge is enabled and occurs. */ + __OM uint32_t MASK_SET : 1; /*!< (@ 0x00000003) Mask set */ + __OM uint32_t MASK_CLEAR : 1; /*!< (@ 0x00000004) Mask Clear */ + __IOM uint32_t RESERVED1 : 27; /*!< (@ 0x00000005) Reserved1 */ + } GPIO_INTR_STATUS_b; + }; +} EGPIO_INTR_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief EGPIO_GPIO_GRP_INTR [GPIO_GRP_INTR] ([0..3]) + */ +typedef struct { + union { + __IOM uint32_t + GPIO_GRP_INTR_CTRL_REG; /*!< (@ 0x00000000) GPIO Interrupt 0 Control Register */ + + struct { + __IOM uint32_t AND_OR : 1; /*!< (@ 0x00000000) AND/OR */ + __IOM uint32_t LEVEL_EDGE : 1; /*!< (@ 0x00000001) Level/Edge */ + __IOM uint32_t ENABLE_WAKEUP : 1; /*!< (@ 0x00000002) For wakeup generation, actual pin status has + to be seen(before double ranking point) */ + __IOM uint32_t + ENABLE_INTERRUPT : 1; /*!< (@ 0x00000003) Enable Interrupt */ + __IOM uint32_t MASK : 1; /*!< (@ 0x00000004) Mask */ + __IOM uint32_t RESERVED1 : 27; /*!< (@ 0x00000005) Reserved1 */ + } GPIO_GRP_INTR_CTRL_REG_b; + }; + + union { + __IOM uint32_t GPIO_GRP_INTR_STS; /*!< (@ 0x00000004) GPIO Interrupt 0 Status Register */ + + struct { + __IOM uint32_t INTERRUPT_STATUS : 1; /*!< (@ 0x00000000) Interrupt status is available in this bit when + interrupt is enabled and generated. When + 1 is written, interrupt gets cleared. */ + __IM uint32_t WAKEUP : 1; /*!< (@ 0x00000001) Double ranked version of wakeup. Gets set when + wakeup is enabled and occurs. When 1 is + written it gets cleared */ + __IOM uint32_t RESERVED1 : 1; /*!< (@ 0x00000002) Reserved1 */ + __IOM uint32_t MASK_SET : 1; /*!< (@ 0x00000003) Gives zero on read */ + __IOM uint32_t MASK_CLEAR : 1; /*!< (@ 0x00000004) Gives zero on read */ + __IOM uint32_t RESERVED2 : 27; /*!< (@ 0x00000005) Reserved2 */ + } GPIO_GRP_INTR_STS_b; + }; +} EGPIO_GPIO_GRP_INTR_Type; +/* ================================================================================ */ +/* ================ I2C0 ================ */ +/* ================================================================================ */ + +/** + * @brief Inter Integrated Circuit(I2C) is programmable control bus that provides support for the communications link between integrated circuits in a system (I2C0) + */ + +/** + * @brief Inter Integrated Circuit(I2C) is programmable control bus that provides support for the communications link between integrated circuits in a system (I2C0) + */ + +typedef struct { /*!< (@ 0x44010000) I2C1 Structure */ + + union { + __IOM uint32_t IC_CON; /*!< (@ 0x00000000) This register can be written only when the i2c + is disabled, which corresponds to IC_ENABLE[0] + being set to 0. Writes at other times have + no effect. */ + + struct { + __IOM uint32_t MASTER_MODE : 1; /*!< (@ 0x00000000) This bit controls whether the I2C master is enabled. */ + __IOM uint32_t SPEED : 2; /*!< (@ 0x00000001) These bits control at which speed the I2C operates. + Hardware protects against illegal values + being programmed by software. */ + __IOM uint32_t IC_10BITADDR_SLAVE : 1; /*!< (@ 0x00000003) When acting as a slave, this bit controls whether + the I2C responds to 7- or 10-bit addresses. */ + __IM uint32_t IC_10BITADDR_MASTER_RD_ONLY : 1; /*!< (@ 0x00000004) the function of this bit is handled by bit 12 + of IC_TAR register, and becomes a read-only + copy called IC_10BITADDR_MASTER_rd_only */ + __IOM uint32_t IC_RESTART_EN : 1; /*!< (@ 0x00000005) Determines whether RESTART conditions may be + sent when acting as a master */ + __IOM uint32_t + IC_SLAVE_DISABLE : 1; /*!< (@ 0x00000006) This bit controls whether I2C has its slave disabled */ + __IOM uint32_t STOP_DET_IFADDRESSED : 1; /*!< (@ 0x00000007) The STOP DETECTION interrupt is generated only + when the transmitted address matches the + slave address of SAR */ + __IOM uint32_t TX_EMPTY_CTRL : 1; /*!< (@ 0x00000008) This bit controls the generation of the TX EMPTY + interrupt, as described in the IC RAW INTR + STAT register. */ + __IM uint32_t RESERVED1 : 1; /*!< (@ 0x00000009) reserved1 */ + __IOM uint32_t + STOP_DET_IF_MASTER_ACTIVE : 1; /*!< (@ 0x0000000A) In Master mode. */ + __IOM uint32_t + BUS_CLEAR_FEATURE_CTRL : 1; /*!< (@ 0x0000000B) In Master mode. */ + __IOM uint32_t RESERVED2 : 20; /*!< (@ 0x0000000C) reserved2 */ + } IC_CON_b; + }; + + union { + __IOM uint32_t IC_TAR; /*!< (@ 0x00000004) I2C Target Address Register */ + + struct { + __IOM uint32_t IC_TAR : 10; /*!< (@ 0x00000000) This is the target address for any master transaction */ + __IOM uint32_t GC_OR_START : 1; /*!< (@ 0x0000000A) If bit 11 (SPECIAL) is set to 1 and bit 13 (Device-ID) + is set to 0, then this bit indicates whether + a General Call or START byte command is + to be performed by the I2C */ + __IOM uint32_t SPECIAL : 1; /*!< (@ 0x0000000B) This bit indicates whether software performs + a General Call or START BYTE command */ + __IOM uint32_t IC_10BITADDR_MASTER : 1; /*!< (@ 0x0000000C) This bit controls whether the i2c starts its + transfers in 7-or 10-bit addressing mode + when acting as a master */ + __IOM uint32_t DEVICE_ID : 1; /*!< (@ 0x0000000D) If bit 11 (SPECIAL) is set to 1, then this bit + indicates whether a Device-ID of a particular + slave mentioned in IC_TAR[6:0] is to be + performed by the I2C Master */ + __IM uint32_t RESERVED1 : 18; /*!< (@ 0x0000000E) reserved1 */ + } IC_TAR_b; + }; + + union { + __IOM uint32_t IC_SAR; /*!< (@ 0x00000008) I2C Slave Address Register */ + + struct { + __IOM uint32_t IC_SAR : 10; /*!< (@ 0x00000000) The IC_SAR holds the slave address when the I2C + is operating as a slave. For 7-bit addressing, + only IC_SAR[6:0] is used. */ + __IM uint32_t RESERVED1 : 22; /*!< (@ 0x0000000A) reserved1 */ + } IC_SAR_b; + }; + + union { + __IOM uint32_t IC_HS_MADDR; /*!< (@ 0x0000000C) I2C High Speed Master Mode Code Address Register */ + + struct { + __IOM uint32_t IC_HS_MAR : 3; /*!< (@ 0x00000000) This bit field holds the value of the I2C HS + mode master code */ + __IM uint32_t RESERVED1 : 29; /*!< (@ 0x00000003) reserved1 */ + } IC_HS_MADDR_b; + }; + + union { + __IOM uint32_t IC_DATA_CMD; /*!< (@ 0x00000010) I2C Rx/Tx Data Buffer and Command Register */ + + struct { + __IOM uint32_t DAT : 8; /*!< (@ 0x00000000) This register contains the data to be transmitted + or received on the I2C bus */ + __OM uint32_t CMD : 1; /*!< (@ 0x00000008) This bit controls whether a read or a write is + performed */ + __OM uint32_t STOP : 1; /*!< (@ 0x00000009) This bit controls whether a STOP is issued after + the byte is sent or received */ + __OM uint32_t RESTART : 1; /*!< (@ 0x0000000A) This bit controls whether a RESTART is issued + before the byte is sent or received */ + __IM uint32_t FIRST_DATA_BYTE : 1; /*!< (@ 0x0000000B) Indicates the first data byte received after + the address phase for receive transfer + in Master receiver or Slave receiver mode */ + __IM uint32_t RESERVED1 : 20; /*!< (@ 0x0000000C) reserved1 */ + } IC_DATA_CMD_b; + }; + + union { + __IOM uint32_t IC_SS_SCL_HCNT; /*!< (@ 0x00000014) Standard Speed I2C Clock SCL High Count Register */ + + struct { + __IOM uint32_t IC_SS_SCL_HCNT : 16; /*!< (@ 0x00000000) This register must be set before any I2C bus + transaction can take place to ensure proper + I/O timing */ + __IM uint32_t RESERVED1 : 16; /*!< (@ 0x00000010) reserved1 */ + } IC_SS_SCL_HCNT_b; + }; + + union { + __IOM uint32_t IC_SS_SCL_LCNT; /*!< (@ 0x00000018) Standard Speed I2C Clock SCL Low Count Register */ + + struct { + __IOM uint32_t IC_SS_SCL_LCNT : 16; /*!< (@ 0x00000000) This register must be set before any I2C bus + transaction can take place to ensure proper + I/O timing */ + __IM uint32_t RESERVED1 : 16; /*!< (@ 0x00000010) reserved1 */ + } IC_SS_SCL_LCNT_b; + }; + + union { + __IOM uint32_t IC_FS_SCL_HCNT; /*!< (@ 0x0000001C) Fast Speed I2C Clock SCL High Count Register */ + + struct { + __IOM uint32_t IC_FS_SCL_HCNT : 16; /*!< (@ 0x00000000) This register must be set before any I2C bus + transaction can take place to ensure proper + I/O timing */ + __IM uint32_t RESERVED1 : 16; /*!< (@ 0x00000010) reserved1 */ + } IC_FS_SCL_HCNT_b; + }; + + union { + __IOM uint32_t IC_FS_SCL_LCNT; /*!< (@ 0x00000020) Fast Speed I2C Clock SCL Low Count Register */ + + struct { + __IOM uint32_t IC_FS_SCL_LCNT : 16; /*!< (@ 0x00000000) This register must be set before any I2C bus + transaction can take place to ensure proper + I/O timing */ + __IM uint32_t RESERVED1 : 16; /*!< (@ 0x00000010) reserved1 */ + } IC_FS_SCL_LCNT_b; + }; + + union { + __IOM uint32_t IC_HS_SCL_HCNT; /*!< (@ 0x00000024) High Speed I2C Clock SCL High Count Register */ + + struct { + __IOM uint32_t IC_HS_SCL_HCNT : 16; /*!< (@ 0x00000000) This register must be set before any I2C bus + transaction can take place to ensure proper + I/O timing */ + __IM uint32_t RESERVED1 : 16; /*!< (@ 0x00000010) reserved1 */ + } IC_HS_SCL_HCNT_b; + }; + + union { + __IOM uint32_t IC_HS_SCL_LCNT; /*!< (@ 0x00000028) High Speed I2C Clock SCL Low Count Register */ + + struct { + __IOM uint32_t IC_HS_SCL_LCNT : 16; /*!< (@ 0x00000000) This register must be set before any I2C bus + transaction can take place to ensure proper + I/O timing */ + __IM uint32_t RESERVED1 : 16; /*!< (@ 0x00000010) reserved1 */ + } IC_HS_SCL_LCNT_b; + }; + + union { + __IM uint32_t IC_INTR_STAT; /*!< (@ 0x0000002C) I2C Interrupt Status Register */ + + struct { + __IM uint32_t R_RX_UNDER : 1; /*!< (@ 0x00000000) Set if the processor attempts to read the receive + buffer when it is empty by reading from + the IC_DATA_CMD register */ + __IM uint32_t R_RX_OVER : 1; /*!< (@ 0x00000001) Set if the receive buffer is completely filled + to IC_RX_BUFFER_DEPTH and an additional + byte is received from an external I2C device */ + __IM uint32_t R_RX_FULL : 1; /*!< (@ 0x00000002) Set when the receive buffer reaches or goes above + the RX_TL threshold in the IC_RX_TL register. */ + __IM uint32_t R_TX_OVER : 1; /*!< (@ 0x00000003) Set during transmit if the transmit buffer is + filled to IC_TX_BUFFER_DEPTH and the processor + attempts to issue another I2C command by + writing to the IC_DATA_CMD register. */ + __IM uint32_t R_TX_EMPTY : 1; /*!< (@ 0x00000004) This bit is set to 1 when the transmit buffer + is at or below the threshold value set + in the IC_TX_TL register. */ + __IM uint32_t R_RD_REQ : 1; /*!< (@ 0x00000005) This bit is set to 1 when DW_apb_i2c is acting + as a slave and another I2C master is attempting + to read data from DW_apb_i2c. */ + __IM uint32_t R_TX_ABRT : 1; /*!< (@ 0x00000006) This bit indicates if DW_apb_i2c, as an I2C transmitter, + is unable to complete the intended actions + on the contents of the transmit FIFO */ + __IM uint32_t R_RX_DONE : 1; /*!< (@ 0x00000007) When the DW_apb_i2c is acting as a slave-transmitter, + this bit is set to 1 if the master does + not acknowledge a transmitted byte */ + __IM uint32_t R_ACTIVITY : 1; /*!< (@ 0x00000008) This bit captures DW_apb_i2c activity and stays + set until it is cleared */ + __IM uint32_t R_STOP_DET : 1; /*!< (@ 0x00000009) Indicates whether a STOP condition has occurred + on the I2C interface regardless of whether + DW_apb_i2c is operating in slave or master + mode. */ + __IM uint32_t R_START_DET : 1; /*!< (@ 0x0000000A) Indicates whether a START or RESTART condition + has occurred on the I2C interface regardless + of whether DW_apb_i2c is operating in slave + or master mode. */ + __IM uint32_t R_GEN_CALL : 1; /*!< (@ 0x0000000B) Set only when a General Call address is received + and it is acknowledged */ + __IM uint32_t R_RESTART_DET : 1; /*!< (@ 0x0000000C) Indicates whether a RESTART condition has occurred + on the I2C interface when DW_apb_i2c is + operating in slave mode and the slave is + the addressed slave */ + __IM uint32_t R_MST_ON_HOLD : 1; /*!< (@ 0x0000000D) Indicates whether a master is holding the bus + and the Tx FIFO is empty. */ + __IM uint32_t M_SCL_STUCK_AT_LOW : 1; /*!< (@ 0x0000000E) Indicates whether the SCL Line is stuck at low + for the IC_SCL_STUCK_LOW_TIMOUT number + of ic_clk periods */ + __IM uint32_t RESERVED1 : 17; /*!< (@ 0x0000000F) reserved1 */ + } IC_INTR_STAT_b; + }; + + union { + __IOM uint32_t IC_INTR_MASK; /*!< (@ 0x00000030) I2C Interrupt Mask Register */ + + struct { + __IOM uint32_t M_RX_UNDER : 1; /*!< (@ 0x00000000) This bit mask their corresponding interrupt status + bits in the IC_INTR_STAT register. */ + __IOM uint32_t M_RX_OVER : 1; /*!< (@ 0x00000001) This bit mask their corresponding interrupt status + bits in the IC_INTR_STAT register. */ + __IOM uint32_t M_RX_FULL : 1; /*!< (@ 0x00000002) This bit mask their corresponding interrupt status + bits in the IC_INTR_STAT register. */ + __IOM uint32_t M_TX_OVER : 1; /*!< (@ 0x00000003) This bit mask their corresponding interrupt status + bits in the IC_INTR_STAT register */ + __IOM uint32_t M_TX_EMPTY : 1; /*!< (@ 0x00000004) This bit mask their corresponding interrupt status + bits in the IC_INTR_STAT register. */ + __IOM uint32_t M_RD_REQ : 1; /*!< (@ 0x00000005) This bit mask their corresponding interrupt status + bits in the IC_INTR_STAT register. */ + __IOM uint32_t M_TX_ABRT : 1; /*!< (@ 0x00000006) This bit mask their corresponding interrupt status + bits in the IC_INTR_STAT register. */ + __IOM uint32_t M_RX_DONE : 1; /*!< (@ 0x00000007) This bit mask their corresponding interrupt status + bits in the IC_INTR_STAT register. */ + __IOM uint32_t M_ACTIVITY : 1; /*!< (@ 0x00000008) This bit mask their corresponding interrupt status + bits in the IC_INTR_STAT register. */ + __IOM uint32_t M_STOP_DET : 1; /*!< (@ 0x00000009) This bit mask their corresponding interrupt status + bits in the IC_INTR_STAT register. */ + __IOM uint32_t M_START_DET : 1; /*!< (@ 0x0000000A) This bit mask their corresponding interrupt status + bits in the IC_INTR_STAT register. */ + __IOM uint32_t M_GEN_CALL : 1; /*!< (@ 0x0000000B) This bit mask their corresponding interrupt status + bits in the IC_INTR_STAT register. */ + __IOM uint32_t M_RESTART_DET : 1; /*!< (@ 0x0000000C) Indicates whether a RESTART condition has occurred + on the I2C interface when DW_apb_i2c is + operating in slave mode and the slave is + the addressed slave */ + __IOM uint32_t M_MST_ON_HOLD : 1; /*!< (@ 0x0000000D) Indicates whether a master is holding the bus + and the Tx FIFO is empty. */ + __IM uint32_t M_SCL_STUCK_AT_LOW : 1; /*!< (@ 0x0000000E) Indicates whether the SCL Line is stuck at low + for the IC_SCL_STUCK_LOW_TIMOUT number + of ic_clk periods */ + __IM uint32_t RESERVED1 : 17; /*!< (@ 0x0000000F) reserved1 */ + } IC_INTR_MASK_b; + }; + + union { + __IM uint32_t IC_RAW_INTR_STAT; /*!< (@ 0x00000034) I2C Raw Interrupt Status Register */ + + struct { + __IM uint32_t RX_UNDER : 1; /*!< (@ 0x00000000) Set if the processor attempts to read the receive + buffer when it is empty by reading from + the IC_DATA_CMD register */ + __IM uint32_t RX_OVER : 1; /*!< (@ 0x00000001) Set if the receive buffer is completely filled + to IC_RX_BUFFER_DEPTH and an additional + byte is received from an external I2C device */ + __IM uint32_t RX_FULL : 1; /*!< (@ 0x00000002) Set when the receive buffer reaches or goes above + the RX_TL threshold in the IC_RX_TL register. */ + __IM uint32_t TX_OVER : 1; /*!< (@ 0x00000003) Set during transmit if the transmit buffer is + filled to IC_TX_BUFFER_DEPTH and the processor + attempts to issue another I2C command by + writing to the IC_DATA_CMD register. */ + __IM uint32_t TX_EMPTY : 1; /*!< (@ 0x00000004) This bit is set to 1 when the transmit buffer + is at or below the threshold value set + in the IC_TX_TL register. */ + __IM uint32_t RD_REQ : 1; /*!< (@ 0x00000005) This bit is set to 1 when DW_apb_i2c is acting + as a slave and another I2C master is attempting + to read data from DW_apb_i2c. */ + __IM uint32_t TX_ABRT : 1; /*!< (@ 0x00000006) This bit indicates if DW_apb_i2c, as an I2C transmitter, + is unable to complete the intended actions + on the contents of the transmit FIFO */ + __IM uint32_t RX_DONE : 1; /*!< (@ 0x00000007) When the DW_apb_i2c is acting as a slave-transmitter, + this bit is set to 1 if the master does + not acknowledge a transmitted byte */ + __IM uint32_t ACTIVITY : 1; /*!< (@ 0x00000008) This bit captures DW_apb_i2c activity and stays + set until it is cleared */ + __IM uint32_t STOP_DET : 1; /*!< (@ 0x00000009) Indicates whether a STOP condition has occurred + on the I2C interface regardless of whether + DW_apb_i2c is operating in slave or master + mode. */ + __IM uint32_t START_DET : 1; /*!< (@ 0x0000000A) Indicates whether a START or RESTART condition + has occurred on the I2C interface regardless + of whether DW_apb_i2c is operating in slave + or master mode. */ + __IM uint32_t GEN_CALL : 1; /*!< (@ 0x0000000B) Set only when a General Call address is received + and it is acknowledged */ + __IM uint32_t RESTART_DET : 1; /*!< (@ 0x0000000C) Indicates whether a RESTART condition has occurred + on the I2C interface when DW_apb_i2c is + operating in slave mode and the slave is + the addressed slave */ + __IM uint32_t MST_ON_HOLD : 1; /*!< (@ 0x0000000D) Indicates whether a master is holding the bus + and the Tx FIFO is empty. */ + __IM uint32_t SCL_STUCK_AT_LOW : 1; /*!< (@ 0x0000000E) Indicates whether the SCL Line is stuck at low + for the IC_SCL_STUCK_LOW_TIMOUT number + of ic_clk periods */ + __IM uint32_t RESERVED1 : 17; /*!< (@ 0x0000000F) reserved1 */ + } IC_RAW_INTR_STAT_b; + }; + + union { + __IOM uint32_t IC_RX_TL; /*!< (@ 0x00000038) I2C Receive FIFO Threshold Register */ + + struct { + __IOM uint32_t RX_TL : 8; /*!< (@ 0x00000000) Receive FIFO Threshold Level */ + __IM uint32_t RESERVED1 : 24; /*!< (@ 0x00000008) reserved1 */ + } IC_RX_TL_b; + }; + + union { + __IOM uint32_t IC_TX_TL; /*!< (@ 0x0000003C) I2C Transmit FIFO Threshold Register */ + + struct { + __IOM uint32_t TX_TL : 8; /*!< (@ 0x00000000) Transmit FIFO Threshold Level */ + __IM uint32_t RESERVED1 : 24; /*!< (@ 0x00000008) reserved1 */ + } IC_TX_TL_b; + }; + + union { + __IM uint32_t IC_CLR_INTR; /*!< (@ 0x00000040) Clear Combined and Individual Interrupt Register */ + + struct { + __IM uint32_t CLR_INTR : 1; /*!< (@ 0x00000000) Read this register to clear the combined interrupt, + all individual interrupts, and the IC_TXABRT_SOURCE + register */ + __IM uint32_t RESERVED1 : 31; /*!< (@ 0x00000001) reserved1 */ + } IC_CLR_INTR_b; + }; + + union { + __IM uint32_t IC_CLR_RX_UNDER; /*!< (@ 0x00000044) Clear RX_UNDER Interrupt Register */ + + struct { + __IM uint32_t CLR_RX_UNDER : 1; /*!< (@ 0x00000000) Read this register to clear the RX_UNDER interrupt + (bit 0) of the IC_RAW_INTR_STAT register. */ + __IM uint32_t RESERVED1 : 31; /*!< (@ 0x00000001) reserved1 */ + } IC_CLR_RX_UNDER_b; + }; + + union { + __IM uint32_t IC_CLR_RX_OVER; /*!< (@ 0x00000048) Clear RX_OVER Interrupt Register */ + + struct { + __IM uint32_t CLR_RX_OVER : 1; /*!< (@ 0x00000000) Read this register to clear the RX_OVER interrupt + (bit 1) of the IC_RAW_INTR_STAT register */ + __IM uint32_t RESERVED1 : 31; /*!< (@ 0x00000001) reserved1 */ + } IC_CLR_RX_OVER_b; + }; + + union { + __IM uint32_t IC_CLR_TX_OVER; /*!< (@ 0x0000004C) Clear TX_OVER Interrupt Register */ + + struct { + __IM uint32_t CLR_TX_OVER : 1; /*!< (@ 0x00000000) Read this register to clear the TX_OVER interrupt + (bit 3) of the IC_RAW_INTR_STAT register. */ + __IM uint32_t RESERVED1 : 31; /*!< (@ 0x00000001) reserved1 */ + } IC_CLR_TX_OVER_b; + }; + + union { + __IM uint32_t IC_CLR_RD_REQ; /*!< (@ 0x00000050) Clear RD_REQ Interrupt Register */ + + struct { + __IM uint32_t CLR_RD_REQ : 1; /*!< (@ 0x00000000) Read this register to clear the RD_REQ interrupt + (bit 5) of the IC_RAW_INTR_STAT register. */ + __IM uint32_t RESERVED1 : 31; /*!< (@ 0x00000001) reserved1 */ + } IC_CLR_RD_REQ_b; + }; + + union { + __IM uint32_t IC_CLR_TX_ABRT; /*!< (@ 0x00000054) Clear TX_ABRT Interrupt Register */ + + struct { + __IM uint32_t CLR_TX_ABRT : 1; /*!< (@ 0x00000000) Read this register to clear the TX_ABRT interrupt + (bit 6) of the C_RAW_INTR_STAT register, + and the IC_TX_ABRT_SOURCE register */ + __IM uint32_t RESERVED1 : 31; /*!< (@ 0x00000001) reserved1 */ + } IC_CLR_TX_ABRT_b; + }; + + union { + __IM uint32_t IC_CLR_RX_DONE; /*!< (@ 0x00000058) Clear RX_DONE Interrupt Register */ + + struct { + __IM uint32_t CLR_RX_DONE : 1; /*!< (@ 0x00000000) Read this register to clear the RX_DONE interrupt + (bit 7) of the IC_RAW_INTR_STAT register */ + __IM uint32_t RESERVED1 : 31; /*!< (@ 0x00000001) reserved1 */ + } IC_CLR_RX_DONE_b; + }; + + union { + __IM uint32_t IC_CLR_ACTIVITY; /*!< (@ 0x0000005C) Clear ACTIVITY Interrupt Register */ + + struct { + __IM uint32_t CLR_ACTIVITY : 1; /*!< (@ 0x00000000) Reading this register clears the ACTIVITY interrupt + if the I2C is not active any more */ + __IM uint32_t RESERVED1 : 31; /*!< (@ 0x00000001) reserved1 */ + } IC_CLR_ACTIVITY_b; + }; + + union { + __IM uint32_t IC_CLR_STOP_DET; /*!< (@ 0x00000060) Clear STOP_DET Interrupt Register */ + + struct { + __IM uint32_t CLR_STOP_DET : 1; /*!< (@ 0x00000000) Read this register to clear the STOP_DET interrupt + (bit 9) of the IC_RAW_INTR_STAT register. */ + __IM uint32_t RESERVED1 : 31; /*!< (@ 0x00000001) reserved1 */ + } IC_CLR_STOP_DET_b; + }; + + union { + __IM uint32_t IC_CLR_START_DET; /*!< (@ 0x00000064) Clear START_DET Interrupt Register */ + + struct { + __IM uint32_t CLR_START_DET : 1; /*!< (@ 0x00000000) Read this register to clear the START_DET interrupt + (bit 10) of the IC_RAW_INTR_STAT register */ + __IM uint32_t RESERVED1 : 31; /*!< (@ 0x00000001) reserved1 */ + } IC_CLR_START_DET_b; + }; + + union { + __IM uint32_t IC_CLR_GEN_CALL; /*!< (@ 0x00000068) Clear GEN_CALL Interrupt Register */ + + struct { + __IM uint32_t CLR_GEN_CALL : 1; /*!< (@ 0x00000000) Read this register to clear the GEN_CALL interrupt + (bit 11) of IC_RAW_INTR_STAT register */ + __IM uint32_t RESERVED1 : 31; /*!< (@ 0x00000001) reserved1 */ + } IC_CLR_GEN_CALL_b; + }; + + union { + __IOM uint32_t IC_ENABLE; /*!< (@ 0x0000006C) Clear GEN_CALL Interrupt Register */ + + struct { + __IOM uint32_t EN : 1; /*!< (@ 0x00000000) Controls whether the DW_apb_i2c is enabled */ + __IOM uint32_t ABORT : 1; /*!< (@ 0x00000001) When set, the controller initiates the transfer + abort */ + __IOM uint32_t TX_CMD_BLOCK : 1; /*!< (@ 0x00000002) none */ + __IOM uint32_t SDA_STUCK_RECOVERY_ENABLE : 1; + __IM uint32_t RESERVED1 : 12; /*!< (@ 0x00000004) reserved1 */ + __IM uint32_t RESERVED2 : 16; /*!< (@ 0x00000010) reserved2 */ + } IC_ENABLE_b; + }; + + union { + __IM uint32_t IC_STATUS; /*!< (@ 0x00000070) I2C Status Register */ + + struct { + __IM uint32_t ACTIVITY : 1; /*!< (@ 0x00000000) I2C Activity Status */ + __IM uint32_t TFNF : 1; /*!< (@ 0x00000001) Transmit FIFO Not Full */ + __IM uint32_t TFE : 1; /*!< (@ 0x00000002) Transmit FIFO Completely Empty */ + __IM uint32_t RFNE : 1; /*!< (@ 0x00000003) Receive FIFO Not Empty */ + __IM uint32_t RFF : 1; /*!< (@ 0x00000004) Receive FIFO Completely Full */ + __IM uint32_t MST_ACTIVITY : 1; /*!< (@ 0x00000005) Master FSM Activity Status */ + __IM uint32_t SLV_ACTIVITY : 1; /*!< (@ 0x00000006) Slave FSM Activity Status */ + __IM uint32_t MST_HOLD_TX_FIFO_EMPTY : 1; /*!< (@ 0x00000007) The I2C master stalls the write transfer when + Tx FIFO is empty, and the the last byte + does not have the Stop bit set. */ + __IM uint32_t MST_HOLD_RX_FIFO_FULL : 1; /*!< (@ 0x00000008) This bit indicates the BUS Hold in Master mode + due to Rx FIFO is Full and additional byte + has been received. */ + __IM uint32_t SLV_HOLD_TX_FIFO_EMPTY : 1; /*!< (@ 0x00000009) This bit indicates the BUS Hold in Slave mode + for the Read request when the Tx FIFO is + empty. */ + __IM uint32_t SLV_HOLD_RX_FIFO_FULL : 1; /*!< (@ 0x0000000A) This bit indicates the BUS Hold in Slave mode + due to the Rx FIFO being Full and an additional + byte being received. */ + __IM uint32_t SDA_STUCK_NOT_RECOVERED : 1; /*!< (@ 0x0000000B) This bit indicates that an SDA stuck at low is + not recovered after the recovery mechanism. */ + __IM uint32_t RESERVED1 : 20; /*!< (@ 0x0000000C) reserved1 */ + } IC_STATUS_b; + }; + + union { + __IM uint32_t IC_TXFLR; /*!< (@ 0x00000074) I2C Transmit FIFO Level Register */ + + struct { + __IM uint32_t TXFLR : 4; /*!< (@ 0x00000000) Contains the number of valid data entries in + the transmit FIFO. */ + __IM uint32_t RESERVED1 : 28; /*!< (@ 0x00000004) reserved1 */ + } IC_TXFLR_b; + }; + + union { + __IM uint32_t IC_RXFLR; /*!< (@ 0x00000078) I2C Receive FIFO Level Register */ + + struct { + __IM uint32_t RXFLR : 4; /*!< (@ 0x00000000) Receive FIFO Level. Contains the number of valid + data entries in the receive FIFO */ + __IM uint32_t RESERVED1 : 28; /*!< (@ 0x00000004) reserved1 */ + } IC_RXFLR_b; + }; + + union { + __IOM uint32_t IC_SDA_HOLD; /*!< (@ 0x0000007C) I2C SDA Hold Time Length Register */ + + struct { + __IOM uint32_t IC_SDA_TX_HOLD : 16; /*!< (@ 0x00000000) Sets the required SDA hold time in units of ic_clk + period,when I2C acts as a transmitter. */ + __IOM uint32_t IC_SDA_RX_HOLD : 8; /*!< (@ 0x00000010) Sets the required SDA hold time in units of ic_clk + period,when I2C acts as a receiver. */ + __IM uint32_t RESERVED1 : 8; /*!< (@ 0x00000018) reserved1 */ + } IC_SDA_HOLD_b; + }; + + union { + __IM uint32_t IC_TX_ABRT_SOURCE; /*!< (@ 0x00000080) I2C Transmit Abort Source Register */ + + struct { + __IM uint32_t ABRT_7B_ADDR_NOACK : 1; /*!< (@ 0x00000000) 1: Master is in 7-bit addressing mode and the + address sent was not acknowledged by any + slave */ + __IM uint32_t ABRT_10ADDR1_NOACK : 1; /*!< (@ 0x00000001) 1: Master is in 10-bit address mode and the first + 10-bit address byte was not acknowledged + by any slave */ + __IM uint32_t ABRT_10ADDR2_NOACK : 1; /*!< (@ 0x00000002) 1: Master is in 10-bit address mode and the second + address byte of the 10-bit address was + not acknowledged by any slave */ + __IM uint32_t ABRT_TXDATA_NOACK : 1; /*!< (@ 0x00000003) 1: This is a master-mode only bit. Master has + received an acknowledgement for the address, + but when it sent data byte(s) following + the address, it did not receive an acknowledge + from the remote slave(s) */ + __IM uint32_t ABRT_GCALL_NOACK : 1; /*!< (@ 0x00000004) 1: DW_apb_i2c in master mode sent a General Call + and no slave on the bus acknowledged the + General Call */ + __IM uint32_t ABRT_GCALL_READ : 1; /*!< (@ 0x00000005) 1: DW_apb_i2c in master mode sent a General Call + but the user programmed the byte following + the General Call to be a read from the + bus (IC_DATA_CMD[9] is set to 1) */ + __IM uint32_t ABRT_HS_ACKDET : 1; /*!< (@ 0x00000006) 1: Master is in High Speed mode and the High + Speed Master code was acknowledged */ + __IM uint32_t ABRT_SBYTE_ACKDET : 1; /*!< (@ 0x00000007) 1: Master has sent a START Byte and the START + Byte was acknowledged (wrong behavior) */ + __IM uint32_t ABRT_HS_NORSTRT : 1; /*!< (@ 0x00000008) 1: The restart is disabled (IC_RESTART_EN bit + (IC_CON[5]) = 0) and the user is trying + to use the master to transfer data in High + Speed mode */ + __IM uint32_t ABRT_SBYTE_NORSTRT : 1; /*!< (@ 0x00000009) 1: The restart is disabled (IC_RESTART_EN bit + (IC_CON[5]) = 0) and the user is trying + to send a START Byte */ + __IM uint32_t ABRT_10B_RD_NORSTRT : 1; /*!< (@ 0x0000000A) 1: The restart is disabled (IC_RESTART_EN bit + (IC_CON[5]) = 0) and the master sends a + read command in 10-bit addressing mode */ + __IM uint32_t ABRT_MASTER_DIS : 1; /*!< (@ 0x0000000B) 1: User tries to initiate a Master operation + with the Master mode disabled */ + __IM uint32_t ARB_LOST : 1; /*!< (@ 0x0000000C) 1: Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] + is also set, then the slave transmitter + has lost arbitration */ + __IM uint32_t ABRT_SLVFLUSH_TXFIFO : 1; /*!< (@ 0x0000000D) 1: Slave has received a read command and some + data exists in the TX FIFO so the slave + issues a TX_ABRT interrupt to flush old + data in TX FIFO */ + __IM uint32_t ABRT_SLV_ARBLOST : 1; /*!< (@ 0x0000000E) 1: Slave lost the bus while transmitting data + to a remote master. IC_TX_ABRT_SOURCE[12] + is set at the same time */ + __IM uint32_t ABRT_SLVRD_INTX : 1; /*!< (@ 0x0000000F) 1: When the processor side responds to a slave + mode request for data to be transmitted + to a remote master and user writes a 1 + in CMD (bit 8) of IC_DATA_CMD register */ + __IM uint32_t ABRT_USER_ABRT : 1; /*!< (@ 0x00000010) This is a master-mode-only bit. Master has detected + the transfer abort (IC_ENABLE[1]). */ + __IM uint32_t ABRT_SDA_STUCK_AT_LOW : 1; /*!< (@ 0x00000011) Master detects the SDA is Stuck at low for the + IC_SDA_STUCK_AT_LOW_TIMEOUT value of ic_clks */ + __IM uint32_t ABRT_DEVICE_NOACK : 1; /*!< (@ 0x00000012) Master initiates the DEVICE_ID transfer and the + device ID sent is not acknowledged by any + slave */ + __IM uint32_t ABRT_DEVICE_SLVADDR_NOACK : 1; /*!< (@ 0x00000013) Master is initiating the DEVICE_ID transfer and + the slave address sent was not acknowledged + by any slave */ + __IM uint32_t ABRT_DEVICE_WRITE : 1; /*!< (@ 0x00000014) Master is initiating the DEVICE_ID transfer and + the Tx- FIFO consists of write commands. */ + __IM uint32_t RESERVED1 : 2; /*!< (@ 0x00000015) reserved1 */ + __IM uint32_t TX_FLUSH_CNT : 9; /*!< (@ 0x00000017) This field indicates the number of Tx FIFO data + commands that are flushed due to TX_ABRT + interrupt */ + } IC_TX_ABRT_SOURCE_b; + }; + + union { + __IOM uint32_t + IC_SLV_DATA_NACK_ONLY; /*!< (@ 0x00000084) Generate Slave Data NACK Register */ + + struct { + __IOM uint32_t NACK : 1; /*!< (@ 0x00000000) Generate NACK. This NACK generation only occurs + when DW_apb_i2c is a slave receiver. */ + __IM uint32_t RESERVED1 : 31; /*!< (@ 0x00000001) reserved1 */ + } IC_SLV_DATA_NACK_ONLY_b; + }; + + union { + __IOM uint32_t IC_DMA_CR; /*!< (@ 0x00000088) DMA Control Register */ + + struct { + __IOM uint32_t RDMAE : 1; /*!< (@ 0x00000000) Receive DMA Enable */ + __IOM uint32_t TDMAE : 1; /*!< (@ 0x00000001) Transmit DMA Enable.This bit enables/disables + the transmit FIFO DMA channel */ + __IM uint32_t RESERVED1 : 30; /*!< (@ 0x00000002) reserved1 */ + } IC_DMA_CR_b; + }; + + union { + __IOM uint32_t IC_DMA_TDLR; /*!< (@ 0x0000008C) DMA Transmit Data Level Register */ + + struct { + __IOM uint32_t DMATDL : 4; /*!< (@ 0x00000000) This bit field controls the level at which a + DMA request is made by the transmit logic */ + __IM uint32_t RESERVED1 : 28; /*!< (@ 0x00000004) reserved1 */ + } IC_DMA_TDLR_b; + }; + + union { + __IOM uint32_t IC_DMA_RDLR; /*!< (@ 0x00000090) I2C Receive Data Level Register */ + + struct { + __IOM uint32_t DMARDL : 4; /*!< (@ 0x00000000) This bit field controls the level at which a + DMA request is made by the receive logic */ + __IM uint32_t RESERVED1 : 28; /*!< (@ 0x00000004) reserved1 */ + } IC_DMA_RDLR_b; + }; + + union { + __IOM uint32_t IC_SDA_SETUP; /*!< (@ 0x00000094) I2C SDA Setup Register */ + + struct { + __IOM uint32_t SDA_SETUP : 8; /*!< (@ 0x00000000) This register controls the amount of time delay + (in terms of number of ic_clk clock periods) */ + __IM uint32_t RESERVED1 : 24; /*!< (@ 0x00000008) reserved1 */ + } IC_SDA_SETUP_b; + }; + + union { + __IOM uint32_t + IC_ACK_GENERAL_CALL; /*!< (@ 0x00000098) I2C ACK General Call Register */ + + struct { + __IOM uint32_t ACK_GEN_CALL : 1; /*!< (@ 0x00000000) ACK General Call */ + __IM uint32_t RESERVED1 : 31; /*!< (@ 0x00000001) reserved1 */ + } IC_ACK_GENERAL_CALL_b; + }; + + union { + __IOM uint32_t IC_ENABLE_STATUS; /*!< (@ 0x0000009C) I2C Enable Status Register */ + + struct { + __IOM uint32_t ACK_GEN_CALL : 1; /*!< (@ 0x00000000) ACK General Call */ + __IM uint32_t SLV_DISABLED_WHILE_BUSY : 1; /*!< (@ 0x00000001) This bit indicates if a potential or active Slave + operation has been aborted due to the setting + of the IC_ENABLE register from 1 to 0 */ + __IM uint32_t + SLV_RX_DATA_LOST : 1; /*!< (@ 0x00000002) Slave Received Data Lost */ + __IOM uint32_t RESERVED1 : 29; /*!< (@ 0x00000003) reserved1 */ + } IC_ENABLE_STATUS_b; + }; + + union { + __IOM uint32_t IC_FS_SPKLEN; /*!< (@ 0x000000A0) I2C SS and FS Spike Suppression Limit Register */ + + struct { + __IOM uint32_t IC_FS_SPKLEN : 8; /*!< (@ 0x00000000) This register sets the duration, measured in + ic_clk cycles, of the longest spike in + the SCL or SDA lines that are filtered + out by the spike suppression logic */ + __IM uint32_t RESERVED1 : 24; /*!< (@ 0x00000008) reserved1 */ + } IC_FS_SPKLEN_b; + }; + + union { + __IOM uint32_t IC_HS_SPKLEN; /*!< (@ 0x000000A4) I2C HS Spike Suppression Limit Register */ + + struct { + __IOM uint32_t IC_HS_SPKLEN : 8; /*!< (@ 0x00000000) This register sets the duration, measured in + ic_clk cycles, of the longest spike in + the SCL or SDA lines that are filtered + out by the spike suppression logic */ + __IM uint32_t RESERVED1 : 24; /*!< (@ 0x00000008) reserved1 */ + } IC_HS_SPKLEN_b; + }; + + union { + __IM uint32_t IC_CLR_RESTART_DET; /*!< (@ 0x000000A8) Clear RESTART_DET Interrupt Register */ + + struct { + __IM uint32_t CLR_RESTART_DET : 1; /*!< (@ 0x00000000) Read this register to clear the RESTART_DET interrupt + (bit 12) of the IC_RAW_INTR_STAT registe */ + __IM uint32_t RESERVED1 : 31; /*!< (@ 0x00000001) reserved1 */ + } IC_CLR_RESTART_DET_b; + }; + + union { + __IOM uint32_t + IC_SCL_STUCK_AT_LOW_TIMEOUT; /*!< (@ 0x000000AC) I2C SCL Stuck at Low Timeout */ + + struct { + __IOM uint32_t IC_SCL_STUCK_LOW_TIMEOUT : 32; /*!< (@ 0x00000000) Generates the interrupt to indicate SCL stuck + at low if it detects the SCL stuck at low + for the IC_SCL_STUCK_LOW_TIMEOUT in units + of ic_clk period */ + } IC_SCL_STUCK_AT_LOW_TIMEOUT_b; + }; + + union { + __IOM uint32_t + IC_SDA_STUCK_AT_LOW_TIMEOUT; /*!< (@ 0x000000B0) I2C SDA Stuck at Low Timeout */ + + struct { + __IOM uint32_t + IC_SDA_STUCK_LOW_TIMEOUT : 32; /*!< (@ 0x00000000) Initiates the recovery of SDA line , if it detects + the SDA stuck at low for the IC_SDA_STUCK_LOW_TIMEOUT + in units of ic_clk period. */ + } IC_SDA_STUCK_AT_LOW_TIMEOUT_b; + }; + + union { + __IM uint32_t + IC_CLR_SCL_STUCK_DET; /*!< (@ 0x000000B4) Clear SCL Stuck at Low Detect Interrupt Register */ + + struct { + __IM uint32_t CLR_SCL_STUCK : 1; /*!< (@ 0x00000000) Read this register to clear the SCL_STUCK_DET + interrupt */ + __IM uint32_t RESERVED1 : 31; /*!< (@ 0x00000001) reserved1 */ + } IC_CLR_SCL_STUCK_DET_b; + }; + + union { + __IM uint32_t IC_DEVICE_ID; /*!< (@ 0x000000B8) I2C Device ID */ + + struct { + __IM uint32_t DEVICE_ID : 24; /*!< (@ 0x00000000) Contains the Device-ID of the component assigned + through the configuration parameter */ + __IM uint32_t RESERVED1 : 8; /*!< (@ 0x00000018) reserved1 */ + } IC_DEVICE_ID_b; + }; + + union { + __IOM uint32_t + IC_SMBUS_CLOCK_LOW_SEXT; /*!< (@ 0x000000BC) SMBUS Slave Clock Extend Timeout Register */ + + struct { + __IOM uint32_t + SMBUS_CLK_LOW_SEXT_TIMEOUT : 32; /*!< (@ 0x00000000) The values in this register are in units of ic_clk + period. */ + } IC_SMBUS_CLOCK_LOW_SEXT_b; + }; + + union { + __IOM uint32_t + IC_SMBUS_CLOCK_LOW_MEXT; /*!< (@ 0x000000C0) SMBUS Master extend clock Timeout Register */ + + struct { + __IOM uint32_t + SMBUS_CLK_LOW_MEXT_TIMEOUT : 32; /*!< (@ 0x00000000) The values in this register are in units of ic_clk + period.. */ + } IC_SMBUS_CLOCK_LOW_MEXT_b; + }; + + union { + __IOM uint32_t + IC_SMBUS_THIGH_MAX_IDLE_COUNT; /*!< (@ 0x000000C4) SMBus Thigh MAX Bus-Idle count Register */ + + struct { + __IOM uint32_t + SMBUS_THIGH_MAX_BUS_IDLE_CNT : 16; /*!< (@ 0x00000000) The values in this register are in units of ic_clk + period. */ + __IOM uint32_t RESERVED1 : 16; /*!< (@ 0x00000010) Reserved1 */ + } IC_SMBUS_THIGH_MAX_IDLE_COUNT_b; + }; + + union { + __IOM uint32_t IC_SMBUS_INTR_STAT; /*!< (@ 0x000000C8) SMBUS Interrupt Status Register */ + + struct { + __IOM uint32_t RESERVED1 : 32; /*!< (@ 0x00000000) Reserved1 */ + } IC_SMBUS_INTR_STAT_b; + }; + + union { + __IOM uint32_t IC_SMBUS_INTR_MASK; /*!< (@ 0x000000CC) Interrupt Mask Register */ + + struct { + __IOM uint32_t RESERVED1 : 32; /*!< (@ 0x00000000) Reserved1 */ + } IC_SMBUS_INTR_MASK_b; + }; + + union { + __IOM uint32_t + IC_SMBUS_INTR_RAW_STATUS; /*!< (@ 0x000000D0) SMBUS Raw Interrupt Status Register */ + + struct { + __IOM uint32_t RESERVED1 : 32; /*!< (@ 0x00000000) Reserved1. */ + } IC_SMBUS_INTR_RAW_STATUS_b; + }; + + union { + __IOM uint32_t IC_CLR_SMBUS_INTR; /*!< (@ 0x000000D4) Clear SMBUS Interrupt Register */ + + struct { + __IOM uint32_t RESERVED1 : 32; /*!< (@ 0x00000000) RESERVED1 */ + } IC_CLR_SMBUS_INTR_b; + }; + + union { + __IOM uint32_t IC_OPTIONAL_SAR; /*!< (@ 0x000000D8) Optional Slave Address Register */ + + struct { + __IOM uint32_t RESERVED1 : 32; /*!< (@ 0x00000000) Reserved1. */ + } IC_OPTIONAL_SAR_b; + }; + + union { + __IOM uint32_t IC_SMBUS_UDID_LSB; /*!< (@ 0x000000DC) SMBUS ARP UDID LSB Register */ + + struct { + __IOM uint32_t IC_SMBUS_ARP_UDID_LSB : 32; /*!< (@ 0x00000000) This field is used to store the LSB 32 bit value + of slave unique device identifier used + in Address Resolution Protocol. */ + } IC_SMBUS_UDID_LSB_b; + }; + __IM uint32_t RESERVED[5]; + + union { + __IM uint32_t IC_COMP_PARAM_1; /*!< (@ 0x000000F4) I2C HS Spike Suppression Limit Register */ + + struct { + __IM uint32_t CLR_RESTART_DET : 1; /*!< (@ 0x00000000) Read this register to clear the RESTART_DET interrupt + (bit 12) of the IC_RAW_INTR_STAT registe */ + __IM uint32_t : 1; + __IM uint32_t + MAX_SPEED_MODE : 2; /*!< (@ 0x00000002) Maximum Speed Mode */ + __IM uint32_t + HC_COUNT_VALUES : 1; /*!< (@ 0x00000004) Hard Code the count values */ + __IM uint32_t INTR_IO : 1; /*!< (@ 0x00000005) Single Interrupt Output port */ + __IM uint32_t HAS_DMA : 1; /*!< (@ 0x00000006) DMA Handshake Interface signal */ + __IM uint32_t + ADD_ENCODED_PARAMS : 1; /*!< (@ 0x00000007) Add Encoded Parameters */ + __IM uint32_t RX_BUFFER_DEPTH : 8; /*!< (@ 0x00000008) Depth of receive buffer;the buffer is 8 bits + wide;2 to 256 */ + __IM uint32_t TX_BUFFER_DEPTH : 8; /*!< (@ 0x00000010) Depth of Transmit buffer;the buffer is 8 bits + wide;2 to 256 */ + __IM uint32_t RESERVED1 : 8; /*!< (@ 0x00000018) reserved1 */ + } IC_COMP_PARAM_1_b; + }; + + union { + __IM uint32_t IC_COMP_VERSION; /*!< (@ 0x000000F8) I2C Component Version Register */ + + struct { + __IM uint32_t + IC_COMP_VERSION : 32; /*!< (@ 0x00000000) Signifies the component version */ + } IC_COMP_VERSION_b; + }; + + union { + __IM uint32_t IC_COMP_TYPE; /*!< (@ 0x000000FC) I2C Component Type Register */ + + struct { + __IM uint32_t IC_COMP_TYPE : 32; /*!< (@ 0x00000000) Design ware Component Type number = 0x44_57_01_40 */ + } IC_COMP_TYPE_b; + }; +} I2C0_Type; + +typedef struct { + union { + __IOM uint32_t PWM_DEADTIME_A; /*!< NONE */ + + struct { + __IOM uint32_t DEADTIME_A_CH : 6; /*!< Dead time A value to load into dead time counter A of channel0 */ + uint32_t : 26; + } PWM_DEADTIME_A_b; /*!< BitSize */ + }; + + union { + __IOM uint32_t PWM_DEADTIME_B; /*!< NONE */ + + struct { + __IOM uint32_t DEADTIME_B_CH : 6; /*!< Dead time B value to load into deadtime counter B of channel0 */ + uint32_t : 26; + } PWM_DEADTIME_B_b; /*!< BitSize */ + }; +} MCPWM_PWM_DEADTIME_Type; + +/* ================================================================================ */ +/* ================ MCPWM ================ */ +/* ================================================================================ */ + +/** + * @brief The Motor Control PWM (MCPWM) controller is used to generate a periodic pulse waveform, which is useful in motor control and power control applications (MCPWM) + */ + +typedef struct { /*!< (@ 0x47070000) MCPWM Structure */ + + union { + __IM uint32_t PWM_INTR_STS; /*!< (@ 0x00000000) PWM Interrupt Status Register */ + + struct { + __IM uint32_t + RISE_PWM_TIME_PERIOD_MATCH_INTR_CH0 : 1; /*!< (@ 0x00000000) This time base interrupt for 0th channel without + considering postscaler */ + __IM uint32_t PWM_TIME_PRD_MATCH_INTR_CH0 : 1; /*!< (@ 0x00000001) This time base interrupt for 0th channel, which + considers postscaler value */ + __IM uint32_t FLT_A_INTR : 1; /*!< (@ 0x00000002) When the fault A pin is driven low, this interrupt + is raised. */ + __IM uint32_t FLT_B_INTR : 1; /*!< (@ 0x00000003) When the fault B pin is driven low, this interrupt + is raised. */ + __IM uint32_t + RISE_PWM_TIME_PERIOD_MATCH_INTR_CH1 : 1; /*!< (@ 0x00000004) This time base interrupt for 1st channel without + considering postscaler value */ + __IM uint32_t PWM_TIME_PRD_MATCH_INTR_CH1 : 1; /*!< (@ 0x00000005) This time base interrupt for 1st channel, which + considers postscaler value. */ + __IM uint32_t + RISE_PWM_TIME_PERIOD_MATCH_INTR_CH2 : 1; /*!< (@ 0x00000006) This time base interrupt for 2nd channel without + considering postscaler value. */ + __IM uint32_t PWM_TIME_PRD_MATCH_INTR_CH2 : 1; /*!< (@ 0x00000007) This time base interrupt for 2nd channel, which + considers postscaler value */ + __IM uint32_t + RISE_PWM_TIME_PERIOD_MATCH_INTR_CH3 : 1; /*!< (@ 0x00000008) This time base interrupt for 3rd channel without + considering postscaler value. */ + __IM uint32_t PWM_TIME_PRD_MATCH_INTR_CH3 : 1; /*!< (@ 0x00000009) This time base interrupt for 3rd channel, which + considers postscaler value. */ + __IM uint32_t RESERVED1 : 22; /*!< (@ 0x0000000A) reserved1 */ + } PWM_INTR_STS_b; + }; + + union { + __IOM uint32_t PWM_INTR_UNMASK; /*!< (@ 0x00000004) PWM Interrupt Unmask Register */ + + struct { + __IOM uint32_t + PWM_INTR_UNMASK : 16; /*!< (@ 0x00000000) Interrupt Unmask */ + __IOM uint32_t RESERVED1 : 16; /*!< (@ 0x00000010) reserved1 */ + } PWM_INTR_UNMASK_b; + }; + + union { + __IOM uint32_t PWM_INTR_MASK; /*!< (@ 0x00000008) PWM Interrupt mask Register */ + + struct { + __IOM uint32_t + PWM_INTR_UNMASK : 16; /*!< (@ 0x00000000) Interrupt Mask */ + __IOM uint32_t RESERVED1 : 16; /*!< (@ 0x00000010) reserved1 */ + } PWM_INTR_MASK_b; + }; + + union { + __IOM uint32_t PWM_INTR_ACK; /*!< (@ 0x0000000C) PWM Interrupt Acknowledgement Register */ + + struct { + __OM uint32_t + RISE_PWM_TIME_PERIOD_MATCH_CH0_ACK : 1; /*!< (@ 0x00000000) pwm time period match interrupt for 0th channel + will be cleared. */ + __OM uint32_t + PWM_TIME_PRD_MATCH_INTR_CH0_ACK : 1; /*!< (@ 0x00000001) pwm time period match interrupt for 0th channel + will be cleared */ + __OM uint32_t + FLT_A_INTR_ACK : 1; /*!< (@ 0x00000002) pwm fault A interrupt will be cleared. */ + __OM uint32_t + FLT_B_INTR_ACK : 1; /*!< (@ 0x00000003) pwm fault B interrupt will be cleared. */ + __OM uint32_t + RISE_PWM_TIME_PERIOD_MATCH_CH1_ACK : 1; /*!< (@ 0x00000004) pwm time period match interrupt for 1st channel + will be cleared */ + __OM uint32_t + PWM_TIME_PRD_MATCH_INTR_CH1_ACK : 1; /*!< (@ 0x00000005) pwm time period match interrupt for 1st channel + will be cleared. */ + __OM uint32_t + RISE_PWM_TIME_PERIOD_MATCH_CH2_ACK : 1; /*!< (@ 0x00000006) pwm time period match interrupt for 2nd channel + will be cleared. */ + __OM uint32_t + PWM_TIME_PRD_MATCH_INTR_CH2_ACK : 1; /*!< (@ 0x00000007) pwm time period match interrupt for 2nd channel + will be cleared. */ + __OM uint32_t + RISE_PWM_TIME_PERIOD_MATCH_CH3_ACK : 1; /*!< (@ 0x00000008) pwm time period match interrupt for 3rd channel + will be cleared. */ + __OM uint32_t + PWM_TIME_PRD_MATCH_INTR_CH3_ACK : 1; /*!< (@ 0x00000009) pwm time period match interrupt for 3rd channel + will be cleared. */ + __IOM uint32_t RESERVED1 : 22; /*!< (@ 0x0000000A) reserved1 */ + } PWM_INTR_ACK_b; + }; + __IM uint32_t RESERVED[6]; + + union { + __IOM uint32_t + PWM_TIME_PRD_WR_REG_CH0; /*!< (@ 0x00000028) Base timer period register of channel 0 */ + + struct { + __IOM uint32_t + PWM_TIME_PRD_REG_WR_VALUE_CH0 : 16; /*!< (@ 0x00000000) Value to update the base timer period register + of channel 0 */ + __IOM uint32_t RESERVED1 : 16; /*!< (@ 0x00000010) reserved1 */ + } PWM_TIME_PRD_WR_REG_CH0_b; + }; + + union { + __IOM uint32_t PWM_TIME_PRD_CNTR_WR_REG_CH0; /*!< (@ 0x0000002C) Base time counter initial value register for + channel 0 */ + + struct { + __IOM uint32_t + PWM_TIME_PRD_CNTR_WR_REG_CH0 : 16; /*!< (@ 0x00000000) To update the base time counter initial value + for channel 0 */ + __IOM uint32_t RESERVED1 : 16; /*!< (@ 0x00000010) reserved1 */ + } PWM_TIME_PRD_CNTR_WR_REG_CH0_b; + }; + + union { + __IOM uint32_t PWM_TIME_PRD_PARAM_REG_CH0; /*!< (@ 0x00000030) Base time period config parameter's register + for channel0 */ + + struct { + __IOM uint32_t + TMR_OPEARATING_MODE_CH0 : 3; /*!< (@ 0x00000000) Base timer operating mode for channel0 */ + __IOM uint32_t RESERVED1 : 1; /*!< (@ 0x00000003) reserved1 */ + __IOM uint32_t + PWM_TIME_PRD_PRE_SCALAR_VALUE_CH0 : 3; /*!< (@ 0x00000004) Base timer input clock pre scale select value + for channel0. */ + __IOM uint32_t RESERVED2 : 1; /*!< (@ 0x00000007) reserved2 */ + __IOM uint32_t + PWM_TIME_PRD_POST_SCALAR_VALUE_CH0 : 4; /*!< (@ 0x00000008) Time base output post scale bits for channel0 */ + __IOM uint32_t RESERVED3 : 20; /*!< (@ 0x0000000C) reserved3 */ + } PWM_TIME_PRD_PARAM_REG_CH0_b; + }; + + union { + __IOM uint32_t PWM_TIME_PRD_CTRL_REG_CH0; /*!< (@ 0x00000034) Base time counter initial value register for + channel 0 */ + + struct { + __IOM uint32_t + PWM_TIME_PRD_CNTR_RST_FRM_REG : 1; /*!< (@ 0x00000000) Time period counter soft reset */ + __IOM uint32_t + PWM_TIME_BASE_EN_FRM_REG_CH0 : 1; /*!< (@ 0x00000001) Base timer enable for channnel0 */ + __IOM uint32_t PWM_SFT_RST : 1; /*!< (@ 0x00000002) MC PWM soft reset */ + __IM uint32_t RESERVED1 : 29; /*!< (@ 0x00000003) reserved1 */ + } PWM_TIME_PRD_CTRL_REG_CH0_b; + }; + + union { + __IM uint32_t + PWM_TIME_PRD_STS_REG_CH0; /*!< (@ 0x00000038) Base time period status register for channel0 */ + + struct { + __IM uint32_t + PWM_TIME_PRD_DIR_STS_CH0 : 1; /*!< (@ 0x00000000) Time period counter direction status for channel0 */ + __IM uint32_t RESERVED1 : 31; /*!< (@ 0x00000001) reserved1 */ + } PWM_TIME_PRD_STS_REG_CH0_b; + }; + + union { + __IM uint32_t PWM_TIME_PRD_CNTR_VALUE_CH0; /*!< (@ 0x0000003C) Base Time period counter current value register + for channel0 */ + + struct { + __IM uint32_t + PWM_TIME_PRD_CNTR_VALUE_CH0 : 16; /*!< (@ 0x00000000) Time period counter current value for channel0 */ + __IM uint32_t RESERVED1 : 16; /*!< (@ 0x00000010) reserved1 */ + } PWM_TIME_PRD_CNTR_VALUE_CH0_b; + }; + __IM uint32_t RESERVED1[4]; + + union { + __IOM uint32_t + PWM_DUTYCYCLE_CTRL_SET_REG; /*!< (@ 0x00000050) Duty cycle Control Set Register */ + + struct { + __IOM uint32_t + IMDT_DUTYCYCLE_UPDATE_EN : 4; /*!< (@ 0x00000000) Enable to update the duty cycle immediately */ + __IOM uint32_t DUTYCYCLE_UPDATE_DISABLE : 4; /*!< (@ 0x00000004) Duty cycle register updation disable. There is + a separate bit for each channel */ + __IM uint32_t RESERVED1 : 24; /*!< (@ 0x00000008) reserved1 */ + } PWM_DUTYCYCLE_CTRL_SET_REG_b; + }; + + union { + __IOM uint32_t + PWM_DUTYCYCLE_CTRL_RESET_REG; /*!< (@ 0x00000054) Duty cycle Control Reset Register */ + + struct { + __IOM uint32_t + IMDT_DUTYCYCLE_UPDATE_EN : 4; /*!< (@ 0x00000000) Enable to update the duty cycle immediately */ + __IOM uint32_t DUTYCYCLE_UPDATE_DISABLE : 4; /*!< (@ 0x00000004) Duty cycle register updation disable. There is + a separate bit for each channel. */ + __IM uint32_t RESERVED1 : 24; /*!< (@ 0x00000008) reserved1 */ + } PWM_DUTYCYCLE_CTRL_RESET_REG_b; + }; + + union { + __IOM uint32_t + PWM_DUTYCYCLE_REG_WR_VALUE[4]; /*!< (@ 0x00000058) Duty cycle Value Register for Channel0 to channel3 */ + + struct { + __IOM uint32_t + PWM_DUTYCYCLE_REG_WR_VALUE_CH : 16; /*!< (@ 0x00000000) Duty cycle value for channel0 to channel3 */ + __IM uint32_t RESERVED1 : 16; /*!< (@ 0x00000010) reserved1 */ + } PWM_DUTYCYCLE_REG_WR_VALUE_b[4]; + }; + __IM uint32_t RESERVED2[4]; + + union { + __IOM uint32_t + PWM_DEADTIME_CTRL_SET_REG; /*!< (@ 0x00000078) Dead time Control Set Register */ + + struct { + __IOM uint32_t + DEADTIME_SELECT_ACTIVE : 4; /*!< (@ 0x00000000) Dead time select bits for PWM going active */ + __IOM uint32_t + DEADTIME_SELECT_INACTIVE : 4; /*!< (@ 0x00000004) Dead time select bits for PWM going inactive */ + __IOM uint32_t + DEADTIME_DISABLE_FRM_REG : 4; /*!< (@ 0x00000008) Dead time counter soft reset for each channel. */ + __IM uint32_t RESERVED1 : 20; /*!< (@ 0x0000000C) reserved1 */ + } PWM_DEADTIME_CTRL_SET_REG_b; + }; + + union { + __IOM uint32_t + PWM_DEADTIME_CTRL_RESET_REG; /*!< (@ 0x0000007C) Dead time Control Reset Register */ + + struct { + __IOM uint32_t + DEADTIME_SELECT_ACTIVE : 4; /*!< (@ 0x00000000) Dead time select bits for PWM going active */ + __IOM uint32_t + DEADTIME_SELECT_INACTIVE : 4; /*!< (@ 0x00000004) Dead time select bits for PWM going inactive */ + __IOM uint32_t + DEADTIME_DISABLE_FRM_REG : 4; /*!< (@ 0x00000008) Dead time counter soft reset for each channel. */ + __IM uint32_t RESERVED1 : 20; /*!< (@ 0x0000000C) reserved1 */ + } PWM_DEADTIME_CTRL_RESET_REG_b; + }; + + union { + __IOM uint32_t + PWM_DEADTIME_PRESCALE_SELECT_A; /*!< (@ 0x00000080) Dead time Prescale Select Register for A */ + + struct { + __IOM uint32_t + DEADTIME_PRESCALE_SELECT_A : 8; /*!< (@ 0x00000000) Dead time prescale selection bits for unit A. */ + __IM uint32_t RESERVED1 : 24; /*!< (@ 0x00000008) reserved1 */ + } PWM_DEADTIME_PRESCALE_SELECT_A_b; + }; + + union { + __IOM uint32_t + PWM_DEADTIME_PRESCALE_SELECT_B; /*!< (@ 0x00000084) Dead time Prescale Select Register for B */ + + struct { + __IOM uint32_t + DEADTIME_PRESCALE_SELECT_B : 8; /*!< (@ 0x00000000) Dead time prescale selection bits for unit B */ + __IM uint32_t RESERVED1 : 24; /*!< (@ 0x00000008) reserved1 */ + } PWM_DEADTIME_PRESCALE_SELECT_B_b; + }; + __IOM MCPWM_PWM_DEADTIME_Type + PWM_DEADTIME[4]; /*!< (@ 0x00000088) [0..3] */ + __IM uint32_t RESERVED3[8]; + + union { + __IOM uint32_t + PWM_OP_OVERRIDE_CTRL_SET_REG; /*!< (@ 0x000000C8) output override control set register */ + + struct { + __IOM uint32_t OP_OVERRIDE_SYNC : 1; /*!< (@ 0x00000000) Output override is synced with pwm time period + depending on operating mode */ + __IM uint32_t RESERVED1 : 31; /*!< (@ 0x00000001) reserved1 */ + } PWM_OP_OVERRIDE_CTRL_SET_REG_b; + }; + + union { + __IOM uint32_t + PWM_OP_OVERRIDE_CTRL_RESET_REG; /*!< (@ 0x000000CC) output override control reset register */ + + struct { + __IOM uint32_t OP_OVERRIDE_SYNC : 1; /*!< (@ 0x00000000) Output override is synced with pwm time period + depending on operating mode */ + __IOM uint32_t RESERVED1 : 31; /*!< (@ 0x00000001) reserved1 */ + } PWM_OP_OVERRIDE_CTRL_RESET_REG_b; + }; + + union { + __IOM uint32_t + PWM_OP_OVERRIDE_ENABLE_SET_REG; /*!< (@ 0x000000D0) output override enable set register */ + + struct { + __IOM uint32_t + PWM_OP_OVERRIDE_ENABLE_REG : 8; /*!< (@ 0x00000000) Pwm output over ride enable */ + __IOM uint32_t RESERVED1 : 24; /*!< (@ 0x00000008) reserved1 */ + } PWM_OP_OVERRIDE_ENABLE_SET_REG_b; + }; + + union { + __IOM uint32_t + PWM_OP_OVERRIDE_ENABLE_RESET_REG; /*!< (@ 0x000000D4) output override enable reset register */ + + struct { + __IOM uint32_t + PWM_OP_OVERRIDE_ENABLE_REG : 8; /*!< (@ 0x00000000) Pwm output over ride enable */ + __IOM uint32_t RESERVED1 : 24; /*!< (@ 0x00000008) reserved1 */ + } PWM_OP_OVERRIDE_ENABLE_RESET_REG_b; + }; + + union { + __IOM uint32_t + PWM_OP_OVERRIDE_VALUE_SET_REG; /*!< (@ 0x000000D8) output override value set register */ + + struct { + __IOM uint32_t + OP_OVERRIDE_VALUE : 8; /*!< (@ 0x00000000) Pwm output over ride value. */ + __IOM uint32_t RESERVED1 : 24; /*!< (@ 0x00000008) reserved1 */ + } PWM_OP_OVERRIDE_VALUE_SET_REG_b; + }; + + union { + __IOM uint32_t + PWM_OP_OVERRIDE_VALUE_RESET_REG; /*!< (@ 0x000000DC) output override enable reset register */ + + struct { + __IOM uint32_t + OP_OVERRIDE_VALUE : 8; /*!< (@ 0x00000000) Pwm output over ride value. */ + __IOM uint32_t RESERVED1 : 24; /*!< (@ 0x00000008) reserved1 */ + } PWM_OP_OVERRIDE_VALUE_RESET_REG_b; + }; + + union { + __IOM uint32_t + PWM_FLT_OVERRIDE_CTRL_SET_REG; /*!< (@ 0x000000E0) fault override control set register */ + + struct { + __IOM uint32_t FLT_A_MODE : 1; /*!< (@ 0x00000000) Fault A mode */ + __IOM uint32_t FLT_B_MODE : 1; /*!< (@ 0x00000001) Fault B mode */ + __IOM uint32_t OP_POLARITY_H : 1; /*!< (@ 0x00000002) Ouput polarity for high (H3, H2, H1, H0) side + signals */ + __IOM uint32_t OP_POLARITY_L : 1; /*!< (@ 0x00000003) Ouput polarity for low (L3, L2, L1, L0) side + signals. */ + __IOM uint32_t FLT_A_ENABLE : 4; /*!< (@ 0x00000004) Fault A enable. Separate enable bit is present + for channel */ + __IOM uint32_t FLT_B_ENABLE : 4; /*!< (@ 0x00000008) Fault B enable. Separate enable bit is present + for channel */ + __IOM uint32_t + COMPLEMENTARY_MODE : 4; /*!< (@ 0x0000000C) PWM I/O pair mode */ + __IOM uint32_t RESERVED1 : 16; /*!< (@ 0x00000010) reserved1 */ + } PWM_FLT_OVERRIDE_CTRL_SET_REG_b; + }; + + union { + __IOM uint32_t + PWM_FLT_OVERRIDE_CTRL_RESET_REG; /*!< (@ 0x000000E4) fault override control reset register */ + + struct { + __IOM uint32_t FLT_A_MODE : 1; /*!< (@ 0x00000000) Fault B mode */ + __IOM uint32_t FLT_B_MODE : 1; /*!< (@ 0x00000001) Fault B mode */ + __IOM uint32_t OP_POLARITY_H : 1; /*!< (@ 0x00000002) Ouput polarity for high (H3, H2, H1, H0) side + signals */ + __IOM uint32_t OP_POLARITY_L : 1; /*!< (@ 0x00000003) Ouput polarity for low (L3, L2, L1, L0) side + signals. */ + __IOM uint32_t FLT_A_ENABLE : 4; /*!< (@ 0x00000004) Fault A enable. Separate enable bit is present + for channel */ + __IOM uint32_t FLT_B_ENABLE : 4; /*!< (@ 0x00000008) Fault B enable. Separate enable bit is present + for channel */ + __IOM uint32_t + COMPLEMENTARY_MODE : 4; /*!< (@ 0x0000000C) PWM I/O pair mode */ + __IOM uint32_t RESERVED1 : 16; /*!< (@ 0x00000010) reserved1 */ + } PWM_FLT_OVERRIDE_CTRL_RESET_REG_b; + }; + + union { + __IOM uint32_t + PWM_FLT_A_OVERRIDE_VALUE_REG; /*!< (@ 0x000000E8) Fault input A PWM override value */ + + struct { + __IOM uint32_t + PWM_FLT_A_OVERRIDE_VALUE_L0 : 1; /*!< (@ 0x00000000) 0 bit for L0 */ + __IOM uint32_t + PWM_FLT_A_OVERRIDE_VALUE_L1 : 1; /*!< (@ 0x00000001) 1 bit for L1 */ + __IOM uint32_t + PWM_FLT_A_OVERRIDE_VALUE_L2 : 1; /*!< (@ 0x00000002) 2 bit for L2 */ + __IOM uint32_t + PWM_FLT_A_OVERRIDE_VALUE_L3 : 1; /*!< (@ 0x00000003) 3 bit for L3 */ + __IOM uint32_t + PWM_FLT_A_OVERRIDE_VALUE_H0 : 1; /*!< (@ 0x00000004) 4 bit for H0 */ + __IOM uint32_t + PWM_FLT_A_OVERRIDE_VALUE_H1 : 1; /*!< (@ 0x00000005) 5 bit for H1 */ + __IOM uint32_t + PWM_FLT_A_OVERRIDE_VALUE_H2 : 1; /*!< (@ 0x00000006) 6 bit for H2 */ + __IOM uint32_t + PWM_FLT_A_OVERRIDE_VALUE_H3 : 1; /*!< (@ 0x00000007) 7 bit for H3 */ + __IOM uint32_t RESERVED1 : 24; /*!< (@ 0x00000008) reserved1 */ + } PWM_FLT_A_OVERRIDE_VALUE_REG_b; + }; + + union { + __IOM uint32_t + PWM_FLT_B_OVERRIDE_VALUE_REG; /*!< (@ 0x000000EC) Fault input B PWM override value */ + + struct { + __IOM uint32_t + PWM_FLT_B_OVERRIDE_VALUE_L0 : 1; /*!< (@ 0x00000000) 0 bit for L0 */ + __IOM uint32_t + PWM_FLT_B_OVERRIDE_VALUE_L1 : 1; /*!< (@ 0x00000001) 1 bit for L1 */ + __IOM uint32_t + PWM_FLT_B_OVERRIDE_VALUE_L2 : 1; /*!< (@ 0x00000002) 2 bit for L2 */ + __IOM uint32_t + PWM_FLT_B_OVERRIDE_VALUE_L3 : 1; /*!< (@ 0x00000003) 3 bit for L3 */ + __IOM uint32_t + PWM_FLT_B_OVERRIDE_VALUE_H0 : 1; /*!< (@ 0x00000004) 4 bit for H0 */ + __IOM uint32_t + PWM_FLT_B_OVERRIDE_VALUE_H1 : 1; /*!< (@ 0x00000005) 5 bit for H1 */ + __IOM uint32_t + PWM_FLT_B_OVERRIDE_VALUE_H2 : 1; /*!< (@ 0x00000006) 6 bit for H2 */ + __IOM uint32_t + PWM_FLT_B_OVERRIDE_VALUE_H3 : 1; /*!< (@ 0x00000007) 7 bit for H3 */ + __IOM uint32_t RESERVED1 : 24; /*!< (@ 0x00000008) reserved1 */ + } PWM_FLT_B_OVERRIDE_VALUE_REG_b; + }; + + union { + __IOM uint32_t + PWM_SVT_CTRL_SET_REG; /*!< (@ 0x000000F0) NONE */ + + struct { + __IOM uint32_t SVT_ENABLE_FRM : 1; /*!< (@ 0x00000000) Special event trigger enable. This is used to + enable generation special event trigger */ + __IOM uint32_t + SVT_DIRECTION_FRM : 1; /*!< (@ 0x00000001) Special event trigger for time base direction */ + __IOM uint32_t RESERVED1 : 30; /*!< (@ 0x00000002) reserved1 */ + } PWM_SVT_CTRL_SET_REG_b; + }; + + union { + __IOM uint32_t + PWM_SVT_CTRL_RESET_REG; /*!< (@ 0x000000F4) Special event control reset register */ + + struct { + __IOM uint32_t SVT_ENABLE_FRM : 1; /*!< (@ 0x00000000) Special event trigger enable. This is used to + enable generation special event trigger */ + __IOM uint32_t + SVT_DIRECTION_FRM : 1; /*!< (@ 0x00000001) Special event trigger for time base direction */ + __IOM uint32_t RESERVED1 : 30; /*!< (@ 0x00000002) reserved1 */ + } PWM_SVT_CTRL_RESET_REG_b; + }; + + union { + __IOM uint32_t PWM_SVT_PARAM_REG; /*!< (@ 0x000000F8) Special event parameter register */ + + struct { + __IOM uint32_t SVT_POSTSCALER_SELECT : 4; /*!< (@ 0x00000000) PWM special event trigger output postscale select + bits */ + __IOM uint32_t RESERVED1 : 28; /*!< (@ 0x00000004) reserved1 */ + } PWM_SVT_PARAM_REG_b; + }; + + union { + __IOM uint32_t + PWM_SVT_COMPARE_VALUE_REG; /*!< (@ 0x000000FC) Special event compare value register */ + + struct { + __IOM uint32_t PWM_SVT_COMPARE_VALUE : 16; /*!< (@ 0x00000000) Special event compare value. This is used to + compare with pwm time period counter to + generate special event trigger */ + __IOM uint32_t RESERVED1 : 16; /*!< (@ 0x00000010) reserved1 */ + } PWM_SVT_COMPARE_VALUE_REG_b; + }; + + union { + __IOM uint32_t + PWM_TIME_PRD_WR_REG_CH1; /*!< (@ 0x00000100) Base timer period register of channel1 */ + + struct { + __IOM uint32_t + PWM_TIME_PRD_REG_WR_VALUE_CH1 : 16; /*!< (@ 0x00000000) Value to update the base timer period register + of channel 1 */ + __IOM uint32_t RESERVED1 : 16; /*!< (@ 0x00000010) reserved1 */ + } PWM_TIME_PRD_WR_REG_CH1_b; + }; + + union { + __IOM uint32_t PWM_TIME_PRD_CNTR_WR_REG_CH1; /*!< (@ 0x00000104) Base time counter initial value register for + channel1 */ + + struct { + __IOM uint32_t + PWM_TIME_PRD_CNTR_WR_REG_CH1 : 16; /*!< (@ 0x00000000) To update the base time counter initial value + for channel 1 */ + __IOM uint32_t RESERVED1 : 16; /*!< (@ 0x00000010) reserved1 */ + } PWM_TIME_PRD_CNTR_WR_REG_CH1_b; + }; + + union { + __IOM uint32_t + PWM_TIME_PRD_PARAM_REG_CH1; /*!< (@ 0x00000108) NONE */ + + struct { + __IOM uint32_t + TMR_OPEARATING_MODE_CH1 : 3; /*!< (@ 0x00000000) Base timer operating mode for channel1 */ + __IOM uint32_t RESERVED1 : 1; /*!< (@ 0x00000003) reserved1 */ + __IOM uint32_t + PWM_TIME_PRD_PRE_SCALAR_VALUE_CH1 : 3; /*!< (@ 0x00000004) Base timer input clock prescale select value + for channel1. */ + __IOM uint32_t RESERVED2 : 1; /*!< (@ 0x00000007) reserved2 */ + __IOM uint32_t + PWM_TIME_PRD_POST_SCALAR_VALUE_CH1 : 4; /*!< (@ 0x00000008) Time base output post scale bits for channel1 */ + __IOM uint32_t RESERVED3 : 20; /*!< (@ 0x0000000C) reserved3 */ + } PWM_TIME_PRD_PARAM_REG_CH1_b; + }; + + union { + __IOM uint32_t + PWM_TIME_PRD_CTRL_REG_CH1; /*!< (@ 0x0000010C) Base time period control register for channel1 */ + + struct { + __IOM uint32_t + PWM_TIME_PRD_CNTR_RST_FRM_REG : 1; /*!< (@ 0x00000000) Time period counter soft reset */ + __IOM uint32_t + PWM_TIME_BASE_EN_FRM_REG_CH1 : 1; /*!< (@ 0x00000001) Base timer enable for channnel1 */ + __IOM uint32_t PWM_SFT_RST : 1; /*!< (@ 0x00000002) MC PWM soft reset */ + __IOM uint32_t RESERVED1 : 29; /*!< (@ 0x00000003) reserved1 */ + } PWM_TIME_PRD_CTRL_REG_CH1_b; + }; + + union { + __IM uint32_t + PWM_TIME_PRD_STS_REG_CH1; /*!< (@ 0x00000110) Base time period status register for channel1 */ + + struct { + __IM uint32_t + PWM_TIME_PRD_DIR_STS_CH1 : 1; /*!< (@ 0x00000000) Time period counter direction status for channel1. */ + __IM uint32_t RESERVED1 : 31; /*!< (@ 0x00000001) reserved1 */ + } PWM_TIME_PRD_STS_REG_CH1_b; + }; + + union { + __IOM uint32_t + PWM_TIME_PRD_CNTR_VALUE_CH1; /*!< (@ 0x00000114) Time period counter current value for channel1 */ + + struct { + __IOM uint32_t + PWM_TIME_PRD_CNTR_VALUE_CH1 : 1; /*!< (@ 0x00000000) Time period counter current value for channel1 */ + __IM uint32_t RESERVED1 : 31; /*!< (@ 0x00000001) reserved1 */ + } PWM_TIME_PRD_CNTR_VALUE_CH1_b; + }; + + union { + __IOM uint32_t + PWM_TIME_PRD_WR_REG_CH2; /*!< (@ 0x00000118) Base timer period register of channel2 */ + + struct { + __IOM uint32_t + PWM_TIME_PRD_REG_WR_VALUE_CH2 : 16; /*!< (@ 0x00000000) Value to update the base timer period register + of channel 2 */ + __IOM uint32_t RESERVED1 : 16; /*!< (@ 0x00000010) reserved1 */ + } PWM_TIME_PRD_WR_REG_CH2_b; + }; + + union { + __IOM uint32_t PWM_TIME_PRD_CNTR_WR_REG_CH2; /*!< (@ 0x0000011C) Base time counter initial value register for + channal2 */ + + struct { + __IOM uint32_t + PWM_TIME_PRD_CNTR_WR_REG_CH2 : 16; /*!< (@ 0x00000000) To update the base time counter initial value + for channel 2 */ + __IOM uint32_t RESERVED1 : 16; /*!< (@ 0x00000010) reserved1 */ + } PWM_TIME_PRD_CNTR_WR_REG_CH2_b; + }; + + union { + __IOM uint32_t PWM_TIME_PRD_PARAM_REG_CH2; /*!< (@ 0x00000120) Base time period config parameter's register + for channel2 */ + + struct { + __IOM uint32_t + TMR_OPEARATING_MODE_CH2 : 3; /*!< (@ 0x00000000) Base timer operating mode for channel2 */ + __IOM uint32_t RESERVED1 : 1; /*!< (@ 0x00000003) reserved1 */ + __IOM uint32_t + PWM_TIME_PRD_PRE_SCALAR_VALUE_CH2 : 3; /*!< (@ 0x00000004) Base timer input clock pre scale select value + for channel2. */ + __IOM uint32_t RESERVED2 : 1; /*!< (@ 0x00000007) reserved2 */ + __IOM uint32_t + PWM_TIME_PRD_POST_SCALAR_VALUE_CH2 : 4; /*!< (@ 0x00000008) Time base output post scale bits for channel2 */ + __IOM uint32_t RESERVED3 : 20; /*!< (@ 0x0000000C) reserved3 */ + } PWM_TIME_PRD_PARAM_REG_CH2_b; + }; + + union { + __IOM uint32_t + PWM_TIME_PRD_CTRL_REG_CH2; /*!< (@ 0x00000124) Base time period control register for channel2 */ + + struct { + __IOM uint32_t + PWM_TIME_PRD_CNTR_RST_FRM_REG : 1; /*!< (@ 0x00000000) Time period counter soft reset */ + __IOM uint32_t + PWM_TIME_BASE_EN_FRM_REG_CH2 : 1; /*!< (@ 0x00000001) Base timer enable for channnel2 */ + __IOM uint32_t PWM_SFT_RST : 1; /*!< (@ 0x00000002) MC PWM soft reset */ + __IOM uint32_t RESERVED1 : 29; /*!< (@ 0x00000003) reserved1 */ + } PWM_TIME_PRD_CTRL_REG_CH2_b; + }; + + union { + __IM uint32_t + PWM_TIME_PRD_STS_REG_CH2; /*!< (@ 0x00000128) Base time period status register for channel2 */ + + struct { + __IM uint32_t + PWM_TIME_PRD_DIR_STS_CH2 : 1; /*!< (@ 0x00000000) Time period counter direction status for channel2. */ + __IM uint32_t RESERVED1 : 31; /*!< (@ 0x00000001) reserved1 */ + } PWM_TIME_PRD_STS_REG_CH2_b; + }; + + union { + __IM uint32_t PWM_TIME_PRD_CNTR_VALUE_CH2; /*!< (@ 0x0000012C) Time period counter current value register for + channel2 */ + + struct { + __IM uint32_t + PWM_TIME_PRD_CNTR_VALUE_CH2 : 1; /*!< (@ 0x00000000) Time period counter current value for channel2 */ + __IM uint32_t RESERVED1 : 11; /*!< (@ 0x00000001) reserved1 */ + __IM uint32_t RESERVED2 : 20; /*!< (@ 0x0000000C) reserved2 */ + } PWM_TIME_PRD_CNTR_VALUE_CH2_b; + }; + + union { + __IOM uint32_t + PWM_TIME_PRD_WR_REG_CH3; /*!< (@ 0x00000130) Base timer period register of channel3 */ + + struct { + __IOM uint32_t + PWM_TIME_PRD_REG_WR_VALUE_CH3 : 16; /*!< (@ 0x00000000) To update the base time counter initial value + for channel 3 */ + __IOM uint32_t RESERVED1 : 16; /*!< (@ 0x00000010) reserved1 */ + } PWM_TIME_PRD_WR_REG_CH3_b; + }; + + union { + __IOM uint32_t PWM_TIME_PRD_CNTR_WR_REG_CH3; /*!< (@ 0x00000134) Base time counter initial value register for + channel3 */ + + struct { + __IOM uint32_t + PWM_TIME_PRD_CNTR_WR_REG_CH3 : 16; /*!< (@ 0x00000000) Value to update the base timer period register + of channel 3 */ + __IOM uint32_t RESERVED1 : 16; /*!< (@ 0x00000010) reserved1 */ + } PWM_TIME_PRD_CNTR_WR_REG_CH3_b; + }; + + union { + __IOM uint32_t PWM_TIME_PRD_PARAM_REG_CH3; /*!< (@ 0x00000138) Base time period config parameter's register + for channel3 */ + + struct { + __IOM uint32_t + TMR_OPEARATING_MODE_CH3 : 3; /*!< (@ 0x00000000) Base timer operating mode for channel3 */ + __IOM uint32_t RESERVED1 : 1; /*!< (@ 0x00000003) reserved1 */ + __IOM uint32_t + PWM_TIME_PRD_PRE_SCALAR_VALUE_CH3 : 3; /*!< (@ 0x00000004) Base timer input clock pre scale select value + for channel2. */ + __IOM uint32_t RESERVED2 : 1; /*!< (@ 0x00000007) reserved2 */ + __IOM uint32_t + PWM_TIME_PRD_POST_SCALAR_VALUE_CH3 : 4; /*!< (@ 0x00000008) Time base output post scale bits for channel3 */ + __IOM uint32_t RESERVED3 : 20; /*!< (@ 0x0000000C) reserved3 */ + } PWM_TIME_PRD_PARAM_REG_CH3_b; + }; + + union { + __IOM uint32_t + PWM_TIME_PRD_CTRL_REG_CH3; /*!< (@ 0x0000013C) Base time period control register for channel3 */ + + struct { + __IOM uint32_t + PWM_TIME_PRD_CNTR_RST_FRM_REG : 1; /*!< (@ 0x00000000) Time period counter soft reset */ + __IOM uint32_t + PWM_TIME_BASE_EN_FRM_REG_CH3 : 1; /*!< (@ 0x00000001) Base timer enable for channnel3 */ + __IOM uint32_t PWM_SFT_RST : 1; /*!< (@ 0x00000002) MC PWM soft reset */ + __IOM uint32_t RESERVED1 : 29; /*!< (@ 0x00000003) reserved1 */ + } PWM_TIME_PRD_CTRL_REG_CH3_b; + }; + + union { + __IM uint32_t + PWM_TIME_PRD_STS_REG_CH3; /*!< (@ 0x00000140) Base time period status register for channel3 */ + + struct { + __IM uint32_t + PWM_TIME_PRD_DIR_STS_CH3 : 1; /*!< (@ 0x00000000) Time period counter direction status for channel3. */ + __IM uint32_t RESERVED1 : 15; /*!< (@ 0x00000001) reserved1 */ + __IM uint32_t RESERVED2 : 16; /*!< (@ 0x00000010) reserved2 */ + } PWM_TIME_PRD_STS_REG_CH3_b; + }; + + union { + __IM uint32_t PWM_TIME_PRD_CNTR_VALUE_CH3; /*!< (@ 0x00000144) Time period counter current value register for + channel3 */ + + struct { + __IM uint32_t + PWM_TIME_PRD_CNTR_VALUE_CH3 : 16; /*!< (@ 0x00000000) Time period counter current value for channe3 */ + __IM uint32_t RESERVED1 : 16; /*!< (@ 0x00000010) reserved1 */ + } PWM_TIME_PRD_CNTR_VALUE_CH3_b; + }; + + union { + __IOM uint32_t + PWM_TIME_PRD_COMMON_REG; /*!< (@ 0x00000148) Time period common register */ + + struct { + __IOM uint32_t + PWM_TIME_PRD_USE_0TH_TIMER_ONLY : 1; /*!< (@ 0x00000000) Instead of use four base timers for four channels, + use only one base timer for all channels. */ + __IOM uint32_t + PWM_TIME_PRD_COMMON_TIMER_VALUE : 2; /*!< (@ 0x00000001) Base timers select to generate special event + trigger */ + __IOM uint32_t USE_EXT_TIMER_TRIG_FRM_REG : 1; /*!< (@ 0x00000003) Enable to use external trigger for base time + counter increment or decrement. */ + __IOM uint32_t RESERVED1 : 28; /*!< (@ 0x00000004) reserved1 */ + } PWM_TIME_PRD_COMMON_REG_b; + }; +} MCPWM_Type; /*!< Size = 332 (0x14c) */ + +/* ================================================================================ */ +/* ================ UDMA0 ================ */ +/* ================================================================================ */ + +/** + * @brief DMA Performs data transfers along with Addresses and control information (UDMA0) + */ +typedef struct { /*!< (@ 0x44030000) UDMA0 Structure */ + + union { + __IM uint32_t DMA_STATUS; /*!< (@ 0x00000000) UDMA Status Register */ + + struct { + __IM uint32_t MASTER_ENABLE : 1; /*!< (@ 0x00000000) Enable status of controller */ + __IM uint32_t RESERVED1 : 3; /*!< (@ 0x00000001) Reserved1 */ + __IM uint32_t STATE : 4; /*!< (@ 0x00000004) Current state of the control state machine */ + __IM uint32_t RESERVED2 : 8; /*!< (@ 0x00000008) Reserved2 */ + __IM uint32_t CHNLS_MINUS1 : 5; /*!< (@ 0x00000010) Number of available DMA channels minus one */ + __IM uint32_t RESERVED3 : 7; /*!< (@ 0x00000015) Reserved3 */ + __IM uint32_t TEST_STATUS : 4; /*!< (@ 0x0000001C) To reduce the gate count you can configure the + controller */ + } DMA_STATUS_b; + }; + + union { + __OM uint32_t DMA_CFG; /*!< (@ 0x00000004) DMA Configuration */ + + struct { + __OM uint32_t MASTER_ENABLE : 1; /*!< (@ 0x00000000) Enable for the controller */ + __OM uint32_t RESERVED1 : 4; /*!< (@ 0x00000001) Reserved1 */ + __OM uint32_t CHNL_PROT_CTRL : 3; /*!< (@ 0x00000005) Sets the AHB-Lite protection by controlling the + HPROT[3:1]] signal levels as follows Bit[7]-Controls + HPROT[3] to indicate if cacheable access + is occurring Bit[6]-Controls HPROT[2] to + indicate if cacheable access is occurring + Bit[5]-Controls HPROT[1] to indicate if + cacheable access is occurring */ + __OM uint32_t RESERVED2 : 24; /*!< (@ 0x00000008) Reserved2 */ + } DMA_CFG_b; + }; + + union { + __IOM uint32_t CTRL_BASE_PTR; /*!< (@ 0x00000008) Channel Control Data Base Pointer */ + + struct { + __OM uint32_t RESERVED1 : 10; /*!< (@ 0x00000000) Reserved1 */ + __IOM uint32_t CTRL_BASE_PTR : 22; /*!< (@ 0x0000000A) Pointer to the base address of the primary data + structure */ + } CTRL_BASE_PTR_b; + }; + + union { + __IM uint32_t ALT_CTRL_BASE_PTR; /*!< (@ 0x0000000C) Channel Alternate Control Data Base Pointer */ + + struct { + __IM uint32_t + ALT_CTRL_BASE_PTR : 32; /*!< (@ 0x00000000) Base address of the alternative data structure */ + } ALT_CTRL_BASE_PTR_b; + }; + + union { + __IM uint32_t + DMA_WAITONREQUEST_STATUS; /*!< (@ 0x00000010) Channel Wait on request status register */ + + struct { + __IM uint32_t + DMA_WAITONREQ_STATUS : 32; /*!< (@ 0x00000000) Per Channel wait on request status */ + } DMA_WAITONREQUEST_STATUS_b; + }; + + union { + __OM uint32_t CHNL_SW_REQUEST; /*!< (@ 0x00000014) Channel Software Request */ + + struct { + __OM uint32_t CHNL_SW_REQUEST : 32; /*!< (@ 0x00000000) Set the appropriate bit to generate a software + DMA request on the corresponding DMA channel */ + } CHNL_SW_REQUEST_b; + }; + + union { + __IOM uint32_t CHNL_USEBURST_SET; /*!< (@ 0x00000018) UDMA Channel use burst set */ + + struct { + __IOM uint32_t CHNL_USEBURST_SET : 32; /*!< (@ 0x00000000) The use burst status, or disables dma_sreq[C] + from generating DMA requests. */ + } CHNL_USEBURST_SET_b; + }; + + union { + __OM uint32_t CHNL_USEBURST_CLR; /*!< (@ 0x0000001C) UDMA Channel use burst clear */ + + struct { + __OM uint32_t CHNL_USEBURST_CLR : 32; /*!< (@ 0x00000000) Set the appropriate bit to enable dma_sreq[] + to generate requests */ + } CHNL_USEBURST_CLR_b; + }; + + union { + __IOM uint32_t CHNL_REQ_MASK_SET; /*!< (@ 0x00000020) UDMA Channel request mask set Register */ + + struct { + __IOM uint32_t CHNL_REQ_MASK_SET : 32; /*!< (@ 0x00000000) Returns the request mask status of dma_req[] + and dma_sreq[], or disables the corresponding + channel from generating DMA requests */ + } CHNL_REQ_MASK_SET_b; + }; + + union { + __OM uint32_t CHNL_REQ_MASK_CLR; /*!< (@ 0x00000024) UDMA Channel request mask clear */ + + struct { + __OM uint32_t CHNL_REQ_MASK_CLR : 32; /*!< (@ 0x00000000) Set the appropriate bit to enable DMA requests + for the channel corresponding to dma_req[] + and dma_sreq[] */ + } CHNL_REQ_MASK_CLR_b; + }; + + union { + __IOM uint32_t CHNL_ENABLE_SET; /*!< (@ 0x00000028) UDMA Channel enable register */ + + struct { + __IOM uint32_t CHNL_ENABLE_SET : 32; /*!< (@ 0x00000000) This Bits are Used to Load the 16bits of Source + address */ + } CHNL_ENABLE_SET_b; + }; + + union { + __OM uint32_t CHNL_ENABLE_CLR; /*!< (@ 0x0000002C) UDMA Channel enable clear register */ + + struct { + __OM uint32_t CHNL_ENABLE_CLR : 32; /*!< (@ 0x00000000) Set the appropriate bit to disable the corresponding + DMA channel */ + } CHNL_ENABLE_CLR_b; + }; + + union { + __IOM uint32_t CHNL_PRI_ALT_SET; /*!< (@ 0x00000030) UDMA Channel primary or alternate set */ + + struct { + __IOM uint32_t CHNL_PRI_ALT_SET : 32; /*!< (@ 0x00000000) Returns the channel control data structure status + or selects the alternate data structure + for the corresponding DMA channel */ + } CHNL_PRI_ALT_SET_b; + }; + + union { + __OM uint32_t CHNL_PRI_ALT_CLR; /*!< (@ 0x00000034) UDMA Channel primary alternate clear */ + + struct { + __OM uint32_t CHNL_PRI_ALT_CLR : 32; /*!< (@ 0x00000000) Set the appropriate bit to select the primary + data structure for the corresponding DMA + channel */ + } CHNL_PRI_ALT_CLR_b; + }; + + union { + __IOM uint32_t CHNL_PRIORITY_SET; /*!< (@ 0x00000038) UDMA Channel Priority Set */ + + struct { + __IOM uint32_t CHNL_PRIORITY_SET : 32; /*!< (@ 0x00000000) Set the appropriate bit to select the primary + data structure for the corresponding DMA + channel */ + } CHNL_PRIORITY_SET_b; + }; + + union { + __OM uint32_t CHNL_PRIORITY_CLR; /*!< (@ 0x0000003C) UDMA Channel Priority Clear */ + + struct { + __OM uint32_t CHNL_PRIORITY_CLR : 32; /*!< (@ 0x00000000) Set the appropriate bit to select the default + priority level for the specified DMA channel */ + } CHNL_PRIORITY_CLR_b; + }; + __IM uint32_t RESERVED[3]; + + union { + __IOM uint32_t ERR_CLR; /*!< (@ 0x0000004C) UDMA Bus Error Clear Register */ + + struct { + __IOM uint32_t ERR_CLR : 1; /*!< (@ 0x00000000) Returns the status of dma_err */ + __IOM uint32_t RESERVED1 : 31; /*!< (@ 0x00000001) Reserved1 */ + } ERR_CLR_b; + }; + + union { + __IOM uint32_t + UDMA_SKIP_DESC_FETCH_REG; /*!< (@ 0x00000050) UDMA skip descriptor fetch Register */ + + struct { + __IOM uint32_t SKIP_DESC_FETCH : 32; /*!< (@ 0x00000000) improving the performance of transfer and saves + bus cycles. This features has to be enabled + always. */ + } UDMA_SKIP_DESC_FETCH_REG_b; + }; + __IM uint32_t RESERVED1[491]; + + union { + __IOM uint32_t + UDMA_DONE_STATUS_REG; /*!< (@ 0x00000800) UDMA Done status Register */ + + struct { + __IOM uint32_t + DONE_STATUS_CHANNEL_0 : 1; /*!< (@ 0x00000000) UDMA done Status of the channel 0 */ + __IOM uint32_t + DONE_STATUS_CHANNEL_1 : 1; /*!< (@ 0x00000001) UDMA done Status of the channel 1 */ + __IOM uint32_t + DONE_STATUS_CHANNEL_2 : 1; /*!< (@ 0x00000002) UDMA done Status of the channel 2 */ + __IOM uint32_t + DONE_STATUS_CHANNEL_3 : 1; /*!< (@ 0x00000003) UDMA done Status of the channel 3 */ + __IOM uint32_t + DONE_STATUS_CHANNEL_4 : 1; /*!< (@ 0x00000004) UDMA done Status of the channel 4 */ + __IOM uint32_t + DONE_STATUS_CHANNEL_5 : 1; /*!< (@ 0x00000005) UDMA done Status of the channel 5 */ + __IOM uint32_t + DONE_STATUS_CHANNEL_6 : 1; /*!< (@ 0x00000006) UDMA done Status of the channel 6 */ + __IOM uint32_t + DONE_STATUS_CHANNEL_7 : 1; /*!< (@ 0x00000007) UDMA done Status of the channel 7 */ + __IOM uint32_t + DONE_STATUS_CHANNEL_8 : 1; /*!< (@ 0x00000008) UDMA done Status of the channel 8 */ + __IOM uint32_t + DONE_STATUS_CHANNEL_9 : 1; /*!< (@ 0x00000009) UDMA done Status of the channel 9 */ + __IOM uint32_t + DONE_STATUS_CHANNEL_10 : 1; /*!< (@ 0x0000000A) UDMA done Status of the channel 10 */ + __IOM uint32_t + DONE_STATUS_CHANNEL_11 : 1; /*!< (@ 0x0000000B) UDMA done Status of the channel 3 */ + __IOM uint32_t + DONE_STATUS_CHANNEL_12 : 1; /*!< (@ 0x0000000C) UDMA done Status of the channel 12 */ + __IOM uint32_t + DONE_STATUS_CHANNEL_13 : 1; /*!< (@ 0x0000000D) UDMA done Status of the channel 13 */ + __IOM uint32_t + DONE_STATUS_CHANNEL_14 : 1; /*!< (@ 0x0000000E) UDMA done Status of the channel 14 */ + __IOM uint32_t + DONE_STATUS_CHANNEL_15 : 1; /*!< (@ 0x0000000F) UDMA done Status of the channel 15 */ + __IOM uint32_t + DONE_STATUS_CHANNEL_16 : 1; /*!< (@ 0x00000010) UDMA done Status of the channel 16 */ + __IOM uint32_t + DONE_STATUS_CHANNEL_17 : 1; /*!< (@ 0x00000011) UDMA done Status of the channel 17 */ + __IOM uint32_t + DONE_STATUS_CHANNEL_18 : 1; /*!< (@ 0x00000012) UDMA done Status of the channel 18 */ + __IOM uint32_t + DONE_STATUS_CHANNEL_19 : 1; /*!< (@ 0x00000013) UDMA done Status of the channel 19 */ + __IOM uint32_t + DONE_STATUS_CHANNEL_20 : 1; /*!< (@ 0x00000014) UDMA done Status of the channel 3 */ + __IOM uint32_t + DONE_STATUS_CHANNEL_21 : 1; /*!< (@ 0x00000015) UDMA done Status of the channel 21 */ + __IOM uint32_t + DONE_STATUS_CHANNEL_22 : 1; /*!< (@ 0x00000016) UDMA done Status of the channel 22 */ + __IOM uint32_t + DONE_STATUS_CHANNEL_23 : 1; /*!< (@ 0x00000017) UDMA done Status of the channel 23 */ + __IOM uint32_t + DONE_STATUS_CHANNEL_24 : 1; /*!< (@ 0x00000018) UDMA done Status of the channel 24 */ + __IOM uint32_t + DONE_STATUS_CHANNEL_25 : 1; /*!< (@ 0x00000019) UDMA done Status of the channel 25 */ + __IOM uint32_t + DONE_STATUS_CHANNEL_26 : 1; /*!< (@ 0x0000001A) UDMA done Status of the channel 26 */ + __IOM uint32_t + DONE_STATUS_CHANNEL_27 : 1; /*!< (@ 0x0000001B) UDMA done Status of the channel 27 */ + __IOM uint32_t + DONE_STATUS_CHANNEL_28 : 1; /*!< (@ 0x0000001C) UDMA done Status of the channel 28 */ + __IOM uint32_t + DONE_STATUS_CHANNEL_29 : 1; /*!< (@ 0x0000001D) UDMA done Status of the channel 29 */ + __IOM uint32_t + DONE_STATUS_CHANNEL_30 : 1; /*!< (@ 0x0000001E) UDMA done Status of the channel 30 */ + __IOM uint32_t + DONE_STATUS_CHANNEL_31 : 1; /*!< (@ 0x0000001F) UDMA done Status of the channel 31 */ + } UDMA_DONE_STATUS_REG_b; + }; + + union { + __IM uint32_t CHANNEL_STATUS_REG; /*!< (@ 0x00000804) Channel status Register */ + + struct { + __IM uint32_t + BUSY_OR_IDEAL_STATUS_CHANNEL_0 : 1; /*!< (@ 0x00000000) Reading 1 indicates that the channel 0 is busy */ + __IM uint32_t + BUSY_OR_IDEAL_STATUS_CHANNEL_1 : 1; /*!< (@ 0x00000001) Reading 1 indicates that the channel 1 is busy */ + __IM uint32_t + BUSY_OR_IDEAL_STATUS_CHANNEL_2 : 1; /*!< (@ 0x00000002) Reading 1 indicates that the channel 2 is busy */ + __IM uint32_t + BUSY_OR_IDEAL_STATUS_CHANNEL_3 : 1; /*!< (@ 0x00000003) Reading 1 indicates that the channel 3 is busy */ + __IM uint32_t + BUSY_OR_IDEAL_STATUS_CHANNEL_4 : 1; /*!< (@ 0x00000004) Reading 1 indicates that the channel 4 is busy */ + __IM uint32_t + BUSY_OR_IDEAL_STATUS_CHANNEL_5 : 1; /*!< (@ 0x00000005) Reading 1 indicates that the channel 5 is busy */ + __IM uint32_t + BUSY_OR_IDEAL_STATUS_CHANNEL_6 : 1; /*!< (@ 0x00000006) Reading 1 indicates that the channel 6 is busy */ + __IM uint32_t + BUSY_OR_IDEAL_STATUS_CHANNEL_7 : 1; /*!< (@ 0x00000007) Reading 1 indicates that the channel 7 is busy */ + __IM uint32_t + BUSY_OR_IDEAL_STATUS_CHANNEL_8 : 1; /*!< (@ 0x00000008) Reading 1 indicates that the channel 8 is busy */ + __IM uint32_t + BUSY_OR_IDEAL_STATUS_CHANNEL_9 : 1; /*!< (@ 0x00000009) Reading 1 indicates that the channel 9 is busy */ + __IM uint32_t + BUSY_OR_IDEAL_STATUS_CHANNEL_10 : 1; /*!< (@ 0x0000000A) Reading 1 indicates that the channel 10 is busy */ + __IM uint32_t + BUSY_OR_IDEAL_STATUS_CHANNEL_11 : 1; /*!< (@ 0x0000000B) Reading 1 indicates that the channel 11 is busy */ + __IM uint32_t + BUSY_OR_IDEAL_STATUS_CHANNEL_12 : 1; /*!< (@ 0x0000000C) Reading 1 indicates that the channel 12 is busy */ + __IM uint32_t + BUSY_OR_IDEAL_STATUS_CHANNEL_13 : 1; /*!< (@ 0x0000000D) Reading 1 indicates that the channel 13 is busy */ + __IM uint32_t + BUSY_OR_IDEAL_STATUS_CHANNEL_14 : 1; /*!< (@ 0x0000000E) Reading 1 indicates that the channel 14 is busy */ + __IM uint32_t + BUSY_OR_IDEAL_STATUS_CHANNEL_15 : 1; /*!< (@ 0x0000000F) Reading 1 indicates that the channel 15 is busy */ + __IM uint32_t + BUSY_OR_IDEAL_STATUS_CHANNEL_16 : 1; /*!< (@ 0x00000010) Reading 1 indicates that the channel 16 is busy */ + __IM uint32_t + BUSY_OR_IDEAL_STATUS_CHANNEL_17 : 1; /*!< (@ 0x00000011) Reading 1 indicates that the channel 17 is busy */ + __IM uint32_t + BUSY_OR_IDEAL_STATUS_CHANNEL_18 : 1; /*!< (@ 0x00000012) Reading 1 indicates that the channel 18 is busy */ + __IM uint32_t + BUSY_OR_IDEAL_STATUS_CHANNEL_19 : 1; /*!< (@ 0x00000013) Reading 1 indicates that the channel 19 is busy */ + __IM uint32_t + BUSY_OR_IDEAL_STATUS_CHANNEL_20 : 1; /*!< (@ 0x00000014) Reading 1 indicates that the channel 20 is busy */ + __IM uint32_t + BUSY_OR_IDEAL_STATUS_CHANNEL_21 : 1; /*!< (@ 0x00000015) Reading 1 indicates that the channel 21 is busy */ + __IM uint32_t + BUSY_OR_IDEAL_STATUS_CHANNEL_22 : 1; /*!< (@ 0x00000016) Reading 1 indicates that the channel 22 is busy */ + __IM uint32_t + BUSY_OR_IDEAL_STATUS_CHANNEL_23 : 1; /*!< (@ 0x00000017) Reading 1 indicates that the channel 23 is busy */ + __IM uint32_t + BUSY_OR_IDEAL_STATUS_CHANNEL_24 : 1; /*!< (@ 0x00000018) Reading 1 indicates that the channel 24 is busy */ + __IM uint32_t + BUSY_OR_IDEAL_STATUS_CHANNEL_25 : 1; /*!< (@ 0x00000019) Reading 1 indicates that the channel 25 is busy */ + __IM uint32_t + BUSY_OR_IDEAL_STATUS_CHANNEL_26 : 1; /*!< (@ 0x0000001A) Reading 1 indicates that the channel 26 is busy */ + __IM uint32_t + BUSY_OR_IDEAL_STATUS_CHANNEL_27 : 1; /*!< (@ 0x0000001B) Reading 1 indicates that the channel 27 is busy */ + __IM uint32_t + BUSY_OR_IDEAL_STATUS_CHANNEL_28 : 1; /*!< (@ 0x0000001C) Reading 1 indicates that the channel 28 is busy */ + __IM uint32_t + BUSY_OR_IDEAL_STATUS_CHANNEL_29 : 1; /*!< (@ 0x0000001D) Reading 1 indicates that the channel 29 is busy */ + __IM uint32_t + BUSY_OR_IDEAL_STATUS_CHANNEL_30 : 1; /*!< (@ 0x0000001E) Reading 1 indicates that the channel 30 is busy */ + __IM uint32_t + BUSY_OR_IDEAL_STATUS_CHANNEL_31 : 1; /*!< (@ 0x0000001F) Reading 1 indicates that the channel 31 is busy */ + } CHANNEL_STATUS_REG_b; + }; + __IM uint32_t RESERVED2[8]; + + union { + __IOM uint32_t + UDMA_CONFIG_CTRL_REG; /*!< (@ 0x00000828) DMA Controller Transfer Length Register */ + + struct { + __IOM uint32_t + SINGLE_REQUEST_ENABLE : 1; /*!< (@ 0x00000000) Enabled signal for single request */ + __IOM uint32_t RESERVED1 : 31; /*!< (@ 0x00000001) Reserved for future use. */ + } UDMA_CONFIG_CTRL_REG_b; + }; + + union { + __IOM uint32_t UDMA_INTR_MASK_REG; /*!< DMA Controller Interrupt mask register */ + + struct { + __IOM uint32_t UDMA_INTR_MASK : 12; /*!< DMA Controller Interrupt mask */ + uint32_t : 20; + } UDMA_INTR_MASK_REG_b; /*!< BitSize */ + }; +} UDMA0_Type; /*!< Size = 2092 (0x82c) */ + +/* ================================================================================ */ +/* ================ HWRNG ================ */ +/* ================================================================================ */ + +/** + * @brief Random numbers generated are 16-bit random numbers and are generated using either the True random number generator or the Pseudo random number generator. (HWRNG) + */ + +typedef struct { /*!< HWRNG Structure */ + + union { + __IO uint32_t HWRNG_CTRL_REG; /*!< Random Number Generator Control Register */ + + struct { + __IO uint32_t HWRNG_RNG_ST : 1; /*!< This bit is used to start the true number generation. */ + __IO uint32_t HWRNG_PRBS_ST : 1; /*!< This bit is used to start the pseudo random number generation */ + __IO uint32_t SOFT_RESET : 1; + uint32_t : 29; + } HWRNG_CTRL_REG_b; /*!< BitSize */ + }; + + union { + __I uint32_t HWRNG_RAND_NUM_REG; /*!< Hardware Random Number Register */ + + struct { + __I uint32_t HWRNG_RAND_NUM : 32; /*!< Generated random number can be read from this register. */ + } HWRNG_RAND_NUM_REG_b; /*!< BitSize */ + }; +} HWRNG_Type; + +/* ================================================================================ */ +/* ================ TIMERS ================ */ +/* ================================================================================ */ + +/** + * @brief TIMER can be used to generate various timing events for the software (TIMERS) + */ + +typedef struct { /*!< (@ 0x24042000) TIMERS Structure */ + __IOM TIMERS_MATCH_CTRL_Type + MATCH_CTRL[4]; /*!< (@ 0x00000000) [0..3] */ + __IM uint32_t RESERVED[24]; + + union { + __IOM uint32_t + MCUULP_TMR_INTR_STAT; /*!< (@ 0x00000080) Timer Status Register */ + + struct { + __IOM uint32_t TMR0_INTR_STATUS : 1; /*!< (@ 0x00000000) This bit indicates status of the interrupt generated + by timer 0 */ + __IOM uint32_t TMR1_INTR_STATUS : 1; /*!< (@ 0x00000001) This bit indicates status of the interrupt generated + by timer 1 */ + __IOM uint32_t TMR2_INTR_STATUS : 1; /*!< (@ 0x00000002) This bit indicates status of the interrupt generated + by timer 2 */ + __IOM uint32_t TMR3_INTR_STATUS : 1; /*!< (@ 0x00000003) This bit indicates status of the interrupt generated + by timer 3 */ + __IM uint32_t RESERVED1 : 28; /*!< (@ 0x00000004) reserved1 */ + } MCUULP_TMR_INTR_STAT_b; + }; + + union { + __IOM uint32_t + MCUULP_TMR_US_PERIOD_INT; /*!< (@ 0x00000084) Timer micro second period Integral Part Register */ + + struct { + __IOM uint32_t TMR_US_PERIOD_INT : 16; /*!< (@ 0x00000000) This bits are used to program the integer part + of number of clock cycles per microseconds + of the system clock used */ + __IM uint32_t RESERVED1 : 16; /*!< (@ 0x00000010) reserved1 */ + } MCUULP_TMR_US_PERIOD_INT_b; + }; + + union { + __IOM uint32_t + MCUULP_TMR_US_PERIOD_FRAC; /*!< (@ 0x00000088) Timer microsecond period Fractional Part Register */ + + struct { + __IOM uint32_t TMR_US_PERIOD_FRAC : 8; /*!< (@ 0x00000000) This bits are used to program the fractional + part of number of clock cycles per microseconds + of the system clock used */ + __IM uint32_t RESERVED1 : 24; /*!< (@ 0x00000008) reserved1 */ + } MCUULP_TMR_US_PERIOD_FRAC_b; + }; + + union { + __IOM uint32_t + MCUULP_TMR_MS_PERIOD_INT; /*!< (@ 0x0000008C) Timer 256 microsecond period Integral Part Register */ + + struct { + __IOM uint32_t TMR_MS_PERIOD_INT : 16; /*!< (@ 0x00000000) This bits are used to program the integer part + of number of clock cycles per 256 microseconds + of the system clock used */ + __IM uint32_t RESERVED1 : 16; /*!< (@ 0x00000010) reserved1 */ + } MCUULP_TMR_MS_PERIOD_INT_b; + }; + + union { + __IOM uint32_t MCUULP_TMR_MS_PERIOD_FRAC; /*!< (@ 0x00000090) Timer 256 microsecond period Fractional Part + Register */ + + struct { + __IOM uint32_t TMR_MS_PERIOD_FRAC : 8; /*!< (@ 0x00000000) This bits are used to program the fractional + part of number of clock cycles per 256 + microseconds of the system clock used */ + __IM uint32_t RESERVED1 : 24; /*!< (@ 0x00000008) reserved1 */ + } MCUULP_TMR_MS_PERIOD_FRAC_b; + }; + __IM uint32_t RESERVED1[2]; + + union { + __IM uint32_t + MCUULP_TMR_ACTIVE_STATUS; /*!< (@ 0x0000009C) Timer Active Status Register */ + + struct { + __IM uint32_t TIMER_ACTIVE : 4; /*!< (@ 0x00000000) Timer active status for each timer. LSB bit specifies + the status for 0th timer and so on. */ + __IM uint32_t RESERVED1 : 28; /*!< (@ 0x00000004) reserved1 */ + } MCUULP_TMR_ACTIVE_STATUS_b; + }; +} TIMERS_Type; /*!< Size = 160 (0xa0) */ + +/* =========================================================================================================================== */ +/* ================ CAN ================ */ +/* =========================================================================================================================== */ + +/** + * @brief The DCAN is a standalone CAN (Controller Area Network) controller widely used in automotive and industrial applications. (CAN) + */ + +typedef struct { /*!< (@ 0x45070000) CAN Structure */ + + union { + __IOM uint8_t CAN_MR; /*!< (@ 0x00000000) Mode Register */ + + struct { + __IOM uint8_t AFM : 1; /*!< (@ 0x00000000) hardware acceptance filter scheme */ + __IOM uint8_t LOM : 1; /*!< (@ 0x00000001) Listen Only Mode */ + __IOM uint8_t RM : 1; /*!< (@ 0x00000002) Reset Mode */ + __IOM uint8_t RESERVED1 : 5; /*!< (@ 0x00000003) Reserved1 */ + } CAN_MR_b; + }; + + union { + __OM uint8_t CAN_CMR; /*!< (@ 0x00000001) Command Register */ + + struct { + __OM uint8_t RESERVED1 : 1; /*!< (@ 0x00000000) Reserved1 */ + __OM uint8_t AT : 1; /*!< (@ 0x00000001) Abort Transmission */ + __OM uint8_t TR : 1; /*!< (@ 0x00000002) Transmit Request */ + __IM uint8_t : 1; + __OM uint8_t RESERVED2 : 4; /*!< (@ 0x00000004) Reserved2 */ + } CAN_CMR_b; + }; + + union { + __IM uint8_t CAN_SR; /*!< (@ 0x00000002) Status register */ + + struct { + __IM uint8_t BS : 1; /*!< (@ 0x00000000) Bus Off Status */ + __IM uint8_t ES : 1; /*!< (@ 0x00000001) Error Status */ + __IM uint8_t TS : 1; /*!< (@ 0x00000002) Transmit Status */ + __IM uint8_t RS : 1; /*!< (@ 0x00000003) Receive Status */ + __IM uint8_t RESERVED1 : 1; /*!< (@ 0x00000004) Reserved1 */ + __IM uint8_t TBS : 1; /*!< (@ 0x00000005) Transmit Buffer Status */ + __IM uint8_t DSO : 1; /*!< (@ 0x00000006) Data Overrun Status */ + __IM uint8_t RBS : 1; /*!< (@ 0x00000007) Data Overrun Status */ + } CAN_SR_b; + }; + + union { + __IOM uint8_t CAN_ISR_IACK; /*!< (@ 0x00000003) Interrupt Status/Acknowledge Register */ + + struct { + __IOM uint8_t DOI : 1; /*!< (@ 0x00000000) Data Overrun Interrupt */ + __IOM uint8_t BEI : 1; /*!< (@ 0x00000001) Bus Error Interrupt */ + __IOM uint8_t TI : 1; /*!< (@ 0x00000002) Transmission Interrupt */ + __IOM uint8_t RI : 1; /*!< (@ 0x00000003) Receive Interrupt */ + __IOM uint8_t EPI : 1; /*!< (@ 0x00000004) Error Passive Interrupt */ + __IOM uint8_t EWI : 1; /*!< (@ 0x00000005) Error Warning Interrupt */ + __IOM uint8_t ALI : 1; /*!< (@ 0x00000006) Arbitration Lost Interrupt */ + __IOM uint8_t RESERVED1 : 1; /*!< (@ 0x00000007) Reserved1 */ + } CAN_ISR_IACK_b; + }; + + union { + __IOM uint8_t CAN_IMR; /*!< (@ 0x00000004) Interrupt Mask register.Setting appropriate bit + in IMR register enables interrupt assigned + to it, clearing disables this interrupt */ + + struct { + __IOM uint8_t DOIM : 1; /*!< (@ 0x00000000) mask for DOI interrupt */ + __IOM uint8_t BEIM : 1; /*!< (@ 0x00000001) mask for BEI interrupt */ + __IOM uint8_t TIM : 1; /*!< (@ 0x00000002) mask for TI interrupt */ + __IOM uint8_t RIM : 1; /*!< (@ 0x00000003) mask for RI interrupt */ + __IOM uint8_t EPIM : 1; /*!< (@ 0x00000004) mask for EPI interrupt */ + __IOM uint8_t EWIM : 1; /*!< (@ 0x00000005) mask for EWI interrupt */ + __IOM uint8_t ALIM : 1; /*!< (@ 0x00000006) mask for ALI interrupt */ + __IOM uint8_t RESERVED1 : 1; /*!< (@ 0x00000007) Reserved1 */ + } CAN_IMR_b; + }; + + union { + __IM uint8_t CAN_RMC; /*!< (@ 0x00000005) Receive Message Counter */ + + struct { + __IM uint8_t RMC : 5; /*!< (@ 0x00000000) number of stored message frames */ + __IM uint8_t RESERVED1 : 3; /*!< (@ 0x00000005) Reserved1 */ + } CAN_RMC_b; + }; + + union { + __IOM uint8_t CAN_BTIM0; /*!< (@ 0x00000006) BUS TIMING REGISTER 0 */ + + struct { + __IOM uint8_t BRP : 6; /*!< (@ 0x00000000) Baud Rate Pre scaler */ + __IOM uint8_t SJW : 2; /*!< (@ 0x00000006) Synchronization Jump Width */ + } CAN_BTIM0_b; + }; + + union { + __IOM uint8_t CAN_BTIM1; /*!< (@ 0x00000007) BUS TIMING REGISTER 1.define the length of bit + period, location of the sample point and + number of samples to be taken at each sample + point */ + + struct { + __IOM uint8_t TSEG1 : 4; /*!< (@ 0x00000000) Number of clock cycles per Time Segment 1 */ + __IOM uint8_t TSEG2 : 3; /*!< (@ 0x00000004) Number of clock cycles per Time Segment 1 */ + __IOM uint8_t SAM : 1; /*!< (@ 0x00000007) Number of bus level samples */ + } CAN_BTIM1_b; + }; + + union { + __OM uint32_t CAN_TXBUF; /*!< (@ 0x00000008) TRANSMIT BUFFER REGISTER */ + + struct { + __OM uint32_t TXBUF0 : 8; /*!< (@ 0x00000000) Transmit Buffer Register is used to write CAN + frame destined to send over CAN network. */ + __OM uint32_t TXBUF1 : 8; /*!< (@ 0x00000008) Transmit Buffer Register is used to write CAN + frame destined to send over CAN network. */ + __OM uint32_t TXBUF2 : 8; /*!< (@ 0x00000010) Transmit Buffer Register is used to write CAN + frame destined to send over CAN network. */ + __OM uint32_t TXBUF3 : 8; /*!< (@ 0x00000018) Transmit Buffer Register is used to write CAN + frame destined to send over CAN network. */ + } CAN_TXBUF_b; + }; + + union { + __IM uint32_t CAN_RXBUF; /*!< (@ 0x0000000C) RECEIVE BUFFER REGISTER */ + + struct { + __IM uint32_t RXBUF0 : 8; /*!< (@ 0x00000000) Receive Buffer Register is used to read CAN frames + received by the DCAN core from CAN network */ + __IM uint32_t RXBUF1 : 8; /*!< (@ 0x00000008) Receive Buffer Register is used to read CAN frames + received by the DCAN core from CAN network */ + __IM uint32_t RXBUF2 : 8; /*!< (@ 0x00000010) Receive Buffer Register is used to read CAN frames + received by the DCAN core from CAN network */ + __IM uint32_t RXBUF3 : 8; /*!< (@ 0x00000018) Receive Buffer Register is used to read CAN frames + received by the DCAN core from CAN network */ + } CAN_RXBUF_b; + }; + + union { + __IOM uint32_t CAN_ACR; /*!< (@ 0x00000010) ACCEPTANCE CODE REGISTER */ + + struct { + __IOM uint32_t ACR0 : 8; /*!< (@ 0x00000000) The acceptance code registers contains bit patterns + of messages to be received */ + __IOM uint32_t ACR1 : 8; /*!< (@ 0x00000008) The acceptance code registers contains bit patterns + of messages to be received */ + __IOM uint32_t ACR2 : 8; /*!< (@ 0x00000010) The acceptance code registers contains bit patterns + of messages to be received */ + __IOM uint32_t ACR3 : 8; /*!< (@ 0x00000018) The acceptance code registers contains bit patterns + of messages to be received */ + } CAN_ACR_b; + }; + + union { + __IOM uint32_t CAN_AMR; /*!< (@ 0x00000014) ACCEPTANCE MASK REGISTER */ + + struct { + __IOM uint32_t AMR0 : 8; /*!< (@ 0x00000000) Acceptance mask registers defines which bit positions + will be compared and which ones are do + not care. Setting certain AMR bit define + corresponding bit in ACR as do not care. */ + __IOM uint32_t AMR1 : 8; /*!< (@ 0x00000008) acceptance mask registers defines which bit positions + will be compared and which ones are do + not care. Setting certain AMR bit define + corresponding bit in ACR as do not care. */ + __IOM uint32_t AMR2 : 8; /*!< (@ 0x00000010) acceptance mask registers defines which bit positions + will be compared and which ones are do + not care. Setting certain AMR bit define + corresponding bit in ACR as do not care. */ + __IOM uint32_t AMR3 : 8; /*!< (@ 0x00000018) acceptance mask registers defines which bit positions + will be compared and which ones are do + not care. Setting certain AMR bit define + corresponding bit in ACR as do not care. */ + } CAN_AMR_b; + }; + + union { + __IM uint8_t CAN_ECC; /*!< (@ 0x00000018) ERROR CODE CAPTURE REGISTER */ + + struct { + __IM uint8_t BER : 1; /*!< (@ 0x00000000) Bit Error occurred */ + __IM uint8_t STFER : 1; /*!< (@ 0x00000001) stuff error occurred */ + __IM uint8_t CRCER : 1; /*!< (@ 0x00000002) CRC error occurred */ + __IM uint8_t FRMER : 1; /*!< (@ 0x00000003) Frame error occurred */ + __IM uint8_t ACKER : 1; /*!< (@ 0x00000004) Acknowledgement error occurred */ + __IM uint8_t EDIR : 1; /*!< (@ 0x00000005) direction of transfer while error occurred */ + __IM uint8_t TXWRN : 1; /*!< (@ 0x00000006) set when TXERR counter is greater than or equal + to 96 */ + __IM uint8_t RXWRN : 1; /*!< (@ 0x00000007) set when RXERR counter is greater than or equal + to 96 */ + } CAN_ECC_b; + }; + + union { + __IM uint8_t CAN_RXERR; /*!< (@ 0x00000019) RECEIVE ERROR COUNTER REGISTER */ + + struct { + __IM uint8_t RXERR : 8; /*!< (@ 0x00000000) The RXERR register reflects current value of + the receive error counter */ + } CAN_RXERR_b; + }; + + union { + __IM uint8_t CAN_TXERR; /*!< (@ 0x0000001A) RECEIVE ERROR COUNTER REGISTER */ + + struct { + __IM uint8_t TXERR : 8; /*!< (@ 0x00000000) The TXERR register reflects current value of + the transmit error counter */ + } TXERR_b; + }; + + union { + __IM uint8_t CAN_ALC; /*!< (@ 0x0000001B) ARBITRATION LOST CODE CAPTURE REGISTER */ + + struct { + __IM uint8_t ALC : 5; /*!< (@ 0x00000000) Arbitration Lost Capture */ + __IM uint8_t RESERVED1 : 3; /*!< (@ 0x00000005) Reserved1 */ + } CAN_ALC_b; + }; +} CAN_Type; /*!< Size = 28 (0x1c) */ + +/* ================================================================================ */ +/* ================ QEI ================ */ +/* ================================================================================ */ + +/** + * @brief The Motor Control PWM (MCPWM) controller is used to generate a periodic pulse waveform, which is useful in motor control and power control applications (QEI) + */ + +typedef struct { /*!< QEI Structure */ + + union { + __I uint32_t QEI_STATUS_REG; /*!< QEI Status Register */ + + struct { + __I uint32_t QEI_INDEX : 1; /*!< This is a direct value from the position signal generator */ + __I uint32_t QEI_POSITION_B : 1; /*!< This is a direct value from the position signal generator.Value + refers to the signal Position_B from the generator. */ + __I uint32_t QEI_POSITION_A : 1; /*!< This is a direct value from the position signal generator.Value + refers to the signal Position_A from the generator. */ + __I uint32_t POSITION_CNTR_ERR : 1; /*!< Count Error Status Flag bit */ + __I uint32_t + POSITION_CNTR_DIRECTION : 1; /*!< Position Counter Direction Status bit */ + } QEI_STATUS_REG_b; /*!< BitSize */ + }; + + union { + __IO uint32_t QEI_CTRL_REG_SET; /*!< QEI Control Set Register */ + + struct { + __I uint32_t QEI_SFT_RST : 1; /*!< Quadrature encoder soft reset. It is self reset signal. */ + __IO uint32_t QEI_SWAP_PHASE_AB : 1; /*!< Phase A and Phase B Input Swap Select bit */ + __IO uint32_t + POS_CNT_RST_WITH_INDEX_EN : 1; /*!< Phase A and Phase B Input Swap Select bit */ + uint32_t : 1; + __IO uint32_t + POS_CNT_DIRECTION_CTRL : 1; /*!< NONE */ + __IO uint32_t + POS_CNT_DIR_FRM_REG : 1; /*!< Position Counter Direction indication from user */ + uint32_t : 2; + __IO uint32_t INDEX_CNT_RST_EN : 1; /*!< NONE */ + __IO uint32_t + DIGITAL_FILTER_BYPASS : 1; /*!< NONE */ + __IO uint32_t TIMER_MODE : 1; /*!< NONE */ + __IO uint32_t + START_VELOCITY_CNTR : 1; /*!< Starting the velocity counter. It is self reset bit. */ + __IO uint32_t QEI_STOP_IN_IDLE : 1; /*!< NONE */ + __IO uint32_t + QEI_POS_CNT_16_BIT_MODE : 1; /*!< Qei position counter 16 bit mode enable */ + __IO uint32_t POS_CNT_RST : 1; /*!< 1=position counter is going to reset */ + __IO uint32_t INDEX_CNT_RST : 1; /*!< 1= index counter is going to reset. */ + } QEI_CTRL_REG_SET_b; /*!< BitSize */ + }; + + union { + __IO uint32_t QEI_CTRL_REG_RESET; /*!< PWM Interrupt mask Register */ + + struct { + __I uint32_t QEI_SFT_RST : 1; /*!< Quadrature encoder soft reset. It is self reset signal */ + __IO uint32_t QEI_SWAP_PHASE_AB : 1; /*!< Phase A and Phase B Input Swap Select bit */ + __IO uint32_t + POS_CNT_RST_WITH_INDEX_EN : 1; /*!< Phase A and Phase B Input Swap Select bit */ + uint32_t : 1; + __IO uint32_t + POS_CNT_DIRECTION_CTRL : 1; /*!< NONE */ + __IO uint32_t + POS_CNT_DIR_FRM_REG : 1; /*!< Position Counter Direction indication from user */ + uint32_t : 2; + __IO uint32_t INDEX_CNT_RST_EN : 1; /*!< NONE */ + __IO uint32_t + DIGITAL_FILTER_BYPASS : 1; /*!< NONE */ + __IO uint32_t TIMER_MODE : 1; /*!< NONE */ + __IO uint32_t + START_VELOCITY_CNTR : 1; /*!< Starting the velocity counter. It is self reset bit. */ + __IO uint32_t QEI_STOP_IN_IDLE : 1; /*!< NONE */ + __IO uint32_t + QEI_POS_CNT_16_BIT_MODE : 1; /*!< Qei position counter 16 bit mode enable */ + __IO uint32_t POS_CNT_RST : 1; /*!< 1=position counter is going to reset */ + __IO uint32_t INDEX_CNT_RST : 1; /*!< 1= index counter is going to reset. */ + } QEI_CTRL_REG_RESET_REg_b; /*!< BitSize */ + }; + + union { + __IO uint32_t QEI_CNTLR_INIT_REG; /*!< NONE */ + + struct { + __IO uint32_t QEI_ENCODING_MODE : 2; /*!< NONE */ + uint32_t : 2; + __IO uint32_t INDEX_MATCH_VALUE : 2; /*!< These bits allow user to specify the state of position A and + B during index pulse generation. */ + __IO uint32_t DF_CLK_DIVIDE_SLT : 4; /*!< Digital Filter Clock Divide Select bits */ + __IO uint32_t + UNIDIRECTIONAL_VELOCITY : 1; /*!< Uni directional velocity enable. */ + __IO uint32_t + UNIDIRECTIONAL_INDEX : 1; /*!< Uni directional index enable. */ + __IO uint32_t INDEX_CNT_INIT : 1; /*!< Index counter initial value in unidirectional index enable mode. */ + } QEI_CNTLR_INIT_REG_b; /*!< BitSize */ + }; + + union { + __IO uint32_t QEI_INDEX_CNT_REG; /*!< NONE */ + + struct { + __IO uint32_t QEI_INDEX_CNT : 16; /*!< Index counter value.User can initialize/change the index counter + using this register */ + } QEI_INDEX_CNT_REG_b; /*!< BitSize */ + }; + + union { + __IO uint32_t QEI_INDEX_MAX_CNT_REG; /*!< NONE */ + + struct { + __IO uint32_t + QEI_INDEX_MAX_CNT : 16; /*!< Qei index maximum count. */ + } QEI_INDEX_MAX_CNT_REG_b; /*!< BitSize */ + }; + + union { + __IO uint32_t QEI_POSITION_CNT_REG; /*!< NONE */ + + struct { + __IO uint32_t QEI_POSITION_CNT_WR_VALUE_L : 16; /*!< This is used to program/change the value of position counter + status[15:0] */ + __IO uint32_t QEI_POSITION_CNT_WR_VALUE_H : 16; /*!< This is used to program/change the value of position counter + status[31:16]. */ + } QEI_POSITION_CNT_REG_b; /*!< BitSize */ + }; + __I uint32_t RESERVED; + + union { + __IO uint32_t + QEI_POSITION_MAX_CNT_LSW_REG; /*!< NONE */ + + struct { + __IO uint32_t QEI_POSITION_MAX_CNT_L : 16; /*!< Qei position maximum count [15:0].This is a maximum count value + that is allowed to increment in the position counter */ + __IO uint32_t QEI_POSITION_MAX_CNT_H : 16; /*!< Qei position maximum count [31:16].This is a maximum count value + that is allowed to increment in the position counter */ + } QEI_POSITION_MAX_CNT_LSW_REG_b; /*!< BitSize */ + }; + __I uint32_t RESERVED1; + + union { + __I uint32_t QEI_INTR_STS_REG; /*!< NONE */ + + struct { + __IO uint32_t + QEI_POSITION_CNT_RESET_INTR_LEV : 1; /*!< This is raised when the position counter reaches it's extremes */ + __I uint32_t QEI_INDEX_CNT_MATCH_INTR_LEV : 1; /*!< This is raised when index counter reaches max value loaded in + to index_max_cnt register. */ + __I uint32_t POSITION_CNTR_ERR_INTR_LEV : 1; /*!< Whenever number of possible positions are mismatched with actual + positions are received between two index pulses this will raised */ + __I uint32_t + VELOCITY_LESS_THAN_INTR_LEV : 1; /*!< When velocity count is less than the value given in velocity_value_to_comp + are register, interrupt is raised */ + __I uint32_t + QEI_POSITION_CNT_MATCH_INTR_LEV : 1; /*!< This is raised when the position counter reaches position match + value, which is programmable. */ + } QEI_INTR_STS_REG_b; /*!< BitSize */ + }; + + union { + __IO uint32_t QEI_INTR_ACK_REG; /*!< NONE */ + + struct { + __IO uint32_t + QEI_POSITION_CNT_RESET_INTR_LEV : 1; /*!< Qei_position_cnt_reset_intr_ack */ + __IO uint32_t + QEI_INDEX_CNT_MATCH_INTR_LEV : 1; /*!< NONE */ + __IO uint32_t + POSITION_CNTR_ERR_INTR_LEV : 1; /*!< Position_cntr_err_intr_ack */ + __IO uint32_t + VELOCITY_LESS_THAN_INTR_LEV : 1; /*!< Velocity_less_than_intr_ack */ + __IO uint32_t + QEI_POSITION_CNT_MATCH_INTR_LEV : 1; /*!< Qei_position_cnt_match_intr_ack */ + } QEI_INTR_ACK_REG_b; /*!< BitSize */ + }; + + union { + __IO uint32_t QEI_INTR_MASK_REG; /*!< NONE */ + + struct { + __IO uint32_t + QEI_POSITION_CNT_RESET_INTR_MASK : 1; /*!< Qei_position_cnt_reset_intr_mask */ + __IO uint32_t + QEI_INDEX_CNT_MATCH_INTR_MASK : 1; /*!< Qei_index_cnt_match_intr_mask */ + __IO uint32_t + POSITION_CNTR_ERR_INTR_MASK : 1; /*!< Position_cntr_err_intr_mask */ + __IO uint32_t + VELOCITY_LESS_THAN_INTR_MASK : 1; /*!< Velocity_less_than_intr_mask */ + __IO uint32_t + QEI_POSITION_CNT_MATCH_INTR_MASK : 1; /*!< Qei_position_cnt_match_intr_mask */ + } QEI_INTR_MASK_REG_b; /*!< BitSize */ + }; + + union { + __IO uint32_t QEI_INTR_UNMASK_REg; /*!< NONE */ + + struct { + __IO uint32_t + QEI_POSITION_CNT_RESET_INTR_UNMASK : 1; /*!< Qei_position_cnt_reset_intr_unmask */ + __IO uint32_t + QEI_INDEX_CNT_MATCH_INTR_UNMASK : 1; /*!< Qei_index_cnt_match_intr_unmask */ + __IO uint32_t + POSITION_CNTR_ERR_INTR_UNMASK : 1; /*!< Position_cntr_err_intr_unmask */ + __IO uint32_t + VELOCITY_LESS_THAN_INTR_UNMASK : 1; /*!< Velocity_less_than_intr_unmask */ + __IO uint32_t + QEI_POSITION_CNT_MATCH_INTR_UNMASK : 1; /*!< Qei_position_cnt_match_intr_unmask */ + } QEI_INTR_UNMASK_REg_b; /*!< BitSize */ + }; + + union { + __IO uint32_t QEI_CLK_FREQ_REG; /*!< NONE */ + + struct { + __IO uint32_t QEI_CLK_FREQ : 9; /*!< Indication of clock frequency on which QEI controller is running. */ + } QEI_CLK_FREQ_REG_b; /*!< BitSize */ + }; + + union { + __IO uint32_t QEI_DELTA_TIME_REG; /*!< NONE */ + + struct { + __IO uint32_t + DELTA_TIME_FOR_VELOCITY : 20; /*!< Delta time LSW to compute velocity */ + } QEI_DELTA_TIME_REG_b; /*!< BitSize */ + }; + __I uint32_t RESERVED2; + + union { + __IO uint32_t QEI_VELOCITY_REG; /*!< NONE */ + + struct { + __I uint32_t VELOCITY_VALUE_TO_COMPARE_L : 16; /*!< If read :Velocity value to compare with velocity count LSW If + write :Velocity LSW count to compare using TA firmware */ + __O uint32_t VELOCITY_VALUE_TO_COMPARE_H : 16; /*!< If write :Velocity value to compare with velocity count MSW. + If read :Velocity MSW count to compare using TA firmware */ + } QEI_VELOCITY_REG_b; /*!< BitSize */ + }; + __I uint32_t RESERVED3; + + union { + __IO uint32_t QEI_POSITION_MATCH_REG; /*!< NONE */ + + struct { + __IO uint32_t + POSTION_MATCH_VALUE_L : 16; /*!< Position match value to compare the position counter. */ + __IO uint32_t + POSTION_MATCH_VALUE_H : 16; /*!< Position match value to compare the position counter. */ + } QEI_POSITION_MATCH_REG_b; /*!< BitSize */ + }; +} QEI_Type; + +/* ================================================================================ */ +/* ================ UART0 ================ */ +/* ================================================================================ */ + +/** + * @brief Universal Asynchronous Receiver/Transmitter is for serial communication with peripherals,modems and datasets (UART0) + */ + +typedef struct { /*!< UART0 Structure */ + + union { + union { + __IO uint32_t DLL; /*!< Divisor Latch Low */ + + struct { + __IO uint32_t DLL : 8; /*!< Lower 8-bits of a 16-bit, read/write, Divisor Latch register + that contains the baud ratedivisor for the UART */ + } DLL_b; /*!< BitSize */ + }; + + union { + __O uint32_t THR; /*!< Transmit Holding Register */ + + struct { + __O uint32_t THR : 8; /*!< Data to be transmitted on serial output port */ + } THR_b; /*!< BitSize */ + }; + + union { + __I uint32_t RBR; /*!< Receive Buffer Register */ + + struct { + __I uint32_t RBR : 8; /*!< Receive Buffer Field */ + } RBR_b; /*!< BitSize */ + }; + }; + + union { + union { + __IO uint32_t IER; /*!< Interrupt Enable Register */ + + struct { + __IO uint32_t ERBFI : 1; /*!< Enable Received Data Available Interrupt */ + __IO uint32_t ETBEI : 1; /*!< Enable Transmit Holding Register Empty Interrupt */ + __IO uint32_t ELSI : 1; /*!< Enable Receiver Line Status Interrupt */ + __IO uint32_t EDSSI : 1; /*!< Enable Modem Status Interrupt */ + uint32_t : 3; + __IO uint32_t PTIME : 1; /*!< Programmable THRE Interrupt Mode Enable */ + } IER_b; /*!< BitSize */ + }; + + union { + __IO uint32_t DLH; /*!< Divisor Latch High */ + + struct { + __IO uint32_t DLH : 8; /*!< Upper 8-bits of a 16-bit, read/write, Divisor Latch register + that contains the baud ratedivisor for the UART */ + } DLH_b; /*!< BitSize */ + }; + }; + + union { + union { + __O uint32_t FCR; /*!< FIFO Control Register */ + + struct { + __O uint32_t FIFOE : 1; /*!< This enables/disables the transmit (XMIT) and receive (RCVR) + FIFOs */ + __O uint32_t RFIFOR : 1; /*!< RCVR FIFO Reset */ + __O uint32_t XFIFOR : 1; /*!< XMIT FIFO Reset */ + __O uint32_t DMAM : 1; /*!< DMA signalling mode */ + __O uint32_t TET : 2; /*!< TX Empty Trigger */ + __O uint32_t RT : 2; /*!< This is used to select the trigger level in the receiver FIFO + at which the Received Data Available Interrupt is generated + */ + } FCR_b; /*!< BitSize */ + }; + + union { + __I uint32_t IIR; /*!< Interrupt Identity Register */ + + struct { + __I uint32_t IID : 4; /*!< Interrupt ID */ + uint32_t : 2; + __I uint32_t FIFOSE : 2; /*!< This is used to indicate whether the FIFOs are enabled or disabled. + */ + } IIR_b; /*!< BitSize */ + }; + }; + + union { + __IO uint32_t LCR; /*!< Line Control Register */ + + struct { + __IO uint32_t DLS : 2; /*!< Data Length Select,This is used to select the number of data + bits per character that the peripheral transmits and receives + */ + __IO uint32_t STOP : 1; /*!< This is used to select the number of stop bits per character + that the peripheral transmits and receives */ + __IO uint32_t PEN : 1; /*!< This bit is used to enable and disable parity generation and + detection in transmitted and received serial character */ + __IO uint32_t EPS : 1; /*!< This is used to select between even and odd parity */ + __IO uint32_t STICK_PARITY : 1; /*!< This bit is used to force parity value */ + __IO uint32_t BC : 1; /*!< This is used to cause a break condition to be transmitted to + the receiving device */ + __IO uint32_t DLAB : 1; /*!< This bit is used to enable reading and writing of the Divisor + Latch register to set the baud rate of the UART */ + } LCR_b; /*!< BitSize */ + }; + + union { + __IO uint32_t MCR; /*!< Modem Control Register */ + + struct { + __IO uint32_t DTR : 1; /*!< This is used to directly control the Data Terminal Ready (dtr_n) + output */ + __IO uint32_t RTS : 1; /*!< This is used to directly control the Request to Send (rts_n) + output */ + __IO uint32_t OUT1 : 1; /*!< This is used to directly control the user-designated Output1 + (out1_n) output */ + __IO uint32_t OUT2 : 1; /*!< This is used to directly control the user-designated Output2 + (out2_n) output */ + __IO uint32_t LB : 1; /*!< This is used to put the UART into a diagnostic mode for test + purposes */ + __IO uint32_t AFCE : 1; /*!< This is used to directly control the user-designated Output2 + (out2_n) output */ + __IO uint32_t SIRE : 1; /*!< This is used to enable/disable the IrDA SIR Mode features */ + } MCR_b; /*!< BitSize */ + }; + + union { + __I uint32_t LSR; /*!< Line Status Register */ + + struct { + __I uint32_t DR : 1; /*!< This is used to indicate that the receiver contains at least + one character in the RBR or the receiver FIFO */ + __I uint32_t OE : 1; /*!< This is used to indicate the occurrence of an overrun error */ + __I uint32_t PE : 1; /*!< This is used to indicate the occurrence of a parity error in + the receiver if the Parity Enable (PEN) bit (LCR[3]) is set + */ + __I uint32_t FE : 1; /*!< This is used to indicate the occurrence of a framing error in + the receiver */ + __I uint32_t BI : 1; /*!< his is used to indicate the detection of a break sequence on + the serial input data */ + __I uint32_t THRE : 1; /*!< Transmit Holding Register Empty bit */ + __I uint32_t TEMT : 1; /*!< Transmitter Empty bit */ + __I uint32_t RFE : 1; /*!< This is used to indicate if there is at least one parity error,framing + error, or break indication in the FIFO */ + } LSR_b; /*!< BitSize */ + }; + + union { + __I uint32_t MSR; /*!< Modem Status Register */ + + struct { + __I uint32_t DCTS : 1; /*!< This is used to indicate that the modem control line cts_n has + changed since the last time the MSR was read */ + __I uint32_t DDSR : 1; /*!< This is used to indicate that the modem control line dsr_n has + changed since the last time the MSR was read */ + __I uint32_t TERI : 1; /*!< This is used to indicate that a change on the input ri_n(from + an active-low to an inactive-high state) has occurred since + the last time the MSR was read */ + __I uint32_t DDCD : 1; /*!< This is used to indicate that the modem control line dcd_n has + changed since the last time the MSR was read */ + __I uint32_t CTS : 1; /*!< This is used to indicate the current state of the modem control + line cts_n */ + __I uint32_t DSR : 1; /*!< This is used to indicate the current state of the modem control + line dsr_n */ + __I uint32_t RI : 1; /*!< This is used to indicate the current state of the modem control + line ri_n */ + __I uint32_t DCD : 1; /*!< This is used to indicate the current state of the modem control + line dcd_n */ + } MSR_b; /*!< BitSize */ + }; + + union { + __IO uint32_t SCR; /*!< Scratch pad Register */ + + struct { + __IO uint32_t SCRATCH_PAD : 8; /*!< This register is for programmers to use as a temporary storage + space. It has no defined purpose */ + } SCR_b; /*!< BitSize */ + }; + + union { + __IO uint32_t LPDLL; /*!< Low Power Divisor Latch Low Register */ + + struct { + __IO uint32_t LOW_POWER_DLL : 8; /*!< This register makes up the lower 8-bits of a 16-bit, read/write, + Low Power Divisor Latch register that contains the baud rate + divisor for the UART, which must give a baud rate of 115.2K + */ + } LPDLL_b; /*!< BitSize */ + }; + + union { + __IO uint32_t LPDLH; /*!< Low Power Divisor Latch High Register */ + + struct { + __IO uint32_t LOW_POWER_DLH : 8; /*!< This register makes up the upper 8-bits of a 16-bit, read/write, + Low Power Divisor Latch register that contains the baud rate + divisor for the UART, which must give a baud rate of 115200 + */ + } LPDLH_b; /*!< BitSize */ + }; + __I uint32_t RESERVED[6]; + + union { + __IO uint32_t HDEN; /*!< none */ + + struct { + __IO uint32_t FULL_DUPLEX_MODE : 1; /*!< none */ + __IO uint32_t TX_MODE_RX_MODE : 1; /*!< This signal is valid when full_duplex_mode is disabled */ + } HDEN_b; /*!< BitSize */ + }; + __I uint32_t RESERVED1[5]; + + union { + __IO uint32_t SMCR; /*!< none */ + + struct { + __IO uint32_t SYNC_MODE : 1; /*!< none */ + __IO uint32_t MST_MODE : 1; /*!< none */ + uint32_t : 2; + __IO uint32_t CONTI_CLK_MODE : 1; /*!< none */ + __IO uint32_t START_STOP_EN : 1; /*!< none */ + } SMCR_b; /*!< BitSize */ + }; + __I uint32_t RESERVED2[5]; + + union { + __IO uint32_t FAR; /*!< none */ + + struct { + __IO uint32_t SYNC_MODE : 1; /*!< none */ + } FAR_b; /*!< BitSize */ + }; + + union { + __I uint32_t TFR; /*!< none */ + + struct { + __IO uint32_t TX_FIFO_RD : 8; /*!< Transmit FIFO Read */ + } TFR_b; /*!< BitSize */ + }; + + union { + __I uint32_t RFW; /*!< none */ + + struct { + __IO uint32_t RFWD : 8; /*!< Receive FIFO Write Data */ + __IO uint32_t RFPE : 1; /*!< Receive FIFO Parity Error */ + __IO uint32_t RFFE : 1; /*!< Receive FIFO Framing Error */ + } RFW_b; /*!< BitSize */ + }; + + union { + __I uint32_t USR; /*!< UART Status Register */ + + struct { + __I uint32_t BUSY : 1; /*!< Indicates that a serial transfer is in progress */ + __I uint32_t TFNF : 1; /*!< To Indicate that the transmit FIFO is not full */ + __I uint32_t TFE : 1; /*!< To Indicate that the transmit FIFO is completely empty */ + __I uint32_t RFNE : 1; /*!< To Indicate that the receive FIFO contains one or more entries */ + __I uint32_t RFE : 1; /*!< To Indicate that the receive FIFO is completely full */ + } USR_b; /*!< BitSize */ + }; + + union { + __I uint32_t TFL; /*!< Transmit FIFO Level */ + + struct { + __I uint32_t FIFO_ADDR_WIDTH : 30; /*!< Transmit FIFO Level. This is indicates the number of data entries + in the transmit FIFO. */ + } TFL_b; /*!< BitSize */ + }; + + union { + __I uint32_t RFL; /*!< Receive FIFO Level */ + + struct { + __I uint32_t FIFO_ADDR_WIDTH : 30; /*!< Receive FIFO Level. This is indicates the number of data entries + in the receive FIFO. */ + } RFL_b; /*!< BitSize */ + }; + + union { + __O uint32_t SRR; /*!< Software Reset Register */ + + struct { + __O uint32_t UR : 1; /*!< UART Reset */ + __O uint32_t RFR : 1; /*!< RCVR FIFO Reset */ + __O uint32_t XFR : 1; /*!< XMIT FIFO Reset */ + } SRR_b; /*!< BitSize */ + }; + + union { + __I uint32_t SRTS; /*!< Shadow Request to Send */ + + struct { + __I uint32_t SRTS : 1; /*!< Shadow Request to Send. */ + } SRTS_b; /*!< BitSize */ + }; + + union { + __I uint32_t SBCR; /*!< Shadow Break Control Register */ + + struct { + __I uint32_t SBCR : 1; /*!< Shadow Break Control Bit */ + } SBCR_b; /*!< BitSize */ + }; + + union { + __I uint32_t SDMAM; /*!< Shadow DMA Mode */ + + struct { + __I uint32_t SDMAM : 1; /*!< Shadow DMA Mode */ + } SDMAM_b; /*!< BitSize */ + }; + + union { + __I uint32_t SFE; /*!< Shadow FIFO Enable */ + + struct { + __I uint32_t SFE : 1; /*!< Shadow FIFO Enable */ + } SFE_b; /*!< BitSize */ + }; + + union { + __I uint32_t SRT; /*!< Shadow RCVR Trigger */ + + struct { + __I uint32_t SRT : 2; /*!< Shadow RCVR Trigger */ + } SRT_b; /*!< BitSize */ + }; + + union { + __I uint32_t STET; /*!< Shadow TX Empty Trigger */ + + struct { + __I uint32_t STET : 2; /*!< Shadow TX Empty Trigger */ + } STET_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HTX; /*!< Halt Transmit */ + + struct { + __IO uint32_t HALT_TX : 1; /*!< This register is use to halt transmissions for testing */ + } HTX_b; /*!< BitSize */ + }; + + union { + __IO uint32_t DMASA; /*!< DMA Software Acknowledge */ + + struct { + __O uint32_t DMA_SOFTWARE_ACK : 1; /*!< This register is use to perform a DMA software acknowledge if + a transfer needs to be terminated due to an error condition + */ + } DMASA_b; /*!< BitSize */ + }; + + union { + __IO uint32_t TCR; /*!< Transceiver Control Register */ + + struct { + __IO uint32_t RS485_EN : 1; /*!< RS485 Transfer Enable */ + __IO uint32_t RE_POL : 1; /*!< Receiver Enable Polarity */ + __IO uint32_t DE_POL : 1; /*!< Driver Enable Polarity */ + __IO uint32_t XFER_MODE : 2; /*!< Transfer Mode */ + } TCR_b; /*!< BitSize */ + }; + + union { + __IO uint32_t DE_EN; /*!< Driver Output Enable Register */ + + struct { + __IO uint32_t DE_EN : 1; /*!< DE Enable control */ + } DE_EN_b; /*!< BitSize */ + }; + + union { + __IO uint32_t RE_EN; /*!< Receiver Output Enable Register */ + + struct { + __IO uint32_t RE_EN : 1; /*!< RE Enable control */ + } RE_EN_b; /*!< BitSize */ + }; + + union { + __IO uint32_t DET; /*!< Driver Output Enable Timing Register */ + + struct { + __IO uint32_t DE_ASSERT_TIME : 8; /*!< Driver enable assertion time. */ + uint32_t : 8; + __IO uint32_t DE_DE_ASSERT_TIME : 8; /*!< Driver enable de-assertion time. */ + } DET_b; /*!< BitSize */ + }; + + union { + __IO uint32_t TAT; /*!< TurnAround Timing Register */ + + struct { + __IO uint32_t DE_RE : 16; /*!< Driver Enable to Receiver Enable TurnAround time. */ + __IO uint32_t RE_DE : 16; /*!< Receiver Enable to Driver Enable TurnAround time. */ + } TAT_b; /*!< BitSize */ + }; + + union { + __IO uint32_t DLF; /*!< Divisor Latch Fraction Register */ + + struct { + __IO uint32_t DLF : 6; /*!< Fractional part of divisor. */ + } DLF_b; /*!< BitSize */ + }; + + union { + __IO uint32_t RAR; /*!< Receive Address Register */ + + struct { + __IO uint32_t RAR : 8; /*!< This is an address matching register during receive mode */ + } RAR_b; /*!< BitSize */ + }; + + union { + __IO uint32_t TAR; /*!< Transmit Address Register */ + + struct { + __IO uint32_t TAR : 8; /*!< This is an address matching register during transmit mode */ + } TAR_b; /*!< BitSize */ + }; + + union { + __IO uint32_t LCR_EXT; /*!< Line Extended Control Register */ + + struct { + __IO uint32_t DLS_E : 1; /*!< Extension for DLS */ + __IO uint32_t ADDR_MATCH : 1; /*!< Address Match Mode */ + __IO uint32_t SEND_ADDR : 1; /*!< Send address control bit. */ + __IO uint32_t TRANSMIT_MODE : 1; /*!< Transmit mode control bit */ + } LCR_EXT_b; /*!< BitSize */ + }; + __I uint32_t RESERVED3[9]; + + union { + __I uint32_t CPR; /*!< Component Parameter Register */ + + struct { + __I uint32_t APB_DATA_WIDTH : 2; /*!< none */ + uint32_t : 2; + __I uint32_t AFCE_MODE : 1; /*!< none */ + __I uint32_t THRE_MODE : 1; /*!< none */ + __I uint32_t SIR_MODE : 1; /*!< none */ + __I uint32_t SIR_LP_MODE : 1; /*!< none */ + __I uint32_t ADDITIONAL_FEAT : 1; /*!< none */ + __I uint32_t FIFO_ACCESS : 1; /*!< none */ + __I uint32_t FIFO_STAT : 1; /*!< none */ + __I uint32_t SHADOW : 1; /*!< none */ + __I uint32_t + UART_ADD_ENCODED_PARAMS : 1; /*!< none */ + __I uint32_t DMA_EXTRA : 1; /*!< none */ + uint32_t : 2; + __I uint32_t FIFO_MODE : 8; /*!< none */ + } CPR_b; /*!< BitSize */ + }; + + union { + __I uint32_t UCV; /*!< UART Component Version */ + + struct { + __I uint32_t UART_COMP_VER : 32; /*!< ASCII value for each number in the version, followed by * */ + } UCV_b; /*!< BitSize */ + }; + + union { + __I uint32_t CTR; /*!< Component Type Register */ + + struct { + __I uint32_t UART_COMP_VER : 32; /*!< This register contains the peripherals identification code. */ + } CTR_b; /*!< BitSize */ + }; +} USART0_Type; + +/* =========================================================================================================================== */ +/* ================ GSPI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief GSPI, or Generic SPI, is a module which has been derived from QSPI. GSPI can act only as a master (GSPI0) + */ + +typedef struct { /*!< (@ 0x45030000) GSPI0 Structure */ + + union { + __IOM uint32_t GSPI_CLK_CONFIG; /*!< (@ 0x00000000) GSPI Clock Configuration Register */ + + struct { + __IOM uint32_t GSPI_CLK_SYNC : 1; /*!< (@ 0x00000000) If the clock frequency to FLASH (spi_clk) and + SOC clk is same. */ + __IOM uint32_t GSPI_CLK_EN : 1; /*!< (@ 0x00000001) GSPI clock enable */ + __IOM uint32_t RESERVED1 : 30; /*!< (@ 0x00000002) reserved for future use */ + } GSPI_CLK_CONFIG_b; + }; + + union { + __IOM uint32_t GSPI_BUS_MODE; /*!< (@ 0x00000004) GSPI Bus Mode Register */ + + struct { + __IOM uint32_t GSPI_DATA_SAMPLE_EDGE : 1; /*!< (@ 0x00000000) Samples MISO data on clock edges. This should + be ZERO for mode3 clock */ + __IOM uint32_t + GSPI_CLK_MODE_CSN0 : 1; /*!< (@ 0x00000001) NONE */ + __IOM uint32_t + GSPI_CLK_MODE_CSN1 : 1; /*!< (@ 0x00000002) NONE */ + __IOM uint32_t + GSPI_CLK_MODE_CSN2 : 1; /*!< (@ 0x00000003) NONE */ + __IOM uint32_t + GSPI_CLK_MODE_CSN3 : 1; /*!< (@ 0x00000004) NONE */ + __IOM uint32_t + GSPI_GPIO_MODE_ENABLES : 6; /*!< (@ 0x00000005) These bits are used to map GSPI on GPIO pins */ + __IOM uint32_t SPI_HIGH_PERFORMANCE_EN : 1; /*!< (@ 0x0000000B) High performance features are enabled when this + bit is set to one */ + __IOM uint32_t RESERVED1 : 20; /*!< (@ 0x0000000C) reserved for future use */ + } GSPI_BUS_MODE_b; + }; + __IM uint32_t RESERVED[2]; + + union { + __IOM uint32_t GSPI_CONFIG1; /*!< (@ 0x00000010) GSPI Configuration 1 Register */ + + struct { + __IOM uint32_t + GSPI_MANUAL_CSN : 1; /*!< (@ 0x00000000) SPI CS in manual mode */ + __IOM uint32_t + GSPI_MANUAL_WR : 1; /*!< (@ 0x00000001) Write enable for manual mode when CS is low. */ + __IOM uint32_t + GSPI_MANUAL_RD : 1; /*!< (@ 0x00000002) Read enable for manual mode when CS is low */ + __IOM uint32_t + GSPI_MANUAL_RD_CNT : 10; /*!< (@ 0x00000003) Indicates total number of bytes to be read */ + __IOM uint32_t GSPI_MANUAL_CSN_SELECT : 2; /*!< (@ 0x0000000D) Indicates which CSn is valid. Can be programmable + in manual mode */ + __IOM uint32_t + SPI_FULL_DUPLEX_EN : 1; /*!< (@ 0x0000000F) Full duplex mode enable */ + __IOM uint32_t RESERVED1 : 16; /*!< (@ 0x00000010) reserved for future use */ + } GSPI_CONFIG1_b; + }; + + union { + __IOM uint32_t GSPI_CONFIG2; /*!< (@ 0x00000014) GSPI Manual Configuration 2 Register */ + + struct { + __IOM uint32_t GSPI_WR_DATA_SWAP_MNL_CSN0 : 1; /*!< (@ 0x00000000) Swap the write data inside the GSPI controller + it-self. */ + __IOM uint32_t GSPI_WR_DATA_SWAP_MNL_CSN1 : 1; /*!< (@ 0x00000001) Swap the write data inside the GSPI controller + it-self. */ + __IOM uint32_t GSPI_WR_DATA_SWAP_MNL_CSN2 : 1; /*!< (@ 0x00000002) Swap the write data inside the GSPI controller + it-self. */ + __IOM uint32_t GSPI_WR_DATA_SWAP_MNL_CSN3 : 1; /*!< (@ 0x00000003) Swap the write data inside the GSPI controller + it-self. */ + __IOM uint32_t GSPI_RD_DATA_SWAP_MNL_CSN0 : 1; /*!< (@ 0x00000004) Swap the read data inside the GSPI controller + it-self. */ + __IOM uint32_t GSPI_RD_DATA_SWAP_MNL_CSN1 : 1; /*!< (@ 0x00000005) Swap the read data inside the GSPI controller + it-self. */ + __IOM uint32_t GSPI_RD_DATA_SWAP_MNL_CSN2 : 1; /*!< (@ 0x00000006) Swap the read data inside the GSPI controller + it-self. */ + __IOM uint32_t GSPI_RD_DATA_SWAP_MNL_CSN3 : 1; /*!< (@ 0x00000007) Swap the read data inside the GSPI controller + it-self. */ + __IOM uint32_t + GSPI_MANUAL_SIZE_FRM_REG : 1; /*!< (@ 0x00000008) Manual reads and manual writes */ + __IOM uint32_t RESERVED1 : 1; /*!< (@ 0x00000009) reserved for future use */ + __IOM uint32_t + TAKE_GSPI_MANUAL_WR_SIZE_FRM_REG : 1; /*!< (@ 0x0000000A) NONE */ + __IOM uint32_t + MANUAL_GSPI_MODE : 1; /*!< (@ 0x0000000B) Internally the priority is given to manual mode */ + __IOM uint32_t RESERVED2 : 20; /*!< (@ 0x0000000C) reserved for future use */ + } GSPI_CONFIG2_b; + }; + + union { + __IOM uint32_t GSPI_WRITE_DATA2; /*!< (@ 0x00000018) GSPI Write Data 2 Register */ + + struct { + __IOM uint32_t + GSPI_MANUAL_WRITE_DATA2 : 4; /*!< (@ 0x00000000) Number of bits to be written in write mode */ + __IOM uint32_t RESERVED1 : 3; /*!< (@ 0x00000004) reserved for future use */ + __IOM uint32_t + USE_PREV_LENGTH : 1; /*!< (@ 0x00000007) Use previous length */ + __IOM uint32_t RESERVED2 : 24; /*!< (@ 0x00000008) reserved for future use */ + } GSPI_WRITE_DATA2_b; + }; + + union { + __IOM uint32_t GSPI_FIFO_THRLD; /*!< (@ 0x0000001C) GSPI FIFO Threshold Register */ + + struct { + __IOM uint32_t + FIFO_AEMPTY_THRLD : 4; /*!< (@ 0x00000000) FIFO almost empty threshold */ + __IOM uint32_t + FIFO_AFULL_THRLD : 4; /*!< (@ 0x00000004) FIFO almost full threshold */ + __IOM uint32_t WFIFO_RESET : 1; /*!< (@ 0x00000008) Write FIFO reset */ + __IOM uint32_t RFIFO_RESET : 1; /*!< (@ 0x00000009) read FIFO reset */ + __IOM uint32_t RESERVED1 : 22; /*!< (@ 0x0000000A) reserved for future use */ + } GSPI_FIFO_THRLD_b; + }; + + union { + __IM uint32_t GSPI_STATUS; /*!< (@ 0x00000020) GSPI Status Register */ + + struct { + __IM uint32_t GSPI_BUSY : 1; /*!< (@ 0x00000000) State of Manual mode */ + __IM uint32_t + FIFO_FULL_WFIFO_S : 1; /*!< (@ 0x00000001) Full status indication for Wfifo in manual mode */ + __IM uint32_t FIFO_AFULL_WFIFO_S : 1; /*!< (@ 0x00000002) Almost full status indication for Wfifo in manual + mode */ + __IM uint32_t + FIFO_EMPTY_WFIFO : 1; /*!< (@ 0x00000003) Empty status indication for Wfifo in manual mode */ + __IM uint32_t RESERVED1 : 1; /*!< (@ 0x00000004) reserved for future use */ + __IM uint32_t + FIFO_FULL_RFIFO : 1; /*!< (@ 0x00000005) Full status indication for Rfifo in manual mode */ + __IM uint32_t RESERVED2 : 1; /*!< (@ 0x00000006) reserved for future use */ + __IM uint32_t + FIFO_EMPTY_RFIFO_S : 1; /*!< (@ 0x00000007) Empty status indication for Rfifo in manual mode */ + __IM uint32_t FIFO_AEMPTY_RFIFO_S : 1; /*!< (@ 0x00000008) Aempty status indication for Rfifo in manual + mode */ + __IM uint32_t + GSPI_MANUAL_RD_CNT : 1; /*!< (@ 0x00000009) This is a result of 10 bits ORing counter */ + __IM uint32_t + GSPI_MANUAL_CSN : 1; /*!< (@ 0x0000000A) Provide the status of chip select signal */ + __IM uint32_t RESERVED3 : 21; /*!< (@ 0x0000000B) reserved for future use */ + } GSPI_STATUS_b; + }; + + union { + __IOM uint32_t GSPI_INTR_MASK; /*!< (@ 0x00000024) GSPI Interrupt Mask Register */ + + struct { + __IOM uint32_t + GSPI_INTR_MASK : 1; /*!< (@ 0x00000000) GSPI Interrupt mask bit */ + __IOM uint32_t + FIFO_AEMPTY_RFIFO_MASK : 1; /*!< (@ 0x00000001) NONE */ + __IOM uint32_t + FIFO_AFULL_RFIFO_MASK : 1; /*!< (@ 0x00000002) NONE */ + __IOM uint32_t + FIFO_AEMPTY_WFIFO_MASK : 1; /*!< (@ 0x00000003) NONE */ + __IOM uint32_t + FIFO_AFULL_WFIFO_MASK : 1; /*!< (@ 0x00000004) NONE */ + __IOM uint32_t + FIFO_FULL_WFIFO_MASK : 1; /*!< (@ 0x00000005) NONE */ + __IOM uint32_t + FIFO_EMPTY_RFIFO_MASK : 1; /*!< (@ 0x00000006) NONE */ + __IOM uint32_t RESERVED1 : 25; /*!< (@ 0x00000007) reserved for future use */ + } GSPI_INTR_MASK_b; + }; + + union { + __IOM uint32_t GSPI_INTR_UNMASK; /*!< (@ 0x00000028) GSPI Interrupt Unmask Register */ + + struct { + __IOM uint32_t + GSPI_INTR_UNMASK : 1; /*!< (@ 0x00000000) GSPI Interrupt unmask bit */ + __IOM uint32_t + FIFO_AEMPTY_RFIFO_UNMASK : 1; /*!< (@ 0x00000001) NONE */ + __IOM uint32_t + FIFO_AFULL_RFIFO_UNMASK : 1; /*!< (@ 0x00000002) NONE */ + __IOM uint32_t + FIFO_AEMPTY_WFIFO_UNMASK : 1; /*!< (@ 0x00000003) NONE */ + __IOM uint32_t + FIFO_AFULL_WFIFO_UNMASK : 1; /*!< (@ 0x00000004) NONE */ + __IOM uint32_t + FIFO_FULL_WFIFO_UNMASK : 1; /*!< (@ 0x00000005) NONE */ + __IOM uint32_t + FIFO_EMPTY_RFIFO_UNMASK : 1; /*!< (@ 0x00000006) NONE */ + __IOM uint32_t RESERVED1 : 25; /*!< (@ 0x00000007) reserved for future use */ + } GSPI_INTR_UNMASK_b; + }; + + union { + __IM uint32_t GSPI_INTR_STS; /*!< (@ 0x0000002C) GSPI Interrupt Status Register */ + + struct { + __IM uint32_t GSPI_INTR_LVL : 1; /*!< (@ 0x00000000) GSPI Interrupt status bit */ + __IM uint32_t + FIFO_AEMPTY_RFIFO_LVL : 1; /*!< (@ 0x00000001) NONE */ + __IM uint32_t RESERVED1 : 2; /*!< (@ 0x00000002) reserved for future use */ + __IM uint32_t + FIFO_AFULL_WFIFO_LVL : 1; /*!< (@ 0x00000004) NONE */ + __IM uint32_t + FIFO_FULL_WFIFO_LVL : 1; /*!< (@ 0x00000005) NONE */ + __IM uint32_t + FIFO_EMPTY_RFIFO_LVL : 1; /*!< (@ 0x00000006) NONE */ + __IM uint32_t RESERVED2 : 25; /*!< (@ 0x00000007) reserved for future use */ + } GSPI_INTR_STS_b; + }; + + union { + __OM uint32_t GSPI_INTR_ACK; /*!< (@ 0x00000030) GSPI Interrupt Acknowledge Register */ + + struct { + __OM uint32_t GSPI_INTR_ACK : 1; /*!< (@ 0x00000000) GSPI Interrupt status bit */ + __OM uint32_t + FIFO_AEMPTY_RFIFO_ACK : 1; /*!< (@ 0x00000001) NONE */ + __OM uint32_t RESERVED1 : 2; /*!< (@ 0x00000002) reserved for future use */ + __OM uint32_t + FIFO_AFULL_WFIFO_ACK : 1; /*!< (@ 0x00000004) NONE */ + __OM uint32_t + FIFO_FULL_WFIFO_ACK : 1; /*!< (@ 0x00000005) NONE */ + __OM uint32_t + FIFO_EMPTY_RFIFO_ACK : 1; /*!< (@ 0x00000006) NONE */ + __OM uint32_t RESERVED2 : 25; /*!< (@ 0x00000007) reserved1 */ + } GSPI_INTR_ACK_b; + }; + + union { + __IM uint32_t GSPI_STS_MC; /*!< (@ 0x00000034) GSPI State Machine Monitor Register */ + + struct { + __IM uint32_t + BUS_CTRL_PSTATE : 3; /*!< (@ 0x00000000) Provides SPI bus controller present state */ + __IM uint32_t SPI_RD_CNT : 13; /*!< (@ 0x00000003) number of pending bytes to be read by device */ + __IM uint32_t RESERVED1 : 16; /*!< (@ 0x00000010) reserved1 */ + } GSPI_STS_MC_b; + }; + + union { + __IM uint32_t GSPI_CLK_DIV; /*!< (@ 0x00000038) GSPI Clock Division Factor Register */ + + struct { + __IOM uint32_t GSPI_CLK_DIV_FACTOR : 8; /*!< (@ 0x00000000) Provides GSPI clock division factor to the clock + divider, which takes SOC clock as input + clock and generates required clock according + to division factor */ + __IM uint32_t RESERVED1 : 24; /*!< (@ 0x00000008) reserved1 */ + } GSPI_CLK_DIV_b; + }; + + union { + __IOM uint32_t GSPI_CONFIG3; /*!< (@ 0x0000003C) GSPI Configuration 3 Register */ + + struct { + __IOM uint32_t SPI_MANUAL_RD_LNTH_TO_BC : 15; /*!< (@ 0x00000000) Bits are used to indicate the total number of + bytes to read from flash during read operation */ + __IOM uint32_t RESERVED1 : 17; /*!< (@ 0x0000000F) reserved1 */ + } GSPI_CONFIG3_b; + }; + __IM uint32_t RESERVED1[16]; + + union { + union { + __OM uint32_t + GSPI_WRITE_FIFO[16]; /*!< (@ 0x00000080) GSPI fifo */ + + struct { + __OM uint32_t WRITE_FIFO : 32; /*!< (@ 0x00000000) FIFO data is write to this address space */ + } GSPI_WRITE_FIFO_b[16]; + }; + + union { + __IM uint32_t + GSPI_READ_FIFO[16]; /*!< (@ 0x00000080) GSPI READ FIFO */ + + struct { + __IM uint32_t READ_FIFO : 32; /*!< (@ 0x00000000) FIFO data is read from this address space */ + } GSPI_READ_FIFO_b[16]; + }; + }; +} GSPI0_Type; /*!< Size = 192 (0xc0) */ + +/* ================================================================================ */ +/* ================ SSI0 ================ */ +/* ================================================================================ */ + +/** + * @brief Synchronous Serial Interface(SSI) (SSI0) + */ + +typedef struct { /*!< (@ 0x44020000) SSI0 Structure */ + + union { + __IOM uint32_t CTRLR0; /*!< (@ 0x00000000) Control Register 0 */ + + struct { + __IOM uint32_t DFS : 4; /*!< [3..0] Select the data frame length (4-bit to 16-bit serial + data transfers) */ + __IOM uint32_t FRF : 2; /*!< [5..4] Frame Format, Selects which serial protocol transfers + the data */ + __IOM uint32_t SCPH : 1; /*!< [6..6] Serial Clock Phase. Valid when the frame format (FRF) + is set to Motorola SPI */ + __IOM uint32_t SCPOL : 1; /*!< [7..7] Serial Clock Polarity. Valid when the frame format (FRF) + is set to Motorola SPI */ + __IOM uint32_t TMOD : 2; /*!< [9..8] Selects the mode of transfer for serial communication */ + __IOM uint32_t SLV_OE : 1; /*!< [10..10] DW_apb_ssi is configured as a serial-slave device */ + __IOM uint32_t SRL : 1; /*!< [11..11] Shift Register Loop Used for testing purposes only */ + __IOM uint32_t CFS : 4; /*!< [15..12] Control Frame Size Selects the length of the control + word for the Micro wire frame format */ + __IOM uint32_t DFS_32 : 5; /*!< [20..16] Selects the data frame length */ + __IOM uint32_t SPI_FRF : 2; /*!< [22..21] Selects data frame format for transmitting or receiving + data */ + __IOM uint32_t RESERVED1 : 9; /*!< [31..23] Reserved for future use */ + } CTRLR0_b; + }; + + union { + __IOM uint32_t CTRLR1; /*!< (@ 0x00000004) Control Register 1 */ + + struct { + __IOM uint32_t NDF : 16; /*!< [15..0] Number of Data Frames.When TMOD = 10 or TMOD = 11, this + register field sets the number of data frames to be continuously + received by the ssi_master */ + __IOM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use. */ + } CTRLR1_b; + }; + + union { + __IOM uint32_t SSIENR; /*!< (@ 0x00000008) SSI Enable Register */ + + struct { + __IOM uint32_t SSI_EN : 1; /*!< [0..0] Enables and disables all ssi operations */ + __IOM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + } SSIENR_b; + }; + + union { + __IOM uint32_t MWCR; /*!< (@ 0x0000000C) Micro wire Control Register */ + + struct { + __IOM uint32_t MWMOD : 1; /*!< [0..0] The Micro wire transfer is sequential or non-sequential */ + __IOM uint32_t MDD : 1; /*!< [1..1] The direction of the data word when the Micro wire serial + protocol is used */ + __IOM uint32_t MHS : 1; /*!< [2..2] Microwire Handshaking. Used to enable and disable the + busy/ready handshaking interface for the Microwire protocol */ + __IOM uint32_t RESERVED1 : 29; /*!< [31..3] Reserved for future use */ + } MWCR_b; + }; + + union { + __IOM uint32_t SER; /*!< (@ 0x00000010) SLAVE ENABLE REGISTER */ + + struct { + __IOM uint32_t SER : 4; /*!< [3..0] Each bit in this register corresponds to a slave select + line (ss_x_n) from the SSI master. */ + __IOM uint32_t RESERVED1 : 28; /*!< [31..4] Reserved for future use */ + } SER_b; + }; + + union { + __IOM uint32_t BAUDR; /*!< (@ 0x00000014) Baud Rate Select Register */ + + struct { + __IOM uint32_t SCKDV : 16; /*!< [15..0] SSI Clock Divider.The LSB for this field is always set + to 0 and is unaffected by a write operation, which ensures + an even value is held in this register */ + __IOM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } BAUDR_b; + }; + + union { + __IOM uint32_t TXFTLR; /*!< (@ 0x00000018) Transmit FIFO Threshold Level Register */ + + struct { + __IOM uint32_t TFT : 4; /*!< [3..0] Controls the level of entries (or below) at which the + transmit FIFO controller triggers an interrupt */ + __IOM uint32_t RESERVED1 : 28; /*!< [31..4] Reserved for future use */ + } TXFTLR_b; + }; + + union { + __IOM uint32_t RXFTLR; /*!< (@ 0x0000001C) Receive FIFO Threshold Level */ + + struct { + __IOM uint32_t RFT : 4; /*!< [3..0] Controls the level of entries (or above) at which the + receive FIFO controller triggers an interrupt */ + __IOM uint32_t RESERVED1 : 28; /*!< [31..4] Reserved for future use */ + } RXFTLR_b; + }; + + union { + __IM uint32_t TXFLR; /*!< (@ 0x00000020) Transmit FIFO Level Register */ + + struct { + __IM uint32_t TXTFL : 5; /*!< [4..0] Contains the number of valid data entries in the transmit + FIFO */ + __IM uint32_t RESERVED1 : 27; /*!< [31..5] Reserved for future use */ + } TXFLR_b; + }; + + union { + __IM uint32_t RXFLR; /*!< (@ 0x00000024) Receive FIFO Level Register */ + + struct { + __IM uint32_t RXTFL : 5; /*!< [4..0] Contains the number of valid data entries in the receive + FIFO */ + __IM uint32_t RESERVED1 : 27; /*!< [31..5] Reserved for future use */ + } RXFLR_b; + }; + + union { + __IM uint32_t SR; /*!< (@ 0x00000028) Status Register */ + + struct { + __IM uint32_t BUSY : 1; /*!< [0..0] indicates that a serial transfer is in progress */ + __IM uint32_t TFNF : 1; /*!< [1..1] Set when the transmit FIFO contains one or more empty + locations and is cleared when the FIFO is full */ + __IM uint32_t TFE : 1; /*!< [2..2] When the transmit FIFO is completely empty this bit is + set */ + __IM uint32_t RFNE : 1; /*!< [3..3] Set when the receive FIFO contains one or more entries + and is cleared when the receive FIFO is empty */ + __IM uint32_t RFF : 1; /*!< [4..4] When the receive FIFO is completely full this bit is + set */ + __IM uint32_t TXE : 1; /*!< [5..5] This bit is cleared when read */ + __IM uint32_t DCOL : 1; /*!< [6..6] This bit is set if the ss_in_n input is asserted by another + master, while the ssi master is in the middle of the transfer */ + __IM uint32_t RESERVED1 : 25; /*!< [31..7] Reserved for future use */ + } SR_b; + }; + + union { + __IOM uint32_t IMR; /*!< (@ 0x0000002C) Interrupt Mask Register */ + + struct { + __IOM uint32_t TXEIM : 1; /*!< [0..0] Transmit FIFO Empty Interrupt Mask */ + __IOM uint32_t TXOIM : 1; /*!< [1..1] Transmit FIFO Overflow Interrupt Mask */ + __IOM uint32_t RXUIM : 1; /*!< [2..2] Receive FIFO Underflow Interrupt Mask */ + __IOM uint32_t RXOIM : 1; /*!< [3..3] Receive FIFO Overflow Interrupt Mask */ + __IOM uint32_t RXFIM : 1; /*!< [4..4] Receive FIFO Full Interrupt Mask */ + __IOM uint32_t MSTIM : 1; /*!< [5..5] Multi-Master Contention Interrupt Mask */ + __IM uint32_t RESERVED1 : 26; /*!< [31..6] Reserved for future use */ + } IMR_b; + }; + + union { + __IM uint32_t ISR; /*!< (@ 0x00000030) Interrupt Status Register */ + + struct { + __IM uint32_t TXEIS : 1; /*!< [0..0] Transmit FIFO Empty Interrupt Status */ + __IM uint32_t TXOIS : 1; /*!< [1..1] Transmit FIFO Overflow Interrupt Status */ + __IM uint32_t RXUIS : 1; /*!< [2..2] Receive FIFO Underflow Interrupt Status */ + __IM uint32_t RXOIS : 1; /*!< [3..3] Receive FIFO Overflow Interrupt Status */ + __IM uint32_t RXFIS : 1; /*!< [4..4] Receive FIFO Full Interrupt Status */ + __IM uint32_t MSTIS : 1; /*!< [5..5] Multi-Master Contention Interrupt Status */ + __IM uint32_t RESERVED1 : 26; /*!< [31..6] Reserved for future use */ + } ISR_b; + }; + + union { + __IM uint32_t RISR; /*!< (@ 0x00000034) Raw Interrupt Status Register */ + + struct { + __IM uint32_t TXEIR : 1; /*!< [0..0] Transmit FIFO Empty Raw Interrupt Status */ + __IM uint32_t TXOIR : 1; /*!< [1..1] Transmit FIFO Overflow Raw Interrupt Status */ + __IM uint32_t RXUIR : 1; /*!< [2..2] Receive FIFO Underflow Raw Interrupt Status */ + __IM uint32_t RXOIR : 1; /*!< [3..3] Receive FIFO Overflow Raw Interrupt Status */ + __IM uint32_t RXFIR : 1; /*!< [4..4] Receive FIFO Full Raw Interrupt Status */ + __IM uint32_t MSTIR : 1; /*!< [5..5] Multi-Master Contention Raw Interrupt Status */ + __IM uint32_t RESERVED1 : 26; /*!< [31..6] Reserved for future use */ + } RISR_b; + }; + + union { + __IM uint32_t TXOICR; /*!< (@ 0x00000038) Transmit FIFO Overflow Interrupt Clear Register */ + + struct { + __IM uint32_t TXOICR : 1; /*!< [0..0] Clear Transmit FIFO Overflow Interrupt This register + reflects the status of the interrupt */ + __IM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + } TXOICR_b; + }; + + union { + __IM uint32_t RXOICR; /*!< (@ 0x0000003C) Receive FIFO Overflow Interrupt Clear Register */ + + struct { + __IM uint32_t RXOICR : 1; /*!< [0..0] This register reflects the status of the interrupt A + read from this register clears the ssi_rxo_intr interrupt */ + __IM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + } RXOICR_b; + }; + + union { + __IM uint32_t RXUICR; /*!< (@ 0x00000040) Receive FIFO Underflow Interrupt Clear Register */ + + struct { + __IM uint32_t RXUICR : 1; /*!< [0..0] This register reflects the status of the interrupt A + read from this register clears the ssi_rxu_intr interrupt */ + __IM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + } RXUICR_b; + }; + + union { + __IM uint32_t MSTICR; /*!< (@ 0x00000044) Multi-Master Interrupt Clear Register */ + + struct { + __IM uint32_t MSTICR : 1; /*!< [0..0] This register reflects the status of the interrupt A + read from this register clears the ssi_mst_intr interrupt */ + __IM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + } MSTICR_b; + }; + + union { + __IM uint32_t ICR; /*!< (@ 0x00000048) Interrupt Clear Register */ + + struct { + __IM uint32_t ICR : 1; /*!< [0..0] This register is set if any of the interrupts below are + active A read clears the ssi_txo_intr, ssi_rxu_intr, ssi_rxo_intr, + and the ssi_mst_intr interrupts */ + __IM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + } ICR_b; + }; + + union { + __IOM uint32_t DMACR; /*!< (@ 0x0000004C) DMA Control Register */ + + struct { + __IOM uint32_t RDMAE : 1; /*!< [0..0] This bit enables/disables the receive FIFO DMA channel */ + __IOM uint32_t TDMAE : 1; /*!< [1..1] This bit enables/disables the transmit FIFO DMA channel */ + __IM uint32_t RESERVED1 : 30; /*!< [31..2] Reserved for future use */ + } DMACR_b; + }; + + union { + __IOM uint32_t DMATDLR; /*!< (@ 0x00000050) DMA Transmit Data Level */ + + struct { + __IOM uint32_t DMATDL : 4; /*!< [3..0] This bit field controls the level at which a DMA request + is made by the transmit logic */ + __IM uint32_t RESERVED1 : 28; /*!< [31..4] Reserved for future use */ + } DMATDLR_b; + }; + + union { + __IOM uint32_t DMARDLR; /*!< (@ 0x00000054) DMA Receive Data Level Register */ + + struct { + __IOM uint32_t DMARDL : 4; /*!< [3..0] This bit field controls the level at which a DMA request + is made by the receive logic */ + __IOM uint32_t RESERVED1 : 28; /*!< [31..4] Reserved for future use */ + } DMARDLR_b; + }; + + union { + __IM uint32_t IDR; /*!< (@ 0x00000058) Identification Register */ + + struct { + __IM uint32_t IDCODE : 32; /*!< [31..0] This register contains the peripherals identification + code */ + } IDR_b; + }; + + union { + __IM uint32_t SSI_COMP_VERSION; /*!< (@ 0x0000005C) coreKit version ID register */ + + struct { + __IM uint32_t SSI_COMP_VERSION : 32; /*!< [31..0] Contains the hex representation of the Synopsys component + version */ + } SSI_COMP_VERSION_b; + }; + + union { + __IOM uint32_t DR; /*!< (@ 0x00000060) Data Register */ + + struct { + __IOM uint32_t DR : 32; /*!< [31..0] When writing to this register must right-justify the + data */ + } DR_b; + }; + __IM uint32_t RESERVED[35]; + + union { + __IOM uint32_t RX_SAMPLE_DLY; /*!< (@ 0x000000F0) Rx Sample Delay Register */ + + struct { + __IOM uint32_t RSD : 8; /*!< [7..0] Receive Data (rxd) Sample Delay. This register is used + to delay the sample of the rxd input signal. */ + __IOM uint32_t RESERVED1 : 24; /*!< [31..8] Reserved for future use */ + } RX_SAMPLE_DLY_b; + }; + + union { + __IOM uint32_t SPI_CTRLR0; /*!< (@ 0x000000F4) SPI control Register */ + + struct { + __IOM uint32_t TRANS_TYPE : 2; /*!< [1..0] Address and instruction transfer format */ + __IOM uint32_t ADDR_L : 4; /*!< [5..2] This bit defines length of address to be transmitted, + The transfer begins only after these many bits are programmed + into the FIFO */ + __IM uint32_t RESERVED1 : 2; /*!< [7..6] Reserved for future use */ + __IOM uint32_t INST_L : 2; /*!< [9..8] DUAL/QUAD length in bits */ + __IM uint32_t RESERVED2 : 1; /*!< [10..10] Reserved for future use */ + __IOM uint32_t WAIT_CYCLES : 4; /*!< [14..11] This bit defines the wait cycles in dual/quad mode + between control frames transmit and data reception, Specified + as number of SPI clock cycles */ + __IM uint32_t RESERVED3 : 17; /*!< [31..15] Reserved for future use */ + } SPI_CTRLR0_b; + }; +} SSI0_Type; /*!< Size = 248 (0xf8) */ + +/* =========================================================================================================================== */ +/* ================ SIO ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SERIAL GENERAL PERPOSE INPUT/OUTPUT (SIO) + */ + +typedef struct { /*!< (@ 0x47000000) SIO Structure */ + + union { + __IOM uint32_t SIO_ENABLE_REG; /*!< (@ 0x00000000) ENABLE REGISTER */ + + struct { + __IOM uint32_t + SIO_OPERATION_ENABLE : 16; /*!< [15..0] Contains the Enables for all SIO */ + __IM uint32_t RESERVED3 : 16; /*!< [31..16] Reserved for future use */ + } SIO_ENABLE_REG_b; + }; + + union { + __IOM uint32_t SIO_PAUSE_REG; /*!< (@ 0x00000004) PAUSE REGISTER */ + + struct { + __IOM uint32_t + SIO_POSITION_COUNTER_DISABLE : 16; /*!< [15..0] Contains sio position counter disable for all SIOs */ + __IM uint32_t RESERVED3 : 16; /*!< [31..16] Reserved for future use */ + } SIO_PAUSE_REG_b; + }; + + union { + __IM uint32_t SIO_GPIO_IN_REG; /*!< (@ 0x00000008) GPIO Input Register */ + + struct { + __IM uint32_t IN_VALUE : 32; /*!< [31..0] GPIO input pin status */ + } SIO_GPIO_IN_REG_b; + }; + + union { + __IOM uint32_t SIO_GPIO_OUT_REG; /*!< (@ 0x0000000C) GPIO Output Register */ + + struct { + __IOM uint32_t OUT_VALUE : 32; /*!< [31..0] Value to be loaded on GPIO out pins */ + } SIO_GPIO_OUT_REG_b; + }; + + union { + __IOM uint32_t SIO_GPIO_OEN_REG; /*!< (@ 0x00000010) GPIO Output enable Register */ + + struct { + __IOM uint32_t OEN_VALUE : 32; /*!< [31..0] OEN for the GPIO pins */ + } SIO_GPIO_OEN_REG_b; + }; + + union { + __IOM uint32_t + SIO_GPIO_INTR_EN_SET_REG; /*!< (@ 0x00000014) GPIO Interrupt Enable Set Register */ + + struct { + __OM uint32_t + INTR_ENABLE_SET : 16; /*!< [15..0] gpio interrupt enable set register for all SIOs */ + __IM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } SIO_GPIO_INTR_EN_SET_REG_b; + }; + + union { + __OM uint32_t + SIO_GPIO_INTR_EN_CLEAR_REG; /*!< (@ 0x00000018) GPIO Interrupt Enable Clear Register */ + + struct { + __OM uint32_t + INTR_ENABLE_CLEAR : 16; /*!< [15..0] gpio interrupt enable Clear register for all SIOs */ + __OM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } SIO_GPIO_INTR_EN_CLEAR_REG_b; + }; + + union { + __IOM uint32_t + SIO_GPIO_INTR_MASK_SET_REG; /*!< (@ 0x0000001C) GPIO Interrupt Enable Clear Register */ + + struct { + __IOM uint32_t + INTR_MASK_SET : 16; /*!< [15..0] Common gpio interrupt mask set register for all SIOs */ + __IM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } SIO_GPIO_INTR_MASK_SET_REG_b; + }; + + union { + __OM uint32_t + SIO_GPIO_INTR_MASK_CLEAR_REG; /*!< (@ 0x00000020) GPIO Interrupt Enable Clear Register */ + + struct { + __OM uint32_t + INTR_MASK_CLEAR : 16; /*!< [15..0] gpio interrupt mask clear register for all SIOs */ + __OM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } SIO_GPIO_INTR_MASK_CLEAR_REG_b; + }; + + union { + __IOM uint32_t + SIO_GPIO_INTR_STATUS_REG; /*!< (@ 0x00000024) GPIO Interrupt Status Register */ + + struct { + __OM uint32_t + INTR_MASK_SET : 16; /*!< [15..0] Common gpio interrupt status register for all SIOs */ + __IM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } SIO_GPIO_INTR_STATUS_REG_b; + }; + + union { + __IM uint32_t + SIO_SHIFT_COUNTER[16]; /*!< (@ 0x00000028) Shift counter register */ + + struct { + __IM uint32_t + SHIFT_COUNTER : 14; /*!< [13..0] shift counter current value */ + __IM uint32_t RESERVED1 : 18; /*!< [31..14] Reserved for future use */ + } SIO_SHIFT_COUNTER_b[16]; + }; + + union { + __IOM uint32_t SIO_BUFFER_REG[16]; /*!< (@ 0x00000068) Buffer Register */ + + struct { + __IOM uint32_t DATA : 32; /*!< [31..0] Data to load into the shift register */ + } SIO_BUFFER_REG_b[16]; + }; + + union { + __IOM uint32_t + SIO_SHIFT_COUNT_PRELOAD_REG[16]; /*!< (@ 0x000000A8) Shift counter Reload Register */ + + struct { + __IOM uint32_t + RELOAD_VALUE : 14; /*!< [13..0] division factor required to generate shift clock */ + __IM uint32_t RESERVED1 : 1; /*!< [14..14] Reserved for future use */ + __IOM uint32_t REVERSE_LOAD : 1; /*!< [15..15] When set, the data on APB is loaded to buffer is reverse + order */ + __IM uint32_t RESERVED2 : 16; /*!< [31..16] Reserved for future use */ + } SIO_SHIFT_COUNT_PRELOAD_REG_b[16]; + }; + + union { + __IOM uint32_t + SIO_DATA_POS_COUNT_REG[16]; /*!< (@ 0x000000E8) Data Position Counter Register */ + + struct { + __IOM uint32_t RELOAD_VALUE : 8; /*!< [7..0] No. of shifts to happen before reloading the shift register + with data/ pausing the operation */ + __IOM uint32_t + POSITION_COUNTER : 8; /*!< [15..8] The position counter can be loaded via AHB */ + __IM uint32_t RESERVED3 : 16; /*!< [31..16] Reserved for future use */ + } SIO_DATA_POS_COUNT_REG_b[16]; + }; + + union { + __IOM uint32_t SIO_CONFIG_REG[16]; /*!< (@ 0x00000128) Configuration Register */ + + struct { + __IOM uint32_t FULL_ENABLE : 1; /*!< [0..0] When set, fifo full indication would be asserted when + internal buffer is full */ + __IOM uint32_t EMPTY_ENABLE : 1; /*!< [1..1] When set, fifo full indication would be asserted when + internal buffer is empty */ + __IOM uint32_t EDGE_SEL : 1; /*!< [2..2] edge selection */ + __IOM uint32_t CLK_SEL : 1; /*!< [3..3] clock selection */ + __IOM uint32_t + IGNORE_FIRST_SHIFT_CONDITION : 1; /*!< [4..4] data shift condition */ + __IOM uint32_t + FLOW_CONTROL_ENABLED : 1; /*!< [5..5] flow control */ + __IOM uint32_t + PATTERN_MATCH_ENABLE : 1; /*!< [6..6] pattern match */ + __IOM uint32_t + QUALIFIER_MODE : 1; /*!< [7..7] qualifier mode */ + __IOM uint32_t + QUALIFY_CLOCK : 1; /*!< [8..8] qualify clock */ + __IOM uint32_t INVERT_CLOCK : 1; /*!< [9..9] invert clock */ + __IOM uint32_t + PARALLEL_MODE : 2; /*!< [11..10] No. of bits to shift/capture at valid clk edge */ + __IOM uint32_t + PIN_DETECTION_MODE : 2; /*!< [13..12] Pin mode to be considered for gpio interrupt */ + __IOM uint32_t SET_CLK_OUT : 1; /*!< [14..14] When high sets the sio clock_out port. This is used + only when sio is not enabled */ + __IOM uint32_t RESET_CLK_OUT : 1; /*!< [15..15] When high resets the sio clock_out port. This is used + only when sio is not enabled */ + __IOM uint32_t + LOAD_DATA_POS_CNTR_VIA_APB : 1; /*!< [16..16] When set, data position counter can be loaded via APB */ + __IM uint32_t RESERVED1 : 15; /*!< [31..17] Reserved for future use */ + } SIO_CONFIG_REG_b[16]; + }; + + union { + __IOM uint32_t + PATTERN_MATCH_MASK_REG_SLICE_0; /*!< (@ 0x00000168) Pattern Match Mask Register 0 */ + + struct { + __IOM uint32_t + MATCH_MASK_LOWER16_BITS : 32; /*!< [31..0] Enable for lower 16 bits */ + } PATTERN_MATCH_MASK_REG_SLICE_0_b; + }; + + union { + __IOM uint32_t + PATTERN_MATCH_MASK_REG_slice_1; /*!< (@ 0x0000016C) Pattern Match Mask Register Slice 1 */ + + struct { + __IOM uint32_t + MATCH_MASK_LOWER16_BITS : 32; /*!< [31..0] Enable for lower 16 bits */ + } PATTERN_MATCH_MASK_REG_slice_1_b; + }; + + union { + __IOM uint32_t + PATTERN_MATCH_MASK_REG_SLICE_2; /*!< (@ 0x00000170) Pattern Match Mask Register Slice 2 */ + + struct { + __IOM uint32_t + MATCH_MASK_LOWER16_BITS : 32; /*!< [31..0] Enable for lower 16 bits */ + } PATTERN_MATCH_MASK_REG_SLICE_2_b; + }; + __IM uint32_t RESERVED[5]; + + union { + __IOM uint32_t + SIO_PATTERN_MATCH_MASK_REG_SLICE_8; /*!< (@ 0x00000188) Pattern Match Mask Register Slice 8 */ + + struct { + __IOM uint32_t + MATCH_MASK_LOWER16_BITS : 32; /*!< [31..0] Enable for lower 16 bits */ + } SIO_PATTERN_MATCH_MASK_REG_SLICE_8_b; + }; + + union { + __IOM uint32_t + SIO_PATTERN_MATCH_MASK_REG_SLICE_9; /*!< (@ 0x0000018C) Pattern Match Mask Register Slice 9 */ + + struct { + __IOM uint32_t + MATCH_MASK_LOWER16_BITS : 32; /*!< [31..0] Enable for lower 16 bits */ + } SIO_PATTERN_MATCH_MASK_REG_SLICE_9_b; + }; + + union { + __IOM uint32_t + SIO_PATTERN_MATCH_MASK_REG_SLICE_10; /*!< (@ 0x00000190) Pattern Match Mask Register Slice 10 */ + + struct { + __IOM uint32_t + MATCH_MASK_LOWER16_BITS : 32; /*!< [31..0] Enable for lower 16 bits */ + } SIO_PATTERN_MATCH_MASK_REG_SLICE_10_b; + }; + __IM uint32_t RESERVED1[5]; + + union { + __IOM uint32_t + SIO_PATTERN_MATCH_REG_SLICE_0; /*!< (@ 0x000001A8) Pattern Match Mask Register Slice 0 */ + + struct { + __IOM uint32_t + PATTERN_MATCH_LOWER16_BITS : 32; /*!< [31..0] Lower 16-bits of pattern to be detected */ + } SIO_PATTERN_MATCH_REG_SLICE_0_b; + }; + + union { + __IOM uint32_t + SIO_PATTERN_MATCH_REG_SLICE_1; /*!< (@ 0x000001AC) Pattern Match Mask Register Slice 1 */ + + struct { + __IOM uint32_t + PATTERN_MATCH_LOWER16_BITS : 32; /*!< [31..0] Lower 16-bits of pattern to be detected */ + } SIO_PATTERN_MATCH_REG_SLICE_1_b; + }; + + union { + __IOM uint32_t + SIO_PATTERN_MATCH_REG_SLICE_2; /*!< (@ 0x000001B0) Pattern Match Mask Register Slice 2 */ + + struct { + __IOM uint32_t + PATTERN_MATCH_LOWER16_BITS : 32; /*!< [31..0] Lower 16-bits of pattern to be detected */ + } SIO_PATTERN_MATCH_REG_SLICE_2_b; + }; + __IM uint32_t RESERVED2[5]; + + union { + __IOM uint32_t + SIO_PATTERN_MATCH_REG_SLICE_8; /*!< (@ 0x000001C8) Pattern Match Mask Register Slice 8 */ + + struct { + __IOM uint32_t + PATTERN_MATCH_LOWER16_BITS : 32; /*!< [31..0] Lower 16 bits of pattern to be detected */ + } SIO_PATTERN_MATCH_REG_SLICE_8_b; + }; + + union { + __IOM uint32_t + SIO_PATTERN_MATCH_REG_SLICE_9; /*!< (@ 0x000001CC) Pattern Match Mask Register Slice 9 */ + + struct { + __IOM uint32_t + PATTERN_MATCH_LOWER16_BITS : 32; /*!< [31..0] Lower 16 bits of pattern to be detected */ + } SIO_PATTERN_MATCH_REG_SLICE_9_b; + }; + + union { + __IOM uint32_t + SIO_PATTERN_MATCH_REG_SLICE_10; /*!< (@ 0x000001D0) Pattern Match Mask Register Slice 10 */ + + struct { + __IOM uint32_t + PATTERN_MATCH_LOWER16_BITS : 32; /*!< [31..0] Lower 16 bits of pattern to be detected */ + } SIO_PATTERN_MATCH_REG_SLICE_10_b; + }; + __IM uint32_t RESERVED3[7]; + + union { + __IOM uint32_t + SIO_SHIFT_INTR_EN_SET_REG; /*!< (@ 0x000001F0) Shift Interrupt Enable Set Register */ + + struct { + __IOM uint32_t + INTR_ENABLE_SET : 16; /*!< [15..0] Common shift interrupt enable set register for all SIOs */ + __IM uint32_t RESERVED3 : 16; /*!< [31..16] Reserved for future use */ + } SIO_SHIFT_INTR_EN_SET_REG_b; + }; + + union { + __OM uint32_t + SIO_SHIFT_INTR_EN_CLEAR_REG; /*!< (@ 0x000001F4) Shift Interrupt Enable Clear Register */ + + struct { + __OM uint32_t INRT_ENABLE_CLEAR : 16; /*!< [15..0] Common shift interrupt enable Clear register for all + SIOs */ + __OM uint32_t RESERVED3 : 16; /*!< [31..16] Reserved for future use */ + } SIO_SHIFT_INTR_EN_CLEAR_REG_b; + }; + + union { + __IOM uint32_t + SIO_SHIFT_INTR_MASK_SET_REG; /*!< (@ 0x000001F8) Shift Interrupt Mask Set Register */ + + struct { + __IOM uint32_t + INTR_MASK_SET : 16; /*!< [15..0] Common shift interrupt enable Set register for all SIOs */ + __IM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } SIO_SHIFT_INTR_MASK_SET_REG_b; + }; + + union { + __OM uint32_t + SIO_SHIFT_INTR_MASK_CLEAR_REG; /*!< (@ 0x000001FC) Shift Interrupt Mask Clear Register */ + + struct { + __OM uint32_t + INTR_MASK_CLEAR : 16; /*!< [15..0] Common shift interrupt mask clear register for all SIOs */ + __OM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } SIO_SHIFT_INTR_MASK_CLEAR_REG_b; + }; + + union { + __IOM uint32_t + SIO_SHIFT_INTR_STATUS_REG; /*!< (@ 0x00000200) Shift Interrupt Status Register */ + + struct { + __IOM uint32_t + INTR_ENABLE_SET : 16; /*!< [15..0] Common shift interrupt mask clear register for all SIOs */ + __IM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } SIO_SHIFT_INTR_STATUS_REG_b; + }; + + union { + __IOM uint32_t + SIO_SWAP_INTR_EN_SET_REG; /*!< (@ 0x00000204) Swap Interrupt Enable Set Register */ + + struct { + __IOM uint32_t + INTR_ENABLE_SET : 16; /*!< [15..0] Swap interrupt enable set register for all SIOs */ + __IM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } SIO_SWAP_INTR_EN_SET_REG_b; + }; + + union { + __OM uint32_t + SIO_SWAP_INTR_EN_CLEAR_REG; /*!< (@ 0x00000208) Swap Interrupt Enable Clear Register */ + + struct { + __OM uint32_t + INTR_ENABLE_CLEAR : 16; /*!< [15..0] Swap interrupt enable Clear register for all SIOs */ + __OM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } SIO_SWAP_INTR_EN_CLEAR_REG_b; + }; + + union { + __IOM uint32_t + SIO_SWAP_INTR_MASK_SET_REG; /*!< (@ 0x0000020C) Swap Interrupt Mask Set Register */ + + struct { + __IOM uint32_t + INTR_MASK_SET : 16; /*!< [15..0] Common swap interrupt mask set register for all SIOs */ + __IM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } SIO_SWAP_INTR_MASK_SET_REG_b; + }; + + union { + __OM uint32_t + SIO_SWAP_INTR_MASK_CLEAR_REG; /*!< (@ 0x00000210) Swap Interrupt Mask Clear Register */ + + struct { + __OM uint32_t + INTR_MASK_CLEAR : 16; /*!< [15..0] Common swap interrupt mask Clear register for all SIOs */ + __OM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } SIO_SWAP_INTR_MASK_CLEAR_REG_b; + }; + + union { + __IOM uint32_t + SIO_SWAP_INTR_STATUS_REG; /*!< (@ 0x00000214) Swap Interrupt Statusr Register */ + + struct { + __IOM uint32_t + INTR_ENABLE_SET : 16; /*!< [15..0] Common swap interrupt status register for all SIOs */ + __IM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } SIO_SWAP_INTR_STATUS_REG_b; + }; + + union { + __IOM uint32_t + SIO_PATTERN_MATCH_INTR_EN_SET_REG; /*!< (@ 0x00000218) Pattern Match Interrupt Enable Set Register */ + + struct { + __IOM uint32_t INTR_ENABLE_SET : 16; /*!< [15..0] Common pattern or buffer under run interrupt enable + set register for all SIOs. Each bit corresponds to one + SIO */ + __IM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } SIO_PATTERN_MATCH_INTR_EN_SET_REG_b; + }; + + union { + __OM uint32_t + SIO_PATTERN_MATCH_INTR_EN_CLEAR_REG; /*!< (@ 0x0000021C) Pattern Match Interrupt Enable Clear Register */ + + struct { + __OM uint32_t INRT_ENABLE_CLEAR : 16; /*!< [15..0] Common pattern or buffer under run interrupt enable + clear register for all SIOs */ + __OM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } SIO_PATTERN_MATCH_INTR_EN_CLEAR_REG_b; + }; + + union { + __IOM uint32_t + SIO_PATTERN_MATCH_INTR_MASK_SET_REG; /*!< (@ 0x00000220) Pattern Match Interrupt Mask Set Register */ + + struct { + __IOM uint32_t INTR_MASK_SET : 16; /*!< [15..0] Common pattern or buffer under run interrupt mask set + register for all SIOs */ + __IM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } SIO_PATTERN_MATCH_INTR_MASK_SET_REG_b; + }; + + union { + __OM uint32_t + SIO_PATTERN_MATCH_INTR_MASK_CLEAR_REG; /*!< (@ 0x00000224) Pattern Match Interrupt Mask Clear Register */ + + struct { + __OM uint32_t INTR_MASK_CLEAR : 16; /*!< [15..0] Common pattern or buffer under run interrupt mask clear + register for all SIOs */ + __OM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } SIO_PATTERN_MATCH_INTR_MASK_CLEAR_REG_b; + }; + + union { + __IOM uint32_t + SIO_PATTERN_MATCH_INTR_STATUS_REG; /*!< (@ 0x00000228) Pattern Match Interrupt Status Register */ + + struct { + __IOM uint32_t INTR_STATUS : 16; /*!< [15..0] Common pattern interrupt status register for all SIOs */ + __IM uint32_t RESERVED3 : 16; /*!< [31..16] Reserved for future use */ + } SIO_PATTERN_MATCH_INTR_STATUS_REG_b; + }; + + union { + __IOM uint32_t + SIO_BUFFER_INTR_STATUS_REG; /*!< (@ 0x0000022C) Buffer Interrupt Status Register */ + + struct { + __IOM uint32_t INTR_STATUS : 16; /*!< [15..0] Common pattern interrupt status register for all SIOs */ + __IM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } SIO_BUFFER_INTR_STATUS_REG_b; + }; + + union { + __IOM uint32_t + SIO_OUT_MUX_REG[16]; /*!< (@ 0x00000230) Output muxing Register */ + + struct { + __IOM uint32_t DOUT_OEN_SEL : 3; /*!< [2..0] OEN select for GPIO pin 0 */ + __IOM uint32_t DOUT_SEL : 3; /*!< [5..3] Output mux select for GPIO pin 0 */ + __IM uint32_t RESERVED1 : 26; /*!< [31..6] Reserved for future use */ + } SIO_OUT_MUX_REG_b[16]; + }; + + union { + __IOM uint32_t + SIO_INPUT_MUX_REG[16]; /*!< (@ 0x00000270) Input muxing Register */ + + struct { + __IOM uint32_t CLK_SEL : 3; /*!< [2..0] Input clock select for SIO 0 */ + __IOM uint32_t + QUALIFIER_SELECT : 2; /*!< [4..3] qualifier select */ + __IOM uint32_t + QUALIFIER_MODE : 2; /*!< [6..5] qualifier mode */ + __IOM uint32_t DIN_SEL : 3; /*!< [9..7] Data in mux select */ + __IM uint32_t RESERVED1 : 22; /*!< [31..10] Reserved for future use */ + } SIO_INPUT_MUX_REG_b[16]; + }; + + union { + __IOM uint32_t SIO_FIFO_WR_RD_REG; /*!< (@ 0x000002B0) FIFO READ/WRITE Register */ + + struct { + __IOM uint32_t FIFO_DATA_REGISTER : 32; /*!< [31..0] Writes and read into this register will be written into + SIO buffer register */ + } SIO_FIFO_WR_RD_REG_b; + }; + + union { + __IOM uint32_t + SIO_FIFO_WR_OFFSET_START_REG; /*!< (@ 0x000002B4) Points to start slice number forming the FIFO */ + + struct { + __IOM uint32_t SIO_START_SLICE_NUMBER : 32; /*!< [31..0] Points to start slice number forming the FIFO,On write, + FIFO_WR_OFFSET_CNT_REG will also be reset to the value + pointed written into this register */ + } SIO_FIFO_WR_OFFSET_START_REG_b; + }; + + union { + __IOM uint32_t + SIO_FIFO_WR_OFFSET_END_REG; /*!< (@ 0x000002B8) SIO last slice no indication Register */ + + struct { + __IOM uint32_t + SIO_END_SLICE_NUMBER : 32; /*!< [31..0] points to last slice no forming fifo */ + } SIO_FIFO_WR_OFFSET_END_REG_b; + }; + + union { + __IOM uint32_t + SIO_FIFO_WR_OFFSET_CNT_REG; /*!< (@ 0x000002BC) Points to current slice number forming the FIFO */ + + struct { + __IOM uint32_t SIO_CURRENT_SLICE_NUMBER : 32; /*!< [31..0] Next FIFO operation will happen to buffer in the slice + pointed by this register */ + } SIO_FIFO_WR_OFFSET_CNT_REG_b; + }; + + union { + __IOM uint32_t + SIO_FIFO_RD_OFFSET_START_REG; /*!< (@ 0x000002C0) Points to start slice number forming the FIFO */ + + struct { + __IOM uint32_t + SIO_START_SLICE_NUMBER : 32; /*!< [31..0] Points to start slice number forming the FIFO */ + } SIO_FIFO_RD_OFFSET_START_REG_b; + }; + + union { + __IOM uint32_t + SIO_FIFO_RD_OFFSET_END_REG; /*!< (@ 0x000002C4) Points to last slice number forming the FIFO */ + + struct { + __IOM uint32_t + SIO_END_SLICE_NUMBER : 32; /*!< [31..0] Points to last slice number forming the FIFO */ + } SIO_FIFO_RD_OFFSET_END_REG_b; + }; + + union { + __IOM uint32_t + SIO_FIFO_RD_OFFSET_CNT_REG; /*!< (@ 0x000002C8) Points to start current number forming the FIFO */ + + struct { + __IOM uint32_t SIO_CURRENT_SLICE_NUMBER : 32; /*!< [31..0] Next FIFO operation will happen to buffer in the slice + pointed by this register This register has to be set to + zero before starting fresh DMA operation */ + } SIO_FIFO_RD_OFFSET_CNT_REG_b; + }; +} SIO_Type; /*!< Size = 716 (0x2cc) */ + +/* ================================================================================ */ +/* ================ QSPI ================ */ +/* ================================================================================ */ + +/** + * @brief The queued serial peripheral interface module provides a serial peripheral interface with queued transfer capability (QSPI) + */ + +typedef struct { /*!< QSPI Structure */ + + union { + __IO uint32_t QSPI_CLK_CONFIG; /*!< QSPI Clock Configuration Register */ + + struct { + __IO uint32_t QSPI_AUTO_CSN_HIGH_CNT : 5; /*!< Minimum SOC clock cycles, during which QSPI auto csn should + be high between consecutive CSN assertions */ + __IO uint32_t QSPI_CLK_SYNC : 1; /*!< If the clock frequency to FLASH(spi_clk) and QSPI(hclk) controller + is same, this bit can be set to one to by-pass the syncros results + in time consumption */ + uint32_t : 2; + __IO uint32_t QSPI_CLK_EN : 1; /*!< QSPI clock enable */ + } QSPI_CLK_CONFIG_b; /*!< BitSize */ + }; + + union { + __IO uint32_t QSPI_BUS_MODE; /*!< QSPI Bus Mode Register */ + + struct { + __IO uint32_t + QSPI_9116_FEATURE_EN : 1; /*!< 9115 specific features are enabled with this enable */ + __IO uint32_t QSPI_MAN_MODE_CONF_CSN0 : 2; /*!< Configures the QSPI flash for Single/Dual/Quad mode operation + in manual mode */ + __IO uint32_t AUTO_MODE_RESET : 1; /*!< QSPI Auto controller reset. This is not a Self clearing bit */ + __IO uint32_t QSPI_PREFETCH_EN : 1; /*!< Pre-fetch of data from the model which is connected to QSPI, + automatically with out reading on AHB and is supplied to AHB, + when address is matched with AHB read transaction address */ + __IO uint32_t QSPI_WRAP_EN : 1; /*!< Model wrap is considered with this bit and uses wrap instruction + to read from FLASH */ + __IO uint32_t + QSPI_AUTO_MODE_FRM_REG : 1; /*!< QSPI Mode of Operation */ + uint32_t : 1; + __IO uint32_t QSPI_D2_OEN_CSN0 : 1; /*!< Direction Control for SPI_IO2 in case of dual/single mode for + chip select0 csn0. It is used both in Auto and Manual Mode */ + __IO uint32_t QSPI_D3_OEN_CSN0 : 1; /*!< Direction Control for SPI_IO3 in case of dual/single mode for + chip select0 csn0. It is used both in Auto and Manual Mode. */ + __IO uint32_t QSPI_D2_DATA_CSN0 : 1; /*!< Value of SPI_IO2 in case of dual/single mode for chip select0 + csn0. It is used both in Auto and Manual Mode. */ + __IO uint32_t QSPI_D3_DATA_CSN0 : 1; /*!< Value of SPI_IO3 in case of dual/single mode for chip select0 + csn0. It is used both in Auto and Manual Mode */ + __IO uint32_t QSPI_D2_OEN_CSN1 : 1; /*!< Direction Control for SPI_IO2 in case of dual/single mode for + chip select1 csn1 */ + __IO uint32_t QSPI_D3_OEN_CSN1 : 1; /*!< Direction Control for SPI_IO3 in case of dual/single mode for + chip select1 csn1 */ + __IO uint32_t QSPI_D2_DATA_CSN1 : 1; /*!< Direction Control for SPI_IO3 in case of dual/single mode for + chip select1 csn1 */ + __IO uint32_t QSPI_D3_DATA_CSN1 : 1; /*!< Value of SPI_IO3 in case of dual/single mode for chip select1 + csn1 */ + __IO uint32_t + QSPI_DATA_SAMPLE_EDGE : 1; /*!< Samples MISO data on clock edges */ + __IO uint32_t + QSPI_CLK_MODE_CSN0 : 1; /*!< QSPI Clock Mode */ + __IO uint32_t + QSPI_CLK_MODE_CSN1 : 1; /*!< QSPI Clock Mode */ + __IO uint32_t + QSPI_CLK_MODE_CSN2 : 1; /*!< QSPI Clock Mode */ + __IO uint32_t + QSPI_CLK_MODE_CSN3 : 1; /*!< QSPI Clock Mode */ + uint32_t : 3; + __IO uint32_t QSPI_D2_OEN_CSN2 : 1; /*!< Direction Control for SPI_IO2 in case of dual/single mode for + chip select2 csn2 */ + __IO uint32_t QSPI_D3_OEN_CSN2 : 1; /*!< Direction Control for SPI_IO3 in case of dual/single mode for + chip select2 csn2 */ + __IO uint32_t QSPI_D2_DATA_CSN2 : 1; /*!< Value of SPI_IO2 in case of dual/single mode for chip select2 + csn2 */ + __IO uint32_t QSPI_D3_DATA_CSN2 : 1; /*!< Value of SPI_IO3 in case of dual/single mode for chip select2 + csn2 */ + __IO uint32_t QSPI_D2_OEN_CSN3 : 1; /*!< Direction Control for SPI_IO2 in case of dual/single mode for + chip select3 csn3 */ + __IO uint32_t QSPI_D3_OEN_CSN3 : 1; /*!< Direction Control for SPI_IO3 in case of dual/single mode for + chip select3 csn3 */ + __IO uint32_t QSPI_D2_DATA_CSN3 : 1; /*!< Value of SPI_IO2 in case of dual/single mode for chip select3 + csn3 */ + __IO uint32_t QSPI_D3_DATA_CSN3 : 1; /*!< Value of SPI_IO3 in case of dual/single mode for chip select3 + csn3 */ + } QSPI_BUS_MODE_b; /*!< BitSize */ + }; + + union { + __IO uint32_t QSPI_AUTO_CONFIG_1; /*!< QSPI Auto Controller Configuration 1 Register */ + + struct { + __IO uint32_t + QSPI_EXT_BYTE_MODE_CSN0 : 2; /*!< Mode of operation of QSPI in the extra byte phase */ + __IO uint32_t + QSPI_DUMMY_MODE_CSN0 : 2; /*!< Mode of operation of QSPI in instruction phase */ + __IO uint32_t + QSPI_ADDR_MODE_CSN0 : 2; /*!< Mode of operation of QSPI in instruction phase */ + __IO uint32_t + QSPI_CMD_MODE_CSN0 : 2; /*!< Mode of operation of QSPI in instruction phase */ + __IO uint32_t + QSPI_DATA_MODE_CSN0 : 2; /*!< Mode of operation of QSPI in DATA phase */ + __IO uint32_t QSPI_EXTRA_BYTE_CSN0 : 8; /*!< Value of the extra byte to be transmitted, if the extra byte + mode is enabled */ + __IO uint32_t QSPI_EXTRA_BYTE_EN_CSN0 : 2; /*!< Value of the extra byte to be transmitted, if the extra byte + mode is enabled */ + uint32_t : 3; + __IO uint32_t QSPI_PG_JUMP_CSN0 : 1; /*!< NONE */ + __IO uint32_t QSPI_DUMMY_BYTES_INCR_CSN0 : 4; /*!< Specifies the number of dummy bytes 0 to 7 for the selected + SPI mode */ + __IO uint32_t QSPI_DUMMY_BYTES_WRAP_CSN0 : 4; /*!< Specifies the number of dummy bytes 0 to 7 for the selected + SPI mode in case of wrap instruction */ + } QSPI_AUTO_CONFIG_1_b; /*!< BitSize */ + }; + + union { + __IO uint32_t QSPI_AUTO_CONFIG_2; /*!< QSPI Auto Controller Configuration 2 Register */ + + struct { + __IO uint32_t + QSPI_RD_DATA_SWAP_AUTO_CSN0 : 1; /*!< NONE */ + __IO uint32_t + QSPI_ADR_SIZE_16_BIT_AUTO_MODE_CSN0 : 1; /*!< NONE */ + __IO uint32_t + QSPI_CONTI_RD_EN_CSN0 : 1; /*!< NONE */ + __IO uint32_t + DUMMY_BYTES_WR_RD_CSN0 : 1; /*!< Dummy bytes to the model to be read or to be write */ + __IO uint32_t + QSPI_DUMMY_BYTES_JMP_CSN : 4; /*!< Dummy cycles to be selected in case of JUMP */ + __IO uint32_t QSPI_RD_INST_CSN0 : 8; /*!< Read instruction to be used for the selected SPI modes and when + wrap */ + __IO uint32_t QSPI_RD_WRAP_INT_CSN0 : 8; /*!< Read instruction to be used, when wrap mode is supported by + QSPI flash */ + __IO uint32_t + QSPI_PG_JUMP_INST_CSN0 : 8; /*!< Read instruction to be used, when Page jump is to be used */ + } QSPI_AUTO_CONFIG_2_b; /*!< BitSize */ + }; + + union { + __IO uint32_t QSPI_MANUAL_CONFIG1; /*!< QSPI Manual Configuration 1 Register */ + + struct { + __IO uint32_t QSPI_MANUAL_CSN : 1; /*!< SPI CS in manual mode */ + __IO uint32_t QSPI_MANUAL_WR : 1; /*!< Write enable for manual mode when CS is low */ + __IO uint32_t QSPI_MANUAL_RD : 1; /*!< Read enable for manual mode when CS is low */ + __IO uint32_t QSPI_MANUAL_RD_CNT : 10; /*!< Indicates total number of bytes to be read along with 31:27 + bits of this register.Maximum length supported is 32k bytes */ + __IO uint32_t + QSPI_MANUAL_CSN_SELECT : 2; /*!< Indicates which CSn is valid */ + uint32_t : 4; + __IO uint32_t + QSPI_MANUAL_SIZE_FRM_REG : 2; /*!< Manual reads and manual writes follow this size */ + __IO uint32_t + TAKE_QSPI_MANUAL_WR_SIZE_FRM_REG : 1; /*!< NONE */ + __IO uint32_t + QSPI_FULL_DUPLEX_EN : 1; /*!< Full duplex mode enable. */ + uint32_t : 2; + __IO uint32_t + HW_CTRLD_QSPI_MODE_CTRL : 1; /*!< Hardware controlled qspi mode in between AUTO and manual */ + __IO uint32_t + QSPI_MANUAL_QSPI_MODE : 1; /*!< Internally the priority is given to manual mode */ + } QSPI_MANUAL_CONFIG1_b; /*!< BitSize */ + }; + + union { + __IO uint32_t QSPI_MANUAL_CONFIG2; /*!< QSPI Manual Configuration 2 Register */ + + struct { + __IO uint32_t + QSPI_WR_DATA_SWAP_MNL_CSN0 : 1; /*!< Swap the write data inside the QSPI controller it-self */ + __IO uint32_t + QSPI_WR_DATA_SWAP_MNL_CSN1 : 1; /*!< Swap the write data inside the QSPI controller it-self. */ + __IO uint32_t + QSPI_WR_DATA_SWAP_MNL_CSN2 : 1; /*!< Swap the write data inside the QSPI controller itself. */ + __IO uint32_t + QSPI_WR_DATA_SWAP_MNL_CSN3 : 1; /*!< Swap the write data inside the QSPI controller itself. */ + __IO uint32_t + QSPI_RD_DATA_SWAP_MNL_CSN0 : 1; /*!< Swap the read data inside the QSPIcontroller it self. */ + __IO uint32_t + QSPI_RD_DATA_SWAP_MNL_CSN1 : 1; /*!< Swap the read data inside the QSPIcontroller itself. */ + __IO uint32_t + QSPI_RD_DATA_SWAP_MNL_CSN2 : 1; /*!< Swap the read data inside the QSPIcontroller it-self */ + __IO uint32_t + QSPI_RD_DATA_SWAP_MNL_CSN3 : 1; /*!< Swap the read data inside the QSPIcontroller itself */ + __IO uint32_t QSPI_MAN_MODE_CONF_CSN1 : 2; /*!< Configures the QSPI flash for Single/Dual/Quad mode operation + in manual mode for chip select1 csn1 */ + __IO uint32_t + QSPI_MAN_MODE_CONF_CSN2 : 2; /*!< Configures the QSPI flash for Single or Dual or Quad mode operation + in manual mode for chip select2 csn2 */ + __IO uint32_t + QSPI_MAN_MODE_CONF_CSN3 : 2; /*!< Configures the QSPI flash for Single or Dual or Quad mode operation + in manual mode for chip select3 csn3 */ + __IO uint32_t LOOP_BACK_EN : 1; /*!< Internal loop back test mode. */ + __IO uint32_t + QSPI_MANUAL_DDR_PHASE : 1; /*!< DDR operations can be performed even in manual mode */ + __IO uint32_t QSPI_DDR_CLK_EN : 1; /*!< DDR operations can be performed even in manual mode */ + } QSPI_MANUAL_CONFIG2_b; /*!< BitSize */ + }; + __IO uint32_t RESERVED3; + + union { + __IO uint32_t QSPI_FIFO_THRLD; /*!< QSPI FIFO Threshold Register */ + + struct { + __IO uint32_t FIFO_AEMPTY_THRLD : 4; /*!< FIFO almost empty threshold */ + __IO uint32_t FIFO_AFULL_THRLD : 4; /*!< FIFO almost full threshold */ + __IO uint32_t WFIFO_RESET : 1; /*!< Write fifo reset */ + __IO uint32_t RFIFO_RESET : 1; /*!< Read fifo reset */ + } QSPI_FIFO_THRLD_b; /*!< BitSize */ + }; + + union { + __I uint32_t QSPI_MANUAL_STATUS; /*!< QSPI Manual Status Register */ + + struct { + __I uint32_t QSPI_BUSY : 1; /*!< State of Manual mode. */ + __I uint32_t FIFO_FULL_WFIFO_S : 1; /*!< Status indication for Wfifo in manual mode */ + __I uint32_t FIFO_AFULL_WFIFO_S : 1; /*!< Status indication for Wfifo in manual mode */ + __I uint32_t FIFO_EMPTY_WFIFO : 1; /*!< Status indication for Wfifo in manual mode */ + __I uint32_t FIFO_AEMPTY_WFIFO : 1; /*!< Status indication for Wfifo in manual mode */ + __I uint32_t FIFO_FULL_RFIFO : 1; /*!< Status indication for Rfifo in manual mode */ + __I uint32_t FIFO_AFULL_RFIFO : 1; /*!< Status indication for Rfifo in manual mode */ + __I uint32_t FIFO_EMPTY_RFIFO_S : 1; /*!< Status indication for Rfifo in manual mode */ + __I uint32_t + FIFO_AEMPTY_RFIFO_S : 1; /*!< Status indication for Rfifo in manual mode */ + __I uint32_t GSPI_MANUAL_RD_CNT : 1; /*!< This is a result of 10 bits ORing counter */ + __I uint32_t + AUTO_MODE_FSM_IDLE_SCLK : 1; /*!< Auto mode idle signal to track auto controller is busy or idle. */ + __I uint32_t QSPI_AUTO_MODE : 1; /*!< QSPI controller status. */ + __I uint32_t QSPI_AUTO_MODE_FRM_REG_SCLK : 1; /*!< QSPI auto mode status. Valid only when HW_CTRLD_QSPI_MODE_CTRL + is zero. */ + __I uint32_t HW_CTRLD_MODE_SCLK : 1; /*!< QSPI mode status in HW_CTRLD_MODE */ + __I uint32_t + HW_CTRLD_MODE_CTRL_SCLK : 1; /*!< HW_CTRLD_MODE status */ + } QSPI_MANUAL_STATUS_b; /*!< BitSize */ + }; + + union { + __IO uint32_t QSPI_INTR_MASK; /*!< QSPI Interrupt Mask Register */ + + struct { + __IO uint32_t QSPI_INTR_MASK : 1; /*!< Interrupt Status bit */ + __IO uint32_t + FIFO_AEMPTY_RFIFO_MASK : 1; /*!< NONE */ + __IO uint32_t + FIFO_AFULL_RFIFO_MASK : 1; /*!< NONE */ + __IO uint32_t + FIFO_AEMPTY_WFIFO_MASK : 1; /*!< NONE */ + __IO uint32_t + FIFO_AFULL_WFIFO_MASK : 1; /*!< NONE */ + __IO uint32_t + FIFO_FULL_WFIFO_MASK : 1; /*!< NONE */ + __IO uint32_t + FIFO_EMPTY_RFIFO_MASK : 1; /*!< NONE */ + } QSPI_INTR_MASK_b; /*!< BitSize */ + }; + + union { + __IO uint32_t QSPI_INTR_UNMASK; /*!< QSPI Interrupt Unmask Register */ + + struct { + __IO uint32_t QSPI_INTR_UNMASK : 1; /*!< Interrupt Status bit */ + __IO uint32_t + FIFO_AEMPTY_RFIFO_UN : 1; /*!< NONE */ + __IO uint32_t + FIFO_AFULL_RFIFO_UNMASK : 1; /*!< NONE */ + __IO uint32_t + FIFO_AEMPTY_WFIFO_UNMASK : 1; /*!< NONE */ + __IO uint32_t + FIFO_AFULL_WFIFO_UNMASK : 1; /*!< NONE */ + __IO uint32_t + FIFO_FULL_WFIFO_UNMASK : 1; /*!< NONE */ + __IO uint32_t + FIFO_EMPTY_RFIFO_UNMASK : 1; /*!< NONE */ + } QSPI_INTR_UNMASK_b; /*!< BitSize */ + }; + + union { + __I uint32_t QSPI_INTR_STS; /*!< QSPI Interrupt Status Register */ + + struct { + __I uint32_t QSPI_INTR_LVL : 1; /*!< Interrupt Status bit */ + __I uint32_t + FIFO_AEMPTY_RFIFO_LVL : 1; /*!< NONE */ + __I uint32_t + FIFO_AFULL_RFIFO_LVL : 1; /*!< NONE */ + __I uint32_t + FIFO_AEMPTY_WFIFO_LVL : 1; /*!< NONE */ + __I uint32_t + FIFO_AFULL_WFIFO_LVL : 1; /*!< NONE */ + __I uint32_t + FIFO_FULL_WFIFO_LVL : 1; /*!< NONE */ + __I uint32_t + FIFO_EMPTY_RFIFO_LVL : 1; /*!< NONE */ + } QSPI_INTR_STS_b; /*!< BitSize */ + }; + + union { + __O uint32_t QSPI_INTR_ACK; /*!< QSPI Interrupt Acknowledge Register */ + + struct { + __O uint32_t QSPI_INTR_ACK : 1; /*!< Interrupt Status bit */ + __O uint32_t + FIFO_AEMPTY_RFIFO_ACK : 1; /*!< NONE */ + __O uint32_t + FIFO_AFULL_RFIFO_ACK : 1; /*!< NONE */ + __O uint32_t + FIFO_AEMPTY_WFIFO_ACK : 1; /*!< NONE */ + __O uint32_t + FIFO_AFULL_WFIFO_ACK : 1; /*!< NONE */ + __O uint32_t + FIFO_FULL_WFIFO_ACK : 1; /*!< NONE */ + __O uint32_t + FIFO_EMPTY_RFIFO_ACK : 1; /*!< NONE */ + } QSPI_INTR_ACK_b; /*!< BitSize */ + }; + + union { + __I uint32_t QSPI_STS_MC; /*!< QSPI State Machine Monitor Register */ + + struct { + __I uint32_t BUS_CTRL_PSTATE : 4; /*!< Bus controller present state */ + __I uint32_t AUTO_CTRL_PSTATE : 3; /*!< Auto controller present state */ + __I uint32_t QSPI_MASTER_PSTATE : 3; /*!< Qspi master present state */ + } QSPI_STS_MC_b; /*!< BitSize */ + }; + + union { + __IO uint32_t QSPI_AUTO_CONFIG_1_CSN1; /*!< QSPI Auto Controller Configuration 1 CSN1 Register */ + + struct { + __IO uint32_t + QSPI_EXT_BYTE_MODE_CSN1 : 2; /*!< Mode of operation of QSPI in instruction phase. */ + __IO uint32_t + QSPI_DUMMY_MODE_CSN1 : 2; /*!< Mode of operation of QSPI in instruction phase */ + __IO uint32_t + QSPI_ADDR_MODE_CSN1 : 2; /*!< Mode of operation of QSPI in instruction phase. */ + __IO uint32_t + QSPI_CMD_MODE_CSN1 : 2; /*!< Mode of operation of QSPI in instruction phase. */ + __IO uint32_t + QSPI_DATA_MODE_CSN1 : 2; /*!< Mode of operation of QSPI in DATA phase. */ + __I uint32_t QSPI_EXTRA_BYTE_CSN1 : 8; /*!< Value of the extra byte to be transmitted, if the extra byte + mode is enabled. */ + __IO uint32_t + QSPI_EXTRA_BYTE_EN_CSN1 : 2; /*!< Mode of operation of QSPI in DATA phase. */ + uint32_t : 3; + __O uint32_t QSPI_PG_JUMP_CSN1 : 1; /*!< NONE */ + __I uint32_t QSPI_DUMMY_BYTES_INCR_CSN1 : 4; /*!< Specifies the number of dummy bytes 0 to 7 for the selected + SPI mode. */ + __I uint32_t QSPI_DUMMY_BYTES_WRAP_CSN1 : 4; /*!< Specifies the number of dummy bytes 0 to 7 for the selected + SPI mode in case of wrap instruction. */ + } QSPI_AUTO_CONFIG_1_CSN1_b; /*!< BitSize */ + }; + + union { + __IO uint32_t + QSPI_AUTO_CONFIG_2_CSN1_REG; /*!< QSPI Auto Controller Configuration 2 CSN1 Register */ + + struct { + __IO uint32_t QSPI_RD_SWAP_AUTO_CSN1 : 1; /*!< Swap the read data from the flash in byte order for chip select1 + csn1 in auto mode. */ + __IO uint32_t + QSPI_ADR_SIZE_16BIT_AUTO_MODE_CSN1 : 1; /*!< NONE */ + __IO uint32_t + QSPI_CONTI_RD_EN_CSN1 : 1; /*!< Continuous read enable bit. */ + __IO uint32_t DUMMY_BYTES_WR_RD : 1; /*!< Dummy bytes to the model to be read or to be write. */ + __IO uint32_t + QSPI_DUMMY_BYTES_JMP_CSN1 : 4; /*!< Dummy cycles to be selected in case of JUMP */ + __IO uint32_t QSPI_RD_INST_CSN1 : 8; /*!< Read instruction to be used for the selected SPI modes and when + wrap is not needed or supported */ + __IO uint32_t QSPI_RD_WRAP_INST_CSN1 : 8; /*!< Read instruction to be used for the selected SPI modes and when + wrap is not needed or supported */ + __IO uint32_t + QSPI_PG_JMP_INST_CSN1 : 8; /*!< Read instruction to be used, when Page jump is to be used. */ + } QSPI_AUTO_CONFIG_2_CSN1_REG_b; /*!< BitSize */ + }; + __IO uint32_t QSPI_MANUAL_RDWR_FIFO[16]; /*!< QSPI FIFOs */ + union { + __IO uint32_t QSPI_MANUAL_WRITE_DATA2; /*!< QSPI Manual Write Data 2 Register */ + + struct { + __IO uint32_t + QSPI_MANUAL_WRITE_DATA2 : 5; /*!< Number of bits to be written in write mode */ + uint32_t : 2; + __IO uint32_t USE_PREV_LENGTH : 1; /*!< Use previous length. */ + } QSPI_MANUAL_WRITE_DATA2_b; /*!< BitSize */ + }; + union { + __IO uint32_t QSPI_AUTO_CONFIG_1_CSN2; /*!< QSPI Auto Controller Configuration 1 CSN2 Register */ + + struct { + __IO uint32_t + QSPI_EXT_BYTE_MODE_CSN2 : 2; /*!< Mode of operation of QSPI in instruction phase. */ + __IO uint32_t + QSPI_DUMMY_MODE_CSN2 : 2; /*!< Mode of operation of QSPI in instruction phase */ + __IO uint32_t + QSPI_ADDR_MODE_CSN2 : 2; /*!< Mode of operation of QSPI in instruction phase. */ + __IO uint32_t + QSPI_CMD_MODE_CSN2 : 2; /*!< Mode of operation of QSPI in instruction phase. */ + __IO uint32_t + QSPI_DATA_MODE_CSN2 : 2; /*!< Mode of operation of QSPI in DATA phase. */ + __I uint32_t QSPI_EXTRA_BYTE_CSN2 : 8; /*!< Value of the extra byte to be transmitted, if the extra byte + mode is enabled. */ + __IO uint32_t + QSPI_EXTRA_BYTE_EN_CSN2 : 2; /*!< Mode of operation of QSPI in DATA phase. */ + uint32_t : 3; + __O uint32_t QSPI_PG_JUMP_CSN2 : 1; /*!< NONE */ + __I uint32_t QSPI_DUMMY_BYTES_INCR_CSN2 : 4; /*!< Specifies the number of dummy bytes 0 to 7 for the selected + SPI mode. */ + __I uint32_t QSPI_DUMMY_BYTES_WRAP_CSN2 : 4; /*!< Specifies the number of dummy bytes 0 to 7 for the selected + SPI mode in case of wrap instruction. */ + } QSPI_AUTO_CONFIG_1_CSN2_b; /*!< BitSize */ + }; + + union { + __IO uint32_t + QSPI_AUTO_CONFIG_2_CSN2_REG; /*!< QSPI Auto Controller Configuration 2 CSN2 Register */ + + struct { + __IO uint32_t QSPI_RD_SWAP_AUTO_CSN2 : 1; /*!< Swap the read data from the flash in byte order for chip select1 + csn1 in auto mode. */ + __IO uint32_t + QSPI_ADR_SIZE_16BIT_AUTO_MODE_CSN2 : 1; /*!< NONE */ + __IO uint32_t + QSPI_CONTI_RD_EN_CSN2 : 1; /*!< Continuous read enable bit. */ + __IO uint32_t + DUMMY_BYTES_WR_RD_CSN2 : 1; /*!< Dummy bytes to the model to be read or to be write. */ + __IO uint32_t + QSPI_DUMMY_BYTES_JMP_CSN2 : 4; /*!< Dummy cycles to be selected in case of JUMP */ + __IO uint32_t QSPI_RD_INST_CSN2 : 8; /*!< Read instruction to be used for the selected SPI modes and when + wrap is not needed or supported */ + __IO uint32_t QSPI_RD_WRAP_INST_CSN2 : 8; /*!< Read instruction to be used for the selected SPI modes and when + wrap is not needed or supported */ + __IO uint32_t + QSPI_PG_JMP_INST_CSN2 : 8; /*!< Read instruction to be used, when Page jump is to be used. */ + } QSPI_AUTO_CONFIG_2_CSN2_REG_b; /*!< BitSize */ + }; + + union { + __IO uint32_t QSPI_AUTO_CONFIG_1_CSN3; /*!< QSPI Auto Controller Configuration 1 CSN3 Register */ + + struct { + __IO uint32_t + QSPI_EXT_BYTE_MODE_CSN3 : 2; /*!< Mode of operation of QSPI in instruction phase. */ + __IO uint32_t + QSPI_DUMMY_MODE_CSN3 : 2; /*!< Mode of operation of QSPI in instruction phase */ + __IO uint32_t + QSPI_ADDR_MODE_CSN3 : 2; /*!< Mode of operation of QSPI in instruction phase. */ + __IO uint32_t + QSPI_CMD_MODE_CSN3 : 2; /*!< Mode of operation of QSPI in instruction phase. */ + __IO uint32_t + QSPI_DATA_MODE_CSN3 : 2; /*!< Mode of operation of QSPI in DATA phase. */ + __I uint32_t QSPI_EXTRA_BYTE_CSN3 : 8; /*!< Value of the extra byte to be transmitted, if the extra byte + mode is enabled. */ + __IO uint32_t + QSPI_EXTRA_BYTE_EN_CSN3 : 2; /*!< Mode of operation of QSPI in DATA phase. */ + uint32_t : 3; + __O uint32_t QSPI_PG_JUMP_CSN3 : 1; /*!< NONE */ + __I uint32_t QSPI_DUMMY_BYTES_INCR_CSN2 : 4; /*!< Specifies the number of dummy bytes 0 to 7 for the selected + SPI mode. */ + __I uint32_t QSPI_DUMMY_BYTES_WRAP_CSN2 : 4; /*!< Specifies the number of dummy bytes 0 to 7 for the selected + SPI mode in case of wrap instruction. */ + } QSPI_AUTO_CONFIG_1_CSN3_b; /*!< BitSize */ + }; + + union { + __IO uint32_t + QSPI_AUTO_CONFIG_2_CSN3_REG; /*!< QSPI Auto Controller Configuration 2 CSN3 Register */ + + struct { + __IO uint32_t QSPI_RD_SWAP_AUTO_CSN3 : 1; /*!< Swap the read data from the flash in byte order for chip select1 + csn1 in auto mode. */ + __IO uint32_t + QSPI_ADR_SIZE_16BIT_AUTO_MODE_CSN3 : 1; /*!< NONE */ + __IO uint32_t + QSPI_CONTI_RD_EN_CSN3 : 1; /*!< Continuous read enable bit. */ + __IO uint32_t + DUMMY_BYTES_WR_RD_CSN3 : 1; /*!< Dummy bytes to the model to be read or to be write. */ + __IO uint32_t + QSPI_DUMMY_BYTES_JMP_CSN3 : 4; /*!< Dummy cycles to be selected in case of JUMP */ + __IO uint32_t QSPI_RD_INST_CSN3 : 8; /*!< Read instruction to be used for the selected SPI modes and when + wrap is not needed or supported */ + __IO uint32_t QSPI_RD_WRAP_INST_CSN3 : 8; /*!< Read instruction to be used for the selected SPI modes and when + wrap is not needed or supported */ + __IO uint32_t + QSPI_PG_JMP_INST_CSN3 : 8; /*!< Read instruction to be used, when Page jump is to be used. */ + } QSPI_AUTO_CONFIG_2_CSN3_REG_b; /*!< BitSize */ + }; + + union { + __IO uint32_t + QSPI_AUTO_CONFIG_3_CSN0_REG; /*!< QSPI Auto Controller Configuration 3 CSN0 Register */ + + struct { + uint32_t : 12; + __IO uint32_t + QSPI_DDR_CMD_MODE_CSN0 : 1; /*!< DDR Command mode */ + __IO uint32_t + QSPI_DDR_ADDR_MODE_CSN0 : 1; /*!< DDR Address mode */ + __IO uint32_t + QSPI_DDR_DUMMY_MODE_CSN0 : 1; /*!< DDR Address mode */ + __IO uint32_t + QSPI_DDR_EXTRA_MODE_CSN0 : 1; /*!< DDR Address mode */ + __IO uint32_t + QSPI_DDR_DATA_MODE_CSN0 : 1; /*!< DDR Address mode */ + } QSPI_AUTO_CONFIG_3_CSN0_REG_b; /*!< BitSize */ + }; + + union { + __IO uint32_t + QSPI_AUTO_CONFIG_3_CSN1_REG; /*!< QSPI Auto Controller Configuration 3 CSN1 Register */ + + struct { + uint32_t : 12; + __IO uint32_t + QSPI_DDR_CMD_MODE_CSN1 : 1; /*!< DDR Command mode */ + __IO uint32_t + QSPI_DDR_ADDR_MODE_CSN1 : 1; /*!< DDR Address mode */ + __IO uint32_t + QSPI_DDR_DUMMY_MODE_CSN1 : 1; /*!< DDR Address mode */ + __IO uint32_t + QSPI_DDR_EXTRA_MODE_CSN1 : 1; /*!< DDR Address mode */ + __IO uint32_t + QSPI_DDR_DATA_MODE_CSN1 : 1; /*!< DDR Address mode */ + } QSPI_AUTO_CONFIG_3_CSN1_REG_b; /*!< BitSize */ + }; + __I uint32_t RESERVED[11]; + + union { + __IO uint32_t + OCTASPI_BUS_CONTROLLER_2_REG; /*!< none */ + + struct { + __IO uint32_t SET_IP_MODE : 1; /*!< This bit enables the qspi interface pins into HiZ mode */ + __IO uint32_t AES_NONCE_INIT : 1; /*!< This bit enables the AES initialization with nonce */ + __IO uint32_t AES_SEC_ENABLE : 1; /*!< This bit enables the AES security enable or not */ + __IO uint32_t DUAL_MODE_EN : 1; /*!< Dual flash mode enable control. */ + __IO uint32_t CSN0_2_CSN : 2; /*!< Map csn0 to the programmed csn. It is valid for both manual + and auto modes */ + __IO uint32_t CSN1_2_CSN : 2; /*!< Map csn1 to the programmed csn. It is valid for both manual + and auto modes */ + __IO uint32_t CSN2_2_CSN : 2; /*!< Map csn2 to the programmed csn. It is valid for both manual + and auto modes */ + __IO uint32_t CSN3_2_CSN : 2; /*!< Map csn3 to the programmed csn. It is valid for both manual + and auto modes */ + __IO uint32_t AES_SEC_ENABLE_SG1 : 1; /*!< This bit enables the AES security enable or not for segment + 1 */ + __IO uint32_t AES_SEC_ENABLE_SG2 : 1; /*!< This bit enables the AES security enable or not for segment + 2 */ + __IO uint32_t AES_SEC_ENABLE_SG3 : 1; /*!< This bit enables the AES security enable or not for segment + 3 */ + __IO uint32_t AES_SEC_ENABLE_SG4 : 1; /*!< This bit enables the AES security enable or not for segment + 4 */ + __IO uint32_t + DUAL_MODE_SWAP_LINES : 1; /*!< This bit controls the 8 lines of qspi with 4 bit swap manner */ + uint32_t : 2; + __IO uint32_t + DUAL_STAGE_EN_MANUAL : 1; /*!< Dual stage en for dual flash mode */ + } OCTASPI_BUS_CONTROLLER_2_REG_b; /*!< BitSize */ + }; + __I uint32_t RESERVED1[15]; + + union { + __IO uint32_t + QSPI_SRAM_CTRL_CSN_REG[4]; /*!< none */ + + struct { + __IO uint32_t BIT_8_MODE : 1; /*!< Flash 8bit (1 byte) boundary mode */ + __IO uint32_t BYTE_32_MODE : 1; /*!< Flash 32 byte boundary mode */ + __IO uint32_t ADDR_16BIT_MODE : 1; /*!< Send only lower 16bits of Address enable. */ + uint32_t : 5; + __IO uint32_t CMD_MODE : 2; /*!< writing cmd mode */ + __IO uint32_t ADDR_MODE : 2; /*!< writing address mode */ + __IO uint32_t DATA_MODE : 2; /*!< writing address mode */ + uint32_t : 2; + __IO uint32_t WR_CMD : 8; /*!< Command to be used for writing */ + } QSPI_SRAM_CTRL_CSN_REG_b[4]; /*!< BitSize */ + }; + __I uint32_t RESERVED2[2]; + __IO uint32_t SEMI_AUTO_MODE_ADDR_REG; /*!< Byte address to read the data from flash in semi auto mode. + It is valid only semi auto mode enable bit is asserted */ + + union { + __IO uint32_t + SEMI_AUTO_MODE_CONFIG_REG; /*!< none */ + + struct { + __IO uint32_t + QSPI_SEMI_AUTO_BSIZE : 8; /*!< This is burst size to read data from flash in semi auto mode */ + __IO uint32_t + QSPI_SEMI_AUTO_HSIZE : 2; /*!< Indicates number of bytes valid in each transaction */ + } SEMI_AUTO_MODE_CONFIG_REG_b; /*!< BitSize */ + }; + + union { + __IO uint32_t + SEMI_AUTO_MODE_CONFIG2_REG; /*!< none */ + + struct { + __IO uint32_t QSPI_SEMI_AUTO_RD_CNT : 12; /*!< Total number of bytes to be read flash continuously from the + address given by SEMI_AUTO_MODE_ADDR_REG */ + __IO uint32_t QSPI_SEMI_AUTO_MODE_EN : 1; /*!< Enable for semi auto mode read operation. Make sure manual mode + read/write operation is completed before asserting this bit */ + __IO uint32_t QSPI_SEMI_AUTO_RD_BUSY : 1; /*!< Indicates status of semi auto mode read status. If it is high, + semi auto mode read operation is progressing */ + } SEMI_AUTO_MODE_CONFIG2_REG_b; /*!< BitSize */ + }; +} QSPI_Type; + +/* =========================================================================================================================== */ +/* ================ CRC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CRC is used in all wireless communication as a first data integrity check (CRC) + */ + +typedef struct { /*!< (@ 0x45080000) CRC Structure */ + + union { + __IOM uint32_t + CRC_GEN_CTRL_SET_REG; /*!< (@ 0x00000000) General control set register */ + + struct { + __IOM uint32_t SOFT_RST : 1; /*!< (@ 0x00000000) Soft reset. This clears the FIFO and settles + all the state machines to their IDLE */ + __IOM uint32_t RESERVED1 : 31; /*!< (@ 0x00000001) Reserved for future use. */ + } CRC_GEN_CTRL_SET_REG_b; + }; + + union { + __IOM uint32_t CRC_GEN_CTRL_RESET; /*!< (@ 0x00000004) General control reset register */ + + struct { + __IOM uint32_t RESERVED1 : 32; /*!< (@ 0x00000000) Reserved for future use. */ + } CRC_GEN_CTRL_RESET_b; + }; + + union { + __IM uint32_t CRC_GEN_STS; /*!< (@ 0x00000008) General status register */ + + struct { + __IM uint32_t CALC_DONE : 1; /*!< (@ 0x00000000) When the computation of final CRC with the data + out of fifo, this will get set to 1 otherwise + 0 */ + __IM uint32_t DIN_NUM_BYTES_DONE : 1; /*!< (@ 0x00000001) When number of bytes requested for computation + of final CRC is read from fifo by internal + FSM, this will get set to 1 otherwise 0. */ + __IM uint32_t RESERVED1 : 30; /*!< (@ 0x00000002) Reserved for future use. */ + } CRC_GEN_STS_b; + }; + + union { + __IOM uint32_t CRC_POLYNOMIAL; /*!< (@ 0x0000000C) This register holds the polynomial with which + the final CRC is computed. */ + + struct { + __IOM uint32_t POLYNOMIAL : 32; /*!< (@ 0x00000000) Polynomial register. This register holds the + polynomial with which the final CRC is + computed.When write Polynomial will be + updated.When read read polynomial. */ + } CRC_POLYNOMIAL_b; + }; + + union { + __IOM uint32_t + CRC_POLYNOMIAL_CTRL_SET; /*!< (@ 0x00000010) Polynomial control set register */ + + struct { + __IOM uint32_t POLYNOMIAL_WIDTH_SET : 5; /*!< (@ 0x00000000) Polynomial width set. Number of bits/width of + the polynomial has to be written here for + the computation of final CRC. If a new + width has to be configured, clear the existing + length first by writing 0x1f in polynomial_ctrl_reset + register. When read, actual polynomial + width is read. */ + __IOM uint32_t RESERVED1 : 27; /*!< (@ 0x00000005) Reserved for future use. */ + } CRC_POLYNOMIAL_CTRL_SET_b; + }; + + union { + __IOM uint32_t + CRC_POLYNOMIAL_CTRL_RESET; /*!< (@ 0x00000014) Polynomial control set register */ + + struct { + __IOM uint32_t POLYNOMIAL_WIDTH_SET : 5; /*!< (@ 0x00000000) Polynomial width reset. If a new width has to + be configured, clear the existing length + first by writing 0x1f. When read, actual + polynomial width is read. */ + __IOM uint32_t RESERVED1 : 27; /*!< (@ 0x00000005) Reserved for future use. */ + } CRC_POLYNOMIAL_CTRL_RESET_b; + }; + + union { + __IOM uint32_t CRC_LFSR_INIT_VAL; /*!< (@ 0x00000018) LFSR initial value */ + + struct { + __IOM uint32_t LFSR_INIT : 32; /*!< (@ 0x00000000) This holds LFSR initialization value. When ever + LFSR needs to be initialized, this has + to be updated with the init value and trigger + init_lfsr in LFSR_INIT_CTRL_SET register. + For example, in WiFi case, 0xffffffff is + used as init value of LFSR. */ + } CRC_LFSR_INIT_VAL_b; + }; + + union { + __IOM uint32_t + CRC_LFSR_INIT_CTRL_SET; /*!< (@ 0x0000001C) LFSR state initialization control set register */ + + struct { + __IOM uint32_t CLEAR_LFSR : 1; /*!< (@ 0x00000000) Clear LFSR state. When this is set, LFSR state + is cleared to 0 */ + __IOM uint32_t INIT_LFSR : 1; /*!< (@ 0x00000001) Initialize LFSR state. When this is set LFSR + state will be initialized with LFSR_INIT_VAL/bit + swapped LFSR_INIT_VAL in the next cycle */ + __IOM uint32_t USE_SWAPPED_INIT_VAL : 1; /*!< (@ 0x00000002) Use bit swapped init value. If this is set bit + swapped version of LFSR init value will + be loaded / initialized to LFSR state */ + __IOM uint32_t RESERVED1 : 29; /*!< (@ 0x00000003) Reserved for future use. */ + } CRC_LFSR_INIT_CTRL_SET_b; + }; + + union { + __IOM uint32_t + CRC_LFSR_INIT_CTRL_RESET; /*!< (@ 0x00000020) LFSR state initialization control reset register */ + + struct { + __IOM uint32_t RESERVED1 : 1; /*!< (@ 0x00000000) Reserved for future use. */ + __IOM uint32_t RESERVED2 : 1; /*!< (@ 0x00000001) Reserved for future use. */ + __IOM uint32_t USE_SWAPPED_INIT_VAL : 1; /*!< (@ 0x00000002) Use bit swapped init value. If this is set bit + swapped version of LFSR init value will + be loaded / initialized to LFSR state */ + __IOM uint32_t RESERVED3 : 29; /*!< (@ 0x00000003) Reserved for future use. */ + } CRC_LFSR_INIT_CTRL_RESET_b; + }; + + union { + __OM uint32_t CRC_DIN_FIFO; /*!< (@ 0x00000024) Data input FIFO register */ + + struct { + __OM uint32_t DIN_FIFO : 32; /*!< (@ 0x00000000) FIFO input port is mapped to this register. Data + on which the final CRC has to be computed + has to be loaded to this FIFO */ + } CRC_DIN_FIFO_b; + }; + + union { + __IOM uint32_t CRC_DIN_CTRL_SET; /*!< (@ 0x00000028) Input data control set register */ + + struct { + __IOM uint32_t DIN_WIDTH_REG : 5; /*!< (@ 0x00000000) Valid number of bits in the input data in din_width_from_reg + set mode. Before writing a new value into + this, din_ctrl_reset_reg has to be written + with 0x1f to clear this field as these + are set/clear bits. */ + __IOM uint32_t DIN_WIDTH_FROM_REG : 1; /*!< (@ 0x00000005) Valid number of bits in the input data. In default, + number of valid bits in the input data + is taken from ULI (uli_be). If this is + set, whatever is the input size, only din_ctrl_reg[4:0] + is taken as valid length/width for inout + data. */ + __IOM uint32_t DIN_WIDTH_FROM_CNT : 1; /*!< (@ 0x00000006) Valid number of bits in the input data. In default, + number of valid bits in the input data + is taken from ULI (uli_be). If this is + set, a mix of ULI length and number of + bytes remaining will form the valid bits + (which ever is less that will be considered + as valid bits). */ + __IOM uint32_t USE_SWAPPED_DIN : 1; /*!< (@ 0x00000007) Use bit swapped input data. If this is set, input + data will be swapped and filled in to FIFO. + Whatever read out from FIFO will be directly + fed to LFSR engine. */ + __IOM uint32_t RESET_FIFO_PTRS : 1; /*!< (@ 0x00000008) Reset fifo pointer. This clears the FIFO.When + this is set, FIFO will be cleared. */ + __IOM uint32_t RESERVED1 : 15; /*!< (@ 0x00000009) Reserved for future use. */ + __IOM uint32_t FIFO_AEMPTY_THRESHOLD : 4; /*!< (@ 0x00000018) FIFO almost empty threshold value. This has to + be cleared by writing 0x0f000000 into din_ctrl_reset + before updating any new value. */ + __IOM uint32_t FIFO_AFULL_THRESHOULD : 4; /*!< (@ 0x0000001C) FIFO almost full threshold value. This has to + be cleared by writing 0xf0000000 into din_ctrl_reset + before updating any new value */ + } CRC_DIN_CTRL_SET_b; + }; + + union { + __IOM uint32_t + CRC_DIN_CTRL_RESET_REG; /*!< (@ 0x0000002C) Input data control set register */ + + struct { + __IOM uint32_t DIN_WIDTH_REG : 5; /*!< (@ 0x00000000) Valid number of bits in the input data in din_width_from_reg + set mode. Before writing a new value into + this, din_ctrl_reset_reg has to be written + with 0x1f to clear this field as these + are set/clear bits. */ + __IOM uint32_t DIN_WIDTH_FROM_REG : 1; /*!< (@ 0x00000005) Valid number of bits in the input data. In default, + number of valid bits in the input data + is taken from ULI (uli_be). If this is + set, whatever is the input size, only din_ctrl_reg[4:0] + is taken as valid length/width for inout + data. */ + __IOM uint32_t DIN_WIDTH_FROM_CNT : 1; /*!< (@ 0x00000006) Valid number of bits in the input data. In default, + number of valid bits in the input data + is taken from ULI (uli_be). If this is + set, a mix of ULI length and number of + bytes remaining will form the valid bits + (which ever is less that will be considered + as valid bits). */ + __IOM uint32_t USE_SWAPPED_DIN : 1; /*!< (@ 0x00000007) Use bit swapped input data. If this is set input + data will be swapped and filled in to FIFO. + Whatever read out from FIFO will be directly + fed to LFSR engine. */ + __IOM uint32_t RESERVED1 : 1; /*!< (@ 0x00000008) Reserved for future use. */ + __IOM uint32_t RESERVED2 : 15; /*!< (@ 0x00000009) Reserved for future use. */ + __IOM uint32_t FIFO_AEMPTY_THRESHOLD : 4; /*!< (@ 0x00000018) FIFO almost empty threshold value. This has to + be cleared by writing 0x0f000000 into din_ctrl_reset + before updating any new value. */ + __IOM uint32_t FIFO_AFULL_THRESHOULD : 4; /*!< (@ 0x0000001C) FIFO almost full threshold value. This has to + be cleared by writing 0xf0000000 into din_ctrl_reset + before updating any new value */ + } CRC_DIN_CTRL_RESET_REG_b; + }; + + union { + __IOM uint32_t CRC_DIN_NUM_BYTES; /*!< (@ 0x00000030) Data input FIFO register */ + + struct { + __IOM uint32_t + DIN_NUM_BYTES : 32; /*!< (@ 0x00000000) in out data number of bytes */ + } CRC_DIN_NUM_BYTES_b; + }; + + union { + __IM uint32_t CRC_DIN_STS; /*!< (@ 0x00000034) Input data status register */ + + struct { + __IM uint32_t FIFO_EMPTY : 1; /*!< (@ 0x00000000) FIFO empty indication status */ + __IM uint32_t FIFO_AEMPTY : 1; /*!< (@ 0x00000001) FIFO almost empty indication status. */ + __IM uint32_t FIFO_AFULL : 1; /*!< (@ 0x00000002) FIFO almost full indication status */ + __IM uint32_t FIFO_FULL : 1; /*!< (@ 0x00000003) FIFO full indication status */ + __IM uint32_t FIFO_OCC : 6; /*!< (@ 0x00000004) FIFO occupancy */ + __IM uint32_t RESERVED1 : 22; /*!< (@ 0x0000000A) Reserved for future use. */ + } CRC_DIN_STS_b; + }; + + union { + __IOM uint32_t CRC_LFSR_STATE; /*!< (@ 0x00000038) LFSR state register */ + + struct { + __IOM uint32_t LFSR_STATE : 32; /*!< (@ 0x00000000) If LFSR dynamic loading is required this can + be used for writing the LFSR state directly. */ + } CRC_LFSR_STATE_b; + }; +} CRC_Type; /*!< Size = 60 (0x3c) */ + +/* ================================================================================ */ +/* ================ EFUSE ================ */ +/* ================================================================================ */ + +/* ================================================================================ */ +/* ================ EFUSE ================ */ +/* ================================================================================ */ + +typedef struct { /*!< (@ 0x4600C000) EFUSE Structure */ + + union { + __IOM uint32_t EFUSE_DA_ADDR_REG; /*!< (@ 0x00000000) Direct Access Registers */ + + struct { + __IOM uint32_t ADDR_BITS : 16; /*!< (@ 0x00000000) These bits specifies the address to write or + read from EFUSE macro model */ + __IOM uint32_t RESERVED1 : 16; /*!< (@ 0x00000010) reserved1 */ + } EFUSE_DA_ADDR_REG_b; + }; + + union { + __IOM uint32_t + EFUSE_DA_CTRL_SET_REG; /*!< (@ 0x00000004) Direct Access Set Registers */ + + struct { + __IOM uint32_t PGENB : 1; /*!< (@ 0x00000000) Set Program enable */ + __IOM uint32_t CSB : 1; /*!< (@ 0x00000001) Set Chip Enable */ + __IOM uint32_t STROBE : 1; /*!< (@ 0x00000002) Set strobe enable */ + __IOM uint32_t LOAD : 1; /*!< (@ 0x00000003) Set Load enable */ + __IOM uint32_t RESERVED1 : 12; /*!< (@ 0x00000004) reserved1 */ + __IOM uint32_t RESERVED2 : 16; /*!< (@ 0x00000010) reserved2 */ + } EFUSE_DA_CTRL_SET_REG_b; + }; + + union { + __IOM uint32_t + EFUSE_DA_CTRL_CLEAR_REG; /*!< (@ 0x00000008) Direct Access Clear Registers */ + + struct { + __IOM uint32_t PGENB : 1; /*!< (@ 0x00000000) Clear Program enable */ + __IOM uint32_t CSB : 1; /*!< (@ 0x00000001) Clear Chip Enable */ + __IM uint32_t RESERVED1 : 1; /*!< (@ 0x00000002) reserved1 */ + __IOM uint32_t LOAD : 1; /*!< (@ 0x00000003) Clear Load enable */ + __IM uint32_t RESERVED2 : 12; /*!< (@ 0x00000004) reserved2 */ + __IM uint32_t RESERVED3 : 16; /*!< (@ 0x00000010) reserved3 */ + } EFUSE_DA_CTRL_CLEAR_REG_b; + }; + + union { + __IOM uint32_t EFUSE_CTRL_REG; /*!< (@ 0x0000000C) Control Register */ + + struct { + __IOM uint32_t EFUSE_ENABLE : 1; /*!< (@ 0x00000000) This bit specifies whether the EFUSE module is + enabled or not */ + __IOM uint32_t EFUSE_DIRECT_PATH_ENABLE : 1; /*!< (@ 0x00000001) This bit specifies whether the EFUSE direct path + is enabled or not for direct accessing + of the EFUSE pins */ + __IOM uint32_t + ENABLE_EFUSE_WRITE : 1; /*!< (@ 0x00000002) Controls the switch on VDDIQ for eFuse read/write. */ + __IM uint32_t RESERVED1 : 13; /*!< (@ 0x00000003) reserved1 */ + __IM uint32_t RESERVED2 : 16; /*!< (@ 0x00000010) reserved2 */ + } EFUSE_CTRL_REG_b; + }; + + union { + __IOM uint32_t + EFUSE_READ_ADDR_REG; /*!< (@ 0x00000010) Read address Register */ + + struct { + __IOM uint32_t READ_ADDR_BITS : 13; /*!< (@ 0x00000000) These bits specifies the address from which read + operation has to be performed */ + __IM uint32_t RESERVED1 : 2; /*!< (@ 0x0000000D) reserved1 */ + __OM uint32_t DO_READ : 1; /*!< (@ 0x0000000F) Enables read FSM after EFUSE is enabled */ + __IM uint32_t RESERVED2 : 16; /*!< (@ 0x00000010) reserved2 */ + } EFUSE_READ_ADDR_REG_b; + }; + + union { + __IOM uint32_t + EFUSE_READ_DATA_REG; /*!< (@ 0x00000014) Read address Register */ + + struct { + __IOM uint32_t READ_DATA_BITS : 8; /*!< (@ 0x00000000) These bits specifies the data bits that are read + from a given address specified in the EFUSE_READ_ADDRESS_ + EGISTER bits 8:0 */ + __IM uint32_t RESERVED1 : 7; /*!< (@ 0x00000008) reserved1 */ + __IM uint32_t READ_FSM_DONE : 1; /*!< (@ 0x0000000F) Indicates read fsm is done. After this read data + is available in EFUSE_READ_DATA_REGISTER + bits 7:0 */ + __IM uint32_t RESERVED2 : 16; /*!< (@ 0x00000010) reserved2 */ + } EFUSE_READ_DATA_REG_b; + }; + + union { + __IM uint32_t EFUSE_STATUS_REG; /*!< (@ 0x00000018) Read address Register */ + + struct { + __IM uint32_t EFUSE_ENABLED : 1; /*!< (@ 0x00000000) This bit specifies whether the EFUSE is enabled + or not */ + __IM uint32_t RESERVED1 : 1; /*!< (@ 0x00000001) reserved1 */ + __IM uint32_t EFUSE_DOUT_SYNC : 8; /*!< (@ 0x00000002) This bit specifies the 8-bit data read out from + the EFUSE macro. This is synchronized with + pclk */ + __IM uint32_t RESERVED2 : 6; /*!< (@ 0x0000000A) reserved2 */ + __IM uint32_t RESERVED3 : 16; /*!< (@ 0x00000010) reserved3 */ + } EFUSE_STATUS_REG_b; + }; + + union { + __IOM uint32_t + EFUSE_RD_TMNG_PARAM_REG; /*!< (@ 0x0000001C) none */ + + struct { + __IOM uint32_t TSUR_CS : 4; /*!< (@ 0x00000000) CSB to STROBE setup time into read mode */ + __IOM uint32_t TSQ : 4; /*!< (@ 0x00000004) Q7-Q0 access time from STROBE rising edge */ + __IOM uint32_t THRA : 4; /*!< (@ 0x00000008) for 32x8 macro: A4 A0 to STROBE hold time into + Read mode 5122x8 macro: A8 A0 to STROBE + hold time into Read mode */ + __IM uint32_t RESERVED1 : 4; /*!< (@ 0x0000000C) reserved1 */ + __IM uint32_t RESERVED2 : 16; /*!< (@ 0x00000010) reserved2 */ + } EFUSE_RD_TMNG_PARAM_REG_b; + }; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t + EFUSE_MEM_MAP_LENGTH_REG; /*!< (@ 0x00000024) none */ + + struct { + __IOM uint32_t + EFUSE_MEM_MAP_LEN : 1; /*!< (@ 0x00000000) 0: 8 bit read 1: 16 bit read */ + __IM uint32_t RESERVED1 : 15; /*!< (@ 0x00000001) reserved1 */ + __IM uint32_t RESERVED2 : 16; /*!< (@ 0x00000010) reserved2 */ + } EFUSE_MEM_MAP_LENGTH_REG_b; + }; + + union { + __IOM uint32_t + EFUSE_READ_BLOCK_STARTING_LOCATION; /*!< (@ 0x00000028) Starting address from which the read has to be + blocked. Once the end address is written, + it cannot be changed till power on reset + is given */ + + struct { + __IOM uint32_t + EFUSE_READ_BLOCK_STARTING_LOCATION : 16; /*!< (@ 0x00000000) Starting address from which the read has to be + blocked. Once the end address is written, + it cannot be changed till power on reset + is given. */ + __IM uint32_t RESERVED1 : 16; /*!< (@ 0x00000010) reserved1 */ + } EFUSE_READ_BLOCK_STARTING_LOCATION_b; + }; + + union { + __IOM uint32_t EFUSE_READ_BLOCK_END_LOCATION; /*!< (@ 0x0000002C) Starting address from which the read has to be + blocked. Once the end address is written, + it cannot be changed till power on reset + is given */ + + struct { + __IOM uint32_t + EFUSE_READ_BLOCK_END_LOCATION : 16; /*!< (@ 0x00000000) End address till which the read has to be blocked. + Once the end address is written , it cannot + be changed till power on reset is given. */ + __IM uint32_t RESERVED1 : 16; /*!< (@ 0x00000010) reserved1 */ + } EFUSE_READ_BLOCK_END_LOCATION_b; + }; + + union { + __IOM uint32_t EFUSE_READ_BLOCK_ENABLE_REG; /*!< (@ 0x00000030) The Transmit Poll Demand register enables the + Transmit DMA to check whether or not the + current descriptor is owned by DMA */ + + struct { + __IOM uint32_t + efuse_read_block_enable : 1; /*!< (@ 0x00000000) Enable for blocking the read access from a programmable + memory location */ + __IM uint32_t RESERVED1 : 15; /*!< (@ 0x00000001) reserved1 */ + __IM uint32_t RESERVED2 : 16; /*!< (@ 0x00000010) reserved2 */ + } EFUSE_READ_BLOCK_ENABLE_REG_b; + }; + + union { + __IOM uint32_t + EFUSE_DA_CLR_STROBE_REG; /*!< (@ 0x00000034) none */ + + struct { + __IOM uint32_t EFUSE_STROBE_CLR_CNT : 9; /*!< (@ 0x00000000) Strobe signal Clear count in direct access mode. + value depends on APB clock frequency of + eFuse controller */ + __IOM uint32_t + EFUSE_STROBE_ENABLE : 1; /*!< (@ 0x00000009) none */ + __IM uint32_t RESERVED1 : 6; /*!< (@ 0x0000000A) reserved1 */ + __IM uint32_t RESERVED2 : 16; /*!< (@ 0x00000010) reserved2 */ + } EFUSE_DA_CLR_STROBE_REG_b; + }; +} EFUSE_Type; + +/* =========================================================================================================================== */ +/* ================ CCI ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CCI module helps external memories and peripherals to communicate with internal AHB bus with less number of pins (CCI) + */ + +typedef struct { /*!< (@ 0x46170000) CCI Structure */ + + union { + __IOM uint32_t CCI_CONTROL; /*!< (@ 0x00000000) CCI control register */ + + struct { + __IOM uint32_t NUM_SLAVES : 2; /*!< (@ 0x00000000) Indicates the number of slaves */ + __IOM uint32_t + ENABLED_SLAVES : 3; /*!< (@ 0x00000002) Indicates Slaves enable. */ + __IOM uint32_t EBT_S : 1; /*!< (@ 0x00000005) Support for Early Burst Termination */ + __IOM uint32_t ADDR_WIDTH_CONFIG : 2; /*!< (@ 0x00000006) address width configuration of AHB slave during + address phase */ + __IOM uint32_t + TRANSLATE_ENABLE : 1; /*!< (@ 0x00000008) translation enable */ + __IOM uint32_t MODE : 3; /*!< (@ 0x00000009) This bit represents mode of the interface */ + __IOM uint32_t RESERVED1 : 1; /*!< (@ 0x0000000C) reserved1 */ + __IOM uint32_t + SLAVE_PRIORITY : 3; /*!< (@ 0x0000000D) This bits will represents priority of the slaves */ + __IOM uint32_t + TIME_OUT_PRG : 10; /*!< (@ 0x00000010) configurable time out value for slave response. */ + __IOM uint32_t RESERVED2 : 3; /*!< (@ 0x0000001A) reserved2 */ + __IOM uint32_t + DISABLE_TIME_OUT_FOR_DATA_ACCESS : 1; /*!< (@ 0x0000001D) configurable time out value for slave response. */ + __IOM uint32_t + SELECT_TIME_OUT_INTR_OR_MSG_INTR : 1; /*!< (@ 0x0000001E) configurable time out value for slave response. */ + __IOM uint32_t + CCI_CTRL_ENABLE : 1; /*!< (@ 0x0000001F) configurable time out value for slave response. */ + } CCI_CONTROL_b; + }; + + union { + __IOM uint32_t CCI_LSB_A_S1; /*!< (@ 0x00000004) Lower Address of slave 0 supported */ + + struct { + __IOM uint32_t LOWER_ADDRESS : 32; /*!< (@ 0x00000000) Lower Address of slave 0 supported. Make sure + that slave0 is enabled. */ + } CCI_LSB_A_S1_b; + }; + + union { + __IOM uint32_t CCI_LSB_A_S2; /*!< (@ 0x00000008) LOWER Address of slave 0 supported */ + + struct { + __IOM uint32_t LOWER_ADDRESS : 32; /*!< (@ 0x00000000) Lower Address of slave 1 supported. Make sure + that slave1 is enabled. */ + } CCI_LSB_A_S2_b; + }; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t CCI_MSB_A_S1; /*!< (@ 0x00000010) upper Address of slave 0 supported */ + + struct { + __IOM uint32_t HIGHER_ADDRESS : 32; /*!< (@ 0x00000000) Higher Address of slave 0 supported. Make sure + that slave0 is enabled. */ + } CCI_MSB_A_S1_b; + }; + + union { + __IOM uint32_t CCI_MSB_A_S2; /*!< (@ 0x00000014) UPPER Address of slave 0 supported */ + + struct { + __IOM uint32_t HIGHER_ADDRESS : 32; /*!< (@ 0x00000000) Higher Address of slave 1 supported. Make sure + that slave1 is enabled. */ + } CCI_MSB_A_S2_b; + }; + __IM uint32_t RESERVED1[4]; + + union { + __IOM uint32_t + CCI_MODE_INTR_STATUS; /*!< (@ 0x00000028) Interrupt Status */ + + struct { + __IOM uint32_t RESERVED1 : 3; /*!< (@ 0x00000000) Reserved1 */ + __IOM uint32_t INTR_CLEAR : 2; /*!< (@ 0x00000003) By setting this bits will clear the interrupt + status */ + __IOM uint32_t RESERVED2 : 6; /*!< (@ 0x00000005) Reserved2 */ + __IM uint32_t INTR_STATUS : 2; /*!< (@ 0x0000000B) These bits will represents the status of the + interrupt in read mode */ + __IOM uint32_t RESERVED3 : 19; /*!< (@ 0x0000000D) RESER */ + } CCI_MODE_INTR_STATUS_b; + }; + __IM uint32_t RESERVED2[117]; + + union { + __IOM uint32_t + CCI_FIFO_THRESHOLD_REG; /*!< (@ 0x00000200) CCI fifo threshold */ + + struct { + __IOM uint32_t + FIFO_AFULL_THRESHOLD : 5; /*!< (@ 0x00000000) ALMOST full threshold */ + __IOM uint32_t + FIFO_AEMPTY_THRESHOLD : 5; /*!< (@ 0x00000005) ALMOST empty threshold */ + __IOM uint32_t RESERVED1 : 22; /*!< (@ 0x0000000A) RESERVED1 */ + } CCI_FIFO_THRESHOLD_REG_b; + }; + + union { + __IOM uint32_t CCI_TRANS_ADDRESS; /*!< (@ 0x00000204) cci trans address */ + + struct { + __IOM uint32_t + TRANSLATION_ADDRESS_VALID : 1; /*!< (@ 0x00000000) Translation is enabled or not */ + __IOM uint32_t + TRANSLATION_ADDRESS : 31; /*!< (@ 0x00000001) Address offset for translation address */ + } CCI_TRANS_ADDRESS_b; + }; + + union { + __IOM uint32_t CCI_PREFETCH_CTRL; /*!< (@ 0x00000208) CCI prefetch control register */ + + struct { + __IOM uint32_t + CCI_PREFETCH_EN : 1; /*!< (@ 0x00000000) cci pre-fetch enables on AHB read operation. */ + __IOM uint32_t + CCI_2X_CLK_ENABLE_FOR_DDR_MODE : 1; /*!< (@ 0x00000001) It is an enable for CCI 2x clock in DDR mode */ + __IOM uint32_t RESERVED1 : 30; /*!< (@ 0x00000002) Reserved1 */ + } CCI_PREFETCH_CTRL_b; + }; +} CCI_Type; /*!< Size = 524 (0x20c) */ + +/* ================================================================================ */ +/* ================ I2S0 ================ */ +/* ================================================================================ */ + +/** + * @brief I2S(Inter-IC Sound) is transferring two-channel digital audio data from one IC device to another (I2S0) + */ +typedef struct { + union { + union { + __IM uint32_t I2S_LRBR; /*!< (@ 0x00000000) Left Receive Buffer Register */ + + struct { + __IM uint32_t LRBR : 24; /*!< (@ 0x00000000) Data received serially from the received channel + input */ + __IM uint32_t RESERVED1 : 8; /*!< (@ 0x00000018) Reserved for future use */ + } I2S_LRBR_b; + }; + + union { + __OM uint32_t I2S_LTHR; /*!< (@ 0x00000000) Left Receive Buffer Register */ + + struct { + __OM uint32_t LTHR : 24; /*!< (@ 0x00000000) The Left Stereo Data to be transmitted serially + from the Transmitted channel output */ + __OM uint32_t RESERVED1 : 8; /*!< (@ 0x00000018) Reserved for future use */ + } I2S_LTHR_b; + }; + }; + + union { + union { + __IM uint32_t I2S_RRBR; /*!< (@ 0x00000004) Right Receive Buffer Register */ + + struct { + __IM uint32_t RRBR : 24; /*!< (@ 0x00000000) The Right Stereo Data received serially from + the received channel input through this + register */ + __IM uint32_t RESERVED1 : 8; /*!< (@ 0x00000018) Reserved for future use */ + } I2S_RRBR_b; + }; + + union { + __OM uint32_t I2S_RTHR; /*!< (@ 0x00000004) Right Transmit Holding Register */ + + struct { + __OM uint32_t RTHR : 24; /*!< (@ 0x00000000) The Right Stereo Data to be transmitted serially + from the Transmit channel output written + through this register */ + __OM uint32_t RESERVED1 : 8; /*!< (@ 0x00000018) Reserved for future use */ + } I2S_RTHR_b; + }; + }; + + union { + __IOM uint32_t I2S_RER; /*!< (@ 0x00000008) Receive Enable Register */ + + struct { + __IOM uint32_t RXCHEN : 1; /*!< (@ 0x00000000) This Bit enables/disables a receive channel independently + of all other channels */ + __IOM uint32_t RESERVED1 : 31; /*!< (@ 0x00000001) Reserved for future use */ + } I2S_RER_b; + }; + + union { + __IOM uint32_t I2S_TER; /*!< (@ 0x0000000C) Transmit Enable Register */ + + struct { + __IOM uint32_t TXCHEN : 1; /*!< (@ 0x00000000) This Bit enables/disables a transmit channel + independently of all other channels */ + __IOM uint32_t RESERVED1 : 31; /*!< (@ 0x00000001) Reserved for future use */ + } I2S_TER_b; + }; + + union { + __IOM uint32_t I2S_RCR; /*!< (@ 0x00000010) Receive Configuration Register */ + + struct { + __IOM uint32_t WLEN : 3; /*!< (@ 0x00000000) This Bits are used to program the desired data + resolution of the receiver and enables + LSB of the incoming left or right word */ + __IOM uint32_t RESERVED1 : 29; /*!< (@ 0x00000003) Reserved for future use */ + } I2S_RCR_b; + }; + + union { + __IOM uint32_t I2S_TCR; /*!< (@ 0x00000014) Transmit Configuration Register */ + + struct { + __IOM uint32_t WLEN : 3; /*!< (@ 0x00000000) This Bits are used to program the desired data + resolution of the transmitter and ensure + that MSB of the data is transmitted first. */ + __IOM uint32_t RESERVED1 : 29; /*!< (@ 0x00000003) Reserved for future use */ + } I2S_TCR_b; + }; + + union { + __IM uint32_t I2S_ISR; /*!< (@ 0x00000018) Interrupt Status Register */ + + struct { + __IM uint32_t RXDA : 1; /*!< (@ 0x00000000) Receive Data Available */ + __IM uint32_t RXFO : 1; /*!< (@ 0x00000001) Receive Data FIFO */ + __IM uint32_t RESERVED1 : 2; /*!< (@ 0x00000002) Reserved for future use */ + __IM uint32_t TXFE : 1; /*!< (@ 0x00000004) Transmit FIFO Empty */ + __IM uint32_t TXFO : 1; /*!< (@ 0x00000005) Transmit FIFO */ + __IM uint32_t RESERVED2 : 26; /*!< (@ 0x00000006) Reserved for future use */ + } I2S_ISR_b; + }; + + union { + __IOM uint32_t I2S_IMR; /*!< (@ 0x0000001C) Interrupt Mask Register */ + + struct { + __IOM uint32_t RXDAM : 1; /*!< (@ 0x00000000) RX Data Available Mask Interrupt */ + __IOM uint32_t RXFOM : 1; /*!< (@ 0x00000001) RX FIFO Overrun Mask Interrupt */ + __IOM uint32_t RESERVED1 : 2; /*!< (@ 0x00000002) Reserved for future use */ + __IOM uint32_t TXFEM : 1; /*!< (@ 0x00000004) TX FIFO Empty Interrupt */ + __IOM uint32_t TXFOM : 1; /*!< (@ 0x00000005) TX FIFO Overrun Interrupt */ + __IOM uint32_t RESERVED2 : 26; /*!< (@ 0x00000006) Reserved for future use */ + } I2S_IMR_b; + }; + + union { + __IM uint32_t I2S_ROR; /*!< (@ 0x00000020) Receive Overrun Register */ + + struct { + __IM uint32_t RXCHO : 1; /*!< (@ 0x00000000) Read this bit to clear the RX FIFO data overrun + interrupt */ + __IM uint32_t RESERVED1 : 31; /*!< (@ 0x00000001) Reserved for future use */ + } I2S_ROR_b; + }; + + union { + __IM uint32_t I2S_TOR; /*!< (@ 0x00000024) Transmit Overrun Register */ + + struct { + __IM uint32_t TXCHO : 1; /*!< (@ 0x00000000) Read this bit to clear the TX FIFO data overrun + interrupt */ + __IM uint32_t RESERVED1 : 31; /*!< (@ 0x00000001) Reserved for future use */ + } I2S_TOR_b; + }; + + union { + __IOM uint32_t I2S_RFCR; /*!< (@ 0x00000028) Receive FIFO Configuration Register0 */ + + struct { + __IOM uint32_t RXCHDT : 4; /*!< (@ 0x00000000) This bits program the trigger level in the RX + FIFO at which the data available interrupt + is generated */ + __IOM uint32_t RESERVED1 : 28; /*!< (@ 0x00000004) Reserved for future use */ + } I2S_RFCR_b; + }; + + union { + __IOM uint32_t I2S_TXFCR; /*!< (@ 0x0000002C) Transmit FIFO Configuration Register */ + + struct { + __IOM uint32_t TXCHET : 4; /*!< (@ 0x00000000) This bits program the trigger level in the TX + FIFO at which the Empty Threshold Reached + interrupt is generated */ + __IM uint32_t RESERVED1 : 28; /*!< (@ 0x00000004) Reserved for future use */ + } I2S_TXFCR_b; + }; + + union { + __OM uint32_t I2S_RFF; /*!< (@ 0x00000030) Receive FIFO Flush */ + + struct { + __OM uint32_t RXCHFR : 1; /*!< (@ 0x00000000) Writing a 1 to this register flushes an individual + RX FIFO RX channel or block must be disable + prior to writing to this bit */ + __OM uint32_t RESERVED1 : 31; /*!< (@ 0x00000001) Reserved for future use */ + } I2S_RFF_b; + }; + + union { + __OM uint32_t I2S_TFF; /*!< (@ 0x00000034) Transmit FIFO Flush */ + + struct { + __OM uint32_t TXCHFR : 1; /*!< (@ 0x00000000) Writing a 1 to this register flushes an individual + TX FIFO TX channel or block must be disable + prior to writing to this bit */ + __OM uint32_t RESERVED1 : 31; /*!< (@ 0x00000001) Reserved for future use */ + } I2S_TFF_b; + }; + __IM uint32_t RSVD0; /*!< (@ 0x00000038) none */ + __IM uint32_t RSVD1; /*!< (@ 0x0000003C) none */ +} I2S0_CHANNEL_CONFIG_Type; + +typedef struct { /*!< (@ 0x47050000) I2S0 Structure */ + + union { + __IOM uint32_t I2S_IER; /*!< (@ 0x00000000) I2S Enable Register */ + + struct { + __IOM uint32_t IEN : 1; /*!< (@ 0x00000000) Inter Block Enable */ + __IOM uint32_t RESERVED1 : 31; /*!< (@ 0x00000001) Reserved for future use */ + } I2S_IER_b; + }; + + union { + __IOM uint32_t I2S_IRER; /*!< (@ 0x00000004) I2S Receiver Block Enable Register */ + + struct { + __IOM uint32_t RXEN : 1; /*!< (@ 0x00000000) Receive Block Enable, Bit Overrides any Individual + Receive Channel Enables */ + __IOM uint32_t RESERVED1 : 31; /*!< (@ 0x00000001) Reserved for future use */ + } I2S_IRER_b; + }; + + union { + __IOM uint32_t I2S_ITER; /*!< (@ 0x00000008) Transmitter Block Enable */ + + struct { + __IOM uint32_t TXEN : 1; /*!< (@ 0x00000000) Transmitter Block Enable, Bit Overrides any Individual + Transmit Channel Enables */ + __IOM uint32_t RESERVED1 : 31; /*!< (@ 0x00000001) Reserved for future use */ + } I2S_ITER_b; + }; + + union { + __IOM uint32_t I2S_CER; /*!< (@ 0x0000000C) Clock Enable Register */ + + struct { + __IOM uint32_t CLKEN : 1; /*!< (@ 0x00000000) Clock generation enable/disable */ + __IOM uint32_t RESERVED1 : 31; /*!< (@ 0x00000001) Reserved for future use */ + } I2S_CER_b; + }; + + union { + __IOM uint32_t I2S_CCR; /*!< (@ 0x00000010) Clock Configuration Register */ + + struct { + __IOM uint32_t SCLKG : 3; /*!< (@ 0x00000000) These bits are used to program the gating of + sclk */ + __IOM uint32_t WSS : 2; /*!< (@ 0x00000003) These bits are used to program the number of + sclk cycles */ + __IOM uint32_t RESERVED1 : 27; /*!< (@ 0x00000005) Reserved for future use */ + } I2S_CCR_b; + }; + + union { + __OM uint32_t I2S_RXFFR; /*!< (@ 0x00000014) Receiver Block FIFO Reset Register */ + + struct { + __OM uint32_t RXFFR : 1; /*!< (@ 0x00000000) Writing a 1 To This Register Flushes All The + RX FIFO's Receiver Block Must be Disable + Prior to Writing This Bit */ + __OM uint32_t RESERVED1 : 31; /*!< (@ 0x00000001) Reserved for future use */ + } I2S_RXFFR_b; + }; + + union { + __OM uint32_t I2S_TXFFR; /*!< (@ 0x00000018) Transmitter Block FIFO Reset Register */ + + struct { + __OM uint32_t TXFFR : 1; /*!< (@ 0x00000000) Writing a 1 To This Register Flushes All The + RX FIFO's Receiver Block Must be Disable + Prior to Writing This Bit */ + __OM uint32_t RESERVED1 : 31; /*!< (@ 0x00000001) Reserved for future use */ + } I2S_TXFFR_b; + }; + __IM uint32_t RESERVED; + __IOM I2S0_CHANNEL_CONFIG_Type + CHANNEL_CONFIG[4]; /*!< (@ 0x00000020) [0..3] */ + __IM uint32_t RESERVED1[40]; + + union { + __IM uint32_t I2S_RXDMA; /*!< (@ 0x000001C0) Receiver Block DMA Register */ + + struct { + __IM uint32_t RXDMA : 32; /*!< (@ 0x00000000) Used to cycle repeatedly through the enabled + receive channels Reading stereo data pairs */ + } I2S_RXDMA_b; + }; + + union { + __OM uint32_t I2S_RRXDMA; /*!< (@ 0x000001C4) Reset Receiver Block DMA Register */ + + struct { + __OM uint32_t RRXDMA : 1; /*!< (@ 0x00000000) Writing a 1 to this self-clearing register resets + the RXDMA register */ + __OM uint32_t RESERVED1 : 31; /*!< (@ 0x00000001) Reserved for future use */ + } I2S_RRXDMA_b; + }; + + union { + __OM uint32_t I2S_TXDMA; /*!< (@ 0x000001C8) Transmitter Block DMA Register */ + + struct { + __OM uint32_t TXDMA : 32; /*!< (@ 0x00000000) Used to cycle repeatedly through the enabled + transmit channels allow to writing of stereo + data pairs */ + } I2S_TXDMA_b; + }; + + union { + __OM uint32_t I2S_RTXDMA; /*!< (@ 0x000001CC) Reset Transmitter Block DMA Register */ + + struct { + __OM uint32_t RTXDMA : 1; /*!< (@ 0x00000000) Writing a 1 to this self-clearing register resets + the TXDMA register */ + __OM uint32_t RESERVED1 : 31; /*!< (@ 0x00000001) Reserved1 */ + } I2S_RTXDMA_b; + }; + __IM uint32_t RESERVED2[8]; + + union { + __IM uint32_t I2S_COMP_PARAM_2; /*!< (@ 0x000001F0) Component Parameter 2 Register */ + + struct { + __IM uint32_t I2S_RX_WORDSIZE_0 : 3; /*!< (@ 0x00000000) On Read returns the value of word size of receiver + channel 0 */ + __IM uint32_t I2S_RX_WORDSIZE_1 : 3; /*!< (@ 0x00000003) On Read returns the value of word size of receiver + channel 1 */ + __IM uint32_t RESERVED1 : 26; /*!< (@ 0x00000006) Reserved1 */ + } I2S_COMP_PARAM_2_b; + }; + + union { + __IM uint32_t I2S_COMP_PARAM_1; /*!< (@ 0x000001F4) Component Parameter 1 Register */ + + struct { + __IM uint32_t + APB_DATA_WIDTH : 2; /*!< (@ 0x00000000) Width of APB data bus */ + __IM uint32_t + I2S_FIFO_DEPTH_GLOBAL : 2; /*!< (@ 0x00000002) Determines FIFO depth for all channels */ + __IM uint32_t I2S_FIFO_MODE_EN : 1; /*!< (@ 0x00000004) Determines whether component act as Master or + Slave */ + __IM uint32_t + I2S_TRANSMITTER_BLOCK : 1; /*!< (@ 0x00000005) Shows the presence of the transmitter block */ + __IM uint32_t + I2S_RECEIVER_BLOCK : 1; /*!< (@ 0x00000006) Shows the presence of the receiver block */ + __IM uint32_t + I2S_RX_CHANNELS : 2; /*!< (@ 0x00000007) Returns the number of receiver channels */ + __IM uint32_t + I2S_TX_CHANNELS : 2; /*!< (@ 0x00000009) Returns the number of transmitter channels */ + __IM uint32_t RESERVED1 : 5; /*!< (@ 0x0000000B) Reserved1 */ + __IM uint32_t I2S_TX_WORDSIZE_0 : 3; /*!< (@ 0x00000010) Returns the value of word size of transmitter + channel 0 */ + __IM uint32_t I2S_TX_WORDSIZE_1 : 3; /*!< (@ 0x00000013) Returns the value of word size of transmitter + channel 1 */ + __IM uint32_t RESERVED2 : 10; /*!< (@ 0x00000016) Reserved2 */ + } I2S_COMP_PARAM_1_b; + }; + + union { + __IM uint32_t + I2S_COMP_VERSION_REG; /*!< (@ 0x000001F8) Component Version ID */ + + struct { + __IM uint32_t + I2S_COMP_VERSION : 32; /*!< (@ 0x00000000) Return the component version(1.02) */ + } I2S_COMP_VERSION_REG_b; + }; + + union { + __IM uint32_t I2S_COMP_TYPE_REG; /*!< (@ 0x000001FC) Component Type */ + + struct { + __IM uint32_t + I2S_COMP_TYPE : 32; /*!< (@ 0x00000000) Return the component type */ + } I2S_COMP_TYPE_REG_b; + }; +} I2S0_Type; +/* ================================================================================ */ +/* ================ IID_AES ================ */ +/* ================================================================================ */ + +/** + * @brief The AES module provides AES encoding and decoding functionality. It can be used in a microprocessor based environment (IID_AES) + */ + +typedef struct { /*!< IID_AES Structure */ + + union { + __IO uint32_t AES_KCR; /*!< AES Key Control register */ + + struct { + __IO uint32_t AES_KEY_CHNG_REQ : 1; /*!< Programming 1 clears the current key and starts a request a + for a new keyAuto-reverts to 0 as soon as the request is accepted + */ + __IO uint32_t AES_KEY_SIZE : 1; /*!< Size of the AES key 0: 128-bit 1: 256-bit */ + uint32_t : 5; + __IO uint32_t AES_KEY_SRC : 1; /*!< Source of the AES key 0: Interface 1: Register */ + } AES_KCR_b; /*!< BitSize */ + }; + + union { + __IO uint32_t AES_MODE_REG; /*!< AES Mode register */ + + struct { + __IO uint32_t AES_MODE : 8; /*!< The AES Mode register defines which mode of AES is used. */ + } AES_MODE_REG_b; /*!< BitSize */ + }; + + union { + __IO uint32_t AES_ACT_REG; /*!< AES Action register */ + + struct { + __IO uint32_t AES_ACTION : 2; /*!< The AES Mode register defines which mode of AES is used. */ + } AES_ACT_REG_b; /*!< BitSize */ + }; + __I uint32_t RESERVED[5]; + + union { + __I uint32_t AES_SR_REG; /*!< AES Status register */ + + struct { + __I uint32_t AES_BUSY : 1; /*!< Indicates that the AES core is processing data */ + uint32_t : 1; + __I uint32_t AES_CLEAR_DONE : 1; /*!< Indicates that the Clear action is finished */ + __I uint32_t AES_KEY_PRESENT : 1; /*!< Indicates that the Clear action is finished */ + uint32_t : 1; + __I uint32_t AES_KEY_REQ : 1; /*!< Indicates that a key must be provided */ + __I uint32_t AES_DATA_REQ : 1; /*!< Indicates that data must be provided */ + __I uint32_t AES_DATA_AV : 1; /*!< Indicates that data is available */ + } AES_SR_REG_b; /*!< BitSize */ + }; + __I uint32_t RESERVED1[7]; + + union { + __O uint32_t AES_KEY_REG; /*!< The AES Key register is used to program a key into the AES module. */ + + struct { + __O uint32_t AES_KEY : 32; /*!< 4 writes of 32 bits make up the 128-bit key for AES, 8 writes + make up the 256-bit key */ + } AES_KEY_REG_b; /*!< BitSize */ + }; + + union { + __O uint32_t AES_DIN_REG; /*!< AES Data In register */ + + struct { + __O uint32_t AES_DIN : 32; /*!< Data for encoding or decoding, 4 writes of 32 bits make up a + 128-bit data word */ + } AES_DIN_REG_b; /*!< BitSize */ + }; + + union { + __I uint32_t AES_DOUT_REG; /*!< AES Data out register */ + + struct { + __I uint32_t AES_DOUT : 32; /*!< Result from encoding or decoding, 4 reads of 32 bits make up + a 128-bit data word */ + } AES_DOUT_REG_b; /*!< BitSize */ + }; + __I uint32_t RESERVED2[36]; + + union { + union { + __O uint32_t AES_IF_SR_C_REG; /*!< AES Interface Status Clear register */ + + struct { + __O uint32_t IFB_ERROR : 1; /*!< Clears the if_error bit */ + } AES_IF_SR_C_REG_b; /*!< BitSize */ + }; + + union { + __I uint32_t AES_IF_SR_REG; /*!< AES Interface Status register */ + + struct { + __I uint32_t IF_ERROR : 1; /*!< Indicates that an interface error has occurred */ + } AES_IF_SR_REG_b; /*!< BitSize */ + }; + }; + + union { + __IO uint32_t AES_TEST_REG; /*!< AES Test register */ + + struct { + __IO uint32_t AES_BIST_ENABLE : 1; /*!< Isolates the iid_aes module and runs a BIST */ + uint32_t : 3; + __IO uint32_t AES_BIST_RUNNING : 1; /*!< BIST is in progress or finishing up */ + __IO uint32_t AES_BIST_ACTIVE : 1; /*!< Indicates that the BIST is running */ + __IO uint32_t AES_BIST_OK : 1; /*!< Indicates that the BIST has passed */ + __IO uint32_t AES_BIST_ERROR : 1; /*!< Indicates that the BIST has failed */ + } AES_TEST_REG_b; /*!< BitSize */ + }; + __I uint32_t RESERVED3[6]; + + union { + __I uint32_t AES_VER_REG; /*!< AES Version register */ + + struct { + __I uint32_t AES_VERSION : 32; /*!< Version of iid_aes */ + } AES_VER_REG_b; /*!< BitSize */ + }; +} IID_AES_Type; + +/* ================================================================================ */ +/* ================ IID_QK ================ */ +/* ================================================================================ */ + +/** + * @brief The purpose of Quiddikey is to provide secure key storage without storing the key. (IID_QK) + */ + +typedef struct { /*!< IID_QK Structure */ + + union { + __O uint32_t QK_CR_REG; /*!< Quiddikey Control register.The Quiddikey Control register defines + which command must be executed next. */ + + struct { + __O uint32_t QK_ZEROIZE : 1; /*!< Begin Zeroize operation and go to Error state */ + __O uint32_t QK_ENROLL : 1; /*!< Begin Enroll operation */ + __O uint32_t QK_START : 1; /*!< Begin Start operation */ + __O uint32_t QK_SET_IK : 1; /*!< Begin Set Intrinsic Key operation */ + __O uint32_t QK_SET_UK : 1; /*!< Begin Set User Key operation */ + __O uint32_t QK_SET_XK : 1; /*!< Begin Set External Key operation */ + __O uint32_t QK_GET_KEY : 1; /*!< Begin Get Key operation */ + } QK_CR_REG_b; /*!< BitSize */ + }; + + union { + __IO uint32_t QK_KIDX_REG; /*!< The Quiddikey Key Index register defines the key index for the + next set_key command */ + + struct { + __IO uint32_t QK_KEY_INDEX : 4; /*!< Key index for Set Key operations */ + } QK_KIDX_REG_b; /*!< BitSize */ + }; + + union { + __IO uint32_t QK_KSZ_REG; /*!< Quiddikey Key Size register */ + + struct { + __IO uint32_t QK_KEY_SIZE : 6; /*!< Key size for Set Key operations */ + } QK_KSZ_REG_b; /*!< BitSize */ + }; + + union { + __IO uint32_t QK_KT_REG; /*!< Quiddikey Key Size register */ + + struct { + __IO uint32_t QK_KEY_TARGET : 1; /*!< Target of reconstructed key */ + } QK_KT_REG_b; /*!< BitSize */ + }; + __I uint32_t RESERVED[4]; + + union { + __I uint32_t QK_SR_REG; /*!< Quiddikey Status register */ + + struct { + __I uint32_t QK_BUSY : 1; /*!< Indicates that operation is in progress */ + __I uint32_t QK_OK : 1; /*!< Last operation was successful */ + __I uint32_t QK_ERROR : 1; /*!< Quiddikey is in the Error state and no operations can be performed + */ + __I uint32_t QK_XO_AV : 1; /*!< Next part of XKPD is available */ + __I uint32_t QK_KI_REQ : 1; /*!< Request for next part of key */ + __I uint32_t QK_KO_AV : 1; /*!< Next part of key is available */ + __I uint32_t QK_CI_REQ : 1; /*!< Request for next part of AC/KC */ + __I uint32_t QK_CO_AV : 1; /*!< Next part of AC/KC is available */ + } QK_SR_REG_b; /*!< BitSize */ + }; + __I uint32_t RESERVED1; + + union { + __I uint32_t QK_AR_REG; /*!< Quiddikey allow register */ + + struct { + __I uint32_t QK_ALLOW_ENROLL : 1; /*!< Enroll operation is allowed */ + __I uint32_t QK_ALLOW_START : 1; /*!< Start operation is allowed */ + __I uint32_t QK_ALLOW_SET_KEY : 1; /*!< Set Key operations are allowed */ + __I uint32_t QK_ALLOW_GET_KEY : 1; /*!< Get Key operation is allowed */ + uint32_t : 3; + __I uint32_t QK_ALLOW_BIST : 1; /*!< BIST is allowed to be started */ + } QK_AR_REG_b; /*!< BitSize */ + }; + __I uint32_t RESERVED2[5]; + + union { + __O uint32_t QK_KI_REG; /*!< Quiddikey Key Input register */ + + struct { + __IO uint32_t QK_KI : 32; /*!< Key input data */ + } QK_KI_REG_b; /*!< BitSize */ + }; + + union { + __O uint32_t QK_CI_REG; /*!< Quiddikey Code Input register */ + + struct { + __IO uint32_t QK_CI : 32; /*!< AC/KC input data */ + } QK_CI_REG_b; /*!< BitSize */ + }; + + union { + __I uint32_t QK_CO_REG; /*!< Quiddikey Code Output register */ + + struct { + __I uint32_t QK_CO : 32; /*!< AC/KC output data */ + } QK_CO_REG_b; /*!< BitSize */ + }; + + union { + __I uint32_t QK_XO_REG; /*!< Quiddikey XKPD Output register */ + + struct { + __I uint32_t QK_XO : 32; /*!< XKPD output data */ + } QK_XO_REG_b; /*!< BitSize */ + }; + __I uint32_t RESERVED3[4]; + + union { + __I uint32_t QK_KO_IDX_REG; /*!< Quiddikey Key Output Index register */ + + struct { + __I uint32_t qk_ko_index : 4; /*!< Key index for the key that is currently output via the Key Output + register */ + } QK_KO_IDX_REG_b; /*!< BitSize */ + }; + + union { + __I uint32_t QK_KO_REG; /*!< Quiddikey Code Output register */ + + struct { + __I uint32_t QK_KO : 32; /*!< Key output data */ + } QK_KO_REG_b; /*!< BitSize */ + }; + __I uint32_t RESERVED4[29]; + + union { + union { + __I uint32_t QK_IF_SR_C_REG; /*!< Quiddikey Interface Status register */ + + struct { + __I uint32_t IF_ERROR : 1; /*!< Clears the if_error bit */ + } QK_IF_SR_C_REG_b; /*!< BitSize */ + }; + + union { + __I uint32_t QK_IF_SR_REG; /*!< Quiddikey Interface Status register */ + + struct { + __I uint32_t IF_ERROR : 1; /*!< Indicates that an interface error has occurred */ + } QK_IF_SR_REG_b; /*!< BitSize */ + }; + }; + + union { + __IO uint32_t QK_TEST_REG; /*!< QK Test register */ + + struct { + __IO uint32_t QK_BIST_ENABLE : 1; /*!< Isolates the iid_quiddikey module and runs a BIST */ + uint32_t : 3; + __IO uint32_t QK_BIST_RUNNING : 1; /*!< BIST is in progress or finishing up */ + __IO uint32_t QK_BIST_ACTIVE : 1; /*!< Indicates that the BIST is running */ + __IO uint32_t QK_BIST_OK : 1; /*!< Indicates that the BIST has passed */ + __IO uint32_t QK_BIST_ERROR : 1; /*!< Indicates that the BIST has failed */ + } QK_TEST_REG_b; /*!< BitSize */ + }; + __I uint32_t RESERVED5[6]; + + union { + __I uint32_t QK_VER_REG; /*!< QK Version register */ + + struct { + __I uint32_t QK_VERSION : 32; /*!< Version of iid_qk */ + } QK_VER_REG_b; /*!< BitSize */ + }; +} IID_QK_Type; + +/* ================================================================================ */ +/* ================ IID_RPINE ================ */ +/* ================================================================================ */ + +/** + * @brief none (IID_RPINE) + */ + +typedef struct { /*!< IID_RPINE Structure */ + + union { + __IO uint32_t IID_BIST_CTRL_REG; /*!< Quiddikey Control register.The Quiddikey Control register defines + which command must be executed next. */ + + struct { + __IO uint32_t QK_BIST_ENABLE : 1; /*!< none */ + __IO uint32_t AES_BIST_ENABLE : 1; /*!< none */ + __IO uint32_t KH_BIST_ENABLE : 1; /*!< none */ + } IID_BIST_CTRL_REG_b; /*!< BitSize */ + }; + + union { + __IO uint32_t IID_BIST_STATUS_REG; /*!< none */ + + struct { + __IO uint32_t QK_BIST_ACTIVE : 1; /*!< none */ + __IO uint32_t QK_BIST_ERROR : 1; /*!< Indicates that the BIST has failed */ + __IO uint32_t QK_BIST_OK : 1; /*!< Indicates that the BIST has passed */ + __IO uint32_t QK_BIST_RUNNING : 1; /*!< Indicates that the BIST is running */ + __IO uint32_t AES_BIST_ACTIVE : 1; /*!< none */ + __IO uint32_t AES_BIST_ERROR : 1; /*!< none */ + __IO uint32_t AES_BIST_OK : 1; /*!< Indicates that the BIST has passed */ + __IO uint32_t AES_BIST_RUNNING : 1; /*!< Indicates that the BIST is running */ + __IO uint32_t KH_BIST_STATUS : 1; /*!< none */ + } IID_BIST_STATUS_REG_b; /*!< BitSize */ + }; + + union { + __IO uint32_t IID_CTRL_REG; /*!< none */ + + struct { + __IO uint32_t AES_MAX_KEY_SIZE : 1; /*!< 1 256 bit key, 0 128 bit key */ + __IO uint32_t SOURCE_KEY_KH : 1; /*!< When set KH will source the key to AES engine. When this is + not QK key output is connected to AES key input */ + __IO uint32_t LATCH_KEY_KH : 1; /*!< When set KH will latch the key given by QK. When this is not + QK key output is connected to AES key input */ + __IO uint32_t KH_RESET_N : 1; /*!< 0 KH will be in reset 1 Out of reset */ + __IO uint32_t KH_KEY_SIZE : 1; /*!< 0 128 bit key 1 256 bit key This is used by KH */ + __IO uint32_t KH_CLOCK_RATIO : 3; /*!< Indicates the division factor to be used for generating kh_clk. + */ + } IID_CTRL_REG_b; /*!< BitSize */ + }; + + union { + __IO uint32_t WKE_CTRL_REG; /*!< none */ + + struct { + __IO uint32_t ENABLE_WKE : 1; /*!< When WKE will be enabled. This is a self clearing bit. Once + enabled WKE can not be disabled till process is done */ + __IO uint32_t WKE_KEY_SIZE : 1; /*!< 0 128 bit size 1 256 bit size */ + __IO uint32_t WKE_FLUSH : 1; /*!< When set, WKE will flush out the data from AES. When WEK is + active, firmware reads to AES engine are masked. This gets cleared + once four dwords are read from AES */ + __IO uint32_t WKE_COMPARE : 1; /*!< When set, WKE will compare the data from AES engine with the + data provided by firmware */ + __IO uint32_t WKE_SET_KEY : 1; /*!< This has to be set after key available from AES */ + __IO uint32_t KEY_CODE_DONE : 1; /*!< This has to be set after reading key code */ + } WKE_CTRL_REG_b; /*!< BitSize */ + }; + __I uint32_t RESERVED; + + union { + __IO uint32_t IID_AES_CTRL_REG; /*!< none */ + + struct { + __IO uint32_t KEY_REQ_IN_DMA_PATH : 1; /*!< Include key req in dma path. With this KEY Also can be loaded + using DMA. */ + __IO uint32_t AES_MAX_KEY_SIZE_FRM_REG : 1; /*!< This is valid only when aes_max_key_size_frm_reg_en is set. + */ + __IO uint32_t AES_MAX_KEY_SIZE_FRM_REG_EN : 1; /*!< When set, WKE will flush out the data from AES. When WEK is + active, firmware reads to AES engine are masked. This gets cleared + once four dwords are read from AES */ + __IO uint32_t OTP_KEY_LOADING : 1; /*!< When set, WKE will compare the data from AES engine with the + data provided by firmware */ + } IID_AES_CTRL_REG_b; /*!< BitSize */ + }; + + union { + __I uint32_t IID_AES_STS_REG; /*!< none */ + + struct { + __I uint32_t DIN_FIFO_FULL : 1; /*!< Input data fifo full indication */ + __I uint32_t DOUT_FIFO_EMPTY : 1; /*!< Output data fifo empty indication */ + } IID_AES_STS_REG_b; /*!< BitSize */ + }; + __I uint32_t RESERVED1; + + union { + __IO uint32_t WKE_STATUS_REG; /*!< none */ + + struct { + __IO uint32_t WKE_ACTIVE : 1; /*!< Will be high when WKE is active */ + __IO uint32_t + WKE_KEY_FEED_IN_PROGRESS : 1; /*!< Will be high when WKE is feeding key to AES engine */ + __IO uint32_t + WKE_FLUSH_IN_PROGRESS : 1; /*!< Will be high when WKE flushing out the data from AES */ + __IO uint32_t + WKE_COMPARE_IN_PROGRESS : 1; /*!< Will be high when WKE is comparing the data from AES */ + __IO uint32_t + WKE_SET_KEY_IN_PROGRESS : 1; /*!< Will be high when WKE is doing set key operation with QK */ + __IO uint32_t WKE_KEY_READY : 1; /*!< Firmware has to load the authentication, which will be compared + with AES output, when this bit is low */ + __IO uint32_t WKE_CMP_DATA_READY : 1; /*!< Firmware has to load the authentication, which will be compared + with AES output, when this bit is low */ + __IO uint32_t WKE_COMPARE_FAIL : 1; /*!< This bit will be set when authentication data comparison fails + */ + } WKE_STATUS_REG_b; /*!< BitSize */ + }; + __I uint32_t RESERVED2; + __IO uint32_t WKE_DATA_REG; /*!< none */ +} IID_RPINE_Type; + +/* ================================================================================ */ +/* ================ SCT0 ================ */ +/* ================================================================================ */ + +/** + * @brief Configurable timer is used in counting clocks, events and states with reference clock external clock and system clock (SCT0) + */ + +typedef struct { /*!< (@ 0x45060000) CT0 Structure */ + + union { + __IOM uint32_t + CT_GEN_CTRL_SET_REG; /*!< (@ 0x00000000) General control set register */ + + struct { + __IOM uint32_t COUNTER_IN_32_BIT_MODE : 1; /*!< (@ 0x00000000) Counter_1 and Counter_0 will be merged and used + as a single 32 bit counter */ + __IOM uint32_t + SOFT_RESET_COUNTER_0_FRM_REG : 1; /*!< (@ 0x00000001) This is applied to 32 bits of counter only when + the counter is in 32 bit counter mode otherwise + this will be applied to only lower 16 bits + of counter */ + __IOM uint32_t + PERIODIC_EN_COUNTER_0_FRM_REG : 1; /*!< (@ 0x00000002) This is applied to 32 bits of counter only when + the counter is in 32 bit counter mode otherwise + this will be applied to only lower 16 bits + of counter */ + __IOM uint32_t + COUNTER_0_TRIG_FRM_REG : 1; /*!< (@ 0x00000003) This enables the counter to run/active */ + __IOM uint32_t + COUNTER_0_UP_DOWN : 2; /*!< (@ 0x00000004) This enables the counter to run in up/down/up-down/down-up + directions */ + __IOM uint32_t COUNTER_0_SYNC_TRIG : 1; /*!< (@ 0x00000006) This is applied to 32 bits of counter only when + the counter is in 32 bit counter mode otherwise + this will be applied to only lower 16 bits + of counter. This enables the counter to + run/active when sync is found. */ + __IOM uint32_t BUF_REG_0_EN : 1; /*!< (@ 0x00000007) Buffer register gets enabled for MATCH REG. MATCH_BUF_REG + is always available and whenever this bit + is set only, gets copied to MATCH REG. */ + __IOM uint32_t RESERVED1 : 9; /*!< (@ 0x00000008) Reserved1 */ + __IOM uint32_t + SOFT_RESET_COUNTER_1_FRM_REG : 1; /*!< (@ 0x00000011) This resets the counter on the write */ + __IOM uint32_t + PERIODIC_EN_COUNTER_1_FRM_REG : 1; /*!< (@ 0x00000012) This resets the counter on the write */ + __IOM uint32_t + COUNTER_1_TRIG_FRM : 1; /*!< (@ 0x00000013) This enables the counter to run/active */ + __IOM uint32_t + COUNTER_1_UP_DOWN : 2; /*!< (@ 0x00000014) This enables the counter to run in upward direction */ + __IOM uint32_t COUNTER_1_SYNC_TRIG : 1; /*!< (@ 0x00000016) This is applied to 32 bits of counter only when + the counter is in 32 bit counter mode otherwise + this will be applied to only lower 16 bits + of counter. This enables the counter to + run/active when sync is found. */ + __IOM uint32_t BUF_REG_1_EN : 1; /*!< (@ 0x00000017) Buffer register gets enabled for MATCH REG. MATCH_BUF_REG + is always available and whenever this bit + is set only, gets copied to MATCH REG. */ + __IOM uint32_t RESERVED2 : 8; /*!< (@ 0x00000018) Reserved2 */ + } CT_GEN_CTRL_SET_REG_b; + }; + + union { + __IOM uint32_t + CT_GEN_CTRL_RESET_REG; /*!< (@ 0x00000004) General control reset register */ + + struct { + __IOM uint32_t COUNTER_IN_32_BIT_MODE : 1; /*!< (@ 0x00000000) Counter_1 and Counter_0 will be merged and used + as a single 32 bit counter */ + __IM uint32_t RESERVED1 : 1; /*!< (@ 0x00000001) Reserved1 */ + __IOM uint32_t + PERIODIC_EN_COUNTER_0_FRM_REG : 1; /*!< (@ 0x00000002) This is applied to 32 bits of counter only when + the counter is in 32 bit counter mode otherwise + this will be applied to only lower 16 bits + of counter */ + __IM uint32_t RESERVED2 : 1; /*!< (@ 0x00000003) Reserved2 */ + __IOM uint32_t + COUNTER_0_UP_DOWN : 2; /*!< (@ 0x00000004) This enables the counter to run in up/down/up-down/down-up + directions */ + __IM uint32_t RESERVED3 : 1; /*!< (@ 0x00000006) Reserved3 */ + __IOM uint32_t BUF_REG_0_EN : 1; /*!< (@ 0x00000007) Buffer register gets enabled for MATCH REG. MATCH_BUF_REG + is always available and whenever this bit + is set only, gets copied to MATCH REG. */ + __IM uint32_t RESERVED4 : 9; /*!< (@ 0x00000008) Reserved4 */ + __IM uint32_t RESERVED5 : 1; /*!< (@ 0x00000011) Reserved5 */ + __IOM uint32_t + PERIODIC_EN_COUNTER_1_FRM_REG : 1; /*!< (@ 0x00000012) This resets the counter on the write */ + __IM uint32_t RESERVED6 : 1; /*!< (@ 0x00000013) Reserved6 */ + __IOM uint32_t + COUNTER_1_UP_DOWN : 2; /*!< (@ 0x00000014) This enables the counter to run in upward direction */ + __IM uint32_t RESERVED7 : 1; /*!< (@ 0x00000016) Reserved7 */ + __IOM uint32_t BUF_REG_1_EN : 1; /*!< (@ 0x00000017) Buffer register gets enabled for MATCH REG. MATCH_BUF_REG + is always available and whenever this bit + is set only, gets copied to MATCH REG. */ + __IM uint32_t RESERVED8 : 8; /*!< (@ 0x00000018) Reserved8 */ + } CT_GEN_CTRL_RESET_REG_b; + }; + + union { + __IM uint32_t CT_INTR_STS; /*!< (@ 0x00000008) Interrupt status */ + + struct { + __IM uint32_t INTR_0_L : 1; /*!< (@ 0x00000000) Indicates the FIFO full signal of channel-0 */ + __IM uint32_t FIFO_0_FULL_L : 1; /*!< (@ 0x00000001) Indicates the FIFO full signal of channel-0 */ + __IM uint32_t + COUNTER_0_IS_ZERO_L : 1; /*!< (@ 0x00000002) Counter 0 hit zero in active mode. */ + __IM uint32_t + COUNTER_0_IS_PEAK_L : 1; /*!< (@ 0x00000003) Counter 0 hit peak (MATCH) in active mode. */ + __IM uint32_t RESERVED1 : 12; /*!< (@ 0x00000004) Reserved1 */ + __IM uint32_t INTR_1_L : 1; /*!< (@ 0x00000010) Indicates the FIFO full signal of channel-1 */ + __IM uint32_t FIFO_1_FULL_L : 1; /*!< (@ 0x00000011) Indicates the FIFO full signal of channel-1 */ + __IM uint32_t + COUNTER_1_IS_ZERO_L : 1; /*!< (@ 0x00000012) Counter 1 hit zero in active mode. */ + __IM uint32_t + COUNTER_1_IS_PEAK_L : 1; /*!< (@ 0x00000013) Counter 1 hit peak (MATCH) in active mode. */ + __IM uint32_t RESERVED2 : 12; /*!< (@ 0x00000014) Reserved2 */ + } CT_INTR_STS_b; + }; + + union { + __IOM uint32_t CT_INTR_MASK; /*!< (@ 0x0000000C) Interrupts mask */ + + struct { + __IOM uint32_t INTR_0_L : 1; /*!< (@ 0x00000000) Interrupt mask signal. */ + __IOM uint32_t + FIFO_0_FULL_L : 1; /*!< (@ 0x00000001) Interrupt mask signal. */ + __IOM uint32_t + COUNTER_0_IS_ZERO_L : 1; /*!< (@ 0x00000002) Interrupt mask signal. */ + __IOM uint32_t + COUNTER_0_IS_PEAK_L : 1; /*!< (@ 0x00000003) Interrupt mask signal. */ + __IOM uint32_t RESERVED1 : 12; /*!< (@ 0x00000004) Reserved1 */ + __IOM uint32_t INTR_1_L : 1; /*!< (@ 0x00000010) Interrupt mask signal. */ + __IOM uint32_t + FIFO_1_FULL_L : 1; /*!< (@ 0x00000011) Interrupt mask signal. */ + __IOM uint32_t + COUNTER_1_IS_ZERO_L : 1; /*!< (@ 0x00000012) Interrupt mask signal. */ + __IOM uint32_t + COUNTER_1_IS_PEAK_L : 1; /*!< (@ 0x00000013) Interrupt mask signal. */ + __IOM uint32_t RESERVED2 : 12; /*!< (@ 0x00000014) Reserved2 */ + } CT_INTR_MASK_b; + }; + + union { + __IOM uint32_t CT_INTER_UNMASK; /*!< (@ 0x00000010) Interrupts unmask */ + + struct { + __IOM uint32_t INTR_0_L : 1; /*!< (@ 0x00000000) Interrupt unmask signal. */ + __IOM uint32_t + FIFO_0_FULL_L : 1; /*!< (@ 0x00000001) Interrupt unmask signal. */ + __IOM uint32_t + COUNTER_0_IS_ZERO_L : 1; /*!< (@ 0x00000002) Interrupt unmask signal. */ + __IOM uint32_t + COUNTER_0_IS_PEAK_L : 1; /*!< (@ 0x00000003) Interrupt unmask signal. */ + __IM uint32_t RESERVED1 : 12; /*!< (@ 0x00000004) Reserved1 */ + __IOM uint32_t INTR_1_L : 1; /*!< (@ 0x00000010) Interrupt unmask signal. */ + __IOM uint32_t + FIFO_1_FULL_L : 1; /*!< (@ 0x00000011) Interrupt unmask signal */ + __IOM uint32_t + COUNTER_1_IS_ZERO_L : 1; /*!< (@ 0x00000012) Interrupt unmask signal. */ + __IOM uint32_t + COUNTER_1_IS_PEAK_L : 1; /*!< (@ 0x00000013) Interrupt unmask signal. */ + __IM uint32_t RESERVED2 : 12; /*!< (@ 0x00000014) Reserved2 */ + } CT_INTER_UNMASK_b; + }; + + union { + __IOM uint32_t CT_INTR_ACK; /*!< (@ 0x00000014) Interrupt clear/ack register */ + + struct { + __IOM uint32_t INTR_0_L : 1; /*!< (@ 0x00000000) Interrupt ack signal. */ + __IOM uint32_t + FIFO_0_FULL_L : 1; /*!< (@ 0x00000001) Interrupt ack signal. */ + __IOM uint32_t + COUNTER_0_IS_ZERO_L : 1; /*!< (@ 0x00000002) Interrupt ack signal. */ + __IOM uint32_t + COUNTER_0_IS_PEAK_L : 1; /*!< (@ 0x00000003) Interrupt ack signal. */ + __IM uint32_t RESERVED1 : 12; /*!< (@ 0x00000004) Reserved1 */ + __IOM uint32_t INTR_1_L : 1; /*!< (@ 0x00000010) Interrupt ack signal. */ + __IOM uint32_t + FIFO_1_FULL_L : 1; /*!< (@ 0x00000011) Interrupt ack signal. */ + __IOM uint32_t + COUNTER_1_IS_ZERO_L : 1; /*!< (@ 0x00000012) Interrupt ack signal. */ + __IOM uint32_t + COUNTER_1_IS_PEAK_L : 1; /*!< (@ 0x00000013) Interrupt ack signal. */ + __IOM uint32_t RESERVED2 : 12; /*!< (@ 0x00000014) Reserved2 */ + } CT_INTR_ACK_b; + }; + + union { + __IOM uint32_t CT_MATCH_REG; /*!< (@ 0x00000018) Match value register */ + + struct { + __IOM uint32_t + COUNTER_0_MATCH : 16; /*!< (@ 0x00000000) This will be used as lower match */ + __IOM uint32_t + COUNTER_1_MATCH : 16; /*!< (@ 0x00000010) This will be used as upper match */ + } CT_MATCH_REG_b; + }; + + union { + __IOM uint32_t CT_MATCH_BUF_REG; /*!< (@ 0x0000001C) Match Buffer register */ + + struct { + __IOM uint32_t COUNTER_0_MATCH_BUF : 16; /*!< (@ 0x00000000) This gets copied to MATCH register if bug_reg_0_en + is set. Copying is done when counter 0 + is active and hits 0. */ + __IOM uint32_t COUNTER_1_MATCH_BUF : 16; /*!< (@ 0x00000010) This gets copied to MATCH register if bug_reg_1_en + is set. Copying is done when counter 1 + is active and hits 0. */ + } CT_MATCH_BUF_REG_b; + }; + + union { + __IM uint32_t CT_CAPTURE_REG; /*!< (@ 0x00000020) Capture Register */ + + struct { + __IM uint32_t COUNTER_0_CAPTURE : 16; /*!< (@ 0x00000000) This is a latched value of counter lower part + when the selected capture_event occurs */ + __IM uint32_t COUNTER_1_CAPTURE : 16; /*!< (@ 0x00000010) This is a latched value of counter upper part + when the selected capture_event occurs */ + } CT_CAPTURE_REG_b; + }; + + union { + __IOM uint32_t CT_COUNTER_REG; /*!< (@ 0x00000024) Counter Register */ + + struct { + __IM uint32_t COUNTER0 : 16; /*!< (@ 0x00000000) This holds the value of counter-0 */ + __IM uint32_t COUNTER1 : 16; /*!< (@ 0x00000010) This holds the value of counter-1 */ + } CT_COUNTER_REG_b; + }; + + union { + __IOM uint32_t CT_OCU_CTRL_REG; /*!< (@ 0x00000028) OCU control register */ + + struct { + __IOM uint32_t OUTPUT_IS_OCU_0 : 1; /*!< (@ 0x00000000) Indicates whether the output is in OCU mode or + not for channel-0 */ + __IOM uint32_t SYNC_WITH_0 : 3; /*!< (@ 0x00000001) Indicates whether the other channel is in sync + with this channel */ + __IOM uint32_t OCU_0_DMA_MODE : 1; /*!< (@ 0x00000004) Indicates whether the OCU DMA mode is active + or not for channel 0 */ + __IOM uint32_t OCU_0_MODE_8_16 : 1; /*!< (@ 0x00000005) Indicates whether entire 16 bits or only 8-bits + of the channel 0 are used in OCU mode */ + __IOM uint32_t MAKE_OUTPUT_0_HIGH_SEL : 3; /*!< (@ 0x00000006) Check counter ocus for possibilities. When this + is hit output will be made high. */ + __IOM uint32_t MAKE_OUTPUT_0_LOW_SEL : 3; /*!< (@ 0x00000009) Check counter ocus for possibilities. When this + is hit output will be made low. */ + __IOM uint32_t RESERVED1 : 4; /*!< (@ 0x0000000C) Reserved1 */ + __IOM uint32_t OUTPUT_1_IS_OCU : 1; /*!< (@ 0x00000010) Indicates whether the output is in OCU mode or + not for channel 1 */ + __IOM uint32_t SYNC_WITH_1 : 3; /*!< (@ 0x00000011) Indicates whether the other channel is in sync + with this channel */ + __IOM uint32_t OCU_1_DMA_MODE : 1; /*!< (@ 0x00000014) Indicates whether the OCU DMA mode is active + or not for channel 1 */ + __IOM uint32_t OCU_1_MODE_8_16_MODE : 1; /*!< (@ 0x00000015) Indicates whether entire 16 bits or only 8-bits + of the channel 1 are used in OCU mode */ + __IOM uint32_t MAKE_OUTPUT_1_HIGH_SEL : 3; /*!< (@ 0x00000016) Check counter ocus for possibilities. When this + is hit output will be made high. */ + __IOM uint32_t MAKE_OUTPUT_1_LOW_SEL : 3; /*!< (@ 0x00000019) Check counter ocus for possibilities. When this + is hit output will be made low. */ + __IOM uint32_t RESERVED2 : 4; /*!< (@ 0x0000001C) Reserved2 */ + } CT_OCU_CTRL_REG_b; + }; + + union { + __IOM uint32_t CT_OCU_COMPARE_REG; /*!< (@ 0x0000002C) OCU Compare Register */ + + struct { + __IOM uint32_t OCU_COMPARE_0_REG : 16; /*!< (@ 0x00000000) Holds the threshold value of present OCU period + which denotes the number of clock cycles + for which the OCU output should be considered + (counter 0) */ + __IOM uint32_t OCU_COMPARE_1_REG : 16; /*!< (@ 0x00000010) Holds the threshold value of present OCU period + which denotes the number of clock cycles + for which the OCU output should be considered + (counter 1) */ + } CT_OCU_COMPARE_REG_b; + }; + + union { + __IOM uint32_t + CT_OCU_COMPARE2_REG; /*!< (@ 0x00000030) OCU Compare2 Register */ + + struct { + __IOM uint32_t OCU_COMPARE2_0_REG : 16; /*!< (@ 0x00000000) Holds the threshold value of present OCU period2 + which denotes the number of clock cycles + for which the OCU output should be considered + (counter 0) */ + __IOM uint32_t OCU_COMPARE2_1_REG : 16; /*!< (@ 0x00000010) Holds the threshold value of present OCU period2 + which denotes the number of clock cycles + for which the OCU output should be considered + (counter 1) */ + } CT_OCU_COMPARE2_REG_b; + }; + + union { + __IOM uint32_t CT_OCU_SYNC_REG; /*!< (@ 0x00000034) OCU Synchronization Register */ + + struct { + __IOM uint32_t OCU_SYNC_CHANNEL0_REG : 16; /*!< (@ 0x00000000) Starting point of channel 0 for synchronization + purpose */ + __IOM uint32_t OCU_SYNC_CHANNEL1_REG : 16; /*!< (@ 0x00000010) Starting point of channel 1 for synchronization + purpose */ + } CT_OCU_SYNC_REG_b; + }; + + union { + __IOM uint32_t + CT_OCU_COMPARE_NXT_REG; /*!< (@ 0x00000038) PWM compare next register */ + + struct { + __IOM uint32_t + OCU_COMPARE_NXT_COUNTER1 : 16; /*!< (@ 0x00000000) OCU output should be high for counter 1 */ + __IOM uint32_t + OCU_COMPARE_NXT_COUNTER0 : 16; /*!< (@ 0x00000010) PWM output should be high for counter 0 */ + } CT_OCU_COMPARE_NXT_REG_b; + }; + + union { + __IOM uint32_t CT_WFG_CTRL_REG; /*!< (@ 0x0000003C) WFG control register */ + + struct { + __IOM uint32_t + MAKE_OUTPUT_0_TGL_0_SEL : 3; /*!< (@ 0x00000000) Check the counter ocus possibilities for description + for channel 0. */ + __IOM uint32_t + MAKE_OUTPUT_0_TGL_1_SEL : 3; /*!< (@ 0x00000003) Check the counter ocus possibilities for description + for channel 0. */ + __IOM uint32_t RESERVED1 : 2; /*!< (@ 0x00000006) Reserved1 */ + __IOM uint32_t WFG_TGL_CNT_0_PEAK : 8; /*!< (@ 0x00000008) WFG mode output toggle count clock for channel + 0. */ + __IOM uint32_t + MAKE_OUTPUT_1_TGL_0_SEL : 3; /*!< (@ 0x00000010) Check the counter ocus possibilities for description + for channel 1. */ + __IOM uint32_t + MAKE_OUTPUT_1_TGL_1_SEL : 3; /*!< (@ 0x00000013) Check the counter ocus possibilities for description + for channel 1. */ + __IOM uint32_t RESERVED2 : 2; /*!< (@ 0x00000016) Reserved2 */ + __IOM uint32_t WFG_TGL_CNT_1_PEAK : 8; /*!< (@ 0x00000018) WFG mode output toggle count clock for channel + 1 */ + } CT_WFG_CTRL_REG_b; + }; + + union { + __IOM uint32_t + CT_OCU_COMPARE2_NXT_REG; /*!< (@ 0x00000040) PWM compare next register */ + + struct { + __IOM uint32_t + OCU_COMPARE2_NXT_COUNTER0 : 16; /*!< (@ 0x00000000) OCU output should be high for counter 1 */ + __IOM uint32_t + OCU_COMPARE2_NXT_COUNTER1 : 16; /*!< (@ 0x00000010) PWM output should be high for counter 0 */ + } CT_OCU_COMPARE2_NXT_REG_b; + }; + __IM uint32_t RESERVED[3]; + + union { + __IOM uint32_t + CT_START_COUNTER_EVENT_SEL; /*!< (@ 0x00000050) Start counter event select register */ + + struct { + __IOM uint32_t START_COUNTER_0_EVENT_SEL : 6; /*!< (@ 0x00000000) For two 16 bit counters mode: Event select for + starting the Counter 0 For 32 bit counter + mode: Event select for starting counter */ + __IOM uint32_t RESERVED1 : 10; /*!< (@ 0x00000006) Reserved1 */ + __IOM uint32_t START_COUNTER_1_EVENT_SEL : 6; /*!< (@ 0x00000010) For two 16 bit counters mode: Event select for + starting the Counter 1. For 32 bit counter + mode: Invalid. Please refer to events table + for description */ + __IM uint32_t RESERVED2 : 10; /*!< (@ 0x00000016) Reserved2 */ + } CT_START_COUNTER_EVENT_SEL_b; + }; + + union { + __IOM uint32_t + CT_START_COUNTER_AND_EVENT; /*!< (@ 0x00000054) Start counter AND event register */ + + struct { + __IOM uint32_t + START_COUNTER_0_AND_EVENT : 4; /*!< (@ 0x00000000) For two 16 bit counter mode: AND expression valids + for AND event in start Counter 0 event + For 32 bit counter mode AND expression + valids for AND event in start counter event */ + __IOM uint32_t RESERVED1 : 4; /*!< (@ 0x00000004) Reserved1 */ + __IOM uint32_t + START_COUNTER_0_AND_VLD : 4; /*!< (@ 0x00000008) none */ + __IM uint32_t RESERVED2 : 4; /*!< (@ 0x0000000C) Reserved2 */ + __IOM uint32_t START_COUNTER_1_AND_EVENT : 4; /*!< (@ 0x00000010) For two 16 bit counters mode: AND expression + valids for AND event in start counter event + For 32 bit counter mode : Invalid */ + __IM uint32_t RESERVED3 : 4; /*!< (@ 0x00000014) Reserved3 */ + __IOM uint32_t + START_COUNTER_1_AND_VLD : 4; /*!< (@ 0x00000018) none */ + __IM uint32_t RESERVED4 : 4; /*!< (@ 0x0000001C) Reserved4 */ + } CT_START_COUNTER_AND_EVENT_b; + }; + + union { + __IOM uint32_t + CT_START_COUNTER_OR_EVENT; /*!< (@ 0x00000058) Start counter OR event register */ + + struct { + __IOM uint32_t START_COUNTER_0_OR_EVENT : 4; /*!< (@ 0x00000000) For two 16 bit counter mode: OR expression valids + for OR event in start Counter 0 event For + 32 bit counter mode OR expression valids + for OR event in start counter event */ + __IOM uint32_t RESERVED1 : 4; /*!< (@ 0x00000004) Reserved1 */ + __IOM uint32_t + START_COUNTER_0_OR_VLD : 4; /*!< (@ 0x00000008) none */ + __IOM uint32_t RESERVED2 : 4; /*!< (@ 0x0000000C) Reserved2 */ + __IOM uint32_t + START_COUNTER_1_OR_EVENT : 4; /*!< (@ 0x00000010) For two 16 bit counters mode: OR expression valids + for OR event in start counter event For + 32 bit counter mode : Invalid. */ + __IM uint32_t RESERVED3 : 4; /*!< (@ 0x00000014) Reserved3 */ + __IOM uint32_t + START_COUNTER_1_OR_VLD : 4; /*!< (@ 0x00000018) none */ + __IM uint32_t RESERVED4 : 4; /*!< (@ 0x0000001C) Reserved4 */ + } CT_START_COUNTER_OR_EVENT_b; + }; + + union { + __IOM uint32_t + CT_CONTINUE_COUNTER_EVENT_SEL; /*!< (@ 0x0000005C) Continue counter event select register */ + + struct { + __IOM uint32_t + CONTINUE_COUNTER_0_EVENT_SEL : 6; /*!< (@ 0x00000000) For two 16 bit counters mode: Event select for + continuing the Counter 0 For 32 bit counter + mode: Event select for continuing counter */ + __IOM uint32_t RESERVED1 : 10; /*!< (@ 0x00000006) Reserved1 */ + __IOM uint32_t + CONTINUE_COUNTER_1_EVENT_SEL : 6; /*!< (@ 0x00000010) For two 16 bit counters mode: Event select for + continuing the Counter 1 For 32 bit counter + mode: Invalid. */ + __IM uint32_t RESERVED2 : 10; /*!< (@ 0x00000016) Reserved2 */ + } CT_CONTINUE_COUNTER_EVENT_SEL_b; + }; + + union { + __IOM uint32_t + CT_CONTINUE_COUNTER_AND_EVENT; /*!< (@ 0x00000060) Continue counter AND event register */ + + struct { + __IOM uint32_t + CONTINUE_COUNTER_0_AND_EVENT : 4; /*!< (@ 0x00000000) For two 16 bit counter mode: AND expression valids + for AND event in continue Counter 0 event + For 32 bit counter mode AND expression + valids for AND event in continue counter + event. */ + __IOM uint32_t RESERVED1 : 4; /*!< (@ 0x00000004) Reserved1 */ + __IOM uint32_t + CONTINUE_COUNTER_0_AND_VLD : 4; /*!< (@ 0x00000008) none */ + __IOM uint32_t RESERVED2 : 4; /*!< (@ 0x0000000C) Reserved2 */ + __IOM uint32_t CONTINUE_COUNTER_1_AND_EVENT : 4; /*!< (@ 0x00000010) For two 16 bit counters mode: AND expression + valids for AND event in continue counter + event For 32 bit counter mode : Invalid */ + __IM uint32_t RESERVED3 : 4; /*!< (@ 0x00000014) Reserved3 */ + __IOM uint32_t + CONTINUE_COUNTER_1_AND_VLD : 4; /*!< (@ 0x00000018) none */ + __IM uint32_t RESERVED4 : 4; /*!< (@ 0x0000001C) Reserved4 */ + } CT_CONTINUE_COUNTER_AND_EVENT_b; + }; + + union { + __IOM uint32_t + CT_CONTINUE_COUNTER_OR_EVENT; /*!< (@ 0x00000064) Continue counter OR event register */ + + struct { + __IOM uint32_t + CONTINUE_COUNTER_0_OR_EVENT : 4; /*!< (@ 0x00000000) For two 16 bit counter mode: OR expression valids + for OR event in continue Counter 0 event + For 32 bit counter mode OR expression valids + for OR event in continue counter event */ + __IOM uint32_t RESERVED1 : 4; /*!< (@ 0x00000004) Reserved1 */ + __IOM uint32_t + CONTINUE_COUNTER_0_OR_VLD : 4; /*!< (@ 0x00000008) none */ + __IOM uint32_t RESERVED2 : 4; /*!< (@ 0x0000000C) Reserved2 */ + __IOM uint32_t + CONTINUE_COUNTER_1_OR_EVENT : 4; /*!< (@ 0x00000010) For two 16 bit counters mode: OR expression valids + for OR event in continue counter event + For 32 bit counter mode : Invalid */ + __IM uint32_t RESERVED3 : 4; /*!< (@ 0x00000014) Reserved3 */ + __IOM uint32_t + CONTINUE_COUNTER_1_OR_VLD : 4; /*!< (@ 0x00000018) none */ + __IM uint32_t RESERVED4 : 4; /*!< (@ 0x0000001C) Reserved4 */ + } CT_CONTINUE_COUNTER_OR_EVENT_b; + }; + + union { + __IOM uint32_t + CT_STOP_COUNTER_EVENT_SEL; /*!< (@ 0x00000068) Stop counter event select register */ + + struct { + __IOM uint32_t STOP_COUNTER_0_EVENT_SEL : 6; /*!< (@ 0x00000000) For two 16 bit counters mode: Event select for + Stopping the Counter 0 For 32 bit counter + mode: Event select for Stopping counter */ + __IOM uint32_t RESERVED1 : 10; /*!< (@ 0x00000006) Reserved1 */ + __IOM uint32_t STOP_COUNTER_1_EVENT_SEL : 6; /*!< (@ 0x00000010) For two 16 bit counters mode: Event select for + Stopping the Counter 1 For 32 bit counter + mode: Invalid */ + __IM uint32_t RESERVED2 : 10; /*!< (@ 0x00000016) Reserved2 */ + } CT_STOP_COUNTER_EVENT_SEL_b; + }; + + union { + __IOM uint32_t + CT_STOP_COUNTER_AND_EVENT; /*!< (@ 0x0000006C) Stop counter AND event register */ + + struct { + __IOM uint32_t + STOP_COUNTER_0_AND_EVENT : 4; /*!< (@ 0x00000000) For two 16 bit counter mode: AND expression valids + for AND event in stop Counter 0 event For + 32 bit counter mode AND expression valids + for AND event in stop counter event */ + __IOM uint32_t RESERVED1 : 4; /*!< (@ 0x00000004) Reserved1 */ + __IOM uint32_t + STOP_COUNTER_0_AND_VLD : 4; /*!< (@ 0x00000008) Indicates which bits in 3:0 are valid for considering + AND event */ + __IOM uint32_t RESERVED2 : 4; /*!< (@ 0x0000000C) Reserved2 */ + __IOM uint32_t STOP_COUNTER_1_AND_EVENT : 4; /*!< (@ 0x00000010) For two 16 bit counters mode: AND expression + valids for AND event in stop counter event + For 32 bit counter mode : Invalid */ + __IM uint32_t RESERVED3 : 4; /*!< (@ 0x00000014) Reserved3 */ + __IOM uint32_t + STOP_COUNTER_1_AND_VLD : 4; /*!< (@ 0x00000018) none */ + __IM uint32_t RESERVED4 : 4; /*!< (@ 0x0000001C) Reserved4 */ + } CT_STOP_COUNTER_AND_EVENT_b; + }; + + union { + __IOM uint32_t + CT_STOP_COUNTER_OR_EVENT; /*!< (@ 0x00000070) Stop counter OR event register */ + + struct { + __IOM uint32_t STOP_COUNTER_0_OR_EVENT : 4; /*!< (@ 0x00000000) For two 16 bit counter mode: OR expression valids + for OR event in Stop Counter 0 event For + 32 bit counter mode OR expression valids + for OR event in Stop counter event */ + __IOM uint32_t RESERVED1 : 4; /*!< (@ 0x00000004) Reserved1 */ + __IOM uint32_t + STOP_COUNTER_0_OR_VLD : 4; /*!< (@ 0x00000008) none */ + __IOM uint32_t RESERVED2 : 4; /*!< (@ 0x0000000C) Reserved2 */ + __IOM uint32_t STOP_COUNTER_1_OR_EVENT : 4; /*!< (@ 0x00000010) For two 16 bit counters mode: OR expression valids + for OR event in Stop counter event For + 32 bit counter mode : Invalid */ + __IM uint32_t RESERVED3 : 4; /*!< (@ 0x00000014) Reserved3 */ + __IOM uint32_t + STOP_COUNTER_1_OR_VLD : 4; /*!< (@ 0x00000018) none */ + __IM uint32_t RESERVED4 : 4; /*!< (@ 0x0000001C) Reserved4 */ + } CT_STOP_COUNTER_OR_EVENT_b; + }; + + union { + __IOM uint32_t + CT_HALT_COUNTER_EVENT_SEL; /*!< (@ 0x00000074) Halt counter event select register */ + + struct { + __IOM uint32_t HALT_COUNTER_0_EVENT_SEL : 6; /*!< (@ 0x00000000) For two 16 bit counters mode: Event select for + Halting the Counter 0 For 32 bit counter + mode: Event select for Halting counter */ + __OM uint32_t RESUME_FROM_HALT_COUNTER_0 : 1; /*!< (@ 0x00000006) For two 16 bit counters mode: Event select for + Halting the Counter 0 For 32 bit counter + mode: Event select for Halting counter */ + __IM uint32_t RESERVED1 : 9; /*!< (@ 0x00000007) Reserved1 */ + __IOM uint32_t HALT_COUNTER_1_EVENT_SEL : 6; /*!< (@ 0x00000010) For two 16 bit counters mode: Event select for + Halting the Counter 1 For 32 bit counter + mode: Invalid */ + __OM uint32_t RESUME_FROM_HALT_COUNTER_1 : 1; /*!< (@ 0x00000016) For two 16 bit counters mode: Event select for + Halting the Counter 0 For 32 bit counter + mode: Event select for Halting counter */ + __IM uint32_t RESERVED2 : 9; /*!< (@ 0x00000017) Reserved2 */ + } CT_HALT_COUNTER_EVENT_SEL_b; + }; + + union { + __IOM uint32_t + CT_HALT_COUNTER_AND_EVENT; /*!< (@ 0x00000078) Halt counter AND event register */ + + struct { + __IOM uint32_t + HALT_COUNTER_0_AND_EVENT : 4; /*!< (@ 0x00000000) For two 16 bit counter mode: AND expression valids + for AND event in stop Counter 0 event For + 32 bit counter mode AND expression valids + for AND event in stop counter event */ + __IOM uint32_t RESERVED1 : 4; /*!< (@ 0x00000004) Reserved1 */ + __IOM uint32_t + HALT_COUNTER_0_AND_VLD : 4; /*!< (@ 0x00000008) Indicates which bits in 3:0 are valid for considering + AND event */ + __IM uint32_t RESERVED2 : 4; /*!< (@ 0x0000000C) Reserved2 */ + __IOM uint32_t HALT_COUNTER_1_AND_EVENT : 4; /*!< (@ 0x00000010) For two 16 bit counters mode: AND expression + valids for AND event in stop counter event + For 32 bit counter mode : Invalid */ + __IM uint32_t RESERVED3 : 4; /*!< (@ 0x00000014) Reserved3 */ + __IOM uint32_t + HALT_COUNTER_1_AND_VLD : 4; /*!< (@ 0x00000018) none */ + __IM uint32_t RESERVED4 : 4; /*!< (@ 0x0000001C) Reserved4 */ + } CT_HALT_COUNTER_AND_EVENT_b; + }; + + union { + __IOM uint32_t + CT_HALT_COUNTER_OR_EVENT; /*!< (@ 0x0000007C) Halt counter OR event register */ + + struct { + __IOM uint32_t HALT_COUNTER_0_OR_EVENT : 4; /*!< (@ 0x00000000) For two 16 bit counter mode: OR expression valids + for OR event in Halt Counter 0 event For + 32 bit counter mode OR expression valids + for OR event in Halt counter event */ + __IOM uint32_t RESERVED1 : 4; /*!< (@ 0x00000004) Reserved1 */ + __IOM uint32_t + HALT_COUNTER_0_OR_VLD : 4; /*!< (@ 0x00000008) none */ + __IM uint32_t RESERVED2 : 4; /*!< (@ 0x0000000C) Reserved2 */ + __IOM uint32_t HALT_COUNTER_1_OR_EVENT : 4; /*!< (@ 0x00000010) For two 16 bit counters mode: OR expression valids + for OR event in Halt counter event For + 32 bit counter mode : Invalid */ + __IM uint32_t RESERVED3 : 4; /*!< (@ 0x00000014) Reserved3 */ + __IOM uint32_t + HALT_COUNTER_1_OR_VLD : 4; /*!< (@ 0x00000018) none */ + __IM uint32_t RESERVED4 : 4; /*!< (@ 0x0000001C) Reserved4 */ + } CT_HALT_COUNTER_OR_EVENT_b; + }; + + union { + __IOM uint32_t + CT_INCREMENT_COUNTER_EVENT_SEL; /*!< (@ 0x00000080) Increment counter event select register */ + + struct { + __IOM uint32_t + INCREMENT_COUNTER_0_EVENT_SEL : 6; /*!< (@ 0x00000000) For two 16 bit counters mode: Event select for + Incrementing the Counter 0 For 32 bit counter + mode: Event select for Incrementing counter */ + __IM uint32_t RESERVED1 : 10; /*!< (@ 0x00000006) Reserved1 */ + __IOM uint32_t + INCREMENT_COUNTER_1_EVENT_SEL : 6; /*!< (@ 0x00000010) For two 16 bit counters mode: Event select for + Incrementing the Counter 1 For 32 bit counter + mode: Invalid */ + __IM uint32_t RESERVED2 : 10; /*!< (@ 0x00000016) Reserved2 */ + } CT_INCREMENT_COUNTER_EVENT_SEL_b; + }; + + union { + __IOM uint32_t + CT_INCREMENT_COUNTER_AND_EVENT; /*!< (@ 0x00000084) Increment counter AND event register */ + + struct { + __IOM uint32_t + INCREMENT_COUNTER_0_AND_EVENT : 4; /*!< (@ 0x00000000) For two 16 bit counter mode: AND expression valids + for AND event in stop Counter 0 event For + 32 bit counter mode AND expression valids + for AND event in stop counter event */ + __IOM uint32_t RESERVED1 : 4; /*!< (@ 0x00000004) Reserved1 */ + __IOM uint32_t + INCREMENT_COUNTER_0_AND_VLD : 4; /*!< (@ 0x00000008) none */ + __IM uint32_t RESERVED2 : 4; /*!< (@ 0x0000000C) Reserved2 */ + __IOM uint32_t INCREMENT_COUNTER_1_AND_EVENT : 4; /*!< (@ 0x00000010) For two 16 bit counters mode: AND expression + valids for AND event in stop counter event + For 32 bit counter mode : Invalid */ + __IM uint32_t RESERVED3 : 4; /*!< (@ 0x00000014) Reserved3 */ + __IOM uint32_t + INCREMENT_COUNTER_1_AND_VLD : 4; /*!< (@ 0x00000018) none */ + __IM uint32_t RESERVED4 : 4; /*!< (@ 0x0000001C) Reserved4 */ + } CT_INCREMENT_COUNTER_AND_EVENT_b; + }; + + union { + __IOM uint32_t + CT_INCREMENT_COUNTER_OR_EVENT; /*!< (@ 0x00000088) Increment counter OR event register */ + + struct { + __IOM uint32_t + INCREMENT_COUNTER_0_OR_EVENT : 4; /*!< (@ 0x00000000) For two 16 bit counter mode: OR expression valids + for OR event in Increment Counter 0 event + For 32 bit counter mode OR expression valids + for OR event in Increment counter event */ + __IOM uint32_t RESERVED1 : 4; /*!< (@ 0x00000004) Reserved1 */ + __IOM uint32_t + INCREMENT_COUNTER_0_OR_VLD : 4; /*!< (@ 0x00000008) none */ + __IM uint32_t RESERVED2 : 4; /*!< (@ 0x0000000C) Reserved2 */ + __IOM uint32_t + INCREMENT_COUNTER_1_OR_EVENT : 4; /*!< (@ 0x00000010) For two 16 bit counters mode: OR expression valids + for OR event in Increment counter event + For 32 bit counter mode : Invalid */ + __IM uint32_t RESERVED4 : 4; /*!< (@ 0x00000014) Reserved4 */ + __IOM uint32_t + INCREMENT_COUNTER_1_OR_VLD : 4; /*!< (@ 0x00000018) none */ + __IM uint32_t RESERVED5 : 4; /*!< (@ 0x0000001C) Reserved5 */ + } CT_INCREMENT_COUNTER_OR_EVENT_b; + }; + + union { + __IOM uint32_t + CT_CAPTURE_COUNTER_EVENT_SEL; /*!< (@ 0x0000008C) Capture counter event select register */ + + struct { + __IOM uint32_t CAPTURE_COUNTER_0_EVENT_SEL : 6; /*!< (@ 0x00000000) For two 16 bit counters mode: Event select for + Capturing the Counter 0 For 32 bit counter + mode: Event select for Capturing counter */ + __IM uint32_t RESERVED1 : 10; /*!< (@ 0x00000006) Reserved1 */ + __IOM uint32_t CAPTURE_COUNTER_1_EVENT_SEL : 6; /*!< (@ 0x00000010) For two 16 bit counters mode: Event select for + Capturing the Counter 1 For 32 bit counter + mode : Invalid */ + __IM uint32_t RESERVED2 : 10; /*!< (@ 0x00000016) Reserved2 */ + } CT_CAPTURE_COUNTER_EVENT_SEL_b; + }; + + union { + __IOM uint32_t + CT_CAPTURE_COUNTER_AND_EVENT; /*!< (@ 0x00000090) Capture counter AND event register */ + + struct { + __IOM uint32_t + CAPTURE_COUNTER_0_AND_EVENT : 4; /*!< (@ 0x00000000) For two 16 bit counter mode: AND expression valids + for AND event in stop Counter 0 event For + 32 bit counter mode AND expression valids + for AND event in stop counter event */ + __IOM uint32_t RESERVED1 : 4; /*!< (@ 0x00000004) Reserved1 */ + __IOM uint32_t + CAPTURE_COUNTER_0_AND_VLD : 4; /*!< (@ 0x00000008) none */ + __IM uint32_t RESERVED2 : 4; /*!< (@ 0x0000000C) Reserved2 */ + __IOM uint32_t CAPTURE_COUNTER_1_AND_EVENT : 4; /*!< (@ 0x00000010) For two 16 bit counters mode: AND expression + valids for AND event in stop counter event + For 32 bit counter mode : Invalid */ + __IM uint32_t RESERVED3 : 4; /*!< (@ 0x00000014) Reserved3 */ + __IOM uint32_t + CAPTURE_COUNTER_1_AND_VLD : 4; /*!< (@ 0x00000018) none */ + __IM uint32_t RESERVED4 : 4; /*!< (@ 0x0000001C) Reserved4 */ + } CT_CAPTURE_COUNTER_AND_EVENT_b; + }; + + union { + __IOM uint32_t + CT_CAPTURE_COUNTER_OR_EVENT; /*!< (@ 0x00000094) Capture counter OR event register */ + + struct { + __IOM uint32_t + CAPTURE_COUNTER_0_OR_EVENT : 4; /*!< (@ 0x00000000) For two 16 bit counter mode: OR expression valids + for OR event in Capture Counter 0 event + For 32 bit counter mode OR expression valids + for OR event in Capture counter event */ + __IOM uint32_t RESERVED1 : 4; /*!< (@ 0x00000004) Reserved1 */ + __IOM uint32_t + CAPTURE_COUNTER_0_OR_VLD : 4; /*!< (@ 0x00000008) none */ + __IM uint32_t RESERVED2 : 4; /*!< (@ 0x0000000C) Reserved2 */ + __IOM uint32_t + CAPTURE_COUNTER_1_OR_EVENT : 4; /*!< (@ 0x00000010) For two 16 bit counters mode: OR expression valids + for OR event in Capture counter event For + 32 bit counter mode : Invalid */ + __IM uint32_t RESERVED3 : 4; /*!< (@ 0x00000014) Reserved3 */ + __IOM uint32_t + CAPTURE_COUNTER_1_OR_VLD : 4; /*!< (@ 0x00000018) none */ + __IM uint32_t RESERVED4 : 4; /*!< (@ 0x0000001C) Reserved4 */ + } CT_CAPTURE_COUNTER_OR_EVENT_b; + }; + + union { + __IOM uint32_t + CT_OUTPUT_EVENT_SEL; /*!< (@ 0x00000098) Output event select register */ + + struct { + __IOM uint32_t OUTPUT_EVENT_SEL_0 : 6; /*!< (@ 0x00000000) For two 16 bit counters mode: Event select for + output event from Counter 0 For 32 bit + counter mode: Event select for output event */ + __IM uint32_t RESERVED1 : 10; /*!< (@ 0x00000006) Reserved1 */ + __IOM uint32_t OUTPUT_EVENT_SEL_1 : 6; /*!< (@ 0x00000010) For two 16 bit counters mode: Event select for + output event from counter 1 For 32 bit + counter mode : Invalid */ + __IM uint32_t RESERVED2 : 10; /*!< (@ 0x00000016) Reserved2 */ + } CT_OUTPUT_EVENT_SEL_b; + }; + + union { + __IOM uint32_t + CT_OUTPUT_AND_EVENT_REG; /*!< (@ 0x0000009C) Output AND event Register */ + + struct { + __IOM uint32_t OUTPUT_0_AND_EVENT : 4; /*!< (@ 0x00000000) AND expression for AND event in output Counter_0 + event. */ + __IOM uint32_t RESERVED1 : 4; /*!< (@ 0x00000004) Reserved1 */ + __IOM uint32_t OUTPUT_0_AND_VLD : 4; /*!< (@ 0x00000008) AND expression for AND event in output Counter_0 + event. */ + __IM uint32_t RESERVED2 : 4; /*!< (@ 0x0000000C) Reserved2 */ + __IOM uint32_t OUTPUT_1_AND_EVENT : 4; /*!< (@ 0x00000010) AND expression for AND event in output Counter_1 + event. */ + __IM uint32_t RESERVED3 : 4; /*!< (@ 0x00000014) Reserved3 */ + __IOM uint32_t OUTPUT_1_AND_VLD : 4; /*!< (@ 0x00000018) AND expression for AND event in output Counter_1 + event. */ + __IM uint32_t RESERVED4 : 4; /*!< (@ 0x0000001C) Reserved4 */ + } CT_OUTPUT_AND_EVENT_REG_b; + }; + + union { + __IOM uint32_t CT_OUTPUT_OR_EVENT; /*!< (@ 0x000000A0) Output OR event Register */ + + struct { + __IOM uint32_t OUTPUT_0_OR_EVENT : 4; /*!< (@ 0x00000000) OR expression for OR event in output Counter_0 + event */ + __IOM uint32_t RESERVED1 : 4; /*!< (@ 0x00000004) Reserved1 */ + __IOM uint32_t OUTPUT_0_OR_VLD : 4; /*!< (@ 0x00000008) Indicates which bits in 3:0 are valid for considering + OR event */ + __IM uint32_t RESERVED2 : 4; /*!< (@ 0x0000000C) Reserved2 */ + __IOM uint32_t OUTPUT_1_OR_EVENT : 4; /*!< (@ 0x00000010) OR expression for OR event in output Counter_0 + event */ + __IM uint32_t RESERVED3 : 4; /*!< (@ 0x00000014) Reserved3 */ + __IOM uint32_t OUTPUT_1_OR_VLD : 4; /*!< (@ 0x00000018) Indicates which bits in 3:0 are valid for considering + OR event */ + __IM uint32_t RESERVED4 : 4; /*!< (@ 0x0000001C) Reserved4 */ + } CT_OUTPUT_OR_EVENT_b; + }; + + union { + __IOM uint32_t CT_INTR_EVENT_SEL; /*!< (@ 0x000000A4) Interrupt Event Select Register */ + + struct { + __IOM uint32_t INTR_EVENT_SEL_0 : 6; /*!< (@ 0x00000000) For two 16 bit counters mode: Event select for + interrupt event from Counter 0 For 32 bit + counter mode: Event select for output event */ + __IM uint32_t RESERVED1 : 10; /*!< (@ 0x00000006) Reserved1 */ + __IOM uint32_t INTR_EVENT_SEL_1 : 6; /*!< (@ 0x00000010) For two 16 bit counters mode: Event select for + interrupt event from counter 1 For 32 bit + counter mode : Invalid */ + __IM uint32_t RESERVED2 : 10; /*!< (@ 0x00000016) Reserved2 */ + } CT_INTR_EVENT_SEL_b; + }; + + union { + __IOM uint32_t CT_INTR_AND_EVENT; /*!< (@ 0x000000A8) Interrupt AND Event Register */ + + struct { + __IOM uint32_t + INTR_0_AND_EVENT : 4; /*!< (@ 0x00000000) None */ + __IOM uint32_t RESERVED1 : 4; /*!< (@ 0x00000004) Reserved1 */ + __IOM uint32_t + INTR_0_AND_VLD : 4; /*!< (@ 0x00000008) None */ + __IM uint32_t RESERVED2 : 4; /*!< (@ 0x0000000C) Reserved2 */ + __IOM uint32_t + INTR_1_AND_EVENT : 4; /*!< (@ 0x00000010) None */ + __IM uint32_t RESERVED3 : 4; /*!< (@ 0x00000014) Reserved3 */ + __IOM uint32_t + INTR_1_AND_VLD : 4; /*!< (@ 0x00000018) None */ + __IM uint32_t RESERVED4 : 4; /*!< (@ 0x0000001C) Reserved4 */ + } CT_INTR_AND_EVENT_b; + }; + + union { + __IOM uint32_t + CT_INTR_OR_EVENT_REG; /*!< (@ 0x000000AC) Interrupt OR Event Register */ + + struct { + __IOM uint32_t + INTR_0_OR_EVENT : 4; /*!< (@ 0x00000000) None */ + __IOM uint32_t RESERVED1 : 4; /*!< (@ 0x00000004) Reserved1 */ + __IOM uint32_t + INTR_0_OR_VLD : 4; /*!< (@ 0x00000008) None */ + __IM uint32_t RESERVED2 : 4; /*!< (@ 0x0000000C) Reserved2 */ + __IOM uint32_t + INTR_1_OR_EVENT : 4; /*!< (@ 0x00000010) None */ + __IM uint32_t RESERVED3 : 4; /*!< (@ 0x00000014) Reserved3 */ + __IOM uint32_t + INTR_1_OR_VLD : 4; /*!< (@ 0x00000018) None */ + __IM uint32_t RESERVED4 : 4; /*!< (@ 0x0000001C) Reserved4 */ + } CT_INTR_OR_EVENT_REG_b; + }; +} CT0_Type; /*!< Size = 176 (0xb0) */ + +/* =========================================================================================================================== */ +/* ================ CT_MUX_REG ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Configurable timer is used in counting clocks, events and states with reference clock + external clock and system clock (CT_MUX_REG) */ + +typedef struct { /*!< (@ 0x4506F000) CT_MUX_REG Structure */ + union { + __IOM uint32_t CT_MUX_SEL_0_REG; /*!< (@ 0x00000000) MUX_SEL_0_REG Register */ + + struct { + __IOM uint32_t MUX_SEL_0 : 4; /*!< [3..0] Select value to select first output value fifo_0_full[0] + out of all the fifo_0_full_muxed signals of counter 0 */ + __IOM uint32_t RESERVED1 : 28; /*!< [31..4] Reserved1 */ + } CT_MUX_SEL_0_REG_b; + }; + + union { + __IOM uint32_t CT_MUX_SEL_1_REG; /*!< (@ 0x00000004) MUX_SEL_1_REG Register */ + + struct { + __IOM uint32_t MUX_SEL_1 : 4; /*!< [3..0] Select value to select first output value fifo_0_full[1] + out of all the fifo_0_full_muxed signals of counter 0 */ + __IOM uint32_t RESERVED1 : 28; /*!< [31..4] Reserved1 */ + } CT_MUX_SEL_1_REG_b; + }; + + union { + __IOM uint32_t CT_MUX_SEL_2_REG; /*!< (@ 0x00000008) MUX_SEL_2_REG Register */ + + struct { + __IOM uint32_t MUX_SEL_2 : 4; /*!< [3..0] Select value to select first output value fifo_1_full[0] + out of all the fifo_1_full_muxed signals of counter 1 */ + __IOM uint32_t RESERVED1 : 28; /*!< [31..4] Reserved1 */ + } CT_MUX_SEL_2_REG_b; + }; + + union { + __IOM uint32_t CT_MUX_SEL_3_REG; /*!< (@ 0x0000000C) MUX_SEL_3_REG Register */ + + struct { + __IOM uint32_t MUX_SEL_3 : 4; /*!< [3..0] Select value to select first output value fifo_1_full[1] + out of all the fifo_1_full_muxed signals of counter 1 */ + __IOM uint32_t RESERVED1 : 28; /*!< [31..4] Reserved1 */ + } CT_MUX_SEL_3_REG_b; + }; + __IM uint32_t RESERVED[2]; + + union { + __IOM uint32_t + CT_OUTPUT_EVENT1_ADC_SEL; /*!< (@ 0x00000018) OUTPUT_EVENT_ADC_SEL Register */ + + struct { + __IOM uint32_t OUTPUT_EVENT_ADC_SEL : 4; /*!< [3..0] Select signals to select one output event out of all + the output events output_event_0 output_event_1, output_event_2, + output_event_3 to enable ADC module */ + __IOM uint32_t RESERVED1 : 28; /*!< [31..4] Reserved1 */ + } CT_OUTPUT_EVENT1_ADC_SEL_b; + }; + + union { + __IOM uint32_t + CT_OUTPUT_EVENT2_ADC_SEL; /*!< (@ 0x0000001C) OUTPUT_EVENT_ADC_SEL Register */ + + struct { + __IOM uint32_t OUTPUT_EVENT_ADC_SEL : 4; /*!< [3..0] Select signals to select one output event out of all + the output events output_event_0 output_event_1, output_event_2, + output_event_3 to enable ADC module */ + __IOM uint32_t RESERVED1 : 28; /*!< [31..4] Reserved1 */ + } CT_OUTPUT_EVENT2_ADC_SEL_b; + }; +} CT_MUX_REG_Type; /*!< Size = 32 (0x20) */ + +/* ================================================================================ */ +/* ================ ETHERNET ================ */ +/* ================================================================================ */ + +/** + * @brief Ether MAC 10/100/1000 Universal enables a host to transmit and receive data over Ethernet in compliance with the IEEE 802.3-2002standard (ETHERNET) + */ + +typedef struct { + union { + __IO uint32_t MAC_ADDR_HIGH_REG; /*!< The MAC Address1 High register holds the upper 16 bits of the + 6-byte second MAC address of thestation. */ + + struct { + __IO uint32_t MAC_ADDR1_HIGH : 16; /*!< This field contains the upper 16 bits (47:32) of the 6-byte + second MAC address. */ + uint32_t : 8; + __IO uint32_t MBC_ADDR1_HIGH : 6; /*!< Mask Byte Control */ + __IO uint32_t SA : 1; /*!< When this bit is set, the MAC Address1[47:0] is used to compare + with the SAfields of the received frame */ + __IO uint32_t AE : 1; /*!< When this bit is set, the Address filter module uses the second + MAC address forperfect filtering */ + } MAC_ADDR_HIGH_REG_b; /*!< BitSize */ + }; + + union { + __IO uint32_t MAC_ADDR_LOW_REG; /*!< The MAC Address1 Low register holds the lower 32 bits of the + 6-byte second MAC address of the station */ + + struct { + __IO uint32_t MAC_ADDR1_LOW : 32; /*!< This field contains the upper 16 bits (47:32) of the 6-byte + second MAC address. */ + } MAC_ADDR_LOW_REG_b; /*!< BitSize */ + }; +} ETHERNET_MAC_16_ADDR_Type; + +typedef struct { + union { + __IO uint32_t MAC_ADDR_HIGH_REG; /*!< The MAC Address1 High register holds the upper 16 bits of the + 6-byte second MAC address of thestation. */ + + struct { + __IO uint32_t MAC_ADDR1_HIGH : 16; /*!< This field contains the upper 16 bits (47:32) of the 6-byte + second MAC address. */ + uint32_t : 8; + __IO uint32_t MBC_ADDR1_HIGH : 6; /*!< Mask Byte Control */ + __IO uint32_t SA : 1; /*!< When this bit is set, the MAC Address1[47:0] is used to compare + with the SAfields of the received frame */ + __IO uint32_t AE : 1; /*!< When this bit is set, the Address filter module uses the second + MAC address forperfect filtering */ + } MAC_ADDR_HIGH_REG_b; /*!< BitSize */ + }; + + union { + __IO uint32_t MAC_ADDR0_LOW_REG19; /*!< The MAC Address1 Low register holds the lower 32 bits of the + 6-byte second MAC address of thestation */ + + struct { + __IO uint32_t MAC_ADDR1_LOW : 32; /*!< This field contains the upper 16 bits (47:32) of the 6-byte + second MAC address. */ + } MAC_ADDR0_LOW_REG19_b; /*!< BitSize */ + }; +} ETHERNET_MAC_31_ADDR_Type; + +/* ================================================================================ */ +/* ================ ETHERNET ================ */ +/* ================================================================================ */ + +/** + * @brief Ether MAC 10/100/1000 Universal enables a host to transmit and receive data over Ethernet in compliance with the IEEE 802.3-2002standard (ETHERNET) + */ + +typedef struct { /*!< ETHERNET Structure */ + + union { + __IO uint32_t MAC_CONFIG_REG0; /*!< This is the operation mode register for the MAC. */ + + struct { + uint32_t : 2; + __IO uint32_t RE : 1; /*!< Receiver Enable */ + __IO uint32_t TE : 1; /*!< Transmitter Enable */ + __IO uint32_t DC : 1; /*!< Deferral Check */ + __IO uint32_t BL : 2; /*!< Back-Off Limit */ + __IO uint32_t ACS : 1; /*!< Automatic Pad/CRC Stripping */ + __IO uint32_t LUD : 1; /*!< Link Up/Down */ + __IO uint32_t DR : 1; /*!< Disable Retry */ + __IO uint32_t IPC : 1; /*!< Checksum Offload */ + __IO uint32_t DM : 1; /*!< Duplex Mode */ + __IO uint32_t LM : 1; /*!< Loop-back Mode */ + __IO uint32_t DO : 1; /*!< Disable Receive Own */ + __IO uint32_t FES : 1; /*!< Indicates the speed in Fast Ethernet (MII) mode: */ + __IO uint32_t PS : 1; /*!< Selects between GMII and MII: */ + __IO uint32_t DCRS : 1; /*!< Disable Carrier Sense During Transmission */ + __IO uint32_t IFG : 3; /*!< Inter-Frame Gap These bits control the minimum IFG between frames + during transmission */ + __IO uint32_t JE : 1; /*!< Jumbo Frame Enable */ + __IO uint32_t BE : 1; /*!< Frame Burst Enable */ + __IO uint32_t JD : 1; /*!< Jabber Disable */ + __IO uint32_t WD : 1; /*!< Watchdog Disable When this bit is set, the GMAC disables the + watchdog timer on the receiver, andcan receive frames of up + to 16,384 bytes */ + __IO uint32_t TC : 1; /*!< Transmit Configuration in RGMII/SGMII */ + } MAC_CONFIG_REG0_b; /*!< BitSize */ + }; + + union { + __IO uint32_t MAC_FRAME_FILTER_REG1; /*!< This is the operation mode register for the MAC. */ + + struct { + __IO uint32_t PR : 1; /*!< Promiscuous Mode */ + __IO uint32_t HUC : 1; /*!< Hash Unicast */ + __IO uint32_t HMC : 1; /*!< Hash Multicast */ + __IO uint32_t DAIF : 1; /*!< DA Inverse Filtering */ + __IO uint32_t PM : 1; /*!< Pass All Multicast */ + __IO uint32_t DBF : 1; /*!< Disable Broadcast Frames */ + __IO uint32_t PCF : 2; /*!< Pass Control Frames */ + __IO uint32_t SAIF : 1; /*!< SA Inverse Filtering */ + __IO uint32_t SAF : 1; /*!< Source Address Filter Enable */ + __IO uint32_t HPF : 1; /*!< Hash or Perfect Filter */ + uint32_t : 20; + __IO uint32_t RA : 1; /*!< Receive All */ + } MAC_FRAME_FILTER_REG1_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HASH_TABLE_HIGH_REG2; /*!< This is the operation mode register for the MAC. */ + + struct { + __IO uint32_t HTH : 32; /*!< Hash Table HighThis field contains the upper 32 bits of Hash + table. */ + } HASH_TABLE_HIGH_REG2_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HASH_TABLE_LOW_REG3; /*!< This is the operation mode register for the MAC. */ + + struct { + __IO uint32_t HTL : 32; /*!< Hash Table LowThis field contains the lower 32 bits of Hash + table. */ + } HASH_TABLE_LOW_REG3_b; /*!< BitSize */ + }; + + union { + __IO uint32_t GMII_ADDR_REG4; /*!< This is the operation mode register for the MAC. */ + + struct { + __IO uint32_t GB : 1; /*!< GMII Busy */ + __IO uint32_t GW : 1; /*!< GMII Write. When set this bit tells the PHY that this will be + a Write operation using the GMIIData register */ + __IO uint32_t CR : 3; /*!< CSR Clock Range. The CSR Clock Range selection determines the + clk_csr_i frequency and isused to decide the frequency of the + MDC clock */ + uint32_t : 1; + __IO uint32_t GR : 5; /*!< GMII RegisterThese bits select the desired GMII register in + the selected PHY device */ + __IO uint32_t PR : 5; /*!< Physical Layer AddressThis field tells which of the 32 possible + PHY devices are being accessed */ + } GMII_ADDR_REG4_b; /*!< BitSize */ + }; + + union { + __IO uint32_t GMII_DATA_REG5; /*!< This is the operation mode register for the MAC. */ + + struct { + __IO uint32_t GD : 16; /*!< GMII Data.This contains the 16-bit data value read from the + PHY after a Management Read operation or the 16-bit data value + to be written to the PHY before a ManagementWrite operation */ + } GMII_DATA_REG5_b; /*!< BitSize */ + }; + + union { + __IO uint32_t FLOW_CTRL_REG6; /*!< The Flow Control register controls the generation and reception + of the Control (Pause Command)frames by the GMAC's Flow control + module. */ + + struct { + __IO uint32_t FCB_BPA : 1; /*!< Flow Control Busy/Back pressure Activate */ + __IO uint32_t TFE : 1; /*!< Transmit Flow Control Enable */ + __IO uint32_t RFE : 1; /*!< Receive Flow Control Enable */ + __IO uint32_t UP : 1; /*!< Unicast Pause Frame Detect */ + __IO uint32_t PLT : 2; /*!< Pause Low Threshold */ + __IO uint32_t DZPQ : 1; /*!< Disable Zero-Quanta Pause */ + uint32_t : 9; + __IO uint32_t PT : 16; /*!< Pause Time */ + } FLOW_CTRL_REG6_b; /*!< BitSize */ + }; + + union { + __IO uint32_t VLAN_TAG_REG7; /*!< The Flow Control register controls the generation and reception + of the Control (Pause Command)frames by the GMAC's Flow control + module. */ + + struct { + __IO uint32_t VL : 16; /*!< VLAN Tag Identifier.This contains the 802.1Q VLAN Tag to identify + the VLAN frames, and is used tocompare with the 15th and 16th + bytes of the receiving frames for VLAN frames */ + } VLAN_TAG_REG7_b; /*!< BitSize */ + }; + __I uint32_t VERSION_REG8; /*!< The Version register s contents identify the version of the + core. */ + __I uint32_t RESERVED; + __IO uint32_t RMT_WKUP_FMFILTER_REG; /*!< This is the address through which the remote Wake-up Frame Filter + registers(wkupfmfilter_reg) are written/read by the Application.This + register contains the higher 16 bits of the 7th MAC address. + */ + + union { + __IO uint32_t PMT_CTRL_STS_REG; /*!< The PMT CSR program the request wake-up events and monitor the + wake-up events. */ + + struct { + __IO uint32_t PD : 1; /*!< When set, all received frames will be dropped */ + __IO uint32_t MPE : 1; /*!< Magic Packet Enable.When set, enables generation of a power + management event due to MagicPacket reception */ + __IO uint32_t WFE : 1; /*!< Wake-Up Frame Enable.When set, enables generation of a power + management event due to wakeupframe reception */ + uint32_t : 2; + __IO uint32_t MPR : 1; /*!< When set, this bit indicates the power management event was + generated bythe reception of a Magic Packet */ + __IO uint32_t WFR : 1; /*!< When set, this bit indicates the power management event was + generateddue to reception of a wake-up frame */ + uint32_t : 2; + __IO uint32_t GU : 1; /*!< When set, enables any unicast packet filtered by the GMAC (DAF) + addressrecognition to be a wake-up frame */ + uint32_t : 21; + __IO uint32_t WFFRPR : 1; /*!< When set, resets the Remote Wake-up Frame Filter register pointer + to000 */ + } PMT_CTRL_STS_REG_b; /*!< BitSize */ + }; + __I uint32_t RESERVED1[2]; + + union { + __I uint32_t INTR_STS_REG14; /*!< The Interrupt Status register contents identify the events in + the GMAC-CORE that can generateinterrupt */ + + struct { + __I uint32_t RGMII_INTR_STS : 1; /*!< This bit is set due to any change in value of the Link Status + of RGMII interface */ + __I uint32_t + PCS_LINK_STATUS_CHANGED : 1; /*!< This bit is set due to any change in Link Status in the TBI/RTBI/SGMII + PHYinterface */ + __I uint32_t PCS_AUTO_NEGOTIATION_COMPLETE : 1; /*!< This bit is set when the Auto-negotiation is completed in the + TBI/RTBI/SGMII PHYinterface */ + __I uint32_t PMT_INTR_STS : 1; /*!< This bit is set when the Auto-negotiation is completed in the + TBI/RTBI/SGMII PHYinterface */ + __I uint32_t MMC_INTR_STS : 1; /*!< This bit is set high whenever any of bits 7:5 is set high and + cleared only when all ofthese bits are low. */ + __I uint32_t MMC_RX_INTR_STS : 1; /*!< MMC Receive Interrupt Status */ + __I uint32_t MMC_TX_INTR_STS : 1; /*!< MMC Transmit Interrupt Status */ + __I uint32_t + MMC_RX_CH_OFF_INTR_STS : 1; /*!< MMC Receive Checksum Offload Interrupt Status */ + } INTR_STS_REG14_b; /*!< BitSize */ + }; + + union { + __IO uint32_t INTR_MASK_REG15; /*!< The Interrupt Mask Register bits enables the user to mask the + interrupt signal due to the correspondingevent in the Interrupt + Status Register */ + + struct { + __IO uint32_t RGMII_M : 1; /*!< This bit when set, will disable the assertion of the interrupt + signal due to the settingof RGMII Interrupt Status bit in Register14. */ + __IO uint32_t PCS_LINK_M : 1; /*!< This bit when set, will disable the assertion of the interrupt + signal due to the settingof RGMII Interrupt Status bit in Register14. */ + __IO uint32_t PCS_AN_COMPLETION_M : 1; /*!< This bit when set, will disable the assertion of the interrupt + signal due to the settingof RGMII Interrupt Status bit in Register14. */ + __IO uint32_t PMT_M : 1; /*!< This bit when set, will disable the assertion of the interrupt + signal due to the settingof PMT Interrupt Status bit in Register14 */ + } INTR_STS_REG15_b; /*!< BitSize */ + }; + + union { + __IO uint32_t MAC_ADDR0_HIGH_REG; /*!< The MAC Address0 High register holds the upper 16 bits of the + 6-byte first MAC address of the station */ + + struct { + __IO uint32_t MAC_ADDR0_HIGH : 16; /*!< This field contains the upper 16 bits (47:32) of the 6-byte + first MAC address */ + uint32_t : 15; + __I uint32_t MO : 1; /*!< Always 1 */ + } MAC_ADDR0_HIGH_REG_b; /*!< BitSize */ + }; + __IO uint32_t MAC_ADDR0_LOW_REG; /*!< The MAC Address0 Low register holds the lower 32 bits of the + 6-byte first MAC address of the station */ + ETHERNET_MAC_16_ADDR_Type + MAC_16_ADDR[15]; /*!< MAC_16_ADDR0 */ + + union { + __IO uint32_t AN_CTRL_REG48; /*!< The AN Control register enables and/or restarts auto-negotiation. */ + + struct { + uint32_t : 9; + __IO uint32_t RAN : 1; /*!< Restart Auto-Negotiation */ + uint32_t : 2; + __IO uint32_t ANE : 1; /*!< Auto-Negotiation Enable */ + uint32_t : 1; + __IO uint32_t ELE : 1; /*!< External Loopback Enable */ + uint32_t : 1; + __IO uint32_t ECD : 1; /*!< Enable Comma Detect */ + __IO uint32_t LR : 1; /*!< Enable Comma Detect */ + __IO uint32_t SGMII_RAL : 1; /*!< SGMII RAL Control */ + } AN_CTRL_REG48_b; /*!< BitSize */ + }; + + union { + __I uint32_t AN_CTRL_REG49; /*!< The AN Status register indicates the link and the auto-negotiation + status */ + + struct { + uint32_t : 2; + __I uint32_t LS : 1; /*!< Link Status */ + __I uint32_t ANA : 1; /*!< Auto-Negotiation Ability */ + uint32_t : 1; + __I uint32_t ANC : 1; /*!< Auto-Negotiation Complete */ + uint32_t : 2; + __I uint32_t ES : 1; /*!< Extended Status */ + } AN_CTRL_REG49_b; /*!< BitSize */ + }; + + union { + __IO uint32_t ANA_ADV_REG50; /*!< The Auto-Negotiation Advertisement register indicates the link + and the auto-negotiation status. */ + + struct { + uint32_t : 5; + __IO uint32_t FD : 1; /*!< Full-Duplex.This bit, when set high, indicates that the GMAC + supports Full-Duplex. */ + __IO uint32_t HD : 1; /*!< Half-Duplex */ + __IO uint32_t PSE : 2; /*!< Pause Encoding */ + uint32_t : 3; + __IO uint32_t RFE : 2; /*!< Remote Fault Encoding */ + uint32_t : 1; + __I uint32_t NP : 1; /*!< Next Page Support */ + } ANA_ADV_REG50_b; /*!< BitSize */ + }; + + union { + __I uint32_t ANL_PA_REG51; /*!< The Auto-Negotiation Link Partner Ability register contains + the advertised ability of the link partner */ + + struct { + uint32_t : 5; + __I uint32_t FD : 1; /*!< Full-Duplex.This bit, when set high, indicates that the GMAC + supports Full-Duplex. */ + __IO uint32_t HD : 1; /*!< Half-Duplex */ + __IO uint32_t PSE : 2; /*!< Pause Encoding */ + uint32_t : 3; + __IO uint32_t RFE : 2; /*!< Remote Fault Encoding */ + __IO uint32_t ACK : 1; /*!< Acknowledge */ + __I uint32_t NP : 1; /*!< Next Page Support */ + } ANL_PA_REG51_b; /*!< BitSize */ + }; + + union { + __I uint32_t ANE_REG52; /*!< The Auto-Negotiation Expansion register indicates whether a + new base page from the link partner hasbeen received */ + + struct { + uint32_t : 1; + __I uint32_t NPR : 1; /*!< New Page Received */ + __I uint32_t NPA : 1; /*!< Next Page Ability */ + } ANE_REG52_b; /*!< BitSize */ + }; + + union { + __I uint32_t TBI_EXT_STS_REG53; /*!< The TBI Extended Status Register register indicates all modes + of operation of the GMAC. */ + + struct { + uint32_t : 14; + __I uint32_t GHD : 1; /*!< 1000BASE-X Half-Duplex Capable */ + __I uint32_t GFD : 1; /*!< 1000BASE-X Full-Duplex Capable */ + } TBI_EXT_STS_REG53_b; /*!< BitSize */ + }; + + union { + __I uint32_t TBI_EXT_STS_REG54; /*!< The SGMII/RGMII Status register indicates the status signals + received by the SGMII/RGMII from the PHY */ + + struct { + __I uint32_t LINK_MODE : 1; /*!< Indicates the current mode of operation of the link */ + __I uint32_t LINK_SPEED : 2; /*!< Indicates the current speed of the link: */ + __I uint32_t LINK_STATUS : 1; /*!< Indicates whether the link is up 1 or down 0. */ + } TBI_EXT_STS_REG54_b; /*!< BitSize */ + }; + __I uint32_t RESERVED2[9]; + + union { + __IO uint32_t MMC_CTRL_REG; /*!< The MMC Control register establishes the operating mode of the + management counters. */ + + struct { + __IO uint32_t MMC_CR : 1; /*!< Counters Reset.When set, all counters will be reset. This bit + will be cleared automaticallyafter 1 clock cycle */ + __IO uint32_t MMC_CSR : 1; /*!< Counter Stop Roll over.When set, counter after reaching maximum + value will not roll over to zero. */ + __IO uint32_t MMC_RR : 1; /*!< Reset on Read. When set, counter after reaching maximum value + will not roll over to zero. */ + __IO uint32_t MMC_CF : 1; /*!< MMC Counter Freeze.When set, this bit freezes all the MMC counters + to their current value. */ + } MMC_CTRL_REG_b; /*!< BitSize */ + }; + + union { + __I uint32_t MMC_RX_INTR_REG; /*!< The MMC Receive Interrupt register maintains the interrupts + generated when receive statistic countersreach half their maximum + values */ + + struct { + __I uint32_t BIT_0 : 1; /*!< The bit is set when the rx framecount_gb counter reaches half + themaximum value */ + __I uint32_t BIT_1 : 1; /*!< The bit is set when the rxoctetcount_gb counter reaches half + the maximumvalue. */ + __I uint32_t BIT_2 : 1; /*!< The bit is set when the rxoctetcount_g counter reaches half + the maximumvalue. */ + __I uint32_t BIT_3 : 1; /*!< The bit is set when the rxbroadcastframes_g counter reaches + half themaximum value */ + __I uint32_t BIT_4 : 1; /*!< The bit is set when the rxmulticastframes_g counter reaches + half themaximum value. */ + __I uint32_t BIT_5 : 1; /*!< The bit is set when the rxcrcerror counter reaches half the + maximumvalue. */ + __I uint32_t BIT_6 : 1; /*!< The bit is set when the rxalignmenterror counter reaches half + themaximum value */ + __I uint32_t BIT_7 : 1; /*!< The bit is set when the rxrunterror counter reaches half the + maximumvalue. */ + __I uint32_t BIT_8 : 1; /*!< The bit is set when the rxjabbererror counter reaches half the + maximumvalue. */ + __I uint32_t BIT_9 : 1; /*!< The bit is set when the rxundersize_g counter reaches half the + maximumvalue. */ + __I uint32_t BIT_10 : 1; /*!< The bit is set when the rxoversize_g counter reaches half the + maximumvalue. */ + __I uint32_t BIT_11 : 1; /*!< The bit is set when the rx64octets_gb counter reaches half the + maximumvalue. */ + __I uint32_t BIT_12 : 1; /*!< The bit is set when the rx65to127octets_gb counter reaches half + themaximum value. */ + __I uint32_t BIT_13 : 1; /*!< The bit is set when the rx128to255octets_gb counter reaches + half themaximum value. */ + __I uint32_t BIT_14 : 1; /*!< The bit is set when the rx256to511octets_gb counter reaches + half themaximum value */ + __I uint32_t BIT_15 : 1; /*!< The bit is set when the rx512to1023octets_gb counter reaches + half themaximum value. */ + __I uint32_t BIT_16 : 1; /*!< The bit is set when the rx1024tomaxoctets_gb counter reaches + half themaximum value. */ + __I uint32_t BIT_17 : 1; /*!< The bit is set when the rxunicastframes_gb counter reaches half + themaximum value. */ + __I uint32_t BIT_18 : 1; /*!< The bit is set when the rx length error counter reaches half + the maximumvalue. */ + __I uint32_t BIT_19 : 1; /*!< The bit is set when the rx out of range type counter reaches + half themaximum value */ + __I uint32_t BIT_20 : 1; /*!< The bit is set when the rx pause frames counter reaches half + the maximum value */ + __I uint32_t BIT_21 : 1; /*!< The bit is set when the rx fifo overflow counter reaches half + the maximumvalue. */ + __I uint32_t BIT_22 : 1; /*!< The bit is set when the rxvlanframes_gb counter reaches half + themaximum value. */ + __I uint32_t BIT_23 : 1; /*!< The bit is set when the rx watchdog error counter reaches half + themaximum value. */ + } MMC_RX_INTR_REG_b; /*!< BitSize */ + }; + + union { + __I uint32_t MMC_TX_INTR_REG; /*!< The MMC Transmit Interrupt register maintains the interrupts + generated when transmit statisticcounters reach half their maximum + values */ + + struct { + __I uint32_t BIT_0 : 1; /*!< The bit is set when the txoctetcount_gb counter reaches half + the maximum value. */ + __I uint32_t BIT_1 : 1; /*!< The bit is set when the txframecount_gb counter reaches half + the maximum value. */ + __I uint32_t BIT_2 : 1; /*!< The bit is set when the txbroadcastframes_g counter reaches + half the maximum value. */ + __I uint32_t BIT_3 : 1; /*!< The bit is set when the txmulticastframes_g counter reaches + half the maximum value. */ + __I uint32_t BIT_4 : 1; /*!< The bit is set when the tx64to127octets_gb counter reaches half + the maximum value. */ + __I uint32_t BIT_5 : 1; /*!< The bit is set when the tx65to127octets_gb counter reaches half + the maximum value */ + __I uint32_t BIT_6 : 1; /*!< The bit is set when the tx128to255octets_gb counter reaches + half the maximum value. */ + __I uint32_t BIT_7 : 1; /*!< The bit is set when the tx256to511octets_gb counter reaches + half the maximum value. */ + __I uint32_t BIT_8 : 1; /*!< The bit is set when the tx512to1023octets_gb counter reaches + half the maximum value */ + __I uint32_t BIT_9 : 1; /*!< The bit is set when the tx1024tomaxoctets_gb counter reaches + half the maximum value */ + __I uint32_t BIT_10 : 1; /*!< The bit is set when the txunicastframes_gb counter reaches half + the maximum value. */ + __I uint32_t BIT_11 : 1; /*!< The bit is set when the txmulticastframes_gb counter reaches + half the maximum value. */ + __I uint32_t BIT_12 : 1; /*!< The bit is set when the txbroadcastframes_gb counter reaches + half the maximum value */ + __I uint32_t BIT_13 : 1; /*!< The bit is set when the txunderflowerror counter reaches half + the maximum value. */ + __I uint32_t BIT_14 : 1; /*!< The bit is set when the txsinglecol_g counter reaches half the + maximum value */ + __I uint32_t BIT_15 : 1; /*!< The bit is set when the txmulticol_g counter reaches half the + maximum value */ + __I uint32_t BIT_16 : 1; /*!< The bit is set when the txdeferred counter reaches half the + maximum value */ + __I uint32_t BIT_17 : 1; /*!< The bit is set when the txlatecol counter reaches half the maximum + value */ + __I uint32_t BIT_18 : 1; /*!< The bit is set when the txexesscol counter reaches half the + maximum value. */ + __I uint32_t BIT_19 : 1; /*!< The bit is set when the txcarriererror counter reaches half + the maximum value */ + __I uint32_t BIT_20 : 1; /*!< The bit is set when the txoctetcount_g counter reaches half + the maximum value */ + __I uint32_t BIT_21 : 1; /*!< The bit is set when the txframecount_g counter reaches half + the maximum value. */ + __I uint32_t BIT_22 : 1; /*!< The bit is set when the txoexcessdef counter reaches half the + maximum value */ + __I uint32_t BIT_23 : 1; /*!< The bit is set when the tx pause frames error counter reaches + half the maximum value. */ + __I uint32_t BIT_24 : 1; /*!< The bit is set when the txvlanframes_g counter reaches half + the maximum value */ + } MMC_TX_INTR_REG_b; /*!< BitSize */ + }; + + union { + __IO uint32_t MMC_RX_INTR_MASK_REG; /*!< MMC Receive Interrupt Mask register maintains the masks for + the interrupts generated whenreceive statistic counters reach + half their maximum value */ + + struct { + __I uint32_t BIT_0 : 1; /*!< Setting this bit masks the interrupt when the rxframecount_gb + counter reaches halfthe maximum value */ + __I uint32_t BIT_1 : 1; /*!< Setting this bit masks the interrupt when the rxoctetcount_gb + counter reaches halfthe maximum value */ + __I uint32_t BIT_2 : 1; /*!< Setting this bit masks the interrupt when the rxoctetcount_g + counter reaches half the maximumvalue. */ + __I uint32_t BIT_3 : 1; /*!< Setting this bit masks the interrupt when the rxbroadcastframes_g + counter reaches half themaximum value */ + __I uint32_t BIT_4 : 1; /*!< The bit is set when the rxmulticastframes_g counter reaches + half themaximum value. */ + __I uint32_t BIT_5 : 1; /*!< Setting this bit masks the interrupt when the rxcrcerror counter + reaches half the maximumvalue. */ + __I uint32_t BIT_6 : 1; /*!< The bit is set when the rxalignmenterror counter reaches half + themaximum value */ + __I uint32_t BIT_7 : 1; /*!< Setting this bit masks the interrupt when the rxrunterror counter + reaches half the maximumvalue. */ + __I uint32_t BIT_8 : 1; /*!< Setting this bit masks the interrupt when the rxjabbererror + counter reaches half the maximumvalue. */ + __I uint32_t BIT_9 : 1; /*!< Setting this bit masks the interrupt when the rxundersize_g + counter reaches half the maximumvalue. */ + __I uint32_t BIT_10 : 1; /*!< The bit is set when the rxoversize_g counter reaches half the + maximumvalue. */ + __I uint32_t BIT_11 : 1; /*!< Setting this bit masks the interrupt when the rx64octets_gb + counter reaches half the maximumvalue. */ + __I uint32_t BIT_12 : 1; /*!< Setting this bit masks the interruptwhen the rx65to127octets_gb + counter reaches half themaximum value. */ + __I uint32_t BIT_13 : 1; /*!< Setting this bit masks the interrupt when the rx128to255octets_gb + counter reaches half themaximum value. */ + __I uint32_t BIT_14 : 1; /*!< Setting this bit masks the interrupt when the rx256to511octets_gb + counter reaches half themaximum value */ + __I uint32_t BIT_15 : 1; /*!< Setting this bit masks the interrupt when the rx512to1023octets_gb + counter reaches half themaximum value. */ + __I uint32_t BIT_16 : 1; /*!< Setting this bit masks the interrupt when the rx1024tomaxoctets_gb + counter reaches half themaximum value. */ + __I uint32_t BIT_17 : 1; /*!< Setting this bit masks the interrupt when the rxunicastframes_gb + counter reaches half themaximum value. */ + __I uint32_t BIT_18 : 1; /*!< Setting this bit masks the interrupt when the rx length error + counter reaches half the maximumvalue. */ + __I uint32_t BIT_19 : 1; /*!< Setting this bit masks the interrupt when the rx out of range + type counter reaches half themaximum value */ + __I uint32_t BIT_20 : 1; /*!< Setting this bit masks the interrupt when the rxpauseframes + counter reaches halfthe maximum value */ + __I uint32_t BIT_21 : 1; /*!< Setting this bit masks the interrupt when the rxfifooverflow + counter reaches half themaximum value */ + __I uint32_t BIT_22 : 1; /*!< Setting this bit masks the interrupt when the rxvlanframes_gb + counter reaches halfthe maximum value */ + __I uint32_t BIT_23 : 1; /*!< Setting this bit masks the interrupt when the rxframecount_gb + counter reaches halfthe maximum value */ + } MMC_RX_INTR_MASK_REG_b; /*!< BitSize */ + }; + + union { + __IO uint32_t MMC_TX_INTR_MASK_REG; /*!< The MMC Transmit Interrupt Mask register maintains the masks + for the interrupts generated whentransmit statistic counters + reach half their maximum value */ + + struct { + __I uint32_t BIT_0 : 1; /*!< Setting this bit masks the interrupt when the txoctetcount_gb + counter reaches halfthe maximum value */ + __I uint32_t BIT_1 : 1; /*!< Setting this bit masks the interrupt when the txframecount_gb + counter reaches halfthe maximum value */ + __I uint32_t BIT_2 : 1; /*!< Setting this bit masks the interrupt when the txbroadcastframes_g + counter reaches half the maximum value. */ + __I uint32_t BIT_3 : 1; /*!< Setting this bit masks the interrupt when the txmulticastframes_g + counter reaches half the maximum value. */ + __I uint32_t BIT_4 : 1; /*!< Setting this bit masks the interrupt when the tx64to127octets_gb + counter reaches half the maximum value. */ + __I uint32_t BIT_5 : 1; /*!< Setting this bit masks the interrupt when the tx65to127octets_gb + counter reaches half the maximum value */ + __I uint32_t BIT_6 : 1; /*!< Setting this bit masks the interrupt when the tx128to255octets_gb + counter reaches half the maximum value. */ + __I uint32_t BIT_7 : 1; /*!< Setting this bit masks the interrupt when the tx256to511octets_gb + counter reaches half the maximum value. */ + __I uint32_t BIT_8 : 1; /*!< Setting this bit masks the interrupt when the tx512to1023octets_gb + counter reaches half the maximum value */ + __I uint32_t BIT_9 : 1; /*!< Setting this bit masks the interrupt when the tx1024tomaxoctets_gb + counter reaches half the maximum value */ + __I uint32_t BIT_10 : 1; /*!< Setting this bit masks the interrupt when the txunicastframes_gb + counter reaches half the maximum value. */ + __I uint32_t BIT_11 : 1; /*!< Setting this bit masks the interrupt when the txmulticastframes_gb + counter reaches half the maximum value. */ + __I uint32_t BIT_12 : 1; /*!< Setting this bit masks the interrupt when the txbroadcastframes_gb + counter reaches half the maximum value */ + __I uint32_t BIT_13 : 1; /*!< Setting this bit masks the interrupt when the txunderflowerror + counter reaches half the maximum value. */ + __I uint32_t BIT_14 : 1; /*!< Setting this bit masks the interrupt when the txsinglecol_g + counter reaches half the maximum value */ + __I uint32_t BIT_15 : 1; /*!< Setting this bit masks the interrupt when the txmulticol_g counter + reaches half the maximum value */ + __I uint32_t BIT_16 : 1; /*!< Setting this bit masks the interrupt when the txdeferred counter + reaches half the maximum value */ + __I uint32_t BIT_17 : 1; /*!< Setting this bit masks the interrupt when the txlatecol counter + reaches half the maximum value */ + __I uint32_t BIT_18 : 1; /*!< Setting this bit masks the interrupt when the txexesscol counter + reaches half the maximum value. */ + __I uint32_t BIT_19 : 1; /*!< Setting this bit masks the interrupt when the txcarriererror + counter reaches half the maximum value */ + __I uint32_t BIT_20 : 1; /*!< Setting this bit masks the interrupt when the txoctetcount_g + counter reaches half the maximum value */ + __I uint32_t BIT_21 : 1; /*!< Setting this bit masks the interrupt when the txframecount_g + counter reaches halfthe maximum value. */ + __I uint32_t BIT_22 : 1; /*!< Setting this bit masks the interrupt when the txoexcessdef counter + reaches half themaximum value. */ + __I uint32_t BIT_23 : 1; /*!< Setting this bit masks the interrupt when the txpauseframes + counter reaches halfthe maximum value. */ + __I uint32_t BIT_24 : 1; /*!< Setting this bit masks the interrupt when the txvlanframes_g + counter reaches halfthe maximum value. */ + } MMC_TX_INTR_MASK_REG_b; /*!< BitSize */ + }; + + __I uint32_t RESERVED3[59]; + + union { + __IO uint32_t MMC_RX_CHOFF_INTR_MASK_REG; /*!< The MMC Receive Checksum Offload Interrupt Mask register maintains + the masks for the interrupts generated when the receive IPC + (Checksum Offload) statistic counters reach half their maximum + value */ + + struct { + __IO uint32_t BIT_0 : 1; /*!< Setting this bit masks the interrupt when the rxipv4_gd_frms + counter reaches halfthe maximum value. */ + __IO uint32_t BIT_1 : 1; /*!< Setting this bit masks the interrupt when the rxipv4_gd_frms + counter reaches halfthe maximum value. */ + __IO uint32_t BIT_2 : 1; /*!< Setting this bit masks the interrupt when the rxipv4_gd_frms + counter reaches halfthe maximum value. */ + __IO uint32_t BIT_3 : 1; /*!< Setting this bit masks the interrupt when the rxipv4_frag_frms + counter reaches halfthe maximum value */ + __IO uint32_t BIT_4 : 1; /*!< Setting this bit masks the interrupt when the rxipv4_udsbl_frms + counter reacheshalf the maximum value */ + __IO uint32_t BIT_5 : 1; /*!< Setting this bit masks the interrupt when the rxipv6_gd_frms + counter reaches halfthe maximum value */ + __IO uint32_t BIT_6 : 1; /*!< Setting this bit masks the interrupt when the rxipv6_hdrerr_frms + counter reacheshalf the maximum value */ + __IO uint32_t BIT_7 : 1; /*!< Setting this bit masks the interrupt when the rxipv6_nopay_frms + counter reacheshalf the maximum value. */ + __IO uint32_t BIT_8 : 1; /*!< Setting this bit masks the interrupt when the rxudp_gd_frms + counter reaches halfthe maximum value */ + __IO uint32_t BIT_9 : 1; /*!< Setting this bit masks the interrupt when the rxudp_err_frms + counter reaches halfthe maximum value */ + __IO uint32_t BIT_10 : 1; /*!< Setting this bit masks the interrupt when the rxtcp_gd_frms + counter reaches halfthe maximum value */ + __IO uint32_t BIT_11 : 1; /*!< Setting this bit masks the interrupt when the rxtcp_err_frms + counter reaches halfthe maximum value */ + __IO uint32_t BIT_12 : 1; /*!< Setting this bit masks the interrupt when the rxicmp_gd_frms + counter reaches halfthe maximum value */ + __IO uint32_t BIT_13 : 1; /*!< Setting this bit masks the interrupt when the rxicmp_err_frms + counter reaches halfthe maximum value. */ + uint32_t : 2; + __IO uint32_t BIT_16 : 1; /*!< Setting this bit masks the interrupt when the rxipv4_gd_octets + counter reaches halfthe maximum value */ + __IO uint32_t BIT_17 : 1; /*!< Setting this bit masks the interrupt when the rxipv4_hdrerr_octets + counter reacheshalf the maximum value. */ + __IO uint32_t BIT_18 : 1; /*!< Setting this bit masks the interrupt when the rxipv4_nopay_octets + counter reacheshalf the maximum value. */ + __IO uint32_t BIT_19 : 1; /*!< Setting this bit masks the interrupt when the rxipv4_frag_octets + counter reacheshalf the maximum value */ + __IO uint32_t BIT_20 : 1; /*!< Setting this bit masks the interrupt when the rxipv4_udsbl_octets + counter reacheshalf the maximum value. */ + __IO uint32_t BIT_21 : 1; /*!< Setting this bit masks the interrupt when the rxipv6_gd_octets + counter reaches halfthe maximum value. */ + __IO uint32_t BIT_22 : 1; /*!< Setting this bit masks the interrupt when the rxipv6_hdrerr_octets + counter reacheshalf the maximum value. */ + __IO uint32_t BIT_23 : 1; /*!< Setting this bit masks the interrupt when the rxipv6_nopay_octets + counter reacheshalf the maximum value */ + __IO uint32_t BIT_24 : 1; /*!< Setting this bit masks the interrupt when the rxudp_gd_octets + counter reaches halfthe maximum value. */ + __IO uint32_t BIT_25 : 1; /*!< Setting this bit masks the interrupt when the rxudp_err_octets + counter reaches halfthe maximum value */ + __IO uint32_t BIT_26 : 1; /*!< Setting this bit masks the interrupt when the rxtcp_gd_octets + counter reaches halfthe maximum value. */ + __IO uint32_t BIT_27 : 1; /*!< Setting this bit masks the interrupt when the rxtcp_err_octets + counter reaches halfthe maximum value. */ + __IO uint32_t BIT_28 : 1; /*!< Setting this bit masks the interrupt when the rxicmp_gd_octets + counter reacheshalf the maximum value */ + __IO uint32_t BIT_29 : 1; /*!< Setting this bit masks the interrupt when the rxicmp_err_octets + counter reacheshalf the maximum value. */ + } MMC_RX_CHOFF_INTR_MASK_REG_b; /*!< BitSize */ + }; + + __I uint32_t RESERVED4; + union { + __I uint32_t MMC_RX_CHOFF_INTR_REG; /*!< The MMC Receive Checksum Offload Interrupt register maintains + the interrupts generated whenreceive IPC statistic counters + reach half their maximum values */ + + struct { + __I uint32_t BIT_0 : 1; /*!< The bit is set when the rxipv4_gd_frms counter reaches half + the maximum value */ + __I uint32_t BIT_1 : 1; /*!< The bit is set when the rxipv4_hdrerr_frms counter reaches half + the maximumvalue. */ + __I uint32_t BIT_2 : 1; /*!< The bit is set when the rxipv4_nopay_frms counter reaches half + the maximumvalue. */ + __IO uint32_t BIT_3 : 1; /*!< The bit is set when the rxipv4_frag_frms counter reaches half + the maximumvalue */ + __I uint32_t BIT_4 : 1; /*!< The bit is set when the rxipv4_udsbl_frms counter reaches half + the maximumvalue */ + __I uint32_t BIT_5 : 1; /*!< The bit is set when the rxipv6_gd_frms counter reaches half + the maximum value */ + __I uint32_t BIT_6 : 1; /*!< The bit is set when the rxipv6_hdrerr_frms counter reaches half + the maximumvalue. */ + __I uint32_t BIT_7 : 1; /*!< The bit is set when the rxipv6_nopay_frms counter reaches half + the maximumvalue */ + __I uint32_t BIT_8 : 1; /*!< The bit is set when the rxudp_gd_frms counter reaches half the + maximum value */ + __I uint32_t BIT_9 : 1; /*!< The bit is set when the rxudp_err_frms counter reaches half + the maximum value */ + __I uint32_t BIT_10 : 1; /*!< The bit is set when the rxtcp_gd_frms counter reaches half the + maximum value */ + __I uint32_t BIT_11 : 1; /*!< The bit is set when the rxtcp_err_frms counter reaches half + the maximum value. */ + __I uint32_t BIT_12 : 1; /*!< The bit is set when the rxicmp_gd_frms counter reaches half + the maximumvalue. */ + __I uint32_t BIT_13 : 1; /*!< The bit is set when the rxicmp_err_frms counter reaches half + the maximumvalue. */ + uint32_t : 2; + __I uint32_t BIT_16 : 1; /*!< The bit is set when the rxipv4_gd_octets counter reaches half + the maximumvalue */ + __I uint32_t BIT_17 : 1; /*!< The bit is set when the rxipv4_hdrerr_octets counter reaches + half the maximumvalue. */ + __I uint32_t BIT_18 : 1; /*!< The bit is set when the rxipv4_nopay_octets counter reaches + half the maximumvalue */ + __I uint32_t BIT_19 : 1; /*!< The bit is set when the rxipv4_frag_octets counter reaches half + the maximumvalue. */ + __I uint32_t BIT_20 : 1; /*!< The bit is set when the rxipv4_udsbl_octets counter reaches + half the maximumvalue. */ + __I uint32_t BIT_21 : 1; /*!< The bit is set when the rxipv6_gd_octets counter reaches half + the maximumvalue. */ + __I uint32_t BIT_22 : 1; /*!< The bit is set when the rxipv6_hdrerr_octets counter reaches + half the maximumvalue. */ + __I uint32_t BIT_23 : 1; /*!< The bit is set when the rxipv6_nopay_octets counter reaches + half the maximumvalue. */ + __I uint32_t BIT_24 : 1; /*!< The bit is set when the rxudp_gd_octets counter reaches half + the maximumvalue. */ + __I uint32_t BIT_25 : 1; /*!< The bit is set when the rxudp_err_octets counter reaches half + the maximumvalue */ + __I uint32_t BIT_26 : 1; /*!< The bit is set when the rxtcp_gd_octets counter reaches half + the maximumvalue. */ + __I uint32_t BIT_27 : 1; /*!< The bit is set when the rxtcp_err_octets counter reaches half + the maximumvalue. */ + __I uint32_t BIT_28 : 1; /*!< The bit is set when the rxicmp_gd_octets counter reaches half + the maximumvalue */ + __I uint32_t BIT_29 : 1; /*!< The bit is set when the rxicmp_err_octets counter reaches half + the maximumvalue. */ + } MMC_RX_CHOFF_INTR_REG_b; /*!< BitSize */ + }; + __I uint32_t RESERVED5[382]; + ETHERNET_MAC_31_ADDR_Type + MAC_31_ADDR[15]; /*!< MAC_31_ADDR0 */ + __I uint32_t RESERVED6[481]; + + union { + __IO uint32_t BUS_MODE_REG0; /*!< The Bus Mode register establishes the bus operating modes for + the DMA. */ + + struct { + __IO uint32_t SWR : 1; /*!< Software Reset */ + __IO uint32_t DA : 1; /*!< DMA Arbitration scheme */ + __IO uint32_t DSL : 5; /*!< Descriptor Skip Length */ + uint32_t : 1; + __IO uint32_t PBL : 6; /*!< Programmable Burst Length.These bits indicate the maximum number + of beats to be transferred in one DMAtransaction */ + __IO uint32_t PR : 2; /*!< Rx:Tx priority ratio */ + __IO uint32_t FB : 1; /*!< Fixed Burst */ + __IO uint32_t RPBL : 6; /*!< RxDMA PBL */ + __IO uint32_t USP : 1; /*!< Use Separate PBL */ + __IO uint32_t PBL_MODE : 1; /*!< When set high, this bit multiplies the PBL value programmed + four times */ + __IO uint32_t AAL : 1; /*!< Address-Aligned Beats */ + } BUS_MODE_REG0_b; /*!< BitSize */ + }; + + union { + __IO uint32_t TX_POLL_DEMAND_REG1; /*!< The Transmit Poll Demand register enables the Transmit DMA to + check whether or not the currentdescriptor is owned by DMA */ + + struct { + __IO uint32_t TPD : 32; /*!< Transmit Poll Demand */ + } TX_POLL_DEMAND_REG1_b; /*!< BitSize */ + }; + + union { + __IO uint32_t RX_POLL_DEMAND_REG; /*!< The Receive Poll Demand register enables the receive DMA to + check for new descriptors */ + + struct { + __IO uint32_t RPD : 32; /*!< Receive Poll Demand */ + } RX_POLL_DEMAND_REG_b; /*!< BitSize */ + }; + + union { + __IO uint32_t RC_DESC_LIST_ADDR_REG3; /*!< The Receive Descriptor List Address register points to the start + of the Receive Descriptor List */ + + struct { + __I uint32_t START_RX_LIST : 32; /*!< This field contains the base address of the First Descriptor + in the Receive Descriptor list. */ + } RC_DESC_LIST_ADDR_REG3_b; /*!< BitSize */ + }; + + union { + __IO uint32_t TX_DESC_LIST_ADDR_REG4; /*!< The Receive Descriptor List Address register points to the start + of the Receive Descriptor List */ + + struct { + __I uint32_t START_TX_LIST : 32; /*!< This field contains the base address of the First Descriptor + in the Transmit Descriptor list. */ + } TX_DESC_LIST_ADDR_REG4_b; /*!< BitSize */ + }; + + union { + __IO uint32_t STATUS_REG5; /*!< The Status register contains all the status bits that the DMA + reports to the host */ + + struct { + __IO uint32_t TI : 1; /*!< Transmit Interrupt.This bit indicates that frame transmission + is finished and TDES1 31 is set inthe First Descriptor. */ + __IO uint32_t TPS : 1; /*!< Transmit Process Stopped */ + __IO uint32_t TU : 1; /*!< Transmit Buffer Unavailable */ + __IO uint32_t TJT : 1; /*!< Transmit Jabber Time out */ + __IO uint32_t OVF : 1; /*!< Receive Overflow */ + __IO uint32_t UNF : 1; /*!< Transmit Underflow */ + __IO uint32_t RI : 1; /*!< Receive Interrupt */ + __IO uint32_t RU : 1; /*!< Receive Buffer Unavailable */ + __IO uint32_t RPS : 1; /*!< Receive Process Stopped */ + __IO uint32_t RWT : 1; /*!< Receive Watchdog Time out */ + __IO uint32_t ETI : 1; /*!< Early Transmit Interrupt */ + uint32_t : 2; + __IO uint32_t FBI : 1; /*!< Fatal Bus Error Interrupt */ + __IO uint32_t ERI : 1; /*!< Early Receive Interrupt */ + __IO uint32_t AIS : 1; /*!< Abnormal Interrupt Summary */ + __IO uint32_t NIS : 1; /*!< Normal Interrupt Summary */ + __I uint32_t RS : 3; /*!< Receive Process State */ + __I uint32_t TS : 3; /*!< Transmit Process State */ + __I uint32_t EB_23 : 1; /*!< Error Bits.These bits indicate the type of error that caused + a Bus Error */ + __I uint32_t EB_24 : 1; /*!< Error Bits.These bits indicate the type of error that caused + a Bus Error */ + __I uint32_t EB_25 : 1; /*!< Error Bits.These bits indicate the type of error that caused + a Bus Error */ + __I uint32_t GLI : 1; /*!< GMAC Line interface Interrupt */ + __I uint32_t GMI : 1; /*!< GMAC MMC Interrupt */ + __I uint32_t GPI : 1; /*!< GMAC PMT Interrupt */ + } STATUS_REG5_b; /*!< BitSize */ + }; + + union { + __IO uint32_t OPR_MODE_REG6; /*!< The Operation Mode register establishes the Transmit and Receive + operating modes and commands */ + + struct { + uint32_t : 1; + __IO uint32_t SR : 1; /*!< Start/Stop Receive */ + __IO uint32_t OSF : 1; /*!< Operate on Second Frame */ + __I uint32_t RTC : 2; /*!< Receive Threshold Control.These two bits control the threshold + level of the MTL Receive FIFO. */ + uint32_t : 1; + __IO uint32_t FUF : 1; /*!< Forward Undersized Good Frames */ + __IO uint32_t FEF : 1; /*!< Forward Error Frames */ + __IO uint32_t EFC : 1; /*!< Enable HW flow control */ + __IO uint32_t RFA : 2; /*!< Threshold for activating flow control */ + __IO uint32_t RFD : 2; /*!< Threshold for deactivating flow control */ + __IO uint32_t ST : 1; /*!< Start/Stop Transmission Command */ + __IO uint32_t TTC : 3; /*!< Transmit Threshold Control */ + uint32_t : 3; + __IO uint32_t FTF : 1; /*!< When this bit is set, the transmit FIFO controller logic is + reset to its defaultvalues and thus all data in the Tx FIFO + is lost/flushed */ + __IO uint32_t TSF : 1; /*!< Transmit Store and Forward */ + __IO uint32_t RFD_2 : 1; /*!< MSB of Threshold for Deactivating Flow Control */ + __IO uint32_t RFA_2 : 1; /*!< MSB of Threshold for Activating Flow Control */ + __IO uint32_t DFF : 1; /*!< Disable Flushing of Received Frames */ + __IO uint32_t RSF : 1; /*!< Receive Store and Forward */ + __IO uint32_t DT : 1; /*!< Disable Dropping of TCP/IP Checksum Error Frames */ + } OPR_MODE_REG6_b; /*!< BitSize */ + }; + + union { + __IO uint32_t IER_REG7; /*!< The Interrupt Enable register enables the interrupts reported + by Register5 */ + + struct { + __IO uint32_t TIE : 1; /*!< Transmit Interrupt Enable */ + __IO uint32_t TSE : 1; /*!< Transmit Stopped Enable */ + __IO uint32_t TUE : 1; /*!< Transmit Buffer Unavailable Enable */ + __IO uint32_t TJE : 1; /*!< Transmit Jabber Time out Enable */ + __IO uint32_t OVE : 1; /*!< Overflow Interrupt Enable */ + __IO uint32_t UNE : 1; /*!< Underflow Interrupt Enable */ + __IO uint32_t RIE : 1; /*!< Receive Interrupt Enable */ + __IO uint32_t RUE : 1; /*!< Receive Buffer Unavailable Enable */ + __IO uint32_t RSE : 1; /*!< Receive Stopped Enable */ + __IO uint32_t RWE : 1; /*!< Receive Watchdog Time out Enable */ + __IO uint32_t ETE : 1; /*!< Early Transmit Interrupt Enable */ + uint32_t : 2; + __IO uint32_t FBE : 1; /*!< Fatal Bus Error Enable */ + __IO uint32_t ERE : 1; /*!< Early Receive Interrupt Enable */ + __IO uint32_t AIE : 1; /*!< Abnormal Interrupt Summary Enable */ + __IO uint32_t NIE : 1; /*!< Normal Interrupt Summary Enable */ + } IER_REG7_b; /*!< BitSize */ + }; + + union { + __IO uint32_t MFBOC_REG8; /*!< The Interrupt Enable register enables the interrupts reported + by Register5 */ + + struct { + __IO uint32_t TIE : 16; /*!< Indicates the number of frames missed by the controller due + to the Host ReceiveBuffer being unavailable */ + __IO uint32_t OVERFLOW_BIT_M : 1; /*!< Overflow bit for Missed Frame Counter */ + __IO uint32_t MISSEED_FRAMES : 11; /*!< Indicates the number of frames missed by the application */ + __IO uint32_t OVERFLOW_BIT_FIFO : 1; /*!< Overflow bit for Missed Frame Counter */ + } MFBOC_REG8_b; /*!< BitSize */ + }; + __I uint32_t RESERVED7[9]; + __I uint32_t CHTX_DESC_REG18; /*!< Host Transmit Descriptor Address Pointer Cleared on Reset. Pointer + updated by DMA during operationBuffer being unavailable */ + __I uint32_t CHRX_DESC_REG19; /*!< Host Receive Descriptor Address PointerCleared on Reset. Pointer + updated by DMA during operation */ + __I uint32_t CHRX_DESC_REG20; /*!< Host Transmit Buffer Address PointerCleared on Reset. Pointer + updated by DMA during operation */ + __I uint32_t CHRX_BUF_ADDR_REG21; /*!< Host Receive Buffer Address PointerCleared on Reset. Pointer + updated by DMA during operation */ +} ETHERNET_Type; + +/* =========================================================================================================================== */ +/* ================ EGPIO ================ */ +/* =========================================================================================================================== */ + +/** + * @brief ENHANCED GENERAL PERPOSE INPUT/OUTPUT (EGPIO) + */ + +typedef struct { /*!< (@ 0x46130000) EGPIO Structure */ + __IOM EGPIO_PIN_CONFIG_Type + PIN_CONFIG[80]; /*!< (@ 0x00000000) [0..79] */ + __IM uint32_t RESERVED[704]; + __IOM EGPIO_PORT_CONFIG_Type + PORT_CONFIG[6]; /*!< (@ 0x00001000) [0..5] */ + __IM uint32_t RESERVED1[80]; + __IOM EGPIO_INTR_Type INTR[6]; /*!< (@ 0x00001200) [0..5] */ + __IM uint32_t RESERVED2[4]; + __IOM EGPIO_GPIO_GRP_INTR_Type + GPIO_GRP_INTR[4]; /*!< (@ 0x00001240) [0..3] */ +} EGPIO_Type; /*!< Size = 4704 (0x1260) */ + +typedef struct { /*!< SDIO structure */ + + union { + __IO uint32_t SDIO_INTR_FN1_STATUS_CLEAR_REG; /*!< SDIO Function1 Interrupt Enable Register */ + + struct { + __IO uint32_t + SDIO_WR_INT_CLR : 1; /*!< This bit is used to enable CMD53 write interrupt. =1 Interrupt is enabled =0 - Interrupt is disabled */ + __IO uint32_t SDIO_RD_INT_CLR : 1; /*!< This bit is used to enable CMD53 read interrupt */ + __IO uint32_t SDIO_CSA_INT_CLR : 1; /*!< This bit is used to enable CMD53 CSA interrupt */ + __IO uint32_t SDIO_CMD52_INT_CLR : 1; /*!< This bit is used to enable CMD52 interrupt. */ + __IO uint32_t SDIO_PWR_LEV_INT_CLR : 1; /*!< This bit is used to enable power level change interrupt. */ + __IO uint32_t SDIO_CRC_ERR_INT_CLR : 1; /*!< This bit is used to enable CRC error interrupt.*/ + __IO uint32_t SDIO_ABORT_INT_CLR : 1; /*!< This bit is used to enable abort interrupt */ + __IO uint32_t SDIO_TOUT_INT_CLR : 1; /*!< This bit is used to enable ?read FIFO wait time over? interrupt. */ + } SDIO_INTR_FN1_STATUS_CLEAR_REG_b; + }; + + union { + __IO uint32_t SDIO_INTR_FN1_ENABLE_REG; /*!< SDIO Function1 Interrupt Enable Register */ + + struct { + __IO uint32_t + SDIO_WR_INT_EN : 1; /*!< This bit is used to enable CMD53 write interrupt. =1 Interrupt is enabled =0 - Interrupt is disabled */ + __IO uint32_t SDIO_RD_INT_EN : 1; /*!< This bit is used to enable CMD53 read interrupt */ + __IO uint32_t SDIO_CSA_INT_EN : 1; /*!< This bit is used to enable CMD53 CSA interrupt */ + __IO uint32_t SDIO_CMD52_INT_EN : 1; /*!< This bit is used to enable CMD52 interrupt. */ + __IO uint32_t SDIO_PWR_LEV_INT_EN : 1; /*!< This bit is used to enable power level change interrupt. */ + __IO uint32_t SDIO_CRC_ERR_INT_EN : 1; /*!< This bit is used to enable CRC error interrupt.*/ + __IO uint32_t SDIO_ABORT_INT_EN : 1; /*!< This bit is used to enable abort interrupt */ + __IO uint32_t SDIO_TOUT_INT_EN : 1; /*!< This bit is used to enable ?read FIFO wait time over? interrupt. */ + } SDIO_INTR_FN1_ENABLE_REG_b; + }; + union { + __IO uint32_t SDIO_INTR_FN1_MASK_REG; /*!< SDIO Function1 Interrupt Mask Register */ + struct { + __IO uint32_t SDIO_WR_INT_MSK : 1; /*!< This bit is used to mask CMD53 write interrupt. */ + __IO uint32_t SDIO_RD_INT_MSK : 1; /*!< This bit is used to mask CMD53 read interrupt */ + __IO uint32_t + SDIO_CSA_MSK : 1; /*!< This bit is used to mask CMD53 CSA interrupt.Setting this bit will mask the interrupt Clearing this bit has no effect */ + __IO uint32_t SDIO_CMD52_MSK : 1; /*!< This bit is used to mask CMD52 interrupt */ + __IO uint32_t SDIO_PWR_LEV_MSK : 1; /*!< This bit is used to mask power level change interrupt */ + __IO uint32_t SDIO_CRC_ERR_MSK : 1; /*!< This bit is used to mask CRC error interrupt */ + __IO uint32_t + SDIO_ABORT_MSK : 2; /*!< This bit is used to mask abort interrupt Setting this bit will mask the interrupt Clearing this bit has no effect */ + __IO uint32_t SDIO_TOUT_MSK : 1; /*!< This bit is used to mask "read FIFO wait time over" interrupt */ + } SDIO_INTR_FN1_MASK_REG_b; + }; + union { + __IO uint32_t SDIO_INTR_FN1_UNMASK_REG; /*!< SDIO Function1 Interrupt Unmask Register */ + struct { + __IO uint32_t SDIO_WR_INT_UNMSK : 1; /*!< This bit is used to unmask CMD53 write interrupt. */ + __IO uint32_t SDIO_RD_INT_UNMSK : 1; /*!< This bit is used to unmask CMD53 read interrupt */ + __IO uint32_t SDIO_CSA_UNMSK : 1; /*!< This bit is used to unmask CMD53 CSA interrupt */ + __IO uint32_t SDIO_CMD52_UNMSK : 1; /*!< This bit is used to unmask CMD52 interrupt */ + __IO uint32_t SDIO_PWR_LEV_UNMSK : 1; /*!< This bit is used to unmask power level change interrupt */ + __IO uint32_t SDIO_CRC_ERR_UNMSK : 1; /*!< This bit is used to unmask CRC error interrupt. */ + __IO uint32_t SDIO_ABORT_UNMSK : 2; /*!< This bit is used to unmask abort interrupt */ + __IO uint32_t SDIO_TOUT_UNMSK : 1; /*!< This bit is used to unmask ?read FIFO wait time over? interrupt */ + } SDIO_INTR_FN1_UNMASK_REG_b; + }; + union { + __I uint32_t SDIO_BLK_LEN_REG; /*!< SDIO Block Length Register */ + struct { + __I uint32_t SDIO_BLK_LEN : 12; /*!< Length of each block for the last received CMD53 */ + uint32_t : 4; /*!< reseerved for future use */ + } SDIO_BLK_LEN_REG_b; + }; + + union { + __I uint32_t SDIO_BLK_CNT_REG; /*!Copyright 2020 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +#ifndef __BASE_TYPES_H__ +#define __BASE_TYPES_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include +#include "stdint.h" +#include +#include +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ +#ifndef TRUE +/** Value is true (boolean_t type) */ +#define TRUE 1 +#endif + +#ifndef FALSE +/** Value is false (boolean_t type) */ +#define FALSE 0 +#endif + +#ifndef MIN +/** Returns the minimum value out of two values */ +#define MIN(X, Y) ((X) < (Y) ? (X) : (Y)) +#endif +#ifndef MAX +/** Returns the maximum value out of two values */ +#define MAX(X, Y) ((X) > (Y) ? (X) : (Y)) +#endif +/** Returns the dimension of an array */ +#define DIM(X) (sizeof(X) / sizeof(X[0])) + +#ifndef BIT +#define BIT(x) ((uint32_t)1U << (x)) +#endif +typedef enum en { Enable = 1, Disable = 0 } en_t; +/****************************************************************************** + * Global type definitions + ******************************************************************************/ + +/** logical datatype (only values are TRUE and FALSE) */ +typedef uint8_t boolean_t; + +/** single precision floating point number (4 byte) */ +typedef float float32_t; + +/** double precision floating point number (8 byte) */ +typedef double float64_t; + +/** ASCCI character for string generation (8 bit) */ +typedef char char_t; + +/** function pointer type to void/void function */ +typedef void (*func_ptr_t)(void); + +/** function pointer type to void/uint8_t function */ +typedef void (*func_ptr_arg1_t)(uint8_t); + +#define RSI_DRIVER_VERSION_MAJOR_MINOR(major, minor) (((major) << 8) | (minor)) + +/** +\brief Driver Version + */ +typedef struct _RSI_DRIVER_VERSION { + uint16_t api; ///< API version + uint16_t drv; ///< Driver version +} RSI_DRIVER_VERSION_M4; + +/* General return codes */ +#define RSI_DRIVER_OK 0 ///< Operation succeeded +#define RSI_DRIVER_ERROR -1 ///< Unspecified error +#define RSI_DRIVER_ERROR_BUSY -2 ///< Driver is busy +#define RSI_DRIVER_ERROR_TIMEOUT -3 ///< Timeout occurred +#define RSI_DRIVER_ERROR_UNSUPPORTED -4 ///< Operation not supported +#define RSI_DRIVER_ERROR_PARAMETER -5 ///< Parameter error +#define RSI_DRIVER_ERROR_SPECIFIC -6 ///< Start of driver specific errors + +#define SET_BIT(n) BIT(n) //((uint32_t)1 << n) +#define CLR_BIT(n) ~BIT(n) //(~((uint32_t)1 << n)) + +#ifndef STATIC +#define STATIC static +#endif + +#ifndef INLINE +#ifdef __CC_ARM +#define INLINE __inline +#else +#define INLINE inline +#endif +#endif + +#define ENABLE 1 +#define DISABLE 0 + +#ifdef __cplusplus +} +#endif + +#endif /* __BASE_TYPES_H__ */ + +/******************************************************************************/ +/* EOF */ +/******************************************************************************/ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/data_types.h b/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/data_types.h new file mode 100644 index 000000000..8f85152c5 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/data_types.h @@ -0,0 +1,78 @@ +/******************************************************************************* +* @file data_types.h +* @brief +******************************************************************************* +* # License +* Copyright 2020 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ +/** @file data_types.h + * + * @brief This file contains data types defines + * + */ + +#ifndef DATA_TYPES_H +#define DATA_TYPES_H + +#include + +//! unsigned char is mapped to uint8 +typedef uint8_t uint8; +//! char is mapped to int8 +typedef int8_t int8; +//! unsigned short int is mapped as uint16 +typedef uint16_t uint16; +//! short int is mapped as int16 +typedef int16_t int16; +//! unsigned int is mapped as uint32 +typedef uint32_t uint32; +//! int is mapped as uint32 +typedef int32_t int32; + +#ifdef SINGLE_IMAGE + +typedef unsigned char UINT8; +typedef char INT8; +typedef unsigned short UINT16; + +typedef char STR; /* 8-bit character */ +typedef unsigned short WSTR; /* 16-bit character */ +typedef unsigned char BYTE; /* 8-bit unsigned integer */ +typedef unsigned char UINT08; /* 8-bit unsigned integer */ +typedef signed char INT08; /* 8-bit signed integer */ +typedef signed short INT16; /* 16-bit signed integer */ +typedef unsigned int UINT32; /* 32-bit unsigned integer */ +typedef signed int INT32; /* 32-bit signed integer */ +typedef unsigned long long UINT64; /* 64-bit unsigned integer */ +typedef signed long long INT64; /* 64-bit signed integer */ +typedef unsigned long ULONG; /* 32-bit long unsigned. */ +typedef long LONG; /* 32-bit long signed. */ +typedef int INTSTK; /* Defines CPU stack word size (in octets). */ +typedef int INTBOOL; +typedef unsigned long SIZE_T; +typedef float FLOAT32; /* 32-bit floating point */ +typedef double FLOAT64; /* 64-bit floating point */ +typedef int INTERR; + +typedef volatile BYTE REG_BYTE; /* 8-bit register */ +typedef volatile UINT16 REG_WORD16; /* 8-bit register */ +typedef volatile UINT32 REG_WORD32; + +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef short SHORT; +typedef unsigned short USHORT; +#endif /* SINGLE_IMAGE */ + +#endif diff --git a/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/rsi_ccp_common.h b/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/rsi_ccp_common.h new file mode 100644 index 000000000..8caf44cdd --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/rsi_ccp_common.h @@ -0,0 +1,23 @@ +/******************************************************************************* +* @file rsi_cpp_common.h +* @brief +******************************************************************************* +* # License +* Copyright 2020 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ +#include "rsi_ccp_user_config.h" +#ifdef SLI_SI917 +#include "si91x_device.h" +#include "RTE_Device_917.h" +#else +#include "RS1xxxx.h" +#endif diff --git a/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/rsi_error.h b/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/rsi_error.h new file mode 100644 index 000000000..8b208062a --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/rsi_error.h @@ -0,0 +1,258 @@ +/******************************************************************************* +* @file rsi_error.h +* @brief +******************************************************************************* +* # License +* Copyright 2020 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +#include + +#ifndef __RSI_ERROR_H__ +#define __RSI_ERROR_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum errnoCode { + RSI_FAIL = -1, + RSI_OK = 0, + INVALID_PARAMETERS, + + /*USART error codes*/ + ERROR_USART_BASE = 0x100, + ERROR_USART_CALLBACK_ERR = ERROR_USART_BASE + 1, + ERROR_USART_NOT_SUPPORTED, + + /* GPDMA error codes */ + ERROR_GPDMA_BASE = 0x200, + ERROR_GPDMA_INVALIDCHNLNUM = ERROR_GPDMA_BASE + 1, + ERROR_GPDMA_FLW_CTRL, + ERROR_GPDMA_BURST, + ERROR_GPDMA_SRC_ADDR, + ERROR_GPDMA_DST_ADDR, + NOERR_GPDMA_FLAG_SET, + ERROR_GPDMA_INVALID_EVENT, + ERROR_GPDMA_INVALID_XFERMODE, + ERROR_GPDMA_INVALID_TRANS_LEN, + ERROR_GPDMA_INVALID_ARG, + ERROR_GPDMA_CHNL_BUSY, + ERROR_GPDMA_NOT_ALIGNMENT, + ERROR_GPDMA_QUEUE_EMPTY, + ERROR_GPDMA_GENERAL, + + /* UDMA error codes */ + ERROR_UDMA_BASE = 0x300, + ERROR_UDMA_INVALIDCHNLNUM = ERROR_UDMA_BASE + 1, + ERROR_UDMA_CTRL_BASE_INVALID, + ERROR_UDMA_INVALID_XFERMODE, + ERROR_UDMA_INVALID_TRANS_LEN, + ERROR_UDMA_INVALID_ARG, + ERROR_UDMA_SRC_ADDR, + ERROR_UDMA_DST_ADDR, + ERROR_UDMA_CHNL_BUSY, + + /* I2C error codes */ + ERROR_I2C_BASE = 0x400, + ERROR_I2C_INVALID_ARG = ERROR_I2C_BASE + 1, + ERROR_I2CS_UNKNOWN, + ERROR_I2C_SPIKE_LOGIC, + ERROR_I2C_IGNORE_GC_OR_START, + ERROR_I2C_STATUS_FLAG_NOT_SET, + ERROR_I2C_BUSY_FLAG, + ERROR_I2C_MST_BUSY_FLAG, + ERROR_I2C_SLV_BUSY_FLAG, + ERROR_I2C_SLV_DIS_WHILE_BUSY, + ERROR_I2C_MST_XFER_ABORT, + ERROR_I2C_MST_TX_CMD_BLOCK, + ERROR_I2C_SLV_RX_DATA_LOST, + ERROR_I2C_NO_TX_DATA, + ERROR_I2C_NO_INTR_FLAG, + ERROR_I2C_ERROR_FLAG_NONE, + ERROR_I2C_INVALID_CB, + ERROR_I2C_INVALID_POINTER, + ERROR_I2C_GENERAL_FAILURE, + ERROR_I2C_TXABORT, + ERROR_I2C_SCL_STUCK_ATLOW, + ERROR_I2C_MST_ON_HOLD, + ERROR_I2C_BUFFER_OVERFLOW, + ERROR_I2C_BUFFER_UNDERFLOW, + + /* I2S error codes */ + ERROR_I2S_BASE = 0x500, + ERROR_I2S_INVALID_ARG = ERROR_I2S_BASE + 1, + ERROR_I2S_INVALID_RES, + ERROR_I2S_INVALID_LENGTH, + ERROR_I2S_BUSY, + ERROR_I2S_TXOVERRUN, + ERROR_I2S_RXOVERRUN, + ERROR_I2S_TXCOMPLETE, + ERROR_I2S_RXCOMPLETE, + + /* UART error codes */ + ERROR_UART_BASE = 0x600, + ERROR_UART_INVALID_ARG = ERROR_UART_BASE + 1, + ERROR_UART_INVALID_RES, + + /* PWM error codes */ + ERROR_PWM_BASE = 0x700, + ERROR_PWM_INVALID_CHNLNUM = ERROR_PWM_BASE + 1, + ERROR_PWM_INVALID_PWMOUT, + ERROR_PWM_NO_INTR, + ERROR_PWM_INVALID_ARG, + + /* Timers error codes */ + ERROR_TIMER_BASE = 0x800, + ERROR_INVAL_TIMER_NUM = ERROR_TIMER_BASE + 1, + ERROR_INVAL_TIMER_MODE, + ERROR_INVAL_TIMERTYPE, + ERROR_INVAL_COUNTER_DIR, + + /* SCT error codes */ + ERROR_CT_BASE = 0x900, + ERROR_CT_INVALID_COUNTER_NUM = ERROR_CT_BASE + 1, + ERROR_CT_INVALID_ARG, + + /* EFUSE ERROR CODES */ + ERROR_EFUSE_BASE = 0xA00, + ERROR_EFUSE_INVALID_WRITE_ADDRESS = ERROR_EFUSE_BASE + 1, + ERROR_EFUSE_INVALID_WRITE_BIT_POSITION, + ERROR_EFUSE_INVALID_PARAMETERS, + + /* CCI ERROR CODES */ + ERROR_CCI_BASE_ADDRESS = 0xB00, + ERROR_CCI_INIT_FAIL = ERROR_CCI_BASE_ADDRESS + 1, + ERROR_CCI_ADDRESS_ERR, + + /* QEI ERROR CODES */ + ERROR_QEI_BASE = 0xC00, + ERROR_INVALID_WRITE_ADDRESS = ERROR_QEI_BASE + 1, + ERROR_INVALID_WRITE_BIT_POSITION, + ERROR_INVALID_PARAMETERS, + + /* SDIO ERROR CODES */ + ERROR_SSDIO_BASE_ADDRESS = 0xD00, /*!< SDIO Error base address */ + ERROR_SSDIO_INIT_FAIL = ERROR_SSDIO_BASE_ADDRESS + 1, + ERROR_SSDIO_ADDRESS_ERR, + ERROR_SSDIO_INVALID_FN, + ERROR_SSDIO_INVALID_PARAM, + + /* SPI ERROR CODES*/ + ERROR_SSPI_BASE_ADDRESS = 0xE00, + ERROR_SSPI_INIT_FAIL = ERROR_SSPI_BASE_ADDRESS + 1, + ERROR_SSPI_ADDRESS_ERR, + ERROR_SSPI_CB_ERROR, + + /* ETHERNET ERROR CODES */ + ERROR_ETH_BASE_ADDRESS = 0xF00, + ERROR_ETH_INIT_FAIL = ERROR_ETH_BASE_ADDRESS + 1, + ERROR_ETH_PARAM, + ERROR_ETH_NULL, + ERR_DMA_NOT_ALIGNMENT, + ERROR_ETH_CALLBACK_ERR, + + /*CAN ERROR CODES*/ + ERROR_CAN_BASE = 0x1000, + ERROR_CAN_INVALID_PARAMETERS = ERROR_CAN_BASE + 1, + ERROR_CAN_INVALID_TIMING_PARAMETERS, + ERROR_CAN_OPERATION_IN_PROGRESS, + + /*GSPI ERROR CODES*/ + ERROR_GSPI_BASE = 0x1100, + ERROR_GSPI_INVALID_ARG = ERROR_GSPI_BASE + 1, + ERROR_GSPI_INVALID_LENGTH = ERROR_GSPI_BASE + 2, + ERROR_GSPI_BUSY = ERROR_GSPI_BASE + 3, + ERROR_GSPI_READ_DONE = ERROR_GSPI_BASE + 4, + ERROR_GSPI_IDLE = ERROR_GSPI_BASE + 5, + ERROR_GSPI_TX_DONE = ERROR_GSPI_BASE + 6, + + /*SSI ERROR CODES*/ + ERROR_SSI_BASE = 0x1200, + ERROR_SSI_INVALID_ARG = ERROR_SSI_BASE + 1, + ERROR_SSI_BUSY = ERROR_SSI_BASE + 2, + ERROR_SSI_IDLE = ERROR_SSI_BASE + 3, + TRANSFER_COMPLETE = ERROR_SSI_BASE + 4, + READ_COMPLETED = ERROR_SSI_BASE + 5, + + /*SSI ERROR CODES*/ + ERROR_CRC_BASE = 0x1300, + ERROR_CRC_INVALID_ARG = ERROR_CRC_BASE + 1, + + /*SSI ERROR CODES*/ + ERROR_RNG_BASE = 0x1400, + ERROR_RNG_INVALID_ARG = ERROR_RNG_BASE + 1, + + /*NPSS ERROR CODES*/ + ERROR_BOD_BASE = 0x1500, + ERROR_PS_BASE = ERROR_BOD_BASE + 1, + ERROR_BOD_INVALID_PARAMETERS, + ERROR_PS_INVALID_PARAMETERS, + ERROR_PS_INVALID_STATE, + + /*TIME PERIOD*/ + ERROR_TIMEPERIOD_BASE = 0x1600, + ERROR_TIME_PERIOD_PARAMETERS = ERROR_TIMEPERIOD_BASE + 1, + ERROR_TIME_PERIOD_RC_CALIB_NOT_DONE, + ERROR_CAL_INVALID_PARAMETERS, + + /*M4SS CLOCKS */ + ERROR_M4SS_CLK_BASE = 0x1700, + ERROR_CLOCK_NOT_ENABLED = ERROR_M4SS_CLK_BASE + 1, + ERROR_INVALID_INPUT_FREQUENCY, + + /*ULPSS CLOCKS */ + ERROR_ULPCLK_BASE = 1800, + ERROR_ULPCLK_INVALID_PARAMETERS = ERROR_ULPCLK_BASE + 1, + + ERROR_SIO_BASE = 0x1900, + ERROR_SIO_I2C_NO_ACK = ERROR_SIO_BASE + 1, + + /* ULPSS FIM */ + ERROR_FIM_BASE = 0x2000, + ERROR_FIM_MATRIX_INVALID_ARG = ERROR_FIM_BASE + 1, + + /* AUX ADC */ + ERROR_NO_MULTI_CHNL_ENABLE = 0x2100, + NO_MODE_SET = ERROR_NO_MULTI_CHNL_ENABLE + 1, + ERROR_PING_PONG_ADDR_MATCH = ERROR_NO_MULTI_CHNL_ENABLE + 2, + ERROR_ADC_INVALID_ARG = ERROR_NO_MULTI_CHNL_ENABLE + 3, + INVALID_SAMPLING_RATE = ERROR_NO_MULTI_CHNL_ENABLE + 4, + INVALID_AUX_REF_VOLTAGE = ERROR_NO_MULTI_CHNL_ENABLE + 5, + INVALID_SAMPLE_LENGTH = ERROR_NO_MULTI_CHNL_ENABLE + 6, + INVALID_ADC_CHANNEL_ENABLE = ERROR_NO_MULTI_CHNL_ENABLE + 6, + + /* AUX DAC */ + ERROR_NO_PAD_SEL = 0x2200, + ERROR_FREQ_VAL = ERROR_NO_PAD_SEL + 1, + + /*SDMEM*/ + ERROR_ACCESS_RIGHTS = 0x2300, + ERROR_ADDR_ALIGHMENGT = ERROR_ACCESS_RIGHTS + 1, + ERROR_SMIH, + ERROR_INAVLID_MODE, + ERROR_OPERATION_INPROGRESS, + ERROR_NOT_READY, + ERROR_UNINITIALIZED, + ERROR_BUFFER_FULL, + ERROR_TIMEOUT, + CARD_NOT_READY_OP, + CARD_TYPE_MEMCARD, +} rsi_error_t; + +#ifdef __cplusplus +} +#endif + +#endif // __RSI_ERROR_H__ + +/*END OF FILE */ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/rsi_ps_ram_func.h b/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/rsi_ps_ram_func.h new file mode 100644 index 000000000..a1367a3e6 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/rsi_ps_ram_func.h @@ -0,0 +1,26 @@ +/******************************************************************************* +* @file rsi_ps_ram_func.h +* @brief +******************************************************************************* +* # License +* Copyright 2020 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +/** + * Includes + */ + +/*This API will be called by the boot loader when it is from non retention wake up +when flash execution is enabled */ +void RSI_PS_Restore(void); +void Init_QspiStc(void); +void RSI_FLASH_Initialize(void); diff --git a/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/rsi_system_config.h b/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/rsi_system_config.h new file mode 100644 index 000000000..f7455051b --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/rsi_system_config.h @@ -0,0 +1,104 @@ +/******************************************************************************* +* @file rsi_system_config.h +* @brief +******************************************************************************* +* # License +* Copyright 2020 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +/** + * Includes + */ + +#ifndef __RSI_SYSTEM_CONFIG_H__ +#define __RSI_SYSTEM_CONFIG_H__ +#include "rsi_ccp_common.h" + +#include "base_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +extern uint32_t scdc_volt_sel1[]; +extern uint32_t lp_scdc_extcapmode[]; +extern uint32_t m32rc_osc_trim_efuse[]; +extern uint32_t m20rc_osc_trim_efuse[]; +extern uint32_t dblr_32m_trim_efuse[]; +extern uint32_t m20ro_osc_trim_efuse[]; +extern uint32_t ro_32khz_trim_efuse[]; +extern uint32_t rc_16khz_trim_efuse[]; +extern uint32_t rc_64khz_trim_efuse[]; +extern uint32_t rc_32khz_trim_efuse[]; +extern uint32_t vbatt_status_trim_efuse[]; +extern uint32_t ro_ts_efuse[]; +extern uint32_t ro_tempsense_config[]; +extern uint32_t vbg_tsbjt_efuse[]; +extern uint32_t auxadc_off_diff_efuse[]; +extern uint32_t auxadc_gain_diff_efuse[]; +extern uint32_t auxadc_off_se_efuse[]; +extern uint32_t auxadc_gain_se_efuse[]; +extern uint32_t bg_trim_efuse[]; +extern uint32_t blackout_trim_efuse[]; +extern uint32_t poc_bias_efuse[]; +extern uint32_t buck_trim_efuse[]; +extern uint32_t ldosoc_trim_efuse[]; +extern uint32_t dpwm_freq_trim_efuse[]; +extern uint32_t delvbe_tsbjt_efuse[]; +extern uint32_t xtal1_bias_efuse[]; +extern uint32_t xtal2_bias_efuse[]; +extern uint32_t bod_cmp_hyst[]; +extern uint32_t ipmu_bod_clks_common_config2[]; +extern uint32_t ipmu_bod_clks_common_config1[]; +extern uint32_t pmu_common_config[]; +extern uint32_t ipmu_common_config[]; +extern uint32_t xtal1_khz_fast_start_en[]; +extern uint32_t xtal1_khz_fast_start_disable[]; +extern uint32_t hp_ldo_voltsel[]; +extern uint32_t poc_bias_current_11[]; +extern uint32_t ro_32khz_trim00_efuse[]; +extern uint32_t retnLP_volt_trim_efuse[]; +extern uint32_t retnHP_volt_trim_efuse[]; +extern uint32_t hpldo_volt_trim_efuse[]; +extern uint32_t scdc_volt_trim_efuse[]; +extern uint32_t poc_bias_current[]; +extern uint32_t scdc_volt_sel2[]; +extern uint32_t scdc_volt_trim_efuse[]; +extern uint32_t ana_perif_ptat_common_config1[]; +extern uint32_t ana_perif_ptat_common_config2[]; +extern uint32_t retn_ldo_0p75[]; +extern uint32_t retn_ldo_lpmode[]; +extern uint32_t retn_ldo_hpmode[]; +extern uint32_t retn_ldo_voltsel[]; +extern uint32_t ipmu_scdc_enable[]; +extern uint32_t buck_fast_transient_duty_1p8[]; +extern uint32_t hpldo_tran[]; +extern uint32_t LDOFLASH_BYPASS[]; +#define POWER_TARN_DISABLE 0 +#define POWER_TARN_ALWAYS_USE 1 +#define POWER_TARN_CONDITIONAL_USE 2 + +#define XTAL_CAP_MODE POWER_TARN_CONDITIONAL_USE + +#define IPMU_DOTC_PROG +#define IPMU_CALIB_DATA +typedef uint32_t uint32; +typedef uint16_t uint16; +typedef int32_t int32; +typedef uint8_t uint8; +#define cmemcpy memcpy + +#ifdef __cplusplus +} +#endif + +#endif //__RSI_SYSTEM_CONFIG_H__ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/si91x_device.h b/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/si91x_device.h new file mode 100644 index 000000000..b451ee286 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/si91x_device.h @@ -0,0 +1,16007 @@ +/******************************************************************************* +* @file si91x_device.h +* @brief +******************************************************************************* +* # License +* Copyright 2023 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +/* + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontroller, but can be equally used for other + * suitable processor architectures. This file can be freely distributed. + * Modifications to this file shall be clearly marked. + * + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + * @file RS1xxxx.h + * @brief CMSIS HeaderFile + * @version 1.2 + * @date 21. June 2021 + * @note Generated by SVDConv V3.3.29 on Monday, 21.06.2021 18:28:44 + * from File 'RS9117.svd', + * last modified on Monday, 21.06.2021 06:14:18 + */ + +/** @addtogroup Silicon Lab Inc. + * @{ + */ + +/** @addtogroup RS1xxxx + * @{ + */ + +#ifndef __RS1XXXX_H__ +#define __RS1XXXX_H__ + +#include "base_types.h" +#include "RS1xxxx.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* =========================================================================================================================== + */ +/* ================ Interrupt Number Definition + * ================ */ +/* =========================================================================================================================== + */ + +typedef enum { + /* ======================================= ARM Cortex-M4 Specific Interrupt + Numbers ======================================== */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, + including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, + other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal + State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* ========================================== RS1xxxx Specific Interrupt + Numbers =========================================== */ + TIMER0_IRQn = 2, /*!< 2 TIMER0 */ + TIMER1_IRQn = 3, /*!< 3 TIMER1 */ + TIMER2_IRQn = 4, /*!< 4 TIMER2 */ + TIMER3_IRQn = 5, /*!< 5 TIMER3 */ + CAP_SENSOR_IRQn = 6, /*!< 6 CAP_SENSOR */ + COMP2_IRQn = 7, /*!< 7 COMP2 */ + COMP1_IRQn = 8, /*!< 8 COMP1 */ + UDMA1_IRQn = 10, /*!< 10 UDMA1 */ + ADC_IRQn = 11, /*!< 11 ADC */ + ULPSS_UART_IRQn = 12, /*!< 12 ULPSS_UART */ + I2C2_IRQn = 13, /*!< 13 I2C2 */ + I2S1_IRQn = 14, /*!< 14 I2S1 */ + IR_DECODER_IRQn = 15, /*!< 15 IR_DECODER */ + SSI2_IRQn = 16, /*!< 16 SSI2 */ + FIM_IRQn = 17, /*!< 17 FIM */ + ULP_EGPIO_PIN_IRQn = 18, /*!< 18 ULP_EGPIO_PIN */ + ULP_EGPIO_GROUP_IRQn = 19, /*!< 19 ULP_EGPIO_GROUP */ + NPSS_TO_MCU_WDT_INTR_IRQn = 20, /*!< 20 NPSS_TO_MCU_WDT_INTR */ + NPSS_TO_MCU_GPIO_INTR_IRQn = 21, /*!< 21 NPSS_TO_MCU_GPIO_INTR */ +#ifdef SLI_SI917B0 + NPSS_TO_MCU_SYRTC_INTR_IRQn = 22, /*!< 22 NPSS_TO_MCU_SYSRTC_INTR */ +#else + NPSS_TO_MCU_CMP_RF_WKP_INTR_IRQn = 22, /*!< 22 NPSS_TO_MCU_CMP_RF_WKP_INTR */ +#endif + NPSS_TO_MCU_BOD_INTR_IRQn = 23, /*!< 23 NPSS_TO_MCU_BOD_INTR */ + NPSS_TO_MCU_BUTTON_INTR_IRQn = 24, /*!< 24 NPSS_TO_MCU_BUTTON_INTR */ + NPSS_TO_MCU_SDC_INTR_IRQn = 25, /*!< 25 NPSS_TO_MCU_SDC_INTR */ + NPSS_TO_MCU_WIRELESS_INTR_IRQn = 26, /*!< 26 NPSS_TO_MCU_WIRELESS_INTR */ + NPSS_MCU_INTR_IRQn = 27, /*!< 27 NPSS_MCU_INTR */ + MCU_CAL_ALARM_IRQn = 28, /*!< 28 MCU_CAL_ALARM */ + MCU_CAL_RTC_IRQn = 29, /*!< 29 MCU_CAL_RTC */ + GPDMA_IRQn = 31, /*!< 31 GPDMA */ + UDMA0_IRQn = 33, /*!< 33 UDMA0 */ + CT_IRQn = 34, /*!< 34 CT */ + HIF0_IRQn = 35, /*!< 35 HIF0 */ + HIF1_IRQn = 36, /*!< 36 HIF1 */ + SIO_IRQn = 37, /*!< 37 SIO */ + USART0_IRQn = 38, /*!< 38 USART0 */ + UART1_IRQn = 39, /*!< 39 UART1 */ + EGPIO_WAKEUP_IRQn = 41, /*!< 41 EGPIO_WAKEUP */ + I2C0_IRQn = 42, /*!< 42 I2C0 */ + SSISlave_IRQn = 44, /*!< 44 SSISlave */ + GSPI0_IRQn = 46, /*!< 46 GSPI0 */ + SSI0_IRQn = 47, /*!< 47 SSI0 */ + MCPWM_IRQn = 48, /*!< 48 MCPWM */ + QEI_IRQn = 49, /*!< 49 QEI */ + EGPIO_GROUP_0_IRQn = 50, /*!< 50 EGPIO_GROUP_0 */ + EGPIO_GROUP_1_IRQn = 51, /*!< 51 EGPIO_GROUP_1 */ + EGPIO_PIN_0_IRQn = 52, /*!< 52 EGPIO_PIN_0 */ + EGPIO_PIN_1_IRQn = 53, /*!< 53 EGPIO_PIN_1 */ + EGPIO_PIN_2_IRQn = 54, /*!< 54 EGPIO_PIN_2 */ + EGPIO_PIN_3_IRQn = 55, /*!< 55 EGPIO_PIN_3 */ + EGPIO_PIN_4_IRQn = 56, /*!< 56 EGPIO_PIN_4 */ + EGPIO_PIN_5_IRQn = 57, /*!< 57 EGPIO_PIN_5 */ + EGPIO_PIN_6_IRQn = 58, /*!< 58 EGPIO_PIN_6 */ + EGPIO_PIN_7_IRQn = 59, /*!< 59 EGPIO_PIN_7 */ + QSPI_IRQn = 60, /*!< 60 QSPI */ + I2C1_IRQn = 61, /*!< 61 I2C1 */ +#ifdef SLI_SI917B0 + MVP_IRQn = 62, /*!< 62 MVP */ + MVP_WAKEUP_IRQn = 63, /*!< 63 MVP_WAKEUP */ +#endif + I2S0_IRQn = 64, /*!< 64 I2S0 */ + PLL_CLOCK_IRQn = 69, /*!< 69 PLL_CLOCK */ + TASS_P2P_IRQn = 74 /*!< 74 TASS_P2P */ +} IRQn_Type; + +/* =========================================================================================================================== + */ +/* ================ Processor and Core Peripheral + * Section ================ */ +/* =========================================================================================================================== + */ + +/* =========================== Configuration of the ARM Cortex-M4 Processor and + * Core Peripherals =========================== */ +#define __CM4_REV 0x0100U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 6 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 1 /*!< MPU present */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ +#include "system_si91x.h" /*!< RS1xxxx System */ + +#ifndef __IM /*!< Fallback for older CMSIS versions */ +#define __IM __I +#endif +#ifndef __OM /*!< Fallback for older CMSIS versions */ +#define __OM __O +#endif +#ifndef __IOM /*!< Fallback for older CMSIS versions */ +#define __IOM __IO +#endif + +/* ======================================== Start of section using anonymous + * unions ======================================== */ +#if defined(__CC_ARM) +#pragma push +#pragma anon_unions +#elif defined(__ICCARM__) +#pragma language = extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wc11-extensions" +#pragma clang diagnostic ignored "-Wreserved-id-macro" +#pragma clang diagnostic ignored "-Wgnu-anonymous-struct" +#pragma clang diagnostic ignored "-Wnested-anon-types" +#elif defined(__GNUC__) +/* anonymous unions are enabled by default */ +#elif defined(__TMS470__) +/* anonymous unions are enabled by default */ +#elif defined(__TASKING__) +#pragma warning 586 +#elif defined(__CSMC__) +/* anonymous unions are enabled by default */ +#else +#warning Not supported compiler type +#endif + +/* =========================================================================================================================== + */ +/* ================ Device Specific Cluster Section + * ================ */ +/* =========================================================================================================================== + */ + +/** @addtogroup Device_Peripheral_clusters + * @{ + */ + +/** + * @brief MCPWM_PWM_DEADTIME [PWM_DEADTIME] ([0..3]) + */ +typedef struct { + union { + __IOM uint32_t PWM_DEADTIME_A; /*!< (@ 0x00000000) PWM deadtime for A and + channel varies from 0 to 3 */ + + struct { + __IOM uint32_t DEADTIME_A_CH : 6; /*!< [5..0] Dead time A value to load into dead + time counter A of channel0 to channel3 */ + __IOM uint32_t RESERVED1 : 26; /*!< [31..6] reserved1 */ + } PWM_DEADTIME_A_b; + }; + + union { + __IOM uint32_t PWM_DEADTIME_B; /*!< (@ 0x00000004) PWM deadtime for B and + channel varies from 0 to 3 */ + + struct { + __IOM uint32_t DEADTIME_B_CH : 6; /*!< [5..0] Dead time B value to load into deadtime + counter B of channel0 to channel3 */ + __IOM uint32_t RESERVED1 : 26; /*!< [31..6] reserved1 */ + } PWM_DEADTIME_B_b; + }; +} MCPWM_PWM_DEADTIME_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief GPDMA_G_GLOBAL [GLOBAL] (GLOBAL) + */ +typedef struct { + union { + __IOM uint32_t INTERRUPT_REG; /*!< (@ 0x00000000) Interrupt Register */ + + struct { + __IOM uint32_t GPDMAC_INT_STAT : 8; /*!< [7..0] Interrupt Status */ + __IM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + } INTERRUPT_REG_b; + }; + + union { + __IOM uint32_t INTERRUPT_MASK_REG; /*!< (@ 0x00000004) Interrupt Mask Register */ + + struct { + __IOM uint32_t RESERVED1 : 8; /*!< [7..0] reserved1 */ + __IOM uint32_t LINK_LIST_FETCH_MASK : 8; /*!< [15..8] Linked list fetch done + interrupt bit mask control. By default, + descriptor fetch done interrupt is + masked. */ + __IOM uint32_t TFR_DONE_MASK : 8; /*!< [23..16] Transfer done interrupt + bit mask control. */ + __IOM uint32_t RESERVED2 : 8; /*!< [31..24] reserved2 */ + } INTERRUPT_MASK_REG_b; + }; + + union { + __IOM uint32_t INTERRUPT_STAT_REG; /*!< (@ 0x00000008) Interrupt status register */ + + struct { + __IOM uint32_t HRESP_ERR0 : 1; /*!< [0..0] DMA error bit */ + __IOM uint32_t LINK_LIST_FETCH_DONE0 : 1; /*!< [1..1] This bit indicates the status + of linked list descriptor + fetch done for channel 0 */ + __IOM uint32_t TFR_DONE0 : 1; /*!< [2..2] This bit indicates the status of DMA + transfer done interrupt for channel 0 */ + __IOM uint32_t GPDMAC_ERR0 : 1; /*!< [3..3] transfer size or burst size or + h size mismatch error */ + __IOM uint32_t HRESP_ERR1 : 1; /*!< [4..4] HRESP error bit */ + __IOM uint32_t LINK_LIST_FETCH_DONE1 : 1; /*!< [5..5] This bit indicates the status + of linked list descriptor + fetch done for channel 1 */ + __IOM uint32_t TFR_DONE1 : 1; /*!< [6..6] This bit indicates the status of DMA + transfer done interrupt for channel 1. */ + __IOM uint32_t GPDMAC_ERR1 : 1; /*!< [7..7] transfer size or burst size or + h size mismatch error */ + __IOM uint32_t HRESP_ERR2 : 1; /*!< [8..8] HRESP error bit */ + __IOM uint32_t LINK_LIST_FETCH_DONE2 : 1; /*!< [9..9] This bit indicates the status + of linked list descriptor + fetch done for channel 2. */ + __IOM uint32_t TFR_DONE2 : 1; /*!< [10..10] This bit indicates the status of DMA + transfer done interrupt for channel 2. */ + __IOM uint32_t GPDMAC_ERR2 : 1; /*!< [11..11] transfer size or burst size + or h size mismatch error */ + __IOM uint32_t HRESP_ERR3 : 1; /*!< [12..12] HRESP error bit */ + __IOM uint32_t LINK_LIST_FETCH_DONE3 : 1; /*!< [13..13] This bit indicates the status + of linked list descriptor + fetch done for channel 3. */ + __IOM uint32_t TFR_DONE3 : 1; /*!< [14..14] This bit indicates the status of DMA + transfer done interrupt for channel 3. */ + __IOM uint32_t GPDMAC_ERR3 : 1; /*!< [15..15] transfer size or burst size + or h size mismatch error */ + __IOM uint32_t HRESP_ERR4 : 1; /*!< [16..16] HRESP error bit */ + __IOM uint32_t LINK_LIST_FETCH_DONE4 : 1; /*!< [17..17] This bit indicates the status + of linked list descriptor + fetch done for channel 4. */ + __IOM uint32_t TFR_DONE4 : 1; /*!< [18..18] This bit indicates the status of DMA + transfer done interrupt for channel 4. */ + __IOM uint32_t GPDMAC_ERR4 : 1; /*!< [19..19] transfer size or burst size + or h size mismatch error */ + __IOM uint32_t HRESP_ERR5 : 1; /*!< [20..20] HRESP error bit */ + __IOM uint32_t LINK_LIST_FETCH_DONE5 : 1; /*!< [21..21] This bit indicates the status + of linked list descriptor + fetch done for channel 5. */ + __IOM uint32_t TFR_DONE5 : 1; /*!< [22..22] This bit indicates the status of DMA + transfer done interrupt for channel 5. */ + __IOM uint32_t GPDMAC_ERR5 : 1; /*!< [23..23] transfer size or burst size + or h size mismatch error */ + __IM uint32_t HRESP_ERR6 : 1; /*!< [24..24] HRESP error bit */ + __IOM uint32_t LINK_LIST_FETCH_DONE6 : 1; /*!< [25..25] This bit indicates the status + of linked list descriptor + fetch done for channel 6. */ + __IOM uint32_t TFR_DONE6 : 1; /*!< [26..26] This bit indicates the status of DMA + transfer done interrupt for channel 6. */ + __IOM uint32_t GPDMAC_ERR6 : 1; /*!< [27..27] transfer size or burst size + or h size mismatch error */ + __IOM uint32_t HRESP_ERR7 : 1; /*!< [28..28] HRESP error bit */ + __IOM uint32_t LINK_LIST_FETCH_DONE7 : 1; /*!< [29..29] This bit indicates the status + of linked list descriptor + fetch done for channel 7. */ + __IOM uint32_t TFR_DONE7 : 1; /*!< [30..30] This bit indicates the status of DMA + transfer done interrupt for channel 7. */ + __IOM uint32_t GPDMAC_ERR7 : 1; /*!< [31..31] transfer size or burst size + or h size mismatch error */ + } INTERRUPT_STAT_REG_b; + }; + + union { + __IOM uint32_t DMA_CHNL_ENABLE_REG; /*!< (@ 0x0000000C) This register used + for enable DMA channel */ + + struct { + __IOM uint32_t CH_ENB : 8; /*!< [7..0] CWhen a bit is set to one, it indicates, + corresponding channel is enabled for dma operation */ + __IM uint32_t RESERVED1 : 24; /*!< [31..8] Reserved1 */ + } DMA_CHNL_ENABLE_REG_b; + }; + + union { + __IOM uint32_t DMA_CHNL_SQUASH_REG; /*!< (@ 0x00000010) This register used + for enable DMA channel squash */ + + struct { + __IOM uint32_t CH_DIS : 8; /*!< [7..0] CPU Will be masked to write zeros, + CPU is allowed write 1 only */ + __IM uint32_t RESERVED1 : 24; /*!< [31..8] Reserved1 */ + } DMA_CHNL_SQUASH_REG_b; + }; + + union { + __IOM uint32_t DMA_CHNL_LOCK_REG; /*!< (@ 0x00000014) This register used for + enable DMA channel squash */ + + struct { + __IOM uint32_t CHNL_LOCK : 8; /*!< [7..0] When set entire DMA block transfer is done, + before other DMA request is serviced */ + __IM uint32_t RESERVED1 : 24; /*!< [31..8] Reserved1 */ + } DMA_CHNL_LOCK_REG_b; + }; +} GPDMA_G_GLOBAL_Type; /*!< Size = 24 (0x18) */ + +/** + * @brief GPDMA_C_CHANNEL_CONFIG [CHANNEL_CONFIG] ([0..7]) + */ +typedef struct { + union { + __IOM uint32_t LINK_LIST_PTR_REGS; /*!< (@ 0x00000000) Link List Register + for channel 0 to 7 */ + + struct { + __IOM uint32_t LINK_LIST_PTR_REG_CHNL : 32; /*!< [31..0] This is the address of the + memory location from which + we get our next descriptor */ + } LINK_LIST_PTR_REGS_b; + }; + + union { + __IOM uint32_t SRC_ADDR_REG_CHNL; /*!< (@ 0x00000004) Source Address + Register for channel 0 to 7 */ + + struct { + __IOM uint32_t SRC_ADDR : 32; /*!< [31..0] This is the address of the memory location + from which we get our next descriptor */ + } SRC_ADDR_REG_CHNL_b; + }; + + union { + __IOM uint32_t DEST_ADDR_REG_CHNL; /*!< (@ 0x00000008) Source Address + Register for channel 0 to 7 */ + + struct { + __IOM uint32_t DEST_ADDR : 32; /*!< [31..0] This is the destination + address to whih the data is sent */ + } DEST_ADDR_REG_CHNL_b; + }; + + union { + __IOM uint32_t CHANNEL_CTRL_REG_CHNL; /*!< (@ 0x0000000C) Channel Control + Register for channel 0 to 7 */ + + struct { + __IOM uint32_t DMA_BLK_SIZE : 12; /*!< [11..0] This is data to be transmitted. Loaded + at the beginning of the DMA transfer and + decremented at every dma transaction. */ + __IOM uint32_t TRNS_TYPE : 2; /*!< [13..12] DMA transfer type */ + __IOM uint32_t DMA_FLOW_CTRL : 2; /*!< [15..14] DMA flow control */ + __IOM uint32_t MSTR_IF_FETCH_SEL : 1; /*!< [16..16] This selects the MASTER IF from + which data to be fetched */ + __IOM uint32_t MSTR_IF_SEND_SEL : 1; /*!< [17..17] This selects the MASTER + IF from which data to be sent */ + __IOM uint32_t DEST_DATA_WIDTH : 2; /*!< [19..18] Data transfer to destination. */ + __IOM uint32_t SRC_DATA_WIDTH : 2; /*!< [21..20] Data transfer from source. */ + __IOM uint32_t SRC_ALIGN : 1; /*!< [22..22] Reserved.Value set to 0 We do not do any + singles. We just do burst, save first 3 bytes in to + residue buffer in one cycle, In the next cycle send + 4 bytes to fifo, save 3 bytes in to residue. This + continues on. */ + __IOM uint32_t LINK_LIST_ON : 1; /*!< [23..23] This mode is set, when we + do link listed operation */ + __IOM uint32_t LINK_LIST_MSTR_SEL : 1; /*!< [24..24] This mode is set, when we do + link listed operation */ + __IOM uint32_t SRC_ADDR_CONTIGUOUS : 1; /*!< [25..25] Indicates Address is + contiguous from previous */ + __IOM uint32_t DEST_ADDR_CONTIGUOUS : 1; /*!< [26..26] Indicates Address is + contiguous from previous */ + __IOM uint32_t RETRY_ON_ERROR : 1; /*!< [27..27] When this bit is set, if + we recieve HRESPERR, We will retry + the DMA for that channel. */ + __IOM uint32_t LINK_INTERRUPT : 1; /*!< [28..28] This bit is set in link list + descriptor.Hard ware will send an interrupt + when the DMA transfer is done for the + corresponding link list address */ + __IOM uint32_t SRC_FIFO_MODE : 1; /*!< [29..29] If set to 1; source address will not + be incremented(means fifo mode for source) */ + __IOM uint32_t DEST_FIFO_MODE : 1; /*!< [30..30] If set to 1; destination address + will not be incremented(means fifo mode for + destination) */ + __IM uint32_t RESERVED1 : 1; /*!< [31..31] Reserved1 */ + } CHANNEL_CTRL_REG_CHNL_b; + }; + + union { + __IOM uint32_t MISC_CHANNEL_CTRL_REG_CHNL; /*!< (@ 0x00000010) Misc Channel Control + Register for channel 0 */ + + struct { + __IOM uint32_t AHB_BURST_SIZE : 3; /*!< [2..0] Burst size */ + __IOM uint32_t DEST_DATA_BURST : 6; /*!< [8..3] Burst writes in beats to + destination.(000000-64 beats + .....111111-63 beats) */ + __IOM uint32_t SRC_DATA_BURST : 6; /*!< [14..9] Burst writes in beats from + source(000000-64 beats + .....111111-63 beats) */ + __IOM uint32_t DEST_CHNL_ID : 6; /*!< [20..15] This is the destination channel Id to + which the data is sent. Must be set up prior to + DMA_CHANNEL_ENABLE */ + __IOM + uint32_t SRC_CHNL_ID : 6; /*!< [26..21] This is the source channel Id, + from which the data is fetched. must be + set up prior to DMA_CHANNEL_ENABLE */ + __IOM uint32_t DMA_PROT : 3; /*!< [29..27] Protection level to go with the data. It + will be concatenated with 1 b1 as there will be no + opcode fetching and directly assign to hprot in AHB + interface */ + __IOM uint32_t MEM_FILL_ENABLE : 1; /*!< [30..30] Enable for memory + filling with either 1s or 0s. */ + __IOM uint32_t MEM_ONE_FILL : 1; /*!< [31..31] Select for memory filling + with either 1s or 0s. */ + } MISC_CHANNEL_CTRL_REG_CHNL_b; + }; + + union { + __IOM uint32_t FIFO_CONFIG_REGS; /*!< (@ 0x00000014) FIFO Configuration + Register for channel 1 */ + + struct { + __IOM uint32_t FIFO_STRT_ADDR : 6; /*!< [5..0] Starting row address of channel */ + __IOM uint32_t FIFO_SIZE : 6; /*!< [11..6] Channel size */ + __IM uint32_t RESERVED1 : 20; /*!< [31..12] Reserved1 */ + } FIFO_CONFIG_REGS_b; + }; + + union { + __IOM uint32_t PRIORITY_CHNL_REGS; /*!< (@ 0x00000018) Priority Register for + channel 0 to 7 */ + + struct { + __IOM uint32_t PRIORITY_CH : 2; /*!< [1..0] Set a value between 2 b00 to 2 b11. The + channel having highest number is the highest + priority channel. */ + __IM uint32_t RESERVED1 : 30; /*!< [31..2] Reserved1 */ + } PRIORITY_CHNL_REGS_b; + }; + __IM uint32_t RESERVED[57]; +} GPDMA_C_CHANNEL_CONFIG_Type; /*!< Size = 256 (0x100) */ + +/** + * @brief TIMERS_MATCH_CTRL [MATCH_CTRL] ([0..3]) + */ +typedef struct { + union { + __IOM uint32_t MCUULP_TMR_MATCH; /*!< (@ 0x00000000) Timer Match Register */ + + struct { + __IOM uint32_t TMR_MATCH : 32; /*!< [31..0] This bits are used to program the lower + significant 16-bits of timer time out value in + millisecond or number of system clocks */ + } MCUULP_TMR_MATCH_b; + }; + + union { + __IOM uint32_t MCUULP_TMR_CNTRL; /*!< (@ 0x00000004) Timer Control Register */ + + struct { + __OM uint32_t TMR_START : 1; /*!< [0..0] This Bit are Used to start the timer timer + gets reset upon setting this bit */ + __OM uint32_t TMR_INTR_CLR : 1; /*!< [1..1] This Bit are Used to clear the + timer */ + __IOM uint32_t TMR_INTR_ENABLE : 1; /*!< [2..2] This Bit are Used to + enable the time out interrupt */ + __IOM uint32_t TMR_TYPE : 2; /*!< [4..3] This Bit are Used to select the + type of timer */ + __IOM uint32_t TMR_MODE : 1; /*!< [5..5] This Bit are Used to select the + mode working of timer */ + __OM uint32_t TMR_STOP : 1; /*!< [6..6] This Bit are Used to stop the timer */ + __IOM uint32_t COUNTER_UP : 1; /*!< [7..7] For reading/tracking counter in + up counting this bit has to be set */ + __IOM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + } MCUULP_TMR_CNTRL_b; + }; +} TIMERS_MATCH_CTRL_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief I2S0_CHANNEL_CONFIG [CHANNEL_CONFIG] ([0..3]) + */ +typedef struct { + union { + union { + __IM uint32_t I2S_LRBR; /*!< (@ 0x00000000) Left Receive Buffer Register */ + + struct { + __IM uint32_t LRBR : 24; /*!< [23..0] Data received serially from the + received channel input */ + __IM uint32_t RESERVED1 : 8; /*!< [31..24] Reserved for future use */ + } I2S_LRBR_b; + }; + + union { + __OM uint32_t I2S_LTHR; /*!< (@ 0x00000000) Left Receive Buffer Register */ + + struct { + __OM uint32_t LTHR : 24; /*!< [23..0] The Left Stereo Data to be transmitted + serially from the Transmitted channel output */ + __OM uint32_t RESERVED1 : 8; /*!< [31..24] Reserved for future use */ + } I2S_LTHR_b; + }; + }; + + union { + union { + __IM uint32_t I2S_RRBR; /*!< (@ 0x00000004) Right Receive Buffer Register */ + + struct { + __IM uint32_t RRBR : 24; /*!< [23..0] The Right Stereo Data received serially from + the received channel input through this register */ + __IM uint32_t RESERVED1 : 8; /*!< [31..24] Reserved for future use */ + } I2S_RRBR_b; + }; + + union { + __OM uint32_t I2S_RTHR; /*!< (@ 0x00000004) Right Transmit Holding Register */ + + struct { + __OM uint32_t RTHR : 24; /*!< [23..0] The Right Stereo Data to be transmitted + serially from the Transmit channel output written + through this register */ + __OM uint32_t RESERVED1 : 8; /*!< [31..24] Reserved for future use */ + } I2S_RTHR_b; + }; + }; + + union { + __IOM uint32_t I2S_RER; /*!< (@ 0x00000008) Receive Enable Register */ + + struct { + __IOM uint32_t RXCHEN : 1; /*!< [0..0] This Bit enables/disables a receive channel + independently of all other channels */ + __IOM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + } I2S_RER_b; + }; + + union { + __IOM uint32_t I2S_TER; /*!< (@ 0x0000000C) Transmit Enable Register */ + + struct { + __IOM uint32_t TXCHEN : 1; /*!< [0..0] This Bit enables/disables a transmit channel + independently of all other channels */ + __IOM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + } I2S_TER_b; + }; + + union { + __IOM uint32_t I2S_RCR; /*!< (@ 0x00000010) Receive Configuration Register */ + + struct { + __IOM uint32_t WLEN : 3; /*!< [2..0] This Bits are used to program the desired data + resolution of the receiver and enables LSB of the + incoming left or right word */ + __IOM uint32_t RESERVED1 : 29; /*!< [31..3] Reserved for future use */ + } I2S_RCR_b; + }; + + union { + __IOM uint32_t I2S_TCR; /*!< (@ 0x00000014) Transmit Configuration Register */ + + struct { + __IOM uint32_t WLEN : 3; /*!< [2..0] This Bits are used to program the desired data + resolution of the transmitter and ensure that MSB of the + data is transmitted first. */ + __IOM uint32_t RESERVED1 : 29; /*!< [31..3] Reserved for future use */ + } I2S_TCR_b; + }; + + union { + __IM uint32_t I2S_ISR; /*!< (@ 0x00000018) Interrupt Status Register */ + + struct { + __IM uint32_t RXDA : 1; /*!< [0..0] Receive Data Available */ + __IM uint32_t RXFO : 1; /*!< [1..1] Receive Data FIFO */ + __IM uint32_t RESERVED1 : 2; /*!< [3..2] Reserved for future use */ + __IM uint32_t TXFE : 1; /*!< [4..4] Transmit FIFO Empty */ + __IM uint32_t TXFO : 1; /*!< [5..5] Transmit FIFO */ + __IM uint32_t RESERVED2 : 26; /*!< [31..6] Reserved for future use */ + } I2S_ISR_b; + }; + + union { + __IOM uint32_t I2S_IMR; /*!< (@ 0x0000001C) Interrupt Mask Register */ + + struct { + __IOM uint32_t RXDAM : 1; /*!< [0..0] RX Data Available Mask Interrupt */ + __IOM uint32_t RXFOM : 1; /*!< [1..1] RX FIFO Overrun Mask Interrupt */ + __IOM uint32_t RESERVED1 : 2; /*!< [3..2] Reserved for future use */ + __IOM uint32_t TXFEM : 1; /*!< [4..4] TX FIFO Empty Interrupt */ + __IOM uint32_t TXFOM : 1; /*!< [5..5] TX FIFO Overrun Interrupt */ + __IOM uint32_t RESERVED2 : 26; /*!< [31..6] Reserved for future use */ + } I2S_IMR_b; + }; + + union { + __IM uint32_t I2S_ROR; /*!< (@ 0x00000020) Receive Overrun Register */ + + struct { + __IM uint32_t RXCHO : 1; /*!< [0..0] Read this bit to clear the RX FIFO + data overrun interrupt */ + __IM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + } I2S_ROR_b; + }; + + union { + __IM uint32_t I2S_TOR; /*!< (@ 0x00000024) Transmit Overrun Register */ + + struct { + __IM uint32_t TXCHO : 1; /*!< [0..0] Read this bit to clear the TX FIFO + data overrun interrupt */ + __IM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + } I2S_TOR_b; + }; + + union { + __IOM uint32_t I2S_RFCR; /*!< (@ 0x00000028) Receive FIFO Configuration Register0 */ + + struct { + __IOM uint32_t RXCHDT : 4; /*!< [3..0] This bits program the trigger level in the RX + FIFO at which the data available interrupt is + generated */ + __IOM uint32_t RESERVED1 : 28; /*!< [31..4] Reserved for future use */ + } I2S_RFCR_b; + }; + + union { + __IOM uint32_t I2S_TXFCR; /*!< (@ 0x0000002C) Transmit FIFO Configuration Register */ + + struct { + __IOM + uint32_t TXCHET : 4; /*!< [3..0] This bits program the trigger level + in the TX FIFO at which the Empty Threshold + Reached interrupt is generated */ + __IM uint32_t RESERVED1 : 28; /*!< [31..4] Reserved for future use */ + } I2S_TXFCR_b; + }; + + union { + __OM uint32_t I2S_RFF; /*!< (@ 0x00000030) Receive FIFO Flush */ + + struct { + __OM uint32_t RXCHFR : 1; /*!< [0..0] Writing a 1 to this register flushes an + individual RX FIFO RX channel or block must be disable + prior to writing to this bit */ + __OM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + } I2S_RFF_b; + }; + + union { + __OM uint32_t I2S_TFF; /*!< (@ 0x00000034) Transmit FIFO Flush */ + + struct { + __OM uint32_t TXCHFR : 1; /*!< [0..0] Writing a 1 to this register flushes an + individual TX FIFO TX channel or block must be disable + prior to writing to this bit */ + __OM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + } I2S_TFF_b; + }; + __IM uint32_t RSVD0; /*!< (@ 0x00000038) none */ + __IM uint32_t RSVD1; /*!< (@ 0x0000003C) none */ +} I2S0_CHANNEL_CONFIG_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief EGPIO_PIN_CONFIG [PIN_CONFIG] ([0..79]) + */ +typedef struct { + union { + __IOM uint32_t GPIO_CONFIG_REG; /*!< (@ 0x00000000) GPIO Configuration Register */ + + struct { + __IOM uint32_t DIRECTION : 1; /*!< [0..0] Direction of the GPIO pin */ + __IOM uint32_t PORTMASK : 1; /*!< [1..1] Port mask value */ + __IOM uint32_t MODE : 4; /*!< [5..2] GPIO Pin Mode Used for GPIO Pin Muxing */ + __IOM uint32_t RESERVED1 : 2; /*!< [7..6] Reserved1 */ + __IOM uint32_t GROUP_INTERRUPT1_ENABLE : 1; /*!< [8..8] When set, the corresponding + GPIO is pin is selected for + group intr 1 generation */ + __IOM uint32_t GROUP_INTERRUPT1_POLARITY : 1; /*!< [9..9] Decides the active value of + the pin to be considered for group + interrupt 1 generation */ + __IOM uint32_t GROUP_INTERRUPT2_ENABLE : 1; /*!< [10..10] When set, the corresponding + GPIO is pin is selected + for group intr 2 generation */ + __IOM uint32_t GROUP_INTERRUPT2_POLARITY : 1; /*!< [11..11] Decides the active value + of the pin to be considered + for group interrupt 2 generation */ + __IOM uint32_t RESERVED2 : 4; /*!< [15..12] Reserved2 */ + __IOM uint32_t RESERVED3 : 16; /*!< [31..16] Reserved3 */ + } GPIO_CONFIG_REG_b; + }; + + union { + __IOM uint32_t BIT_LOAD_REG; /*!< (@ 0x00000004) Bit Load */ + + struct { + __IOM uint32_t BIT_LOAD : 1; /*!< [0..0] Loads 0th bit on to the pin on write. And + reads the value on pin on read into 0th bit */ + __IOM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved1 */ + } BIT_LOAD_REG_b; + }; + + union { + __IOM uint32_t WORD_LOAD_REG; /*!< (@ 0x00000008) Word Load */ + + struct { + __IOM uint32_t WORD_LOAD : 16; /*!< [15..0] Loads 1 on the pin when any of the bit in + load value is 1. On read pass the bit status into + all bits. */ + __IOM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved1 */ + } WORD_LOAD_REG_b; + }; + __IM uint32_t RESERVED; +} EGPIO_PIN_CONFIG_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief EGPIO_PORT_CONFIG [PORT_CONFIG] ([0..5]) + */ +typedef struct { + union { + __IOM uint32_t PORT_LOAD_REG; /*!< (@ 0x00000000) Port Load */ + + struct { + __IOM uint32_t PORT_LOAD : 16; /*!< [15..0] Loads the value on to pin on write. And + reads the value of load register on read */ + __IM uint32_t RES : 16; /*!< [31..16] RES */ + } PORT_LOAD_REG_b; + }; + + union { + __OM uint32_t PORT_SET_REG; /*!< (@ 0x00000004) Port Set Register */ + + struct { + __OM uint32_t PORT_SET : 16; /*!< [15..0] Sets the pin when corresponding bit is + high. Writing zero has no effect. */ + __OM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved1 */ + } PORT_SET_REG_b; + }; + + union { + __OM uint32_t PORT_CLEAR_REG; /*!< (@ 0x00000008) Port Clear Register */ + + struct { + __OM uint32_t PORT_CLEAR : 16; /*!< [15..0] Clears the pin when corresponding bit is + high. Writing zero has no effect. */ + __OM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved1 */ + } PORT_CLEAR_REG_b; + }; + + union { + __OM uint32_t PORT_MASKED_LOAD_REG; /*!< (@ 0x0000000C) Port Masked Load Register */ + + struct { + __OM uint32_t PORT_MASKED_LOAD : 16; /*!< [15..0] Only loads into pins which are not + masked. On read, pass only status unmasked + pins */ + __OM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved1 */ + } PORT_MASKED_LOAD_REG_b; + }; + + union { + __OM uint32_t PORT_TOGGLE_REG; /*!< (@ 0x00000010) Port Toggle Register */ + + struct { + __OM uint32_t PORT_TOGGLE : 16; /*!< [15..0] Toggles the pin when corresponding bit + is high. Writing zero has not effect. */ + __OM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved1 */ + } PORT_TOGGLE_REG_b; + }; + + union { + __IM uint32_t PORT_READ_REG; /*!< (@ 0x00000014) Port Read Register */ + + struct { + __IM uint32_t PORT_READ : 16; /*!< [15..0] Reads the value on GPIO pins + irrespective of the pin mode. */ + __IM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved1 */ + } PORT_READ_REG_b; + }; + __IM uint32_t RESERVED[2]; +} EGPIO_PORT_CONFIG_Type; /*!< Size = 32 (0x20) */ + +/** + * @brief EGPIO_INTR [INTR] ([0..5]) + */ +typedef struct { + union { + __IOM uint32_t GPIO_INTR_CTRL; /*!< (@ 0x00000000) GPIO Interrupt Control Register */ + + struct { + __IOM uint32_t LEVEL_HIGH_ENABLE : 1; /*!< [0..0] enables interrupt generation when + pin level is 1 */ + __IOM uint32_t LEVEL_LOW_ENABLE : 1; /*!< [1..1] enables interrupt generation when + pin level is 0 */ + __IOM uint32_t RISE_EDGE_ENABLE : 1; /*!< [2..2] enables interrupt generation when + rising edge is detected on pin */ + __IOM uint32_t FALL_EDGE_ENABLE : 1; /*!< [3..3] enables interrupt generation when + Falling edge is detected on pin */ + __IOM uint32_t MASK : 1; /*!< [4..4] Masks the interrupt. Interrupt will still be + seen in status register when enabled */ + __IOM uint32_t RESERVED1 : 3; /*!< [7..5] Reserved1 */ + __IOM uint32_t PIN_NUMBER : 4; /*!< [11..8] GPIO Pin to be chosen for + interrupt generation */ + __IOM uint32_t PORT_NUMBER : 2; /*!< [13..12] GPIO Port to be chosen for + interrupt generation */ + __IOM uint32_t RESERVED2 : 18; /*!< [31..14] Reserved2 */ + } GPIO_INTR_CTRL_b; + }; + + union { + __IOM uint32_t GPIO_INTR_STATUS; /*!< (@ 0x00000004) GPIO Interrupt Status + Register */ + + struct { + __IOM uint32_t INTERRUPT_STATUS : 1; /*!< [0..0] Gets set when interrupt + is enabled and occurs. */ + __IOM uint32_t RISE_EDGE_STATUS : 1; /*!< [1..1] Gets set when rise edge + is enabled and occurs. */ + __IOM uint32_t FALL_EDGE_STATUS : 1; /*!< [2..2] Gets set when Fall edge + is enabled and occurs. */ + __OM uint32_t MASK_SET : 1; /*!< [3..3] Mask set */ + __OM uint32_t MASK_CLEAR : 1; /*!< [4..4] Mask Clear */ + __IOM uint32_t RESERVED1 : 27; /*!< [31..5] Reserved1 */ + } GPIO_INTR_STATUS_b; + }; +} EGPIO_INTR_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief EGPIO_GPIO_GRP_INTR [GPIO_GRP_INTR] ([0..3]) + */ +typedef struct { + union { + __IOM uint32_t GPIO_GRP_INTR_CTRL_REG; /*!< (@ 0x00000000) GPIO Interrupt 0 + Control Register */ + + struct { + __IOM uint32_t AND_OR : 1; /*!< [0..0] AND/OR */ + __IOM uint32_t LEVEL_EDGE : 1; /*!< [1..1] Level/Edge */ + __IOM uint32_t ENABLE_WAKEUP : 1; /*!< [2..2] For wakeup generation, actual pin + status has to be seen(before double ranking + point) */ + __IOM uint32_t ENABLE_INTERRUPT : 1; /*!< [3..3] Enable Interrupt */ + __IOM uint32_t MASK : 1; /*!< [4..4] Mask */ + __IOM uint32_t RESERVED1 : 27; /*!< [31..5] Reserved1 */ + } GPIO_GRP_INTR_CTRL_REG_b; + }; + + union { + __IOM uint32_t GPIO_GRP_INTR_STS; /*!< (@ 0x00000004) GPIO Interrupt 0 + Status Register */ + + struct { + __IOM uint32_t INTERRUPT_STATUS : 1; /*!< [0..0] Interrupt status is available in + this bit when interrupt is enabled and + generated. When 1 is written, interrupt + gets cleared. */ + __IM uint32_t WAKEUP : 1; /*!< [1..1] Double ranked version of wakeup. + Gets set when wakeup is enabled and occurs. + When 1 is written it gets cleared */ + __IOM uint32_t RESERVED1 : 1; /*!< [2..2] Reserved1 */ + __IOM uint32_t MASK_SET : 1; /*!< [3..3] Gives zero on read */ + __IOM uint32_t MASK_CLEAR : 1; /*!< [4..4] Gives zero on read */ + __IOM uint32_t RESERVED2 : 27; /*!< [31..5] Reserved2 */ + } GPIO_GRP_INTR_STS_b; + }; +} EGPIO_GPIO_GRP_INTR_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief MCU_RET_NPSS_GPIO_CNTRL [NPSS_GPIO_CNTRL] ([0..4]) + */ +typedef struct { + union { + __IOM uint32_t NPSS_GPIO_CTRLS; /*!< (@ 0x00000000) NPSS GPIO Control register */ + + struct { + __IOM uint32_t NPSS_GPIO_MODE : 3; /*!< [2..0] NPSS GPIO 0 mode select. */ + __IOM uint32_t NPSS_GPIO_REN : 1; /*!< [3..3] NPSS GPIO 0 Input Buffer + Enable. 1- Enable 0- Disable. */ + __IOM uint32_t NPSS_GPIO_OEN : 1; /*!< [4..4] NPSS GPIO 0 Output Buffer Enable. 1- + Input Direction 0- Output Direction. */ + __IOM uint32_t NPSS_GPIO_OUT : 1; /*!< [5..5] NPSS GPIO 0 Output value. */ + __IOM uint32_t RESERVED1 : 2; /*!< [7..6] Reserved1 */ + __IOM uint32_t NPSS_GPIO_POLARITY : 1; /*!< [8..8] NPSS GPIO 0 Polarity 1 + - When signal is High 0 - When + signal is Ligh. */ + __IOM uint32_t RESERVED2 : 7; /*!< [15..9] Reserved2 */ + __IOM uint32_t USE_ULPSS_PAD : 1; /*!< [16..16] Input from ULPSS GPIOs. */ + __IOM uint32_t RESERVED3 : 15; /*!< [31..17] Reserved3 */ + } NPSS_GPIO_CTRLS_b; + }; +} MCU_RET_NPSS_GPIO_CNTRL_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief ULPCLK_ULP_SOC_GPIO_MODE_REG [ULP_SOC_GPIO_MODE_REG] ([0..15]) + */ +typedef struct { + union { + __IOM uint32_t ULP_SOC_GPIO_MODE_REG; /*!< (@ 0x00000000) ulp soc gpio mode + register */ + + struct { + __IOM uint32_t ULP_SOC_GPIO_MODE_REG : 3; /*!< [2..0] mode bits for soc gpio. */ + __IOM uint32_t RESERVED1 : 29; /*!< [31..3] reserved1 */ + } ULP_SOC_GPIO_MODE_REG_b; + }; +} ULPCLK_ULP_SOC_GPIO_MODE_REG_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief AUX_ADC_DAC_COMP_ADC_CH_BIT_MAP_CONFIG [ADC_CH_BIT_MAP_CONFIG] + * ([0..15]) + */ +typedef struct { + union { + __IOM uint32_t ADC_CH_BIT_MAP_CONFIG_0; /*!< (@ 0x00000000) This is configuration + register0 to explain the bit map for ADC + channels */ + + struct { + __IOM uint32_t CHANNEL_BITMAP : 32; /*!< [31..0] ADC Channels bit map */ + } ADC_CH_BIT_MAP_CONFIG_0_b; + }; + + union { + __IOM uint32_t ADC_CH_BIT_MAP_CONFIG_1; /*!< (@ 0x00000004) This is configuration + register1 to explain the bit map for ADC + channels */ + + struct { + __IOM uint32_t CHANNEL_BITMAP : 32; /*!< [31..0] ADC Channels bit map */ + } ADC_CH_BIT_MAP_CONFIG_1_b; + }; + + union { + __IOM uint32_t ADC_CH_BIT_MAP_CONFIG_2; /*!< (@ 0x00000008) This is configuration + register2 to explain the bit map for ADC + channels */ + + struct { + __IOM uint32_t CHANNEL_BITMAP : 32; /*!< [31..0] ADC Channels bit map */ + } ADC_CH_BIT_MAP_CONFIG_2_b; + }; + + union { + __IOM uint32_t ADC_CH_BIT_MAP_CONFIG_3; /*!< (@ 0x0000000C) This is configuration + register3 to explain the bit map for ADC + channels */ + + struct { + __IOM uint32_t CHANNEL_BITMAP : 5; /*!< [4..0] ADC Channels bit map */ + __IOM uint32_t RESERVED1 : 27; /*!< [31..5] Reserved1 */ + } ADC_CH_BIT_MAP_CONFIG_3_b; + }; +} AUX_ADC_DAC_COMP_ADC_CH_BIT_MAP_CONFIG_Type; /*!< Size = 16 (0x10) */ + +/** @} */ /* End of group Device_Peripheral_clusters */ + +/* =========================================================================================================================== + */ +/* ================ Device Specific Peripheral + * Section ================ */ +/* =========================================================================================================================== + */ + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + +/* =========================================================================================================================== + */ +/* ================ I2C0 + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief Inter Integrated Circuit(I2C) is programmable control bus that + provides support for the communications link between integrated circuits in a + system (I2C0) + */ + +typedef struct { /*!< (@ 0x44010000) I2C0 Structure */ + + union { + __IOM uint32_t IC_CON; /*!< (@ 0x00000000) This register can be written only + when the i2c is disabled, which corresponds to + IC_ENABLE[0] being set to 0. Writes at other times + have no effect. */ + + struct { + __IOM uint32_t MASTER_MODE : 1; /*!< [0..0] This bit controls whether the + I2C master is enabled. */ + __IOM uint32_t SPEED : 2; /*!< [2..1] These bits control at which speed + the I2C operates. Hardware protects against + illegal values being programmed by software. + */ + __IOM uint32_t IC_10BITADDR_SLAVE : 1; /*!< [3..3] When acting as a slave, + this bit controls whether the + I2C responds to 7- or + 10-bit addresses. */ + __IM uint32_t IC_10BITADDR_MASTER_RD_ONLY : 1; /*!< [4..4] the function of this bit + is handled by bit 12 of IC_TAR + register, and becomes a + read-only copy called + IC_10BITADDR_MASTER_rd_onl + */ + __IOM uint32_t IC_RESTART_EN : 1; /*!< [5..5] Determines whether RESTART conditions + may be sent when acting as a master */ + __IOM uint32_t IC_SLAVE_DISABLE : 1; /*!< [6..6] This bit controls whether + I2C has its slave disabled */ + __IOM uint32_t STOP_DET_IFADDRESSED : 1; /*!< [7..7] The STOP DETECTION interrupt is + generated only when the transmitted + address matches the slave address of SAR + */ + __IOM uint32_t TX_EMPTY_CTRL : 1; /*!< [8..8] This bit controls the + generation of the TX EMPTY interrupt, + as described in the IC RAW INTR + STAT register. */ + __IM uint32_t RESERVED1 : 1; /*!< [9..9] reserved1 */ + __IOM uint32_t STOP_DET_IF_MASTER_ACTIVE : 1; /*!< [10..10] In Master mode. */ + __IOM uint32_t BUS_CLEAR_FEATURE_CTRL : 1; /*!< [11..11] In Master mode. */ + __IOM uint32_t RESERVED2 : 20; /*!< [31..12] reserved2 */ + } IC_CON_b; + }; + + union { + __IOM uint32_t IC_TAR; /*!< (@ 0x00000004) I2C Target Address Register */ + + struct { + __IOM uint32_t IC_TAR : 10; /*!< [9..0] This is the target address for any + master transaction */ + __IOM uint32_t GC_OR_START : 1; /*!< [10..10] If bit 11 (SPECIAL) is set + to 1, then this bit indicates whether a + General Call or START byte command is + to be performed by the DW_apb_i2c */ + __IOM uint32_t SPECIAL : 1; /*!< [11..11] This bit indicates whether software + performs a General Call or START BYTE command */ + __IOM uint32_t IC_10BITADDR_MASTER : 1; /*!< [12..12] This bit controls + whether the i2c starts its + transfers in 7-or 10-bit + addressing mode when acting as + a master */ + __IOM uint32_t DEVICE_ID : 1; /*!< [13..13] If bit 11 (SPECIAL) is set to 1, then + this bit indicates whether a Device-ID of a + particular slave mentioned in IC_TAR[6:0] is to be + performed by the I2C Master */ + __IM uint32_t RESERVED1 : 18; /*!< [31..14] reserved1 */ + } IC_TAR_b; + }; + + union { + __IOM uint32_t IC_SAR; /*!< (@ 0x00000008) I2C Slave Address Register */ + + struct { + __IOM uint32_t IC_SAR : 10; /*!< [9..0] The IC_SAR holds the slave address when the + I2C is operating as a slave. For 7-bit addressing, + only IC_SAR[6:0] is used. */ + __IM uint32_t RESERVED1 : 22; /*!< [31..10] reserved1 */ + } IC_SAR_b; + }; + + union { + __IOM uint32_t IC_HS_MADDR; /*!< (@ 0x0000000C) I2C High Speed Master Mode + Code Address Register */ + + struct { + __IOM uint32_t IC_HS_MAR : 3; /*!< [2..0] This bit field holds the value + of the I2C HS mode master code */ + __IM uint32_t RESERVED1 : 29; /*!< [31..3] reserved1 */ + } IC_HS_MADDR_b; + }; + + union { + __IOM uint32_t IC_DATA_CMD; /*!< (@ 0x00000010) I2C Rx/Tx Data Buffer and + Command Register */ + + struct { + __IOM uint32_t DAT : 8; /*!< [7..0] This register contains the data to be + transmitted or received on the I2C bus */ + __OM uint32_t CMD : 1; /*!< [8..8] This bit controls whether a read or a + write is performed */ + __OM uint32_t STOP : 1; /*!< [9..9] This bit controls whether a STOP is + issued after the byte is sent or received */ + __OM uint32_t RESTART : 1; /*!< [10..10] This bit controls whether a RESTART is + issued before the byte is sent or received */ + __IM uint32_t FIRST_DATA_BYTE : 1; /*!< [11..11] Indicates the first data byte + received after the address phase for receive + transfer in Master receiver or Slave + receiver mode */ + __IM uint32_t RESERVED1 : 20; /*!< [31..12] reserved1 */ + } IC_DATA_CMD_b; + }; + + union { + __IOM uint32_t IC_SS_SCL_HCNT; /*!< (@ 0x00000014) Standard Speed I2C Clock + SCL High Count Register */ + + struct { + __IOM uint32_t IC_SS_SCL_HCNT : 16; /*!< [15..0] This register must be set before any + I2C bus transaction can take place to ensure + proper I/O timing */ + __IM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + } IC_SS_SCL_HCNT_b; + }; + + union { + __IOM uint32_t IC_SS_SCL_LCNT; /*!< (@ 0x00000018) Standard Speed I2C Clock + SCL Low Count Register */ + + struct { + __IOM uint32_t IC_SS_SCL_LCNT : 16; /*!< [15..0] This register must be set before any + I2C bus transaction can take place to ensure + proper I/O timing */ + __IM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + } IC_SS_SCL_LCNT_b; + }; + + union { + __IOM uint32_t IC_FS_SCL_HCNT; /*!< (@ 0x0000001C) Fast Speed I2C Clock SCL + High Count Register */ + + struct { + __IOM uint32_t IC_FS_SCL_HCNT : 16; /*!< [15..0] This register must be set before any + I2C bus transaction can take place to ensure + proper I/O timing */ + __IM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + } IC_FS_SCL_HCNT_b; + }; + + union { + __IOM uint32_t IC_FS_SCL_LCNT; /*!< (@ 0x00000020) Fast Speed I2C Clock SCL + Low Count Register */ + + struct { + __IOM uint32_t IC_FS_SCL_LCNT : 16; /*!< [15..0] This register must be set before any + I2C bus transaction can take place to ensure + proper I/O timing */ + __IM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + } IC_FS_SCL_LCNT_b; + }; + + union { + __IOM uint32_t IC_HS_SCL_HCNT; /*!< (@ 0x00000024) High Speed I2C Clock SCL + High Count Register */ + + struct { + __IOM uint32_t IC_HS_SCL_HCNT : 16; /*!< [15..0] This register must be set before any + I2C bus transaction can take place to ensure + proper I/O timing */ + __IM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + } IC_HS_SCL_HCNT_b; + }; + + union { + __IOM uint32_t IC_HS_SCL_LCNT; /*!< (@ 0x00000028) High Speed I2C Clock SCL + Low Count Register */ + + struct { + __IOM uint32_t IC_HS_SCL_LCNT : 16; /*!< [15..0] This register must be set before any + I2C bus transaction can take place to ensure + proper I/O timing */ + __IM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + } IC_HS_SCL_LCNT_b; + }; + + union { + __IM uint32_t IC_INTR_STAT; /*!< (@ 0x0000002C) I2C Interrupt Status Register */ + + struct { + __IM uint32_t R_RX_UNDER : 1; /*!< [0..0] Set if the processor attempts to + read the receive buffer + when it is empty by reading + from the IC_DATA_CMD register */ + __IM uint32_t R_RX_OVER : 1; /*!< [1..1] Set if the receive buffer is completely + filled to IC_RX_BUFFER_DEPTH and an additional byte + is received from an external I2C device */ + __IM uint32_t R_RX_FULL : 1; /*!< [2..2] Set when the receive buffer + reaches or goes above the RX_TL threshold + in the IC_RX_TL register. */ + __IM uint32_t R_TX_OVER : 1; /*!< [3..3] Set during transmit if the + transmit buffer is filled to + IC_TX_BUFFER_DEPTH and the processor + attempts to issue another I2C command by + writing to the IC_DATA_CMD register. */ + __IM uint32_t R_TX_EMPTY : 1; /*!< [4..4] This bit is set to 1 when the transmit + buffer is at or below the threshold value set in + the IC_TX_TL register. */ + __IM uint32_t R_RD_REQ : 1; /*!< [5..5] This bit is set to 1 when DW_apb_i2c is + acting as a slave and another I2C master is + attempting to read data from DW_apb_i2c. */ + __IM uint32_t R_TX_ABRT : 1; /*!< [6..6] This bit indicates if DW_apb_i2c, as an I2C + transmitter, is unable to complete the intended + actions on the contents of the transmit FIFO */ + __IM uint32_t R_RX_DONE : 1; /*!< [7..7] When the DW_apb_i2c is acting as a + slave-transmitter, this bit is set to 1 if the + master does not acknowledge a transmitted byte */ + __IM uint32_t R_ACTIVITY : 1; /*!< [8..8] This bit captures DW_apb_i2c activity and + stays set until it is cleared */ + __IM uint32_t R_STOP_DET : 1; /*!< [9..9] Indicates whether a STOP + condition has occurred on the I2C + interface regardless of whether DW_apb_i2c + is operating in slave or master mode. */ + __IM uint32_t R_START_DET : 1; /*!< [10..10] Indicates whether a START or + RESTART condition has occurred on the + I2C interface regardless of whether + DW_apb_i2c is operating in slave or + master mode. */ + __IM uint32_t R_GEN_CALL : 1; /*!< [11..11] Set only when a General Call address is + received and it is acknowledged */ + __IM uint32_t R_RESTART_DET : 1; /*!< [12..12] Indicates whether a RESTART condition + has occurred on the I2C interface when + DW_apb_i2c is operating in slave mode and the + slave is the addressed slave */ + __IM uint32_t R_MST_ON_HOLD : 1; /*!< [13..13] Indicates whether a master is holding + the bus and the Tx FIFO is empty. */ + __IM uint32_t M_SCL_STUCK_AT_LOW : 1; /*!< [14..14] Indicates whether the + SCL Line is stuck at low for + the IC_SCL_STUCK_LOW_TIMOUT + number of ic_clk periods */ + __IM uint32_t RESERVED1 : 17; /*!< [31..15] reserved1 */ + } IC_INTR_STAT_b; + }; + + union { + __IOM uint32_t IC_INTR_MASK; /*!< (@ 0x00000030) I2C Interrupt Mask Register */ + + struct { + __IOM uint32_t M_RX_UNDER : 1; /*!< [0..0] This bit mask their + corresponding interrupt status bits in + the IC_INTR_STAT register. */ + __IOM uint32_t M_RX_OVER : 1; /*!< [1..1] This bit mask their corresponding interrupt + status bits in the IC_INTR_STAT register. */ + __IOM uint32_t M_RX_FULL : 1; /*!< [2..2] This bit mask their corresponding interrupt + status bits in the IC_INTR_STAT register. */ + __IOM uint32_t M_TX_OVER : 1; /*!< [3..3] This bit mask their corresponding interrupt + status bits in the IC_INTR_STAT register */ + __IOM uint32_t M_TX_EMPTY : 1; /*!< [4..4] This bit mask their + corresponding interrupt status bits in + the IC_INTR_STAT register. */ + __IOM uint32_t M_RD_REQ : 1; /*!< [5..5] This bit mask their corresponding interrupt + status bits in the IC_INTR_STAT register. */ + __IOM uint32_t M_TX_ABRT : 1; /*!< [6..6] This bit mask their corresponding interrupt + status bits in the IC_INTR_STAT register. */ + __IOM uint32_t M_RX_DONE : 1; /*!< [7..7] This bit mask their corresponding interrupt + status bits in the IC_INTR_STAT register. */ + __IOM uint32_t M_ACTIVITY : 1; /*!< [8..8] This bit mask their + corresponding interrupt status bits in + the IC_INTR_STAT register. */ + __IOM uint32_t M_STOP_DET : 1; /*!< [9..9] This bit mask their + corresponding interrupt status bits in + the IC_INTR_STAT register. */ + __IOM uint32_t M_START_DET : 1; /*!< [10..10] This bit mask their corresponding + interrupt status bits in the IC_INTR_STAT + register. */ + __IOM uint32_t M_GEN_CALL : 1; /*!< [11..11] This bit mask their + corresponding interrupt status bits in + the IC_INTR_STAT register. */ + __IOM uint32_t M_RESTART_DET : 1; /*!< [12..12] Indicates whether a RESTART condition + has occurred on the I2C interface when + DW_apb_i2c is operating in slave mode and the + slave is the addressed slave */ + __IOM uint32_t M_MST_ON_HOLD : 1; /*!< [13..13] Indicates whether a master is holding + the bus and the Tx FIFO is empty. */ + __IOM uint32_t M_SCL_STUCK_AT_LOW : 1; /*!< [14..14] Indicates whether the + SCL Line is stuck at low for + the IC_SCL_STUCK_LOW_TIMOUT + number of ic_clk periods */ + __IM uint32_t RESERVED1 : 17; /*!< [31..15] reserved1 */ + } IC_INTR_MASK_b; + }; + + union { + __IM uint32_t IC_RAW_INTR_STAT; /*!< (@ 0x00000034) I2C Raw Interrupt Status + Register */ + + struct { + __IM uint32_t RX_UNDER : 1; /*!< [0..0] Set if the processor attempts to read the + receive buffer when it is empty by reading from the + IC_DATA_CMD register */ + __IM uint32_t RX_OVER : 1; /*!< [1..1] Set if the receive buffer is completely + filled to IC_RX_BUFFER_DEPTH and an additional byte is + received from an external I2C device */ + __IM uint32_t RX_FULL : 1; /*!< [2..2] Set when the receive buffer reaches + or goes above the RX_TL threshold in the + IC_RX_TL register. */ + __IM uint32_t TX_OVER : 1; /*!< [3..3] Set during transmit if the transmit buffer is + filled to IC_TX_BUFFER_DEPTH and the processor + attempts to issue another I2C command by writing to + the IC_DATA_CMD register. */ + __IM uint32_t TX_EMPTY : 1; /*!< [4..4] This bit is set to 1 when the + transmit buffer is at or below the + threshold value set in the IC_TX_TL + register. */ + __IM uint32_t RD_REQ : 1; /*!< [5..5] This bit is set to 1 when DW_apb_i2c is acting + as a slave and another I2C master is attempting to read + data from DW_apb_i2c. */ + __IM uint32_t TX_ABRT : 1; /*!< [6..6] This bit indicates if DW_apb_i2c, as an I2C + transmitter, is unable to complete the intended + actions on the contents of the transmit FIFO */ + __IM uint32_t RX_DONE : 1; /*!< [7..7] When the DW_apb_i2c is acting as a + slave-transmitter, this bit is set to 1 if the master + does not acknowledge a transmitted byte */ + __IM uint32_t ACTIVITY : 1; /*!< [8..8] This bit captures DW_apb_i2c activity and + stays set until it is cleared */ + __IM uint32_t STOP_DET : 1; /*!< [9..9] Indicates whether a STOP condition has + occurred on the I2C interface regardless of whether + DW_apb_i2c is operating in slave or master mode. */ + __IM uint32_t START_DET : 1; /*!< [10..10] Indicates whether a START or RESTART + condition has occurred on the I2C interface + regardless of whether DW_apb_i2c is operating in + slave or master mode. */ + __IM uint32_t GEN_CALL : 1; /*!< [11..11] Set only when a General Call address is + received and it is acknowledged */ + __IM uint32_t RESTART_DET : 1; /*!< [12..12] Indicates whether a RESTART condition + has occurred on the I2C interface when DW_apb_i2c + is operating in slave mode and the slave is the + addressed slave */ + __IM uint32_t MST_ON_HOLD : 1; /*!< [13..13] Indicates whether a master is holding + the bus and the Tx FIFO is empty. */ + __IM uint32_t SCL_STUCK_AT_LOW : 1; /*!< [14..14] Indicates whether the + SCL Line is stuck at low for the + IC_SCL_STUCK_LOW_TIMOUT number of + ic_clk periods */ + __IM uint32_t RESERVED1 : 17; /*!< [31..15] reserved1 */ + } IC_RAW_INTR_STAT_b; + }; + + union { + __IOM uint32_t IC_RX_TL; /*!< (@ 0x00000038) I2C Receive FIFO Threshold Register */ + + struct { + __IOM uint32_t RX_TL : 8; /*!< [7..0] Receive FIFO Threshold Level */ + __IM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + } IC_RX_TL_b; + }; + + union { + __IOM uint32_t IC_TX_TL; /*!< (@ 0x0000003C) I2C Transmit FIFO Threshold Register */ + + struct { + __IOM uint32_t TX_TL : 8; /*!< [7..0] Transmit FIFO Threshold Level */ + __IM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + } IC_TX_TL_b; + }; + + union { + __IM uint32_t IC_CLR_INTR; /*!< (@ 0x00000040) Clear Combined and Individual + Interrupt Register */ + + struct { + __IM uint32_t CLR_INTR : 1; /*!< [0..0] Read this register to clear the combined + interrupt, all individual interrupts, and the + IC_TXABRT_SOURCE register */ + __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + } IC_CLR_INTR_b; + }; + + union { + __IM uint32_t IC_CLR_RX_UNDER; /*!< (@ 0x00000044) Clear RX_UNDER Interrupt + Register */ + + struct { + __IM uint32_t CLR_RX_UNDER : 1; /*!< [0..0] Read this register to clear + the RX_UNDER interrupt (bit 0) of the + IC_RAW_INTR_STAT register. */ + __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + } IC_CLR_RX_UNDER_b; + }; + + union { + __IM uint32_t IC_CLR_RX_OVER; /*!< (@ 0x00000048) Clear RX_OVER Interrupt + Register */ + + struct { + __IM uint32_t CLR_RX_OVER : 1; /*!< [0..0] Read this register to clear the + RX_OVER interrupt (bit 1) of the + IC_RAW_INTR_STAT register */ + __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + } IC_CLR_RX_OVER_b; + }; + + union { + __IM uint32_t IC_CLR_TX_OVER; /*!< (@ 0x0000004C) Clear TX_OVER Interrupt + Register */ + + struct { + __IM uint32_t CLR_TX_OVER : 1; /*!< [0..0] Read this register to clear the + TX_OVER interrupt (bit 3) of the + IC_RAW_INTR_STAT register. */ + __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + } IC_CLR_TX_OVER_b; + }; + + union { + __IM uint32_t IC_CLR_RD_REQ; /*!< (@ 0x00000050) Clear RD_REQ Interrupt Register */ + + struct { + __IM uint32_t CLR_RD_REQ : 1; /*!< [0..0] Read this register to clear the + RD_REQ interrupt (bit 5) of the + IC_RAW_INTR_STAT register. */ + __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + } IC_CLR_RD_REQ_b; + }; + + union { + __IM uint32_t IC_CLR_TX_ABRT; /*!< (@ 0x00000054) Clear TX_ABRT Interrupt + Register */ + + struct { + __IM uint32_t CLR_TX_ABRT : 1; /*!< [0..0] Read this register to clear the TX_ABRT + interrupt (bit 6) of the C_RAW_INTR_STAT register, + and the IC_TX_ABRT_SOURCE register */ + __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + } IC_CLR_TX_ABRT_b; + }; + + union { + __IM uint32_t IC_CLR_RX_DONE; /*!< (@ 0x00000058) Clear RX_DONE Interrupt + Register */ + + struct { + __IM uint32_t CLR_RX_DONE : 1; /*!< [0..0] Read this register to clear the + RX_DONE interrupt (bit 7) of the + IC_RAW_INTR_STAT register */ + __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + } IC_CLR_RX_DONE_b; + }; + + union { + __IM uint32_t IC_CLR_ACTIVITY; /*!< (@ 0x0000005C) Clear ACTIVITY Interrupt + Register */ + + struct { + __IM uint32_t CLR_ACTIVITY : 1; /*!< [0..0] Reading this register clears + the ACTIVITY interrupt if the I2C is + not active any more */ + __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + } IC_CLR_ACTIVITY_b; + }; + + union { + __IM uint32_t IC_CLR_STOP_DET; /*!< (@ 0x00000060) Clear STOP_DET Interrupt + Register */ + + struct { + __IM uint32_t CLR_STOP_DET : 1; /*!< [0..0] Read this register to clear + the STOP_DET interrupt (bit 9) of the + IC_RAW_INTR_STAT register. */ + __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + } IC_CLR_STOP_DET_b; + }; + + union { + __IM uint32_t IC_CLR_START_DET; /*!< (@ 0x00000064) Clear START_DET + Interrupt Register */ + + struct { + __IM uint32_t CLR_START_DET : 1; /*!< [0..0] Read this register to clear + the START_DET interrupt (bit 10) of + the IC_RAW_INTR_STAT register */ + __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + } IC_CLR_START_DET_b; + }; + + union { + __IM uint32_t IC_CLR_GEN_CALL; /*!< (@ 0x00000068) Clear GEN_CALL Interrupt + Register */ + + struct { + __IM uint32_t CLR_GEN_CALL : 1; /*!< [0..0] Read this register to clear + the GEN_CALL interrupt (bit 11) of + IC_RAW_INTR_STAT register */ + __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + } IC_CLR_GEN_CALL_b; + }; + + union { + __IOM uint32_t IC_ENABLE; /*!< (@ 0x0000006C) Clear GEN_CALL Interrupt Register */ + + struct { + __IOM uint32_t EN : 1; /*!< [0..0] Controls whether the DW_apb_i2c is enabled */ + __IOM uint32_t ABORT : 1; /*!< [1..1] When set, the controller initiates + the transfer abort */ + __IOM uint32_t TX_CMD_BLOCK : 1; /*!< [2..2] none */ + __IOM uint32_t SDA_STUCK_RECOVERY_ENABLE : 1; /*!< [3..3] SDA STUCK + RECOVERY ENABLE */ + __IM uint32_t RESERVED1 : 28; /*!< [31..4] reserved1 */ + } IC_ENABLE_b; + }; + + union { + __IM uint32_t IC_STATUS; /*!< (@ 0x00000070) I2C Status Register */ + + struct { + __IM uint32_t ACTIVITY : 1; /*!< [0..0] I2C Activity Status */ + __IM uint32_t TFNF : 1; /*!< [1..1] Transmit FIFO Not Full */ + __IM uint32_t TFE : 1; /*!< [2..2] Transmit FIFO Completely Empty */ + __IM uint32_t RFNE : 1; /*!< [3..3] Receive FIFO Not Empty */ + __IM uint32_t RFF : 1; /*!< [4..4] Receive FIFO Completely Full */ + __IM uint32_t MST_ACTIVITY : 1; /*!< [5..5] Master FSM Activity Status */ + __IM uint32_t SLV_ACTIVITY : 1; /*!< [6..6] Slave FSM Activity Status */ + __IM uint32_t MST_HOLD_TX_FIFO_EMPTY : 1; /*!< [7..7] The I2C master stalls the + write transfer when Tx FIFO is empty, + and the the last byte does not have + the Stop bit set. */ + __IM uint32_t MST_HOLD_RX_FIFO_FULL : 1; /*!< [8..8] This bit indicates the BUS Hold + in Master mode due to Rx FIFO is Full + and additional byte has been received. + */ + __IM uint32_t SLV_HOLD_TX_FIFO_EMPTY : 1; /*!< [9..9] This bit indicates the BUS + Hold in Slave mode for the + Read request when the Tx FIFO is + empty. */ + __IM uint32_t SLV_HOLD_RX_FIFO_FULL : 1; /*!< [10..10] This bit indicates the BUS + Hold in Slave mode due to the Rx FIFO + being Full and an additional byte being + received. */ + __IM uint32_t SDA_STUCK_NOT_RECOVERED : 1; /*!< [11..11] This bit indicates that an + SDA stuck at low is not recovered + after the recovery mechanism. */ + __IM uint32_t RESERVED1 : 20; /*!< [31..12] reserved1 */ + } IC_STATUS_b; + }; + + union { + __IM uint32_t IC_TXFLR; /*!< (@ 0x00000074) I2C Transmit FIFO Level Register */ + + struct { + __IM uint32_t TXFLR : 4; /*!< [3..0] Contains the number of valid data + entries in the transmit FIFO. */ + __IM uint32_t RESERVED1 : 28; /*!< [31..4] reserved1 */ + } IC_TXFLR_b; + }; + + union { + __IM uint32_t IC_RXFLR; /*!< (@ 0x00000078) I2C Receive FIFO Level Register */ + + struct { + __IM uint32_t RXFLR : 4; /*!< [3..0] Receive FIFO Level. Contains the number of + valid data entries in the receive FIFO */ + __IM uint32_t RESERVED1 : 28; /*!< [31..4] reserved1 */ + } IC_RXFLR_b; + }; + + union { + __IOM uint32_t IC_SDA_HOLD; /*!< (@ 0x0000007C) I2C SDA Hold Time Length Register */ + + struct { + __IOM uint32_t IC_SDA_TX_HOLD : 16; /*!< [15..0] Sets the required SDA hold time in + units of ic_clk period,when I2C acts as a + transmitter. */ + __IOM uint32_t IC_SDA_RX_HOLD : 8; /*!< [23..16] Sets the required SDA hold time in + units of ic_clk period,when I2C acts as a + receiver. */ + __IM uint32_t RESERVED1 : 8; /*!< [31..24] reserved1 */ + } IC_SDA_HOLD_b; + }; + + union { + __IM uint32_t IC_TX_ABRT_SOURCE; /*!< (@ 0x00000080) I2C Transmit Abort + Source Register */ + + struct { + __IM uint32_t ABRT_7B_ADDR_NOACK : 1; /*!< [0..0] 1: Master is in 7-bit addressing + mode and the address sent was not + acknowledged by any slave */ + __IM uint32_t ABRT_10ADDR1_NOACK : 1; /*!< [1..1] 1: Master is in 10-bit + address mode and the first 10-bit + address byte was not + acknowledged by any slave */ + __IM uint32_t ABRT_10ADDR2_NOACK : 1; /*!< [2..2] 1: Master is in 10-bit address + mode and the second address byte of the + 10-bit address was not acknowledged by any + slave */ + __IM uint32_t ABRT_TXDATA_NOACK : 1; /*!< [3..3] 1: This is a master-mode only bit. + Master has received an acknowledgement for + the address, but when it sent data byte(s) + following the address, it did not receive an + acknowledge from the remote slave(s) */ + __IM uint32_t ABRT_GCALL_NOACK : 1; /*!< [4..4] 1: DW_apb_i2c in master mode sent a + General Call and no slave on the bus + acknowledged the General Call */ + __IM uint32_t ABRT_GCALL_READ : 1; /*!< [5..5] 1: DW_apb_i2c in master mode sent a + General Call but the user programmed the byte + following the General Call + to be a read from the bus (IC_DATA_CMD[9] + is set to 1) */ + __IM uint32_t ABRT_HS_ACKDET : 1; /*!< [6..6] 1: Master is in High Speed + mode and the High Speed Master code + was acknowledged */ + __IM uint32_t ABRT_SBYTE_ACKDET : 1; /*!< [7..7] 1: Master has sent a START Byte and + the START Byte was acknowledged (wrong + behavior) */ + __IM uint32_t ABRT_HS_NORSTRT : 1; /*!< [8..8] 1: The restart is disabled + (IC_RESTART_EN bit (IC_CON[5]) = 0) and the + user is trying to use the master to transfer + data in High Speed mode */ + __IM uint32_t ABRT_SBYTE_NORSTRT : 1; /*!< [9..9] 1: The restart is disabled + (IC_RESTART_EN bit (IC_CON[5]) + = 0) and the user is trying to send a + START Byte */ + __IM uint32_t ABRT_10B_RD_NORSTRT : 1; /*!< [10..10] 1: The restart is disabled + (IC_RESTART_EN bit (IC_CON[5]) = 0) and + the master sends a read command in 10-bit + addressing mode */ + __IM uint32_t ABRT_MASTER_DIS : 1; /*!< [11..11] 1: User tries to initiate a Master + operation with the Master mode disabled */ + __IM uint32_t ARB_LOST : 1; /*!< [12..12] 1: Master has lost arbitration, or if + IC_TX_ABRT_SOURCE[14] is also set, then the slave + transmitter has lost arbitration */ + __IM uint32_t ABRT_SLVFLUSH_TXFIFO : 1; /*!< [13..13] 1: Slave has received a + read command and some data exists in + the TX FIFO so the slave issues a + TX_ABRT interrupt to flush old data + in TX FIFO */ + __IM uint32_t ABRT_SLV_ARBLOST : 1; /*!< [14..14] 1: Slave lost the bus + while transmitting data to a remote + master. IC_TX_ABRT_SOURCE[12] is + set at the same time */ + __IM uint32_t ABRT_SLVRD_INTX : 1; /*!< [15..15] 1: When the processor side responds + to a slave mode request for data to be + transmitted to a remote master and + user writes a 1 in CMD (bit 8) of + IC_DATA_CMD register */ + __IM uint32_t ABRT_USER_ABRT : 1; /*!< [16..16] This is a master-mode-only bit. + Master has detected the transfer abort + (IC_ENABLE[1]). */ + __IM uint32_t ABRT_SDA_STUCK_AT_LOW : 1; /*!< [17..17] Master detects the + SDA is Stuck at low for the + IC_SDA_STUCK_AT_LOW_TI EOUT + value of ic_clks */ + __IM uint32_t ABRT_DEVICE_NOACK : 1; /*!< [18..18] Master initiates the DEVICE_ID + transfer and the device ID sent is not + acknowledged by any slave */ + __IM uint32_t ABRT_DEVICE_SLVADDR_NOACK : 1; /*!< [19..19] Master is initiating the + DEVICE_ID transfer and the slave + address sent was not acknowledged by + any slave */ + __IM uint32_t ABRT_DEVICE_WRITE : 1; /*!< [20..20] Master is initiating the + DEVICE_ID transfer and the + Tx- FIFO consists of write commands. */ + __IM uint32_t RESERVED1 : 2; /*!< [22..21] reserved1 */ + __IM uint32_t TX_FLUSH_CNT : 9; /*!< [31..23] This field indicates the number of Tx + FIFO data commands that are flushed due to + TX_ABRT interrupt */ + } IC_TX_ABRT_SOURCE_b; + }; + + union { + __IOM uint32_t IC_SLV_DATA_NACK_ONLY; /*!< (@ 0x00000084) Generate Slave + Data NACK Register */ + + struct { + __IOM uint32_t NACK : 1; /*!< [0..0] Generate NACK. This NACK generation only occurs + when DW_apb_i2c is a slave receiver. */ + __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + } IC_SLV_DATA_NACK_ONLY_b; + }; + + union { + __IOM uint32_t IC_DMA_CR; /*!< (@ 0x00000088) DMA Control Register */ + + struct { + __IOM uint32_t RDMAE : 1; /*!< [0..0] Receive DMA Enable */ + __IOM uint32_t TDMAE : 1; /*!< [1..1] Transmit DMA Enable.This bit enables/disables + the transmit FIFO DMA channel */ + __IM uint32_t RESERVED1 : 30; /*!< [31..2] reserved1 */ + } IC_DMA_CR_b; + }; + + union { + __IOM uint32_t IC_DMA_TDLR; /*!< (@ 0x0000008C) DMA Transmit Data Level Register */ + + struct { + __IOM uint32_t DMATDL : 4; /*!< [3..0] This bit field controls the level at which a + DMA request is made by the transmit logic */ + __IM uint32_t RESERVED1 : 28; /*!< [31..4] reserved1 */ + } IC_DMA_TDLR_b; + }; + + union { + __IOM uint32_t IC_DMA_RDLR; /*!< (@ 0x00000090) I2C Receive Data Level Register */ + + struct { + __IOM uint32_t DMARDL : 4; /*!< [3..0] This bit field controls the level at which a + DMA request is made by the receive logic */ + __IM uint32_t RESERVED1 : 28; /*!< [31..4] reserved1 */ + } IC_DMA_RDLR_b; + }; + + union { + __IOM uint32_t IC_SDA_SETUP; /*!< (@ 0x00000094) I2C SDA Setup Register */ + + struct { + __IOM uint32_t SDA_SETUP : 8; /*!< [7..0] This register controls the amount of time + delay (in terms of number of ic_clk clock periods) + */ + __IM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + } IC_SDA_SETUP_b; + }; + + union { + __IOM uint32_t IC_ACK_GENERAL_CALL; /*!< (@ 0x00000098) I2C ACK General Call + Register */ + + struct { + __IOM uint32_t ACK_GEN_CALL : 1; /*!< [0..0] ACK General Call */ + __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + } IC_ACK_GENERAL_CALL_b; + }; + + union { + __IM uint32_t IC_ENABLE_STATUS; /*!< (@ 0x0000009C) I2C Enable Status Register */ + + struct { + __IM uint32_t IC_EN : 1; /*!< [0..0] This bit always reflects the value + driven on the output port ic_en. */ + __IM uint32_t SLV_DISABLED_WHILE_BUSY : 1; /*!< [1..1] This bit indicates if a + potential or active Slave operation + has been aborted due to + the setting of the IC_ENABLE register + from 1 to 0 */ + __IM uint32_t SLV_RX_DATA_LOST : 1; /*!< [2..2] Slave Received Data Lost */ + __IM uint32_t RESERVED1 : 29; /*!< [31..3] reserved1 */ + } IC_ENABLE_STATUS_b; + }; + + union { + __IOM uint32_t IC_FS_SPKLEN; /*!< (@ 0x000000A0) I2C SS and FS Spike + Suppression Limit Register */ + + struct { + __IOM uint32_t IC_FS_SPKLEN : 8; /*!< [7..0] This register sets the + duration, measured in ic_clk cycles, + of the longest spike in the + SCL or SDA lines that are filtered + out by the spike + suppression logic */ + __IM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + } IC_FS_SPKLEN_b; + }; + + union { + __IOM uint32_t IC_HS_SPKLEN; /*!< (@ 0x000000A4) I2C HS Spike Suppression + Limit Register */ + + struct { + __IOM uint32_t IC_HS_SPKLEN : 8; /*!< [7..0] This register sets the + duration, measured in ic_clk cycles, + of the longest spike in the + SCL or SDA lines that are filtered + out by the spike + suppression logic */ + __IM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + } IC_HS_SPKLEN_b; + }; + + union { + __IM uint32_t IC_CLR_RESTART_DET; /*!< (@ 0x000000A8) Clear RESTART_DET + Interrupt Register */ + + struct { + __IM uint32_t CLR_RESTART_DET : 1; /*!< [0..0] Read this register to clear + the RESTART_DET interrupt (bit 12) + of the IC_RAW_INTR_STAT registe */ + __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + } IC_CLR_RESTART_DET_b; + }; + + union { + __IOM uint32_t IC_SCL_STUCK_AT_LOW_TIMEOUT; /*!< (@ 0x000000AC) I2C SCL + Stuck at Low Timeout */ + + struct { + __IOM uint32_t IC_SCL_STUCK_LOW_TIMEOUT : 32; /*!< [31..0] Generates the interrupt to + indicate SCL stuck at low if it + detects the SCL stuck at low for the + IC_SCL_STUCK_LOW_TIMEOUT in units of + ic_clk period */ + } IC_SCL_STUCK_AT_LOW_TIMEOUT_b; + }; + + union { + __IOM uint32_t IC_SDA_STUCK_AT_LOW_TIMEOUT; /*!< (@ 0x000000B0) I2C SDA + Stuck at Low Timeout */ + + struct { + __IOM uint32_t IC_SDA_STUCK_LOW_TIMEOUT : 32; /*!< [31..0] Initiates the recovery of + SDA line , if it detects the SDA stuck + at low for the + IC_SDA_STUCK_LOW_TIMEOUT in units of + ic_clk period. */ + } IC_SDA_STUCK_AT_LOW_TIMEOUT_b; + }; + + union { + __IM uint32_t IC_CLR_SCL_STUCK_DET; /*!< (@ 0x000000B4) Clear SCL Stuck at + Low Detect Interrupt Register */ + + struct { + __IM uint32_t CLR_SCL_STUCK : 1; /*!< [0..0] Read this register to clear + the SCL_STUCK_DET interrupt */ + __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + } IC_CLR_SCL_STUCK_DET_b; + }; + + union { + __IM uint32_t IC_DEVICE_ID; /*!< (@ 0x000000B8) I2C Device ID */ + + struct { + __IM uint32_t DEVICE_ID : 24; /*!< [23..0] Contains the Device-ID of the component + assigned through the configuration parameter */ + __IM uint32_t RESERVED1 : 8; /*!< [31..24] reserved1 */ + } IC_DEVICE_ID_b; + }; + + union { + __IOM uint32_t IC_SMBUS_CLOCK_LOW_SEXT; /*!< (@ 0x000000BC) SMBUS Slave Clock Extend + Timeout Register */ + + struct { + __IOM uint32_t SMBUS_CLK_LOW_SEXT_TIMEOUT : 32; /*!< [31..0] The values in this + register are in units of ic_clk + period. */ + } IC_SMBUS_CLOCK_LOW_SEXT_b; + }; + + union { + __IOM uint32_t IC_SMBUS_CLOCK_LOW_MEXT; /*!< (@ 0x000000C0) SMBUS Master extend clock + Timeout Register */ + + struct { + __IOM uint32_t SMBUS_CLK_LOW_MEXT_TIMEOUT : 32; /*!< [31..0] The values in this + register are in units of ic_clk + period.. */ + } IC_SMBUS_CLOCK_LOW_MEXT_b; + }; + + union { + __IOM uint32_t IC_SMBUS_THIGH_MAX_IDLE_COUNT; /*!< (@ 0x000000C4) SMBus Thigh MAX + Bus-Idle count Register */ + + struct { + __IOM uint32_t SMBUS_THIGH_MAX_BUS_IDLE_CNT : 16; /*!< [15..0] The values in this + register are in units of ic_clk + period. */ + __IOM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved1 */ + } IC_SMBUS_THIGH_MAX_IDLE_COUNT_b; + }; + + union { + __IOM uint32_t IC_SMBUS_INTR_STAT; /*!< (@ 0x000000C8) SMBUS Interrupt + Status Register */ + + struct { + __IOM uint32_t RESERVED1 : 32; /*!< [31..0] Reserved1 */ + } IC_SMBUS_INTR_STAT_b; + }; + + union { + __IOM uint32_t IC_SMBUS_INTR_MASK; /*!< (@ 0x000000CC) Interrupt Mask Register */ + + struct { + __IOM uint32_t RESERVED1 : 32; /*!< [31..0] Reserved1 */ + } IC_SMBUS_INTR_MASK_b; + }; + + union { + __IOM uint32_t IC_SMBUS_INTR_RAW_STATUS; /*!< (@ 0x000000D0) SMBUS Raw + Interrupt Status Register */ + + struct { + __IOM uint32_t RESERVED1 : 32; /*!< [31..0] Reserved1. */ + } IC_SMBUS_INTR_RAW_STATUS_b; + }; + + union { + __IOM uint32_t IC_CLR_SMBUS_INTR; /*!< (@ 0x000000D4) Clear SMBUS Interrupt + Register */ + + struct { + __IOM uint32_t RESERVED1 : 32; /*!< [31..0] RESERVED1 */ + } IC_CLR_SMBUS_INTR_b; + }; + + union { + __IOM uint32_t IC_OPTIONAL_SAR; /*!< (@ 0x000000D8) Optional Slave Address + Register */ + + struct { + __IOM uint32_t RESERVED1 : 32; /*!< [31..0] Reserved1. */ + } IC_OPTIONAL_SAR_b; + }; + + union { + __IOM uint32_t IC_SMBUS_UDID_LSB; /*!< (@ 0x000000DC) SMBUS ARP UDID LSB Register */ + + struct { + __IOM uint32_t IC_SMBUS_ARP_UDID_LSB : 32; /*!< [31..0] This field is used to store + the LSB 32 bit value of slave unique + device identifier used in Address + Resolution Protocol. */ + } IC_SMBUS_UDID_LSB_b; + }; + __IM uint32_t RESERVED[5]; + + union { + __IM uint32_t IC_COMP_PARAM_1; /*!< (@ 0x000000F4) I2C HS Spike Suppression + Limit Register */ + + struct { + __IM uint32_t CLR_RESTART_DET : 2; /*!< [1..0] Read this register to clear the + RESTART_DET interrupt (bit 12) of the + IC_RAW_INTR_STAT register */ + __IM uint32_t MAX_SPEED_MODE : 2; /*!< [3..2] Maximum Speed Mode */ + __IM uint32_t HC_COUNT_VALUES : 1; /*!< [4..4] Hard Code the count values */ + __IM uint32_t INTR_IO : 1; /*!< [5..5] Single Interrupt Output port */ + __IM uint32_t HAS_DMA : 1; /*!< [6..6] DMA Handshake Interface signal */ + __IM uint32_t ADD_ENCODED_PARAMS : 1; /*!< [7..7] Add Encoded Parameters */ + __IM uint32_t RX_BUFFER_DEPTH : 8; /*!< [15..8] Depth of receive buffer;the buffer + is 8 bits wide;2 to 256 */ + __IM uint32_t TX_BUFFER_DEPTH : 8; /*!< [23..16] Depth of Transmit buffer;the buffer + is 8 bits wide;2 to 256 */ + __IM uint32_t RESERVED1 : 8; /*!< [31..24] reserved1 */ + } IC_COMP_PARAM_1_b; + }; + + union { + __IM uint32_t IC_COMP_VERSION; /*!< (@ 0x000000F8) I2C Component Version Register */ + + struct { + __IM uint32_t IC_COMP_VERSION : 32; /*!< [31..0] Signifies the component + version */ + } IC_COMP_VERSION_b; + }; + + union { + __IM uint32_t IC_COMP_TYPE; /*!< (@ 0x000000FC) I2C Component Type Register */ + + struct { + __IM uint32_t IC_COMP_TYPE : 32; /*!< [31..0] Design ware Component Type + number = 0x44_57_01_40 */ + } IC_COMP_TYPE_b; + }; +} I2C0_Type; /*!< Size = 256 (0x100) */ + +/* =========================================================================================================================== + */ +/* ================ MCPWM + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief The Motor Control PWM (MCPWM) controller is used to generate a + periodic pulse waveform, which is useful in motor control and power control + applications (MCPWM) + */ + +typedef struct { /*!< (@ 0x47070000) MCPWM Structure */ + + union { + __IM uint32_t PWM_INTR_STS; /*!< (@ 0x00000000) PWM Interrupt Status Register */ + + struct { + __IM uint32_t RISE_PWM_TIME_PERIOD_MATCH_INTR_CH0 : 1; /*!< [0..0] This time base + interrupt for 0th channel + without considering + postscaler */ + __IM uint32_t PWM_TIME_PRD_MATCH_INTR_CH0 : 1; /*!< [1..1] This time base interrupt + for 0th channel, which considers + postscaler value */ + __IM uint32_t FLT_A_INTR : 1; /*!< [2..2] When the fault A pin is driven + low, this interrupt is raised. */ + __IM uint32_t FLT_B_INTR : 1; /*!< [3..3] When the fault B pin is driven + low, this interrupt is raised. */ + __IM uint32_t RISE_PWM_TIME_PERIOD_MATCH_INTR_CH1 : 1; /*!< [4..4] This time base + interrupt for 1st channel + without considering + postscaler value */ + __IM uint32_t PWM_TIME_PRD_MATCH_INTR_CH1 : 1; /*!< [5..5] This time base interrupt + for 1st channel, which considers + postscaler value. */ + __IM uint32_t RISE_PWM_TIME_PERIOD_MATCH_INTR_CH2 : 1; /*!< [6..6] This time base + interrupt for 2nd channel + without considering + postscaler value. */ + __IM uint32_t PWM_TIME_PRD_MATCH_INTR_CH2 : 1; /*!< [7..7] This time base interrupt + for 2nd channel, which considers + postscaler value */ + __IM uint32_t RISE_PWM_TIME_PERIOD_MATCH_INTR_CH3 : 1; /*!< [8..8] This time base + interrupt for 3rd channel + without considering + postscaler value. */ + __IM uint32_t PWM_TIME_PRD_MATCH_INTR_CH3 : 1; /*!< [9..9] This time base interrupt + for 3rd channel, which considers + postscaler value. */ + __IM uint32_t RESERVED1 : 22; /*!< [31..10] reserved1 */ + } PWM_INTR_STS_b; + }; + + union { + __IOM uint32_t PWM_INTR_UNMASK; /*!< (@ 0x00000004) PWM Interrupt Unmask Register */ + + struct { + __IOM uint32_t PWM_INTR_UNMASK : 16; /*!< [15..0] Interrupt Unmask */ + __IOM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + } PWM_INTR_UNMASK_b; + }; + + union { + __IOM uint32_t PWM_INTR_MASK; /*!< (@ 0x00000008) PWM Interrupt mask Register */ + + struct { + __IOM uint32_t PWM_INTR_UNMASK : 16; /*!< [15..0] Interrupt Mask */ + __IOM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + } PWM_INTR_MASK_b; + }; + + union { + __IOM uint32_t PWM_INTR_ACK; /*!< (@ 0x0000000C) PWM Interrupt + Acknowledgement Register */ + + struct { + __OM uint32_t RISE_PWM_TIME_PERIOD_MATCH_CH0_ACK : 1; /*!< [0..0] pwm time + period match + interrupt for 0th + channel will be + cleared. */ + __OM uint32_t PWM_TIME_PRD_MATCH_INTR_CH0_ACK : 1; /*!< [1..1] pwm time period match + interrupt for 0th channel will + be cleared */ + __OM uint32_t FLT_A_INTR_ACK : 1; /*!< [2..2] pwm fault A interrupt will + be cleared. */ + __OM uint32_t FLT_B_INTR_ACK : 1; /*!< [3..3] pwm fault B interrupt will + be cleared. */ + __OM uint32_t RISE_PWM_TIME_PERIOD_MATCH_CH1_ACK : 1; /*!< [4..4] pwm time + period match + interrupt for 1st + channel will be + cleared */ + __OM uint32_t PWM_TIME_PRD_MATCH_INTR_CH1_ACK : 1; /*!< [5..5] pwm time period match + interrupt for 1st channel will + be cleared. */ + __OM uint32_t RISE_PWM_TIME_PERIOD_MATCH_CH2_ACK : 1; /*!< [6..6] pwm time + period match + interrupt for 2nd + channel will be + cleared. */ + __OM uint32_t PWM_TIME_PRD_MATCH_INTR_CH2_ACK : 1; /*!< [7..7] pwm time period match + interrupt for 2nd channel will + be cleared. */ + __OM uint32_t RISE_PWM_TIME_PERIOD_MATCH_CH3_ACK : 1; /*!< [8..8] pwm time + period match + interrupt for 3rd + channel will be + cleared. */ + __OM uint32_t PWM_TIME_PRD_MATCH_INTR_CH3_ACK : 1; /*!< [9..9] pwm time period match + interrupt for 3rd channel will + be cleared. */ + __IOM uint32_t RESERVED1 : 22; /*!< [31..10] reserved1 */ + } PWM_INTR_ACK_b; + }; + __IM uint32_t RESERVED[6]; + + union { + __IOM uint32_t PWM_TIME_PRD_WR_REG_CH0; /*!< (@ 0x00000028) Base timer + period register of channel 0 */ + + struct { + __IOM uint32_t PWM_TIME_PRD_REG_WR_VALUE_CH0 : 16; /*!< [15..0] Value to update the + base timer period register of + channel + 0 */ + __IOM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + } PWM_TIME_PRD_WR_REG_CH0_b; + }; + + union { + __IOM uint32_t PWM_TIME_PRD_CNTR_WR_REG_CH0; /*!< (@ 0x0000002C) Base time + counter initial value + register for channel 0 */ + + struct { + __IOM uint32_t PWM_TIME_PRD_CNTR_WR_REG_CH0 : 16; /*!< [15..0] To update the base + time counter initial value for + channel + 0 */ + __IOM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + } PWM_TIME_PRD_CNTR_WR_REG_CH0_b; + }; + + union { + __IOM uint32_t PWM_TIME_PRD_PARAM_REG_CH0; /*!< (@ 0x00000030) Base time period config + parameter's register for channel0 */ + + struct { + __IOM uint32_t TMR_OPEARATING_MODE_CH0 : 3; /*!< [2..0] Base timer operating mode for + channel0 */ + __IOM uint32_t RESERVED1 : 1; /*!< [3..3] reserved1 */ + __IOM uint32_t PWM_TIME_PRD_PRE_SCALAR_VALUE_CH0 : 3; /*!< [6..4] Base timer input + clock pre scale select value + for channel0. */ + __IOM uint32_t RESERVED2 : 1; /*!< [7..7] reserved2 */ + __IOM uint32_t PWM_TIME_PRD_POST_SCALAR_VALUE_CH0 : 4; /*!< [11..8] Time base output + post scale bits for + channel0 */ + __IOM uint32_t RESERVED3 : 20; /*!< [31..12] reserved3 */ + } PWM_TIME_PRD_PARAM_REG_CH0_b; + }; + + union { + __IOM uint32_t PWM_TIME_PRD_CTRL_REG_CH0; /*!< (@ 0x00000034) Base time counter initial + value register for channel 0 */ + + struct { + __IOM uint32_t PWM_TIME_PRD_CNTR_RST_FRM_REG : 1; /*!< [0..0] Time period counter + soft reset */ + __IOM uint32_t PWM_TIME_BASE_EN_FRM_REG_CH0 : 1; /*!< [1..1] Base timer enable for + channnel0 */ + __IOM uint32_t PWM_SFT_RST : 1; /*!< [2..2] MC PWM soft reset */ + __IM uint32_t RESERVED1 : 29; /*!< [31..3] reserved1 */ + } PWM_TIME_PRD_CTRL_REG_CH0_b; + }; + + union { + __IM uint32_t PWM_TIME_PRD_STS_REG_CH0; /*!< (@ 0x00000038) Base time period + status register for channel0 */ + + struct { + __IM uint32_t PWM_TIME_PRD_DIR_STS_CH0 : 1; /*!< [0..0] Time period counter + direction status for channel0 */ + __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + } PWM_TIME_PRD_STS_REG_CH0_b; + }; + + union { + __IM uint32_t PWM_TIME_PRD_CNTR_VALUE_CH0; /*!< (@ 0x0000003C) Base Time + period counter current value + register for channel0 */ + + struct { + __IM uint32_t PWM_TIME_PRD_CNTR_VALUE_CH0 : 16; /*!< [15..0] Time period counter + current value for channel0 */ + __IM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + } PWM_TIME_PRD_CNTR_VALUE_CH0_b; + }; + __IM uint32_t RESERVED1[4]; + + union { + __IOM uint32_t PWM_DUTYCYCLE_CTRL_SET_REG; /*!< (@ 0x00000050) Duty cycle + Control Set Register */ + + struct { + __IOM uint32_t IMDT_DUTYCYCLE_UPDATE_EN : 4; /*!< [3..0] Enable to update the duty + cycle immediately */ + __IOM uint32_t DUTYCYCLE_UPDATE_DISABLE : 4; /*!< [7..4] Duty cycle register updation + disable. There is a separate + bit for each channel */ + __IM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + } PWM_DUTYCYCLE_CTRL_SET_REG_b; + }; + + union { + __IOM uint32_t PWM_DUTYCYCLE_CTRL_RESET_REG; /*!< (@ 0x00000054) Duty cycle + Control Reset Register */ + + struct { + __IOM uint32_t IMDT_DUTYCYCLE_UPDATE_EN : 4; /*!< [3..0] Enable to update the duty + cycle immediately */ + __IOM uint32_t DUTYCYCLE_UPDATE_DISABLE : 4; /*!< [7..4] Duty cycle + register updation disable. + There is a separate bit + for each channel. */ + __IM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + } PWM_DUTYCYCLE_CTRL_RESET_REG_b; + }; + + union { + __IOM uint32_t PWM_DUTYCYCLE_REG_WR_VALUE[4]; /*!< (@ 0x00000058) Duty cycle Value + Register for Channel0 to channel3 */ + + struct { + __IOM uint32_t PWM_DUTYCYCLE_REG_WR_VALUE_CH : 16; /*!< [15..0] Duty cycle value for + channel0 to channel3 */ + __IM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + } PWM_DUTYCYCLE_REG_WR_VALUE_b[4]; + }; + __IM uint32_t RESERVED2[4]; + + union { + __IOM uint32_t PWM_DEADTIME_CTRL_SET_REG; /*!< (@ 0x00000078) Dead time + Control Set Register */ + + struct { + __IOM uint32_t DEADTIME_SELECT_ACTIVE : 4; /*!< [3..0] Dead time select bits for PWM + going active */ + __IOM uint32_t DEADTIME_SELECT_INACTIVE : 4; /*!< [7..4] Dead time select bits for + PWM going inactive */ + __IOM uint32_t DEADTIME_DISABLE_FRM_REG : 4; /*!< [11..8] Dead time counter soft + reset for each channel. */ + __IM uint32_t RESERVED1 : 20; /*!< [31..12] reserved1 */ + } PWM_DEADTIME_CTRL_SET_REG_b; + }; + + union { + __IOM uint32_t PWM_DEADTIME_CTRL_RESET_REG; /*!< (@ 0x0000007C) Dead time + Control Reset Register */ + + struct { + __IOM uint32_t DEADTIME_SELECT_ACTIVE : 4; /*!< [3..0] Dead time select bits for PWM + going active */ + __IOM uint32_t DEADTIME_SELECT_INACTIVE : 4; /*!< [7..4] Dead time select bits for + PWM going inactive */ + __IOM uint32_t DEADTIME_DISABLE_FRM_REG : 4; /*!< [11..8] Dead time counter soft + reset for each channel. */ + __IM uint32_t RESERVED1 : 20; /*!< [31..12] reserved1 */ + } PWM_DEADTIME_CTRL_RESET_REG_b; + }; + + union { + __IOM uint32_t PWM_DEADTIME_PRESCALE_SELECT_A; /*!< (@ 0x00000080) Dead time Prescale + Select Register for A */ + + struct { + __IOM uint32_t DEADTIME_PRESCALE_SELECT_A : 8; /*!< [7..0] Dead time prescale + selection bits for unit A. */ + __IM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + } PWM_DEADTIME_PRESCALE_SELECT_A_b; + }; + + union { + __IOM uint32_t PWM_DEADTIME_PRESCALE_SELECT_B; /*!< (@ 0x00000084) Dead time Prescale + Select Register for B */ + + struct { + __IOM uint32_t DEADTIME_PRESCALE_SELECT_B : 8; /*!< [7..0] Dead time prescale + selection bits for unit B */ + __IM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + } PWM_DEADTIME_PRESCALE_SELECT_B_b; + }; + __IOM MCPWM_PWM_DEADTIME_Type PWM_DEADTIME[4]; /*!< (@ 0x00000088) [0..3] */ + __IM uint32_t RESERVED3[8]; + + union { + __IOM uint32_t PWM_OP_OVERRIDE_CTRL_SET_REG; /*!< (@ 0x000000C8) output override + control set register */ + + struct { + __IOM uint32_t OP_OVERRIDE_SYNC : 1; /*!< [0..0] Output override is synced with pwm + time period depending on operating mode */ + __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + } PWM_OP_OVERRIDE_CTRL_SET_REG_b; + }; + + union { + __IOM uint32_t PWM_OP_OVERRIDE_CTRL_RESET_REG; /*!< (@ 0x000000CC) output override + control reset register */ + + struct { + __IOM uint32_t OP_OVERRIDE_SYNC : 1; /*!< [0..0] Output override is synced with pwm + time period depending on operating mode */ + __IOM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + } PWM_OP_OVERRIDE_CTRL_RESET_REG_b; + }; + + union { + __IOM uint32_t PWM_OP_OVERRIDE_ENABLE_SET_REG; /*!< (@ 0x000000D0) output override + enable set register */ + + struct { + __IOM uint32_t PWM_OP_OVERRIDE_ENABLE_REG : 8; /*!< [7..0] Pwm output over + ride enable */ + __IOM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + } PWM_OP_OVERRIDE_ENABLE_SET_REG_b; + }; + + union { + __IOM uint32_t PWM_OP_OVERRIDE_ENABLE_RESET_REG; /*!< (@ 0x000000D4) output override + enable reset register */ + + struct { + __IOM uint32_t PWM_OP_OVERRIDE_ENABLE_REG : 8; /*!< [7..0] Pwm output over + ride enable */ + __IOM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + } PWM_OP_OVERRIDE_ENABLE_RESET_REG_b; + }; + + union { + __IOM uint32_t PWM_OP_OVERRIDE_VALUE_SET_REG; /*!< (@ 0x000000D8) output override value + set register */ + + struct { + __IOM uint32_t OP_OVERRIDE_VALUE : 8; /*!< [7..0] Pwm output over ride value. */ + __IOM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + } PWM_OP_OVERRIDE_VALUE_SET_REG_b; + }; + + union { + __IOM uint32_t PWM_OP_OVERRIDE_VALUE_RESET_REG; /*!< (@ 0x000000DC) output override + enable reset register */ + + struct { + __IOM uint32_t OP_OVERRIDE_VALUE : 8; /*!< [7..0] Pwm output over ride value. */ + __IOM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + } PWM_OP_OVERRIDE_VALUE_RESET_REG_b; + }; + + union { + __IOM uint32_t PWM_FLT_OVERRIDE_CTRL_SET_REG; /*!< (@ 0x000000E0) fault override + control set register */ + + struct { + __IOM uint32_t FLT_A_MODE : 1; /*!< [0..0] Fault A mode */ + __IOM uint32_t FLT_B_MODE : 1; /*!< [1..1] Fault B mode */ + __IOM uint32_t OP_POLARITY_H : 1; /*!< [2..2] Ouput polarity for high (H3, + H2, H1, H0) side signals */ + __IOM uint32_t OP_POLARITY_L : 1; /*!< [3..3] Ouput polarity for low (L3, + L2, L1, L0) side signals. */ + __IOM uint32_t FLT_A_ENABLE : 4; /*!< [7..4] Fault A enable. Separate + enable bit is present for channel */ + __IOM uint32_t FLT_B_ENABLE : 4; /*!< [11..8] Fault B enable. Separate + enable bit is present for channel */ + __IOM uint32_t COMPLEMENTARY_MODE : 4; /*!< [15..12] PWM I/O pair mode */ + __IOM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + } PWM_FLT_OVERRIDE_CTRL_SET_REG_b; + }; + + union { + __IOM uint32_t PWM_FLT_OVERRIDE_CTRL_RESET_REG; /*!< (@ 0x000000E4) fault override + control reset register */ + + struct { + __IOM uint32_t FLT_A_MODE : 1; /*!< [0..0] Fault B mode */ + __IOM uint32_t FLT_B_MODE : 1; /*!< [1..1] Fault B mode */ + __IOM uint32_t OP_POLARITY_H : 1; /*!< [2..2] Ouput polarity for high (H3, + H2, H1, H0) side signals */ + __IOM uint32_t OP_POLARITY_L : 1; /*!< [3..3] Ouput polarity for low (L3, + L2, L1, L0) side signals. */ + __IOM uint32_t FLT_A_ENABLE : 4; /*!< [7..4] Fault A enable. Separate + enable bit is present for channel */ + __IOM uint32_t FLT_B_ENABLE : 4; /*!< [11..8] Fault B enable. Separate + enable bit is present for channel */ + __IOM uint32_t COMPLEMENTARY_MODE : 4; /*!< [15..12] PWM I/O pair mode */ + __IOM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + } PWM_FLT_OVERRIDE_CTRL_RESET_REG_b; + }; + + union { + __IOM uint32_t PWM_FLT_A_OVERRIDE_VALUE_REG; /*!< (@ 0x000000E8) Fault input + A PWM override value */ + + struct { + __IOM uint32_t PWM_FLT_A_OVERRIDE_VALUE_L0 : 1; /*!< [0..0] 0 bit for L0 */ + __IOM uint32_t PWM_FLT_A_OVERRIDE_VALUE_L1 : 1; /*!< [1..1] 1 bit for L1 */ + __IOM uint32_t PWM_FLT_A_OVERRIDE_VALUE_L2 : 1; /*!< [2..2] 2 bit for L2 */ + __IOM uint32_t PWM_FLT_A_OVERRIDE_VALUE_L3 : 1; /*!< [3..3] 3 bit for L3 */ + __IOM uint32_t PWM_FLT_A_OVERRIDE_VALUE_H0 : 1; /*!< [4..4] 4 bit for H0 */ + __IOM uint32_t PWM_FLT_A_OVERRIDE_VALUE_H1 : 1; /*!< [5..5] 5 bit for H1 */ + __IOM uint32_t PWM_FLT_A_OVERRIDE_VALUE_H2 : 1; /*!< [6..6] 6 bit for H2 */ + __IOM uint32_t PWM_FLT_A_OVERRIDE_VALUE_H3 : 1; /*!< [7..7] 7 bit for H3 */ + __IOM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + } PWM_FLT_A_OVERRIDE_VALUE_REG_b; + }; + + union { + __IOM uint32_t PWM_FLT_B_OVERRIDE_VALUE_REG; /*!< (@ 0x000000EC) Fault input + B PWM override value */ + + struct { + __IOM uint32_t PWM_FLT_B_OVERRIDE_VALUE_L0 : 1; /*!< [0..0] 0 bit for L0 */ + __IOM uint32_t PWM_FLT_B_OVERRIDE_VALUE_L1 : 1; /*!< [1..1] 1 bit for L1 */ + __IOM uint32_t PWM_FLT_B_OVERRIDE_VALUE_L2 : 1; /*!< [2..2] 2 bit for L2 */ + __IOM uint32_t PWM_FLT_B_OVERRIDE_VALUE_L3 : 1; /*!< [3..3] 3 bit for L3 */ + __IOM uint32_t PWM_FLT_B_OVERRIDE_VALUE_H0 : 1; /*!< [4..4] 4 bit for H0 */ + __IOM uint32_t PWM_FLT_B_OVERRIDE_VALUE_H1 : 1; /*!< [5..5] 5 bit for H1 */ + __IOM uint32_t PWM_FLT_B_OVERRIDE_VALUE_H2 : 1; /*!< [6..6] 6 bit for H2 */ + __IOM uint32_t PWM_FLT_B_OVERRIDE_VALUE_H3 : 1; /*!< [7..7] 7 bit for H3 */ + __IOM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + } PWM_FLT_B_OVERRIDE_VALUE_REG_b; + }; + + union { + __IOM uint32_t PWM_SVT_CTRL_SET_REG; /*!< (@ 0x000000F0) NONE */ + + struct { + __IOM uint32_t SVT_ENABLE_FRM : 1; /*!< [0..0] Special event trigger enable. This is + used to enable + generation special event trigger */ + __IOM uint32_t SVT_DIRECTION_FRM : 1; /*!< [1..1] Special event trigger + for time base direction */ + __IOM uint32_t RESERVED1 : 30; /*!< [31..2] reserved1 */ + } PWM_SVT_CTRL_SET_REG_b; + }; + + union { + __IOM uint32_t PWM_SVT_CTRL_RESET_REG; /*!< (@ 0x000000F4) Special event + control reset register */ + + struct { + __IOM uint32_t SVT_ENABLE_FRM : 1; /*!< [0..0] Special event trigger enable. This is + used to enable + generation special event trigger */ + __IOM uint32_t SVT_DIRECTION_FRM : 1; /*!< [1..1] Special event trigger + for time base direction */ + __IOM uint32_t RESERVED1 : 30; /*!< [31..2] reserved1 */ + } PWM_SVT_CTRL_RESET_REG_b; + }; + + union { + __IOM uint32_t PWM_SVT_PARAM_REG; /*!< (@ 0x000000F8) Special event + parameter register */ + + struct { + __IOM uint32_t SVT_POSTSCALER_SELECT : 4; /*!< [3..0] PWM special event trigger + output postscale select bits */ + __IOM uint32_t RESERVED1 : 28; /*!< [31..4] reserved1 */ + } PWM_SVT_PARAM_REG_b; + }; + + union { + __IOM uint32_t PWM_SVT_COMPARE_VALUE_REG; /*!< (@ 0x000000FC) Special event + compare value register */ + + struct { + __IOM uint32_t PWM_SVT_COMPARE_VALUE : 16; /*!< [15..0] Special event compare value. + This is used to compare with pwm time + period counter to generate special + event trigger */ + __IOM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + } PWM_SVT_COMPARE_VALUE_REG_b; + }; + + union { + __IOM uint32_t PWM_TIME_PRD_WR_REG_CH1; /*!< (@ 0x00000100) Base timer + period register of channel1 */ + + struct { + __IOM uint32_t PWM_TIME_PRD_REG_WR_VALUE_CH1 : 16; /*!< [15..0] Value to update the + base timer period register of + channel + 1 */ + __IOM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + } PWM_TIME_PRD_WR_REG_CH1_b; + }; + + union { + __IOM uint32_t PWM_TIME_PRD_CNTR_WR_REG_CH1; /*!< (@ 0x00000104) Base time + counter initial value + register for channel1 */ + + struct { + __IOM uint32_t PWM_TIME_PRD_CNTR_WR_REG_CH1 : 16; /*!< [15..0] To update the base + time counter initial value for + channel + 1 */ + __IOM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + } PWM_TIME_PRD_CNTR_WR_REG_CH1_b; + }; + + union { + __IOM uint32_t PWM_TIME_PRD_PARAM_REG_CH1; /*!< (@ 0x00000108) NONE */ + + struct { + __IOM uint32_t TMR_OPEARATING_MODE_CH1 : 3; /*!< [2..0] Base timer operating mode for + channel1 */ + __IOM uint32_t RESERVED1 : 1; /*!< [3..3] reserved1 */ + __IOM uint32_t PWM_TIME_PRD_PRE_SCALAR_VALUE_CH1 : 3; /*!< [6..4] Base timer input + clock prescale select value + for channel1. */ + __IOM uint32_t RESERVED2 : 1; /*!< [7..7] reserved2 */ + __IOM uint32_t PWM_TIME_PRD_POST_SCALAR_VALUE_CH1 : 4; /*!< [11..8] Time base output + post scale bits for + channel1 */ + __IOM uint32_t RESERVED3 : 20; /*!< [31..12] reserved3 */ + } PWM_TIME_PRD_PARAM_REG_CH1_b; + }; + + union { + __IOM uint32_t PWM_TIME_PRD_CTRL_REG_CH1; /*!< (@ 0x0000010C) Base time period control + register for channel1 */ + + struct { + __IOM uint32_t PWM_TIME_PRD_CNTR_RST_FRM_REG : 1; /*!< [0..0] Time period counter + soft reset */ + __IOM uint32_t PWM_TIME_BASE_EN_FRM_REG_CH1 : 1; /*!< [1..1] Base timer enable for + channnel1 */ + __IOM uint32_t PWM_SFT_RST : 1; /*!< [2..2] MC PWM soft reset */ + __IOM uint32_t RESERVED1 : 29; /*!< [31..3] reserved1 */ + } PWM_TIME_PRD_CTRL_REG_CH1_b; + }; + + union { + __IM uint32_t PWM_TIME_PRD_STS_REG_CH1; /*!< (@ 0x00000110) Base time period + status register for channel1 */ + + struct { + __IM uint32_t PWM_TIME_PRD_DIR_STS_CH1 : 1; /*!< [0..0] Time period counter + direction status for channel1. */ + __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + } PWM_TIME_PRD_STS_REG_CH1_b; + }; + + union { + __IOM uint32_t PWM_TIME_PRD_CNTR_VALUE_CH1; /*!< (@ 0x00000114) Time period counter + current value for channel1 */ + + struct { + __IOM uint32_t PWM_TIME_PRD_CNTR_VALUE_CH1 : 1; /*!< [0..0] Time period counter + current value for channel1 */ + __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + } PWM_TIME_PRD_CNTR_VALUE_CH1_b; + }; + + union { + __IOM uint32_t PWM_TIME_PRD_WR_REG_CH2; /*!< (@ 0x00000118) Base timer + period register of channel2 */ + + struct { + __IOM uint32_t PWM_TIME_PRD_REG_WR_VALUE_CH2 : 16; /*!< [15..0] Value to update the + base timer period register of + channel + 2 */ + __IOM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + } PWM_TIME_PRD_WR_REG_CH2_b; + }; + + union { + __IOM uint32_t PWM_TIME_PRD_CNTR_WR_REG_CH2; /*!< (@ 0x0000011C) Base time + counter initial value + register for channel2 */ + + struct { + __IOM uint32_t PWM_TIME_PRD_CNTR_WR_REG_CH2 : 16; /*!< [15..0] To update the base + time counter initial value for + channel + 2 */ + __IOM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + } PWM_TIME_PRD_CNTR_WR_REG_CH2_b; + }; + + union { + __IOM uint32_t PWM_TIME_PRD_PARAM_REG_CH2; /*!< (@ 0x00000120) Base time period config + parameter's register for channel2 */ + + struct { + __IOM uint32_t TMR_OPEARATING_MODE_CH2 : 3; /*!< [2..0] Base timer operating mode for + channel2 */ + __IOM uint32_t RESERVED1 : 1; /*!< [3..3] reserved1 */ + __IOM uint32_t PWM_TIME_PRD_PRE_SCALAR_VALUE_CH2 : 3; /*!< [6..4] Base timer input + clock pre scale select value + for channel2. */ + __IOM uint32_t RESERVED2 : 1; /*!< [7..7] reserved2 */ + __IOM uint32_t PWM_TIME_PRD_POST_SCALAR_VALUE_CH2 : 4; /*!< [11..8] Time base output + post scale bits for + channel2 */ + __IOM uint32_t RESERVED3 : 20; /*!< [31..12] reserved3 */ + } PWM_TIME_PRD_PARAM_REG_CH2_b; + }; + + union { + __IOM uint32_t PWM_TIME_PRD_CTRL_REG_CH2; /*!< (@ 0x00000124) Base time period control + register for channel2 */ + + struct { + __IOM uint32_t PWM_TIME_PRD_CNTR_RST_FRM_REG : 1; /*!< [0..0] Time period counter + soft reset */ + __IOM uint32_t PWM_TIME_BASE_EN_FRM_REG_CH2 : 1; /*!< [1..1] Base timer enable for + channnel2 */ + __IOM uint32_t PWM_SFT_RST : 1; /*!< [2..2] MC PWM soft reset */ + __IOM uint32_t RESERVED1 : 29; /*!< [31..3] reserved1 */ + } PWM_TIME_PRD_CTRL_REG_CH2_b; + }; + + union { + __IM uint32_t PWM_TIME_PRD_STS_REG_CH2; /*!< (@ 0x00000128) Base time period + status register for channel2 */ + + struct { + __IM uint32_t PWM_TIME_PRD_DIR_STS_CH2 : 1; /*!< [0..0] Time period counter + direction status for channel2. */ + __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + } PWM_TIME_PRD_STS_REG_CH2_b; + }; + + union { + __IM uint32_t PWM_TIME_PRD_CNTR_VALUE_CH2; /*!< (@ 0x0000012C) Time period counter + current value register for channel2 */ + + struct { + __IM uint32_t PWM_TIME_PRD_CNTR_VALUE_CH2 : 1; /*!< [0..0] Time period counter + current value for channel2 */ + __IM uint32_t RESERVED1 : 11; /*!< [11..1] reserved1 */ + __IM uint32_t RESERVED2 : 20; /*!< [31..12] reserved2 */ + } PWM_TIME_PRD_CNTR_VALUE_CH2_b; + }; + + union { + __IOM uint32_t PWM_TIME_PRD_WR_REG_CH3; /*!< (@ 0x00000130) Base timer + period register of channel3 */ + + struct { + __IOM uint32_t PWM_TIME_PRD_REG_WR_VALUE_CH3 : 16; /*!< [15..0] To update the base + time counter initial value for + channel + 3 */ + __IOM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + } PWM_TIME_PRD_WR_REG_CH3_b; + }; + + union { + __IOM uint32_t PWM_TIME_PRD_CNTR_WR_REG_CH3; /*!< (@ 0x00000134) Base time + counter initial value + register for channel3 */ + + struct { + __IOM uint32_t PWM_TIME_PRD_CNTR_WR_REG_CH3 : 16; /*!< [15..0] Value to update the + base timer period register of + channel + 3 */ + __IOM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + } PWM_TIME_PRD_CNTR_WR_REG_CH3_b; + }; + + union { + __IOM uint32_t PWM_TIME_PRD_PARAM_REG_CH3; /*!< (@ 0x00000138) Base time period config + parameter's register for channel3 */ + + struct { + __IOM uint32_t TMR_OPEARATING_MODE_CH3 : 3; /*!< [2..0] Base timer operating mode for + channel3 */ + __IOM uint32_t RESERVED1 : 1; /*!< [3..3] reserved1 */ + __IOM uint32_t PWM_TIME_PRD_PRE_SCALAR_VALUE_CH3 : 3; /*!< [6..4] Base timer input + clock pre scale select value + for channel2. */ + __IOM uint32_t RESERVED2 : 1; /*!< [7..7] reserved2 */ + __IOM uint32_t PWM_TIME_PRD_POST_SCALAR_VALUE_CH3 : 4; /*!< [11..8] Time base output + post scale bits for + channel3 */ + __IOM uint32_t RESERVED3 : 20; /*!< [31..12] reserved3 */ + } PWM_TIME_PRD_PARAM_REG_CH3_b; + }; + + union { + __IOM uint32_t PWM_TIME_PRD_CTRL_REG_CH3; /*!< (@ 0x0000013C) Base time period control + register for channel3 */ + + struct { + __IOM uint32_t PWM_TIME_PRD_CNTR_RST_FRM_REG : 1; /*!< [0..0] Time period counter + soft reset */ + __IOM uint32_t PWM_TIME_BASE_EN_FRM_REG_CH3 : 1; /*!< [1..1] Base timer enable for + channnel3 */ + __IOM uint32_t PWM_SFT_RST : 1; /*!< [2..2] MC PWM soft reset */ + __IOM uint32_t RESERVED1 : 29; /*!< [31..3] reserved1 */ + } PWM_TIME_PRD_CTRL_REG_CH3_b; + }; + + union { + __IM uint32_t PWM_TIME_PRD_STS_REG_CH3; /*!< (@ 0x00000140) Base time period + status register for channel3 */ + + struct { + __IM uint32_t PWM_TIME_PRD_DIR_STS_CH3 : 1; /*!< [0..0] Time period counter + direction status for channel3. */ + __IM uint32_t RESERVED1 : 15; /*!< [15..1] reserved1 */ + __IM uint32_t RESERVED2 : 16; /*!< [31..16] reserved2 */ + } PWM_TIME_PRD_STS_REG_CH3_b; + }; + + union { + __IM uint32_t PWM_TIME_PRD_CNTR_VALUE_CH3; /*!< (@ 0x00000144) Time period counter + current value register for channel3 */ + + struct { + __IM uint32_t PWM_TIME_PRD_CNTR_VALUE_CH3 : 16; /*!< [15..0] Time period counter + current value for channe3 */ + __IM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + } PWM_TIME_PRD_CNTR_VALUE_CH3_b; + }; + + union { + __IOM uint32_t PWM_TIME_PRD_COMMON_REG; /*!< (@ 0x00000148) Time period + common register */ + + struct { + __IOM uint32_t PWM_TIME_PRD_USE_0TH_TIMER_ONLY : 1; /*!< [0..0] Instead of use four + base timers for four channels, + use only one base timer for + all channels. */ + __IOM uint32_t PWM_TIME_PRD_COMMON_TIMER_VALUE : 2; /*!< [2..1] Base timers select to + generate special event trigger + */ + __IOM uint32_t USE_EXT_TIMER_TRIG_FRM_REG : 1; /*!< [3..3] Enable to use external + trigger for base time counter + increment or decrement. */ + __IOM uint32_t RESERVED1 : 28; /*!< [31..4] reserved1 */ + } PWM_TIME_PRD_COMMON_REG_b; + }; +} MCPWM_Type; /*!< Size = 332 (0x14c) */ + +/* =========================================================================================================================== + */ +/* ================ UDMA0 + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief DMA Performs data transfers along with Addresses and control + * information (UDMA0) + */ + +typedef struct { /*!< (@ 0x44030000) UDMA0 Structure */ + + union { + __IM uint32_t DMA_STATUS; /*!< (@ 0x00000000) UDMA Status Register */ + + struct { + __IM uint32_t MASTER_ENABLE : 1; /*!< [0..0] Enable status of controller */ + __IM uint32_t RESERVED1 : 3; /*!< [3..1] Reserved1 */ + __IM uint32_t STATE : 4; /*!< [7..4] Current state of the control state machine */ + __IM uint32_t RESERVED2 : 8; /*!< [15..8] Reserved2 */ + __IM uint32_t CHNLS_MINUS1 : 5; /*!< [20..16] Number of available DMA + channels minus one */ + __IM uint32_t RESERVED3 : 7; /*!< [27..21] Reserved3 */ + __IM uint32_t TEST_STATUS : 4; /*!< [31..28] To reduce the gate count you + can configure the controller */ + } DMA_STATUS_b; + }; + + union { + __OM uint32_t DMA_CFG; /*!< (@ 0x00000004) DMA Configuration */ + + struct { + __OM uint32_t MASTER_ENABLE : 1; /*!< [0..0] Enable for the controller */ + __OM uint32_t RESERVED1 : 4; /*!< [4..1] Reserved1 */ + __OM uint32_t CHNL_PROT_CTRL : 3; /*!< [7..5] Sets the AHB-Lite protection by + controlling the HPROT[3:1]] signal levels as + follows Bit[7]-Controls HPROT[3] to indicate if + cacheable access is occurring Bit[6]-Controls + HPROT[2] to indicate if cacheable access is + occurring Bit[5]-Controls + HPROT[1] to indicate if cacheable + access is occurring */ + __OM uint32_t RESERVED2 : 24; /*!< [31..8] Reserved2 */ + } DMA_CFG_b; + }; + + union { + __IOM uint32_t CTRL_BASE_PTR; /*!< (@ 0x00000008) Channel Control Data Base + Pointer */ + + struct { + __OM uint32_t RESERVED1 : 10; /*!< [9..0] Reserved1 */ + __IOM uint32_t CTRL_BASE_PTR : 22; /*!< [31..10] Pointer to the base address of the + primary data structure */ + } CTRL_BASE_PTR_b; + }; + + union { + __IM uint32_t ALT_CTRL_BASE_PTR; /*!< (@ 0x0000000C) Channel Alternate + Control Data Base Pointer */ + + struct { + __IM uint32_t ALT_CTRL_BASE_PTR : 32; /*!< [31..0] Base address of the + alternative data structure */ + } ALT_CTRL_BASE_PTR_b; + }; + + union { + __IM uint32_t DMA_WAITONREQUEST_STATUS; /*!< (@ 0x00000010) Channel Wait on + request status register */ + + struct { + __IM uint32_t DMA_WAITONREQ_STATUS : 32; /*!< [31..0] Per Channel wait on + request status */ + } DMA_WAITONREQUEST_STATUS_b; + }; + + union { + __OM uint32_t CHNL_SW_REQUEST; /*!< (@ 0x00000014) Channel Software Request */ + + struct { + __OM uint32_t CHNL_SW_REQUEST : 32; /*!< [31..0] Set the appropriate bit to generate + a software DMA request on the corresponding + DMA channel */ + } CHNL_SW_REQUEST_b; + }; + + union { + __IOM uint32_t CHNL_USEBURST_SET; /*!< (@ 0x00000018) UDMA Channel use burst set */ + + struct { + __IOM uint32_t CHNL_USEBURST_SET : 32; /*!< [31..0] The use burst status, + or disables dma_sreq[C] from + generating DMA requests. */ + } CHNL_USEBURST_SET_b; + }; + + union { + __OM uint32_t CHNL_USEBURST_CLR; /*!< (@ 0x0000001C) UDMA Channel use burst clear */ + + struct { + __OM uint32_t CHNL_USEBURST_CLR : 32; /*!< [31..0] Set the appropriate bit to enable + dma_sreq[] to generate requests */ + } CHNL_USEBURST_CLR_b; + }; + + union { + __IOM uint32_t CHNL_REQ_MASK_SET; /*!< (@ 0x00000020) UDMA Channel request + mask set Register */ + + struct { + __IOM uint32_t CHNL_REQ_MASK_SET : 32; /*!< [31..0] Returns the request mask status + of dma_req[] and dma_sreq[], or disables + the corresponding channel from generating + DMA requests */ + } CHNL_REQ_MASK_SET_b; + }; + + union { + __OM uint32_t CHNL_REQ_MASK_CLR; /*!< (@ 0x00000024) UDMA Channel request + mask clear */ + + struct { + __OM uint32_t CHNL_REQ_MASK_CLR : 32; /*!< [31..0] Set the appropriate bit + to enable DMA requests for the + channel corresponding to + dma_req[] and dma_sreq[] */ + } CHNL_REQ_MASK_CLR_b; + }; + + union { + __IOM uint32_t CHNL_ENABLE_SET; /*!< (@ 0x00000028) UDMA Channel enable register */ + + struct { + __IOM uint32_t CHNL_ENABLE_SET : 32; /*!< [31..0] This Bits are Used to Load the + 16bits of Source address */ + } CHNL_ENABLE_SET_b; + }; + + union { + __OM uint32_t CHNL_ENABLE_CLR; /*!< (@ 0x0000002C) UDMA Channel enable clear + register */ + + struct { + __OM uint32_t CHNL_ENABLE_CLR : 32; /*!< [31..0] Set the appropriate bit to disable + the corresponding DMA channel */ + } CHNL_ENABLE_CLR_b; + }; + + union { + __IOM uint32_t CHNL_PRI_ALT_SET; /*!< (@ 0x00000030) UDMA Channel primary or + alternate set */ + + struct { + __IOM uint32_t CHNL_PRI_ALT_SET : 32; /*!< [31..0] Returns the channel control data + structure status or selects the alternate + data structure for the corresponding DMA + channel */ + } CHNL_PRI_ALT_SET_b; + }; + + union { + __OM uint32_t CHNL_PRI_ALT_CLR; /*!< (@ 0x00000034) UDMA Channel primary + alternate clear */ + + struct { + __OM uint32_t CHNL_PRI_ALT_CLR : 32; /*!< [31..0] Set the appropriate bit to select + the primary data structure for the + corresponding DMA channel */ + } CHNL_PRI_ALT_CLR_b; + }; + + union { + __IOM uint32_t CHNL_PRIORITY_SET; /*!< (@ 0x00000038) UDMA Channel Priority Set */ + + struct { + __IOM uint32_t CHNL_PRIORITY_SET : 32; /*!< [31..0] Set the appropriate bit to select + the primary data structure for the + corresponding DMA channel */ + } CHNL_PRIORITY_SET_b; + }; + + union { + __OM uint32_t CHNL_PRIORITY_CLR; /*!< (@ 0x0000003C) UDMA Channel Priority Clear */ + + struct { + __OM uint32_t CHNL_PRIORITY_CLR : 32; /*!< [31..0] Set the appropriate bit to select + the default priority level for the + specified DMA channel */ + } CHNL_PRIORITY_CLR_b; + }; + __IM uint32_t RESERVED[3]; + + union { + __IOM uint32_t ERR_CLR; /*!< (@ 0x0000004C) UDMA Bus Error Clear Register */ + + struct { + __IOM uint32_t ERR_CLR : 1; /*!< [0..0] Returns the status of dma_err */ + __IOM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved1 */ + } ERR_CLR_b; + }; + + union { + __IOM uint32_t UDMA_SKIP_DESC_FETCH_REG; /*!< (@ 0x00000050) UDMA skip + descriptor fetch Register */ + + struct { + __IOM uint32_t SKIP_DESC_FETCH : 32; /*!< [31..0] improving the + performance of transfer and saves + bus cycles. This features has to + be enabled always. */ + } UDMA_SKIP_DESC_FETCH_REG_b; + }; + __IM uint32_t RESERVED1[491]; + + union { + __IOM uint32_t UDMA_DONE_STATUS_REG; /*!< (@ 0x00000800) UDMA Done status Register */ + + struct { + __IOM uint32_t DONE_STATUS_CHANNEL_0 : 1; /*!< [0..0] UDMA done Status of + the channel 0 */ + __IOM uint32_t DONE_STATUS_CHANNEL_1 : 1; /*!< [1..1] UDMA done Status of + the channel 1 */ + __IOM uint32_t DONE_STATUS_CHANNEL_2 : 1; /*!< [2..2] UDMA done Status of + the channel 2 */ + __IOM uint32_t DONE_STATUS_CHANNEL_3 : 1; /*!< [3..3] UDMA done Status of + the channel 3 */ + __IOM uint32_t DONE_STATUS_CHANNEL_4 : 1; /*!< [4..4] UDMA done Status of + the channel 4 */ + __IOM uint32_t DONE_STATUS_CHANNEL_5 : 1; /*!< [5..5] UDMA done Status of + the channel 5 */ + __IOM uint32_t DONE_STATUS_CHANNEL_6 : 1; /*!< [6..6] UDMA done Status of + the channel 6 */ + __IOM uint32_t DONE_STATUS_CHANNEL_7 : 1; /*!< [7..7] UDMA done Status of + the channel 7 */ + __IOM uint32_t DONE_STATUS_CHANNEL_8 : 1; /*!< [8..8] UDMA done Status of + the channel 8 */ + __IOM uint32_t DONE_STATUS_CHANNEL_9 : 1; /*!< [9..9] UDMA done Status of + the channel 9 */ + __IOM uint32_t DONE_STATUS_CHANNEL_10 : 1; /*!< [10..10] UDMA done Status + of the channel 10 */ + __IOM uint32_t DONE_STATUS_CHANNEL_11 : 1; /*!< [11..11] UDMA done Status + of the channel 3 */ + __IOM uint32_t DONE_STATUS_CHANNEL_12 : 1; /*!< [12..12] UDMA done Status + of the channel 12 */ + __IOM uint32_t DONE_STATUS_CHANNEL_13 : 1; /*!< [13..13] UDMA done Status + of the channel 13 */ + __IOM uint32_t DONE_STATUS_CHANNEL_14 : 1; /*!< [14..14] UDMA done Status + of the channel 14 */ + __IOM uint32_t DONE_STATUS_CHANNEL_15 : 1; /*!< [15..15] UDMA done Status + of the channel 15 */ + __IOM uint32_t DONE_STATUS_CHANNEL_16 : 1; /*!< [16..16] UDMA done Status + of the channel 16 */ + __IOM uint32_t DONE_STATUS_CHANNEL_17 : 1; /*!< [17..17] UDMA done Status + of the channel 17 */ + __IOM uint32_t DONE_STATUS_CHANNEL_18 : 1; /*!< [18..18] UDMA done Status + of the channel 18 */ + __IOM uint32_t DONE_STATUS_CHANNEL_19 : 1; /*!< [19..19] UDMA done Status + of the channel 19 */ + __IOM uint32_t DONE_STATUS_CHANNEL_20 : 1; /*!< [20..20] UDMA done Status + of the channel 3 */ + __IOM uint32_t DONE_STATUS_CHANNEL_21 : 1; /*!< [21..21] UDMA done Status + of the channel 21 */ + __IOM uint32_t DONE_STATUS_CHANNEL_22 : 1; /*!< [22..22] UDMA done Status + of the channel 22 */ + __IOM uint32_t DONE_STATUS_CHANNEL_23 : 1; /*!< [23..23] UDMA done Status + of the channel 23 */ + __IOM uint32_t DONE_STATUS_CHANNEL_24 : 1; /*!< [24..24] UDMA done Status + of the channel 24 */ + __IOM uint32_t DONE_STATUS_CHANNEL_25 : 1; /*!< [25..25] UDMA done Status + of the channel 25 */ + __IOM uint32_t DONE_STATUS_CHANNEL_26 : 1; /*!< [26..26] UDMA done Status + of the channel 26 */ + __IOM uint32_t DONE_STATUS_CHANNEL_27 : 1; /*!< [27..27] UDMA done Status + of the channel 27 */ + __IOM uint32_t DONE_STATUS_CHANNEL_28 : 1; /*!< [28..28] UDMA done Status + of the channel 28 */ + __IOM uint32_t DONE_STATUS_CHANNEL_29 : 1; /*!< [29..29] UDMA done Status + of the channel 29 */ + __IOM uint32_t DONE_STATUS_CHANNEL_30 : 1; /*!< [30..30] UDMA done Status + of the channel 30 */ + __IOM uint32_t DONE_STATUS_CHANNEL_31 : 1; /*!< [31..31] UDMA done Status + of the channel 31 */ + } UDMA_DONE_STATUS_REG_b; + }; + + union { + __IM uint32_t CHANNEL_STATUS_REG; /*!< (@ 0x00000804) Channel status Register */ + + struct { + __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_0 : 1; /*!< [0..0] Reading 1 indicates + that the channel 0 is busy */ + __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_1 : 1; /*!< [1..1] Reading 1 indicates + that the channel 1 is busy */ + __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_2 : 1; /*!< [2..2] Reading 1 indicates + that the channel 2 is busy */ + __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_3 : 1; /*!< [3..3] Reading 1 indicates + that the channel 3 is busy */ + __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_4 : 1; /*!< [4..4] Reading 1 indicates + that the channel 4 is busy */ + __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_5 : 1; /*!< [5..5] Reading 1 indicates + that the channel 5 is busy */ + __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_6 : 1; /*!< [6..6] Reading 1 indicates + that the channel 6 is busy */ + __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_7 : 1; /*!< [7..7] Reading 1 indicates + that the channel 7 is busy */ + __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_8 : 1; /*!< [8..8] Reading 1 indicates + that the channel 8 is busy */ + __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_9 : 1; /*!< [9..9] Reading 1 indicates + that the channel 9 is busy */ + __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_10 : 1; /*!< [10..10] Reading 1 + indicates that the + channel 10 is busy + */ + __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_11 : 1; /*!< [11..11] Reading 1 + indicates that the + channel 11 is busy + */ + __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_12 : 1; /*!< [12..12] Reading 1 + indicates that the + channel 12 is busy + */ + __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_13 : 1; /*!< [13..13] Reading 1 + indicates that the + channel 13 is busy + */ + __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_14 : 1; /*!< [14..14] Reading 1 + indicates that the + channel 14 is busy + */ + __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_15 : 1; /*!< [15..15] Reading 1 + indicates that the + channel 15 is busy + */ + __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_16 : 1; /*!< [16..16] Reading 1 + indicates that the + channel 16 is busy + */ + __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_17 : 1; /*!< [17..17] Reading 1 + indicates that the + channel 17 is busy + */ + __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_18 : 1; /*!< [18..18] Reading 1 + indicates that the + channel 18 is busy + */ + __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_19 : 1; /*!< [19..19] Reading 1 + indicates that the + channel 19 is busy + */ + __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_20 : 1; /*!< [20..20] Reading 1 + indicates that the + channel 20 is busy + */ + __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_21 : 1; /*!< [21..21] Reading 1 + indicates that the + channel 21 is busy + */ + __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_22 : 1; /*!< [22..22] Reading 1 + indicates that the + channel 22 is busy + */ + __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_23 : 1; /*!< [23..23] Reading 1 + indicates that the + channel 23 is busy + */ + __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_24 : 1; /*!< [24..24] Reading 1 + indicates that the + channel 24 is busy + */ + __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_25 : 1; /*!< [25..25] Reading 1 + indicates that the + channel 25 is busy + */ + __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_26 : 1; /*!< [26..26] Reading 1 + indicates that the + channel 26 is busy + */ + __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_27 : 1; /*!< [27..27] Reading 1 + indicates that the + channel 27 is busy + */ + __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_28 : 1; /*!< [28..28] Reading 1 + indicates that the + channel 28 is busy + */ + __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_29 : 1; /*!< [29..29] Reading 1 + indicates that the + channel 29 is busy + */ + __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_30 : 1; /*!< [30..30] Reading 1 + indicates that the + channel 30 is busy + */ + __IM uint32_t BUSY_OR_IDEAL_STATUS_CHANNEL_31 : 1; /*!< [31..31] Reading 1 + indicates that the + channel 31 is busy + */ + } CHANNEL_STATUS_REG_b; + }; + __IM uint32_t RESERVED2[8]; + + union { + __IOM uint32_t UDMA_CONFIG_CTRL_REG; /*!< (@ 0x00000828) DMA Controller + Transfer Length Register */ + + struct { + __IOM uint32_t SINGLE_REQUEST_ENABLE : 1; /*!< [0..0] Enabled signal for + single request */ + __IOM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved for future use. */ + } UDMA_CONFIG_CTRL_REG_b; + }; + + union { + __IOM uint32_t UDMA_INTR_MASK_REG; /*!< (@ 0x0000082C) Mask the uDMA + interrupt register */ + + struct { + __IOM uint32_t UDMA_INTR_MASK : 12; /*!< [11..0] Mask the uDMA interrupt + register */ + __IM uint32_t RESERVED1 : 20; /*!< [31..12] RESERVED1 */ + } UDMA_INTR_MASK_REG_b; + }; +} UDMA0_Type; /*!< Size = 2096 (0x830) */ + +/* =========================================================================================================================== + */ +/* ================ GPDMA_G + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief GPDMA is an AMBA complaint peripheral unit supports 8-channels + * (GPDMA_G) + */ + +typedef struct { /*!< (@ 0x21080000) GPDMA_G Structure */ + __IM uint32_t RESERVED[1057]; + __IOM GPDMA_G_GLOBAL_Type GLOBAL; /*!< (@ 0x00001084) GLOBAL */ +} GPDMA_G_Type; /*!< Size = 4252 (0x109c) */ + +/* =========================================================================================================================== + */ +/* ================ GPDMA_C + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief GPDMAC (dma controller) is an AMBA complaint peripheral unit supports + * 8-channels (GPDMA_C) + */ + +typedef struct { /*!< (@ 0x21081004) GPDMA_C Structure */ + __IOM GPDMA_C_CHANNEL_CONFIG_Type CHANNEL_CONFIG[8]; /*!< (@ 0x00000000) [0..7] */ +} GPDMA_C_Type; /*!< Size = 2048 (0x800) */ + +/* =========================================================================================================================== + */ +/* ================ HWRNG + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief Random numbers generated are 16-bit random numbers and are generated + using either the True random number generator or the Pseudo random number + generator. (HWRNG) + */ + +typedef struct { /*!< (@ 0x45090000) HWRNG Structure */ + + union { + __IOM uint32_t HWRNG_CTRL_REG; /*!< (@ 0x00000000) Random Number Generator + Control Register */ + + struct { + __IOM uint32_t HWRNG_RNG_ST : 1; /*!< [0..0] This bit is used to start the + true number generation. */ + __IOM uint32_t HWRNG_PRBS_ST : 1; /*!< [1..1] This bit is used to start the pseudo + random number generation */ + __IOM uint32_t SOFT_RESET : 1; /*!< [2..2] This bit is used to start the + pseudo random number generation */ + __IM uint32_t RESERVED1 : 29; /*!< [31..3] RESERVED1 */ + } HWRNG_CTRL_REG_b; + }; + + union { + __IM uint32_t HWRNG_RAND_NUM_REG; /*!< (@ 0x00000004) Hardware Random Number + Register */ + + struct { + __IM uint32_t HWRNG_RAND_NUM : 32; /*!< [31..0] Generated random number + can be read from this register. */ + } HWRNG_RAND_NUM_REG_b; + }; +} HWRNG_Type; /*!< Size = 8 (0x8) */ + +/* =========================================================================================================================== + */ +/* ================ TIMERS + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief TIMER can be used to generate various timing events for the software + * (TIMERS) + */ + +typedef struct { /*!< (@ 0x24042000) TIMERS Structure */ + __IOM TIMERS_MATCH_CTRL_Type MATCH_CTRL[4]; /*!< (@ 0x00000000) [0..3] */ + __IM uint32_t RESERVED[24]; + + union { + __IOM uint32_t MCUULP_TMR_INTR_STAT; /*!< (@ 0x00000080) Timer Status Register */ + + struct { + __IOM uint32_t TMR0_INTR_STATUS : 1; /*!< [0..0] This bit indicates status of the + interrupt generated by timer 0 */ + __IOM uint32_t TMR1_INTR_STATUS : 1; /*!< [1..1] This bit indicates status of the + interrupt generated by timer 1 */ + __IOM uint32_t TMR2_INTR_STATUS : 1; /*!< [2..2] This bit indicates status of the + interrupt generated by timer 2 */ + __IOM uint32_t TMR3_INTR_STATUS : 1; /*!< [3..3] This bit indicates status of the + interrupt generated by timer 3 */ + __IM uint32_t RESERVED1 : 28; /*!< [31..4] reserved1 */ + } MCUULP_TMR_INTR_STAT_b; + }; + + union { + __IOM uint32_t MCUULP_TMR_US_PERIOD_INT; /*!< (@ 0x00000084) Timer micro second period + Integral Part Register */ + + struct { + __IOM uint32_t TMR_US_PERIOD_INT : 16; /*!< [15..0] This bits are used to program the + integer part of number + of clock cycles per microseconds of + the system clock used */ + __IM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + } MCUULP_TMR_US_PERIOD_INT_b; + }; + + union { + __IOM uint32_t MCUULP_TMR_US_PERIOD_FRAC; /*!< (@ 0x00000088) Timer microsecond period + Fractional Part Register */ + + struct { + __IOM uint32_t TMR_US_PERIOD_FRAC : 8; /*!< [7..0] This bits are used to program the + fractional part of number of clock cycles + per microseconds of the system clock used + */ + __IM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + } MCUULP_TMR_US_PERIOD_FRAC_b; + }; + + union { + __IOM uint32_t MCUULP_TMR_MS_PERIOD_INT; /*!< (@ 0x0000008C) Timer 256 microsecond + period Integral Part Register */ + + struct { + __IOM uint32_t TMR_MS_PERIOD_INT : 16; /*!< [15..0] This bits are used to program the + integer part of number of clock cycles per + 256 microseconds of the system clock used + */ + __IM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + } MCUULP_TMR_MS_PERIOD_INT_b; + }; + + union { + __IOM uint32_t MCUULP_TMR_MS_PERIOD_FRAC; /*!< (@ 0x00000090) Timer 256 microsecond + period Fractional Part Register */ + + struct { + __IOM uint32_t TMR_MS_PERIOD_FRAC : 8; /*!< [7..0] This bits are used to program the + fractional part of number of clock cycles + per 256 microseconds of the system clock + used */ + __IM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + } MCUULP_TMR_MS_PERIOD_FRAC_b; + }; + __IM uint32_t RESERVED1[2]; + + union { + __IM uint32_t MCUULP_TMR_ACTIVE_STATUS; /*!< (@ 0x0000009C) Timer Active + Status Register */ + + struct { + __IM uint32_t TIMER_ACTIVE : 4; /*!< [3..0] Timer active status for each + timer. LSB bit specifies + the status for 0th timer + and so on. */ + __IM uint32_t RESERVED1 : 28; /*!< [31..4] reserved1 */ + } MCUULP_TMR_ACTIVE_STATUS_b; + }; +} TIMERS_Type; /*!< Size = 160 (0xa0) */ + +/* =========================================================================================================================== + */ +/* ================ QEI + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief The Quadrature Encoder Interface (QEI) module provides the interface + to incremental encoders for obtaining mechanical position data (QEI) + */ + +typedef struct { /*!< (@ 0x47060000) QEI Structure */ + + union { + __IM uint32_t QEI_STATUS_REG; /*!< (@ 0x00000000) Quadrature Encoder status + register */ + + struct { + __IM uint32_t QEI_INDEX : 1; /*!< [0..0] This is a direct value from the + position signal generator */ + __IM uint32_t QEI_POSITION_B : 1; /*!< [1..1] This is a direct value from the + position signal generator.Value refers to the + signal Position_B from the generator. */ + __IM uint32_t QEI_POSITION_A : 1; /*!< [2..2] This is a direct value from the + position signal generator.Value refers to the + signal Position_A from the generator. */ + __IM uint32_t POSITION_CNTR_ERR : 1; /*!< [3..3] Count Error Status Flag bit */ + __IM uint32_t POSITION_CNTR_DIRECTION : 1; /*!< [4..4] Position Counter + Direction Status bit */ + __IM uint32_t RESERVED1 : 27; /*!< [31..5] Reserved1 */ + } QEI_STATUS_REG_b; + }; + + union { + __IOM uint32_t QEI_CTRL_REG_SET; /*!< (@ 0x00000004) Quadrature Encoder + control set register */ + + struct { + __IM uint32_t QEI_SFT_RST : 1; /*!< [0..0] Quadrature encoder soft reset. + It is self reset signal. */ + __IOM uint32_t QEI_SWAP_PHASE_AB : 1; /*!< [1..1] Phase A and Phase B + Input Swap Select bit */ + __IOM uint32_t POS_CNT_RST_WITH_INDEX_EN : 1; /*!< [2..2] Phase A and Phase B Input + Swap Select bit */ + __IOM uint32_t RESERVED1 : 1; /*!< [3..3] Reserved1 */ + __IOM uint32_t POS_CNT_DIRECTION_CTRL : 1; /*!< [4..4] NONE */ + __IOM uint32_t POS_CNT_DIR_FRM_REG : 1; /*!< [5..5] Position Counter Direction + indication from user */ + __IOM uint32_t RESERVED2 : 1; /*!< [6..6] Reserved2 */ + __IOM uint32_t RESERVED3 : 1; /*!< [7..7] Reserved3 */ + __IOM uint32_t INDEX_CNT_RST_EN : 1; /*!< [8..8] Index count reset enable */ + __IOM uint32_t DIGITAL_FILTER_BYPASS : 1; /*!< [9..9] NONE */ + __IOM uint32_t TIMER_MODE : 1; /*!< [10..10] NONE */ + __IOM uint32_t START_VELOCITY_CNTR : 1; /*!< [11..11] Starting the velocity counter. + It is self reset bit. */ + __IOM uint32_t QEI_STOP_IN_IDLE : 1; /*!< [12..12] NONE */ + __IOM uint32_t QEI_POS_CNT_16_BIT_MODE : 1; /*!< [13..13] Qei position counter 16 bit + mode enable */ + __IOM uint32_t POS_CNT_RST : 1; /*!< [14..14] 1=position counter is going + to reset */ + __IOM uint32_t INDEX_CNT_RST : 1; /*!< [15..15] 1= index counter is going + to reset. */ + __IOM uint32_t RESERVED4 : 16; /*!< [31..16] Reserved4 */ + } QEI_CTRL_REG_SET_b; + }; + + union { + __IOM uint32_t QEI_CTRL_REG_RESET; /*!< (@ 0x00000008) Quadrature Encoder + control reset register */ + + struct { + __IM uint32_t QEI_SFT_RST : 1; /*!< [0..0] Quadrature encoder soft reset. + It is self reset signal */ + __IOM uint32_t QEI_SWAP_PHASE_AB : 1; /*!< [1..1] Phase A and Phase B + Input Swap Select bit */ + __IOM uint32_t POS_CNT_RST_WITH_INDEX_EN : 1; /*!< [2..2] Phase A and Phase B Input + Swap Select bit */ + __IOM uint32_t RESERVED1 : 1; /*!< [3..3] Reserved1 */ + __IOM uint32_t POS_CNT_DIRECTION_CTRL : 1; /*!< [4..4] NONE */ + __IOM uint32_t POS_CNT_DIR_FRM_REG : 1; /*!< [5..5] Position Counter Direction + indication from user */ + __IOM uint32_t RESERVED2 : 1; /*!< [6..6] Reserved2 */ + __IOM uint32_t RESERVED3 : 1; /*!< [7..7] Reserved3 */ + __IOM uint32_t INDEX_CNT_RST_EN : 1; /*!< [8..8] NONE */ + __IOM uint32_t DIGITAL_FILTER_BYPASS : 1; /*!< [9..9] NONE */ + __IOM uint32_t TIMER_MODE : 1; /*!< [10..10] NONE */ + __IOM uint32_t START_VELOCITY_CNTR : 1; /*!< [11..11] Starting the velocity counter. + It is self reset bit. */ + __IOM uint32_t QEI_STOP_IN_IDLE : 1; /*!< [12..12] NONE */ + __IOM uint32_t QEI_POS_CNT_16_BIT_MODE : 1; /*!< [13..13] Qei position counter 16 bit + mode enable */ + __IOM uint32_t POS_CNT_RST : 1; /*!< [14..14] 1=position counter is going + to reset */ + __IOM uint32_t INDEX_CNT_RST : 1; /*!< [15..15] 1= index counter is going + to reset. */ + __IOM uint32_t RESERVED4 : 16; /*!< [31..16] Reserved4 */ + } QEI_CTRL_REG_RESET_b; + }; + + union { + __IOM uint32_t QEI_CNTLR_INIT_REG; /*!< (@ 0x0000000C) Quadrature Encoder + initialization register */ + + struct { + __IOM uint32_t QEI_ENCODING_MODE : 2; /*!< [1..0] NONE */ + __IOM uint32_t RESERVED1 : 2; /*!< [3..2] Reserved1 */ + __IOM uint32_t INDEX_MATCH_VALUE : 2; /*!< [5..4] These bits allow user to specify + the state of position A and B during index + pulse generation. */ + __IOM uint32_t DF_CLK_DIVIDE_SLT : 4; /*!< [9..6] Digital Filter Clock + Divide Select bits */ + __IOM uint32_t UNIDIRECTIONAL_VELOCITY : 1; /*!< [10..10] Uni directional + velocity enable. */ + __IOM uint32_t UNIDIRECTIONAL_INDEX : 1; /*!< [11..11] Uni directional + index enable. */ + __IOM uint32_t INDEX_CNT_INIT : 1; /*!< [12..12] Index counter initial value in + unidirectional index enable mode. */ + __IOM uint32_t RESERVED2 : 19; /*!< [31..13] Reserved2 */ + } QEI_CNTLR_INIT_REG_b; + }; + + union { + __IOM uint32_t QEI_INDEX_CNT_REG; /*!< (@ 0x00000010) Quadrature Encoder + index counter register */ + + struct { + __IOM uint32_t QEI_INDEX_CNT : 16; /*!< [15..0] Index counter value.User + can initialize/change the index + counter using this register */ + __IOM uint32_t QEI_INDEX_CNT_WR_VALUE : 16; /*!< [31..16] User can initialize/change + the index counter using + this register. */ + } QEI_INDEX_CNT_REG_b; + }; + + union { + __IOM uint32_t QEI_INDEX_MAX_CNT_REG; /*!< (@ 0x00000014) Quadrature Encoder maximum + index counter value register */ + + struct { + __IOM uint32_t QEI_INDEX_MAX_CNT : 16; /*!< [15..0] This is a maximum count value + that is allowed to increment in the index + counter. If index counter reaches this + value, will get reset to zero */ + __IOM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved1 */ + } QEI_INDEX_MAX_CNT_REG_b; + }; + + union { + __IOM uint32_t QEI_POSITION_CNT_REG; /*!< (@ 0x00000018) Quadrature Encoder maximum + position counter value register */ + + struct { + __IOM uint32_t QEI_POSITION_CNT_WR_VALUE_L : 16; /*!< [15..0] This is a maximum count + value that is allowed to + increment in the position + counter. */ + __IOM uint32_t QEI_POSITION_CNT_WR_VALUE_H : 16; /*!< [31..16] This is a maximum + count value that is allowed to + increment in the position + counter. */ + } QEI_POSITION_CNT_REG_b; + }; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t QEI_POSITION_MAX_CNT_LSW_REG; /*!< (@ 0x00000020) Quadrature + Encoder maximum position + counter value register */ + + struct { + __IOM uint32_t QEI_POSITION_MAX_CNT_L : 16; /*!< [15..0] This is a maximum + count value that is allowed + to increment in the + position counter. */ + __IOM uint32_t QEI_POSITION_MAX_CNT_H : 16; /*!< [31..16] This is a maximum count + value that is allowed to increment + in the position counter. + */ + } QEI_POSITION_MAX_CNT_LSW_REG_b; + }; + __IM uint32_t RESERVED1; + + union { + __IM uint32_t QEI_INTR_STS_REG; /*!< (@ 0x00000028) Quadrature Encoder + interrupt status register */ + + struct { + __IM uint32_t QEI_POSITION_CNT_RESET_INTR_LEV : 1; /*!< [0..0] This is raised when + the position counter reaches + it's extremes */ + __IM uint32_t QEI_INDEX_CNT_MATCH_INTR_LEV : 1; /*!< [1..1] This is raised when + index counter reaches max value + loaded in to index_max_cnt + register. */ + __IM uint32_t POSITION_CNTR_ERR_INTR_LEV : 1; /*!< [2..2] Whenever number of + possible positions are mismatched + with actual positions are received + between two index pulses this will + raised */ + __IM uint32_t VELOCITY_LESS_THAN_INTR_LEV : 1; /*!< [3..3] When velocity count is + less than the value given in + velocity_value_to_c mpare + register, interrupt is raised */ + __IM uint32_t QEI_POSITION_CNT_MATCH_INTR_LEV : 1; /*!< [4..4] This is raised when + the position counter reaches + position + match value, which is + programmable. */ + __IM uint32_t QEI_VELOCITY_COMPUTATION_OVER_INTR_LEV : 1; /*!< [5..5] When velocity + count is computed for + given delta time, than + interrupt is raised. */ + __IM uint32_t RESERVED1 : 26; /*!< [31..6] Reserved1 */ + } QEI_INTR_STS_REG_b; + }; + + union { + __IOM uint32_t QEI_INTR_ACK_REG; /*!< (@ 0x0000002C) Quadrature Encoder + interrupt acknowledge register */ + + struct { + __IOM uint32_t QEI_POSITION_CNT_RESET_INTR_LEV : 1; /*!< [0..0] + Qei_position_cnt_reset_intr_ack + */ + __IOM uint32_t QEI_INDEX_CNT_MATCH_INTR_LEV : 1; /*!< [1..1] NONE */ + __IOM uint32_t POSITION_CNTR_ERR_INTR_LEV : 1; /*!< [2..2] Position_cntr_err_intr_ack + */ + __IOM uint32_t VELOCITY_LESS_THAN_INTR_LEV : 1; /*!< [3..3] + Velocity_less_than_intr_ack */ + __IOM uint32_t QEI_POSITION_CNT_MATCH_INTR_LEV : 1; /*!< [4..4] + Qei_position_cnt_match_intr_ack + */ + __IOM uint32_t VELOCITY_COMPUTATION_OVER_INTR_LEV : 1; /*!< [5..5] + Velocity_computation_over_intr_ack + */ + __IOM uint32_t RESERVED1 : 26; /*!< [31..6] Reserved1 */ + } QEI_INTR_ACK_REG_b; + }; + + union { + __IOM uint32_t QEI_INTR_MASK_REG; /*!< (@ 0x00000030) Quadrature Encoder + interrupt mask register */ + + struct { + __IOM uint32_t QEI_POSITION_CNT_RESET_INTR_MASK : 1; /*!< [0..0] + Qei_position_cnt_reset_intr_mask + */ + __IOM uint32_t QEI_INDEX_CNT_MATCH_INTR_MASK : 1; /*!< [1..1] + Qei_index_cnt_match_intr_mask + */ + __IOM uint32_t POSITION_CNTR_ERR_INTR_MASK : 1; /*!< [2..2] + Position_cntr_err_intr_mask */ + __IOM uint32_t VELOCITY_LESS_THAN_INTR_MASK : 1; /*!< [3..3] + Velocity_less_than_intr_mask */ + __IOM uint32_t QEI_POSITION_CNT_MATCH_INTR_MASK : 1; /*!< [4..4] + Qei_position_cnt_match_intr_mask + */ + __IOM uint32_t VELOCITY_COMPUTATION_OVER_INTR_MASK : 1; /*!< [5..5] + Velocity_computation_over_intr_mask + */ + __IOM uint32_t RESERVED1 : 26; /*!< [31..6] Reserved1 */ + } QEI_INTR_MASK_REG_b; + }; + + union { + __IOM uint32_t QEI_INTR_UNMASK_REg; /*!< (@ 0x00000034) Quadrature Encoder + interrupt unmask register */ + + struct { + __IOM uint32_t QEI_POSITION_CNT_RESET_INTR_UNMASK : 1; /*!< [0..0] + Qei_position_cnt_reset_intr_unmask + */ + __IOM uint32_t QEI_INDEX_CNT_MATCH_INTR_UNMASK : 1; /*!< [1..1] + Qei_index_cnt_match_intr_unmask + */ + __IOM uint32_t POSITION_CNTR_ERR_INTR_UNMASK : 1; /*!< [2..2] + Position_cntr_err_intr_unmask + */ + __IOM uint32_t VELOCITY_LESS_THAN_INTR_UNMASK : 1; /*!< [3..3] + Velocity_less_than_intr_unmask + */ + __IOM uint32_t QEI_POSITION_CNT_MATCH_INTR_UNMASK : 1; /*!< [4..4] + Qei_position_cnt_match_intr_unmask + */ + __IOM uint32_t RESERVED1 : 27; /*!< [31..5] Reserved1 */ + } QEI_INTR_UNMASK_REg_b; + }; + + union { + __IOM uint32_t QEI_CLK_FREQ_REG; /*!< (@ 0x00000038) Quadrature Encoder + clock frequency register */ + + struct { + __IOM uint32_t QEI_CLK_FREQ : 9; /*!< [8..0] Indication of clock frequency on which + QEI controller is running. */ + __IOM uint32_t RESERVED1 : 23; /*!< [31..9] Reserved1 */ + } QEI_CLK_FREQ_REG_b; + }; + + union { + __IOM uint32_t QEI_DELTA_TIME_REG; /*!< (@ 0x0000003C) Quadrature Delta time + register */ + + struct { + __IOM uint32_t DELTA_TIME_FOR_VELOCITY : 20; /*!< [19..0] Delta time LSW + to compute velocity */ + __IOM uint32_t RESERVED1 : 12; /*!< [31..20] Reserved1 */ + } QEI_DELTA_TIME_REG_b; + }; + __IM uint32_t RESERVED2; + + union { + __IOM uint32_t QEI_VELOCITY_REG; /*!< (@ 0x00000044) Quadrature velocity register */ + + struct { + __IOM uint32_t VELOCITY_VALUE_TO_COMPARE_L : 16; /*!< [15..0] For read operation :It + is the velocity count to compare + using TA firmware For + write operation :It is the + velocity value to compare with + velocity count */ + __IOM uint32_t VELOCITY_VALUE_TO_COMPARE_H : 16; /*!< [31..16] For read operation :It + is the velocity count to compare + using TA firmware For + write operation :It is the + velocity value to compare with + velocity count */ + } QEI_VELOCITY_REG_b; + }; + __IM uint32_t RESERVED3; + + union { + __IOM uint32_t QEI_POSITION_MATCH_REG; /*!< (@ 0x0000004C) Quadrature + position match register */ + + struct { + __IOM uint32_t POSTION_MATCH_VALUE_L : 16; /*!< [15..0] Position match value to + compare the position counter. */ + __IOM uint32_t POSTION_MATCH_VALUE_H : 16; /*!< [31..16] Position match value to + compare the position counter. */ + } QEI_POSITION_MATCH_REG_b; + }; +} QEI_Type; /*!< Size = 80 (0x50) */ + +/* =========================================================================================================================== + */ +/* ================ USART0 + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief Universal Asynchronous Receiver/Transmitter is for serial + communication with peripherals, modems and datasets (USART0) + */ + +typedef struct { /*!< (@ 0x44000100) USART0 Structure */ + + union { + union { + __IOM uint32_t DLL; /*!< (@ 0x00000000) Divisor Latch Low */ + + struct { + __IOM uint32_t DLL : 8; /*!< [7..0] Lower 8-bits of a 16-bit, read/write, Divisor + Latch register that contains the baud rate divisor for + the UART. */ + __IM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + } DLL_b; + }; + + union { + __OM uint32_t THR; /*!< (@ 0x00000000) Transmit Holding Register */ + + struct { + __OM uint32_t THR : 8; /*!< [7..0] Data to be transmitted on serial + output port */ + __OM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + } THR_b; + }; + + union { + __IM uint32_t RBR; /*!< (@ 0x00000000) Receive Buffer Register */ + + struct { + __IM uint32_t RBR : 8; /*!< [7..0] Receive Buffer Field */ + __IM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + } RBR_b; + }; + }; + + union { + union { + __IOM uint32_t IER; /*!< (@ 0x00000004) Interrupt Enable Register */ + + struct { + __IOM uint32_t ERBFI : 1; /*!< [0..0] Enable Received Data Available Interrupt */ + __IOM uint32_t ETBEI : 1; /*!< [1..1] Enable Transmit Holding Register + Empty Interrupt */ + __IOM uint32_t ELSI : 1; /*!< [2..2] Enable Receiver Line Status Interrupt */ + __IOM uint32_t EDSSI : 1; /*!< [3..3] Enable Modem Status Interrupt */ + __IM uint32_t RESERVED1 : 3; /*!< [6..4] reserved1 */ + __IOM uint32_t PTIME : 1; /*!< [7..7] Programmable THRE Interrupt Mode Enable */ + __IM uint32_t RESERVED2 : 24; /*!< [31..8] reserved2 */ + } IER_b; + }; + + union { + __IOM uint32_t DLH; /*!< (@ 0x00000004) Divisor Latch High */ + + struct { + __IOM uint32_t DLH : 8; /*!< [7..0] Upper 8-bits of a 16-bit, read/write, Divisor + Latch register that contains the baud rate divisor for + the UART */ + __IM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + } DLH_b; + }; + }; + + union { + union { + __OM uint32_t FCR; /*!< (@ 0x00000008) FIFO Control Register */ + + struct { + __OM uint32_t FIFOE : 1; /*!< [0..0] This enables/disables the transmit + (XMIT) and receive (RCVR) FIFOs */ + __OM uint32_t RFIFOR : 1; /*!< [1..1] RCVR FIFO Reset */ + __OM uint32_t XFIFOR : 1; /*!< [2..2] XMIT FIFO Reset */ + __OM uint32_t DMAM : 1; /*!< [3..3] DMA signalling mode */ + __OM uint32_t TET : 2; /*!< [5..4] TX Empty Trigger */ + __OM uint32_t RT : 2; /*!< [7..6] This is used to select the trigger level in the + receiver FIFO at which the Received Data Available + Interrupt is generated */ + __OM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + } FCR_b; + }; + + union { + __IM uint32_t IIR; /*!< (@ 0x00000008) Interrupt Identity Register */ + + struct { + __IM uint32_t IID : 4; /*!< [3..0] Interrupt ID */ + __IM uint32_t RESERVED1 : 2; /*!< [5..4] reserved1 */ + __IM uint32_t FIFOSE : 2; /*!< [7..6] This is used to indicate whether + the FIFOs are enabled or disabled. */ + __IM uint32_t RESERVED2 : 24; /*!< [31..8] reserved2 */ + } IIR_b; + }; + }; + + union { + __IOM uint32_t LCR; /*!< (@ 0x0000000C) Line Control Register */ + + struct { + __IOM uint32_t DLS : 2; /*!< [1..0] Data Length Select,This is used to + select the number of data bits per character + that the peripheral transmits and receives */ + __IOM uint32_t STOP : 1; /*!< [2..2] This is used to select the number of + stop bits per character that the peripheral + transmits and receives */ + __IOM uint32_t PEN : 1; /*!< [3..3] This bit is used to enable and disable parity + generation and detection in transmitted and received + serial character */ + __IOM uint32_t EPS : 1; /*!< [4..4] This is used to select between even + and odd parity */ + __IOM uint32_t STICK_PARITY : 1; /*!< [5..5] This bit is used to force + parity value */ + __IOM uint32_t BC : 1; /*!< [6..6] This is used to cause a break condition + to be transmitted to the receiving device */ + __IOM uint32_t DLAB : 1; /*!< [7..7] This bit is used to enable reading + and writing of the Divisor Latch register to + set the baud rate of the UART */ + __IOM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + } LCR_b; + }; + + union { + __IOM uint32_t MCR; /*!< (@ 0x00000010) Modem Control Register */ + + struct { + __IOM uint32_t DTR : 1; /*!< [0..0] This is used to directly control the + Data Terminal Ready (dtr_n) output */ + __IOM uint32_t RTS : 1; /*!< [1..1] This is used to directly control the + Request to Send (rts_n) output */ + __IOM uint32_t OUT1 : 1; /*!< [2..2] This is used to directly control the + user-designated Output1 (out1_n) output */ + __IOM uint32_t OUT2 : 1; /*!< [3..3] This is used to directly control the + user-designated Output2 (out2_n) output */ + __IOM uint32_t LB : 1; /*!< [4..4] This is used to put the UART into a + diagnostic mode for test purposes */ + __IOM uint32_t AFCE : 1; /*!< [5..5] This is used to directly control the + user-designated Output2 (out2_n) output */ + __IOM uint32_t SIRE : 1; /*!< [6..6] This is used to enable/disable the + IrDA SIR Mode features */ + __IM uint32_t RESERVED1 : 25; /*!< [31..7] reserved1 */ + } MCR_b; + }; + + union { + __IM uint32_t LSR; /*!< (@ 0x00000014) Line Status Register */ + + struct { + __IM uint32_t DR : 1; /*!< [0..0] This is used to indicate that the + receiver contains at least one character in the + RBR or the receiver FIFO */ + __IM uint32_t OE : 1; /*!< [1..1] This is used to indicate the occurrence + of an overrun error */ + __IM uint32_t PE : 1; /*!< [2..2] This is used to indicate the occurrence + of a parity error in the receiver if the Parity + Enable (PEN) bit (LCR[3]) is set */ + __IM uint32_t FE : 1; /*!< [3..3] This is used to indicate the occurrence + of a framing error in the receiver */ + __IM uint32_t BI : 1; /*!< [4..4] his is used to indicate the detection of + a break sequence on the serial input data */ + __IM uint32_t THRE : 1; /*!< [5..5] Transmit Holding Register Empty bit */ + __IM uint32_t TEMT : 1; /*!< [6..6] Transmitter Empty bit */ + __IM uint32_t RFE : 1; /*!< [7..7] This is used to indicate if there is at + least one parity error,framing error, or break + indication in the FIFO */ + __IM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + } LSR_b; + }; + + union { + __IM uint32_t MSR; /*!< (@ 0x00000018) Modem Status Register */ + + struct { + __IM uint32_t DCTS : 1; /*!< [0..0] This is used to indicate that the modem control + line cts_n has changed since the last time the MSR was + read */ + __IM uint32_t DDSR : 1; /*!< [1..1] This is used to indicate that the modem control + line dsr_n has changed since the last time the MSR was + read */ + __IM uint32_t TERI : 1; /*!< [2..2] This is used to indicate that a change on the + input ri_n(from an active-low to an inactive-high state) + has occurred since the last time the MSR was read */ + __IM uint32_t DDCD : 1; /*!< [3..3] This is used to indicate that the modem control + line dcd_n has changed since the last time the MSR was + read */ + __IM uint32_t CTS : 1; /*!< [4..4] This is used to indicate the current + state of the modem control line cts_n */ + __IM uint32_t DSR : 1; /*!< [5..5] This is used to indicate the current + state of the modem control line dsr_n */ + __IM uint32_t RI : 1; /*!< [6..6] This is used to indicate the current + state of the modem control line ri_n */ + __IM uint32_t DCD : 1; /*!< [7..7] This is used to indicate the current + state of the modem control line dcd_n */ + __IM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + } MSR_b; + }; + + union { + __IOM uint32_t SCR; /*!< (@ 0x0000001C) Scratch pad Register */ + + struct { + __IOM uint32_t SCRATCH_PAD : 8; /*!< [7..0] This register is for programmers to use + as a temporary storage space. It has no defined + purpose */ + __IM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + } SCR_b; + }; + + union { + __IOM uint32_t LPDLL; /*!< (@ 0x00000020) Low Power Divisor Latch Low Register */ + + struct { + __IOM uint32_t LOW_POWER_DLL : 8; /*!< [7..0] This register makes up the lower 8-bits + of a 16-bit, read/write, Low Power Divisor Latch + register that contains the baud rate divisor for + the UART, which must give a baud + rate of 115.2K */ + __IOM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + } LPDLL_b; + }; + + union { + __IOM uint32_t LPDLH; /*!< (@ 0x00000024) Low Power Divisor Latch High Register */ + + struct { + __IOM uint32_t LOW_POWER_DLH : 8; /*!< [7..0] This register makes up the upper 8-bits + of a 16-bit, read/write, Low Power Divisor Latch + register that contains the baud rate divisor for + the UART, which must give a baud + rate of 115200 */ + __IOM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + } LPDLH_b; + }; + __IM uint32_t RESERVED[6]; + + union { + __IOM uint32_t HDEN; /*!< (@ 0x00000040) none */ + + struct { + __IOM uint32_t FULL_DUPLEX_MODE : 1; /*!< [0..0] none */ + __IOM uint32_t TX_MODE_RX_MODE : 1; /*!< [1..1] This signal is valid when + full_duplex_mode is disabled */ + __IM uint32_t RESERVED1 : 30; /*!< [31..2] reserved1 */ + } HDEN_b; + }; + __IM uint32_t RESERVED1[5]; + + union { + __IOM uint32_t SMCR; /*!< (@ 0x00000058) none */ + + struct { + __IOM uint32_t SYNC_MODE : 1; /*!< [0..0] none */ + __IOM uint32_t MST_MODE : 1; /*!< [1..1] none */ + __IOM uint32_t RESERVED1 : 2; /*!< [3..2] reserved1 */ + __IOM uint32_t CONTI_CLK_MODE : 1; /*!< [4..4] none */ + __IOM uint32_t START_STOP_EN : 1; /*!< [5..5] none */ + __IOM uint32_t RESERVED2 : 26; /*!< [31..6] reserved2 */ + } SMCR_b; + }; + __IM uint32_t RESERVED2[5]; + + union { + __IOM uint32_t FAR; /*!< (@ 0x00000070) none */ + + struct { + __IOM uint32_t SYNC_MODE : 1; /*!< [0..0] none */ + __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + } FAR_b; + }; + + union { + __IM uint32_t TFR; /*!< (@ 0x00000074) none */ + + struct { + __IM uint32_t TX_FIFO_RD : 8; /*!< [7..0] Transmit FIFO Read */ + __IM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + } TFR_b; + }; + + union { + __IOM uint32_t RFW; /*!< (@ 0x00000078) none */ + + struct { + __IOM uint32_t RFWD : 8; /*!< [7..0] Receive FIFO Write Data */ + __IOM uint32_t RFPE : 1; /*!< [8..8] Receive FIFO Parity Error */ + __IOM uint32_t RFFE : 1; /*!< [9..9] Receive FIFO Framing Error */ + __IM uint32_t RESERVED1 : 22; /*!< [31..10] reserved1 */ + } RFW_b; + }; + + union { + __IM uint32_t USR; /*!< (@ 0x0000007C) UART Status Register */ + + struct { + __IM uint32_t BUSY : 1; /*!< [0..0] Indicates that a serial transfer is in + progress */ + __IM uint32_t TFNF : 1; /*!< [1..1] To Indicate that the transmit FIFO is + not full */ + __IM uint32_t TFE : 1; /*!< [2..2] To Indicate that the transmit FIFO is + completely empty */ + __IM uint32_t RFNE : 1; /*!< [3..3] To Indicate that the receive FIFO + contains one or more entries */ + __IM uint32_t RFE : 1; /*!< [4..4] To Indicate that the receive FIFO is + completely full */ + __IM uint32_t RESERVED1 : 27; /*!< [31..5] reserved1 */ + } USR_b; + }; + + union { + __IM uint32_t TFL; /*!< (@ 0x00000080) Transmit FIFO Level */ + + struct { + __IM uint32_t FIFO_ADDR_WIDTH : 30; /*!< [29..0] Transmit FIFO Level. This + is indicates the number of data + entries in the transmit FIFO. */ + __IM uint32_t RESERVED1 : 2; /*!< [31..30] reserved1 */ + } TFL_b; + }; + + union { + __IM uint32_t RFL; /*!< (@ 0x00000084) Receive FIFO Level */ + + struct { + __IM uint32_t FIFO_ADDR_WIDTH : 30; /*!< [29..0] Receive FIFO Level. This + is indicates the number of data + entries in the receive FIFO. */ + __IM uint32_t RESERVED1 : 2; /*!< [31..30] reserved1 */ + } RFL_b; + }; + + union { + __OM uint32_t SRR; /*!< (@ 0x00000088) Software Reset Register */ + + struct { + __OM uint32_t UR : 1; /*!< [0..0] UART Reset */ + __OM uint32_t RFR : 1; /*!< [1..1] RCVR FIFO Reset */ + __OM uint32_t XFR : 1; /*!< [2..2] XMIT FIFO Reset */ + __OM uint32_t RESERVED1 : 29; /*!< [31..3] reserved1 */ + } SRR_b; + }; + + union { + __IOM uint32_t SRTS; /*!< (@ 0x0000008C) Shadow Request to Send */ + + struct { + __IOM uint32_t SRTS : 1; /*!< [0..0] Shadow Request to Send. */ + __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + } SRTS_b; + }; + + union { + __IOM uint32_t SBCR; /*!< (@ 0x00000090) Shadow Break Control Register */ + + struct { + __IOM uint32_t SBCR : 1; /*!< [0..0] Shadow Break Control Bit */ + __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + } SBCR_b; + }; + + union { + __IOM uint32_t SDMAM; /*!< (@ 0x00000094) Shadow DMA Mode */ + + struct { + __IOM uint32_t SDMAM : 1; /*!< [0..0] Shadow DMA Mode */ + __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + } SDMAM_b; + }; + + union { + __IOM uint32_t SFE; /*!< (@ 0x00000098) Shadow FIFO Enable */ + + struct { + __IOM uint32_t SFE : 1; /*!< [0..0] Shadow FIFO Enable */ + __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + } SFE_b; + }; + + union { + __IOM uint32_t SRT; /*!< (@ 0x0000009C) Shadow RCVR Trigger */ + + struct { + __IOM uint32_t SRT : 2; /*!< [1..0] Shadow RCVR Trigger */ + __IM uint32_t RESERVED1 : 30; /*!< [31..2] reserved1 */ + } SRT_b; + }; + + union { + __IOM uint32_t STET; /*!< (@ 0x000000A0) Shadow TX Empty Trigger */ + + struct { + __IOM uint32_t STET : 2; /*!< [1..0] Shadow TX Empty Trigger */ + __IM uint32_t RESERVED1 : 30; /*!< [31..2] reserved1 */ + } STET_b; + }; + + union { + __IOM uint32_t HTX; /*!< (@ 0x000000A4) Halt Transmit */ + + struct { + __IOM uint32_t HALT_TX : 1; /*!< [0..0] This register is use to halt + transmissions for testing */ + __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + } HTX_b; + }; + + union { + __IOM uint32_t DMASA; /*!< (@ 0x000000A8) DMA Software Acknowledge */ + + struct { + __OM uint32_t DMA_SOFTWARE_ACK : 1; /*!< [0..0] This register is use to perform a + DMA software acknowledge + if a transfer needs to be terminated + due to an error condition */ + __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + } DMASA_b; + }; + + union { + __IOM uint32_t TCR; /*!< (@ 0x000000AC) Transceiver Control Register. */ + + struct { + __IOM uint32_t RS485_EN : 1; /*!< [0..0] RS485 Transfer Enable. */ + __IOM uint32_t RE_POL : 1; /*!< [1..1] Receiver Enable Polarity. */ + __IOM uint32_t DE_POL : 1; /*!< [2..2] Driver Enable Polarity. */ + __IOM uint32_t XFER_MODE : 2; /*!< [4..3] Transfer Mode. */ + __IM uint32_t RESERVED1 : 27; /*!< [31..5] reserved1 */ + } TCR_b; + }; + + union { + __IOM uint32_t DE_EN; /*!< (@ 0x000000B0) Driver Output Enable Register. */ + + struct { + __IOM uint32_t DE_EN : 1; /*!< [0..0] DE Enable control. */ + __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + } DE_EN_b; + }; + + union { + __IOM uint32_t RE_EN; /*!< (@ 0x000000B4) Receiver Output Enable Register. */ + + struct { + __IOM uint32_t RE_EN : 1; /*!< [0..0] RE Enable control. */ + __IM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + } RE_EN_b; + }; + + union { + __IOM uint32_t DET; /*!< (@ 0x000000B8) Driver Output Enable Timing Register. */ + + struct { + __IOM uint32_t DE_ASSERT_TIME : 8; /*!< [7..0] Driver enable assertion time. */ + __IOM uint32_t RES : 8; /*!< [15..8] reserved. */ + __IOM uint32_t DE_DE_ASSERT_TIME : 8; /*!< [23..16] Driver enable + de-assertion time. */ + __IM uint32_t RESERVED1 : 8; /*!< [31..24] reserved1 */ + } DET_b; + }; + + union { + __IOM uint32_t TAT; /*!< (@ 0x000000BC) TurnAround Timing Register */ + + struct { + __IOM uint32_t DE_RE : 16; /*!< [15..0] Driver Enable to Receiver Enable + TurnAround time. */ + __IOM uint32_t RE_DE : 16; /*!< [31..16] Receiver Enable to Driver Enable + TurnAround time. */ + } TAT_b; + }; + + union { + __IOM uint32_t DLF; /*!< (@ 0x000000C0) Divisor Latch Fraction Register. */ + + struct { + __IOM uint32_t DLF : 6; /*!< [5..0] Fractional part of divisor. */ + __IM uint32_t : 1; + __IM uint32_t RESERVED1 : 25; /*!< [31..7] reserved1 */ + } DLF_b; + }; + + union { + __IOM uint32_t RAR; /*!< (@ 0x000000C4) Receive Address Register. */ + + struct { + __IOM uint32_t RAR : 8; /*!< [7..0] This is an address matching register + during receive mode. */ + __IM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + } RAR_b; + }; + + union { + __IOM uint32_t TAR; /*!< (@ 0x000000C8) Transmit Address Register. */ + + struct { + __IOM uint32_t TAR : 8; /*!< [7..0] This is an address matching register + during transmit mode. */ + __IM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + } TAR_b; + }; + + union { + __IOM uint32_t LCR_EXT; /*!< (@ 0x000000CC) Line Extended Control Register */ + + struct { + __IOM uint32_t DLS_E : 1; /*!< [0..0] Extension for DLS. */ + __IOM uint32_t ADDR_MATCH : 1; /*!< [1..1] Address Match Mode. */ + __IOM uint32_t SEND_ADDR : 1; /*!< [2..2] Send address control bit. */ + __IOM uint32_t TRANSMIT_MODE : 1; /*!< [3..3] Transmit mode control bit. */ + __IM uint32_t RESERVED1 : 28; /*!< [31..4] reserved1 */ + } LCR_EXT_b; + }; + __IM uint32_t RESERVED3[9]; + + union { + __IM uint32_t CPR; /*!< (@ 0x000000F4) Component Parameter Register */ + + struct { + __IM uint32_t APB_DATA_WIDTH : 2; /*!< [1..0] APB data width register. */ + __IM uint32_t RESERVED1 : 2; /*!< [3..2] reserved1 */ + __IM uint32_t AFCE_MODE : 1; /*!< [4..4] none */ + __IM uint32_t THRE_MODE : 1; /*!< [5..5] none */ + __IM uint32_t SIR_MODE : 1; /*!< [6..6] none */ + __IM uint32_t SIR_LP_MODE : 1; /*!< [7..7] none */ + __IM uint32_t ADDITIONAL_FEAT : 1; /*!< [8..8] none */ + __IM uint32_t FIFO_ACCESS : 1; /*!< [9..9] none */ + __IM uint32_t FIFO_STAT : 1; /*!< [10..10] none */ + __IM uint32_t SHADOW : 1; /*!< [11..11] none */ + __IM uint32_t UART_ADD_ENCODED_PARAMS : 1; /*!< [12..12] none */ + __IM uint32_t DMA_EXTRA : 1; /*!< [13..13] none */ + __IM uint32_t RESERVED2 : 2; /*!< [15..14] reserved2 */ + __IM uint32_t FIFO_MODE : 8; /*!< [23..16] none */ + __IM uint32_t RESERVED3 : 8; /*!< [31..24] reserved3 */ + } CPR_b; + }; + + union { + __IM uint32_t UCV; /*!< (@ 0x000000F8) UART Component Version */ + + struct { + __IM uint32_t UART_COMP_VER : 32; /*!< [31..0] ASCII value for each number + in the version, followed by * */ + } UCV_b; + }; + + union { + __IM uint32_t CTR; /*!< (@ 0x000000FC) Component Type Register */ + + struct { + __IM uint32_t UART_COMP_VER : 32; /*!< [31..0] This register contains the + peripherals identification code. */ + } CTR_b; + }; +} USART0_Type; /*!< Size = 256 (0x100) */ + +/* =========================================================================================================================== + */ +/* ================ GSPI0 + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief GSPI, or Generic SPI, is a module which has been derived from QSPI. + * GSPI can act only as a master (GSPI0) + */ + +typedef struct { /*!< (@ 0x45030000) GSPI0 Structure */ + + union { + __IOM uint32_t GSPI_CLK_CONFIG; /*!< (@ 0x00000000) GSPI Clock Configuration + Register */ + + struct { + __IOM uint32_t GSPI_CLK_SYNC : 1; /*!< [0..0] If the clock frequency to FLASH + (spi_clk) and SOC clk is same. */ + __IOM uint32_t GSPI_CLK_EN : 1; /*!< [1..1] GSPI clock enable */ + __IOM uint32_t RESERVED1 : 30; /*!< [31..2] reserved for future use */ + } GSPI_CLK_CONFIG_b; + }; + + union { + __IOM uint32_t GSPI_BUS_MODE; /*!< (@ 0x00000004) GSPI Bus Mode Register */ + + struct { + __IOM uint32_t GSPI_DATA_SAMPLE_EDGE : 1; /*!< [0..0] Samples MISO data on + clock edges. This should be + ZERO for mode3 clock */ + __IOM uint32_t GSPI_CLK_MODE_CSN0 : 1; /*!< [1..1] NONE */ + __IOM uint32_t GSPI_CLK_MODE_CSN1 : 1; /*!< [2..2] NONE */ + __IOM uint32_t GSPI_CLK_MODE_CSN2 : 1; /*!< [3..3] NONE */ + __IOM uint32_t GSPI_CLK_MODE_CSN3 : 1; /*!< [4..4] NONE */ + __IOM uint32_t GSPI_GPIO_MODE_ENABLES : 6; /*!< [10..5] These bits are used to map + GSPI on GPIO pins */ + __IOM uint32_t SPI_HIGH_PERFORMANCE_EN : 1; /*!< [11..11] High performance + features are enabled when + this bit is set to one */ + __IOM uint32_t RESERVED1 : 20; /*!< [31..12] reserved for future use */ + } GSPI_BUS_MODE_b; + }; + __IM uint32_t RESERVED[2]; + + union { + __IOM uint32_t GSPI_CONFIG1; /*!< (@ 0x00000010) GSPI Configuration 1 Register */ + + struct { + __IOM uint32_t GSPI_MANUAL_CSN : 1; /*!< [0..0] SPI CS in manual mode */ + __IOM uint32_t GSPI_MANUAL_WR : 1; /*!< [1..1] Write enable for manual + mode when CS is low. */ + __IOM uint32_t GSPI_MANUAL_RD : 1; /*!< [2..2] Read enable for manual mode + when CS is low */ + __IOM uint32_t GSPI_MANUAL_RD_CNT : 10; /*!< [12..3] Indicates total + number of bytes to be read */ + __IOM uint32_t GSPI_MANUAL_CSN_SELECT : 2; /*!< [14..13] Indicates which CSn is + valid. Can be programmable in manual + mode */ + __IOM uint32_t SPI_FULL_DUPLEX_EN : 1; /*!< [15..15] Full duplex mode enable */ + __IOM uint32_t RESERVED1 : 16; /*!< [31..16] reserved for future use */ + } GSPI_CONFIG1_b; + }; + + union { + __IOM uint32_t GSPI_CONFIG2; /*!< (@ 0x00000014) GSPI Manual Configuration 2 + Register */ + + struct { + __IOM uint32_t GSPI_WR_DATA_SWAP_MNL_CSN0 : 1; /*!< [0..0] Swap the write data inside + the GSPI controller it-self. */ + __IOM uint32_t GSPI_WR_DATA_SWAP_MNL_CSN1 : 1; /*!< [1..1] Swap the write data inside + the GSPI controller it-self. */ + __IOM uint32_t GSPI_WR_DATA_SWAP_MNL_CSN2 : 1; /*!< [2..2] Swap the write data inside + the GSPI controller it-self. */ + __IOM uint32_t GSPI_WR_DATA_SWAP_MNL_CSN3 : 1; /*!< [3..3] Swap the write data inside + the GSPI controller it-self. */ + __IOM uint32_t GSPI_RD_DATA_SWAP_MNL_CSN0 : 1; /*!< [4..4] Swap the read data inside + the GSPI controller it-self. */ + __IOM uint32_t GSPI_RD_DATA_SWAP_MNL_CSN1 : 1; /*!< [5..5] Swap the read data inside + the GSPI controller it-self. */ + __IOM uint32_t GSPI_RD_DATA_SWAP_MNL_CSN2 : 1; /*!< [6..6] Swap the read data inside + the GSPI controller it-self. */ + __IOM uint32_t GSPI_RD_DATA_SWAP_MNL_CSN3 : 1; /*!< [7..7] Swap the read data inside + the GSPI controller it-self. */ + __IOM uint32_t GSPI_MANUAL_SIZE_FRM_REG : 1; /*!< [8..8] Manual reads and + manual writes */ + __IOM uint32_t RESERVED1 : 1; /*!< [9..9] reserved for future use */ + __IOM uint32_t TAKE_GSPI_MANUAL_WR_SIZE_FRM_REG : 1; /*!< [10..10] NONE */ + __IOM uint32_t MANUAL_GSPI_MODE : 1; /*!< [11..11] Internally the priority + is given to manual mode */ + __IOM uint32_t RESERVED2 : 20; /*!< [31..12] reserved for future use */ + } GSPI_CONFIG2_b; + }; + + union { + __IOM uint32_t GSPI_WRITE_DATA2; /*!< (@ 0x00000018) GSPI Write Data 2 Register */ + + struct { + __IOM uint32_t GSPI_MANUAL_WRITE_DATA2 : 4; /*!< [3..0] Number of bits to be written + in write mode */ + __IOM uint32_t RESERVED1 : 3; /*!< [6..4] reserved for future use */ + __IOM uint32_t USE_PREV_LENGTH : 1; /*!< [7..7] Use previous length */ + __IOM uint32_t RESERVED2 : 24; /*!< [31..8] reserved for future use */ + } GSPI_WRITE_DATA2_b; + }; + + union { + __IOM uint32_t GSPI_FIFO_THRLD; /*!< (@ 0x0000001C) GSPI FIFO Threshold Register */ + + struct { + __IOM uint32_t FIFO_AEMPTY_THRLD : 4; /*!< [3..0] FIFO almost empty threshold */ + __IOM uint32_t FIFO_AFULL_THRLD : 4; /*!< [7..4] FIFO almost full threshold */ + __IOM uint32_t WFIFO_RESET : 1; /*!< [8..8] Write FIFO reset */ + __IOM uint32_t RFIFO_RESET : 1; /*!< [9..9] read FIFO reset */ + __IOM uint32_t RESERVED1 : 22; /*!< [31..10] reserved for future use */ + } GSPI_FIFO_THRLD_b; + }; + + union { + __IM uint32_t GSPI_STATUS; /*!< (@ 0x00000020) GSPI Status Register */ + + struct { + __IM uint32_t GSPI_BUSY : 1; /*!< [0..0] State of Manual mode */ + __IM uint32_t FIFO_FULL_WFIFO_S : 1; /*!< [1..1] Full status indication + for Wfifo in manual mode */ + __IM uint32_t FIFO_AFULL_WFIFO_S : 1; /*!< [2..2] Almost full status indication for + Wfifo in manual mode */ + __IM uint32_t FIFO_EMPTY_WFIFO : 1; /*!< [3..3] Empty status indication + for Wfifo in manual mode */ + __IM uint32_t RESERVED1 : 1; /*!< [4..4] reserved for future use */ + __IM uint32_t FIFO_FULL_RFIFO : 1; /*!< [5..5] Full status indication for + Rfifo in manual mode */ + __IM uint32_t RESERVED2 : 1; /*!< [6..6] reserved for future use */ + __IM uint32_t FIFO_EMPTY_RFIFO_S : 1; /*!< [7..7] Empty status indication + for Rfifo in manual mode */ + __IM uint32_t FIFO_AEMPTY_RFIFO_S : 1; /*!< [8..8] Aempty status indication for + Rfifo in manual mode */ + __IM uint32_t GSPI_MANUAL_RD_CNT : 1; /*!< [9..9] This is a result of 10 + bits ORing counter */ + __IM uint32_t GSPI_MANUAL_CSN : 1; /*!< [10..10] Provide the status of + chip select signal */ + __IM uint32_t RESERVED3 : 21; /*!< [31..11] reserved for future use */ + } GSPI_STATUS_b; + }; + + union { + __IOM uint32_t GSPI_INTR_MASK; /*!< (@ 0x00000024) GSPI Interrupt Mask Register */ + + struct { + __IOM uint32_t GSPI_INTR_MASK : 1; /*!< [0..0] GSPI Interrupt mask bit */ + __IOM uint32_t FIFO_AEMPTY_RFIFO_MASK : 1; /*!< [1..1] NONE */ + __IOM uint32_t FIFO_AFULL_RFIFO_MASK : 1; /*!< [2..2] NONE */ + __IOM uint32_t FIFO_AEMPTY_WFIFO_MASK : 1; /*!< [3..3] NONE */ + __IOM uint32_t FIFO_AFULL_WFIFO_MASK : 1; /*!< [4..4] NONE */ + __IOM uint32_t FIFO_FULL_WFIFO_MASK : 1; /*!< [5..5] NONE */ + __IOM uint32_t FIFO_EMPTY_RFIFO_MASK : 1; /*!< [6..6] NONE */ + __IOM uint32_t RESERVED1 : 25; /*!< [31..7] reserved for future use */ + } GSPI_INTR_MASK_b; + }; + + union { + __IOM uint32_t GSPI_INTR_UNMASK; /*!< (@ 0x00000028) GSPI Interrupt Unmask + Register */ + + struct { + __IOM uint32_t GSPI_INTR_UNMASK : 1; /*!< [0..0] GSPI Interrupt unmask bit */ + __IOM uint32_t FIFO_AEMPTY_RFIFO_UNMASK : 1; /*!< [1..1] NONE */ + __IOM uint32_t FIFO_AFULL_RFIFO_UNMASK : 1; /*!< [2..2] NONE */ + __IOM uint32_t FIFO_AEMPTY_WFIFO_UNMASK : 1; /*!< [3..3] NONE */ + __IOM uint32_t FIFO_AFULL_WFIFO_UNMASK : 1; /*!< [4..4] NONE */ + __IOM uint32_t FIFO_FULL_WFIFO_UNMASK : 1; /*!< [5..5] NONE */ + __IOM uint32_t FIFO_EMPTY_RFIFO_UNMASK : 1; /*!< [6..6] NONE */ + __IOM uint32_t RESERVED1 : 25; /*!< [31..7] reserved for future use */ + } GSPI_INTR_UNMASK_b; + }; + + union { + __IM uint32_t GSPI_INTR_STS; /*!< (@ 0x0000002C) GSPI Interrupt Status Register */ + + struct { + __IM uint32_t GSPI_INTR_LVL : 1; /*!< [0..0] GSPI Interrupt status bit */ + __IM uint32_t FIFO_AEMPTY_RFIFO_LVL : 1; /*!< [1..1] NONE */ + __IM uint32_t FIFO_AFULL_RFIFO_LVL : 1; /*!< [2..2] NONE */ + __IM uint32_t FIFO_AEMPTY_WFIFO_LVL : 1; /*!< [3..3] NONE */ + __IM uint32_t FIFO_AFULL_WFIFO_LVL : 1; /*!< [4..4] NONE */ + __IM uint32_t FIFO_FULL_WFIFO_LVL : 1; /*!< [5..5] NONE */ + __IM uint32_t FIFO_EMPTY_RFIFO_LVL : 1; /*!< [6..6] NONE */ + __IM uint32_t RESERVED2 : 25; /*!< [31..7] reserved for future use */ + } GSPI_INTR_STS_b; + }; + + union { + __OM uint32_t GSPI_INTR_ACK; /*!< (@ 0x00000030) GSPI Interrupt Acknowledge + Register */ + + struct { + __OM uint32_t GSPI_INTR_ACK : 1; /*!< [0..0] GSPI Interrupt status bit */ + __OM uint32_t FIFO_AEMPTY_RFIFO_ACK : 1; /*!< [1..1] NONE */ + __OM uint32_t FIFO_AFULL_RFIFO_ACK : 1; /*!< [2..2] NONE */ + __OM uint32_t FIFO_AEMPTY_WFIFO_ACK : 1; /*!< [3..3] NONE */ + __OM uint32_t FIFO_AFULL_WFIFO_ACK : 1; /*!< [4..4] NONE */ + __OM uint32_t FIFO_FULL_WFIFO_ACK : 1; /*!< [5..5] NONE */ + __OM uint32_t FIFO_EMPTY_RFIFO_ACK : 1; /*!< [6..6] NONE */ + __OM uint32_t RESERVED2 : 25; /*!< [31..7] reserved1 */ + } GSPI_INTR_ACK_b; + }; + + union { + __IM uint32_t GSPI_STS_MC; /*!< (@ 0x00000034) GSPI State Machine Monitor + Register */ + + struct { + __IM uint32_t BUS_CTRL_PSTATE : 3; /*!< [2..0] Provides SPI bus controller + present state */ + __IM uint32_t SPI_RD_CNT : 13; /*!< [15..3] number of pending bytes to be + read by device */ + __IM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + } GSPI_STS_MC_b; + }; + + union { + __IOM uint32_t GSPI_CLK_DIV; /*!< (@ 0x00000038) GSPI Clock Division Factor + Register */ + + struct { + __IOM uint32_t GSPI_CLK_DIV_FACTOR : 8; /*!< [7..0] Provides GSPI clock division + factor to the clock divider, which takes + SOC clock as input clock and generates + required clock according to division + factor */ + __IM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + } GSPI_CLK_DIV_b; + }; + + union { + __IOM uint32_t GSPI_CONFIG3; /*!< (@ 0x0000003C) GSPI Configuration 3 Register */ + + struct { + __IOM uint32_t SPI_MANUAL_RD_LNTH_TO_BC : 15; /*!< [14..0] Bits are used to indicate + the total number of bytes + to read from flash during read + operation */ + __IOM uint32_t RESERVED1 : 17; /*!< [31..15] reserved1 */ + } GSPI_CONFIG3_b; + }; + __IM uint32_t RESERVED1[16]; + + union { + union { + __OM uint32_t GSPI_WRITE_FIFO[16]; /*!< (@ 0x00000080) GSPI fifo */ + + struct { + __OM uint32_t WRITE_FIFO : 32; /*!< [31..0] FIFO data is write to this + address space */ + } GSPI_WRITE_FIFO_b[16]; + }; + + union { + __IM uint32_t GSPI_READ_FIFO[16]; /*!< (@ 0x00000080) GSPI READ FIFO */ + + struct { + __IM uint32_t READ_FIFO : 32; /*!< [31..0] FIFO data is read from this + address space */ + } GSPI_READ_FIFO_b[16]; + }; + }; +} GSPI0_Type; /*!< Size = 192 (0xc0) */ + +/* =========================================================================================================================== + */ +/* ================ SSI0 + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief Synchronous Serial Interface(SSI) (SSI0) + */ + +typedef struct { /*!< (@ 0x44020000) SSI0 Structure */ + + union { + __IOM uint32_t CTRLR0; /*!< (@ 0x00000000) Control Register 0 */ + + struct { + __IOM uint32_t DFS : 4; /*!< [3..0] Select the data frame length (4-bit to + 16-bit serial data transfers) */ + __IOM uint32_t FRF : 2; /*!< [5..4] Frame Format, Selects which serial + protocol transfers the data */ + __IOM uint32_t SCPH : 1; /*!< [6..6] Serial Clock Phase. Valid when the + frame format (FRF) is set to Motorola SPI */ + __IOM uint32_t SCPOL : 1; /*!< [7..7] Serial Clock Polarity. Valid when the frame + format (FRF) is set to Motorola SPI */ + __IOM uint32_t TMOD : 2; /*!< [9..8] Selects the mode of transfer for + serial communication */ + __IOM uint32_t SLV_OE : 1; /*!< [10..10] DW_apb_ssi is configured as a + serial-slave device */ + __IOM uint32_t SRL : 1; /*!< [11..11] Shift Register Loop Used for testing + purposes only */ + __IOM uint32_t CFS : 4; /*!< [15..12] Control Frame Size Selects the length of the + control word for the Micro wire frame format */ + __IOM uint32_t DFS_32 : 5; /*!< [20..16] Selects the data frame length */ + __IOM uint32_t SPI_FRF : 2; /*!< [22..21] Selects data frame format for + transmitting or receiving data */ + __IOM uint32_t RESERVED1 : 9; /*!< [31..23] Reserved for future use */ + } CTRLR0_b; + }; + + union { + __IOM uint32_t CTRLR1; /*!< (@ 0x00000004) Control Register 1 */ + + struct { + __IOM uint32_t NDF : 16; /*!< [15..0] Number of Data Frames.When TMOD = 10 or TMOD = + 11, this register field sets the number of data frames to + be continuously received by the ssi_master */ + __IOM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use. */ + } CTRLR1_b; + }; + + union { + __IOM uint32_t SSIENR; /*!< (@ 0x00000008) SSI Enable Register */ + + struct { + __IOM uint32_t SSI_EN : 1; /*!< [0..0] Enables and disables all ssi operations */ + __IOM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + } SSIENR_b; + }; + + union { + __IOM uint32_t MWCR; /*!< (@ 0x0000000C) Micro wire Control Register */ + + struct { + __IOM uint32_t MWMOD : 1; /*!< [0..0] The Micro wire transfer is + sequential or non-sequential */ + __IOM uint32_t MDD : 1; /*!< [1..1] The direction of the data word when + the Micro wire serial protocol is used */ + __IOM uint32_t MHS : 1; /*!< [2..2] Microwire Handshaking. Used to enable + and disable the busy/ready handshaking + interface for the Microwire protocol */ + __IOM uint32_t RESERVED1 : 29; /*!< [31..3] Reserved for future use */ + } MWCR_b; + }; + + union { + __IOM uint32_t SER; /*!< (@ 0x00000010) SLAVE ENABLE REGISTER */ + + struct { + __IOM uint32_t SER : 4; /*!< [3..0] Each bit in this register corresponds to a slave + select line (ss_x_n) from the SSI master. */ + __IOM uint32_t RESERVED1 : 28; /*!< [31..4] Reserved for future use */ + } SER_b; + }; + + union { + __IOM uint32_t BAUDR; /*!< (@ 0x00000014) Baud Rate Select Register */ + + struct { + __IOM uint32_t SCKDV : 16; /*!< [15..0] SSI Clock Divider.The LSB for this + field is always set to 0 and is unaffected + by a write operation, which ensures + an even value is held in this + register */ + __IOM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } BAUDR_b; + }; + + union { + __IOM uint32_t TXFTLR; /*!< (@ 0x00000018) Transmit FIFO Threshold Level Register */ + + struct { + __IOM uint32_t TFT : 4; /*!< [3..0] Controls the level of entries (or below) at which + the transmit FIFO controller triggers an interrupt */ + __IOM uint32_t RESERVED1 : 28; /*!< [31..4] Reserved for future use */ + } TXFTLR_b; + }; + + union { + __IOM uint32_t RXFTLR; /*!< (@ 0x0000001C) Receive FIFO Threshold Level */ + + struct { + __IOM uint32_t RFT : 4; /*!< [3..0] Controls the level of entries (or above) at which + the receive FIFO controller triggers an interrupt */ + __IOM uint32_t RESERVED1 : 28; /*!< [31..4] Reserved for future use */ + } RXFTLR_b; + }; + + union { + __IM uint32_t TXFLR; /*!< (@ 0x00000020) Transmit FIFO Level Register */ + + struct { + __IM uint32_t TXTFL : 5; /*!< [4..0] Contains the number of valid data + entries in the transmit FIFO */ + __IM uint32_t RESERVED1 : 27; /*!< [31..5] Reserved for future use */ + } TXFLR_b; + }; + + union { + __IM uint32_t RXFLR; /*!< (@ 0x00000024) Receive FIFO Level Register */ + + struct { + __IM uint32_t RXTFL : 5; /*!< [4..0] Contains the number of valid data + entries in the receive FIFO */ + __IM uint32_t RESERVED1 : 27; /*!< [31..5] Reserved for future use */ + } RXFLR_b; + }; + + union { + __IM uint32_t SR; /*!< (@ 0x00000028) Status Register */ + + struct { + __IM uint32_t BUSY : 1; /*!< [0..0] indicates that a serial transfer is in + progress */ + __IM uint32_t TFNF : 1; /*!< [1..1] Set when the transmit FIFO contains one or more + empty locations and is cleared when the FIFO is full */ + __IM uint32_t TFE : 1; /*!< [2..2] When the transmit FIFO is completely + empty this bit is set */ + __IM uint32_t RFNE : 1; /*!< [3..3] Set when the receive FIFO contains one + or more entries and is cleared when the + receive FIFO is empty */ + __IM uint32_t RFF : 1; /*!< [4..4] When the receive FIFO is completely + full this bit is set */ + __IM uint32_t TXE : 1; /*!< [5..5] This bit is cleared when read */ + __IM uint32_t DCOL : 1; /*!< [6..6] This bit is set if the ss_in_n input + is asserted by another master, while the ssi + master is in the middle of the transfer */ + __IM uint32_t RESERVED1 : 25; /*!< [31..7] Reserved for future use */ + } SR_b; + }; + + union { + __IOM uint32_t IMR; /*!< (@ 0x0000002C) Interrupt Mask Register */ + + struct { + __IOM uint32_t TXEIM : 1; /*!< [0..0] Transmit FIFO Empty Interrupt Mask */ + __IOM uint32_t TXOIM : 1; /*!< [1..1] Transmit FIFO Overflow Interrupt Mask */ + __IOM uint32_t RXUIM : 1; /*!< [2..2] Receive FIFO Underflow Interrupt Mask */ + __IOM uint32_t RXOIM : 1; /*!< [3..3] Receive FIFO Overflow Interrupt Mask */ + __IOM uint32_t RXFIM : 1; /*!< [4..4] Receive FIFO Full Interrupt Mask */ + __IOM uint32_t MSTIM : 1; /*!< [5..5] Multi-Master Contention Interrupt Mask */ + __IM uint32_t RESERVED1 : 26; /*!< [31..6] Reserved for future use */ + } IMR_b; + }; + + union { + __IM uint32_t ISR; /*!< (@ 0x00000030) Interrupt Status Register */ + + struct { + __IM uint32_t TXEIS : 1; /*!< [0..0] Transmit FIFO Empty Interrupt Status */ + __IM uint32_t TXOIS : 1; /*!< [1..1] Transmit FIFO Overflow Interrupt Status */ + __IM uint32_t RXUIS : 1; /*!< [2..2] Receive FIFO Underflow Interrupt Status */ + __IM uint32_t RXOIS : 1; /*!< [3..3] Receive FIFO Overflow Interrupt Status */ + __IM uint32_t RXFIS : 1; /*!< [4..4] Receive FIFO Full Interrupt Status */ + __IM uint32_t MSTIS : 1; /*!< [5..5] Multi-Master Contention Interrupt Status */ + __IM uint32_t RESERVED1 : 26; /*!< [31..6] Reserved for future use */ + } ISR_b; + }; + + union { + __IM uint32_t RISR; /*!< (@ 0x00000034) Raw Interrupt Status Register */ + + struct { + __IM uint32_t TXEIR : 1; /*!< [0..0] Transmit FIFO Empty Raw Interrupt Status */ + __IM uint32_t TXOIR : 1; /*!< [1..1] Transmit FIFO Overflow Raw Interrupt + Status */ + __IM uint32_t RXUIR : 1; /*!< [2..2] Receive FIFO Underflow Raw Interrupt + Status */ + __IM uint32_t RXOIR : 1; /*!< [3..3] Receive FIFO Overflow Raw Interrupt Status */ + __IM uint32_t RXFIR : 1; /*!< [4..4] Receive FIFO Full Raw Interrupt Status */ + __IM uint32_t MSTIR : 1; /*!< [5..5] Multi-Master Contention Raw Interrupt + Status */ + __IM uint32_t RESERVED1 : 26; /*!< [31..6] Reserved for future use */ + } RISR_b; + }; + + union { + __IM uint32_t TXOICR; /*!< (@ 0x00000038) Transmit FIFO Overflow Interrupt + Clear Register */ + + struct { + __IM uint32_t TXOICR : 1; /*!< [0..0] Clear Transmit FIFO Overflow Interrupt This + register reflects the status of the interrupt */ + __IM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + } TXOICR_b; + }; + + union { + __IM uint32_t RXOICR; /*!< (@ 0x0000003C) Receive FIFO Overflow Interrupt + Clear Register */ + + struct { + __IM uint32_t RXOICR : 1; /*!< [0..0] This register reflects the status of + the interrupt A read from this register + clears the ssi_rxo_intr interrupt */ + __IM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + } RXOICR_b; + }; + + union { + __IM uint32_t RXUICR; /*!< (@ 0x00000040) Receive FIFO Underflow Interrupt + Clear Register */ + + struct { + __IM uint32_t RXUICR : 1; /*!< [0..0] This register reflects the status of + the interrupt A read from this register + clears the ssi_rxu_intr interrupt */ + __IM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + } RXUICR_b; + }; + + union { + __IM uint32_t MSTICR; /*!< (@ 0x00000044) Multi-Master Interrupt Clear Register */ + + struct { + __IM uint32_t MSTICR : 1; /*!< [0..0] This register reflects the status of + the interrupt A read from this register + clears the ssi_mst_intr interrupt */ + __IM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + } MSTICR_b; + }; + + union { + __IM uint32_t ICR; /*!< (@ 0x00000048) Interrupt Clear Register */ + + struct { + __IM uint32_t ICR : 1; /*!< [0..0] This register is set if any of the + interrupts below are active A read clears the + ssi_txo_intr, ssi_rxu_intr, ssi_rxo_intr, and + the ssi_mst_intr interrupts */ + __IM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + } ICR_b; + }; + + union { + __IOM uint32_t DMACR; /*!< (@ 0x0000004C) DMA Control Register */ + + struct { + __IOM uint32_t RDMAE : 1; /*!< [0..0] This bit enables/disables the + receive FIFO DMA channel */ + __IOM uint32_t TDMAE : 1; /*!< [1..1] This bit enables/disables the + transmit FIFO DMA channel */ + __IM uint32_t RESERVED1 : 30; /*!< [31..2] Reserved for future use */ + } DMACR_b; + }; + + union { + __IOM uint32_t DMATDLR; /*!< (@ 0x00000050) DMA Transmit Data Level */ + + struct { + __IOM uint32_t DMATDL : 4; /*!< [3..0] This bit field controls the level at which a + DMA request is made by the transmit logic */ + __IM uint32_t RESERVED1 : 28; /*!< [31..4] Reserved for future use */ + } DMATDLR_b; + }; + + union { + __IOM uint32_t DMARDLR; /*!< (@ 0x00000054) DMA Receive Data Level Register */ + + struct { + __IOM uint32_t DMARDL : 4; /*!< [3..0] This bit field controls the level at which a + DMA request is made by the receive logic */ + __IOM uint32_t RESERVED1 : 28; /*!< [31..4] Reserved for future use */ + } DMARDLR_b; + }; + + union { + __IM uint32_t IDR; /*!< (@ 0x00000058) Identification Register */ + + struct { + __IM uint32_t IDCODE : 32; /*!< [31..0] This register contains the + peripherals identification code */ + } IDR_b; + }; + + union { + __IM uint32_t SSI_COMP_VERSION; /*!< (@ 0x0000005C) coreKit version ID register */ + + struct { + __IM uint32_t SSI_COMP_VERSION : 32; /*!< [31..0] Contains the hex representation of + the Synopsys component version */ + } SSI_COMP_VERSION_b; + }; + + union { + __IOM uint32_t DR; /*!< (@ 0x00000060) Data Register */ + + struct { + __IOM uint32_t DR : 32; /*!< [31..0] When writing to this register must + right-justify the data */ + } DR_b; + }; + __IM uint32_t RESERVED[35]; + + union { + __IOM uint32_t RX_SAMPLE_DLY; /*!< (@ 0x000000F0) Rx Sample Delay Register */ + + struct { + __IOM uint32_t RSD : 8; /*!< [7..0] Receive Data (rxd) Sample Delay. This register is + used to delay the sample of the rxd input signal. */ + __IOM uint32_t RESERVED1 : 24; /*!< [31..8] Reserved for future use */ + } RX_SAMPLE_DLY_b; + }; + + union { + __IOM uint32_t SPI_CTRLR0; /*!< (@ 0x000000F4) SPI control Register */ + + struct { + __IOM uint32_t TRANS_TYPE : 2; /*!< [1..0] Address and instruction + transfer format */ + __IOM uint32_t ADDR_L : 4; /*!< [5..2] This bit defines length of address to be + transmitted, The transfer begins only after these many + bits are programmed into the FIFO */ + __IM uint32_t RESERVED1 : 2; /*!< [7..6] Reserved for future use */ + __IOM uint32_t INST_L : 2; /*!< [9..8] DUAL/QUAD length in bits */ + __IM uint32_t RESERVED2 : 1; /*!< [10..10] Reserved for future use */ + __IOM uint32_t WAIT_CYCLES : 4; /*!< [14..11] This bit defines the wait cycles in + dual/quad mode between control frames transmit and + data reception, Specified as number of SPI clock + cycles */ + __IM uint32_t RESERVED3 : 17; /*!< [31..15] Reserved for future use */ + } SPI_CTRLR0_b; + }; +} SSI0_Type; /*!< Size = 248 (0xf8) */ + +/* =========================================================================================================================== + */ +/* ================ SIO + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief SERIAL GENERAL PERPOSE INPUT/OUTPUT (SIO) + */ + +typedef struct { /*!< (@ 0x47000000) SIO Structure */ + + union { + __IOM uint32_t SIO_ENABLE_REG; /*!< (@ 0x00000000) ENABLE REGISTER */ + + struct { + __IOM uint32_t SIO_OPERATION_ENABLE : 16; /*!< [15..0] Contains the + Enables for all SIO */ + __IM uint32_t RESERVED3 : 16; /*!< [31..16] Reserved for future use */ + } SIO_ENABLE_REG_b; + }; + + union { + __IOM uint32_t SIO_PAUSE_REG; /*!< (@ 0x00000004) PAUSE REGISTER */ + + struct { + __IOM uint32_t SIO_POSITION_COUNTER_DISABLE : 16; /*!< [15..0] Contains + sio position counter + disable for all SIOs + */ + __IM uint32_t RESERVED3 : 16; /*!< [31..16] Reserved for future use */ + } SIO_PAUSE_REG_b; + }; + + union { + __IM uint32_t SIO_GPIO_IN_REG; /*!< (@ 0x00000008) GPIO Input Register */ + + struct { + __IM uint32_t IN_VALUE : 32; /*!< [31..0] GPIO input pin status */ + } SIO_GPIO_IN_REG_b; + }; + + union { + __IOM uint32_t SIO_GPIO_OUT_REG; /*!< (@ 0x0000000C) GPIO Output Register */ + + struct { + __IOM uint32_t OUT_VALUE : 32; /*!< [31..0] Value to be loaded on GPIO out pins */ + } SIO_GPIO_OUT_REG_b; + }; + + union { + __IOM uint32_t SIO_GPIO_OEN_REG; /*!< (@ 0x00000010) GPIO Output enable Register */ + + struct { + __IOM uint32_t OEN_VALUE : 32; /*!< [31..0] OEN for the GPIO pins */ + } SIO_GPIO_OEN_REG_b; + }; + + union { + __IOM uint32_t SIO_GPIO_INTR_EN_SET_REG; /*!< (@ 0x00000014) GPIO Interrupt + Enable Set Register */ + + struct { + __OM uint32_t INTR_ENABLE_SET : 16; /*!< [15..0] gpio interrupt enable set + register for all SIOs */ + __IM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } SIO_GPIO_INTR_EN_SET_REG_b; + }; + + union { + __OM uint32_t SIO_GPIO_INTR_EN_CLEAR_REG; /*!< (@ 0x00000018) GPIO Interrupt + Enable Clear Register */ + + struct { + __OM uint32_t INTR_ENABLE_CLEAR : 16; /*!< [15..0] gpio interrupt enable + Clear register for all SIOs */ + __OM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } SIO_GPIO_INTR_EN_CLEAR_REG_b; + }; + + union { + __IOM uint32_t SIO_GPIO_INTR_MASK_SET_REG; /*!< (@ 0x0000001C) GPIO Interrupt Enable + Clear Register */ + + struct { + __IOM uint32_t INTR_MASK_SET : 16; /*!< [15..0] Common gpio interrupt mask + set register for all SIOs */ + __IM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } SIO_GPIO_INTR_MASK_SET_REG_b; + }; + + union { + __OM uint32_t SIO_GPIO_INTR_MASK_CLEAR_REG; /*!< (@ 0x00000020) GPIO Interrupt Enable + Clear Register */ + + struct { + __OM uint32_t INTR_MASK_CLEAR : 16; /*!< [15..0] gpio interrupt mask clear + register for all SIOs */ + __OM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } SIO_GPIO_INTR_MASK_CLEAR_REG_b; + }; + + union { + __IOM uint32_t SIO_GPIO_INTR_STATUS_REG; /*!< (@ 0x00000024) GPIO Interrupt + Status Register */ + + struct { + __OM uint32_t INTR_MASK_SET : 16; /*!< [15..0] Common gpio interrupt + status register for all SIOs */ + __IM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } SIO_GPIO_INTR_STATUS_REG_b; + }; + + union { + __IM uint32_t SIO_SHIFT_COUNTER[16]; /*!< (@ 0x00000028) Shift counter register */ + + struct { + __IM uint32_t SHIFT_COUNTER : 14; /*!< [13..0] shift counter current value */ + __IM uint32_t RESERVED1 : 18; /*!< [31..14] Reserved for future use */ + } SIO_SHIFT_COUNTER_b[16]; + }; + + union { + __IOM uint32_t SIO_BUFFER_REG[16]; /*!< (@ 0x00000068) Buffer Register */ + + struct { + __IOM uint32_t DATA : 32; /*!< [31..0] Data to load into the shift register */ + } SIO_BUFFER_REG_b[16]; + }; + + union { + __IOM uint32_t SIO_SHIFT_COUNT_PRELOAD_REG[16]; /*!< (@ 0x000000A8) Shift counter + Reload Register */ + + struct { + __IOM uint32_t RELOAD_VALUE : 14; /*!< [13..0] division factor required to + generate shift clock */ + __IM uint32_t RESERVED1 : 1; /*!< [14..14] Reserved for future use */ + __IOM uint32_t REVERSE_LOAD : 1; /*!< [15..15] When set, the data on APB is loaded to + buffer is reverse order */ + __IM uint32_t RESERVED2 : 16; /*!< [31..16] Reserved for future use */ + } SIO_SHIFT_COUNT_PRELOAD_REG_b[16]; + }; + + union { + __IOM uint32_t SIO_DATA_POS_COUNT_REG[16]; /*!< (@ 0x000000E8) Data Position + Counter Register */ + + struct { + __IOM uint32_t RELOAD_VALUE : 8; /*!< [7..0] No. of shifts to happen before reloading + the shift register with data/ pausing the + operation */ + __IOM uint32_t POSITION_COUNTER : 8; /*!< [15..8] The position counter can + be loaded via AHB */ + __IM uint32_t RESERVED3 : 16; /*!< [31..16] Reserved for future use */ + } SIO_DATA_POS_COUNT_REG_b[16]; + }; + + union { + __IOM uint32_t SIO_CONFIG_REG[16]; /*!< (@ 0x00000128) Configuration Register */ + + struct { + __IOM uint32_t FULL_ENABLE : 1; /*!< [0..0] When set, fifo full indication would be + asserted when internal buffer is full */ + __IOM uint32_t EMPTY_ENABLE : 1; /*!< [1..1] When set, fifo full indication would be + asserted when internal buffer is empty */ + __IOM uint32_t EDGE_SEL : 1; /*!< [2..2] edge selection */ + __IOM uint32_t CLK_SEL : 1; /*!< [3..3] clock selection */ + __IOM uint32_t IGNORE_FIRST_SHIFT_CONDITION : 1; /*!< [4..4] data shift + condition */ + __IOM uint32_t FLOW_CONTROL_ENABLED : 1; /*!< [5..5] flow control */ + __IOM uint32_t PATTERN_MATCH_ENABLE : 1; /*!< [6..6] pattern match */ + __IOM uint32_t QUALIFIER_MODE : 1; /*!< [7..7] qualifier mode */ + __IOM uint32_t QUALIFY_CLOCK : 1; /*!< [8..8] qualify clock */ + __IOM uint32_t INVERT_CLOCK : 1; /*!< [9..9] invert clock */ + __IOM uint32_t PARALLEL_MODE : 2; /*!< [11..10] No. of bits to + shift/capture at valid clk edge */ + __IOM uint32_t PIN_DETECTION_MODE : 2; /*!< [13..12] Pin mode to be considered for + gpio interrupt */ + __IOM uint32_t SET_CLK_OUT : 1; /*!< [14..14] When high sets the sio clock_out port. + This is used only when sio is not enabled */ + __IOM uint32_t RESET_CLK_OUT : 1; /*!< [15..15] When high resets the sio + clock_out port. This is used only + when sio is not enabled */ + __IOM uint32_t LOAD_DATA_POS_CNTR_VIA_APB : 1; /*!< [16..16] When set, data position + counter can be loaded via APB */ + __IM uint32_t RESERVED1 : 15; /*!< [31..17] Reserved for future use */ + } SIO_CONFIG_REG_b[16]; + }; + + union { + __IOM uint32_t SIO_PATTERN_MATCH_MASK_REG_SLICE_0; /*!< (@ 0x00000168) Pattern Match + Mask Register 0 */ + + struct { + __IOM uint32_t MATCH_MASK_LOWER16_BITS : 32; /*!< [31..0] Enable for lower + 16 bits */ + } SIO_PATTERN_MATCH_MASK_REG_SLICE_0_b; + }; + + union { + __IOM uint32_t SIO_PATTERN_MATCH_MASK_REG_SLICE_1; /*!< (@ 0x0000016C) Pattern Match + Mask Register Slice 1 */ + + struct { + __IOM uint32_t MATCH_MASK_LOWER16_BITS : 32; /*!< [31..0] Enable for lower + 16 bits */ + } SIO_PATTERN_MATCH_MASK_REG_SLICE_1_b; + }; + + union { + __IOM uint32_t SIO_PATTERN_MATCH_MASK_REG_SLICE_2; /*!< (@ 0x00000170) Pattern Match + Mask Register Slice 2 */ + + struct { + __IOM uint32_t MATCH_MASK_LOWER16_BITS : 32; /*!< [31..0] Enable for lower + 16 bits */ + } SIO_PATTERN_MATCH_MASK_REG_SLICE_2_b; + }; + __IM uint32_t RESERVED[5]; + + union { + __IOM uint32_t SIO_PATTERN_MATCH_MASK_REG_SLICE_8; /*!< (@ 0x00000188) Pattern Match + Mask Register Slice 8 */ + + struct { + __IOM uint32_t MATCH_MASK_LOWER16_BITS : 32; /*!< [31..0] Enable for lower + 16 bits */ + } SIO_PATTERN_MATCH_MASK_REG_SLICE_8_b; + }; + + union { + __IOM uint32_t SIO_PATTERN_MATCH_MASK_REG_SLICE_9; /*!< (@ 0x0000018C) Pattern Match + Mask Register Slice 9 */ + + struct { + __IOM uint32_t MATCH_MASK_LOWER16_BITS : 32; /*!< [31..0] Enable for lower + 16 bits */ + } SIO_PATTERN_MATCH_MASK_REG_SLICE_9_b; + }; + + union { + __IOM uint32_t SIO_PATTERN_MATCH_MASK_REG_SLICE_10; /*!< (@ 0x00000190) Pattern Match + Mask Register Slice 10 */ + + struct { + __IOM uint32_t MATCH_MASK_LOWER16_BITS : 32; /*!< [31..0] Enable for lower + 16 bits */ + } SIO_PATTERN_MATCH_MASK_REG_SLICE_10_b; + }; + __IM uint32_t RESERVED1[5]; + + union { + __IOM uint32_t SIO_PATTERN_MATCH_REG_SLICE_0; /*!< (@ 0x000001A8) Pattern Match Mask + Register Slice 0 */ + + struct { + __IOM uint32_t PATTERN_MATCH_LOWER16_BITS : 32; /*!< [31..0] Lower 16-bits of pattern + to be detected */ + } SIO_PATTERN_MATCH_REG_SLICE_0_b; + }; + + union { + __IOM uint32_t SIO_PATTERN_MATCH_REG_SLICE_1; /*!< (@ 0x000001AC) Pattern Match Mask + Register Slice 1 */ + + struct { + __IOM uint32_t PATTERN_MATCH_LOWER16_BITS : 32; /*!< [31..0] Lower 16-bits of pattern + to be detected */ + } SIO_PATTERN_MATCH_REG_SLICE_1_b; + }; + + union { + __IOM uint32_t SIO_PATTERN_MATCH_REG_SLICE_2; /*!< (@ 0x000001B0) Pattern Match Mask + Register Slice 2 */ + + struct { + __IOM uint32_t PATTERN_MATCH_LOWER16_BITS : 32; /*!< [31..0] Lower 16-bits of pattern + to be detected */ + } SIO_PATTERN_MATCH_REG_SLICE_2_b; + }; + __IM uint32_t RESERVED2[5]; + + union { + __IOM uint32_t SIO_PATTERN_MATCH_REG_SLICE_8; /*!< (@ 0x000001C8) Pattern Match Mask + Register Slice 8 */ + + struct { + __IOM uint32_t PATTERN_MATCH_LOWER16_BITS : 32; /*!< [31..0] Lower 16 bits of pattern + to be detected */ + } SIO_PATTERN_MATCH_REG_SLICE_8_b; + }; + + union { + __IOM uint32_t SIO_PATTERN_MATCH_REG_SLICE_9; /*!< (@ 0x000001CC) Pattern Match Mask + Register Slice 9 */ + + struct { + __IOM uint32_t PATTERN_MATCH_LOWER16_BITS : 32; /*!< [31..0] Lower 16 bits of pattern + to be detected */ + } SIO_PATTERN_MATCH_REG_SLICE_9_b; + }; + + union { + __IOM uint32_t SIO_PATTERN_MATCH_REG_SLICE_10; /*!< (@ 0x000001D0) Pattern Match Mask + Register Slice 10 */ + + struct { + __IOM uint32_t PATTERN_MATCH_LOWER16_BITS : 32; /*!< [31..0] Lower 16 bits of pattern + to be detected */ + } SIO_PATTERN_MATCH_REG_SLICE_10_b; + }; + __IM uint32_t RESERVED3[7]; + + union { + __IOM uint32_t SIO_SHIFT_INTR_EN_SET_REG; /*!< (@ 0x000001F0) Shift Interrupt Enable + Set Register */ + + struct { + __IOM uint32_t INTR_ENABLE_SET : 16; /*!< [15..0] Common shift interrupt enable set + register for all SIOs */ + __IM uint32_t RESERVED3 : 16; /*!< [31..16] Reserved for future use */ + } SIO_SHIFT_INTR_EN_SET_REG_b; + }; + + union { + __OM uint32_t SIO_SHIFT_INTR_EN_CLEAR_REG; /*!< (@ 0x000001F4) Shift Interrupt Enable + Clear Register */ + + struct { + __OM uint32_t INRT_ENABLE_CLEAR : 16; /*!< [15..0] Common shift interrupt enable + Clear register for all SIOs */ + __OM uint32_t RESERVED3 : 16; /*!< [31..16] Reserved for future use */ + } SIO_SHIFT_INTR_EN_CLEAR_REG_b; + }; + + union { + __IOM uint32_t SIO_SHIFT_INTR_MASK_SET_REG; /*!< (@ 0x000001F8) Shift Interrupt Mask + Set Register */ + + struct { + __IOM uint32_t INTR_MASK_SET : 16; /*!< [15..0] Common shift interrupt enable Set + register for all SIOs */ + __IM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } SIO_SHIFT_INTR_MASK_SET_REG_b; + }; + + union { + __OM uint32_t SIO_SHIFT_INTR_MASK_CLEAR_REG; /*!< (@ 0x000001FC) Shift Interrupt Mask + Clear Register */ + + struct { + __OM uint32_t INTR_MASK_CLEAR : 16; /*!< [15..0] Common shift interrupt mask clear + register for all SIOs */ + __OM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } SIO_SHIFT_INTR_MASK_CLEAR_REG_b; + }; + + union { + __IOM uint32_t SIO_SHIFT_INTR_STATUS_REG; /*!< (@ 0x00000200) Shift + Interrupt Status Register */ + + struct { + __IOM uint32_t INTR_ENABLE_SET : 16; /*!< [15..0] Common shift interrupt mask clear + register for all SIOs */ + __IM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } SIO_SHIFT_INTR_STATUS_REG_b; + }; + + union { + __IOM uint32_t SIO_SWAP_INTR_EN_SET_REG; /*!< (@ 0x00000204) Swap Interrupt + Enable Set Register */ + + struct { + __IOM uint32_t INTR_ENABLE_SET : 16; /*!< [15..0] Swap interrupt enable + set register for all SIOs */ + __IM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } SIO_SWAP_INTR_EN_SET_REG_b; + }; + + union { + __OM uint32_t SIO_SWAP_INTR_EN_CLEAR_REG; /*!< (@ 0x00000208) Swap Interrupt + Enable Clear Register */ + + struct { + __OM uint32_t INTR_ENABLE_CLEAR : 16; /*!< [15..0] Swap interrupt enable + Clear register for all SIOs */ + __OM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } SIO_SWAP_INTR_EN_CLEAR_REG_b; + }; + + union { + __IOM uint32_t SIO_SWAP_INTR_MASK_SET_REG; /*!< (@ 0x0000020C) Swap Interrupt Mask Set + Register */ + + struct { + __IOM uint32_t INTR_MASK_SET : 16; /*!< [15..0] Common swap interrupt mask + set register for all SIOs */ + __IM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } SIO_SWAP_INTR_MASK_SET_REG_b; + }; + + union { + __OM uint32_t SIO_SWAP_INTR_MASK_CLEAR_REG; /*!< (@ 0x00000210) Swap Interrupt Mask + Clear Register */ + + struct { + __OM uint32_t INTR_MASK_CLEAR : 16; /*!< [15..0] Common swap interrupt mask Clear + register for all SIOs */ + __OM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } SIO_SWAP_INTR_MASK_CLEAR_REG_b; + }; + + union { + __IOM uint32_t SIO_SWAP_INTR_STATUS_REG; /*!< (@ 0x00000214) Swap Interrupt + Statusr Register */ + + struct { + __IOM uint32_t INTR_ENABLE_SET : 16; /*!< [15..0] Common swap interrupt + status register for all SIOs */ + __IM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } SIO_SWAP_INTR_STATUS_REG_b; + }; + + union { + __IOM uint32_t SIO_PATTERN_MATCH_INTR_EN_SET_REG; /*!< (@ 0x00000218) Pattern Match + Interrupt Enable Set Register */ + + struct { + __IOM uint32_t INTR_ENABLE_SET : 16; /*!< [15..0] Common pattern or buffer under run + interrupt enable set register for all SIOs. + Each bit corresponds to one SIO */ + __IM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } SIO_PATTERN_MATCH_INTR_EN_SET_REG_b; + }; + + union { + __OM uint32_t SIO_PATTERN_MATCH_INTR_EN_CLEAR_REG; /*!< (@ 0x0000021C) Pattern Match + Interrupt Enable Clear Register + */ + + struct { + __OM uint32_t INRT_ENABLE_CLEAR : 16; /*!< [15..0] Common pattern or buffer under + run interrupt enable + clear register for all SIOs */ + __OM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } SIO_PATTERN_MATCH_INTR_EN_CLEAR_REG_b; + }; + + union { + __IOM uint32_t SIO_PATTERN_MATCH_INTR_MASK_SET_REG; /*!< (@ 0x00000220) Pattern Match + Interrupt Mask Set Register */ + + struct { + __IOM uint32_t INTR_MASK_SET : 16; /*!< [15..0] Common pattern or buffer under run + interrupt mask set register for all SIOs */ + __IM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } SIO_PATTERN_MATCH_INTR_MASK_SET_REG_b; + }; + + union { + __OM uint32_t SIO_PATTERN_MATCH_INTR_MASK_CLEAR_REG; /*!< (@ 0x00000224) Pattern Match + Interrupt Mask Clear Register + */ + + struct { + __OM uint32_t INTR_MASK_CLEAR : 16; /*!< [15..0] Common pattern or buffer + under run interrupt mask clear + register for all SIOs */ + __OM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } SIO_PATTERN_MATCH_INTR_MASK_CLEAR_REG_b; + }; + + union { + __IOM uint32_t SIO_PATTERN_MATCH_INTR_STATUS_REG; /*!< (@ 0x00000228) Pattern Match + Interrupt Status Register */ + + struct { + __IOM uint32_t INTR_STATUS : 16; /*!< [15..0] Common pattern interrupt + status register for all SIOs */ + __IM uint32_t RESERVED3 : 16; /*!< [31..16] Reserved for future use */ + } SIO_PATTERN_MATCH_INTR_STATUS_REG_b; + }; + + union { + __IOM uint32_t SIO_BUFFER_INTR_STATUS_REG; /*!< (@ 0x0000022C) Buffer + Interrupt Status Register */ + + struct { + __IOM uint32_t INTR_STATUS : 16; /*!< [15..0] Common pattern interrupt + status register for all SIOs */ + __IM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } SIO_BUFFER_INTR_STATUS_REG_b; + }; + + union { + __IOM uint32_t SIO_OUT_MUX_REG[16]; /*!< (@ 0x00000230) Output muxing Register */ + + struct { + __IOM uint32_t DOUT_OEN_SEL : 3; /*!< [2..0] OEN select for GPIO pin 0 */ + __IOM uint32_t DOUT_SEL : 3; /*!< [5..3] Output mux select for GPIO pin 0 */ + __IM uint32_t RESERVED1 : 26; /*!< [31..6] Reserved for future use */ + } SIO_OUT_MUX_REG_b[16]; + }; + + union { + __IOM uint32_t SIO_INPUT_MUX_REG[16]; /*!< (@ 0x00000270) Input muxing Register */ + + struct { + __IOM uint32_t CLK_SEL : 3; /*!< [2..0] Input clock select for SIO 0 */ + __IOM uint32_t QUALIFIER_SELECT : 2; /*!< [4..3] qualifier select */ + __IOM uint32_t QUALIFIER_MODE : 2; /*!< [6..5] qualifier mode */ + __IOM uint32_t DIN_SEL : 3; /*!< [9..7] Data in mux select */ + __IM uint32_t RESERVED1 : 22; /*!< [31..10] Reserved for future use */ + } SIO_INPUT_MUX_REG_b[16]; + }; + + union { + __IOM uint32_t SIO_FIFO_WR_RD_REG; /*!< (@ 0x000002B0) FIFO READ/WRITE Register */ + + struct { + __IOM uint32_t FIFO_DATA_REGISTER : 32; /*!< [31..0] Writes and read into + this register will be written + into SIO buffer register */ + } SIO_FIFO_WR_RD_REG_b; + }; + + union { + __IOM uint32_t SIO_FIFO_WR_OFFSET_START_REG; /*!< (@ 0x000002B4) Points to start slice + number forming the FIFO */ + + struct { + __IOM uint32_t SIO_START_SLICE_NUMBER : 32; /*!< [31..0] Points to start slice number + forming the FIFO,On write, + FIFO_WR_OFFSET_CNT_REG will also be + reset to the value pointed written + into this register */ + } SIO_FIFO_WR_OFFSET_START_REG_b; + }; + + union { + __IOM uint32_t SIO_FIFO_WR_OFFSET_END_REG; /*!< (@ 0x000002B8) SIO last slice no + indication Register */ + + struct { + __IOM uint32_t SIO_END_SLICE_NUMBER : 32; /*!< [31..0] points to last + slice no forming fifo */ + } SIO_FIFO_WR_OFFSET_END_REG_b; + }; + + union { + __IOM uint32_t SIO_FIFO_WR_OFFSET_CNT_REG; /*!< (@ 0x000002BC) Points to current slice + number forming the FIFO */ + + struct { + __IOM uint32_t SIO_CURRENT_SLICE_NUMBER : 32; /*!< [31..0] Next FIFO operation will + happen to buffer in the slice + pointed by this register */ + } SIO_FIFO_WR_OFFSET_CNT_REG_b; + }; + + union { + __IOM uint32_t SIO_FIFO_RD_OFFSET_START_REG; /*!< (@ 0x000002C0) Points to start slice + number forming the FIFO */ + + struct { + __IOM uint32_t SIO_START_SLICE_NUMBER : 32; /*!< [31..0] Points to start slice number + forming the FIFO */ + } SIO_FIFO_RD_OFFSET_START_REG_b; + }; + + union { + __IOM uint32_t SIO_FIFO_RD_OFFSET_END_REG; /*!< (@ 0x000002C4) Points to last slice + number forming the FIFO */ + + struct { + __IOM uint32_t SIO_END_SLICE_NUMBER : 32; /*!< [31..0] Points to last slice number + forming the FIFO */ + } SIO_FIFO_RD_OFFSET_END_REG_b; + }; + + union { + __IOM uint32_t SIO_FIFO_RD_OFFSET_CNT_REG; /*!< (@ 0x000002C8) Points to start current + number forming the FIFO */ + + struct { + __IOM uint32_t SIO_CURRENT_SLICE_NUMBER : 32; /*!< [31..0] Next FIFO operation will + happen to buffer in the slice pointed + by this register This register has to + be set to zero before starting fresh + DMA operation */ + } SIO_FIFO_RD_OFFSET_CNT_REG_b; + }; +} SIO_Type; /*!< Size = 716 (0x2cc) */ + +/* =========================================================================================================================== + */ +/* ================ QSPI + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief The queued serial peripheral interface module provides a serial + * peripheral interface with queued transfer capability (QSPI) + */ + +typedef struct { /*!< (@ 0x12000000) QSPI Structure */ + + union { + __IOM uint32_t QSPI_CLK_CONFIG; /*!< (@ 0x00000000) QSPI Clock Configuration + Register */ + + struct { + __IOM uint32_t QSPI_AUTO_CSN_HIGH_CNT : 5; /*!< [4..0] Minimum SOC clock cycles, + during which QSPI auto csn should be + high between consecutive CSN assertions + */ + __IOM uint32_t QSPI_CLK_SYNC : 1; /*!< [5..5] If the clock frequency to + FLASH(spi_clk) and QSPI(hclk) controller is + same, this bit can be set to one to by-pass + the syncros results in time consumption */ + __IOM uint32_t RESERVED1 : 2; /*!< [7..6] reserved1 */ + __IOM uint32_t QSPI_CLK_EN : 1; /*!< [8..8] QSPI clock enable */ + __IOM uint32_t RESERVED2 : 3; /*!< [11..9] reserved2 */ + __IOM uint32_t SPI_CLK_DELAY_VAL : 6; /*!< [17..12] Delay value programmed to RX QSPI + DLL on read side. This delay is used to + delay the pad clock/DQS according to the + requirement */ + __IOM uint32_t OCTA_MODE_ENABLE_WITH_DQS : 1; /*!< [18..18] Enables SPI octa mode + along with DQS in DDR mode */ + __IOM uint32_t QSPI_DLL_ENABLE : 1; /*!< [19..19] Enable for RX QSPI DLL in read + mode.This is used in M4SS QSPI DDR pads to + delay the pad clock DQS input */ + __IOM uint32_t DDR_CLK_POLARITY_FROM_REG : 1; /*!< [20..20] Used this bit to sample + the data at posedge negedge after + interface FFs with internal qspi clock + 0-Sample at negedge 1-Sample at + posedge */ + __IOM uint32_t QSPI_DLL_ENABLE_TX : 1; /*!< [21..21] Enable for TX QSPI DLL in write + path. This is used in M4SS QSPI DDR pads to + delay the qspi clock output. 0–DLL is + disabled bypassed 1–DLL is enabled */ + __IOM uint32_t SPI_CLK_DELAY_VAL_TX : 6; /*!< [27..22] Delay value programmed to TX + QSPI DLL in write path. This delay is used + to delay the qspi clock output according + to the requirement */ + __IOM uint32_t QSPI_RX_DQS_DLL_CALIB : 1; /*!< [28..28] Delay value programmed to TX + QSPI DLL in write path. This delay is used + to delay the qspi clock output according + to the requirement */ + __IOM uint32_t RESERVED3 : 3; /*!< [31..29] reserved3 */ + } QSPI_CLK_CONFIG_b; + }; + + union { + __IOM uint32_t QSPI_BUS_MODE; /*!< (@ 0x00000004) QSPI Bus Mode Register */ + + struct { + __IOM uint32_t QSPI_9116_FEATURE_EN : 1; /*!< [0..0] 9115 specific features are + enabled with this enable */ + __IOM uint32_t QSPI_MAN_MODE_CONF_CSN0 : 2; /*!< [2..1] Configures the QSPI flash for + Single/Dual/Quad mode operation in + manual mode */ + __IOM uint32_t AUTO_MODE_RESET : 1; /*!< [3..3] QSPI Auto controller reset. This is + not a Self clearing bit */ + __IOM uint32_t QSPI_PREFETCH_EN : 1; /*!< [4..4] Pre-fetch of data from the model + which is connected to QSPI, automatically + with out reading on AHB and is supplied to + AHB, when address is matched with AHB read + transaction address */ + __IOM uint32_t QSPI_WRAP_EN : 1; /*!< [5..5] Model wrap is considered with this bit + and uses wrap instruction to read from FLASH */ + __IOM uint32_t QSPI_AUTO_MODE_FRM_REG : 1; /*!< [6..6] QSPI Mode of Operation */ + __IOM uint32_t PROGRAMMABLE_AUTO_CSN_BASE_ADDR_EN : 1; /*!< [7..7] Programmable auto + csn mode enable */ + __IOM uint32_t QSPI_D2_OEN_CSN0 : 1; /*!< [8..8] Direction Control for SPI_IO2 in + case of dual/single mode for chip select0 + csn0. It is used both in Auto and + Manual Mode */ + __IOM uint32_t QSPI_D3_OEN_CSN0 : 1; /*!< [9..9] Direction Control for SPI_IO3 in + case of dual/single mode for chip select0 + csn0. It is used both in Auto and Manual + Mode. */ + __IOM uint32_t QSPI_D2_DATA_CSN0 : 1; /*!< [10..10] Value of SPI_IO2 in case of + dual/single mode for chip select0 csn0. It + is used both in Auto and Manual Mode. */ + __IOM uint32_t QSPI_D3_DATA_CSN0 : 1; /*!< [11..11] Value of SPI_IO3 in case of + dual/single mode for chip select0 csn0. It + is used both in Auto and Manual Mode */ + __IOM uint32_t QSPI_D2_OEN_CSN1 : 1; /*!< [12..12] Direction Control for + SPI_IO2 in case of dual/single + mode for chip select1 csn1 */ + __IOM uint32_t QSPI_D3_OEN_CSN1 : 1; /*!< [13..13] Direction Control for + SPI_IO3 in case of dual/single + mode for chip select1 csn1 */ + __IOM uint32_t QSPI_D2_DATA_CSN1 : 1; /*!< [14..14] Direction Control for + SPI_IO3 in case of dual/single + mode for chip select1 csn1 */ + __IOM uint32_t QSPI_D3_DATA_CSN1 : 1; /*!< [15..15] Value of SPI_IO3 in case of + dual/single mode for chip select1 csn1 */ + __IOM uint32_t QSPI_DATA_SAMPLE_EDGE : 1; /*!< [16..16] Samples MISO data + on clock edges */ + __IOM uint32_t QSPI_CLK_MODE_CSN0 : 1; /*!< [17..17] QSPI Clock Mode */ + __IOM uint32_t QSPI_CLK_MODE_CSN1 : 1; /*!< [18..18] QSPI Clock Mode */ + __IOM uint32_t QSPI_CLK_MODE_CSN2 : 1; /*!< [19..19] QSPI Clock Mode */ + __IOM uint32_t QSPI_CLK_MODE_CSN3 : 1; /*!< [20..20] QSPI Clock Mode */ + __IOM uint32_t FLASH_AW_FIFO_LS_EN : 1; /*!< [21..21] Qspi flash auto write fifo + light sleep enable */ + __IOM uint32_t FLASH_SEC_AES_LS_EN : 1; /*!< [22..22] Qspi flash auto write fifo + light sleep enable */ + __IOM uint32_t RESERVED1 : 1; /*!< [23..23] reserved1 */ + __IOM uint32_t QSPI_D2_OEN_CSN2 : 1; /*!< [24..24] Direction Control for SPI_IO2 in + case of dual/single mode for chip select2 + csn2 */ + __IOM uint32_t QSPI_D3_OEN_CSN2 : 1; /*!< [25..25] Direction Control for SPI_IO3 in + case of dual/single mode for chip select2 + csn2 */ + __IOM uint32_t QSPI_D2_DATA_CSN2 : 1; /*!< [26..26] Value of SPI_IO2 in case of + dual/single mode for chip select2 csn2 */ + __IOM uint32_t QSPI_D3_DATA_CSN2 : 1; /*!< [27..27] Value of SPI_IO3 in case of + dual/single mode for chip select2 csn2 */ + __IOM uint32_t QSPI_D2_OEN_CSN3 : 1; /*!< [28..28] Direction Control for SPI_IO2 in + case of dual/single mode for chip select3 + csn3 */ + __IOM uint32_t QSPI_D3_OEN_CSN3 : 1; /*!< [29..29] Direction Control for SPI_IO3 in + case of dual/single mode for chip select3 + csn3 */ + __IOM uint32_t QSPI_D2_DATA_CSN3 : 1; /*!< [30..30] Value of SPI_IO2 in case of + dual/single mode for chip select3 csn3 */ + __IOM uint32_t QSPI_D3_DATA_CSN3 : 1; /*!< [31..31] Value of SPI_IO3 in case of + dual/single mode for chip select3 csn3 */ + } QSPI_BUS_MODE_b; + }; + + union { + __IOM uint32_t QSPI_AUTO_CONFIG_1; /*!< (@ 0x00000008) QSPI Auto Controller + Configuration 1 Register */ + + struct { + __IOM uint32_t QSPI_EXT_BYTE_MODE_CSN0 : 2; /*!< [1..0] Mode of operation of QSPI in + the extra byte phase */ + __IOM uint32_t QSPI_DUMMY_MODE_CSN0 : 2; /*!< [3..2] Mode of operation of + QSPI in instruction phase */ + __IOM uint32_t QSPI_ADDR_MODE_CSN0 : 2; /*!< [5..4] Mode of operation of + QSPI in instruction phase */ + __IOM uint32_t QSPI_CMD_MODE_CSN0 : 2; /*!< [7..6] Mode of operation of + QSPI in instruction phase */ + __IOM uint32_t QSPI_DATA_MODE_CSN0 : 2; /*!< [9..8] Mode of operation of + QSPI in DATA phase */ + __IOM uint32_t QSPI_EXTRA_BYTE_CSN0 : 8; /*!< [17..10] Value of the extra byte to be + transmitted, if the extra byte mode is + enabled */ + __IOM uint32_t QSPI_EXTRA_BYTE_EN_CSN0 : 2; /*!< [19..18] Value of the extra byte to + be transmitted, if the extra + byte mode is enabled */ + __IOM uint32_t QSPI_WRAP_SIZE : 2; /*!< [21..20] Qspi auto wrap size */ + __IOM uint32_t RESERVED1 : 1; /*!< [22..22] reserved1 */ + __IOM uint32_t QSPI_PG_JUMP_CSN0 : 1; /*!< [23..23] NONE */ + __IOM uint32_t QSPI_DUMMY_BYTES_INCR_CSN0 : 4; /*!< [27..24] Specifies the number of + dummy bytes 0 to 7 for the selected + SPI mode */ + __IOM uint32_t QSPI_DUMMY_BYTES_WRAP_CSN0 : 4; /*!< [31..28] Specifies the number of + dummy bytes 0 to 7 for the selected + SPI mode in case of wrap instruction + */ + } QSPI_AUTO_CONFIG_1_b; + }; + + union { + __IOM uint32_t QSPI_AUTO_CONFIG_2; /*!< (@ 0x0000000C) QSPI Auto Controller + Configuration 2 Register */ + + struct { + __IOM uint32_t QSPI_RD_DATA_SWAP_AUTO_CSN0 : 1; /*!< [0..0] NONE */ + __IOM uint32_t QSPI_ADR_SIZE_16_BIT_AUTO_MODE_CSN0 : 1; /*!< [1..1] NONE */ + __IOM uint32_t QSPI_CONTI_RD_EN_CSN0 : 1; /*!< [2..2] NONE */ + __IOM uint32_t DUMMY_BYTES_WR_RD_CSN0 : 1; /*!< [3..3] Dummy bytes to the model to be + read or to be write */ + __IOM uint32_t QSPI_DUMMY_BYTES_JMP_CSN : 4; /*!< [7..4] Dummy cycles to be selected + in case of JUMP */ + __IOM uint32_t QSPI_RD_INST_CSN0 : 8; /*!< [15..8] Read instruction to be used for + the selected SPI modes and when wrap */ + __IOM uint32_t QSPI_RD_WRAP_INT_CSN0 : 8; /*!< [23..16] Read instruction + to be used, when wrap mode is + supported by QSPI flash */ + __IOM uint32_t QSPI_PG_JUMP_INST_CSN0 : 8; /*!< [31..24] Read instruction to be used, + when Page jump is to be used */ + } QSPI_AUTO_CONFIG_2_b; + }; + + union { + __IOM uint32_t QSPI_MANUAL_CONFIG1; /*!< (@ 0x00000010) QSPI Manual + Configuration 1 Register */ + + struct { + __IOM uint32_t QSPI_MANUAL_CSN : 1; /*!< [0..0] SPI CS in manual mode */ + __IOM uint32_t QSPI_MANUAL_WR : 1; /*!< [1..1] Write enable for manual + mode when CS is low */ + __IOM uint32_t QSPI_MANUAL_RD : 1; /*!< [2..2] Read enable for manual mode + when CS is low */ + __IOM uint32_t QSPI_MANUAL_RD_CNT : 10; /*!< [12..3] Indicates total number of bytes + to be read along with 31:27 bits of this + register. Maximum length supported is + 32k bytes */ + __IOM uint32_t QSPI_MANUAL_CSN_SELECT : 2; /*!< [14..13] Indicates which + CSn is valid */ + __IOM uint32_t RESERVED1 : 4; /*!< [18..15] reserved1 */ + __IOM uint32_t QSPI_MANUAL_SIZE_FRM_REG : 2; /*!< [20..19] Manual reads and manual + writes follow this size */ + __IOM uint32_t TAKE_QSPI_MANUAL_WR_SIZE_FRM_REG : 1; /*!< [21..21] NONE */ + __IOM uint32_t QSPI_FULL_DUPLEX_EN : 1; /*!< [22..22] Full duplex mode enable. */ + __IOM uint32_t RESERVED2 : 2; /*!< [24..23] reserved2 */ + __IOM uint32_t HW_CTRLD_QSPI_MODE_CTRL : 1; /*!< [25..25] Hardware controlled qspi + mode in between AUTO and manual */ + __IOM uint32_t QSPI_MANUAL_QSPI_MODE : 1; /*!< [26..26] Internally the priority is + given to manual mode */ + __IOM uint32_t QSPI_MANUAL_RD_CNT1 : 5; /*!< [31..27] Indicates total + number of bytes or bits */ + } QSPI_MANUAL_CONFIG1_b; + }; + + union { + __IOM uint32_t QSPI_MANUAL_CONFIG2; /*!< (@ 0x00000014) QSPI Manual + Configuration 2 Register */ + + struct { + __IOM uint32_t QSPI_WR_DATA_SWAP_MNL_CSN0 : 1; /*!< [0..0] Swap the write data inside + the QSPI controller it-self */ + __IOM uint32_t QSPI_WR_DATA_SWAP_MNL_CSN1 : 1; /*!< [1..1] Swap the write data inside + the QSPI controller it-self. */ + __IOM uint32_t QSPI_WR_DATA_SWAP_MNL_CSN2 : 1; /*!< [2..2] Swap the write data inside + the QSPI controller itself. */ + __IOM uint32_t QSPI_WR_DATA_SWAP_MNL_CSN3 : 1; /*!< [3..3] Swap the write data inside + the QSPI controller itself. */ + __IOM uint32_t QSPI_RD_DATA_SWAP_MNL_CSN0 : 1; /*!< [4..4] Swap the read data inside + the QSPIcontroller it self. */ + __IOM uint32_t QSPI_RD_DATA_SWAP_MNL_CSN1 : 1; /*!< [5..5] Swap the read data inside + the QSPIcontroller itself. */ + __IOM uint32_t QSPI_RD_DATA_SWAP_MNL_CSN2 : 1; /*!< [6..6] Swap the read data inside + the QSPIcontroller it-self */ + __IOM uint32_t QSPI_RD_DATA_SWAP_MNL_CSN3 : 1; /*!< [7..7] Swap the read data inside + the QSPIcontroller itself */ + __IOM uint32_t QSPI_MAN_MODE_CONF_CSN1 : 2; /*!< [9..8] Configures the QSPI flash for + Single/Dual/Quad mode operation in + manual mode for chip select1 csn1 */ + __IOM uint32_t QSPI_MAN_MODE_CONF_CSN2 : 2; /*!< [11..10] Configures the QSPI flash + for Single or Dual or Quad mode + operation in manual mode for chip + select2 csn2 */ + __IOM uint32_t QSPI_MAN_MODE_CONF_CSN3 : 2; /*!< [13..12] Configures the QSPI flash + for Single or Dual or Quad mode + operation in manual mode for chip + select3 csn3 */ + __IOM uint32_t LOOP_BACK_EN : 1; /*!< [14..14] Internal loop back test mode. */ + __IOM uint32_t QSPI_MANUAL_DDR_PHASE : 1; /*!< [15..15] DDR operations can be + performed even in manual mode */ + __IOM uint32_t QSPI_DDR_CLK_EN : 1; /*!< [16..16] DDR operations can be + performed even in manual mode */ + __IOM uint32_t RESERVED1 : 1; /*!< [17..17] reserved1 */ + __IOM uint32_t QSPI_RD_DATA_SWAP_WORD_LVL_MNL_CSN0 : 1; /*!< [18..18] Set this bit + for read data byte + swapping within the word. + It is valid only for octa + ddr mode. It is valid + for csn0. */ + __IOM uint32_t QSPI_RD_DATA_SWAP_WORD_LVL_MNL_CSN1 : 1; /*!< [19..19] Set this bit + for read data byte + swapping within the word. + It is valid only for octa + ddr mode. It is valid + for csn1. */ + __IOM uint32_t QSPI_RD_DATA_SWAP_WORD_LVL_MNL_CSN2 : 1; /*!< [20..20] Set this bit + for read data byte + swapping within the word. + It is valid only for octa + ddr mode. It is valid + for csn2. */ + __IOM uint32_t QSPI_WR_DATA_SWAP_WORD_LVL_MNL_CSN0 : 1; /*!< [21..21] Set this bit + for write data byte + swapping within the word. + It is valid only for octa + ddr mode. It is valid + for csn0. */ + __IOM uint32_t QSPI_WR_DATA_SWAP_WORD_LVL_MNL_CSN1 : 1; /*!< [22..22] Set this bit + for write data byte + swapping within the word. + It is valid only for octa + ddr mode. It is valid + for csn1. */ + __IOM uint32_t QSPI_WR_DATA_SWAP_WORD_LVL_MNL_CSN2 : 1; /*!< [23..23] Set this bit + for write data byte + swapping within the word. + It is valid only for octa + ddr mode. It is valid + for csn2. */ + __IOM uint32_t QSPI_WR_DATA_SWAP_WORD_LVL_MNL_CSN3 : 1; /*!< [24..24] Set this bit + for write data byte + swapping within the word. + It is valid only for octa + ddr mode. It is valid + for csn3. */ + __IOM uint32_t QSPI_MANUAL_DUMMY_BYTE_OR_BIT_MODE : 1; /*!< [25..25] Indicates + qspi_manual_rd_cnt values + are dummy bytes + or bits in manual mode. + */ + __IOM uint32_t RESERVED2 : 6; /*!< [31..26] reserved2 */ + } QSPI_MANUAL_CONFIG2_b; + }; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t QSPI_FIFO_THRLD; /*!< (@ 0x0000001C) QSPI FIFO Threshold Register */ + + struct { + __IOM uint32_t FIFO_AEMPTY_THRLD : 4; /*!< [3..0] FIFO almost empty threshold */ + __IOM uint32_t FIFO_AFULL_THRLD : 4; /*!< [7..4] FIFO almost full threshold */ + __IOM uint32_t WFIFO_RESET : 1; /*!< [8..8] Write fifo reset */ + __IOM uint32_t RFIFO_RESET : 1; /*!< [9..9] Read fifo reset */ + __IOM uint32_t RESERVED1 : 22; /*!< [31..10] reserved1 */ + } QSPI_FIFO_THRLD_b; + }; + + union { + __IM uint32_t QSPI_MANUAL_STATUS; /*!< (@ 0x00000020) QSPI Manual Status Register */ + + struct { + __IM uint32_t QSPI_BUSY : 1; /*!< [0..0] State of Manual mode. */ + __IM uint32_t FIFO_FULL_WFIFO_S : 1; /*!< [1..1] Status indication for + Wfifo in manual mode */ + __IM uint32_t FIFO_AFULL_WFIFO_S : 1; /*!< [2..2] Status indication for + Wfifo in manual mode */ + __IM uint32_t FIFO_EMPTY_WFIFO : 1; /*!< [3..3] Status indication for + Wfifo in manual mode */ + __IM uint32_t FIFO_AEMPTY_WFIFO : 1; /*!< [4..4] Status indication for + Wfifo in manual mode */ + __IM uint32_t FIFO_FULL_RFIFO : 1; /*!< [5..5] Status indication for Rfifo + in manual mode */ + __IM uint32_t FIFO_AFULL_RFIFO : 1; /*!< [6..6] Status indication for + Rfifo in manual mode */ + __IM uint32_t FIFO_EMPTY_RFIFO_S : 1; /*!< [7..7] Status indication for + Rfifo in manual mode */ + __IM uint32_t FIFO_AEMPTY_RFIFO_S : 1; /*!< [8..8] Status indication for + Rfifo in manual mode */ + __IM uint32_t GSPI_MANUAL_RD_CNT : 1; /*!< [9..9] This is a result of 10 + bits ORing counter */ + __IM uint32_t AUTO_MODE_FSM_IDLE_SCLK : 1; /*!< [10..10] Auto mode idle signal to + track auto controller is busy + or idle. */ + __IM uint32_t QSPI_AUTO_MODE : 1; /*!< [11..11] QSPI controller status. */ + __IM uint32_t QSPI_AUTO_MODE_FRM_REG_SCLK : 1; /*!< [12..12] QSPI auto mode status. + Valid only when + HW_CTRLD_QSPI_MODE_CTRL is zero. + */ + __IM uint32_t HW_CTRLD_MODE_SCLK : 1; /*!< [13..13] QSPI mode status in + HW_CTRLD_MODE */ + __IM uint32_t HW_CTRLD_MODE_CTRL_SCLK : 1; /*!< [14..14] HW_CTRLD_MODE status */ + __IM uint32_t AW_CTRL_BUSY : 1; /*!< [15..15] Auto write busy indication. */ + __IM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + } QSPI_MANUAL_STATUS_b; + }; + + union { + __IOM uint32_t QSPI_INTR_MASK; /*!< (@ 0x00000024) QSPI Interrupt Mask Register */ + + struct { + __IOM uint32_t QSPI_INTR_MASK : 1; /*!< [0..0] Interrupt Status bit */ + __IOM uint32_t FIFO_AEMPTY_RFIFO_MASK : 1; /*!< [1..1] NONE */ + __IOM uint32_t FIFO_AFULL_RFIFO_MASK : 1; /*!< [2..2] NONE */ + __IOM uint32_t FIFO_AEMPTY_WFIFO_MASK : 1; /*!< [3..3] NONE */ + __IOM uint32_t FIFO_AFULL_WFIFO_MASK : 1; /*!< [4..4] NONE */ + __IOM uint32_t FIFO_FULL_WFIFO_MASK : 1; /*!< [5..5] NONE */ + __IOM uint32_t FIFO_EMPTY_RFIFO_MASK : 1; /*!< [6..6] NONE */ + __IOM uint32_t AHB_AUTO_WRITE_INTR_MASK : 1; /*!< [7..7] Rising interrupt for any + auto write operation on AHB + bus. This bit is a mask for this + interrupt */ + __IOM uint32_t QSPI_AUTO_BASE_ADDR_ERR_INTR_MASK : 1; /*!< [8..8] Rising interrupt + when no csn is selected + using programmable + auto base address. This + bit is a mask for this + interrupt. */ + __IOM uint32_t M4QSPI_MANUAL_BLOCKED_INTR_MASK : 1; /*!< [9..9] Rising interrupt when + M4 QSPI tries to do manual + mode transactions in Common + flash mode (3). This bit is a + mask for this interrupt. */ + __IOM uint32_t M4_AUTO_READ_OUT_range_intr_mask : 1; /*!< [10..10] Rising interrupt + when M4 QSPI tries to read TA + locations in Common flash + mode (3). This bit is a mask + for this interrupt. */ + __IOM uint32_t RESERVED1 : 21; /*!< [31..11] reserved1 */ + } QSPI_INTR_MASK_b; + }; + + union { + __IOM uint32_t QSPI_INTR_UNMASK; /*!< (@ 0x00000028) QSPI Interrupt Unmask + Register */ + + struct { + __IOM uint32_t QSPI_INTR_UNMASK : 1; /*!< [0..0] Interrupt Status bit */ + __IOM uint32_t FIFO_AEMPTY_RFIFO_UN : 1; /*!< [1..1] NONE */ + __IOM uint32_t FIFO_AFULL_RFIFO_UNMASK : 1; /*!< [2..2] NONE */ + __IOM uint32_t FIFO_AEMPTY_WFIFO_UNMASK : 1; /*!< [3..3] NONE */ + __IOM uint32_t FIFO_AFULL_WFIFO_UNMASK : 1; /*!< [4..4] NONE */ + __IOM uint32_t FIFO_FULL_WFIFO_UNMASK : 1; /*!< [5..5] NONE */ + __IOM uint32_t FIFO_EMPTY_RFIFO_UNMASK : 1; /*!< [6..6] NONE */ + __IOM uint32_t AHB_AUTO_WRITE_INTR_UNMASK : 1; /*!< [7..7] Rising interrupt for any + auto write operation on AHB + bus. This bit is a unmask for this + interrupt. */ + __IOM uint32_t QSPI_AUTO_BASE_ADDR_ERR_INTR_UNMASK : 1; /*!< [8..8] Rising interrupt + when M4 QSPI tries to do + manual mode transactions + in Common flash mode (3). + This bit is a unmask for + this interrupt. */ + __IOM uint32_t M4QSPI_MANUAL_BLOCKED_INTR_UNMASK : 1; /*!< [9..9] Rising interrupt + when M4 QSPI tries to do + manual mode transactions in + Common flash mode (3). This + bit is a unmask for this + interrupt. */ + __IOM uint32_t M4_AUTO_READ_OUT_RANGE_INTR_UNMASK : 1; /*!< [10..10] Rising interrupt + when M4 QSPI tries to read + TA locations in Common + flash mode (3). This bit + is a unmask for this + interrupt. */ + __IOM uint32_t RESERVED1 : 21; /*!< [31..11] reserved1 */ + } QSPI_INTR_UNMASK_b; + }; + + union { + __IM uint32_t QSPI_INTR_STS; /*!< (@ 0x0000002C) QSPI Interrupt Status Register */ + + struct { + __IM uint32_t QSPI_INTR_LVL : 1; /*!< [0..0] Interrupt Status bit */ + __IM uint32_t FIFO_AEMPTY_RFIFO_LVL : 1; /*!< [1..1] NONE */ + __IM uint32_t FIFO_AFULL_RFIFO_LVL : 1; /*!< [2..2] NONE */ + __IM uint32_t FIFO_AEMPTY_WFIFO_LVL : 1; /*!< [3..3] NONE */ + __IM uint32_t FIFO_AFULL_WFIFO_LVL : 1; /*!< [4..4] NONE */ + __IM uint32_t FIFO_FULL_WFIFO_LVL : 1; /*!< [5..5] NONE */ + __IM uint32_t FIFO_EMPTY_RFIFO_LVL : 1; /*!< [6..6] NONE */ + __IM uint32_t AHB_AUTO_WRITE_INTR_LEV : 1; /*!< [7..7] rising interrupt for any auto + write operation on AHB bus. */ + __IM uint32_t QSPI_AUTO_BASE_ADDR_ERR_INTR_LVL : 1; /*!< [8..8] Rising interrupt + when no csn is selected using + programmable auto base + address. */ + __IM uint32_t M4QSPI_MANUAL_BLOCKED_LVL : 1; /*!< [9..9] Rising interrupt when M4 + QSPI tries to do manual mode + transactions in Common flash mode + (3). */ + __IM uint32_t M4_AUTO_READ_OUT_RANGE_LVL : 1; /*!< [10..10] Rising interrupt when M4 + QSPI tries to read TA locations + in Common flash mode (3). + */ + __IM uint32_t RESERVED1 : 21; /*!< [31..11] reserved1 */ + } QSPI_INTR_STS_b; + }; + + union { + __IOM uint32_t QSPI_INTR_ACK; /*!< (@ 0x00000030) QSPI Interrupt Acknowledge + Register */ + + struct { + __OM uint32_t QSPI_INTR_ACK : 1; /*!< [0..0] Interrupt Status bit */ + __OM uint32_t FIFO_AEMPTY_RFIFO_ACK : 1; /*!< [1..1] NONE */ + __OM uint32_t FIFO_AFULL_RFIFO_ACK : 1; /*!< [2..2] NONE */ + __OM uint32_t FIFO_AEMPTY_WFIFO_ACK : 1; /*!< [3..3] NONE */ + __OM uint32_t FIFO_AFULL_WFIFO_ACK : 1; /*!< [4..4] NONE */ + __OM uint32_t FIFO_FULL_WFIFO_ACK : 1; /*!< [5..5] NONE */ + __OM uint32_t FIFO_EMPTY_RFIFO_ACK : 1; /*!< [6..6] NONE */ + __OM uint32_t AHB_AUTO_WRITE_INTR_ACK : 1; /*!< [7..7] Rising interrupt for any auto + write operation on AHB bus. This bit + is an ack for this interrupt. */ + __OM uint32_t QSPI_AUTO_BASE_ADDR_ERR_INTR_ACK : 1; /*!< [8..8] Rising interrupt + when no csn is selected using + programmable auto base + address. This bit is an ack + for this interrupt. */ + __IOM uint32_t M4QSPI_MANUAL_BLOCKED_INTR_ACK : 1; /*!< [9..9] Rising interrupt when + M4 QSPI tries to do manual mode + transactions in Common + flash mode (3). This bit is an + ack for this interrupt. + */ + __IOM uint32_t M4_AUTO_READ_OUT_RANGE_INTR_ACK : 1; /*!< [10..10] Rising interrupt + when M4 QSPI tries to read TA + locations + in Common flash mode (3). + This bit is an ack for this + interrupt. */ + __OM uint32_t RESERVED1 : 21; /*!< [31..11] reserved1 */ + } QSPI_INTR_ACK_b; + }; + + union { + __IM uint32_t QSPI_STS_MC; /*!< (@ 0x00000034) QSPI State Machine Monitor + Register */ + + struct { + __IM uint32_t BUS_CTRL_PSTATE : 4; /*!< [3..0] Bus controller present state */ + __IM uint32_t AUTO_CTRL_PSTATE : 3; /*!< [6..4] Auto controller present state */ + __IM uint32_t QSPI_MASTER_PSTATE : 3; /*!< [9..7] Qspi master present state */ + __IM uint32_t QSPI_MANUAL_RD_CNT : 15; /*!< [24..10] Qspi manual read + counter value */ + __IM uint32_t RESERVED1 : 7; /*!< [31..25] reserved1 */ + } QSPI_STS_MC_b; + }; + + union { + __IOM uint32_t QSPI_AUTO_CONFIG_1_CSN1; /*!< (@ 0x00000038) QSPI Auto Controller + Configuration 1 CSN1 Register */ + + struct { + __IOM uint32_t QSPI_EXT_BYTE_MODE_CSN1 : 2; /*!< [1..0] Mode of operation of QSPI in + instruction phase. */ + __IOM uint32_t QSPI_DUMMY_MODE_CSN1 : 2; /*!< [3..2] Mode of operation of + QSPI in instruction phase */ + __IOM uint32_t QSPI_ADDR_MODE_CSN1 : 2; /*!< [5..4] Mode of operation of + QSPI in instruction phase. */ + __IOM uint32_t QSPI_CMD_MODE_CSN1 : 2; /*!< [7..6] Mode of operation of + QSPI in instruction phase. */ + __IOM uint32_t QSPI_DATA_MODE_CSN1 : 2; /*!< [9..8] Mode of operation of + QSPI in DATA phase. */ + __IM uint32_t QSPI_EXTRA_BYTE_CSN1 : 8; /*!< [17..10] Value of the extra byte to be + transmitted, if the extra byte mode is + enabled. */ + __IOM uint32_t QSPI_EXTRA_BYTE_EN_CSN1 : 2; /*!< [19..18] Mode of operation of QSPI + in DATA phase. */ + __IOM uint32_t QSPI_WRAP_SIZE : 2; /*!< [21..20] Qspi auto wrap size */ + __IOM uint32_t RESERVED1 : 1; /*!< [22..22] reserved1 */ + __OM uint32_t QSPI_PG_JUMP_CSN1 : 1; /*!< [23..23] NONE */ + __IM uint32_t QSPI_DUMMY_BYTES_INCR_CSN1 : 4; /*!< [27..24] Specifies the number of + dummy bytes 0 to 7 for the selected + SPI mode. */ + __IM uint32_t QSPI_DUMMY_BYTES_WRAP_CSN1 : 4; /*!< [31..28] Specifies the number of + dummy bytes 0 to 7 for the selected + SPI mode in case of wrap instruction. + */ + } QSPI_AUTO_CONFIG_1_CSN1_b; + }; + + union { + __IOM uint32_t QSPI_AUTO_CONFIG_2_CSN1_REG; /*!< (@ 0x0000003C) QSPI Auto Controller + Configuration 2 CSN1 Register */ + + struct { + __IOM uint32_t QSPI_RD_SWAP_AUTO_CSN1 : 1; /*!< [0..0] Swap the read data from the + flash in byte order for chip select1 + csn1 in auto mode. */ + __IOM uint32_t QSPI_ADR_SIZE_16BIT_AUTO_MODE_CSN1 : 1; /*!< [1..1] NONE */ + __IOM uint32_t QSPI_CONTI_RD_EN_CSN1 : 1; /*!< [2..2] Continuous read + enable bit. */ + __IOM uint32_t DUMMY_BYTES_WR_RD : 1; /*!< [3..3] Dummy bytes to the model + to be read or to be write. */ + __IOM uint32_t QSPI_DUMMY_BYTES_JMP_CSN1 : 4; /*!< [7..4] Dummy cycles to be selected + in case of JUMP */ + __IOM uint32_t QSPI_RD_INST_CSN1 : 8; /*!< [15..8] Read instruction to be + used for the selected SPI modes + and when wrap is not needed or + supported */ + __IOM uint32_t QSPI_RD_WRAP_INST_CSN1 : 8; /*!< [23..16] Read instruction to be used + for the selected SPI modes and when + wrap is not needed or supported */ + __IOM uint32_t QSPI_PG_JMP_INST_CSN1 : 8; /*!< [31..24] Read instruction to be used, + when Page jump is to be used. */ + } QSPI_AUTO_CONFIG_2_CSN1_REG_b; + }; + __IOM uint32_t QSPI_MANUAL_RDWR_FIFO[16]; /*!< (@ 0x00000040) QSPI FIFOs */ + + union { + __IOM uint32_t QSPI_MANUAL_WRITE_DATA2; /*!< (@ 0x00000080) QSPI Manual + Write Data 2 Register */ + + struct { + __IOM uint32_t QSPI_MANUAL_WRITE_DATA2 : 5; /*!< [4..0] Number of bits to be written + in write mode */ + __IOM uint32_t RESERVED1 : 2; /*!< [6..5] reserved1 */ + __IOM uint32_t USE_PREV_LENGTH : 1; /*!< [7..7] Use previous length. */ + __IOM uint32_t QSPI_CLK_ENABLE_HCLK : 1; /*!< [8..8] reserved2 */ + __IOM uint32_t RESERVED2 : 23; /*!< [31..9] reserved2 */ + } QSPI_MANUAL_WRITE_DATA2_b; + }; + __IM uint32_t RESERVED1[3]; + + union { + __IOM uint32_t QSPI_AUTO_CONFIG_3_CSN0_REG; /*!< (@ 0x00000090) QSPI Auto Controller + Configuration 3 CSN0 Register */ + + struct { + __IOM uint32_t QSPI_DUMMY_BYTE_OR_BIT_CSN0 : 1; /*!< [0..0] Indicates all above + mention values are dummy bytes or + bits in auto mode. */ + __IOM uint32_t QSPI_DUMMY_BYTES_INCR_CSN0 : 4; /*!< [4..1] Specifies the number of + dummy bytes for the selected + SPI mode. It contains MS nibble for + byte. */ + __IOM uint32_t QSPI_DUMMY_BYTES_WRAP_CSN0 : 4; /*!< [8..5] Specifies the number of + dummy bytes for the selected SPI mode + in case of wrap instruction. It + contains MS nibble for byte. */ + __IOM uint32_t RESERVED1 : 3; /*!< [11..9] reserved1 */ + __IOM uint32_t QSPI_DDR_CMD_MODE_CSN0 : 1; /*!< [12..12] DDR Command mode */ + __IOM uint32_t QSPI_DDR_ADDR_MODE_CSN0 : 1; /*!< [13..13] DDR Address mode */ + __IOM uint32_t QSPI_DDR_DUMMY_MODE_CSN0 : 1; /*!< [14..14] DDR Address mode */ + __IOM uint32_t QSPI_DDR_EXTRA_MODE_CSN0 : 1; /*!< [15..15] DDR Address mode */ + __IOM uint32_t QSPI_DDR_DATA_MODE_CSN0 : 1; /*!< [16..16] DDR Address mode */ + __IOM uint32_t QSPI_AUTO_DDR_CMD_MODE_CSN0 : 1; /*!< [17..17] DDR data mode. */ + __IOM uint32_t QSPI_CMD_SIZE_16BIT_CSN0 : 1; /*!< [18..18] Enable for 16 read cmd + size for csn0. */ + __IOM uint32_t QSPI_ADR_SIZE_32BIT_AUTO_MODE : 1; /*!< [19..19] 32 bit addressing + support enable. */ + __IOM uint32_t QSPI_RD_DATA_SWAP_WORD_LVL_AUTO_CSN0 : 1; /*!< [20..20] Rd data swap + at word level in auto + mode for csn0. It is + valid for octa mode. */ + __IOM uint32_t RESERVED3 : 3; /*!< [23..21] reserved3 */ + __IOM uint32_t QSPI_RD_INST_CSN0_MSB : 8; /*!< [31..24] Read instruction MS byte to + be used the selected SPI + modes and when wrap is not needed or + supported. */ + } QSPI_AUTO_CONFIG_3_CSN0_REG_b; + }; + + union { + __IOM uint32_t QSPI_AUTO_CONFIG_3_CSN1_REG; /*!< (@ 0x00000094) QSPI Auto Controller + Configuration 3 CSN1 Register */ + + struct { + __IOM uint32_t QSPI_DUMMY_BYTE_OR_BIT_CSN1 : 1; /*!< [0..0] Indicates all above + mention values are dummy bytes or + bits in auto mode. */ + __IOM uint32_t QSPI_DUMMY_BYTES_INCR_CSN1 : 4; /*!< [4..1] Specifies the number of + dummy bytes for the selected + SPI mode. It contains MS nibble for + byte. */ + __IOM uint32_t QSPI_DUMMY_BYTES_WRAP_CSN1 : 4; /*!< [8..5] Specifies the number of + dummy bytes for the selected SPI mode + in case of wrap instruction. It + contains MS nibble for byte. */ + __IOM uint32_t RESERVED1 : 3; /*!< [11..9] reserved1 */ + __IOM uint32_t QSPI_DDR_CMD_MODE_CSN1 : 1; /*!< [12..12] DDR Command mode */ + __IOM uint32_t QSPI_DDR_ADDR_MODE_CSN1 : 1; /*!< [13..13] DDR Address mode */ + __IOM uint32_t QSPI_DDR_DUMMY_MODE_CSN1 : 1; /*!< [14..14] DDR Address mode */ + __IOM uint32_t QSPI_DDR_EXTRA_MODE_CSN1 : 1; /*!< [15..15] DDR Address mode */ + __IOM uint32_t QSPI_DDR_DATA_MODE_CSN1 : 1; /*!< [16..16] DDR Address mode */ + __IOM uint32_t QSPI_AUTO_DDR_CMD_MODE_CSN1 : 1; /*!< [17..17] DDR data mode. */ + __IOM uint32_t QSPI_CMD_SIZE_16BIT_CSN1 : 1; /*!< [18..18] Enable for 16 read cmd + size for csn1. */ + __IOM uint32_t RESERVED3 : 1; /*!< [19..19] RESERVED3 */ + __IOM uint32_t QSPI_RD_DATA_SWAP_WORD_LVL_AUTO_CSN1 : 1; /*!< [20..20] Rd data swap + at word level in auto + mode for csn1. It is + valid for octa mode. */ + __IOM uint32_t RESERVED4 : 3; /*!< [23..21] reserved4 */ + __IOM uint32_t QSPI_RD_INST_CSN1_MSB : 8; /*!< [31..24] Read instruction MS byte to + be used the selected SPI + modes and when wrap is not needed or + supported. */ + } QSPI_AUTO_CONFIG_3_CSN1_REG_b; + }; + __IM uint32_t RESERVED2[2]; + + union { + __IOM uint32_t QSPI_AUTO_BASE_ADDR_CSN0; /*!< (@ 0x000000A0) none */ + + struct { + __IOM uint32_t QSPI_AUTO_BASE_ADDR_CSN0 : 32; /*!< [31..0] Holds the 32 bit base + address for select chip select0 in + programmable auto csn mode. It is + valid only programmable + auto csn mode is enabled. */ + } QSPI_AUTO_BASE_ADDR_CSN0_b; + }; + + union { + __IOM uint32_t QSPI_AUTO_BASE_ADDR_CSN1; /*!< (@ 0x000000A4) none */ + + struct { + __IOM uint32_t QSPI_AUTO_BASE_ADDR_CSN1 : 32; /*!< [31..0] Holds the 32 bit base + address for select chip select1 in + programmable auto csn mode. It is + valid only programmable + auto csn mode is enabled. */ + } QSPI_AUTO_BASE_ADDR_CSN1_b; + }; + __IM uint32_t RESERVED3[2]; + + union { + __IOM uint32_t OCTASPI_BUS_CONTROLLER; /*!< (@ 0x000000B0) none */ + + struct { + __IOM uint32_t QSPI_D7TOD4_DATA_CSN0 : 4; /*!< [3..0] Value of SPI_IO7,6,5 and 4 in + case of quad/dual/single mode for chip + select1 (cs_n0). It is used both in Auto + and Manual Mode. */ + __IOM uint32_t QSPI_D7TOD4_OEN_CSN0 : 4; /*!< [7..4] Direction Control for SPI_IO + 7,6,5 and 4 in case of quad/dual/single + mode for chip select0 + (cs_n0). It is used both in Auto and + Manual Mode. */ + __IOM uint32_t QSPI_D7TOD4_DATA_CSN1 : 4; /*!< [11..8] Value of SPI_IO7,6,5 and 4 in + case of quad/dual/single mode for chip + select1 (cs_n1). It is used both in + Auto and Manual Mode. */ + __IOM uint32_t QSPI_D7TOD4_OEN_CSN1 : 4; /*!< [15..12] Direction Control for SPI_IO + 7,6,5 and 4 in case of quad/dual/single + mode for chip select1 (cs_n1). It is + used both in Auto and Manual Mode. */ + __IOM uint32_t QSPI_D7TOD4_DATA_CSN2 : 4; /*!< [19..16] Value of SPI_IO7,6,5 and 4 in + case of quad/dual/single mode for chip + select2 (cs_n2). It is used both in + Auto and Manual Mode. */ + __IOM uint32_t QSPI_D7TOD4_OEN_CSN2 : 4; /*!< [23..20] Direction Control for SPI_IO + 7,6,5 and 4 in case of quad/dual/single + mode for chip select2 (cs_n2). It is + used both in Auto and Manual Mode. */ + __IOM uint32_t QSPI_D7TOD4_DATA_CSN3 : 4; /*!< [27..24] Value of SPI_IO7,6,5 and 4 in + case of quad/dual/single mode for chip + select3 (cs_n3). It is used both in Auto + and Manual Mode. */ + __IOM uint32_t QSPI_D7TOD4_OEN_CSN3 : 4; /*!< [31..28] Direction Control for SPI_IO + 7,6,5 and 4 in case of quad/dual/single + mode for chip select3 (cs_n3). It is + used both in Auto and Manual Mode. */ + } OCTASPI_BUS_CONTROLLER_b; + }; + + union { + __IOM uint32_t QSPI_AUTO_BASE_ADDR_UNMASK_CSN0; /*!< (@ 0x000000B4) none */ + + struct { + __IOM uint32_t QSPI_AUTO_BASE_ADDR_UNMASK_CSN0 : 32; /*!< [31..0] Holds the 32 bit + base address unmask value for + select chip select0 in + programmable auto csn mode. + It is valid + only programmable auto + csn mode is enabled. */ + } QSPI_AUTO_BASE_ADDR_UNMASK_CSN0_b; + }; + + union { + __IOM uint32_t QSPI_AUTO_BASE_ADDR_UNMASK_CSN1; /*!< (@ 0x000000B8) none */ + + struct { + __IOM uint32_t QSPI_AUTO_BASE_ADDR_UNMASK_CSN1 : 32; /*!< [31..0] Holds the 32 bit + base address unmask value for + select chip select1 in + programmable auto csn mode. + It is valid + only programmable auto + csn mode is enabled. */ + } QSPI_AUTO_BASE_ADDR_UNMASK_CSN1_b; + }; + __IM uint32_t RESERVED4[2]; + + union { + __IOM uint32_t OCTASPI_BUS_CONTROLLER_2_REG; /*!< (@ 0x000000C4) none */ + + struct { + __IOM uint32_t SET_IP_MODE : 1; /*!< [0..0] This bit enables the qspi + interface pins into HiZ mode */ + __IOM uint32_t AES_NONCE_INIT : 1; /*!< [1..1] This bit enables the AES + initialization with nonce */ + __IOM uint32_t AES_SEC_ENABLE : 1; /*!< [2..2] This bit enables the AES + security enable or not */ + __IOM uint32_t DUAL_MODE_EN : 1; /*!< [3..3] Dual flash mode enable control. */ + __IOM uint32_t CSN0_2_CSN : 2; /*!< [5..4] Map csn0 to the programmed csn. It is + valid for both manual and auto modes */ + __IOM uint32_t CSN1_2_CSN : 2; /*!< [7..6] Map csn1 to the programmed csn. It is + valid for both manual and auto modes */ + __IOM uint32_t CSN2_2_CSN : 2; /*!< [9..8] Map csn2 to the programmed csn. It is + valid for both manual and auto modes */ + __IOM uint32_t CSN3_2_CSN : 2; /*!< [11..10] Map csn3 to the programmed csn. It is + valid for both manual and auto modes */ + __IOM uint32_t AES_SEC_ENABLE_SG1 : 1; /*!< [12..12] This bit enables the AES + security enable or not for segment 1 */ + __IOM uint32_t AES_SEC_ENABLE_SG2 : 1; /*!< [13..13] This bit enables the AES + security enable or not for segment 2 */ + __IOM uint32_t AES_SEC_ENABLE_SG3 : 1; /*!< [14..14] This bit enables the AES + security enable or not for segment 3 */ + __IOM uint32_t AES_SEC_ENABLE_SG4 : 1; /*!< [15..15] This bit enables the AES + security enable or not for segment 4 */ + __IOM uint32_t DUAL_MODE_SWAP_LINES : 1; /*!< [16..16] This bit controls the 8 lines + of qspi with 4 bit swap manner */ + __IOM uint32_t AUTO_MODE_IN_DEFAULT_EN : 1; /*!< [17..17] Qspi works in auto mode if + set this is bit by default. */ + __IOM uint32_t OTP_KEY_LOAD : 1; /*!< [18..18] Enable to load key from OTP/KH */ + __IOM uint32_t DUAL_STAGE_EN_MANUAL : 1; /*!< [19..19] Dual stage en for + dual flash mode */ + __IOM uint32_t RESERVED2 : 12; /*!< [31..20] reserved2 */ + } OCTASPI_BUS_CONTROLLER_2_REG_b; + }; + + union { + __IOM uint32_t QSPI_AES_CONFIG; /*!< (@ 0x000000C8) QSPI AES CONFIG REG */ + + struct { + __IOM uint32_t QSPI_AES_MODE : 9; /*!< [8..0] AES mode of decryption CTR/XTS */ + __IOM uint32_t QSPI_AES_DECKEYCAL : 1; /*!< [9..9] Enables pre-calculation of KEY + before decryption operation */ + __IOM uint32_t FLIP_KEY_FRM_REG : 1; /*!< [10..10] writing 1 to this Flips the 32-bit + endian key taken from kh */ + __IOM uint32_t FLIP_KEY_FRM_KH : 1; /*!< [11..11] writing 1 to this Flips the 32-bit + endian key taken from kh */ + __OM uint32_t QSPI_AES_SRST : 1; /*!< [12..12] Synchronous soft reset for + AES Module. Write only bit. Reading + this bit gives alway 0 */ + __IOM uint32_t RESERVED1 : 19; /*!< [31..13] reserved1 */ + } QSPI_AES_CONFIG_b; + }; + + union { + __IOM uint32_t QSPI_AES_KEY_IV_VALID; /*!< (@ 0x000000CC) QSPI AES KEYS and + IVS VALID */ + + struct { + __IOM uint32_t QSPI_AES_KEY1_VALID : 4; /*!< [3..0] Write enables for AES KEY 1. + Denotes which bytes of key1 is valid */ + __IOM uint32_t RESERVED1 : 4; /*!< [7..4] reserved1 */ + __IOM uint32_t QSPI_AES_KEY2_VALID : 4; /*!< [11..8] Write enables for AES KEY 2. + Denotes which bytes of key2 is valid */ + __IOM uint32_t RESERVED2 : 4; /*!< [15..12] reserved2 */ + __IOM uint32_t QSPI_AES_IV1_VALID : 4; /*!< [19..16] Write enables for AES IV 1. + Denotes which bytes of IV1 is valid */ + __IOM uint32_t RESERVED3 : 12; /*!< [31..20] reserved3 */ + } QSPI_AES_KEY_IV_VALID_b; + }; + + union { + __IM uint32_t QSPI_CMNFLASH_STS; /*!< (@ 0x000000D0) QSPI Common Flash Status */ + + struct { + __IM uint32_t QSPI_MANUAL_BLOCKED : 1; /*!< [0..0] 1 - Manual read/write transaction + initiated is blocked.0- No manual + transactions */ + __IM uint32_t AUTO_READ_OUT_RANGE : 1; /*!< [1..1] 1- Auto read transaction is out + of M4 Address range 0- Auto read + transaction is in Address range */ + __IM uint32_t QSPI_AUTO_RD_BUSY : 1; /*!< [2..2] 1 - Auto read transactions in + progress.0 - No Auto read transactions */ + __IM uint32_t RESERVED1 : 29; /*!< [31..3] reserved1 */ + } QSPI_CMNFLASH_STS_b; + }; + __IM uint32_t RESERVED5[4]; + + union { + __IOM uint32_t QSPI_AES_SEC_SEG_LS_ADDR_1; /*!< (@ 0x000000E4) + QSPI_AES_SEC_SEG_LS_ADDR_1 */ + + struct { + __IOM uint32_t QSPI_AES_SEC_SEG_LS_ADDR_1 : 32; /*!< [31..0] This register specifies + the lower boundary address of + 1st segment */ + } QSPI_AES_SEC_SEG_LS_ADDR_1_b; + }; + + union { + __IOM uint32_t QSPI_AES_SEC_SEG_MS_ADDR_1; /*!< (@ 0x000000E8) + QSPI_AES_SEC_SEG_MS_ADDR_1 */ + + struct { + __IOM uint32_t QSPI_AES_SEC_SEG_MS_ADDR_1 : 32; /*!< [31..0] This register specifies + the upper boundary address of + 1st segment */ + } QSPI_AES_SEC_SEG_MS_ADDR_1_b; + }; + + union { + __IOM uint32_t QSPI_AES_SEC_SEG_LS_ADDR_2; /*!< (@ 0x000000EC) + QSPI_AES_SEC_SEG_LS_ADDR_2 */ + + struct { + __IOM uint32_t QSPI_AES_SEC_SEG_LS_ADDR_2 : 32; /*!< [31..0] This register specifies + the lower boundary address of + 2nd segment */ + } QSPI_AES_SEC_SEG_LS_ADDR_2_b; + }; + + union { + __IOM uint32_t QSPI_AES_SEC_SEG_MS_ADDR_2; /*!< (@ 0x000000F0) + QSPI_AES_SEC_SEG_MS_ADDR_2 */ + + struct { + __IOM uint32_t QSPI_AES_SEC_SEG_MS_ADDR_2 : 32; /*!< [31..0] This register specifies + the upper boundary address of + 2nd segment */ + } QSPI_AES_SEC_SEG_MS_ADDR_2_b; + }; + + union { + __IOM uint32_t QSPI_AES_SEC_SEG_LS_ADDR_3; /*!< (@ 0x000000F4) + QSPI_AES_SEC_SEG_LS_ADDR_3 */ + + struct { + __IOM uint32_t QSPI_AES_SEC_SEG_LS_ADDR_3 : 32; /*!< [31..0] This register specifies + the lower boundary address of + 3rd segment */ + } QSPI_AES_SEC_SEG_LS_ADDR_3_b; + }; + + union { + __IOM uint32_t QSPI_AES_SEC_SEG_MS_ADDR_3; /*!< (@ 0x000000F8) + QSPI_AES_SEC_SEG_MS_ADDR_3 */ + + struct { + __IOM uint32_t QSPI_AES_SEC_SEG_MS_ADDR_3 : 32; /*!< [31..0] This register specifies + the upper boundary address of + 3rd segment */ + } QSPI_AES_SEC_SEG_MS_ADDR_3_b; + }; + + union { + __IOM uint32_t QSPI_AES_SEC_SEG_LS_ADDR_4; /*!< (@ 0x000000FC) + QSPI_AES_SEC_SEG_LS_ADDR_4 */ + + struct { + __IOM uint32_t QSPI_AES_SEC_SEG_LS_ADDR_4 : 32; /*!< [31..0] This register specifies + the lower boundary address of + 4th segment */ + } QSPI_AES_SEC_SEG_LS_ADDR_4_b; + }; + + union { + __IOM uint32_t QSPI_AES_SEC_SEG_MS_ADDR_4; /*!< (@ 0x00000100) + QSPI_AES_SEC_SEG_MS_ADDR_4 */ + + struct { + __IOM uint32_t QSPI_AES_SEC_SEG_MS_ADDR_4 : 32; /*!< [31..0] This register specifies + the upper boundary address of + 4th segment */ + } QSPI_AES_SEC_SEG_MS_ADDR_4_b; + }; + + union { + __IOM uint32_t QSPI_SRAM_CTRL_CSN_REG[4]; /*!< (@ 0x00000104) QSPI SRAM CTRL CSN */ + + struct { + __IOM uint32_t BIT_8_MODE : 1; /*!< [0..0] Flash 8bit (1 byte) boundary mode */ + __IOM uint32_t BYTE_32_MODE : 1; /*!< [1..1] Flash 32 byte boundary mode */ + __IOM uint32_t ADDR_16BIT_MODE : 1; /*!< [2..2] Send only lower 16bits of + Address enable. */ + __IOM uint32_t RESERVED1 : 5; /*!< [7..3] reserved1 */ + __IOM uint32_t CMD_MODE : 2; /*!< [9..8] writing cmd mode */ + __IOM uint32_t ADDR_MODE : 2; /*!< [11..10] writing address mode */ + __IOM uint32_t DATA_MODE : 2; /*!< [13..12] writing address mode */ + __IOM uint32_t RESERVED2 : 2; /*!< [15..14] reserved2 */ + __IOM uint32_t WR_CMD : 8; /*!< [23..16] Command to be used for writing */ + __IOM uint32_t RESERVED3 : 8; /*!< [31..24] reserved3 */ + } QSPI_SRAM_CTRL_CSN_REG_b[4]; + }; + __IM uint32_t RESERVED6[2]; + __IOM + uint32_t SEMI_AUTO_MODE_ADDR_REG; /*!< (@ 0x0000011C) Byte address to read + the data from flash in semi auto + mode. It is valid only semi auto + mode enable bit is asserted */ + + union { + __IOM uint32_t SEMI_AUTO_MODE_CONFIG_REG; /*!< (@ 0x00000120) none */ + + struct { + __IOM uint32_t QSPI_SEMI_AUTO_BSIZE : 8; /*!< [7..0] This is burst size to read data + from flash in semi auto mode */ + __IOM uint32_t QSPI_SEMI_AUTO_HSIZE : 2; /*!< [9..8] Indicates number of bytes valid + in each transaction */ + __IOM uint32_t RESERVED1 : 22; /*!< [31..10] reserved1 */ + } SEMI_AUTO_MODE_CONFIG_REG_b; + }; + + union { + __IOM uint32_t SEMI_AUTO_MODE_CONFIG2_REG; /*!< (@ 0x00000124) none */ + + struct { + __IOM uint32_t QSPI_SEMI_AUTO_RD_CNT : 12; /*!< [11..0] Total number of bytes to be + read flash continuously from the + address given by + SEMI_AUTO_MODE_ADDR_REG */ + __IOM uint32_t QSPI_SEMI_AUTO_MODE_EN : 1; /*!< [12..12] Enable for semi auto mode + read operation. Make sure manual mode + read/write operation is completed + before asserting this bit */ + __IOM uint32_t QSPI_SEMI_AUTO_RD_BUSY : 1; /*!< [13..13] Indicates status of semi + auto mode read status. If it is high, + semi auto mode read operation is + progressing */ + __IOM uint32_t RESERVED1 : 18; /*!< [31..14] reserved1 */ + } SEMI_AUTO_MODE_CONFIG2_REG_b; + }; + + union { + __IOM uint32_t QSPI_BUS_MODE2_REG; /*!< (@ 0x00000128) none */ + + struct { + __IOM uint32_t PREFETCH_ENBLD_MSTR_ID : 4; /*!< [3..0] Holds the programmable + prefetch enabled AHB master ID. This is + commonly used for enabling prefetch for + icache master. */ + __IOM uint32_t PREFETCH_EN_FOR_ICACHE_MSTR : 1; /*!< [4..4] Prefetch enable for + icache AHB master. */ + __IOM uint32_t RESERVED1 : 3; /*!< [7..5] Reserved for future use */ + __IOM + uint32_t QSPI_PREFETCH_ENBLD_TRANS_BYTES : 8; /*!< [15..8] Programmable + prefetch enabled AHB + master transfer bytes. + Assume this is used + for icache and dma ahb + master access in auto + mode. */ + __IOM uint32_t RESERVED2 : 16; /*!< [31..16] Reserved for future use */ + } QSPI_BUS_MODE2_REG_b; + }; + + union { + __IOM uint32_t QSPI_AES_SEC_KEY_FRM_KH_REG; /*!< (@ 0x0000012C) none */ + + struct { + __OM uint32_t START_LOADING_SEC_KEY_FRM_KH : 1; /*!< [0..0] Start Security key + loading from KH. */ + __IM uint32_t LOADING_SEC_KEY_FRM_KH : 1; /*!< [1..1] Indicates security key loading + status from KH. */ + __IOM uint32_t SEC_KEY_READING_INTERVAL : 4; /*!< [5..2] Security key + reading interval */ + __IOM uint32_t RESERVED1 : 26; /*!< [31..6] Reserved for future use */ + } QSPI_AES_SEC_KEY_FRM_KH_REG_b; + }; + + union { + __IOM uint32_t QSPI_AUTO_CONITNUE_FETCH_CTRL_REG; /*!< (@ 0x00000130) none */ + + struct { + __IOM uint32_t CONTINUE_FETCH_WAIT_TIMEOUT_VALUE_FRM_REG : 12; /*!< [11..0] Maximum + Continue fetch wait time + between two qspi auto + reads. */ + __IOM uint32_t CONTINUE_FETCH_EN : 1; /*!< [12..12] Continue fetch feature + enable. */ + __IOM uint32_t RESERVED1 : 19; /*!< [31..13] Reserved for future use */ + } QSPI_AUTO_CONITNUE_FETCH_CTRL_REG_b; + }; + + union { + __IOM uint32_t QSPI_AES_KEY1_0_3; /*!< (@ 0x00000134) QSPI_AES_KEY1_0_3 */ + + struct { + __IOM uint32_t QSPI_AES_KEY1_0_3 : 32; /*!< [31..0] To hold first 3-0 bytes of aes + key1 as 0 referred as lsb in the key */ + } QSPI_AES_KEY1_0_3_b; + }; + + union { + __IOM uint32_t QSPI_AES_KEY1_4_7; /*!< (@ 0x00000138) QSPI_AES_KEY1_4_7 */ + + struct { + __IOM uint32_t QSPI_AES_KEY1_4_7 : 32; /*!< [31..0] To hold first 7-4 bytes of aes + key1 as 0 referred as lsb */ + } QSPI_AES_KEY1_4_7_b; + }; + + union { + __IOM uint32_t QSPI_AES_KEY1_8_B; /*!< (@ 0x0000013C) QSPI_AES_KEY1_8_B */ + + struct { + __IOM uint32_t QSPI_AES_KEY1_8_B : 32; /*!< [31..0] To hold first 11-8 bytes of aes + key1 as 0 referred as lsb */ + } QSPI_AES_KEY1_8_B_b; + }; + + union { + __IOM uint32_t QSPI_AES_KEY1_C_F; /*!< (@ 0x00000140) QSPI_AES_KEY1_C_F */ + + struct { + __IOM uint32_t QSPI_AES_KEY1_C_F : 32; /*!< [31..0] To hold first 11-8 bytes of aes + key1 as 0 referred as lsb */ + } QSPI_AES_KEY1_C_F_b; + }; + __IM uint32_t RESERVED7[4]; + + union { + __IOM uint32_t QSPI_AES_KEY2_0_3; /*!< (@ 0x00000154) QSPI_AES_KEY2_0_3 */ + + struct { + __IOM uint32_t QSPI_AES_KEY2_0_3 : 32; /*!< [31..0] To hold first 3-0 bytes of aes + key2 as 0 referred as lsb in the key */ + } QSPI_AES_KEY2_0_3_b; + }; + + union { + __IOM uint32_t QSPI_AES_KEY2_4_7; /*!< (@ 0x00000158) QSPI_AES_KEY2_4_7 */ + + struct { + __IOM uint32_t QSPI_AES_KEY2_4_7 : 32; /*!< [31..0] To hold first 7-4 bytes of aes + key2 as 0 referred as lsb */ + } QSPI_AES_KEY2_4_7_b; + }; + + union { + __IOM uint32_t QSPI_AES_KEY2_8_B; /*!< (@ 0x0000015C) QSPI_AES_KEY2_8_B */ + + struct { + __IOM uint32_t QSPI_AES_KEY2_8_B : 32; /*!< [31..0] To hold first 11-8 bytes of aes + key2 as 0 referred as lsb */ + } QSPI_AES_KEY2_8_B_b; + }; + + union { + __IOM uint32_t QSPI_AES_KEY2_C_F; /*!< (@ 0x00000160) QSPI_AES_KEY2_C_F */ + + struct { + __IOM uint32_t QSPI_AES_KEY2_C_F : 32; /*!< [31..0] To hold first 15-12 bytes of aes + key2 as 0 referred as lsb */ + } QSPI_AES_KEY2_C_F_b; + }; +} QSPI_Type; /*!< Size = 356 (0x164) */ + +/* =========================================================================================================================== + */ +/* ================ CRC + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief CRC is used in all wireless communication as a first data integrity + * check (CRC) + */ + +typedef struct { /*!< (@ 0x45080000) CRC Structure */ + + union { + __IOM uint32_t CRC_GEN_CTRL_SET_REG; /*!< (@ 0x00000000) General control set + register */ + + struct { + __IOM uint32_t SOFT_RST : 1; /*!< [0..0] Soft reset. This clears the FIFO and settles + all the state machines to their IDLE */ + __IOM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved for future use. */ + } CRC_GEN_CTRL_SET_REG_b; + }; + + union { + __IOM uint32_t CRC_GEN_CTRL_RESET; /*!< (@ 0x00000004) General control reset + register */ + + struct { + __IOM uint32_t RESERVED1 : 32; /*!< [31..0] Reserved for future use. */ + } CRC_GEN_CTRL_RESET_b; + }; + + union { + __IM uint32_t CRC_GEN_STS; /*!< (@ 0x00000008) General status register */ + + struct { + __IM uint32_t CALC_DONE : 1; /*!< [0..0] When the computation of final CRC + with the data out of fifo, this will get + set to 1 otherwise 0 */ + __IM uint32_t DIN_NUM_BYTES_DONE : 1; /*!< [1..1] When number of bytes requested for + computation of final CRC is read from fifo + by internal FSM, this will get set to 1 + otherwise 0. */ + __IM uint32_t RESERVED1 : 30; /*!< [31..2] Reserved for future use. */ + } CRC_GEN_STS_b; + }; + + union { + __IOM uint32_t CRC_POLYNOMIAL; /*!< (@ 0x0000000C) This register holds the polynomial + with which the final CRC is computed. */ + + struct { + __IOM uint32_t POLYNOMIAL : 32; /*!< [31..0] Polynomial register. This register holds + the polynomial with which the final CRC is + computed.When write Polynomial will be + updated.When read read polynomial. */ + } CRC_POLYNOMIAL_b; + }; + + union { + __IOM uint32_t CRC_POLYNOMIAL_CTRL_SET; /*!< (@ 0x00000010) Polynomial + control set register */ + + struct { + __IOM uint32_t POLYNOMIAL_WIDTH_SET : 5; /*!< [4..0] Polynomial width set. Number of + bits/width of the polynomial has to be + written here for the computation of final + CRC. If a new width has to be configured, + clear the existing length first by + writing 0x1f in polynomial_ctrl_reset + register. When read, actual polynomial + width is read. */ + __IOM uint32_t RESERVED1 : 27; /*!< [31..5] Reserved for future use. */ + } CRC_POLYNOMIAL_CTRL_SET_b; + }; + + union { + __IOM uint32_t CRC_POLYNOMIAL_CTRL_RESET; /*!< (@ 0x00000014) Polynomial + control set register */ + + struct { + __IOM uint32_t POLYNOMIAL_WIDTH_SET : 5; /*!< [4..0] Polynomial width reset. If a new + width has to be configured, clear the + existing length first by writing 0x1f. + When read, actual polynomial width is + read. */ + __IOM uint32_t RESERVED1 : 27; /*!< [31..5] Reserved for future use. */ + } CRC_POLYNOMIAL_CTRL_RESET_b; + }; + + union { + __IOM uint32_t CRC_LFSR_INIT_VAL; /*!< (@ 0x00000018) LFSR initial value */ + + struct { + __IOM uint32_t LFSR_INIT : 32; /*!< [31..0] This holds LFSR initialization value. + When ever LFSR needs to be initialized, this has to + be updated with the init value and trigger + init_lfsr in LFSR_INIT_CTRL_SET register. For + example, in WiFi case, 0xffffffff is used as init + value of LFSR. */ + } CRC_LFSR_INIT_VAL_b; + }; + + union { + __IOM uint32_t CRC_LFSR_INIT_CTRL_SET; /*!< (@ 0x0000001C) LFSR state initialization + control set register */ + + struct { + __IOM uint32_t CLEAR_LFSR : 1; /*!< [0..0] Clear LFSR state. When this is + set, LFSR state is cleared to 0 */ + __IOM uint32_t INIT_LFSR : 1; /*!< [1..1] Initialize LFSR state. When this + is set LFSR state will be initialized + with LFSR_INIT_VAL/bit swapped + LFSR_INIT_VAL in the next cycle */ + __IOM uint32_t USE_SWAPPED_INIT_VAL : 1; /*!< [2..2] Use bit swapped init value. If + this is set bit swapped version of LFSR + init value will be loaded / initialized + to LFSR state */ + __IOM uint32_t RESERVED1 : 29; /*!< [31..3] Reserved for future use. */ + } CRC_LFSR_INIT_CTRL_SET_b; + }; + + union { + __IOM uint32_t CRC_LFSR_INIT_CTRL_RESET; /*!< (@ 0x00000020) LFSR state initialization + control reset register */ + + struct { + __IOM uint32_t RESERVED1 : 1; /*!< [0..0] Reserved for future use. */ + __IOM uint32_t RESERVED2 : 1; /*!< [1..1] Reserved for future use. */ + __IOM uint32_t USE_SWAPPED_INIT_VAL : 1; /*!< [2..2] Use bit swapped init value. If + this is set bit swapped version of LFSR + init value will be loaded / initialized + to LFSR state */ + __IOM uint32_t RESERVED3 : 29; /*!< [31..3] Reserved for future use. */ + } CRC_LFSR_INIT_CTRL_RESET_b; + }; + + union { + __OM uint32_t CRC_DIN_FIFO; /*!< (@ 0x00000024) Data input FIFO register */ + + struct { + __OM uint32_t DIN_FIFO : 32; /*!< [31..0] FIFO input port is mapped to this + register. Data on which the final CRC has to be + computed has to be loaded to this FIFO */ + } CRC_DIN_FIFO_b; + }; + + union { + __IOM uint32_t CRC_DIN_CTRL_SET; /*!< (@ 0x00000028) Input data control set + register */ + + struct { + __IOM uint32_t DIN_WIDTH_REG : 5; /*!< [4..0] Valid number of bits in the input data + in din_width_from_reg set mode. Before writing a + new value into this, din_ctrl_reset_reg has to + be written with 0x1f to clear this field as + these are set/clear bits. */ + __IOM uint32_t DIN_WIDTH_FROM_REG : 1; /*!< [5..5] Valid number of bits in the input + data. In default, number of valid bits in + the input data is taken from ULI (uli_be). + If this is set, whatever is the input + size, only din_ctrl_reg[4:0] is taken as + valid length/width for inout data. */ + __IOM uint32_t DIN_WIDTH_FROM_CNT : 1; /*!< [6..6] Valid number of bits in the input + data. In default, number of valid bits in + the input data is taken from ULI (uli_be). + If this is set, a mix of ULI length + and number of bytes remaining will form the + valid bits (which ever is less + that will be considered as valid + bits). */ + __IOM uint32_t USE_SWAPPED_DIN : 1; /*!< [7..7] Use bit swapped input data. If this + is set, input data will be swapped and filled + in to FIFO. Whatever read out from FIFO will + be directly fed to LFSR engine. */ + __IOM uint32_t RESET_FIFO_PTRS : 1; /*!< [8..8] Reset fifo pointer. This + clears the FIFO.When this is set, + FIFO will be cleared. */ + __IOM uint32_t RESERVED1 : 15; /*!< [23..9] Reserved for future use. */ + __IOM uint32_t FIFO_AEMPTY_THRESHOLD : 4; /*!< [27..24] FIFO almost empty threshold + value. This has to be cleared by writing + 0x0f000000 into din_ctrl_reset before + updating any new value. */ + __IOM uint32_t FIFO_AFULL_THRESHOULD : 4; /*!< [31..28] FIFO almost full threshold + value. This has to be cleared by writing + 0xf0000000 into din_ctrl_reset before + updating any new value */ + } CRC_DIN_CTRL_SET_b; + }; + + union { + __IOM uint32_t CRC_DIN_CTRL_RESET_REG; /*!< (@ 0x0000002C) Input data + control set register */ + + struct { + __IOM uint32_t DIN_WIDTH_REG : 5; /*!< [4..0] Valid number of bits in the input data + in din_width_from_reg set mode. Before writing a + new value into this, din_ctrl_reset_reg has to + be written with 0x1f to clear this field as + these are set/clear bits. */ + __IOM uint32_t DIN_WIDTH_FROM_REG : 1; /*!< [5..5] Valid number of bits in the input + data. In default, number of valid bits in + the input data is taken from ULI (uli_be). + If this is set, whatever is the input + size, only din_ctrl_reg[4:0] is taken as + valid length/width for inout data. */ + __IOM uint32_t DIN_WIDTH_FROM_CNT : 1; /*!< [6..6] Valid number of bits in the input + data. In default, number of valid bits in + the input data is taken from ULI (uli_be). + If this is set, a mix of ULI length + and number of bytes remaining will form the + valid bits (which ever is less + that will be considered as valid + bits). */ + __IOM uint32_t USE_SWAPPED_DIN : 1; /*!< [7..7] Use bit swapped input data. If this + is set input data will be swapped and filled + in to FIFO. Whatever read out from FIFO will + be directly fed to LFSR engine. */ + __IOM uint32_t RESERVED1 : 1; /*!< [8..8] Reserved for future use. */ + __IOM uint32_t RESERVED2 : 15; /*!< [23..9] Reserved for future use. */ + __IOM uint32_t FIFO_AEMPTY_THRESHOLD : 4; /*!< [27..24] FIFO almost empty threshold + value. This has to be cleared by writing + 0x0f000000 into din_ctrl_reset before + updating any new value. */ + __IOM uint32_t FIFO_AFULL_THRESHOULD : 4; /*!< [31..28] FIFO almost full threshold + value. This has to be cleared by writing + 0xf0000000 into din_ctrl_reset before + updating any new value */ + } CRC_DIN_CTRL_RESET_REG_b; + }; + + union { + __IOM uint32_t CRC_DIN_NUM_BYTES; /*!< (@ 0x00000030) Data input FIFO register */ + + struct { + __IOM uint32_t DIN_NUM_BYTES : 32; /*!< [31..0] in out data number of bytes */ + } CRC_DIN_NUM_BYTES_b; + }; + + union { + __IM uint32_t CRC_DIN_STS; /*!< (@ 0x00000034) Input data status register */ + + struct { + __IM uint32_t FIFO_EMPTY : 1; /*!< [0..0] FIFO empty indication status */ + __IM uint32_t FIFO_AEMPTY : 1; /*!< [1..1] FIFO almost empty indication status. */ + __IM uint32_t FIFO_AFULL : 1; /*!< [2..2] FIFO almost full indication status */ + __IM uint32_t FIFO_FULL : 1; /*!< [3..3] FIFO full indication status */ + __IM uint32_t FIFO_OCC : 6; /*!< [9..4] FIFO occupancy */ + __IM uint32_t RESERVED1 : 22; /*!< [31..10] Reserved for future use. */ + } CRC_DIN_STS_b; + }; + + union { + __IOM uint32_t CRC_LFSR_STATE; /*!< (@ 0x00000038) LFSR state register */ + + struct { + __IOM uint32_t LFSR_STATE : 32; /*!< [31..0] If LFSR dynamic loading is + required this can be used for writing + the LFSR state directly. */ + } CRC_LFSR_STATE_b; + }; +} CRC_Type; /*!< Size = 60 (0x3c) */ + +/* =========================================================================================================================== + */ +/* ================ EFUSE + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief The EFUSE controller is used to provide an interface to one time + * program memory (EFUSE macro) to perform write and read operations (EFUSE) + */ + +typedef struct { /*!< (@ 0x4600C000) EFUSE Structure */ + + union { + __IOM uint32_t EFUSE_DA_ADDR_REG; /*!< (@ 0x00000000) Direct Access Registers */ + + struct { + __IOM uint32_t ADDR_BITS : 16; /*!< [15..0] These bits specifies the address to write + or read from EFUSE macro model */ + __IOM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + } EFUSE_DA_ADDR_REG_b; + }; + + union { + __IOM uint32_t EFUSE_DA_CTRL_SET_REG; /*!< (@ 0x00000004) Direct Access Set + Registers */ + + struct { + __IOM uint32_t PGENB : 1; /*!< [0..0] Set Program enable */ + __IOM uint32_t CSB : 1; /*!< [1..1] Set Chip Enable */ + __IOM uint32_t STROBE : 1; /*!< [2..2] Set strobe enable */ + __IOM uint32_t LOAD : 1; /*!< [3..3] Set Load enable */ + __IOM uint32_t RESERVED1 : 12; /*!< [15..4] reserved1 */ + __IOM uint32_t RESERVED2 : 16; /*!< [31..16] reserved2 */ + } EFUSE_DA_CTRL_SET_REG_b; + }; + + union { + __IOM uint32_t EFUSE_DA_CTRL_CLEAR_REG; /*!< (@ 0x00000008) Direct Access + Clear Registers */ + + struct { + __IOM uint32_t PGENB : 1; /*!< [0..0] Clear Program enable */ + __IOM uint32_t CSB : 1; /*!< [1..1] Clear Chip Enable */ + __IM uint32_t RESERVED1 : 1; /*!< [2..2] reserved1 */ + __IOM uint32_t LOAD : 1; /*!< [3..3] Clear Load enable */ + __IM uint32_t RESERVED2 : 12; /*!< [15..4] reserved2 */ + __IM uint32_t RESERVED3 : 16; /*!< [31..16] reserved3 */ + } EFUSE_DA_CTRL_CLEAR_REG_b; + }; + + union { + __IOM uint32_t EFUSE_CTRL_REG; /*!< (@ 0x0000000C) Control Register */ + + struct { + __IOM uint32_t EFUSE_ENABLE : 1; /*!< [0..0] This bit specifies whether the EFUSE + module is enabled or not */ + __IOM uint32_t EFUSE_DIRECT_PATH_ENABLE : 1; /*!< [1..1] This bit specifies whether + the EFUSE direct path is enabled or + not for direct accessing of the EFUSE + pins */ + __IOM uint32_t ENABLE_EFUSE_WRITE : 1; /*!< [2..2] Controls the switch on + VDDIQ for eFuse read/write. */ + __IM uint32_t RESERVED1 : 13; /*!< [15..3] reserved1 */ + __IM uint32_t RESERVED2 : 16; /*!< [31..16] reserved2 */ + } EFUSE_CTRL_REG_b; + }; + + union { + __IOM uint32_t EFUSE_READ_ADDR_REG; /*!< (@ 0x00000010) Read address Register */ + + struct { + __IOM uint32_t READ_ADDR_BITS : 13; /*!< [12..0] These bits specifies the + address from which read operation + has to be performed */ + __IM uint32_t RESERVED1 : 2; /*!< [14..13] reserved1 */ + __OM uint32_t DO_READ : 1; /*!< [15..15] Enables read FSM after EFUSE is + enabled */ + __IM uint32_t RESERVED2 : 16; /*!< [31..16] reserved2 */ + } EFUSE_READ_ADDR_REG_b; + }; + + union { + __IOM uint32_t EFUSE_READ_DATA_REG; /*!< (@ 0x00000014) Read address Register */ + + struct { + __IOM uint32_t READ_DATA_BITS : 8; /*!< [7..0] These bits specifies the data bits + that are read from a given address specified in + the EFUSE_READ_ADDRESS_REGISTER bits 8:0 */ + __IM uint32_t RESERVED1 : 7; /*!< [14..8] reserved1 */ + __IM uint32_t READ_FSM_DONE : 1; /*!< [15..15] Indicates read fsm is done. + After this read data is available in + EFUSE_READ_DATA_REGISTER bits 7:0 */ + __IM uint32_t RESERVED2 : 16; /*!< [31..16] reserved2 */ + } EFUSE_READ_DATA_REG_b; + }; + + union { + __IM uint32_t EFUSE_STATUS_REG; /*!< (@ 0x00000018) Read address Register */ + + struct { + __IM uint32_t EFUSE_ENABLED : 1; /*!< [0..0] This bit specifies whether + the EFUSE is enabled or not */ + __IM uint32_t RESERVED1 : 1; /*!< [1..1] reserved1 */ + __IM uint32_t EFUSE_DOUT_SYNC : 8; /*!< [9..2] This bit specifies the 8-bit data + read out from the EFUSE macro. This is + synchronized with pclk */ + __IM uint32_t STROBE_CLEAR_BIT : 1; /*!< [10..10] This bit indicates STROBE signal + goes low after strobe + count value reached '0' */ + __IM uint32_t RESERVED2 : 5; /*!< [15..11] reserved2 */ + __IM uint32_t RESERVED3 : 16; /*!< [31..16] reserved3 */ + } EFUSE_STATUS_REG_b; + }; + + union { + __IOM uint32_t EFUSE_RD_TMNG_PARAM_REG; /*!< (@ 0x0000001C) none */ + + struct { + __IOM uint32_t TSUR_CS : 4; /*!< [3..0] CSB to STROBE setup time into read mode */ + __IOM uint32_t TSQ : 4; /*!< [7..4] Q7-Q0 access time from STROBE rising edge */ + __IOM uint32_t THRA : 4; /*!< [11..8] for 32x8 macro: A4 A0 to STROBE hold + time into Read mode 5122x8 macro: A8 A0 to + STROBE hold time into Read mode */ + __IM uint32_t RESERVED1 : 4; /*!< [15..12] reserved1 */ + __IM uint32_t RESERVED2 : 16; /*!< [31..16] reserved2 */ + } EFUSE_RD_TMNG_PARAM_REG_b; + }; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t EFUSE_MEM_MAP_LENGTH_REG; /*!< (@ 0x00000024) none */ + + struct { + __IOM uint32_t EFUSE_MEM_MAP_LEN : 1; /*!< [0..0] 0: 8 bit read 1: 16 bit read */ + __IM uint32_t RESERVED1 : 15; /*!< [15..1] reserved1 */ + __IM uint32_t RESERVED2 : 16; /*!< [31..16] reserved2 */ + } EFUSE_MEM_MAP_LENGTH_REG_b; + }; + + union { + __IOM + uint32_t EFUSE_READ_BLOCK_STARTING_LOCATION; /*!< (@ 0x00000028) Starting + address from which the read + has to be blocked. Once the + end address is written, it + cannot be changed till power + on reset is given */ + + struct { + __IOM uint32_t EFUSE_READ_BLOCK_STARTING_LOCATION : 16; /*!< [15..0] Starting address + from which the read has to + be blocked. Once the end + address is written, it + cannot be changed till + power on reset is given. + */ + __IM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + } EFUSE_READ_BLOCK_STARTING_LOCATION_b; + }; + + union { + __IOM uint32_t EFUSE_READ_BLOCK_END_LOCATION; /*!< (@ 0x0000002C) Starting address from + which the read has to be blocked. Once + the end address is written, it cannot + be changed till power on reset is + given */ + + struct { + __IOM uint32_t EFUSE_READ_BLOCK_END_LOCATION : 16; /*!< [15..0] End address till + which the read has to be + blocked. Once the end address + is written , it cannot be + changed till + power on reset is given. + */ + __IM uint32_t RESERVED1 : 16; /*!< [31..16] reserved1 */ + } EFUSE_READ_BLOCK_END_LOCATION_b; + }; + + union { + __IOM uint32_t EFUSE_READ_BLOCK_ENABLE_REG; /*!< (@ 0x00000030) The Transmit Poll + Demand register enables the Transmit DMA + to check whether or not the current + descriptor is owned by DMA */ + + struct { + __IOM uint32_t EFUSE_READ_BLOCK_ENABLE : 1; /*!< [0..0] Enable for blocking the read + access from a programmable memory + location */ + __IM uint32_t RESERVED1 : 15; /*!< [15..1] reserved1 */ + __IM uint32_t RESERVED2 : 16; /*!< [31..16] reserved2 */ + } EFUSE_READ_BLOCK_ENABLE_REG_b; + }; + + union { + __IOM uint32_t EFUSE_DA_CLR_STROBE_REG; /*!< (@ 0x00000034) none */ + + struct { + __IOM uint32_t EFUSE_STROBE_CLR_CNT : 9; /*!< [8..0] Strobe signal Clear count in + direct access mode. value + depends on APB clock frequency of + eFuse controller */ + __IOM uint32_t EFUSE_STROBE_ENABLE : 1; /*!< [9..9] none */ + __IM uint32_t RESERVED1 : 6; /*!< [15..10] reserved1 */ + __IM uint32_t RESERVED2 : 16; /*!< [31..16] reserved2 */ + } EFUSE_DA_CLR_STROBE_REG_b; + }; +} EFUSE_Type; /*!< Size = 56 (0x38) */ + +/* =========================================================================================================================== + */ +/* ================ I2S0 + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief I2S(Inter-IC Sound) is transferring two-channel digital audio data + * from one IC device to another (I2S0) + */ + +typedef struct { /*!< (@ 0x47050000) I2S0 Structure */ + + union { + __IOM uint32_t I2S_IER; /*!< (@ 0x00000000) I2S Enable Register */ + + struct { + __IOM uint32_t IEN : 1; /*!< [0..0] Inter Block Enable */ + __IOM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + } I2S_IER_b; + }; + + union { + __IOM uint32_t I2S_IRER; /*!< (@ 0x00000004) I2S Receiver Block Enable Register */ + + struct { + __IOM uint32_t RXEN : 1; /*!< [0..0] Receive Block Enable, Bit Overrides + any Individual Receive Channel Enables */ + __IOM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + } I2S_IRER_b; + }; + + union { + __IOM uint32_t I2S_ITER; /*!< (@ 0x00000008) Transmitter Block Enable */ + + struct { + __IOM uint32_t TXEN : 1; /*!< [0..0] Transmitter Block Enable, Bit Overrides any + Individual Transmit Channel Enables */ + __IOM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + } I2S_ITER_b; + }; + + union { + __IOM uint32_t I2S_CER; /*!< (@ 0x0000000C) Clock Enable Register */ + + struct { + __IOM uint32_t CLKEN : 1; /*!< [0..0] Clock generation enable/disable */ + __IOM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + } I2S_CER_b; + }; + + union { + __IOM uint32_t I2S_CCR; /*!< (@ 0x00000010) Clock Configuration Register */ + + struct { + __IOM uint32_t SCLKG : 3; /*!< [2..0] These bits are used to program the + gating of sclk */ + __IOM uint32_t WSS : 2; /*!< [4..3] These bits are used to program the + number of sclk cycles */ + __IOM uint32_t RESERVED1 : 27; /*!< [31..5] Reserved for future use */ + } I2S_CCR_b; + }; + + union { + __OM uint32_t I2S_RXFFR; /*!< (@ 0x00000014) Receiver Block FIFO Reset Register */ + + struct { + __OM uint32_t RXFFR : 1; /*!< [0..0] Writing a 1 To This Register Flushes + All The RX FIFO's Receiver Block Must be + Disable Prior to Writing This Bit */ + __OM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + } I2S_RXFFR_b; + }; + + union { + __OM uint32_t I2S_TXFFR; /*!< (@ 0x00000018) Transmitter Block FIFO Reset + Register */ + + struct { + __OM uint32_t TXFFR : 1; /*!< [0..0] Writing a 1 To This Register Flushes + All The RX FIFO's Receiver Block Must be + Disable Prior to Writing This Bit */ + __OM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + } I2S_TXFFR_b; + }; + __IM uint32_t RESERVED; + __IOM I2S0_CHANNEL_CONFIG_Type CHANNEL_CONFIG[4]; /*!< (@ 0x00000020) [0..3] */ + __IM uint32_t RESERVED1[40]; + + union { + __IM uint32_t I2S_RXDMA; /*!< (@ 0x000001C0) Receiver Block DMA Register */ + + struct { + __IM uint32_t RXDMA : 32; /*!< [31..0] Used to cycle repeatedly through the enabled + receive channels Reading stereo data pairs */ + } I2S_RXDMA_b; + }; + + union { + __OM uint32_t I2S_RRXDMA; /*!< (@ 0x000001C4) Reset Receiver Block DMA Register */ + + struct { + __OM uint32_t RRXDMA : 1; /*!< [0..0] Writing a 1 to this self-clearing + register resets the RXDMA register */ + __OM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + } I2S_RRXDMA_b; + }; + + union { + __OM uint32_t I2S_TXDMA; /*!< (@ 0x000001C8) Transmitter Block DMA Register */ + + struct { + __OM uint32_t TXDMA : 32; /*!< [31..0] Used to cycle repeatedly through + the enabled transmit channels allow to + writing of stereo data pairs */ + } I2S_TXDMA_b; + }; + + union { + __OM uint32_t I2S_RTXDMA; /*!< (@ 0x000001CC) Reset Transmitter Block DMA + Register */ + + struct { + __OM uint32_t RTXDMA : 1; /*!< [0..0] Writing a 1 to this self-clearing + register resets the TXDMA register */ + __OM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved1 */ + } I2S_RTXDMA_b; + }; + __IM uint32_t RESERVED2[8]; + + union { + __IM uint32_t I2S_COMP_PARAM_2; /*!< (@ 0x000001F0) Component Parameter 2 + Register */ + + struct { + __IM uint32_t I2S_RX_WORDSIZE_0 : 3; /*!< [2..0] On Read returns the value + of word size of receiver channel + 0 */ + __IM uint32_t I2S_RX_WORDSIZE_1 : 3; /*!< [5..3] On Read returns the value + of word size of receiver channel + 1 */ + __IM uint32_t RESERVED1 : 1; /*!< [6..6] Reserved1 */ + __IM uint32_t I2S_RX_WORDSIZE_2 : 3; /*!< [9..7] On Read returns the value + of word size of receiver channel + 2 */ + __IM uint32_t I2S_RX_WORDSIZE_3 : 3; /*!< [12..10] On Read returns the value of word + size of receiver channel 3 */ + __IM uint32_t RESERVED2 : 19; /*!< [31..13] Reserved2 */ + } I2S_COMP_PARAM_2_b; + }; + + union { + __IM uint32_t I2S_COMP_PARAM_1; /*!< (@ 0x000001F4) Component Parameter 1 + Register */ + + struct { + __IM uint32_t APB_DATA_WIDTH : 2; /*!< [1..0] Width of APB data bus */ + __IM uint32_t I2S_FIFO_DEPTH_GLOBAL : 2; /*!< [3..2] Determines FIFO depth + for all channels */ + __IM uint32_t I2S_FIFO_MODE_EN : 1; /*!< [4..4] Determines whether component act as + Master or Slave */ + __IM uint32_t I2S_TRANSMITTER_BLOCK : 1; /*!< [5..5] Shows the presence of + the transmitter block */ + __IM uint32_t I2S_RECEIVER_BLOCK : 1; /*!< [6..6] Shows the presence of + the receiver block */ + __IM uint32_t I2S_RX_CHANNELS : 2; /*!< [8..7] Returns the number of + receiver channels */ + __IM uint32_t I2S_TX_CHANNELS : 2; /*!< [10..9] Returns the number of + transmitter channels */ + __IM uint32_t RESERVED1 : 5; /*!< [15..11] Reserved1 */ + __IM uint32_t I2S_TX_WORDSIZE_0 : 3; /*!< [18..16] Returns the value of + word size of transmitter channel + 0 */ + __IM uint32_t I2S_TX_WORDSIZE_1 : 3; /*!< [21..19] Returns the value of + word size of transmitter channel + 1 */ + __IM uint32_t I2S_TX_WORDSIZE_2 : 3; /*!< [24..22] Returns the value of + word size of transmitter channel + 2 */ + __IM uint32_t I2S_TX_WORDSIZE_3 : 3; /*!< [27..25] Returns the value of + word size of transmitter channel + 3 */ + __IM uint32_t RESERVED2 : 4; /*!< [31..28] Reserved2 */ + } I2S_COMP_PARAM_1_b; + }; + + union { + __IM uint32_t I2S_COMP_VERSION_REG; /*!< (@ 0x000001F8) Component Version ID */ + + struct { + __IM uint32_t I2S_COMP_VERSION : 32; /*!< [31..0] Return the component + version(1.02) */ + } I2S_COMP_VERSION_REG_b; + }; + + union { + __IM uint32_t I2S_COMP_TYPE_REG; /*!< (@ 0x000001FC) Component Type */ + + struct { + __IM uint32_t I2S_COMP_TYPE : 32; /*!< [31..0] Return the component type */ + } I2S_COMP_TYPE_REG_b; + }; +} I2S0_Type; /*!< Size = 512 (0x200) */ + +/* =========================================================================================================================== + */ +/* ================ IID_AES + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief The AES module provides AES encoding and decoding functionality. It + * can be used in a microprocessor based environment (IID_AES) + */ + +typedef struct { /*!< (@ 0x20480500) IID_AES Structure */ + + union { + __IOM uint32_t AES_KCR; /*!< (@ 0x00000000) AES Key Control register */ + + struct { + __IOM uint32_t AES_KEY_CHNG_REQ : 1; /*!< [0..0] Programming 1 clears the current key + and starts a request a for a new key + Auto-reverts to 0 as soon as the request is + accepted */ + __IOM uint32_t AES_KEY_SIZE : 1; /*!< [1..1] Size of the AES key 0: + 128-bit 1: 256-bit */ + __IM uint32_t : 5; + __IOM uint32_t AES_KEY_SRC : 1; /*!< [7..7] Source of the AES key 0: + Interface 1: Register */ + __IM uint32_t : 24; + } AES_KCR_b; + }; + + union { + __IOM uint32_t AES_MODE_REG; /*!< (@ 0x00000004) AES Mode register */ + + struct { + __IOM uint32_t AES_MODE : 8; /*!< [7..0] The AES Mode register defines + which mode of AES is used. */ + __IM uint32_t : 24; + } AES_MODE_REG_b; + }; + + union { + __IOM uint32_t AES_ACT_REG; /*!< (@ 0x00000008) AES Action register */ + + struct { + __IOM uint32_t AES_ACTION : 2; /*!< [1..0] The AES Mode register defines + which mode of AES is used. */ + __IM uint32_t : 30; + } AES_ACT_REG_b; + }; + __IM uint32_t RESERVED[5]; + + union { + __IM uint32_t AES_SR_REG; /*!< (@ 0x00000020) AES Status register */ + + struct { + __IM uint32_t AES_BUSY : 1; /*!< [0..0] Indicates that the AES core is + processing data */ + __IM uint32_t : 1; + __IM uint32_t AES_CLEAR_DONE : 1; /*!< [2..2] Indicates that the Clear + action is finished */ + __IM uint32_t AES_KEY_PRESENT : 1; /*!< [3..3] Indicates that the Clear + action is finished */ + __IM uint32_t : 1; + __IM uint32_t AES_KEY_REQ : 1; /*!< [5..5] Indicates that a key must be + provided */ + __IM uint32_t AES_DATA_REQ : 1; /*!< [6..6] Indicates that data must be + provided */ + __IM uint32_t AES_DATA_AV : 1; /*!< [7..7] Indicates that data is available */ + __IM uint32_t : 24; + } AES_SR_REG_b; + }; + __IM uint32_t RESERVED1[7]; + + union { + __OM uint32_t AES_KEY_REG; /*!< (@ 0x00000040) The AES Key register is used + to program a key into the AES module. */ + + struct { + __OM uint32_t AES_KEY : 32; /*!< [31..0] 4 writes of 32 bits make up the 128-bit key + for AES, 8 writes make up the 256-bit key */ + } AES_KEY_REG_b; + }; + + union { + __OM uint32_t AES_DIN_REG; /*!< (@ 0x00000044) AES Data In register */ + + struct { + __OM uint32_t AES_DIN : 32; /*!< [31..0] Data for encoding or decoding, 4 writes of + 32 bits make up a 128-bit data word */ + } AES_DIN_REG_b; + }; + + union { + __IM uint32_t AES_DOUT_REG; /*!< (@ 0x00000048) AES Data out register */ + + struct { + __IM uint32_t AES_DOUT : 32; /*!< [31..0] Result from encoding or decoding, 4 reads + of 32 bits make up a 128-bit data word */ + } AES_DOUT_REG_b; + }; + __IM uint32_t RESERVED2[36]; + + union { + __OM uint32_t AES_IF_SR_C_REG; /*!< (@ 0x000000DC) AES Interface Status + Clear register */ + + struct { + __OM uint32_t IFB_ERROR : 1; /*!< [0..0] Clears the if_error bit */ + __IM uint32_t : 31; + } AES_IF_SR_C_REG_b; + }; + + union { + __IM uint32_t AES_IF_SR_REG; /*!< (@ 0x000000E0) AES Interface Status register */ + + struct { + __IM uint32_t IF_ERROR : 1; /*!< [0..0] Indicates that an interface error + has occurred */ + __IM uint32_t : 31; + } AES_IF_SR_REG_b; + }; + + union { + __IOM uint32_t AES_TEST_REG; /*!< (@ 0x000000E4) AES Test register */ + + struct { + __IOM uint32_t AES_BIST_ENABLE : 1; /*!< [0..0] Isolates the iid_aes + module and runs a BIST */ + __IM uint32_t : 3; + __IOM uint32_t AES_BIST_RUNNING : 1; /*!< [4..4] BIST is in progress or + finishing up */ + __IOM uint32_t AES_BIST_ACTIVE : 1; /*!< [5..5] Indicates that the BIST is + running */ + __IOM uint32_t AES_BIST_OK : 1; /*!< [6..6] Indicates that the BIST has passed */ + __IOM uint32_t AES_BIST_ERROR : 1; /*!< [7..7] Indicates that the BIST has + failed */ + __IM uint32_t : 24; + } AES_TEST_REG_b; + }; + __IM uint32_t RESERVED3[6]; + + union { + __IM uint32_t AES_VER_REG; /*!< (@ 0x00000100) AES Version register */ + + struct { + __IM uint32_t AES_VERSION : 32; /*!< [31..0] Version of iid_aes */ + } AES_VER_REG_b; + }; +} IID_AES_Type; /*!< Size = 260 (0x104) */ + +/* =========================================================================================================================== + */ +/* ================ IID_QK + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief The purpose of Quiddikey is to provide secure key storage without + * storing the key. (IID_QK) + */ + +typedef struct { /*!< (@ 0x20480600) IID_QK Structure */ + + union { + __OM uint32_t QK_CR_REG; /*!< (@ 0x00000000) Quiddikey Control register.The + Quiddikey Control register defines which command + must be executed next. */ + + struct { + __OM uint32_t QK_ZEROIZE : 1; /*!< [0..0] Begin Zeroize operation and go + to Error state */ + __OM uint32_t QK_ENROLL : 1; /*!< [1..1] Begin Enroll operation */ + __OM uint32_t QK_START : 1; /*!< [2..2] Begin Start operation */ + __OM uint32_t QK_SET_IK : 1; /*!< [3..3] Begin Set Intrinsic Key operation */ + __OM uint32_t QK_SET_UK : 1; /*!< [4..4] Begin Set User Key operation */ + __OM uint32_t QK_SET_XK : 1; /*!< [5..5] Begin Set External Key operation */ + __OM uint32_t QK_GET_KEY : 1; /*!< [6..6] Begin Get Key operation */ + __IM uint32_t : 25; + } QK_CR_REG_b; + }; + + union { + __IOM uint32_t QK_KIDX_REG; /*!< (@ 0x00000004) The Quiddikey Key Index register + defines the key index for the next set_key command */ + + struct { + __IOM uint32_t QK_KEY_INDEX : 4; /*!< [3..0] Key index for Set Key operations */ + __IM uint32_t : 28; + } QK_KIDX_REG_b; + }; + + union { + __IOM uint32_t QK_KSZ_REG; /*!< (@ 0x00000008) Quiddikey Key Size register */ + + struct { + __IOM uint32_t QK_KEY_SIZE : 6; /*!< [5..0] Key size for Set Key operations */ + __IM uint32_t : 26; + } QK_KSZ_REG_b; + }; + + union { + __IOM uint32_t QK_KT_REG; /*!< (@ 0x0000000C) Quiddikey Key Size register */ + + struct { + __IOM uint32_t QK_KEY_TARGET : 1; /*!< [0..0] Target of reconstructed key */ + __IM uint32_t : 31; + } QK_KT_REG_b; + }; + __IM uint32_t RESERVED[4]; + + union { + __IM uint32_t QK_SR_REG; /*!< (@ 0x00000020) Quiddikey Status register */ + + struct { + __IM uint32_t QK_BUSY : 1; /*!< [0..0] Indicates that operation is in progress */ + __IM uint32_t QK_OK : 1; /*!< [1..1] Last operation was successful */ + __IM uint32_t QK_ERROR : 1; /*!< [2..2] Quiddikey is in the Error state + and no operations can be performed */ + __IM uint32_t QK_XO_AV : 1; /*!< [3..3] Next part of XKPD is available */ + __IM uint32_t QK_KI_REQ : 1; /*!< [4..4] Request for next part of key */ + __IM uint32_t QK_KO_AV : 1; /*!< [5..5] Next part of key is available */ + __IM uint32_t QK_CI_REQ : 1; /*!< [6..6] Request for next part of AC/KC */ + __IM uint32_t QK_CO_AV : 1; /*!< [7..7] Next part of AC/KC is available */ + __IM uint32_t : 24; + } QK_SR_REG_b; + }; + __IM uint32_t RESERVED1; + + union { + __IM uint32_t QK_AR_REG; /*!< (@ 0x00000028) Quiddikey allow register */ + + struct { + __IM uint32_t QK_ALLOW_ENROLL : 1; /*!< [0..0] Enroll operation is allowed */ + __IM uint32_t QK_ALLOW_START : 1; /*!< [1..1] Start operation is allowed */ + __IM uint32_t QK_ALLOW_SET_KEY : 1; /*!< [2..2] Set Key operations are allowed */ + __IM uint32_t QK_ALLOW_GET_KEY : 1; /*!< [3..3] Get Key operation is allowed */ + __IM uint32_t : 3; + __IM uint32_t QK_ALLOW_BIST : 1; /*!< [7..7] BIST is allowed to be started */ + __IM uint32_t : 24; + } QK_AR_REG_b; + }; + __IM uint32_t RESERVED2[5]; + + union { + __IOM uint32_t QK_KI_REG; /*!< (@ 0x00000040) Quiddikey Key Input register */ + + struct { + __IOM uint32_t QK_KI : 32; /*!< [31..0] Key input data */ + } QK_KI_REG_b; + }; + + union { + __IOM uint32_t QK_CI_REG; /*!< (@ 0x00000044) Quiddikey Code Input register */ + + struct { + __IOM uint32_t QK_CI : 32; /*!< [31..0] AC/KC input data */ + } QK_CI_REG_b; + }; + + union { + __IM uint32_t QK_CO_REG; /*!< (@ 0x00000048) Quiddikey Code Output register */ + + struct { + __IM uint32_t QK_CO : 32; /*!< [31..0] AC/KC output data */ + } QK_CO_REG_b; + }; + + union { + __IM uint32_t QK_XO_REG; /*!< (@ 0x0000004C) Quiddikey XKPD Output register */ + + struct { + __IM uint32_t QK_XO : 32; /*!< [31..0] XKPD output data */ + } QK_XO_REG_b; + }; + __IM uint32_t RESERVED3[4]; + + union { + __IM uint32_t QK_KO_IDX_REG; /*!< (@ 0x00000060) Quiddikey Key Output Index + register */ + + struct { + __IM uint32_t qk_ko_index : 4; /*!< [3..0] Key index for the key that is currently + output via the Key Output register */ + __IM uint32_t : 28; + } QK_KO_IDX_REG_b; + }; + + union { + __IM uint32_t QK_KO_REG; /*!< (@ 0x00000064) Quiddikey Code Output register */ + + struct { + __IM uint32_t QK_KO : 32; /*!< [31..0] Key output data */ + } QK_KO_REG_b; + }; + __IM uint32_t RESERVED4[29]; + + union { + __IM uint32_t QK_IF_SR_C_REG; /*!< (@ 0x000000DC) Quiddikey Interface Status + register */ + + struct { + __IM uint32_t IF_ERROR : 1; /*!< [0..0] Clears the if_error bit */ + __IM uint32_t : 31; + } QK_IF_SR_C_REG_b; + }; + + union { + __IM uint32_t QK_IF_SR_REG; /*!< (@ 0x000000E0) Quiddikey Interface Status + register */ + + struct { + __IM uint32_t IF_ERROR : 1; /*!< [0..0] Indicates that an interface error + has occurred */ + __IM uint32_t : 31; + } QK_IF_SR_REG_b; + }; + + union { + __IOM uint32_t QK_TEST_REG; /*!< (@ 0x000000E4) QK Test register */ + + struct { + __IOM uint32_t QK_BIST_ENABLE : 1; /*!< [0..0] Isolates the iid_quiddikey + module and runs a BIST */ + __IM uint32_t : 3; + __IOM uint32_t QK_BIST_RUNNING : 1; /*!< [4..4] BIST is in progress or + finishing up */ + __IOM uint32_t QK_BIST_ACTIVE : 1; /*!< [5..5] Indicates that the BIST is + running */ + __IOM uint32_t QK_BIST_OK : 1; /*!< [6..6] Indicates that the BIST has passed */ + __IOM uint32_t QK_BIST_ERROR : 1; /*!< [7..7] Indicates that the BIST has failed */ + __IM uint32_t : 24; + } QK_TEST_REG_b; + }; + __IM uint32_t RESERVED5[6]; + + union { + __IM uint32_t QK_VER_REG; /*!< (@ 0x00000100) QK Version register */ + + struct { + __IM uint32_t QK_VERSION : 32; /*!< [31..0] Version of iid_qk */ + } QK_VER_REG_b; + }; +} IID_QK_Type; /*!< Size = 260 (0x104) */ + +/* =========================================================================================================================== + */ +/* ================ IID_RPINE + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief none (IID_RPINE) + */ + +typedef struct { /*!< (@ 0x20480400) IID_RPINE Structure */ + + union { + __IOM uint32_t IID_BIST_CTRL_REG; /*!< (@ 0x00000000) Quiddikey Control register.The + Quiddikey Control register defines which command + must be executed next. */ + + struct { + __IOM uint32_t QK_BIST_ENABLE : 1; /*!< [0..0] none */ + __IOM uint32_t AES_BIST_ENABLE : 1; /*!< [1..1] none */ + __IOM uint32_t KH_BIST_ENABLE : 1; /*!< [2..2] none */ + __IM uint32_t : 29; + } IID_BIST_CTRL_REG_b; + }; + + union { + __IOM uint32_t IID_BIST_STATUS_REG; /*!< (@ 0x00000004) none */ + + struct { + __IOM uint32_t QK_BIST_ACTIVE : 1; /*!< [0..0] none */ + __IOM uint32_t QK_BIST_ERROR : 1; /*!< [1..1] Indicates that the BIST has failed */ + __IOM uint32_t QK_BIST_OK : 1; /*!< [2..2] Indicates that the BIST has passed */ + __IOM uint32_t QK_BIST_RUNNING : 1; /*!< [3..3] Indicates that the BIST is + running */ + __IOM uint32_t AES_BIST_ACTIVE : 1; /*!< [4..4] none */ + __IOM uint32_t AES_BIST_ERROR : 1; /*!< [5..5] none */ + __IOM uint32_t AES_BIST_OK : 1; /*!< [6..6] Indicates that the BIST has passed */ + __IOM uint32_t AES_BIST_RUNNING : 1; /*!< [7..7] Indicates that the BIST + is running */ + __IOM uint32_t KH_BIST_STATUS : 1; /*!< [8..8] none */ + __IM uint32_t : 23; + } IID_BIST_STATUS_REG_b; + }; + + union { + __IOM uint32_t IID_CTRL_REG; /*!< (@ 0x00000008) none */ + + struct { + __IOM uint32_t AES_MAX_KEY_SIZE : 1; /*!< [0..0] 1 256 bit key, 0 128 bit key */ + __IOM uint32_t SOURCE_KEY_KH : 1; /*!< [1..1] When set KH will source the key to AES + engine. When this is not QK key output is + connected to AES key input */ + __IOM uint32_t LATCH_KEY_KH : 1; /*!< [2..2] When set KH will latch the key given by + QK. When this is not QK key output is connected + to AES key input */ + __IOM uint32_t KH_RESET_N : 1; /*!< [3..3] 0 KH will be in reset 1 Out of reset */ + __IOM uint32_t KH_KEY_SIZE : 1; /*!< [4..4] 0 128 bit key 1 256 bit key + This is used by KH */ + __IOM uint32_t KH_CLOCK_RATIO : 3; /*!< [7..5] Indicates the division factor to be + used for generating kh_clk. */ + __IM uint32_t : 24; + } IID_CTRL_REG_b; + }; + + union { + __IOM uint32_t WKE_CTRL_REG; /*!< (@ 0x0000000C) none */ + + struct { + __IOM uint32_t ENABLE_WKE : 1; /*!< [0..0] When WKE will be enabled. This + is a self clearing bit. + Once enabled WKE can not be + disabled till process is done */ + __IOM uint32_t WKE_KEY_SIZE : 1; /*!< [1..1] 0 128 bit size 1 256 bit size */ + __IOM uint32_t WKE_FLUSH : 1; /*!< [2..2] When set, WKE will flush out the data from + AES. When WEK is active, firmware reads to AES + engine are masked. This gets cleared once four + dwords are read from AES */ + __IOM uint32_t WKE_COMPARE : 1; /*!< [3..3] When set, WKE will compare the data from + AES engine with the data provided by firmware */ + __IOM uint32_t WKE_SET_KEY : 1; /*!< [4..4] This has to be set after key + available from AES */ + __IOM uint32_t KEY_CODE_DONE : 1; /*!< [5..5] This has to be set after + reading key code */ + __IM uint32_t : 26; + } WKE_CTRL_REG_b; + }; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t IID_AES_CTRL_REG; /*!< (@ 0x00000014) none */ + + struct { + __IOM uint32_t KEY_REQ_IN_DMA_PATH : 1; /*!< [0..0] Include key req in dma path. With + this KEY Also can be loaded using DMA. */ + __IOM uint32_t AES_MAX_KEY_SIZE_FRM_REG : 1; /*!< [1..1] This is valid + only when + aes_max_key_size_frm_reg_en + is set. */ + __IOM uint32_t AES_MAX_KEY_SIZE_FRM_REG_EN : 1; /*!< [2..2] When set, WKE will flush + out the data from AES. When WEK is + active, firmware reads to AES engine + are masked. This gets cleared once + four dwords are read from AES */ + __IOM uint32_t OTP_KEY_LOADING : 1; /*!< [3..3] When set, WKE will compare + the data from AES engine with the + data provided by firmware */ + __IM uint32_t : 28; + } IID_AES_CTRL_REG_b; + }; + + union { + __IM uint32_t IID_AES_STS_REG; /*!< (@ 0x00000018) none */ + + struct { + __IM uint32_t DIN_FIFO_FULL : 1; /*!< [0..0] Input data fifo full indication */ + __IM uint32_t DOUT_FIFO_EMPTY : 1; /*!< [1..1] Output data fifo empty + indication */ + __IM uint32_t : 30; + } IID_AES_STS_REG_b; + }; + __IM uint32_t RESERVED1; + + union { + __IOM uint32_t WKE_STATUS_REG; /*!< (@ 0x00000020) none */ + + struct { + __IOM uint32_t WKE_ACTIVE : 1; /*!< [0..0] Will be high when WKE is active */ + __IOM uint32_t WKE_KEY_FEED_IN_PROGRESS : 1; /*!< [1..1] Will be high when WKE is + feeding key to AES engine */ + __IOM uint32_t WKE_FLUSH_IN_PROGRESS : 1; /*!< [2..2] Will be high when WKE flushing + out the data from AES */ + __IOM uint32_t WKE_COMPARE_IN_PROGRESS : 1; /*!< [3..3] Will be high when WKE is + comparing the data from AES */ + __IOM uint32_t WKE_SET_KEY_IN_PROGRESS : 1; /*!< [4..4] Will be high when WKE is + doing set key operation with QK */ + __IOM uint32_t WKE_KEY_READY : 1; /*!< [5..5] Firmware has to load the + authentication, which will be + compared with AES output, when this + bit is low */ + __IOM uint32_t WKE_CMP_DATA_READY : 1; /*!< [6..6] Firmware has to load + the authentication, which will + be compared with AES output, + when this bit is low */ + __IOM uint32_t WKE_COMPARE_FAIL : 1; /*!< [7..7] This bit will be set when + authentication data comparison fails */ + __IM uint32_t : 24; + } WKE_STATUS_REG_b; + }; + __IM uint32_t RESERVED2; + __IOM uint32_t WKE_DATA_REG; /*!< (@ 0x00000028) none */ +} IID_RPINE_Type; /*!< Size = 44 (0x2c) */ + +/* =========================================================================================================================== + */ +/* ================ CT0 + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief Configurable timer is used in counting clocks, events and states with + reference clock external clock and system clock (CT0) + */ + +typedef struct { /*!< (@ 0x45060000) CT0 Structure */ + + union { + __IOM uint32_t CT_GEN_CTRL_SET_REG; /*!< (@ 0x00000000) General control set + register */ + + struct { + __IOM uint32_t COUNTER_IN_32_BIT_MODE : 1; /*!< [0..0] Counter_1 and Counter_0 will + be merged and used as a single 32 bit + counter */ + __IOM uint32_t SOFT_RESET_COUNTER_0_FRM_REG : 1; /*!< [1..1] This is applied to 32 + bits of counter only when the + counter is in 32 bit counter mode + otherwise this will be applied + to only lower 16 bits of + counter */ + __IOM uint32_t PERIODIC_EN_COUNTER_0_FRM_REG : 1; /*!< [2..2] This is applied to 32 + bits of counter only when the + counter is in 32 bit counter + mode otherwise this will be + applied + to only lower 16 bits of + counter */ + __IOM uint32_t COUNTER_0_TRIG_FRM_REG : 1; /*!< [3..3] This enables the + counter to run/active */ + __IOM uint32_t COUNTER_0_UP_DOWN : 2; /*!< [5..4] This enables the counter to run in + up/down/up-down/down-up directions */ + __IOM uint32_t COUNTER_0_SYNC_TRIG : 1; /*!< [6..6] This is applied to 32 bits of + counter only when the counter is in 32 bit + counter mode otherwise this will be + applied to only lower 16 bits of counter. + This enables the counter to run/active + when sync is found. */ + __IOM uint32_t BUF_REG_0_EN : 1; /*!< [7..7] Buffer register gets enabled + for MATCH REG. MATCH_BUF_REG is always + available and whenever this bit is set + only, gets copied to MATCH REG. */ + __IOM uint32_t RESERVED1 : 9; /*!< [16..8] Reserved1 */ + __IOM uint32_t SOFT_RESET_COUNTER_1_FRM_REG : 1; /*!< [17..17] This resets the + counter on the write */ + __IOM uint32_t PERIODIC_EN_COUNTER_1_FRM_REG : 1; /*!< [18..18] This resets the + counter on the write */ + __IOM uint32_t COUNTER_1_TRIG_FRM : 1; /*!< [19..19] This enables the + counter to run/active */ + __IOM uint32_t COUNTER_1_UP_DOWN : 2; /*!< [21..20] This enables the counter to run + in upward direction */ + __IOM uint32_t COUNTER_1_SYNC_TRIG : 1; /*!< [22..22] This is applied to 32 bits of + counter only when the counter is in 32 bit + counter mode otherwise this will be + applied to only lower 16 bits of + counter. This enables the counter to + run/active when sync is found. */ + __IOM uint32_t BUF_REG_1_EN : 1; /*!< [23..23] Buffer register gets enabled for MATCH + REG. MATCH_BUF_REG is always available and + whenever this bit is set only, gets copied to + MATCH REG. */ + __IOM uint32_t RESERVED2 : 8; /*!< [31..24] Reserved2 */ + } CT_GEN_CTRL_SET_REG_b; + }; + + union { + __IOM uint32_t CT_GEN_CTRL_RESET_REG; /*!< (@ 0x00000004) General control + reset register */ + + struct { + __IOM uint32_t COUNTER_IN_32_BIT_MODE : 1; /*!< [0..0] Counter_1 and Counter_0 will + be merged and used as a single 32 bit + counter */ + __IM uint32_t RESERVED1 : 1; /*!< [1..1] Reserved1 */ + __IOM uint32_t PERIODIC_EN_COUNTER_0_FRM_REG : 1; /*!< [2..2] This is applied to 32 + bits of counter only when the + counter is in 32 bit counter + mode otherwise this will be + applied + to only lower 16 bits of + counter */ + __IM uint32_t RESERVED2 : 1; /*!< [3..3] Reserved2 */ + __IOM uint32_t COUNTER_0_UP_DOWN : 2; /*!< [5..4] This enables the counter to run in + up/down/up-down/down-up directions */ + __IM uint32_t RESERVED3 : 1; /*!< [6..6] Reserved3 */ + __IOM uint32_t BUF_REG_0_EN : 1; /*!< [7..7] Buffer register gets enabled + for MATCH REG. MATCH_BUF_REG is always + available and whenever this bit is set + only, gets copied to MATCH REG. */ + __IM uint32_t RESERVED4 : 9; /*!< [16..8] Reserved4 */ + __IM uint32_t RESERVED5 : 1; /*!< [17..17] Reserved5 */ + __IOM uint32_t PERIODIC_EN_COUNTER_1_FRM_REG : 1; /*!< [18..18] This resets the + counter on the write */ + __IM uint32_t RESERVED6 : 1; /*!< [19..19] Reserved6 */ + __IOM uint32_t COUNTER_1_UP_DOWN : 2; /*!< [21..20] This enables the counter to run + in upward direction */ + __IM uint32_t RESERVED7 : 1; /*!< [22..22] Reserved7 */ + __IOM uint32_t BUF_REG_1_EN : 1; /*!< [23..23] Buffer register gets enabled for MATCH + REG. MATCH_BUF_REG is always available and + whenever this bit is set only, gets copied to + MATCH REG. */ + __IM uint32_t RESERVED8 : 8; /*!< [31..24] Reserved8 */ + } CT_GEN_CTRL_RESET_REG_b; + }; + + union { + __IM uint32_t CT_INTR_STS; /*!< (@ 0x00000008) Interrupt status */ + + struct { + __IM uint32_t INTR_0_L : 1; /*!< [0..0] Indicates the FIFO full signal of + channel-0 */ + __IM uint32_t FIFO_0_FULL_L : 1; /*!< [1..1] Indicates the FIFO full + signal of channel-0 */ + __IM uint32_t COUNTER_0_IS_ZERO_L : 1; /*!< [2..2] Counter 0 hit zero in + active mode. */ + __IM uint32_t COUNTER_0_IS_PEAK_L : 1; /*!< [3..3] Counter 0 hit peak + (MATCH) in active mode. */ + __IM uint32_t RESERVED1 : 12; /*!< [15..4] Reserved1 */ + __IM uint32_t INTR_1_L : 1; /*!< [16..16] Indicates the FIFO full signal + of channel-1 */ + __IM uint32_t FIFO_1_FULL_L : 1; /*!< [17..17] Indicates the FIFO full + signal of channel-1 */ + __IM uint32_t COUNTER_1_IS_ZERO_L : 1; /*!< [18..18] Counter 1 hit zero in + active mode. */ + __IM uint32_t COUNTER_1_IS_PEAK_L : 1; /*!< [19..19] Counter 1 hit peak + (MATCH) in active mode. */ + __IM uint32_t RESERVED2 : 12; /*!< [31..20] Reserved2 */ + } CT_INTR_STS_b; + }; + + union { + __IOM uint32_t CT_INTR_MASK; /*!< (@ 0x0000000C) Interrupts mask */ + + struct { + __IOM uint32_t INTR_0_L : 1; /*!< [0..0] Interrupt mask signal. */ + __IOM uint32_t FIFO_0_FULL_L : 1; /*!< [1..1] Interrupt mask signal. */ + __IOM uint32_t COUNTER_0_IS_ZERO_L : 1; /*!< [2..2] Interrupt mask signal. */ + __IOM uint32_t COUNTER_0_IS_PEAK_L : 1; /*!< [3..3] Interrupt mask signal. */ + __IOM uint32_t RESERVED1 : 12; /*!< [15..4] Reserved1 */ + __IOM uint32_t INTR_1_L : 1; /*!< [16..16] Interrupt mask signal. */ + __IOM uint32_t FIFO_1_FULL_L : 1; /*!< [17..17] Interrupt mask signal. */ + __IOM uint32_t COUNTER_1_IS_ZERO_L : 1; /*!< [18..18] Interrupt mask signal. */ + __IOM uint32_t COUNTER_1_IS_PEAK_L : 1; /*!< [19..19] Interrupt mask signal. */ + __IOM uint32_t RESERVED2 : 12; /*!< [31..20] Reserved2 */ + } CT_INTR_MASK_b; + }; + + union { + __IOM uint32_t CT_INTER_UNMASK; /*!< (@ 0x00000010) Interrupts unmask */ + + struct { + __IOM uint32_t INTR_0_L : 1; /*!< [0..0] Interrupt unmask signal. */ + __IOM uint32_t FIFO_0_FULL_L : 1; /*!< [1..1] Interrupt unmask signal. */ + __IOM uint32_t COUNTER_0_IS_ZERO_L : 1; /*!< [2..2] Interrupt unmask signal. */ + __IOM uint32_t COUNTER_0_IS_PEAK_L : 1; /*!< [3..3] Interrupt unmask signal. */ + __IM uint32_t RESERVED1 : 12; /*!< [15..4] Reserved1 */ + __IOM uint32_t INTR_1_L : 1; /*!< [16..16] Interrupt unmask signal. */ + __IOM uint32_t FIFO_1_FULL_L : 1; /*!< [17..17] Interrupt unmask signal */ + __IOM uint32_t COUNTER_1_IS_ZERO_L : 1; /*!< [18..18] Interrupt unmask signal. */ + __IOM uint32_t COUNTER_1_IS_PEAK_L : 1; /*!< [19..19] Interrupt unmask signal. */ + __IM uint32_t RESERVED2 : 12; /*!< [31..20] Reserved2 */ + } CT_INTER_UNMASK_b; + }; + + union { + __IOM uint32_t CT_INTR_ACK; /*!< (@ 0x00000014) Interrupt clear/ack register */ + + struct { + __IOM uint32_t INTR_0_L : 1; /*!< [0..0] Interrupt ack signal. */ + __IOM uint32_t FIFO_0_FULL_L : 1; /*!< [1..1] Interrupt ack signal. */ + __IOM uint32_t COUNTER_0_IS_ZERO_L : 1; /*!< [2..2] Interrupt ack signal. */ + __IOM uint32_t COUNTER_0_IS_PEAK_L : 1; /*!< [3..3] Interrupt ack signal. */ + __IM uint32_t RESERVED1 : 12; /*!< [15..4] Reserved1 */ + __IOM uint32_t INTR_1_L : 1; /*!< [16..16] Interrupt ack signal. */ + __IOM uint32_t FIFO_1_FULL_L : 1; /*!< [17..17] Interrupt ack signal. */ + __IOM uint32_t COUNTER_1_IS_ZERO_L : 1; /*!< [18..18] Interrupt ack signal. */ + __IOM uint32_t COUNTER_1_IS_PEAK_L : 1; /*!< [19..19] Interrupt ack signal. */ + __IOM uint32_t RESERVED2 : 12; /*!< [31..20] Reserved2 */ + } CT_INTR_ACK_b; + }; + + union { + __IOM uint32_t CT_MATCH_REG; /*!< (@ 0x00000018) Match value register */ + + struct { + __IOM uint32_t COUNTER_0_MATCH : 16; /*!< [15..0] This will be used as + lower match */ + __IOM uint32_t COUNTER_1_MATCH : 16; /*!< [31..16] This will be used as + upper match */ + } CT_MATCH_REG_b; + }; + + union { + __IOM uint32_t CT_MATCH_BUF_REG; /*!< (@ 0x0000001C) Match Buffer register */ + + struct { + __IOM uint32_t COUNTER_0_MATCH_BUF : 16; /*!< [15..0] This gets copied to MATCH + register if bug_reg_0_en is set. Copying + is done when counter 0 is active and hits + 0. */ + __IOM uint32_t COUNTER_1_MATCH_BUF : 16; /*!< [31..16] This gets copied to MATCH + register if bug_reg_1_en is set. Copying + is done when counter 1 is active and hits + 0. */ + } CT_MATCH_BUF_REG_b; + }; + + union { + __IM uint32_t CT_CAPTURE_REG; /*!< (@ 0x00000020) Capture Register */ + + struct { + __IM uint32_t COUNTER_0_CAPTURE : 16; /*!< [15..0] This is a latched value of + counter lower part when the selected + capture_event occurs */ + __IM uint32_t COUNTER_1_CAPTURE : 16; /*!< [31..16] This is a latched value of + counter upper part when the selected + capture_event occurs */ + } CT_CAPTURE_REG_b; + }; + + union { + __IOM uint32_t CT_COUNTER_REG; /*!< (@ 0x00000024) Counter Register */ + + struct { + __IM uint32_t COUNTER0 : 16; /*!< [15..0] This holds the value of counter-0 */ + __IM uint32_t COUNTER1 : 16; /*!< [31..16] This holds the value of counter-1 */ + } CT_COUNTER_REG_b; + }; + + union { + __IOM uint32_t CT_OCU_CTRL_REG; /*!< (@ 0x00000028) OCU control register */ + + struct { + __IOM uint32_t OUTPUT_IS_OCU_0 : 1; /*!< [0..0] Indicates whether the output is in + OCU mode or not for channel-0 */ + __IOM uint32_t SYNC_WITH_0 : 3; /*!< [3..1] Indicates whether the other channel is in + sync with this channel */ + __IOM uint32_t OCU_0_DMA_MODE : 1; /*!< [4..4] Indicates whether the OCU DMA mode is + active or not for channel 0 */ + __IOM uint32_t OCU_0_MODE_8_16 : 1; /*!< [5..5] Indicates whether entire 16 bits or + only 8-bits of the channel 0 are used in OCU + mode */ + __IOM uint32_t MAKE_OUTPUT_0_HIGH_SEL : 3; /*!< [8..6] Check counter ocus for + possibilities. When this is hit + output will be made high. */ + __IOM uint32_t MAKE_OUTPUT_0_LOW_SEL : 3; /*!< [11..9] Check counter ocus for + possibilities. When this is hit output + will be made low. */ + __IOM uint32_t RESERVED1 : 4; /*!< [15..12] Reserved1 */ + __IOM uint32_t OUTPUT_1_IS_OCU : 1; /*!< [16..16] Indicates whether the output is in + OCU mode or not for channel 1 */ + __IOM uint32_t SYNC_WITH_1 : 3; /*!< [19..17] Indicates whether the other channel is + in sync with this channel */ + __IOM uint32_t OCU_1_DMA_MODE : 1; /*!< [20..20] Indicates whether the OCU DMA mode + is active or not for channel 1 */ + __IOM uint32_t OCU_1_MODE_8_16_MODE : 1; /*!< [21..21] Indicates whether entire 16 + bits or only 8-bits of + the channel 1 are used in OCU mode */ + __IOM uint32_t MAKE_OUTPUT_1_HIGH_SEL : 3; /*!< [24..22] Check counter ocus for + possibilities. When this is + hit output will be made high. */ + __IOM uint32_t MAKE_OUTPUT_1_LOW_SEL : 3; /*!< [27..25] Check counter ocus for + possibilities. When this is hit output + will be made low. */ + __IOM uint32_t RESERVED2 : 4; /*!< [31..28] Reserved2 */ + } CT_OCU_CTRL_REG_b; + }; + + union { + __IOM uint32_t CT_OCU_COMPARE_REG; /*!< (@ 0x0000002C) OCU Compare Register */ + + struct { + __IOM uint32_t OCU_COMPARE_0_REG : 16; /*!< [15..0] Holds the threshold value of + present OCU period which denotes the number + of clock cycles for which the OCU output + should be considered (counter 0) */ + __IOM uint32_t OCU_COMPARE_1_REG : 16; /*!< [31..16] Holds the threshold value of + present OCU period which denotes the number + of clock cycles for which the OCU output + should be considered (counter 1) */ + } CT_OCU_COMPARE_REG_b; + }; + + union { + __IOM uint32_t CT_OCU_COMPARE2_REG; /*!< (@ 0x00000030) OCU Compare2 Register */ + + struct { + __IOM uint32_t OCU_COMPARE2_0_REG : 16; /*!< [15..0] Holds the threshold + value of present OCU period2 + which denotes the number of + clock cycles for which the OCU + output should be considered + (counter 0) */ + __IOM uint32_t OCU_COMPARE2_1_REG : 16; /*!< [31..16] Holds the threshold + value of present OCU period2 + which denotes the number of + clock cycles for which the OCU + output should be considered + (counter 1) */ + } CT_OCU_COMPARE2_REG_b; + }; + + union { + __IOM uint32_t CT_OCU_SYNC_REG; /*!< (@ 0x00000034) OCU Synchronization Register */ + + struct { + __IOM uint32_t OCU_SYNC_CHANNEL0_REG : 16; /*!< [15..0] Starting point of channel 0 + for synchronization purpose */ + __IOM uint32_t OCU_SYNC_CHANNEL1_REG : 16; /*!< [31..16] Starting point of channel 1 + for synchronization purpose */ + } CT_OCU_SYNC_REG_b; + }; + + union { + __IOM uint32_t CT_OCU_COMPARE_NXT_REG; /*!< (@ 0x00000038) PWM compare next + register */ + + struct { + __IOM uint32_t OCU_COMPARE_NXT_COUNTER1 : 16; /*!< [15..0] OCU output should be high + for counter 1 */ + __IOM uint32_t OCU_COMPARE_NXT_COUNTER0 : 16; /*!< [31..16] PWM output should be high + for counter 0 */ + } CT_OCU_COMPARE_NXT_REG_b; + }; + + union { + __IOM uint32_t CT_WFG_CTRL_REG; /*!< (@ 0x0000003C) WFG control register */ + + struct { + __IOM uint32_t MAKE_OUTPUT_0_TGL_0_SEL : 3; /*!< [2..0] Check the counter ocus + possibilities for description for + channel 0. */ + __IOM uint32_t MAKE_OUTPUT_0_TGL_1_SEL : 3; /*!< [5..3] Check the counter ocus + possibilities for description for + channel 0. */ + __IOM uint32_t RESERVED1 : 2; /*!< [7..6] Reserved1 */ + __IOM uint32_t WFG_TGL_CNT_0_PEAK : 8; /*!< [15..8] WFG mode output toggle + count clock for channel 0. */ + __IOM uint32_t MAKE_OUTPUT_1_TGL_0_SEL : 3; /*!< [18..16] Check the counter ocus + possibilities for description for + channel 1. */ + __IOM uint32_t MAKE_OUTPUT_1_TGL_1_SEL : 3; /*!< [21..19] Check the counter ocus + possibilities for description for + channel 1. */ + __IOM uint32_t RESERVED2 : 2; /*!< [23..22] Reserved2 */ + __IOM uint32_t WFG_TGL_CNT_1_PEAK : 8; /*!< [31..24] WFG mode output toggle count + clock for channel 1 */ + } CT_WFG_CTRL_REG_b; + }; + + union { + __IOM uint32_t CT_OCU_COMPARE2_NXT_REG; /*!< (@ 0x00000040) PWM compare next + register */ + + struct { + __IOM uint32_t OCU_COMPARE2_NXT_COUNTER0 : 16; /*!< [15..0] OCU output should be high + for counter 1 */ + __IOM uint32_t OCU_COMPARE2_NXT_COUNTER1 : 16; /*!< [31..16] PWM output should be + high for counter 0 */ + } CT_OCU_COMPARE2_NXT_REG_b; + }; + __IM uint32_t RESERVED[3]; + + union { + __IOM uint32_t CT_START_COUNTER_EVENT_SEL; /*!< (@ 0x00000050) Start counter + event select register */ + + struct { + __IOM uint32_t START_COUNTER_0_EVENT_SEL : 6; /*!< [5..0] For two 16 bit counters + mode: Event select for starting the + Counter 0 For 32 bit counter mode: + Event select for starting counter */ + __IOM uint32_t RESERVED1 : 10; /*!< [15..6] Reserved1 */ + __IOM uint32_t START_COUNTER_1_EVENT_SEL : 6; /*!< [21..16] For two 16 bit counters + mode: Event select for starting the + Counter 1. For 32 bit counter mode: + Invalid. Please refer to events + table for description */ + __IM uint32_t RESERVED2 : 10; /*!< [31..22] Reserved2 */ + } CT_START_COUNTER_EVENT_SEL_b; + }; + + union { + __IOM uint32_t CT_START_COUNTER_AND_EVENT; /*!< (@ 0x00000054) Start counter + AND event register */ + + struct { + __IOM uint32_t START_COUNTER_0_AND_EVENT : 4; /*!< [3..0] For two 16 bit counter + mode: AND expression valids for AND + event in start Counter 0 event For 32 + bit counter mode + AND expression valids for AND event in + start counter event */ + __IOM uint32_t RESERVED1 : 4; /*!< [7..4] Reserved1 */ + __IOM uint32_t START_COUNTER_0_AND_VLD : 4; /*!< [11..8] none */ + __IM uint32_t RESERVED2 : 4; /*!< [15..12] Reserved2 */ + __IOM uint32_t START_COUNTER_1_AND_EVENT : 4; /*!< [19..16] For two 16 bit counters + mode: AND expression valids for AND + event in start counter event For 32 + bit counter mode : Invalid */ + __IM uint32_t RESERVED3 : 4; /*!< [23..20] Reserved3 */ + __IOM uint32_t START_COUNTER_1_AND_VLD : 4; /*!< [27..24] none */ + __IM uint32_t RESERVED4 : 4; /*!< [31..28] Reserved4 */ + } CT_START_COUNTER_AND_EVENT_b; + }; + + union { + __IOM uint32_t CT_START_COUNTER_OR_EVENT; /*!< (@ 0x00000058) Start counter + OR event register */ + + struct { + __IOM uint32_t START_COUNTER_0_OR_EVENT : 4; /*!< [3..0] For two 16 bit counter mode: + OR expression valids for OR event in + start Counter 0 event For 32 bit + counter mode + OR expression valids for OR event in + start counter event */ + __IOM uint32_t RESERVED1 : 4; /*!< [7..4] Reserved1 */ + __IOM uint32_t START_COUNTER_0_OR_VLD : 4; /*!< [11..8] none */ + __IOM uint32_t RESERVED2 : 4; /*!< [15..12] Reserved2 */ + __IOM uint32_t START_COUNTER_1_OR_EVENT : 4; /*!< [19..16] For two 16 bit counters + mode: OR expression valids for OR + event in start counter event For 32 + bit counter mode : Invalid. */ + __IM uint32_t RESERVED3 : 4; /*!< [23..20] Reserved3 */ + __IOM uint32_t START_COUNTER_1_OR_VLD : 4; /*!< [27..24] none */ + __IM uint32_t RESERVED4 : 4; /*!< [31..28] Reserved4 */ + } CT_START_COUNTER_OR_EVENT_b; + }; + + union { + __IOM uint32_t CT_CONTINUE_COUNTER_EVENT_SEL; /*!< (@ 0x0000005C) Continue counter + event select register */ + + struct { + __IOM uint32_t CONTINUE_COUNTER_0_EVENT_SEL : 6; /*!< [5..0] For two 16 bit counters + mode: Event select for continuing + the Counter 0 For 32 bit + counter mode: Event select for + continuing counter */ + __IOM uint32_t RESERVED1 : 10; /*!< [15..6] Reserved1 */ + __IOM uint32_t CONTINUE_COUNTER_1_EVENT_SEL : 6; /*!< [21..16] For two 16 bit + counters mode: Event select for + continuing + the Counter 1 For 32 bit + counter mode: Invalid. */ + __IM uint32_t RESERVED2 : 10; /*!< [31..22] Reserved2 */ + } CT_CONTINUE_COUNTER_EVENT_SEL_b; + }; + + union { + __IOM uint32_t CT_CONTINUE_COUNTER_AND_EVENT; /*!< (@ 0x00000060) Continue counter AND + event register */ + + struct { + __IOM uint32_t CONTINUE_COUNTER_0_AND_EVENT : 4; /*!< [3..0] For two 16 bit counter + mode: AND expression valids for + AND event in continue + Counter 0 event For 32 bit + counter mode AND expression + valids for AND event in continue + counter event. */ + __IOM uint32_t RESERVED1 : 4; /*!< [7..4] Reserved1 */ + __IOM uint32_t CONTINUE_COUNTER_0_AND_VLD : 4; /*!< [11..8] none */ + __IOM uint32_t RESERVED2 : 4; /*!< [15..12] Reserved2 */ + __IOM uint32_t CONTINUE_COUNTER_1_AND_EVENT : 4; /*!< [19..16] For two 16 bit + counters mode: AND expression + valids for AND event in continue + counter event For 32 bit counter + mode : Invalid */ + __IM uint32_t RESERVED3 : 4; /*!< [23..20] Reserved3 */ + __IOM uint32_t CONTINUE_COUNTER_1_AND_VLD : 4; /*!< [27..24] none */ + __IM uint32_t RESERVED4 : 4; /*!< [31..28] Reserved4 */ + } CT_CONTINUE_COUNTER_AND_EVENT_b; + }; + + union { + __IOM uint32_t CT_CONTINUE_COUNTER_OR_EVENT; /*!< (@ 0x00000064) Continue counter OR + event register */ + + struct { + __IOM uint32_t CONTINUE_COUNTER_0_OR_EVENT : 4; /*!< [3..0] For two 16 bit counter + mode: OR expression valids for OR + event in continue Counter 0 event For + 32 bit counter mode OR expression + valids for OR event in continue + counter event */ + __IOM uint32_t RESERVED1 : 4; /*!< [7..4] Reserved1 */ + __IOM uint32_t CONTINUE_COUNTER_0_OR_VLD : 4; /*!< [11..8] none */ + __IOM uint32_t RESERVED2 : 4; /*!< [15..12] Reserved2 */ + __IOM uint32_t CONTINUE_COUNTER_1_OR_EVENT : 4; /*!< [19..16] For two 16 bit counters + mode: OR expression valids for OR + event in continue counter event For + 32 bit counter mode : Invalid */ + __IM uint32_t RESERVED3 : 4; /*!< [23..20] Reserved3 */ + __IOM uint32_t CONTINUE_COUNTER_1_OR_VLD : 4; /*!< [27..24] none */ + __IM uint32_t RESERVED4 : 4; /*!< [31..28] Reserved4 */ + } CT_CONTINUE_COUNTER_OR_EVENT_b; + }; + + union { + __IOM uint32_t CT_STOP_COUNTER_EVENT_SEL; /*!< (@ 0x00000068) Stop counter + event select register */ + + struct { + __IOM uint32_t STOP_COUNTER_0_EVENT_SEL : 6; /*!< [5..0] For two 16 bit counters + mode: Event select for Stopping the + Counter 0 For 32 bit counter mode: + Event select for Stopping counter */ + __IOM uint32_t RESERVED1 : 10; /*!< [15..6] Reserved1 */ + __IOM uint32_t STOP_COUNTER_1_EVENT_SEL : 6; /*!< [21..16] For two 16 bit counters + mode: Event select for Stopping the + Counter 1 For 32 bit counter mode: + Invalid */ + __IM uint32_t RESERVED2 : 10; /*!< [31..22] Reserved2 */ + } CT_STOP_COUNTER_EVENT_SEL_b; + }; + + union { + __IOM uint32_t CT_STOP_COUNTER_AND_EVENT; /*!< (@ 0x0000006C) Stop counter + AND event register */ + + struct { + __IOM uint32_t STOP_COUNTER_0_AND_EVENT : 4; /*!< [3..0] For two 16 bit counter mode: + AND expression valids for AND event in + stop Counter 0 event For 32 bit + counter mode + AND expression valids for AND event in + stop counter event */ + __IOM uint32_t RESERVED1 : 4; /*!< [7..4] Reserved1 */ + __IOM uint32_t STOP_COUNTER_0_AND_VLD : 4; /*!< [11..8] Indicates which + bits in 3:0 are valid for + considering AND event */ + __IOM uint32_t RESERVED2 : 4; /*!< [15..12] Reserved2 */ + __IOM uint32_t STOP_COUNTER_1_AND_EVENT : 4; /*!< [19..16] For two 16 bit counters + mode: AND expression valids for AND + event in stop counter event For 32 bit + counter mode : Invalid */ + __IM uint32_t RESERVED3 : 4; /*!< [23..20] Reserved3 */ + __IOM uint32_t STOP_COUNTER_1_AND_VLD : 4; /*!< [27..24] none */ + __IM uint32_t RESERVED4 : 4; /*!< [31..28] Reserved4 */ + } CT_STOP_COUNTER_AND_EVENT_b; + }; + + union { + __IOM uint32_t CT_STOP_COUNTER_OR_EVENT; /*!< (@ 0x00000070) Stop counter OR + event register */ + + struct { + __IOM uint32_t STOP_COUNTER_0_OR_EVENT : 4; /*!< [3..0] For two 16 bit counter mode: + OR expression valids for OR event in + Stop Counter 0 event For 32 bit + counter mode + OR expression valids for OR event in + Stop counter event */ + __IOM uint32_t RESERVED1 : 4; /*!< [7..4] Reserved1 */ + __IOM uint32_t STOP_COUNTER_0_OR_VLD : 4; /*!< [11..8] none */ + __IOM uint32_t RESERVED2 : 4; /*!< [15..12] Reserved2 */ + __IOM uint32_t STOP_COUNTER_1_OR_EVENT : 4; /*!< [19..16] For two 16 bit counters + mode: OR expression valids for OR + event in Stop counter event For 32 bit + counter mode : Invalid */ + __IM uint32_t RESERVED3 : 4; /*!< [23..20] Reserved3 */ + __IOM uint32_t STOP_COUNTER_1_OR_VLD : 4; /*!< [27..24] none */ + __IM uint32_t RESERVED4 : 4; /*!< [31..28] Reserved4 */ + } CT_STOP_COUNTER_OR_EVENT_b; + }; + + union { + __IOM uint32_t CT_HALT_COUNTER_EVENT_SEL; /*!< (@ 0x00000074) Halt counter + event select register */ + + struct { + __IOM uint32_t HALT_COUNTER_0_EVENT_SEL : 6; /*!< [5..0] For two 16 bit counters + mode: Event select for Halting the + Counter 0 For 32 bit counter mode: + Event select for Halting counter */ + __OM uint32_t RESUME_FROM_HALT_COUNTER_0 : 1; /*!< [6..6] For two 16 bit counters + mode: Event select for Halting the + Counter 0 For 32 bit counter mode: + Event select for Halting counter */ + __IM uint32_t RESERVED1 : 9; /*!< [15..7] Reserved1 */ + __IOM uint32_t HALT_COUNTER_1_EVENT_SEL : 6; /*!< [21..16] For two 16 bit counters + mode: Event select for Halting the + Counter 1 For 32 bit counter mode: + Invalid */ + __OM uint32_t RESUME_FROM_HALT_COUNTER_1 : 1; /*!< [22..22] For two 16 bit + counters mode: Event select for + Halting the Counter 0 For 32 + bit counter mode: Event select + for Halting counter */ + __IM uint32_t RESERVED2 : 9; /*!< [31..23] Reserved2 */ + } CT_HALT_COUNTER_EVENT_SEL_b; + }; + + union { + __IOM uint32_t CT_HALT_COUNTER_AND_EVENT; /*!< (@ 0x00000078) Halt counter + AND event register */ + + struct { + __IOM uint32_t HALT_COUNTER_0_AND_EVENT : 4; /*!< [3..0] For two 16 bit counter mode: + AND expression valids for AND event in + stop Counter 0 event For 32 bit + counter mode + AND expression valids for AND event in + stop counter event */ + __IOM uint32_t RESERVED1 : 4; /*!< [7..4] Reserved1 */ + __IOM uint32_t HALT_COUNTER_0_AND_VLD : 4; /*!< [11..8] Indicates which + bits in 3:0 are valid for + considering AND event */ + __IM uint32_t RESERVED2 : 4; /*!< [15..12] Reserved2 */ + __IOM uint32_t HALT_COUNTER_1_AND_EVENT : 4; /*!< [19..16] For two 16 bit counters + mode: AND expression valids for AND + event in stop counter event For 32 bit + counter mode : Invalid */ + __IM uint32_t RESERVED3 : 4; /*!< [23..20] Reserved3 */ + __IOM uint32_t HALT_COUNTER_1_AND_VLD : 4; /*!< [27..24] none */ + __IM uint32_t RESERVED4 : 4; /*!< [31..28] Reserved4 */ + } CT_HALT_COUNTER_AND_EVENT_b; + }; + + union { + __IOM uint32_t CT_HALT_COUNTER_OR_EVENT; /*!< (@ 0x0000007C) Halt counter OR + event register */ + + struct { + __IOM uint32_t HALT_COUNTER_0_OR_EVENT : 4; /*!< [3..0] For two 16 bit counter mode: + OR expression valids for OR event in + Halt Counter 0 event For 32 bit + counter mode + OR expression valids for OR event in + Halt counter event */ + __IOM uint32_t RESERVED1 : 4; /*!< [7..4] Reserved1 */ + __IOM uint32_t HALT_COUNTER_0_OR_VLD : 4; /*!< [11..8] none */ + __IM uint32_t RESERVED2 : 4; /*!< [15..12] Reserved2 */ + __IOM uint32_t HALT_COUNTER_1_OR_EVENT : 4; /*!< [19..16] For two 16 bit counters + mode: OR expression valids for OR + event in Halt counter event For 32 bit + counter mode : Invalid */ + __IM uint32_t RESERVED3 : 4; /*!< [23..20] Reserved3 */ + __IOM uint32_t HALT_COUNTER_1_OR_VLD : 4; /*!< [27..24] none */ + __IM uint32_t RESERVED4 : 4; /*!< [31..28] Reserved4 */ + } CT_HALT_COUNTER_OR_EVENT_b; + }; + + union { + __IOM uint32_t CT_INCREMENT_COUNTER_EVENT_SEL; /*!< (@ 0x00000080) Increment counter + event select register */ + + struct { + __IOM uint32_t INCREMENT_COUNTER_0_EVENT_SEL : 6; /*!< [5..0] For two 16 bit counters + mode: Event select for + Incrementing the Counter 0 For + 32 bit counter mode: Event + select for + Incrementing counter */ + __IM uint32_t RESERVED1 : 10; /*!< [15..6] Reserved1 */ + __IOM uint32_t INCREMENT_COUNTER_1_EVENT_SEL : 6; /*!< [21..16] For two 16 + bit counters mode: + Event select for + Incrementing the + Counter 1 For 32 bit + counter mode: Invalid + */ + __IM uint32_t RESERVED2 : 10; /*!< [31..22] Reserved2 */ + } CT_INCREMENT_COUNTER_EVENT_SEL_b; + }; + + union { + __IOM uint32_t CT_INCREMENT_COUNTER_AND_EVENT; /*!< (@ 0x00000084) Increment counter + AND event register */ + + struct { + __IOM uint32_t INCREMENT_COUNTER_0_AND_EVENT : 4; /*!< [3..0] For two 16 bit counter + mode: AND expression valids for + AND event in stop Counter + 0 event For 32 bit counter mode + AND expression valids for + AND event in stop counter event + */ + __IOM uint32_t RESERVED1 : 4; /*!< [7..4] Reserved1 */ + __IOM uint32_t INCREMENT_COUNTER_0_AND_VLD : 4; /*!< [11..8] none */ + __IM uint32_t RESERVED2 : 4; /*!< [15..12] Reserved2 */ + __IOM uint32_t INCREMENT_COUNTER_1_AND_EVENT : 4; /*!< [19..16] For two 16 bit + counters mode: AND expression + valids for AND event in stop + counter event For 32 bit counter + mode : Invalid */ + __IM uint32_t RESERVED3 : 4; /*!< [23..20] Reserved3 */ + __IOM uint32_t INCREMENT_COUNTER_1_AND_VLD : 4; /*!< [27..24] none */ + __IM uint32_t RESERVED4 : 4; /*!< [31..28] Reserved4 */ + } CT_INCREMENT_COUNTER_AND_EVENT_b; + }; + + union { + __IOM uint32_t CT_INCREMENT_COUNTER_OR_EVENT; /*!< (@ 0x00000088) Increment counter OR + event register */ + + struct { + __IOM uint32_t INCREMENT_COUNTER_0_OR_EVENT : 4; /*!< [3..0] For two 16 bit counter + mode: OR expression valids for OR + event in Increment Counter 0 + event For 32 bit counter mode OR + expression valids for OR event in + Increment counter event */ + __IOM uint32_t RESERVED1 : 4; /*!< [7..4] Reserved1 */ + __IOM uint32_t INCREMENT_COUNTER_0_OR_VLD : 4; /*!< [11..8] none */ + __IM uint32_t RESERVED2 : 4; /*!< [15..12] Reserved2 */ + __IOM uint32_t INCREMENT_COUNTER_1_OR_EVENT : 4; /*!< [19..16] For two 16 bit + counters mode: OR expression valids + for OR event in Increment counter + event For 32 bit counter mode : + Invalid */ + __IM uint32_t RESERVED4 : 4; /*!< [23..20] Reserved4 */ + __IOM uint32_t INCREMENT_COUNTER_1_OR_VLD : 4; /*!< [27..24] none */ + __IM uint32_t RESERVED5 : 4; /*!< [31..28] Reserved5 */ + } CT_INCREMENT_COUNTER_OR_EVENT_b; + }; + + union { + __IOM uint32_t CT_CAPTURE_COUNTER_EVENT_SEL; /*!< (@ 0x0000008C) Capture counter event + select register */ + + struct { + __IOM uint32_t CAPTURE_COUNTER_0_EVENT_SEL : 6; /*!< [5..0] For two 16 bit counters + mode: Event select for Capturing + the Counter 0 For 32 bit + counter mode: Event select for + Capturing counter */ + __IM uint32_t RESERVED1 : 10; /*!< [15..6] Reserved1 */ + __IOM uint32_t CAPTURE_COUNTER_1_EVENT_SEL : 6; /*!< [21..16] For two 16 bit counters + mode: Event select for Capturing + the Counter 1 For 32 bit + counter mode : Invalid */ + __IM uint32_t RESERVED2 : 10; /*!< [31..22] Reserved2 */ + } CT_CAPTURE_COUNTER_EVENT_SEL_b; + }; + + union { + __IOM uint32_t CT_CAPTURE_COUNTER_AND_EVENT; /*!< (@ 0x00000090) Capture counter AND + event register */ + + struct { + __IOM + uint32_t CAPTURE_COUNTER_0_AND_EVENT : 4; /*!< [3..0] For two 16 bit + counter mode: AND expression + valids for AND event in stop + Counter 0 event For 32 bit + counter mode AND expression + valids for AND event in stop + counter event */ + __IOM uint32_t RESERVED1 : 4; /*!< [7..4] Reserved1 */ + __IOM uint32_t CAPTURE_COUNTER_0_AND_VLD : 4; /*!< [11..8] none */ + __IM uint32_t RESERVED2 : 4; /*!< [15..12] Reserved2 */ + __IOM uint32_t CAPTURE_COUNTER_1_AND_EVENT : 4; /*!< [19..16] For two 16 bit counters + mode: AND expression valids for AND + event in stop counter event For 32 bit + counter mode : Invalid */ + __IM uint32_t RESERVED3 : 4; /*!< [23..20] Reserved3 */ + __IOM uint32_t CAPTURE_COUNTER_1_AND_VLD : 4; /*!< [27..24] none */ + __IM uint32_t RESERVED4 : 4; /*!< [31..28] Reserved4 */ + } CT_CAPTURE_COUNTER_AND_EVENT_b; + }; + + union { + __IOM uint32_t CT_CAPTURE_COUNTER_OR_EVENT; /*!< (@ 0x00000094) Capture counter OR + event register */ + + struct { + __IOM uint32_t CAPTURE_COUNTER_0_OR_EVENT : 4; /*!< [3..0] For two 16 bit counter + mode: OR expression valids for OR + event in Capture Counter 0 event For + 32 bit counter mode OR expression + valids for OR event in Capture counter + event */ + __IOM uint32_t RESERVED1 : 4; /*!< [7..4] Reserved1 */ + __IOM uint32_t CAPTURE_COUNTER_0_OR_VLD : 4; /*!< [11..8] none */ + __IM uint32_t RESERVED2 : 4; /*!< [15..12] Reserved2 */ + __IOM uint32_t CAPTURE_COUNTER_1_OR_EVENT : 4; /*!< [19..16] For two 16 bit counters + mode: OR expression valids for OR + event in Capture counter event For 32 + bit counter mode : Invalid */ + __IM uint32_t RESERVED3 : 4; /*!< [23..20] Reserved3 */ + __IOM uint32_t CAPTURE_COUNTER_1_OR_VLD : 4; /*!< [27..24] none */ + __IM uint32_t RESERVED4 : 4; /*!< [31..28] Reserved4 */ + } CT_CAPTURE_COUNTER_OR_EVENT_b; + }; + + union { + __IOM uint32_t CT_OUTPUT_EVENT_SEL; /*!< (@ 0x00000098) Output event select + register */ + + struct { + __IOM uint32_t OUTPUT_EVENT_SEL_0 : 6; /*!< [5..0] For two 16 bit counters mode: + Event select for output event from Counter + 0 For 32 bit counter mode: Event select + for output event */ + __IM uint32_t RESERVED1 : 10; /*!< [15..6] Reserved1 */ + __IOM uint32_t OUTPUT_EVENT_SEL_1 : 6; /*!< [21..16] For two 16 bit counters mode: + Event select for output + event from counter 1 For 32 bit + counter mode : Invalid */ + __IM uint32_t RESERVED2 : 10; /*!< [31..22] Reserved2 */ + } CT_OUTPUT_EVENT_SEL_b; + }; + + union { + __IOM uint32_t CT_OUTPUT_AND_EVENT_REG; /*!< (@ 0x0000009C) Output AND event + Register */ + + struct { + __IOM uint32_t OUTPUT_0_AND_EVENT : 4; /*!< [3..0] AND expression for AND event in + output Counter_0 event. */ + __IOM uint32_t RESERVED1 : 4; /*!< [7..4] Reserved1 */ + __IOM uint32_t OUTPUT_0_AND_VLD : 4; /*!< [11..8] AND expression for AND event in + output Counter_0 event. */ + __IM uint32_t RESERVED2 : 4; /*!< [15..12] Reserved2 */ + __IOM uint32_t OUTPUT_1_AND_EVENT : 4; /*!< [19..16] AND expression for AND event in + output Counter_1 event. */ + __IM uint32_t RESERVED3 : 4; /*!< [23..20] Reserved3 */ + __IOM uint32_t OUTPUT_1_AND_VLD : 4; /*!< [27..24] AND expression for AND event in + output Counter_1 event. */ + __IM uint32_t RESERVED4 : 4; /*!< [31..28] Reserved4 */ + } CT_OUTPUT_AND_EVENT_REG_b; + }; + + union { + __IOM uint32_t CT_OUTPUT_OR_EVENT; /*!< (@ 0x000000A0) Output OR event Register */ + + struct { + __IOM uint32_t OUTPUT_0_OR_EVENT : 4; /*!< [3..0] OR expression for OR event in + output Counter_0 event */ + __IOM uint32_t RESERVED1 : 4; /*!< [7..4] Reserved1 */ + __IOM uint32_t OUTPUT_0_OR_VLD : 4; /*!< [11..8] Indicates which bits in 3:0 are + valid for considering OR event */ + __IM uint32_t RESERVED2 : 4; /*!< [15..12] Reserved2 */ + __IOM uint32_t OUTPUT_1_OR_EVENT : 4; /*!< [19..16] OR expression for OR event in + output Counter_0 event */ + __IM uint32_t RESERVED3 : 4; /*!< [23..20] Reserved3 */ + __IOM uint32_t OUTPUT_1_OR_VLD : 4; /*!< [27..24] Indicates which bits in 3:0 are + valid for considering OR event */ + __IM uint32_t RESERVED4 : 4; /*!< [31..28] Reserved4 */ + } CT_OUTPUT_OR_EVENT_b; + }; + + union { + __IOM uint32_t CT_INTR_EVENT_SEL; /*!< (@ 0x000000A4) Interrupt Event Select + Register */ + + struct { + __IOM uint32_t INTR_EVENT_SEL_0 : 6; /*!< [5..0] For two 16 bit counters mode: Event + select for interrupt event from Counter 0 For + 32 bit counter mode: Event select + for output event */ + __IM uint32_t RESERVED1 : 10; /*!< [15..6] Reserved1 */ + __IOM uint32_t INTR_EVENT_SEL_1 : 6; /*!< [21..16] For two 16 bit counters + mode: Event select for interrupt + event from counter 1 For 32 + bit counter mode : Invalid */ + __IM uint32_t RESERVED2 : 10; /*!< [31..22] Reserved2 */ + } CT_INTR_EVENT_SEL_b; + }; + + union { + __IOM uint32_t CT_INTR_AND_EVENT; /*!< (@ 0x000000A8) Interrupt AND Event Register */ + + struct { + __IOM uint32_t INTR_0_AND_EVENT : 4; /*!< [3..0] None */ + __IOM uint32_t RESERVED1 : 4; /*!< [7..4] Reserved1 */ + __IOM uint32_t INTR_0_AND_VLD : 4; /*!< [11..8] None */ + __IM uint32_t RESERVED2 : 4; /*!< [15..12] Reserved2 */ + __IOM uint32_t INTR_1_AND_EVENT : 4; /*!< [19..16] None */ + __IM uint32_t RESERVED3 : 4; /*!< [23..20] Reserved3 */ + __IOM uint32_t INTR_1_AND_VLD : 4; /*!< [27..24] None */ + __IM uint32_t RESERVED4 : 4; /*!< [31..28] Reserved4 */ + } CT_INTR_AND_EVENT_b; + }; + + union { + __IOM uint32_t CT_INTR_OR_EVENT_REG; /*!< (@ 0x000000AC) Interrupt OR Event + Register */ + + struct { + __IOM uint32_t INTR_0_OR_EVENT : 4; /*!< [3..0] None */ + __IOM uint32_t RESERVED1 : 4; /*!< [7..4] Reserved1 */ + __IOM uint32_t INTR_0_OR_VLD : 4; /*!< [11..8] None */ + __IM uint32_t RESERVED2 : 4; /*!< [15..12] Reserved2 */ + __IOM uint32_t INTR_1_OR_EVENT : 4; /*!< [19..16] None */ + __IM uint32_t RESERVED3 : 4; /*!< [23..20] Reserved3 */ + __IOM uint32_t INTR_1_OR_VLD : 4; /*!< [27..24] None */ + __IM uint32_t RESERVED4 : 4; /*!< [31..28] Reserved4 */ + } CT_INTR_OR_EVENT_REG_b; + }; +} CT0_Type; /*!< Size = 176 (0xb0) */ + +/* =========================================================================================================================== + */ +/* ================ CT_MUX_REG + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief Configurable timer is used in counting clocks, events and states with + reference clock external clock and system clock (CT_MUX_REG) + */ + +typedef struct { /*!< (@ 0x4506F000) CT_MUX_REG Structure */ + + union { + __IOM uint32_t CT_MUX_SEL_0_REG; /*!< (@ 0x00000000) MUX_SEL_0_REG Register */ + + struct { + __IOM uint32_t MUX_SEL_0 : 4; /*!< [3..0] Select value to select first output value + fifo_0_full[0] out of all the fifo_0_full_muxed + signals of counter 0 */ + __IOM uint32_t RESERVED1 : 28; /*!< [31..4] Reserved1 */ + } CT_MUX_SEL_0_REG_b; + }; + + union { + __IOM uint32_t CT_MUX_SEL_1_REG; /*!< (@ 0x00000004) MUX_SEL_1_REG Register */ + + struct { + __IOM uint32_t MUX_SEL_1 : 4; /*!< [3..0] Select value to select first output value + fifo_0_full[1] out of all the fifo_0_full_muxed + signals of counter 0 */ + __IOM uint32_t RESERVED1 : 28; /*!< [31..4] Reserved1 */ + } CT_MUX_SEL_1_REG_b; + }; + + union { + __IOM uint32_t CT_MUX_SEL_2_REG; /*!< (@ 0x00000008) MUX_SEL_2_REG Register */ + + struct { + __IOM uint32_t MUX_SEL_2 : 4; /*!< [3..0] Select value to select first output value + fifo_1_full[0] out of all the fifo_1_full_muxed + signals of counter 1 */ + __IOM uint32_t RESERVED1 : 28; /*!< [31..4] Reserved1 */ + } CT_MUX_SEL_2_REG_b; + }; + + union { + __IOM uint32_t CT_MUX_SEL_3_REG; /*!< (@ 0x0000000C) MUX_SEL_3_REG Register */ + + struct { + __IOM uint32_t MUX_SEL_3 : 4; /*!< [3..0] Select value to select first output value + fifo_1_full[1] out of all the fifo_1_full_muxed + signals of counter 1 */ + __IOM uint32_t RESERVED1 : 28; /*!< [31..4] Reserved1 */ + } CT_MUX_SEL_3_REG_b; + }; + __IM uint32_t RESERVED[2]; + + union { + __IOM uint32_t CT_OUTPUT_EVENT1_ADC_SEL; /*!< (@ 0x00000018) OUTPUT_EVENT_ADC_SEL + Register */ + + struct { + __IOM + uint32_t OUTPUT_EVENT_ADC_SEL : 4; /*!< [3..0] Select signals to select one + output event out of all the output + events output_event_0 output_event_1, + output_event_2, output_event_3 to + enable ADC module */ + __IOM uint32_t RESERVED1 : 28; /*!< [31..4] Reserved1 */ + } CT_OUTPUT_EVENT1_ADC_SEL_b; + }; + + union { + __IOM uint32_t CT_OUTPUT_EVENT2_ADC_SEL; /*!< (@ 0x0000001C) OUTPUT_EVENT_ADC_SEL + Register */ + + struct { + __IOM + uint32_t OUTPUT_EVENT_ADC_SEL : 4; /*!< [3..0] Select signals to select one + output event out of all the output + events output_event_0 output_event_1, + output_event_2, output_event_3 to + enable ADC module */ + __IOM uint32_t RESERVED1 : 28; /*!< [31..4] Reserved1 */ + } CT_OUTPUT_EVENT2_ADC_SEL_b; + }; +} CT_MUX_REG_Type; /*!< Size = 32 (0x20) */ + +/* =========================================================================================================================== + */ +/* ================ EGPIO + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief ENHANCED GENERAL PERPOSE INPUT/OUTPUT (EGPIO) + */ + +typedef struct { /*!< (@ 0x46130000) EGPIO Structure */ + __IOM EGPIO_PIN_CONFIG_Type PIN_CONFIG[80]; /*!< (@ 0x00000000) [0..79] */ + __IM uint32_t RESERVED[704]; + __IOM EGPIO_PORT_CONFIG_Type PORT_CONFIG[6]; /*!< (@ 0x00001000) [0..5] */ + __IM uint32_t RESERVED1[80]; + __IOM EGPIO_INTR_Type INTR[8]; /*!< (@ 0x00001200) [0..7] */ + __IOM EGPIO_GPIO_GRP_INTR_Type GPIO_GRP_INTR[4]; /*!< (@ 0x00001240) [0..3] */ +} EGPIO_Type; /*!< Size = 4704 (0x1260) */ + +/* =========================================================================================================================== + */ +/* ================ SDIO0 + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief The Secure Digital I/O (SDIO) Slave module implements the + * functionality of the SDIO card based on the SDIO specifications version 2.0. + * (SDIO0) + */ + +typedef struct { /*!< (@ 0x40000000) SDIO0 Structure */ + + union { + __IOM uint32_t SDIO_INTR_FN1_STATUS_CLEAR_REG; /*!< (@ 0x00000000) SDIO Function1 + Interrupt Enable Register */ + + struct { + __IOM uint32_t SDIO_WR_INT_CLR : 1; /*!< [0..0] This bit is used to enable + CMD53 write interrupt. =1 + Interrupt is enabled =0 - + Interrupt is disabled */ + __IOM uint32_t SDIO_RD_INT_CLR : 1; /*!< [1..1] This bit is used to enable + CMD53 read interrupt */ + __IOM uint32_t SDIO_CSA_INT_CLR : 1; /*!< [2..2] This bit is used to + enable CMD53 CSA interrupt */ + __IOM uint32_t SDIO_CMD52_INT_CLR : 1; /*!< [3..3] This bit is used to + enable CMD52 interrupt */ + __IOM uint32_t SDIO_PWR_LEV_INT_CLR : 1; /*!< [4..4] This bit is used to enable power + level change interrupt */ + __IOM uint32_t SDIO_CRC_ERR_INT_CLR : 1; /*!< [5..5] This bit is used to enable CRC + error interrupt */ + __IOM uint32_t SDIO_ABORT_INT_CLR : 1; /*!< [6..6] This bit is used to + enable abort interrupt */ + __IOM uint32_t SDIO_TOUT_INT_CLR : 1; /*!< [7..7] This bit is used to enable ?read + FIFO wait time over? interrupt */ + __IOM uint32_t SDIO_WR_RDZ : 1; /*!< [8..8] SDIO_WR_RDZ */ + __IOM uint32_t SDIO_CSA_ACCESS : 1; /*!< [9..9] csa_window_access When set, indicates + that current request is for CSA window + register. This is only status signal */ + __IOM uint32_t RES : 22; /*!< [31..10] reserved1 */ + } SDIO_INTR_FN1_STATUS_CLEAR_REG_b; + }; + + union { + __IOM uint32_t SDIO_INTR_FN1_ENABLE_REG; /*!< (@ 0x00000004) SDIO Function1 + Interrupt Enable Register */ + + struct { + __IOM uint32_t SDIO_WR_INT_EN : 1; /*!< [0..0] This bit is used to enable + CMD53 write interrupt. */ + __IOM uint32_t SDIO_RD_INT_EN : 1; /*!< [1..1] This bit is used to enable + CMD53 read interrupt */ + __IOM uint32_t SDIO_CSA_INT_EN : 1; /*!< [2..2] This bit is used to enable + CMD53 CSA interrupt */ + __IOM uint32_t SDIO_CMD52_INT_EN : 1; /*!< [3..3] This bit is used to + enable CMD52 interrupt */ + __IOM uint32_t SDIO_PWR_LEV_INT_EN : 1; /*!< [4..4] This bit is used to enable power + level change interrupt */ + __IOM uint32_t SDIO_CRC_ERR_INT_EN : 1; /*!< [5..5] This bit is used to + enable CRC error interrupt */ + __IOM uint32_t SDIO_ABORT_INT_EN : 1; /*!< [6..6] This bit is used to + enable abort interrupt */ + __IOM uint32_t SDIO_TOUT_INT_EN : 1; /*!< [7..7] This bit is used to enable ?read + FIFO wait time over? interrupt */ + __IOM uint32_t RES : 24; /*!< [31..8] reserved5 */ + } SDIO_INTR_FN1_ENABLE_REG_b; + }; + + union { + __IOM uint32_t SDIO_INTR_FN1_MASK_REG; /*!< (@ 0x00000008) SDIO Function1 + Interrupt Mask Register */ + + struct { + __IOM uint32_t SDIO_WR_INT_MSK : 1; /*!< [0..0] This bit is used to mask + CMD53 write interrupt */ + __IOM uint32_t SDIO_RD_INT_MSK : 1; /*!< [1..1] This bit is used to mask + CMD53 read interrupt */ + __IOM uint32_t SDIO_CSA_MSK : 1; /*!< [2..2] This bit is used to mask CMD53 CSA + interrupt.Setting this bit will mask the + interrupt Clearing this bit has no effect */ + __IOM uint32_t SDIO_CMD52_MSK : 1; /*!< [3..3] This bit is used to mask + CMD52 interrupt */ + __IOM uint32_t SDIO_PWR_LEV_MSK : 1; /*!< [4..4] This bit is used to mask + power level change interrupt */ + __IOM uint32_t SDIO_CRC_ERR_MSK : 1; /*!< [5..5] This bit is used to mask + CRC error interrupt */ + __IOM uint32_t SDIO_ABORT_MSK : 1; /*!< [6..6] This bit is used to mask abort + interrupt Setting this bit will mask the + interrupt Clearing this bit has no effect */ + __IOM uint32_t SDIO_TOUT_MSK : 1; /*!< [7..7] This bit is used to mask read FIFO wait + time over interrupt */ + __IOM uint32_t RES : 24; /*!< [31..8] reserved5 */ + } SDIO_INTR_FN1_MASK_REG_b; + }; + + union { + __IOM uint32_t SDIO_INTR_FN1_UNMASK_REG; /*!< (@ 0x0000000C) SDIO Function1 + Interrupt UnMask Register */ + + struct { + __IOM uint32_t SDIO_WR_INT_UNMSK : 1; /*!< [0..0] This bit is used to + unmask CMD53 write interrupt */ + __IOM uint32_t SDIO_RD_INT_UNMSK : 1; /*!< [1..1] This bit is used to + unmask CMD53 read interrupt */ + __IOM uint32_t SDIO_CSA_UNMSK : 1; /*!< [2..2] This bit is used to unmask CMD53 CSA + interrupt.Setting this bit will mask the + interrupt Clearing this bit has no effect */ + __IOM uint32_t SDIO_CMD52_UNMSK : 1; /*!< [3..3] This bit is used to + unmask CMD52 interrupt */ + __IOM uint32_t SDIO_PWR_LEV_UNMSK : 1; /*!< [4..4] This bit is used to unmask power + level change interrupt */ + __IOM uint32_t SDIO_CRC_ERR_UNMSK : 1; /*!< [5..5] This bit is used to + unmask CRC error interrupt */ + __IOM + uint32_t SDIO_ABORT_UNMSK : 1; /*!< [6..6] This bit is used to unmask + abort interrupt Setting this bit + will mask the interrupt Clearing + this bit has no effect */ + __IOM uint32_t SDIO_TOUT_UNMSK : 1; /*!< [7..7] This bit is used to unmask read FIFO + wait time over interrupt */ + __IOM uint32_t RES : 24; /*!< [31..8] reserved5 */ + } SDIO_INTR_FN1_UNMASK_REG_b; + }; + + union { + __IM uint32_t SDIO_BLK_LEN_REG; /*!< (@ 0x00000010) SDIO Block Length Register */ + + struct { + __IM uint32_t SDIO_BLK_LEN : 12; /*!< [11..0] Length of each block for the + last received CMD53 */ + __IM uint32_t RES : 20; /*!< [31..12] reserved5 */ + } SDIO_BLK_LEN_REG_b; + }; + + union { + __IM uint32_t SDIO_BLK_CNT_REG; /*!< (@ 0x00000014) SDIO Block Length Register */ + + struct { + __IM uint32_t SDIO_BLK_CNT : 9; /*!< [8..0] Block count for the last + received CMD53 */ + __IM uint32_t RES : 23; /*!< [31..9] reserved5 */ + } SDIO_BLK_CNT_REG_b; + }; + + union { + __IM uint32_t SDIO_ADDRESS_REG; /*!< (@ 0x00000018) SDIO Address Register */ + + struct { + __IM uint32_t SDIO_ADDR : 16; /*!< [15..0] Lower 16-bits of the 17-bit address field + in the last received CMD53 */ + __IM uint32_t RES : 16; /*!< [31..16] reserved5 */ + } SDIO_ADDRESS_REG_b; + }; + __IOM uint32_t SDIO_CMD52_RDATA_REGISTER; /*!< (@ 0x0000001C) SDIO CMD52 RDATA + Register */ + __IOM uint32_t SDIO_CMD52_WDATA_REGISTER; /*!< (@ 0x00000020) SDIO CMD52 WDATA + Register */ + + union { + __IM uint32_t SDIO_INTR_STATUS_REG; /*!< (@ 0x00000024) SDIO Interrupt + Status Register */ + + struct { + __IM uint32_t SDIO_INT_ERROR : 1; /*!< [0..0] Interrupt is pending because of error + condition from any of the functions */ + __IM uint32_t SDIO_INT_FN1 : 1; /*!< [1..1] Interrupt is pending for function1 */ + __IM uint32_t SDIO_INT_FN2 : 1; /*!< [2..2] Interrupt is pending for function2 */ + __IM uint32_t SDIO_INT_FN3 : 1; /*!< [3..3] Interrupt is pending for function3 */ + __IM uint32_t SDIO_INT_FN4 : 1; /*!< [4..4] Interrupt is pending for function4 */ + __IM uint32_t SDIO_INT_FN5 : 1; /*!< [5..5] Interrupt is pending for function5 */ + __IM uint32_t RES : 26; /*!< [31..6] reserved5 */ + } SDIO_INTR_STATUS_REG_b; + }; + + union { + __IM uint32_t SDIO_INTR_FN_NUMBER_REG; /*!< (@ 0x00000028) SDIO Interrupt + Function Number Register */ + + struct { + __IM uint32_t SDIO_INTR_FN_NUM : 3; /*!< [2..0] Indicates the function number to + which interrupt is pending. */ + __IM uint32_t RES : 29; /*!< [31..3] reserved5 */ + } SDIO_INTR_FN_NUMBER_REG_b; + }; + + union { + __IM uint32_t SDIO_FIFO_STATUS_REG; /*!< (@ 0x0000002C) SDIO FIFO Status Register */ + + struct { + __IM uint32_t SDIO_WFIFO_FULL : 1; /*!< [0..0] When set, indicates that + WFIFO is full WFIFO is used + in SDIO reads from host for + sending data from AHB to Host */ + __IM uint32_t SDIO_WFIFO_AFULL : 1; /*!< [1..1] When set, indicates that + WFIFO is almost full */ + __IM uint32_t SDIO_RFIFO_EMPTY : 1; /*!< [2..2] When set, indicates that RFIFO is + empty RFIFO is used in SDIO writes from host + for sending data from host to AHB */ + __IM uint32_t SDIO_RFIFO_AEMPTY : 1; /*!< [3..3] When set, indicates that + RFIFO is almost empty */ + __IM uint32_t SDIO_CURRENT_FN_NUM : 3; /*!< [6..4] Indicates the function number of + the last received command */ + __IM uint32_t SDIO_BUS_CONTROL_STATE : 5; /*!< [11..7] Indicates the function number + of the last received command */ + __IM uint32_t RES : 20; /*!< [31..12] reserved5 */ + } SDIO_FIFO_STATUS_REG_b; + }; + + union { + __IM uint32_t SDIO_FIFO_OCC_REG; /*!< (@ 0x00000030) SDIO FIFO Occupancy Register */ + + struct { + __IM uint32_t SDIO_WFIFO_OCC : 8; /*!< [7..0] Indicates the occupancy + level of the write FIFO */ + __IM uint32_t SDIO_RFIFO_AVAIL : 8; /*!< [15..8] Indicates the available + space in the read FIFO */ + __IM uint32_t RES : 16; /*!< [31..16] reserved5 */ + } SDIO_FIFO_OCC_REG_b; + }; + + union { + __IOM uint32_t SDIO_HOST_INTR_SET_REG; /*!< (@ 0x00000034) SDIO Host + Interrupt Set Register */ + + struct { + __IOM uint32_t SDIO_INTSET_FN2 : 1; /*!< [0..0] This bit is used to raise an + interrupt to host for function2. Setting this + bit will raise the interrupt Clearing this + bit has no effect */ + __IOM uint32_t SDIO_INTSET_FN3 : 1; /*!< [1..1] This bit is used to raise an + interrupt to host for function3. Setting this + bit will raise the interrupt Clearing this + bit has no effect */ + __IOM uint32_t SDIO_INTSET_FN4 : 1; /*!< [2..2] This bit is used to raise an + interrupt to host for function4. Setting this + bit will raise the interrupt Clearing this + bit has no effect */ + __IOM uint32_t SDIO_INTSET_FN5 : 1; /*!< [3..3] This bit is used to raise an + interrupt to host for function5. Setting this + bit will raise the interrupt Clearing this + bit has no effect */ + __IOM uint32_t RES : 28; /*!< [31..4] reserved5 */ + } SDIO_HOST_INTR_SET_REG_b; + }; + + union { + __IOM uint32_t SDIO_HOST_INTR_CLEAR_REG; /*!< (@ 0x00000038) SDIO Host + Interrupt Clear Register */ + + struct { + __IOM uint32_t SDIO_INTCLR_FN2 : 1; /*!< [0..0] This bit is used to clear the + interrupt to host for function2. Setting this + bit will clear the interrupt Clearing this + bit has no effect */ + __IOM uint32_t SDIO_INTCLR_FN3 : 1; /*!< [1..1] This bit is used to clear the + interrupt to host for function3. Setting this + bit will clear the interrupt Clearing this + bit has no effect */ + __IOM uint32_t SDIO_INTCLR_FN4 : 1; /*!< [2..2] This bit is used to clear the + interrupt to host for function4. Setting this + bit will clear the interrupt Clearing this + bit has no effectt */ + __IOM uint32_t SDIO_INTCLR_FN5 : 1; /*!< [3..3] This bit is used to clear the + interrupt to host for function5. Setting this + bit will clear the interrupt Clearing this + bit has no effect */ + __IOM uint32_t RES : 28; /*!< [31..4] reserved5 */ + } SDIO_HOST_INTR_CLEAR_REG_b; + }; + __IM uint32_t RESERVED; + + union { + __OM uint32_t SDIO_RFIFO_DATA_REG[16]; /*!< (@ 0x00000040) SDIO Read FIFO + Data Register */ + + struct { + __OM uint32_t SDIO_RFIFO : 32; /*!< [31..0] Data to be written into SDIO Read FIFO + has to be written in this register. */ + } SDIO_RFIFO_DATA_REG_b[16]; + }; + + union { + __IM uint32_t SDIO_WFIFO_DATA_REG[16]; /*!< (@ 0x00000080) SDIO Write FIFO + Data Register */ + + struct { + __IM uint32_t SDIO_WFIFO : 32; /*!< [31..0] SDIO Write FIFO data can be + read through this register. */ + } SDIO_WFIFO_DATA_REG_b[16]; + }; + + union { + __IOM uint32_t SDIO_INTR_FN2_STATUS_CLEAR_REG; /*!< (@ 0x000000C0) SDIO Function2 + Status Clear Register */ + + struct { + __IOM uint32_t SDIO_WR_INT_CLR : 1; /*!< [0..0] This bit is used to enable + CMD53 write interrupt. =1 + Interrupt is enabled =0 - + Interrupt is disabled */ + __IOM uint32_t SDIO_RD_INT_CLR : 1; /*!< [1..1] This bit is used to enable + CMD53 read interrupt */ + __IOM uint32_t SDIO_CSA_INT_CLR : 1; /*!< [2..2] This bit is used to + enable CMD53 CSA interrupt */ + __IOM uint32_t SDIO_CMD52_INT_CLR : 1; /*!< [3..3] This bit is used to + enable CMD52 interrupt */ + __IOM uint32_t SDIO_PWR_LEV_INT_CLR : 1; /*!< [4..4] This bit is used to enable power + level change interrupt */ + __IOM uint32_t SDIO_CRC_ERR_INT_CLR : 1; /*!< [5..5] This bit is used to enable CRC + error interrupt */ + __IOM uint32_t SDIO_ABORT_INT_CLR : 1; /*!< [6..6] This bit is used to + enable abort interrupt */ + __IOM uint32_t SDIO_TOUT_INT_CLR : 1; /*!< [7..7] This bit is used to enable ?read + FIFO wait time over? interrupt */ + __IOM uint32_t RES : 24; /*!< [31..8] reserved5 */ + } SDIO_INTR_FN2_STATUS_CLEAR_REG_b; + }; + + union { + __IOM uint32_t SDIO_INTR_FN2_ENABLE_REG; /*!< (@ 0x000000C4) SDIO Function1 + Interrupt Enable Register */ + + struct { + __IOM uint32_t SDIO_WR_INT_EN : 1; /*!< [0..0] This bit is used to enable + CMD53 write interrupt. */ + __IOM uint32_t SDIO_RD_INT_EN : 1; /*!< [1..1] This bit is used to enable + CMD53 read interrupt */ + __IOM uint32_t SDIO_CSA_INT_EN : 1; /*!< [2..2] This bit is used to enable + CMD53 CSA interrupt */ + __IOM uint32_t SDIO_CMD52_INT_EN : 1; /*!< [3..3] This bit is used to + enable CMD52 interrupt */ + __IOM uint32_t SDIO_PWR_LEV_INT_EN : 1; /*!< [4..4] This bit is used to enable power + level change interrupt */ + __IOM uint32_t SDIO_CRC_ERR_INT_EN : 1; /*!< [5..5] This bit is used to + enable CRC error interrupt */ + __IOM uint32_t SDIO_ABORT_INT_EN : 1; /*!< [6..6] This bit is used to + enable abort interrupt */ + __IOM uint32_t SDIO_TOUT_INT_EN : 1; /*!< [7..7] This bit is used to enable ?read + FIFO wait time over? interrupt */ + __IOM uint32_t RES : 24; /*!< [31..8] reserved5 */ + } SDIO_INTR_FN2_ENABLE_REG_b; + }; + + union { + __IOM uint32_t SDIO_INTR_FN2_MASK_REG; /*!< (@ 0x000000C8) SDIO Function2 + Interrupt Mask Register */ + + struct { + __IOM uint32_t SDIO_WR_INT_MSK : 1; /*!< [0..0] This bit is used to mask + CMD53 write interrupt */ + __IOM uint32_t SDIO_RD_INT_MSK : 1; /*!< [1..1] This bit is used to mask + CMD53 read interrupt */ + __IOM uint32_t SDIO_CSA_MSK : 1; /*!< [2..2] This bit is used to mask CMD53 CSA + interrupt.Setting this bit will mask the + interrupt Clearing this bit has no effect */ + __IOM uint32_t SDIO_CMD52_MSK : 1; /*!< [3..3] This bit is used to mask + CMD52 interrupt */ + __IOM uint32_t SDIO_PWR_LEV_MSK : 1; /*!< [4..4] This bit is used to mask + power level change interrupt */ + __IOM uint32_t SDIO_CRC_ERR_MSK : 1; /*!< [5..5] This bit is used to mask + CRC error interrupt */ + __IOM uint32_t SDIO_ABORT_MSK : 1; /*!< [6..6] This bit is used to mask abort + interrupt Setting this bit will mask the + interrupt Clearing this bit has no effect */ + __IOM uint32_t SDIO_TOUT_MSK : 1; /*!< [7..7] This bit is used to mask read FIFO wait + time over interrupt */ + __IOM uint32_t RES : 24; /*!< [31..8] reserved5 */ + } SDIO_INTR_FN2_MASK_REG_b; + }; + + union { + __IOM uint32_t SDIO_INTR_FN2_UNMASK_REG; /*!< (@ 0x000000CC) SDIO Function2 + Interrupt Mask Register */ + + struct { + __IOM uint32_t SDIO_WR_INT_UNMSK : 1; /*!< [0..0] This bit is used to + unmask CMD53 write interrupt */ + __IOM uint32_t SDIO_RD_INT_UNMSK : 1; /*!< [1..1] This bit is used to + unmask CMD53 read interrupt */ + __IOM uint32_t SDIO_CSA_UNMSK : 1; /*!< [2..2] This bit is used to unmask CMD53 CSA + interrupt.Setting this bit will mask the + interrupt Clearing this bit has no effect */ + __IOM uint32_t SDIO_CMD52_UNMSK : 1; /*!< [3..3] This bit is used to + unmask CMD52 interrupt */ + __IOM uint32_t SDIO_PWR_LEV_UNMSK : 1; /*!< [4..4] This bit is used to unmask power + level change interrupt */ + __IOM uint32_t SDIO_CRC_ERR_UNMSK : 1; /*!< [5..5] This bit is used to + unmask CRC error interrupt */ + __IOM + uint32_t SDIO_ABORT_UNMSK : 1; /*!< [6..6] This bit is used to unmask + abort interrupt Setting this bit + will mask the interrupt Clearing + this bit has no effect */ + __IOM uint32_t SDIO_TOUT_UNMSK : 1; /*!< [7..7] This bit is used to unmask read FIFO + wait time over interrupt */ + __IOM uint32_t RES : 24; /*!< [31..8] reserved5 */ + } SDIO_INTR_FN2_UNMASK_REG_b; + }; + + union { + __IOM uint32_t SDIO_INTR_FN3_STATUS_CLEAR_REG; /*!< (@ 0x000000D0) SDIO Function3 + Status Clear Register */ + + struct { + __IOM uint32_t SDIO_WR_INT_CLR : 1; /*!< [0..0] This bit is used to enable + CMD53 write interrupt. =1 + Interrupt is enabled =0 - + Interrupt is disabled */ + __IOM uint32_t SDIO_RD_INT_CLR : 1; /*!< [1..1] This bit is used to enable + CMD53 read interrupt */ + __IOM uint32_t SDIO_CSA_INT_CLR : 1; /*!< [2..2] This bit is used to + enable CMD53 CSA interrupt */ + __IOM uint32_t SDIO_CMD52_INT_CLR : 1; /*!< [3..3] This bit is used to + enable CMD52 interrupt */ + __IOM uint32_t SDIO_PWR_LEV_INT_CLR : 1; /*!< [4..4] This bit is used to enable power + level change interrupt */ + __IOM uint32_t SDIO_CRC_ERR_INT_CLR : 1; /*!< [5..5] This bit is used to enable CRC + error interrupt */ + __IOM uint32_t SDIO_ABORT_INT_CLR : 1; /*!< [6..6] This bit is used to + enable abort interrupt */ + __IOM uint32_t SDIO_TOUT_INT_CLR : 1; /*!< [7..7] This bit is used to enable ?read + FIFO wait time over? interrupt */ + __IOM uint32_t RES : 24; /*!< [31..8] reserved5 */ + } SDIO_INTR_FN3_STATUS_CLEAR_REG_b; + }; + + union { + __IOM uint32_t SDIO_INTR_FN3_ENABLE_REG; /*!< (@ 0x000000D4) SDIO Function3 + Interrupt Enable Register */ + + struct { + __IOM uint32_t SDIO_WR_INT_EN : 1; /*!< [0..0] This bit is used to enable + CMD53 write interrupt. */ + __IOM uint32_t SDIO_RD_INT_EN : 1; /*!< [1..1] This bit is used to enable + CMD53 read interrupt */ + __IOM uint32_t SDIO_CSA_INT_EN : 1; /*!< [2..2] This bit is used to enable + CMD53 CSA interrupt */ + __IOM uint32_t SDIO_CMD52_INT_EN : 1; /*!< [3..3] This bit is used to + enable CMD52 interrupt */ + __IOM uint32_t SDIO_PWR_LEV_INT_EN : 1; /*!< [4..4] This bit is used to enable power + level change interrupt */ + __IOM uint32_t SDIO_CRC_ERR_INT_EN : 1; /*!< [5..5] This bit is used to + enable CRC error interrupt */ + __IOM uint32_t SDIO_ABORT_INT_EN : 1; /*!< [6..6] This bit is used to + enable abort interrupt */ + __IOM uint32_t SDIO_TOUT_INT_EN : 1; /*!< [7..7] This bit is used to enable ?read + FIFO wait time over? interrupt */ + __IOM uint32_t RES : 24; /*!< [31..8] reserved5 */ + } SDIO_INTR_FN3_ENABLE_REG_b; + }; + + union { + __IOM uint32_t SDIO_INTR_FN3_MASK_REG; /*!< (@ 0x000000D8) SDIO Function3 + Interrupt Mask Register */ + + struct { + __IOM uint32_t SDIO_WR_INT_MSK : 1; /*!< [0..0] This bit is used to mask + CMD53 write interrupt */ + __IOM uint32_t SDIO_RD_INT_MSK : 1; /*!< [1..1] This bit is used to mask + CMD53 read interrupt */ + __IOM uint32_t SDIO_CSA_MSK : 1; /*!< [2..2] This bit is used to mask CMD53 CSA + interrupt.Setting this bit will mask the + interrupt Clearing this bit has no effect */ + __IOM uint32_t SDIO_CMD52_MSK : 1; /*!< [3..3] This bit is used to mask + CMD52 interrupt */ + __IOM uint32_t SDIO_PWR_LEV_MSK : 1; /*!< [4..4] This bit is used to mask + power level change interrupt */ + __IOM uint32_t SDIO_CRC_ERR_MSK : 1; /*!< [5..5] This bit is used to mask + CRC error interrupt */ + __IOM uint32_t SDIO_ABORT_MSK : 1; /*!< [6..6] This bit is used to mask abort + interrupt Setting this bit will mask the + interrupt Clearing this bit has no effect */ + __IOM uint32_t SDIO_TOUT_MSK : 1; /*!< [7..7] This bit is used to mask read FIFO wait + time over interrupt */ + __IOM uint32_t RES : 24; /*!< [31..8] reserved5 */ + } SDIO_INTR_FN3_MASK_REG_b; + }; + + union { + __IOM uint32_t SDIO_INTR_FN3_UNMASK_REG; /*!< (@ 0x000000DC) SDIO Function3 + Interrupt Mask Register */ + + struct { + __IOM uint32_t SDIO_WR_INT_UNMSK : 1; /*!< [0..0] This bit is used to + unmask CMD53 write interrupt */ + __IOM uint32_t SDIO_RD_INT_UNMSK : 1; /*!< [1..1] This bit is used to + unmask CMD53 read interrupt */ + __IOM uint32_t SDIO_CSA_UNMSK : 1; /*!< [2..2] This bit is used to unmask CMD53 CSA + interrupt.Setting this bit will mask the + interrupt Clearing this bit has no effect */ + __IOM uint32_t SDIO_CMD52_UNMSK : 1; /*!< [3..3] This bit is used to + unmask CMD52 interrupt */ + __IOM uint32_t SDIO_PWR_LEV_UNMSK : 1; /*!< [4..4] This bit is used to unmask power + level change interrupt */ + __IOM uint32_t SDIO_CRC_ERR_UNMSK : 1; /*!< [5..5] This bit is used to + unmask CRC error interrupt */ + __IOM + uint32_t SDIO_ABORT_UNMSK : 1; /*!< [6..6] This bit is used to unmask + abort interrupt Setting this bit + will mask the interrupt Clearing + this bit has no effect */ + __IOM uint32_t SDIO_TOUT_UNMSK : 1; /*!< [7..7] This bit is used to unmask read FIFO + wait time over interrupt */ + __IOM uint32_t RES : 24; /*!< [31..8] reserved5 */ + } SDIO_INTR_FN3_UNMASK_REG_b; + }; + + union { + __IOM uint32_t SDIO_INTR_FN4_STATUS_CLEAR_REG; /*!< (@ 0x000000E0) SDIO Function4 + Status Clear Register */ + + struct { + __IOM uint32_t SDIO_WR_INT_CLR : 1; /*!< [0..0] This bit is used to enable + CMD53 write interrupt. =1 + Interrupt is enabled =0 - + Interrupt is disabled */ + __IOM uint32_t SDIO_RD_INT_CLR : 1; /*!< [1..1] This bit is used to enable + CMD53 read interrupt */ + __IOM uint32_t SDIO_CSA_INT_CLR : 1; /*!< [2..2] This bit is used to + enable CMD53 CSA interrupt */ + __IOM uint32_t SDIO_CMD52_INT_CLR : 1; /*!< [3..3] This bit is used to + enable CMD52 interrupt */ + __IOM uint32_t SDIO_PWR_LEV_INT_CLR : 1; /*!< [4..4] This bit is used to enable power + level change interrupt */ + __IOM uint32_t SDIO_CRC_ERR_INT_CLR : 1; /*!< [5..5] This bit is used to enable CRC + error interrupt */ + __IOM uint32_t SDIO_ABORT_INT_CLR : 1; /*!< [6..6] This bit is used to + enable abort interrupt */ + __IOM uint32_t SDIO_TOUT_INT_CLR : 1; /*!< [7..7] This bit is used to enable ?read + FIFO wait time over? interrupt */ + __IOM uint32_t RES : 24; /*!< [31..8] reserved5 */ + } SDIO_INTR_FN4_STATUS_CLEAR_REG_b; + }; + + union { + __IOM uint32_t SDIO_INTR_FN4_ENABLE_REG; /*!< (@ 0x000000E4) SDIO Function4 + Interrupt Enable Register */ + + struct { + __IOM uint32_t SDIO_WR_INT_EN : 1; /*!< [0..0] This bit is used to enable + CMD53 write interrupt. */ + __IOM uint32_t SDIO_RD_INT_EN : 1; /*!< [1..1] This bit is used to enable + CMD53 read interrupt */ + __IOM uint32_t SDIO_CSA_INT_EN : 1; /*!< [2..2] This bit is used to enable + CMD53 CSA interrupt */ + __IOM uint32_t SDIO_CMD52_INT_EN : 1; /*!< [3..3] This bit is used to + enable CMD52 interrupt */ + __IOM uint32_t SDIO_PWR_LEV_INT_EN : 1; /*!< [4..4] This bit is used to enable power + level change interrupt */ + __IOM uint32_t SDIO_CRC_ERR_INT_EN : 1; /*!< [5..5] This bit is used to + enable CRC error interrupt */ + __IOM uint32_t SDIO_ABORT_INT_EN : 1; /*!< [6..6] This bit is used to + enable abort interrupt */ + __IOM uint32_t SDIO_TOUT_INT_EN : 1; /*!< [7..7] This bit is used to enable ?read + FIFO wait time over? interrupt */ + __IOM uint32_t RES : 24; /*!< [31..8] reserved5 */ + } SDIO_INTR_FN4_ENABLE_REG_b; + }; + + union { + __IOM uint32_t SDIO_INTR_FN4_MASK_REG; /*!< (@ 0x000000E8) SDIO Function4 + Interrupt Mask Register */ + + struct { + __IOM uint32_t SDIO_WR_INT_MSK : 1; /*!< [0..0] This bit is used to mask + CMD53 write interrupt */ + __IOM uint32_t SDIO_RD_INT_MSK : 1; /*!< [1..1] This bit is used to mask + CMD53 read interrupt */ + __IOM uint32_t SDIO_CSA_MSK : 1; /*!< [2..2] This bit is used to mask CMD53 CSA + interrupt.Setting this bit will mask the + interrupt Clearing this bit has no effect */ + __IOM uint32_t SDIO_CMD52_MSK : 1; /*!< [3..3] This bit is used to mask + CMD52 interrupt */ + __IOM uint32_t SDIO_PWR_LEV_MSK : 1; /*!< [4..4] This bit is used to mask + power level change interrupt */ + __IOM uint32_t SDIO_CRC_ERR_MSK : 1; /*!< [5..5] This bit is used to mask + CRC error interrupt */ + __IOM uint32_t SDIO_ABORT_MSK : 1; /*!< [6..6] This bit is used to mask abort + interrupt Setting this bit will mask the + interrupt Clearing this bit has no effect */ + __IOM uint32_t SDIO_TOUT_MSK : 1; /*!< [7..7] This bit is used to mask read FIFO wait + time over interrupt */ + __IOM uint32_t RES : 24; /*!< [31..8] reserved5 */ + } SDIO_INTR_FN4_MASK_REG_b; + }; + + union { + __IOM uint32_t SDIO_INTR_FN4_UNMASK_REG; /*!< (@ 0x000000EC) SDIO Function4 + Interrupt Mask Register */ + + struct { + __IOM uint32_t SDIO_WR_INT_UNMSK : 1; /*!< [0..0] This bit is used to + unmask CMD53 write interrupt */ + __IOM uint32_t SDIO_RD_INT_UNMSK : 1; /*!< [1..1] This bit is used to + unmask CMD53 read interrupt */ + __IOM uint32_t SDIO_CSA_UNMSK : 1; /*!< [2..2] This bit is used to unmask CMD53 CSA + interrupt.Setting this bit will mask the + interrupt Clearing this bit has no effect */ + __IOM uint32_t SDIO_CMD52_UNMSK : 1; /*!< [3..3] This bit is used to + unmask CMD52 interrupt */ + __IOM uint32_t SDIO_PWR_LEV_UNMSK : 1; /*!< [4..4] This bit is used to unmask power + level change interrupt */ + __IOM uint32_t SDIO_CRC_ERR_UNMSK : 1; /*!< [5..5] This bit is used to + unmask CRC error interrupt */ + __IOM + uint32_t SDIO_ABORT_UNMSK : 1; /*!< [6..6] This bit is used to unmask + abort interrupt Setting this bit + will mask the interrupt Clearing + this bit has no effect */ + __IOM uint32_t SDIO_TOUT_UNMSK : 1; /*!< [7..7] This bit is used to unmask read FIFO + wait time over interrupt */ + __IOM uint32_t RES : 24; /*!< [31..8] reserved5 */ + } SDIO_INTR_FN4_UNMASK_REG_b; + }; + + union { + __IOM uint32_t SDIO_INTR_FN5_STATUS_CLEAR_REG; /*!< (@ 0x000000F0) SDIO Function5 + Status Clear Register */ + + struct { + __IOM uint32_t SDIO_WR_INT_CLR : 1; /*!< [0..0] This bit is used to enable + CMD53 write interrupt. =1 + Interrupt is enabled =0 - + Interrupt is disabled */ + __IOM uint32_t SDIO_RD_INT_CLR : 1; /*!< [1..1] This bit is used to enable + CMD53 read interrupt */ + __IOM uint32_t SDIO_CSA_INT_CLR : 1; /*!< [2..2] This bit is used to + enable CMD53 CSA interrupt */ + __IOM uint32_t SDIO_CMD52_INT_CLR : 1; /*!< [3..3] This bit is used to + enable CMD52 interrupt */ + __IOM uint32_t SDIO_PWR_LEV_INT_CLR : 1; /*!< [4..4] This bit is used to enable power + level change interrupt */ + __IOM uint32_t SDIO_CRC_ERR_INT_CLR : 1; /*!< [5..5] This bit is used to enable CRC + error interrupt */ + __IOM uint32_t SDIO_ABORT_INT_CLR : 1; /*!< [6..6] This bit is used to + enable abort interrupt */ + __IOM uint32_t SDIO_TOUT_INT_CLR : 1; /*!< [7..7] This bit is used to enable ?read + FIFO wait time over? interrupt */ + __IOM uint32_t RES : 24; /*!< [31..8] reserved5 */ + } SDIO_INTR_FN5_STATUS_CLEAR_REG_b; + }; + + union { + __IOM uint32_t SDIO_INTR_FN5_ENABLE_REG; /*!< (@ 0x000000F4) SDIO Function5 + Interrupt Enable Register */ + + struct { + __IOM uint32_t SDIO_WR_INT_EN : 1; /*!< [0..0] This bit is used to enable + CMD53 write interrupt. */ + __IOM uint32_t SDIO_RD_INT_EN : 1; /*!< [1..1] This bit is used to enable + CMD53 read interrupt */ + __IOM uint32_t SDIO_CSA_INT_EN : 1; /*!< [2..2] This bit is used to enable + CMD53 CSA interrupt */ + __IOM uint32_t SDIO_CMD52_INT_EN : 1; /*!< [3..3] This bit is used to + enable CMD52 interrupt */ + __IOM uint32_t SDIO_PWR_LEV_INT_EN : 1; /*!< [4..4] This bit is used to enable power + level change interrupt */ + __IOM uint32_t SDIO_CRC_ERR_INT_EN : 1; /*!< [5..5] This bit is used to + enable CRC error interrupt */ + __IOM uint32_t SDIO_ABORT_INT_EN : 1; /*!< [6..6] This bit is used to + enable abort interrupt */ + __IOM uint32_t SDIO_TOUT_INT_EN : 1; /*!< [7..7] This bit is used to enable ?read + FIFO wait time over? interrupt */ + __IOM uint32_t RES : 24; /*!< [31..8] reserved5 */ + } SDIO_INTR_FN5_ENABLE_REG_b; + }; + + union { + __IOM uint32_t SDIO_INTR_FN5_MASK_REG; /*!< (@ 0x000000F8) SDIO Function5 + Interrupt Mask Register */ + + struct { + __IOM uint32_t SDIO_WR_INT_MSK : 1; /*!< [0..0] This bit is used to mask + CMD53 write interrupt */ + __IOM uint32_t SDIO_RD_INT_MSK : 1; /*!< [1..1] This bit is used to mask + CMD53 read interrupt */ + __IOM uint32_t SDIO_CSA_MSK : 1; /*!< [2..2] This bit is used to mask CMD53 CSA + interrupt.Setting this bit will mask the + interrupt Clearing this bit has no effect */ + __IOM uint32_t SDIO_CMD52_MSK : 1; /*!< [3..3] This bit is used to mask + CMD52 interrupt */ + __IOM uint32_t SDIO_PWR_LEV_MSK : 1; /*!< [4..4] This bit is used to mask + power level change interrupt */ + __IOM uint32_t SDIO_CRC_ERR_MSK : 1; /*!< [5..5] This bit is used to mask + CRC error interrupt */ + __IOM uint32_t SDIO_ABORT_MSK : 1; /*!< [6..6] This bit is used to mask abort + interrupt Setting this bit will mask the + interrupt Clearing this bit has no effect */ + __IOM uint32_t SDIO_TOUT_MSK : 1; /*!< [7..7] This bit is used to mask read FIFO wait + time over interrupt */ + __IOM uint32_t RES : 24; /*!< [31..8] reserved5 */ + } SDIO_INTR_FN5_MASK_REG_b; + }; + + union { + __IOM uint32_t SDIO_INTR_FN5_UNMASK_REG; /*!< (@ 0x000000FC) SDIO Function5 + Interrupt Mask Register */ + + struct { + __IOM uint32_t SDIO_WR_INT_UNMSK : 1; /*!< [0..0] This bit is used to + unmask CMD53 write interrupt */ + __IOM uint32_t SDIO_RD_INT_UNMSK : 1; /*!< [1..1] This bit is used to + unmask CMD53 read interrupt */ + __IOM uint32_t SDIO_CSA_UNMSK : 1; /*!< [2..2] This bit is used to unmask CMD53 CSA + interrupt.Setting this bit will mask the + interrupt Clearing this bit has no effect */ + __IOM uint32_t SDIO_CMD52_UNMSK : 1; /*!< [3..3] This bit is used to + unmask CMD52 interrupt */ + __IOM uint32_t SDIO_PWR_LEV_UNMSK : 1; /*!< [4..4] This bit is used to unmask power + level change interrupt */ + __IOM uint32_t SDIO_CRC_ERR_UNMSK : 1; /*!< [5..5] This bit is used to + unmask CRC error interrupt */ + __IOM + uint32_t SDIO_ABORT_UNMSK : 1; /*!< [6..6] This bit is used to unmask + abort interrupt Setting this bit + will mask the interrupt Clearing + this bit has no effect */ + __IOM uint32_t SDIO_TOUT_UNMSK : 1; /*!< [7..7] This bit is used to unmask read FIFO + wait time over interrupt */ + __IOM uint32_t RES : 24; /*!< [31..8] reserved5 */ + } SDIO_INTR_FN5_UNMASK_REG_b; + }; + + union { + __IOM uint32_t SDIO_ERROR_COND_CHK_ENABLE_REG; /*!< (@ 0x00000100) SDIO error condition + check enable register */ + + struct { + __IOM uint32_t SDIO_CRC_EN : 1; /*!< [0..0] When set, stops the DMA from doing data + accesses till CRC error interrupt is cleared */ + __IOM uint32_t SDIO_ABORT_EN : 1; /*!< [1..1] When set, stops the DMA from doing data + accesses till ABORT interrupt is cleared */ + __IOM uint32_t SDIO_SPI_RD_DATA_ERROR_EN : 1; /*!< [2..2] When set, stops the DMA + from doing data accesses till read + data error interrupt is cleared in SPI + mode */ + __IOM uint32_t RES : 29; /*!< [31..3] reserved5 */ + } SDIO_ERROR_COND_CHK_ENABLE_REG_b; + }; + + union { + __IOM uint32_t SDIO_ERROR_COND_STATE_REG; /*!< (@ 0x00000104) SDIO error + condition state register */ + + struct { + __IOM uint32_t SDIO_ERROR_BYTE_CNT : 12; /*!< [11..0] Indicates byte count when one + of the error condition occurred */ + __IOM uint32_t RESERVED1 : 4; /*!< [15..12] RESERVED1 */ + __IOM uint32_t SDIO_ERROR_BLK_CNT : 7; /*!< [22..16] Indicates block count when one + of error condition occurred */ + __IOM uint32_t RESERVED2 : 9; /*!< [31..23] RESERVED2 */ + } SDIO_ERROR_COND_STATE_REG_b; + }; + + union { + __IM uint32_t SDIO_BOOT_CONFIG_VALS_0_REG; /*!< (@ 0x00000108) SDIO Boot + Config Values Register 0 */ + + struct { + __IM uint32_t OCR_R : 24; /*!< [23..0] Operating conditions. The value + written by bootloader can be read here. */ + __IM uint32_t CSA_MSBYTE : 8; /*!< [31..24] MS byre of CSA address. Lower + 24 bits of CSA will come through SDIO CSA + registers. Whenever CSA access is + done, 32-bit address will + be prepared using these fields. */ + } SDIO_BOOT_CONFIG_VALS_0_REG_b; + }; + + union { + __IM uint32_t SDIO_BOOT_CONFIG_VALS_1_REG; /*!< (@ 0x0000010C) SDIO Boot + Config Values Register 1 */ + + struct { + __IM uint32_t NO_OF_IO_FUNCTIONS : 3; /*!< [2..0] Indicates number functions + supported. The value written + by bootloader can be read here. */ + __IM uint32_t COMBOCARD : 1; /*!< [3..3] When set, combo mode will be enabled. */ + __IM uint32_t SDMEM_IGNOTRE_SDMEM_PRESENT : 1; /*!< [4..4] When set, sdmem_present + signal, coming from GPIO, will be + ignored. */ + __IM uint32_t SDMEM_DRIVE_HIZ_MB_READ : 1; /*!< [5..5] When set, High will be driven + in the second cycle of interrupt period + during sd memory mb read transfer */ + __IM uint32_t SDMEM_DISABLE_INTERRUPT_MB_READ : 1; /*!< [6..6] When set, + interrupt will be + not be driven during + sd memory mb read + transfer */ + __IM uint32_t IGNORE_DISABLE_HS : 1; /*!< [7..7] if ignore_disable_hs is set, + sdmem_disable_high_speed_switching coming + from combo mode module is ignored */ + __IM uint32_t RESERVED2 : 24; /*!< [31..8] RESERVED2 */ + } SDIO_BOOT_CONFIG_VALS_1_REG_b; + }; +} SDIO0_Type; /*!< Size = 272 (0x110) */ + +/* =========================================================================================================================== + */ +/* ================ SPI_SLAVE + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief The SPI Interface is a full duplex serial host interface, which + supports 8-bit and 32-bit data granularity. It also supports gated mode of SPI + clock and both the low and the high frequency modes (SPI_SLAVE) + */ + +typedef struct { /*!< (@ 0x20200000) SPI_SLAVE Structure */ + + union { + __IOM uint8_t SPI_HOST_INTR; /*!< (@ 0x00000000) SPI Host interupt resgister. */ + + struct { + __IOM uint8_t SPI_HOST_INTR : 8; /*!< [7..0] These bits indicate the interrupt + vector value coming from system side. */ + } SPI_HOST_INTR_b; + }; + __IM uint8_t RESERVED; + + union { + __IOM uint8_t SPI_RFIFO_START; /*!< (@ 0x00000002) SPI FIFO start Level Register. */ + + struct { + __IOM uint8_t SPI_RFIFO_ST : 8; /*!< [7..0] These bits indicate the interrupt vector + value coming from system side. */ + } SPI_RFIFO_START_b; + }; + __IM uint8_t RESERVED1; + + union { + __IOM uint8_t SPI_RFIFO_AFULL_LEV; /*!< (@ 0x00000004) SPI RFIFO AFULL Level + Register. */ + + struct { + __IOM uint8_t SPI_RFIFO_AFULL_LEV : 8; /*!< [7..0] These bits are used to program + the FIFO occupancy level to trigger the + Almost Full indication. */ + } SPI_RFIFO_AFULL_LEV_b; + }; + __IM uint8_t RESERVED2; + + union { + __IOM uint8_t SPI_RFIFO_AEMPTY_LEV; /*!< (@ 0x00000006) SPI WFIFO Almost + Empty Register. */ + + struct { + __IOM uint8_t SPI_RFIFO_AEMPTY_LEV : 8; /*!< [7..0] These bits are used to + program the occupancy level to + trigger the Almost Empty + indication. */ + } SPI_RFIFO_AEMPTY_LEV_b; + }; + __IM uint8_t RESERVED3; + + union { + __IOM uint8_t SPI_MODE; /*!< (@ 0x00000008) SPI Mode Register. */ + + struct { + __IOM uint8_t SPI_OP_MODE : 1; /*!< [0..0] This bit is used to program the + mode of working of SPI Interface. */ + __IOM uint8_t SPI_FIX_EN : 1; /*!< [1..1] This bit is used to enable the + fix made for bus_ctrl_busy being asserted + when success_state is being asserted + getting deasserted when FSM has decided + to move to BUSY_STATE or not. */ + __IOM uint8_t VHS_EN : 1; /*!< [2..2] This bit is used to enable Very high + speed mode (120Mhz). */ + __IOM uint8_t BYPASS_INIT : 1; /*!< [3..3] This bit is used to bypass the + SPI initialization.0 - + Doesn't bypass,1 - bypasses + SPI initialization */ + __IOM uint8_t RESERVED1 : 4; /*!< [7..4] reserved1 */ + } SPI_MODE_b; + }; + __IM uint8_t RESERVED4; + + union { + __IOM uint16_t SPI_INTR_STATUS; /*!< (@ 0x0000000A) SPI interrupt status register. */ + + struct { + __IOM uint16_t SPI_WR_REQ : 1; /*!< [0..0] Write request received. */ + __IOM uint16_t SPI_RD_REQ : 1; /*!< [1..1] Read request received. */ + __IOM uint16_t SPI_CS_DEASSERT : 1; /*!< [2..2] SPI chip deassert interrupt. */ + __IOM uint16_t RESERVED1 : 13; /*!< [15..3] reserved1 */ + } SPI_INTR_STATUS_b; + }; + + union { + __IOM uint16_t SPI_INTR_EN; /*!< (@ 0x0000000C) SPI interrupt enable register. */ + + struct { + __IOM uint16_t SPI_WR_INT_EN : 1; /*!< [0..0] This bit is used to enable + the write interrupt. */ + __IOM uint16_t SPI_RD_INT_EN : 1; /*!< [1..1] This bit is used to enable + the read interrupt. */ + __IOM uint16_t SPI_CS_DEASSERT_INT_EN : 1; /*!< [2..2] This bit is used to enable the + interrupt due to wrong deassertion of + CS. */ + __IOM uint16_t RESERVED1 : 13; /*!< [15..3] reserved1 */ + } SPI_INTR_EN_b; + }; + + union { + __IOM uint16_t SPI_INTR_MASK; /*!< (@ 0x0000000E) SPI interrupt Mask register */ + + struct { + __IOM uint16_t SPI_WR_INTR_MSK : 1; /*!< [0..0] This bit is used to mask + the write interrupt. */ + __IOM uint16_t SPI_RD_INTR_MSK : 1; /*!< [1..1] This bit is used to mask + the read interrupt. */ + __IOM uint16_t SPI_CS_DEASSERT_INT_MSK : 1; /*!< [2..2] This bit is used to mask the + CS deassertion interrupt. */ + __IOM uint16_t RESERVED1 : 13; /*!< [15..3] reserved1 */ + } SPI_INTR_MASK_b; + }; + + union { + __IOM uint16_t SPI_INTR_UNMASK; /*!< (@ 0x00000010) SPI interrupt unmask register */ + + struct { + __IOM uint16_t SPI_WR_INT_UNMASK : 1; /*!< [0..0] This bit is used to + unmask the write interrupt. */ + __IOM uint16_t SPI_RD_INTR_UNMSK : 1; /*!< [1..1] This bit is used to + unmask the read interrupt. */ + __IOM uint16_t SPI_CS_DEASSERT_INT_UNMSK : 1; /*!< [2..2] This bit is used to unmask + the CS deassertion interrupt. */ + __IOM uint16_t RESERVED1 : 13; /*!< [15..3] reserved1 */ + } SPI_INTR_UNMASK_b; + }; + + union { + __IM uint16_t SPI_LENGTH; /*!< (@ 0x00000012) SPI Length Register */ + + struct { + __IM uint16_t SPI_LEN : 16; /*!< [15..0] These bit indicate the length of + the transfer as transmitted + in the Commands C3 and C4. + */ + } SPI_LENGTH_b; + }; + + union { + __IM uint16_t SPI_COMMAND; /*!< (@ 0x00000014) SPI Command Register */ + + struct { + __IM uint16_t SPI_C1 : 8; /*!< [7..0] These bits store the received command C1. */ + __IM uint16_t SPI_C2 : 8; /*!< [15..8] These bits store the received + command C2. */ + } SPI_COMMAND_b; + }; + + union { + __IM uint16_t SPI_DEV_ID; /*!< (@ 0x00000016) SPI Device ID Register */ + + struct { + __IM uint16_t SPI_DEVID : 16; /*!< [15..0] These bits store the Device ID + information. */ + } SPI_DEV_ID_b; + }; + + union { + __IM uint16_t SPI_VERSION; /*!< (@ 0x00000018) SPI Device ID Register */ + + struct { + __IM uint16_t SPI_VERNO : 8; /*!< [7..0] These bits store the version number. */ + __IM uint16_t RESERVED1 : 8; /*!< [15..8] reserved1 */ + } SPI_VERSION_b; + }; + + union { + __IM uint16_t SPI_STATUS; /*!< (@ 0x0000001A) SPI Status Register */ + + struct { + __IM uint16_t SPI_RFIFO_FULL : 1; /*!< [0..0] This bit indicates if the + read FIFO is almost full. */ + __IM uint16_t SPI_RFIFO_AFULL : 1; /*!< [1..1] This bit indicates if the + read FIFO is almost full. */ + __IM uint16_t SPI_WFIFO_EMPTY : 1; /*!< [2..2] This bit indicates if write + FIFO is empty. */ + __IM uint16_t SPI_WFIFO_AEMPTY : 1; /*!< [3..3] This bit indicates if + write FIFO is almost empty. */ + __IM uint16_t SPI_RFIFO_EMPTY : 1; /*!< [4..4] This bit indicates if read FIFO is + empty (Read from SOC to host). */ + __IM uint16_t SPI_RFIFO_AEMPTY : 1; /*!< [5..5] This bit indicates if read FIFO is + empty (Read from SOC to host). */ + __IM uint16_t SPI_WFIFO_FULL : 1; /*!< [6..6] This bit indicates if write FIFO is + full (Write from Host to SOC). */ + __IM uint16_t SPI_WFIFO_AFULL : 1; /*!< [7..7] This bit indicates if write FIFO is + full (Write from Host to SOC). */ + __IM uint16_t RESERVED1 : 8; /*!< [15..8] reserved1 */ + } SPI_STATUS_b; + }; + + union { + __IM uint16_t SPI_BC_STATE; /*!< (@ 0x0000001C) SPI Bus Controller State Register */ + + struct { + __IM uint16_t SPI_BC : 14; /*!< [13..0] These bits indicate the Bus + Controller FSM state. */ + __IM uint16_t RESERVED1 : 2; /*!< [15..14] reserved1 */ + } SPI_BC_STATE_b; + }; + __IM uint16_t RESERVED5; + __IM uint32_t RESERVED6[23]; + + union { + __IOM uint16_t SPI_SYS_RESET_REQ; /*!< (@ 0x0000007C) SPI SYS Reset Req Register */ + + struct { + __IOM + uint16_t SPI_SYS_RESET_REQ : 1; /*!< [0..0] When set generates system reset + request to reset controller. This gets + reset once, reset controller generates + reset. Host should not reset this bit. + With this reset request, reset + controller generates non por reset. */ + __IOM uint16_t RESERVED1 : 15; /*!< [15..1] reserved1 */ + } SPI_SYS_RESET_REQ_b; + }; + + union { + __IOM uint16_t SPI_WAKE_UP; /*!< (@ 0x0000007E) SPI Wakeup Register */ + + struct { + __IOM uint16_t SPI_WAKEUP : 1; /*!< [0..0] Wakeup Interrupt,Interrupt for waking up + the system from Deep Sleep. */ + __IOM uint16_t SPI_DEEP_SLEEP_ST : 1; /*!< [1..1] Deep Sleep Start,Indicates the + device to enter Deep Sleep + state for maximum power save. */ + __IOM uint16_t RESERVED1 : 14; /*!< [15..2] reserved1 */ + } SPI_WAKE_UP_b; + }; + __IM uint32_t RESERVED7[192]; + + union { + __IM uint32_t SPI_RFIFO_DATA; /*!< (@ 0x00000380) SPI RFIFO Data Register */ + + struct { + __IM uint32_t SPI_RFIFO : 32; /*!< [31..0] These bits store the data + received from the host */ + } SPI_RFIFO_DATA_b; + }; + __IM uint32_t RESERVED8[15]; + + union { + __OM uint32_t SPI_WFIFO_DATA; /*!< (@ 0x000003C0) SPI WFIFO Data Register */ + + struct { + __OM uint32_t SPI_WFIFO : 32; /*!< [31..0] These bits are used to write, + the data to be sent to the host. */ + } SPI_WFIFO_DATA_b; + }; +} SPI_SLAVE_Type; /*!< Size = 964 (0x3c4) */ + +/* =========================================================================================================================== + */ +/* ================ M4CLK + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief MCU HP (High Performance) domain contains the Cortex-M4F Processor, + * FPU, Debugger, MCU High Speed Interfaces, MCU HP Peripherals, MCU HP DMA and + * MCU/SZP shareable Interfaces (M4CLK) + */ + +typedef struct { /*!< (@ 0x46000000) M4CLK Structure */ + + union { + __IOM uint32_t CLK_ENABLE_SET_REG1; /*!< (@ 0x00000000) Clock Enable Set + Register 1 */ + + struct { + __IOM uint32_t USART1_PCLK_ENABLE_b : 1; /*!< [0..0] Static Clock gating Enable for + usart1 pclk1'b1 => Clock + is enabled 1'b0 => Invalid */ + __IOM uint32_t USART1_SCLK_ENABLE_b : 1; /*!< [1..1] Static Clock gating Enable for + usart1 sclk1'b1 => Clock + is enabled 1'b0 => Invalid */ + __IOM uint32_t USART2_PCLK_ENABLE_b : 1; /*!< [2..2] Static Clock gating Enable for + usart2 pclk1'b1 => Clock + is enabled 1'b0 => Invalid */ + __IOM uint32_t USART2_SCLK_ENABLE_b : 1; /*!< [3..3] Static Clock gating Enable for + usart2 sclk1'b1 => Clock + is enabled 1'b0 => Invalid */ + __IOM uint32_t Reserved1 : 5; /*!< [8..4] It is recommended to write these + bits to 0. */ + __IOM uint32_t CT_CLK_ENABLE_b : 1; /*!< [9..9] Static Clock gating Enable + for sct clk1'b1 => Clock is + enabled 1'b0 => Invalid. */ + __IOM uint32_t CT_PCLK_ENABLE_b : 1; /*!< [10..10] Static Clock gating + Enable for sct pclk1'b1 => Clock + is enabled 1'b0 => Invalid. */ + __IOM uint32_t ICACHE_CLK_ENABLE_b : 1; /*!< [11..11] Static Clock gating Enable for + icache clk1'b1 => Clock + is enabled 1'b0 => Invalid. */ + __IOM uint32_t ICACHE_CLK_2X_ENABLE_b : 1; /*!< [12..12] Static Clock gating Enable + for icache 2x clk1'b1 => Clock is + enabled 1'b0 => Invalid. */ + __IOM uint32_t RPDMA_HCLK_ENABLE_b : 1; /*!< [13..13] Static Clock gating Enable for + rpdma hclk1'b1 => Clock + is enabled 1'b0 => Invalid. */ + __IOM uint32_t SOC_PLL_SPI_CLK_ENABLE_b : 1; /*!< [14..14] Static Clock gating Enable + for soc pll spi clk1'b1 + => Clock is enabled 1'b0 => Invalid. + */ + __IOM uint32_t Reserved2 : 1; /*!< [15..15] It is recommended to write + these bits to 0. */ + __IOM uint32_t IID_CLK_ENABLE_b : 1; /*!< [16..16] Static Clock gating + Enable for iid clk1'b1 => Clock + is enabled 1'b0 => Invalid. */ + __IOM uint32_t SDIO_SYS_HCLK_ENABLE_b : 1; /*!< [17..17] Static Clock gating Enable + for sdio sys hclk1'b1 => Clock is + enabled 1'b0 => Invalid */ + __IOM uint32_t CRC_CLK_ENABLE_b : 1; /*!< [18..18] Static Clock gating + Enable for crc clk1'b1 => Clock + is enabled 1'b0 => Invalid */ + __IOM uint32_t Reserved3 : 3; /*!< [21..19] It is recommended to write + these bits to 0. */ + __IOM uint32_t HWRNG_PCLK_ENABLE_b : 1; /*!< [22..22] Static Clock gating Enable for + HWRNG pclk1'b1 => Clock + is enabled 1'b0 => Invalid. */ + __IOM uint32_t GNSS_MEM_CLK_ENABLE_b : 1; /*!< [23..23] Static Clock gating Enable + for GNSS mem clk1'b1 => + Clock is enabled 1'b0 => Invalid */ + __IOM uint32_t Reserved4 : 3; /*!< [26..24] It is recommended to write + these bits to 0. */ + __IOM uint32_t MASK_HOST_CLK_WAIT_FIX_b : 1; /*!< [27..27] This bit decides whether + to wait for a fixed number of xtal + clock cycles(based on + mask31_host_clk_cnt) or wait for a + internally generated signal to come + out of WAIT state in host mux FSM 1'b1 + => Wait for fixed number of xtal clk + cycles 1'b0 => Invalid This bit along + with mask_host_clk_available_fix and + mask31_host_clk_cnt are to take care + in case of any bugs. */ + __IOM uint32_t MASK31_HOST_CLK_CNT_b : 1; /*!< [28..28] When mask_host_clk_wait_fix + is 1'b1, this bit decides whether to + count for 32 0r 16 xtal clock cycles to + come out of WAIT state in host mux FSM + 1'b1 => Wait for 32 clock cycles 1'b0 => + Invalid This bit along with + mask_host_clk_available_fix and + mask_host_clk_wait_fix are to take care + in case of any bugs. */ + __IOM uint32_t Reserved5 : 1; /*!< [29..29] It is recommended to write + these bits to 0. */ + __IOM uint32_t MASK_HOST_CLK_AVAILABLE_FIX_b : 1; /*!< [30..30] This bit decides + whether to consider negedge of + host_clk_available in the + generation of clock enable for + host_clk gate in host mux 1'b1 + => Don't consider 1'b0 => + Invalid This bit along with + mask_host_clk_wait_fix and + mask31_host_clk_cnt + are to take care in case + of any bugs. */ + __IOM uint32_t ULPSS_CLK_ENABLE_b : 1; /*!< [31..31] Static Clock gating Enable for + m4 soc_clk to ulpss1'b1 + => Clock is enabled 1'b0 => Invalid. + */ + } CLK_ENABLE_SET_REG1_b; + }; + + union { + __IOM uint32_t CLK_ENABLE_CLEAR_REG1; /*!< (@ 0x00000004) Clock Enable Clear + Register 1 */ + + struct { + __IOM uint32_t USART1_PCLK_ENABLE_b : 1; /*!< [0..0] Static Clock Clear + for usart1 pclk1'b1 => Clock + is Clear 1'b0 => Invalid */ + __IOM uint32_t USART1_SCLK_ENABLE_b : 1; /*!< [1..1] Static Clock Clear + for usart1 sclk1'b1 => Clock + is Clear 1'b0 => Invalid */ + __IOM uint32_t USART2_PCLK_ENABLE_b : 1; /*!< [2..2] Static Clock Clear + for usart2 pclk 1'b1 => Clock + is Clear 1'b0 => Invalid */ + __IOM uint32_t USART2_SCLK_ENABLE_b : 1; /*!< [3..3] Static Clock Clear + for usart2 sclk1'b1 => Clock + is Clear 1'b0 => Invalid */ + __IOM uint32_t Reserved1 : 5; /*!< [8..4] It is recommended to write these + bits to 0. */ + __IOM uint32_t CT_CLK_ENABLE_b : 1; /*!< [9..9] Static Clock Clear for sct clk1'b1 => + Clock is Clear 1'b0 => Invalid. */ + __IOM uint32_t CT_PCLK_ENABLE_b : 1; /*!< [10..10] Static Clock Clear for + sct pclk1'b1 => Clock is Clear + 1'b0 => Invalid. */ + __IOM uint32_t ICACHE_CLK_ENABLE_b : 1; /*!< [11..11] Static Clock Clear + for icache clk1'b1 => Clock is + Clear 1'b0 => Invalid. */ + __IOM uint32_t ICACHE_CLK_2X_ENABLE_b : 1; /*!< [12..12] Static Clock Clear for + icache 2x clk1'b1 => Clock is Clear + 1'b0 => Invalid. */ + __IOM uint32_t RPDMA_HCLK_ENABLE_b : 1; /*!< [13..13] Static Clock Clear + for rpdma hclk1'b1 => Clock is + Clear 1'b0 => Invalid. */ + __IOM uint32_t SOC_PLL_SPI_CLK_ENABLE_b : 1; /*!< [14..14] Static Clock Clear for soc + pll spi clk1'b1 => Clock + is Clear 1'b0 => Invalid. */ + __IOM uint32_t Reserved2 : 1; /*!< [15..15] It is recommended to write + these bits to 0. */ + __IOM uint32_t IID_CLK_ENABLE_b : 1; /*!< [16..16] Static Clock Clear for iid clk1'b1 + => Clock is Clear 1'b0 => Invalid. */ + __IOM uint32_t SDIO_SYS_HCLK_ENABLE_b : 1; /*!< [17..17] Static Clock Clear for sdio + sys hclk1'b1 => Clock is + Clear 1'b0 => Invalid */ + __IOM uint32_t CRC_CLK_ENABLE_b : 1; /*!< [18..18] Static Clock Clear for crc clk1'b1 + => Clock is Clear 1'b0 => Invalid */ + __IOM uint32_t Reserved3 : 3; /*!< [21..19] It is recommended to write + these bits to 0. */ + __IOM uint32_t HWRNG_PCLK_ENABLE_b : 1; /*!< [22..22] Static Clock Clear + for HWRNG pclk1'b1 => Clock is + Clear 1'b0 => Invalid. */ + __IOM uint32_t GNSS_MEM_CLK_ENABLE_b : 1; /*!< [23..23] Static Clock Clear + for GNSS mem clk1'b1 => Clock + is Clear 1'b0 => Invalid */ + __IOM uint32_t Reserved4 : 3; /*!< [26..24] It is recommended to write + these bits to 0. */ + __IOM uint32_t MASK_HOST_CLK_WAIT_FIX_b : 1; /*!< [27..27] This bit decides whether + to wait for a fixed number of xtal + clock cycles(based on + mask31_host_clk_cnt) or wait for a + internally generated signal to come + out of WAIT state in host mux FSM 1'b1 + => Wait for fixed number of xtal clk + cycles 1'b0 => Invalid This bit along + with mask_host_clk_available_fix and + mask31_host_clk_cnt are to take care + in case of any bugs. */ + __IOM uint32_t MASK31_HOST_CLK_CNT_b : 1; /*!< [28..28] When mask_host_clk_wait_fix + is 1'b1, this bit decides whether to + count for 32 0r 16 xtal clock cycles to + come out of WAIT state in host mux FSM + 1'b1 => Wait for 32 clock cycles 1'b0 => + Invalid This bit along with + mask_host_clk_available_fix and + mask_host_clk_wait_fix are to take care + in case of any bugs. */ + __IOM uint32_t Reserved5 : 1; /*!< [29..29] It is recommended to write + these bits to 0. */ + __IOM uint32_t MASK_HOST_CLK_AVAILABLE_FIX_b : 1; /*!< [30..30] This bit decides + whether to consider negedge of + host_clk_available in the + generation of clock enable for + host_clk gate in host mux 1'b1 + => Don't consider 1'b0 => + Invalid This bit along with + mask_host_clk_wait_fix and + mask31_host_clk_cnt + are to take care in case + of any bugs. */ + __IOM uint32_t ULPSS_CLK_ENABLE_b : 1; /*!< [31..31] Static Clock gating Enable for + m4 soc_clk to ulpss1'b1 + => Clock is enabled 1'b0 => Invalid. + */ + } CLK_ENABLE_CLEAR_REG1_b; + }; + + union { + __IOM uint32_t CLK_ENABLE_SET_REG2; /*!< (@ 0x00000008) Clock Enable Set + Register 2 */ + + struct { + __IOM uint32_t GEN_SPI_MST1_HCLK_ENABLE_b : 1; /*!< [0..0] Static Clock gating Enable + for gen spi master1 hclk 1'b1 + => Clock is enabled 1'b0 + => Invalid */ + __IOM uint32_t Reserved1 : 5; /*!< [5..1] It is recommended to write these + bits to 0. */ + __IOM uint32_t UDMA_HCLK_ENABLE_b : 1; /*!< [6..6] Static Clock gating Enable for + udma hclk 1'b1 => Clock + is enabled 1'b0 => Invalid. */ + __IOM uint32_t I2C_BUS_CLK_ENABLE_b : 1; /*!< [7..7] Static Clock gating Enable for + i2c-1 bus clk1'b1 => Clock is enabled + 1'b0 => Invalid. */ + __IOM uint32_t I2C_2_BUS_CLK_ENABLE_b : 1; /*!< [8..8] Static Clock gating Enable for + i2c-2 bus clk 1'b1 => + Clock is enabled 1'b0 => Invalid. */ + __IOM uint32_t SSI_SLV_PCLK_ENABLE_b : 1; /*!< [9..9] Static Clock gating Enable for + ssi slave pclk 1'b1 => + Clock is enabled 1'b0 => Invalid. */ + __IOM + uint32_t SSI_SLV_SCLK_ENABLE_b : 1; /*!< [10..10] Static Clock gating + Enable for ssi slave sclk 1'b1 + => Clock is enabled 1'b0 => + Invalid. */ + __IOM uint32_t QSPI_CLK_ENABLE_b : 1; /*!< [11..11] Static Clock gating + Enable for qspi clk 1'b1 => Clock + is enabled 1'b0 => Invalid. */ + __IOM uint32_t QSPI_HCLK_ENABLE_b : 1; /*!< [12..12] Static Clock gating Enable for + qspi hclk 1'b1 => Clock + is enabled 1'b0 => Invalid. */ + __IOM uint32_t I2SM_SCLK_ENABLE_b : 1; /*!< [13..13] Static Clock gating Enable for + sclk of I2S at Root Clock generation 1'b1 + => Clock is enabled 1'b0 => Invalid. */ + __IOM uint32_t I2SM_INTF_SCLK_ENABLE_b : 1; /*!< [14..14] Static Clock gating Enable + for i2s interface sclk 1'b1 + => Clock is enabled 1'b0 => Invalid. + */ + __IOM uint32_t I2SM_PCLK_ENABLE_b : 1; /*!< [15..15] Static Clock gating Enable for + i2s master pclk 1'b1 + => Clock is enabled 1'b0 => Invalid. */ + __IOM uint32_t Reserved2 : 1; /*!< [16..16] It is recommended to write + these bits to 0. */ + __IOM uint32_t QE_PCLK_ENABLE_b : 1; /*!< [17..17] Static Clock gating Enable for qe + pclk 1'b1 => Clock is enabled 1'b0 => + Invalid. */ + __IOM uint32_t MCPWM_PCLK_ENABLE_b : 1; /*!< [18..18] Static Clock gating Enable for + mcpwm pclk 1'b1 => Clock is enabled 1'b0 + => Invalid. */ + __IOM uint32_t Reserved3 : 1; /*!< [19..19] It is recommended to write + these bits to 0. */ + __IOM uint32_t SGPIO_PCLK_ENABLE_b : 1; /*!< [20..20] Static Clock gating Enable for + sgpio pclk 1'b1 => Clock is enabled 1'b0 + => Invalid. */ + __IOM uint32_t EGPIO_PCLK_ENABLE_b : 1; /*!< [21..21] Static Clock gating Enable for + egpio pclk 1'b1 => Clock is enabled 1'b0 + => Invalid. */ + __IOM uint32_t ARM_CLK_ENABLE_b : 1; /*!< [22..22] Static Clock gating + Enable for arm clk 1'b1 => Clock + is enabled 1'b0 => Invalid. */ + __IOM uint32_t SSI_MST_PCLK_ENABLE_b : 1; /*!< [23..23] Static Clock gating Enable + for ssi master pclk 1'b1 + => Clock is enabled 1'b0 => Invalid. + */ + __IOM uint32_t SSI_MST_SCLK_ENABLE_b : 1; /*!< [24..24] Static Clock gating Enable + for ssi master sclk 1'b1 + => Clock is enabled 1'b0 => Invalid. + */ + __IOM uint32_t Reserved4 : 1; /*!< [25..25] It is recommended to write + these bits to 0. */ + __IOM uint32_t MEM_CLK_ULP_ENABLE_b : 1; /*!< [26..26] Static Clock gating Enable for + mem ulp clk 1'b1 => + Clock is enabled 1'b0 => Invalid. */ + __IOM uint32_t ROM_CLK_ENABLE_b : 1; /*!< [27..27] Static Clock gating + Enable for rom clk 1'b1 => Clock + is enabled 1'b0 => Invalid. */ + __IOM uint32_t PLL_INTF_CLK_ENABLE_b : 1; /*!< [28..28] Static Clock gating Enable + for pll intf clk 1'b1 => Clock is + enabled 1'b0 => Invalid. */ + __IOM uint32_t Reserved5 : 3; /*!< [31..29] It is recommended to write + these bits to 0. */ + } CLK_ENABLE_SET_REG2_b; + }; + + union { + __IOM uint32_t CLK_ENABLE_CLEAR_REG2; /*!< (@ 0x0000000C) Clock Enable Clear + Register 2 */ + + struct { + __IOM uint32_t GEN_SPI_MST1_HCLK_ENABLE_b : 1; /*!< [0..0] Static Clock Clear for gen + spi master1 hclk 1'b1 => Clock is + Clear 1'b0 => Invalid */ + __IOM uint32_t Reserved1 : 5; /*!< [5..1] It is recommended to write these + bits to 0. */ + __IOM uint32_t UDMA_HCLK_ENABLE_b : 1; /*!< [6..6] Static Clock Clear for + udma hclk 1'b1 => Clock is Clear + 1'b0 => Invalid. */ + __IOM uint32_t I2C_BUS_CLK_ENABLE_b : 1; /*!< [7..7] Static Clock Clear + for i2c-1 bus clk1'b1 => Clock + is Clear 1'b0 => Invalid. */ + __IOM uint32_t I2C_2_BUS_CLK_ENABLE_b : 1; /*!< [8..8] Static Clock Clear for i2c-2 + bus clk 1'b1 => Clock is + Clear 1'b0 => Invalid. */ + __IOM uint32_t SSI_SLV_PCLK_ENABLE_b : 1; /*!< [9..9] Static Clock Clear for ssi + slave pclk 1'b1 => Clock is Clear 1'b0 + => Invalid. */ + __IOM uint32_t SSI_SLV_SCLK_ENABLE_b : 1; /*!< [10..10] Static Clock Clear for ssi + slave sclk 1'b1 => Clock is Clear 1'b0 + => Invalid. */ + __IOM uint32_t QSPI_CLK_ENABLE_b : 1; /*!< [11..11] Static Clock Clear for qspi clk + 1'b1 => Clock is Clear 1'b0 => Invalid. */ + __IOM uint32_t QSPI_HCLK_ENABLE_b : 1; /*!< [12..12] Static Clock Clear + for qspi hclk 1'b1 => Clock is + Clear 1'b0 => Invalid. */ + __IOM uint32_t I2SM_SCLK_ENABLE_b : 1; /*!< [13..13] Static Clock Clear + for sclk of I2S at Root Clock + generation 1'b1 => Clock is + Clear 1'b0 => Invalid. */ + __IOM uint32_t I2SM_INTF_SCLK_ENABLE_b : 1; /*!< [14..14] Static Clock Clear for i2s + interface sclk 1'b1 => Clock + is Clear 1'b0 => Invalid. */ + __IOM uint32_t I2SM_PCLK_ENABLE_b : 1; /*!< [15..15] Static Clock Clear for i2s + master pclk 1'b1 => Clock + is Clear 1'b0 => Invalid. */ + __IOM uint32_t Reserved2 : 1; /*!< [16..16] It is recommended to write + these bits to 0. */ + __IOM uint32_t QE_PCLK_ENABLE_b : 1; /*!< [17..17] Static Clock Clear for qe pclk + 1'b1 => Clock is Clear 1'b0 => Invalid. */ + __IOM uint32_t MCPWM_PCLK_ENABLE_b : 1; /*!< [18..18] Static Clock Clear + for mcpwm pclk 1'b1 => Clock is + Clear 1'b0 => Invalid. */ + __IOM uint32_t Reserved3 : 1; /*!< [19..19] It is recommended to write + these bits to 0. */ + __IOM uint32_t SGPIO_PCLK_ENABLE_b : 1; /*!< [20..20] Static Clock Clear + for sgpio pclk 1'b1 => Clock is + Clear 1'b0 => Invalid. */ + __IOM uint32_t EGPIO_PCLK_ENABLE_b : 1; /*!< [21..21] Static Clock Clear + for egpio pclk 1'b1 => Clock is + Clear 1'b0 => Invalid. */ + __IOM uint32_t ARM_CLK_ENABLE_b : 1; /*!< [22..22] Static Clock Clear for arm clk + 1'b1 => Clock is Clear 1'b0 => Invalid. */ + __IOM uint32_t SSI_MST_PCLK_ENABLE_b : 1; /*!< [23..23] Static Clock Clear for ssi + master pclk 1'b1 => Clock + is Clear 1'b0 => Invalid. */ + __IOM uint32_t SSI_MST_SCLK_ENABLE_b : 1; /*!< [24..24] Static Clock Clear for ssi + master sclk 1'b1 => Clock + is Clear 1'b0 => Invalid. */ + __IOM uint32_t Reserved4 : 1; /*!< [25..25] It is recommended to write + these bits to 0. */ + __IOM uint32_t MEM_CLK_ULP_ENABLE_b : 1; /*!< [26..26] Static Clock Clear + for mem ulp clk 1'b1 => Clock + is Clear 1'b0 => Invalid. */ + __IOM uint32_t ROM_CLK_ENABLE_b : 1; /*!< [27..27] Static Clock Clear for rom clk + 1'b1 => Clock is Clear 1'b0 => Invalid. */ + __IOM uint32_t PLL_INTF_CLK_ENABLE_b : 1; /*!< [28..28] Static Clock Clear for pll + intf clk 1'b1 => Clock is + Clear 1'b0 => Invalid. */ + __IOM uint32_t Reserved5 : 3; /*!< [31..29] It is recommended to write + these bits to 0. */ + } CLK_ENABLE_CLEAR_REG2_b; + }; + + union { + __IOM uint32_t CLK_ENABLE_SET_REG3; /*!< (@ 0x00000010) Clock Enable Set + Register 3 */ + + struct { + __IOM uint32_t BUS_CLK_ENABLE_b : 1; /*!< [0..0] Static Clock gating + Enable for bus clk 1'b1 => Clock + is enabled 1'b0 => Invalid */ + __IOM uint32_t M4_CORE_CLK_ENABLE_b : 1; /*!< [1..1] Static Clock gating Enable for + M4 Core clk 1'b1 => Clock + is enabled 1'b0 => Invalid. */ + __IOM uint32_t CM_BUS_CLK_ENABLE_b : 1; /*!< [2..2] Static Clock gating Enable for cm + bus clk1'b1 => Clock is enabled1'b0 => + Invalid. */ + __IOM uint32_t Reserved1 : 1; /*!< [3..3] It is recommended to write these + bits to 0. */ + __IOM uint32_t MISC_CONFIG_PCLK_ENABLE_b : 1; /*!< [4..4] Static Clock gating Enable + for misc config regs clk 1'b1 + => Clock is enabled 1'b0 => + Invalid. */ + __IOM uint32_t EFUSE_CLK_ENABLE_b : 1; /*!< [5..5] Static Clock gating Enable for + efuse clk 1'b1 => Clock + is enabled 1'b0 => Invalid. */ + __IOM uint32_t ICM_CLK_ENABLE_b : 1; /*!< [6..6] Static Clock gating Enable for icm + clk 1'b1 => Clock + is enabled 1'b0 => Invalid. */ + __IOM uint32_t Reserved2 : 6; /*!< [12..7] It is recommended to write + these bits to 0. */ + __IOM uint32_t QSPI_CLK_ONEHOT_ENABLE_b : 1; /*!< [13..13] Static Clock gating Enable + for QSPI clock generated from the + dynamic mux 1b1 - Clock is enabled 1b0 + - Invalid. */ + __IOM uint32_t QSPI_M4_SOC_SYNC_b : 1; /*!< [14..14] Specifies whether QSPI clock is + in sync with Soc clock. Before enabling + this make sure that qspi_clk_onehot_enable + is 1b0 to enable glitch free switching + 1b1 - QSPI clock is in sync with M4 clock + 1b0 - Invalid. */ + __IOM uint32_t Reserved3 : 1; /*!< [15..15] It is recommended to write + these bits to 0. */ + __IOM uint32_t EGPIO_CLK_ENABLE_b : 1; /*!< [16..16] Static Clock gating enable for + Enhanced-GPIO 1b1 - + Clock is enabled 1b0 - Invalid. */ + __IOM uint32_t I2C_CLK_ENABLE_b : 1; /*!< [17..17] Static Clock gating enable for + I2C-1 Module 1b1 - Clock is enabled 1b0 - + Invalid. */ + __IOM uint32_t I2C_2_CLK_ENABLE_b : 1; /*!< [18..18] Static Clock gating enable for + I2C-2 Module 1b1 - Clock is enabled 1b0 - + Invalid. */ + __IOM uint32_t EFUSE_PCLK_ENABLE_b : 1; /*!< [19..19] Static Clock gating + enable for EFUSE APB Interface + 1b1 - Clock is enabled 1b0 + - Invalid. */ + __IOM uint32_t SGPIO_CLK_ENABLE_b : 1; /*!< [20..20] Static Clock gating enable for + SIO Module 1b1 - Clock is enabled 1b0 - + Invalid. */ + __IOM uint32_t TASS_M4SS_64K_SWITCH_CLK_ENABLE_b : 1; /*!< [21..21] Unused. */ + __IOM uint32_t TASS_M4SS_128K_SWITCH_CLK_ENABLE_b : 1; /*!< [22..22] Unused. */ + __IOM uint32_t TASS_M4SS_SDIO_SWITCH_CLK_ENABLE_b : 1; /*!< [23..23] Unused. */ + __IOM uint32_t Reserved4 : 1; /*!< [24..24] It is recommended to write + these bits to 0. */ + __IOM uint32_t ROM_MISC_STATIC_ENABLE_b : 1; /*!< [25..25] Static Clock gating enable + for rom ahb Clock 1b1 - Clock is + enabled 1b0 - Invalid. */ + __IOM uint32_t M4_SOC_CLK_FOR_OTHER_ENABLE_b : 1; /*!< [26..26] Static Clock gating + enable for M4-SOC Other Clock + 1b1 + - Clock is enabled 1b0 - + Invalid. */ + __IOM uint32_t ICACHE_ENABLE_b : 1; /*!< [27..27] Static Clock gating enable for + Icache. This has to be enable for Icache + operations. 1b1 - Clock is enabled 1b0 - + Invalid. */ + __IOM uint32_t Reserved5 : 4; /*!< [31..28] It is recommended to write + these bits to 0. */ + } CLK_ENABLE_SET_REG3_b; + }; + + union { + __IOM uint32_t CLK_ENABLE_CLEAR_REG3; /*!< (@ 0x00000014) Clock Enable Clear + Register 3 */ + + struct { + __IOM uint32_t BUS_CLK_ENABLE_b : 1; /*!< [0..0] Static Clock Clear for bus clk 1'b1 + => Clock is Clear 1'b0 => Invalid */ + __IOM uint32_t M4_CORE_CLK_ENABLE_b : 1; /*!< [1..1] Static Clock Clear + for M4 Core clk 1'b1 => Clock + is Clear 1'b0 => Invalid. */ + __IOM uint32_t CM_BUS_CLK_ENABLE_b : 1; /*!< [2..2] Static Clock gating Enable for cm + bus clk1'b1 => Clock is enabled1'b0 => + Invalid. */ + __IOM uint32_t Reserved1 : 1; /*!< [3..3] It is recommended to write these + bits to 0. */ + __IOM uint32_t MISC_CONFIG_PCLK_ENABLE_b : 1; /*!< [4..4] Static Clock Clear for misc + config regs clk 1'b1 => Clock is + Clear 1'b0 => Invalid. */ + __IOM uint32_t EFUSE_CLK_ENABLE_b : 1; /*!< [5..5] Static Clock Clear for + efuse clk 1'b1 => Clock is Clear + 1'b0 => Invalid. */ + __IOM uint32_t ICM_CLK_ENABLE_b : 1; /*!< [6..6] Static Clock Clear for icm clk 1'b1 + => Clock is Clear 1'b0 => Invalid. */ + __IOM uint32_t Reserved2 : 6; /*!< [12..7] It is recommended to write + these bits to 0. */ + __IOM uint32_t QSPI_CLK_ONEHOT_ENABLE_b : 1; /*!< [13..13] Static Clock Clear for + QSPI clock generated from the + dynamic mux 1b1 - Clock is Gated 1b0 - + Invalid. */ + __IOM uint32_t QSPI_M4_SOC_SYNC_b : 1; /*!< [14..14] Specifies whether QSPI clock is + in sync with Soc clock. Before enabling + this make sure that qspi_clk_onehot_enable + is 1b0 to enable glitch free switching + 1b1 - QSPI clock is in sync with M4 clock + 1b0 - Invalid. */ + __IOM uint32_t Reserved3 : 1; /*!< [15..15] It is recommended to write + these bits to 0. */ + __IOM uint32_t EGPIO_CLK_ENABLE_b : 1; /*!< [16..16] Static Clock Disable for + Enhanced-GPIO 1b1 - Clock + is Disable 1b0 - Invalid. */ + __IOM uint32_t I2C_CLK_ENABLE_b : 1; /*!< [17..17] Static Clock Disable + for I2C-1 Module 1b1 - Clock is + Disable 1b0 - Invalid. */ + __IOM uint32_t I2C_2_CLK_ENABLE_b : 1; /*!< [18..18] Static Clock Disable + for I2C-2 Module 1b1 - Clock is + Disable 1b0 - Invalid. */ + __IOM uint32_t EFUSE_PCLK_ENABLE_b : 1; /*!< [19..19] Static Clock Disable for EFUSE + APB Interface 1b1 - + Clock is Disable 1b0 - Invalid. */ + __IOM uint32_t SGPIO_CLK_ENABLE_b : 1; /*!< [20..20] Static Clock gating enable for + SIO Module 1b1 - Clock is enabled 1b0 - + Invalid. */ + __IOM uint32_t TASS_M4SS_64K_SWITCH_CLK_ENABLE_b : 1; /*!< [21..21] Unused. */ + __IOM uint32_t TASS_M4SS_128K_SWITCH_CLK_ENABLE_b : 1; /*!< [22..22] Unused. */ + __IOM uint32_t TASS_M4SS_SDIO_SWITCH_CLK_ENABLE_b : 1; /*!< [23..23] Unused. */ + __IOM uint32_t Reserved4 : 1; /*!< [24..24] It is recommended to write + these bits to 0. */ + __IOM uint32_t ROM_MISC_STATIC_ENABLE_b : 1; /*!< [25..25] Static Clock Disable for + rom ahb Clock 1b1 - Clock is Disable + 1b0 - Invalid. */ + __IOM uint32_t M4_SOC_CLK_FOR_OTHER_ENABLE_b : 1; /*!< [26..26] Static Clock Disable + for M4-SOC Other Clock 1b1 - + Clock + is Disable 1b0 - Invalid. + */ + __IOM uint32_t ICACHE_ENABLE_b : 1; /*!< [27..27] Static Clock Disable for Icache. + This has to be enable for Icache operations. + 1b1 - Clock is Disable 1b0 - Invalid. */ + __IOM uint32_t Reserved5 : 4; /*!< [31..28] It is recommended to write + these bits to 0. */ + } CLK_ENABLE_CLEAR_REG3_b; + }; + + union { + __IOM uint32_t CLK_CONFIG_REG1; /*!< (@ 0x00000018) Clock Config Register 1 */ + + struct { + __IOM uint32_t QSPI_CLK_SEL : 3; /*!< [2..0] Selects one of the following clocks for + ssi master 000 + - ULP Ref Clock(generated inside M4SS based on + m4ss_ref_clk_sel from NPSS) 001 - Intf PLL Clock + Clock (program bypass_intf_pll_clk if the bypass + clock has to be selected) 010 - Modem PLL + Clock2(Not Intended for the programmer) + (program bypass_modem_pll_clk + if the bypass clock has to be selected) 011 - + SoC PLL Clock */ + __IOM uint32_t QSPI_CLK_DIV_FAC : 6; /*!< [8..3] Clock divison factor for QSPI. If + qspi_clk_enable is 1b0 clock is gated. Else + 1)when qspi_clk_swallow_sel is 1b1 and + qspi_odd_div_sel is 1b0 output clock is a + swallowed clock with the following frequency. + 6h0,6h1 => clk_out = clk_in >6h1 => clk_out = + clk_in/ qspi_clk_div_fac 2)when + qspi_clk_swallow_sel is 1b0 */ + __IOM + uint32_t QSPI_CLK_SWALLOW_SEL : 1; /*!< [9..9] Clock select for clock + swallow or clock divider for QSPI 1b0 + => 50% divider is selected with + division factor qspi_clk_div_fac 1b1 + => Swallowed clock is selected with + division factor qspi_clk_div_fac + Before Changing this ensure that the + input clocks are gated */ + __IOM uint32_t SLP_RF_CLK_SEL : 1; /*!< [10..10] clock select for + m4_soc_rf_ref_clk 0 - m4_soc_clk 1 + - rf_ref_clk. */ + __IOM uint32_t SSI_MST_SCLK_DIV_FAC : 4; /*!< [14..11] Clock division factor for + ssi_mst_sclk. If ssi_mst_sclk_enable is + 1b0 clock is gated. Else output clock is + a swallowed clock with the following + frequency. 4h0,4h1 => Divider + is bypassed >4h1 => clk_out = + clk_in/ ssi_mst_sclk_div_fac. */ + __IOM uint32_t SSI_MST_SCLK_SEL : 3; /*!< [17..15] Selects one of the following + clocks for ssi master 000 - ULP Ref + Clock(generated inside M4SS based on + m4ss_ref_clk_sel from NPSS) 001 - SoC PLL + Clock(program bypass_soc_pll_clk if the + bypass clock has to be selected) 010 - Modem + PLL Clock1(Not Intended for the programmer) + (program bypass_modem_pll_clk if the bypass + clock has to be selected) 011 - Intf PLL + Clock(program bypass_intf_pll_clk if + the */ + __IOM uint32_t PLL_INTF_CLK_SEL : 1; /*!< [18..18] Selects one of the following + clocks for pll intf clock 0 - Intf Pll + Clock(program bypass_intf_pll_clk if the + bypass clock has to be selected) 1 - SoC Pll + Clock(program bypass_soc_pll_clk if the + bypass clock has to be selected) */ + __IOM uint32_t PLL_INTF_CLK_DIV_FAC : 4; /*!< [22..19] Clock division factor for + pll_intf_clk. If pll_intf_clk_enable is + 1b0 clock is gated. Else, when + pll_intf_clk_swallow_sel is 1b1, output + clock is a swallowed clock. when + pll_intf_clk_swallow_sel is 1b0, output + clock is a 50 Per duty cycle clock. */ + __IOM uint32_t PLL_INTF_CLK_SWALLOW_SEL : 1; /*!< [23..23] Clock select for clock + swallow or clock divider for PLL INTF + Clk 1b0 - 50% divider is selected with + division factor 2; 1b1 - Swallowed + clock is selected with division + factor pll_intf_clk_div_fac */ + __IOM uint32_t GEN_SPI_MST1_SCLK_SEL : 3; /*!< [26..24] Selects one of the following + clocks for USART1 clk 000 - + m4_soc_clk_for_other_clocks 001 - ulp ref + Clock(generated inside M4SS based on + m4ss_ref_clk_sel from NPSS) 010 - SoC PLL + Clock(program bypass_soc_pll_clk if the + bypass clock has to be selected) 011 - + Modem PLL Clock2(Not Intended for the + pragrammer) (program bypass_modem_pll_clk + if the bypass clock has to be sele */ + __IOM uint32_t Reserved1 : 5; /*!< [31..27] It is recommended to write + these bits to 0. */ + } CLK_CONFIG_REG1_b; + }; + + union { + __IOM uint32_t CLK_CONFIG_REG2; /*!< (@ 0x0000001C) Clock Config Register 1 */ + + struct { + __IOM uint32_t USART1_SCLK_SEL : 3; /*!< [2..0] Selects one of the following clocks + for USART1 clk 000 + - ulp ref Clock(generated inside M4SS + based on m4ss_ref_clk_sel from NPSS) 001 - SoC + PLL Clock(program bypass_soc_pll_clk if the + bypass clock has to be selected) 010 - Modem + PLL Clock2(Not Intended for the + pragrammer)(program bypass_modem_pll_clk if + the bypass clock has to be selected) 011 - + Intf PLL + Clock(program bypass_intf_pll_clk if the b + */ + __IOM uint32_t USART1_SCLK_DIV_FAC : 4; /*!< [6..3] Clock division factor for USART1 + Clock. If usart1_sclk_enable is 1b0 clock + is gated. Else output clock is a swallowed + clock. */ + __IOM uint32_t USART2_SCLK_SEL : 3; /*!< [9..7] Selects one of the following clocks + for USART2 clk 000 + - ulp ref Clock(generated inside M4SS + based on m4ss_ref_clk_sel from NPSS) 001 - SoC + PLL Clock(program bypass_soc_pll_clk if the + bypass clock has to be selected) 010 - Modem + PLL Clock2(Not Intended for the + pragrammer)(program bypass_modem_pll_clk if + the bypass clock has to be selected) 011 - + Intf PLL + Clock(program bypass_intf_pll_clk if the b + */ + __IOM uint32_t USART2_SCLK_DIV_FAC : 4; /*!< [13..10] Clock division factor for + USART2 Clock. If usart2_sclk_enable is 1b0 + clock is gated. Else output clock is a + swallowed clock. */ + __IOM uint32_t Reserved1 : 14; /*!< [27..14] It is recommended to write + these bits to 0. */ + __IOM uint32_t QSPI_ODD_DIV_SEL : 1; /*!< [28..28] Clock select for clock swallow or + 50% even clock divider or 50% odd divider + clock for QSPI 1b1 - 50% odd clock divider + output is selected with division factor + qspi_clk_div_fac 1b0 - 50% even clock divider + output or swallowed is selected + with division factor qspi_clk_div_fac + based on qspi_clk_swallow_sel. */ + __IOM uint32_t USART1_SCLK_FRAC_SEL : 1; /*!< [29..29] Selects the type of divider + for uart1_clk 1b0 - Clock Swallow is + selected 1b1 - Fractional Divider is + selected. */ + __IOM uint32_t USART2_SCLK_FRAC_SEL : 1; /*!< [30..30] Selects the type of divider + for uart2_clk 1b0 - Clock Swallow is + selected 1b1 - Fractional Divider is + selected. */ + __IOM uint32_t USART3_SCLK_FRAC_SEL : 1; /*!< [31..31] Selects the type of divider + for uart3_clk 1b0 - Clock Swallow is + selected 1b1 - Fractional Divider is + selected. */ + } CLK_CONFIG_REG2_b; + }; + + union { + __IOM uint32_t CLK_CONFIG_REG3; /*!< (@ 0x00000020) Clock Config Register 3 */ + + struct { + __IOM uint32_t Reserved1 : 8; /*!< [7..0] It is recommended to write these + bits to 0. */ + __IOM uint32_t MCU_CLKOUT_SEL : 4; /*!< [11..8] Clock Select for the clock + on mcu_clkout (Mapped to GPIO) */ + __IOM uint32_t MCU_CLKOUT_DIV_FAC : 6; /*!< [17..12] Division factor for + mcu_clkout (Mapped to GPIO) */ + __IOM uint32_t MCU_CLKOUT_ENABLE : 1; /*!< [18..18] Clock Enable for the clock on + nwp_clkout (Mapped to GPIO) 1b0 - Clock is + Gated 1b1 - Clock is Enabled */ + __IOM uint32_t Reserved2 : 13; /*!< [31..19] It is recommended to write + these bits to 0. */ + } CLK_CONFIG_REG3_b; + }; + + union { + __IOM uint32_t CLK_CONFIG_REG4; /*!< (@ 0x00000024) Clock Config Register 4 */ + + struct { + __IOM uint32_t SOC_PLL_CLK_BYP_SEL : 2; /*!< [1..0] Selects one of the bypass clocks + for SoC PLL Clock */ + __IOM uint32_t I2S_PLL_CLK_BYP_SEL : 2; /*!< [3..2] Selects one of the bypass clocks + for I2S PLL Clock */ + __IOM uint32_t MODEM_PLL_CLK_BYP_SEL : 2; /*!< [5..4] Selects one of the bypass + clocks for Modem PLL Clock */ + __IOM uint32_t INTF_PLL_CLK_BYP_SEL : 2; /*!< [7..6] Selects one of the bypass clocks + for Intf PLL Clock */ + __IOM uint32_t SOC_INTF_PLL_BYPCLK_CLKCLNR_ON : 1; /*!< [8..8] Clock cleaner ON + Control for SoC PLL Bypass + Clock */ + __IOM uint32_t SOC_INTF_PLL_BYPCLK_CLKCLNR_OFF : 1; /*!< [9..9] Clock cleaner OFF + Control for SoC PLL Bypass + Clock */ + __IOM uint32_t Reserved1 : 2; /*!< [11..10] It is recommended to write + these bits to 0. */ + __IOM uint32_t I2S_PLL_BYPCLK_CLKCLNR_ON : 1; /*!< [12..12] Clock cleaner ON Control + for I2S PLL Bypass Clock. */ + __IOM uint32_t I2S_PLL_BYPCLK_CLKCLNR_OFF : 1; /*!< [13..13] Clock cleaner + OFF Control for I2S PLL + Bypass Clock. */ + __IOM uint32_t MODEM_PLL_BYPCLK_CLKCLNR_ON : 1; /*!< [14..14] Clock cleaner ON + Control for Modem PLL Bypass + Clock. */ + __IOM uint32_t MODEM_PLL_BYPCLK_CLKCLNR_OFF : 1; /*!< [15..15] Clock cleaner OFF + Control for Modem PLL Bypass + Clock. */ + __IOM uint32_t BYPASS_SOC_PLL_CLK : 1; /*!< [16..16] Select to choose bypass clock or + PLL clock 1b0 - soc_pll_clk 1b1 - One of + the bypass clocks based on + soc_pll_clk_byp_sel. */ + __IOM uint32_t BYPASS_I2S_PLL_CLK : 1; /*!< [17..17] Select to choose bypass clock or + PLL clock 1b0 - i2s_pll_clk 1b1 - One of + the bypass clocks based on + soc_pll_clk_byp_sel. */ + __IOM uint32_t BYPASS_MODEM_PLL_CLK1 : 1; /*!< [18..18] Select to choose bypass clock + or PLL clock 1b0 - modem_pll_clk1 + 1b1 - One of the bypass + clocks based on modem_pll_clk_byp_sel. + */ + __IOM uint32_t BYPASS_MODEM_PLL_CLK2 : 1; /*!< [19..19] Select to choose bypass clock + or PLL clock 1b0 - modem_pll_clk2 + 1b1 - One of the bypass + clocks based on modem_pll_clk_byp_sel. + */ + __IOM uint32_t BYPASS_INTF_PLL_CLK : 1; /*!< [20..20] Select to choose bypass clock + or PLL clock 1b0 - intf_pll_clk + 1b1 - One of the bypass clocks + based on soc_pll_clk_byp_sel. */ + __IOM uint32_t SLEEP_CLK_SEL : 2; /*!< [22..21] Select to choose sleep clk + 00 - ulp_32khz_rc_clk 01 + - ulp_32khz_xtal_clk 10 - + Gated 11 - ulp_32khz_ro_clk. */ + __IOM uint32_t Reserved2 : 2; /*!< [24..23] It is recommended to write + these bits to 0. */ + __IOM uint32_t ULPSS_CLK_DIV_FAC : 6; /*!< [30..25] Clock division factor for clock + to ULPSS. If ulpss_clk_enable is 1b0 clock + is gated. Else output clock is a divided + clock with the following frequency. 6h0 - + Divider is bypassed > 6h0 - clk_out = + clk_in/ 2* ulpss_clk_div_fac */ + __IOM uint32_t Reserved3 : 1; /*!< [31..31] It is recommended to write + these bits to 0. */ + } CLK_CONFIG_REG4_b; + }; + + union { + __IOM uint32_t CLK_CONFIG_REG5; /*!< (@ 0x00000028) Clock Config Register 5 */ + + struct { + __IOM uint32_t M4_SOC_CLK_SEL : 4; /*!< [3..0] Selects one of the clock sources for + M4 SoC clock. These clocks are selected for + m4_soc_clk when 1)m4_soc_host_clk_sel is 1b0 or + 2)when m4_soc_host_clk_sel is 1b1, xtal is + ON(xtal_off from slp_fsm should be zero) and + host_clk_available(from host logic) is 1b0. + 0000 - ULP Ref Clock (generated inside M4SS + based on m4ss_ref_clk_sel from NPSS) 0001 - + Reserved 0010 - */ + __IOM uint32_t M4_SOC_CLK_DIV_FAC : 6; /*!< [9..4] Clock divison factor for TA SoC + Clock If ta_soc_clk_enable(from NPSS) is + 1b0 clock is gated. Else output clock is a + swallowed clock with the following + frequency. 6h0,6h1 - Divider is bypassed + >6h1 - clk_out = clk_in/ ta_soc_clk_div_fac + */ + __IOM uint32_t I2S_CLK_SEL : 1; /*!< [10..10] Selects one of the following clocks for + config timer I2S interface 00/11 - I2S PLL Clock + (program bypass_i2s_pll_clk if the bypass clock + has to be selected) 01 - I2S PLL Clock_1 (program + bypass_i2s_pll_clk_1 if the bypass clock has to + be selected) 10 - + m4_soc_clk_for_other_clocks */ + __IOM uint32_t I2S_CLK_DIV_FAC : 6; /*!< [16..11] Clock division factor for i2s_clk. + Else output clock is a 50% divided clock with + the following frequency. 6h0 + - Divider is bypassed >6h0 - clk_out = + clk_in/ 2*i2s_clk_div_fac */ + __IOM uint32_t CT_CLK_SEL : 3; /*!< [19..17] Selects one of the following clocks for + config timer 000 - ulp ref Clock(generated inside + M4SS based on m4ss_ref_clk_sel from NPSS) 001 - + Intf PLL Clock(program bypass_intf_pll_clk if the + bypass clock has to be selected) 010 - SoC PLL + Clock(program bypass_soc_pll_clk if the bypass + clock has to be selected) 011 - + m4_soc_clk_for_other_clocks 100,110 - Invalid */ + __IOM uint32_t CT_CLK_DIV_FAC : 6; /*!< [25..20] Clock division factor for sct_clk. + If sct_clk_enable is 1b0 clock is gated. Else + output clock is a 50% divided clock with the + following frequency. 6h0 - Divider is bypassed + >6h0 - clk_out = clk_in/ + 2*sct_clk_div_fac */ + __IOM uint32_t M4_SOC_HOST_CLK_SEL : 1; /*!< [26..26] Selects the previous muxed + output(xtal_clk) or host_clk as the clock + source for M4 SoC clock based on the + following combinations of {xtal_off(from + slp fsm), host_clk_available(from host + logic),m4_soc_host_clk_sel} XX0 - xtal_clk + 001 - After wait time based on + mask_host_clk_wait_fix ; xtal_clk X11 + - host_clk 101 - No Clock */ + __IOM uint32_t Reserved1 : 1; /*!< [27..27] It is recommended to write + these bits to 0. */ + __IOM uint32_t ULPSS_ODD_DIV_SEL : 1; /*!< [28..28] Selects the type of divider for + m4_soc_clk_2ulpss 1b0 + - Clock Divider(even) is selected 1b1 + - Odd Divider is selected. */ + __IOM uint32_t Reserved2 : 2; /*!< [30..29] It is recommended to write + these bits to 0. */ + __IOM uint32_t I2S_CLK_SEL_1 : 1; /*!< [31..31] Selects one of the following clocks + for config timer for I2S interface 00/11 - I2S + PLL Clock (program bypass_i2s_pll_clk if the + bypass clock has to be selected) 01 - I2S PLL + Clock_1 (program bypass_i2s_pll_clk_1 if the + bypass clock has to be selected) 10 - + m4_soc_clk_for_other_clocks */ + } CLK_CONFIG_REG5_b; + }; + __IM uint32_t RESERVED[6]; + + union { + __IOM uint32_t DYN_CLK_GATE_DISABLE_REG; /*!< (@ 0x00000044) Dynamic Clock + Gate Disable Register */ + + struct { + __IOM uint32_t SDIO_SYS_HCLK_DYN_CTRL_DISABLE_b : 1; /*!< [0..0] Dynamic clock gate + disable control sdio sys + clk1'b0 => Dynamic control of + the clock is disbaled 1'b1 => + Dynamic + control of the clock is + enabled */ + __IOM uint32_t BUS_CLK_DYN_CTRL_DISABLE_b : 1; /*!< [1..1] Dynamic clock gate disable + control bus clk1'b0 => Dynamic + control of the clock is + disbaled 1'b1 => Dynamic control + of the clock is enabled + */ + __IOM uint32_t Reserved1 : 2; /*!< [3..2] It is recommended to write these + bits to 0. */ + __IOM uint32_t GPDMA_HCLK_DYN_CTRL_DISABLE_b : 1; /*!< [4..4] Dynamic clock gate + disable control gpdma clk1'b0 => + Dynamic control of the clock is + disbaled 1'b1 => Dynamic control + of the clock is enabled + */ + __IOM uint32_t EGPIO_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [5..5] Dynamic clock gate + disable control egpio clk1'b0 => + Dynamic control of the clock is + disbaled 1'b1 => Dynamic control + of the clock is enabled + */ + __IOM uint32_t SGPIO_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [6..6] Dynamic clock gate + disable control sgpio clk1'b0 => + Dynamic control of the clock is + disbaled 1'b1 => Dynamic control + of the clock is enabled + */ + __IOM uint32_t TOT_CLK_DYN_CTRL_DISABLE_b : 1; /*!< [7..7] Dynamic clock gate disable + control tot clk1'b0 => Dynamic + control of the clock is + disbaled 1'b1 => Dynamic control + of the clock is enabled + */ + __IOM uint32_t Reserved2 : 1; /*!< [8..8] It is recommended to write these + bits to 0. */ + __IOM uint32_t USART1_SCLK_DYN_CTRL_DISABLE_b : 1; /*!< [9..9] Dynamic clock gate + disable control usart1 sclk1'b0 + => Dynamic control of the clock + is disbaled 1'b1 => Dynamic + control of the clock is + enabled. */ + __IOM uint32_t USART1_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [10..10] Dynamic clock gate + disable control usart1 pclk1'b0 + => Dynamic control of the + clock is disbaled 1'b1 => + Dynamic + control of the clock is + enabled. */ + __IOM uint32_t USART2_SCLK_DYN_CTRL_DISABLE_b : 1; /*!< [11..11] Dynamic clock gate + disable control usart2 sclk1'b0 + => Dynamic control of the + clock is disbaled 1'b1 => + Dynamic + control of the clock is + enabled. */ + __IOM uint32_t USART2_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [12..12] Dynamic clock gate + disable control usart2 pclk1'b0 + => Dynamic control of the + clock is disbaled 1'b1 => + Dynamic + control of the clock is + enabled. */ + __IOM uint32_t Reserved3 : 2; /*!< [14..13] It is recommended to write + these bits to 0. */ + __IOM uint32_t SSI_SLV_SCLK_DYN_CTRL_DISABLE_b : 1; /*!< [15..15] Dynamic clock gate + disable control ssi slave + sclk1'b0 + => Dynamic control of the + clock is disbaled 1'b1 => + Dynamic control of the clock + is enabled */ + __IOM uint32_t SSI_SLV_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [16..16] Dynamic clock gate + disable control ssi slave + pclk1'b0 + => Dynamic control of the + clock is disbaled 1'b1 => + Dynamic control of the clock + is enabled */ + __IOM uint32_t Reserved4 : 2; /*!< [18..17] It is recommended to write + these bits to 0. */ + __IOM uint32_t SEMAPHORE_CLK_DYN_CTRL_DISABLE_b : 1; /*!< [19..19] Dynamic clock gate + disable control semaphore + clk1'b0 + => Dynamic control of the + clock is disbaled 1'b1 => + Dynamic + control of the clock is + enabled. */ + __IOM uint32_t ARM_CLK_DYN_CTRL_DISABLE_b : 1; /*!< [20..20] Dynamic clock gate + disable control arm clk1'b0 => + Dynamic control of the clock is + disbaled 1'b1 => Dynamic control + of the clock is enabled. + */ + __IOM uint32_t SSI_MST_SCLK_DYN_CTRL_DISABLE_b : 1; /*!< [21..21] Dynamic clock gate + disable control ssi mst + sclk1'b0 + => Dynamic control of the + clock is disbaled 1'b1 => + Dynamic control of the clock + is enabled. */ + __IOM uint32_t Reserved5 : 2; /*!< [23..22] It is recommended to write + these bits to 0. */ + __IOM uint32_t MEM_CLK_ULP_DYN_CTRL_DISABLE_b : 1; /*!< [24..24] Dynamic clock gate + disable control mem clk1'b0 => + Dynamic control of the clock is + disbaled 1'b1 => Dynamic + control of the clock is + enabled. */ + __IOM uint32_t Reserved6 : 3; /*!< [27..25] It is recommended to write + these bits to 0. */ + __IOM uint32_t SSI_MST_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [28..28] Dynamic clock gate + disable control ssi mst pclk + 1'b0 + => Dynamic control of the + clock is disbaled 1'b1 => + Dynamic control of the clock + is enabled */ + __IOM uint32_t ICACHE_DYN_GATING_DISABLE_b : 1; /*!< [29..29] Dynamic clock gate + disable control icache clk1'b0 => + Dynamic control of the + clock is disbaled 1'b1 => Dynamic + control of the clock is + enabled */ + __IOM uint32_t Reserved7 : 1; /*!< [30..30] It is recommended to write + these bits to 0. */ + __IOM uint32_t MISC_CONFIG_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [31..31] Dynamic clock + gate disable control miscn + config pclk 1'b0 => + Dynamic control of the + clock is disbaled 1'b1 => + Dynamic control of the + clock is enabled. */ + } DYN_CLK_GATE_DISABLE_REG_b; + }; + __IM uint32_t RESERVED1[2]; + + union { + __IOM uint32_t PLL_ENABLE_SET_REG; /*!< (@ 0x00000050) PLL Enable Set Register */ + + struct { + __IOM uint32_t SOCPLL_SPI_SW_RESET : 1; /*!< [0..0] SPI soft reset for SoC PLL1'b1 => + soft reset is enabled1'b0 + => Invalid */ + __IOM uint32_t Reserved1 : 31; /*!< [31..1] It is recommended to write + these bits to 0. */ + } PLL_ENABLE_SET_REG_b; + }; + + union { + __IOM uint32_t PLL_ENABLE_CLEAR_REG; /*!< (@ 0x00000054) PLL Enable Clear Register */ + + struct { + __IOM uint32_t SOCPLL_SPI_SW_RESET : 1; /*!< [0..0] SPI soft reset for SoC PLL1'b1 => + soft reset is disabled1'b0 + => Invalid */ + __IOM uint32_t Reserved1 : 31; /*!< [31..1] It is recommended to write + these bits to 0. */ + } PLL_ENABLE_CLEAR_REG_b; + }; + + union { + __IM uint32_t PLL_STAT_REG; /*!< (@ 0x00000058) PLL Status Register */ + + struct { + __IM uint32_t LCDPLL_LOCK : 1; /*!< [0..0] Lock Signal from LCD PLL */ + __IM uint32_t DDRPLL_LOCK : 1; /*!< [1..1] Lock Signal from DDR PLL */ + __IM uint32_t APPLL_LOCK : 1; /*!< [2..2] Lock Signal from AP PLL */ + __IM uint32_t INTFPLL_LOCK : 1; /*!< [3..3] Lock Signal from INTF PLL */ + __IM uint32_t I2SPLL_LOCK : 1; /*!< [4..4] Lock Signal from I2S PLL */ + __IM uint32_t SOCPLL_LOCK : 1; /*!< [5..5] Lock Signal from SoC PLL */ + __IM uint32_t MODEMPLL_LOCK : 1; /*!< [6..6] Lock Signal from Modem PLL */ + __IM uint32_t PLL_LOCK_DATA_TRIG : 1; /*!< [7..7] This is set to 1'b1 when the PLL + Locks are equal to pll_lock_int_data_r + g */ + __IM uint32_t M4_SOC_CLK_SWITCHED : 1; /*!< [8..8] Indication from M4 SoC + Clock Dynamic mux that the + switching happened */ + __IM uint32_t QSPI_CLK_SWITCHED : 1; /*!< [9..9] Indication from QSPI Clock Dynamic + mux that the switching happened */ + __IM uint32_t USART1_SCLK_SWITCHED : 1; /*!< [10..10] Indication from + USART1 Clock Dynamic mux that + the switching happened */ + __IM uint32_t USART2_SCLK_SWITCHED : 1; /*!< [11..11] Indication from + USART1 Clock Dynamic mux that + the switching happened */ + __IM uint32_t GEN_SPI_MST1_SCLK_SWITCHED : 1; /*!< [12..12] Indication from USART2 + Clock Dynamic mux that the + switching happened */ + __IM uint32_t SSI_MST_SCLK_SWITCHED : 1; /*!< [13..13] Indication from SSi + Master SClock Dynamic mux that + the switching happened */ + __IM uint32_t Reserved1 : 1; /*!< [14..14] It is recommended to write + these bits to 0. */ + __IM uint32_t CT_CLK_SWITCHED : 1; /*!< [15..15] Indication from SCT Clock Dynamic + mux that the switching happened */ + __IM uint32_t M4_TA_SOC_CLK_SWITCHED_SDIO : 1; /*!< [16..16] Indication + from M4-TA Soc SDIO + Clock Dynamic mux that + the switching + happened(TBD) */ + __IM uint32_t I2S_CLK_SWITCHED : 1; /*!< [17..17] Indication from I2S Clock Dynamic + mux that the switching happened */ + __IM uint32_t PLL_INTF_CLK_SWITCHED : 1; /*!< [18..18] Indication from Pll + Intf Clock Dynamic mux that + the switching happened */ + __IM uint32_t Reserved2 : 2; /*!< [20..19] It is recommended to write + these bits to 0. */ + __IM uint32_t SLEEP_CLK_SWITCHED : 1; /*!< [21..21] Indication from Sleep + clcok Dynamic mux that the + switching happened */ + __IM uint32_t MCU_CLKOUT_SWITCHED : 1; /*!< [22..22] Indication from + mcu_clkout Dynamic mux that the + switching happened */ + __IM uint32_t QSPI_2_CLK_SWITCHED : 1; /*!< [23..23] Indication from QSPI + Clock Dynamic mux that the + switching happened */ + __IM uint32_t TASS_M4SS_64K_CLK_SWITCHED : 1; /*!< [24..24] Indication when TA + accessing 2nd memory chunk of M4, + clock to Dynamic mux switching + happened */ + __IM uint32_t CC_CLOCK_MUX_SWITCHED : 1; /*!< [25..25] Indication from cc + clock Dynamic mux that the + switching happened */ + __IM uint32_t TASS_M4SS_192K_CLK_SWITCHED : 1; /*!< [26..26] Indication when TA + accessing 0th memory chunk of M4, + clock to Dynamic mux switching + happened */ + __IM uint32_t USART1_CLK_SWITCHED : 1; /*!< [27..27] Indication from + usart1 sclk or pclk Dynamic mux + that the switching happened */ + __IM uint32_t USART2_CLK_SWITCHED : 1; /*!< [28..28] Indication from + usart2 sclk or pclk Dynamic mux + that the switching happened */ + __IM uint32_t TASS_M4SS_64K0_CLK_SWITCHED : 1; /*!< [29..29] Indication when TA + accessing 1st memory chunk of M4, + clock to Dynamic mux switching + happened */ + __IM uint32_t CLK_FREE_OR_SLP_SWITCHED : 1; /*!< [30..30] Indication from + clk_free_or_slp Dynamic mux that the + switching happened */ + __IM uint32_t ULP_REF_CLK_SWITCHED : 1; /*!< [31..31] Indication from + ulp_ref_clk Dynamic mux that + the switching happened */ + } PLL_STAT_REG_b; + }; + + union { + __IOM uint32_t PLL_LOCK_INT_MASK_REG; /*!< (@ 0x0000005C) PLL Lock Interrupt + Mask Register */ + + struct { + __IOM uint32_t LCD_PLL_LOCK_MASK_BIT_OF_RISING_EDGE : 1; /*!< [0..0] 1'b1 => + Masked;1'b0 => Not Masked + */ + __IOM uint32_t DDR_PLL_LOCK_MASK_BIT_OF_RISING_EDGE : 1; /*!< [1..1] 1'b1 => + Masked;1'b0 => Not Masked + */ + __IOM uint32_t AP_PLL_LOCK_MASK_BIT_OF_RISING_EDGE : 1; /*!< [2..2] 1'b1 => + Masked;1'b0 => Not Masked + */ + __IOM uint32_t INTF_PLL_LOCK_MASK_BIT_OF_RISING_EDGE : 1; /*!< [3..3] 1'b1 => + Masked;1'b0 => Not + Masked */ + __IOM uint32_t I2S_PLL_LOCK_MASK_BIT_OF_RISING_EDGE : 1; /*!< [4..4] 1'b1 => + Masked;1'b0 => Not Masked + */ + __IOM uint32_t SOC_PLL_LOCK_MASK_BIT_OF_RISING_EDGE : 1; /*!< [5..5] 1'b1 => + Masked;1'b0 => Not Masked + */ + __IOM uint32_t MODEM_PLL_LOCK_MASK_BIT_OF_RISING_EDGE : 1; /*!< [6..6] 1'b1 => + Masked;1'b0 => Not + Masked */ + __IOM uint32_t PLL_LOCK_DATA_TRIGGER_MASK_BIT_OF_RISING_EDGE : 1; /*!< [7..7] 1'b1 => + Masked;1'b0 => + Not Masked */ + __IOM uint32_t LCD_PLL_LOCK_MASK_BIT_OF_FALLING_EDGE : 1; /*!< [8..8] 1'b1 => + Masked;1'b0 => Not + Masked */ + __IOM uint32_t DDR_PLL_LOCK_MASK_BIT_OF_FALLING_EDGE : 1; /*!< [9..9] 1'b1 => + Masked;1'b0 => Not + Masked */ + __IOM uint32_t AP_PLL_LOCK_MASK_BIT_OF_FALLING_EDGE : 1; /*!< [10..10] 1'b1 => + Masked;1'b0 => Not Masked + */ + __IOM uint32_t INTF_PLL_LOCK_MASK_BIT_OF_FALLING_EDGE : 1; /*!< [11..11] 1'b1 => + Masked;1'b0 => Not + Masked */ + __IOM uint32_t I2S_PLL_LOCK_MASK_BIT_OF_FALLING_EDGE : 1; /*!< [12..12] 1'b1 => + Masked;1'b0 => Not + Masked */ + __IOM uint32_t SOC_PLL_LOCK_MASK_BIT_OF_FALLING_EDGE : 1; /*!< [13..13] 1'b1 => + Masked;1'b0 => Not + Masked */ + __IOM uint32_t MODEM_PLL_LOCK_MASK_BIT_OF_FALLING_EDGE : 1; /*!< [14..14] 1'b1 => + Masked;1'b0 => Not + Masked */ + __IOM uint32_t PLL_LOCK_DATA_TRIGGER_MASK_BIT_OF_FALLING_EDGE : 1; /*!< [15..15] 1'b1 + => Masked;1'b0 + => Not Masked + */ + __IOM uint32_t Reserved1 : 16; /*!< [31..16] It is recommended to write + these bits to 0. */ + } PLL_LOCK_INT_MASK_REG_b; + }; + + union { + __IOM uint32_t PLL_LOCK_INT_CLR_REG; /*!< (@ 0x00000060) PLL Lock Interrupt + Clear Register */ + + struct { + __IOM uint32_t LCD_PLL_LOCK_CLEAR_BIT_OF_RISING_EDGE : 1; /*!< [0..0] 1'b0 => Not + Cleared 1'b1 => Cleared + */ + __IOM uint32_t DDR_PLL_LOCK_CLEAR_BIT_OF_RISING_EDGE : 1; /*!< [1..1] 1'b0 => Not + Cleared 1'b1 => Cleared + */ + __IOM uint32_t AP_PLL_LOCK_CLEAR_BIT_OF_RISING_EDGE : 1; /*!< [2..2] 1'b0 => Not + Cleared 1'b1 => Cleared + */ + __IOM uint32_t INTF_PLL_LOCK_CLEAR_BIT_OF_RISING_EDGE : 1; /*!< [3..3] 1'b0 => Not + Cleared 1'b1 => Cleared + */ + __IOM uint32_t I2S_PLL_LOCK_CLEAR_BIT_OF_RISING_EDGE : 1; /*!< [4..4] 1'b0 => Not + Cleared 1'b1 => Cleared + */ + __IOM uint32_t SOC_PLL_LOCK_CLEAR_BIT_OF_RISING_EDGE : 1; /*!< [5..5] 1'b0 => Not + Cleared 1'b1 => Cleared + */ + __IOM uint32_t MODEM_PLL_LOCK_CLEAR_BIT_OF_RISING_EDGE : 1; /*!< [6..6] 1'b0 => Not + Cleared 1'b1 => + Cleared */ + __IOM uint32_t PLL_LOCK_DATA_TRIGGER_CLEAR_BIT_OF_RISING_EDGE : 1; /*!< [7..7] 1'b0 + => Not Cleared + 1'b1 => Cleared + */ + __IOM uint32_t LCD_PLL_LOCK_CLEAR_BIT_OF_FALLING_EDGE : 1; /*!< [8..8] 1'b0 => Not + Cleared 1'b1 => Cleared + */ + __IOM uint32_t DDR_PLL_LOCK_CLEAR_BIT_OF_FALLING_EDGE : 1; /*!< [9..9] 1'b0 => Not + Cleared 1'b1 => Cleared + */ + __IOM uint32_t AP_PLL_LOCK_CLEAR_BIT_OF_FALLING_EDGE : 1; /*!< [10..10] 1'b0 => Not + Cleared 1'b1 => Cleared + */ + __IOM uint32_t INTF_PLL_LOCK_CLEAR_BIT_OF_FALLING_EDGE : 1; /*!< [11..11] 1'b0 => Not + Cleared 1'b1 => + Cleared */ + __IOM uint32_t I2S_PLL_LOCK_CLEAR_BIT_OF_FALLING_EDGE : 1; /*!< [12..12] 1'b0 => Not + Cleared 1'b1 => Cleared + */ + __IOM uint32_t SOC_PLL_LOCK_CLEAR_BIT_OF_FALLING_EDGE : 1; /*!< [13..13] 1'b0 => Not + Cleared 1'b1 => Cleared + */ + __IOM uint32_t MODEM_PLL_LOCK_CLEAR_BIT_OF_FALLING_EDGE : 1; /*!< [14..14] 1'b0 => + Not Cleared 1'b1 => + Cleared */ + __IOM uint32_t PLL_LOCK_DATA_TRIGGER_CLEAR_BIT_OF_FALLING_EDGE : 1; /*!< + [15..15] + 1'b0 + => + Not + Cleared + 1'b1 + => + Cleared + */ + __IOM uint32_t Reserved1 : 16; /*!< [31..16] It is recommended to write + these bits to 0. */ + } PLL_LOCK_INT_CLR_REG_b; + }; + + union { + __IOM uint32_t PLL_LOCK_INT_DATA_REG; /*!< (@ 0x00000064) PLL Lock Interrupt + DATA Register */ + + struct { + __IOM uint32_t LCD_PLL_LOCK : 1; /*!< [0..0] 1'b1 => LCD PLL Lock has to be used as + trigger1'b0 => LCD PLL Lock not to be used as + trigger */ + __IOM uint32_t DDR_PLL_LOCK : 1; /*!< [1..1] 1'b1 => DDR PLL Lock has to be used as + trigger1'b0 => DDR PLL Lock not to be used as + trigger */ + __IOM uint32_t AP_PLL_LOCK : 1; /*!< [2..2] 1'b1 => AP PLL Lock has to be used as + trigger1'b0 => Ap PLL Lock not to be used as + trigger */ + __IOM uint32_t INTF_PLL_LOCK : 1; /*!< [3..3] 1'b1 => INTF PLL Lock has to + be used as trigger1'b0 => INTF PLL + Lock not to be used as trigger */ + __IOM uint32_t I2S_PLL_LOCK : 1; /*!< [4..4] 1'b1 => I2S PLL Lock has to be used as + trigger1'b0 => I2S PLL Lock not to be used as + trigger */ + __IOM uint32_t SOC_PLL_LOCK : 1; /*!< [5..5] 1'b1 => SoC PLL Lock has to be used as + trigger1'b0 => SoC PLL Lock not to be used as + trigger */ + __IOM uint32_t MODEM_PLL_LOCK : 1; /*!< [6..6] 1'b1 => Modem PLL Lock has + to be used as trigger1'b0 + => Modem PLL Lock not to be + used as trigger */ + __IOM uint32_t Reserved1 : 25; /*!< [31..7] It is recommended to write + these bits to 0. */ + } PLL_LOCK_INT_DATA_REG_b; + }; + + union { + __IOM uint32_t SLEEP_CALIB_REG; /*!< (@ 0x00000068) Sleep Calib Register */ + + struct { + __IOM uint32_t SLP_CALIB_START_b : 1; /*!< [0..0] This bit is used to start the + calibration. 1b1 - Start calibration. + slp_calib_duration should be loaded before + this bit is set. This bit is + self-clearing. When read, + if high indicates the completion of + calibration process. */ + __IOM uint32_t SLP_CALIB_CYCLES : 2; /*!< [2..1] These bits are used to program the + number of clock cycles over which clock + calibration is to be done. */ + __IOM uint32_t SLP_CALIB_DURATION_b : 16; /*!< [18..3] Duration of the sleep clock in + terms of processor clocks. This has to + be divided with number of calibration + cycles to get number of clock + cycles(reference clock) in single clock + period). 1b1 - AP PLL Lock has to be + used as trigger1b0 + - Ap PLL Lock not to be used as + trigger */ + __IOM uint32_t SLP_CALIB_DONE_b : 1; /*!< [19..19] Indicates the end of + calibration */ + __IOM uint32_t Reserved1 : 12; /*!< [31..20] It is recommended to write + these bits to 0. */ + } SLEEP_CALIB_REG_b; + }; + + union { + __IOM uint32_t CLK_CALIB_CTRL_REG1; /*!< (@ 0x0000006C) Clock Calib Control + Register1 */ + + struct { + __IOM uint32_t CC_SOFT_RST_b : 1; /*!< [0..0] Soft Reset for clock + calibrator 1b1 - reset enabled 1b0 + - reset disabled. */ + __IOM uint32_t CC_START_b : 1; /*!< [1..1] start clk calibration 1b1 - start */ + __IOM uint32_t CC_CHANGE_TEST_CLK_b : 1; /*!< [2..2] change test clk. Set + this bit to 1'b1 only when + test_clk is being changed, + else this should be 1'b0. */ + __IOM uint32_t CC_CLKIN_SEL_b : 4; /*!< [6..3] select the clock to be calibrated 4d0 + - ulp_ref_clk 4d1 + - mems_ref_clk 4d2 - ulp_20mhz_ringosc_clk + 4d3 - modem_pll_clk1 4d4 - modem_pll_clk2 4d5 - + intf_pll_clk 4d6 - soc_pll_clk 4d7 - + i2s_pll_clk 4d8 - sleep_clk 4d9 - bus_clkby2_ap + */ + __IOM uint32_t Reserved1 : 25; /*!< [31..7] It is recommended to write + these bits to 0. */ + } CLK_CALIB_CTRL_REG1_b; + }; + + union { + __IOM uint32_t CLK_CALIB_CTRL_REG2; /*!< (@ 0x00000070) Clock Calib Control + Register2 */ + + struct { + __IOM uint32_t CC_NUM_REF_CLKS : 32; /*!< [31..0] number of ref_clk cycles to be + considered for calibrating. */ + } CLK_CALIB_CTRL_REG2_b; + }; + + union { + __IOM uint32_t CLK_CALIB_STS_REG1; /*!< (@ 0x00000074) Clock Calib Status + Register1 */ + + struct { + __IOM uint32_t CC_DONE_b : 1; /*!< [0..0] indicates clock calibratioon + done1'b1 => done1'b0 => none */ + __IOM uint32_t CC_ERROR_b : 1; /*!< [1..1] indicates clock calibration + error1'b1 => error1'b0 => none */ + __IOM uint32_t Reserved1 : 30; /*!< [31..2] It is recommended to write + these bits to 0. */ + } CLK_CALIB_STS_REG1_b; + }; + + union { + __IOM uint32_t CLK_CALIB_STS_REG2; /*!< (@ 0x00000078) Clock Calib Status + Register2 */ + + struct { + __IOM uint32_t CC_NUM_TEST_CLKS : 32; /*!< [31..0] number of test clk cycles occurred + for the specified number of ref_clk cycles + */ + } CLK_CALIB_STS_REG2_b; + }; + + union { + __IOM uint32_t CLK_CONFIG_REG6; /*!< (@ 0x0000007C) Clock Config Register6 */ + + struct { + __IOM uint32_t IID_KH_CLK_DIV_FAC : 3; /*!< [2..0] Clock division factor + for iid_clk. */ + __IOM uint32_t Reserved1 : 2; /*!< [4..3] It is recommended to write these + bits to 0. */ + __IOM uint32_t PADCFG_PCLK_DIV_FAC : 4; /*!< [8..5] Clock division factor + for pclk_pad_config_m4ss */ + __IOM uint32_t QSPI_2_CLK_SEL : 3; /*!< [11..9] Selects one of the following clocks + for ssi master 000 + - ULP Ref Clock(generated inside M4SS based on + m4ss_ref_clk_sel from NPSS) 001 - Intf PLL + Clock Clock (program bypass_intf_pll_clk if the + bypass clock has to be selected) 010 - Modem + PLL Clock2(Not Intended for the programmer) + (program bypass_modem_pll_clk if the bypass + clock has to be selected) 011 - SoC PLL Clock + */ + __IOM uint32_t QSPI_2_CLK_DIV_FAC : 6; /*!< [17..12] Clock divison factor for QSPI. + If qspi_clk_enable is 1b0 clock is gated. + Else 1)when qspi_clk_swallow_sel is 1b1 and + qspi_odd_div_sel is 1b0 output clock is a + swallowed clock with the following + frequency. 6h0,6h1 => clk_out = clk_in >6h1 + => clk_out = clk_in/ qspi_clk_div_fac + 2)when qspi_clk_swallow_sel is 1b0 */ + __IOM uint32_t QSPI_2_CLK_SWALLOW_SEL : 1; /*!< [18..18] Clock select for clock + swallow or clock divider for QSPI 1b0 + => 50% divider is selected with + division factor qspi_clk_div_fac 1b1 => + Swallowed clock is selected with + division factor qspi_clk_div_fac Before + Changing this ensure that the input + clocks are gated */ + __IOM uint32_t QSPI_2_ODD_DIV_SEL : 1; /*!< [19..19] Clock select for clock swallow + or 50% even clock divider or 50% odd + divider clock for QSPI 1b1 - 50% odd clock + divider output is selected with division + factor qspi_clk_div_fac 1b0 - 50% even + clock divider output or swallowed is + selected with division factor + qspi_clk_div_fac based on + qspi_clk_swallow_sel. */ + __IOM uint32_t Reserved2 : 12; /*!< [31..20] It is recommended to write + these bits to 0. */ + } CLK_CONFIG_REG6_b; + }; + + union { + __IOM uint32_t DYN_CLK_GATE_DISABLE_REG2; /*!< (@ 0x00000080) Dynamic Clock + Gate Disable Register2 */ + + struct { + __IOM uint32_t SOC_PLL_SPI_CLK_DYN_CTRL_DISABLE_b : 1; /*!< [0..0] Dynamic clock gate + disable control soc pll spi + clk 1b1 + - Dynamic control of the + clock is disbaled 1b0 - + Dynamic control of the + clock is enabled */ + __IOM uint32_t Reserved1 : 2; /*!< [2..1] It is recommended to write these + bits to 0. */ + __IOM uint32_t CT_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [3..3] Dynamic clock gate disable + control SCT pclk 1b1 - Dynamic + control of the clock is + disbaled 1b0 - Dynamic control + of the clock is enabled + */ + __IOM uint32_t Reserved2 : 2; /*!< [5..4] It is recommended to write these + bits to 0. */ + __IOM uint32_t EFUSE_CLK_DYN_CTRL_DISABLE_b : 1; /*!< [6..6] Dynamic clock gate + disable control efuse clk 1b1 - + Dynamic control of the clock is + disbaled 1b0 - Dynamic control + of the clock is enabled + */ + __IOM uint32_t EFUSE_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [7..7] Dynamic clock gate + disable control efuse pclk 1b1 + - Dynamic control of the clock + is disbaled 1b0 - Dynamic + control of the clock is + enabled */ + __IOM uint32_t Reserved3 : 24; /*!< [31..8] It is recommended to write + these bits to 0. */ + } DYN_CLK_GATE_DISABLE_REG2_b; + }; + + union { + __IOM uint32_t PLL_LOCK_INT_STATUS_REG; /*!< (@ 0x00000084) PLL Lock + Interrupt Status Register */ + + struct { + __IOM uint32_t LCD_PLL_LOCK_OF_RISING_EDGE : 1; /*!< [0..0] 1b0 - No Interrupt; 1b1 - + Interrupt encountered. */ + __IOM uint32_t DDR_PLL_LOCK_OF_RISING_EDGE : 1; /*!< [1..1] 1'b0 => No Interrupt;1'b1 + => Interrupt encountered. */ + __IOM uint32_t AP_PLL_LOCK_OF_RISING_EDGE : 1; /*!< [2..2] 1'b0 => No Interrupt;1'b1 + => Interrupt encountered. */ + __IOM uint32_t INTF_PLL_LOCK_OF_RISING_EDGE : 1; /*!< [3..3] 1'b0 => No + Interrupt;1'b1 => Interrupt + encountered. */ + __IOM uint32_t I2S_PLL_LOCK_OF_RISING_EDGE : 1; /*!< [4..4] 1'b0 => No Interrupt;1'b1 + => Interrupt encountered. */ + __IOM uint32_t SOC_PLL_LOCK_OF_RISING_EDGE : 1; /*!< [5..5] 1'b0 => No Interrupt;1'b1 + => Interrupt encountered. */ + __IOM uint32_t MODEM_PLL_LOCK_OF_RISING_EDGE : 1; /*!< [6..6] 1'b0 => No + Interrupt;1'b1 => Interrupt + encountered. */ + __IOM uint32_t PLL_LOCK_DATA_TRIGGER_INTR_OF_RISING_EDGE : 1; /*!< [7..7] 1'b0 => No + Interrupt;1'b1 => + Interrupt + encountered. */ + __IOM uint32_t LCD_PLL_LOCK_OF_FALLING_EDGE : 1; /*!< [8..8] 1'b0 => No + Interrupt;1'b1 => Interrupt + encountered. */ + __IOM uint32_t DDR_PLL_LOCK_OF_FALLING_EDGE : 1; /*!< [9..9] 1'b0 => No + Interrupt;1'b1 => Interrupt + encountered. */ + __IOM uint32_t AP_PLL_LOCK_OF_FALLING_EDGE : 1; /*!< [10..10] 1'b0 => No + Interrupt;1'b1 => Interrupt + encountered. */ + __IOM uint32_t INTF_PLL_LOCK_OF_FALLING_EDGE : 1; /*!< [11..11] 1'b0 => No + Interrupt;1'b1 => Interrupt + encountered. */ + __IOM uint32_t I2S_PLL_LOCK_OF_FALLING_EDGE : 1; /*!< [12..12] 1'b0 => No + Interrupt;1'b1 => Interrupt + encountered. */ + __IOM uint32_t SOC_PLL_LOCK_OF_FALLING_EDGE : 1; /*!< [13..13] 1'b0 => No + Interrupt;1'b1 => Interrupt + encountered. */ + __IOM uint32_t MODEM_PLL_LOCK_OF_FALLING_EDGE : 1; /*!< [14..14] 1'b0 => No + Interrupt;1'b1 => Interrupt + encountered. */ + __IOM uint32_t PLL_LOCK_DATA_TRIGGER_INTR_OF_FALLING_EDGE : 1; /*!< [15..15] 1'b0 => + No Interrupt;1'b1 + => Interrupt + encountered. */ + __IOM uint32_t Reserved1 : 16; /*!< [31..16] It is recommended to write + these bits to 0. */ + } PLL_LOCK_INT_STATUS_REG_b; + }; +} M4CLK_Type; /*!< Size = 136 (0x88) */ + +/* =========================================================================================================================== + */ +/* ================ TIME_PERIOD + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief In this the time periods of 32KHz RC clock, 32KHz RO clock and 32KHz + * XTAL clock can be calibrated (TIME_PERIOD) + */ + +typedef struct { /*!< (@ 0x24048200) TIME_PERIOD Structure */ + + union { + __IOM uint32_t MCU_CAL_RO_TIMEPERIOD_READ; /*!< (@ 0x00000000) RO timeperiod + read register */ + + struct { + __IM uint32_t TIMEPERIOD_RO : 25; /*!< [24..0] Calibrated RO timeperiod */ + __IM uint32_t RESERVED1 : 7; /*!< [31..25] reser */ + } MCU_CAL_RO_TIMEPERIOD_READ_b; + }; + + union { + __IOM uint32_t MCU_CAL_TIMER_CLOCK_PERIOD; /*!< (@ 0x00000004) MCU calender timer clock + period register */ + + struct { + __IOM uint32_t RTC_TIMER_CLK_PERIOD : 25; /*!< [24..0] RTC timer clock + period programmed by SOC */ + __IM uint32_t RESERVED1 : 6; /*!< [30..25] reser */ + __IM uint32_t SPI_RTC_TIMER_CLK_PERIOD_APPLIED_b : 1; /*!< [31..31] Indicated SOC + programmed rtc_timer clock + period is applied at KHz + clock domain */ + } MCU_CAL_TIMER_CLOCK_PERIOD_b; + }; + + union { + __IOM uint32_t MCU_CAL_TEMP_PROG_REG; /*!< (@ 0x00000008) temprature program + register */ + + struct { + __IOM uint32_t BYPASS_CALIB_PG : 1; /*!< [0..0] To bypass power gating and + keep all the blocks always on */ + __IM uint32_t RESERVED1 : 15; /*!< [15..1] reser */ + __IOM uint32_t MAX_TEMP_CHANGE : 5; /*!< [20..16] maximum temperature change after + which rc calibration must be trigger */ + __IOM uint32_t TEMP_TRIGGER_TIME_SEL : 2; /*!< [22..21] temperature + trigger time select */ + __IOM uint32_t PERIODIC_TEMP_CALIB_EN : 1; /*!< [23..23] Enable periodic + checking of temperature */ + __IOM uint32_t RTC_TIMER_PERIOD_MUX_SEL : 1; /*!< [24..24] rtc timer + period mux select */ + __IM uint32_t RESERVED2 : 7; /*!< [31..25] reser */ + } MCU_CAL_TEMP_PROG_REG_b; + }; + + union { + __IOM uint32_t MCU_CAL_START_REG; /*!< (@ 0x0000000C) mcu cal start register */ + + struct { + __IOM uint32_t ALPHA_RO : 3; /*!< [2..0] alpha = 1/2^alpha_ro , averaging factor of + RO timeperiod T = alpha(t_inst) + (1- alpha )t_prev + */ + __IOM uint32_t ALPHA_RC : 3; /*!< [5..3] alpha = 1/2^alpha_rc , averaging factor of + RC timeperiod T = alpha(t_inst) + (1- alpha )t_prev + */ + __IOM uint32_t NO_OF_RO_CLKS : 4; /*!< [9..6] 2^no_of_ro_clks no of clocks + of ro clock counts for no of rc + clocks in that time to measure + timeperiod */ + __IOM uint32_t NO_OF_RC_CLKS : 3; /*!< [12..10] 2^no_of_rc_clocks = no of + rc clocks used in calibration */ + __IOM uint32_t RC_SETTLE_TIME : 3; /*!< [15..13] no of clocks of RO for the RC clk to + settle when enabled */ + __IOM uint32_t RO_TRIGGER_TIME_SEL : 2; /*!< [17..16] ro trigger time select */ + __IOM uint32_t RC_TRIGGER_TIME_SEL : 3; /*!< [20..18] rc trigger time select */ + __IOM uint32_t PERIODIC_RO_CALIB_EN : 1; /*!< [21..21] periodically calibrate RO + timeperiod based ro trigger time sel */ + __IOM uint32_t PERIODIC_RC_CALIB_EN : 1; /*!< [22..22] periodically calibrate RC + timeperiod based rc trigger time sel */ + __OM uint32_t START_CALIB_RO : 1; /*!< [23..23] to initiate RO calibration */ + __OM uint32_t START_CALIB_RC : 1; /*!< [24..24] to initiate RC calibration */ + __IOM uint32_t RC_XTAL_MUX_SEL : 1; /*!< [25..25] xtal mux select */ + __IOM uint32_t LOW_POWER_TRIGGER_SEL : 1; /*!< [26..26] power trigger select */ + __IOM uint32_t VBATT_TRIGGER_TIME_SEL : 3; /*!< [29..27] trigger to ipmu block for + checking vbatt status periodicaly */ + __IM uint32_t RESERVED1 : 2; /*!< [31..30] reser */ + } MCU_CAL_START_REG_b; + }; + + union { + __IOM uint32_t MCU_CAL_REF_CLK_SETTLE_REG; /*!< (@ 0x00000010) reference + clock settle register */ + + struct { + __IOM uint32_t XTAL_SETTLE : 7; /*!< [6..0] no of 32khz clocks for xtal + 40mhz clk to settle */ + __IM uint32_t RESERVED1 : 9; /*!< [15..7] reser */ + __IM uint32_t VALID_RC_TIMEPERIOD : 1; /*!< [16..16] Valid signal for reading RC + timeperiod calibrated */ + __IM uint32_t VALID_RO_TIMEPERIOD : 1; /*!< [17..17] Valid signal for + reading RO timeperiod */ + __IM uint32_t RESERVED2 : 14; /*!< [31..18] reser */ + } MCU_CAL_REF_CLK_SETTLE_REG_b; + }; + + union { + __IOM uint32_t MCU_CAL_RC_TIMEPERIOD_READ; /*!< (@ 0x00000014) rc timeperiod + read register */ + + struct { + __IM uint32_t TIMEPERIOD_RC : 25; /*!< [24..0] Calibrated RC timeperiod */ + __IM uint32_t RESERVED1 : 7; /*!< [31..25] reser */ + } MCU_CAL_RC_TIMEPERIOD_READ_b; + }; + + union { + __IOM uint32_t MCU_CAL_REF_CLK_TIEMPERIOD_REG; /*!< (@ 0x00000018) reference clock + timeperiod register */ + + struct { + __IOM uint32_t TIMEPERIOD_REF_CLK : 24; /*!< [23..0] timeperiod of reference clk with + each bit corresponding to granularity of + 2^27 = 1us */ + __IM uint32_t RESERVED1 : 8; /*!< [31..24] reser */ + } MCU_CAL_REF_CLK_TIEMPERIOD_REG_b; + }; +} TIME_PERIOD_Type; /*!< Size = 28 (0x1c) */ + +/* =========================================================================================================================== + */ +/* ================ MCU_WDT + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief A dedicated window watch dog timer for MCU applications (MCU_WDT) + */ + +typedef struct { /*!< (@ 0x24048300) MCU_WDT Structure */ + + union { + __IOM uint32_t MCU_WWD_INTERRUPT_TIMER; /*!< (@ 0x00000000) WATCHDOG + interrupt timer register */ + + struct { + __IOM uint32_t WWD_INTERRUPT_TIMER : 5; /*!< [4..0] Watchdog Timer + programming values */ + __IM uint32_t RESERVED1 : 27; /*!< [31..5] reser */ + } MCU_WWD_INTERRUPT_TIMER_b; + }; + + union { + __IOM uint32_t MCU_WWD_SYSTEM_RESET_TIMER; /*!< (@ 0x00000004) MCU watchdog + system reset register */ + + struct { + __IOM uint32_t WWD_SYSTEM_RESET_TIMER : 5; /*!< [4..0] Watch dog soc reset delay + timer programming values */ + __IM uint32_t RESERVED1 : 27; /*!< [31..5] reser */ + } MCU_WWD_SYSTEM_RESET_TIMER_b; + }; + + union { + __IOM uint32_t MCU_WWD_WINDOW_TIMER; /*!< (@ 0x00000008) watchdog window + timer register */ + + struct { + __IOM uint32_t WINDOW_TIMER : 4; /*!< [3..0] watchdog window timer */ + __IM uint32_t RESERVED1 : 28; /*!< [31..4] reser */ + } MCU_WWD_WINDOW_TIMER_b; + }; + + union { + __IOM uint32_t MCU_WWD_ARM_STUCK_EN; /*!< (@ 0x0000000C) watchdog arm stuck + enable register */ + + struct { + __IM uint32_t RESERVED1 : 16; /*!< [15..0] reser */ + __OM uint32_t PROCESSOR_STUCK_RESET_EN : 1; /*!< [16..16] Enable to reset M4 core on + seeing LOCKUP signal */ + __IM uint32_t RESERVED2 : 7; /*!< [23..17] reser */ + __IM uint32_t PROCESSOR_STUCK_RESET_EN_ : 1; /*!< [24..24] Read signal for processor + stuck reset enable */ + __IM uint32_t RESERVED3 : 7; /*!< [31..25] reser */ + } MCU_WWD_ARM_STUCK_EN_b; + }; + + union { + __IOM uint32_t MCU_WWD_MODE_AND_RSTART; /*!< (@ 0x00000010) WATCHDOG mode + and restart register */ + + struct { + __IOM uint32_t WWD_MODE_RSTART : 1; /*!< [0..0] restart pulse to restart + watchdog timer */ + __IM uint32_t RESERVED1 : 15; /*!< [15..1] reser */ + __IOM uint32_t WWD_MODE_EN_STATUS : 8; /*!< [23..16] Watchdog timer mode */ + __IM uint32_t RESERVED2 : 8; /*!< [31..24] reser */ + } MCU_WWD_MODE_AND_RSTART_b; + }; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t MCU_WWD_KEY_ENABLE; /*!< (@ 0x00000018) watchdog key enable + register */ + + struct { + __OM uint32_t WWD_KEY_ENABLE : 32; /*!< [31..0] enable access to program + Watch dog registers */ + } MCU_WWD_KEY_ENABLE_b; + }; +} MCU_WDT_Type; /*!< Size = 28 (0x1c) */ + +/* =========================================================================================================================== + */ +/* ================ RTC + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief The MCU calender acts as RTC with time in seconds, minutes, hours, + * days, months, years and centuries (RTC) + */ + +typedef struct { /*!< (@ 0x2404821C) RTC Structure */ + + union { + __IOM uint32_t MCU_CAL_ALARM_PROG_1; /*!< (@ 0x00000000) MCU calender alarm + prog register 1 */ + + struct { + __IOM uint32_t PROG_ALARM_MSEC : 10; /*!< [9..0] milli seconds value of + alarm time */ + __IOM uint32_t PROG_ALARM_SEC : 6; /*!< [15..10] seconds value of alarm time */ + __IOM uint32_t PROG_ALARM_MIN : 6; /*!< [21..16] mins value of alarm time */ + __IOM uint32_t PROG_ALARM_HOUR : 5; /*!< [26..22] hours value of alarm time */ + __IM uint32_t RESERVED1 : 5; /*!< [31..27] reser */ + } MCU_CAL_ALARM_PROG_1_b; + }; + + union { + __IOM uint32_t MCU_CAL_ALARM_PROG_2; /*!< (@ 0x00000004) MCU calender alarm + prog register 2 */ + + struct { + __IOM uint32_t PROG_ALARM_DAY : 5; /*!< [4..0] day count in alarm time 1-31 */ + __IM uint32_t RESERVED1 : 3; /*!< [7..5] reser */ + __IOM uint32_t PROG_ALARM_MONTH : 4; /*!< [11..8] month count in alarm time */ + __IM uint32_t RESERVED2 : 4; /*!< [15..12] reser */ + __IOM uint32_t PROG_ALARM_YEAR : 7; /*!< [22..16] year count in alarm time + 0 - 99 */ + __IOM uint32_t PROG_ALARM_CENTURY : 2; /*!< [24..23] century count in alarm time */ + __IM uint32_t RESERVED3 : 6; /*!< [30..25] reser */ + __IOM uint32_t ALARM_EN : 1; /*!< [31..31] alarm function enable for calendar */ + } MCU_CAL_ALARM_PROG_2_b; + }; + + union { + __IOM uint32_t MCU_CAL_POWERGATE_REG; /*!< (@ 0x00000008) MCU calender + powergate register */ + + struct { + __IOM uint32_t PG_EN_CALENDER : 1; /*!< [0..0] Start calender block */ + __IOM uint32_t ENABLE_CALENDER_COMBI : 1; /*!< [1..1] Enable calender + combitional logic block */ + __IOM uint32_t DISABLE_COMBI_DYN_PWRGATE_EN : 1; /*!< [2..2] Disable option for + dynamic combo RTC power gate */ + __IOM uint32_t STATIC_COMBI_RTC_PG_EN : 1; /*!< [3..3] Enable static combo + RTC power gate */ + __IM uint32_t RESERVED1 : 28; /*!< [31..4] RESERVED1 */ + } MCU_CAL_POWERGATE_REG_b; + }; + + union { + __IOM uint32_t MCU_CAL_PROG_TIME_1; /*!< (@ 0x0000000C) MCU calendar prog + time 1 register */ + + struct { + __IOM uint32_t PROG_MSEC : 10; /*!< [9..0] Milli seconds value to be programmed to + real time in calendar when pro_time_trig is 1 */ + __IOM uint32_t PROG_SEC : 6; /*!< [15..10] seconds value to be programmed to real + time in calendar when pro_time_trig is 1 */ + __IOM uint32_t PROG_MIN : 6; /*!< [21..16] minutes value to be programmed to real + time in calendar when pro_time_trig is 1 */ + __IOM uint32_t PROG_HOUR : 5; /*!< [26..22] hours value to be programmed to real time + in calendar when pro_time_trig is 1 */ + __IM uint32_t RESERVED2 : 5; /*!< [31..27] reser */ + } MCU_CAL_PROG_TIME_1_b; + }; + + union { + __IOM uint32_t MCU_CAL_PROG_TIME_2; /*!< (@ 0x00000010) MCU calendar prog + time 2 register */ + + struct { + __IOM uint32_t PROG_DAY : 5; /*!< [4..0] day count value to be programmed to real + time in calendar when pro_time_trig is 1 */ + __IOM uint32_t PROG_WEEK_DAY : 3; /*!< [7..5] program which week day it is */ + __IOM uint32_t PROG_MONTH : 4; /*!< [11..8] month value to be programmed to real time + in calendar when pro_time_trig is 1 */ + __IM uint32_t RES : 4; /*!< [15..12] reser */ + __IOM uint32_t PROG_YEAR : 7; /*!< [22..16] year value to be programmed to real time + in calendar when pro_time_trig is 1 */ + __IOM uint32_t PROG_CENTURY : 2; /*!< [24..23] century value to be programmed to real + time in calendar when pro_time_trig is 1 */ + __IM uint32_t RESERVED1 : 6; /*!< [30..25] reser */ + __OM uint32_t PROG_TIME_TRIG : 1; /*!< [31..31] load the programmed to the + real time in calendar block */ + } MCU_CAL_PROG_TIME_2_b; + }; + + union { + __IM uint32_t MCU_CAL_READ_TIME_MSB; /*!< (@ 0x00000014) MCU calendar read + time msb */ + + struct { + __IM uint32_t WEEK_DAY : 3; /*!< [2..0] week day */ + __IM uint32_t MONTHS_COUNT : 4; /*!< [6..3] months count */ + __IM uint32_t YEAR_COUNT : 7; /*!< [13..7] years count */ + __IM uint32_t CENTURY_COUNT : 2; /*!< [15..14] century count */ + __IM uint32_t RESERVED1 : 16; /*!< [31..16] reser */ + } MCU_CAL_READ_TIME_MSB_b; + }; + + union { + __IM uint32_t MCU_CAL_READ_TIME_LSB; /*!< (@ 0x00000018) MCU calendar read + time lsb */ + + struct { + __IM uint32_t MILLISECONDS_COUNT : 10; /*!< [9..0] milliseconds count */ + __IM uint32_t SECONDS_COUNT : 6; /*!< [15..10] seconds count */ + __IM uint32_t MINS_COUNT : 6; /*!< [21..16] mins count */ + __IM uint32_t HOURS_COUNT : 5; /*!< [26..22] hours count */ + __IM uint32_t DAYS_COUNT : 5; /*!< [31..27] days count */ + } MCU_CAL_READ_TIME_LSB_b; + }; + + union { + __IM uint32_t MCU_CAL_READ_COUNT_TIMER; /*!< (@ 0x0000001C) MCU calendar + read count timer */ + + struct { + __IM uint32_t READ_COUNT_TIMER : 27; /*!< [26..0] Read timer which increments by + time period value to reach to count + milliseconds */ + __IM uint32_t RESERVED1 : 5; /*!< [31..27] reser */ + } MCU_CAL_READ_COUNT_TIMER_b; + }; + + union { + __IM uint32_t MCU_CAL_SLEEP_CLK_COUNTERS; /*!< (@ 0x00000020) MCU calendar + sleep clock counter */ + + struct { + __IM uint32_t SLEEP_CLK_DURATION : 12; /*!< [11..0] No of sleep clks with respect to + APB clock so far from + the posedge of sleep clk */ + __IM uint32_t RESERVED1 : 4; /*!< [15..12] reser */ + __IM uint32_t PCLK_COUNT_WRT_SLEEP_CLK : 12; /*!< [27..16] no. of APB clks in 1 + sleep clock duration */ + __IM uint32_t RESERVED2 : 4; /*!< [31..28] reser */ + } MCU_CAL_SLEEP_CLK_COUNTERS_b; + }; + + union { + __OM uint32_t MCU_CAL_KEY_EANBLE; /*!< (@ 0x00000024) MCU calendar key enable */ + + struct { + __OM uint32_t RTC_KEY : 32; /*!< [31..0] enable access to program Watch + dog registers */ + } MCU_CAL_KEY_EANBLE_b; + }; +} RTC_Type; /*!< Size = 40 (0x28) */ + +/* =========================================================================================================================== + */ +/* ================ BATT_FF + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief The use of this is to store some information in ULP over wake-ups to + * reduce wake-up time (BATT_FF) + */ + +typedef struct { /*!< (@ 0x24048400) BATT_FF Structure */ + + union { + __IOM uint32_t M4SS_BYPASS_PWRCTRL_REG1; /*!< (@ 0x00000000) M4ss bypass + power control register 1 */ + + struct { + __IM uint32_t RES : 3; /*!< [2..0] reserved1 */ + __IOM uint32_t BYPASS_M4SS_PWRCTL_ULP_M4_ULP_AON_b : 1; /*!< [3..3] Enables software + based control of isolation + and reset + for ULP AON M4ss */ + __IOM uint32_t BYPASS_M4SS_PWRCTL_ULP_EFUSE_b : 1; /*!< [4..4] Enables software based + control of isolation and reset + for ULP EFUSE */ + __IOM uint32_t RESERVED2 : 4; /*!< [8..5] reserved2 */ + __IOM uint32_t BYPASS_M4SS_PWRCTL_ULP_RPDMA_b : 1; /*!< [9..9] Enables software based + control of isolation and reset + for RPDMA */ + __IOM uint32_t RESERVED3 : 1; /*!< [10..10] reserved3 */ + __IOM uint32_t BYPASS_M4SS_PWRCTL_ULP_HIF_SDIO_SPI_b : 1; /*!< [11..11] Enables + software based control of + isolation and reset for + HIF SDIO SPI */ + __IOM uint32_t RESERVED4 : 1; /*!< [12..12] reserved4 */ + __IOM uint32_t BYPASS_M4SS_PWRCTL_ULP_QSPI_ICACHE_b : 1; /*!< [13..13] Enables + software based control of + isolation and reset for + ULP quad SPI and ICACHE + */ + __IOM uint32_t BYPASS_M4SS_PWRCTL_ULP_IID_b : 1; /*!< [14..14] Enables software based + control of isolation and reset + for ULP IID */ + __IOM uint32_t RESERVED5 : 2; /*!< [16..15] reserved5 */ + __IOM + uint32_t BYPASS_M4SS_PWRCTL_ULP_M4_DEBUG_b : 1; /*!< [17..17] Enables + software based control + of isolation and reset + for M4ss DEBUG */ + __IOM uint32_t BYPASS_M4SS_PWRCTL_ULP_M4_CORE_b : 1; /*!< [18..18] Enables software + based control of isolation + and reset for M4ss CORE */ + __IOM uint32_t BYPASS_M4SS_PWRCTL_ULP_AON_b : 1; /*!< [19..19] Enables software based + control of isolation and reset + for ULP AON */ + __IM uint32_t RESERVED6 : 2; /*!< [21..20] reserved6 */ + __IOM uint32_t BYPASS_M4SS_PWRCTL_ULP_ROM_b : 1; /*!< [22..22] Enables software based + control of isolation and reset + for M4ss ROM */ + __IM uint32_t RESERVED7 : 9; /*!< [31..23] reserved7 */ + } M4SS_BYPASS_PWRCTRL_REG1_b; + }; + + union { + __IOM uint32_t M4SS_BYPASS_PWRCTRL_REG2; /*!< (@ 0x00000004) M4SS bypass + power control register 2 */ + + struct { + __IOM uint32_t BYPASS_M4SS_PWRCTL_ULP_SRAM_1 : 10; /*!< [9..0] Enables software based + control of isolation and reset + for M4ss SRAM 1 */ + __IM uint32_t RESERVED1 : 6; /*!< [15..10] reserved1 */ + __IOM uint32_t BYPASS_M4SS_PWRCTL_ULP_SRAM_2 : 4; /*!< [19..16] Enables software + based control of isolation and + reset for M4ss SRAM 2 */ + __IM uint32_t RESERVED2 : 12; /*!< [31..20] reserved1 */ + } M4SS_BYPASS_PWRCTRL_REG2_b; + }; + + union { + __IOM uint32_t M4SS_PWRCTRL_SET_REG; /*!< (@ 0x00000008) M4SS power control + set register */ + + struct { + __IM uint32_t RES : 4; /*!< [3..0] reserved1 */ + __IOM uint32_t M4SS_PWRGATE_EN_N_ULP_EFUSE_b : 1; /*!< [4..4] Power Gate control for + EFUSE */ + __IM uint32_t RESERVED2 : 4; /*!< [8..5] reserved2 */ + __IOM uint32_t M4SS_PWRGATE_EN_N_ULP_RPDMA_b : 1; /*!< [9..9] Power Gate control for + RPDMA */ + __IM uint32_t RESERVED3 : 1; /*!< [10..10] reserved3 */ + __IOM uint32_t M4SS_PWRGATE_EN_N_ULP_HIF_SDIO_SPI_b : 1; /*!< [11..11] Power Gate + control for HIF SDIO SPI + */ + __IM uint32_t RESERVED4 : 1; /*!< [12..12] reserved4 */ + __IOM uint32_t M4SS_PWRGATE_EN_N_ULP_QSPI_ICACHE_b : 1; /*!< [13..13] Power Gate + control for QSPI and + ICACHE */ + __IOM uint32_t M4SS_PWRGATE_EN_N_ULP_IID_b : 1; /*!< [14..14] Power Gate control for + IID Block.If set, powered ON + Clearing this bit has no effect */ + __IM uint32_t RESERVED5 : 2; /*!< [16..15] reserved5 */ + __IOM uint32_t M4SS_PWRGATE_EN_N_ULP_M4_DEBUG_b : 1; /*!< [17..17] Power Gate control + for M4 DEBUG */ + __IOM uint32_t M4SS_PWRGATE_EN_N_ULP_M4_CORE_b : 1; /*!< [18..18] Power Gate control + for M4 CORE */ + __IM uint32_t RESERVED6 : 3; /*!< [21..19] reserved6 */ + __IOM uint32_t M4SS_EXT_PWRGATE_EN_N_ULP_ROM_b : 1; /*!< [22..22] External power gate + enable signal for ROM */ + __IM uint32_t RESERVED7 : 9; /*!< [31..23] reserved7 */ + } M4SS_PWRCTRL_SET_REG_b; + }; + + union { + __IOM uint32_t M4SS_PWRCTRL_CLEAR_REG; /*!< (@ 0x0000000C) M4SS power + control clear register */ + + struct { + __IM uint32_t RES : 4; /*!< [3..0] reserved1 */ + __IOM uint32_t M4SS_PWRGATE_EN_N_ULP_EFUSE_b : 1; /*!< [4..4] Power Gate control for + EFUSE */ + __IM uint32_t RESERVED2 : 4; /*!< [8..5] reserved2 */ + __IOM uint32_t M4SS_PWRGATE_EN_N_ULP_RPDMA_b : 1; /*!< [9..9] Power Gate control for + RPDMA */ + __IM uint32_t RESERVED3 : 1; /*!< [10..10] reserved3 */ + __IOM uint32_t M4SS_PWRGATE_EN_N_ULP_HIF_SDIO_SPI_b : 1; /*!< [11..11] Power Gate + control for HIF SDIO SPI + */ + __IM uint32_t RESERVED4 : 1; /*!< [12..12] reserved4 */ + __IOM uint32_t M4SS_PWRGATE_EN_N_ULP_QSPI_ICACHE_b : 1; /*!< [13..13] Power Gate + control for QSPI and + ICACHE */ + __IOM uint32_t M4SS_PWRGATE_EN_N_ULP_IID_b : 1; /*!< [14..14] Power Gate control for + IID Block.If set, powered ON + Clearing this bit has no effect */ + __IM uint32_t RESERVED5 : 2; /*!< [16..15] reserved5 */ + __IOM uint32_t M4SS_PWRGATE_EN_N_ULP_M4_DEBUG_b : 1; /*!< [17..17] Power Gate control + for M4 DEBUG */ + __IOM uint32_t M4SS_PWRGATE_EN_N_ULP_M4_CORE_b : 1; /*!< [18..18] Power Gate control + for M4 CORE */ + __IM uint32_t RESERVED6 : 3; /*!< [21..19] reserved6 */ + __IOM uint32_t M4SS_EXT_PWRGATE_EN_N_ULP_ROM_b : 1; /*!< [22..22] External power gate + enable signal for ROM */ + __IM uint32_t RESERVED7 : 9; /*!< [31..23] reserved7 */ + } M4SS_PWRCTRL_CLEAR_REG_b; + }; + + union { + __IOM uint32_t M4_SRAM_PWRCTRL_SET_REG1; /*!< (@ 0x00000010) M4SS power + control set register 1 */ + + struct { + __IOM uint32_t M4SS_EXT_PWRGATE_EN_N_ULP_SRAM_1 : 10; /*!< [9..0] Functional Control + signal for M4SS SRAM */ + __IM uint32_t RESERVED1 : 6; /*!< [15..10] reserved1 */ + __IOM uint32_t M4SS_EXT_PWRGATE_EN_N_ULP_SRAM_2 : 4; /*!< [19..16] Functional Control + signal for TASS SRAM shared + with M4SS */ + __IOM uint32_t RESERVED2 : 12; /*!< [31..20] reserved1 */ + } M4_SRAM_PWRCTRL_SET_REG1_b; + }; + + union { + __IOM uint32_t M4_SRAM_PWRCTRL_CLEAR_REG1; /*!< (@ 0x00000014) M4SS power + control clear register 1 */ + + struct { + __IOM uint32_t M4SS_EXT_PWRGATE_EN_N_ULP_SRAM_1 : 10; /*!< [9..0] Functional Control + signal for M4SS SRAM */ + __IOM uint32_t RESERVED1 : 6; /*!< [15..10] reserved1 */ + __IOM uint32_t M4SS_EXT_PWRGATE_EN_N_ULP_SRAM_2 : 4; /*!< [19..16] Functional Control + signal for TASS SRAM shared + with M4SS */ + __IOM uint32_t RESERVED2 : 12; /*!< [31..20] reserved1 */ + } M4_SRAM_PWRCTRL_CLEAR_REG1_b; + }; + + union { + __IOM uint32_t M4_SRAM_PWRCTRL_SET_REG2; /*!< (@ 0x00000018) M4SS power + control set register 2 */ + + struct { + __IOM uint32_t M4SS_EXT_PWRGATE_EN_N_ULP_SRAM_PERI_1 : 10; /*!< [9..0] Functional + Control signal for M4SS + SRAM Dual Rail pins */ + __IOM uint32_t RESERVED1 : 6; /*!< [15..10] reserved1 */ + __IOM uint32_t M4SS_EXT_PWRGATE_EN_N_ULP_SRAM_PERI_2 : 4; /*!< [19..16] Functional + Control signal for TASS + SRAM Dual Rail pins + shared with M4SS */ + __IOM uint32_t RESERVED2 : 12; /*!< [31..20] reserved1 */ + } M4_SRAM_PWRCTRL_SET_REG2_b; + }; + + union { + __IOM uint32_t M4_SRAM_PWRCTRL_CLEAR_REG2; /*!< (@ 0x0000001C) M4SS power + control clear register 2 */ + + struct { + __IOM uint32_t M4SS_EXT_PWRGATE_EN_N_ULP_SRAM_PERI_1 : 10; /*!< [9..0] Functional + Control signal for M4SS + SRAM Dual Rail pins */ + __IOM uint32_t RESERVED1 : 6; /*!< [15..10] reserved1 */ + __IOM uint32_t M4SS_EXT_PWRGATE_EN_N_ULP_SRAM_PERI_2 : 4; /*!< [19..16] Functional + Control signal for TASS + SRAM Dual Rail pins + shared with M4SS */ + __IOM uint32_t RESERVED2 : 12; /*!< [31..20] reserved1 */ + } M4_SRAM_PWRCTRL_CLEAR_REG2_b; + }; + + union { + __IOM uint32_t M4_SRAM_PWRCTRL_SET_REG3; /*!< (@ 0x00000020) M4SS power + control set register 3 */ + + struct { + __IOM uint32_t M4SS_SRAM_INPUT_DISABLE_ISOLATION_ULP_1 : 10; /*!< [9..0] Input + isolation control for + M4SS SRAM */ + __IOM uint32_t RESERVED1 : 6; /*!< [15..10] reserved1 */ + __IOM uint32_t M4SS_SRAM_INPUT_DISABLE_ISOLATION_ULP_2 : 4; /*!< [19..16] Input + isolation control for + TASS SRAM shared with + M4SS */ + __IOM uint32_t RESERVED2 : 12; /*!< [31..20] reserved1 */ + } M4_SRAM_PWRCTRL_SET_REG3_b; + }; + + union { + __IOM uint32_t M4_SRAM_PWRCTRL_CLEAR_REG3; /*!< (@ 0x00000024) M4SS power + control clear register 3 */ + + struct { + __IOM uint32_t M4SS_SRAM_INPUT_DISABLE_ISOLATION_ULP_1 : 10; /*!< [9..0] Input + isolation control for + M4SS SRAM */ + __IOM uint32_t RESERVED1 : 6; /*!< [15..10] reserved1 */ + __IOM uint32_t M4SS_SRAM_INPUT_DISABLE_ISOLATION_ULP_2 : 4; /*!< [19..16] Input + isolation control for + TASS SRAM shared with + M4SS */ + __IOM uint32_t RESERVED2 : 12; /*!< [31..20] reserved1 */ + } M4_SRAM_PWRCTRL_CLEAR_REG3_b; + }; + + union { + __IOM uint32_t M4_SRAM_PWRCTRL_SET_REG4; /*!< (@ 0x00000028) M4SS power + control set register 4 */ + + struct { + __IOM uint32_t M4SS_SRAM_DS_1 : 24; /*!< [23..0] Deep-Sleep control for + M4SS SRAM */ + __IOM uint32_t RESERVED1 : 8; /*!< [31..24] reserved1 */ + } M4_SRAM_PWRCTRL_SET_REG4_b; + }; + + union { + __IOM uint32_t M4_SRAM_PWRCTRL_CLEAR_REG4; /*!< (@ 0x0000002C) M4SS power + control clear register 4 */ + + struct { + __IOM uint32_t M4SS_SRAM_DS_1 : 24; /*!< [23..0] Deep-Sleep control for + M4SS SRAM */ + __IOM uint32_t RESERVED1 : 8; /*!< [31..24] reserved1 */ + } M4_SRAM_PWRCTRL_CLEAR_REG4_b; + }; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t M4SS_TASS_CTRL_SET_REG; /*!< (@ 0x00000034) M4SS_TASS control + set register */ + + struct { + __IOM uint32_t M4SS_CTRL_TASS_AON_PWRGATE_EN : 1; /*!< [0..0] M4SS controlling Power + supply for TASS AON domain */ + __IOM uint32_t M4SS_CTRL_TASS_AON_DISABLE_ISOLATION_BYPASS : 1; /*!< [1..1] M4SS + controlling Power supply + for TASS AON domains + isolation enable in + bypass mode */ + __IOM uint32_t M4SS_CTRL_TASS_AON_PWR_DMN_RST_BYPASS : 1; /*!< [2..2] M4SS + controlling Power supply + for TASS AON domains + reset + pin in bypass mode */ + __IOM uint32_t RESERVED1 : 29; /*!< [31..3] reserved1 */ + } M4SS_TASS_CTRL_SET_REG_b; + }; + + union { + __IOM uint32_t M4SS_TASS_CTRL_CLEAR_REG; /*!< (@ 0x00000038) M4SS_TASS + control CLEAR register */ + + struct { + __IOM uint32_t M4SS_CTRL_TASS_AON_PWRGATE_EN : 1; /*!< [0..0] M4SS controlling Power + supply for TASS AON domain */ + __IOM uint32_t M4SS_CTRL_TASS_AON_DISABLE_ISOLATION_BYPASS : 1; /*!< [1..1] M4SS + controlling Power supply + for TASS AON domains + isolation enable in + bypass mode */ + __IOM uint32_t M4SS_CTRL_TASS_AON_PWR_DMN_RST_BYPASS : 1; /*!< [2..2] M4SS + controlling Power supply + for TASS AON domains + reset + pin in bypass mode */ + __IOM uint32_t RESERVED1 : 29; /*!< [31..3] reserved1 */ + } M4SS_TASS_CTRL_CLEAR_REG_b; + }; + + union { + __IOM uint32_t M4_ULP_MODE_CONFIG; /*!< (@ 0x0000003C) m4 ulp mode config register */ + + struct { + __IOM uint32_t ULPMODE_ISOLATION_CTRL_ULPSS : 1; /*!< [0..0] Isolation Control for + ULP-Mode non-functional paths for + ULPSS */ + __IOM uint32_t ULPMODE_ISOLATION_CTRL_M4SS_AON : 1; /*!< [1..1] Isolation Control for + ULP-Mode non-functional paths + for M4SS-AON */ + __IOM uint32_t ULPMODE_ISOLATION_CTRL_M4_ULP : 1; /*!< [2..2] Isolation Control for + ULP-Mode non-functional paths + for M4ULP_AON */ + __IOM uint32_t ULPMODE_ISOLATION_CTRL_M4_CORE : 1; /*!< [3..3] Isolation Control for + ULP-Mode non-functional paths + for M4_CORE */ + __IOM uint32_t ULPMODE_ISOLATION_CTRL_M4_DEBUG_FPU : 1; /*!< [4..4] Isolation Control + for ULP-Mode + non-functional paths for + M4_DEBUG */ + __IOM uint32_t ULPMODE_ISOLATION_CTRL_M4_ROM : 1; /*!< [5..5] Isolation Control for + ULP-Mode non-functional paths + for ROM */ + __IOM uint32_t RES : 26; /*!< [31..6] reserved1 */ + } M4_ULP_MODE_CONFIG_b; + }; + + union { + __IOM uint32_t ULPSS_BYPASS_PWRCTRL_REG; /*!< (@ 0x00000040) ULPSS bypass + power control register */ + + struct { + __IOM uint32_t RES : 2; /*!< [1..0] reserved1 */ + __IOM uint32_t BYPASS_ULPTASS_PWRCTL_ULP_AON : 1; /*!< [2..2] Enables software based + control of output isolation for + ULPTASS AON */ + __IOM + uint32_t BYPASS_ULPSDCSS_PWRCTRL_ULP_AON : 1; /*!< [3..3] Enables software + based control of output + isolation for + ULPSDCSS AON */ + __IOM uint32_t RESERVED2 : 1; /*!< [4..4] reser */ + __IOM uint32_t BYPASS_ULPTASS_PWRCTL_ULP_MISC : 1; /*!< [5..5] Enables software based + control of output isolation for + ULP MISC */ + __IOM uint32_t BYPASS_ULPTASS_PWRCTL_ULP_CAP : 1; /*!< [6..6] Enables software based + control of output isolation for + ULP CAP */ + __IOM uint32_t BYPASS_ULPTASS_PWRCTL_ULP_VAD : 1; /*!< [7..7] Enables software based + control of output isolation for + ULP VAD */ + __IOM uint32_t BYPASS_ULPTASS_PWRCTL_ULP_UART : 1; /*!< [8..8] Enables software based + control of output isolation for + ULP UART */ + __IOM uint32_t BYPASS_ULPTASS_PWRCTL_ULP_SSI : 1; /*!< [9..9] Enables software based + control of output isolation for + ULP SSI */ + __IOM uint32_t BYPASS_ULPTASS_PWRCTL_ULP_I2S : 1; /*!< [10..10] Enables software + based control of output + isolation for ULP I2S */ + __IOM uint32_t BYPASS_ULPTASS_PWRCTL_ULP_I2C : 1; /*!< [11..11] Enables software + based control of output + isolation for ULP I2C */ + __IOM uint32_t BYPASS_ULPTASS_PWRCTL_ULP_AUX : 1; /*!< [12..12] Enables software + based control of output isolation + for ULP AUX */ + __IOM uint32_t BYPASS_ULPTASS_PWRCTL_ULP_IR : 1; /*!< [13..13] Enables software based + control of output isolation + for ULP IR */ + __IOM uint32_t BYPASS_ULPTASS_PWRCTL_ULP_UDMA : 1; /*!< [14..14] Enables software + based control of output + isolation for ULP UDMA */ + __IOM uint32_t BYPASS_ULPTASS_PWRCTL_ULP_FIM : 1; /*!< [15..15] Enables software + based control of output + isolation for ULP FIM */ + __IOM uint32_t RESERVED3 : 3; /*!< [18..16] reserved1 */ + __IOM uint32_t BYPASS_ULPTASS_PWRCTL_ULP_SRAM : 4; /*!< [22..19] Enables software + based control of output + isolation for ULPTASS SRAM */ + __IOM uint32_t RESERVED4 : 9; /*!< [31..23] reserved1 */ + } ULPSS_BYPASS_PWRCTRL_REG_b; + }; + + union { + __IOM uint32_t ULPSS_PWRCTRL_SET_REG; /*!< (@ 0x00000044) ULPSS power + control set register */ + + struct { + __IOM uint32_t RES : 18; /*!< [17..0] reserved1 */ + __IOM uint32_t ULPTASS_EXT_PWRGATE_EN_N_ULP_MISC : 1; /*!< [18..18] Functional + Control signal for ULPTASS + MISC */ + __IOM uint32_t ULPTASS_EXT_PWRGATE_EN_N_ULP_CAP : 1; /*!< [19..19] Functional Control + signal for ULPTASS CAP */ + __IOM uint32_t RESERVED2 : 1; /*!< [20..20] reserved2 */ + __IOM uint32_t ULPTASS_EXT_PWRGATE_EN_N_ULP_UART : 1; /*!< [21..21] Functional + Control signal for ULPTASS + UART */ + __IOM uint32_t ULPTASS_EXT_PWRGATE_EN_N_ULP_SSI : 1; /*!< [22..22] Functional Control + signal for ULPTASS SSI */ + __IOM uint32_t ULPTASS_EXT_PWRGATE_EN_N_ULP_I2S : 1; /*!< [23..23] Functional Control + signal for ULPTASS I2S */ + __IOM uint32_t ULPTASS_EXT_PWRGATE_EN_N_ULP_I2C : 1; /*!< [24..24] Functional Control + signal for ULPTASS I2C */ + __IOM uint32_t ULPTASS_EXT_PWRGATE_EN_N_ULP_AUX : 1; /*!< [25..25] Functional Control + signal for ULPTASS AUX */ + __IOM uint32_t ULPTASS_EXT_PWRGATE_EN_N_ULP_IR : 1; /*!< [26..26] Functional Control + signal for ULPTASS IR */ + __IOM uint32_t ULPTASS_EXT_PWRGATE_EN_N_ULP_UDMA : 1; /*!< [27..27] Functional + Control signal for ULPTASS + UDMA */ + __IOM uint32_t ULPTASS_EXT_PWRGATE_EN_N_ULP_FIM : 1; /*!< [28..28] Functional Control + signal for ULPTASS FIM */ + __IOM uint32_t RESERVED3 : 3; /*!< [31..29] RESERVED3 */ + } ULPSS_PWRCTRL_SET_REG_b; + }; + + union { + __IOM uint32_t ULPSS_PWRCTRL_CLEAR_REG; /*!< (@ 0x00000048) ULPSS power + control clear register */ + + struct { + __IOM uint32_t RESERVED1 : 18; /*!< [17..0] reserved1 */ + __IOM uint32_t ULPTASS_EXT_PWRGATE_EN_N_ULP_MISC : 1; /*!< [18..18] Functional + Control signal for ULPTASS + MISC */ + __IOM uint32_t ULPTASS_EXT_PWRGATE_EN_N_ULP_CAP : 1; /*!< [19..19] Functional Control + signal for ULPTASS CAP */ + __IOM uint32_t RESERVED2 : 1; /*!< [20..20] reserved2 */ + __IOM uint32_t ULPTASS_EXT_PWRGATE_EN_N_ULP_UART : 1; /*!< [21..21] Functional + Control signal for ULPTASS + UART */ + __IOM uint32_t ULPTASS_EXT_PWRGATE_EN_N_ULP_SSI : 1; /*!< [22..22] Functional Control + signal for ULPTASS SSI */ + __IOM uint32_t ULPTASS_EXT_PWRGATE_EN_N_ULP_I2S : 1; /*!< [23..23] Functional Control + signal for ULPTASS I2S */ + __IOM uint32_t ULPTASS_EXT_PWRGATE_EN_N_ULP_I2C : 1; /*!< [24..24] Functional Control + signal for ULPTASS I2C */ + __IOM uint32_t ULPTASS_EXT_PWRGATE_EN_N_ULP_AUX : 1; /*!< [25..25] Functional Control + signal for ULPTASS AUX */ + __IOM uint32_t ULPTASS_EXT_PWRGATE_EN_N_ULP_IR : 1; /*!< [26..26] Functional Control + signal for ULPTASS IR */ + __IOM uint32_t ULPTASS_EXT_PWRGATE_EN_N_ULP_UDMA : 1; /*!< [27..27] Functional + Control signal for ULPTASS + UDMA */ + __IOM uint32_t ULPTASS_EXT_PWRGATE_EN_N_ULP_FIM : 1; /*!< [28..28] Functional Control + signal for ULPTASS FIM */ + __IOM uint32_t RESERVED3 : 3; /*!< [31..29] RESERVED3 */ + } ULPSS_PWRCTRL_CLEAR_REG_b; + }; + + union { + __IOM uint32_t ULPSS_RAM_PWRCTRL_SET_REG1; /*!< (@ 0x0000004C) ULPSS ram power control + set register1 */ + + struct { + __IOM uint32_t ULPTASS_EXT_PWRGATE_EN_N_ULP_SRAM : 4; /*!< [3..0] Functional Control + signal for ULPSS SRAM pins + */ + __IOM uint32_t RESERVED1 : 28; /*!< [31..4] reserved1 */ + } ULPSS_RAM_PWRCTRL_SET_REG1_b; + }; + + union { + __IOM uint32_t ULPSS_RAM_PWRCTRL_CLEAR_REG1; /*!< (@ 0x00000050) ULPSS ram power + control clear register1 */ + + struct { + __IOM uint32_t ULPTASS_EXT_PWRGATE_EN_N_ULP_SRAM : 4; /*!< [3..0] Functional Control + signal for ULPSS SRAM pins + */ + __IOM uint32_t RESERVED1 : 28; /*!< [31..4] reserved1 */ + } ULPSS_RAM_PWRCTRL_CLEAR_REG1_b; + }; + + union { + __IOM uint32_t ULPSS_RAM_PWRCTRL_SET_REG2; /*!< (@ 0x00000054) ULPSS ram power control + set register2 */ + + struct { + __IOM uint32_t ULPTASS_SRAM_INPUT_DISABLE_ISOLATION_ULP : 4; /*!< [3..0] Input + isolation control for + ULPTASS SRAM */ + __IOM uint32_t RESERVED1 : 12; /*!< [15..4] reserved1 */ + __IOM uint32_t SRAM_DS_ULP_PROC_1 : 4; /*!< [19..16] Deep-Sleep control + for ULPTASS SRAM */ + __IOM uint32_t RESERVED2 : 12; /*!< [31..20] reserved1 */ + } ULPSS_RAM_PWRCTRL_SET_REG2_b; + }; + + union { + __IOM uint32_t ULPSS_RAM_PWRCTRL_CLEAR_REG2; /*!< (@ 0x00000058) ULPSS ram power + control clear register2 */ + + struct { + __IOM uint32_t ULPTASS_SRAM_INPUT_DISABLE_ISOLATION_ULP : 4; /*!< [3..0] Input + isolation control for + ULPTASS SRAM */ + __IOM uint32_t RESERVED1 : 12; /*!< [15..4] reserved1 */ + __IOM uint32_t SRAM_DS_ULP_PROC_1 : 4; /*!< [19..16] Deep-Sleep control + for ULPTASS SRAM */ + __IOM uint32_t RESERVED2 : 12; /*!< [31..20] reserved1 */ + } ULPSS_RAM_PWRCTRL_CLEAR_REG2_b; + }; + + union { + __IOM uint32_t ULPSS_RAM_PWRCTRL_SET_REG3; /*!< (@ 0x0000005C) ULPSS ram power control + set register3 */ + + struct { + __IOM uint32_t ULPTASS_EXT_PWRGATE_EN_N_ULP_SRAM_PERI_1 : 4; /*!< [3..0] Functional + Control signal for + ULPTASS SRAM Dual Rail + pins */ + __IOM uint32_t RES : 28; /*!< [31..4] reserved1 */ + } ULPSS_RAM_PWRCTRL_SET_REG3_b; + }; + + union { + __IOM uint32_t ULPSS_RAM_PWRCTRL_CLEAR_REG3; /*!< (@ 0x00000060) ULPSS ram power + control clear register3 */ + + struct { + __IOM uint32_t ULPTASS_EXT_PWRGATE_EN_N_ULP_SRAM_PERI_1 : 4; /*!< [3..0] Functional + Control signal for + ULPTASS SRAM Dual Rail + pins */ + __IOM uint32_t RES : 28; /*!< [31..4] reserved1 */ + } ULPSS_RAM_PWRCTRL_CLEAR_REG3_b; + }; + + union { + __IOM uint32_t MCU_FSM_CTRL_BYPASS; /*!< (@ 0x00000064) MCU FSM control + bypass register */ + + struct { + __IOM uint32_t MCU_XTAL_EN_40MHZ_BYPASS_CTRL : 1; /*!< [0..0] Xtal 40mhz enable + bypass from MCU */ + __IOM uint32_t MCU_XTAL_EN_40MHZ_BYPASS : 1; /*!< [1..1] Value of Xtal + Enable in bypass mode */ + __IOM uint32_t MCU_PMU_SHUT_DOWN_BYPASS_CTRL : 1; /*!< [2..2] Enable bypass mode to + Control pmu shut down */ + __IOM uint32_t MCU_PMU_SHUT_DOWN_BYPASS : 1; /*!< [3..3] Value of pmu shutdown in + bypass mode */ + __IOM uint32_t MCU_BUCK_BOOST_ENABLE_BYPASS_CTRL : 1; /*!< [4..4] Enable software + control for buck boost + enable */ + __IOM uint32_t MCU_BUCK_BOOST_ENABLE_BYPASS : 1; /*!< [5..5] Value for MCU BuckBoost + Enable in bypass mode */ + __IOM uint32_t RES : 26; /*!< [31..6] reserved1 */ + } MCU_FSM_CTRL_BYPASS_b; + }; + + union { + __IOM uint32_t MCU_PMU_LDO_CTRL_SET; /*!< (@ 0x00000068) MCU PMU LD0 control + set register */ + + struct { + __IOM uint32_t MCU_FLASH_LDO_EN : 1; /*!< [0..0] Enable Flash LDO from M4SS */ + __IOM uint32_t MCU_SCO_LDO_EN : 1; /*!< [1..1] Enable SoC LDO from M4SS */ + __IOM uint32_t MCU_DCDC_EN : 1; /*!< [2..2] Enable PMU DCDC from M4SS */ + __IOM uint32_t RESER : 14; /*!< [16..3] reserved1 */ + __IOM uint32_t MCU_SOC_LDO_LVL : 1; /*!< [17..17] PMU SOC LDO High and Low + Voltage selection */ + __IOM uint32_t MCU_DCDC_LVL : 1; /*!< [18..18] PMU DCDC High and Low + Voltage selection */ + __IOM uint32_t RES : 13; /*!< [31..19] reserved1 */ + } MCU_PMU_LDO_CTRL_SET_b; + }; + + union { + __IOM uint32_t MCU_PMU_LDO_CTRL_CLEAR; /*!< (@ 0x0000006C) MCU PMU LD0 + control clear register */ + + struct { + __IOM uint32_t MCU_FLASH_LDO_EN : 1; /*!< [0..0] Enable Flash LDO from M4SS */ + __IOM uint32_t MCU_SOC_LDO_EN : 1; /*!< [1..1] Enable SoC LDO from M4SS */ + __IOM uint32_t MCU_DCDC_EN : 1; /*!< [2..2] Enable PMU DCDC from M4SS */ + __IOM uint32_t RESER : 14; /*!< [16..3] reserved1 */ + __IOM uint32_t MCU_SOC_LDO_LVL : 1; /*!< [17..17] PMU SOC LDO High and Low + Voltage selection */ + __IOM uint32_t MCU_DCDC_LVL : 1; /*!< [18..18] PMU DCDC High and Low + Voltage selection */ + __IOM uint32_t RES : 13; /*!< [31..19] reserved1 */ + } MCU_PMU_LDO_CTRL_CLEAR_b; + }; + __IM uint32_t RESERVED1[4]; + + union { + __IOM uint32_t PLLCCI_PWRCTRL_REG; /*!< (@ 0x00000080) PLL CCI power control + register */ + + struct { + __IOM uint32_t I2SPLL_ISO_EN : 1; /*!< [0..0] Enables software based control of + isolation and reset for I2SPLL */ + __IOM uint32_t I2SPLL_BYPASS_ISO_GEN : 1; /*!< [1..1] Isolation value */ + __IOM uint32_t INTFPLL_ISO_EN : 1; /*!< [2..2] Enables software based control of + isolation and reset for INTF PLL */ + __IOM uint32_t INTFPLL_BYPASS_ISO_GEN : 1; /*!< [3..3] Isolation value */ + __IOM uint32_t SOCPLL_ISO_ENABLE : 1; /*!< [4..4] Enables software based control of + isolation and reset for SOCPLL */ + __IOM uint32_t SOCPLL_BYPASS_ISO_GEN : 1; /*!< [5..5] Isolation value */ + __IOM uint32_t SOCPLL_SPI_PG_EN : 1; /*!< [6..6] SOCPLL SPI Power Control */ + __IOM uint32_t SOCPLL_VDD13_ISO_EN : 1; /*!< [7..7] SOCPLL MACRO POC Control */ + __IOM uint32_t RES : 24; /*!< [31..8] reserved1 */ + } PLLCCI_PWRCTRL_REG_b; + }; + + union { + __IOM uint32_t DLL_PWRCTRL_REG; /*!< (@ 0x00000084) DLL power control register */ + + struct { + __IOM uint32_t QSPI_DLL_RX_ISO_ENABLE : 1; /*!< [0..0] Enables software based control + of isolation and reset + for QSPI_DLL_TX */ + __IOM uint32_t QSPI_DLL_RX_BYPASS_ISO_GEN : 1; /*!< [1..1] Isolation value */ + __IOM uint32_t QSPI_DLL_RX_PG_EN_N : 1; /*!< [2..2] QPSI DLL RX Power Control */ + __IOM uint32_t RESER : 1; /*!< [3..3] reserved1 */ + __IOM uint32_t QSPI_DLL_TX_ISO_ENABLE : 1; /*!< [4..4] Enables software based control + of isolation and reset + for QSPI_DLL_TX */ + __IOM uint32_t QSPI_DLL_TX_BYPASS_ISO_GEN : 1; /*!< [5..5] Isolation value */ + __IOM uint32_t QSPI_DLL_TX_PG_EN_N : 1; /*!< [6..6] QPSI DLL TX Power Control */ + __IOM uint32_t RESERVED1 : 25; /*!< [31..7] reserved1 */ + } DLL_PWRCTRL_REG_b; + }; +} BATT_FF_Type; /*!< Size = 136 (0x88) */ + +/* =========================================================================================================================== + */ +/* ================ MCU_FSM + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief This is explain the Sleep FSM registers. (MCU_FSM) + */ + +typedef struct { /*!< (@ 0x24048100) MCU_FSM Structure */ + + union { + __IOM uint32_t MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE; /*!< (@ 0x00000000) Sleep Control + Signals and Wakeup source + selection */ + + struct { + __IOM uint32_t MCUFSM_SHUTDOWN_ENABLE : 1; /*!< [0..0] shutdown enable pulse. */ + __IOM uint32_t Reserved1 : 1; /*!< [1..1] It is recommended to write these + bits to 0. */ + __IOM uint32_t LP_SLEEP_MODE_b : 1; /*!< [2..2] setting this bit enables retention of + TASS-RAM, M4SS-RAM in PS2 Active/Sleep state + */ + __IOM uint32_t M4SS_RAM_RETENTION_MODE_EN : 1; /*!< [3..3] shutdown enable + pulse. */ + __IOM uint32_t M4ULP_RAM_RETENTION_MODE_EN_b : 1; /*!< [4..4] RAM retention enable + for ULP M4 ram during deep sleep + */ + __IOM uint32_t TA_RAM_RETENTION_MODE_EN : 1; /*!< [5..5] RAM retention enable for ta + ram during deep sleep */ + __IOM uint32_t ULPSS_RAM_RETENTION_MODE_EN : 1; /*!< [6..6] RAM retention enable for + ulpss ram during deep sleep */ + __IOM uint32_t M4ULP_RAM16K_RETENTION_MODE_EN : 1; /*!< [7..7] To enable retention + mode for m4ulp 16k RAM */ + __IOM uint32_t LDO_SOC_ON_b : 1; /*!< [8..8] ON ldo soc during deep sleep */ + __IOM uint32_t LDO_FLASH_ON_b : 1; /*!< [9..9] ON flash ldo during deep sleep */ + __IOM uint32_t PMU_DCDC_ON_b : 1; /*!< [10..10] 1: PMU DCDC(BUCK) ON,0: + PMU DCDC(BUCK) OFF. */ + __IOM uint32_t SKIP_XTAL_WAIT_TIME : 1; /*!< [11..11] 1 : Skips Xtal Good + Delay wait time. */ + __IOM uint32_t Reserved2 : 2; /*!< [13..12] It is recommended to write + these bits to 0. */ + __IOM uint32_t MCUFSM_WAKEUP_NWPFSM : 1; /*!< [14..14] When Set, mcufsm wakeup enable + will wakeup both NWP FSM and MCU + FSM.Clear this BIT if this feature is not + required.. */ + __IOM uint32_t SLEEP_WAKEUP : 1; /*!< [15..15] Wakeup indication from Processor */ + __IOM uint32_t TIMER_BASED_WAKEUP_b : 1; /*!< [16..16] wakeup enable after deep sleep + counter elapses */ + __IOM uint32_t HOST_BASED_WAKEUP_b : 1; /*!< [17..17] host based wakeup enable */ + __IOM uint32_t WIRELESS_BASED_WAKEUP_b : 1; /*!< [18..18] wireless based + wakeup enable */ + __IOM uint32_t M4_PROC_BASED_WAKEUP_b : 1; /*!< [19..19] wakeup based on + m4 processor enable */ + __IOM uint32_t GPIO_BASED_WAKEUP_b : 1; /*!< [20..20] wakeup on gpio interrupt enable + based in configuration in GPIO WAKEUP + REGISTER */ + __IOM uint32_t COMPR_BASED_WAKEUP_b : 1; /*!< [21..21] compartor based + wakeup enable, either of any 6 + comparator interrupts */ +#ifdef SLI_SI917B0 + __IOM uint32_t SYSRTC_BASED_WAKEUP_b : 1; /*!< [22..22] SYSRTC Based Wakeup */ +#else + __IOM uint32_t Reserved3 : 1; /*!< [22..22] It is recommended to write + these bits to 0. */ +#endif + __IOM uint32_t WIC_BASED_WAKEUP_b : 1; /*!< [23..23] WIC based wakeup mask */ + __IOM uint32_t ULPSS_BASED_WAKEUP_b : 1; /*!< [24..24] ULPSS peripheral + based wakeup */ + __IOM uint32_t SDCSS_BASED_WAKEUP_b : 1; /*!< [25..25] Sensor Data + collector based wakeup */ + __IOM uint32_t ALARM_BASED_WAKEUP_b : 1; /*!< [26..26] Alarm Based wakeup */ + __IOM uint32_t SEC_BASED_WAKEUP_b : 1; /*!< [27..27] Second Pulse Based wakeup */ + __IOM uint32_t MSEC_BASED_WAKEUP_b : 1; /*!< [28..28] Millisecond Pulse + Based wakeup */ + __IOM uint32_t WDT_INTR_BASED_WAKEUP_b : 1; /*!< [29..29] Millisecond + Pulse Based wakeup */ + __IOM uint32_t ULPSS_BASED_SLEEP : 1; /*!< [30..30] ULPSS initiated DeepSleep. */ + __IOM uint32_t SDCSS_BASED_SLEEP : 1; /*!< [31..31] SDCSS initiated DeepSleep. */ + } MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE_b; + }; + + union { + __IOM uint32_t MCU_FSM_PERI_CONFIG_REG; /*!< (@ 0x00000004) Configuration + for Ultra Low-Power Mode of the + processor + (PS2 State) */ + + struct { + __IOM uint32_t ULP_MCU_MODE_EN : 1; /*!< [0..0] Enables voltage switching + for PS2-PS4/PS3 and PS4/PS3-PS2 + state transitions. */ + __IOM uint32_t M4SS_CONTEXT_SWITCH_TOP_ULP_MODE : 2; /*!< [2..1] Enable functional + switching for PS2-PS4/PS3 and + PS4/PS3-PS2 + state transitions */ + __IOM uint32_t WICENREQ : 1; /*!< [3..3] Its enable or disable maximum of 32KB of + LP-SRAM for operation in PS2 state */ + __IOM uint32_t Reserved1 : 12; /*!< [15..4] It is recommended to write + these bits to 0. */ + __IOM uint32_t BGPMU_SAMPLING_EN_R : 1; /*!< [16..16] Controls the mode of Band-Gap + for DC-DC 1.35 during PS2 state. */ + __IOM uint32_t Reserved2 : 15; /*!< [31..17] It is recommended to write + these bits to 0. */ + } MCU_FSM_PERI_CONFIG_REG_b; + }; + + union { + __IOM uint32_t GPIO_WAKEUP_REGISTER; /*!< (@ 0x00000008) GPIO Wakeup Register */ + + struct { + __IOM uint32_t GPIO_0_WAKEUP : 1; /*!< [0..0] Enable gpio 0 based wakeup. */ + __IOM uint32_t GPIO_1_WAKEUP : 1; /*!< [1..1] Enable gpio 1 based wakeup */ + __IOM uint32_t GPIO_2_WAKEUP : 1; /*!< [2..2] Enable gpio 2 based wakeup */ + __IOM uint32_t GPIO_3_WAKEUP : 1; /*!< [3..3] Enable gpio 3 based wakeup */ + __IOM uint32_t GPIO_4_WAKEUP : 1; /*!< [4..4] Enable gpio 3 based wakeup */ + __IOM uint32_t Reserved1 : 11; /*!< [15..5] It is recommended to write + these bits to 0. */ + __IOM uint32_t CONTINIOUS_START : 1; /*!< [16..16] Trigger Deep sleep + timer to start counting. */ + __IOM uint32_t CONTINIOUS_TIMER_ENABLE : 1; /*!< [17..17] Enable Deep sleep timer + mode continuous. */ + __IOM uint32_t DS_TIMER_SOFT_RESET : 1; /*!< [18..18] Enable Deep sleep + timer mode continuous. */ + __IOM uint32_t Reserved2 : 13; /*!< [31..19] It is recommended to write + these bits to 0. */ + } GPIO_WAKEUP_REGISTER_b; + }; + + union { + __IOM uint32_t MCU_FSM_DEEP_SLEEP_DURATION_LSB_REG; /*!< (@ 0x0000000C) MCU FSM DEEP + SLEEP DURATION LSB Register */ + + struct { + __IOM + uint32_t MCUFSM_DEEPSLEEP_DURATION_COUNT : 32; /*!< [31..0] LSB bits of + deep sleep duration + counter after which + system wakes up is + timeout wakeup is + enabled. */ + } MCU_FSM_DEEP_SLEEP_DURATION_LSB_REG_b; + }; + + union { + __IOM uint32_t MCU_FSM_XTAL_AND_PMU_GOOD_COUNT_REG; /*!< (@ 0x00000010) MCU FSM XTAL + AND PMU GOOD COUNT Register */ + + struct { + __IOM uint32_t MCUFSM_PMU_POWERGOOD_DURATION_COUNT : 7; /*!< [6..0] Wait Delay for + PMU POWER GOOD 0 - 5us 1 - + 10us 2 - 12.5us + 3 - 25us 4 - 50us 5 - + 75us. */ + __IOM uint32_t Reserved1 : 9; /*!< [15..7] It is recommended to write + these bits to 0. */ + __IOM uint32_t MCUFSM_XTAL_GOODTIME_DURATION_COUNT : 7; /*!< [22..16] Wait Delay for + XTAL GOOD Time 0 - 5us 1 - + 10us. */ + __IOM uint32_t Reserved2 : 9; /*!< [31..23] It is recommended to write + these bits to 0. */ + } MCU_FSM_XTAL_AND_PMU_GOOD_COUNT_REG_b; + }; + + union { + __IOM uint32_t MCU_FSM_POWER_CTRL_AND_DELAY; /*!< (@ 0x00000014) Power Control and + Delay Configuration for Ultra + Low-Power Mode of the + processor (PS2 State) */ + + struct { + __IOM uint32_t PS2_PMU_LDO_OFF_DELAY : 5; /*!< [4..0] PMU BUCK And LDO + Turn-OFF Delay. */ + __IOM uint32_t Reserved1 : 3; /*!< [7..5] It is recommended to write these + bits to 0. */ + __IOM uint32_t PS4_SOCLDO_ON_DELAY : 4; /*!< [11..8] PMU SOCLDO Turn-ON Delay. */ + __IOM uint32_t PG4_BUCK_ON_DELAY : 4; /*!< [15..12] PMU Buck Turn-ON Delay. */ + __IOM uint32_t FSM_PERI_SOC_LDO_EN : 1; /*!< [16..16] Enable SOCLDO in + Peri mode. */ + __IOM uint32_t FSM_PERI_DCDC_EN : 1; /*!< [17..17] Enable DCDC in Peri mode. */ + __IOM uint32_t Reserved2 : 1; /*!< [18..18] It is recommended to write + these bits to 0. */ + __IOM uint32_t POWER_MUX_SEL_ULPSS : 1; /*!< [19..19] Select value for + ULPSS(Peripherals) Power Mux */ + __IOM uint32_t POWER_MUX_SEL_M4_ULP : 2; /*!< [21..20] Select value for M4 + ULP (Peripherals + Cortex Core + )Power Mux. */ + __IOM uint32_t POWER_MUX_SEL_M4_ULP_RAM_16K : 2; /*!< [23..22] Select value for M4 + ULP RAM 16K Power Mux */ + __IOM uint32_t POWER_MUX_SEL_M4_ULP_RAM : 2; /*!< [25..24] Select value for M4 ULP + RAM Power Mux. */ + __IOM uint32_t POWER_MUX_SEL_ULPSS_RAM : 2; /*!< [27..26] Select value for + ULPSS RAM Power Mux. */ + __IOM uint32_t Reserved3 : 4; /*!< [31..28] It is recommended to write + these bits to 0. */ + } MCU_FSM_POWER_CTRL_AND_DELAY_b; + }; + + union { + __IOM uint32_t MCU_FSM_CLKS_REG; /*!< (@ 0x00000018) MCU FSM Clocks Register */ + + struct { + __IOM uint32_t Reserved1 : 2; /*!< [1..0] It is recommended to write these + bits to 0. */ + __IOM uint32_t HF_FSM_CLK_SELECT : 3; /*!< [4..2] Disable signal for m4ss + reference clock. */ + __IOM uint32_t Reserved2 : 10; /*!< [14..5] It is recommended to write + these bits to 0. */ + __IOM uint32_t HF_FSM_CLK_SWITCHED_SYNC : 1; /*!< [15..15] If high freq fsm clock + select is modified. */ + __IOM uint32_t HF_FSM_CLK_FREQ : 6; /*!< [21..16] High Frequency Source + Clock value in MHz. */ + __IOM uint32_t US_DIV_COUNT : 2; /*!< [23..22] One Micro second division factor. + Program value to + 3. If hf_fsm_gen_2mhz is 0 Program + value to 1. If hf_fsm_gen_2mhz is 1. */ + __IOM uint32_t HF_FSM_GEN_2MHZ : 1; /*!< [24..24] Enable 2Mhz clock for FSM 1 -Enable + 2Mhz option 0- Enable 4MHz option. */ + __IOM uint32_t HF_FSM_CLK_EN : 1; /*!< [25..25] high frequency mcu fsm + clock enable. */ + __IOM uint32_t Reserved3 : 6; /*!< [31..26] It is recommended to write + these bits to 0. */ + } MCU_FSM_CLKS_REG_b; + }; + + union { + __IOM uint32_t MCU_FSM_REF_CLK_REG; /*!< (@ 0x0000001C) MCU FSM Clocks Register */ + + struct { + __IOM uint32_t M4SS_REF_CLK_SEL : 3; /*!< [2..0] Dynamic Reference Clock Mux select + of M4SS 0 - Clock will be gated at dynamic + mux output of M4SS 1 - ulp_32mhz_rc_byp_clk + 2 - ulp_32mhz_rc_clk 3 - rf_ref_clk 4 + - mems_ref_clk 5 + - ulp_20mhz_ringosc_clk 6 - + ulp_doubler_clk 7 - ref_byp_clk to TASS. */ + __IOM uint32_t Reserved1 : 4; /*!< [6..3] It is recommended to write these + bits to 0. */ + __IOM uint32_t M4SS_REF_CLK_CLEANER_OFF_b : 1; /*!< [7..7] Disable signal for m4ss + reference clock. */ + __IOM uint32_t M4SS_REF_CLK_CLEANER_ON_b : 1; /*!< [8..8] Enable clk cleaner for m4ss + reference clock. */ + __IOM uint32_t Reserved2 : 3; /*!< [11..9] It is recommended to write + these bits to 0. */ + __IOM uint32_t TASS_REF_CLK_SEL : 3; /*!< [14..12] Dynamic Reference Clock Mux select + of TASS controlled by M4. 0 : Clock will be + gated at dynamic mux output of TASS 1 : + ulp_32mhz_rc_byp_clk 2 : ulp_32mhz_rc_clk 3 : + rf_ref_clk 4 : mems_ref_clk 5 : + ulp_20mhz_ringosc_clk 6 : ref_byp_clk to + TASS. */ + __IOM uint32_t Reserved3 : 1; /*!< [15..15] It is recommended to write + these bits to 0. */ + __IOM uint32_t ULPSS_REF_CLK_SEL_b : 3; /*!< [18..16] Dynamic Reference Clock Mux + select of TASS controlled by M4. 0 : Clock + will be gated at dynamic mux output of + TASS 1 : ulp_32mhz_rc_byp_clk 2 : + ulp_32mhz_rc_clk 3 : rf_ref_clk 4 : + mems_ref_clk 5 : ulp_20mhz_ringosc_clk 6 + : ref_byp_clk to TASS. */ + __IOM uint32_t Reserved4 : 4; /*!< [22..19] It is recommended to write + these bits to 0. */ + __IOM uint32_t ULPSS_REF_CLK_CLEANER_OFF_b : 1; /*!< [23..23] Clock cleaner Off + signal for ulpss ref clock. */ + __IOM uint32_t ULPSS_REF_CLK_CLEANER_ON_b : 1; /*!< [24..24] Clock cleaner Off signal + for ulpss ref clock. */ + __IOM uint32_t Reserved5 : 3; /*!< [27..25] It is recommended to write + these bits to 0. */ + __IOM uint32_t SDCSS_CLK_SEL_b : 2; /*!< [29..28] select between RC / RO + 32KHz clk in sdcss 01 - 32MHz RC + Clock 10- 20MHz RO Clock. */ + __IOM uint32_t SDCSS_CLK_EN_b : 1; /*!< [30..30] To enable dynamic clock + for sdcss */ + __IOM uint32_t SDCSS_STATIC_CLK_EN_b : 1; /*!< [31..31] To enable static clk for + sensor data collector subsystem */ + } MCU_FSM_REF_CLK_REG_b; + }; + + union { + __IOM uint32_t MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP; /*!< (@ 0x00000020) MCU FSM + And First Bootup */ + + struct { + __IOM uint32_t FIRST_BOOTUP_MCU_N_b : 1; /*!< [0..0] Indication for S/W to + distinguish b/w First Power or ULP + wakeup.S/W need to set this Bit after + first power .. */ + __IM uint32_t RAM_RETENTION_STATUS_M4SS_b : 1; /*!< [1..1] Indicates to S/W that + RAM's were in retention mode + during Sleep time. 1 - RAM are in + retention mode during sleep. 0 - + RAM are not in retention mode + during sleep.Domain is OFF.. */ + __IOM uint32_t RETENTION_DOMAIN_ON_b : 1; /*!< [2..2] Indicates to S/W that Retention + domain is ON. 1 - Domain is ON. 0 - + Domain is OFF.. */ + __IOM uint32_t CHIP_MODE_VALID_b : 1; /*!< [3..3] Indicates to S/W that ChipMode + programming are valid and need not read + EFUSE. 1 - ChipMode are Valid. 0 - ChipModes + are invalid. */ + __IOM uint32_t STORAGE_DOMAIN_ON_b : 1; /*!< [4..4] Indicates to S/W that + MCU Data Storage 1 domain is + ON. 1 - Domain is ON. 0 - + Domain is OFF.. */ +#ifndef SLI_SI917B0 + __IOM uint32_t Reserved1 : 10; /*!< [14..5] It is recommended to write + these bits to 0. */ +#else + __IOM uint32_t Reserved1 : 9; /*!< [13..5] It is recommended to write + these bits to 0. */ + __IOM uint32_t MCU_ULP_1KHZ_RC_CLK_EN_b : 1; /*!< [14..14] Enables ULP 1KHz Rc Clock + (For SYSRTC and MCU WWD). */ +#endif + __IOM uint32_t MCU_FSM_RESET_N_SYNC_b : 1; /*!< [15..15] Indicated MCU FSM is out of + reset. 1 : Indicated MCU + FSM is out of reset 0 : Indicated MCU + FSM is in reset. */ + __IOM uint32_t MCU_ULP_32KHZ_RC_CLK_EN_b : 1; /*!< [16..16] Enables ULP + 32KHz Rc Clock. */ + __IOM uint32_t MCU_ULP_32KHZ_RO_CLK_EN_b : 1; /*!< [17..17] Enables ULP + 32KHz RO Clock. */ + __IOM uint32_t MCU_ULP_32KHZ_XTAL_CLK_EN_b : 1; /*!< [18..18] Enables ULP + 32KHz Xtal Clock. */ + __IOM uint32_t MCU_ULP_32MHZ_RC_CLK_EN_b : 1; /*!< [19..19] Enables ULP + 32MHz RC Clock. */ + __IOM uint32_t MCU_ULP_20MHZ_RING_OSC_CLK_EN_b : 1; /*!< [20..20] Enables ULP 20mhz + RO Clock. */ + __IOM uint32_t MCU_ULP_DOUBLER_CLK_EN_b : 1; /*!< [21..21] Enables ULP + Doubler Clock. */ + __IOM uint32_t MCU_ULP_40MHZ_CLK_EN_b : 1; /*!< [22..22] Enables 40MHz + XTAL clock. */ + __IOM uint32_t Reserved2 : 9; /*!< [31..23] It is recommended to write + these bits to 0. */ + } MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b; + }; + + union { + __IOM uint32_t MCU_FSM_CRTL_PDM_AND_ENABLES; /*!< (@ 0x00000024) Power Domains + Controlled by Sleep FSM. */ + + struct { + __IOM uint32_t ENABLE_WDT_IN_SLEEP_b : 1; /*!< [0..0] Its enable or disable WDT + during Sleep/Shutdown states. */ + __IOM uint32_t ENABLE_WURX_DETECTION_b : 1; /*!< [1..1] Its enable or disable + detection of On-Air Pattern using + Wake-Fi Rx. */ + __IOM uint32_t RESET_MCU_BBF_DM_EN_b : 1; /*!< [2..2] Its enable or disable reset of + Power Domain Control Battery FF's on + wakeup. */ + __IOM uint32_t DISABLE_TURNOFF_SRAM_PERI_b : 1; /*!< [3..3] Enable MCU SRAM periphery + during Deepsleep 1 - Enable SRAM + periphery during Deepsleep 0 - Disable + SRAM periphery during Deepsleep. */ + __IOM uint32_t ENABLE_SRAM_DS_CRTL_b : 1; /*!< [4..4] Enable signal for controlling + Deepsleep signal of all SRAM used by M4 1- + Enable SRAM Deepsleep Signal 0- Disable + SRAM Deepsleep Signal. */ + __IOM uint32_t Reserved1 : 11; /*!< [15..5] It is recommended to write + these bits to 0. */ + __IOM uint32_t POWER_ENABLE_FSM_PERI_b : 1; /*!< [16..16] Its enable or disable Power + to Low-Power FSM. */ + __IOM uint32_t POWER_ENABLE_TIMESTAMPING_b : 1; /*!< [17..17] Its enable or disable + Power to TIMESTAMP. */ + __IOM uint32_t POWER_ENABLE_DEEPSLEEP_TIMER_b : 1; /*!< [18..18] Its enable or + disable Power to DEEP SLEEP + Timer. */ + __IOM uint32_t POWER_ENABLE_RETENTION_DM_b : 1; /*!< [19..19] Its enable or disable + Power to Retention Flops during + SHIP state.These Flops + are used for storing Chip + Configuration. */ + __IOM uint32_t Reserved2 : 12; /*!< [31..20] It is recommended to write + these bits to 0. */ + } MCU_FSM_CRTL_PDM_AND_ENABLES_b; + }; + + union { + __IOM uint32_t MCU_GPIO_TIMESTAMPING_CONFIG; /*!< (@ 0x00000028) MCU GPIO + TIMESTAMPING CONFIG. */ + + struct { + __IOM uint32_t ENABLE_GPIO_TIMESTAMPING_b : 1; /*!< [0..0] Enable GPIO time stamping + Feature.. */ + __IOM uint32_t TIMESTAMPING_ON_GPIO0_b : 1; /*!< [1..1] Enable GPIO time + stamping on GPIO0. */ + __IOM uint32_t TIMESTAMPING_ON_GPIO1_b : 1; /*!< [2..2] Enable GPIO time + stamping on GPIO1. */ + __IOM uint32_t TIMESTAMPING_ON_GPIO2_b : 1; /*!< [3..3] Enable GPIO time + stamping on GPIO2. */ + __IOM uint32_t TIMESTAMPING_ON_GPIO3_b : 1; /*!< [4..4] Enable GPIO time + stamping on GPIO3. */ + __IOM uint32_t TIMESTAMPING_ON_GPIO4_b : 1; /*!< [5..5] Enable GPIO time + stamping on GPIO4. */ + __IOM uint32_t Reserved1 : 26; /*!< [31..6] It is recommended to write + these bits to 0. */ + } MCU_GPIO_TIMESTAMPING_CONFIG_b; + }; + + union { + __IM uint32_t MCU_GPIO_TIMESTAMP_READ; /*!< (@ 0x0000002C) MCU GPIO + TIMESTAMPING READ. */ + + struct { + __IM uint32_t GPIO_EVENT_COUNT_PARTIAL : 11; /*!< [10..0] Counter value indicating + the duration from GPIO going high to + first Sleep clock( MCU FSM Clock) + posedge from GPIO going high with + respect to 32MHz clock. */ + __IM uint32_t Reserved1 : 5; /*!< [15..11] It is recommended to write + these bits to 0. */ + __IM uint32_t GPIO_EVENT_COUNT_FULL : 11; /*!< [26..16] Counter value indicating + number for 32MHz clock present in 1 + Sleep clock (MCU FSM Clock). */ + __IM uint32_t Reserved2 : 5; /*!< [31..27] It is recommended to write + these bits to 0. */ + } MCU_GPIO_TIMESTAMP_READ_b; + }; + + union { + __IOM uint32_t MCU_SLEEPHOLD_REQ; /*!< (@ 0x00000030) MCU SLEEP HOLD REQ. */ + + struct { + __IOM uint32_t SLEEPHOLDREQn : 1; /*!< [0..0] Sleepholdreq when enable + will gate the clock to M4. 1 + - Sleepholdreq is Disabled. + 0 - Sleepholdreq is Enabled. */ + __IM uint32_t SLEEPHOLDACKn : 1; /*!< [1..1] SLEEPHOLDACK response to + SLEEPHOLDREQ. */ + __IOM uint32_t Reserved1 : 14; /*!< [15..2] It is recommended to write + these bits to 0. */ + __IOM uint32_t SELECT_FSM_MODE : 1; /*!< [16..16] Enable for selecting secondary FSM. + 1 - Select Secondary FSM 0 - Select Primary + FSM. */ + __IOM uint32_t Reserved2 : 15; /*!< [31..17] It is recommended to write + these bits to 0. */ + } MCU_SLEEPHOLD_REQ_b; + }; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t MCU_FSM_WAKEUP_STATUS_REG; /*!< (@ 0x00000038) MCU FSM Wakeup + Status Register. */ + + struct { + __IOM uint32_t WAKEUP_STATUS : 11; /*!< [10..0] To know the wakeup source. */ + __IOM uint32_t Reserved1 : 5; /*!< [15..11] It is recommended to write + these bits to 0. */ + __IOM uint32_t MCU_FIRST_POWERUP_POR : 1; /*!< [16..16] Indication to Processor that + system came out first power up. */ + __IOM uint32_t MCU_FIRST_POWERUP_RESET_N : 1; /*!< [17..17] Indication to Processor + that system came out of Reset. */ + __IOM uint32_t Reserve2 : 14; /*!< [31..18] It is recommended to write + these bits to 0. */ + } MCU_FSM_WAKEUP_STATUS_REG_b; + }; + + union { + __IOM uint32_t MCU_FSM_WAKEUP_STATUS_CLEAR; /*!< (@ 0x0000003C) MCU FSM + Wakeup Status Clear. */ + + struct { + __IOM uint32_t WWD_INTERRUPT_STATUS_CLEAR_b : 1; /*!< [0..0] To Clear WatchDog + Interrupt status indication. */ + __IOM uint32_t MILLI_SEC_BASED_STATUS_CLEAR_b : 1; /*!< [1..1] To Clear Milli-Second + Wakeup status indication. */ + __IOM uint32_t RTC_SEC_BASED_STATUS_CLEAR_b : 1; /*!< [2..2] To Clear Second Tick + wakeup status indication. */ + __IOM uint32_t RTC_ALARM_BASED_WAKEUP_STATUS_CLEAR_b : 1; /*!< [3..3] To Clear RTC + Alarm wakeup status + indicaition. */ + __IOM uint32_t COMP1_BASED_WAKEUP_STATUS_CLEAR_b : 1; /*!< [4..4] To Clear comp1 + wakeup (Analog IP1 and + Analog IP2) status + indication. */ + __IOM uint32_t COMP2_BASED_WAKEUP_STATUS_CLEAR_b : 1; /*!< [5..5] To Clear comp2 + wakeup (Analog IP1 and + BandGap Scale) status + indication. */ + __IOM + uint32_t COMP3_BASED_WAKEUP_STATUS_CLEAR_b : 1; /*!< [6..6] To Clear comp3 + wakeup (Analog IP1 and + VBatt Scale) status + indication. */ + __IOM + uint32_t COMP4_BASED_WAKEUP_STATUS_CLEAR_b : 1; /*!< [7..7] To Clear Comp4 + wakeup (Bandgap En and + VBatt Scale) status + indication. */ + __IOM uint32_t COMP5_BASED_WAKEUP_STATUS_CLEAR_b : 1; /*!< [8..8] To Clear BOD Wakeup + status indication. */ + __IOM uint32_t COMP6_BASED_WAKEUP_STATUS_CLEAR_b : 1; /*!< [9..9] To Clear + Button-wake status + indication. */ +#ifndef SLI_SI917B0 + __IOM uint32_t RF_WAKEUP_CLEAR_b : 1; /*!< [10..10] To Clear WuRX status + indication. */ +#else + __IOM uint32_t SYSRTC_WAKEUP_CLEAR_b : 1; /*!< [10..10] To Clear SYSRTC Wakeup status + indication. */ +#endif + __IOM uint32_t Reserved1 : 21; /*!< [31..11] It is recommended to write + these bits to 0. */ + } MCU_FSM_WAKEUP_STATUS_CLEAR_b; + }; + + union { + __IOM uint32_t MCU_FSM_PMU_STATUS_REG; /*!< (@ 0x00000040) MCU FSM PMU + Status Register. */ + + struct { + __IOM uint32_t SCDCDC_LP_MODE_EN : 1; /*!< [0..0] SCDC in LP mode. */ + __IOM uint32_t BGPMU_SLEEP_EN_R_b : 1; /*!< [1..1] Sleep en for BG PMU. */ + __IOM uint32_t Reserved1 : 15; /*!< [16..2] It is recommended to write + these bits to 0. */ + __IOM uint32_t STANDBY_LDORF_R : 1; /*!< [17..17] Standby state for LDO RF. */ + __IOM uint32_t STANDBY_LDOSOC_R : 1; /*!< [18..18] Standby state for LDO soc. */ + __IOM uint32_t STANDBY_DC1P3_R : 1; /*!< [19..19] Standby state for DC1p3. */ + __IM uint32_t POWERGOOD_LDOSOC : 1; /*!< [20..20] Powergood signal from ldosoc. */ + __IM uint32_t LEVEL_OK_DC1P3 : 1; /*!< [21..21] Powergood signal from LDORF. */ + __IM uint32_t CL_FLAG_DC1P3 : 1; /*!< [22..22] Powergood signal read for + DC 1.3V. */ + __IOM uint32_t Reserved2 : 9; /*!< [31..23] It is recommended to write + these bits to 0. */ + } MCU_FSM_PMU_STATUS_REG_b; + }; + + union { + __IOM uint32_t MCU_FSM_PMUX_CTRLS_RET; /*!< (@ 0x00000044) MCU FSM PMUX + Controls Retention. */ + + struct { + __IOM uint32_t POWER_SW_CTRL_TASS_RAM_IN_RETAIN : 1; /*!< [0..0] Select value for + TASS RAM Power Mux In + Retention mode */ + __IOM uint32_t POWER_SW_CTRL_M4SS_RAM_IN_RETAIN : 1; /*!< [1..1] Select value for + M4SS RAM Power Mux In + Retention mode */ + __IOM uint32_t POWER_SW_CTRL_M4ULP_RAM_IN_RETAIN : 2; /*!< [3..2] Select value for + M4ULP RAM Power Mux In + Retention mode */ + __IOM uint32_t POWER_SW_CTRL_M4ULP_RAM16K_IN_RETAIN : 2; /*!< [5..4] Select value for + M4ULP 16K RAM Power Mux + In Retention mode */ + __IOM uint32_t POWER_SW_CTRL_ULPSS_RAM_IN_RETAIN : 2; /*!< [7..6] Select value for + ULPSS RAM Power Mux In + Retention mode */ + __IOM uint32_t Reserved1 : 24; /*!< [31..8] It is recommended to write + these bits to 0. */ + } MCU_FSM_PMUX_CTRLS_RET_b; + }; + + union { + __IOM uint32_t MCU_FSM_TOGGLE_COUNT; /*!< (@ 0x00000048) MCU FSM Toggle Count. */ + + struct { + __OM uint32_t TOGGLE_COUNT_RSTART : 1; /*!< [0..0] Start counting GIPO Toggles. */ + __IOM uint32_t Reserved1 : 14; /*!< [14..1] It is recommended to write + these bits to 0. */ + __OM uint32_t LATCH_TOGGLE_DATA : 1; /*!< [15..15] Trigger indication to + read GPIO toggle data. */ + __IM uint32_t GPIO_TOGGLE_COUNT : 12; /*!< [27..16] GPIO toogle data count. */ + __IOM uint32_t Reserved2 : 3; /*!< [30..28] It is recommended to write + these bits to 0. */ + __IM uint32_t TOGGLE_DATA_READY : 1; /*!< [31..31] GPIO toogle data count. */ + } MCU_FSM_TOGGLE_COUNT_b; + }; +} MCU_FSM_Type; /*!< Size = 76 (0x4c) */ + +/* =========================================================================================================================== + */ +/* ================ MCU_ProcessSensor + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief The process sensor module, count the process clock (high frequency + ring clock) over one MCU FSM clock and divide this clock by programmable + value. (MCU_ProcessSensor) + */ + +typedef struct { /*!< (@ 0x24048540) MCU_ProcessSensor Structure */ + + union { + __IOM uint32_t PROCESS_SENSOR_ENABLE_AND_READ; /*!< (@ 0x00000000) Process sensor + enable and read for operation */ + + struct { + __IOM uint32_t PROCESS_SENSOR_EN : 1; /*!< [0..0] enable or on the process sensor,if + this bit is set the sensor enable else + sensor is disable. */ + __IOM uint32_t PS_RING_CLK_START : 1; /*!< [1..1] Start Ring-Oscillator clock for + estimating process corner. */ + __IOM uint32_t PS_CLK_SW_ON : 1; /*!< [2..2] Clock cleaner on signal to clock cleaner + block on clock generated by delay chain. */ + __IOM uint32_t PS_CLK_SW_OFF : 1; /*!< [3..3] Clock cleaner off signal to clock + cleaner block on clock + generated by delay chain. */ + __IOM uint32_t NUM_CYCLES : 2; /*!< [5..4] Number of MCU FSM clock(32KHz)for which + measurement need to be done.if bits is 1 then 1 + clock, 2 then 2 clocks,3 then 3 clocks,4 then 4 + clocks. */ + __IM uint32_t PS_MEAS_DONE_SYNC : 1; /*!< [6..6] Processor sensor + measurement done. */ + __IOM uint32_t RESERVED1 : 9; /*!< [15..7] Reserved1 */ + __IM uint32_t PS_COUNT : 16; /*!< [31..16] Processor sensor read back */ + } PROCESS_SENSOR_ENABLE_AND_READ_b; + }; +} MCU_ProcessSensor_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== + */ +/* ================ MCU_RET + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief NPSS has Retention domain logic which is a power domain . + This domain consisted all logic which will turned off if none of + the M4 memories are retained. (MCU_RET) + */ + +typedef struct { /*!< (@ 0x24048600) MCU_RET Structure */ + + union { + __IOM uint32_t MCURET_QSPI_WR_OP_DIS; /*!< (@ 0x00000000) MCURET QSPI WR OP DIS */ + + struct { + __IOM uint32_t M4SS_QSPI_WRSR_WR_OP_DISABLE : 1; /*!< [0..0] M4SS Write operation + disable to Flash. 1 - Write + Operation to Flash is not + allowed. 0 - Write Operation to + Flash is allowed. */ + __IM uint32_t TASS_QSPI_WRSR_WR_OP_DISABLE : 1; /*!< [1..1] TASS Write operation + disable to Flash. 1 - Write + Operation to Flash is not + allowed. 0 - Write Operation to + Flash is allowed. */ + __IOM uint32_t RESERVED1 : 30; /*!< [31..2] Reserved1 */ + } MCURET_QSPI_WR_OP_DIS_b; + }; + + union { + __IM uint32_t MCURET_BOOTSTATUS; /*!< (@ 0x00000004) MCURET BOOT Status */ + + struct { + __IM uint32_t BOOT_STATUS : 1; /*!< [0..0] Boot Status/Configuration + information to MCU */ + __IM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved1 */ + } MCURET_BOOTSTATUS_b; + }; + __IM uint32_t RESERVED; + + union { + __IM uint32_t CHIP_CONFIG_MCU_READ; /*!< (@ 0x0000000C) MCURET BOOT Status */ + + struct { + __IM uint32_t DISABLE_M4 : 1; /*!< [0..0] When set, disables the M4 by + clock gating and putting M4 in reset */ + __IM uint32_t LIMIT_M4_FREQ_110MHZ_b : 1; /*!< [1..1] When set, limits the M4SS SoC + clock to Max clock/2 */ + __IM uint32_t DISABLE_M4_ULP_MODE : 1; /*!< [2..2] When set, limits the M4SS SoC + clock to Max clock/2 */ + __IM uint32_t RESERVED1 : 7; /*!< [9..3] Reserved1 */ + __IM uint32_t M4_FLASH_SIZE : 3; /*!< [12..10] 0xx - Unrestricted 100 - Auto mode + accesses to flash are restricted to 4 MBit 101 - + Auto mode accesses to flash are restricted to 8 + MBit 110 - Auto mode accesses to flash are + restricted to 16 MBit 111 - Auto mode accesses + to flash are restricted to 32 MBit */ + __IM uint32_t DISABLE_FIM_COP : 1; /*!< [13..13] When set, disable FIMV */ + __IM uint32_t DISABLE_VAP : 1; /*!< [14..14] When set, disables VAD */ + __IM uint32_t DISABLE_TOUCH : 1; /*!< [15..15] When set, disables touch + interface */ + __IM uint32_t RESERVED2 : 1; /*!< [16..16] Reserved2 */ + __IM uint32_t DISABLE_ANALOG_PERIPH : 1; /*!< [17..17] When set, disables + analog peripherals */ + __IM uint32_t DISABLE_JTAG : 1; /*!< [18..18] When set, disable JTAG + interface(both M4 and TA) */ + __IM uint32_t DISABLE_M4SS_KH_ACCESS : 1; /*!< [19..19] When set, disables + access to key in the key + holder from M4SS QSPI */ + __IM uint32_t DISABLE_M4SS_ACCESS_FRM_TASS_SEC : 1; /*!< [20..20] When set, M4 can + not access TASS memory or + registers except for host + communication registers */ + __IM uint32_t RESERVED3 : 11; /*!< [31..21] Reserved3 */ + } CHIP_CONFIG_MCU_READ_b; + }; + + union { + __IOM uint32_t MCUAON_CTRL_REG4; /*!< (@ 0x00000010) MCURET Control Register4 */ + + struct { + __IOM uint32_t RESERVED1 : 16; /*!< [15..0] Reserved1 */ + __IOM uint32_t ULP_GPIO_2_TEST_MODE_OUT_SEL : 4; /*!< [19..16] NPSS Test modes */ + __IOM uint32_t ULP_GPIO_1_TEST_MODE_OUT_SEL : 4; /*!< [23..20] NPSS Test modes */ + __IOM uint32_t ULP_GPIO_0_TEST_MODE_OUT_SEL : 4; /*!< [27..24] NPSS Test modes */ + __IOM uint32_t ULP_GPIOS_IN_TEST_MODE : 1; /*!< [28..28] NPSS Test modes */ + __IOM uint32_t RESERVED2 : 3; /*!< [31..29] Reserved2 */ + } MCUAON_CTRL_REG4_b; + }; + __IM uint32_t RESERVED1[2]; + __IOM MCU_RET_NPSS_GPIO_CNTRL_Type NPSS_GPIO_CNTRL[5]; /*!< (@ 0x0000001C) [0..4] */ +} MCU_RET_Type; /*!< Size = 48 (0x30) */ + +/* =========================================================================================================================== + */ +/* ================ MCU_TEMP + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief The temperature sensor is used to read the temperature by using APB + registers, which is access through direct to ULPSS system. (MCU_TEMP) + */ + +typedef struct { /*!< (@ 0x24048500) MCU_TEMP Structure */ + + union { + __IOM uint32_t TS_ENABLE_AND_TEMPERATURE_DONE; /*!< (@ 0x00000000) Temperature sensor + enable and measurement calculation + done + indication register */ + + struct { + __OM uint32_t TEMP_SENS_EN : 1; /*!< [0..0] Temperature sensing + enable,self clearing register */ + __IOM uint32_t REF_CLK_SEL : 1; /*!< [1..1] if this bit is zero then reference RO + clock from analog,else this bit is one then MCU + FSM clock */ + __IOM uint32_t CONT_COUNT_FREEZE : 10; /*!< [11..2] Count of reference clock on which + ptat clock counts */ + __IM uint32_t TEMP_MEASUREMENT_DONE : 1; /*!< [12..12] temperature measurement done + indication. */ + __IOM uint32_t RESERVED1 : 19; /*!< [31..13] reserved1 */ + } TS_ENABLE_AND_TEMPERATURE_DONE_b; + }; + + union { + __IOM uint32_t TS_SLOPE_SET; /*!< (@ 0x00000004) temperature sensor slope set(slope + will be change with respect to temperature change) */ + + struct { + __IOM uint32_t SLOPE : 10; /*!< [9..0] This is one time measurement for one package + after chip arrives from fab,this is signed bit. */ + __IOM uint32_t RESERVED1 : 6; /*!< [15..10] Reserved1 */ + __IOM uint32_t TEMPERATURE_SPI : 11; /*!< [26..16] temperature known */ + __OM uint32_t TEMP_UPDATED : 1; /*!< [27..27] temperature updated signal for the reg + to capture this temperature. */ + __IOM uint32_t BJT_BASED_TEMP : 1; /*!< [28..28] Temperature is updated through which + is calculated using bjt based if bit is high(1) + through spi and bit is low(0) then through + calculation RO based */ + __IOM uint32_t RESERVED2 : 3; /*!< [31..29] Reserved2 */ + } TS_SLOPE_SET_b; + }; + + union { + __IOM uint32_t TS_FE_COUNTS_NOMINAL_SETTINGS; /*!< (@ 0x00000008) determine + calibrated temperature */ + + struct { + __IOM uint32_t F2_NOMINAL : 10; /*!< [9..0] ptat clock count during calibration,This + will vary with chip to chip. */ + __IOM uint32_t RESERVED1 : 6; /*!< [15..10] Reserved1 */ + __IOM uint32_t NOMINAL_TEMPERATURE : 7; /*!< [22..16] calibrated temperature */ + __IOM uint32_t RESERVED2 : 9; /*!< [31..23] Reserved2 */ + } TS_FE_COUNTS_NOMINAL_SETTINGS_b; + }; + + union { + __IM uint32_t TS_COUNTS_READ; /*!< (@ 0x0000000C) temperature sensor count read. */ + + struct { + __IM uint32_t COUNT_F2 : 10; /*!< [9..0] COUNT_F2 */ + __IM uint32_t RESERVED1 : 6; /*!< [15..10] Reserved1 */ + __IM uint32_t COUNT_F1 : 10; /*!< [25..16] COUNT_F1 */ + __IM uint32_t RESERVED2 : 6; /*!< [31..26] Reserved2 */ + } TS_COUNTS_READ_b; + }; + + union { + __IOM uint32_t TEMPERATURE_READ; /*!< (@ 0x00000010) read the temperature */ + + struct { + __IM uint32_t TEMPERATURE_RD : 11; /*!< [10..0] Temperature value for read + in signed format */ + __IOM uint32_t RES10 : 21; /*!< [31..11] reserved10 */ + } TEMPERATURE_READ_b; + }; +} MCU_TEMP_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== + */ +/* ================ MCU_AON + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief NPSS has always ON domain logic which is not power gatable Which + consistes of power, reset, isolation controls for different power domains in + NPSS. (MCU_AON) + */ + +typedef struct { /*!< (@ 0x24048000) MCU_AON Structure */ + + union { + __IOM uint32_t MCUAON_NPSS_PWRCTRL_SET_REG; /*!< (@ 0x00000000) This register used for + NPSS power control set register. */ + + struct { + __IOM uint32_t RES : 1; /*!< [0..0] bit is reserved */ + __IOM uint32_t SLPSS_PWRGATE_EN_N_ULP_MCUBFFS : 1; /*!< [1..1] MCU domain battery + FF's power gate enable.If + set,Power + Supply is On clearing + this bit has no effect. */ + __IOM uint32_t SLPSS_PWRGATE_EN_N_ULP_MCUFSM : 1; /*!< [2..2] MCU FSM power gate + enable,If set power supply is on + clearing + this bit has no effect. + */ + __IOM uint32_t SLPSS_PWRGATE_EN_N_ULP_MCURTC : 1; /*!< [3..3] MCU RTC power gate + enable if set,power supply is on + clearing + this bit has no effect. + */ + __IOM + uint32_t SLPSS_PWRGATE_EN_N_ULP_MCUWDT : 1; /*!< [4..4] MCU WDT power + gate enable if + set,power supply is on + clearing this bit has + no effect */ + __IOM + uint32_t SLPSS_PWRGATE_EN_N_ULP_MCUPS : 1; /*!< [5..5] MCU PS power gate + enable.if set,power supply is + on clearing this bit has no + effect. */ + __IOM uint32_t SLPSS_PWRGATE_EN_N_ULP_MCUTS : 1; /*!< [6..6] MCU temperature sensor + power gate enable if set,power + supply is on.clearing + this bit has no effect */ + __IOM uint32_t SLPSS_PWRGATE_EN_N_ULP_MCUSTORE1 : 1; /*!< [7..7] MCU Storage 1 power + gate enable for 64-bit.if + set,power supply is + on,clearing this bit has no + effect. */ + __IOM uint32_t SLPSS_PWRGATE_EN_N_ULP_MCUSTORE2 : 1; /*!< [8..8] MCU Storage 2 power + gate enable for 64-bit.if + set,power supply is + on,clearing this bit has no + effect. */ + __IOM uint32_t SLPSS_PWRGATE_EN_N_ULP_MCUSTORE3 : 1; /*!< [9..9] MCU Storage 3 power + gate enable for 64-bit.if + set,power supply is + on,clearing this bit has no + effect. */ + __IOM uint32_t SLPSS_PWRGATE_EN_N_ULP_TIMEPERIOD : 1; /*!< [10..10] TIMEPERIOD power + gate enable. */ + __IOM uint32_t RESERVED1 : 5; /*!< [15..11] reserved1 */ + __IOM uint32_t SLPSS_PWRGATE_EN_N_ULP_NWPAPB_MCU_CTRL : 1; /*!< [16..16] NWPAPB MCU + control power gate + enable */ + __IOM uint32_t RESERVED2 : 15; /*!< [31..17] reserved2 */ + } MCUAON_NPSS_PWRCTRL_SET_REG_b; + }; + + union { + __IOM uint32_t MCUAON_NPSS_PWRCTRL_CLEAR_REG; /*!< (@ 0x00000004) This register used + for NPSS power control clear + register. */ + + struct { + __IOM uint32_t RES : 1; /*!< [0..0] bit is reserved */ + __IOM uint32_t SLPSS_PWRGATE_EN_N_ULP_MCUBFFS : 1; /*!< [1..1] MCU domain battery + FF's power gate enable.If + set,Power Supply is OFF + clearing this bit has no + effect. */ + __IOM uint32_t SLPSS_PWRGATE_EN_N_ULP_MCUFSM : 1; /*!< [2..2] MCU FSM power gate + enable,If set power supply is + OFF clearing this bit has no + effect. */ + __IOM uint32_t SLPSS_PWRGATE_EN_N_ULP_MCURTC : 1; /*!< [3..3] MCU RTC power gate + enable if set,power supply is + OFF clearing this bit has no + effect. */ + __IOM uint32_t SLPSS_PWRGATE_EN_N_ULP_MCUWDT : 1; /*!< [4..4] MCU WDT power gate + enable if set,power supply is + OFF clearing this bit has no + effect */ + __IOM uint32_t SLPSS_PWRGATE_EN_N_ULP_MCUPS : 1; /*!< [5..5] MCU PS power gate + enable.if set,power supply is OFF + clearing + this bit has no effect. + */ + __IOM uint32_t SLPSS_PWRGATE_EN_N_ULP_MCUTS : 1; /*!< [6..6] MCU temperature sensor + power gate enable if set,power + supply is OFF.clearing + this bit has no effect */ + __IOM uint32_t SLPSS_PWRGATE_EN_N_ULP_MCUSTORE1 : 1; /*!< [7..7] MCU Storage 1 power + gate enable for 64-bit.if + set,power supply is + OFF,clearing this bit has no + effect. */ + __IOM uint32_t SLPSS_PWRGATE_EN_N_ULP_MCUSTORE2 : 1; /*!< [8..8] MCU Storage 2 power + gate enable for 64-bit.if + set,power supply is + OFF,clearing this bit has no + effect. */ + __IOM uint32_t SLPSS_PWRGATE_EN_N_ULP_MCUSTORE3 : 1; /*!< [9..9] MCU Storage 3 power + gate enable for 64-bit.if + set,power supply is + OFF,clearing this bit has no + effect. */ + __IOM uint32_t SLPSS_PWRGATE_EN_N_ULP_TIMEPERIOD : 1; /*!< [10..10] TIMEPERIOD power + gate enable. */ + __IOM uint32_t RESERVED1 : 5; /*!< [15..11] reserved1 */ + __IOM uint32_t SLPSS_PWRGATE_EN_N_ULP_NWPAPB_MCU_CTRL : 1; /*!< [16..16] NWPAPB MCU + control power gate + enable */ + __IOM uint32_t RESERVED2 : 15; /*!< [31..17] reserved2 */ + } MCUAON_NPSS_PWRCTRL_CLEAR_REG_b; + }; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t MCUAON_IPMU_RESET_CTRL; /*!< (@ 0x0000000C) This register used for ipmu + reset control register */ + + struct { + __IOM uint32_t ULP_ANALOG_SPI_RESET_N : 1; /*!< [0..0] ULP Analog SPI Reset Signal, + if bit is 1 then outoff reset,else in + reset */ + __IOM uint32_t IPMU_SPI_RESET_N : 1; /*!< [1..1] IPMU SPI Reset Signal,if bit is 1 + then outoff reset,else in reset */ + __IOM uint32_t RESERVED1 : 30; /*!< [31..2] reserved1 */ + } MCUAON_IPMU_RESET_CTRL_b; + }; + + union { + __IOM uint32_t MCUAON_SHELF_MODE; /*!< (@ 0x00000010) This register used for + control shelf mode. */ + + struct { + __OM uint32_t ENTER_SHELF_MODE : 16; /*!< [15..0] Program 0xAAAA for + entering shelf mode. */ + __IOM uint32_t SHUTDOWN_WAKEUP_MODE : 2; /*!< [17..16] GPIO based wakeup + mode configuration. */ + __IOM uint32_t SHELF_MODE_GPIOBASED : 1; /*!< [18..18] GPIO based shelf mode + entering,If set 1 by processor, On + Falling edge of GPIO (Based on the option + used in shutdown_wakeup_mode register) + chip will enter Shelf mode. */ + __IOM uint32_t SHELF_MODE_WAKEUP_DELAY : 3; /*!< [21..19] Programmable delay for + resetting Chip during exit phase of + shelf mode. */ + __IOM uint32_t RESERVED1 : 10; /*!< [31..22] reserved1 */ + } MCUAON_SHELF_MODE_b; + }; + + union { + __IOM uint32_t MCUAON_GEN_CTRLS; /*!< (@ 0x00000014) This register used for + MCUON gen control mode. */ + + struct { + __IOM uint32_t XTAL_CLK_FROM_GPIO : 1; /*!< [0..0] Select external 32KHz clock from + NPSS GPIO's,if bit is 1 then select XTAL + clock from GPIO Pins. Please refer to NPSS + GPIO Pin muxing for configuration.else + select XTAL clock from IPMU clock sources. + */ + __IOM uint32_t ULP_ANALOG_WAKEUP_ACCESS : 1; /*!< [1..1] ULP analog wakeup Source + Access,if bit is 1 then TASS + else bit is 0 then M4SS. */ + __IOM uint32_t RES : 14; /*!< [15..2] reser */ + __IOM uint32_t ENABLE_PDO : 1; /*!< [16..16] Enable turning Off POD power + domain when SOC_LDO EN is low,When Set + to 1, Up on SoC LDO Enable going low, IO + supply (3.3v)to SOC Pads + will be tuned-off. */ + __IOM uint32_t NPSS_SUPPLY_0P9 : 1; /*!< [17..17] keep npss supply always at 0.9V,if + bit is 1 then npss supply always at 0.9V else + bit is zero then npss supply will switch from + 0.6V to 0.9V based on high frequency + enables. */ + __IOM uint32_t RESERVED1 : 14; /*!< [31..18] reser */ + } MCUAON_GEN_CTRLS_b; + }; + + union { + __IOM uint32_t MCUAON_PDO_CTRLS; /*!< (@ 0x00000018) This register used for + MCUON PDO control mode. */ + + struct { + __IOM + uint32_t SOC_B_IO_DOMAIN_EN_B : 1; /*!< [0..0] Turn-Off IO supply of SOC + domain on bottom side,if bit is 1 + then turn-off and 0 then turn on */ + __IOM uint32_t SOC_L_IO_DOMAIN_EN_B : 1; /*!< [1..1] Turn-Off IO supply of SOC domain + on left side,if bit is 1 then turn-off + and 0 then turn on */ + __IOM uint32_t SOC_T_IO_DOMAIN_EN_B : 1; /*!< [2..2] Turn-Off IO supply of SOC domain + on top side,if bit is 1 then turn-off + and 0 then turn on */ + __IOM uint32_t QSPI_IO_DOMAIN_EN_B : 1; /*!< [3..3] Turn-Off IO supply of QSPI + domain,if bit is 1 then turn-off and 0 + then turn on */ + __IOM uint32_t SDIO_IO_DOMAIN_EN_B : 1; /*!< [4..4] Turn-Off IO supply of SDIO + domain.,if bit is 1 then turn-off and 0 + then turn on */ + __IOM uint32_t RES : 27; /*!< [31..5] reser */ + } MCUAON_PDO_CTRLS_b; + }; + + union { + __IOM uint32_t MCUAON_WDT_CHIP_RST; /*!< (@ 0x0000001C) This register used + for wdt chip reset purpose. */ + + struct { + __IOM uint32_t MCU_WDT_BASED_CHIP_RESET : 1; /*!< [0..0] When cleared, Up on host + reset request.Power-On Reset (POR) + will be generated */ + __IOM uint32_t RESERVED1 : 31; /*!< [31..1] reserved1 */ + } MCUAON_WDT_CHIP_RST_b; + }; + + union { + __IOM uint32_t MCUAON_KHZ_CLK_SEL_POR_RESET_STATUS; /*!< (@ 0x00000020) This register + used for khz clock select and + reset status */ + + struct { + __IOM uint32_t AON_KHZ_CLK_SEL : 3; /*!< [2..0] NPSS AON KHz clock selection,if 001 + Khz RO clock select,else + if 010 - Khz RC clock select,else 100 + Khz Xtal clock select */ + __IM uint32_t AON_KHZ_CLK_SEL_CLOCK_SWITCHED : 1; /*!< [3..3] If Khz clock mux + select is modified,please poll + this bit and wait till it + becomes one. */ + +#ifdef SLI_SI917B0 + __IOM uint32_t AON_KHZ_CLK_SEL_WWD : 4; /* [4 .. 7] NPSS AON KHz clock + selection for WWD */ + __IM uint32_t AON_KHZ_CLK_SEL_CLOCK_SWITCHED_WWD : 1; /*!< [8..8] If Khz clock mux + select is modified for + wwd,please poll this bit + and wait till it becomes + one. */ + __IOM uint32_t AON_KHZ_CLK_SEL_SYSRTC : 4; /* [9 .. 12] NPSS AON KHz clock + selection for SYSRTC */ + __IM uint32_t AON_KHZ_CLK_SEL_CLOCK_SWITCHED_SYSRTC : 1; /*!< [13..13] If Khz clock + mux select is modified + for sysrtc,please poll + this + bit and + wait till it becomes + one. */ + __IOM uint32_t RES : 2; /*!< [14..15] reserved */ +#else + __IOM uint32_t RES : 12; /*!< [15..4] reser */ +#endif + + __IOM uint32_t MCU_FIRST_POWERUP_POR : 1; /*!< [16..16] Program this bit to '1' upon + power_up.It will be clear when Vbatt + power is removed */ + __IOM uint32_t MCU_FIRST_POWERUP_RESET_N : 1; /*!< [17..17] Program this bit to '1' + upon power_up,It will be clear + when reset pin is pulled + low. */ +#ifdef SLI_SI917B0 + __IOM uint32_t SYSRTC_32KHZ_RC_CLK_DIV_FACTOR : 6; /* [18..23] Clock division factor + for 32Khz_rc_clk (Used in + SYSRTC and MCU WWD) */ + __IOM uint32_t RESERVED1 : 8; /*!< [24..31] reserved1 */ +#else + __IOM uint32_t RESERVED1 : 14; /*!< [31..18] reserved1 */ +#endif + } MCUAON_KHZ_CLK_SEL_POR_RESET_STATUS_b; + }; +} MCU_AON_Type; /*!< Size = 36 (0x24) */ + +/* =========================================================================================================================== + */ +/* ================ ULPCLK + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief This block provides programming support for miscellaneous blocks in + the chip. Various features in the chip are enabled using this. (ULPCLK) + */ + +typedef struct { /*!< (@ 0x24041400) ULPCLK Structure */ + + union { + __IOM uint32_t ULP_MISC_SOFT_SET_REG; /*!< (@ 0x00000000) ULP MISC soft + register set. */ + + struct { + __IOM uint32_t PCM_ENABLE_b : 1; /*!< [0..0] Used in pcm */ + __IOM uint32_t PCM_FSYNC_START_b : 1; /*!< [1..1] Used in pcm */ + __IOM uint32_t BIT_RES : 2; /*!< [3..2] Used in pcm */ + __IOM uint32_t IR_PCLK_EN_b : 1; /*!< [4..4] Static clock enable for IR + APB Interface */ + __IOM uint32_t PCLK_ENABLE_I2C_b : 1; /*!< [5..5] This bit is used as Static enable + for APB clock to I2C module,if bit is zero + then clock is disabled else bit is + one then clock is enabled. */ + __IOM uint32_t CLK_ENABLE_I2S_b : 1; /*!< [6..6] This bit is used to enable clock to + I2S module if bit is set(1)then clock is + enabled is bit is zero then clock disabled. + */ + __IOM uint32_t PCLK_ENABLE_SSI_MASTER_b : 1; /*!< [7..7] This bit is used to enable + APB bus clock to SSI master,if bit is + zero clock will be available only + when the request from the module is + present.else bit is one then clock + is enabled. */ + __IOM uint32_t SCLK_ENABLE_SSI_MASTER_b : 1; /*!< [8..8] This bit is used to enable + clock serial clock to SSI master,if + bit is zero clock will be available + only when the request from the module + is present.else bit is one + then clock is enabled. */ + __IOM uint32_t PCLK_ENABLE_UART_b : 1; /*!< [9..9] This bit is used to enable + peripheral bus clock to UART4,if bit zero + then clock will be available only when the + request from the module is present or a + transaction is pending + on the APB bus,else bit is one then + clock is enabled. */ + __IOM uint32_t SCLK_ENABLE_UART_b : 1; /*!< [10..10] This bit is used to enable + asynchronous serial clock to UART4,if bit + is zero clock will be available only when + the request from the module is + present.else bit is one then clock is + enabled. */ + __IOM uint32_t FIM_PCLK_ENABLE_b : 1; /*!< [11..11] This bit is used to enable clock + to FIM reg file,if this bit is zero then + clock will be available only when the + request from the module is present else bit + is set(1)then clock is enabled. */ + __IOM uint32_t VAD_PCLK_ENABLE_b : 1; /*!< [12..12] This bit is used to enable clock + to FIM reg file,if this bit is zero then + clock will be available only when the + request from the module is present else bit + is set(1)then clock is enabled. */ + __IOM uint32_t CLK_ENABLE_TIMER_b : 1; /*!< [13..13] This bit is used to enable clock + to Timer,if this bit is zero then clock + will be available only when the request + from the module is present else bit + is set(1)then clock is enabled. */ + __IOM uint32_t EGPIO_CLK_EN_b : 1; /*!< [14..14] This bit is used to enable clock to + gpio,if this bit is zero then clock will be + available only when the request from the module + is present else bit is set(1)then clock is + enabled. */ + __IOM uint32_t REG_ACCESS_SPI_CLK_EN_b : 1; /*!< [15..15] This bit is used to enable + clock to register access spi,if this + bit is zero then clock will be + available only when the request from + the module is present else bit is + set(1)then clock is enabled. */ + __IOM uint32_t FIM_CLK_EN_b : 1; /*!< [16..16] This bit is used to enable clock to + FIM module,if this bit is zero then clock will be + gated,else bit is one then clock is enabled. */ + __IOM uint32_t VAD_CLK_EN_b : 1; /*!< [17..17] This bit is used to enable clock to + vad module,if this bit is zero then clock will be + gated,else bit is one then clock is enabled. */ + __IOM uint32_t CLK_ENABLE_ULP_MEMORIES_b : 1; /*!< [18..18] This bit is used to + enable clock to memories,if this bit + is zero then clock will be available + only when the request from the module + is present else bit is set(1)then + clock is enabled. */ + __IOM uint32_t EGPIO_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [19..19] This bit is used to + disable dynamic clock gating on + APB clock to egpio */ + __IOM uint32_t EGPIO_PCLK_ENABLE_b : 1; /*!< [20..20] This bit is used to enable + static clock to egpio APB interface */ + __IOM uint32_t TIMER_PCLK_EN_b : 1; /*!< [21..21] This bit is used to enable static + clock to Timer APB Interface */ + __IOM uint32_t AUX_ULP_EXT_TRIG_1_SEL_b : 1; /*!< [22..22] aux adc dac controller + external trigger2 mux select, to + choose between ulp gpio aux ext + trigger2 and timer interrupt. */ + __IOM uint32_t AUX_ULP_EXT_TRIG_2_SEL_b : 1; /*!< [23..23] aux adc dac controller + external trigger2 mux select, to + choose between ulp gpio aux ext + trigger2 and timer interrupt. */ + __IOM uint32_t AUX_SOC_EXT_TRIG_1_SEL_b : 1; /*!< [24..24] aux adc dac controller + external trigger3 mux select, to + choose between soc aux ext + trigger1and soc aux ext trigger3. */ + __IOM uint32_t AUX_SOC_EXT_TRIG_2_SEL_b : 1; /*!< [25..25] aux adc dac controller + external trigger4 mux select, to + choose between soc aux ext trigger2and + soc aux ext trigger4. */ + __IOM uint32_t ULPSS_M4SS_SLV_SEL_b : 1; /*!< [26..26] select slave */ + __IOM uint32_t ULPSS_TASS_QUASI_SYNC_b : 1; /*!< [27..27] TASS quasi sync */ + __IOM uint32_t RESERVED1 : 2; /*!< [29..28] reserved1 */ + __IOM uint32_t FIM_AHB_CLK_ENABLE_b : 1; /*!< [30..30] static clock enable + for FIM AHB interface */ + __IOM uint32_t TOUCH_SENSOR_PCLK_ENABLE_b : 1; /*!< [31..31] Static clock enable for + touch APB interface */ + } ULP_MISC_SOFT_SET_REG_b; + }; + + union { + __IOM uint32_t ULP_TA_PERI_ISO_REG; /*!< (@ 0x00000004) ULP TA isolation register. */ + + struct { + __IOM uint32_t UDMA_ISO_CNTRL_b : 1; /*!< [0..0] UDMA module isolation enable,if bit + is set(1) then enable else bit is zero then + disable. */ + __IOM uint32_t IR_ISO_CNTRL_b : 1; /*!< [1..1] IR module isolation enable,if bit is + set(1) then enable else bit is zero then + disable. */ + __IOM uint32_t I2C_ISO_CNTRL_b : 1; /*!< [2..2] I2C module isolation enable,if bit is + set(1) then enable else bit is zero then + disable. */ + __IOM uint32_t I2S_ISO_CNTRL_b : 1; /*!< [3..3] I2S module isolation enable,if bit is + set(1) then enable else bit is zero then + disable. */ + __IOM uint32_t SSI_ISO_CNTRL_b : 1; /*!< [4..4] SSI module isolation enable ,if bit + is set(1) then enable else bit is zero then + disable. */ + __IOM uint32_t UART_ISO_CNTRL_b : 1; /*!< [5..5] UART module isolation enable,if bit + is set(1) then enable else bit is zero then + disable. */ + __IOM uint32_t AUX_A2D_ISO_CNTRL_b : 1; /*!< [6..6] AUX a2d module isolation + enable,if bit is set(1) then enable else + bit is zero then disable. */ + __IOM uint32_t VAD_ISO_CNTRL_b : 1; /*!< [7..7] VAD module isolation enable,if bit is + set(1) then enable else bit is zero then + disable. */ + __IOM uint32_t TOUCH_ISO_CNTRL_b : 1; /*!< [8..8] CAP sensor module isolation + enable,if bit is set(1) then + enable else bit is zero then disable. */ + __IOM uint32_t PROC_MISC_ISO_CNTRL_b : 1; /*!< [9..9] mis top(TOT, semaphore, + interrupt cntrl, Timer) module isolation + enable ,if bit is set(1) then enable + else bit is zero then disable. */ + __IOM uint32_t RESERVED0 : 1; /*!< [10..10] reserved0 */ + __IOM uint32_t RESERVED1 : 1; /*!< [11..11] reserved1 */ + __IOM uint32_t RESERVED2 : 1; /*!< [12..12] reserved2 */ + __IOM uint32_t RESERVED3 : 1; /*!< [13..13] reserved3 */ + __IOM uint32_t FIM_ISO_CNTRL_b : 1; /*!< [14..14] FIM module isolation enable ,if bit + is set(1) then enable else bit is zero then + disable. */ + __IOM uint32_t MEM_2K_1_ISO_CNTRL_b : 1; /*!< [15..15] 2k SRAM memory isolation + enable ,if bit is set(1) then + enable else bit is zero then disable. + */ + __IOM uint32_t MEM_2K_2_ISO_CNTRL_b : 1; /*!< [16..16] 2k SRAM memory isolation + enable ,if bit is set(1) then + enable else bit is zero then disable. + */ + __IOM uint32_t MEM_2K_3_ISO_CNTRL_b : 1; /*!< [17..17] 2k SRAM memory isolation + enable ,if bit is set(1) then + enable else bit is zero then disable. + */ + __IOM uint32_t MEM_2K_4_ISO_CNTRL_b : 1; /*!< [18..18] 2k SRAM memory isolation + enable ,if bit is set(1) then + enable else bit is zero then disable. + */ + __IOM uint32_t RESERVED4 : 13; /*!< [31..19] reserved4 */ + } ULP_TA_PERI_ISO_REG_b; + }; + + union { + __IOM uint32_t ULP_TA_PERI_RESET_REG; /*!< (@ 0x00000008) ULP TA peri reset + register. */ + + struct { + __IOM uint32_t UDMA_SOFT_RESET_CNTRL_b : 1; /*!< [0..0] UDMA module soft reset + enable,if bit is set(1) then out of + soft reset else bit is zero then in + reset. */ + __IOM uint32_t IR_SOFT_RESET_CNTRL_b : 1; /*!< [1..1] IR module soft reset enable,if + bit is set(1) then out of soft reset + else bit is zero then in reset. */ + __IOM uint32_t I2C_SOFT_RESET_CNTRL_b : 1; /*!< [2..2] I2C module soft reset enable + ,if bit is set(1) then out of soft + reset else bit is zero then in reset. + */ + __IOM uint32_t I2S_SOFT_RESET_CNTRL_b : 1; /*!< [3..3] I2S module soft reset enable + ,if bit is set(1) then out of soft + reset else bit is zero then in reset. + */ + __IOM uint32_t SSI_SOFT_RESET_CNTRL_b : 1; /*!< [4..4] SSI module soft reset enable + ,if bit is set(1) then out of soft + reset else bit is zero then in reset. + */ + __IOM uint32_t UART_SOFT_RESET_CNTRL_b : 1; /*!< [5..5] UART module soft reset enable + ,if bit is set(1) then out of soft + reset else bit is zero then in reset. + */ + __IOM uint32_t AUX_A2D_SOFT_RESET_CNTRL_b : 1; /*!< [6..6] AUX a2d module soft reset + enable,if bit is set(1) then out of + soft reset else bit is zero then in + reset. */ + __IOM uint32_t VAD_SOFT_RESET_CNTRL_b : 1; /*!< [7..7] VAD module soft reset + enable,if bit is set(1) then out of soft + reset else bit is zero then in reset. */ + __IOM uint32_t TOUCH_SOFT_RESET_CNTRL_b : 1; /*!< [8..8] CAP Sensor module soft reset + enable,if bit is set(1) + then out of soft reset else bit is zero + then in reset. */ + __IOM uint32_t PROC_MISC_SOFT_RESET_CNTRL_b : 1; /*!< [9..9] mis top(TOT, semaphore, + interrupt control, Timer) module + soft reset enable,if bit is + set(1) then out of soft reset + else bit is zero then in reset + */ + __IOM uint32_t COMP1_OUTPUT_CNTRL_b : 1; /*!< [10..10] This is ULP comparator1 + interrupt unmasking signal. 0 means + comparator1 interrupt is masked and 1 + means unmasking. + It is masked at power-on time. */ + __IOM uint32_t COMP2_OUTPUT_CNTRL_b : 1; /*!< [11..11] This is ULP comparator2 + interrupt unmasking signal. 0 means + comparator2 interrupt is masked and 1 + means unmasking. + It is masked at power-on time. */ + __IOM uint32_t RESERVED1 : 2; /*!< [13..12] reserved1 */ + __IOM uint32_t FIM_SOFT_RESET_CNTRL_b : 1; /*!< [14..14] FIM module soft reset + enable,if bit is set(1) then out of + soft reset else bit is zero then in + reset */ + __IOM uint32_t RESERVED2 : 17; /*!< [31..15] reserved2 */ + } ULP_TA_PERI_RESET_REG_b; + }; + __IM uint32_t RESERVED[2]; + + union { + __IOM uint32_t ULP_TA_CLK_GEN_REG; /*!< (@ 0x00000014) ULP TA clock + generation register. */ + + struct { + __IOM uint32_t ULP2M4_A2A_BRDG_CLK_EN_b : 1; /*!< [0..0] Clock enable for ULP-M4SS + AHB-AHB bridge,if bit is set(1) + then enable else bit is + zero then in disable */ + __IOM uint32_t ULP_PROC_CLK_SEL : 4; /*!< [4..1] ulp bus clock select. */ + __IOM uint32_t ULP_PROC_CLK_DIV_FACTOR : 8; /*!< [12..5] ulp bus clock + division factor */ + __IOM uint32_t RES : 19; /*!< [31..13] reserved1 */ + } ULP_TA_CLK_GEN_REG_b; + }; + + union { + __IOM uint32_t ULP_I2C_SSI_CLK_GEN_REG; /*!< (@ 0x00000018) ULP I2C SSI + clock generation register. */ + + struct { + __IOM uint32_t ULP_I2C_CLK_EN_b : 1; /*!< [0..0] ulp i2c clock enable,if bit is + set(1) then enable else bit is zero then in + disable */ + __IOM uint32_t RESERVED1 : 4; /*!< [4..1] reserved1 */ + __IOM uint32_t RESERVED2 : 8; /*!< [12..5] reserved2 */ + __IOM uint32_t RESERVED3 : 3; /*!< [15..13] reserved3 */ + __IOM uint32_t ULP_SSI_CLK_EN_b : 1; /*!< [16..16] ssi clk enable if set(1) then + enable else bit is zero then disable */ + __IOM uint32_t ULP_SSI_CLK_DIV_FACTOR : 7; /*!< [23..17] ssi clk enable if + set(1) then enable else bit + is zero then disable */ + __IOM uint32_t RESERVED4 : 4; /*!< [27..24] reserved4 */ + __IOM uint32_t ULP_SSI_CLK_SEL : 4; /*!< [31..28] Ulp ssi clock select. */ + } ULP_I2C_SSI_CLK_GEN_REG_b; + }; + + union { + __IOM uint32_t ULP_I2S_CLK_GEN_REG; /*!< (@ 0x0000001C) ULP I2S clock + generation register. */ + + struct { + __IOM uint32_t ULP_I2S_CLK_EN_b : 1; /*!< [0..0] ulp i2s clk enable,if bit is set(1) + then enable else + bit is zero then in disable */ + __IOM uint32_t ULP_I2S_CLK_SEL_b : 4; /*!< [4..1] ulp i2s clock select. */ + __IOM uint32_t ULP_I2S_CLKDIV_FACTOR : 8; /*!< [12..5] ulp i2s clock + division factor. */ + __IOM uint32_t ULP_I2S_MASTER_SLAVE_MODE_b : 1; /*!< [13..13] i2s master slave mode + decide field. */ + __IOM uint32_t ULP_I2S_SCLK_DYN_CTRL_DISABLE_b : 1; /*!< [14..14] Disable dynamic + clock gating of System clock + in I2S */ + __IOM uint32_t RESERVED1 : 1; /*!< [15..15] reserved1 */ + __IOM uint32_t ULP_I2S_LOOP_BACK_MODE_b : 1; /*!< [16..16] Enables loop + back mode in I2S. */ + __IOM uint32_t ULP_I2S_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [17..17] Disable dynamic + clock gating of APB clock in + I2S */ + __IOM uint32_t ULP_I2S_PCLK_EN_b : 1; /*!< [18..18] Static clock enable + for APB clock in I2S */ + __IOM uint32_t RESERVED2 : 13; /*!< [31..19] reserved2 */ + } ULP_I2S_CLK_GEN_REG_b; + }; + + union { + __IOM uint32_t ULP_UART_CLK_GEN_REG; /*!< (@ 0x00000020) ulp uart clock + generation register. */ + + struct { + __IOM uint32_t ULP_UART_FRAC_CLK_SEL_b : 1; /*!< [0..0] ulp uart clk selection,if bit + is set(1) then fractional divider + output is selected else swallow + divider output is selected */ + __IOM uint32_t ULP_UART_CLK_SEL : 4; /*!< [4..1] ulp uart clock select. */ + __IOM uint32_t ULP_UART_CLKDIV_FACTOR : 3; /*!< [7..5] ulp uart clock + division factor */ + __IOM uint32_t RESERVED1 : 24; /*!< [31..8] reserved1 */ + } ULP_UART_CLK_GEN_REG_b; + }; + + union { + __IOM uint32_t M4LP_CTRL_REG; /*!< (@ 0x00000024) m4 ulp control register */ + + struct { + __IOM uint32_t RESERVED0 : 2; /*!< [1..0] reserved0 */ + __IOM uint32_t ULP_M4_CORE_CLK_ENABLE_b : 1; /*!< [2..2] Static clock + enable m4 core in ULP + mode,if bit is set(1) + then clock enable else + clock is disable */ + __IOM uint32_t ULP_MEM_CLK_ULP_ENABLE_b : 1; /*!< [3..3] Static clock enable for M4 + memories in ULP mode,if bit + is set(1) then clock enable else + dynamic control */ + __IOM uint32_t ULP_MEM_CLK_ULP_DYN_CTRL_DISABLE_b : 1; /*!< [4..4] Disable the + dynamic clock gating for M4 + memories in ULP mode,if bit + is set(1) then dynamic + control disabled else + dynamic control enabled. + */ + __IOM uint32_t RESERVED1 : 27; /*!< [31..5] reserved1 */ + } M4LP_CTRL_REG_b; + }; + + union { + __IOM uint32_t CLOCK_STAUS_REG; /*!< (@ 0x00000028) read clock status register */ + + struct { + __IM uint32_t CLOCK_SWITCHED_UART_CLK_b : 1; /*!< [0..0] status of clock mux for + uart,if bit is set(1) then clock is + switched,else bit is zero then clock + not switched. */ + __IM uint32_t CLOCK_SWITCHED_I2S_CLK_b : 1; /*!< [1..1] Status of clock mux for + i2s,if bit is set(1) then clock is + switched,else bit is zero then clock + not switched. */ + __IM uint32_t CLOCK_SWITCHED_CORTEX_SLEEP_CLK_b : 1; /*!< [2..2] Status of clock mux + for m4 sleep clk,if bit is + set(1) then clock is + switched,else bit is zero + then clock not switched. */ + __IM uint32_t CLOCK_SWITCHED_PROC_CLK_b : 1; /*!< [3..3] Status of clock mux for + pclk,if bit is set(1) then clock is + switched,else bit is zero then clock + not switched. */ + __IM uint32_t CLOCK_SWITCHED_I2C_b : 1; /*!< [4..4] Status of clock mux for i2c,if + bit is set(1) then clock + is switched,else bit is zero then clock + not switched. */ + __IM uint32_t CLOCK_SWITCHED_SSI_b : 1; /*!< [5..5] Status of clock mux for ssi,if + bit is set(1) then clock + is switched,else bit is zero then clock + not switched. */ + __IM uint32_t CLOCK_SWITCHED_VAD_b : 1; /*!< [6..6] Status of clock mux for vad,if + bit is set(1) then clock + is switched,else bit is zero then clock + not switched. */ + __IM uint32_t CLOCK_SWITCHED_AUXADC_b : 1; /*!< [7..7] Status of clock mux for aux + adc dac clock,if bit is set(1) then + clock is switched,else bit is zero + then clock not switched. */ + __IM uint32_t CLOCK_SWITCHED_TIMER_b : 1; /*!< [8..8] Status of clock mux for async + timers,if bit is set(1) then clock is + switched,else bit is zero then clock + not switched. */ + __IM uint32_t CLOCK_SWITCHED_TOUCH_SENSOR_b : 1; /*!< [9..9] Status of clock mux for + touch sensor,if bit is set(1) + then clock is + switched,else bit is zero then + clock not switched. */ + __IM uint32_t CLOCK_SWITCHED_FCLK_VAD_b : 1; /*!< [10..10] Status of clock mux for + vad fast clock,if bit is set(1) then + clock is switched,else bit is zero + then clock not switched. */ + __IM uint32_t CLOCK_SWITCHED_SCLK_VAD_b : 1; /*!< [11..11] Status of clock mux for + vad slow clock,if bit is set(1) then + clock is switched,else bit is zero + then clock not switched. */ + __IM uint32_t CLOCK_SWITCHED_SYSTICK_b : 1; /*!< [12..12] Status of clock mux for + systick clock,if bit is set(1) then + clock is switched,else bit is zero + then clock not switched. */ + __IOM uint32_t RESERVED1 : 19; /*!< [31..13] reserved1 */ + } CLOCK_STAUS_REG_b; + }; + + union { + __IOM uint32_t ULP_TOUCH_CLK_GEN_REG; /*!< (@ 0x0000002C) ULP touch clock + generation register */ + + struct { + __IOM uint32_t ULP_TOUCH_CLK_EN_b : 1; /*!< [0..0] ulp touch clk enable,if bit is + set(1) then enable,else bit is zero then + disable. */ + __IOM uint32_t ULP_TOUCH_CLK_SEL : 4; /*!< [4..1] ulp touch clock select. */ + __IOM uint32_t ULP_TOUCH_CLKDIV_FACTOR : 8; /*!< [12..5] ulp touch clock + division factor. */ + __IOM uint32_t RESERVED1 : 19; /*!< [31..13] reserved1 */ + } ULP_TOUCH_CLK_GEN_REG_b; + }; + + union { + __IOM uint32_t ULP_TIMER_CLK_GEN_REG; /*!< (@ 0x00000030) ULP clock + generation for timer */ + + struct { + __IOM uint32_t RESERVED1 : 1; /*!< [0..0] reserved1 */ + __IOM uint32_t ULP_TIMER_CLK_SEL : 4; /*!< [4..1] ulp timer clock select. */ + __IOM uint32_t RESERVED2 : 8; /*!< [12..5] reserved2 */ + __IOM uint32_t ULP_TIMER_IN_SYNC_b : 1; /*!< [13..13] Ulp timer in synchronous mode + to ULPSS pclk */ + __IOM uint32_t RESERVED3 : 18; /*!< [31..14] reserved3 */ + } ULP_TIMER_CLK_GEN_REG_b; + }; + + union { + __IOM uint32_t ULP_AUXADC_CLK_GEN_REG; /*!< (@ 0x00000034) ULP AUX clock + generation register */ + + struct { + __IOM uint32_t ULP_AUX_CLK_EN_b : 1; /*!< [0..0] ulp aux clk enable,if bit is one + then clock enable else + bit is zero then clock disable. */ + __IOM uint32_t ULP_AUX_CLK_SEL : 4; /*!< [4..1] ulp aux clock select. */ + __IOM uint32_t RESERVED1 : 27; /*!< [31..5] reserved1 */ + } ULP_AUXADC_CLK_GEN_REG_b; + }; + + union { + __IOM uint32_t ULP_VAD_CLK_GEN_REG; /*!< (@ 0x00000038) ULP vad clock + generation register */ + + struct { + __IOM uint32_t ULP_VAD_CLK_EN_b : 1; /*!< [0..0] ulp vad clk enable ,if bit is one + then clock enable else + bit is zero then clock disable. */ + __IOM uint32_t ULP_VAD_CLK_SEL : 3; /*!< [3..1] ulp vad clock select. */ + __IOM uint32_t ULP_VAD_FCLK_EN : 1; /*!< [4..4] Enables Fast clock to VAD. */ + __IOM uint32_t ULP_VAD_FCLK_SEL : 4; /*!< [8..5] ulp vad Fast clock select. */ + __IOM uint32_t ULP_VAD_CLKDIV_FACTOR : 8; /*!< [16..9] ulp vad clock + division factor */ + __IOM uint32_t RESERVED1 : 15; /*!< [31..17] reserved1 */ + } ULP_VAD_CLK_GEN_REG_b; + }; + + union { + __IOM uint32_t BYPASS_I2S_CLK_REG; /*!< (@ 0x0000003C) bypass i2s clock register */ + + struct { + __IOM uint32_t BYPASS_I2S_PLL_SEL : 1; /*!< [0..0] Bypass_I2S PLL clock,if + bit is one bypass clock is used + else bit is zero then I2S + Clock is used. */ + __IOM uint32_t BYPASS_I2S_PLL_CLK_CLN_ON : 1; /*!< [1..1] I2S PLL Bypass + clock cleaner ON */ + __IOM uint32_t BYPASS_I2S_PLL_CLK_CLN_OFF : 1; /*!< [2..2] I2S PLL Bypass + clock cleaner OFF */ + __IOM uint32_t RESERVED3 : 29; /*!< [31..3] reserved3 */ + } BYPASS_I2S_CLK_REG_b; + }; + __IM uint32_t RESERVED1; + + union { + __IOM uint32_t ULP_RM_RME_REG; /*!< (@ 0x00000044) ulp rm rem register */ + + struct { + __IOM uint32_t ULP_MEM_RME_b : 1; /*!< [0..0] RM enable signal for memories internal + tp peripherals. This needs to be programmed when + the peripheral memories are not active. */ + __IOM uint32_t ULP_MEM_RM : 2; /*!< [2..1] RM ports for memories internal to + peripheral. This needs to be programmed when the + peripheral memories are not active. */ + __IM uint32_t RESERVED1 : 1; /*!< [3..3] reserved1 */ + __IOM uint32_t ULP_MEM_RME_SRAM_b : 1; /*!< [4..4] RM enable signal for + sram memories. This needs to be + programmed when the SRAM is + not active. */ + __IOM uint32_t ULP_MEM_RM_SRAM : 2; /*!< [6..5] RM ports for sram memories. This + needs to be programmed when the SRAM is not + active */ + __IOM uint32_t RESERVED2 : 25; /*!< [31..7] reserved2 */ + } ULP_RM_RME_REG_b; + }; + + union { + __IOM uint32_t ULP_CLK_ENABLE_REG; /*!< (@ 0x00000048) ulp clock enable register. */ + + struct { + __IOM uint32_t ULP_32KHZ_RO_CLK_EN_PROG_b : 1; /*!< [0..0] Static Clock enable to + iPMU for 32KHz RO Clock,if bit is + one(set) then clock enable else not + enable. */ + __IOM uint32_t ULP_32KHZ_RC_CLK_EN_PROG_b : 1; /*!< [1..1] Static Clock enable to + iPMU for 32KHz RC Clock,if bit is + one(set) then clock enable else not + enable. */ + __IOM uint32_t ULP_32KHZ_XTAL_CLK_EN_PROG_b : 1; /*!< [2..2] Static Clock enable to + iPMU for 32KHz XTAL Clock,if bit + is one(set) then clock enable else + not enable. */ + __IOM uint32_t ULP_DOUBLER_CLK_EN_PROG_b : 1; /*!< [3..3] Static Clock + enable to iPMU for Doubler + Clock,if bit is one(set) + then clock enable else not + enable. */ + __IOM uint32_t ULP_20MHZ_RO_CLK_EN_PROG_b : 1; /*!< [4..4] Static Clock enable to + iPMU for 20MHz RO clock,if bit is + one(set) then clock enable else not + enable. */ + __IOM uint32_t ULP_32MHZ_RC_CLK_EN_PROG_b : 1; /*!< [5..5] Static Clock enable to + iPMU for 32MHz RC Clock,if bit is + one(set) then clock enable else not + enable. */ + __IOM uint32_t SOC_CLK_EN_PROG_b : 1; /*!< [6..6] Static Clock enable to iPMU for + PLL-500 Clock,if bit is one(set) then clock + enable else not enable. */ + __IOM uint32_t I2S_PLLCLK_EN_PROG_b : 1; /*!< [7..7] Static clock enable + to iPMU for I2S-PLL Clock,if bit + is one(set) then clock enable + else not enable. */ + __IOM uint32_t REF_CLK_EN_IPS_PROG_b : 1; /*!< [8..8] Static Clock enable to iPMU for + REF Clock,if bit is one(set) + then clock enable else not + enable. */ + __IOM uint32_t RESERVED1 : 23; /*!< [31..9] reserved1 */ + } ULP_CLK_ENABLE_REG_b; + }; + __IM uint32_t RESERVED2; + + union { + __IOM uint32_t SYSTICK_CLK_GEN_REG; /*!< (@ 0x00000050) sys tick clock + generation register. */ + + struct { + __IOM uint32_t SYSTICK_CLK_EN_b : 1; /*!< [0..0] sys tick clock enable ,if bit is + one(set) then clock enable else not enable. + */ + __IOM uint32_t SYSTICK_CLK_SEL : 4; /*!< [4..1] sys tick clock select */ + __IOM uint32_t SYSTICK_CLKDIV_FACTOR : 8; /*!< [12..5] sys tick clock + division factor */ + __IOM uint32_t RESERVED1 : 19; /*!< [31..13] reserved1 */ + } SYSTICK_CLK_GEN_REG_b; + }; + __IM uint32_t RESERVED3[3]; + __IOM ULPCLK_ULP_SOC_GPIO_MODE_REG_Type ULP_SOC_GPIO_MODE_REG[16]; /*!< (@ 0x00000060) [0..15] */ + + union { + __IOM uint32_t ULP_DYN_CLK_CTRL_DISABLE; /*!< (@ 0x000000A0) this register used for ULP + dynamic clock control disable. */ + + struct { + __IOM uint32_t I2C_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [0..0] Dynamic clock control + disable for APB interface in i2c + module,if bit is one(set) then + dynamic control disabled + else bit is zero then Dynamic control + enabled. */ + __IOM uint32_t I2S_CLK_DYN_CTRL_DISABLE_b : 1; /*!< [1..1] Dynamic clock control + disable for i2s module,if bit is + one(set) then dynamic control + disabled else bit is zero + then Dynamic control enabled. */ + __IOM uint32_t SSI_MST_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [2..2] Dynamic clock control + disable for pclk ssi module,if + bit is one(set) then + dynamic control disabled else + bit is zero then Dynamic + control enabled. */ + __IOM uint32_t SSI_MST_SCLK_DYN_CTRL_DISABLE_b : 1; /*!< [3..3] Dynamic clock control + disable for ssi module,if bit + is one(set) then dynamic + control disabled else bit is + zero then Dynamic control + enabled. */ + __IOM uint32_t UART_CLK_DYN_CTRL_DISABLE_b : 1; /*!< [4..4] Dynamic clock control + disable for pclk uart module ,if + bit is one(set) then + dynamic control disabled else bit + is zero then Dynamic + control enabled. */ + __IOM uint32_t UART_SCLK_DYN_CTRL_DISABLE_b : 1; /*!< [5..5] Dynamic clock + control disable for uart + module,if bit is one(set) + then dynamic control + disabled else bit is zero + then Dynamic control + enabled. */ + __IOM uint32_t TIMER_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [6..6] Dynamic clock control + disable for timer pclk module,if + bit is one(set) then + dynamic control disabled else + bit + is zero then Dynamic + control enabled. */ + __IOM uint32_t TIMER_SCLK_DYN_CTRL_DISABLE_b : 1; /*!< [7..7] Dynamic clock control + disable for timer sclk module,if + bit is one(set) then + dynamic control disabled else + bit + is zero then Dynamic + control enabled. */ + __IOM uint32_t REG_ACCESS_SPI_CLK_DYN_CTRL_DISABLE_b : 1; /*!< [8..8] Dynamic clock + control disable for reg + access spi module,if bit + is one(set) then dynamic + control disabled else bit + is zero then Dynamic + control enabled. */ + __IOM uint32_t FIM_CLK_DYN_CTRL_DISABLE_b : 1; /*!< [9..9] Dynamic clock control + disable for fim module,if bit is + one(set) then dynamic control + disabled else bit is zero + then Dynamic control enabled. */ + __IOM uint32_t VAD_CLK_DYN_CTRL_DISABLE_b : 1; /*!< [10..10] Dynamic clock + control disable for vad + module,if bit is one(set) + then dynamic control + disabled else bit is zero + then Dynamic control + enabled. */ + __IOM uint32_t AUX_PCLK_EN_b : 1; /*!< [11..11] Static Enable for Aux adc pclk. */ + __IOM uint32_t AUX_CLK_EN_b : 1; /*!< [12..12] Static Enable for Aux adc clk. */ + __IOM uint32_t AUX_MEM_EN_b : 1; /*!< [13..13] Static Enable for Aux adc mem. */ + __IOM uint32_t AUX_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [14..14] Dynamic clock control + disable for aux adc module,if bit is + one(set) then dynamic control + disabled else bit + is zero then Dynamic control enabled. + */ + __IOM uint32_t AUX_CLK_DYN_CTRL_DISABLE_b : 1; /*!< [15..15] Dynamic clock control + disable for aux adc module,if bit is + one(set) then dynamic control disabled + else bit is zero then Dynamic control + enabled. */ + __IOM uint32_t AUX_CLK_MEM_DYN_CTRL_DISABLE_b : 1; /*!< [16..16] Dynamic clock + control disable for aux adc + mem,if bit is one(set) then + dynamic control disabled else + bit is zero then Dynamic + control enabled. */ + __IOM uint32_t UDMA_CLK_ENABLE_b : 1; /*!< [17..17] Static Enable for UDMA. */ + __IOM uint32_t IR_CLK_ENABLE_b : 1; /*!< [18..18] Static Enable for IR. */ + __IOM + uint32_t IR_CLK_DYN_CTRL_DISABLE_b : 1; /*!< [19..19] Dynamic clock control + disable for ir module ,if bit is + one(set) then dynamic control + disabled else bit is zero then + Dynamic control enabled. */ + __IOM uint32_t RESERVED1 : 12; /*!< [31..20] reserved1 */ + } ULP_DYN_CLK_CTRL_DISABLE_b; + }; + + union { + __IOM uint32_t SLP_SENSOR_CLK_REG; /*!< (@ 0x000000A4) this register used + for SLP sensor clock register. */ + + struct { + __IOM uint32_t DIVISON_FACTOR : 8; /*!< [7..0] Division factor for apb interface + clock to sleep sensor subsystem. */ + __IOM uint32_t ENABLE_b : 1; /*!< [8..8] Enable for APB clock to SLPSS */ + __IOM uint32_t RESERVED1 : 23; /*!< [31..9] reserved1 */ + } SLP_SENSOR_CLK_REG_b; + }; +} ULPCLK_Type; /*!< Size = 168 (0xa8) */ + +/* =========================================================================================================================== + */ +/* ================ FIM + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief FIM support fixed point Multiplications implemented through + * programmable shifting. (FIM) + */ + +typedef struct { /*!< (@ 0x24070000) FIM Structure */ + + union { + __IOM uint32_t FIM_MODE_INTERRUPT; /*!< (@ 0x00000000) Configuration for FIM Operation + Mode and Interrupt Control */ + + struct { + __IOM uint32_t LATCH_MODE : 1; /*!< [0..0] Enable latch mode */ + __IOM uint32_t OPER_MODE : 8; /*!< [8..1] Indicates the Mode of Operation + to be performed. */ + __IM uint32_t RESERVED1 : 1; /*!< [9..9] reserved1 */ + __OM uint32_t INTR_CLEAR : 1; /*!< [10..10] Writing 1 to this bit clears + the interrupt */ + __IM uint32_t RESERVED2 : 21; /*!< [31..11] reserved2 */ + } FIM_MODE_INTERRUPT_b; + }; + + union { + __IOM uint32_t FIM_INP1_ADDR; /*!< (@ 0x00000004) This register used for COP + input address for 0 register. */ + + struct { + __IOM uint32_t INP1_ADDR : 32; /*!< [31..0] Indicates the Start Address of + 1st Input Data for FIM Operations */ + } FIM_INP1_ADDR_b; + }; + + union { + __IOM uint32_t FIM_INP2_ADDR; /*!< (@ 0x00000008) This register used for COP + input address for 1 register */ + + struct { + __IOM uint32_t INP2_ADDR : 32; /*!< [31..0] Indicates the Start Address of + 2nd Input Data for FIM Operations */ + } FIM_INP2_ADDR_b; + }; + + union { + __IOM uint32_t FIM_OUT_ADDR; /*!< (@ 0x0000000C) Memory Offset Address for + Output from FIM Operations */ + + struct { + __IOM uint32_t OUT_ADDR : 32; /*!< [31..0] Indicates the Start Address of + Output Data for FIM Operations */ + } FIM_OUT_ADDR_b; + }; + + union { + __IOM uint32_t FIM_SCALAR_POLE_DATA1; /*!< (@ 0x00000010) Indicates the Input Scalar + Data for Scalar Operations indicates the + feedback coefficient for IIR Operations */ + + struct { + __IOM uint32_t SCALAR_POLE_DATA1 : 32; /*!< [31..0] Pole 0/Scalar Value */ + } FIM_SCALAR_POLE_DATA1_b; + }; + + union { + __IOM uint32_t FIM_POLE_DATA2; /*!< (@ 0x00000014) Feedback coefficient for + IIR filter operation */ + + struct { + __IOM uint32_t POLE_DATA2 : 32; /*!< [31..0] Indicates the feedback + coefficient for IIR Operations */ + } FIM_POLE_DATA2_b; + }; + + union { + __IOM uint32_t FIM_SAT_SHIFT; /*!< (@ 0x00000018) Configuration for precision of Output + Data for FIM Operations */ + + struct { + __IOM uint32_t SAT_VAL : 5; /*!< [4..0] Indicates the number of MSB's to + be saturated for Output Data */ + __IOM uint32_t TRUNCATE : 5; /*!< [9..5] Truncate */ + __IOM uint32_t SHIFT_VAL : 6; /*!< [15..10] Indicates the number of bits + to be right-shifted for Output Data */ + __IOM uint32_t ROUND : 2; /*!< [17..16] Round */ + __IOM uint32_t SAT_EN : 1; /*!< [18..18] Saturation enable bit */ + __IM uint32_t RESERVED2 : 13; /*!< [31..19] reserved2 */ + } FIM_SAT_SHIFT_b; + }; + + union { + __IOM uint32_t FIM_CONFIG_REG1; /*!< (@ 0x0000001C) Configuration Register + for FIM Operations. */ + + struct { + __IOM uint32_t MAT_LEN : 6; /*!< [5..0] Indicates the number of columns in 1st input + for Matrix Multiplication. This is same as number of + rows in 2nd input for Matrix Multiplication. */ + __IOM uint32_t INP1_LEN : 10; /*!< [15..6] Indicates the length of 1st input for FIM + Operations other than filtering (FIR, IIR) and + Interpolation */ + __IOM uint32_t INP2_LEN : 10; /*!< [25..16] Indicates the length of 2nd input for FIM + Operations other than filtering (FIR, IIR) and + Interpolation. */ + __IOM uint32_t DECIM_FAC : 6; /*!< [31..26] Decimation Factor */ + } FIM_CONFIG_REG1_b; + }; + + union { + __IOM uint32_t FIM_CONFIG_REG2; /*!< (@ 0x00000020) Configuration Register + for FIM Operations */ + + struct { + __OM uint32_t START_OPER : 1; /*!< [0..0] Start trigger for the FIM operations,this + is reset upon write register */ + __IOM uint32_t INSTR_BUFF_ENABLE : 1; /*!< [1..1] Instruction buffer enable */ + __IM uint32_t RES : 6; /*!< [7..2] reserved5 */ + __IOM uint32_t CPLX_FLAG : 2; /*!< [9..8] Complex Flag,not valid in matrix mode */ + __IOM uint32_t COL_M2 : 6; /*!< [15..10] Indicates the number of columns + in 2nd input for Matrix Multiplication */ + __IOM uint32_t ROW_M1 : 6; /*!< [21..16] Indicates the number of rows in + 1st input for Matrix Multiplication */ + __IOM uint32_t INTRP_FAC : 6; /*!< [27..22] Indicates the Interpolation Factor */ + __IM uint32_t RESERVED1 : 4; /*!< [31..28] reserved1 */ + } FIM_CONFIG_REG2_b; + }; +} FIM_Type; /*!< Size = 36 (0x24) */ + +/* =========================================================================================================================== + */ +/* ================ NWP_FSM + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief NWP FSM one register Structure (NWP_FSM) + */ + +typedef struct { /*!< (@ 0x41300110) NWP_FSM Structure */ + + union { + __IOM uint32_t TASS_REF_CLOCK_SELECT; /*!< (@ 0x00000000) TASS REF CLOCK SELECT */ + + struct { + __IOM uint32_t M4SS_REF_CLK_SEL_NWP : 3; /*!< [2..0] M4SS REF CLK SEL NWP */ + __IOM uint32_t RESERVED1 : 1; /*!< [3..3] reserved1 */ + __IOM uint32_t ULPSS_REF_CLK_SEL_NWP : 3; /*!< [6..4] ULPSS REF CLK SEL NWP */ + __IOM uint32_t RESERVED2 : 9; /*!< [15..7] reserved2 */ + __IOM uint32_t TASS_REF_CLK_SEL_NWP : 3; /*!< [18..16] TASS REF CLK SEL NWP */ + __IOM uint32_t RESERVED3 : 3; /*!< [21..19] reserved3 */ + __IOM uint32_t TASS_REF_CLK_CLEANER_OFF_NWP : 1; /*!< [22..22] TASS REF CLK CLEANER + OFF NWP */ + __IOM uint32_t TASS_REF_CLK_CLEANER_ON_NWP : 1; /*!< [23..23] TASS REF CLK + CLEANER ON NWP */ + __IOM uint32_t RESERVED4 : 8; /*!< [31..24] reserved4 */ + } TASS_REF_CLOCK_SELECT_b; + }; +} NWP_FSM_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== + */ +/* ================ OPAMP + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief The opamps top consists of 3 general purpose Operational Amplifiers + * (OPAMP) offering rail-to-rail inputs and outputs (OPAMP) + */ + +typedef struct { /*!< (@ 0x24043A14) OPAMP Structure */ + + union { + __IOM uint32_t OPAMP_1; /*!< (@ 0x00000000) Programs opamp1 */ + + struct { + __IOM uint32_t OPAMP1_ENABLE : 1; /*!< [0..0] To enable opamp 1 */ + __IOM uint32_t OPAMP1_LP_MODE : 1; /*!< [1..1] Enable or disable low power mode */ + __IOM uint32_t OPAMP1_R1_SEL : 2; /*!< [3..2] Programmability to select + resister bank R1 */ + __IOM uint32_t OPAMP1_R2_SEL : 3; /*!< [6..4] Programmability to select + resister bank R2 */ + __IOM uint32_t OPAMP1_EN_RES_BANK : 1; /*!< [7..7] enables the resistor bank 1 for + enable 0 for disable */ + __IOM uint32_t OPAMP1_RES_MUX_SEL : 3; /*!< [10..8] selecting input for + registor bank */ + __IOM uint32_t OPAMP1_RES_TO_OUT_VDD : 1; /*!< [11..11] connect resistor bank to out + or vdd i.e 0-out and 1-vdd */ + __IOM uint32_t OPAMP1_OUT_MUX_EN : 1; /*!< [12..12] out mux enable */ + __IOM uint32_t OPAMP1_INN_SEL : 3; /*!< [15..13] selecting -ve input of opamp */ + __IOM uint32_t OPAMP1_INP_SEL : 4; /*!< [19..16] selecting +ve input of opamp */ + __IOM uint32_t OPAMP1_OUT_MUX_SEL : 1; /*!< [20..20] to connect opamp1 + output to pad */ + __IOM uint32_t MEMS_RES_BANK_EN : 1; /*!< [21..21] enables mems res bank */ + __IOM uint32_t VREF_MUX_EN : 4; /*!< [25..22] vref mux enable */ + __IOM uint32_t MUX_EN : 1; /*!< [26..26] Mux Enable */ + __IOM uint32_t VREF_MUX_SEL : 4; /*!< [30..27] vref mux enable */ + __IOM uint32_t OPAMP1_DYN_EN : 1; /*!< [31..31] dynamic enable for opamp1 */ + } OPAMP_1_b; + }; + + union { + __IOM uint32_t OPAMP_2; /*!< (@ 0x00000004) Programs opamp2 */ + + struct { + __IOM uint32_t OPAMP2_ENABLE : 1; /*!< [0..0] enables the opamp2 */ + __IOM uint32_t OPAMP2_LP_MODE : 1; /*!< [1..1] select the power mode 0-normal mode + and 1-low power mode */ + __IOM uint32_t OPAMP2_R1_SEL : 2; /*!< [3..2] Programmability to select + resister bank R1 */ + __IOM uint32_t OPAMP2_R2_SEL : 3; /*!< [6..4] Programmability to select + resister bank R2 */ + __IOM uint32_t OPAMP2_EN_RES_BANK : 1; /*!< [7..7] enables the resistor bank 1 for + enable 0 for disable */ + __IOM uint32_t OPAMP2_RES_MUX_SEL : 3; /*!< [10..8] selecting input for + registor bank */ + __IOM uint32_t OPAMP2_RES_TO_OUT_VDD : 2; /*!< [12..11] connect resistor bank to out + or vdd or gnd or DAC i.e + 0-out and 1-vdd 2-DAC 3-gnd */ + __IOM uint32_t OPAMP2_OUT_MUX_EN : 1; /*!< [13..13] out mux enable */ + __IOM uint32_t OPAMP2_INN_SEL : 2; /*!< [15..14] selecting -ve input of opamp */ + __IOM uint32_t OPAMP2_INP_SEL : 3; /*!< [18..16] selecting +ve input of opamp2 */ + __IOM uint32_t OPAMP2_DYN_EN : 1; /*!< [19..19] dynamic enable for opamp2 */ + __IOM uint32_t RESERVED1 : 12; /*!< [31..20] res */ + } OPAMP_2_b; + }; + + union { + __IOM uint32_t OPAMP_3; /*!< (@ 0x00000008) Programs opamp3 */ + + struct { + __IOM uint32_t OPAMP3_ENABLE : 1; /*!< [0..0] enables the opamp3 1 for + enable 0 for disable */ + __IOM uint32_t OPAMP3_LP_MODE : 1; /*!< [1..1] select the power mode 0-normal mode + and 1-low power mode */ + __IOM uint32_t OPAMP3_R1_SEL : 2; /*!< [3..2] Programmability to select + resister bank R1 */ + __IOM uint32_t OPAMP3_R2_SEL : 3; /*!< [6..4] Programmability to select + resister bank R2 */ + __IOM uint32_t OPAMP3_EN_RES_BANK : 1; /*!< [7..7] enables the resistor bank 1 for + enable 0 for disable */ + __IOM uint32_t OPAMP3_RES_MUX_SEL : 3; /*!< [10..8] selecting input for + registor bank */ + __IOM uint32_t OPAMP3_RES_TO_OUT_VDD : 1; /*!< [11..11] connect resistor bank to out + or vdd i.e 0-out and 1-vdd */ + __IOM uint32_t OPAMP3_OUT_MUX_EN : 1; /*!< [12..12] out mux enable */ + __IOM uint32_t OPAMP3_INN_SEL : 2; /*!< [14..13] selecting -ve input of opamp */ + __IOM uint32_t OPAMP3_INP_SEL : 3; /*!< [17..15] selecting +ve input of opamp */ + __IOM uint32_t OPAMP3_DYN_EN : 1; /*!< [18..18] dynamic enable for opamp2 */ + __IOM uint32_t RESERVED1 : 13; /*!< [31..19] res */ + } OPAMP_3_b; + }; +} OPAMP_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== + */ +/* ================ AUX_ADC_DAC_COMP + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief The ADC-DAC Controller works on a ADC with a resolution of 12bits at + 5Mega sample per second when ADC reference Voltage is greater than 2.8v or + 5Mega sample per second when ADC reference Voltage is less than 2.8v. + (AUX_ADC_DAC_COMP) + */ + +typedef struct { /*!< (@ 0x24043800) AUX_ADC_DAC_COMP Structure */ + + union { + __IOM uint32_t AUXDAC_CTRL_1; /*!< (@ 0x00000000) Control register1 for DAC */ + + struct { + __IOM uint32_t ENDAC_FIFO_CONFIG : 1; /*!< [0..0] This bit activates the + DAC path in Aux ADC-DAC + controller. Data samples will be + played on DAC only when this bit + is set. */ + __IOM uint32_t DAC_STATIC_MODE : 1; /*!< [1..1] This bit is used to select + non-FIFO mode in DAC. */ + __IOM uint32_t DAC_FIFO_FLUSH : 1; /*!< [2..2] This bit is used to flush + the DAC FIFO. */ + __IOM uint32_t DAC_FIFO_THRESHOLD : 3; /*!< [5..3] These bits control the DAC FIFO + threshold. When used by DMA, this will act + as almost full threshold. For TA, it acts + as almost empty threshold */ + __IOM uint32_t DAC_ENABLE_F : 1; /*!< [6..6] This bit is used to enable + AUX DAC controller ,valid only when + DAC enable is happpen */ + __IOM uint32_t DAC_WORD_MODE : 1; /*!< [7..7] This bit is used to select + the data size valid on the APB */ + __IOM uint32_t AUX_DAC_MAC_MUX_SEL : 1; /*!< [8..8] It is recommended to + write these bits to 0 */ + + __IOM uint32_t DAC_FIFO_AEMPTY_THRESHOLD : 4; /*!< [12..9] It is recommended to write + these bits to 0 */ + + __IOM uint32_t DAC_FIFO_AFULL_THRESHOLD : 4; /*!< [16..13] It is recommended to write + these bits to 0 */ + + __IOM uint32_t RESERVED1 : 15; /*!< [31..9] Reserved1 */ + } AUXDAC_CTRL_1_b; + }; + + union { + __IOM uint32_t AUXADC_CTRL_1; /*!< (@ 0x00000004) Control register1 for ADC */ + + struct { + __IOM uint32_t ADC_ENABLE : 1; /*!< [0..0] This bits activates the ADC + path in Aux ADC-DAC controller. */ + __IOM uint32_t ADC_STATIC_MODE : 1; /*!< [1..1] This bit is used to select + non-FIFO mode in ADC. */ + __IOM uint32_t ADC_FIFO_FLUSH : 1; /*!< [2..2] This bit is used to flush + the ADC FIFO */ + __IOM uint32_t RESERVED1 : 3; /*!< [5..3] RESERVED1 */ + __IOM uint32_t ADC_MULTIPLE_CHAN_ACTIVE : 1; /*!< [6..6] This bit is used to control + the auxadc sel signal going + to the Aux ADC. */ + __IOM uint32_t ADC_CH_SEL_MSB : 2; /*!< [8..7] It is recommended to write + these bits to 0 */ + __IOM uint32_t BYPASS_NOISE_AVG : 1; /*!< [9..9] ADC in Bypass noise avg mode. */ + __IOM uint32_t EN_ADC_CLK : 1; /*!< [10..10] Enable AUX ADC Divider output clock */ + __IOM uint32_t ENDIFF : 1; /*!< [11..11] Control to the Aux ADC TODO */ + __IOM uint32_t ADC_CH_SEL_LS : 2; /*!< [13..12] Aux ADC channel number from which the + data has to be sampled This is valid only when + adc multiple channel active is zero. When + channel number is greater than three, upper bits + should also be programmed ADC CHANNEL SELECT MS + to bits in this register */ + __IOM uint32_t ADC_WORD_MODE : 1; /*!< [14..14] This bit is used to select the read + data size valid on the APB */ + __IOM uint32_t AUX_ADC_MAC_MUX_SEK : 1; /*!< [15..15] When set, AUX-ADC control is + handed over to Aux ADC-ADC controller. By + default, AUX-ADC is under the control of + baseband. */ + __IOM + uint32_t OVERRUN_DMA : 1; /*!< [16..16] overrun bit in dma mode to + enable the over-writing of buffer from + beginning when buffer is full. */ + __IOM uint32_t RESERVED2 : 4; /*!< [20..17] Reserved2 */ + __IOM uint32_t ADC_WAKE_UP_TIME : 5; /*!< [25..21] overrun bit in dma mode to enable + the over-writing of buffer from beginning + when buffer is wake up time (number + of clock cycles) , dependant upon AUX + ADC latency. */ + __IOM uint32_t EN_ADC_TRUN_OFF : 1; /*!< [26..26] Enable power save mode to turn off + AUX ADC when sampling clock is idle and enable + it before sampling event, programmed by + adc_wake_up_time */ + __IOM uint32_t ADC_NUM_PHASE : 1; /*!< [27..27] ADC number of phase */ + __IOM uint32_t RESERVED3 : 4; /*!< [31..28] Reserved3 */ + } AUXADC_CTRL_1_b; + }; + + union { + __IOM uint32_t AUXDAC_CLK_DIV_FAC; /*!< (@ 0x00000008) DAC clock division register */ + + struct { + __IOM uint32_t DAC_CLK_DIV_FAC : 10; /*!< [9..0] These bits control the + DAC clock division factor */ + __IOM uint32_t RESERVED1 : 22; /*!< [31..10] Reserved1 */ + } AUXDAC_CLK_DIV_FAC_b; + }; + + union { + __IOM uint32_t AUXADC_CLK_DIV_FAC; /*!< (@ 0x0000000C) ADC clock division register */ + + struct { + __IOM uint32_t ADC_CLK_DIV_FAC : 10; /*!< [9..0] These bits control the + Total-Duration of the ADC clock */ + __IOM uint32_t RESERVED1 : 6; /*!< [15..10] Reserved1 */ + __IOM uint32_t ADC_CLK_ON_DUR : 9; /*!< [24..16] These bits control the + On-Duration of the ADC clock */ + __IOM uint32_t RESERVED2 : 7; /*!< [31..25] Reserved2 */ + } AUXADC_CLK_DIV_FAC_b; + }; + + union { + __IOM uint32_t AUXDAC_DATA_REG; /*!< (@ 0x00000010) Writing to this register will fill + DAC FIFO for streaming Data to DAC */ + + struct { + __IOM uint32_t AUXDAC_DATA : 10; /*!< [9..0] Writing to this register will fill DAC + FIFO for streaming Data to DAC */ + __IOM uint32_t RESERVED1 : 22; /*!< [31..10] Reserved1 */ + } AUXDAC_DATA_REG_b; + }; + + union { + __IOM uint32_t AUXADC_DATA; /*!< (@ 0x00000014) AUXADC Data Read through Register. */ + + struct { + __IM uint32_t AUXADC_DATA : 12; /*!< [11..0] AUXADC Data Read through Register */ + __IM uint32_t AUXADC_CH_ID : 4; /*!< [15..12] AUXADC Channel ID */ + __IOM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved1 */ + } AUXADC_DATA_b; + }; + + union { + __IOM uint32_t ADC_DET_THR_CTRL_0; /*!< (@ 0x00000018) ADC detection + threshold control 0 */ + + struct { + __IOM uint32_t ADC_INPUT_DETECTION_THRESHOLD_0 : 8; /*!< [7..0] The value against + which the ADC output has to be + compared is to be programmed + in this register */ + __IOM uint32_t COMP_LESS_THAN_EN : 1; /*!< [8..8] When set, Aux ADC-DAC controller + raises an interrupt to processor when the + Aux ADC output falls below the programmed + Aux ADC detection threshold. */ + __IOM + uint32_t COMP_GRTR_THAN_EN : 1; /*!< [9..9] When set, Aux ADC-DAC + controller raises an interrupt to + processor when the Aux ADC output is + greater than the programmed Aux ADC + detection threshold.. */ + __IOM uint32_t COMP_EQ_EN : 1; /*!< [10..10] When set, Aux ADC-DAC controller raises + an interrupt to processor when the Aux ADC output + is equal to the programmed Aux ADC detection + threshold */ + __IOM uint32_t RANGE_COMPARISON_ENABLE : 1; /*!< [11..11] When set, Aux ADC-DAC + controller raises an interrupt to + processor when the Aux ADC output + falls within the range specified in + AUX ADC Detection threshold0 and AUX + ADC Detection threshold1 */ + __IOM uint32_t ADC_INPUT_DETECTION_THRESHOLD_1 : 4; /*!< [15..12] Carries upper four + bits of ADC detection + threshold */ + __IOM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved1 */ + } ADC_DET_THR_CTRL_0_b; + }; + + union { + __IOM uint32_t ADC_DET_THR_CTRL_1; /*!< (@ 0x0000001C) ADC detection + threshold control 1 */ + + struct { + __IOM uint32_t ADC_INPUT_DETECTION_THRESHOLD_2 : 8; /*!< [7..0] The value against + which the ADC output has to be + compared is to be programmed + in this register. */ + __IOM uint32_t COMP_LESS_THAN_EN : 1; /*!< [8..8] When set, Aux ADC-DAC controller + raises an interrupt to TA when the Aux ADC + output falls below the programmed Aux ADC + detection threshold. */ + __IOM uint32_t COMP_GRTR_THAN_EN : 1; /*!< [9..9] When set, Aux ADC-DAC controller + raises an interrupt to TA when the Aux ADC + output is greater than the programmed Aux + ADC detection threshold. */ + __IOM uint32_t COMP_EQ_EN : 1; /*!< [10..10] When set, Aux ADC-DAC controller raises + an interrupt to TA when the Aux ADC output is + equal to the programmed Aux ADC detection + threshold. */ + __IOM uint32_t ADC_DETECTION_THRESHOLD_4_UPPER_BITS : 4; /*!< [14..11] Upper 4 bits + of ADC detection + threshold 2 for ADC */ + __IOM uint32_t RESERVED1 : 17; /*!< [31..15] Reserved1 */ + } ADC_DET_THR_CTRL_1_b; + }; + + union { + __IOM uint32_t INTR_CLEAR_REG; /*!< (@ 0x00000020) ADC detection threshold + control 1 */ + + struct { + __IOM uint32_t CLR_INTR : 1; /*!< [0..0] This bit is used to clear + threshold detection interrupt */ + __IOM uint32_t RESERVED1 : 7; /*!< [7..1] Reserved1 */ + __IOM uint32_t INTR_CLEAR_REG : 16; /*!< [23..8] If enabled, corresponding + first_mem_switch_intr bits + will be cleared. */ + __IOM uint32_t RESERVED2 : 8; /*!< [31..24] Reserved2 */ + } INTR_CLEAR_REG_b; + }; + + union { + __IOM uint32_t INTR_MASK_REG; /*!< (@ 0x00000024) Mask interrupt register */ + + struct { + __IOM uint32_t THRESHOLD_DETECTION_INTR_EN : 1; /*!< [0..0] When Cleared, threshold + detection interrupt will be + unmasked */ + __IOM uint32_t DAC_FIFO_EMPTY_INTR_MASK : 1; /*!< [1..1] When Cleared, dac_FIFO_empty + interrupt will be unmasked */ + __IOM uint32_t DAC_FIFO_AEMPTY_INTR_MASK : 1; /*!< [2..2] When Cleared, adc FIFO full + interrupt will be unmasked */ + __IOM uint32_t ADC_FIFO_FULL_INTR_MASK : 1; /*!< [3..3] When Cleared, adc FIFO full + interrupt will be unmasked */ + __IOM uint32_t ADC_FIFO_AFULL_INTR_MASK : 1; /*!< [4..4] When Cleared, adc FIFO afull + interrupt will be unmasked */ + __IOM uint32_t ADC_FIFO_OVERFLOW_INTR_MASK : 1; /*!< [5..5] When Cleared, dac FIFO + underrun interrupt will be + unmasked */ + __IOM uint32_t DAC_FIFO_UNDERRUN_INTR_MASK : 1; /*!< [6..6] When Cleared, dac FIFO + underrun interrupt will be + unmasked */ + __IOM uint32_t FIRST_MEM_SWITCH_INTR_MASK : 16; /*!< [22..7] When Cleared, + first_mem_switch_intr + will be unmasked */ + __IOM uint32_t ADC_STATIC_MODE_DATA_INTR_MASK : 1; /*!< [23..23] When Cleared, adc + static_mode_data_intr will be + unmasked */ + __IOM uint32_t DAC_STATIC_MODE_DATA_INTR_MASK : 1; /*!< [24..24] When Cleared, dac + static_mode_data_intr will be + unmasked */ + __IOM uint32_t RESERVED1 : 7; /*!< [31..25] Reserved1 */ + } INTR_MASK_REG_b; + }; + + union { + __IM uint32_t INTR_STATUS_REG; /*!< (@ 0x00000028) Status interrupt register */ + + struct { + __IM uint32_t ADC_THRESHOLD_DETECTION_INTR : 1; /*!< [0..0] This bit is set when ADC + threshold matches with the + programmed conditions This will + be be cleared as soon as this + interrupt is acknowledged by + processor */ + __IM uint32_t DAC_FIFO_EMPTY : 1; /*!< [1..1] Set when DAC FIFO is empty. This bit + gets cleared when the DAC FIFO at least a + single sample is available in DAC FIFO */ + __IM uint32_t DAC_FIFO_AEMPTY : 1; /*!< [2..2] Set when the FIFO occupancy grater + than or equal to DAC FIFO threshold. */ + __IM uint32_t ADC_FIFO_FULL : 1; /*!< [3..3] Set when ADC FIFO is full,This bit gets + cleared when data is read from the FIFO */ + __IM uint32_t ADC_FIFO_AFULL : 1; /*!< [4..4] Set when ADC FIFO occupancy less than + or equal to ADC FIFO threshold */ + __IM uint32_t ADC_FIFO_OVERFLOW : 1; /*!< [5..5] Set when a write attempt is made to + ADC FIFO when the FIFO is already full */ + __IM uint32_t DAC_FIFO_UNDERRUN : 1; /*!< [6..6] Set when a read is done on DAC FIFO + when the FIFO is empty */ + __IM uint32_t FIRST_MEM_SWITCH_INTR : 16; /*!< [22..7] Interrupt + indicating the first memory + has been filled and the DMA + write is being shifted to + second memory chunk for + ping-pong operation */ + __IM uint32_t ADC_STATIC_MODE_DATA_INTR : 1; /*!< [23..23] Set when a proper data + packet is ready to read in static + mode for ADC */ + __IM uint32_t DAC_STATIC_MODE_DATA_INTR : 1; /*!< [24..24] Set when a proper data + packet is ready to read in static + mode for DAC */ + __IM uint32_t RESERVED1 : 7; /*!< [31..25] Reserved1 */ + } INTR_STATUS_REG_b; + }; + + union { + __IM uint32_t INTR_MASKED_STATUS_REG; /*!< (@ 0x0000002C) Interrupt masked + status register */ + + struct { + __IM uint32_t ADC_THRESHOLD_DETECTION_INTR_MASKED : 1; /*!< [0..0] Masked Interrupt. + This bit is set when ADC + threshold matches with + the programmed conditions + */ + __IM uint32_t DAC_FIFO_EMPTY_MASKED : 1; /*!< [1..1] Masked Interrupt.Set + when DAC FIFO is empty */ + __IM uint32_t DAC_FIFO_AEMPTY_MASKED : 1; /*!< [2..2] Masked Interrupt. Set when the + FIFO occupancy less than equal to DAC + FIFO threshold. */ + __IM uint32_t ADC_FIFO_FULL_MASKED : 1; /*!< [3..3] Masked Interrupt. Set + when ADC FIFO is full. */ + __IM uint32_t ADC_FIFO_AFULL_MASKED : 1; /*!< [4..4] Masked Interrupt. Set when ADC + FIFO occupancy greater than ADC FIFO + threshold */ + __IM uint32_t ADC_FIFO_OVERFLOW_MASKED : 1; /*!< [5..5] Masked Interrupt. Set when a + write attempt is made to ADC FIFO + when the FIFO is already full. */ + __IM uint32_t DAC_FIFO_UNDERRUN_MASKED : 1; /*!< [6..6] Masked Interrupt. Set when a + read is done on DAC FIFO when the + FIFO is empty. */ + __IM uint32_t FIRST_MEM_SWITCH_INTR_MASKED : 16; /*!< [22..7] Masked Interrupt + status indicating the first memory + has been filled and the DMA write is + being shifted to + second memory chunk for ping-pong + operation */ + __IM uint32_t ADC_STATIC_MODE_DATA_INTR_MASKED : 1; /*!< [23..23] Masked Interrupt. + Set when a proper data packet + is ready to read in static + mode for ADC */ + __IM uint32_t DAC_STATIC_MODE_DATA_INTR_MASKED : 1; /*!< [24..24] Masked Interrupt. + Set when a proper data packet + is ready to read in static + mode for DAC */ + __IM uint32_t RESERVED1 : 7; /*!< [31..25] Reserved1 */ + } INTR_MASKED_STATUS_REG_b; + }; + + union { + __IM uint32_t FIFO_STATUS_REG; /*!< (@ 0x00000030) Interrupt masked status + register */ + + struct { + __IM uint32_t DAC_FIFO_FULL : 1; /*!< [0..0] Set when DAC FIFO is full. In + word mode, FIFO will be shown as full + unless there is space for 16-bits. */ + __IM uint32_t DAC_FIFO_AFULL : 1; /*!< [1..1] Set when DAC FIFO occupancy + greater than FIFO threshold */ + __IM uint32_t ADC_FIFO_EMPTY : 1; /*!< [2..2] Set when FIFO is empty. This bit gets + cleared when the ADC FIFO is not empty. */ + __IM uint32_t ADC_FIFO_AEMPTY : 1; /*!< [3..3] Set when the FIFO occupancy + less than ADC FIFO threshold */ + __IM uint32_t DAC_FIFO_EMPTY : 1; /*!< [4..4] Set when FIFO is empty. This bit gets + cleared when the DAC FIFO is not empty. */ + __IM uint32_t DAC_FIFO_AEMPTY : 1; /*!< [5..5] Set when the FIFO occupancy + less than DAC FIFO threshold */ + __IM uint32_t ADC_FIFO_FULL : 1; /*!< [6..6] Set when ADC FIFO is full. + This bit gets cleared when data is + read from the FIFO. */ + __IM uint32_t ADC_FIFO_AFULL : 1; /*!< [7..7] Set when ADC FIFO occupancy + greater than ADC FIFO threshold. */ + __IM uint32_t RESERVED1 : 24; /*!< [31..8] Reserved1 */ + } FIFO_STATUS_REG_b; + }; + + union { + __IOM uint32_t ADC_CTRL_REG_2; /*!< (@ 0x00000034) ADC Control register2 */ + + struct { + __IOM uint32_t EXT_TRIG_DETECT_1 : 2; /*!< [1..0] Condition to detect event on + external trigger 1 00: None (trigger + disabled) 01: Positive edge 10: Negative + edge 11: Positive or negative edge. */ + __IOM uint32_t EXT_TRIG_DETECT_2 : 2; /*!< [3..2] Condition to detect event on + external trigger 2 00: None (trigger + disabled) 01: Positive edge 10: Negative + edge 11: Positive or negative edge. */ + __IOM uint32_t EXT_TRIG_DETECT_3 : 2; /*!< [5..4] Condition to detect event on + external trigger 3 00: None (trigger + disabled) 01: Positive edge 10: Negative + edge 11: Positive or negative edge. */ + __IOM uint32_t EXT_TRIG_DETECT_4 : 2; /*!< [7..6] Condition to detect event on + external trigger 4 00: None (trigger + disabled) 01: Positive edge 10: Negative + edge 11: Positive or negative edge. */ + __IOM uint32_t EXT_TRIGGER_SEL_4 : 4; /*!< [11..8] 4-bit Channel ID corresponding to + external trigger 4. */ + __IOM uint32_t EXT_TRIGGER_SEL_3 : 4; /*!< [15..12] 4-bit Channel ID corresponding to + external trigger 3. */ + __IOM uint32_t EXT_TRIGGER_SEL_2 : 4; /*!< [19..16] Enable bit corresponding to + channel id selected for trigger 2. */ + __IOM uint32_t EXT_TRIGGER_SEL_1 : 4; /*!< [23..20] 4-bit Channel ID corresponding to + external trigger 1. */ + __IOM uint32_t TRIG_1_MATCH : 1; /*!< [24..24] indicating trigger 1 is matched. Write + 1 to clear this bit. */ + __IOM uint32_t TRIG_2_MATCH : 1; /*!< [25..25] indicating trigger 2 is matched. Write + 1 to clear this bit. */ + __IOM uint32_t TRIG_3_MATCH : 1; /*!< [26..26] indicating trigger 3 is matched. Write + 1 to clear this bit. */ + __IOM uint32_t TRIG_4_MATCH : 1; /*!< [27..27] indicating trigger 4 is matched. Write + 1 to clear this bit. */ + __IOM uint32_t RESERVED1 : 4; /*!< [31..28] Reserved1 */ + } ADC_CTRL_REG_2_b; + }; + __IOM AUX_ADC_DAC_COMP_ADC_CH_BIT_MAP_CONFIG_Type ADC_CH_BIT_MAP_CONFIG[16]; /*!< (@ 0x00000038) [0..15] */ + + union { + __IOM uint32_t ADC_CH_OFFSET[16]; /*!< (@ 0x00000138) This Register specifies initial + offset value with respect to AUX_ADC clock after + which Channel(0-16)should be sampled. */ + + struct { + __IOM uint32_t CH_OFFSET : 16; /*!< [15..0] This Register field specifies initial + offset value with respect to AUX_ADC clock after + which Channel(0-16)should be sampled. */ + __IOM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved1 */ + } ADC_CH_OFFSET_b[16]; + }; + + union { + __IOM uint32_t ADC_CH_FREQ[16]; /*!< (@ 0x00000178) This register specifies Sampling + frequency rate at which AUX ADC Date is sampled for + Channel(1 to 16 ) */ + + struct { + __IOM uint32_t CH_FREQ_VALUE : 16; /*!< [15..0] This register specifies Sampling + frequency rate at which AUX ADC Date is sampled + for Channel all respective channel (1-16) */ + __IOM uint32_t RESERVED1 : 16; /*!< [31..16] Reserved1 */ + } ADC_CH_FREQ_b[16]; + }; + + union { + __IOM uint32_t ADC_CH_PHASE_1; /*!< (@ 0x000001B8) ADC Channel Phase 1 */ + + struct { + __IOM uint32_t CH1_PHASE : 4; /*!< [3..0] Phase corresponding to channel-1 */ + __IOM uint32_t CH2_PHASE : 4; /*!< [7..4] Phase corresponding to channel-2 */ + __IOM uint32_t CH3_PHASE : 4; /*!< [11..8] Phase corresponding to channel-3 */ + __IOM uint32_t CH4_PHASE : 4; /*!< [15..12] Phase corresponding to channel-4 */ + __IOM uint32_t CH5_PHASE : 4; /*!< [19..16] Phase corresponding to channel-5 */ + __IOM uint32_t CH6_PHASE : 4; /*!< [23..20] Phase corresponding to channel-6 */ + __IOM uint32_t CH7_PHASE : 4; /*!< [27..24] Phase corresponding to channel-7 */ + __IOM uint32_t CH8_PHASE : 4; /*!< [31..28] Phase corresponding to channel-8 */ + } ADC_CH_PHASE_1_b; + }; + + union { + __IOM uint32_t ADC_CH_PHASE_2; /*!< (@ 0x000001BC) ADC Channel Phase 2 */ + + struct { + __IOM uint32_t CH9_PHASE : 4; /*!< [3..0] Phase corresponding to channel-9 */ + __IOM uint32_t CH10_PHASE : 4; /*!< [7..4] Phase corresponding to channel-10 */ + __IOM uint32_t CH11_PHASE : 4; /*!< [11..8] Phase corresponding to channel-11 */ + __IOM uint32_t CH12_PHASE : 4; /*!< [15..12] Phase corresponding to channel-12 */ + __IOM uint32_t CH13_PHASE : 4; /*!< [19..16] Phase corresponding to channel-13 */ + __IOM uint32_t CH14_PHASE : 4; /*!< [23..20] Phase corresponding to channel-14 */ + __IOM uint32_t CH15_PHASE : 4; /*!< [27..24] Phase corresponding to channel-15 */ + __IOM uint32_t CH16_PHASE : 4; /*!< [31..28] Phase corresponding to channel-16 */ + } ADC_CH_PHASE_2_b; + }; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t ADC_SINGLE_CH_CTRL_1; /*!< (@ 0x000001C4) ADC SINGLE Channel + Configuration */ + + struct { + __IOM uint32_t ADC_CH_INDEX_SINGLE_CHAN_1 : 32; /*!< [31..0] [31:0]out of total 48 + bits of bit map for single channel + mode of a particular + channel. */ + } ADC_SINGLE_CH_CTRL_1_b; + }; + + union { + __IOM uint32_t ADC_SINGLE_CH_CTRL_2; /*!< (@ 0x000001C8) ADC SINGLE Channel + Configuration */ + + struct { + __IOM uint32_t ADC_CH_INDEX_SINGLE_CHAN_2 : 16; /*!< [15..0] [47:32] out of total 48 + bits of bit map for single channel + mode of a particular + channel. */ + __IOM uint32_t ADC_INTERPOL_SINGLE_CHAN : 2; /*!< [17..16] Interpolation angle for + the particular channel in single + channel mode whose bit + sequence has been written to + adc_ch_index_single_c an. */ + __IOM uint32_t RESERVED1 : 14; /*!< [31..18] Reserved1 */ + } ADC_SINGLE_CH_CTRL_2_b; + }; + + union { + __IOM uint32_t ADC_SEQ_CTRL; /*!< (@ 0x000001CC) This register explain + configuration parameter for AUXADC */ + + struct { + __IOM uint32_t ADC_SEQ_CTRL_PING_PONG : 16; /*!< [15..0] To enable/disable per + channel DAM mode (One-hot coding) */ + __IOM uint32_t ADC_SEQ_CTRL_DMA_MODE : 16; /*!< [31..16] To enable/disable per + channel ping-pong operation (One-hot + coding). */ + } ADC_SEQ_CTRL_b; + }; + + union { + __IOM uint32_t VAD_BBP_ID; /*!< (@ 0x000001D0) This register explain VDD BBP ID */ + + struct { + __IOM uint32_t BPP_ID : 4; /*!< [3..0] Channel id for bbp samples. */ + __IOM uint32_t BPP_EN : 1; /*!< [4..4] Enables Aux-ADC samples to BBP */ + __IOM uint32_t AUX_ADC_BPP_EN : 1; /*!< [5..5] Enable Indication for BBP */ + __IOM uint32_t RESERVED1 : 10; /*!< [15..6] RESERVED1 */ + __IOM uint32_t DISCONNET_MODE : 16; /*!< [31..16] Per channel discontinuous mode + enable signal. When discontinuous mode is + enabled, data is sampled only once from that + channel and the enable bit is reset to 0. */ + } VAD_BBP_ID_b; + }; + + union { + __IOM uint32_t ADC_INT_MEM_1; /*!< (@ 0x000001D4) This register explain start address + of first/second buffer corresponding to the channel + location ADC INT MEM 2 */ + + struct { + __IOM uint32_t PROG_WR_DATA : 32; /*!< [31..0] These 32-bits specifies the + start address of first/second + buffer corresponding to the + channel location ADC INT MEM */ + } ADC_INT_MEM_1_b; + }; + + union { + __IOM uint32_t ADC_INT_MEM_2; /*!< (@ 0x000001D8) This register explain ADC + INT MEM2. */ + + struct { + __IOM uint32_t PROG_WR_DATA : 10; /*!< [9..0] These 10-bits specify the buffer length + of first/second buffer corresponding to the + channel location ADC INT MEM2 */ + __IOM uint32_t PROG_WR_ADDR : 5; /*!< [14..10] These bits correspond to + the address of the internal memory + basing on the channel number, whose + information we want to program */ + __IOM uint32_t PROG_WR_DATA1 : 1; /*!< [15..15] Valid bit for first/second buffers + corresponding to ADC INT MEM2 */ + __IOM uint32_t RESERVED3 : 16; /*!< [31..16] Reserved3 */ + } ADC_INT_MEM_2_b; + }; + + union { + __IOM uint32_t INTERNAL_DMA_CH_ENABLE; /*!< (@ 0x000001DC) This register is + internal channel enable */ + + struct { + __IOM uint32_t PER_CHANNEL_ENABLE : 16; /*!< [15..0] Enable bit for Each + channel,like channel0 for bit0 + to channel15 for bit15 etc */ + __IOM uint32_t RESERVED3 : 15; /*!< [30..16] Reserved3 */ + __IOM uint32_t INTERNAL_DMA_ENABLE : 1; /*!< [31..31] When Set, Internal DMA will be + used for reading ADC + samples from ADC FIFO and writing + them to ULP SRAM Memories. */ + } INTERNAL_DMA_CH_ENABLE_b; + }; + + union { + __IOM uint32_t TS_PTAT_ENABLE; /*!< (@ 0x000001E0) This register is enable + PTAT for temperature sensor */ + + struct { + __IOM uint32_t TS_PTAT_EN : 1; /*!< [0..0] BJT based Temperature sensor */ + __IOM uint32_t RESERVED1 : 31; /*!< [31..1] Reserved1 */ + } TS_PTAT_ENABLE_b; + }; + + union { + __OM uint32_t ADC_FIFO_THRESHOLD; /*!< (@ 0x000001E4) Configured FIFO to ADC */ + + struct { + __OM uint32_t ADC_FIFO_AEMPTY_THRESHOLD : 4; /*!< [3..0] FIFO almost empty + threshold for ADC */ + __OM uint32_t ADC_FIFO_AFULL_THRESHOLD : 4; /*!< [7..4] FIFO almost full + threshold for ADC */ + __OM uint32_t RESERVED1 : 24; /*!< [31..8] Reserved1 */ + } ADC_FIFO_THRESHOLD_b; + }; + __IM uint32_t RESERVED1[6]; + + union { + __IOM uint32_t BOD; /*!< (@ 0x00000200) Programs resistor bank, reference + buffer and scaler */ + + struct { + __IOM uint32_t EN_BOD_TEST_MUX : 1; /*!< [0..0] 1 - To enable test mux */ + __IOM uint32_t BOD_TEST_SEL : 2; /*!< [2..1] Select bits for test mux */ + __IOM uint32_t REFBUF_EN : 1; /*!< [3..3] Reference buffer configuration 1 + for enable 0 for disable */ + __IOM uint32_t REFBUF_VOLT_SEL : 4; /*!< [7..4] selection of voltage of + reference buffer */ + __IOM uint32_t BOD_RES_EN : 1; /*!< [8..8] configuration of register bank + 1 for enable and 0 for disable */ + __IOM uint32_t BOD_THRSH : 5; /*!< [13..9] Programmability for resistor bank */ + __IOM uint32_t RESERVED2 : 18; /*!< [31..14] Reserved2 */ + } BOD_b; + }; + + union { + __IOM uint32_t COMPARATOR1; /*!< (@ 0x00000204) Programs comparators1 and + comparators2 */ + + struct { + __IOM uint32_t CMP1_EN : 1; /*!< [0..0] To enable comparator1 */ + __IOM uint32_t CMP1_EN_FILTER : 1; /*!< [1..1] To enable filter for comparator 1 */ + __IOM uint32_t CMP1_HYST : 2; /*!< [3..2] Programmability to control + hysteresis of comparator1 */ + __IOM uint32_t CMP1_MUX_SEL_P : 4; /*!< [7..4] Select for positive input + of comparator_1 */ + __IOM uint32_t CMP1_MUX_SEL_N : 4; /*!< [11..8] Select for negative input + of comparator_1 */ + __IOM uint32_t CMP2_EN : 1; /*!< [12..12] To enable comparator 2 */ + __IOM uint32_t CMP2_EN_FILTER : 1; /*!< [13..13] To enable filter for + comparator 2 */ + __IOM uint32_t CMP2_HYST : 2; /*!< [15..14] Programmability to control + hysteresis of comparator2 */ + __IOM uint32_t CMP2_MUX_SEL_P : 4; /*!< [19..16] Select for positive input + of comparator_2 */ + __IOM uint32_t CMP2_MUX_SEL_N : 4; /*!< [23..20] Select for negative input + of comparator_2 */ + __IOM uint32_t COM_DYN_EN : 1; /*!< [24..24] Dynamic enable for registers */ + __IOM uint32_t RESERVED1 : 7; /*!< [31..25] Reserved1 */ + } COMPARATOR1_b; + }; + + union { + __IOM uint32_t AUXADC_CONFIG_2; /*!< (@ 0x00000208) This register is AUX-ADC + config2 */ + + struct { + __IOM uint32_t AUXADC_INP_SEL : 5; /*!< [4..0] Mux select for positive + input of adc */ + __IOM uint32_t AUXADC_INN_SEL : 4; /*!< [8..5] Mux select for negetive + input of adc */ + __IOM uint32_t AUXADC_DIFF_MODE : 1; /*!< [9..9] AUX ADC Differential Mode */ + __IOM uint32_t AUXADC_ENABLE : 1; /*!< [10..10] Static Enable */ + __IOM uint32_t AUXADC_DYN_ENABLE : 1; /*!< [11..11] Aux ADC Configuration Enable */ + __IOM uint32_t RESERVED2 : 20; /*!< [31..12] Reserved2 */ + } AUXADC_CONFIG_2_b; + }; + + union { + __IOM uint32_t AUXDAC_CONIG_1; /*!< (@ 0x0000020C) This register is AUX-DAC + config1 */ + + struct { + __IOM uint32_t AUXDAC_EN_S : 1; /*!< [0..0] Enable signal DAC */ + __IOM uint32_t AUXDAC_OUT_MUX_EN : 1; /*!< [1..1] Aux OUT mux Enable */ + __IOM uint32_t AUXDAC_OUT_MUX_SEL : 1; /*!< [2..2] AUXDAC OUT MUX SELECT Enable */ + __IOM uint32_t RESERVED1 : 1; /*!< [3..3] Reserved1 */ + __IOM uint32_t AUXDAC_DATA_S : 10; /*!< [13..4] Satatic AUX Dac Data */ + __IOM uint32_t AUXDAC_DYN_EN : 1; /*!< [14..14] Satatic AUX Dac Data */ + __IOM uint32_t RESERVED2 : 17; /*!< [31..15] RESERVED2 */ + } AUXDAC_CONIG_1_b; + }; + + union { + __IOM uint32_t AUX_LDO; /*!< (@ 0x00000210) This register is AUX-LDO configuration */ + + struct { + __IOM uint32_t LDO_CTRL : 4; /*!< [3..0] Enable ldo control field */ + __IOM uint32_t LDO_DEFAULT_MODE : 1; /*!< [4..4] ldo default mode enable */ + __IOM uint32_t BYPASS_LDO : 1; /*!< [5..5] bypass the LDO */ + __IOM uint32_t ENABLE_LDO : 1; /*!< [6..6] Turn LDO */ + __IOM uint32_t DYN_EN : 1; /*!< [7..7] Dynamic Enable */ + __IOM uint32_t RESERVED1 : 24; /*!< [31..8] It is recommended to write + these bits to 0. */ + } AUX_LDO_b; + }; +} AUX_ADC_DAC_COMP_Type; /*!< Size = 532 (0x214) */ + +/* =========================================================================================================================== + */ +/* ================ IR + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief IR Decoder are used for the decoding the external ir sensor input. + * (IR) + */ + +typedef struct { /*!< (@ 0x24040C00) IR Structure */ + + union { + __IOM uint32_t IR_OFF_TIME_DURATION; /*!< (@ 0x00000000) This register used for IR + sleep duration timer value. */ + + struct { + __IOM uint32_t IR_OFF_TIME_DURATION : 17; /*!< [16..0] This field define + ir off time */ + __IM uint32_t RES : 15; /*!< [31..17] reserved5 */ + } IR_OFF_TIME_DURATION_b; + }; + + union { + __IOM uint32_t IR_ON_TIME_DURATION; /*!< (@ 0x00000004) This register used for IR + Detection duration timer value. */ + + struct { + __IOM uint32_t IR_ON_TIME_DURATION : 12; /*!< [11..0] This field define ir on time + for ir detection on */ + __IM uint32_t RES : 20; /*!< [31..12] reserved5 */ + } IR_ON_TIME_DURATION_b; + }; + + union { + __IOM uint32_t IR_FRAME_DONE_THRESHOLD; /*!< (@ 0x00000008) This register used count + with respect to 32KHz clock after not more + toggle are expected to a given pattern. */ + + struct { + __IOM uint32_t IR_FRAME_DONE_THRESHOLD : 15; /*!< [14..0] count with respect to 32KHz + clock after not more toggle are + expected to a given pattern */ + __IM uint32_t RES : 17; /*!< [31..15] reserved5 */ + } IR_FRAME_DONE_THRESHOLD_b; + }; + + union { + __IOM uint32_t IR_DET_THRESHOLD; /*!< (@ 0x0000000C) This register used Minimum Number + of edges to detected during on-time failing which + IR detection is re-stated. */ + + struct { + __IOM uint32_t IR_DET_THRESHOLD : 7; /*!< [6..0] Minimum Number of edges to detected + during on-time failing + which IR detection is re-stated. */ + __IM uint32_t RES : 25; /*!< [31..7] reserved5 */ + } IR_DET_THRESHOLD_b; + }; + + union { + __IOM uint32_t IR_CONFIG; /*!< (@ 0x00000010) This register used to configure the ir + structure for application purpose. */ + + struct { + __IOM uint32_t EN_IR_DET : 1; /*!< [0..0] Enable IR detection logic bit if bit 1 then + detection enable if 0 then not enable. */ + __IOM uint32_t IR_DET_RSTART : 1; /*!< [1..1] Enable IR detection re-start logic bit + if bit 1 then re-start. */ + __IOM uint32_t EN_CLK_IR_CORE : 1; /*!< [2..2] Enable 32KHz clock to IR Core bit ,if + bit 1 then clock gating disable and bit is 0 + then clock gating Enable */ + __IM uint32_t RES : 5; /*!< [7..3] reserved5 */ + __IOM uint32_t EN_CONT_IR_DET : 1; /*!< [8..8] This bit is Enable continues IR + detection,When enabled there will be no power + cycling on External IR Sensor. */ + __IM uint32_t RES1 : 7; /*!< [15..9] reserved6 */ + __IOM uint32_t SREST_IR_CORE : 1; /*!< [16..16] This bit is used soft + reset IR core block */ + __IM uint32_t RES2 : 15; /*!< [31..17] reserved7 */ + } IR_CONFIG_b; + }; + + union { + __IOM uint32_t IR_MEM_ADDR_ACCESS; /*!< (@ 0x00000014) This register used to access + memory address for application purpose. */ + + struct { + __IOM uint32_t IR_MEM_ADDR : 7; /*!< [6..0] This field is used to IR read + address. */ + __IOM uint32_t RES : 1; /*!< [7..7] reserved5 */ + __IOM uint32_t IR_MEM_WR_EN : 1; /*!< [8..8] IR memory write enable. */ + __IOM uint32_t IR_MEM_RD_EN : 1; /*!< [9..9] This field used to IR memory + read enable. */ + __IOM uint32_t RES1 : 6; /*!< [15..10] reserved1 */ + __IOM uint32_t IR_MEM_WR_TEST_MODE : 1; /*!< [16..16] IR memory write + enable in test mode.. */ + __IOM uint32_t RES2 : 15; /*!< [31..17] reserved2 */ + } IR_MEM_ADDR_ACCESS_b; + }; + + union { + __IM uint32_t IR_MEM_READ; /*!< (@ 0x00000018) This register used to IR Read + data from memory. */ + + struct { + __IM uint32_t IR_MEM_DATA_OUT : 16; /*!< [15..0] This field is used to IR + Read data from memory. */ + __IM uint32_t RES : 8; /*!< [23..16] reserved5 */ + __IM uint32_t IR_DATA_MEM_DEPTH : 7; /*!< [30..24] This field used to indicated + valid number of IR Address + in the memory to be read. */ + __IM uint32_t RES1 : 1; /*!< [31..31] reserved6 */ + } IR_MEM_READ_b; + }; +} IR_Type; /*!< Size = 28 (0x1c) */ + +/* =========================================================================================================================== + */ +/* ================ CTS + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief The capacitive touch sensor (CTS) controller is used to detect the + position of the touch from the user on the capacitive touch screen (CTS) + */ + +typedef struct { /*!< (@ 0x24042C00) CTS Structure */ + + union { + __IOM uint32_t CTS_CONFIG_REG_0_0; /*!< (@ 0x00000000) Configuration Register 0_0 */ + + struct { + __IOM uint32_t CLK_SEL1 : 2; /*!< [1..0] Mux select for clock_mux_1 */ + __IOM uint32_t PRE_SCALAR_1 : 8; /*!< [9..2] Division factor for clock divider */ + __IOM uint32_t PRE_SCALAR_2 : 4; /*!< [13..10] Division factor for clock divider */ + __IOM uint32_t CLK_SEL2 : 1; /*!< [14..14] Mux select for clock_mux_2 */ + __IOM uint32_t CTS_STATIC_CLK_EN : 1; /*!< [15..15] Enable static for + capacitive touch sensor */ + __IOM uint32_t FIFO_AFULL_THRLD : 6; /*!< [21..16] Threshold for fifo afull */ + __IOM uint32_t FIFO_AEMPTY_THRLD : 6; /*!< [27..22] Threshold for fifo aempty */ + __IM uint32_t FIFO_EMPTY : 1; /*!< [28..28] FIFO empty status bit */ + __IM uint32_t RESERVED1 : 3; /*!< [31..29] Reserved1 */ + } CTS_CONFIG_REG_0_0_b; + }; + + union { + __IOM uint32_t CTS_FIFO_ADDRESS; /*!< (@ 0x00000004) FIFO Address Register */ + + struct { + __IOM uint32_t FIFO : 32; /*!< [31..0] Used for FIFO reads and write operations */ + } CTS_FIFO_ADDRESS_b; + }; + __IM uint32_t RESERVED[62]; + + union { + __IOM uint32_t CTS_CONFIG_REG_1_1; /*!< (@ 0x00000100) Configuration Register 1_1 */ + + struct { + __IOM uint32_t POLYNOMIAL_LEN : 2; /*!< [1..0] Length of polynomial */ + __IOM uint32_t SEED_LOAD : 1; /*!< [2..2] Seed of polynomial */ + __IOM uint32_t BUFFER_DELAY : 5; /*!< [7..3] Delay of buffer. Delay programmed will + be equal to delay in nano seconds. Max delay + value is 32.Default delay should be programmed + before using Capacitive touch sensor module. */ + __IOM uint32_t WAKE_UP_ACK : 1; /*!< [8..8] Ack for wake up interrupt. This is a + level signal. To acknowledge wake up , set this + bit to one and reset it + . */ + __IOM uint32_t ENABLE1 : 1; /*!< [9..9] Enable signal */ + __IOM uint32_t SOFT_RESET_2 : 1; /*!< [10..10] Reset the FIFO write and + FIFO read occupancy pointers */ + __IOM uint32_t CNT_ONEHOT_MODE : 1; /*!< [11..11] Continuous or One hot mode */ + __IOM uint32_t SAMPLE_MODE : 2; /*!< [13..12] Select bits for FIFO write + and FIFO average */ + __IOM uint32_t RESET_WR_FIFO : 1; /*!< [14..14] Resets the signal fifo_wr_int */ + __OM uint32_t BYPASS : 1; /*!< [15..15] Bypass signal */ + __IOM uint32_t BIT_SEL : 2; /*!< [17..16] Selects different set of 12 bits + to be stored in FIFO */ + __IOM uint32_t EXT_TRIG_SEL : 1; /*!< [18..18] Select bit for NPSS clock + or Enable */ + __IOM uint32_t EXT_TRIG_EN : 1; /*!< [19..19] Select bit for NPSS clock or + Enable */ + __IOM uint32_t RESERVED2 : 12; /*!< [31..20] Reserved2 */ + } CTS_CONFIG_REG_1_1_b; + }; + + union { + __IOM uint32_t CTS_CONFIG_REG_1_2; /*!< (@ 0x00000104) Configuration Register 1_2 */ + + struct { + __IOM uint32_t PWM_ON_PERIOD : 16; /*!< [15..0] PWM ON period */ + __IOM uint32_t PWM_OFF_PERIOD : 16; /*!< [31..16] PWM OFF period */ + } CTS_CONFIG_REG_1_2_b; + }; + + union { + __IOM uint32_t CTS_CONFIG_REG_1_3; /*!< (@ 0x00000108) Configuration Register 1_3 */ + + struct { + __IOM uint32_t PRS_SEED : 32; /*!< [31..0] Pseudo random generator (PRS) + seed value */ + } CTS_CONFIG_REG_1_3_b; + }; + + union { + __IOM uint32_t CTS_CONFIG_REG_1_4; /*!< (@ 0x0000010C) Configuration Register 1_4 */ + + struct { + __IOM uint32_t PRS_POLY : 32; /*!< [31..0] Polynomial programming register + for PRS generator */ + } CTS_CONFIG_REG_1_4_b; + }; + + union { + __IOM uint32_t CTS_CONFIG_REG_1_5; /*!< (@ 0x00000110) Configuration Register 1_5 */ + + struct { + __IOM uint32_t INTER_SENSOR_DELAY : 16; /*!< [15..0] Inter-sensor scan + delay value */ + __IOM uint32_t N_SAMPLE_COUNT : 16; /*!< [31..16] Number of repetitions of + sensor scan */ + } CTS_CONFIG_REG_1_5_b; + }; + + union { + __IOM uint32_t CTS_CONFIG_REG_1_6; /*!< (@ 0x00000114) Configuration Register 1_6 */ + + struct { + __IOM uint32_t SENSOR_CFG : 32; /*!< [31..0] Register of scan controller + containing the programmed bit map */ + } CTS_CONFIG_REG_1_6_b; + }; + + union { + __IOM uint32_t CTS_CONFIG_REG_1_7; /*!< (@ 0x00000118) Configuration Register 1_7 */ + + struct { + __IOM uint32_t VALID_SENSORS : 4; /*!< [3..0] Value of number of sensors + valid in the bit map */ + __IOM uint32_t RESERVED1 : 2; /*!< [5..4] Reserved1 */ + __IOM uint32_t REF_VOLT_CONFIG : 9; /*!< [14..6] This is given as an input voltage to + analog model as + comparator reference voltage. */ + __IOM uint32_t WAKEUP_MODE : 1; /*!< [15..15] Select bit for high/low mode. */ + __IOM uint32_t WAKE_UP_THRESHOLD : 16; /*!< [31..16] Wakeup threshold. */ + } CTS_CONFIG_REG_1_7_b; + }; + + union { + __IM uint32_t CTS_CONFIG_REG_1_8; /*!< (@ 0x0000011C) Configuration Register 1_8 */ + + struct { + __IM uint32_t PRS_STATE : 32; /*!< [31..0] Current state of PRS */ + } CTS_CONFIG_REG_1_8_b; + }; + + union { + __IOM uint32_t CTS_CONFIG_REG_1_9; /*!< (@ 0x00000120) Configuration Register 1_9 */ + + struct { + __IOM uint32_t TRIG_DIV : 10; /*!< [9..0] Allows one pulse for every 'trig_div' no. + of pulses of 1 ms clock */ + __IOM uint32_t RESERVED1 : 22; /*!< [31..10] Reserved1 */ + } CTS_CONFIG_REG_1_9_b; + }; +} CTS_Type; /*!< Size = 292 (0x124) */ + +/* =========================================================================================================================== + */ +/* ================ MISC_CONFIG + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief MISC CONFIG Register (MISC_CONFIG) + */ + +typedef struct { /*!< (@ 0x46008000) MISC_CONFIG Structure */ + + union { + __IOM uint32_t MISC_CFG_HOST_INTR_MASK; /*!< (@ 0x00000000) MISC CFG HOST + INTR MASK */ + + struct { + __IOM uint32_t HOST_INTR_MSK : 8; /*!< [7..0] Writing 1 in any bit masks + the corresponding interrupt in + HOST_INTR_STATUS. */ + __IOM uint32_t HOST_SPI_INTR_OPEN_DRAIN_MODE : 1; /*!< [8..8] Writing 1 to this bit + configures the host SPI + interrupt in open drain mode. + When open drain mode is enabled + and interrupt is configured in + active high mode, external + PULLDOWN has to be used + on the board. */ + __IOM + uint32_t HOST_SPI_INTR_ACTIVE_LOW_MODE : 1; /*!< [9..9] Writing 1 to this + bit configures the host SPI + interrupt in active low + mode. By default, it will be + active high. */ + __IOM uint32_t RESERVED1 : 22; /*!< [31..10] reserved1 */ + } MISC_CFG_HOST_INTR_MASK_b; + }; +} MISC_CONFIG_Type; /*!< Size = 4 (0x4) */ + +#ifdef SLI_SI917B0 +/**************************************************************************/ /** + * @defgroup RSI_DEVICE_SYSRTC SYSRTC + * @{ + * @brief RSI_DEVICE SYSRTC Register Declaration. + *****************************************************************************/ + +/** SYSRTC Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP VERSION */ + __IOM uint32_t EN; /**< Module Enable Register */ + __IOM uint32_t SWRST; /**< Software Reset Register */ + __IOM uint32_t CFG; /**< Configuration Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status register */ + __IOM uint32_t CNT; /**< Counter Value Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + uint32_t RESERVED0[3U]; /**< Reserved for future use */ + __IOM uint32_t FAILDETCTRL; /**< Failure Detection */ + __IOM uint32_t FAILDETLOCK; /**< FAILDET Lock Register */ + uint32_t RESERVED1[2U]; /**< Reserved for future use */ + __IOM uint32_t GRP0_IF; /**< Group Interrupt Flags */ + __IOM uint32_t GRP0_IEN; /**< Group Interrupt Enables */ + __IOM uint32_t GRP0_CTRL; /**< Group Control Register */ + __IOM uint32_t GRP0_CMP0VALUE; /**< Compare 0 Value Register */ + __IOM uint32_t GRP0_CMP1VALUE; /**< Compare 1 Value Register */ + __IM uint32_t GRP0_CAP0VALUE; /**< Capture 0 Value Register */ + __IM uint32_t GRP0_SYNCBUSY; /**< Synchronization busy Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IOM uint32_t GRP1_IF; /**< Group Interrupt Flags */ + __IOM uint32_t GRP1_IEN; /**< Group Interrupt Enables */ + __IOM uint32_t GRP1_CTRL; /**< Group Control Register */ + __IOM uint32_t GRP1_CMP0VALUE; /**< Compare 0 Value Register */ + __IOM uint32_t GRP1_CMP1VALUE; /**< Compare 1 Value Register */ + __IM uint32_t GRP1_CAP0VALUE; /**< Capture 0 Value Register */ + __IM uint32_t GRP1_SYNCBUSY; /**< Synchronization busy Register */ + uint32_t RESERVED3[33U]; /**< GRP2 - GRP7,Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP VERSION */ + __IOM uint32_t EN_SET; /**< Module Enable Register */ + __IOM uint32_t SWRST_SET; /**< Software Reset Register */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATUS_SET; /**< Status register */ + __IOM uint32_t CNT_SET; /**< Counter Value Register */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + uint32_t RESERVED4[3U]; /**< Reserved for future use */ + __IOM uint32_t FAILDETCTRL_SET; /**< Failure Detection */ + __IOM uint32_t FAILDETLOCK_SET; /**< FAILDET Lock Register */ + uint32_t RESERVED5[2U]; /**< Reserved for future use */ + __IOM uint32_t GRP0_IF_SET; /**< Group Interrupt Flags */ + __IOM uint32_t GRP0_IEN_SET; /**< Group Interrupt Enables */ + __IOM uint32_t GRP0_CTRL_SET; /**< Group Control Register */ + __IOM uint32_t GRP0_CMP0VALUE_SET; /**< Compare 0 Value Register */ + __IOM uint32_t GRP0_CMP1VALUE_SET; /**< Compare 1 Value Register */ + __IM uint32_t GRP0_CAP0VALUE_SET; /**< Capture 0 Value Register */ + __IM uint32_t GRP0_SYNCBUSY_SET; /**< Synchronization busy Register */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IOM uint32_t GRP1_IF_SET; /**< Group Interrupt Flags */ + __IOM uint32_t GRP1_IEN_SET; /**< Group Interrupt Enables */ + __IOM uint32_t GRP1_CTRL_SET; /**< Group Control Register */ + __IOM uint32_t GRP1_CMP0VALUE_SET; /**< Compare 0 Value Register */ + __IOM uint32_t GRP1_CMP1VALUE_SET; /**< Compare 1 Value Register */ + __IM uint32_t GRP1_CAP0VALUE_SET; /**< Capture 0 Value Register */ + __IM uint32_t GRP1_SYNCBUSY_SET; /**< Synchronization busy Register */ + uint32_t RESERVED7[33U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP VERSION */ + __IOM uint32_t EN_CLR; /**< Module Enable Register */ + __IOM uint32_t SWRST_CLR; /**< Software Reset Register */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATUS_CLR; /**< Status register */ + __IOM uint32_t CNT_CLR; /**< Counter Value Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + uint32_t RESERVED8[3U]; /**< Reserved for future use */ + __IOM uint32_t FAILDETCTRL_CLR; /**< Failure Detection */ + __IOM uint32_t FAILDETLOCK_CLR; /**< FAILDET Lock Register */ + uint32_t RESERVED9[2U]; /**< Reserved for future use */ + __IOM uint32_t GRP0_IF_CLR; /**< Group Interrupt Flags */ + __IOM uint32_t GRP0_IEN_CLR; /**< Group Interrupt Enables */ + __IOM uint32_t GRP0_CTRL_CLR; /**< Group Control Register */ + __IOM uint32_t GRP0_CMP0VALUE_CLR; /**< Compare 0 Value Register */ + __IOM uint32_t GRP0_CMP1VALUE_CLR; /**< Compare 1 Value Register */ + __IM uint32_t GRP0_CAP0VALUE_CLR; /**< Capture 0 Value Register */ + __IM uint32_t GRP0_SYNCBUSY_CLR; /**< Synchronization busy Register */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ + __IOM uint32_t GRP1_IF_CLR; /**< Group Interrupt Flags */ + __IOM uint32_t GRP1_IEN_CLR; /**< Group Interrupt Enables */ + __IOM uint32_t GRP1_CTRL_CLR; /**< Group Control Register */ + __IOM uint32_t GRP1_CMP0VALUE_CLR; /**< Compare 0 Value Register */ + __IOM uint32_t GRP1_CMP1VALUE_CLR; /**< Compare 1 Value Register */ + __IM uint32_t GRP1_CAP0VALUE_CLR; /**< Capture 0 Value Register */ + __IM uint32_t GRP1_SYNCBUSY_CLR; /**< Synchronization busy Register */ + uint32_t RESERVED11[33U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP VERSION */ + __IOM uint32_t EN_TGL; /**< Module Enable Register */ + __IOM uint32_t SWRST_TGL; /**< Software Reset Register */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATUS_TGL; /**< Status register */ + __IOM uint32_t CNT_TGL; /**< Counter Value Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ + uint32_t RESERVED12[3U]; /**< Reserved for future use */ + __IOM uint32_t FAILDETCTRL_TGL; /**< Failure Detection */ + __IOM uint32_t FAILDETLOCK_TGL; /**< FAILDET Lock Register */ + uint32_t RESERVED13[2U]; /**< Reserved for future use */ + __IOM uint32_t GRP0_IF_TGL; /**< Group Interrupt Flags */ + __IOM uint32_t GRP0_IEN_TGL; /**< Group Interrupt Enables */ + __IOM uint32_t GRP0_CTRL_TGL; /**< Group Control Register */ + __IOM uint32_t GRP0_CMP0VALUE_TGL; /**< Compare 0 Value Register */ + __IOM uint32_t GRP0_CMP1VALUE_TGL; /**< Compare 1 Value Register */ + __IM uint32_t GRP0_CAP0VALUE_TGL; /**< Capture 0 Value Register */ + __IM uint32_t GRP0_SYNCBUSY_TGL; /**< Synchronization busy Register */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + __IOM uint32_t GRP1_IF_TGL; /**< Group Interrupt Flags */ + __IOM uint32_t GRP1_IEN_TGL; /**< Group Interrupt Enables */ + __IOM uint32_t GRP1_CTRL_TGL; /**< Group Control Register */ + __IOM uint32_t GRP1_CMP0VALUE_TGL; /**< Compare 0 Value Register */ + __IOM uint32_t GRP1_CMP1VALUE_TGL; /**< Compare 1 Value Register */ + __IM uint32_t GRP1_CAP0VALUE_TGL; /**< Capture 0 Value Register */ + __IM uint32_t GRP1_SYNCBUSY_TGL; /**< Synchronization busy Register */ + uint32_t RESERVED15[32U]; /**< Reserved for future use */ + __IOM uint32_t MCUSYSRTC_REG1; /**< input and output configuration */ + +} SYSRTC_TypeDef; + +/* =========================================================================================================================== */ +/* ================ SDC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SDC_SDC_DATA_REG [SDC_DATA_REG] (SDC Data registers (0-15)) + */ +typedef struct { + union { + __IM uint32_t DATA_REG; /*!< (@ 0x00000000) SDC Data register */ + + struct { + __IM uint32_t + SDC_DATA_SAMPLE : 12; /*!< [11..0] Sample 0 collected from Sensor through Aux ADC. */ + __IM uint32_t SMP_ID_CH : 2; /*!< [13..12] Channel iD for sample */ + __IM uint32_t RESERVED1 : 18; /*!< [31..14] reserved1 */ + } DATA_REG_b; + }; +} SDC_SDC_DATA_REG_Type; + +/** + * @brief Sensor Data Collector Register structure (SDC) + */ + +typedef struct { /*!< (@ 0x24042400) SDC Structure */ + + union { + __IOM uint32_t SDC_GEN_CONFIG_0; /*!< (@ 0x00000000) SDC general configuration 0 */ + + struct { + __IOM uint32_t INTR_STATUS_CLEAR : 1; /*!< [0..0] Writing 1 clears interrupt, reading gives SDC Interrupt + status */ + __IOM uint32_t RESERVED1 : 31; /*!< [31..1] Reserevd */ + } SDC_GEN_CONFIG_0_b; + }; + + union { + __IOM uint32_t SDC_GEN_CONFIG_1; /*!< (@ 0x00000004) SDC general configuration 1 */ + + struct { + __IOM uint32_t RST_WRT_PTR : 1; /*!< [0..0] Writing 1 will resets the write pointer so that new samples + can be filled in Buffer. */ + __IM uint32_t WRT_PTR : 4; /*!< [4..1] Write pointer Value */ + __IOM uint32_t SAMP_THRESH : 4; /*!< [8..5] Number of data sampled to be collected from Aux-ADC and + stored in Buffer before interrupt is raised/wakeup is initialed */ + __IOM uint32_t RESERVED1 : 23; /*!< [31..9] Reserevd */ + } SDC_GEN_CONFIG_1_b; + }; + + union { + __IOM uint32_t SDC_GEN_CONFIG_2; /*!< (@ 0x00000008) SDC general configuration 2 */ + + struct { + __IOM uint32_t SDC_SAMP_EN : 1; /*!< [0..0] SDC Data Sampling mode */ + __IOM uint32_t NUM_CH_SEL : 3; /*!< [3..1] Number of Channels to be used */ + __IOM uint32_t RESERVED1 : 28; /*!< [31..4] Reserevd */ + } SDC_GEN_CONFIG_2_b; + }; + + union { + __IOM uint32_t SDC_GEN_CONFIG_3; /*!< (@ 0x00000014) SDC general configuration 3 */ + + struct { + __IOM uint32_t + SAMP_TRIG_SEL : 1; /*!< [0..0] select the trigger event on which AUX-ADC Data is sampled */ + __IOM uint32_t + CNT_TRIG_EVNT : 10; /*!< [10..1] which trigger event AUX-ADC Data will sampled */ + __IOM uint32_t SDC_CLK_DIV : 10; /*!< [20..11] SDCSS clock division factor */ + __IOM uint32_t RESERVED1 : 11; /*!< [31..21] Reserevd */ + } SDC_GEN_CONFIG_3_b; + }; + __IM uint32_t RESERVED[2]; + union { + __IOM uint32_t + SDC_AUXADC_CONFIG_1; /*!< (@ 0x00000018) SDC AUX ADC configuration 1 */ + + struct { + __IOM uint32_t + SDC_AUXADC_INPUT_P_SEL_CH1 : 5; /*!< [4..0] AUXADC's Positive Input Mux Select for Channel-1 */ + __IOM uint32_t + SDC_AUXADC_INPUT_N_SEL_CH1 : 4; /*!< [8..5] AUXADC's Negative Input Mux Select for Channel-1 */ + __IOM uint32_t + SDC_AUXADC_DIFF_MODE_CH1 : 1; /*!< [9..9] Enable Differential Mode in AUX ADC for Channel -1 */ + __IOM uint32_t + SDC_AUXADC_EN : 1; /*!< [10..10] AUXADC Enable from SDC Block */ + __IOM uint32_t SDC_ADC_CONFIG_EN : 1; /*!< [11..11] On Enabling this register, SDC ADC Configuration will + be Applied. */ + __IOM uint32_t RESERVED1 : 20; /*!< [31..12] Reserevd */ + } SDC_AUXADC_CONFIG_1_b; + }; + + union { + __IOM uint32_t + SDC_AUXDAC_CONFIG_1; /*!< (@ 0x0000001C) SDC AUX DAC configuration 1 */ + + struct { + __IOM uint32_t SDC_DAC_EN : 1; /*!< [0..0] Enable signal DAC */ + __IOM uint32_t + SDC_DAC_OUT_MUX_EN : 1; /*!< [1..1] Enable signal for Connecting DAC Output to GPIO */ + __IOM uint32_t SDC_DAC_OUT_MUX_SEL : 1; /*!< [2..2] Programming register for choosing GPIO in which DAC Output + is connected */ + __IOM uint32_t RESERVED1 : 1; /*!< [3..3] Reserved */ + __IOM uint32_t + SDC_DAC_DATA : 10; /*!< [13..4] SDC Aux DAC Data */ + __IOM uint32_t SDC_DAC_CONFIG_EN : 1; /*!< [14..14] On Enabling this register, SDC DAC Configuration will + be Applied. */ + __IOM uint32_t RESERVED2 : 17; /*!< [31..15] Reserevd */ + } SDC_AUXDAC_CONFIG_1_b; + }; + + union { + __IOM uint32_t SDC_AUXLDO_CONFIG; /*!< (@ 0x00000020) SDC AUX LDO configuration */ + + struct { + __IOM uint32_t + SDC_AUXLDO_VOLT_CTRL : 4; /*!< [3..0] SDC AUX LDO Voltage Control Selection */ + __IOM uint32_t RESERVED1 : 1; /*!< [4..4] RESERVED */ + __IOM uint32_t SDC_AUXLDO_BYP_EB : 1; /*!< [5..5] Configure AUXLDO in Buypass mode.When Enabled, Ouput + supply of LDO will be same as Input supply. */ + __IOM uint32_t + SDC_AUXLDO_EN : 1; /*!< [6..6] Turn-On AUX LDO */ + __IOM uint32_t + SDC_AUXLDO_CONFIG_EN : 1; /*!< [7..7] SDC Aux LDO Configuration Control Enable */ + __IOM uint32_t RESERVED2 : 24; /*!< [31..8] Reserved */ + } SDC_AUXLDO_CONFIG_b; + }; + + union { + __IOM uint32_t + SDC_AUXOPAMP_CONFIG_1; /*!< (@ 0x00000024) SDC AUX OPAMP configuration 1 */ + + struct { + __IOM uint32_t SDC_OPAMP_EN_CH1 : 1; /*!< [0..0] Enable signal for turning OPAMP to used for Channel-1 + Operation */ + __IOM uint32_t + SDC_OPAMP_LP_MODE : 1; /*!< [1..1] Configuration of OPAMP1 Operation mode */ + __IOM uint32_t SDC_OPAMP_R1_SEL : 2; /*!< [3..2] Configuration for Resistor Ladder R1 of OPAMP1 for controlling + it gain. */ + __IOM uint32_t SDC_OPAMP_R2_SEL : 3; /*!< [6..4] Configuration for Resistor Ladder R2 of OPAMP1 for controlling + it gain. */ + __IOM uint32_t SDC_OPAMP_RES_BACK_EN : 1; /*!< [7..7] Configuration register for controlling Resistor Bank + of OPAMP */ + __IOM uint32_t SDC_OPAMP_RES_MUX_SEL : 3; /*!< [10..8] Configuration register for Connecting R1 Resistor Ladder + input */ + __IOM uint32_t + SDC_OPAMP_RES_TO_OUT_VDD : 1; /*!< [11..11] Configuration register for Connecting R2 Resistor Ladder + input */ + __IOM uint32_t SDC_OPAMP_OUT_MUX_EN : 1; /*!< [12..12] Configur this register to OPAMP1 Output will be connected + to GPIO */ + __IOM uint32_t + SDC_OPAMP_IN_N_SEL : 3; /*!< [15..13] Configuration register for selecting N Input of OPAMP1. */ + __IOM uint32_t + SDC_OPAMP_IN_P_SEL_CH1 : 4; /*!< [19..16] Configuration register for selecting P Input of OPAMP1.,for + CH1 */ + __IOM uint32_t SDC_OPAMP_OUT_MUX_SEL : 1; /*!< [20..20] Configuration register for connecting OPAMP1 output + to GPIO */ + __IM uint32_t RESERVED1 : 1; /*!< [21..21] Reserved */ + __IOM uint32_t SDC_VREF_MUX_1_EN : 1; /*!< [22..22] Connect Low Drive Strength voltage reference for ULP + GPIO 1 For external use */ + __IOM uint32_t SDC_VREF_MUX_2_EN : 1; /*!< [23..23] Connect Low Drive Strength voltage reference for ULP + GPIO 3 For external use */ + __IOM uint32_t SDC_VREF_MUX_3_EN : 1; /*!< [24..24] Connect Low Drive Strength voltage reference for ULP + GPIO 4 For external use */ + __IOM uint32_t SDC_VREF_MUX_4_EN : 1; /*!< [25..25] Connect Low Drive Strength voltage reference for ULP + GPIO 15 For external use */ + __IOM uint32_t RESERVED2 : 1; /*!< [26..26] Reserved */ + __IOM uint32_t SDC_VREF_MUX_1_SEL : 1; /*!< [27..27] Selection register for choosing Voltage reference to + external use on ULP_GPIO_1 */ + __IOM uint32_t SDC_VREF_MUX_2_SEL : 1; /*!< [28..28] Selection register for choosing Voltage reference to + external use on ULP_GPIO_3 */ + __IOM uint32_t SDC_VREF_MUX_3_SEL : 1; /*!< [29..29] Selection register for choosing Voltage reference to + external use on ULP_GPIO_4 */ + __IOM uint32_t SDC_VREF_MUX_4_SEL : 1; /*!< [30..30] Selection register for choosing Voltage reference to + external use on ULP_GPIO_15 */ + __IOM uint32_t SDC_OPAMP_CONFIG_EN : 1; /*!< [31..31] On Enabling this register, SDC OPAMP Configuration + will be Applied. */ + } SDC_AUXOPAMP_CONFIG_1_b; + }; + + union { + __IOM uint32_t + SDC_AUXADC_CONFIG_2; /*!< (@ 0x00000028) SDC AUX ADC configuration 2 */ + + struct { + __IOM uint32_t + SDC_AUXADC_INPUT_P_SEL_CH2 : 5; /*!< [4..0] AUXADC's Positive Input Mux Select for Channel-2 */ + __IOM uint32_t + SDC_AUXADC_INPUT_N_SEL_CH2 : 4; /*!< [8..5] AUXADC's Negative Input Mux Select for Channel-2 */ + __IOM uint32_t + SDC_AUXADC_DIFF_MODE_CH2 : 1; /*!< [9..9] 1-AUX ADC Differencial mode, 0 - Single Ended Mode */ + __IOM uint32_t RESERVED1 : 22; /*!< [31..10] Reserevd */ + } SDC_AUXADC_CONFIG_2_b; + }; + + union { + __IOM uint32_t + SDC_AUXADC_CONFIG_3; /*!< (@ 0x0000002C) SDC AUX ADC configuration 3 */ + + struct { + __IOM uint32_t + SDC_AUXADC_INPUT_P_SEL_CH3 : 5; /*!< [4..0] AUXADC's Positive Input Mux Select for Channel-3 */ + __IOM uint32_t + SDC_AUXADC_INPUT_N_SEL_CH3 : 4; /*!< [8..5] AUXADC's Negative Input Mux Select for Channel-3 */ + __IOM uint32_t + SDC_AUXADC_DIFF_MODE_CH3 : 1; /*!< [9..9] 1-AUX ADC Differencial mode, 0 - Single Ended Mode */ + __IOM uint32_t RESERVED1 : 22; /*!< [31..10] Reserved */ + } SDC_AUXADC_CONFIG_3_b; + }; + + union { + __IOM uint32_t + SDC_AUXADC_CONFIG_4; /*!< (@ 0x00000030) SDC AUX ADC configuration 4 */ + + struct { + __IOM uint32_t + SDC_AUXADC_INPUT_P_SEL_CH4 : 5; /*!< [4..0] AUXADC's Positive Input Mux Select for Channel-4 */ + __IOM uint32_t + SDC_AUXADC_INPUT_N_SEL_CH4 : 4; /*!< [8..5] AUXADC's Negative Input Mux Select for Channel-4 */ + __IOM uint32_t + SDC_AUXADC_DIFF_MODE_CH4 : 1; /*!< [9..9] 1-AUX ADC Differencial mode, 0 - Single Ended Mode */ + __IOM uint32_t RESERVED1 : 22; /*!< [31..10] Reserved */ + } SDC_AUXADC_CONFIG_4_b; + }; + + union { + __IOM uint32_t + SDC_AUXOPAMP_CONFIG_2; /*!< (@ 0x00000034) SDC AUX OPAMP Configuration 2 */ + + struct { + __IOM uint32_t SDC_OPAMP_EN_CH2 : 1; /*!< [0..0] Enable signal for turning OPAMP to used for Channel-2 + Operation */ + __IOM uint32_t SDC_OPAMP_IN_P_SEL_CH2 : 4; /*!< [4..1] Configuration register for selecting P Input of OPAMP1 + for Channel-2 */ + __IOM uint32_t SDC_OPAMP_EN_CH3 : 1; /*!< [5..5] Enable signal for turning OPAMP to used for Channel-4 + Operation */ + __IOM uint32_t SDC_OPAMP_IN_P_SEL_CH3 : 4; /*!< [9..6] Configuration register for selecting P Input of OPAMP1 + for Channel-3 */ + __IOM uint32_t SDC_OPAMP_EN_CH4 : 1; /*!< [10..10] Enable signal for turning OPAMP to used for Channel-4 + Operation */ + __IOM uint32_t SDC_OPAMP_IN_P_SEL_CH4 : 1; /*!< [11..11] Configuration register for selecting P Input of OPAMP1 + for Channel-4 */ + uint32_t : 3; + __IOM uint32_t RESERVED1 : 17; /*!< [31..15] Reserved */ + } SDC_AUXOPAMP_CONFIG_2_b; + }; + __IOM SDC_SDC_DATA_REG_Type + SDC_DATA_REG[16]; /*!< (@ 0x00000038) SDC Data registers (0-15) */ +} SDC_Type; +/** @} End of group RSI_DEVICE_SYSRTC */ + +#include "si91x_mvp.h" + +#endif + +/** @} */ /* End of group Device_Peripheral_peripherals */ + +/* =========================================================================================================================== + */ +/* ================ Device Specific Peripheral Address + * Map ================ */ +/* =========================================================================================================================== + */ + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + +#define I2C0_BASE 0x44010000UL +#define I2C1_BASE 0x47040000UL +#define I2C2_BASE 0x24040000UL +#define MCPWM_BASE 0x47070000UL +#define UDMA0_BASE 0x44030000UL +#define UDMA1_BASE 0x24078000UL +#define GPDMA_G_BASE 0x21080000UL +#define GPDMA_C_BASE 0x21081004UL +#define HWRNG_BASE 0x45090000UL +#define TIMERS_BASE 0x24042000UL +#define QEI_BASE 0x47060000UL +#define USART0_BASE 0x44000100UL +#define UART0_BASE 0x44000000UL +#define UART1_BASE 0x45020000UL +#define ULP_UART_BASE 0x24041800UL +#define GSPI0_BASE 0x45030000UL +#define SSI0_BASE 0x44020000UL +#define SSISlave_BASE 0x45010000UL +#define SSI2_BASE 0x24040800UL +#define SIO_BASE 0x47000000UL +#define QSPI_BASE 0x12000000UL +#define CRC_BASE 0x45080000UL +#define EFUSE_BASE 0x4600C000UL +#define I2S0_BASE 0x47050000UL +#define I2S1_BASE 0x24040400UL +#define IID_AES_BASE 0x20480500UL +#define IID_QK_BASE 0x20480600UL +#define IID_RPINE_BASE 0x20480400UL +#define CT0_BASE 0x45060000UL +#define CT1_BASE 0x45060100UL +#define CT2_BASE 0x45061000UL +#define CT3_BASE 0x45061100UL +#define CT_MUX_REG_BASE 0x4506F000UL +#define EGPIO_BASE 0x46130000UL +#define EGPIO1_BASE 0x2404C000UL +#define SDIO0_BASE 0x20200000UL +#define SPI_SLAVE_BASE 0x20200000UL +#define M4CLK_BASE 0x46000000UL +#define TIME_PERIOD_BASE 0x24048200UL +#define MCU_WDT_BASE 0x24048300UL +#define RTC_BASE 0x2404821CUL +#define BATT_FF_BASE 0x24048400UL +#define MCU_FSM_BASE 0x24048100UL +#define MCU_ProcessSensor_BASE 0x24048540UL +#define MCU_RET_BASE 0x24048600UL +#define MCU_TEMP_BASE 0x24048500UL +#define MCU_AON_BASE 0x24048000UL +#define ULPCLK_BASE 0x24041400UL +#define SDC_BASE 0x24042400UL + +#ifdef SLI_SI917B0 +#define SYSRTC_BASE 0x24048C00UL + +#define MVP_S_BASE (0x24000000UL) /* MVP_S base address */ +#define MVP_NS_BASE (0x24000000UL) /* MVP_NS base address */ + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MVP_S)) \ + || (defined(SL_TRUSTZONE_PERIPHERAL_MVP_S) && (SL_TRUSTZONE_PERIPHERAL_MVP_S == 1))) +#define MVP_BASE (MVP_S_BASE) /* MVP base address */ +#else +#define MVP_BASE (MVP_NS_BASE) /* MVP base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_MVP_S */ +#endif + +#if ((defined ENHANCED_FIM) && (defined INST_BUFF_ENABLE)) +/* Asign some random ULPSS memory when instruction buffer is enabled */ +#define FIM_BASE 0x24060100UL +#else +#define FIM_BASE 0x24070000UL +#endif +#define NWP_FSM_BASE 0x41300110UL +#define OPAMP_BASE 0x24043A14UL +#define AUX_ADC_DAC_COMP_BASE 0x24043800UL +#define IR_BASE 0x24040C00UL +#define CTS_BASE 0x24042C00UL +#define MISC_CONFIG_BASE 0x46008000UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + +/* =========================================================================================================================== + */ +/* ================ Peripheral declaration + * ================ */ +/* =========================================================================================================================== + */ + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + +#define I2C0 ((I2C0_Type *)I2C0_BASE) +#define I2C1 ((I2C0_Type *)I2C1_BASE) +#define I2C2 ((I2C0_Type *)I2C2_BASE) +#define MCPWM ((MCPWM_Type *)MCPWM_BASE) +#define UDMA0 ((UDMA0_Type *)UDMA0_BASE) +#define UDMA1 ((UDMA0_Type *)UDMA1_BASE) +#define GPDMA_G ((GPDMA_G_Type *)GPDMA_G_BASE) +#define GPDMA_C ((GPDMA_C_Type *)GPDMA_C_BASE) +#define HWRNG ((HWRNG_Type *)HWRNG_BASE) +#define TIMERS ((TIMERS_Type *)TIMERS_BASE) +#define QEI ((QEI_Type *)QEI_BASE) +#define USART0 ((USART0_Type *)USART0_BASE) +#define UART0 ((USART0_Type *)UART0_BASE) +#define UART1 ((USART0_Type *)UART1_BASE) +#define ULP_UART ((USART0_Type *)ULP_UART_BASE) +#define GSPI0 ((GSPI0_Type *)GSPI0_BASE) +#define SSI0 ((SSI0_Type *)SSI0_BASE) +#define SSISlave ((SSI0_Type *)SSISlave_BASE) +#define SSI2 ((SSI0_Type *)SSI2_BASE) +#define SIO ((SIO_Type *)SIO_BASE) +#define QSPI ((QSPI_Type *)QSPI_BASE) +#define CRC ((CRC_Type *)CRC_BASE) +#define EFUSE ((EFUSE_Type *)EFUSE_BASE) +#define I2S0 ((I2S0_Type *)I2S0_BASE) +#define I2S1 ((I2S0_Type *)I2S1_BASE) +#define IID_AES ((IID_AES_Type *)IID_AES_BASE) +#define IID_QK ((IID_QK_Type *)IID_QK_BASE) +#define IID_RPINE ((IID_RPINE_Type *)IID_RPINE_BASE) +#define CT0 ((CT0_Type *)CT0_BASE) +#define CT1 ((CT0_Type *)CT1_BASE) +#define CT2 ((CT0_Type *)CT2_BASE) +#define CT3 ((CT0_Type *)CT3_BASE) +#define CT_MUX_REG ((CT_MUX_REG_Type *)CT_MUX_REG_BASE) +#define EGPIO ((EGPIO_Type *)EGPIO_BASE) +#define EGPIO1 ((EGPIO_Type *)EGPIO1_BASE) +#define SDIO0 ((SDIO0_Type *)SDIO0_BASE) +#define SPI_SLAVE ((SPI_SLAVE_Type *)SPI_SLAVE_BASE) +#define M4CLK ((M4CLK_Type *)M4CLK_BASE) +#define TIME_PERIOD ((TIME_PERIOD_Type *)TIME_PERIOD_BASE) +#define MCU_WDT ((MCU_WDT_Type *)MCU_WDT_BASE) +#define RTC ((RTC_Type *)RTC_BASE) +#define BATT_FF ((BATT_FF_Type *)BATT_FF_BASE) +#define MCU_FSM ((MCU_FSM_Type *)MCU_FSM_BASE) +#define MCU_ProcessSensor ((MCU_ProcessSensor_Type *)MCU_ProcessSensor_BASE) +#define MCU_RET ((MCU_RET_Type *)MCU_RET_BASE) +#define MCU_TEMP ((MCU_TEMP_Type *)MCU_TEMP_BASE) +#define MCU_AON ((MCU_AON_Type *)MCU_AON_BASE) +#define ULPCLK ((ULPCLK_Type *)ULPCLK_BASE) +#define FIM ((FIM_Type *)FIM_BASE) +#define NWP_FSM ((NWP_FSM_Type *)NWP_FSM_BASE) +#define OPAMP ((OPAMP_Type *)OPAMP_BASE) +#define AUX_ADC_DAC_COMP ((AUX_ADC_DAC_COMP_Type *)AUX_ADC_DAC_COMP_BASE) +#define IR ((IR_Type *)IR_BASE) +#define CTS ((CTS_Type *)CTS_BASE) +#define MISC_CONFIG ((MISC_CONFIG_Type *)MISC_CONFIG_BASE) +#define SDC ((SDC_Type *)SDC_BASE) +#ifdef SLI_SI917B0 +#define SYSRTC0 ((SYSRTC_TypeDef *)SYSRTC_BASE) +#define MVP ((MVP_TypeDef *)MVP_BASE) /**< MVP base pointer */ +#endif +/** @} */ /* End of group Device_Peripheral_declaration */ + +/* ========================================= End of section using anonymous + * unions ========================================= */ +#if defined(__CC_ARM) +#pragma pop +#elif defined(__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang diagnostic pop +#elif defined(__GNUC__) +/* anonymous unions are enabled by default */ +#elif defined(__TMS470__) +/* anonymous unions are enabled by default */ +#elif defined(__TASKING__) +#pragma warning restore +#elif defined(__CSMC__) +/* anonymous unions are enabled by default */ +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* RS1XXXX_H */ + +/** @} */ /* End of group RS1xxxx */ + +/** @} */ /* End of group Silicon Lab Inc. */ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/system_si91x.h b/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/system_si91x.h new file mode 100644 index 000000000..ea20cb7a2 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/system_si91x.h @@ -0,0 +1,298 @@ +/******************************************************************************* +* @file system_si91x.h +* @brief +******************************************************************************* +* # License +* Copyright 2020 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +#include + +#ifndef __SYSTEM_ARMCM4_H__ +#define __SYSTEM_ARMCM4_H__ + +/** + * + */ +#include "rsi_error.h" +#include "rsi_ccp_user_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +extern uint32_t npssIntrState; +extern uint32_t __sp; +extern uint32_t SiliconRev; +extern uint32_t package_type; + +void RSI_PS_ConfigureTaMemories(void); +/*WiSeAOC specific VTOR values*/ +#if defined(WISE_AOC_MODE) +#define VECTOR_OFF_SET_TA_ROM (0x100000 + 0x70100) /*Copyright 2020 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ +#ifdef SLI_SI91X_MCU_INTERFACE +#include +#include "rsi_ipmu.h" +//#ifdef PTE_DEEP_SLEEP_APP +#include "rsi_system_config.h" +//#endif +#define IPMU_DOTC_PROG +#define IPMU_CALIB_DATA +typedef uint16_t uint16; +typedef uint32_t uint32; +typedef int32_t int32; +typedef uint8_t uint8; +#define cmemcpy memcpy +#endif +#ifndef SLI_SI91X_MCU_INTERFACE +#include "data_types.h" +#include "defines.h" +#include "pm.h" +#include "soc_intf.h" +#include "lib_intf.h" +#include "gpio.h" +#include "timer.h" +#include "semaphore.h" +#include "error_code.h" +#include "common_intf.h" +#include "sleep_state.h" +#include "pll.h" +#include "pmu.h" +#include "misc_config.h" +#include "intr.h" +#include "bb_rf_prog_intf.h" +#include "bb_rf_prog.h" +#include "wlan_coex_intf.h" +#include "dev_ps.h" +#include "common_lmac.h" +#include "dbg.h" +#include "soft_timer.h" +#include "bb_rf_prog.h" +#include "dma.h" +#include "dynamic_clock.h" +#include "structures.h" +#include "ps.h" +#include "spi.h" +#include "hwrng.h" +#include "fmc.h" +#ifdef CHIP_9118 +#include "pwr_ctrl.h" +#endif +#include "rsi_global_non_rom.h" +#include "obe_low_pwr.h" +#include "common_ram.h" +#include "bb_rf_prog_ram.h" +#include "soc_address_map.h" +#include "ipmu_defines.h" +#include "no_host_intf.h" /* BT_DEV_MODE */ +#include "bt/bt.h" +#include "bt/bt_common.h" +#include "wakefi.h" +#include "cortex_m4.h" +#include "bb_rf_calib.h" +#include "wrappers_common.h" +#endif +void program_ipmu_data(uint32_t *src); +#ifndef BT_LE_ONLY_MODE +#ifdef SLI_SI91X_MCU_INTERFACE +void ipmu_init_mcu(void); +#else +void ipmu_init_mcu(void) __attribute__((section(".common_non_tcm_code"))); +#endif +void set_scdc(uint32 Deepsleep); +void ipmu_init_mcu(void) +{ +#ifdef IPMU_DOTC_PROG + program_ipmu_data(ipmu_common_config); //IPMU1 + program_ipmu_data(pmu_common_config); //PMU1 +#ifndef SLI_SI91X_MCU_INTERFACE + if (HF_RC_CLK_MODE == 0) { + program_ipmu_data(m20rc_osc_trim_efuse); //M20RC_EFUSE + } else if (HF_RC_CLK_MODE == 1) { + program_ipmu_data(m32rc_osc_trim_efuse); //M32RC_EFUSE + } + program_ipmu_data(dblr_32m_trim_efuse); //DBLR_EFUSE + program_ipmu_data(m20ro_osc_trim_efuse); //M20RO_EFUSE + program_ipmu_data(ro_32khz_trim_efuse); //RO32K_EFUSE + if (RC_CLK_MODE == 0) { + program_ipmu_data(rc_16khz_trim_efuse); //RC16K_EFUSE + } else if (RC_CLK_MODE == 1) { + program_ipmu_data(rc_32khz_trim_efuse); //RC32K_EFUSE + } else if (RC_CLK_MODE == 2) { + program_ipmu_data(rc_64khz_trim_efuse); //RC64K_EFUSE + } +#endif +#ifdef SLI_SI91X_MCU_INTERFACE + if (HF_RC_CLK_MODE == 0) { + /* program the trim value for 32Mhz RC oscillator */ + RSI_IPMU_M20rcOsc_TrimEfuse(); //M20RC_EFUSE + } else if (HF_RC_CLK_MODE == 1) { + /* program the trim value for 32Mhz RC oscillator */ + RSI_IPMU_M32rc_OscTrimEfuse(); //M32RC_EFUSE + } + /* program the trim value for 32MHz doubler */ + RSI_IPMU_DBLR32M_TrimEfuse(); //DBLR_EFUSE + /* program the trim value for 20MHz RC oscillator */ + RSI_IPMU_M20roOsc_TrimEfuse(); //M20RO_EFUSE + /* program the trim value for 32KHZ RO oscillator */ + RSI_IPMU_RO32khz_TrimEfuse(); //RO32K_EFUSE + if (RC_CLK_MODE == 0) { + /* program the trim value for 16KHz RC oscillator */ + RSI_IPMU_RC16khz_TrimEfuse(); //RC16K_EFUSE + } else if (RC_CLK_MODE == 1) { + /* program the trim value for 32KHz RC oscillator */ + RSI_IPMU_RC32khz_TrimEfuse(); //RC32K_EFUSE + } else if (RC_CLK_MODE == 2) { + /* program the trim value for 64KHz RC oscillator */ + RSI_IPMU_RC64khz_TrimEfuse(); //RC64K_EFUSE + } +#endif + program_ipmu_data(vbatt_status_trim_efuse); //VBATT_MON_EFUSE +#ifndef SLI_SI91X_MCU_INTERFACE + program_ipmu_data(ro_ts_efuse); //RO_TS_EFUSE + program_ipmu_data(vbg_tsbjt_efuse); //VBG_TS_EFUSE + program_ipmu_data(auxadc_off_diff_efuse); //AUXADC_DIFFOFF_EFUSE + program_ipmu_data(auxadc_gain_diff_efuse); //AUXADC_DIFFGAIN_EFUSE + program_ipmu_data(auxadc_off_se_efuse); //AUXADC_SEOFF_EFUSE + program_ipmu_data(auxadc_gain_se_efuse); //AUXADC_SEGAIN_EFUSE +#endif + program_ipmu_data(bg_trim_efuse); //bg_trim_efuse + program_ipmu_data(blackout_trim_efuse); //blackout_trim_efuse + program_ipmu_data(poc_bias_efuse); //poc_bias_efuse + program_ipmu_data(buck_trim_efuse); + program_ipmu_data(ldosoc_trim_efuse); + program_ipmu_data(dpwm_freq_trim_efuse); + program_ipmu_data(delvbe_tsbjt_efuse); + program_ipmu_data(xtal1_bias_efuse); +#ifdef SLI_SI91X_MCU_INTERFACE + program_ipmu_data(xtal2_bias_efuse); +#endif +#ifdef V1P20_IPMU_CHANGES + //http://192.168.1.215:8090/display/RS9116/Release+V1.19+Porting+Guide + //Retention-LDO Configuration + program_ipmu_data(retn_ldo_lpmode); //RETN1 + program_ipmu_data(retnLP_volt_trim_efuse); //RETNLP_TRIM_EFUSE +#ifdef SCDC_EXTCAP_MODE + program_ipmu_data(lp_scdc_extcapmode); //SCDC1 +#endif +#endif +#endif +} +#endif + +#ifdef IPMU_CALIB_DATA +/** + * @brief This function reads, modifies & writes to the iPMU registers based on different PMU SPI register type + * @param void + * @return void + */ +void update_ipmu_data(uint32_t reg_addr, uint32_t reg_type, uint32_t data, uint32_t mask) +{ + uint32_t value = 0; + + if (reg_type == ULP_SPI) { + value = PMU_DIRECT_ACCESS(reg_addr); + } else if (reg_type == PMU_SPI) { + value = PMU_SPI_DIRECT_ACCESS(reg_addr); + } else if (reg_type == DIRECT) { + value = *(volatile uint32_t *)(reg_addr); + } + value &= ~mask; + value |= data; + if (reg_type == ULP_SPI) { + PMU_DIRECT_ACCESS(reg_addr) = value; + } else if (reg_type == PMU_SPI) { + PMU_SPI_DIRECT_ACCESS(reg_addr) = value; + } else if (reg_type == DIRECT) { + *(volatile uint32_t *)(reg_addr) = value; + } +} +uint16 scdc_active; +uint16 scdc_sleep; +/** + * @brief This function prepares the data from the ipmu calib structure content and writes to each specific register + * @param void + * @return void + */ +void update_ipmu_calib_data(efuse_ipmu_t *ipmu_calib_data) __attribute__((section(".common_tcm_code"))); +void update_ipmu_calib_data(efuse_ipmu_t *ipmu_calib_data) +{ + uint32_t data; + uint32_t mask; + uint32 calibratedtrim_scdc; + uint32 calibratedtrim; +#ifndef SLI_SI91X_MCU_INTERFACE + common_info_ext_t *glbl_common_info_ext_p = (common_info_ext_t *)glbl_common_info.reserved_ptr; +#endif + //ROW 4,5,6 +#ifdef SLI_SI91X_MCU_INTERFACE + data = (ipmu_calib_data->trim_0p5na1 << 18); + mask = MASK_BITS(1, 18); +#else + data = (0 << 18) | (ipmu_calib_data->resbank_trim << 10); + mask = MASK_BITS(1, 18) | MASK_BITS(2, 10); +#endif + update_ipmu_data(iPMU_SPARE_REG1_OFFSET, ULP_SPI, data, mask); + + //ROW 5 + data = (ipmu_calib_data->bg_r_ptat_vdd_ulp << 19); + mask = MASK_BITS(3, 19); + if (ipmu_calib_data->set_vref1p3 == 0) { + data |= (2 << 10) | (2 << 7); + } else { + data |= (uint32_t)(ipmu_calib_data->scdc_dcdc_trim << 10) | (ipmu_calib_data->scdc_hpldo_trim << 7); + } + mask |= MASK_BITS(3, 10) | MASK_BITS(3, 7); + update_ipmu_data(BG_SCDC_PROG_REG_1_OFFSET, ULP_SPI, data, mask); + + scdc_active = (uint16)data; + + calibratedtrim = ((data >> 7) & 7); + calibratedtrim_scdc = ((data >> 10) & 7); +#ifdef DEEPSLEEP_SCDC_0P95 + if (calibratedtrim_scdc < 4) { + calibratedtrim_scdc = calibratedtrim_scdc + 2; + } else if (calibratedtrim_scdc == 4) { + calibratedtrim_scdc = calibratedtrim_scdc + 1; + } + if (calibratedtrim == 0) { + calibratedtrim = calibratedtrim + 3; + } else if (calibratedtrim == 1) { + calibratedtrim = calibratedtrim + 1; + } else if ((calibratedtrim == 2) || (calibratedtrim == 3)) { + calibratedtrim = calibratedtrim + 2; + } else if (calibratedtrim == 4) { + calibratedtrim = calibratedtrim + 1; + } +#else + if (calibratedtrim_scdc < 5) { + calibratedtrim_scdc = calibratedtrim_scdc + 1; + } + if (calibratedtrim == 0) { + calibratedtrim = calibratedtrim + 2; + } else if (calibratedtrim == 1) { + calibratedtrim = calibratedtrim - 1; + } else if ((calibratedtrim == 2) || (calibratedtrim == 3) || (calibratedtrim == 4)) { + calibratedtrim = calibratedtrim + 1; + } +#endif + scdc_sleep = (uint16)((calibratedtrim << 7) | (calibratedtrim_scdc << 10)); + //ROW 2 + data = ipmu_calib_data->bg_r_vdd_ulp; + mask = MASK_BITS(5, 0); + update_ipmu_data(BG_BLACKOUT_REG_OFFSET, ULP_SPI, data, mask); + + //ROW 7,17 + update_ipmu_data(ULPCLKS_32MRC_CLK_REG_OFFSET, ULP_SPI, (ipmu_calib_data->trim_sel << 14), MASK_BITS(7, 14)); + + //ROW 9 + update_ipmu_data(ULPCLKS_DOUBLER_XTAL_REG_OFFSET, ULP_SPI, (ipmu_calib_data->del_2x_sel << 15), MASK_BITS(6, 15)); + + //ROW 10 + update_ipmu_data(ULPCLKS_32KRO_CLK_REG_OFFSET, + ULP_SPI, + (ipmu_calib_data->ro_32khz_00_trim << 16), + MASK_BITS(5, 16)); //rahul + + //ROW 11 + if (RC_CLK_MODE == 0) { + data = (ipmu_calib_data->fine_trim_16k << 14); + } else if (RC_CLK_MODE == 1) { + data = (ipmu_calib_data->fine_trim_32k << 14); + } else if (RC_CLK_MODE == 2) { + data = (ipmu_calib_data->fine_trim_64k << 14); + } + mask = MASK_BITS(7, 14); + update_ipmu_data(ULPCLKS_32KRC_CLK_REG_OFFSET, ULP_SPI, data, mask); + + //ROW 12 + if (XTAL_SEL == 1) { + data = ipmu_calib_data->xtal1_trim_32k << 13; + } else if (XTAL_SEL == 2) { + data = ipmu_calib_data->xtal2_trim_32k << 13; + } + update_ipmu_data(ULPCLKS_32KXTAL_CLK_REG_OFFSET, ULP_SPI, data, MASK_BITS(4, 13)); + + //ROW 13 + update_ipmu_data(ULPCLKS_HF_RO_CLK_REG_OFFSET, ULP_SPI, (ipmu_calib_data->trim_ring_osc << 14), MASK_BITS(7, 14)); + + //ROW 16 + data = (ipmu_calib_data->f2_nominal); + mask = MASK_BITS(10, 0); + update_ipmu_data((TEMP_SENSOR_BASE_ADDRESS + TS_NOMINAL_SETTINGS_OFFSET), DIRECT, data, mask); + + //ROW 18 + data = *(volatile uint32_t *)(ULP_TASS_MISC_CONFIG_REG + 0x34); + //! For AUX_LDO register access, need to enable ulp_aux_clock + *(volatile uint32_t *)(ULP_TASS_MISC_CONFIG_REG + 0x34) = 0x1; + update_ipmu_data((AUX_BASE_ADDR + 0x210), DIRECT, ipmu_calib_data->ldo_ctrl, MASK_BITS(4, 0)); + //! restore the reg + *(volatile uint32_t *)(ULP_TASS_MISC_CONFIG_REG + 0x34) = data; + + //ROW 34 + if (ipmu_calib_data->set_vref1p3 == 0) { + data = (0xC << 17); + } else { + data = (ipmu_calib_data->set_vref1p3 << 17); + } + mask = MASK_BITS(4, 17); + update_ipmu_data(PMU_1P3_CTRL_REG_OFFSET, PMU_SPI, data, mask); + + //ROW 38 + data = ipmu_calib_data->trim_r1_resistorladder; + mask = MASK_BITS(4, 0); + update_ipmu_data(SPARE_REG_3_OFFSET, PMU_SPI, data, mask); + + //ROW 48 + data = (((ipmu_calib_data->dpwm_freq_trim)) << 13); + mask = MASK_BITS(4, 13); + update_ipmu_data(PMU_ADC_REG_OFFSET, PMU_SPI, data, mask); + +#ifdef V1P20_IPMU_CHANGES + if (ipmu_calib_data->set_vref1p3 == 0) { + data = (0x2 << 18); + } else { + data = ((ipmu_calib_data->retn_ldo_lptrim) << 18); + } + mask = MASK_BITS(3, 18); + update_ipmu_data(BG_LDO_REG_OFFSET, ULP_SPI, data, mask); +#endif +#ifndef SLI_SI91X_MCU_INTERFACE + glbl_common_info_ext_p->eeprom_calib_values.vbatt_status_trim_efuse = ipmu_calib_data->vbatt_status_1; +#endif +} +/** + * @brief This API is used to reduce or increase the SCDC voltage by 1 value + * @param Deepsleep : provide '1' before going to sleep.(i.e.Reduce the SCDC voltage by one value) + * provide '0' after wake up.(i.e.Set the SCDC voltage to the actual value) + * @return void + */ +void set_scdc(uint32 Deepsleep) +{ + uint32 mask; + + mask = MASK_BITS(3, 10) | MASK_BITS(3, 7); + update_ipmu_data(BG_SCDC_PROG_REG_1_OFFSET, ULP_SPI, Deepsleep ? scdc_sleep : scdc_active, mask); +} +/** + * @brief This function checks for magic byte in efuse/flash, copies the content if valid data present and calls to update the ipmu registers + * @param void + * @return void + */ +uint32_t init_ipmu_calib_data(uint32_t m4_present) +{ + (void)m4_present; + efuse_ipmu_t ipmu_calib_data; + efuse_ipmu_t *ipmu_calib_data_p; +#ifndef SLI_SI91X_MCU_INTERFACE + common_info_ext_t *glbl_common_info_ext_p; +#endif + ipmu_calib_data_p = &ipmu_calib_data; +#ifndef SLI_SI91X_MCU_INTERFACE + common_info_t *glbl_common_info_p = &glbl_common_info; + glbl_common_info_ext_p = (common_info_ext_t *)glbl_common_info_p->reserved_ptr; + + if ((*(uint8 *)(MANF_DATA_BASE_ADDR + BASE_OFFSET_BB_RF_IN_FLASH)) != MAGIC_WORD) { + //NO CALIB DATA. Return + return 1; + } +#endif + if ((*(uint8 *)(MANF_DATA_BASE_ADDR + IPMU_VALUES_OFFSET) == 0x00)) { + //NO CALIB DATA. Return + return 1; + } + if ((*(uint8 *)(MANF_DATA_BASE_ADDR + IPMU_VALUES_OFFSET) == 0xFF)) { + //NO CALIB DATA. Return + return 1; + } + memcpy(ipmu_calib_data_p, (efuse_ipmu_t *)(MANF_DATA_BASE_ADDR + IPMU_VALUES_OFFSET), sizeof(efuse_ipmu_t)); +#ifndef SLI_SI91X_MCU_INTERFACE + glbl_common_info_ext_p->auxadc_offset_single = ipmu_calib_data_p->auxadc_offset_single; + glbl_common_info_ext_p->vbg_tsbjt_efuse = ipmu_calib_data_p->vbg_tsbjt_efuse; + glbl_common_info_ext_p->str_bjt_temp_sense_off = ipmu_calib_data_p->str_bjt_temp_sense_off; + if (m4_present == 0) { +#endif + //Dummy read + PMU_SPI_DIRECT_ACCESS(PMU_PFM_REG_OFFSET); + + update_ipmu_calib_data(ipmu_calib_data_p); +#ifdef SLI_SI91X_MCU_INTERFACE + RSI_IPMU_UpdateIpmuCalibData_efuse(ipmu_calib_data_p); +#endif + //Dummy read + PMU_SPI_DIRECT_ACCESS(PMU_PFM_REG_OFFSET); +#ifndef SLI_SI91X_MCU_INTERFACE + } +#endif +#ifndef SLI_SI91X_MCU_INTERFACE + //ROW 38 + update_ipmu_data((NWP_AHB_ADDR + 0x604), DIRECT, (ipmu_calib_data_p->scale_soc_ldo_vref << 31), MASK_BITS(1, 31)); +#endif + return 0; +} +#endif +#ifdef IPMU_DOTC_PROG +#ifdef SLI_SI91X_MCU_INTERFACE +void program_ipmu_data(uint32_t *src); +#else +void program_ipmu_data(uint32_t *src) __attribute__((section(".common_non_tcm_code"))); +#endif +void program_ipmu_data(uint32_t *src) +{ + uint32_t write_data, num_of_reg, mask = 0, read_data; + uint32_t addr; + uint32_t ls_shift, ms_shift, mask_bits, inx = 0; + num_of_reg = src[inx]; + inx++; + + //Dummy Read + PMU_SPI_DIRECT_ACCESS(PMU_PFM_REG_OFFSET); + + while (num_of_reg--) { + addr = src[inx]; + //! 32bit Write data [31:27] ms shift and [26:22] ls shift and [21:0] data + write_data = src[inx + 1]; + //! extracting bit positions in which the data should be updated + ls_shift = (write_data >> LS_SHIFT) & 0x1F; + ms_shift = (write_data >> MS_SHIFT) & 0x1F; + //! Extracting 21-bit data from the structure + write_data = write_data & IPMU_DATAMASK; + read_data = *(uint32_t *)addr; + //! no of bits be updated + mask_bits = ms_shift - ls_shift + 1; + //! creating mask for the no of bits to be updated + while (mask_bits--) { + mask |= BIT(mask_bits); + } + //! resetting the bits in the read_data to update the data and writing the data to it + read_data &= ~(mask << ls_shift); + read_data |= (write_data & mask) << ls_shift; + *(uint32_t *)addr = read_data; + inx += 2; + mask = 0; + } +} +#endif +#ifdef SLI_SI91X_MCU_INTERFACE +void shut_down_non_wireless_mode_pds(void); +#else +// Power Domain Controls +void shut_down_non_wireless_mode_pds(void) __attribute__((section(".common_non_tcm_code"))); +#endif +void shut_down_non_wireless_mode_pds(void) +{ + uint32_t reg_val = 0; + // WuRX + PMU_DIRECT_ACCESS(iPMU_SPARE_REG2_OFFSET) &= ~(wurx_lvl_shift_en); + PMU_DIRECT_ACCESS(iPMU_SPARE_REG2_OFFSET) &= ~(wurx_pg_en_1); + + PMU_DIRECT_ACCESS(ULPCLKS_REF_CLK_REG_OFFSET) &= ~pass_clk_40m_buffer_enable; + +#ifndef IPMU_DOTC_PROG + PMU_DIRECT_ACCESS(0x125) |= (BIT(2)); //! Added by Nagaraj + PMU_DIRECT_ACCESS(0x127) &= ~((BIT(3)) | BIT(4)); //! Added by Nagaraj +#else + program_ipmu_data(ana_perif_ptat_common_config2); + program_ipmu_data(ipmu_bod_clks_common_config2); +#endif + + reg_val = (PMU_DIRECT_ACCESS(POWERGATE_REG_READ_OFFSET) >> 5); + reg_val &= ~(cmp_npss_pg_enb | ulp_ang_clks_pg_enb | wurx_corr_pg_enb | wurx_pg_enb | auxadc_pg_enb | auxdac_pg_enb); + PMU_DIRECT_ACCESS(POWERGATE_REG_WRITE_OFFSET) = reg_val; +#ifndef SLI_SI91X_MCU_INTERFACE + // 32MHz RC + PMU_DIRECT_ACCESS(ULPCLKS_32MRC_CLK_REG_OFFSET) &= ~rc_32mhz_en; + MCU_FSM_DIRECT_ACCESS(MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP) &= ~mcu_ulp_32mhz_rc_clk_en; +#endif +#if 0 + reg_val = (PMU_DIRECT_ACCESS(POWERGATE_REG_READ_OFFSET) >> 5); + reg_val &= ~(wurx_corr_pg_enb | wurx_pg_enb); + PMU_DIRECT_ACCESS(POWERGATE_REG_WRITE_OFFSET) = reg_val; + + // BG-PMU_SPI + reg_val = (PMU_DIRECT_ACCESS(POWERGATE_REG_READ_OFFSET) >> 5); + reg_val &= ~(ulp_ang_pwrsupply_pg_enb | wurx_pg_enb); + PMU_DIRECT_ACCESS(POWERGATE_REG_WRITE_OFFSET) = reg_val; + + // Button-Wakeup + PMU_DIRECT_ACCESS(BOD_TEST_PG_VBATT_STATUS_REG_OFFSET) &= ~bod_pwrgate_en_n_ulp_button_calib; + + // Clk Calibration + PMU_DIRECT_ACCESS(ULPCLKS_TRIM_SEL_REG_OFFSET) &= ~calib_powergate_en; + + // Adaptive Calibration + PMU_DIRECT_ACCESS(ULPCLKS_ADAPTIVE_REG_OFFSET) &= ~adapt_powergate_en; + + // High Freq RO + PMU_DIRECT_ACCESS(ULPCLKS_HF_RO_CLK_REG_OFFSET) &= ~ro_hf_en; + MCU_FSM_DIRECT_ACCESS(MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP) &= ~mcu_ulp_20mhz_ring_osc_clk_en; + ULP_DIRECT_ACCESS(NWP_FSM_FIRST_BOOTUP) &= ~nwp_ulp_20mhz_ring_osc_clk_en; + + // 32KHz XTAL + PMU_DIRECT_ACCESS(ULPCLKS_32KXTAL_CLK_REG_OFFSET) &= ~xtal_32khz_en; + MCU_FSM_DIRECT_ACCESS(MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP) &= ~mcu_ulp_32khz_xtal_clk_en; + ULP_DIRECT_ACCESS(NWP_FSM_FIRST_BOOTUP) &= ~nwp_ulp_32khz_xtal_clk_en; + + // 32MHz Doubler + PMU_DIRECT_ACCESS(ULPCLKS_DOUBLER_XTAL_REG_OFFSET) &= ~doubler_en; + MCU_FSM_DIRECT_ACCESS(MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP) &= ~mcu_ulp_doubler_clk_en; + ULP_DIRECT_ACCESS(NWP_FSM_FIRST_BOOTUP) &= ~nwp_ulp_doubler_clk_en; + + // 32MHz RC + PMU_DIRECT_ACCESS(ULPCLKS_32MRC_CLK_REG_OFFSET) &= ~rc_32mhz_en; + MCU_FSM_DIRECT_ACCESS(MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP) &= ~mcu_ulp_32mhz_rc_clk_en; + ULP_DIRECT_ACCESS(NWP_FSM_FIRST_BOOTUP) &= ~nwp_ulp_32mhz_rc_clk_en; + + // Tempsense_RO + TS_ENABLE_AND_TEMPERATURE_DONE &= ~temp_sens_en; + + // Tempsense_BJT + //TEMP_SENSOR_BJT &= ~BIT(0); + + // Aux-ADC/Aux-DAC + reg_val = (PMU_DIRECT_ACCESS(POWERGATE_REG_READ_OFFSET) >> 5); + reg_val &= ~(auxadc_pg_enb | auxdac_pg_enb); + PMU_DIRECT_ACCESS(POWERGATE_REG_WRITE_OFFSET) = reg_val; +#endif + + //PMU_DIRECT_ACCESS(SELECT_BG_CLK_OFFSET) &= ~(latch_transparent_lf | latch_transparent_hf | latch_top_spi); //! Added by Nagaraj +} +#ifdef SLI_SI91X_MCU_INTERFACE +void ipmu_init(void); +#else +void ipmu_init(void) __attribute__((section(".common_non_tcm_code"))); +#endif +void ipmu_init(void) +{ +#ifndef SLI_SI91X_MCU_INTERFACE + //http://192.168.1.215:8090/display/IPMU40GF/Registers+Summary + uint32_t ipmu_calb_data_invalid = 1; +#endif +#ifndef IPMU_DOTC_PROG + uint32_t pmu_1p3_ctrl_data; +#endif + uint32_t pmu_1p2_ctrl_word, bypass_curr_ctrl_data; + retention_boot_status_word_t *retention_reg = (retention_boot_status_word_t *)MCURET_BOOTSTATUS; + + //! If M4 present and host interface with M4(M4 master) case, total IPMU and MCU FSM registers has to be initialised in M4. + //! Always NWP FSM registers has to be programmed here. + //! In WiSE MCU BLE only mode IPMU programming will be done in MCU + +#ifndef SLI_SI91X_MCU_INTERFACE +#ifndef BT_LE_ONLY_MODE + if (!retention_reg->m4_present) { + ipmu_init_mcu(); + } +#endif +#ifdef IPMU_CALIB_DATA + //! Read calib data from efuse/flash and update to iPMU registers + ipmu_calb_data_invalid = init_ipmu_calib_data(retention_reg->m4_present); +#endif +#else + ipmu_init_mcu(); + //! Read calib data from efuse/flash and update to iPMU registers + init_ipmu_calib_data(retention_reg->m4_present); +#endif + +#ifndef DISABLE_M4SS_SWITCH_OFF +#ifndef SLI_SI91X_MCU_INTERFACE + if (!retention_reg->m4_present) +#endif + { +#ifdef SLI_SI91X_MCU_INTERFACE + MCU_PMU_LDO_CTRL_CLEAR_REG_1 = +#else + MCU_PMU_LDO_CTRL_CLEAR = +#endif + (mcu_soc_ldo_lvl | mcu_dcdc_lvl); //Dynamic control of LDO-SoC and VOUTBCK o/p volt from NWP + MCU_FSM_PMU_CTRL |= standby_dc1p3; //Dynamic control of PFM Mode from NWP + MCU_FSM_DIRECT_ACCESS(MCU_FSM_PMU_STATUS_REG_OFFSET) |= (scdcdc_lp_mode_en); + MCU_FSM_DIRECT_ACCESS(MCU_FSM_PMU_STATUS_REG_OFFSET) |= (bgpmu_sleep_en); + +#ifdef IPMU_DOTC_PROG +#ifndef IPMU_POWER_ENHANCEMENT + //This is commented sothat retention ldo trim value BG_LDO_REG_OFFSET[20:18] is not over written + program_ipmu_data(retn_ldo_lpmode); +#endif +#else + PMU_DIRECT_ACCESS(0x129) |= (BIT(15) | BIT(16)); //! Added by Nagaraj + PMU_DIRECT_ACCESS(0x140) |= (BIT(15) | BIT(18) | BIT(19)); //! Added by Nagaraj +#endif + +#ifdef IPMU_DOTC_PROG + //program_ipmu_data(lp_scdc_extcapmode); +#else + PMU_DIRECT_ACCESS(BG_SCDC_PROG_REG_2_OFFSET); + PMU_DIRECT_ACCESS(SCDC_CTRL_REG_0_OFFSET) = 0x3e002f; + PMU_DIRECT_ACCESS(BG_SCDC_PROG_REG_2_OFFSET) = 0x200020; + PMU_DIRECT_ACCESS(BG_LDO_REG_OFFSET) = 0x58000; +#endif + + PMU_DIRECT_ACCESS(SELECT_BG_CLK_OFFSET) |= BIT(1); //! BG-PMU Clock configured to MCU_FSM_SLEEP_CLK +#ifndef SLI_SI91X_MCU_INTERFACE + shut_down_non_wireless_mode_pds(); +#endif +#ifdef SLI_SI91X_MCU_INTERFACE + MCUAON_GEN_CTRLS_REG &= ~NPSS_SUPPLY_0P9_BIT; //Dynamic switching of NPSS/iPMU supply during sleep + MCUAON_GEN_CTRLS_REG |= ENABLE_PDO_BIT; //Dynamic control of PADs PDO during sleep +#else + MCUAON_GEN_CTRLS_REG &= ~NPSS_SUPPLY_0P9; //Dynamic switching of NPSS/iPMU supply during sleep + MCUAON_GEN_CTRLS_REG |= ENABLE_PDO; //Dynamic control of PADs PDO during sleep +#endif +#ifndef IPMU_DOTC_PROG + PMU_SPI_DIRECT_ACCESS(PMU_LDO_REG_OFFSET) &= ~LDOSOC_DEFAULT_MODE_EN; //LDO-SoC o/p Volt is configurable from NPSS + PMU_SPI_DIRECT_ACCESS(PMU_PWRTRAIN_REG_OFFSET) |= BYPASS_LDORF_CTRL; //LDO-FLASH is configurable from NPSS + + if (ipmu_calb_data_invalid) { + PMU_SPI_DIRECT_ACCESS(0x1DA) = 0x2818; + PMU_SPI_DIRECT_ACCESS(0x1DD) = 0x26249A; + PMU_SPI_DIRECT_ACCESS(0x1D0) = 0x132241; + PMU_SPI_DIRECT_ACCESS(0x1D2) = 0xE80D7; + PMU_SPI_DIRECT_ACCESS(0x1D3) = 0x872B; + } + + // Setting VOUTBCK to 1.35V (Finally Done from Calibration Data in EFUSE) + pmu_1p3_ctrl_data = PMU_SPI_DIRECT_ACCESS(PMU_1P3_CTRL_REG_OFFSET); + pmu_1p3_ctrl_data &= ~(0xF << 17); + PMU_SPI_DIRECT_ACCESS(PMU_1P3_CTRL_REG_OFFSET) = (pmu_1p3_ctrl_data | (0xA << 17)); + //////////////////////////////////////////////////////////// +#endif + + // Setting VOUTBCK_LOW to 1.25V based on the data obtained from Calibration Data + bypass_curr_ctrl_data = PMU_SPI_DIRECT_ACCESS(PMU_1P3_CTRL_REG_OFFSET); + pmu_1p2_ctrl_word = ((bypass_curr_ctrl_data >> 17) & 0xF) - 2; + bypass_curr_ctrl_data = (uint32_t)PMU_SPI_DIRECT_ACCESS(BYPASS_CURR_CTRL_REG_OFFSET); + bypass_curr_ctrl_data &= (uint32_t)(~(0xF << 5)); + PMU_SPI_DIRECT_ACCESS(BYPASS_CURR_CTRL_REG_OFFSET) = (bypass_curr_ctrl_data | (pmu_1p2_ctrl_word << 5)); + + PMU_DIRECT_ACCESS(BG_SLEEP_TIMER_REG_OFFSET) |= BIT(19); //bgs_active_timer_sel + //http://192.168.1.215:8090/display/RS9116/MCU+AON+Registers#MCUAONRegisters-MCUAON_SHELF_MODE + MCUAON_SHELF_MODE |= (7 << 19); //Programmable delay for resetting Chip + } +#endif + +#ifndef SLI_SI91X_MCU_INTERFACE + +#ifdef BGPMU_SAMPLING_EN + ULP_DIRECT_ACCESS(NWP_PMU_CTRLS) |= (scdcdc_lp_mode_en); + ULP_DIRECT_ACCESS(NWP_PMU_CTRLS) |= (bgpmu_sleep_en); //Disabling Brownout Detection. enable once issue is fixed. +#endif +#ifdef DCDC_STANDBY_MODE_EN + ULP_DIRECT_ACCESS(NWP_PMU_CTRLS) |= standby_dc1p3; +#endif + + //BIT(16) is added for smooth reset of bandgap in 1.4REV Silicon + ULP_DIRECT_ACCESS(NWPAON_POR_CTRL_BITS) |= (poc_cntrl_reg_0 | BIT(16)); + + //! 32MHz disable from NWP + ULP_DIRECT_ACCESS(NWP_FSM_FIRST_BOOTUP) &= ~nwp_ulp_32mhz_rc_clk_en; + + TASS_FSM_CTRL_BYPASS &= ~ta_pmu_shut_down_bypass; + TASS_FSM_CTRL_BYPASS &= ~ta_pmu_shut_down_bypass_cntrl; + + TASS_FSM_CTRL_BYPASS |= ta_buck_boost_enable_bypass; +#endif +} +#ifdef SLI_SI91X_MCU_INTERFACE +void configure_uulp_gpio_to_1p8v(void); +#else +void configure_uulp_gpio_to_1p8v(void) __attribute__((section(".common_non_tcm_code"))); +#endif +void configure_uulp_gpio_to_1p8v(void) +{ + //! UULP GPIO to operate at 1.8v + //http://192.168.1.215:8090/display/IPMU40GF/Registers+Summary + PMU_DIRECT_ACCESS(iPMU_SPARE_REG1_OFFSET); //Dummy read + PMU_DIRECT_ACCESS(iPMU_SPARE_REG1_OFFSET) |= BIT(13); +} + +#ifdef SLI_SI91X_MCU_INTERFACE +void configure_ipmu_mode(uint32_t mode); +#else +void configure_ipmu_mode(uint32_t mode) __attribute__((section(".common_non_tcm_code"))); +#endif +void configure_ipmu_mode(uint32_t mode) +{ + if (mode) { + //program_ipmu_data(hpldo_volt_trim_efuse); //HPLDO_TRIM_EFUSE + program_ipmu_data(hpldo_tran); //SCDC3 + program_ipmu_data(buck_fast_transient_duty_1p8); //SCDC3 + program_ipmu_data(LDOFLASH_BYPASS); //keeping ldoflash in bypass mode in 1p8V supply mode; + } else { + //program_ipmu_data(scdc_volt_trim_efuse); //SCDC_TRIM_EFUSE + program_ipmu_data(ipmu_scdc_enable); //EXT CAP Mode + program_ipmu_data(lp_scdc_extcapmode); //EXT CAP Mode + } +} +#ifndef SLI_SI91X_MCU_INTERFACE +void disable_ipmu_write_access() __attribute__((section(".common_non_tcm_code"))); +void disable_ipmu_write_access() +{ + PMU_DIRECT_ACCESS(SELECT_BG_CLK_OFFSET); + PMU_DIRECT_ACCESS(SELECT_BG_CLK_OFFSET) &= + ~(latch_transparent_lf | latch_transparent_hf | latch_top_spi); //! Added by Nagaraj + PMU_DIRECT_ACCESS(SELECT_BG_CLK_OFFSET); +} +// temp sensor +uint16 adc_read_data_func() +{ + uint16 adc_data; + uint32_t dummy_read; + uint32_t adc_data_avg; + //uint16 fifo_data[16][32]; + uint32_t inxx2 = 0; + + adc_data_avg = 0; + + for (dummy_read = 0; dummy_read < 32; dummy_read++) { + while ((*(volatile uint32_t *)(0x24043830)) & BIT(2)) + ; + adc_data = ((*(volatile uint32_t *)(0x24043814)) & 0xFFF); + adc_data = BIT(11) ^ adc_data; + if (dummy_read > 15) { + adc_data_avg += adc_data; + } + //fifo_data[inxx2][dummy_read] = adc_data; + } + adc_data_avg /= 16; + inxx2 = (inxx2 + 1) & 15; + return adc_data_avg; +} + +uint32_t adccalibDone; +#define ULP_SPI_MEM_MAP(REG_ADR) (*((uint32_t volatile *)(PMU_SPI_BASE_ADDR + (0xa000 + (REG_ADR * 4))))) +#define AUX_LDO *(volatile uint32_t *)(0x24043a10) +void calibrate_adc() +{ + uint32_t auxadcCalibValueLoad = 0, auxadcCalibValue = 0; + + if (adccalibDone == 0) { + ULP_SPI_MEM_MAP(0x110) |= BIT(11); + ULP_SPI_MEM_MAP(0x110) |= (BIT(12) | BIT(13) | BIT(8) | BIT(7) | BIT(6)); + while (*(volatile uint32_t *)(0x24050000 + 0x02) & BIT(8)) + ; + while (!(ULP_SPI_MEM_MAP(0x1C1) & BIT(0))) + ; + while ((ULP_SPI_MEM_MAP(0x1C1) & BIT(0))) + ; + usleep(20); + auxadcCalibValue = ULP_SPI_MEM_MAP(0x112); + usleep(20); + auxadcCalibValueLoad |= BIT(0) | BIT(7); + auxadcCalibValueLoad |= (auxadcCalibValue & 0x1F) << 2; + auxadcCalibValueLoad |= (((auxadcCalibValue >> 6) & 0x1F) << 8); + auxadcCalibValueLoad |= (((auxadcCalibValue >> 11) & 0x1F) << 13); + adccalibDone = 1; + } + ULP_SPI_MEM_MAP(0x111) = (auxadcCalibValueLoad); + + while (*(volatile uint32_t *)(0x24050000 + 0x02) & BIT(8)) + ; + + /* read calibrated p and n values */ + //calibrated_value = ULP_SPI_MEM_MAP(0x112); +} + +void get_ipmu_temperature(common_info_t *glbl_common_info_p) +{ + int32 adc_off; + int32 Vbg; + int32 Voffset; + uint32_t pmu_reg; + int32 irf_temperature; + int32 adc_bjt; + int32 adc_bg; + // int32 dbg_adc_bjt[32]; + // int32 dbg_adc_bg[32]; + // int16 temp[32]; + uint8 inxx = 0; + common_info_ext_t *glbl_common_info_ext_p = (common_info_ext_t *)glbl_common_info_p->reserved_ptr; + + if ((glbl_common_info_p->host_if == CORTEX_M4) || (!glbl_common_info_ext_p->chip_version_1p4_or_more)) { + irf_temperature = 70; + goto end_temp_measurement; + } + get_m4ss_access(); + *(volatile uint32_t *)(0x2405a000 + (0x142 * 4)); //dummy read + + //reg_val1 = PMU_DIRECT_ACCESS(BG_SCDC_PROG_REG_1_OFFSET); + + //PMU_DIRECT_ACCESS(BG_SCDC_PROG_REG_1_OFFSET) = reg_val1 | BIT(4); + + *(volatile uint32_t *)(0x2405a000 + (0x143 * 4)) = 0; + *(volatile uint32_t *)(0x2405a000 + (0x142 * 4)) = 0x1F910; + + ULPSS_PWRCTRL_SET_REG = ulpss_ext_pwrgate_en_n_ulp_AUX; + + ULP_DYN_CLK_CTRL_DISABLE |= BIT(11) | BIT(12) | BIT(13); + ULP_MISC_SOFT_SET_REG &= 0xfff8001f; + ULP_MISC_SOFT_SET_REG |= 0x0007ffe0; + ULP_AUXADC_CLK_GEN_REG = 0x1; + AUX_LDO = 0x7b; + + *(volatile uint32_t *)(0x2404380C) = 40; + + // wait for 50us + usleep(100); + + //*(uint32_t*)(0x2404C000 + 9 *(0x10))=(7<<2);//FIXME DELETE + + pmu_reg = ~0x1E & (*(volatile uint32_t *)(0x2405a000 + (0x129 * 4))); + *(volatile uint32_t *)(0x2405a000 + (0x129 * 4)) = pmu_reg | (8 << 1); + *(volatile uint32_t *)(0x24043a18) = 0x2e005; + + while (*(volatile uint32_t *)(0x24050000 + 0x02) & BIT(8)) + ; + + *(volatile uint32_t *)(0x24043800 + 0x24) &= ~BIT(4); + *((volatile uint32_t *)(0x24043800 + (512 + 8))) = 0x00000C15; //OPAMP2 Channel21 + *((volatile uint32_t *)(0x24043800 + (78 * 4))) = 0x00000000; + *((volatile uint32_t *)(0x24043800 + (94 * 4))) = 0x00000001; + *((volatile uint32_t *)(0x24043800 + (119 * 4))) = 0x00000001; + *((volatile uint32_t *)(0x24043800 + (1 * 4))) = 0x8000C05; + + usleep(400); + calibrate_adc(); + + adc_bg = adc_read_data_func(); + + *((volatile uint32_t *)(0x24043800 + (1 * 4))) = 0x0; + *((volatile uint32_t *)(0x24043800 + (512 + 8))) = 0x15; + ////////////TS BJT ///////////////////////// + + TS_SLOPE_SET |= BIT(28); + VAD_BBP_ID |= BIT(16); + //To control ADC channel + ADC_CHANNEL = 0x002e0000; + //For ADC channel contro + ADC_CHANNEL_CNTRL = 0x00000000; + //Internal DMA disable and channel enable + DMA = 0x00000001; + + //Enbale temperature sensor + TEM = 0x00000001; + + //BJT TEMP TEST MUX + *(volatile uint32_t *)(0x2405a000 + (0x143 * 4)) = 0x3C0010; + *(volatile uint32_t *)(0x2405a000 + (0x140 * 4)) = 0x220; + while (*(volatile uint32_t *)(0x24050000 + 0x02) & BIT(8)) + ; + + *(volatile uint32_t *)(0x2404380C) = 20; + *(volatile uint32_t *)(0x24043800 + 0x24) &= ~BIT(4); + *((volatile uint32_t *)(0x24043800 + (512 + 8))) = 0x00000C17; + *((volatile uint32_t *)(0x24043800 + (1 * 4))) = 0x8000C05; + + adc_bjt = adc_read_data_func(); + + ADC_CHANNEL = 0x00000000; + ADC_CHANNEL; + /* turn off adc */ + *((volatile uint32_t *)(0x24043800 + (512 + 8))) &= ~((BIT(10) | BIT(11))); + *((volatile uint32_t *)(0x24043800 + (1 * 4))) &= ~BIT(0); + //PMU_DIRECT_ACCESS(BG_SCDC_PROG_REG_1_OFFSET) = reg_val1; + + adc_off = glbl_common_info_ext_p->auxadc_offset_single; + Vbg = glbl_common_info_ext_p->vbg_tsbjt_efuse; + Voffset = 961 - glbl_common_info_ext_p->str_bjt_temp_sense_off; + + //dbg_adc_bg[inxx] = adc_bg; + //dbg_adc_bjt[inxx] = adc_bjt; + irf_temperature = -268 + (310 * (((Vbg * (adc_bjt - adc_off)) / (adc_bg - adc_off)) + Voffset) / 1000) + 40; + + //temp[inxx] = irf_temperature -40; + if ((irf_temperature > 100) || (irf_temperature < 50)) { + //while(1); + } + if (inxx == 7) + while (1) + ; + inxx = (inxx + 1) & 31; + release_m4ss_access(); +end_temp_measurement: + glbl_common_info_ext_p->chip_temperature = irf_temperature; +} +#endif + +#endif diff --git a/wiseconnect/components/device/silabs/si91x/mcu/core/chip/src/iPMU_prog/iPMU_dotc/rsi_system_config_917.c b/wiseconnect/components/device/silabs/si91x/mcu/core/chip/src/iPMU_prog/iPMU_dotc/rsi_system_config_917.c new file mode 100644 index 000000000..812beeed3 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/core/chip/src/iPMU_prog/iPMU_dotc/rsi_system_config_917.c @@ -0,0 +1,500 @@ +#ifdef SLI_SI91X_MCU_ENABLE_IPMU_APIS +/******************************************************************************* +* @file rsi_system_config_917.c +* @version v1p0_p77 +* @date 17 OCT 2023 +* @brief +******************************************************************************* +* # License +* Copyright 2020 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +#include +#include + +#ifdef ONEBOXE +#define _COMMON_IPMU_RAM_ __attribute__((section(".rodata .rodata."))); +#elif defined(SLI_SI91X_MCU_INTERFACE) +#define _COMMON_IPMU_RAM_ ; +#else +#define _COMMON_IPMU_RAM_ __attribute__((section(".common_tcm_rodata"))); +#endif + +uint32_t ipmu_common_config[] _COMMON_IPMU_RAM_ //IPMU1 + uint32_t ipmu_common_config[] = { + 9, 0x2405A49C, 0x49C00001, // ldo trim =1 for 1.15V in 9117 + 0x2405A4A4, 0x84000001, 0x2405A500, 0x9BC00019, 0x2405A494, + 0x10800001, 0x2405A414, 0x63000001, 0x2405A494, 0x8C000001, // active timer sel 9117 + 0x2405A494, 0xAD000002, // sleeptimer_sel 9117 + 0x2405A4AC, 0x29400000, // blackout disable 9117 + 0x2405A510, 0x29400001, // powergate_top_spi_disable - to keep ulp_analog_top spi always ON - 9117 + }; +uint32_t pmu_common_config[] _COMMON_IPMU_RAM_ //PMU1 + uint32_t pmu_common_config[] = { +#ifdef BUCK_UNDERSHOOT_DUTY_CYCLE_50 + 20, +#else + 19, +#endif + 0x24058740, 0xA440000C, 0x24058740, 0x600000BF, 0x24058748, 0x60000026, 0x24058748, 0x94400003, 0x2405874C, + 0x70000320, 0x24058768, 0x20C00003, 0x24058744, 0x9CC00001, 0x24058760, 0x10800001, 0x24058778, 0x41400007, + 0x24058758, 0x580000CC, //ldo soc set to 1.15V by default + 0x24058774, 0xA812249A, //9117 trim change,Buck Undershoot voltage of 20mV + 0x24058774, 0x41800003, 0x24058740, 0x83400008, 0x24058770, 0x7B000005, 0x24058770, 0x10000004, 0x24058774, + 0xAD000002, 0x24058770, 0x84000001, 0x2405877C, 0x8C400001, 0x24058738, 0x10800001, // 1CE 2nd BIT enabled +#ifdef BUCK_UNDERSHOOT_DUTY_CYCLE_50 + 0x24058774, 0x9C400003, //fast transient duty cycle changed to 50% +#endif + }; +uint32 pmu_pfm_mode[] _COMMON_IPMU_RAM_ //PMU2 + uint32 pmu_pfm_mode[] = { + 2, 0x24058754, 0x21000001, 0x24058744, 0x8C400001, + }; +uint32 pmu_pwm_mode[] _COMMON_IPMU_RAM_ //PMU2 + uint32 pmu_pwm_mode[] = { + 2, 0x24058754, 0x21000000, 0x24058744, 0x8C400000, + }; +uint32 buck_op_1p35[] _COMMON_IPMU_RAM_ //BUCK1 + uint32 buck_op_1p35[] = { + 1, + 0x24058740, + 0xA440000C, + }; +uint32 buck_op_1p2[] _COMMON_IPMU_RAM_ //BUCK1 + uint32 buck_op_1p2[] = { + 1, + 0x24058740, + 0xA4400009, + }; +uint32 pmu_LP_config[] _COMMON_IPMU_RAM_ //PMU2 + uint32 pmu_LP_config[] = { + 6, 0x24058774, 0x41800003, 0x24058748, 0x83400000, 0x24058740, 0x83400003, + 0x24058770, 0x7B000002, 0x24058770, 0x10000007, 0x24058774, 0xAD000002, // 9117 trim change,Buck Undershoot voltage of 20mV + }; +uint32 pmu_HP_config[] _COMMON_IPMU_RAM_ //PMU3 + uint32 pmu_HP_config[] = { + 5, 0x24058774, 0xA82224DA, 0x24058748, 0x83400000, 0x24058740, + 0x8340000C, 0x24058770, 0x7B00000C, 0x24058770, 0x10000004, + }; +uint32 pmu_socldo_0p95[] _COMMON_IPMU_RAM_ //PMU4 + uint32 pmu_socldo_0p95[] = { + 1, + 0x24058778, + 0x18000008, + }; +uint32 pmu_socldo_1p0[] _COMMON_IPMU_RAM_ //PMU5 + uint32 pmu_socldo_1p0[] = { + 1, + 0x24058778, + 0x18000009, + }; +uint32 ultrasleep_less_than_2V[] _COMMON_IPMU_RAM_ //PMU6 + uint32 ultrasleep_less_than_2V[] = { + 2, 0x24058760, 0xAC800003, 0x24058770, 0xAD400001, + }; +uint32_t buck_fast_transient_duty_1p8[] _COMMON_IPMU_RAM_ //PMU6 + uint32_t buck_fast_transient_duty_1p8[] = { + 3, 0x24058760, 0xAC800003, //pfm pon time set to max setting for 1p8V supply + 0x24058774, 0x9C400006, //fast transient duty cycle changed to 86% for 1p8V supply + 0x24058774, 0x5A400004, //increasing buck max duty cycle threshold from 92% to 95% to maintain output voltage at 1.71V supply and 250mA load condition + }; +uint32 LDOFLASH_BYPASS[] _COMMON_IPMU_RAM_ //PMU7 + uint32 LDOFLASH_BYPASS[] = { + 1, + 0x24058758, + 0x52800001, + }; +uint32 LDOSOC_BYPASS[] _COMMON_IPMU_RAM_ //PMU8 + uint32 LDOSOC_BYPASS[] = { + 2, 0x24058754, 0x39C00001, //set LDOSOC bypass + 0x24058758, 0x21000001, //set LDOSOC bypass, 2 reg programming needed + }; +uint32_t ipmu_scdc_enable[] _COMMON_IPMU_RAM_ //IPMU1_1 + uint32_t ipmu_scdc_enable[] = { + 2, 0x2405A498, 0xA83E002F, 0x2405A4A0, 0xA8200020, + }; +uint32 scdc_volt_sel1[] _COMMON_IPMU_RAM_ //SCDC0 + uint32 scdc_volt_sel1[] = { + 2, 0x2405A49C, 0x49C00002, // ldo trim =2 for 1.05V in 9117 + 0x2405A4A0, 0xAD400000, + }; +uint32 scdc_volt_sel2[] _COMMON_IPMU_RAM_ //SCDC0_1 + uint32 scdc_volt_sel2[] = { + 2, 0x2405A498, 0xA34000F0, 0x2405A4A0, 0xAD400001, + }; +uint32_t lp_scdc_extcapmode[] _COMMON_IPMU_RAM_ //SCDC1 + uint32_t lp_scdc_extcapmode[] = { + 5, 0x2405A4A0, 0xAD400000, 0x2405A49C, 0x62800002, // scdc trim = 2 ,trim change for 9117 + 0x2405A498, 0xA34000F8, 0x2405A4A0, 0x51800010, 0x2405A4A0, 0xAD400001, + }; +uint32 hp_ldo_voltsel[] _COMMON_IPMU_RAM_ //SCDC2 + uint32 hp_ldo_voltsel[] = { + 2, 0x2405A49C, 0x49C00000, 0x2405A4A0, 0xAD400000, + }; +uint32_t hpldo_tran[] _COMMON_IPMU_RAM_ //SCDC3 + uint32_t hpldo_tran[] = { + 1, + 0x2405A4A0, + 0xAD400000, + }; +uint32 SCDC_tran[] _COMMON_IPMU_RAM_ //SCDC4 + uint32 SCDC_tran[] = { + 3, 0x2405A498, 0xA34000F8, 0x2405A4A0, 0x51800010, 0x2405A4A0, 0xAD400001, + }; +uint32 retn_ldo_voltsel[] _COMMON_IPMU_RAM_ //RETN0 + uint32 retn_ldo_voltsel[] = { + 1, + 0x2405A4A4, + 0xA4800002, + }; +uint32 retn_ldo_0p75[] _COMMON_IPMU_RAM_ //RETN3 + uint32 retn_ldo_0p75[] = { + 1, + 0x2405A4A4, + 0xA4800001, + }; +uint32_t retn_ldo_lpmode[] _COMMON_IPMU_RAM_ //RETN1 + uint32_t retn_ldo_lpmode[] = { + 2, 0x2405A4A4, 0xA4800000, 0x2405A4A4, 0x84000001, + }; +uint32 retn_ldo_hpmode[] _COMMON_IPMU_RAM_ //RETN2 + uint32 retn_ldo_hpmode[] = { + 2, 0x2405A4A4, 0xA4800000, 0x2405A4A4, 0x84000000, + }; +uint32 poc_bias_current[] _COMMON_IPMU_RAM_ //POC1 + uint32 poc_bias_current[] = { + 1, + 0x2405A500, + 0x9C800000, + }; +uint32 poc_bias_current_11[] _COMMON_IPMU_RAM_ //POC2 + uint32 poc_bias_current_11[] = { + 1, + 0x2405A500, + 0x9C800003, + }; +uint32 ref_sel_pmu[] _COMMON_IPMU_RAM_ //BG_PMU_PFM + uint32 ref_sel_pmu[] = { + 1, + 0x2405A49C, + 0x10000000, + }; +uint32 bg_sleep_time[] _COMMON_IPMU_RAM_ //BG_SLEEP1 + uint32 bg_sleep_time[] = { + 2, 0x2405A494, 0x94000001, // active timer sel 9117 + 0x2405A494, 0xAD000002, // sleeptimer_sel 9117 + }; +uint32 ana_perif_ptat_common_config1[] _COMMON_IPMU_RAM_ //ANAPERIF_BIAS_EN + uint32 ana_perif_ptat_common_config1[] = { + 1, + 0x2405A49C, + 0x18C00001, + }; +uint32_t ana_perif_ptat_common_config2[] _COMMON_IPMU_RAM_ //ANAPERIF_BIAS_DIS + uint32_t ana_perif_ptat_common_config2[] = { + 1, + 0x2405A49C, + 0x18C00000, + }; +uint32 ipmu_bod_clks_common_config1[] _COMMON_IPMU_RAM_ //BOD_BIAS_EN + uint32 ipmu_bod_clks_common_config1[] = { + 1, + 0x2405A49C, + 0x21000001, + }; +uint32_t ipmu_bod_clks_common_config2[] _COMMON_IPMU_RAM_ //BOD_BIAS_DIS + uint32_t ipmu_bod_clks_common_config2[] = { + 1, + 0x2405A49C, + 0x21000000, + }; +uint32 xtal1_khz_fast_start_en[] _COMMON_IPMU_RAM_ //XTAL1_FS_EN + uint32 xtal1_khz_fast_start_en[] = { + 1, + 0x2405A438, + 0xA440000F, + }; +uint32 xtal1_khz_fast_start_disable[] _COMMON_IPMU_RAM_ //XTAL1_FS_DIS + uint32 xtal1_khz_fast_start_disable[] = { + 1, + 0x2405A438, + 0xA4400007, + }; +uint32 xtal2_khz_fast_start_en[] _COMMON_IPMU_RAM_ //XTAL2_FS_EN + uint32 xtal2_khz_fast_start_en[] = { + 1, + 0x2405A438, + 0xA440000F, + }; +uint32 xtal2_khz_fast_start_disable[] _COMMON_IPMU_RAM_ //XTAL2_FS_DIS + uint32 xtal2_khz_fast_start_disable[] = { + 1, + 0x2405A438, + 0xA4400007, + }; +uint32 button_wakeup_thresh[] _COMMON_IPMU_RAM_ //BOD_BUTTON + uint32 button_wakeup_thresh[] = { + 1, + 0x2405A400, + 0xA0830556, + }; +uint32 bod_cmp_hyst[] _COMMON_IPMU_RAM_ //BOD_CMP_HYST + uint32 bod_cmp_hyst[] = { + 1, + 0x2405A400, + 0x8000000, + }; +uint32 buck_op_ctrl[] _COMMON_IPMU_RAM_ //BUCK1 + uint32 buck_op_ctrl[] = { + 1, + 0x24058740, + 0xA440000C, + }; +uint32 ldosoc_op_ctrl[] _COMMON_IPMU_RAM_ //LDOSOC3 + uint32 ldosoc_op_ctrl[] = { + 1, + 0x24058758, + 0x2800000C, + }; +uint32 ldoflash_op_ctrl[] _COMMON_IPMU_RAM_ //LDORF3 + uint32 ldoflash_op_ctrl[] = { + 1, + 0x24058758, + 0x59800003, + }; +uint32 ro_tempsense_config[] _COMMON_IPMU_RAM_ //RO_TS_CONFIG + uint32 ro_tempsense_config[] = { + 1, + 0x2405A4D0, + 0x800000F2, + }; +uint32 bjt_tempsense_config[] _COMMON_IPMU_RAM_ //BJT_TS_CONFIG + uint32 bjt_tempsense_config[] = { + 1, + 0x2405A4D4, + 0x78000001, + }; + +uint32_t poc_bias_efuse[] _COMMON_IPMU_RAM_ //POC_BIAS_EFUSE + uint32_t poc_bias_efuse[] = { + 1, + 0x2405A500, + 0x9C800003, + }; +uint32_t bg_trim_efuse[] _COMMON_IPMU_RAM_ //BG_TRIM_EFUSE + uint32_t bg_trim_efuse[] = { + 2, 0x2405A49C, 0xACC00003, // BG_R_PTAT in 9117 + 0x2405A4AC, 0x20000010, // BG_R in 9117 + }; +uint32_t blackout_trim_efuse[] _COMMON_IPMU_RAM_ //POC3 + uint32_t blackout_trim_efuse[] = { + 1, + 0x2405A500, + 0x5A800000, + }; +uint32 m32rc_osc_trim_efuse[] _COMMON_IPMU_RAM_ //M32RC_EFUSE + uint32 m32rc_osc_trim_efuse[] = { + 1, + 0x2405A410, + 0xA380005A, + }; +uint32 m20rc_osc_trim_efuse[] _COMMON_IPMU_RAM_ //M20RC_EFUSE + uint32 m20rc_osc_trim_efuse[] = { + 1, + 0x2405A410, + 0xA3800038, + }; +uint32 dblr_32m_trim_efuse[] _COMMON_IPMU_RAM_ //DBLR_EFUSE + uint32 dblr_32m_trim_efuse[] = { + 1, + 0x2405A404, + 0xA3C00020, + }; +uint32 ro_32khz_trim_efuse[] _COMMON_IPMU_RAM_ //RO32K_EFUSE + uint32 ro_32khz_trim_efuse[] = { + 1, + 0x2405A408, + 0xA4000007, + }; +uint32 ro_32khz_trim00_efuse[] _COMMON_IPMU_RAM_ //RO32K_00_EFUSE + uint32 ro_32khz_trim00_efuse[] = { + 1, + 0x2405A408, + 0xA4000015, + }; +uint32 rc_16khz_trim_efuse[] _COMMON_IPMU_RAM_ //RC16K_EFUSE + uint32 rc_16khz_trim_efuse[] = { + 3, 0x2405A40C, 0xA380005A, // register bits changed in 9117 + 0x2405A40C, 0x10400000, 0x2405A40C, 0x00000000, + + }; +uint32 rc_64khz_trim_efuse[] _COMMON_IPMU_RAM_ //RC64K_EFUSE + uint32 rc_64khz_trim_efuse[] = { + 3, 0x2405A40C, 0xA380005A, // register bits changed in 9117 + 0x2405A40C, 0x10400003, 0x2405A40C, 0x00000000, + }; +uint32 rc_32khz_trim_efuse[] _COMMON_IPMU_RAM_ //RC32K_EFUSE + uint32 rc_32khz_trim_efuse[] = { + 3, 0x2405A40C, 0xA380005A, // register bits changed in 9117 + 0x2405A40C, 0x10400002, 0x2405A40C, 0x00000000, + }; +uint32_t xtal1_bias_efuse[] _COMMON_IPMU_RAM_ //XTAL1_BIAS_EFUSE + uint32_t xtal1_bias_efuse[] = { + 1, + 0x2405A438, + 0x83400003, + }; +uint32_t xtal2_bias_efuse[] _COMMON_IPMU_RAM_ //XTAL2_BIAS_EFUSE + uint32_t xtal2_bias_efuse[] = { + 1, + 0x2405A438, + 0x83400003, + }; +uint32 m20ro_osc_trim_efuse[] _COMMON_IPMU_RAM_ //M20RO_EFUSE + uint32 m20ro_osc_trim_efuse[] = { + 1, + 0x2405A414, + 0xA3800027, + }; +uint32_t vbatt_status_trim_efuse[] _COMMON_IPMU_RAM_ //VBATT_MON_EFUSE + uint32_t vbatt_status_trim_efuse[] = { + 1, + 0x2405A438, + 0x28000000, + }; +uint32 ro_ts_efuse[] _COMMON_IPMU_RAM_ //RO_TS_EFUSE + uint32 ro_ts_efuse[] = { + 1, + 0x2405A4D8, + 0x4800010E, + }; +uint32 vbg_tsbjt_efuse[] _COMMON_IPMU_RAM_ //VBG_TS_EFUSE + uint32 vbg_tsbjt_efuse[] = { + 1, + 0x2405A4DC, + 0x580004BF, + }; +uint32_t delvbe_tsbjt_efuse[] _COMMON_IPMU_RAM_ //DELVBE_TS_EFUSE + uint32_t delvbe_tsbjt_efuse[] = { + 1, + 0x2405A4E0, + 0x500003D9, + }; +uint32 auxadc_off_diff_efuse[] _COMMON_IPMU_RAM_ //AUXADC_DIFFOFF_EFUSE + uint32 auxadc_off_diff_efuse[] = { + 1, + 0x2405A4C0, + 0x58000064, + }; +uint32 auxadc_gain_diff_efuse[] _COMMON_IPMU_RAM_ //AUXADC_DIFFGAIN_EFUSE + uint32 auxadc_gain_diff_efuse[] = { + 1, + 0x2405A4C4, + 0x78008000, + }; +uint32 auxadc_off_se_efuse[] _COMMON_IPMU_RAM_ //AUXADC_SEOFF_EFUSE + uint32 auxadc_off_se_efuse[] = { + 1, + 0x2405A4C8, + 0x58000064, + }; +uint32 auxadc_gain_se_efuse[] _COMMON_IPMU_RAM_ //AUXADC_SEGAIN_EFUSE + uint32 auxadc_gain_se_efuse[] = { + 1, + 0x2405A4CC, + 0x78008000, + }; +uint32_t buck_trim_efuse[] _COMMON_IPMU_RAM_ //BUCK_TRIM_EFUSE + uint32_t buck_trim_efuse[] = { + 1, + 0x24058740, + 0xA440000C, + }; +uint32_t ldosoc_trim_efuse[] _COMMON_IPMU_RAM_ //LDOSOC_TRIM_EFUSE + uint32_t ldosoc_trim_efuse[] = { + 1, + 0x2405877C, + 0x18000000, + }; +uint32_t dpwm_freq_trim_efuse[] _COMMON_IPMU_RAM_ //DPWM_FREQ_TRIM_EFUSE + uint32_t dpwm_freq_trim_efuse[] = { + 1, + 0x24058748, + 0x83400000, + }; +uint32 scdc_volt_trim_efuse[] _COMMON_IPMU_RAM_ //SCDC_TRIM_EFUSE + uint32 scdc_volt_trim_efuse[] = { + 1, + 0x2405A49C, + 0x62800000, + }; +uint32 hpldo_volt_trim_efuse[] _COMMON_IPMU_RAM_ //HPLDO_TRIM_EFUSE + uint32 hpldo_volt_trim_efuse[] = { + 1, + 0x2405A49C, + 0x49C00001, // in 9117, trim for max voltage is 1 + }; +uint32 retnHP_volt_trim_efuse[] _COMMON_IPMU_RAM_ //RETNHP_TRIM_EFUSE + uint32 retnHP_volt_trim_efuse[] = { + 1, + 0x2405A4A4, + 0xA4800000, + }; +uint32 retnLP_volt_trim_efuse[] _COMMON_IPMU_RAM_ //RETNLP_TRIM_EFUSE + uint32 retnLP_volt_trim_efuse[] = { + 1, + 0x2405A4A4, + 0xA4800000, + }; +uint32 scdc_volt_trim_bump_efuse[] _COMMON_IPMU_RAM_ //SCDC_TRIM_BUMP_EFUSE + uint32 scdc_volt_trim_bump_efuse[] = { + 1, + 0x2405A49C, + 0x62800000, + }; +uint32 hpldo_volt_trim_bump_efuse[] _COMMON_IPMU_RAM_ //HPLDO_TRIM_BUMP_EFUSE + uint32 hpldo_volt_trim_bump_efuse[] = { + 1, + 0x2405A49C, + 0x49C00001, // in 9117, trim for max voltage is 1 + }; +uint32 scdc_freq_efuse[] _COMMON_IPMU_RAM_ //SCDC_FREQ_EFUSE + uint32 scdc_freq_efuse[] = { + 1, + 0x2405A4C4, + 0x2000001F, + }; +uint32 scdc_freqtrim_efuse[] _COMMON_IPMU_RAM_ // SCDC_FREQTRIM_EFUSE + uint32 scdc_freqtrim_efuse[] = { + 1, + 0x2405A504, + 0x20C00000, + }; +uint32 blackout_enable[] _COMMON_IPMU_RAM_ //IPMU1 + uint32 blackout_enable[] = { + 1, + 0x2405A4AC, + 0x29400001, // blackout enable 9117 + }; +uint32 blackout_disable[] _COMMON_IPMU_RAM_ //IPMU1 + uint32 blackout_disable[] = { + 1, + 0x2405A4AC, + 0x29400000, // blackout disable 9117 + }; +uint32 dblr_input_sel[] _COMMON_IPMU_RAM_ //IPMU1 + uint32 dblr_input_sel[] = { + 1, + 0x2405A404, + 0x42000000, // doubler inp clk sel - 9117 + }; +#endif diff --git a/wiseconnect/components/device/silabs/si91x/mcu/core/chip/src/system_si91x.c b/wiseconnect/components/device/silabs/si91x/mcu/core/chip/src/system_si91x.c new file mode 100644 index 000000000..134b7ae73 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/core/chip/src/system_si91x.c @@ -0,0 +1,250 @@ +/******************************************************************************* +* @file system_si91x.c +* @brief +******************************************************************************* +* # License +* Copyright 2020 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +/** + * Includes + */ + +#include +#include "system_si91x.h" +#include "rsi_error.h" +#include "rsi_ccp_common.h" +#include "rsi_ps_ram_func.h" +#include "rsi_ipmu.h" +#include "rsi_pll.h" +#include "rsi_power_save.h" +#include "rsi_ulpss_clk.h" +#include "rsi_rom_ulpss_clk.h" +#include "rsi_rom_clks.h" +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __SYSTEM_CLOCK 32000000 // 32MhzMhz Reference clock + +/*Cortex-m4 FPU registers*/ +#define FPU_CPACR 0xE000ED88 +#define SCB_MVFR0 0xE000EF40 +#define SCB_MVFR0_RESET 0x10110021 +#define SCB_MVFR1 0xE000EF44 +#define SCB_MVFR1_RESET 0x11000011 + +/*Simulation macros*/ +#define SIMULATION_SILICON_REV 0x14 +#define SIMULATION_PACKAGE_TYPE 0x1 + +/* Constants required to manipulate the NVIC. */ +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ + +SYSTEM_CLOCK_SOURCE_FREQUENCIES_T system_clocks; /*!< System Clock sources Frequencies */ + +uint32_t npssIntrState = 0; +uint32_t __sp; +uint32_t SiliconRev; +uint32_t package_type; + +/** + * @fn void SystemCoreClockUpdate (void) + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + * @return none + */ +void SystemCoreClockUpdate(void) /* Get Core Clock Frequency */ +{ + retention_boot_status_word_t *retention_reg = (retention_boot_status_word_t *)MCURET_BOOTSTATUS; + /*Updated the default SOC clock frequency*/ + SystemCoreClock = DEFAULT_32MHZ_RC_CLOCK; +#if (defined(RAM_COMPILATION) && defined(SLI_SI91X_MCU_COMMON_FLASH_MODE)) + /*Initialize QSPI for RAM based execution for common flash boards */ + RSI_FLASH_Initialize(); +#endif +#ifndef SIMULATION +#if defined(RAM_COMPILATION) && defined(SIMULATION) + if (retention_reg->product_mode == MCU) { + SiliconRev = SIMULATION_SILICON_REV; + package_type = SIMULATION_PACKAGE_TYPE; + } else { + SiliconRev = SILICON_REV_WMCU; + package_type = PACKAGE_TYPE_WMCU; + } +#else + if (retention_reg->product_mode == MCU) { + SiliconRev = SILICON_REV_MCU; + package_type = PACKAGE_TYPE_MCU; + } else { + SiliconRev = SILICON_REV_WMCU; + package_type = PACKAGE_TYPE_WMCU; + } + +#endif + /*Initialize IPMU and MCU FSM blocks */ + RSI_Ipmu_Init(); + /*configures chip supply mode */ + RSI_Configure_Ipmu_Mode(); +#endif + + /*Default clock mux configurations */ + RSI_CLK_PeripheralClkEnable3(M4CLK, M4_SOC_CLK_FOR_OTHER_ENABLE); + RSI_CLK_M4ssRefClkConfig(M4CLK, ULP_32MHZ_RC_CLK); + RSI_ULPSS_RefClkConfig(ULPSS_ULP_32MHZ_RC_CLK); + + /* TA clock is selected as RC32MHZ clock from MCU */ + MCU_FSM->MCU_FSM_REF_CLK_REG_b.TASS_REF_CLK_SEL = ULP_32MHZ_RC_CLK; + /* Changing NPSS GPIO 0 mode to 0, to disable buck-boost enable mode*/ + MCU_RET->NPSS_GPIO_CNTRL[0].NPSS_GPIO_CTRLS_b.NPSS_GPIO_MODE = 0; + /* Configuring RO-32KHz Clock for BG_PMU */ + RSI_IPMU_ClockMuxSel(1); + /* Configuring XTAL 32KHz Clock for LF-FSM */ + RSI_PS_FsmLfClkSel(KHZ_XTAL_CLK_SEL); + /* Configuring RC-32MHz Clock for HF-FSM */ + RSI_PS_FsmHfClkSel(FSM_32MHZ_RC); + +#if ((defined SLI_SI91X_MCU_COMMON_FLASH_MODE) && (!(defined(RAM_COMPILATION)))) + /* Before TA is going to power save mode ,set m4ss_ref_clk_mux_ctrl , + tass_ref_clk_mux_ctrl, AON domain power supply controls form TA to M4 */ + RSI_Set_Cntrls_To_M4(); + +#endif + /*Update the system clock sources with source generating frequency*/ + system_clocks.m4ss_ref_clk = DEFAULT_32MHZ_RC_CLOCK; + system_clocks.ulpss_ref_clk = DEFAULT_32MHZ_RC_CLOCK; + system_clocks.soc_pll_clock = DEFAULT_SOC_PLL_CLOCK; + system_clocks.modem_pll_clock = DEFAULT_MODEM_PLL_CLOCK; + system_clocks.modem_pll_clock2 = DEFAULT_MODEM_PLL_CLOCK; + system_clocks.intf_pll_clock = DEFAULT_INTF_PLL_CLOCK; + system_clocks.soc_clock = DEFAULT_32MHZ_RC_CLOCK; + system_clocks.rc_32khz_clock = DEFAULT_32KHZ_RC_CLOCK; + system_clocks.rc_32mhz_clock = DEFAULT_32MHZ_RC_CLOCK; + system_clocks.ro_20mhz_clock = DEFAULT_20MHZ_RO_CLOCK; + system_clocks.ro_32khz_clock = DEFAULT_32KHZ_RO_CLOCK; + system_clocks.xtal_32khz_clock = DEFAULT_32KHZ_XTAL_CLOCK; + system_clocks.doubler_clock = DEFAULT_DOUBLER_CLOCK; + system_clocks.rf_ref_clock = DEFAULT_RF_REF_CLOCK; + system_clocks.mems_ref_clock = DEFAULT_MEMS_REF_CLOCK; + system_clocks.byp_rc_ref_clock = DEFAULT_32MHZ_RC_CLOCK; + system_clocks.i2s_pll_clock = DEFAULT_I2S_PLL_CLOCK; + + return; +} + +/** + * @fn void fpuInit(void) + * @brief This API is used to Early initialization of the FPU + * @return none + * + */ +void fpuInit(void) +{ +#if __FPU_PRESENT != 0 + // from arm trm manual: + // ; CPACR is located at address 0xE000ED88 + // LDR.W R0, =0xE000ED88 + // ; Read CPACR + // LDR R1, [R0] + // ; Set bits 20-23 to enable CP10 and CP11 coprocessors + // ORR R1, R1, #(0xF << 20) + // ; Write back the modified value to the CPACR + // STR R1, [R0] + + volatile uint32_t *regCpacr = (uint32_t *)FPU_CPACR; + volatile uint32_t *regMvfr0 = (uint32_t *)SCB_MVFR0; + volatile uint32_t *regMvfr1 = (uint32_t *)SCB_MVFR1; + volatile uint32_t Cpacr; + volatile uint32_t Mvfr0; + volatile uint32_t Mvfr1; + char vfpPresent = 0; + + Mvfr0 = *regMvfr0; + Mvfr1 = *regMvfr1; + + vfpPresent = ((SCB_MVFR0_RESET == Mvfr0) && (SCB_MVFR1_RESET == Mvfr1)); + + if (vfpPresent) { + Cpacr = *regCpacr; + Cpacr |= (0xF << 20); + *regCpacr = Cpacr; // enable CP10 and CP11 for full access + } +#endif /* __FPU_PRESENT != 0 */ +} + +/** + * @fn void SystemInit (void) + * @brief This API is used Setup the RS1xxxx chip(Initialize the system) + * @return none + */ +void SystemInit(void) +{ + volatile uint32_t ipmuDummyRead = 0; + volatile uint32_t spareReg2 = 0; + + /*IPMU dummy read to make IPMU block out of RESET*/ + ipmuDummyRead = ULP_SPI_MEM_MAP(0x144); + ipmuDummyRead = ipmuDummyRead; + + /*Update the REG Access SPI division factor to increase the SPI read/write speed*/ + RSI_SetRegSpiDivision(0U); + + ULP_SPI_MEM_MAP(BG_SCDC_PROG_REG_1) &= REF_SEL_LP_DCDC; + + /*Spare register write sequence*/ + spareReg2 = ULP_SPI_MEM_MAP(0x1C1); + ULP_SPI_MEM_MAP(0x141) = spareReg2; + //while(GSPI_CTRL_REG1 & SPI_ACTIVE); + /*Spare register write sequence*/ + spareReg2 = ULP_SPI_MEM_MAP(0x1C0); + ULP_SPI_MEM_MAP(0x140) = spareReg2; + + /*Set IPMU BITS*/ + ULP_SPI_MEM_MAP(SELECT_BG_CLK) |= (LATCH_TOP_SPI | LATCH_TRANSPARENT_HF | LATCH_TRANSPARENT_LF); + + while (GSPI_CTRL_REG1 & SPI_ACTIVE) + ; + + MCU_AON->MCUAON_GEN_CTRLS_b.ENABLE_PDO = 1; + MCU_AON->MCUAON_GEN_CTRLS_b.NPSS_SUPPLY_0P9 = 0; + + /*Enable FPU*/ + fpuInit(); + + /* Enable REF Clock Control*/ + //FIXME: This will be configured by boot-loader based on product mode + *(volatile uint32_t *)0x41300004 = BIT(24); + + /*Moving to BG sampling mode */ + *(volatile uint32_t *)0x24048140 = (BIT(19) | BIT(1) | BIT(0)); + + /*Disable WIC based wake up */ + MCU_FSM->MCU_FSM_PERI_CONFIG_REG_b.WICENREQ = 0; + + /*Set ulp_wakeup_por*/ + MCU_AON->MCUAON_KHZ_CLK_SEL_POR_RESET_STATUS_b.MCU_FIRST_POWERUP_POR = 1U; + MCU_AON->MCUAON_KHZ_CLK_SEL_POR_RESET_STATUS_b.MCU_FIRST_POWERUP_RESET_N = 1U; + /*Programmable delay 4mes for WDT reset */ + PMU_DIRECT_ACCESS(BG_SLEEP_TIMER_REG_OFFSET) |= BIT(19); //bgs_active_timer_sel + /*Programmable delay 4mes for WDT reset */ + MCU_AON->MCUAON_SHELF_MODE_b.SHELF_MODE_WAKEUP_DELAY = 0x7; + /* Enables software based control of isolation and reset for ULP AON */ + BATT_FF->M4SS_BYPASS_PWRCTRL_REG1_b.BYPASS_M4SS_PWRCTL_ULP_AON_b = 1; + /* Enables software based control of isolation and reset for M4ss CORE */ + BATT_FF->M4SS_BYPASS_PWRCTRL_REG1_b.BYPASS_M4SS_PWRCTL_ULP_M4_CORE_b = 1; + return; +} +/** + *@} + */ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/core/config/rsi_ccp_user_config.h b/wiseconnect/components/device/silabs/si91x/mcu/core/config/rsi_ccp_user_config.h new file mode 100644 index 000000000..344bbb2ba --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/core/config/rsi_ccp_user_config.h @@ -0,0 +1,64 @@ +/******************************************************************************* +* @file rsi_ccp_user_config.h +* @brief +******************************************************************************* +* # License +* Copyright 2020 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +/*rsi_ccp_user_config.h --> user configurations w.r.t CCP*/ + +/* To enable 917 chip --> Add #define SLI_SI917 */ +/* To enable 9116 chip --> Add #define CHIP_9118 */ +/* To enable 9115 chip --> Add #define CHIP_915 */ + +/* #define CHIP_9118 */ +/* #define CHIP_915 */ +//#define CHIP_917_6x6 +//#define SLI_SI917 + +#ifdef CHIP_915 +#ifndef SLI_SI917 +#define SLI_SI917 +#endif +#endif + +/*1. By default A10 ROM is enabled */ +/*2. To enable A11 ROM --> Add #define A11_ROM (this disables A10 ROM) */ +/*3. To enable OS --> Add SLI_SI91X_ENABLE_OS in preprocessor */ +/*4. To enable ROM Wireless --> Add #define ROM_WIRELESS */ +#define A11_ROM + +#ifndef SLI_SI91X_MCU_MOV_ROM_API_TO_FLASH +#define ROMDRIVER_PRESENT +#endif + +//#define ROM_WIRELESS + +/* To enable uart prints --> Add #define DEBUG_UART as below */ +/* To disable uart prints --> Remove /Comment #define DEBUG_UART */ +//#define DEBUG_UART + +/*To compile code for simulations --> Add #define SIMULATION*/ +//#define SIMULATION + +/*To compile code for simulations with RAM based settings --> Add #define RAM_COMPILATION */ +//#define RAM_COMPILATION + +/*Enable this macro for Radio board database*/ +//#define SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER + +/*Enable this macro when chip supply is on 1.8v */ +//#define ENABLE_1P8V +#ifdef SLI_SI917B0 +#define SI91X_SYSRTC_COUNT 2 +#endif diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_Common.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_Common.h new file mode 100644 index 000000000..b11a115c4 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_Common.h @@ -0,0 +1,72 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2013-2014 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * + * $Date: 2. Jan 2014 + * $Revision: V2.00 + * + * Project: Common Driver definitions + * -------------------------------------------------------------------------- */ + +/* History: + * Version 2.00 + * Changed prefix ARM_DRV -> ARM_DRIVER + * Added General return codes definitions + * Version 1.10 + * Namespace prefix ARM_ added + * Version 1.00 + * Initial release + */ + +#ifndef __DRIVER_COMMON_H +#define __DRIVER_COMMON_H + +#include +#include +#include + +#define ARM_DRIVER_VERSION_MAJOR_MINOR(major,minor) (((major) << 8) | (minor)) + +/** +\brief Driver Version +*/ +typedef struct _ARM_DRIVER_VERSION { + uint16_t api; ///< API version + uint16_t drv; ///< Driver version +} ARM_DRIVER_VERSION; + +/* General return codes */ +#define ARM_DRIVER_OK 0 ///< Operation succeeded +#define ARM_DRIVER_ERROR -1 ///< Unspecified error +#define ARM_DRIVER_ERROR_BUSY -2 ///< Driver is busy +#define ARM_DRIVER_ERROR_TIMEOUT -3 ///< Timeout occurred +#define ARM_DRIVER_ERROR_UNSUPPORTED -4 ///< Operation not supported +#define ARM_DRIVER_ERROR_PARAMETER -5 ///< Parameter error +#define ARM_DRIVER_ERROR_SPECIFIC -6 ///< Start of driver specific errors + +/** +\brief General power states +*/ +typedef enum _ARM_POWER_STATE { + ARM_POWER_OFF, ///< Power off: no operation possible + ARM_POWER_LOW, ///< Low Power mode: retain state, detect and signal wake-up events + ARM_POWER_FULL ///< Power on: full operation at maximum performance +} ARM_POWER_STATE; + +#endif /* __DRIVER_COMMON_H */ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_I2C.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_I2C.h new file mode 100644 index 000000000..7ed887cd2 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_I2C.h @@ -0,0 +1,208 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2013-2014 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * + * $Date: 9. May 2014 + * $Revision: V2.02 + * + * Project: I2C (Inter-Integrated Circuit) Driver definitions + * -------------------------------------------------------------------------- */ + +/* History: + * Version 2.02 + * Removed function ARM_I2C_MasterTransfer in order to simplify drivers + * and added back parameter "xfer_pending" to functions + * ARM_I2C_MasterTransmit and ARM_I2C_MasterReceive + * Version 2.01 + * Added function ARM_I2C_MasterTransfer and removed parameter "xfer_pending" + * from functions ARM_I2C_MasterTransmit and ARM_I2C_MasterReceive + * Added function ARM_I2C_GetDataCount + * Removed flag "address_nack" from ARM_I2C_STATUS + * Replaced events ARM_I2C_EVENT_MASTER_DONE and ARM_I2C_EVENT_SLAVE_DONE + * with event ARM_I2C_EVENT_TRANSFER_DONE + * Added event ARM_I2C_EVENT_TRANSFER_INCOMPLETE + * Removed parameter "arg" from function ARM_I2C_SignalEvent + * Version 2.00 + * New simplified driver: + * complexity moved to upper layer (especially data handling) + * more unified API for different communication interfaces + * Added: + * Slave Mode + * Changed prefix ARM_DRV -> ARM_DRIVER + * Version 1.10 + * Namespace prefix ARM_ added + * Version 1.00 + * Initial release + */ + +#ifndef __DRIVER_I2C_H +#define __DRIVER_I2C_H + +#include "Driver_Common.h" + + +#define ARM_I2C_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,02) /* API version */ + + +/****** I2C Control Codes *****/ + +#define ARM_I2C_OWN_ADDRESS (0x01) ///< Set Own Slave Address; arg = address +#define ARM_I2C_BUS_SPEED (0x02) ///< Set Bus Speed; arg = speed +#define ARM_I2C_BUS_CLEAR (0x03) ///< Execute Bus clear: send nine clock pulses +#define ARM_I2C_ABORT_TRANSFER (0x04) ///< Abort Master/Slave Transmit/Receive + +/*----- I2C Bus Speed -----*/ +#define ARM_I2C_BUS_SPEED_STANDARD (0x01) ///< Standard Speed (100kHz) +#define ARM_I2C_BUS_SPEED_FAST (0x02) ///< Fast Speed (400kHz) +#define ARM_I2C_BUS_SPEED_FAST_PLUS (0x03) ///< Fast+ Speed ( 1MHz) +#define ARM_I2C_BUS_SPEED_HIGH (0x04) ///< High Speed (3.4MHz) + + +/****** I2C Address Flags *****/ + +#define ARM_I2C_ADDRESS_10BIT 0x0400 ///< 10-bit address flag +#define ARM_I2C_ADDRESS_GC 0x8000 ///< General Call flag + + +/** +\brief I2C Status +*/ +typedef struct _ARM_I2C_STATUS { + uint32_t busy : 1; ///< Busy flag + uint32_t mode : 1; ///< Mode: 0=Slave, 1=Master + uint32_t direction : 1; ///< Direction: 0=Transmitter, 1=Receiver + uint32_t general_call : 1; ///< General Call indication (cleared on start of next Slave operation) + uint32_t arbitration_lost : 1; ///< Master lost arbitration (cleared on start of next Master operation) + uint32_t bus_error : 1; ///< Bus error detected (cleared on start of next Master/Slave operation) +} ARM_I2C_STATUS; + + +/****** I2C Event *****/ +#define ARM_I2C_EVENT_TRANSFER_DONE (1UL << 0) ///< Master/Slave Transmit/Receive finished +#define ARM_I2C_EVENT_TRANSFER_INCOMPLETE (1UL << 1) ///< Master/Slave Transmit/Receive incomplete transfer +#define ARM_I2C_EVENT_SLAVE_TRANSMIT (1UL << 2) ///< Slave Transmit operation requested +#define ARM_I2C_EVENT_SLAVE_RECEIVE (1UL << 3) ///< Slave Receive operation requested +#define ARM_I2C_EVENT_ADDRESS_NACK (1UL << 4) ///< Address not acknowledged from Slave +#define ARM_I2C_EVENT_GENERAL_CALL (1UL << 5) ///< General Call indication +#define ARM_I2C_EVENT_ARBITRATION_LOST (1UL << 6) ///< Master lost arbitration +#define ARM_I2C_EVENT_BUS_ERROR (1UL << 7) ///< Bus error detected (START/STOP at illegal position) +#define ARM_I2C_EVENT_BUS_CLEAR (1UL << 8) ///< Bus clear finished + + +// Function documentation +/** + \fn ARM_DRIVER_VERSION ARM_I2C_GetVersion (void) + \brief Get driver version. + \return \ref ARM_DRIVER_VERSION + + \fn ARM_I2C_CAPABILITIES ARM_I2C_GetCapabilities (void) + \brief Get driver capabilities. + \return \ref ARM_I2C_CAPABILITIES + + \fn int32_t ARM_I2C_Initialize (ARM_I2C_SignalEvent_t cb_event) + \brief Initialize I2C Interface. + \param[in] cb_event Pointer to \ref ARM_I2C_SignalEvent + \return \ref execution_status + + \fn int32_t ARM_I2C_Uninitialize (void) + \brief De-initialize I2C Interface. + \return \ref execution_status + + \fn int32_t ARM_I2C_PowerControl (ARM_POWER_STATE state) + \brief Control I2C Interface Power. + \param[in] state Power state + \return \ref execution_status + + \fn int32_t ARM_I2C_MasterTransmit (uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) + \brief Start transmitting data as I2C Master. + \param[in] addr Slave address (7-bit or 10-bit) + \param[in] data Pointer to buffer with data to transmit to I2C Slave + \param[in] num Number of data bytes to transmit + \param[in] xfer_pending Transfer operation is pending - Stop condition will not be generated + \return \ref execution_status + + \fn int32_t ARM_I2C_MasterReceive (uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) + \brief Start receiving data as I2C Master. + \param[in] addr Slave address (7-bit or 10-bit) + \param[out] data Pointer to buffer for data to receive from I2C Slave + \param[in] num Number of data bytes to receive + \param[in] xfer_pending Transfer operation is pending - Stop condition will not be generated + \return \ref execution_status + + \fn int32_t ARM_I2C_SlaveTransmit (const uint8_t *data, uint32_t num) + \brief Start transmitting data as I2C Slave. + \param[in] data Pointer to buffer with data to transmit to I2C Master + \param[in] num Number of data bytes to transmit + \return \ref execution_status + + \fn int32_t ARM_I2C_SlaveReceive (uint8_t *data, uint32_t num) + \brief Start receiving data as I2C Slave. + \param[out] data Pointer to buffer for data to receive from I2C Master + \param[in] num Number of data bytes to receive + \return \ref execution_status + + \fn int32_t ARM_I2C_GetDataCount (void) + \brief Get transferred data count. + \return number of data bytes transferred; -1 when Slave is not addressed by Master + + \fn int32_t ARM_I2C_Control (uint32_t control, uint32_t arg) + \brief Control I2C Interface. + \param[in] control Operation + \param[in] arg Argument of operation (optional) + \return \ref execution_status + + \fn ARM_I2C_STATUS ARM_I2C_GetStatus (void) + \brief Get I2C status. + \return I2C status \ref ARM_I2C_STATUS + + \fn void ARM_I2C_SignalEvent (uint32_t event) + \brief Signal I2C Events. + \param[in] event \ref I2C_events notification mask +*/ + +typedef void (*ARM_I2C_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_I2C_SignalEvent : Signal I2C Event. + + +/** +\brief I2C Driver Capabilities. +*/ +typedef struct _ARM_I2C_CAPABILITIES { + uint32_t address_10_bit : 1; ///< supports 10-bit addressing +} ARM_I2C_CAPABILITIES; + + +/** +\brief Access structure of the I2C Driver. +*/ +typedef struct _ARM_DRIVER_I2C { + ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_I2C_GetVersion : Get driver version. + ARM_I2C_CAPABILITIES (*GetCapabilities)(void); ///< Pointer to \ref ARM_I2C_GetCapabilities : Get driver capabilities. + int32_t (*Initialize) (ARM_I2C_SignalEvent_t cb_event); ///< Pointer to \ref ARM_I2C_Initialize : Initialize I2C Interface. + int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_I2C_Uninitialize : De-initialize I2C Interface. + int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_I2C_PowerControl : Control I2C Interface Power. + int32_t (*MasterTransmit) (uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending); ///< Pointer to \ref ARM_I2C_MasterTransmit : Start transmitting data as I2C Master. + int32_t (*MasterReceive) (uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending); ///< Pointer to \ref ARM_I2C_MasterReceive : Start receiving data as I2C Master. + int32_t (*SlaveTransmit) ( const uint8_t *data, uint32_t num); ///< Pointer to \ref ARM_I2C_SlaveTransmit : Start transmitting data as I2C Slave. + int32_t (*SlaveReceive) ( uint8_t *data, uint32_t num); ///< Pointer to \ref ARM_I2C_SlaveReceive : Start receiving data as I2C Slave. + int32_t (*GetDataCount) (void); ///< Pointer to \ref ARM_I2C_GetDataCount : Get transferred data count. + int32_t (*Control) (uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_I2C_Control : Control I2C Interface. + ARM_I2C_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_I2C_GetStatus : Get I2C status. +} const ARM_DRIVER_I2C; + +#endif /* __DRIVER_I2C_H */ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_SAI.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_SAI.h new file mode 100644 index 000000000..f1d5b3d2d --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_SAI.h @@ -0,0 +1,298 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2013-2014 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * + * $Date: 9. Dec 2014 + * $Revision: V1.00 + * + * Project: SAI (Serial Audio Interface) Driver definitions + * -------------------------------------------------------------------------- */ + +/* History: + * Version 1.00 + * Initial release + */ + +#ifndef __DRIVER_SAI_H +#define __DRIVER_SAI_H + +#include "Driver_Common.h" + +#define ARM_SAI_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,00) /* API version */ + + +/****** SAI Control Codes *****/ + +#define ARM_SAI_CONTROL_Msk (0xFFU) +#define ARM_SAI_CONFIGURE_TX (0x01U) ///< Configure Transmitter; arg1 and arg2 provide additional configuration +#define ARM_SAI_CONFIGURE_RX (0x02U) ///< Configure Receiver; arg1 and arg2 provide additional configuration +#define ARM_SAI_CONTROL_TX (0x03U) ///< Control Transmitter; arg1.0: 0=disable (default), 1=enable; arg1.1: mute +#define ARM_SAI_CONTROL_RX (0x04U) ///< Control Receiver; arg1.0: 0=disable (default), 1=enable +#define ARM_SAI_MASK_SLOTS_TX (0x05U) ///< Mask Transmitter slots; arg1 = mask (bit: 0=active, 1=inactive); all configured slots are active by default +#define ARM_SAI_MASK_SLOTS_RX (0x06U) ///< Mask Receiver slots; arg1 = mask (bit: 0=active, 1=inactive); all configured slots are active by default +#define ARM_SAI_ABORT_SEND (0x07U) ///< Abort \ref ARM_SAI_Send +#define ARM_SAI_ABORT_RECEIVE (0x08U) ///< Abort \ref ARM_SAI_Receive + +/*----- SAI Control Codes: Configuration Parameters: Mode -----*/ +#define ARM_SAI_MODE_Pos 8 +#define ARM_SAI_MODE_Msk (1U << ARM_SAI_MODE_Pos) +#define ARM_SAI_MODE_MASTER (1U << ARM_SAI_MODE_Pos) ///< Master Mode +#define ARM_SAI_MODE_SLAVE (0U << ARM_SAI_MODE_Pos) ///< Slave Mode (default) + +/*----- SAI Control Codes: Configuration Parameters: Synchronization -----*/ +#define ARM_SAI_SYNCHRONIZATION_Pos 9 +#define ARM_SAI_SYNCHRONIZATION_Msk (1U << ARM_SAI_SYNCHRONIZATION_Pos) +#define ARM_SAI_ASYNCHRONOUS (0U << ARM_SAI_SYNCHRONIZATION_Pos) ///< Asynchronous (default) +#define ARM_SAI_SYNCHRONOUS (1U << ARM_SAI_SYNCHRONIZATION_Pos) ///< Synchronous + +/*----- SAI Control Codes: Configuration Parameters: Protocol -----*/ +#define ARM_SAI_PROTOCOL_Pos 10 +#define ARM_SAI_PROTOCOL_Msk (7U << ARM_SAI_PROTOCOL_Pos) +#define ARM_SAI_PROTOCOL_USER (0U << ARM_SAI_PROTOCOL_Pos) ///< User defined (default) +#define ARM_SAI_PROTOCOL_I2S (1U << ARM_SAI_PROTOCOL_Pos) ///< I2S +#define ARM_SAI_PROTOCOL_MSB_JUSTIFIED (2U << ARM_SAI_PROTOCOL_Pos) ///< MSB (left) justified +#define ARM_SAI_PROTOCOL_LSB_JUSTIFIED (3U << ARM_SAI_PROTOCOL_Pos) ///< LSB (right) justified +#define ARM_SAI_PROTOCOL_PCM_SHORT (4U << ARM_SAI_PROTOCOL_Pos) ///< PCM with short frame +#define ARM_SAI_PROTOCOL_PCM_LONG (5U << ARM_SAI_PROTOCOL_Pos) ///< PCM with long frame +#define ARM_SAI_PROTOCOL_AC97 (6U << ARM_SAI_PROTOCOL_Pos) ///< AC'97 + +/*----- SAI Control Codes: Configuration Parameters: Data Size -----*/ +#define ARM_SAI_DATA_SIZE_Pos 13 +#define ARM_SAI_DATA_SIZE_Msk (0x1FU << ARM_SAI_DATA_SIZE_Pos) +#define ARM_SAI_DATA_SIZE(n) ((((n)-1)&0x1FU) << ARM_SAI_DATA_SIZE_Pos) ///< Data size in bits (8..32) + +/*----- SAI Control Codes: Configuration Parameters: Bit Order -----*/ +#define ARM_SAI_BIT_ORDER_Pos 18 +#define ARM_SAI_BIT_ORDER_Msk (1U << ARM_SAI_BIT_ORDER_Pos) +#define ARM_SAI_MSB_FIRST (0U << ARM_SAI_BIT_ORDER_Pos) ///< Data is transferred with MSB first (default) +#define ARM_SAI_LSB_FIRST (1U << ARM_SAI_BIT_ORDER_Pos) ///< Data is transferred with LSB first; User Protocol only (ignored otherwise) + +/*----- SAI Control Codes: Configuration Parameters: Mono Mode -----*/ +#define ARM_SAI_MONO_MODE (1U << 19) ///< Mono Mode (only for I2S, MSB/LSB justified) + +/*----- SAI Control Codes:Configuration Parameters: Companding -----*/ +#define ARM_SAI_COMPANDING_Pos 20 +#define ARM_SAI_COMPANDING_Msk (3U << ARM_SAI_COMPANDING_Pos) +#define ARM_SAI_COMPANDING_NONE (0U << ARM_SAI_COMPANDING_Pos) ///< No compading (default) +#define ARM_SAI_COMPANDING_A_LAW (2U << ARM_SAI_COMPANDING_Pos) ///< A-Law companding +#define ARM_SAI_COMPANDING_U_LAW (3U << ARM_SAI_COMPANDING_Pos) ///< u-Law companding + +/*----- SAI Control Codes: Configuration Parameters: Clock Polarity -----*/ +#define ARM_SAI_CLOCK_POLARITY_Pos 23 +#define ARM_SAI_CLOCK_POLARITY_Msk (1U << ARM_SAI_CLOCK_POLARITY_Pos) +#define ARM_SAI_CLOCK_POLARITY_0 (0U << ARM_SAI_CLOCK_POLARITY_Pos) ///< Drive on falling edge, Capture on rising edge (default) +#define ARM_SAI_CLOCK_POLARITY_1 (1U << ARM_SAI_CLOCK_POLARITY_Pos) ///< Drive on rising edge, Capture on falling edge + +/*----- SAI Control Codes: Configuration Parameters: Master Clock Pin -----*/ +#define ARM_SAI_MCLK_PIN_Pos 24 +#define ARM_SAI_MCLK_PIN_Msk (3U << ARM_SAI_MCLK_PIN_Pos) +#define ARM_SAI_MCLK_PIN_INACTIVE (0U << ARM_SAI_MCLK_PIN_Pos) ///< MCLK not used (default) +#define ARM_SAI_MCLK_PIN_OUTPUT (1U << ARM_SAI_MCLK_PIN_Pos) ///< MCLK is output (Master only) +#define ARM_SAI_MCLK_PIN_INPUT (2U << ARM_SAI_MCLK_PIN_Pos) ///< MCLK is input (Master only) + + +/****** SAI Configuration (arg1) *****/ + +/*----- SAI Configuration (arg1): Frame Length -----*/ +#define ARM_SAI_FRAME_LENGTH_Pos 0 +#define ARM_SAI_FRAME_LENGTH_Msk (0x3FFU << ARM_SAI_FRAME_LENGTH_Pos) +#define ARM_SAI_FRAME_LENGTH(n) ((((n)-1)&0x3FFU) << ARM_SAI_FRAME_LENGTH_Pos) ///< Frame length in bits (8..1024); default depends on protocol and data + +/*----- SAI Configuration (arg1): Frame Sync Width -----*/ +#define ARM_SAI_FRAME_SYNC_WIDTH_Pos 10 +#define ARM_SAI_FRAME_SYNC_WIDTH_Msk (0xFFU << ARM_SAI_FRAME_SYNC_WIDTH_Pos) +#define ARM_SAI_FRAME_SYNC_WIDTH(n) ((((n)-1)&0xFFU) << ARM_SAI_FRAME_SYNC_WIDTH_Pos) ///< Frame Sync width in bits (1..256); default=1; User Protocol only (ignored otherwise) + +/*----- SAI Configuration (arg1): Frame Sync Polarity -----*/ +#define ARM_SAI_FRAME_SYNC_POLARITY_Pos 18 +#define ARM_SAI_FRAME_SYNC_POLARITY_Msk (1U << ARM_SAI_FRAME_SYNC_POLARITY_Pos) +#define ARM_SAI_FRAME_SYNC_POLARITY_HIGH (0U << ARM_SAI_FRAME_SYNC_POLARITY_Pos) ///< Frame Sync is active high (default); User Protocol only (ignored otherwise) +#define ARM_SAI_FRAME_SYNC_POLARITY_LOW (1U << ARM_SAI_FRAME_SYNC_POLARITY_Pos) ///< Frame Sync is active low; User Protocol only (ignored otherwise) + +/*----- SAI Configuration (arg1): Frame Sync Early -----*/ +#define ARM_SAI_FRAME_SYNC_EARLY (1U << 19) ///< Frame Sync one bit before the first bit of the frame; User Protocol only (ignored otherwise) + +/*----- SAI Configuration (arg1): Slot Count -----*/ +#define ARM_SAI_SLOT_COUNT_Pos 20 +#define ARM_SAI_SLOT_COUNT_Msk (0x1FU << ARM_SAI_SLOT_COUNT_Pos) +#define ARM_SAI_SLOT_COUNT(n) ((((n)-1)&0x1FU) << ARM_SAI_SLOT_COUNT_Pos) ///< Number of slots in frame (1..32); default=1; User Protocol only (ignored otherwise) + +/*----- SAI Configuration (arg1): Slot Size -----*/ +#define ARM_SAI_SLOT_SIZE_Pos 25 +#define ARM_SAI_SLOT_SIZE_Msk (3U << ARM_SAI_SLOT_SIZE_Pos) +#define ARM_SAI_SLOT_SIZE_DEFAULT (0U << ARM_SAI_SLOT_SIZE_Pos) ///< Slot size is equal to data size (default) +#define ARM_SAI_SLOT_SIZE_16 (1U << ARM_SAI_SLOT_SIZE_Pos) ///< Slot size = 16 bits; User Protocol only (ignored otherwise) +#define ARM_SAI_SLOT_SIZE_32 (3U << ARM_SAI_SLOT_SIZE_Pos) ///< Slot size = 32 bits; User Protocol only (ignored otherwise) + +/*----- SAI Configuration (arg1): Slot Offset -----*/ +#define ARM_SAI_SLOT_OFFSET_Pos 27 +#define ARM_SAI_SLOT_OFFSET_Msk (0x1FU << ARM_SAI_SLOT_OFFSET_Pos) +#define ARM_SAI_SLOT_OFFSET(n) (((n)&0x1FU) << ARM_SAI_SLOT_OFFSET_Pos) ///< Offset of first data bit in slot (0..31); default=0; User Protocol only (ignored otherwise) + +/****** SAI Configuration (arg2) *****/ + +/*----- SAI Control Codes: Configuration Parameters: Audio Frequency (Master only) -----*/ +#define ARM_SAI_AUDIO_FREQ_Msk (0x0FFFFFU) ///< Audio frequency mask + +/*----- SAI Control Codes: Configuration Parameters: Master Clock Prescaler (Master only and MCLK Pin) -----*/ +#define ARM_SAI_MCLK_PRESCALER_Pos 20 +#define ARM_SAI_MCLK_PRESCALER_Msk (0xFFFU << ARM_SAI_MCLK_PRESCALER_Pos) +#define ARM_SAI_MCLK_PRESCALER(n) ((((n)-1)&0xFFFU) << ARM_SAI_MCLK_PRESCALER_Pos) ///< MCLK prescaler; Audio_frequency = MCLK/n; n = 1..4096 (default=1) + + +/****** SAI specific error codes *****/ +#define ARM_SAI_ERROR_SYNCHRONIZATION (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< Specified Synchronization not supported +#define ARM_SAI_ERROR_PROTOCOL (ARM_DRIVER_ERROR_SPECIFIC - 2) ///< Specified Protocol not supported +#define ARM_SAI_ERROR_DATA_SIZE (ARM_DRIVER_ERROR_SPECIFIC - 3) ///< Specified Data size not supported +#define ARM_SAI_ERROR_BIT_ORDER (ARM_DRIVER_ERROR_SPECIFIC - 4) ///< Specified Bit order not supported +#define ARM_SAI_ERROR_MONO_MODE (ARM_DRIVER_ERROR_SPECIFIC - 5) ///< Specified Mono mode not supported +#define ARM_SAI_ERROR_COMPANDING (ARM_DRIVER_ERROR_SPECIFIC - 6) ///< Specified Companding not supported +#define ARM_SAI_ERROR_CLOCK_POLARITY (ARM_DRIVER_ERROR_SPECIFIC - 7) ///< Specified Clock polarity not supported +#define ARM_SAI_ERROR_AUDIO_FREQ (ARM_DRIVER_ERROR_SPECIFIC - 8) ///< Specified Audio frequency not supported +#define ARM_SAI_ERROR_MCLK_PIN (ARM_DRIVER_ERROR_SPECIFIC - 9) ///< Specified MCLK Pin setting not supported +#define ARM_SAI_ERROR_MCLK_PRESCALER (ARM_DRIVER_ERROR_SPECIFIC - 10) ///< Specified MCLK Prescaler not supported +#define ARM_SAI_ERROR_FRAME_LENGHT (ARM_DRIVER_ERROR_SPECIFIC - 11) ///< Specified Frame length not supported +#define ARM_SAI_ERROR_FRAME_SYNC_WIDTH (ARM_DRIVER_ERROR_SPECIFIC - 12) ///< Specified Frame Sync width not supported +#define ARM_SAI_ERROR_FRAME_SYNC_POLARITY (ARM_DRIVER_ERROR_SPECIFIC - 13) ///< Specified Frame Sync polarity not supported +#define ARM_SAI_ERROR_FRAME_SYNC_EARLY (ARM_DRIVER_ERROR_SPECIFIC - 14) ///< Specified Frame Sync early not supported +#define ARM_SAI_ERROR_SLOT_COUNT (ARM_DRIVER_ERROR_SPECIFIC - 15) ///< Specified Slot count not supported +#define ARM_SAI_ERROR_SLOT_SIZE (ARM_DRIVER_ERROR_SPECIFIC - 16) ///< Specified Slot size not supported +#define ARM_SAI_ERROR_SLOT_OFFESET (ARM_DRIVER_ERROR_SPECIFIC - 17) ///< Specified Slot offset not supported + + +/** +\brief SAI Status +*/ +typedef struct _ARM_SAI_STATUS { + uint32_t tx_busy : 1; ///< Transmitter busy flag + uint32_t rx_busy : 1; ///< Receiver busy flag + uint32_t tx_underflow : 1; ///< Transmit data underflow detected (cleared on start of next send operation) + uint32_t rx_overflow : 1; ///< Receive data overflow detected (cleared on start of next receive operation) + uint32_t frame_error : 1; ///< Sync Frame error detected (cleared on start of next send/receive operation) +} ARM_SAI_STATUS; + + +/****** SAI Event *****/ +#define ARM_SAI_EVENT_SEND_COMPLETE (1U << 0) ///< Send completed +#define ARM_SAI_EVENT_RECEIVE_COMPLETE (1U << 1) ///< Receive completed +#define ARM_SAI_EVENT_TX_UNDERFLOW (1U << 2) ///< Transmit data not available +#define ARM_SAI_EVENT_RX_OVERFLOW (1U << 3) ///< Receive data overflow +#define ARM_SAI_EVENT_FRAME_ERROR (1U << 4) ///< Sync Frame error in Slave mode (optional) + + +// Function documentation +/** + \fn ARM_DRIVER_VERSION ARM_SAI_GetVersion (void) + \brief Get driver version. + \return \ref ARM_DRIVER_VERSION + + \fn ARM_SAI_CAPABILITIES ARM_SAI_GetCapabilities (void) + \brief Get driver capabilities. + \return \ref ARM_SAI_CAPABILITIES + + \fn int32_t ARM_SAI_Initialize (ARM_SAI_SignalEvent_t cb_event) + \brief Initialize SAI Interface. + \param[in] cb_event Pointer to \ref ARM_SAI_SignalEvent + \return \ref execution_status + + \fn int32_t ARM_SAI_Uninitialize (void) + \brief De-initialize SAI Interface. + \return \ref execution_status + + \fn int32_t ARM_SAI_PowerControl (ARM_POWER_STATE state) + \brief Control SAI Interface Power. + \param[in] state Power state + \return \ref execution_status + + \fn int32_t ARM_SAI_Send (const void *data, uint32_t num) + \brief Start sending data to SAI transmitter. + \param[in] data Pointer to buffer with data to send to SAI transmitter + \param[in] num Number of data items to send + \return \ref execution_status + + \fn int32_t ARM_SAI_Receive (void *data, uint32_t num) + \brief Start receiving data from SAI receiver. + \param[out] data Pointer to buffer for data to receive from SAI receiver + \param[in] num Number of data items to receive + \return \ref execution_status + + \fn uint32_t ARM_SAI_GetTxCount (void) + \brief Get transmitted data count. + \return number of data items transmitted + + \fn uint32_t ARM_SAI_GetRxCount (void) + \brief Get received data count. + \return number of data items received + + \fn int32_t ARM_SAI_Control (uint32_t control, uint32_t arg1, uint32_t arg2) + \brief Control SAI Interface. + \param[in] control Operation + \param[in] arg1 Argument 1 of operation (optional) + \param[in] arg2 Argument 2 of operation (optional) + \return common \ref execution_status and driver specific \ref sai_execution_status + + \fn ARM_SAI_STATUS ARM_SAI_GetStatus (void) + \brief Get SAI status. + \return SAI status \ref ARM_SAI_STATUS + + \fn void ARM_SAI_SignalEvent (uint32_t event) + \brief Signal SAI Events. + \param[in] event \ref SAI_events notification mask + \return none +*/ + +typedef void (*ARM_SAI_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_SAI_SignalEvent : Signal SAI Event. + + +/** +\brief SAI Driver Capabilities. +*/ +typedef struct _ARM_SAI_CAPABILITIES { + uint32_t asynchronous : 1; ///< supports asynchronous Transmit/Receive + uint32_t synchronous : 1; ///< supports synchronous Transmit/Receive + uint32_t protocol_user : 1; ///< supports user defined Protocol + uint32_t protocol_i2s : 1; ///< supports I2S Protocol + uint32_t protocol_justified : 1; ///< supports MSB/LSB justified Protocol + uint32_t protocol_pcm : 1; ///< supports PCM short/long frame Protocol + uint32_t protocol_ac97 : 1; ///< supports AC'97 Protocol + uint32_t mono_mode : 1; ///< supports Mono mode + uint32_t companding : 1; ///< supports Companding + uint32_t mclk_pin : 1; ///< supports MCLK (Master Clock) pin + uint32_t event_frame_error : 1; ///< supports Frame error event: \ref ARM_SAI_EVENT_FRAME_ERROR +} ARM_SAI_CAPABILITIES; + + +/** +\brief Access structure of the SAI Driver. +*/ +typedef struct _ARM_DRIVER_SAI { + ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_SAI_GetVersion : Get driver version. + ARM_SAI_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_SAI_GetCapabilities : Get driver capabilities. + int32_t (*Initialize) (ARM_SAI_SignalEvent_t cb_event); ///< Pointer to \ref ARM_SAI_Initialize : Initialize SAI Interface. + int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_SAI_Uninitialize : De-initialize SAI Interface. + int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_SAI_PowerControl : Control SAI Interface Power. + int32_t (*Send) (const void *data, uint32_t num); ///< Pointer to \ref ARM_SAI_Send : Start sending data to SAI Interface. + int32_t (*Receive) ( void *data, uint32_t num); ///< Pointer to \ref ARM_SAI_Receive : Start receiving data from SAI Interface. + uint32_t (*GetTxCount) (void); ///< Pointer to \ref ARM_SAI_GetTxCount : Get transmitted data count. + uint32_t (*GetRxCount) (void); ///< Pointer to \ref ARM_SAI_GetRxCount : Get received data count. + int32_t (*Control) (uint32_t control, uint32_t arg1, uint32_t arg2); ///< Pointer to \ref ARM_SAI_Control : Control SAI Interface. + ARM_SAI_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_SAI_GetStatus : Get SAI status. +} const ARM_DRIVER_SAI; + +#endif /* __DRIVER_SAI_H */ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_SPI.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_SPI.h new file mode 100644 index 000000000..b55381cee --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_SPI.h @@ -0,0 +1,238 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2013-2014 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * + * $Date: 17. Apr 2014 + * $Revision: V2.01 + * + * Project: SPI (Serial Peripheral Interface) Driver definitions + * -------------------------------------------------------------------------- */ + +/* History: + * Version 2.01 + * Renamed status flag "tx_rx_busy" to "busy" + * Version 2.00 + * New simplified driver: + * complexity moved to upper layer (especially data handling) + * more unified API for different communication interfaces + * Added: + * Slave Mode + * Half-duplex Modes + * Configurable number of data bits + * Support for TI Mode and Microwire + * Changed prefix ARM_DRV -> ARM_DRIVER + * Version 1.10 + * Namespace prefix ARM_ added + * Version 1.01 + * Added "send_done_event" to Capabilities + * Version 1.00 + * Initial release + */ + +#ifndef __DRIVER_SPI_H +#define __DRIVER_SPI_H + +#include "Driver_Common.h" + +#define ARM_SPI_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,00) /* API version */ + + +/****** SPI Control Codes *****/ + +#define ARM_SPI_CONTROL_Pos 0 +#define ARM_SPI_CONTROL_Msk (0xFFUL << ARM_SPI_CONTROL_Pos) + +/*----- SPI Control Codes: Mode -----*/ +#define ARM_SPI_MODE_INACTIVE (0x00UL << ARM_SPI_CONTROL_Pos) ///< SPI Inactive +#define ARM_SPI_MODE_MASTER (0x01UL << ARM_SPI_CONTROL_Pos) ///< SPI Master (Output on MOSI, Input on MISO); arg = Bus Speed in bps +#define ARM_SPI_MODE_SLAVE (0x02UL << ARM_SPI_CONTROL_Pos) ///< SPI Slave (Output on MISO, Input on MOSI) +#define ARM_SPI_MODE_MASTER_SIMPLEX (0x03UL << ARM_SPI_CONTROL_Pos) ///< SPI Master (Output/Input on MOSI); arg = Bus Speed in bps +#define ARM_SPI_MODE_SLAVE_SIMPLEX (0x04UL << ARM_SPI_CONTROL_Pos) ///< SPI Slave (Output/Input on MISO) + +/*----- SPI Control Codes: Mode Parameters: Frame Format -----*/ +#define ARM_SPI_FRAME_FORMAT_Pos 8 +#define ARM_SPI_FRAME_FORMAT_Msk (7UL << ARM_SPI_FRAME_FORMAT_Pos) +#define ARM_SPI_CPOL0_CPHA0 (0UL << ARM_SPI_FRAME_FORMAT_Pos) ///< Clock Polarity 0, Clock Phase 0 (default) +#define ARM_SPI_CPOL0_CPHA1 (1UL << ARM_SPI_FRAME_FORMAT_Pos) ///< Clock Polarity 0, Clock Phase 1 +#define ARM_SPI_CPOL1_CPHA0 (2UL << ARM_SPI_FRAME_FORMAT_Pos) ///< Clock Polarity 1, Clock Phase 0 +#define ARM_SPI_CPOL1_CPHA1 (3UL << ARM_SPI_FRAME_FORMAT_Pos) ///< Clock Polarity 1, Clock Phase 1 +#define ARM_SPI_TI_SSI (4UL << ARM_SPI_FRAME_FORMAT_Pos) ///< Texas Instruments Frame Format +#define ARM_SPI_MICROWIRE (5UL << ARM_SPI_FRAME_FORMAT_Pos) ///< National Microwire Frame Format + +/*----- SPI Control Codes: Mode Parameters: Data Bits -----*/ +#define ARM_SPI_DATA_BITS_Pos 12 +#define ARM_SPI_DATA_BITS_Msk (0x3FUL << ARM_SPI_DATA_BITS_Pos) +#define ARM_SPI_DATA_BITS(n) (((n) & 0x3F) << ARM_SPI_DATA_BITS_Pos) ///< Number of Data bits + +/*----- SPI Control Codes: Mode Parameters: Bit Order -----*/ +#define ARM_SPI_BIT_ORDER_Pos 18 +#define ARM_SPI_BIT_ORDER_Msk (1UL << ARM_SPI_BIT_ORDER_Pos) +#define ARM_SPI_MSB_LSB (0UL << ARM_SPI_BIT_ORDER_Pos) ///< SPI Bit order from MSB to LSB (default) +#define ARM_SPI_LSB_MSB (1UL << ARM_SPI_BIT_ORDER_Pos) ///< SPI Bit order from LSB to MSB + +/*----- SPI Control Codes: Mode Parameters: Slave Select Mode -----*/ +#define ARM_SPI_SS_MASTER_MODE_Pos 19 +#define ARM_SPI_SS_MASTER_MODE_Msk (3UL << ARM_SPI_SS_MASTER_MODE_Pos) +#define ARM_SPI_SS_MASTER_UNUSED (0UL << ARM_SPI_SS_MASTER_MODE_Pos) ///< SPI Slave Select when Master: Not used (default) +#define ARM_SPI_SS_MASTER_SW (1UL << ARM_SPI_SS_MASTER_MODE_Pos) ///< SPI Slave Select when Master: Software controlled +#define ARM_SPI_SS_MASTER_HW_OUTPUT (2UL << ARM_SPI_SS_MASTER_MODE_Pos) ///< SPI Slave Select when Master: Hardware controlled Output +#define ARM_SPI_SS_MASTER_HW_INPUT (3UL << ARM_SPI_SS_MASTER_MODE_Pos) ///< SPI Slave Select when Master: Hardware monitored Input +#define ARM_SPI_SS_SLAVE_MODE_Pos 21 +#define ARM_SPI_SS_SLAVE_MODE_Msk (1UL << ARM_SPI_SS_SLAVE_MODE_Pos) +#define ARM_SPI_SS_SLAVE_HW (0UL << ARM_SPI_SS_SLAVE_MODE_Pos) ///< SPI Slave Select when Slave: Hardware monitored (default) +#define ARM_SPI_SS_SLAVE_SW (1UL << ARM_SPI_SS_SLAVE_MODE_Pos) ///< SPI Slave Select when Slave: Software controlled + + +/*----- SPI Control Codes: Miscellaneous Controls -----*/ +#define ARM_SPI_SET_BUS_SPEED (0x10UL << ARM_SPI_CONTROL_Pos) ///< Set Bus Speed in bps; arg = value +#define ARM_SPI_GET_BUS_SPEED (0x11UL << ARM_SPI_CONTROL_Pos) ///< Get Bus Speed in bps +#define ARM_SPI_SET_DEFAULT_TX_VALUE (0x12UL << ARM_SPI_CONTROL_Pos) ///< Set default Transmit value; arg = value +#define ARM_SPI_CONTROL_SS (0x13UL << ARM_SPI_CONTROL_Pos) ///< Control Slave Select; arg: 0=inactive, 1=active +#define ARM_SPI_ABORT_TRANSFER (0x14UL << ARM_SPI_CONTROL_Pos) ///< Abort current data transfer + + +/****** SPI Slave Select Signal definitions *****/ +#define ARM_SPI_SS_INACTIVE 0 ///< SPI Slave Select Signal Inactive +#define ARM_SPI_SS_ACTIVE 1 ///< SPI Slave Select Signal Active + + +/****** SPI specific error codes *****/ +#define ARM_SPI_ERROR_MODE (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< Specified Mode not supported +#define ARM_SPI_ERROR_FRAME_FORMAT (ARM_DRIVER_ERROR_SPECIFIC - 2) ///< Specified Frame Format not supported +#define ARM_SPI_ERROR_DATA_BITS (ARM_DRIVER_ERROR_SPECIFIC - 3) ///< Specified number of Data bits not supported +#define ARM_SPI_ERROR_BIT_ORDER (ARM_DRIVER_ERROR_SPECIFIC - 4) ///< Specified Bit order not supported +#define ARM_SPI_ERROR_SS_MODE (ARM_DRIVER_ERROR_SPECIFIC - 5) ///< Specified Slave Select Mode not supported + + +/** +\brief SPI Status +*/ +typedef struct _ARM_SPI_STATUS { + uint32_t busy : 1; ///< Transmitter/Receiver busy flag + uint32_t data_lost : 1; ///< Data lost: Receive overflow / Transmit underflow (cleared on start of transfer operation) + uint32_t mode_fault : 1; ///< Mode fault detected; optional (cleared on start of transfer operation) +} ARM_SPI_STATUS; + + +/****** SPI Event *****/ +#define ARM_SPI_EVENT_TRANSFER_COMPLETE (1UL << 0) ///< Data Transfer completed +#define ARM_SPI_EVENT_DATA_LOST (1UL << 1) ///< Data lost: Receive overflow / Transmit underflow +#define ARM_SPI_EVENT_MODE_FAULT (1UL << 2) ///< Master Mode Fault (SS deactivated when Master) +#define ARM_SPI_EVENT_SEND_COMPLETE (1UL << 3) ///< Master Mode Fault (SS deactivated when Master) + + +// Function documentation +/** + \fn ARM_DRIVER_VERSION ARM_SPI_GetVersion (void) + \brief Get driver version. + \return \ref ARM_DRIVER_VERSION + + \fn ARM_SPI_CAPABILITIES ARM_SPI_GetCapabilities (void) + \brief Get driver capabilities. + \return \ref ARM_SPI_CAPABILITIES + + \fn int32_t ARM_SPI_Initialize (ARM_SPI_SignalEvent_t cb_event) + \brief Initialize SPI Interface. + \param[in] cb_event Pointer to \ref ARM_SPI_SignalEvent + \return \ref execution_status + + \fn int32_t ARM_SPI_Uninitialize (void) + \brief De-initialize SPI Interface. + \return \ref execution_status + + \fn int32_t ARM_SPI_PowerControl (ARM_POWER_STATE state) + \brief Control SPI Interface Power. + \param[in] state Power state + \return \ref execution_status + + \fn int32_t ARM_SPI_Send (const void *data, uint32_t num) + \brief Start sending data to SPI transmitter. + \param[in] data Pointer to buffer with data to send to SPI transmitter + \param[in] num Number of data items to send + \return \ref execution_status + + \fn int32_t ARM_SPI_Receive (void *data, uint32_t num) + \brief Start receiving data from SPI receiver. + \param[out] data Pointer to buffer for data to receive from SPI receiver + \param[in] num Number of data items to receive + \return \ref execution_status + + \fn int32_t ARM_SPI_Transfer (const void *data_out, + void *data_in, + uint32_t num) + \brief Start sending/receiving data to/from SPI transmitter/receiver. + \param[in] data_out Pointer to buffer with data to send to SPI transmitter + \param[out] data_in Pointer to buffer for data to receive from SPI receiver + \param[in] num Number of data items to transfer + \return \ref execution_status + + \fn uint32_t ARM_SPI_GetDataCount (void) + \brief Get transferred data count. + \return number of data items transferred + + \fn int32_t ARM_SPI_Control (uint32_t control, uint32_t arg) + \brief Control SPI Interface. + \param[in] control Operation + \param[in] arg Argument of operation (optional) + \return common \ref execution_status and driver specific \ref spi_execution_status + + \fn ARM_SPI_STATUS ARM_SPI_GetStatus (void) + \brief Get SPI status. + \return SPI status \ref ARM_SPI_STATUS + + \fn void ARM_SPI_SignalEvent (uint32_t event) + \brief Signal SPI Events. + \param[in] event \ref SPI_events notification mask + \return none +*/ + +typedef void (*ARM_SPI_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_SPI_SignalEvent : Signal SPI Event. + + +/** +\brief SPI Driver Capabilities. +*/ +typedef struct _ARM_SPI_CAPABILITIES { + uint32_t simplex : 1; ///< supports Simplex Mode (Master and Slave) + uint32_t ti_ssi : 1; ///< supports TI Synchronous Serial Interface + uint32_t microwire : 1; ///< supports Microwire Interface + uint32_t event_mode_fault : 1; ///< Signal Mode Fault event: \ref ARM_SPI_EVENT_MODE_FAULT +} ARM_SPI_CAPABILITIES; + + +/** +\brief Access structure of the SPI Driver. +*/ +typedef struct _ARM_DRIVER_SPI { + ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_SPI_GetVersion : Get driver version. + ARM_SPI_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_SPI_GetCapabilities : Get driver capabilities. + int32_t (*Initialize) (ARM_SPI_SignalEvent_t cb_event); ///< Pointer to \ref ARM_SPI_Initialize : Initialize SPI Interface. + int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_SPI_Uninitialize : De-initialize SPI Interface. + int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_SPI_PowerControl : Control SPI Interface Power. + int32_t (*Send) (const void *data, uint32_t num); ///< Pointer to \ref ARM_SPI_Send : Start sending data to SPI Interface. + int32_t (*Receive) ( void *data, uint32_t num); ///< Pointer to \ref ARM_SPI_Receive : Start receiving data from SPI Interface. + int32_t (*Transfer) (const void *data_out, + void *data_in, + uint32_t num); ///< Pointer to \ref ARM_SPI_Transfer : Start sending/receiving data to/from SPI. + uint32_t (*GetDataCount) (void); ///< Pointer to \ref ARM_SPI_GetDataCount : Get transferred data count. + int32_t (*Control) (uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_SPI_Control : Control SPI Interface. + ARM_SPI_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_SPI_GetStatus : Get SPI status. +} const ARM_DRIVER_SPI; + +#endif /* __DRIVER_SPI_H */ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_USART.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_USART.h new file mode 100644 index 000000000..5b3b519f2 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_USART.h @@ -0,0 +1,330 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2013-2014 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * + * $Date: 24. Nov 2014 + * $Revision: V2.02 + * + * Project: USART (Universal Synchronous Asynchronous Receiver Transmitter) + * Driver definitions + * -------------------------------------------------------------------------- */ + +/* History: + * Version 2.02 + * Corrected ARM_USART_CPOL_Pos and ARM_USART_CPHA_Pos definitions + * Version 2.01 + * Removed optional argument parameter from Signal Event + * Version 2.00 + * New simplified driver: + * complexity moved to upper layer (especially data handling) + * more unified API for different communication interfaces + * renamed driver UART -> USART (Asynchronous & Synchronous) + * Added modes: + * Synchronous + * Single-wire + * IrDA + * Smart Card + * Changed prefix ARM_DRV -> ARM_DRIVER + * Version 1.10 + * Namespace prefix ARM_ added + * Version 1.01 + * Added events: + * ARM_UART_EVENT_TX_EMPTY, ARM_UART_EVENT_RX_TIMEOUT + * ARM_UART_EVENT_TX_THRESHOLD, ARM_UART_EVENT_RX_THRESHOLD + * Added functions: SetTxThreshold, SetRxThreshold + * Added "rx_timeout_event" to capabilities + * Version 1.00 + * Initial release + */ + +#ifndef __DRIVER_USART_H +#define __DRIVER_USART_H + +#include "Driver_Common.h" + +#define ARM_USART_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,02) /* API version */ + + +/****** USART Control Codes *****/ + +#define ARM_USART_CONTROL_Pos 0 +#define ARM_USART_CONTROL_Msk (0xFFUL << ARM_USART_CONTROL_Pos) + +/*----- USART Control Codes: Mode -----*/ +#define ARM_USART_MODE_ASYNCHRONOUS (0x01UL << ARM_USART_CONTROL_Pos) ///< UART (Asynchronous); arg = Baudrate +#define ARM_USART_MODE_SYNCHRONOUS_MASTER (0x02UL << ARM_USART_CONTROL_Pos) ///< Synchronous Master (generates clock signal); arg = Baudrate +#define ARM_USART_MODE_SYNCHRONOUS_SLAVE (0x03UL << ARM_USART_CONTROL_Pos) ///< Synchronous Slave (external clock signal) +#define ARM_USART_MODE_SINGLE_WIRE (0x04UL << ARM_USART_CONTROL_Pos) ///< UART Single-wire (half-duplex); arg = Baudrate +#define ARM_USART_MODE_IRDA (0x05UL << ARM_USART_CONTROL_Pos) ///< UART IrDA; arg = Baudrate +#define ARM_USART_MODE_SMART_CARD (0x06UL << ARM_USART_CONTROL_Pos) ///< UART Smart Card; arg = Baudrate + +/*----- USART Control Codes: Mode Parameters: Data Bits -----*/ +#define ARM_USART_DATA_BITS_Pos 8 +#define ARM_USART_DATA_BITS_Msk (7UL << ARM_USART_DATA_BITS_Pos) +#define ARM_USART_DATA_BITS_5 (5UL << ARM_USART_DATA_BITS_Pos) ///< 5 Data bits +#define ARM_USART_DATA_BITS_6 (6UL << ARM_USART_DATA_BITS_Pos) ///< 6 Data bit +#define ARM_USART_DATA_BITS_7 (7UL << ARM_USART_DATA_BITS_Pos) ///< 7 Data bits +#define ARM_USART_DATA_BITS_8 (0UL << ARM_USART_DATA_BITS_Pos) ///< 8 Data bits (default) +#define ARM_USART_DATA_BITS_9 (1UL << ARM_USART_DATA_BITS_Pos) ///< 9 Data bits + +/*----- USART Control Codes: Mode Parameters: Parity -----*/ +#define ARM_USART_PARITY_Pos 12 +#define ARM_USART_PARITY_Msk (3UL << ARM_USART_PARITY_Pos) +#define ARM_USART_PARITY_NONE (0UL << ARM_USART_PARITY_Pos) ///< No Parity (default) +#define ARM_USART_PARITY_EVEN (1UL << ARM_USART_PARITY_Pos) ///< Even Parity +#define ARM_USART_PARITY_ODD (2UL << ARM_USART_PARITY_Pos) ///< Odd Parity + +/*----- USART Control Codes: Mode Parameters: Stop Bits -----*/ +#define ARM_USART_STOP_BITS_Pos 14 +#define ARM_USART_STOP_BITS_Msk (3UL << ARM_USART_STOP_BITS_Pos) +#define ARM_USART_STOP_BITS_1 (0UL << ARM_USART_STOP_BITS_Pos) ///< 1 Stop bit (default) +#define ARM_USART_STOP_BITS_2 (1UL << ARM_USART_STOP_BITS_Pos) ///< 2 Stop bits +#define ARM_USART_STOP_BITS_1_5 (2UL << ARM_USART_STOP_BITS_Pos) ///< 1.5 Stop bits +#define ARM_USART_STOP_BITS_0_5 (3UL << ARM_USART_STOP_BITS_Pos) ///< 0.5 Stop bits + +/*----- USART Control Codes: Mode Parameters: Flow Control -----*/ +#define ARM_USART_FLOW_CONTROL_Pos 16 +#define ARM_USART_FLOW_CONTROL_Msk (3UL << ARM_USART_FLOW_CONTROL_Pos) +#define ARM_USART_FLOW_CONTROL_NONE (0UL << ARM_USART_FLOW_CONTROL_Pos) ///< No Flow Control (default) +#define ARM_USART_FLOW_CONTROL_RTS (1UL << ARM_USART_FLOW_CONTROL_Pos) ///< RTS Flow Control +#define ARM_USART_FLOW_CONTROL_CTS (2UL << ARM_USART_FLOW_CONTROL_Pos) ///< CTS Flow Control +#define ARM_USART_FLOW_CONTROL_RTS_CTS (3UL << ARM_USART_FLOW_CONTROL_Pos) ///< RTS/CTS Flow Control + +/*----- USART Control Codes: Mode Parameters: Clock Polarity (Synchronous mode) -----*/ +#define ARM_USART_CPOL_Pos 18 +#define ARM_USART_CPOL_Msk (1UL << ARM_USART_CPOL_Pos) +#define ARM_USART_CPOL0 (0UL << ARM_USART_CPOL_Pos) ///< CPOL = 0 (default) +#define ARM_USART_CPOL1 (1UL << ARM_USART_CPOL_Pos) ///< CPOL = 1 + +/*----- USART Control Codes: Mode Parameters: Clock Phase (Synchronous mode) -----*/ +#define ARM_USART_CPHA_Pos 19 +#define ARM_USART_CPHA_Msk (1UL << ARM_USART_CPHA_Pos) +#define ARM_USART_CPHA0 (0UL << ARM_USART_CPHA_Pos) ///< CPHA = 0 (default) +#define ARM_USART_CPHA1 (1UL << ARM_USART_CPHA_Pos) ///< CPHA = 1 + + +/*----- USART Control Codes: Miscellaneous Controls -----*/ +#define ARM_USART_SET_DEFAULT_TX_VALUE (0x10UL << ARM_USART_CONTROL_Pos) ///< Set default Transmit value (Synchronous Receive only); arg = value +#define ARM_USART_SET_IRDA_PULSE (0x11UL << ARM_USART_CONTROL_Pos) ///< Set IrDA Pulse in ns; arg: 0=3/16 of bit period +#define ARM_USART_SET_SMART_CARD_GUARD_TIME (0x12UL << ARM_USART_CONTROL_Pos) ///< Set Smart Card Guard Time; arg = number of bit periods +#define ARM_USART_SET_SMART_CARD_CLOCK (0x13UL << ARM_USART_CONTROL_Pos) ///< Set Smart Card Clock in Hz; arg: 0=Clock not generated +#define ARM_USART_CONTROL_SMART_CARD_NACK (0x14UL << ARM_USART_CONTROL_Pos) ///< Smart Card NACK generation; arg: 0=disabled, 1=enabled +#define ARM_USART_CONTROL_TX (0x15UL << ARM_USART_CONTROL_Pos) ///< Transmitter; arg: 0=disabled, 1=enabled +#define ARM_USART_CONTROL_RX (0x16UL << ARM_USART_CONTROL_Pos) ///< Receiver; arg: 0=disabled, 1=enabled +#define ARM_USART_CONTROL_BREAK (0x17UL << ARM_USART_CONTROL_Pos) ///< Continuous Break transmission; arg: 0=disabled, 1=enabled +#define ARM_USART_ABORT_SEND (0x18UL << ARM_USART_CONTROL_Pos) ///< Abort \ref ARM_USART_Send +#define ARM_USART_ABORT_RECEIVE (0x19UL << ARM_USART_CONTROL_Pos) ///< Abort \ref ARM_USART_Receive +#define ARM_USART_ABORT_TRANSFER (0x1AUL << ARM_USART_CONTROL_Pos) ///< Abort \ref ARM_USART_Transfer + + + +/****** USART specific error codes *****/ +#define ARM_USART_ERROR_MODE (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< Specified Mode not supported +#define ARM_USART_ERROR_BAUDRATE (ARM_DRIVER_ERROR_SPECIFIC - 2) ///< Specified baudrate not supported +#define ARM_USART_ERROR_DATA_BITS (ARM_DRIVER_ERROR_SPECIFIC - 3) ///< Specified number of Data bits not supported +#define ARM_USART_ERROR_PARITY (ARM_DRIVER_ERROR_SPECIFIC - 4) ///< Specified Parity not supported +#define ARM_USART_ERROR_STOP_BITS (ARM_DRIVER_ERROR_SPECIFIC - 5) ///< Specified number of Stop bits not supported +#define ARM_USART_ERROR_FLOW_CONTROL (ARM_DRIVER_ERROR_SPECIFIC - 6) ///< Specified Flow Control not supported +#define ARM_USART_ERROR_CPOL (ARM_DRIVER_ERROR_SPECIFIC - 7) ///< Specified Clock Polarity not supported +#define ARM_USART_ERROR_CPHA (ARM_DRIVER_ERROR_SPECIFIC - 8) ///< Specified Clock Phase not supported + + +/** +\brief USART Status +*/ +typedef struct _ARM_USART_STATUS { + uint32_t tx_busy : 1; ///< Transmitter busy flag + uint32_t rx_busy : 1; ///< Receiver busy flag + uint32_t tx_underflow : 1; ///< Transmit data underflow detected (cleared on start of next send operation) + uint32_t rx_overflow : 1; ///< Receive data overflow detected (cleared on start of next receive operation) + uint32_t rx_break : 1; ///< Break detected on receive (cleared on start of next receive operation) + uint32_t rx_framing_error : 1; ///< Framing error detected on receive (cleared on start of next receive operation) + uint32_t rx_parity_error : 1; ///< Parity error detected on receive (cleared on start of next receive operation) +} ARM_USART_STATUS; + +/** +\brief USART Modem Control +*/ +typedef enum _ARM_USART_MODEM_CONTROL { + ARM_USART_RTS_CLEAR, ///< Deactivate RTS + ARM_USART_RTS_SET, ///< Activate RTS + ARM_USART_DTR_CLEAR, ///< Deactivate DTR + ARM_USART_DTR_SET ///< Activate DTR +} ARM_USART_MODEM_CONTROL; + +/** +\brief USART Modem Status +*/ +typedef struct _ARM_USART_MODEM_STATUS { + uint32_t cts : 1; ///< CTS state: 1=Active, 0=Inactive + uint32_t dsr : 1; ///< DSR state: 1=Active, 0=Inactive + uint32_t dcd : 1; ///< DCD state: 1=Active, 0=Inactive + uint32_t ri : 1; ///< RI state: 1=Active, 0=Inactive +} ARM_USART_MODEM_STATUS; + + +/****** USART Event *****/ +#define ARM_USART_EVENT_SEND_COMPLETE (1UL << 0) ///< Send completed; however USART may still transmit data +#define ARM_USART_EVENT_RECEIVE_COMPLETE (1UL << 1) ///< Receive completed +#define ARM_USART_EVENT_TRANSFER_COMPLETE (1UL << 2) ///< Transfer completed +#define ARM_USART_EVENT_TX_COMPLETE (1UL << 3) ///< Transmit completed (optional) +#define ARM_USART_EVENT_TX_UNDERFLOW (1UL << 4) ///< Transmit data not available (Synchronous Slave) +#define ARM_USART_EVENT_RX_OVERFLOW (1UL << 5) ///< Receive data overflow +#define ARM_USART_EVENT_RX_TIMEOUT (1UL << 6) ///< Receive character timeout (optional) +#define ARM_USART_EVENT_RX_BREAK (1UL << 7) ///< Break detected on receive +#define ARM_USART_EVENT_RX_FRAMING_ERROR (1UL << 8) ///< Framing error detected on receive +#define ARM_USART_EVENT_RX_PARITY_ERROR (1UL << 9) ///< Parity error detected on receive +#define ARM_USART_EVENT_CTS (1UL << 10) ///< CTS state changed (optional) +#define ARM_USART_EVENT_DSR (1UL << 11) ///< DSR state changed (optional) +#define ARM_USART_EVENT_DCD (1UL << 12) ///< DCD state changed (optional) +#define ARM_USART_EVENT_RI (1UL << 13) ///< RI state changed (optional) + + +// Function documentation +/** + \fn ARM_DRIVER_VERSION ARM_USART_GetVersion (void) + \brief Get driver version. + \return \ref ARM_DRIVER_VERSION + + \fn ARM_USART_CAPABILITIES ARM_USART_GetCapabilities (void) + \brief Get driver capabilities + \return \ref ARM_USART_CAPABILITIES + + \fn int32_t ARM_USART_Initialize (ARM_USART_SignalEvent_t cb_event) + \brief Initialize USART Interface. + \param[in] cb_event Pointer to \ref ARM_USART_SignalEvent + \return \ref execution_status + + \fn int32_t ARM_USART_Uninitialize (void) + \brief De-initialize USART Interface. + \return \ref execution_status + + \fn int32_t ARM_USART_PowerControl (ARM_POWER_STATE state) + \brief Control USART Interface Power. + \param[in] state Power state + \return \ref execution_status + + \fn int32_t ARM_USART_Send (const void *data, uint32_t num) + \brief Start sending data to USART transmitter. + \param[in] data Pointer to buffer with data to send to USART transmitter + \param[in] num Number of data items to send + \return \ref execution_status + + \fn int32_t ARM_USART_Receive (void *data, uint32_t num) + \brief Start receiving data from USART receiver. + \param[out] data Pointer to buffer for data to receive from USART receiver + \param[in] num Number of data items to receive + \return \ref execution_status + + \fn int32_t ARM_USART_Transfer (const void *data_out, + void *data_in, + uint32_t num) + \brief Start sending/receiving data to/from USART transmitter/receiver. + \param[in] data_out Pointer to buffer with data to send to USART transmitter + \param[out] data_in Pointer to buffer for data to receive from USART receiver + \param[in] num Number of data items to transfer + \return \ref execution_status + + \fn uint32_t ARM_USART_GetTxCount (void) + \brief Get transmitted data count. + \return number of data items transmitted + + \fn uint32_t ARM_USART_GetRxCount (void) + \brief Get received data count. + \return number of data items received + + \fn int32_t ARM_USART_Control (uint32_t control, uint32_t arg) + \brief Control USART Interface. + \param[in] control Operation + \param[in] arg Argument of operation (optional) + \return common \ref execution_status and driver specific \ref usart_execution_status + + \fn ARM_USART_STATUS ARM_USART_GetStatus (void) + \brief Get USART status. + \return USART status \ref ARM_USART_STATUS + + \fn int32_t ARM_USART_SetModemControl (ARM_USART_MODEM_CONTROL control) + \brief Set USART Modem Control line state. + \param[in] control \ref ARM_USART_MODEM_CONTROL + \return \ref execution_status + + \fn ARM_USART_MODEM_STATUS ARM_USART_GetModemStatus (void) + \brief Get USART Modem Status lines state. + \return modem status \ref ARM_USART_MODEM_STATUS + + \fn void ARM_USART_SignalEvent (uint32_t event) + \brief Signal USART Events. + \param[in] event \ref USART_events notification mask + \return none +*/ + +typedef void (*ARM_USART_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_USART_SignalEvent : Signal USART Event. + + +/** +\brief USART Device Driver Capabilities. +*/ +typedef struct _ARM_USART_CAPABILITIES { + uint32_t asynchronous : 1; ///< supports UART (Asynchronous) mode + uint32_t synchronous_master : 1; ///< supports Synchronous Master mode + uint32_t synchronous_slave : 1; ///< supports Synchronous Slave mode + uint32_t single_wire : 1; ///< supports UART Single-wire mode + uint32_t irda : 1; ///< supports UART IrDA mode + uint32_t smart_card : 1; ///< supports UART Smart Card mode + uint32_t smart_card_clock : 1; ///< Smart Card Clock generator available + uint32_t flow_control_rts : 1; ///< RTS Flow Control available + uint32_t flow_control_cts : 1; ///< CTS Flow Control available + uint32_t event_tx_complete : 1; ///< Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE + uint32_t event_rx_timeout : 1; ///< Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT + uint32_t rts : 1; ///< RTS Line: 0=not available, 1=available + uint32_t cts : 1; ///< CTS Line: 0=not available, 1=available + uint32_t dtr : 1; ///< DTR Line: 0=not available, 1=available + uint32_t dsr : 1; ///< DSR Line: 0=not available, 1=available + uint32_t dcd : 1; ///< DCD Line: 0=not available, 1=available + uint32_t ri : 1; ///< RI Line: 0=not available, 1=available + uint32_t event_cts : 1; ///< Signal CTS change event: \ref ARM_USART_EVENT_CTS + uint32_t event_dsr : 1; ///< Signal DSR change event: \ref ARM_USART_EVENT_DSR + uint32_t event_dcd : 1; ///< Signal DCD change event: \ref ARM_USART_EVENT_DCD + uint32_t event_ri : 1; ///< Signal RI change event: \ref ARM_USART_EVENT_RI +} ARM_USART_CAPABILITIES; + + +/** +\brief Access structure of the USART Driver. +*/ +typedef struct _ARM_DRIVER_USART { + ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_USART_GetVersion : Get driver version. + ARM_USART_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_USART_GetCapabilities : Get driver capabilities. + int32_t (*Initialize) (ARM_USART_SignalEvent_t cb_event); ///< Pointer to \ref ARM_USART_Initialize : Initialize USART Interface. + int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_USART_Uninitialize : De-initialize USART Interface. + int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_USART_PowerControl : Control USART Interface Power. + int32_t (*Send) (const void *data, uint32_t num); ///< Pointer to \ref ARM_USART_Send : Start sending data to USART transmitter. + int32_t (*Receive) ( void *data, uint32_t num); ///< Pointer to \ref ARM_USART_Receive : Start receiving data from USART receiver. + int32_t (*Transfer) (const void *data_out, + void *data_in, + uint32_t num); ///< Pointer to \ref ARM_USART_Transfer : Start sending/receiving data to/from USART. + uint32_t (*GetTxCount) (void); ///< Pointer to \ref ARM_USART_GetTxCount : Get transmitted data count. + uint32_t (*GetRxCount) (void); ///< Pointer to \ref ARM_USART_GetRxCount : Get received data count. + int32_t (*Control) (uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_USART_Control : Control USART Interface. + ARM_USART_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_USART_GetStatus : Get USART status. + int32_t (*SetModemControl) (ARM_USART_MODEM_CONTROL control); ///< Pointer to \ref ARM_USART_SetModemControl : Set USART Modem Control line state. + ARM_USART_MODEM_STATUS (*GetModemStatus) (void); ///< Pointer to \ref ARM_USART_GetModemStatus : Get USART Modem Status lines state. +} const ARM_DRIVER_USART; + +#endif /* __DRIVER_USART_H */ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/GSPI.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/GSPI.h new file mode 100644 index 000000000..9bb3f4fb1 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/GSPI.h @@ -0,0 +1,164 @@ +/******************************************************************************* +* @file GSPI.h +* @brief +******************************************************************************* +* # License +* Copyright 2023 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + + +#ifndef __GSPI_H__ +#define __GSPI_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "rsi_pll.h" +#include "Driver_SPI.h" +#include "rsi_ccp_common.h" + +#include "UDMA.h" + + + +/* Current driver status flag definition */ +#define SPI_INITIALIZED (1 << 0) // SPI initialized +#define SPI_POWERED (1 << 1) // SPI powered on +#define SPI_CONFIGURED (1 << 2) // SPI configured +#define SPI_DATA_LOST (1 << 3) // SPI data lost occurred +#define SPI_MODE_FAULT (1 << 4) // SPI mode fault occurred +#define RSI_MUTLI_SLAVE_SELECT_ERROR -7 + +/** + * Macro defines for GSPI MANUAL STATUS Register + */ + +#define GSPI_MANUAL_STATUS_BITMASK 0x07AF /*!< GSPI Manual Status reg bitmask*/ +#define GSPI_BUSY_F 0x01 /*!< A read,write or dummy cycle operation is in process in manual mode*/ +#define GSPI_FIFO_FULL_WFIFO_S 0x02 /*!< Full status indication for Wfifo in manual mode*/ +#define GSPI_FIFO_AFULL_WFIFO_S 0x04 /*!< AFull status indication for Wfifo in manual mode*/ +#define GSPI_FIFO_EMPTY_WFIFO_S 0x08 /*!< Empty status indication for Wfifo in manual mode*/ +#define GSPI_FIFO_EMPTY_RFIFO_S 0x80 /*!< Empty status indication for Rfifo in manual mode*/ +#define GSPI_FIFO_AEMPTY_WFIFO_S 0x100 /*!< AEmpty status indication for Rfifo in manual mode*/ +#define GSPI_MAN_CSN 0x400 /*!< Status of chip select signal*/ + +/** + * Macro defines for GSPI INTR MASK Register + */ +#define GSPI_INTR_MASK_BITMASK 0x7F /*!< GSPI Interrupt mask reg bitmask*/ +#define GSPI_INTR_MASK_BIT 0x01 /*!< Mask the GSPI intr*/ +#define GSPI_FIFO_AEMPTY_RFIFO_MASK 0x02 /*!< read fifo almost empty intr mask */ +#define GSPI_FIFO_AFULL_RFIFO_MASK 0x04 /*!< read fifo almost full intr mask*/ +#define GSPI_FIFO_AEMPTY_WFIFO_MASK 0x08 /*!< write fifo almost empty intr mask*/ +#define GSPI_FIFO_AFULL_WFIFO_MASK 0x10 /*!< Write Fifo almost full intr mask*/ +#define GSPI_FIFO_FULL_WFIFO_MASK 0x20 /*!< write fifo is full intr mask*/ +#define GSPI_FIFO_EMPTY_RFIFO_MASK 0x40 /*!< read fifo is empty intr mask*/ +/** + * Macro defines for GSPI INTR UNMASK Register + */ +#define GSPI_INTR_UNMASK_BITMASK 0x7F /*!< GSPI Interrupt Unmask reg bitmask*/ +#define GSPI_INTR_UNMASK_BIT 0x01 /*!< Unmask the GSPI intr*/ +#define GSPI_FIFO_AEMPTY_RFIFO_UNMASK 0x02 /*!< read fifo almost empty intr unmask */ +#define GSPI_FIFO_AFULL_RFIFO_UNMASK 0x04 /*!< read fifo almost full intr unmask*/ +#define GSPI_FIFO_AEMPTY_WFIFO_UNMASK 0x08 /*!< write fifo almost empty intr unmask*/ +#define GSPI_FIFO_AFULL_WFIFO_UNMASK 0x10 /*!< Write Fifo almost full intr unmask*/ +#define GSPI_FIFO_FULL_WFIFO_UNMASK 0x20 /*!< write fifo is full intr unmask*/ +#define GSPI_FIFO_EMPTY_RFIFO_UNMASK 0x40 /*!< read fifo is empty intr unmask*/ + +#define GSPI_CS0 0 +#define GSPI_CS1 1 +#define GSPI_CS2 2 + +// SPI DMA +typedef struct _SPI_DMA +{ + RSI_UDMA_CHA_CFG_T chnl_cfg; + uint8_t channel; // DMA Channel number + UDMA_SignalEvent_t cb_event; // DMA Event callback +} GSPI_DMA; +/* SPI status */ +typedef struct _SPI_STATUS { + uint8_t busy; // Transmitter/Receiver busy flag + uint8_t data_lost; // Data lost: Receive overflow / Transmit underflow (cleared on start of transfer operation) + uint8_t mode_fault; // Mode fault detected; optional (cleared on start of transfer operation) +} GSPI_STATUS; + +/* SPI Information (Run-time) */ +typedef struct _SPI_INFO { + ARM_SPI_SignalEvent_t cb_event; // Event Callback + GSPI_STATUS status; // Status flags + uint8_t state; // Current SPI state + uint32_t mode; // Current SPI mode +} GSPI_INFO; + +/* SPI Transfer Information (Run-Time) */ +typedef struct _SPI_TRANSFER_INFO { + uint32_t num; // Total number of transfers + uint8_t *rx_buf; // Pointer to in data buffer + uint8_t *tx_buf; // Pointer to out data buffer + uint32_t rx_cnt; // Number of data received + uint32_t tx_cnt; // Number of data sent + uint32_t dump_val; // Variable for dumping DMA data + uint16_t def_val; // Default transfer value +} GSPI_TRANSFER_INFO; + +/* SPI Pins Configuration */ +typedef const struct _GSPI_PIN { + uint8_t port; ///< SPI GPIO port + uint8_t pin; ///< SPI GPIO pin + uint8_t mode; ///< SPI GPIO mode + uint8_t pad_sel; ///< SPI GPIO pad selection +}GSPI_PIN; + +// SPI Input/Output Configuration +typedef struct GSPI_IO_PINS { + GSPI_PIN *clock; + GSPI_PIN *cs0; +#ifdef GSPI_MULTI_SLAVE + GSPI_PIN *cs1; + GSPI_PIN *cs2; +#endif + GSPI_PIN *mosi; + GSPI_PIN *miso; +} GSPI_IO; + +typedef struct __GSPI_FIFO_THRESHOLDS { + uint8_t txdma_arb_size; + uint8_t rxdma_arb_size; + uint8_t gspi_afull_threshold ; + uint8_t gspi_aempty_threshold; +}GSPI_FIFO_THRESHOLDS; + +/* SPI Resources */ +typedef const struct { + GSPI0_Type *reg; // SPI peripheral register interface + IRQn_Type irq_num; // SPI IRQ number + GSPI_DMA *rx_dma; // Receive stream register interface + GSPI_DMA *tx_dma; // Transmit stream register interface + GSPI_INFO *info; // SPI Run-time information + GSPI_TRANSFER_INFO *xfer; // SPI transfer information + GSPI_IO io; + GSPI_CLK_SRC_SEL_T clock_source; + GSPI_FIFO_THRESHOLDS *threshold; + uint32_t cs_en; +} GSPI_RESOURCES; + +void RSI_GSPI_SetSlaveSelectNumber(uint8_t slavenumber); +uint8_t RSI_GSPI_GetSlaveSelectNumber(void); +ARM_DRIVER_VERSION GSPI_MASTER_GetVersion(void); +uint8_t RSI_GSPI_GetSlaveSelectNumber(void); +ARM_SPI_CAPABILITIES GSPI_MASTER_GetCapabilities(void); +#ifdef __cplusplus +} +#endif +#endif // __GSPI_H__ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/I2C.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/I2C.h new file mode 100644 index 000000000..be54d5ac9 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/I2C.h @@ -0,0 +1,299 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2013-2016 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * + * $Date: 29. March 2016 + * $Revision: V2.6 + * + * Project: Inter Integrated Circuit(I2C) Definitions for Silicon Labs MCU + * -------------------------------------------------------------------------- */ + +#ifndef __I2C_H +#define __I2C_H + +#include "rsi_pll.h" +#include "rsi_ulpss_clk.h" +#include "Driver_I2C.h" +#include "rsi_ccp_common.h" + + +/* I2C Interrupt Events */ +#define RSI_I2C_EVENT_RECEIVE_UNDER (1UL << 0) /*!< read the receive buffer when it is empty inerrupt */ +#define RSI_I2C_EVENT_RECEIVE_OVER (1UL << 1) /*!< receive buffer is completely filled interrupt */ +#define RSI_I2C_EVENT_RECEIVE_FULL (1UL << 2) /*!< receive buffer above the RX_TL threshold interrupt */ +#define RSI_I2C_EVENT_TRANSMIT_OVER (1UL << 3) /*!< issue write command after transmit buffer is filled completely */ +#define RSI_I2C_EVENT_TRANSMIT_EMPTY (1UL << 4) /*!< TX FIFO is empty interrupt */ +#define RSI_I2C_EVENT_READ_REQ (1UL << 5) /*!< In slave mode holds SCL if another I2C master is attempting to read */ +#define RSI_I2C_EVENT_TRANSMIT_ABRT (1UL << 6) /*!< Transmit abort interrupt */ +#define RSI_I2C_EVENT_RECEIVE_DONE (1UL << 7) /*!< receive done interrupt */ +#define RSI_I2C_EVENT_ACTIVITY_ON_BUS (1UL << 8) /*!< I2C activity interrupt */ +#define RSI_I2C_EVENT_STOP_DETECT (1UL << 9) /*!< Stop condition on bus detection interrupt */ +#define RSI_I2C_EVENT_START_DETECT (1UL << 10) /*!< START or RESTART condition interrupt */ +#define RSI_I2C_EVENT_GENERAL_CALL (1UL << 11) /*!< General call interrupt */ +#define RSI_I2C_EVENT_RESTART_DET (1UL << 12) /*!< RESTART condition in slave mode */ +#define RSI_I2C_EVENT_MST_ON_HOLD (1UL << 13) /*!< master is holding the bus and the Tx FIFO is empty */ +#define RSI_I2C_EVENT_SCL_STUCK_AT_LOW (1UL << 14) + +#define I2C_RECEIVE_UNDER (0) /*!< read the receive buffer when it is empty inerrupt */ +#define I2C_RECEIVE_OVER (1) /*!< receive buffer is completely filled interrupt */ +#define I2C_RECEIVE_FULL (2) /*!< receive buffer above the RX_TL threshold interrupt */ +#define I2C_TRANSMIT_OVER (3) /*!< issue write command after transmit buffer is filled completely */ +#define I2C_TRANSMIT_EMPTY (4) /*!< TX FIFO is empty interrupt */ +#define I2C_READ_REQ (5) /*!< In slave mode holds SCL if another I2C master is attempting to read */ +#define I2C_TRANSMIT_ABRT (6) /*!< Transmit abort interrupt */ +#define I2C_RECEIVE_DONE (7) /*!< receive done interrupt */ +#define I2C_ACTIVITY_ON_BUS (8) /*!< I2C activity interrupt */ +#define I2C_STOP_DETECT (9) /*!< Stop condition on bus detection interrupt */ +#define I2C_START_DETECT (10) /*!< START or RESTART condition interrupt */ +#define I2C_GENERAL_CALL (11) /*!< General call interrupt */ +#define I2C_RESTART_DET (12) /*!< RESTART condition in slave mode */ +#define I2C_MST_ON_HOLD (13) /*!< master is holding the bus and the Tx FIFO is empty */ +#define I2C_SCL_STUCK_AT_LOW (14) + +/* TX Abort Sources */ +#define I2C_TX_ABRT_7B_ADDR_NOACK (15) +#define I2C_TX_ABRT_10ADDR1_NOACK (16) +#define I2C_TX_ABRT_10ADDR2_NOACK (17) +#define I2C_TX_ABRT_TXDATA_NOACK (18) +#define I2C_TX_ABRT_GCALL_NOACK (19) +#define I2C_TX_ABRT_GCALL_READ (20) +#define I2C_TX_ABRT_HS_ACKDET (21) +#define I2C_TX_ABRT_SBYTE_ACKDET (22) +#define I2C_TX_ABRT_HS_NORSTRT (23) +#define I2C_TX_ABRT_SBYTE_NORSTRT (24) +#define I2C_TX_ABRT_10B_RD_NORSTRT (25) +#define I2C_TX_ABRT_MASTER_DIS (26) +#define I2C_TX_ARB_LOST (27) +#define I2C_TX_ABRT_SLVFLUSH_TXFIFO (28) +#define I2C_TX_ABRT_SLV_ARBLOST (29) +#define I2C_TX_ABRT_SLVRD_INTX (30) +#define I2C_TX_ABRT_USER_ABRT (31) +#define I2C_TX_ABRT_SDA_STUCK_AT_LOW (32) +#define I2C_TX_ABRT_DEVICE_NOACK (33) +#define I2C_TX_ABRT_DEVICE_SLVADDR_NOACK (34) +#define I2C_TX_ABRT_DEVICE_WRITE (35) +#define I2C_TX_TX_FLUSH_CNT (36) + +#define SLAVE_ADDR_CHECK_ARG 0x01 +#define SLAVE_RX_ARG 0x02 +#define SLAVE_TX_ARG 0x03 + +#define NACK 1 +#define ACK 0 + +#define F_RX_UNDER 0 +#define F_RX_OVER 1 +#define F_RX_FULL 2 +#define F_TX_OVER 3 +#define F_TX_EMPTY 4 +#define F_RD_REQ 5 +#define F_TX_ABRT 6 +#define F_RX_DONE 7 +#define F_ACTIVITY 8 +#define F_STOP_DET 9 +#define F_START_DET 10 +#define F_GEN_CALL 11 +#define F_RESTART_DET 12 +#define F_MST_ON_HOLD 13 + +#define I2C_ACTIVITY (1UL << 0) +#define I2C_TFNF (1UL << 1) +#define I2C_TFE (1UL << 2) +#define I2C_RFNE (1UL << 3) +#define I2C_RFF (1UL << 4) +#define I2C_MST_ACTIVITY (1UL << 5) +#define I2C_SLV_ACTIVITY (1UL << 6) + + +#define I2C_STAT_ACTIVITY 0 +#define I2C_STAT_TFNF 1 +#define I2C_STAT_TFE 2 +#define I2C_STAT_RFNE 3 +#define I2C_STAT_RFF 4 +#define I2C_STAT_MST_ACTIVITY 5 +#define I2C_STAT_SLV_ACTIVITY 6 +#define I2C_TX_ABRT_SOURCE 7 + +#define TX_ABRT_7B_ADDR_NOACK (1UL << 0) +#define TX_ABRT_10ADDR1_NOACK (1UL << 1) +#define TX_ABRT_10ADDR2_NOACK (1UL << 2) +#define TX_ABRT_TXDATA_NOACK (1UL << 3) +#define TX_ABRT_GCALL_NOACK (1UL << 4) +#define TX_ABRT_GCALL_READ (1UL << 5) +#define TX_ABRT_HS_ACKDET (1UL << 6) +#define TX_ABRT_SBYTE_ACKDET (1UL << 7) +#define TX_ABRT_HS_NORSTRT (1UL << 8) +#define TX_ABRT_SBYTE_NORSTRT (1UL << 9) +#define TX_ABRT_10B_RD_NORSTRT (1UL << 10) +#define TX_ABRT_MASTER_DIS (1UL << 11) +#define TX_ARB_LOST (1UL << 12) +#define TX_ABRT_SLVFLUSH_TXFIFO (1UL << 13) +#define TX_ABRT_SLV_ARBLOST (1UL << 14) +#define TX_ABRT_SLVRD_INTX (1UL << 15) +#define TX_ABRT_USER_ABRT (1UL << 16) +#define TX_ABRT_SDA_STUCK_AT_LOW (1UL << 17) +#define TX_ABRT_DEVICE_NOACK (1UL << 18) +#define TX_ABRT_DEVICE_SLVADDR_NOACK (1UL << 19) +#define TX_ABRT_DEVICE_WRITE (1UL << 20) +#define TX_TX_FLUSH_CNT (1UL << 23) + +/* bit defines */ +#define I2C2_BUS_CLK_ENABLE (1UL << 8) +#define I2C_STATIC_CLK_EN (1UL << 17) +#define UDMA_HCLK_ENBALE (1UL << 6) +#define ULP_UDMA_STATIC_CLK_EN (1UL << 17) +#define I2C2_STATIC_CLK_EN (1UL << 18) +#define I2C_FIFO_DEPTH 8 + + +/* I2C example defines */ +#define CHNL_30 30 +#define CHNL_31 31 +#define PRIMARY 0 +#define ALTERNATE 1 + + +#define I2C_RESTART_EN 0x1 + +#define I2C_MST_ADDR_7BIT_MODE 0x0 +#define I2C_MST_ADDR_10BIT_MODE 0x1 +#define I2C_SLV_ADDR_7BIT_MODE 0x0 + +#define I2C_SLV_ADDR 0x50 + +#define I2C_SCL_LOW_CLK 0x6 +#define I2C_SCL_HIGH_CLK 0x1 + +#define I2C_TX_TL 0x1 +#define I2C_RX_TL 0x4 +#define ADDRESS_WIDTH 8 + +#define MULTI_PAGE_WRITE 1 +#define SINGLE_PAGE_WRITE 0 + +#define BIT_WIDTH_8 0 +#define BIT_WIDTH_16 1 +#define BIT_WIDTH_32 2 + +#define READ_CMD 1 +#define WRITE_CMD 0 + +#define TX_EN 1 +#define RX_EN 1 + +#define I2C_DMA_TX_REQ 0x2 +#define I2C_DMA_RX_REQ 0x2 +#define DMA_ACK (1UL << 7) + +/* PAD pin selection */ +#define I2C0_PAD_SEL_6_8 1 +#define GPIO_6_REN 6 +#define GPIO_8_REN 8 + +#define I2CM_BLOCKING_XFER 1 +#define I2CM_NONBLOCKING_XFER 0 + + +#define SS_MIN_SCL_HIGH 5200 +#define SS_MIN_SCL_LOW 4700 +#define FS_MIN_SCL_HIGH 1160 +#define FS_MIN_SCL_LOW 1300 +#define HS_MIN_SCL_HIGH_400PF 274 +#define HS_MIN_SCL_LOW_400PF 333 +#define HS_MIN_SCL_HIGH_100PF 60 +#define HS_MIN_SCL_LOW_100PF 120 + +#define RSI_I2C_HIGH_SPEED 0x3 + +/* I2C Driver state flags */ +#define I2C_FLAG_INIT (1 << 0) // Driver initialized +#define I2C_FLAG_POWER (1 << 1) // Driver power on +#define I2C_FLAG_SETUP (1 << 2) // Master configured, clock set +#define I2C_FLAG_SLAVE_RX (1 << 3) // Slave receive registered +#define I2C_FLAG_STOP_DET (1 << 4) + +/* I2C Stalled Status flags */ +#define I2C_MASTER (1 << 0) // Master stalled +#define I2C_SLAVE_TX (1 << 1) // Slave stalled on transmit +#define I2C_SLAVE_RX (1 << 2) // Slave stalled on receive +#define I2C_SLAVE (I2C_SLAVE_TX | I2C_SLAVE_RX) + +/* I2C Interrupt Events */ +#define I2C_EVENT_RECEIVE_UNDER (1UL << 0) /*!< read the receive buffer when it is empty inerrupt */ +#define I2C_EVENT_RECEIVE_OVER (1UL << 1) /*!< receive buffer is completely filled interrupt */ +#define I2C_EVENT_RECEIVE_FULL (1UL << 2) /*!< receive buffer above the RX_TL threshold interrupt */ +#define I2C_EVENT_TRANSMIT_OVER (1UL << 3) /*!< issue write command after transmit buffer is filled completely */ +#define I2C_EVENT_TRANSMIT_EMPTY (1UL << 4) /*!< TX FIFO is empty interrupt */ +#define I2C_EVENT_READ_REQ (1UL << 5) /*!< In slave mode holds SCL if another I2C master is attempting to read */ +#define I2C_EVENT_TRANSMIT_ABRT (1UL << 6) /*!< Transmit abort interrupt */ +#define I2C_EVENT_RECEIVE_DONE (1UL << 7) /*!< receive done interrupt */ +#define I2C_EVENT_ACTIVITY_ON_BUS (1UL << 8) /*!< I2C activity interrupt */ +#define I2C_EVENT_STOP_DETECT (1UL << 9) /*!< Stop condition on bus detection interrupt */ +#define I2C_EVENT_START_DETECT (1UL << 10) /*!< START or RESTART condition interrupt */ +#define I2C_EVENT_GENERAL_CALL (1UL << 11) /*!< General call interrupt */ +#define I2C_EVENT_RESTART_DET (1UL << 12) /*!< RESTART condition in slave mode */ +#define I2C_EVENT_MST_ON_HOLD (1UL << 13) /*!< master is holding the bus and the Tx FIFO is empty */ +#define I2C_EVENT_SCL_STUCK_AT_LOW (1UL << 14) + +#define TRANSMITTER 0 +#define RECEIVER 1 + +void I2C0_IRQHandler (void); +void I2C1_IRQHandler (void); +void I2C2_IRQHandler (void); +/* I2C Control Information */ +typedef struct +{ + ARM_I2C_SignalEvent_t cb_event; // Event callback + ARM_I2C_STATUS status; // Status flags + uint8_t flags; // Control and state flags + uint16_t sla_rw; // Slave address and RW bit + bool pending; // Transfer pending (no STOP) + uint8_t stalled; // Stall mode status flags + uint8_t con_aa; // I2C slave CON flag + int32_t cnt; // Master transfer count + uint8_t *data; // Master data to transfer + uint32_t num; // Number of bytes to transfer + uint8_t *sdata; // Slave data to transfer + uint32_t snum; // Number of bytes to transfer +} I2C_CTRL; + +typedef const struct _I2C_PIN { + uint8_t port; ///< CAN GPIO port + uint8_t pin; ///< CAN GPIO pin + uint8_t mode; ///< CAN GPIO mode + uint8_t pad_sel; ///< CAN GPIO pad selection +}I2C_PIN; + +typedef const struct _I2C_IO { + I2C_PIN *scl; + I2C_PIN *sda; +} I2C_IO; + +/* I2C Resource Configuration */ +typedef struct +{ + I2C0_Type *reg; // I2C register interface + IRQn_Type i2c_ev_irq; // I2C Event IRQ Numbe + I2C_CTRL *ctrl; // Run-Time control information + I2C_IO io; //pins +} I2C_RESOURCES; + +#endif + diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/SAI.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/SAI.h new file mode 100644 index 000000000..831457350 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/SAI.h @@ -0,0 +1,254 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2013-2014 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * + * $Date: 9. Dec 2014 + * $Revision: V1.00 + * + * Project: SAI (Serial Audio Interface) Driver definitions + * -------------------------------------------------------------------------- */ + +/* History: + * Version 1.00 + * Initial release + */ + +#ifndef __SAI_H__ +#define __SAI_H__ + +#include "rsi_pll.h" +#include "rsi_ulpss_clk.h" +#include "Driver_SAI.h" +#include "rsi_ccp_common.h" + +#include "UDMA.h" + + +/****** I2S Events *****/ +#define RSI_I2S_EVENT_RXDA 0x0 /*!< Receive Data available event */ +#define RSI_I2S_EVENT_RXDATA_OVERRUN 0x1 /*!< RX data overrun event */ +#define RSI_I2S_EVENT_TRANSMIT_EMPTY 0x2 /*!< TX FIFO empty event */ +#define RSI_I2S_EVENT_TXDATA_OVERRUN 0x3 /*!< TX data overrun event */ +#define RSI_I2S_EVENT_DMA_ENABLE 0x4 /*!< DMA enable event */ + +/****** I2S Status Flags *****/ +#define I2S_STAT_RXDA (1UL << 0) /*!< RXDA interrupt flag */ +#define I2S_STAT_RXDATA_OVERRUN (1UL << 1) /*!< RXDO interrupt flag */ +#define I2S_STAT_TRANSMIT_EMPTY (1UL << 4) /*!< TXFE interrupt flag */ +#define I2S_STAT_TXDATA_OVERRUN (1UL << 5) /*!< TXFO interrupt flag */ + +#define F_RXDA 0x01 +#define F_RXFO 0x02 +#define F_TXFE 0x03 +#define F_TXFO 0x04 + +#define F_RXDAM (1UL << 0) +#define F_RXFOM (1UL << 1) +#define F_TXFEM (1UL << 4) +#define F_TXFOM (1UL << 5) + +#define MASTER 0x1 +#define SLAVE 0x0 +#define RES_12 0x1 +#define RES_16 0x2 +#define RES_20 0x3 +#define RES_24 0x4 + +#define MISC_SOFT_SET_REG_2 (*((uint32_t volatile *)(0x46008000UL + 0x34))) +#define CHNL_0 0 +#define CHNL_1 1 + +/* Number of sclk cycles for which the word select + line (ws_out) stays in the left or right sample mode */ +#define WSS_24_CYCLES 0x1 +#define WSS_16_CYCLES 0x0 +#define WSS_32_CYCLES 0x2 + +#define SCLKG_12_CYCLES 0x1 +#define SCLKG_16_CYCLES 0x2 +#define SCLKG_20_CYCLES 0x3 +#define SCLKG_24_CYCLES 0x4 +#define SCLKG_NO_GATE 0x0 + + +#define RX_BLOCK_EN 0x1 +#define TX_BLOCK_EN 0x1 + +#define RES_12_BIT 0x1 +#define RES_16_BIT 0x2 +#define RES_20_BIT 0x3 +#define RES_24_BIT 0x4 +#define RES_32_BIT 0x5 + +#define I2S_FIFO_DEPTH 8 +#define I2S_TX_TL 7 +#define I2S_RX_TL 7 + +#define MASTER 0x1 +#define SLAVE 0x0 + +#define PCM_EN 1 +#define PCM_DIS 0 +#define FSYNC_EN 1 +#define FSYNC_DIS 0 + +#define ULP_I2S_CLK_SEL 8 +#define ULP_I2S_CLK_DIV_FACT 1 +#define M4_I2S_CLK_SEL 0 +#define M4_I2S_CLK_DIV_FACT 0 + +/** + \brief Macro defines for MISC_SOFT_SET3_REG + */ +#define PCM_ENA (1UL << 0) +#define PCM_FSYNC_START_M (1UL << 1) +#define PCM_BIT_RES_8_SET (0 << 2) +#define PCM_BIT_RES_12_SET (1 << 2) +#define PCM_BIT_RES_16_SET (2 << 2) +#define PCM_BIT_RES_24_SET (3 << 2) + +/** + \brief Macro defines for MISC_SOFT_CLR3_REG + */ +#define PCMEN (1UL << 0) +#define PCM_FSYNCSTART (1UL << 1) +#define PCM_BIT_RES_8_CLR (0 << 2) +#define PCM_BIT_RES_12_CLR (1 << 2) +#define PCM_BIT_RES_16_CLR (2 << 2) +#define PCM_BIT_RES_24_CLR (3 << 2) + +/** + \brief Macro defines for MISC_CFG_MISC_CTRL1 + */ +#define I2S_MASTER_SLAVE_MODE (1 << 23) /*!< Sets I2S/ PCM master mode */ +#define ARM_SOFT_RESET (1 << 19) + + +/** + \brief Macro defines for ULP_MISC_SOFT_SET_REG + */ +#define ULP_I2S_CLK_ENABLE (1UL << 6) +#define ULP_PCM_FSYNC_START (1UL << 1) +#define ULP_PCM_ENABLE (1UL << 0) +#define ULP_PCM_BIT_RES_8_SET (0 << 2) +#define ULP_PCM_BIT_RES_12_SET (1 << 2) +#define ULP_PCM_BIT_RES_16_SET (2 << 2) +#define ULP_PCM_BIT_RES_24_SET (3 << 2) + +#define I2S_BLOCKING_XFER 1 +#define I2S_NONBLOCKING_XFER 0 + +// I2S flags +#define I2S_FLAG_INITIALIZED (1U) +#define I2S_FLAG_POWERED (1U << 1) +#define I2S_FLAG_CONFIGURED (1U << 2) + +#define INTR_MASK 1 +#define INTR_UNMASK 0 + +#define I2S_PROTOCOL 0 +#define PCM_PROTOCOL 1 + + + +// I2S Stream Information (Run-Time) +typedef struct _I2S_STREAM_INFO +{ + uint32_t num; // Total number of data to be transmited/received + uint8_t *buf; // Pointer to data buffer + uint32_t cnt; // Number of data transmited/receive + uint8_t data_bits; // Number of data bits + uint8_t master; // Master flag + uint8_t residue_num; + uint8_t residue_buf[4]; + uint8_t residue_cnt; +} I2S_STREAM_INFO; + +typedef struct _I2S_STATUS { + uint8_t tx_busy; // Transmitter busy flag + uint8_t rx_busy; // Receiver busy flag + uint8_t tx_underflow; // Transmit data underflow detected (cleared on start of next send operation) + uint8_t rx_overflow; // Receive data overflow detected (cleared on start of next receive operation) + uint8_t frame_error; // Sync Frame error detected (cleared on start of next send/receive operation) +} I2S_STATUS; + +// I2S Information (Run-Time) +typedef struct _I2S_INFO +{ + ARM_SAI_SignalEvent_t cb_event; // Event callback + I2S_STATUS status; // Status flags + I2S_STREAM_INFO tx; // Transmit information + I2S_STREAM_INFO rx; // Receive information +} I2S_INFO; + +// I2S DMA +typedef struct _I2S_DMA +{ + RSI_UDMA_CHA_CONFIG_DATA_T control; + uint8_t channel; // DMA Channel number + UDMA_SignalEvent_t cb_event; // DMA Event callback +} I2S_DMA; + +// I2S Clock Config +typedef struct _I2S_CLK +{ + uint8_t clk_src; // I2S Clock Source + uint8_t div_fact; // Clock Division factor +} I2S_CLK; + +/* Pins Configuration */ +typedef const struct _I2S_PIN { + uint8_t port; ///< SPI GPIO port + uint8_t pin; ///< SPI GPIO pin + uint8_t mode; ///< SPI GPIO mode + uint8_t pad_sel; ///< SPI GPIO pad selection +}I2S_PIN; + +// Input/Output Configuration +typedef struct I2S_IO_PINS { + I2S_PIN *sclk; + I2S_PIN *wsclk; + I2S_PIN *din0; + I2S_PIN *dout0; + I2S_PIN *din1; + I2S_PIN *dout1; +}I2S_IO; + +// I2S Reseurces definitions +typedef struct +{ + ARM_SAI_CAPABILITIES capabilities; // Capabilities + I2S0_Type *reg; // Pointer to I2S peripheral + IRQn_Type irq_num; // I2S IRQ Number + I2S_DMA *dma_tx; // I2S TX DMA configuration + I2S_DMA *dma_rx; // I2S RX DMA configuration + uint8_t tx_fifo_level; // I2S transmit fifo level + uint8_t rx_fifo_level; // I2S receive fifo level + uint8_t xfer_chnl; + I2S_INFO *info; // Run-Time information + uint32_t flags; + uint8_t protocol; + I2S_CLK *clk; + I2S_IO io; +} I2S_RESOURCES; +void IRQ064_Handler (void); +void IRQ014_Handler (void); + + +#endif /* __DRIVER_SAI_H */ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/SPI.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/SPI.h new file mode 100644 index 000000000..c511ba8d9 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/SPI.h @@ -0,0 +1,406 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * $Date: 02. March 2016 + * $Revision: V2.2 + * + * Project: SPI Driver Definitions for Silicon Labs MCU + * -------------------------------------------------------------------------- */ + +#ifndef __SPI_H +#define __SPI_H + +#include "rsi_pll.h" +#include "Driver_SPI.h" +#include "rsi_ccp_common.h" + +#include "UDMA.h" +#include "rsi_ulpss_clk.h" +#ifdef SSI_CONFIG +#include "sl_si91x_ssi_common_config.h" +#endif + +#define SSI_DISABLE 0x00 /*!< Disable the SSI Operation*/ +#define SSI_ENABLE 0x01 /*!< Enable the SSI Operation*/ +#define TXEIM 0x1 +#define TXOIM 0x2 +#define RXUIM 0x4 +#define RXOIM 0x8 +#define RXFIM 0x10 +#define TRANSMIT_AND_RECEIVE 0x00 +#define TRANSMIT_ONLY 0x01 +#define RECEIVE_ONLY 0x02 +#define STANDARD_SPI_FORMAT 0x00 +#define MOTOROLA_SPI 0x00 +#define TEXAS_INSTRUMENTS_SSP 0x01 +#define NATIONAL_SEMICONDUCTORS_MICROWIRE 0x02 +#define SPI_MASTER_MODE 1U +#define SPI_SLAVE_MODE 2U +#define SPI_ULP_MASTER_MODE 3U + +#define SPI_ISR_TX_FIFO_EMPTY BIT(0) +#define SPI_ISR_TX_FIFO_OVERFLOW BIT(1) +#define SPI_ISR_RX_FIFO_UNDERFLOW BIT(2) +#define SPI_ISR_RX_FIFO_OVERFLOW BIT(3) +#define SPI_ISR_RX_FIFO_FULL BIT(4) + + +ARM_DRIVER_VERSION SPI_GetVersion(void); +ARM_SPI_CAPABILITIES SPI_GetCapabilities(void); +void IRQ047_Handler(void) ; +void IRQ044_Handler(void); +void IRQ016_Handler(void); +void mySPI_callback(uint32_t event); + +#if ((defined(RTE_Drivers_SSI_MASTER) || \ + defined(RTE_Drivers_SSI_SLAVE) || \ + defined(RTE_Drivers_SSI_ULP_MASTER)) \ + && (RTE_SSI_MASTER == 0) \ + && (RTE_SSI_SLAVE == 0) \ + && (RTE_SSI_ULP_MASTER == 0)) +#error "SPI not configured in RTE_Device_917.h!" +#endif + + +#if defined(RTE_SSI_MASTER) && (RTE_SSI_MASTER == 1) +#define SSI_MASTER 1U + +#if defined (SL_SSI_MASTER_DMA_CONFIG_ENABLE) && (SL_SSI_MASTER_DMA_CONFIG_ENABLE == ENABLE) +#define RTE_SSI_MASTER_RX_DMA 1 +#define RTE_SSI_MASTER_TX_DMA 1 +#endif + +#if defined (SL_SSI_SLAVE_DMA_CONFIG_ENABLE) && (SL_SSI_SLAVE_DMA_CONFIG_ENABLE == ENABLE) +#define RTE_SSI_SLAVE_RX_DMA 1 +#define RTE_SSI_SLAVE_TX_DMA 1 +#endif + +#if defined (SL_SSI_ULP_MASTER_DMA_CONFIG_ENABLE) && (SL_SSI_ULP_MASTER_DMA_CONFIG_ENABLE == ENABLE) +#define RTE_SSI_ULP_MASTER_RX_DMA 1 +#define RTE_SSI_ULP_MASTER_TX_DMA 1 +#endif + +#if defined(RTE_SSI_MASTER_RX_DMA) && (RTE_SSI_MASTER_RX_DMA == 1) +#define SSI_MASTER_RX_DMA_Instance 1U +#define SSI_MASTER_RX_DMA_Channel RTE_SSI_MASTER_UDMA_RX_CH +#endif + +#if defined(RTE_SSI_MASTER_TX_DMA) && (RTE_SSI_MASTER_TX_DMA == 1) +#define SSI_MASTER_TX_DMA_Instance 1U +#define SSI_MASTER_TX_DMA_Channel RTE_SSI_MASTER_UDMA_TX_CH +#endif + +#if defined(RTE_SSI_MASTER_MISO) && (RTE_SSI_MASTER_MISO == 1) +#define SSI_MASTER_MISO_SEL 1U +#define SSI_MASTER_MISO_PORT RTE_SSI_MASTER_MISO_PORT +#define SSI_MASTER_MISO_PIN RTE_SSI_MASTER_MISO_PIN +#define SSI_MASTER_MISO_MODE RTE_SSI_MASTER_MISO_MODE +#define SSI_MASTER_MISO_PADSEL RTE_SSI_MASTER_MISO_PADSEL +#endif + +#if defined(RTE_SSI_MASTER_MOSI) && (RTE_SSI_MASTER_MOSI == 1) +#define SSI_MASTER_MOSI_SEL 1U +#define SSI_MASTER_MOSI_PORT RTE_SSI_MASTER_MOSI_PORT +#define SSI_MASTER_MOSI_PIN RTE_SSI_MASTER_MOSI_PIN +#define SSI_MASTER_MOSI_MODE RTE_SSI_MASTER_MOSI_MODE +#define SSI_MASTER_MOSI_PADSEL RTE_SSI_MASTER_MOSI_PADSEL +#endif + +#if defined(RTE_SSI_MASTER_SCK) && (RTE_SSI_MASTER_SCK == 1) +#define SSI_MASTER_SCK_SEL 1U +#define SSI_MASTER_SCK_PORT RTE_SSI_MASTER_SCK_PORT +#define SSI_MASTER_SCK_PIN RTE_SSI_MASTER_SCK_PIN +#define SSI_MASTER_SCK_MODE RTE_SSI_MASTER_SCK_MODE +#define SSI_MASTER_SCK_PADSEL RTE_SSI_MASTER_SCK_PADSEL +#endif + +#if defined(RTE_SSI_MASTER_CS0) && (RTE_SSI_MASTER_CS0 == 1) +#define SSI_MASTER_CS0_SEL 1U +#define SSI_MASTER_CS0_PORT RTE_SSI_MASTER_CS0_PORT +#define SSI_MASTER_CS0_PIN RTE_SSI_MASTER_CS0_PIN +#define SSI_MASTER_CS0_MODE RTE_SSI_MASTER_CS0_MODE +#define SSI_MASTER_CS0_PADSEL RTE_SSI_MASTER_CS0_PADSEL +#endif + +#if defined(RTE_SSI_MASTER_CS1) && (RTE_SSI_MASTER_CS1 == 1) +#define SSI_MASTER_CS1_SEL 1U +#define SSI_MASTER_CS1_PORT RTE_SSI_MASTER_CS1_PORT +#define SSI_MASTER_CS1_PIN RTE_SSI_MASTER_CS1_PIN +#define SSI_MASTER_CS1_MODE RTE_SSI_MASTER_CS1_MODE +#define SSI_MASTER_CS1_PADSEL RTE_SSI_MASTER_CS1_PADSEL +#endif + +#if defined(RTE_SSI_MASTER_CS2) && (RTE_SSI_MASTER_CS2 == 1) +#define SSI_MASTER_CS2_SEL 1U +#define SSI_MASTER_CS2_PORT RTE_SSI_MASTER_CS2_PORT +#define SSI_MASTER_CS2_PIN RTE_SSI_MASTER_CS2_PIN +#define SSI_MASTER_CS2_MODE RTE_SSI_MASTER_CS2_MODE +#define SSI_MASTER_CS2_PADSEL RTE_SSI_MASTER_CS2_PADSEL +#endif + +#if defined(RTE_SSI_MASTER_CS3) && (RTE_SSI_MASTER_CS3 == 1) +#define SSI_MASTER_CS3_SEL 1U +#define SSI_MASTER_CS3_PORT RTE_SSI_MASTER_CS3_PORT +#define SSI_MASTER_CS3_PIN RTE_SSI_MASTER_CS3_PIN +#define SSI_MASTER_CS3_MODE RTE_SSI_MASTER_CS3_MODE +#define SSI_MASTER_CS3_PADSEL RTE_SSI_MASTER_CS3_PADSEL +#endif +#endif + +#if defined(RTE_SSI_SLAVE) && (RTE_SSI_SLAVE == 1) +#define SSI_SLAVE 1U + +#if defined(RTE_SSI_SLAVE_RX_DMA) && (RTE_SSI_SLAVE_RX_DMA == 1) +#define SSI_SLAVE_RX_DMA_Instance 1U +#define SSI_SLAVE_RX_DMA_Channel RTE_SSI_SLAVE_UDMA_RX_CH +#endif + +#if defined(RTE_SSI_SLAVE_TX_DMA) && (RTE_SSI_SLAVE_TX_DMA == 1) +#define SSI_SLAVE_TX_DMA_Instance 1U +#define SSI_SLAVE_TX_DMA_Channel RTE_SSI_SLAVE_UDMA_TX_CH +#endif + +#if defined(RTE_SSI_SLAVE_MISO) && (RTE_SSI_SLAVE_MISO == 1) +#define SSI_SLAVE_MISO_SEL 1U +#define SSI_SLAVE_MISO_PORT RTE_SSI_SLAVE_MISO_PORT +#define SSI_SLAVE_MISO_PIN RTE_SSI_SLAVE_MISO_PIN +#define SSI_SLAVE_MISO_MODE RTE_SSI_SLAVE_MISO_MODE +#define SSI_SLAVE_MISO_PADSEL RTE_SSI_SLAVE_MISO_PADSEL +#endif + +#if defined(RTE_SSI_SLAVE_MOSI) && (RTE_SSI_SLAVE_MOSI == 1) +#define SSI_SLAVE_MOSI_SEL 1U +#define SSI_SLAVE_MOSI_PORT RTE_SSI_SLAVE_MOSI_PORT +#define SSI_SLAVE_MOSI_PIN RTE_SSI_SLAVE_MOSI_PIN +#define SSI_SLAVE_MOSI_MODE RTE_SSI_SLAVE_MOSI_MODE +#define SSI_SLAVE_MOSI_PADSEL RTE_SSI_SLAVE_MOSI_PADSEL +#endif + +#if defined(RTE_SSI_SLAVE_SCK) && (RTE_SSI_SLAVE_SCK == 1) +#define SSI_SLAVE_SCK_SEL 1U +#define SSI_SLAVE_SCK_PORT RTE_SSI_SLAVE_SCK_PORT +#define SSI_SLAVE_SCK_PIN RTE_SSI_SLAVE_SCK_PIN +#define SSI_SLAVE_SCK_MODE RTE_SSI_SLAVE_SCK_MODE +#define SSI_SLAVE_SCK_PADSEL RTE_SSI_SLAVE_SCK_PADSEL +#endif + +#if defined(RTE_SSI_SLAVE_CS) && (RTE_SSI_SLAVE_CS == 1) +#define SSI_SLAVE_CS0_SEL 1U +#define SSI_SLAVE_CS0_PORT RTE_SSI_SLAVE_CS_PORT +#define SSI_SLAVE_CS0_PIN RTE_SSI_SLAVE_CS_PIN +#define SSI_SLAVE_CS0_MODE RTE_SSI_SLAVE_CS_MODE +#define SSI_SLAVE_CS0_PADSEL RTE_SSI_SLAVE_CS_PADSEL +#endif +#endif + +#if defined(RTE_SSI_ULP_MASTER) && (RTE_SSI_ULP_MASTER == 1) +#define SSI_ULP_MASTER 1U + +#if defined(RTE_SSI_ULP_MASTER_RX_DMA) && (RTE_SSI_ULP_MASTER_RX_DMA == 1) +#define SSI_ULP_MASTER_RX_DMA_Instance 1U +#define SSI_ULP_MASTER_RX_DMA_Channel RTE_SSI_ULP_MASTER_UDMA_RX_CH +#endif + +#if defined(RTE_SSI_ULP_MASTER_TX_DMA) && (RTE_SSI_ULP_MASTER_TX_DMA == 1) +#define SSI_ULP_MASTER_TX_DMA_Instance 1U +#define SSI_ULP_MASTER_TX_DMA_Channel RTE_SSI_ULP_MASTER_UDMA_TX_CH +#endif + +#if defined(RTE_SSI_ULP_MASTER_MISO) && (RTE_SSI_ULP_MASTER_MISO == 1) +#define SSI_ULP_MASTER_MISO_SEL 1U +#define SSI_ULP_MASTER_MISO_PORT RTE_SSI_ULP_MASTER_MISO_PORT +#define SSI_ULP_MASTER_MISO_PIN RTE_SSI_ULP_MASTER_MISO_PIN +#define SSI_ULP_MASTER_MISO_MODE RTE_SSI_ULP_MASTER_MISO_MODE +#endif + +#if defined(RTE_SSI_ULP_MASTER_MOSI) && (RTE_SSI_ULP_MASTER_MOSI == 1) +#define SSI_ULP_MASTER_MOSI_SEL 1U +#define SSI_ULP_MASTER_MOSI_PORT RTE_SSI_ULP_MASTER_MOSI_PORT +#define SSI_ULP_MASTER_MOSI_PIN RTE_SSI_ULP_MASTER_MOSI_PIN +#define SSI_ULP_MASTER_MOSI_MODE RTE_SSI_ULP_MASTER_MOSI_MODE +#endif + +#if defined(RTE_SSI_ULP_MASTER_SCK) && (RTE_SSI_ULP_MASTER_SCK == 1) +#define SSI_ULP_MASTER_SCK_SEL 1U +#define SSI_ULP_MASTER_SCK_PORT RTE_SSI_ULP_MASTER_SCK_PORT +#define SSI_ULP_MASTER_SCK_PIN RTE_SSI_ULP_MASTER_SCK_PIN +#define SSI_ULP_MASTER_SCK_MODE RTE_SSI_ULP_MASTER_SCK_MODE +#endif + +#if defined(RTE_SSI_ULP_MASTER_CS0) && (RTE_SSI_ULP_MASTER_CS0 == 1) +#define SSI_ULP_MASTER_CS0_SEL 1U +#define SSI_ULP_MASTER_CS0_PORT RTE_SSI_ULP_MASTER_CS0_PORT +#define SSI_ULP_MASTER_CS0_PIN RTE_SSI_ULP_MASTER_CS0_PIN +#define SSI_ULP_MASTER_CS0_MODE RTE_SSI_ULP_MASTER_CS0_MODE +#endif +#if defined(RTE_SSI_ULP_MASTER_CS1) && (RTE_SSI_ULP_MASTER_CS1 == 1) +#define SSI_ULP_MASTER_CS1_SEL 1U +#define SSI_ULP_MASTER_CS1_PORT RTE_SSI_ULP_MASTER_CS1_PORT +#define SSI_ULP_MASTER_CS1_PIN RTE_SSI_ULP_MASTER_CS1_PIN +#define SSI_ULP_MASTER_CS1_MODE RTE_SSI_ULP_MASTER_CS1_MODE +#endif +#if defined(RTE_SSI_ULP_MASTER_CS2) && (RTE_SSI_ULP_MASTER_CS2 == 1) +#define SSI_ULP_MASTER_CS2_SEL 1U +#define SSI_ULP_MASTER_CS2_PORT RTE_SSI_ULP_MASTER_CS2_PORT +#define SSI_ULP_MASTER_CS2_PIN RTE_SSI_ULP_MASTER_CS2_PIN +#define SSI_ULP_MASTER_CS2_MODE RTE_SSI_ULP_MASTER_CS2_MODE +#endif +#endif + + +/* SPI Register Interface Definitions */ +#ifdef SSI_MASTER +#if (defined(SSI_MASTER_RX_DMA_Instance) || defined(SSI_MASTER_TX_DMA_Instance)) +#ifndef SSI_MASTER_RX_DMA_Instance +#error "SSI_MASTER using DMA requires Rx and Tx DMA channel enabled in RTE_Device_917.h!" +#endif +#ifndef SSI_MASTER_TX_DMA_Instance +#error "SSI_MASTER using DMA requires Rx and Tx DMA channel enabled in RTE_Device_917.h!" +#endif +#endif +#endif + +#ifdef SSI_SLAVE +#if (defined(SSI_SLAVE_RX_DMA_Instance) || defined(SSI_SLAVE_TX_DMA_Instance)) +#ifndef SSI_SLAVE_RX_DMA_Instance +#error "SSI_SLAVE using DMA requires Rx and Tx DMA channel enabled in RTE_Device_917.h!" +#endif +#ifndef SSI_SLAVE_TX_DMA_Instance +#error "SSI_SLAVE using DMA requires Rx and Tx DMA channel enabled in RTE_Device_917.h!" +#endif +#endif +#endif + +#ifdef SSI_ULP_MASTER +#if (defined(SSI_ULP_MASTER_RX_DMA_Instance) || defined(SSI_ULP_MASTER_TX_DMA_Instance)) +#ifndef SSI_ULP_MASTER_RX_DMA_Instance +#error "SSI_ULP_MASTER using DMA requires Rx and Tx DMA channel enabled in RTE_Device_917.h!" +#endif +#ifndef SSI_ULP_MASTER_TX_DMA_Instance +#error "SSI_ULP_MASTER using DMA requires Rx and Tx DMA channel enabled in RTE_Device_917.h!" +#endif +#endif +#endif + + +#if ((defined(SSI_MASTER) && defined(SSI_MASTER_RX_DMA_Instance)) || \ + (defined(SSI_SLAVE) && defined(SSI_SLAVE_RX_DMA_Instance)) || \ + (defined(SSI_ULP_MASTER) && defined(SSI_ULP_MASTER_RX_DMA_Instance))) +#define __SPI_DMA_RX +#endif +#if ((defined(SSI_MASTER) && defined(SSI_MASTER_TX_DMA_Instance)) || \ + (defined(SSI_SLAVE) && defined(SSI_SLAVE_TX_DMA_Instance)) || \ + (defined(SSI_ULP_MASTER) && defined(SSI_ULP_MASTER_TX_DMA_Instance))) +#define __SPI_DMA_TX +#endif +#if (defined(__SPI_DMA_RX) && defined(__SPI_DMA_TX)) +#define __SPI_DMA +#endif + +/* Current driver status flag definition */ +#define SPI_INITIALIZED (1 << 0) // SPI initialized +#define SPI_POWERED (1 << 1) // SPI powered on +#define SPI_CONFIGURED (1 << 2) // SPI configured +#define SPI_DATA_LOST (1 << 3) // SPI data lost occurred +#define SPI_MODE_FAULT (1 << 4) // SPI mode fault occurred + + +#define SPI_CS0 0 +#define SPI_CS1 1 +#define SPI_CS2 2 +#define SPI_CS3 3 + +/* SPI Pins Configuration */ +typedef const struct _SPI_PIN { + uint8_t port; ///< SPI GPIO port + uint8_t pin; ///< SPI GPIO pin + uint8_t mode; ///< SPI GPIO mode + uint8_t pad_sel; ///< SPI GPIO pad selection +}SPI_PIN; + +// SPI Input/Output Configuration +typedef const struct _SPI_IO { + SPI_PIN *mosi; // Pointer to MOSI pin configuration + SPI_PIN *miso; // Pointer to MISO pin configuration + SPI_PIN *sck; // Pointer to SCK pin configuration + SPI_PIN *cs0; // Pointer to CS(CHIP SELECT) pin configuration +#ifdef SPI_MULTI_SLAVE + SPI_PIN *cs1; // Pointer to CS(CHIP SELECT) pin configuration + SPI_PIN *cs2; // Pointer to CS(CHIP SELECT) pin configuration + SPI_PIN *cs3; // Pointer to CS(CHIP SELECT) pin configuration +#endif +} SPI_IO; + +// SPI DMA +typedef struct SPI_DMA +{ + RSI_UDMA_CHA_CFG_T chnl_cfg; + uint8_t channel; // DMA Channel number + UDMA_SignalEvent_t cb_event; // DMA Event callback +} SPI_DMA; + +/* SPI status */ +typedef struct SPI_STATUS { + uint8_t busy; // Transmitter/Receiver busy flag + uint8_t data_lost; // Data lost: Receive overflow / Transmit underflow (cleared on start of transfer operation) + uint8_t mode_fault; // Mode fault detected; optional (cleared on start of transfer operation) +} SPI_STATUS; + +/* SPI Information (Run-time) */ +typedef struct SPI_INFO { + ARM_SPI_SignalEvent_t cb_event; // Event Callback + SPI_STATUS status; // Status flags + uint8_t state; // Current SPI state + uint32_t mode; // Current SPI mode +} SPI_INFO; + +/* SPI Transfer Information (Run-Time) */ +typedef struct SPI_TRANSFER_INFO { + uint32_t num; // Total number of transfers + uint8_t *rx_buf; // Pointer to in data buffer + uint8_t *tx_buf; // Pointer to out data buffer + uint32_t rx_cnt; // Number of data received + uint32_t tx_cnt; // Number of data sent + uint32_t dump_val; // Variable for dumping DMA data + uint16_t def_val; // Default transfer value +} SPI_TRANSFER_INFO; + +typedef struct _SPI_CLOCK +{ + SSI_MST_CLK_SRC_SEL_T spi_clk_src; + ULP_SSI_CLK_SELECT_T ulp_spi_clk_src; + uint32_t divfact; + }SPI_CLOCK; + +/* SPI Resources */ +typedef struct { + SSI0_Type *reg; // SPI peripheral register interface + SPI_IO io; // SPI pins configuration + IRQn_Type irq_num; // SPI IRQ number + SPI_DMA *rx_dma; // Receive stream register interface + SPI_DMA *tx_dma; // Transmit stream register interface + SPI_INFO *info; // SPI Run-time information + SPI_TRANSFER_INFO *xfer; // SPI transfer information + uint8_t instance_mode; + SPI_CLOCK clock; + +} const SPI_RESOURCES; + +void RSI_SPI_SetSlaveSelectNumber(uint8_t slavenumber); +void RSI_SPI_Slave_Disable(void); +void RSI_SPI_Slave_Set_CS_Init_State(void); +#endif /* __SPI_H */ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/UDMA.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/UDMA.h new file mode 100644 index 000000000..c5cadc507 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/UDMA.h @@ -0,0 +1,92 @@ +/******************************************************************************* +* @file UDMA.h +* @brief +******************************************************************************* +* # License +* Copyright 2023 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +#ifndef __UDMA_H__ +#define __UDMA_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "rsi_ccp_common.h" +#include "Driver_Common.h" +#include "rsi_udma.h" + +#define UDMA_EVENT_XFER_DONE (1) +#define UDMA_EVENT_ERROR (2) + +void IRQ033_Handler (void); +void IRQ010_Handler (void); +#if defined(DAC_FIFO_MODE_EN) || defined(ADC_MULTICHANNEL_WITH_EXT_DMA) +#define DAC_UDMA_CHANNEL 10 +#define ADC_UDMA_CHANNEL 11 +#endif + +/* UDMA Resource Configuration */ +typedef struct +{ + UDMA0_Type *reg; // UDMA register interface + IRQn_Type udma_irq_num; // UDMA Event IRQ Numbe + RSI_UDMA_DESC_T *desc; // Run-Time control information +} UDMA_RESOURCES; + +/* Number of UDMA channels */ +#define UDMA_NUMBER_OF_CHANNELS ((uint8_t) 32) +#define ULP_UDMA_NUMBER_OF_CHANNELS ((uint8_t) 12) + + +#define CONTROL_STRUCT0 (UDMA_NUMBER_OF_CHANNELS * 2) +#define CONTROL_STRUCT1 (ULP_UDMA_NUMBER_OF_CHANNELS * 2) + +/** + * @fn void UDMA_SignalEvent_t (uint32_t event) + * @brief Signal UDMA Events. + * @param[in] event UDMA Event mask + * @param[in] ch Channel no + * @return none +*/ +typedef void (*UDMA_SignalEvent_t) (uint32_t event, uint32_t ch); + + +/** +\brief Access structure of the UDMA Driver. +*/ +typedef struct _RSI_DRIVER_UDMA { + + int32_t (*Initialize) ( void ); + int32_t (*Uninitialize) ( void ); + int32_t (*ChannelConfigure)( uint8_t ch, + uint32_t src_addr, + uint32_t dest_addr, + uint32_t size, + RSI_UDMA_CHA_CONFIG_DATA_T control, + RSI_UDMA_CHA_CFG_T *config, + UDMA_SignalEvent_t cb_event ); + int32_t (*ChannelEnable) ( uint8_t ch ); + int32_t (*ChannelDisable) ( uint8_t ch ); + uint32_t (*ChannelGetCount) ( uint8_t ch, + RSI_UDMA_CHA_CONFIG_DATA_T control, + RSI_UDMA_CHA_CFG_T config ); + int32_t (*DMAEnable) ( void ); +} const RSI_DRIVER_UDMA; + +#ifdef __cplusplus +} +#endif +#endif // __UDMA_H__ + + diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/USART.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/USART.h new file mode 100644 index 000000000..db1fe9e54 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/USART.h @@ -0,0 +1,276 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2013-2014 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * + * $Date: 24. Nov 2014 + * $Revision: V2.02 + * + * Project: USART (Universal Synchronous Asynchronous Receiver Transmitter) + * Driver definitions + * -------------------------------------------------------------------------- */ +/* + * Version 1.00 + * Initial release + */ + +#ifndef __USART_H__ +#define __USART_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "rsi_pll.h" +#include "rsi_ulpss_clk.h" +#include "Driver_USART.h" +#include "rsi_ccp_common.h" + +#include "UDMA.h" + +#define USART_INSTANCE_BIT 30 // USART Instance bit postion stored in event variable +#define USART_EVENT_MASK 0x3FFFFFFF // USART Event Mask + +// USART Transfer Information (Run-Time) +typedef struct _USART_TRANSFER_INFO { + uint32_t rx_num; // Total number of data to be received + uint32_t tx_num; // Total number of data to be send + uint8_t *rx_buf; // Pointer to in data buffer + uint8_t *tx_buf; // Pointer to out data buffer + uint32_t rx_cnt; // Number of data received + uint32_t tx_cnt; // Number of data sent + uint8_t tx_def_val; // Transmit default value (used in USART_SYNC_MASTER_MODE_RX) + uint8_t rx_dump_val; // Receive dump value (used in USART_SYNC_MASTER_MODE_TX) + uint8_t send_active; // Send active flag + uint8_t sync_mode; // Synchronous mode +} USART_TRANSFER_INFO; + +typedef struct _USART_RX_STATUS { + uint8_t rx_busy; // Receiver busy flag + uint8_t rx_overflow; // Receive data overflow detected (cleared on start of next receive operation) + uint8_t rx_break; // Break detected on receive (cleared on start of next receive operation) + uint8_t rx_framing_error; // Framing error detected on receive (cleared on start of next receive operation) + uint8_t rx_parity_error; // Parity error detected on receive (cleared on start of next receive operation) +} USART_RX_STATUS; + +// USART DMA +typedef struct _USART0_DMA +{ + RSI_UDMA_CHA_CONFIG_DATA_T control; + uint8_t channel; // DMA Channel number + UDMA_SignalEvent_t cb_event; // DMA Event callback +} USART_DMA; + + +// USART flags +#define USART_FLAG_INITIALIZED (1U << 0) +#define USART_FLAG_POWERED (1U << 1) +#define USART_FLAG_CONFIGURED (1U << 2) +#define USART_FLAG_TX_ENABLED (1U << 3) +#define USART_FLAG_RX_ENABLED (1U << 4) +#define USART_FLAG_SEND_ACTIVE (1U << 5) + +/*!< USART Configuration control bits (Line control Register)*/ +#define USART_CNTL_DATALEN_5 (0x00 << 0) /*!< USART 5 bit length mode */ +#define USART_CNTL_DATALEN_6 (0x01 << 0) /*!< USART 6 bit length mode */ +#define USART_CNTL_DATALEN_7 (0x02 << 0) /*!< USART 7 bit length mode */ +#define USART_CNTL_DATALEN_8 (0x03 << 0) /*!< USART 8 bit length mode */ +#define USART_CNTL_STOPBIT_1 (0x00 << 2) /*!< USART One Stop Bit Select */ +#define USART_CNTL_STOPBIT_2 (0x01 << 2) /*!< USART Two Stop Bits Select */ +#define USART_CNTL_STOPBIT_1P5 (0x01 << 2) /*!< USART Two Stop Bits Select */ +#define USART_CNTL_PARITY_OFF (0x00 << 3) /*!< Parity Enabled */ +#define USART_CNTL_PARITY_ON (0x01 << 3) /*!< Parity Disabled */ +#define USART_CNTL_PARITY_ODD (0x00 << 4) /*!< Odd parity */ +#define USART_CNTL_PARITY_EVEN (0x01 << 4) /*!< Even parity */ +#define USART_PARITY_ENABLE (0x01 << 3) /*!< Set parity */ +#define USART_CNTL_DLAB_SET (0x01 << 7) +#define USART_CNTL_DLAB_RESET (0x00) +#define USART_CNTL_DATALEN_9 (0x01 << 0) /*!< USART 9 bit length mode */ + +/*!< USART FIFO Configuration control bits (FIFO control Register)*/ +#define USART_FIFO_ENABLE (0x01 << 0) /*!< FIFO Enable */ +#define USART_FIFO_RX_RESET (0x01 << 1) /*!< Receive FIFO Reset */ +#define USART_FIFO_TX_RESET (0x01 << 2) /*!< Transmit FIFO Reset */ +#define USART_FIFO_TX_EMPTY (0x00 << 4) /*!< Transmit Empty */ +#define USART_FIFO_TX_AEMPTY (0x01 << 4) /*!< Transmit Almost Empty */ +#define USART_FIFO_TX_QUARTER_FULL (0x02 << 4) /*!< Transmit FIFO Quarter full */ +#define USART_FIFO_TX_HALF_FULL (0x03 << 4) /*!< Transmit FIFO Half full */ +#define USART_FIFO_RX_AEMPTY (0x00 << 6) /*!< Receive FIFO AEMPTY */ +#define USART_FIFO_RX_QUARTER_FULL (0x01 << 6) /*!< Receive FIFO Quarter full */ +#define USART_FIFO_RX_HALF_FULL (0x01 << 7) /*!< Receive FIFO half full */ +#define USART_FIFO_RX_AFULL (0x03 << 6) /*!< RX FIFO Almost Full */ +#define USART_DMA_MODE_EN (1UL << 3) + +/*!< USART (Interrupt Enable Register)*/ +#define USART_INTR_RX_DATA (0x01 << 0) /*!< Enable Received Data Available Interrupt. */ +#define USART_INTR_THRE (0x01 << 1) /*!< Enable Transmit Holding Register Empty Interrupt.*/ +#define USART_INTR_RXRDY (0x01 << 2) /*!< Receive Ready Interrupt */ +#define USART_INTR_MODEM_STATUS (0x01 << 3) /*!< TODO */ +#define USART_INTR_PROGRAMMABLE_THRE (0x01 << 7) /*!< TODO THRE Interrupt */ + +/*!< USART (Interrupt Identity Register)*/ +#define USART_MODEM_STATUS_INTR (0x00 << 0) +#define USART_NO_INTR_PENDING (0x01 << 0) /*!< NO Interrupt Pending */ +#define USART_THR_EMPTY (0x01 << 1) /*!< THR Empty */ +#define USART_RX_DATA_AVAILABLE (0x01 << 2) /*!< Received Data Available */ +#define USART_RX_LINE_STATUS (0x03 << 1) /*!< Receiver line status */ +#define USART_BUSY_DETECT (0x07 << 0) /*!< USART busy detect */ +#define USART_RX_CHAR_TIMEOUT (0x03 << 2) /*!< Receive character timeout */ +#define USART_IIR_FIFO_ENABLE (0x03 << 6) /*!< IIR FIFO enabled */ + +/*!< USART (Modem status registers)*/ +#define USART_MSR_DCTS (0x1 << 0) /*!>> -------------------- + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H +#include "rsi_ccp_user_config.h" + +// USART0 [Driver_USART0] +// Configuration settings for Driver_USART0 in component ::CMSIS Driver:USART +#define RTE_ENABLE_FIFO 1 + +#define RTE_USART0 1 + +#define RTE_USART0_CLK_SRC USART_INTFPLLCLK +#define RTE_USART0_CLK_DIV_FACT 1 +#define RTE_USART0_FRAC_DIV_SEL USART_FRACTIONAL_DIVIDER + +#define RTE_USART_MODE 0 //!Usart mode macros +#define RTE_CONTINUOUS_CLOCK_MODE 0 + +#define RTE_USART0_LOOPBACK 0 +#define RTE_USART0_DTR_EANBLE 0 + +#define RTE_USART0_DMA_MODE1_EN 0 //!dma mode + +#define RTE_USART0_TX_FIFO_THRESHOLD USART_TRIGGER_TX_EMPTY +#define RTE_USART0_RX_FIFO_THRESHOLD USART_TRIGGER_RX_AEMPTY + +#define RTE_USART0_DMA_TX_LEN_PER_DES 1024 +#define RTE_USART0_DMA_RX_LEN_PER_DES 1024 + +#define RTE_USART0_CHNL_UDMA_TX_EN 0 +#define RTE_USART0_CHNL_UDMA_TX_CH 25 + +#define RTE_USART0_CHNL_UDMA_RX_EN 0 +#define RTE_USART0_CHNL_UDMA_RX_CH 24 + + +// USART0_CLK <0=>P0_8 <1=>P0_25 <2=>P0_52 <3=>P0_64 +// CLK of USART0 +#define RTE_USART0_CLK_PORT_ID 0 +#ifdef CHIP_917_6x6 +#if((RTE_USART0_CLK_PORT_ID == 2)||(RTE_USART0_CLK_PORT_ID == 3)) + #error "Invalid USART0 RTE_USART0_CLK_PIN pin Configuration!" +#endif +#endif +#if(RTE_USART0_CLK_PORT_ID == 0) +#define RTE_USART0_CLK_PORT 0 +#define RTE_USART0_CLK_PIN 8 +#define RTE_USART0_CLK_MUX 2 +#define RTE_USART0_CLK_PAD 3 +#elif(RTE_USART0_CLK_PORT_ID ==1) +#define RTE_USART0_CLK_PORT 0 +#define RTE_USART0_CLK_PIN 25 +#define RTE_USART0_CLK_MUX 2 +#define RTE_USART0_CLK_PAD 0//NO PAD +#elif(RTE_USART0_CLK_PORT_ID ==2) +#define RTE_USART0_CLK_PORT 0 +#define RTE_USART0_CLK_PIN 52 +#define RTE_USART0_CLK_MUX 2 +#define RTE_USART0_CLK_PAD 16 +#elif(RTE_USART0_CLK_PORT_ID ==3) +#define RTE_USART0_CLK_PORT 0 +#define RTE_USART0_CLK_PIN 64 +#define RTE_USART0_CLK_MUX 2 +#define RTE_USART0_CLK_PAD 22 +#else + #error "Invalid USART0 RTE_USART0_CLK_PIN Pin Configuration!" +#endif + +// USART0_TX <0=>P0_15 <1=>P0_30 <2=>P0_54 <3=>P0_68 <4=>P0_71 +// TX for USART0 +#ifndef CHIP_917_6x6 +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_USART0_TX_PORT_ID 1 +#else +#define RTE_USART0_TX_PORT_ID 0 +#endif +#endif + +#ifdef CHIP_917_6x6 +#define RTE_USART0_TX_PORT_ID 3 +#if((RTE_USART0_TX_PORT_ID == 0)||(RTE_USART0_TX_PORT_ID ==2)) + #error "Invalid USART0 RTE_USART0_TX_PIN pin Configuration!" +#endif +#endif +#if(RTE_USART0_TX_PORT_ID == 0) +#define RTE_USART0_TX_PORT 0 +#define RTE_USART0_TX_PIN 15 +#define RTE_USART0_TX_MUX 2 +#define RTE_USART0_TX_PAD 8 +#elif(RTE_USART0_TX_PORT_ID == 1) +#define RTE_USART0_TX_PORT 0 +#define RTE_USART0_TX_PIN 30 +#define RTE_USART0_TX_MUX 2 +#define RTE_USART0_TX_PAD 0 //NO PAD +#elif(RTE_USART0_TX_PORT_ID ==2) +#define RTE_USART0_TX_PORT 0 +#define RTE_USART0_TX_PIN 54 +#define RTE_USART0_TX_MUX 2 +#define RTE_USART0_TX_PAD 18 +#elif(RTE_USART0_TX_PORT_ID ==3) +#define RTE_USART0_TX_PORT 0 +#define RTE_USART0_TX_PIN 68 +#define RTE_USART0_TX_MUX 2 +#define RTE_USART0_TX_PAD 26 +#elif(RTE_USART0_TX_PORT_ID ==4) +#define RTE_USART0_TX_PORT 0 +#define RTE_USART0_TX_PIN 71 +#define RTE_USART0_TX_MUX 4 +#define RTE_USART0_TX_PAD 29 +#else + #error "Invalid USART0 RTE_USART0_TX_PIN Pin Configuration!" +#endif + +// USART0_RX <0=>P0_10 <1=>P0_29 <2=>P0_55 <3=>P0_65 <4=>P0_70 +// RX for USART0 +#ifndef CHIP_917_6x6 +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_USART0_RX_PORT_ID 1 +#else +#define RTE_USART0_RX_PORT_ID 0 +#endif +#endif + +#ifdef CHIP_917_6x6 +#define RTE_USART0_RX_PORT_ID 0 +#if((RTE_USART0_RX_PORT_ID == 2)||(RTE_USART0_RX_PORT_ID == 3)) + #error "Invalid USART0 RTE_USART0_RX_PIN pin Configuration!" +#endif +#endif +#if(RTE_USART0_RX_PORT_ID ==0) +#define RTE_USART0_RX_PORT 0 +#define RTE_USART0_RX_PIN 10 +#define RTE_USART0_RX_MUX 2 +#define RTE_USART0_RX_PAD 5 +#elif(RTE_USART0_RX_PORT_ID ==1) +#define RTE_USART0_RX_PORT 0 +#define RTE_USART0_RX_PIN 29 +#define RTE_USART0_RX_MUX 2 +#define RTE_USART0_RX_PAD 0//no pad +#elif(RTE_USART0_RX_PORT_ID ==2) +#define RTE_USART0_RX_PORT 0 +#define RTE_USART0_RX_PIN 55 +#define RTE_USART0_RX_MUX 2 +#define RTE_USART0_RX_PAD 19 +#elif(RTE_USART0_RX_PORT_ID ==3) +#define RTE_USART0_RX_PORT 0 +#define RTE_USART0_RX_PIN 65 +#define RTE_USART0_RX_MUX 2 +#define RTE_USART0_RX_PAD 24 +#elif(RTE_USART0_RX_PORT_ID ==4) +#define RTE_USART0_RX_PORT 0 +#define RTE_USART0_RX_PIN 70 +#define RTE_USART0_RX_MUX 4 +#define RTE_USART0_RX_PAD 28 +#else + #error "Invalid USART0 RTE_USART0_RX_PIN Pin Configuration!" +#endif + +// USART0_CTS <0=>P0_6 <1=>P0_26 <2=>P0_56 <3=>P0_70 +// CTS for USART0 +#define RTE_USART0_CTS_PORT_ID 0 +#ifdef CHIP_917_6x6 +#if((RTE_USART0_CTS_PORT_ID == 2)) + #error "Invalid USART0 RTE_USART0_CTS_PIN pin Configuration!" +#endif +#endif +#if(RTE_USART0_CTS_PORT_ID ==0) +#define RTE_USART0_CTS_PORT 0 +#define RTE_USART0_CTS_PIN 6 +#define RTE_USART0_CTS_MUX 2 +#define RTE_USART0_CTS_PAD 1 +#elif(RTE_USART0_CTS_PORT_ID ==1) +#define RTE_USART0_CTS_PORT 0 +#define RTE_USART0_CTS_PIN 26 +#define RTE_USART0_CTS_MUX 2 +#define RTE_USART0_CTS_PAD 0//NO PAD +#elif(RTE_USART0_CTS_PORT_ID ==2) +#define RTE_USART0_CTS_PORT 0 +#define RTE_USART0_CTS_PIN 56 +#define RTE_USART0_CTS_MUX 2 +#define RTE_USART0_CTS_PAD 20 +#elif(RTE_USART0_CTS_PORT_ID ==3) +#define RTE_USART0_CTS_PORT 0 +#define RTE_USART0_CTS_PIN 70 +#define RTE_USART0_CTS_MUX 2 +#define RTE_USART0_CTS_PAD 28 +#else + #error "Invalid USART0 RTE_USART0_CTS_PIN Pin Configuration!" +#endif + + +// USART0_RTS <0=>P0_9 <1=>P0_28 <2=>P0_53 <3=>P0_69 +// RTS for USART0 +#define RTE_USART0_RTS_PORT_ID 0 +#ifdef CHIP_917_6x6 +#if((RTE_USART0_RTS_PORT_ID == 2)) + #error "Invalid USART0 RTE_USART0_RTS_PIN pin Configuration!" +#endif +#endif +#if(RTE_USART0_RTS_PORT_ID ==0) +#define RTE_USART0_RTS_PORT 0 +#define RTE_USART0_RTS_PIN 9 +#define RTE_USART0_RTS_MUX 2 +#define RTE_USART0_RTS_PAD 4 +#elif(RTE_USART0_RTS_PORT_ID ==1) +#define RTE_USART0_RTS_PORT 0 +#define RTE_USART0_RTS_PIN 28 +#define RTE_USART0_RTS_MUX 2 +#define RTE_USART0_RTS_PAD 0 //NO PAD +#elif(RTE_USART0_RTS_PORT_ID ==2) +#define RTE_USART0_RTS_PORT 0 +#define RTE_USART0_RTS_PIN 53 +#define RTE_USART0_RTS_MUX 2 +#define RTE_USART0_RTS_PAD 17 +#elif(RTE_USART0_RTS_PORT_ID ==3) +#define RTE_USART0_RTS_PORT 0 +#define RTE_USART0_RTS_PIN 69 +#define RTE_USART0_RTS_MUX 2 +#define RTE_USART0_RTS_PAD 27 +#else + #error "Invalid USART0 RTE_USART0_RTS_PIN Pin Configuration!" +#endif + +// USART0_IR_TX <0=>P0_48 <1=>P0_72 +// IR TX for USART0 +#ifndef CHIP_917_6x6 +#define RTE_IR_TX_PORT_ID 0 +#if((RTE_IR_TX_PORT_ID ==2 )) + #error "Invalid USART0 RTE_USART0_IR_TX_PIN Pin Configuration!" +#endif +#endif +#ifdef CHIP_917_6x6 +#define RTE_IR_TX_PORT_ID 2 +#if((RTE_IR_TX_PORT_ID ==0 )||(RTE_IR_TX_PORT_ID ==1 )) + #error "Invalid USART0 RTE_USART0_IR_TX_PIN Pin Configuration!" +#endif +#endif +#if(RTE_IR_TX_PORT_ID ==0) +#define RTE_USART0_IR_TX_PORT 0 +#define RTE_USART0_IR_TX_PIN 48 +#define RTE_USART0_IR_TX_MUX 2 +#define RTE_USART0_IR_TX_PAD 12 +#elif(RTE_IR_TX_PORT_ID ==1) +#define RTE_USART0_IR_TX_PORT 0 +#define RTE_USART0_IR_TX_PIN 72 +#define RTE_USART0_IR_TX_MUX 2 +#define RTE_USART0_IR_TX_PAD 30 +#elif(RTE_IR_TX_PORT_ID ==2) +#define RTE_USART0_IR_TX_PORT 0 +#define RTE_USART0_IR_TX_PIN 26 +#define RTE_USART0_IR_TX_MUX 13 +#define RTE_USART0_IR_TX_PAD 0//No pad +#else + #error "Invalid USART0 RTE_USART0_IR_TX_PIN Pin Configuration!" +#endif + + +// USART0_IR_RX <0=>P0_47 <1=>P0_71 <2=>P0_64 <3=>P0_25 +// IR RX for USART0 +#ifndef CHIP_917_6x6 +#define RTE_IR_RX_PORT_ID 0 +#if((RTE_IR_RX_PORT_ID ==2 )) + #error "Invalid USART0 RTE_USART0_IR_RX_PIN Pin Configuration!" +#endif +#endif +#ifdef CHIP_917_6x6 +#define RTE_IR_RX_PORT_ID 2 +#if((RTE_IR_RX_PORT_ID == 0)) + #error "Invalid USART0 RTE_USART0_IR_RX_PIN Pin Configuration!" +#endif +#endif +#if(RTE_IR_RX_PORT_ID ==0) +#define RTE_USART0_IR_RX_PORT 0 +#define RTE_USART0_IR_RX_PIN 47 +#define RTE_USART0_IR_RX_MUX 2 +#define RTE_USART0_IR_RX_PAD 11 +#elif(RTE_IR_RX_PORT_ID ==1) +#define RTE_USART0_IR_RX_PORT 0 +#define RTE_USART0_IR_RX_PIN 71 +#define RTE_USART0_IR_RX_MUX 2 +#define RTE_USART0_IR_RX_PAD 29 +#elif(RTE_IR_RX_PORT_ID ==2) +#define RTE_USART0_IR_RX_PORT 0 +#define RTE_USART0_IR_RX_PIN 25 +#define RTE_USART0_IR_RX_MUX 13 +#define RTE_USART0_IR_RX_PAD 0//no pad +#else + #error "Invalid USART0 RTE_USART0_IR_RX_PIN Pin Configuration!" +#endif + + +// USART0_RI <0=>P0_27 <1=>P0_46 <2=>P0_68 +// RI for USART0 +#define RTE_RI_PORT_ID 0 + +#ifndef CHIP_917_6x6 + +#if((RTE_RI_PORT_ID == 2)) + #error "Invalid USART0 RTE_USART0_RI_PIN Pin Configuration!" +#endif + +#endif + + +#ifdef CHIP_917_6x6 + +#if((RTE_RI_PORT_ID == 1)) + #error "Invalid USART0 RTE_USART0_RI_PIN Pin Configuration!" +#endif + +#endif +#if(RTE_RI_PORT_ID ==0) +#define RTE_USART0_RI_PORT 0 +#define RTE_USART0_RI_PIN 27 +#define RTE_USART0_RI_MUX 2 +#define RTE_USART0_RI_PAD 0//no pad +#elif(RTE_RI_PORT_ID ==1) +#define RTE_USART0_RI_PORT 0 +#define RTE_USART0_RI_PIN 46 +#define RTE_USART0_RI_MUX 2 +#define RTE_USART0_RI_PAD 10 +#elif(RTE_RI_PORT_ID ==2) +#define RTE_USART0_RI_PORT 0 +#define RTE_USART0_RI_PIN 68 +#define RTE_USART0_RI_MUX 11 +#define RTE_USART0_RI_PAD 26 +#else + #error "Invalid USART0 RTE_USART0_RI_PIN Pin Configuration!" +#endif + +// USART0_DSR <0=>P0_11 <1=>P0_57 +// DSR for USART0 +#define RTE_DSR_PORT_ID 0 +#ifdef CHIP_917_6x6 +#if((RTE_DSR_PORT_ID == 1)) + #error "Invalid USART0 RTE_USART0_RI_PIN pin Configuration!" +#endif +#endif +#if(RTE_DSR_PORT_ID == 0) +#define RTE_USART0_DSR_PORT 0 +#define RTE_USART0_DSR_PIN 11 +#define RTE_USART0_DSR_MUX 2 +#define RTE_USART0_DSR_PAD 6 +#elif(RTE_DSR_PORT_ID == 1) +#define RTE_USART0_DSR_PORT 0 +#define RTE_USART0_DSR_PIN 57 +#define RTE_USART0_DSR_MUX 2 +#define RTE_USART0_DSR_PAD 21 +#else + #error "Invalid USART0 RTE_USART0_RI_PIN Pin Configuration!" +#endif +// USART0_DCD <0=>P0_12 <1=>P0_29 +// DCD for USART0 + +#ifndef CHIP_917_6x6 +#define RTE_USART0_DCD_PORT 0 +#define RTE_USART0_DCD_PIN 12 +#define RTE_USART0_DCD_MUX 2 +#define RTE_USART0_DCD_PAD 7 +#endif + +#ifdef CHIP_917_6x6 +#define RTE_USART0_DCD_PORT 0 +#define RTE_USART0_DCD_PIN 29 +#define RTE_USART0_DCD_MUX 12 +#define RTE_USART0_DCD_PAD 0//no pad +#endif + + +// USART0_DTR <0=>P0_7 +// DTR for USART0 +#define RTE_USART0_DTR_PORT 0 +#define RTE_USART0_DTR_PIN 7 +#define RTE_USART0_DTR_MUX 2 +#define RTE_USART0_DTR_PAD 2 +// + +// UART1 [Driver_UART1] +// Configuration settings for Driver_UART1 in component ::CMSIS Driver:USART +#define RTE_UART1 1 + +#define RTE_UART1_CLK_SRC USART_INTFPLLCLK +#define RTE_UART1_CLK_DIV_FACT 1 +#define RTE_UART1_FRAC_DIV_SEL USART_FRACTIONAL_DIVIDER + +#define RTE_UART1_LOOPBACK 0 +#define RTE_UART1_DMA_MODE1_EN 0 + +#define RTE_UART1_TX_FIFO_THRESHOLD USART_TRIGGER_TX_EMPTY +#define RTE_UART1_RX_FIFO_THRESHOLD USART_TRIGGER_RX_AEMPTY + +#define RTE_UART1_DMA_TX_LEN_PER_DES 1024 +#define RTE_UART1_DMA_RX_LEN_PER_DES 1024 + +#define RTE_UART1_CHNL_UDMA_TX_EN 0 +#define RTE_UART1_CHNL_UDMA_TX_CH 27 + +#define RTE_UART1_CHNL_UDMA_RX_EN 0 +#define RTE_UART1_CHNL_UDMA_RX_CH 26 + +/*UART1 PINS*/ +// UART1_TX <0=>P0_7 <1=>P0_30 <2=>P0_67 <3=>P0_69 <4=>P0_73 <5=>P0_75 <6=>P0_34 +// TX of UART1 +#ifndef CHIP_917_6x6 +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_UART1_TX_PORT_ID 4 +#else +#define RTE_UART1_TX_PORT_ID 0 +#endif + +#if((RTE_UART1_TX_PORT_ID == 6)) + #error "Invalid UART1 RTE_UART1_TX_PIN Configuration!" +#endif +#endif + +#ifdef CHIP_917_6x6 +#define RTE_UART1_TX_PORT_ID 0 +#if((RTE_UART1_TX_PORT_ID == 2)||(RTE_UART1_TX_PORT_ID == 4)||(RTE_UART1_TX_PORT_ID == 5)) + #error "Invalid UART1 RTE_UART1_TX_PIN Configuration!" +#endif +#endif +#if(RTE_UART1_TX_PORT_ID ==0) +#define RTE_UART1_TX_PORT 0 +#define RTE_UART1_TX_PIN 7 +#define RTE_UART1_TX_MUX 6 +#define RTE_UART1_TX_PAD 2 +#elif(RTE_UART1_TX_PORT_ID ==1) +#define RTE_UART1_TX_PORT 0 +#define RTE_UART1_TX_PIN 30 +#define RTE_UART1_TX_MUX 6 +#define RTE_UART1_TX_PAD 0//no pad +#elif(RTE_UART1_TX_PORT_ID ==2) +#define RTE_UART1_TX_PORT 0 +#define RTE_UART1_TX_PIN 67 +#define RTE_UART1_TX_MUX 9 +#define RTE_UART1_TX_PAD 25 +#elif(RTE_UART1_TX_PORT_ID ==3) +#define RTE_UART1_TX_PORT 0 +#define RTE_UART1_TX_PIN 69 +#define RTE_UART1_TX_MUX 6 +#define RTE_UART1_TX_PAD 27 +#elif(RTE_UART1_TX_PORT_ID ==4) +#define RTE_UART1_TX_PORT 0 +#define RTE_UART1_TX_PIN 73 +#define RTE_UART1_TX_MUX 6 +#define RTE_UART1_TX_PAD 31 +#elif(RTE_UART1_TX_PORT_ID ==5) +#define RTE_UART1_TX_PORT 0 +#define RTE_UART1_TX_PIN 75 +#define RTE_UART1_TX_MUX 9 +#define RTE_UART1_TX_PAD 33 +#elif(RTE_UART1_TX_PORT_ID ==6) +#define RTE_UART1_TX_PORT 0 +#define RTE_UART1_TX_PIN 34 +#define RTE_UART1_TX_MUX 12 +#define RTE_UART1_TX_PAD 9 +#else + #error "Invalid UART1 RTE_UART1_TX_PIN Pin Configuration!" +#endif + +// UART1_RX <0=>P0_6 <1=>P0_29 <2=>P0_66 <3=>P0_68 <4=>P0_72 <5=>P0_74 <6=>P0_33 +// RX of UART1 + +#ifndef CHIP_917_6x6 +#define RTE_UART1_RX_PORT_ID 0 +#if((RTE_UART1_RX_PORT_ID == 6)) + #error "Invalid UART1 RTE_UART1_RX_PIN Configuration!" +#endif +#endif + +#ifdef CHIP_917_6x6 +#define RTE_UART1_RX_PORT_ID 0 +#if((RTE_UART1_RX_PORT_ID == 2)||(RTE_UART1_RX_PORT_ID == 4)||(RTE_UART1_RX_PORT_ID == 5)) + #error "Invalid UART1 RTE_UART1_RX_PIN Configuration!" +#endif +#endif +#if(RTE_UART1_RX_PORT_ID ==0) +#define RTE_UART1_RX_PORT 0 +#define RTE_UART1_RX_PIN 6 +#define RTE_UART1_RX_MUX 6 +#define RTE_UART1_RX_PAD 1 +#elif(RTE_UART1_RX_PORT_ID ==1) +#define RTE_UART1_RX_PORT 0 +#define RTE_UART1_RX_PIN 29 +#define RTE_UART1_RX_MUX 6 +#define RTE_UART1_RX_PAD 0//no pad +#elif(RTE_UART1_RX_PORT_ID ==2) +#define RTE_UART1_RX_PORT 0 +#define RTE_UART1_RX_PIN 66 +#define RTE_UART1_RX_MUX 9 +#define RTE_UART1_RX_PAD 24 +#elif(RTE_UART1_RX_PORT_ID ==3) +#define RTE_UART1_RX_PORT 0 +#define RTE_UART1_RX_PIN 68 +#define RTE_UART1_RX_MUX 6 +#define RTE_UART1_RX_PAD 26 +#elif(RTE_UART1_RX_PORT_ID ==4) +#define RTE_UART1_RX_PORT 0 +#define RTE_UART1_RX_PIN 72 +#define RTE_UART1_RX_MUX 6 +#define RTE_UART1_RX_PAD 30 +#elif(RTE_UART1_RX_PORT_ID ==5) +#define RTE_UART1_RX_PORT 0 +#define RTE_UART1_RX_PIN 74 +#define RTE_UART1_RX_MUX 9 +#define RTE_UART1_RX_PAD 32 +#elif(RTE_UART1_RX_PORT_ID ==6) +#define RTE_UART1_RX_PORT 0 +#define RTE_UART1_RX_PIN 33 +#define RTE_UART1_RX_MUX 12 +#define RTE_UART1_RX_PAD 9 +#else + #error "Invalid UART1 RTE_UART1_RX_PIN Pin Configuration!" +#endif + +// UART1_CTS <0=>P0_11 <1=>P0_28 <2=>P0_51 <3=>P0_65 <4=>P0_71 <5=>P0_73 <6=>P0_32 +// CTS of UART1 +#ifndef CHIP_917_6x6 +#define RTE_UART1_CTS_PORT_ID 0 +#if((RTE_UART1_CTS_PORT_ID == 6)) + #error "Invalid UART1 RTE_UART1_CTS_PIN Configuration!" +#endif +#endif + +#ifdef CHIP_917_6x6 +#define RTE_UART1_CTS_PORT_ID 6 +#if((RTE_UART1_CTS_PORT_ID == 2)||(RTE_UART1_CTS_PORT_ID == 3)||(RTE_UART1_CTS_PORT_ID == 5)) + #error "Invalid UART1 RTE_UART1_CTS_PIN Configuration!" +#endif +#endif + +#if(RTE_UART1_CTS_PORT_ID ==0) +#define RTE_UART1_CTS_PORT 0 +#define RTE_UART1_CTS_PIN 11 +#define RTE_UART1_CTS_MUX 6 +#define RTE_UART1_CTS_PAD 6 +#elif(RTE_UART1_CTS_PORT_ID ==1) +#define RTE_UART1_CTS_PORT 0 +#define RTE_UART1_CTS_PIN 28 +#define RTE_UART1_CTS_MUX 6 +#define RTE_UART1_CTS_PAD 0//no pad +#elif(RTE_UART1_CTS_PORT_ID ==2) +#define RTE_UART1_CTS_PORT 0 +#define RTE_UART1_CTS_PIN 51 +#define RTE_UART1_CTS_MUX 9 +#define RTE_UART1_CTS_PAD 15 +#elif(RTE_UART1_CTS_PORT_ID ==3) +#define RTE_UART1_CTS_PORT 0 +#define RTE_UART1_CTS_PIN 65 +#define RTE_UART1_CTS_MUX 9 +#define RTE_UART1_CTS_PAD 23 +#elif(RTE_UART1_CTS_PORT_ID ==4) +#define RTE_UART1_CTS_PORT 0 +#define RTE_UART1_CTS_PIN 71 +#define RTE_UART1_CTS_MUX 6 +#define RTE_UART1_CTS_PAD 29 +#elif(RTE_UART1_CTS_PORT_ID ==5) +#define RTE_UART1_CTS_PORT 0 +#define RTE_UART1_CTS_PIN 73 +#define RTE_UART1_CTS_MUX 9 +#define RTE_UART1_CTS_PAD 31 +#elif(RTE_UART1_CTS_PORT_ID ==6) +#define RTE_UART1_CTS_PORT 0 +#define RTE_UART1_CTS_PIN 32 +#define RTE_UART1_CTS_MUX 12 +#define RTE_UART1_CTS_PAD 9 +#else + #error "Invalid UART1 RTE_UART1_CTS_PIN Pin Configuration!" +#endif + +// UART1_RTS <0=>P0_10 <1=>P0_27 <2=>P0_50 <3=>P0_64 <4=>P0_70 <5=>P0_72 <6=>P0_31 +// RTS of UART1 +#ifndef CHIP_917_6x6 +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_UART1_RTS_PORT_ID 1 +#else +#define RTE_UART1_RTS_PORT_ID 0 +#endif +#if((RTE_UART1_RTS_PORT_ID == 6)) + #error "Invalid UART1 RTE_UART1_RTS_PIN Configuration!" +#endif +#endif + +#ifdef CHIP_917_6x6 +#define RTE_UART1_RTS_PORT_ID 6 +#if((RTE_UART1_RTS_PORT_ID == 2)||(RTE_UART1_RTS_PORT_ID == 3)||(RTE_UART1_RTS_PORT_ID == 5)) + #error "Invalid UART1 RTE_UART1_RTS_PIN Configuration!" +#endif +#endif +#if(RTE_UART1_RTS_PORT_ID ==0) +#define RTE_UART1_RTS_PORT 0 +#define RTE_UART1_RTS_PIN 10 +#define RTE_UART1_RTS_MUX 6 +#define RTE_UART1_RTS_PAD 5 +#elif(RTE_UART1_RTS_PORT_ID == 1) +#define RTE_UART1_RTS_PORT 0 +#define RTE_UART1_RTS_PIN 27 +#define RTE_UART1_RTS_MUX 6 +#define RTE_UART1_RTS_PAD 0//no pad +#elif(RTE_UART1_RTS_PORT_ID ==2) +#define RTE_UART1_RTS_PORT 0 +#define RTE_UART1_RTS_PIN 50 +#define RTE_UART1_RTS_MUX 9 +#define RTE_UART1_RTS_PAD 14 +#elif(RTE_UART1_RTS_PORT_ID ==3) +#define RTE_UART1_RTS_PORT 0 +#define RTE_UART1_RTS_PIN 64 +#define RTE_UART1_RTS_MUX 9 +#define RTE_UART1_RTS_PAD 22 +#elif(RTE_UART1_RTS_PORT_ID ==4) +#define RTE_UART1_RTS_PORT 0 +#define RTE_UART1_RTS_PIN 70 +#define RTE_UART1_RTS_MUX 6 +#define RTE_UART1_RTS_PAD 28 +#elif(RTE_UART1_RTS_PORT_ID ==5) +#define RTE_UART1_RTS_PORT 0 +#define RTE_UART1_RTS_PIN 72 +#define RTE_UART1_RTS_MUX 9 +#define RTE_UART1_RTS_PAD 30 +#elif(RTE_UART1_RTS_PORT_ID ==6) +#define RTE_UART1_RTS_PORT 0 +#define RTE_UART1_RTS_PIN 31 +#define RTE_UART1_RTS_MUX 12 +#define RTE_UART1_RTS_PAD 9 +#else + #error "Invalid UART1 RTE_UART1_RTS_PIN Pin Configuration!" +#endif +// + +// ULP_UART [Driver_ULP_UART] +// Configuration settings for Driver_ULP_UART in component ::CMSIS Driver:USART +#define RTE_ULP_UART 1 + +#define RTE_ULP_UART_CLK_SRC ULP_UART_REF_CLK +#define RTE_ULP_UART_CLK_DIV_FACT 0 +#define RTE_ULP_UART_FRAC_SEL USART_FRACTIONAL_DIVIDER + +#define RTE_ULP_UART_LOOPBACK 0 +#define RTE_ULP_UART_DMA_MODE1_EN 0 + +#define RTE_ULP_UART_TX_FIFO_THRESHOLD USART_TRIGGER_TX_EMPTY +#define RTE_ULP_UART_RX_FIFO_THRESHOLD USART_TRIGGER_RX_AEMPTY + +#define RTE_ULP_UART_DMA_TX_LEN_PER_DES 1024 +#define RTE_ULP_UART_DMA_RX_LEN_PER_DES 1024 + +#define RTE_ULPUART_CHNL_UDMA_TX_EN 0 +#define RTE_ULPUART_CHNL_UDMA_TX_CH 1 + +#define RTE_ULPUART_CHNL_UDMA_RX_EN 0 +#define RTE_ULPUART_CHNL_UDMA_RX_CH 0 + +/*ULPSS UART PINS*/ +// UART1_TX <0=>P0_3 <1=>P0_7 <2=>P0_11 +// TX of ULPSS UART +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_VER2 +#define RTE_ULP_UART_TX_PORT_ID 2 +#else +#define RTE_ULP_UART_TX_PORT_ID 1 +#endif +#if (RTE_ULP_UART_TX_PORT_ID == 0) +#define RTE_ULP_UART_TX_PORT 0 +#define RTE_ULP_UART_TX_PIN 3 +#define RTE_ULP_UART_TX_MUX 3 +#elif (RTE_ULP_UART_TX_PORT_ID == 1) +#define RTE_ULP_UART_TX_PORT 0 +#define RTE_ULP_UART_TX_PIN 7 +#define RTE_ULP_UART_TX_MUX 3 +#elif (RTE_ULP_UART_TX_PORT_ID == 2) +#define RTE_ULP_UART_TX_PORT 0 +#define RTE_ULP_UART_TX_PIN 11 +#define RTE_ULP_UART_TX_MUX 3 +#else +#error "Invalid ULPSS UART RTE_ULP_UART_TX_PIN Pin Configuration!" +#endif + +// UART1_RX <0=>P0_2 <1=>P0_6 <2=>P0_9 +// RX of ULPSS UART +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_VER2 +#define RTE_ULP_UART_RX_PORT_ID 2 +#else +#define RTE_ULP_UART_RX_PORT_ID 1 +#endif +#if (RTE_ULP_UART_RX_PORT_ID == 0) +#define RTE_ULP_UART_RX_PORT 0 +#define RTE_ULP_UART_RX_PIN 2 +#define RTE_ULP_UART_RX_MUX 3 +#elif (RTE_ULP_UART_RX_PORT_ID == 1) +#define RTE_ULP_UART_RX_PORT 0 +#define RTE_ULP_UART_RX_PIN 6 +#define RTE_ULP_UART_RX_MUX 3 +#elif (RTE_ULP_UART_RX_PORT_ID == 2) +#define RTE_ULP_UART_RX_PORT 0 +#define RTE_ULP_UART_RX_PIN 9 +#define RTE_ULP_UART_RX_MUX 3 +#else +#error "Invalid ULPSS UART RTE_ULP_UART_RX_PIN Pin Configuration!" +#endif + +// UART1_CTS <0=>P0_1 <1=>P0_5 <2=>P0_8 +// CTS of ULPSS UART +#define RTE_ULP_UART_CTS_PORT_ID 1 +#if(RTE_ULP_UART_CTS_PORT_ID ==0) +#define RTE_ULP_UART_CTS_PORT 0 +#define RTE_ULP_UART_CTS_PIN 1 +#define RTE_ULP_UART_CTS_MUX 3 +#elif(RTE_ULP_UART_CTS_PORT_ID ==1) +#define RTE_ULP_UART_CTS_PORT 0 +#define RTE_ULP_UART_CTS_PIN 5 +#define RTE_ULP_UART_CTS_MUX 3 +#elif(RTE_ULP_UART_CTS_PORT_ID ==2) +#define RTE_ULP_UART_CTS_PORT 0 +#define RTE_ULP_UART_CTS_PIN 8 +#define RTE_ULP_UART_CTS_MUX 3 +#else + #error "Invalid ULPSS UART RTE_ULP_UART_CTS_PIN Pin Configuration!" +#endif + +// UART1_RTS <0=>P0_0 <1=>P0_4 <2=>P0_10 +// RTS of ULPSS UART +#define RTE_ULP_UART_RTS_PORT_ID 1 +#if(RTE_ULP_UART_RTS_PORT_ID ==0) +#define RTE_ULP_UART_RTS_PORT 0 +#define RTE_ULP_UART_RTS_PIN 0 +#define RTE_ULP_UART_RTS_MUX 3 +#elif(RTE_ULP_UART_RTS_PORT_ID ==1) +#define RTE_ULP_UART_RTS_PORT 0 +#define RTE_ULP_UART_RTS_PIN 4 +#define RTE_ULP_UART_RTS_MUX 3 +#elif(RTE_ULP_UART_RTS_PORT_ID ==2) +#define RTE_ULP_UART_RTS_PORT 0 +#define RTE_ULP_UART_RTS_PIN 10 +#define RTE_ULP_UART_RTS_MUX 8 +#else + #error "Invalid ULPSS UART RTE_ULP_UART_RTS_PIN Pin Configuration!" +#endif +// + + + +// SSI_MASTER (Serial Peripheral Interface 1) [Driver_SSI_MASTER] +// Configuration settings for Driver_SSI_MASTER in component ::CMSIS Driver:SPI +#define RTE_SSI_MASTER 1 + +// SSI_MASTER_MISO Pin <0=>GPIO_12 <1=>GPIO_27 <2=>GPIO_57 +#ifndef CHIP_917_6x6 +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_SSI_MASTER_MISO_PORT_ID 1 +#else +#define RTE_SSI_MASTER_MISO_PORT_ID 0 +#endif +#if((RTE_SSI_MASTER_MISO_PORT_ID == 3)) + #error "Invalid SSI RTE_SSI_MASTER_MISO_PIN Configuration!" +#endif +#endif + +#ifdef CHIP_917_6x6 +#define RTE_SSI_MASTER_MISO_PORT_ID 3 +#if((RTE_SSI_MASTER_MISO_PORT_ID == 0)||(RTE_SSI_MASTER_MISO_PORT_ID == 2)) + #error "Invalid SSI RTE_SSI_MASTER_MISO_PIN Configuration!" +#endif +#endif +#if (RTE_SSI_MASTER_MISO_PORT_ID == 0) +#define RTE_SSI_MASTER_MISO 1 +#define RTE_SSI_MASTER_MISO_PORT 0 +#define RTE_SSI_MASTER_MISO_PIN 12 +#define RTE_SSI_MASTER_MISO_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_MISO_PADSEL 7 +#elif (RTE_SSI_MASTER_MISO_PORT_ID == 1) +#define RTE_SSI_MASTER_MISO 1 +#define RTE_SSI_MASTER_MISO_PORT 0 +#define RTE_SSI_MASTER_MISO_PIN 27 +#define RTE_SSI_MASTER_MISO_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_MISO_PADSEL 0//NO PAD +#elif (RTE_SSI_MASTER_MISO_PORT_ID == 2) +#define RTE_SSI_MASTER_MISO 1 +#define RTE_SSI_MASTER_MISO_PORT 0 +#define RTE_SSI_MASTER_MISO_PIN 57 +#define RTE_SSI_MASTER_MISO_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_MISO_PADSEL 21 +#elif (RTE_SSI_MASTER_MISO_PORT_ID == 3) +#define RTE_SSI_MASTER_MISO 1 +#define RTE_SSI_MASTER_MISO_PORT 0 +#define RTE_SSI_MASTER_MISO_PIN 10 +#define RTE_SSI_MASTER_MISO_MODE 12 +#define RTE_SSI_MASTER_MISO_PADSEL 5 +#else +#error "Invalid SSI_MASTER_MISO Pin Configuration!" +#endif + +// SSI_MASTER_MOSI Pin <0=>GPIO_11 <1=>GPIO_26 <2=>GPIO_56 +#define RTE_SSI_MASTER_MOSI_PORT_ID 1 +#ifdef CHIP_917_6x6 +#if((RTE_SSI_MASTER_MOSI_PORT_ID == 2)) + #error "Invalid SSI_MASTER_MOSI pin Configuration!" +#endif +#endif +#if (RTE_SSI_MASTER_MOSI_PORT_ID == 0) +#define RTE_SSI_MASTER_MOSI 1 +#define RTE_SSI_MASTER_MOSI_PORT 0 +#define RTE_SSI_MASTER_MOSI_PIN 11 +#define RTE_SSI_MASTER_MOSI_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_MOSI_PADSEL 6 +#elif (RTE_SSI_MASTER_MOSI_PORT_ID == 1) +#define RTE_SSI_MASTER_MOSI 1 +#define RTE_SSI_MASTER_MOSI_PORT 0 +#define RTE_SSI_MASTER_MOSI_PIN 26 +#define RTE_SSI_MASTER_MOSI_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_MOSI_PADSEL 0//NO PAD +#elif (RTE_SSI_MASTER_MOSI_PORT_ID == 2) +#define RTE_SSI_MASTER_MOSI 1 +#define RTE_SSI_MASTER_MOSI_PORT 0 +#define RTE_SSI_MASTER_MOSI_PIN 56 +#define RTE_SSI_MASTER_MOSI_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_MOSI_PADSEL 20 +#else +#error "Invalid SSI_MASTER_MOSI Pin Configuration!" +#endif + +// SSI_MASTER_SCK Pin <0=>GPIO_8 <1=>GPIO_25 <2=>GPIO_52 +#define RTE_SSI_MASTER_SCK_PORT_ID 1 +#ifdef CHIP_917_6x6 +#if((RTE_SSI_MASTER_SCK_PORT_ID == 2)) + #error "Invalid SSI_MASTER_SCK pin Configuration!" +#endif +#endif +#if (RTE_SSI_MASTER_SCK_PORT_ID == 0) +#define RTE_SSI_MASTER_SCK 1 +#define RTE_SSI_MASTER_SCK_PORT 0 +#define RTE_SSI_MASTER_SCK_PIN 8 +#define RTE_SSI_MASTER_SCK_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_SCK_PADSEL 3 +#elif (RTE_SSI_MASTER_SCK_PORT_ID == 1) +#define RTE_SSI_MASTER_SCK 1 +#define RTE_SSI_MASTER_SCK_PORT 0 +#define RTE_SSI_MASTER_SCK_PIN 25 +#define RTE_SSI_MASTER_SCK_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_SCK_PADSEL 0//NO PAD +#elif (RTE_SSI_MASTER_SCK_PORT_ID == 2) +#define RTE_SSI_MASTER_SCK 1 +#define RTE_SSI_MASTER_SCK_PORT 0 +#define RTE_SSI_MASTER_SCK_PIN 52 +#define RTE_SSI_MASTER_SCK_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_SCK_PADSEL 16 +#else +#error "Invalid SSI_MASTER_SCK Pin Configuration!" +#endif + +#define M4_SSI_CS0 1 +#define M4_SSI_CS1 0 +#ifndef CHIP_917_6x6 +#define M4_SSI_CS2 0 +#define M4_SSI_CS3 0 +#endif + +// SSI_MASTER_CS Pin <0=>GPIO_9 <1=>GPIO_28 <2=>GPIO_53 <3=>GPIO_10 <4=>GPIO_15 <5=>GPIO_50 <6=>GPIO_51 +#define RTE_SSI_MASTER_CS0_PORT_ID 1 +#ifdef CHIP_917_6x6 +#if((RTE_SSI_MASTER_CS0_PORT_ID == 2)) + #error "Invalid SSI_MASTER_CS pin Configuration!" +#endif +#endif +#if (RTE_SSI_MASTER_CS0_PORT_ID == 0) +#define RTE_SSI_MASTER_CS0 M4_SSI_CS0 +#define RTE_SSI_MASTER_CS0_PORT 0 +#define RTE_SSI_MASTER_CS0_PIN 9 +#define RTE_SSI_MASTER_CS0_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_CS0_PADSEL 4 +#elif (RTE_SSI_MASTER_CS0_PORT_ID == 1) +#define RTE_SSI_MASTER_CS0 M4_SSI_CS0 +#define RTE_SSI_MASTER_CS0_PORT 0 +#define RTE_SSI_MASTER_CS0_PIN 28 +#define RTE_SSI_MASTER_CS0_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_CS0_PADSEL 0//NO PAD +#elif (RTE_SSI_MASTER_CS0_PORT_ID == 2) +#define RTE_SSI_MASTER_CS0 M4_SSI_CS0 +#define RTE_SSI_MASTER_CS0_PORT 0 +#define RTE_SSI_MASTER_CS0_PIN 53 +#define RTE_SSI_MASTER_CS0_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_CS0_PADSEL 17 +#else +#error "Invalid SSI_MASTER_CS0 Pin Configuration!" +#endif + +//CS1 +#define RTE_SSI_MASTER_CS1_PORT_ID 0 +#if (RTE_SSI_MASTER_CS1_PORT_ID == 0) +#define RTE_SSI_MASTER_CS1 M4_SSI_CS1 +#define RTE_SSI_MASTER_CS1_PORT 0 +#define RTE_SSI_MASTER_CS1_PIN 10 +#define RTE_SSI_MASTER_CS1_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_CS1_PADSEL 5 +#else +#error "Invalid SSI_MASTER_CS1 Pin Configuration!" +#endif + +#ifndef CHIP_917_6x6 +//CS2 +#define RTE_SSI_MASTER_CS2_PORT_ID 1 +#if (RTE_SSI_MASTER_CS2_PORT_ID == 0) +#define RTE_SSI_MASTER_CS2 M4_SSI_CS2 +#define RTE_SSI_MASTER_CS2_PORT 0 +#define RTE_SSI_MASTER_CS2_PIN 15 +#define RTE_SSI_MASTER_CS2_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_CS2_PADSEL 8 +#elif (RTE_SSI_MASTER_CS2_PORT_ID == 1) +#define RTE_SSI_MASTER_CS2 M4_SSI_CS2 +#define RTE_SSI_MASTER_CS2_PORT 0 +#define RTE_SSI_MASTER_CS2_PIN 50 +#define RTE_SSI_MASTER_CS2_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_CS2_PADSEL 14 +#else +#error "Invalid SSI_MASTER_CS2 Pin Configuration!" +#endif + + +//CS3 +#define RTE_SSI_MASTER_CS3_PORT_ID 0 +#if (RTE_SSI_MASTER_CS3_PORT_ID == 0) +#define RTE_SSI_MASTER_CS3 M4_SSI_CS3 +#define RTE_SSI_MASTER_CS3_PORT 0 +#define RTE_SSI_MASTER_CS3_PIN 51 +#define RTE_SSI_MASTER_CS3_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_CS3_PADSEL 15 +#else +#error "Invalid SSI_MASTER_CS3 Pin Configuration!" +#endif +#endif + +// DMA Rx +// Channel <28=>28 +// Selects DMA Channel (only Channel 28 can be used) +// +#define RTE_SSI_MASTER_RX_DMA 0 +#define RTE_SSI_MASTER_UDMA_RX_CH 28 + +// DMA Tx +// Channel <29=>29 +// Selects DMA Channel (only Channel 29 can be used) +// +#define RTE_SSI_MASTER_TX_DMA 0 +#define RTE_SSI_MASTER_UDMA_TX_CH 29 +// + +// SSI_SLAVE (Serial Peripheral Interface 2) [Driver_SSI_SLAVE] +// Configuration settings for Driver_SSI_SLAVE in component ::CMSIS Driver:SPI +#define RTE_SSI_SLAVE 1 + + +#define RTE_SSI_SLAVE_INPUT_CLOCK SSISLAVE_CLK + +// SSI_SLAVE_MISO Pin <0=>Not Used <1=>GPIO_11 <2=>GPIO_28 <3=>GPIO_49 <4=>GPIO_57 +#define RTE_SSI_SLAVE_MISO_PORT_ID 2 +#ifdef CHIP_917_6x6 +#if((RTE_SSI_SLAVE_MISO_PORT_ID == 3)||(RTE_SSI_SLAVE_MISO_PORT_ID == 4)) + #error "Invalid SSI_SLAVE_MISO pin Configuration!" +#endif +#endif +#if (RTE_SSI_SLAVE_MISO_PORT_ID == 0) +#define RTE_SSI_SLAVE_MISO 0 +#elif (RTE_SSI_SLAVE_MISO_PORT_ID == 1) +#define RTE_SSI_SLAVE_MISO 1 +#define RTE_SSI_SLAVE_MISO_PORT 0 +#define RTE_SSI_SLAVE_MISO_PIN 11 +#define RTE_SSI_SLAVE_MISO_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_MISO_PADSEL 6 +#elif (RTE_SSI_SLAVE_MISO_PORT_ID == 2) +#define RTE_SSI_SLAVE_MISO 1 +#define RTE_SSI_SLAVE_MISO_PORT 0 +#define RTE_SSI_SLAVE_MISO_PIN 28 +#define RTE_SSI_SLAVE_MISO_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_MISO_PADSEL 0//no pad +#elif (RTE_SSI_SLAVE_MISO_PORT_ID == 3) +#define RTE_SSI_SLAVE_MISO 1 +#define RTE_SSI_SLAVE_MISO_PORT 0 +#define RTE_SSI_SLAVE_MISO_PIN 49 +#define RTE_SSI_SLAVE_MISO_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_MISO_PADSEL 13 +#elif (RTE_SSI_SLAVE_MISO_PORT_ID == 4) +#define RTE_SSI_SLAVE_MISO 1 +#define RTE_SSI_SLAVE_MISO_PORT 0 +#define RTE_SSI_SLAVE_MISO_PIN 57 +#define RTE_SSI_SLAVE_MISO_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_MISO_PADSEL 21 +#else +#error "Invalid SSI_SLAVE_MISO Pin Configuration!" +#endif + +// SSI_SLAVE_MOSI Pin <0=>Not Used <1=>GPIO_10 <2=>GPIO_27 <3=>GPIO_48 <4=>GPIO_56 +#ifndef CHIP_917_6x6 +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_SSI_SLAVE_MOSI_PORT_ID 2 +#else +#define RTE_SSI_SLAVE_MOSI_PORT_ID 1 +#endif +#endif + +#ifdef CHIP_917_6x6 +#define RTE_SSI_SLAVE_MOSI_PORT_ID 2 +#if((RTE_SSI_SLAVE_MOSI_PORT_ID == 3)||(RTE_SSI_SLAVE_MOSI_PORT_ID == 4)) + #error "Invalid SSI_SLAVE_MOSI pin Configuration!" +#endif +#endif +#if (RTE_SSI_SLAVE_MOSI_PORT_ID == 0) +#define RTE_SSI_SLAVE_MOSI 0 +#elif (RTE_SSI_SLAVE_MOSI_PORT_ID == 1) +#define RTE_SSI_SLAVE_MOSI 1 +#define RTE_SSI_SLAVE_MOSI_PORT 0 +#define RTE_SSI_SLAVE_MOSI_PIN 10 +#define RTE_SSI_SLAVE_MOSI_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_MOSI_PADSEL 5 +#elif (RTE_SSI_SLAVE_MOSI_PORT_ID == 2) +#define RTE_SSI_SLAVE_MOSI 1 +#define RTE_SSI_SLAVE_MOSI_PORT 0 +#define RTE_SSI_SLAVE_MOSI_PIN 27 +#define RTE_SSI_SLAVE_MOSI_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_MOSI_PADSEL 0 //no pad +#elif (RTE_SSI_SLAVE_MOSI_PORT_ID == 3) +#define RTE_SSI_SLAVE_MOSI 1 +#define RTE_SSI_SLAVE_MOSI_PORT 0 +#define RTE_SSI_SLAVE_MOSI_PIN 48 +#define RTE_SSI_SLAVE_MOSI_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_MOSI_PADSEL 12 +#elif (RTE_SSI_SLAVE_MOSI_PORT_ID == 4) +#define RTE_SSI_SLAVE_MOSI 1 +#define RTE_SSI_SLAVE_MOSI_PORT 0 +#define RTE_SSI_SLAVE_MOSI_PIN 56 +#define RTE_SSI_SLAVE_MOSI_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_MOSI_PADSEL 20 +#else +#error "Invalid SSI_SLAVE_MOSI Pin Configuration!" +#endif + +// SSI_SLAVE_SCK Pin <0=>Not Used <1=>GPIO_8 <2=>GPIO_26 <3=>GPIO_47 <4=>GPIO_52 +#define RTE_SSI_SLAVE_SCK_PORT_ID 2 +#ifdef CHIP_917_6x6 +#if((RTE_SSI_SLAVE_SCK_PORT_ID == 3)||(RTE_SSI_SLAVE_SCK_PORT_ID == 4)) + #error "Invalid SSI_SLAVE_SCK pin Configuration!" +#endif +#endif +#if (RTE_SSI_SLAVE_SCK_PORT_ID == 0) +#define RTE_SSI_SLAVE_SCK 0 +#elif (RTE_SSI_SLAVE_SCK_PORT_ID == 1) +#define RTE_SSI_SLAVE_SCK 1 +#define RTE_SSI_SLAVE_SCK_PORT 0 +#define RTE_SSI_SLAVE_SCK_PIN 8 +#define RTE_SSI_SLAVE_SCK_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_SCK_PADSEL 3 +#elif (RTE_SSI_SLAVE_SCK_PORT_ID == 2) +#define RTE_SSI_SLAVE_SCK 1 +#define RTE_SSI_SLAVE_SCK_PORT 0 +#define RTE_SSI_SLAVE_SCK_PIN 26 +#define RTE_SSI_SLAVE_SCK_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_SCK_PADSEL 0 //no pad +#elif (RTE_SSI_SLAVE_SCK_PORT_ID == 3) +#define RTE_SSI_SLAVE_SCK 1 +#define RTE_SSI_SLAVE_SCK_PORT 0 +#define RTE_SSI_SLAVE_SCK_PIN 47 +#define RTE_SSI_SLAVE_SCK_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_SCK_PADSEL 11 +#elif (RTE_SSI_SLAVE_SCK_PORT_ID == 4) +#define RTE_SSI_SLAVE_SCK 1 +#define RTE_SSI_SLAVE_SCK_PORT 0 +#define RTE_SSI_SLAVE_SCK_PIN 52 +#define RTE_SSI_SLAVE_SCK_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_SCK_PADSEL 16 +#else +#error "Invalid SSI_SLAVE_SCK Pin Configuration!" +#endif + +// SSI_SLAVE_CS Pin <0=>Not Used <1=>GPIO_9 <2=>GPIO_25 <3=>GPIO_46 <4=>GPIO_53 +#define RTE_SSI_SLAVE_CS_PORT_ID 1 +#ifdef CHIP_917_6x6 +#if((RTE_SSI_SLAVE_CS_PORT_ID == 3)||(RTE_SSI_SLAVE_CS_PORT_ID == 4)) + #error "Invalid SSI_SLAVE_CS pin Configuration!" +#endif +#endif +#if (RTE_SSI_SLAVE_CS_PORT_ID == 0) +#define RTE_SSI_SLAVE_CS 0 +#elif (RTE_SSI_SLAVE_CS_PORT_ID == 1) +#define RTE_SSI_SLAVE_CS 1 +#define RTE_SSI_SLAVE_CS_PORT 0 +#define RTE_SSI_SLAVE_CS_PIN 9 +#define RTE_SSI_SLAVE_CS_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_CS_PADSEL 4 +#elif (RTE_SSI_SLAVE_CS_PORT_ID == 2) +#define RTE_SSI_SLAVE_CS 1 +#define RTE_SSI_SLAVE_CS_PORT 0 +#define RTE_SSI_SLAVE_CS_PIN 25 +#define RTE_SSI_SLAVE_CS_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_CS_PADSEL 0//no pad +#elif (RTE_SSI_SLAVE_CS_PORT_ID == 3) +#define RTE_SSI_SLAVE_CS 1 +#define RTE_SSI_SLAVE_CS_PORT 0 +#define RTE_SSI_SLAVE_CS_PIN 46 +#define RTE_SSI_SLAVE_CS_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_CS_PADSEL 10 +#elif (RTE_SSI_SLAVE_CS_PORT_ID == 4) +#define RTE_SSI_SLAVE_CS 1 +#define RTE_SSI_SLAVE_CS_PORT 0 +#define RTE_SSI_SLAVE_CS_PIN 53 +#define RTE_SSI_SLAVE_CS_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_CS_PADSEL 17 +#else +#error "Invalid SSI_SLAVE_CS Pin Configuration!" +#endif + +// DMA Rx +// Channel <22=>22 +// Selects DMA Channel (only Channel 22 can be used) +// +#define RTE_SSI_SLAVE_RX_DMA 1 +#define RTE_SSI_SLAVE_UDMA_RX_CH 22 +#define RTE_SSI_SLAVE_DMA_RX_LEN_PER_DES 1024 + +// DMA Tx +// Channel <23=>23 +// Selects DMA Channel (only Channel 23 can be used) +// +#define RTE_SSI_SLAVE_TX_DMA 1 +#define RTE_SSI_SLAVE_UDMA_TX_CH 23 +#define RTE_SSI_SLAVE_DMA_TX_LEN_PER_DES 1024 + +// + +// SSI_ULP_MASTER (Serial Peripheral Interface 3) [Driver_SSI_ULP_MASTER] +// Configuration settings for Driver_SSI_ULP_MASTER in component ::CMSIS Driver:SPI +#define RTE_SSI_ULP_MASTER 1 + +// Enable multiple CSN lines +#define ULP_SSI_CS0 1 +#define ULP_SSI_CS1 0 +#define ULP_SSI_CS2 0 + +// SSI_ULP_MASTER_MISO Pin <0=>Not Used <1=>ULP_GPIO_2 <2=>ULP_GPIO_9 +#define RTE_SSI_ULP_MASTER_MISO_PORT_ID 2 +#if (RTE_SSI_ULP_MASTER_MISO_PORT_ID == 0) +#define RTE_SSI_ULP_MASTER_MISO 0 +#elif (RTE_SSI_ULP_MASTER_MISO_PORT_ID == 1) +#if ( (PACKAGE_TYPE == CC0 ) || (PACKAGE_TYPE == SB0N_B00) || (PACKAGE_TYPE == SB00_B00) ) +#define RTE_SSI_ULP_MASTER_MISO 1 +#define RTE_SSI_ULP_MASTER_MISO_PORT 0 +#define RTE_SSI_ULP_MASTER_MISO_PIN 2 +#define RTE_SSI_ULP_MASTER_MISO_MODE 1 +#else + #error "Change RTE_SSI_ULP_MASTER_MISO_PORT_ID other than '1' as per PACKAGE_TYPE" +#endif +#elif (RTE_SSI_ULP_MASTER_MISO_PORT_ID == 2) +#define RTE_SSI_ULP_MASTER_MISO 1 +#define RTE_SSI_ULP_MASTER_MISO_PORT 0 +#define RTE_SSI_ULP_MASTER_MISO_PIN 9 +#define RTE_SSI_ULP_MASTER_MISO_MODE 1 +#else +#error "Invalid SSI_ULP_MISO Pin Configuration!" +#endif + +// SSI_ULP_MASTER_MOSI Pin <0=>Not Used <1=>ULP_GPIO_1 <2=>ULP_GPIO_11 +#define RTE_SSI_ULP_MASTER_MOSI_PORT_ID 2 +#if (RTE_SSI_ULP_MASTER_MOSI_PORT_ID == 0) +#define RTE_SSI_ULP_MASTER_MOSI 0 +#elif (RTE_SSI_ULP_MASTER_MOSI_PORT_ID == 1) +#if ( !(PACKAGE_TYPE == SB0N_WMS )) +#define RTE_SSI_ULP_MASTER_MOSI 1 +#define RTE_SSI_ULP_MASTER_MOSI_PORT 0 +#define RTE_SSI_ULP_MASTER_MOSI_PIN 1 +#define RTE_SSI_ULP_MASTER_MOSI_MODE 1 +#else + #error "Change RTE_SSI_ULP_MASTER_MOSI_PORT_ID other than '1' as per PACKAGE_TYPE" +#endif +#elif (RTE_SSI_ULP_MASTER_MOSI_PORT_ID == 2) +#define RTE_SSI_ULP_MASTER_MOSI 1 +#define RTE_SSI_ULP_MASTER_MOSI_PORT 0 +#define RTE_SSI_ULP_MASTER_MOSI_PIN 11 +#define RTE_SSI_ULP_MASTER_MOSI_MODE 1 +#else +#error "Invalid SSI_ULP_MOSI Pin Configuration!" +#endif + +// SSI_ULP_MASTER_SCK Pin <0=>Not Used <1=>ULP_GPIO_0 <2=>ULP_GPIO_8 +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_SSI_ULP_MASTER_SCK_PORT_ID 1 +#else +#define RTE_SSI_ULP_MASTER_SCK_PORT_ID 2 +#endif +#if (RTE_SSI_ULP_MASTER_SCK_PORT_ID == 0) +#define RTE_SSI_ULP_MASTER_SCK 0 +#elif (RTE_SSI_ULP_MASTER_SCK_PORT_ID == 1) +#define RTE_SSI_ULP_MASTER_SCK 1 +#define RTE_SSI_ULP_MASTER_SCK_PORT 0 +#define RTE_SSI_ULP_MASTER_SCK_PIN 0 +#define RTE_SSI_ULP_MASTER_SCK_MODE 1 +#elif (RTE_SSI_ULP_MASTER_SCK_PORT_ID == 2) +#define RTE_SSI_ULP_MASTER_SCK 1 +#define RTE_SSI_ULP_MASTER_SCK_PORT 0 +#define RTE_SSI_ULP_MASTER_SCK_PIN 8 +#define RTE_SSI_ULP_MASTER_SCK_MODE 1 +#else +#error "Invalid SSI_ULP_SCK Pin Configuration!" +#endif + +// CS0 +#define RTE_SSI_ULP_MASTER_CS0_PORT_ID 0 +#if (RTE_SSI_ULP_MASTER_CS0_PORT_ID == 0) +#define RTE_SSI_ULP_MASTER_CS0 ULP_SSI_CS0 +#define RTE_SSI_ULP_MASTER_CS0_PORT 0 +#define RTE_SSI_ULP_MASTER_CS0_PIN 3 +#define RTE_SSI_ULP_MASTER_CS0_MODE 1 +#elif (RTE_SSI_ULP_MASTER_CS0_PORT_ID == 1) +#define RTE_SSI_ULP_MASTER_CS0 ULP_SSI_CS0 +#define RTE_SSI_ULP_MASTER_CS0_PORT 0 +#define RTE_SSI_ULP_MASTER_CS0_PIN 10 +#define RTE_SSI_ULP_MASTER_CS0_MODE 1 +#else + #error "Change RTE_SSI_ULP_MASTER_CS_PORT_ID other than '1' or'3' as per PACKAGE_TYPE" +#endif + +// CS1 +#define RTE_SSI_ULP_MASTER_CS1 ULP_SSI_CS1 +#define RTE_SSI_ULP_MASTER_CS1_PORT 0 +#define RTE_SSI_ULP_MASTER_CS1_PIN 4 +#define RTE_SSI_ULP_MASTER_CS1_MODE 1 + +// CS2 +#define RTE_SSI_ULP_MASTER_CS2 ULP_SSI_CS2 +#define RTE_SSI_ULP_MASTER_CS2_PORT 0 +#define RTE_SSI_ULP_MASTER_CS2_PIN 6 +#define RTE_SSI_ULP_MASTER_CS2_MODE 1 + + +// DMA Rx +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// +#define RTE_SSI_ULP_MASTER_RX_DMA 1 +#define RTE_SSI_ULP_MASTER_UDMA_RX_CH 2 +#define RTE_SSI_ULP_MASTER_DMA_RX_LEN_PER_DES 96 + +// DMA Tx +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// +#define RTE_SSI_ULP_MASTER_TX_DMA 1 +#define RTE_SSI_ULP_MASTER_UDMA_TX_CH 3 +#define RTE_SSI_ULP_MASTER_DMA_TX_LEN_PER_DES 96 + +// +/*=================================================================== + UDMA Defines +====================================================================*/ +// UDMA [Driver_UDMA] +#define DESC_MAX_LEN 0x400 +#define RTE_UDMA0 1 +#define UDMA0_IRQHandler IRQ033_Handler +#define CHNL_MASK_REQ0 0 +#define CHNL_PRIORITY0 0 +#define DMA_PERI_ACK0 0 +#define BURST_REQ0_EN 1 +#define UDMA0_CHNL_PRIO_LVL 1 +#define UDMA0_SRAM_BASE 0x1FC00 + +#define RTE_UDMA1 1 +#define UDMA1_IRQHandler IRQ010_Handler +#define CHNL_MASK_REQ1 0 +#define CHNL_PRIORITY1 0 +#define BURST_REQ1_EN 1 +#define CHNL_HIGH_PRIO_EN1 1 +#define UDMA1_CHNL_PRIO_LVL 1 +#define ULP_SRAM_START_ADDR 0x24060000 +#define ULP_SRAM_END_ADDR 0x24063E00 +// RTE_UDMA1_BASE_MEM <0=>PS2 <1=>PS4 +#define RTE_UDMA1_BASE_MEM 0 +#if(RTE_UDMA1_BASE_MEM == 0) +#define UDMA1_SRAM_BASE 0x24060000 +#elif(RTE_UDMA1_BASE_MEM == 1) +#define UDMA1_SRAM_BASE 0x1CC00 +#else + #error "Invalid UDMA1 Control Base Address!" +#endif +// + +// I2S0 [Driver_I2S0] +// Configuration settings for Driver_I2S0 in component ::CMSIS Driver:I2S + +#define RTE_I2S0 1 +#define I2S0_IRQHandler IRQ064_Handler +/*I2S0 PINS*/ + +// I2S0_SCLK <0=>P0_8 <1=>P0_25 <2=>P0_46 <3=>P0_52 +// SCLK of I2S0 +#define RTE_I2S0_SCLK_PORT_ID 1 +#ifdef CHIP_917_6x6 +#if((RTE_I2S0_SCLK_PORT_ID == 2)||(RTE_I2S0_SCLK_PORT_ID == 3)) + #error "Invalid I2S0 RTE_I2S0_SCLK pin Configuration!" +#endif +#endif +#if(RTE_I2S0_SCLK_PORT_ID == 0) +#define RTE_I2S0_SCLK_PORT 0 +#define RTE_I2S0_SCLK_PIN 8 +#define RTE_I2S0_SCLK_MUX 7 +#define RTE_I2S0_SCLK_PAD 3 +#elif(RTE_I2S0_SCLK_PORT_ID ==1) +#define RTE_I2S0_SCLK_PORT 0 +#define RTE_I2S0_SCLK_PIN 25 +#define RTE_I2S0_SCLK_MUX 7 +#define RTE_I2S0_SCLK_PAD 0//no pad +#elif(RTE_I2S0_SCLK_PORT_ID ==2) +#define RTE_I2S0_SCLK_PORT 0 +#define RTE_I2S0_SCLK_PIN 46 +#define RTE_I2S0_SCLK_MUX 7 +#define RTE_I2S0_SCLK_PAD 10 +#elif(RTE_I2S0_SCLK_PORT_ID ==3) +#define RTE_I2S0_SCLK_PORT 0 +#define RTE_I2S0_SCLK_PIN 52 +#define RTE_I2S0_SCLK_MUX 7 +#define RTE_I2S0_SCLK_PAD 16 +#else + #error "Invalid I2S0 RTE_I2S0_SCLK Pin Configuration!" +#endif + +// I2S0_WSCLK <0=>P0_9 <1=>P0_26 <2=>P0_47 <3=>P0_53 +// WSCLK for I2S0 +#define RTE_I2S0_WSCLK_PORT_ID 1 +#ifdef CHIP_917_6x6 +#if((RTE_I2S0_WSCLK_PORT_ID == 2)||(RTE_I2S0_WSCLK_PORT_ID == 3)) + #error "Invalid I2S0 RTE_I2S0_WSCLK pin Configuration!" +#endif +#endif +#if(RTE_I2S0_WSCLK_PORT_ID == 0) +#define RTE_I2S0_WSCLK_PORT 0 +#define RTE_I2S0_WSCLK_PIN 9 +#define RTE_I2S0_WSCLK_MUX 7 +#define RTE_I2S0_WSCLK_PAD 4 +#elif(RTE_I2S0_WSCLK_PORT_ID == 1) +#define RTE_I2S0_WSCLK_PORT 0 +#define RTE_I2S0_WSCLK_PIN 26 +#define RTE_I2S0_WSCLK_MUX 7 +#define RTE_I2S0_WSCLK_PAD 0//no pad +#elif(RTE_I2S0_WSCLK_PORT_ID ==2) +#define RTE_I2S0_WSCLK_PORT 0 +#define RTE_I2S0_WSCLK_PIN 47 +#define RTE_I2S0_WSCLK_MUX 7 +#define RTE_I2S0_WSCLK_PAD 11 +#elif(RTE_I2S0_WSCLK_PORT_ID ==3) +#define RTE_I2S0_WSCLK_PORT 0 +#define RTE_I2S0_WSCLK_PIN 53 +#define RTE_I2S0_WSCLK_MUX 7 +#define RTE_I2S0_WSCLK_PAD 17 +#else + #error "Invalid I2S0 RTE_I2S0_WSCLK Pin Configuration!" +#endif + +// I2S0_DOUT0 <0=>P0_11 <1=>P0_28 <2=>P0_49 <3=>P0_57 +// DOUT0 for I2S0 +#define RTE_I2S0_DOUT0_PORT_ID 1 +#ifdef CHIP_917_6x6 +#if((RTE_I2S0_DOUT0_PORT_ID == 2)||(RTE_I2S0_DOUT0_PORT_ID == 3)) + #error "Invalid I2S0 RTE_I2S0_DOUT0 pin Configuration!" +#endif +#endif +#if(RTE_I2S0_DOUT0_PORT_ID ==0) +#define RTE_I2S0_DOUT0_PORT 0 +#define RTE_I2S0_DOUT0_PIN 11 +#define RTE_I2S0_DOUT0_MUX 7 +#define RTE_I2S0_DOUT0_PAD 6 +#elif(RTE_I2S0_DOUT0_PORT_ID ==1) +#define RTE_I2S0_DOUT0_PORT 0 +#define RTE_I2S0_DOUT0_PIN 28 +#define RTE_I2S0_DOUT0_MUX 7 +#define RTE_I2S0_DOUT0_PAD 0// no pad +#elif(RTE_I2S0_DOUT0_PORT_ID ==2) +#define RTE_I2S0_DOUT0_PORT 0 +#define RTE_I2S0_DOUT0_PIN 49 +#define RTE_I2S0_DOUT0_MUX 7 +#define RTE_I2S0_DOUT0_PAD 13 +#elif(RTE_I2S0_DOUT0_PORT_ID ==3) +#define RTE_I2S0_DOUT0_PORT 0 +#define RTE_I2S0_DOUT0_PIN 57 +#define RTE_I2S0_DOUT0_MUX 7 +#define RTE_I2S0_DOUT0_PAD 21 +#else + #error "Invalid I2S0 RTE_I2S0_DOUT0 Pin Configuration!" +#endif + +// I2S0_DIN0 <0=>P0_10 <1=>P0_27 <2=>P0_48 <3=>P0_56 +// DIN0 for I2S0 +#define RTE_I2S0_DIN0_PORT_ID 1 +#ifdef CHIP_917_6x6 +#if((RTE_I2S0_DIN0_PORT_ID == 2)||(RTE_I2S0_DIN0_PORT_ID == 3)) + #error "Invalid USART0 RTE_I2S0_DIN0 pin Configuration!" +#endif +#endif +#if(RTE_I2S0_DIN0_PORT_ID ==0) +#define RTE_I2S0_DIN0_PORT 0 +#define RTE_I2S0_DIN0_PIN 10 +#define RTE_I2S0_DIN0_MUX 7 +#define RTE_I2S0_DIN0_PAD 5 +#elif(RTE_I2S0_DIN0_PORT_ID ==1) +#define RTE_I2S0_DIN0_PORT 0 +#define RTE_I2S0_DIN0_PIN 27 +#define RTE_I2S0_DIN0_MUX 7 +#define RTE_I2S0_DIN0_PAD 0 // no pad +#elif(RTE_I2S0_DIN0_PORT_ID ==2) +#define RTE_I2S0_DIN0_PORT 0 +#define RTE_I2S0_DIN0_PIN 48 +#define RTE_I2S0_DIN0_MUX 7 +#define RTE_I2S0_DIN0_PAD 12 +#elif(RTE_I2S0_DIN0_PORT_ID ==3) +#define RTE_I2S0_DIN0_PORT 0 +#define RTE_I2S0_DIN0_PIN 56 +#define RTE_I2S0_DIN0_MUX 7 +#define RTE_I2S0_DIN0_PAD 20 +#else + #error "Invalid I2S0 RTE_I2S0_DIN0 Pin Configuration!" +#endif + +// I2S0_DOUT1 <0=>P0_7 <1=>P0_30 <2=>P0_51 <3=>P0_55 +// DOUT1 for I2S0 +#ifndef CHIP_917_6x6 +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_I2S0_DOUT1_PORT_ID 1 +#else +#define RTE_I2S0_DOUT1_PORT_ID 0 +#endif +#endif +#ifdef CHIP_917_6x6 +#define RTE_I2S0_DOUT1_PORT_ID 1 +#if((RTE_I2S0_DOUT1_PORT_ID == 2)||(RTE_I2S0_DOUT1_PORT_ID == 3)) + #error "Invalid I2S0 RTE_I2S0_DOUT1 pin Configuration!" +#endif +#endif +#if(RTE_I2S0_DOUT1_PORT_ID ==0) +#define RTE_I2S0_DOUT1_PORT 0 +#define RTE_I2S0_DOUT1_PIN 7 +#define RTE_I2S0_DOUT1_MUX 7 +#define RTE_I2S0_DOUT1_PAD 2 +#elif(RTE_I2S0_DOUT1_PORT_ID ==1) +#define RTE_I2S0_DOUT1_PORT 0 +#define RTE_I2S0_DOUT1_PIN 30 +#define RTE_I2S0_DOUT1_MUX 7 +#define RTE_I2S0_DOUT1_PAD 0//no pad +#elif(RTE_I2S0_DOUT1_PORT_ID ==2) +#define RTE_I2S0_DOUT1_PORT 0 +#define RTE_I2S0_DOUT1_PIN 51 +#define RTE_I2S0_DOUT1_MUX 7 +#define RTE_I2S0_DOUT1_PAD 15 +#elif(RTE_I2S0_DOUT1_PORT_ID ==3) +#define RTE_I2S0_DOUT1_PORT 0 +#define RTE_I2S0_DOUT1_PIN 55 +#define RTE_I2S0_DOUT1_MUX 7 +#define RTE_I2S0_DOUT1_PAD 19 +#else + #error "Invalid I2S0 RTE_I2S0_DOUT1 Pin Configuration!" +#endif + +// I2S0_DIN1 <0=>P0_6 <1=>P0_29 <2=>P0_50 <3=>P0_54 +// DIN1 for I2S0 +#define RTE_I2S0_DIN1_PORT_ID 0 +#ifdef CHIP_917_6x6 +#if((RTE_I2S0_DIN1_PORT_ID == 2)||(RTE_I2S0_DIN1_PORT_ID == 3)) + #error "Invalid I2S0 RTE_I2S0_DIN1 pin Configuration!" +#endif +#endif +#if(RTE_I2S0_DIN1_PORT_ID ==0) +#define RTE_I2S0_DIN1_PORT 0 +#define RTE_I2S0_DIN1_PIN 6 +#define RTE_I2S0_DIN1_MUX 7 +#define RTE_I2S0_DIN1_PAD 1 +#elif(RTE_I2S0_DIN1_PORT_ID ==1) +#define RTE_I2S0_DIN1_PORT 0 +#define RTE_I2S0_DIN1_PIN 29 +#define RTE_I2S0_DIN1_MUX 7 +#define RTE_I2S0_DIN1_PAD 0//no pad +#elif(RTE_I2S0_DIN1_PORT_ID ==2) +#define RTE_I2S0_DIN1_PORT 0 +#define RTE_I2S0_DIN1_PIN 50 +#define RTE_I2S0_DIN1_MUX 7 +#define RTE_I2S0_DIN1_PAD 14 +#elif(RTE_I2S0_DIN1_PORT_ID ==3) +#define RTE_I2S0_DIN1_PORT 0 +#define RTE_I2S0_DIN1_PIN 54 +#define RTE_I2S0_DIN1_MUX 7 +#define RTE_I2S0_DIN1_PAD 18 +#else + #error "Invalid I2S0 RTE_I2S0_DIN1 Pin Configuration!" +#endif +// FIFO level can have value 1 to 7 +#define I2S0_TX_FIFO_LEVEL ( 2U ) +#define I2S0_RX_FIFO_LEVEL ( 2U ) + +// I2S0_TX_RES <0=>12 +// <1=>16 +// <2=>20 +// <3=>24 +#define RTE_I2S0_TX_RES 1 +#if (RTE_I2S0_TX_RES ==0) +#define I2S0_TX_RES RES_12_BIT +#elif(RTE_I2S0_TX_RES ==1) +#define I2S0_TX_RES RES_16_BIT +#elif(RTE_I2S0_TX_RES ==2) +#define I2S0_TX_RES RES_20_BIT +#elif(RTE_I2S0_TX_RES ==3) +#define I2S0_TX_RES RES_24_BIT +#else + #error "Invalid I2S0 TX channel resolution!" +#endif + +// I2S0_RX_RES <0=>12 +// <1=>16 +// <2=>20 +// <3=>24 +#define RTE_I2S0_RX_RES 1 +#if (RTE_I2S0_RX_RES ==0) +#define I2S0_RX_RES RES_12_BIT +#elif(RTE_I2S0_RX_RES ==1) +#define I2S0_RX_RES RES_16_BIT +#elif(RTE_I2S0_RX_RES ==2) +#define I2S0_RX_RES RES_20_BIT +#elif(RTE_I2S0_RX_RES ==3) +#define I2S0_RX_RES RES_24_BIT +#else + #error "Invalid I2S0 RX channel resolution!" +#endif + +#define RTE_I2S0_CHNL_UDMA_TX_EN 1 +#define RTE_I2S0_CHNL_UDMA_TX_CH 15 + +#define RTE_I2S0_CHNL_UDMA_RX_EN 1 +#define RTE_I2S0_CHNL_UDMA_RX_CH 14 + +#define RTE_I2S0_DMA_TX_LEN_PER_DES 1024 +#define RTE_I2S0_DMA_RX_LEN_PER_DES 1024 + +// + +// I2S1 [Driver_I2S1] +// Configuration settings for Driver_I2S1 in component ::Drivers:I2S +#define RTE_I2S1 1 +#define I2S1_IRQHandler IRQ014_Handler + +// I2S1_SCLK Pin <0=>P0_3 <1=>P0_7 <2=>P0_8 +/*I2S1 PINS*/ +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_I2S1_SCLK_PORT_ID 0 +#else +#define RTE_I2S1_SCLK_PORT_ID 2 +#endif +#if(RTE_I2S1_SCLK_PORT_ID == 0) +#define RTE_I2S1_SCLK_PORT 0 +#define RTE_I2S1_SCLK_PIN 3 +#define RTE_I2S1_SCLK_MUX 2 +#elif(RTE_I2S1_SCLK_PORT_ID ==1) +#define RTE_I2S1_SCLK_PORT 0 +#define RTE_I2S1_SCLK_PIN 7 +#define RTE_I2S1_SCLK_MUX 2 +#elif(RTE_I2S1_SCLK_PORT_ID ==2) +#define RTE_I2S1_SCLK_PORT 0 +#define RTE_I2S1_SCLK_PIN 8 +#define RTE_I2S1_SCLK_MUX 2 +#else + #error "Invalid I2S1 RTE_I2S1_SCLK Pin Configuration!" +#endif + +// I2S1_WSCLK Pin <0=>P0_2 <1=>P0_4 <2=>P0_10 +#define RTE_I2S1_WSCLK_PORT_ID 0 +#if(RTE_I2S1_WSCLK_PORT_ID == 0) +#define RTE_I2S1_WSCLK_PORT 0 +#define RTE_I2S1_WSCLK_PIN 2 +#define RTE_I2S1_WSCLK_MUX 2 +#elif(RTE_I2S0_WSCLK_PORT_ID == 1) +#define RTE_I2S1_WSCLK_PORT 0 +#define RTE_I2S1_WSCLK_PIN 4 +#define RTE_I2S1_WSCLK_MUX 2 +#elif(RTE_I2S1_WSCLK_PORT_ID ==2) +#define RTE_I2S1_WSCLK_PORT 0 +#define RTE_I2S1_WSCLK_PIN 10 +#define RTE_I2S1_WSCLK_MUX 2 +#else + #error "Invalid I2S1 RTE_I2S1_WSCLK Pin Configuration!" +#endif + +// I2S1_DOUT0 Pin <0=>P0_1 <1=>P0_5 <2=>P0_11 +#define RTE_I2S1_DOUT0_PORT_ID 1 +#if(RTE_I2S1_DOUT0_PORT_ID ==0) +#define RTE_I2S1_DOUT0_PORT 0 +#define RTE_I2S1_DOUT0_PIN 1 +#define RTE_I2S1_DOUT0_MUX 2 +#elif(RTE_I2S1_DOUT0_PORT_ID ==1) +#define RTE_I2S1_DOUT0_PORT 0 +#define RTE_I2S1_DOUT0_PIN 5 +#define RTE_I2S1_DOUT0_MUX 2 +#elif(RTE_I2S1_DOUT0_PORT_ID ==2) +#define RTE_I2S1_DOUT0_PORT 0 +#define RTE_I2S1_DOUT0_PIN 11 +#define RTE_I2S1_DOUT0_MUX 2 +#else + #error "Invalid I2S1 RTE_I2S1_DOUT0 Pin Configuration!" +#endif + +// I2S1_DIN0 Pin <0=>P0_0 <1=>P0_6 <2=>P0_9 <3=>P0_13 +#define RTE_I2S1_DIN0_PORT_ID 1 +#if(RTE_I2S1_DIN0_PORT_ID ==0) +#define RTE_I2S1_DIN0_PORT 0 +#define RTE_I2S1_DIN0_PIN 0 +#define RTE_I2S1_DIN0_MUX 2 +#elif(RTE_I2S1_DIN0_PORT_ID ==1) +#define RTE_I2S1_DIN0_PORT 0 +#define RTE_I2S1_DIN0_PIN 6 +#define RTE_I2S1_DIN0_MUX 2 +#elif(RTE_I2S1_DIN0_PORT_ID ==2) +#define RTE_I2S1_DIN0_PORT 0 +#define RTE_I2S1_DIN0_PIN 9 +#define RTE_I2S1_DIN0_MUX 2 +#else + #error "Invalid I2S1 RTE_I2S1_DIN0 Pin Configuration!" +#endif + +// FIFO level can have value 1 to 7 +#define I2S1_TX_FIFO_LEVEL ( 2U ) +#define I2S1_RX_FIFO_LEVEL ( 2U ) + +// I2S1_TX_RES <0=>12 +// <1=>16 +// <2=>20 +// <3=>24 +#define RTE_I2S1_TX_RES 1 +#if (RTE_I2S1_TX_RES ==0) +#define I2S1_TX_RES RES_12_BIT +#elif(RTE_I2S1_TX_RES ==1) +#define I2S1_TX_RES RES_16_BIT +#elif(RTE_I2S1_TX_RES ==2) +#define I2S1_TX_RES RES_20_BIT +#elif(RTE_I2S1_TX_RES ==3) +#define I2S1_TX_RES RES_24_BIT +#else + #error "Invalid I2S1 TX channel resolution!" +#endif + +// I2S1_RX_RES <0=>12 +// <1=>16 +// <2=>20 +// <3=>24 +#define RTE_I2S1_RX_RES 1 +#if (RTE_I2S1_RX_RES ==0) +#define I2S1_RX_RES RES_12_BIT +#elif(RTE_I2S1_RX_RES ==1) +#define I2S1_RX_RES RES_16_BIT +#elif(RTE_I2S1_RX_RES ==2) +#define I2S1_RX_RES RES_20_BIT +#elif(RTE_I2S1_RX_RES ==3) +#define I2S1_RX_RES RES_24_BIT +#else + #error "Invalid I2S1 RX channel resolution!" +#endif + +#define RTE_I2S1_CHNL_UDMA_TX_EN 1 +#define RTE_I2S1_CHNL_UDMA_TX_CH 7 + +#define RTE_I2S1_CHNL_UDMA_RX_EN 1 +#define RTE_I2S1_CHNL_UDMA_RX_CH 6 + +#define RTE_I2S1_DMA_TX_LEN_PER_DES 1024 +#define RTE_I2S1_DMA_RX_LEN_PER_DES 1024 + +// I2S1 [Driver_I2S1] + +// I2C0 (Inter-integrated Circuit Interface 0) [Driver_I2C0] +// Configuration settings for Driver_I2C0 in component ::Drivers:I2C + +#define RTE_I2C0 1 +#define I2C0_IRQHandler IRQ042_Handler + +// I2C0_SCL Pin <0=>P0_7 <1=>P0_65 <2=>P0_66 <3=>P0_75 <4=>P0_32 + +#ifndef CHIP_917_6x6 +#define RTE_I2C0_SCL_PORT_ID 0 +#if((RTE_I2C0_SCL_PORT_ID == 4)) + #error "Invalid I2C0 RTE_I2C0_SCL_PIN Configuration!" +#endif +#endif + +#ifdef CHIP_917_6x6 +#define RTE_I2C0_SCL_PORT_ID 0 +#if((RTE_I2C0_SCL_PORT_ID == 1)||(RTE_I2C0_SCL_PORT_ID == 2)||(RTE_I2C0_SCL_PORT_ID == 3)) + #error "Invalid I2C0 RTE_I2C0_SCL_PIN Configuration!" +#endif +#endif +#if (RTE_I2C0_SCL_PORT_ID == 0) +#define RTE_I2C0_SCL_PORT 0 +#define RTE_I2C0_SCL_PIN 7 +#define RTE_I2C0_SCL_MUX 4 +#define RTE_I2C0_SCL_PAD 2 +#define RTE_I2C0_SCL_I2C_REN 7 +#elif(RTE_I2C0_SCL_PORT_ID == 1) +#define RTE_I2C0_SCL_PORT 0 +#define RTE_I2C0_SCL_PIN 65 +#define RTE_I2C0_SCL_MUX 4 +#define RTE_I2C0_SCL_PAD 23 +#define RTE_I2C0_SCL_I2C_REN 1 +#elif(RTE_I2C0_SCL_PORT_ID == 2) +#define RTE_I2C0_SCL_PORT 0 +#define RTE_I2C0_SCL_PIN 66 +#define RTE_I2C0_SCL_MUX 4 +#define RTE_I2C0_SCL_PAD 24 +#define RTE_I2C0_SCL_I2C_REN 2 +#elif(RTE_I2C0_SCL_PORT_ID == 3) +#define RTE_I2C0_SCL_PORT 0 +#define RTE_I2C0_SCL_PIN 75 +#define RTE_I2C0_SCL_MUX 4 +#define RTE_I2C0_SCL_PAD 33 +#define RTE_I2C0_SCL_I2C_REN 11 +#elif(RTE_I2C0_SCL_PORT_ID == 4) +#define RTE_I2C0_SCL_PORT 0 +#define RTE_I2C0_SCL_PIN 32 +#define RTE_I2C0_SCL_MUX 11 +#define RTE_I2C0_SCL_PAD 9 +#define RTE_I2C0_SCL_I2C_REN 32 +#else + #error "Invalid I2C0 RTE_I2C0_SCL Pin Configuration!" +#endif + +// I2C0_SCL Pin <0=>P0_6 <1=>P0_64 <2=>P0_67 <3=>P0_74 <4=>P0_31 +#ifndef CHIP_917_6x6 +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_I2C0_SDA_PORT_ID 3 +#else +#define RTE_I2C0_SDA_PORT_ID 0 +#endif +#if((RTE_I2C0_SDA_PORT_ID == 4)) + #error "Invalid I2C0 RTE_I2C0_SDA Configuration!" +#endif +#endif +#ifdef CHIP_917_6x6 +#define RTE_I2C0_SDA_PORT_ID 0 +#if((RTE_I2C0_SDA_PORT_ID == 1)||(RTE_I2C0_SDA_PORT_ID == 2)||(RTE_I2C0_SDA_PORT_ID == 3)) + #error "Invalid I2C0 RTE_I2C0_SDA Configuration!" +#endif +#endif +#if (RTE_I2C0_SDA_PORT_ID == 0) +#define RTE_I2C0_SDA_PORT 0 +#define RTE_I2C0_SDA_PIN 6 +#define RTE_I2C0_SDA_MUX 4 +#define RTE_I2C0_SDA_PAD 1 +#define RTE_I2C0_SDA_I2C_REN 6 +#elif(RTE_I2C0_SDA_PORT_ID == 1) +#define RTE_I2C0_SDA_PORT 0 +#define RTE_I2C0_SDA_PIN 64 +#define RTE_I2C0_SDA_MUX 4 +#define RTE_I2C0_SDA_PAD 22 +#define RTE_I2C0_SDA_I2C_REN 0 +#elif(RTE_I2C0_SDA_PORT_ID == 2) +#define RTE_I2C0_SDA_PORT 0 +#define RTE_I2C0_SDA_PIN 67 +#define RTE_I2C0_SDA_MUX 4 +#define RTE_I2C0_SDA_PAD 25 +#define RTE_I2C0_SDA_I2C_REN 3 +#elif(RTE_I2C0_SDA_PORT_ID == 3) +#define RTE_I2C0_SDA_PORT 0 +#define RTE_I2C0_SDA_PIN 74 +#define RTE_I2C0_SDA_MUX 4 +#define RTE_I2C0_SDA_PAD 32 +#define RTE_I2C0_SDA_I2C_REN 10 +#elif(RTE_I2C0_SDA_PORT_ID == 4) +#define RTE_I2C0_SDA_PORT 0 +#define RTE_I2C0_SDA_PIN 31 +#define RTE_I2C0_SDA_MUX 11 +#define RTE_I2C0_SDA_PAD 9 +#define RTE_I2C0_SDA_I2C_REN 31 +#else + #error "Invalid I2C0 RTE_I2C0_SDA Pin Configuration!" +#endif + +#define IC_SCL_STUCK_TIMEOUT 20 +#define IC_SDA_STUCK_TIMEOUT 20 + +#define I2C_DMA 0 +#if (I2C_DMA == 1) +#define DMA_TX_TL 1 +#define DMA_RX_TL 1 +#endif +// I2C0 [Driver_I2C0] + +// I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1] +// Configuration settings for Driver_I2C1 in component ::Drivers:I2C + +#define RTE_I2C1 1 +#define I2C1_IRQHandler IRQ061_Handler +// I2C1_SCL Pin <0=>P0_6 <1=>P0_29 <2=>P0_50 <3=>P0_54 <4=>P0_64 <4=>P0_66 <4=>P0_70 <7=>P0_33 +#ifndef CHIP_917_6x6 +#define RTE_I2C1_SCL_PORT_ID 2 +#if((RTE_I2C1_SCL_PORT_ID == 7)) + #error "Invalid I2C1_SCL pin Configuration!" +#endif +#endif +#ifdef CHIP_917_6x6 +#define RTE_I2C1_SCL_PORT_ID 7 +#if((RTE_I2C1_SCL_PORT_ID == 2)||(RTE_I2C1_SCL_PORT_ID == 3)||(RTE_I2C1_SCL_PORT_ID == 4)||(RTE_I2C1_SCL_PORT_ID == 5)) + #error "Invalid I2C1_SCL pin Configuration!" +#endif +#endif +#if (RTE_I2C1_SCL_PORT_ID == 0) +#define RTE_I2C1_SCL_PORT 0 +#define RTE_I2C1_SCL_PIN 6 +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 1 +#define RTE_I2C1_SCL_REN 6 +#elif(RTE_I2C1_SCL_PORT_ID == 1) +#define RTE_I2C1_SCL_PORT 0 +#define RTE_I2C1_SCL_PIN 29 +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 0//no pad +#define RTE_I2C1_SCL_REN 29 +#elif(RTE_I2C1_SCL_PORT_ID == 2) +#define RTE_I2C1_SCL_PORT 0 +#define RTE_I2C1_SCL_PIN 50 +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 14 +#define RTE_I2C1_SCL_REN 50 +#elif(RTE_I2C1_SCL_PORT_ID == 3) +#define RTE_I2C1_SCL_PORT 0 +#define RTE_I2C1_SCL_PIN 54 +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 18 +#define RTE_I2C1_SCL_REN 54 +#elif(RTE_I2C1_SCL_PORT_ID == 4) +#define RTE_I2C1_SCL_PORT 0 +#define RTE_I2C1_SCL_PIN 64 +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 22 +#define RTE_I2C1_SCL_REN 0 +#elif(RTE_I2C1_SCL_PORT_ID == 5) +#define RTE_I2C1_SCL_PORT 0 +#define RTE_I2C1_SCL_PIN 66 +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 24 +#define RTE_I2C1_SCL_REN 2 +#elif(RTE_I2C1_SCL_PORT_ID == 6) +#define RTE_I2C1_SCL_PORT 0 +#define RTE_I2C1_SCL_PIN 70 +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 29 +#define RTE_I2C1_SCL_REN 6 +#elif(RTE_I2C1_SCL_PORT_ID == 7) +#define RTE_I2C1_SCL_PORT 0 +#define RTE_I2C1_SCL_PIN 33 +#define RTE_I2C1_SCL_MUX 11 +#define RTE_I2C1_SCL_PAD 9 +#define RTE_I2C1_SCL_REN 33 +/**/ +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1_SCL Pin <0=>P0_7 <1=>P0_30 <2=>P0_51 <3=>P0_55 <4=>P0_65 <4=>P0_67 <4=>P0_71 <7=>P0_34 +#ifdef CHIP_917_6x6 +#define RTE_I2C1_SDA_PORT_ID 7 +#if((RTE_I2C1_SDA_PORT_ID == 2)||(RTE_I2C1_SDA_PORT_ID == 3)||(RTE_I2C1_SDA_PORT_ID == 4)||(RTE_I2C1_SDA_PORT_ID == 5)) + #error "Invalid I2C1_SDA pin Configuration!" +#endif +#endif + +#ifndef CHIP_917_6x6 +#define RTE_I2C1_SDA_PORT_ID 2 +#if((RTE_I2C1_SDA_PORT_ID == 7)) + #error "Invalid I2C1_SDA pin Configuration!" +#endif +#endif +#if (RTE_I2C1_SDA_PORT_ID == 0) +#define RTE_I2C1_SDA_PORT 0 +#define RTE_I2C1_SDA_PIN 7 +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 2 +#define RTE_I2C1_SDA_REN 7 +#elif(RTE_I2C1_SDA_PORT_ID == 1) +#define RTE_I2C1_SDA_PORT 0 +#define RTE_I2C1_SDA_PIN 30 +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 0//no pad +#define RTE_I2C1_SDA_REN 30 +#elif(RTE_I2C1_SDA_PORT_ID == 2) +#define RTE_I2C1_SDA_PORT 0 +#define RTE_I2C1_SDA_PIN 51 +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 15 +#define RTE_I2C1_SDA_REN 51 +#elif(RTE_I2C1_SDA_PORT_ID == 3) +#define RTE_I2C1_SDA_PORT 0 +#define RTE_I2C1_SDA_PIN 55 +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 19 +#define RTE_I2C1_SDA_REN 55 +#elif(RTE_I2C1_SDA_PORT_ID == 4) +#define RTE_I2C1_SDA_PORT 0 +#define RTE_I2C1_SDA_PIN 65 +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 23 +#define RTE_I2C1_SDA_REN 1 +#elif(RTE_I2C1_SDA_PORT_ID == 5) +#define RTE_I2C1_SDA_PORT 0 +#define RTE_I2C1_SDA_PIN 67 +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 25 +#define RTE_I2C1_SDA_REN 3 +#elif(RTE_I2C1_SDA_PORT_ID == 6) +#define RTE_I2C1_SDA_PORT 0 +#define RTE_I2C1_SDA_PIN 71 +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 29 +#define RTE_I2C1_SDA_REN 7 +#elif(RTE_I2C1_SDA_PORT_ID == 7) +#define RTE_I2C1_SDA_PORT 0 +#define RTE_I2C1_SDA_PIN 34 +#define RTE_I2C1_SDA_MUX 11 +#define RTE_I2C1_SDA_PAD 9 +#define RTE_I2C1_SDA_REN 34 +#else +#error "Invalid I2C1_SDA Pin Configuration!" +#endif + + +#define IC_SCL_STUCK_TIMEOUT 20 +#define IC_SDA_STUCK_TIMEOUT 20 + +#define DMA_EN 0 +#if (DMA_EN == 1) +#define DMA_TX_TL 1 +#define DMA_RX_TL 1 +#endif + +// I2C1 [Driver_I2C1] + +// I2C2 (Inter-integrated Circuit Interface 2) [Driver_I2C2] +// Configuration settings for Driver_I2C2 in component ::Drivers:I2C +#define RTE_I2C2 1 +#define I2C2_IRQHandler IRQ013_Handler + +// I2C2_SCL Pin <0=>P0_1 <1=>P0_5 <2=>P0_7 <3=>P0_8 <4=>P0_13 +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_I2C2_SCL_PORT_ID 1 +#else +#define RTE_I2C2_SCL_PORT_ID 0 +#endif +#if (RTE_I2C2_SCL_PORT_ID == 0) +#define RTE_I2C2_SCL_PORT 0 +#define RTE_I2C2_SCL_PIN 1 +#define RTE_I2C2_SCL_MUX 4 +#define RTE_I2C2_SCL_REN 1 +#elif(RTE_I2C2_SCL_PORT_ID == 1) +#define RTE_I2C2_SCL_PORT 0 +#define RTE_I2C2_SCL_PIN 5 +#define RTE_I2C2_SCL_MUX 4 +#define RTE_I2C2_SCL_REN 5 +#elif(RTE_I2C2_SCL_PORT_ID == 2) +#define RTE_I2C2_SCL_PORT 0 +#define RTE_I2C2_SCL_PIN 7 +#define RTE_I2C2_SCL_MUX 4 +#define RTE_I2C2_SCL_REN 7 +#elif(RTE_I2C2_SCL_PORT_ID == 3) +#define RTE_I2C2_SCL_PORT 0 +#define RTE_I2C2_SCL_PIN 8 +#define RTE_I2C2_SCL_MUX 4 +#define RTE_I2C2_SCL_REN 8 +#else +#error "Invalid I2C2_SCL Pin Configuration!" +#endif + +// I2C2_SDA Pin <0=>P0_0 <1=>P0_4 <2=>P0_6 <3=>P0_9 <4=>P0_11 <5=>P0_12 +#define RTE_I2C2_SDA_PORT_ID 1 +#if (RTE_I2C2_SDA_PORT_ID == 0) +#define RTE_I2C2_SDA_PORT 0 +#define RTE_I2C2_SDA_PIN 0 +#define RTE_I2C2_SDA_MUX 4 +#define RTE_I2C2_SDA_I2C_REN 0 +#elif(RTE_I2C2_SDA_PORT_ID == 1) +#define RTE_I2C2_SDA_PORT 0 +#define RTE_I2C2_SDA_PIN 4 +#define RTE_I2C2_SDA_MUX 4 +#define RTE_I2C2_SDA_REN 4 +#elif(RTE_I2C2_SDA_PORT_ID == 2) +#define RTE_I2C2_SDA_PORT 0 +#define RTE_I2C2_SDA_PIN 6 +#define RTE_I2C2_SDA_MUX 4 +#define RTE_I2C2_SDA_REN 6 +#elif(RTE_I2C2_SDA_PORT_ID == 3) +#define RTE_I2C2_SDA_PORT 0 +#define RTE_I2C2_SDA_PIN 9 +#define RTE_I2C2_SDA_MUX 4 +#define RTE_I2C2_SDA_I2C_REN 9 +#elif(RTE_I2C2_SDA_PORT_ID == 4) +#define RTE_I2C2_SDA_PORT 0 +#define RTE_I2C2_SDA_PIN 11 +#define RTE_I2C2_SDA_MUX 4 +#define RTE_I2C2_SDA_REN 11 +#else +#error "Invalid I2C2_SDA Pin Configuration!" +#endif + +#define IC_SCL_STUCK_TIMEOUT 20 +#define IC_SDA_STUCK_TIMEOUT 20 + +#define DMA_EN 0 +#if (DMA_EN == 1) +#define DMA_TX_TL 1 +#define DMA_RX_TL 1 +#endif + +// I2C2 [Driver_I2C2] + +// GSPI (Generic SPI master) [Driver_GSPI_MASTER] +// Configuration settings for Driver_GSPI_MASTER in component ::Drivers:GSPI +#define RTE_GSPI_MASTER 1 + +// GSPI_MASTER_CLK <0=>P0_8 <1=>P0_25 <2=>P0_46 <3=>P0_52 +// CLK of GSPI0 +#ifndef CHIP_917_6x6 +#define RTE_GSPI_MASTER_CLK_PORT_ID 1 +#endif + +#ifdef CHIP_917_6x6 +#define RTE_GSPI_MASTER_CLK_PORT_ID 1 +#if((RTE_GSPI_MASTER_CLK_PORT_ID == 2)||(RTE_GSPI_MASTER_CLK_PORT_ID == 3)) + #error "Invalid GSPI0 RTE_GSPI_MASTER_CLK_PIN pin Configuration!" +#endif +#endif +#if(RTE_GSPI_MASTER_CLK_PORT_ID == 0) +#define RTE_GSPI_MASTER_CLK_PORT 0 +#define RTE_GSPI_MASTER_CLK_PIN 8 +#define RTE_GSPI_MASTER_CLK_MUX 4 +#define RTE_GSPI_MASTER_CLK_PAD 3 +#elif(RTE_GSPI_MASTER_CLK_PORT_ID ==1) +#define RTE_GSPI_MASTER_CLK_PORT 0 +#define RTE_GSPI_MASTER_CLK_PIN 25 +#define RTE_GSPI_MASTER_CLK_MUX 4 +#define RTE_GSPI_MASTER_CLK_PAD 0//NO PAD +#elif(RTE_GSPI_MASTER_CLK_PORT_ID ==2) +#define RTE_GSPI_MASTER_CLK_PORT 0 +#define RTE_GSPI_MASTER_CLK_PIN 46 +#define RTE_GSPI_MASTER_CLK_MUX 4 +#define RTE_GSPI_MASTER_CLK_PAD 10 +#elif(RTE_GSPI_MASTER_CLK_PORT_ID ==3) +#define RTE_GSPI_MASTER_CLK_PORT 0 +#define RTE_GSPI_MASTER_CLK_PIN 52 +#define RTE_GSPI_MASTER_CLK_MUX 4 +#define RTE_GSPI_MASTER_CLK_PAD 16 +#else + #error "Invalid GSPI0 RTE_GSPI_MASTER_CLK_PIN Pin Configuration!" +#endif + +// GSPI_MASTER_CS0 +// <0=>P0_9 <1=>P0_28 <2=>P0_49 <3=>P0_53 +// CS0 of GSPI0 +// +#ifndef CHIP_917_6x6 +#define RTE_GSPI_MASTER_CS0_PORT_ID 0 +#endif + +#ifdef CHIP_917_6x6 +#define RTE_GSPI_MASTER_CS0_PORT_ID 1 +#if((RTE_GSPI_MASTER_CS0_PORT_ID == 2)||(RTE_GSPI_MASTER_CS0_PORT_ID == 3)) + #error "Invalid GSPI0 RTE_GSPI_MASTER_CS0_PIN pin Configuration!" +#endif +#endif +#if(RTE_GSPI_MASTER_CS0_PORT_ID == 0) +#define RTE_GSPI_MASTER_CS0 1 +#define RTE_GSPI_MASTER_CS0_PORT 0 +#define RTE_GSPI_MASTER_CS0_PIN 9 +#define RTE_GSPI_MASTER_CS0_MUX 4 +#define RTE_GSPI_MASTER_CS0_PAD 4 +#elif(RTE_GSPI_MASTER_CS0_PORT_ID ==1) +#define RTE_GSPI_MASTER_CS0 1 +#define RTE_GSPI_MASTER_CS0_PORT 0 +#define RTE_GSPI_MASTER_CS0_PIN 28 +#define RTE_GSPI_MASTER_CS0_MUX 4 +#define RTE_GSPI_MASTER_CS0_PAD 0//NO PAD +#elif(RTE_GSPI_MASTER_CS0_PORT_ID ==2) +#define RTE_GSPI_MASTER_CS0 1 +#define RTE_GSPI_MASTER_CS0_PORT 0 +#define RTE_GSPI_MASTER_CS0_PIN 49 +#define RTE_GSPI_MASTER_CS0_MUX 4 +#define RTE_GSPI_MASTER_CS0_PAD 13 +#elif(RTE_GSPI_MASTER_CS0_PORT_ID ==3) +#define RTE_GSPI_MASTER_CS0 1 +#define RTE_GSPI_MASTER_CS0_PORT 0 +#define RTE_GSPI_MASTER_CS0_PIN 53 +#define RTE_GSPI_MASTER_CS0_MUX 4 +#define RTE_GSPI_MASTER_CS0_PAD 17 +#else + #error "Invalid GSPI0 RTE_GSPI_MASTER_CS0_PIN Pin Configuration!" +#endif + +#ifndef CHIP_917_6x6 +// GSPI_MASTER_CS1 +// <0=>P0_10 <1=>P0_29 <2=>P0_50 <3=>P0_54 +// CS1 of GSPI0 +// +#define RTE_GSPI_MASTER_CS1_PORT_ID 2 +#if(RTE_GSPI_MASTER_CS1_PORT_ID == 0) +#define RTE_GSPI_MASTER_CS1 1 +#define RTE_GSPI_MASTER_CS1_PORT 0 +#define RTE_GSPI_MASTER_CS1_PIN 10 +#define RTE_GSPI_MASTER_CS1_MUX 4 +#define RTE_GSPI_MASTER_CS1_PAD 5 +#elif(RTE_GSPI_MASTER_CS1_PORT_ID ==1) +#define RTE_GSPI_MASTER_CS1 1 +#define RTE_GSPI_MASTER_CS1_PORT 0 +#define RTE_GSPI_MASTER_CS1_PIN 29 +#define RTE_GSPI_MASTER_CS1_MUX 4 +#define RTE_GSPI_MASTER_CS1_PAD 0//NO PAD +#elif(RTE_GSPI_MASTER_CS1_PORT_ID ==2) +#define RTE_GSPI_MASTER_CS1 1 +#define RTE_GSPI_MASTER_CS1_PORT 0 +#define RTE_GSPI_MASTER_CS1_PIN 50 +#define RTE_GSPI_MASTER_CS1_MUX 4 +#define RTE_GSPI_MASTER_CS1_PAD 14 +#elif(RTE_GSPI_MASTER_CS1_PORT_ID ==3) +#define RTE_GSPI_MASTER_CS1 1 +#define RTE_GSPI_MASTER_CS1_PORT 0 +#define RTE_GSPI_MASTER_CS1_PIN 54 +#define RTE_GSPI_MASTER_CS1_MUX 4 +#define RTE_GSPI_MASTER_CS1_PAD 18 +#else + #error "Invalid GSPI0 RTE_GSPI_MASTER_CS1_PIN Pin Configuration!" +#endif + +// GSPI_MASTER_CS2 +// <0=>P0_15 <1=>P0_30 <2=>P0_51 <3=>P0_55 +// CS2 of GSPI0 +// +#define RTE_GSPI_MASTER_CS2_PORT_ID 1 +#if(RTE_GSPI_MASTER_CS2_PORT_ID == 0) +#define RTE_GSPI_MASTER_CS2 1 +#define RTE_GSPI_MASTER_CS2_PORT 0 +#define RTE_GSPI_MASTER_CS2_PIN 15 +#define RTE_GSPI_MASTER_CS2_MUX 4 +#define RTE_GSPI_MASTER_CS2_PAD 8 +#elif(RTE_GSPI_MASTER_CS2_PORT_ID ==1) +#define RTE_GSPI_MASTER_CS2 1 +#define RTE_GSPI_MASTER_CS2_PORT 0 +#define RTE_GSPI_MASTER_CS2_PIN 30 +#define RTE_GSPI_MASTER_CS2_MUX 4 +#define RTE_GSPI_MASTER_CS2_PAD 0//NO PAD +#elif(RTE_GSPI_MASTER_CS2_PORT_ID ==2) +#define RTE_GSPI_MASTER_CS2 1 +#define RTE_GSPI_MASTER_CS2_PORT 0 +#define RTE_GSPI_MASTER_CS2_PIN 51 +#define RTE_GSPI_MASTER_CS2_MUX 4 +#define RTE_GSPI_MASTER_CS2_PAD 15 +#elif(RTE_GSPI_MASTER_CS2_PORT_ID ==3) +#define RTE_GSPI_MASTER_CS2 1 +#define RTE_GSPI_MASTER_CS2_PORT 0 +#define RTE_GSPI_MASTER_CS2_PIN 55 +#define RTE_GSPI_MASTER_CS2_MUX 4 +#define RTE_GSPI_MASTER_CS2_PAD 19 +#else + #error "Invalid GSPI0 RTE_GSPI_MASTER_CS2_PIN Pin Configuration!" +#endif +#endif + +// GSPI_MASTER_MOSI <0=>P0_12 <1=>P0_27 <2=>P0_48 <3=>P0_57 <4=>P0_6 +// MOSI of GSPI0 +#ifndef CHIP_917_6x6 +#define RTE_GSPI_MASTER_MOSI_PORT_ID 1 +#if((RTE_GSPI_MASTER_MOSI_PORT_ID == 4)) + #error "Invalid GSPI0 RTE_GSPI_MASTER_MOSI_PIN pin Configuration!" +#endif +#endif + +#ifdef CHIP_917_6x6 +#define RTE_GSPI_MASTER_MOSI_PORT_ID 1 +#if((RTE_GSPI_MASTER_MOSI_PORT_ID == 0)||(RTE_GSPI_MASTER_MOSI_PORT_ID == 2)||(RTE_GSPI_MASTER_MOSI_PORT_ID == 3)) + #error "Invalid GSPI0 RTE_GSPI_MASTER_MOSI_PIN pin Configuration!" +#endif +#endif +#if(RTE_GSPI_MASTER_MOSI_PORT_ID == 0) +#define RTE_GSPI_MASTER_MOSI_PORT 0 +#define RTE_GSPI_MASTER_MOSI_PIN 12 +#define RTE_GSPI_MASTER_MOSI_MUX 4 +#define RTE_GSPI_MASTER_MOSI_PAD 7 +#elif(RTE_GSPI_MASTER_MOSI_PORT_ID ==1) +#define RTE_GSPI_MASTER_MOSI_PORT 0 +#define RTE_GSPI_MASTER_MOSI_PIN 27 +#define RTE_GSPI_MASTER_MOSI_MUX 4 +#define RTE_GSPI_MASTER_MOSI_PAD 0//NO PAD +#elif(RTE_GSPI_MASTER_MOSI_PORT_ID ==2) +#define RTE_GSPI_MASTER_MOSI_PORT 0 +#define RTE_GSPI_MASTER_MOSI_PIN 48 +#define RTE_GSPI_MASTER_MOSI_MUX 4 +#define RTE_GSPI_MASTER_MOSI_PAD 12 +#elif(RTE_GSPI_MASTER_MOSI_PORT_ID ==3) +#define RTE_GSPI_MASTER_MOSI_PORT 0 +#define RTE_GSPI_MASTER_MOSI_PIN 57 +#define RTE_GSPI_MASTER_MOSI_MUX 4 +#define RTE_GSPI_MASTER_MOSI_PAD 21 +#elif(RTE_GSPI_MASTER_MOSI_PORT_ID ==4) +#define RTE_GSPI_MASTER_MOSI_PORT 0 +#define RTE_GSPI_MASTER_MOSI_PIN 6 +#define RTE_GSPI_MASTER_MOSI_MUX 12 +#define RTE_GSPI_MASTER_MOSI_PAD 1 +#else + #error "Invalid GSPI0 RTE_GSPI_MASTER_MOSI_PIN Pin Configuration!" +#endif + +// GSPI_MASTER_MISO <0=>P0_11 <1=>P0_26 <2=>P0_47 <3=>P0_56 +// MISO of GSPI0 +#ifndef CHIP_917_6x6 +#define RTE_GSPI_MASTER_MISO_PORT_ID 1 +#endif +#ifdef CHIP_917_6x6 +#define RTE_GSPI_MASTER_MISO_PORT_ID 1 +#if((RTE_GSPI_MASTER_MISO_PORT_ID == 2)||(RTE_GSPI_MASTER_MISO_PORT_ID == 3)) + #error "Invalid GSPI0 RTE_GSPI_MASTER_MISO_PIN pin Configuration!" +#endif +#endif +#if(RTE_GSPI_MASTER_MISO_PORT_ID == 0) +#define RTE_GSPI_MASTER_MISO_PORT 0 +#define RTE_GSPI_MASTER_MISO_PIN 11 +#define RTE_GSPI_MASTER_MISO_MUX 4 +#define RTE_GSPI_MASTER_MISO_PAD 6 +#elif(RTE_GSPI_MASTER_MISO_PORT_ID ==1) +#define RTE_GSPI_MASTER_MISO_PORT 0 +#define RTE_GSPI_MASTER_MISO_PIN 26 +#define RTE_GSPI_MASTER_MISO_MUX 4 +#define RTE_GSPI_MASTER_MISO_PAD 0//NO PAD +#elif(RTE_GSPI_MASTER_MISO_PORT_ID ==2) +#define RTE_GSPI_MASTER_MISO_PORT 0 +#define RTE_GSPI_MASTER_MISO_PIN 47 +#define RTE_GSPI_MASTER_MISO_MUX 4 +#define RTE_GSPI_MASTER_MISO_PAD 11 +#elif(RTE_GSPI_MASTER_MISO_PORT_ID ==3) +#define RTE_GSPI_MASTER_MISO_PORT 0 +#define RTE_GSPI_MASTER_MISO_PIN 56 +#define RTE_GSPI_MASTER_MISO_MUX 4 +#define RTE_GSPI_MASTER_MISO_PAD 20 +#else + #error "Invalid GSPI0 RTE_GSPI_MASTER_MISO_PIN Pin Configuration!" +#endif + +#if defined(HIGH_THROUGHPUT_EN) && (HIGH_THROUGHPUT_EN == 1) +#define RTE_GSPI_MASTER_CHNL_UDMA_TX_EN 1 +#define RTE_GSPI_MASTER_CHNL_UDMA_TX_CH 11 + + +#define RTE_GSPI_MASTER_CHNL_UDMA_RX_EN 1 +#define RTE_GSPI_MASTER_CHNL_UDMA_RX_CH 10 + +#define RTE_FIFO_AFULL_THRLD 3 +#define RTE_FIFO_AEMPTY_THRLD 7 + +#define TX_DMA_ARB_SIZE ARBSIZE_4 +#define RX_DMA_ARB_SIZE ARBSIZE_8 +#else +#define RTE_GSPI_MASTER_CHNL_UDMA_TX_EN 0 +#define RTE_GSPI_MASTER_CHNL_UDMA_TX_CH 11 + +#define RTE_GSPI_MASTER_CHNL_UDMA_RX_EN 0 +#define RTE_GSPI_MASTER_CHNL_UDMA_RX_CH 10 + +#define RTE_FIFO_AFULL_THRLD 0 +#define RTE_FIFO_AEMPTY_THRLD 0 + +#define TX_DMA_ARB_SIZE ARBSIZE_1 +#define RX_DMA_ARB_SIZE ARBSIZE_1 +#endif + +// (Generic SPI master)[Driver_GSPI_MASTER] + + +// (State Configurable Timer) Interface +#define SCT_CLOCK_SOURCE M4_SOCCLKFOROTHERCLKSCT +#define SCT_CLOCK_DIV_FACT 1 + +//SCT_IN_0 <0=>GPIO_25 <1=>GPIO_64 <2=>GPIO_68 +#ifndef CHIP_917_6x6 +#define RTE_SCT_IN_0_PORT_ID 1 +#endif +#ifdef CHIP_917_6x6 +#define RTE_SCT_IN_0_PORT_ID 0 +#if((RTE_SCT_IN_0_PORT_ID == 1)) + #error "Invalid RTE_SCT_IN_0_PIN pin Configuration!" +#endif +#endif +#if(RTE_SCT_IN_0_PORT_ID == 0) +#define RTE_SCT_IN_0_PORT 0 +#define RTE_SCT_IN_0_PIN 25 +#define RTE_SCT_IN_0_MUX 9 +#define RTE_SCT_IN_0_PAD 0//no pad +#elif(RTE_SCT_IN_0_PORT_ID == 1) +#define RTE_SCT_IN_0_PORT 0 +#define RTE_SCT_IN_0_PIN 64 +#define RTE_SCT_IN_0_MUX 7 +#define RTE_SCT_IN_0_PAD 22 +#elif(RTE_SCT_IN_0_PORT_ID == 2) +#define RTE_SCT_IN_0_PORT 0 +#define RTE_SCT_IN_0_PIN 68 +#define RTE_SCT_IN_0_MUX 9 +#define RTE_SCT_IN_0_PAD 26 +#else + #error "Invalid RTE_SCT_IN_0_PIN Pin Configuration!" +#endif + +//SCT_IN_1 <0=>GPIO_26 <1=>GPIO_65 <2=>GPIO_69 +#ifndef CHIP_917_6x6 +#define RTE_SCT_IN_1_PORT_ID 1 +#endif +#ifdef CHIP_917_6x6 +#define RTE_SCT_IN_1_PORT_ID 0 +#if((RTE_SCT_IN_1_PORT_ID == 1)) + #error "Invalid RTE_SCT_IN_1_PIN pin Configuration!" +#endif +#endif +#if(RTE_SCT_IN_1_PORT_ID == 0) +#define RTE_SCT_IN_1_PORT 0 +#define RTE_SCT_IN_1_PIN 26 +#define RTE_SCT_IN_1_MUX 9 +#define RTE_SCT_IN_1_PAD 0//no pad +#elif(RTE_SCT_IN_1_PORT_ID == 1) +#define RTE_SCT_IN_1_PORT 0 +#define RTE_SCT_IN_1_PIN 65 +#define RTE_SCT_IN_1_MUX 7 +#define RTE_SCT_IN_1_PAD 23 +#elif(RTE_SCT_IN_1_PORT_ID == 2) +#define RTE_SCT_IN_1_PORT 0 +#define RTE_SCT_IN_1_PIN 69 +#define RTE_SCT_IN_1_MUX 9 +#define RTE_SCT_IN_1_PAD 27 +#else + #error "Invalid RTE_SCT_IN_1_PIN Pin Configuration!" +#endif + +//SCT_IN_2 <0=>GPIO_27 <1=>GPIO_66 <2=>GPIO_70 +#ifndef CHIP_917_6x6 +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_SCT_IN_2_PORT_ID 0 +#else +#define RTE_SCT_IN_2_PORT_ID 1 +#endif +#endif +#ifdef CHIP_917_6x6 +#define RTE_SCT_IN_2_PORT_ID 0 +#if((RTE_SCT_IN_2_PORT_ID == 1)) + #error "Invalid RTE_SCT_IN_2_PIN pin Configuration!" +#endif +#endif +#if(RTE_SCT_IN_2_PORT_ID == 0) +#define RTE_SCT_IN_2_PORT 0 +#define RTE_SCT_IN_2_PIN 27 +#define RTE_SCT_IN_2_MUX 9 +#define RTE_SCT_IN_2_PAD 0//no pad +#elif(RTE_SCT_IN_2_PORT_ID == 1) +#define RTE_SCT_IN_2_PORT 0 +#define RTE_SCT_IN_2_PIN 66 +#define RTE_SCT_IN_2_MUX 7 +#define RTE_SCT_IN_2_PAD 24 +#elif(RTE_SCT_IN_2_PORT_ID == 2) +#define RTE_SCT_IN_2_PORT 0 +#define RTE_SCT_IN_2_PIN 70 +#define RTE_SCT_IN_2_MUX 9 +#define RTE_SCT_IN_2_PAD 28 +#else + #error "Invalid RTE_SCT_IN_0_PIN Pin Configuration!" +#endif + +//SCT_IN_3 <0=>GPIO_28 <1=>GPIO_67 <2=>GPIO_71 +#ifndef CHIP_917_6x6 +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_SCT_IN_3_PORT_ID 0 +#else +#define RTE_SCT_IN_3_PORT_ID 1 +#endif +#endif +#ifdef CHIP_917_6x6 +#define RTE_SCT_IN_3_PORT_ID 0 +#if((RTE_SCT_IN_3_PORT_ID == 1)) + #error "Invalid RTE_SCT_IN_3_PIN pin Configuration!" +#endif +#endif +#if(RTE_SCT_IN_3_PORT_ID == 0) +#define RTE_SCT_IN_3_PORT 0 +#define RTE_SCT_IN_3_PIN 28 +#define RTE_SCT_IN_3_MUX 9 +#define RTE_SCT_IN_3_PAD 0//no pad +#elif(RTE_SCT_IN_3_PORT_ID == 1) +#define RTE_SCT_IN_3_PORT 0 +#define RTE_SCT_IN_3_PIN 67 +#define RTE_SCT_IN_3_MUX 7 +#define RTE_SCT_IN_3_PAD 25 +#elif(RTE_SCT_IN_3_PORT_ID == 2) +#define RTE_SCT_IN_3_PORT 0 +#define RTE_SCT_IN_3_PIN 71 +#define RTE_SCT_IN_3_MUX 9 +#define RTE_SCT_IN_3_PAD 29 +#else + #error "Invalid RTE_SCT_IN_0_PIN Pin Configuration!" +#endif + +// SCT_OUT_0 <0=>GPIO_29 <1=>GPIO_68 +#define RTE_SCT_OUT_0_PORT_ID 0 +#if(RTE_SCT_OUT_0_PORT_ID == 0) +#define RTE_SCT_OUT_0_PORT 0 +#define RTE_SCT_OUT_0_PIN 29 +#define RTE_SCT_OUT_0_MUX 9 +#define RTE_SCT_OUT_0_PAD 0//no pad +#elif(RTE_SCT_OUT_0_PORT_ID ==1) +#define RTE_SCT_OUT_0_PORT 0 +#define RTE_SCT_OUT_0_PIN 68 +#define RTE_SCT_OUT_0_MUX 7 +#define RTE_SCT_OUT_0_PAD 26 +#else + #error "Invalid RTE_SCT_OUT_0_PIN Pin Configuration!" +#endif + +// SCT_OUT_1 <0=>GPIO_30 <1=>GPIO_69 +#define RTE_SCT_OUT_1_PORT_ID 0 +#if(RTE_SCT_OUT_1_PORT_ID == 0) +#define RTE_SCT_OUT_1_PORT 0 +#define RTE_SCT_OUT_1_PIN 30 +#define RTE_SCT_OUT_1_MUX 9 +#define RTE_SCT_OUT_1_PAD 0//no pad +#elif(RTE_SCT_OUT_1_PORT_ID == 1) +#define RTE_SCT_OUT_1_PORT 0 +#define RTE_SCT_OUT_1_PIN 69 +#define RTE_SCT_OUT_1_MUX 7 +#define RTE_SCT_OUT_1_PAD 27 +#else + #error "Invalid RTE_SCT_OUT_1_PIN Pin Configuration!" +#endif + +/// SCT_OUT_2 <0=>GPIO_70 <1=>GPIO_8 +#define RTE_SCT_OUT_2_PORT_ID 0 +#ifndef CHIP_917_6x6 +#if((RTE_SCT_OUT_2_PORT_ID == 1)) + #error "Invalid RTE_SCT_OUT_2_PIN pin Configuration!" +#endif +#endif +#if(RTE_SCT_OUT_2_PORT_ID == 0) +#define RTE_SCT_OUT_2_PORT 0 +#define RTE_SCT_OUT_2_PIN 70 +#define RTE_SCT_OUT_2_MUX 7 +#define RTE_SCT_OUT_2_PAD 28 +#elif(RTE_SCT_OUT_2_PORT_ID == 1) +#define RTE_SCT_OUT_2_PORT 0 +#define RTE_SCT_OUT_2_PIN 8 +#define RTE_SCT_OUT_2_MUX 12 +#define RTE_SCT_OUT_2_PAD 3 +#else + #error "Invalid RTE_SCT_OUT_2_PIN Pin Configuration!" +#endif +/**/ +//SCT_OUT_3 <0=>GPIO_71 <1=>GPIO_9 +#define RTE_SCT_OUT_3_PORT_ID 0 +#ifndef CHIP_917_6x6 +#if((RTE_SCT_OUT_3_PORT_ID == 1)) + #error "Invalid RTE_SCT_OUT_3_PIN pin Configuration!" +#endif +#endif +#if(RTE_SCT_OUT_3_PORT_ID == 0) +#define RTE_SCT_OUT_3_PORT 0 +#define RTE_SCT_OUT_3_PIN 71 +#define RTE_SCT_OUT_3_MUX 7 +#define RTE_SCT_OUT_3_PAD 29 +#elif(RTE_SCT_OUT_3_PORT_ID == 1) +#define RTE_SCT_OUT_3_PORT 0 +#define RTE_SCT_OUT_3_PIN 9 +#define RTE_SCT_OUT_3_MUX 12 +#define RTE_SCT_OUT_3_PAD 4 +#else + #error "Invalid RTE_SCT_OUT_3_PIN Pin Configuration!" +#endif + +//SCT_OUT_4 <0=>GPIO_72 <1=>GPIO_68 + +#ifndef CHIP_917_6x6 +#define RTE_SCT_OUT_4_PORT_ID 0 +#if((RTE_SCT_OUT_4_PORT_ID == 1)) + #error "Invalid RTE_SCT_OUT_4_PIN pin Configuration!" +#endif +#endif +#ifdef CHIP_917_6x6 +#define RTE_SCT_OUT_4_PORT_ID 1 +#if((RTE_SCT_OUT_4_PORT_ID == 0)) + #error "Invalid RTE_SCT_OUT_4_PIN pin Configuration!" +#endif +#endif +#if(RTE_SCT_OUT_4_PORT_ID == 0) +/**/ +#define RTE_SCT_OUT_4_PORT 0 +#define RTE_SCT_OUT_4_PIN 72 +#define RTE_SCT_OUT_4_MUX 7 +#define RTE_SCT_OUT_4_PAD 30 +#elif(RTE_SCT_OUT_4_PORT_ID == 1) +#define RTE_SCT_OUT_4_PORT 0 +#define RTE_SCT_OUT_4_PIN 68 +#define RTE_SCT_OUT_4_MUX 13 +#define RTE_SCT_OUT_4_PAD 26 +#else + #error "Invalid RTE_SCT_OUT_4_PIN Pin Configuration!" +#endif +//SCT_OUT_5 <0=>GPIO_73 <1=>GPIO_69 +#ifndef CHIP_917_6x6 +#define RTE_SCT_OUT_5_PORT_ID 0 +#if((RTE_SCT_OUT_5_PORT_ID == 1)) + #error "Invalid RTE_SCT_OUT_5_PIN pin Configuration!" +#endif +#endif +#ifdef CHIP_917_6x6 +#define RTE_SCT_OUT_5_PORT_ID 1 +#if((RTE_SCT_OUT_5_PORT_ID == 0)) + #error "Invalid RTE_SCT_OUT_5_PIN pin Configuration!" +#endif +#endif +#if(RTE_SCT_OUT_5_PORT_ID == 0) +#define RTE_SCT_OUT_5_PORT 2 +#define RTE_SCT_OUT_5_PIN 73 +#define RTE_SCT_OUT_5_MUX 7 +#define RTE_SCT_OUT_5_PAD 31 +#elif(RTE_SCT_OUT_5_PORT_ID == 1) +#define RTE_SCT_OUT_5_PORT 0 +#define RTE_SCT_OUT_5_PIN 69 +#define RTE_SCT_OUT_5_MUX 13 +#define RTE_SCT_OUT_5_PAD 27 +#else + #error "Invalid RTE_SCT_OUT_5_PIN Pin Configuration!" +#endif + +//SCT_OUT_6 <0=>GPIO_74 <1=>GPIO_70 +#ifndef CHIP_917_6x6 +#define RTE_SCT_OUT_6_PORT_ID 0 +#if((RTE_SCT_OUT_6_PORT_ID == 1)) + #error "Invalid RTE_SCT_OUT_6_PIN pin Configuration!" +#endif +#endif +#ifdef CHIP_917_6x6 +#define RTE_SCT_OUT_6_PORT_ID 1 +#if((RTE_SCT_OUT_6_PORT_ID == 0)) + #error "Invalid RTE_SCT_OUT_6_PIN pin Configuration!" +#endif +#endif +#if(RTE_SCT_OUT_6_PORT_ID == 0) +#define RTE_SCT_OUT_6_PORT 0 +#define RTE_SCT_OUT_6_PIN 74 +#define RTE_SCT_OUT_6_MUX 7 +#define RTE_SCT_OUT_6_PAD 32 +#elif(RTE_SCT_OUT_6_PORT_ID == 1) +#define RTE_SCT_OUT_6_PORT 0 +#define RTE_SCT_OUT_6_PIN 70 +#define RTE_SCT_OUT_6_MUX 13 +#define RTE_SCT_OUT_6_PAD 28 +#else + #error "Invalid RTE_SCT_OUT_6_PIN Pin Configuration!" +#endif + +// SCT_OUT_7 <0=>GPIO_75 <1=>GPIO_71 + +#ifndef CHIP_917_6x6 +#define RTE_SCT_OUT_7_PORT_ID 0 +#if((RTE_SCT_OUT_7_PORT_ID == 1)) + #error "Invalid RTE_SCT_OUT_7_PIN pin Configuration!" +#endif +#endif +#ifdef CHIP_917_6x6 +#define RTE_SCT_OUT_7_PORT_ID 1 +#if((RTE_SCT_OUT_7_PORT_ID == 0)) + #error "Invalid RTE_SCT_OUT_7_PIN pin Configuration!" +#endif +#endif +#if(RTE_SCT_OUT_7_PORT_ID == 0) +#define RTE_SCT_OUT_7_PORT 0 +#define RTE_SCT_OUT_7_PIN 75 +#define RTE_SCT_OUT_7_MUX 7 +#define RTE_SCT_OUT_7_PAD 33 +#elif(RTE_SCT_OUT_7_PORT_ID == 1) +#define RTE_SCT_OUT_7_PORT 0 +#define RTE_SCT_OUT_7_PIN 71 +#define RTE_SCT_OUT_7_MUX 13 +#define RTE_SCT_OUT_7_PAD 29 +#else + #error "Invalid RTE_SCT_OUT_7_PIN Pin Configuration!" +#endif + +// SIO // +//<> Serial Input Output +//SIO_0 <0=>GPIO_6 <1=>GPIO_25 <2=>GPIO_64 <3=>GPIO_72 +#ifndef CHIP_917_6x6 +#define RTE_SIO_0_PORT_ID 0 +#endif +#ifdef CHIP_917_6x6 +#define RTE_SIO_0_PORT_ID 0 +#if((RTE_SIO_0_PORT_ID == 2)||(RTE_SIO_0_PORT_ID == 3)) + #error "Invalid RTE_SIO_0_PIN pin Configuration!" +#endif +#endif +#if(RTE_SIO_0_PORT_ID == 0) +#define RTE_SIO_0_PORT 0 +#define RTE_SIO_0_PIN 6 +#define RTE_SIO_0_MUX 1 +#define RTE_SIO_0_PAD 1 +#elif(RTE_SIO_0_PORT_ID == 1) +#define RTE_SIO_0_PORT 0 +#define RTE_SIO_0_PIN 25 +#define RTE_SIO_0_MUX 1 +#define RTE_SIO_0_PAD 0//no pad +#elif(RTE_SIO_0_PORT_ID == 2) +#define RTE_SIO_0_PORT 0 +#define RTE_SIO_0_PIN 64 +#define RTE_SIO_0_MUX 1 +#define RTE_SIO_0_PAD 22 +#elif(RTE_SIO_0_PORT_ID == 3) +#define RTE_SIO_0_PORT 0 +#define RTE_SIO_0_PIN 72 +#define RTE_SIO_0_MUX 1 +#define RTE_SIO_0_PAD 30 +#else + #error "Invalid RTE_SIO_0_PIN Pin Configuration!" +#endif + +//SIO_1 <0=>GPIO_7 <1=>GPIO_26 <2=>GPIO_65 <3=>GPIO_73 +#ifndef CHIP_917_6x6 +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_SIO_1_PORT_ID 1 +#else +#define RTE_SIO_1_PORT_ID 0 +#endif +#endif +#ifdef CHIP_917_6x6 +#define RTE_SIO_1_PORT_ID 1 +#if((RTE_SIO_1_PORT_ID == 2)||(RTE_SIO_1_PORT_ID == 3)) + #error "Invalid RTE_SIO_1_PIN Configuration!" +#endif +#endif +#if(RTE_SIO_1_PORT_ID == 0) +#define RTE_SIO_1_PORT 0 +#define RTE_SIO_1_PIN 7 +#define RTE_SIO_1_MUX 1 +#define RTE_SIO_1_PAD 2 +#elif(RTE_SIO_1_PORT_ID == 1) +#define RTE_SIO_1_PORT 0 +#define RTE_SIO_1_PIN 26 +#define RTE_SIO_1_MUX 1 +#define RTE_SIO_1_PAD 0// no pad +#elif(RTE_SIO_1_PORT_ID == 2) +#define RTE_SIO_1_PORT 0 +#define RTE_SIO_1_PIN 65 +#define RTE_SIO_1_MUX 1 +#define RTE_SIO_1_PAD 23 +#elif(RTE_SIO_1_PORT_ID == 3) +#define RTE_SIO_1_PORT 0 +#define RTE_SIO_1_PIN 73 +#define RTE_SIO_1_MUX 1 +#define RTE_SIO_1_PAD 31 +#else + #error "Invalid RTE_SIO_1_PIN Pin Configuration!" +#endif + + +// SIO_2 <0=>GPIO_8 <1=>GPIO_27 <2=>GPIO_66 <3=>GPIO_74 +#ifndef CHIP_917_6x6 +#define RTE_SIO_2_PORT_ID 1 +#endif +#ifdef CHIP_917_6x6 +#define RTE_SIO_2_PORT_ID 0 +#if((RTE_SIO_2_PORT_ID == 2)||(RTE_SIO_2_PORT_ID == 3)) + #error "Invalid RTE_SIO_2_PIN Configuration!" +#endif +#endif +#if(RTE_SIO_2_PORT_ID == 0) +#define RTE_SIO_2_PORT 0 +#define RTE_SIO_2_PIN 8 +#define RTE_SIO_2_MUX 1 +#define RTE_SIO_2_PAD 3 +#elif(RTE_SIO_2_PORT_ID == 1) +#define RTE_SIO_2_PORT 0 +#define RTE_SIO_2_PIN 27 +#define RTE_SIO_2_MUX 1 +#define RTE_SIO_2_PAD 0//no pad +#elif(RTE_SIO_2_PORT_ID == 2) +#define RTE_SIO_2_PORT 0 +#define RTE_SIO_2_PIN 66 +#define RTE_SIO_2_MUX 1 +#define RTE_SIO_2_PAD 24 +#elif(RTE_SIO_2_PORT_ID == 3) +#define RTE_SIO_2_PORT 0 +#define RTE_SIO_2_PIN 74 +#define RTE_SIO_2_MUX 1 +#define RTE_SIO_2_PAD 32 +#else + #error "Invalid RTE_SIO_2_PIN Pin Configuration!" +#endif + + + +//SIO_3 <0=>GPIO_9 <1=>GPIO_28 <2=>GPIO_67 <3=>GPIO_75 +#ifndef CHIP_917_6x6 +#define RTE_SIO_3_PORT_ID 1 +#endif +#ifdef CHIP_917_6x6 +#define RTE_SIO_3_PORT_ID 0 +#if((RTE_SIO_3_PORT_ID == 2)||(RTE_SIO_3_PORT_ID == 3)) + #error "Invalid RTE_SIO_3_PIN Configuration!" +#endif +#endif +#if(RTE_SIO_3_PORT_ID == 0) +#define RTE_SIO_3_PORT 0 +#define RTE_SIO_3_PIN 9 +#define RTE_SIO_3_MUX 1 +#define RTE_SIO_3_PAD 4 +#elif(RTE_SIO_3_PORT_ID == 1) +#define RTE_SIO_3_PORT 0 +#define RTE_SIO_3_PIN 28 +#define RTE_SIO_3_MUX 1 +#define RTE_SIO_3_PAD 0//no pad +#elif(RTE_SIO_3_PORT_ID == 2) +#define RTE_SIO_3_PORT 0 +#define RTE_SIO_3_PIN 67 +#define RTE_SIO_3_MUX 1 +#define RTE_SIO_3_PAD 25 +#elif(RTE_SIO_3_PORT_ID == 3) +#define RTE_SIO_3_PORT 0 +#define RTE_SIO_3_PIN 75 +#define RTE_SIO_3_MUX 1 +#define RTE_SIO_3_PAD 33 +#else + #error "Invalid RTE_SIO_3_PIN Pin Configuration!" +#endif + + +//SIO_4 <0=>GPIO_10 <1=>GPIO_29 <2=>GPIO_68 +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_SIO_4_PORT_ID 1 +#else +#define RTE_SIO_4_PORT_ID 0 +#endif +#if(RTE_SIO_4_PORT_ID == 0) +#define RTE_SIO_4_PORT 0 +#define RTE_SIO_4_PIN 10 +#define RTE_SIO_4_MUX 1 +#define RTE_SIO_4_PAD 5 +#elif(RTE_SIO_4_PORT_ID == 1) +#define RTE_SIO_4_PORT 0 +#define RTE_SIO_4_PIN 29 +#define RTE_SIO_4_MUX 1 +#define RTE_SIO_4_PAD 0//NO PAD +#elif(RTE_SIO_4_PORT_ID == 2) +#define RTE_SIO_4_PORT 0 +#define RTE_SIO_4_PIN 68 +#define RTE_SIO_4_MUX 1 +#define RTE_SIO_4_PAD 26 +#else + #error "Invalid RTE_SIO_3_PIN Pin Configuration!" +#endif + +// SIO_5 <0=>GPIO_11 <1=>GPIO_30 <2=>GPIO_69 +#define RTE_SIO_5_PORT_ID 0 +#if(RTE_SIO_5_PORT_ID == 0) +#define RTE_SIO_5_PORT 0 +#define RTE_SIO_5_PIN 11 +#define RTE_SIO_5_MUX 1 +#define RTE_SIO_5_PAD 6 +#elif(RTE_SIO_5_PORT_ID == 1) +#define RTE_SIO_5_PORT 0 +#define RTE_SIO_5_PIN 30 +#define RTE_SIO_5_MUX 1 +#define RTE_SIO_5_PAD 0//no pad +#elif(RTE_SIO_5_PORT_ID == 2) +#define RTE_SIO_5_PORT 0 +#define RTE_SIO_5_PIN 69 +#define RTE_SIO_5_MUX 1 +#define RTE_SIO_5_PAD 27 +#else + #error "Invalid RTE_SIO_5_PIN Pin Configuration!" +#endif + +// SIO_6 GPIO_70 +#define RTE_SIO_6_PORT 0 +#define RTE_SIO_6_PIN 70 +#define RTE_SIO_6_MUX 1 +#define RTE_SIO_6_PAD 28 + +// SIO_7 <0=>GPIO_15 <1=>GPIO_71 +#ifndef CHIP_917_6x6 +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_SIO_7_PORT_ID 1 +#else +#define RTE_SIO_7_PORT_ID 0 +#endif +#endif +#ifdef CHIP_917_6x6 +#define RTE_SIO_7_PORT_ID 1 +#if((RTE_SIO_7_PORT_ID == 0)) + #error "Invalid RTE_SIO_7_PIN Configuration!" +#endif +#endif +#if(RTE_SIO_7_PORT_ID == 0) +#define RTE_SIO_7_PORT 0 +#define RTE_SIO_7_PIN 15 +#define RTE_SIO_7_MUX 1 +#define RTE_SIO_7_PAD 8 +#elif(RTE_SIO_7_PORT_ID == 1) +#define RTE_SIO_7_PORT 0 +#define RTE_SIO_7_PIN 71 +#define RTE_SIO_7_MUX 1 +#define RTE_SIO_7_PAD 29 +#else + #error "Invalid RTE_SIO_7_PIN Pin Configuration!" +#endif + + +//<> Pulse Width Modulation +//PWM_1H <0=>GPIO_7 <1=>GPIO_64 <2=>GPIO_65 +#ifndef CHIP_917_6x6 +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_PWM_1H_PORT_ID 0 +#else +#define RTE_PWM_1H_PORT_ID 1 +#endif +#endif +#ifdef CHIP_917_6x6 +#define RTE_PWM_1H_PORT_ID 0 +#if((RTE_PWM_1H_PORT_ID == 1)) + #error "Invalid RTE_PWM_1H_PIN Configuration!" +#endif +#endif +#if(RTE_PWM_1H_PORT_ID == 0) +#define RTE_PWM_1H_PORT 0 +#define RTE_PWM_1H_PIN 7 +#define RTE_PWM_1H_MUX 10 +#define RTE_PWM_1H_PAD 2 +#elif(RTE_PWM_1H_PORT_ID == 1) +#define RTE_PWM_1H_PORT 0 +#define RTE_PWM_1H_PIN 65 +#define RTE_PWM_1H_MUX 8 +#define RTE_PWM_1H_PAD 22 +#else + #error "Invalid RTE_PWM_1H_PIN Pin Configuration!" +#endif + + +// PWM_1L <0=>GPIO_6 <1=>GPIO_64 <2=>GPIO_64 +#ifndef CHIP_917_6x6 +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_PWM_1L_PORT_ID 1 +#else +#define RTE_PWM_1L_PORT_ID 0 +#endif +#endif +#ifdef CHIP_917_6x6 +#define RTE_PWM_1L_PORT_ID 0 +#if((RTE_PWM_1L_PORT_ID == 1)) + #error "Invalid RTE_PWM_1L_PIN Configuration!" +#endif +#endif +#if(RTE_PWM_1L_PORT_ID == 0) +#define RTE_PWM_1L_PORT 0 +#define RTE_PWM_1L_PIN 6 +#define RTE_PWM_1L_MUX 10 +#define RTE_PWM_1L_PAD 1 +#elif(RTE_PWM_1L_PORT_ID == 1) +#define RTE_PWM_1L_PORT 0 +#define RTE_PWM_1L_PIN 64 +#define RTE_PWM_1L_MUX 8 +#define RTE_PWM_1L_PAD 22 +#else + #error "Invalid RTE_PWM_1L_PIN Pin Configuration!" +#endif + +//PWM_2H <0=>GPIO_9 <1=>GPIO_67 <2=>GPIO_69 +#ifndef CHIP_917_6x6 +#define RTE_PWM_2H_PORT_ID 0 +#if((RTE_PWM_2H_PORT_ID == 2)) + #error "Invalid RTE_PWM_2H_PIN pin Configuration!" +#endif +#endif +#ifdef CHIP_917_6x6 +#define RTE_PWM_2H_PORT_ID 0 +#if((RTE_PWM_2H_PORT_ID == 1)) + #error "Invalid RTE_PWM_2H_PIN pin Configuration!" +#endif +#endif +#if(RTE_PWM_2H_PORT_ID == 0) +#define RTE_PWM_2H_PORT 0 +#define RTE_PWM_2H_PIN 9 +#define RTE_PWM_2H_MUX 10 +#define RTE_PWM_2H_PAD 4 +#elif(RTE_PWM_2H_PORT_ID == 1) +#define RTE_PWM_2H_PORT 0 +#define RTE_PWM_2H_PIN 67 +#define RTE_PWM_2H_MUX 8 +#define RTE_PWM_2H_PAD 25 +#elif(RTE_PWM_2H_PORT_ID == 2) +#define RTE_PWM_2H_PORT 0 +#define RTE_PWM_2H_PIN 69 +#define RTE_PWM_2H_MUX 12 +#define RTE_PWM_2H_PAD 27 +#else + #error "Invalid RTE_PWM_2H_PIN Pin Configuration!" +#endif + + +// PWM_2L <0=>GPIO_8 <1=>GPIO_66 <2=>GPIO_68 +#ifndef CHIP_917_6x6 +#define RTE_PWM_2L_PORT_ID 0 +#if((RTE_PWM_2L_PORT_ID == 2)) + #error "Invalid RTE_PWM_2L_PIN pin Configuration!" +#endif +#endif +#ifdef CHIP_917_6x6 +#define RTE_PWM_2L_PORT_ID 0 +#if((RTE_PWM_2L_PORT_ID == 1)) + #error "Invalid RTE_PWM_2L_PIN pin Configuration!" +#endif +#endif +#if(RTE_PWM_2L_PORT_ID == 0) +#define RTE_PWM_2L_PORT 0 +#define RTE_PWM_2L_PIN 8 +#define RTE_PWM_2L_MUX 10 +#define RTE_PWM_2L_PAD 3 +#elif(RTE_PWM_2L_PORT_ID == 1) +#define RTE_PWM_2L_PORT 0 +#define RTE_PWM_2L_PIN 66 +#define RTE_PWM_2L_MUX 8 +#define RTE_PWM_2L_PAD 24 +#elif(RTE_PWM_2L_PORT_ID == 2) +#define RTE_PWM_2L_PORT 0 +#define RTE_PWM_2L_PIN 68 +#define RTE_PWM_2L_MUX 12 +#define RTE_PWM_2L_PAD 26 +#else + #error "Invalid RTE_PWM_2L_PIN Pin Configuration!" +#endif + +// PWM_3H <0=>GPIO_11 <1=>GPIO_69 +#define RTE_PWM_3H_PORT_ID 0 +#if(RTE_PWM_3H_PORT_ID == 0) +#define RTE_PWM_3H_PORT 0 +#define RTE_PWM_3H_PIN 11 +#define RTE_PWM_3H_MUX 10 +#define RTE_PWM_3H_PAD 6 +#elif(RTE_PWM_3H_PORT_ID == 1) +#define RTE_PWM_3H_PORT 0 +#define RTE_PWM_3H_PIN 69 +#define RTE_PWM_3H_MUX 8 +#define RTE_PWM_3H_PAD 27 +#else + #error "Invalid RTE_PWM_3H_PIN Pin Configuration!" +#endif + +// PWM_3L <0=>GPIO_10 <1=>GPIO_68 +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_PWM_3L_PORT_ID 1 +#else +#define RTE_PWM_3L_PORT_ID 0 +#endif +#if(RTE_PWM_3L_PORT_ID == 0) +#define RTE_PWM_3L_PORT 0 +#define RTE_PWM_3L_PIN 10 +#define RTE_PWM_3L_MUX 10 +#define RTE_PWM_3L_PAD 5 +#elif(RTE_PWM_3L_PORT_ID == 1) +#define RTE_PWM_3L_PORT 0 +#define RTE_PWM_3L_PIN 68 +#define RTE_PWM_3L_MUX 8 +#define RTE_PWM_3L_PAD 26 +#else + #error "Invalid RTE_PWM_3L_PIN Pin Configuration!" +#endif + + +// PWM_4H <0=>GPIO_15 <1=>GPIO_71 + +#ifndef CHIP_917_6x6 +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_PWM_4H_PORT_ID 1 +#else +#define RTE_PWM_4H_PORT_ID 0 +#endif +#endif +#ifdef CHIP_917_6x6 +#define RTE_PWM_4H_PORT_ID 1 +#if((RTE_PWM_4H_PORT_ID == 0)) + #error "Invalid RTE_PWM_4H_PIN pin Configuration!" +#endif +#endif +#if(RTE_PWM_4H_PORT_ID == 0) +#define RTE_PWM_4H_PORT 0 +#define RTE_PWM_4H_PIN 15 +#define RTE_PWM_4H_MUX 10 +#define RTE_PWM_4H_PAD 8 +#elif(RTE_PWM_4H_PORT_ID == 1) +#define RTE_PWM_4H_PORT 0 +#define RTE_PWM_4H_PIN 71 +#define RTE_PWM_4H_MUX 8 +#define RTE_PWM_4H_PAD 29 +#else + #error "Invalid RTE_PWM_4H_PIN Pin Configuration!" +#endif + + +// PWM_4H <0=>GPIO_12 <1=>GPIO_70 +#ifndef CHIP_917_6x6 +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_PWM_4L_PORT_ID 1 +#else +#define RTE_PWM_4L_PORT_ID 0 +#endif +#endif +#ifdef CHIP_917_6x6 +#define RTE_PWM_4L_PORT_ID 1 +#if(RTE_PWM_4L_PORT_ID == 0) + #error "Invalid RTE_PWM_4L_PIN pin Configuration!" +#endif +#endif +#if(RTE_PWM_4L_PORT_ID == 0) +#define RTE_PWM_4L_PORT 0 +#define RTE_PWM_4L_PIN 12 +#define RTE_PWM_4L_MUX 10 +#define RTE_PWM_4L_PAD 7 +#elif(RTE_PWM_4L_PORT_ID == 1) +#define RTE_PWM_4L_PORT 0 +#define RTE_PWM_4L_PIN 70 +#define RTE_PWM_4L_MUX 8 +#define RTE_PWM_4L_PAD 28 +#else + #error "Invalid RTE_PWM_4L_PIN Pin Configuration!" +#endif + + +// PWM_FAULTA <0=>GPIO_25 <1=>GPIO_68 <1=>GPIO_73 +#define RTE_PWM_FAULTA_PORT_ID 0 +#ifdef CHIP_917_6x6 +#if((RTE_PWM_FAULTA_PORT_ID == 2)) + #error "Invalid RTE_PWM_FAULTA_PIN pin Configuration!" +#endif +#endif +#if(RTE_PWM_FAULTA_PORT_ID == 0) +#define RTE_PWM_FAULTA_PORT 0 +#define RTE_PWM_FAULTA_PIN 25 +#define RTE_PWM_FAULTA_MUX 10 +#define RTE_PWM_FAULTA_PAD 0//no pad +#elif(RTE_PWM_FAULTA_PORT_ID == 1) +#define RTE_PWM_FAULTA_PORT 0 +#define RTE_PWM_FAULTA_PIN 68 +#define RTE_PWM_FAULTA_MUX 10 +#define RTE_PWM_FAULTA_PAD 26 +#elif(RTE_PWM_FAULTA_PORT_ID == 2) +#define RTE_PWM_FAULTA_PORT 0 +#define RTE_PWM_FAULTA_PIN 73 +#define RTE_PWM_FAULTA_MUX 8 +#define RTE_PWM_FAULTA_PAD 31 +#else + #error "Invalid RTE_PWM_FAULTA_PIN Pin Configuration!" +#endif + +// PWM_FAULTB <0=>GPIO_26 <1=>GPIO_69 <1=>GPIO_74 +#define RTE_PWM_FAULTB_PORT_ID 0 +#ifdef CHIP_917_6x6 +#if((RTE_PWM_FAULTB_PORT_ID == 2)) + #error "Invalid RTE_PWM_FAULTB_PIN pin Configuration!" +#endif +#endif +#if(RTE_PWM_FAULTB_PORT_ID == 0) +#define RTE_PWM_FAULTB_PORT 0 +#define RTE_PWM_FAULTB_PIN 26 +#define RTE_PWM_FAULTB_MUX 10 +#define RTE_PWM_FAULTB_PAD 0//no pad +#elif(RTE_PWM_FAULTB_PORT_ID == 1) +#define RTE_PWM_FAULTB_PORT 0 +#define RTE_PWM_FAULTB_PIN 69 +#define RTE_PWM_FAULTB_MUX 10 +#define RTE_PWM_FAULTB_PAD 27 +#elif(RTE_PWM_FAULTB_PORT_ID == 2) +#define RTE_PWM_FAULTB_PORT 0 +#define RTE_PWM_FAULTB_PIN 74 +#define RTE_PWM_FAULTB_MUX 8 +#define RTE_PWM_FAULTB_PAD 32 +#else + #error "Invalid RTE_PWM_FAULTB_PIN Pin Configuration!" +#endif +//PWM_SLP_EVENT_TRIG GPIO_72 +#define RTE_PWM_SLP_EVENT_TRIG_PORT 0 +#define RTE_PWM_SLP_EVENT_TRIG_PIN 72 +#define RTE_PWM_SLP_EVENT_TRIG_MUX 8 +#define RTE_PWM_SLP_EVENT_TRIG_PAD 30 + +//PWM_TMR_EXT_TRIG_1 <0=>GPIO_27 <1=>GPIO_51 <2=>GPIO_70 <3=>GPIO_75 +#define RTE_PWM_TMR_EXT_TRIG_1_PORT_ID 0 +#ifdef CHIP_917_6x6 +#if((RTE_PWM_TMR_EXT_TRIG_1_PORT_ID == 1)||(RTE_PWM_TMR_EXT_TRIG_1_PORT_ID == 3)) + #error "Invalid RTE_PWM_TMR_EXT_TRIG_1_PIN pin Configuration!" +#endif +#endif +#if(RTE_PWM_TMR_EXT_TRIG_1_PORT_ID == 0) +#define RTE_PWM_TMR_EXT_TRIG_1_PORT 0 +#define RTE_PWM_TMR_EXT_TRIG_1_PIN 27 +#define RTE_PWM_TMR_EXT_TRIG_1_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_1_PAD 0//no pad +#elif(RTE_PWM_TMR_EXT_TRIG_1_PORT_ID == 1) +#define RTE_PWM_TMR_EXT_TRIG_1_PORT 0 +#define RTE_PWM_TMR_EXT_TRIG_1_PIN 51 +#define RTE_PWM_TMR_EXT_TRIG_1_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_1_PAD 15 +#elif(RTE_PWM_TMR_EXT_TRIG_1_PORT_ID == 2) +#define RTE_PWM_TMR_EXT_TRIG_1_PORT 0 +#define RTE_PWM_TMR_EXT_TRIG_1_PIN 70 +#define RTE_PWM_TMR_EXT_TRIG_1_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_1_PAD 28 +#elif(RTE_PWM_TMR_EXT_TRIG_1_PORT_ID == 3) +#define RTE_PWM_TMR_EXT_TRIG_1_PORT 0 +#define RTE_PWM_TMR_EXT_TRIG_1_PIN 75 +#define RTE_PWM_TMR_EXT_TRIG_1_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_1_PAD 33 +#else + #error "Invalid RTE_PWM_TMR_EXT_TRIG_1_PIN Pin Configuration!" +#endif + + +//PWM_TMR_EXT_TRIG_2 <0=>GPIO_28 <1=>GPIO_54 <2=>GPIO_71 +#define RTE_PWM_TMR_EXT_TRIG_2_PORT_ID 0 +#ifdef CHIP_917_6x6 +#if((RTE_PWM_TMR_EXT_TRIG_2_PORT_ID == 1)) + #error "Invalid RTE_PWM_TMR_EXT_TRIG_2_PIN pin Configuration!" +#endif +#endif +#if(RTE_PWM_TMR_EXT_TRIG_2_PORT_ID == 0) +#define RTE_PWM_TMR_EXT_TRIG_2_PORT 0 +#define RTE_PWM_TMR_EXT_TRIG_2_PIN 28 +#define RTE_PWM_TMR_EXT_TRIG_2_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_2_PAD 0//no pad +#elif(RTE_PWM_TMR_EXT_TRIG_2_PORT_ID == 1) +#define RTE_PWM_TMR_EXT_TRIG_2_PORT 0 +#define RTE_PWM_TMR_EXT_TRIG_2_PIN 54 +#define RTE_PWM_TMR_EXT_TRIG_2_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_2_PAD 18 +#elif(RTE_PWM_TMR_EXT_TRIG_2_PORT_ID == 2) +#define RTE_PWM_TMR_EXT_TRIG_2_PORT 0 +#define RTE_PWM_TMR_EXT_TRIG_2_PIN 71 +#define RTE_PWM_TMR_EXT_TRIG_2_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_2_PAD 29 +#else + #error "Invalid RTE_PWM_TMR_EXT_TRIG_2_PIN Pin Configuration!" +#endif + + +//<> QEI (Quadrature Encode Interface) + +//QEI_DIR <0=>GPIO_28 <1=>GPIO_49 <2=>GPIO_57 <3=>GPIO_67 <4=>GPIO_71 <5=>GPIO_73 <6=>GPIO_11 <7=>GPIO_34 +#ifndef CHIP_917_6x6 +#define RTE_QEI_DIR_PORT_ID 4 +#if((RTE_QEI_DIR_PORT_ID == 7)||(RTE_QEI_DIR_PORT_ID == 6)) + #error "Invalid RTE_QEI_DIR_PIN pin Configuration!" +#endif +#endif +#ifdef CHIP_917_6x6 +#define RTE_QEI_DIR_PORT_ID 6 +#if((RTE_QEI_DIR_PORT_ID == 1)||(RTE_QEI_DIR_PORT_ID == 2)|| (RTE_QEI_DIR_PORT_ID == 3)||(RTE_QEI_DIR_PORT_ID == 5)) + #error "Invalid RTE_QEI_DIR_PIN pin Configuration!" +#endif +#endif +#if(RTE_QEI_DIR_PORT_ID == 0) +#define RTE_QEI_DIR_PORT 0 +#define RTE_QEI_DIR_PIN 28 +#define RTE_QEI_DIR_MUX 5 +#define RTE_QEI_DIR_PAD 0//no pad +#elif(RTE_QEI_DIR_PORT_ID == 1) +#define RTE_QEI_DIR_PORT 0 +#define RTE_QEI_DIR_PIN 49 +#define RTE_QEI_DIR_MUX 3 +#define RTE_QEI_DIR_PAD 13 +#elif(RTE_QEI_DIR_PORT_ID == 2) +#define RTE_QEI_DIR_PORT 0 +#define RTE_QEI_DIR_PIN 57 +#define RTE_QEI_DIR_MUX 5 +#define RTE_QEI_DIR_PAD 21 +#elif(RTE_QEI_DIR_PORT_ID == 3) +#define RTE_QEI_DIR_PORT 0 +#define RTE_QEI_DIR_PIN 67 +#define RTE_QEI_DIR_MUX 3 +#define RTE_QEI_DIR_PAD 25 +#elif(RTE_QEI_DIR_PORT_ID == 4) +#define RTE_QEI_DIR_PORT 0 +#define RTE_QEI_DIR_PIN 71 +#define RTE_QEI_DIR_MUX 3 +#define RTE_QEI_DIR_PAD 29 +#elif(RTE_QEI_DIR_PORT_ID == 5) +#define RTE_QEI_DIR_PORT 0 +#define RTE_QEI_DIR_PIN 73 +#define RTE_QEI_DIR_MUX 3 +#define RTE_QEI_DIR_PAD 31 +#elif(RTE_QEI_DIR_PORT_ID == 6) +#define RTE_QEI_DIR_PORT 0 +#define RTE_QEI_DIR_PIN 11 +#define RTE_QEI_DIR_MUX 5 +#define RTE_QEI_DIR_PAD 6 +#elif(RTE_QEI_DIR_PORT_ID == 7) +#define RTE_QEI_DIR_PORT 0 +#define RTE_QEI_DIR_PIN 34 +#define RTE_QEI_DIR_MUX 13 +#define RTE_QEI_DIR_PAD 9 +#else + #error "Invalid RTE_QEI_DIR_PIN Pin Configuration!" +#endif + + +//QEI_IDX <0=>GPIO_25 <1=>GPIO_46 <2=>GPIO_52 <3=>GPIO_64 <4=>GPIO_68 <5=>GPIO_72 <6=>GPIO_8 <7=>GPIO_13 +#ifndef CHIP_917_6x6 +#define RTE_QEI_IDX_PORT_ID 4 +#if((RTE_QEI_IDX_PORT_ID == 7)||(RTE_QEI_IDX_PORT_ID == 6)) + #error "Invalid RTE_QEI_IDX_PIN pin Configuration!" +#endif +#endif +#ifdef CHIP_917_6x6 +#define RTE_QEI_IDX_PORT_ID 6 +#if((RTE_QEI_IDX_PORT_ID == 1) || (RTE_QEI_IDX_PORT_ID == 2)||(RTE_QEI_IDX_PORT_ID == 3)||(RTE_QEI_IDX_PORT_ID == 5)) + #error "Invalid RTE_QEI_IDX_PIN pin Configuration!" +#endif +#endif +#if(RTE_QEI_IDX_PORT_ID == 0) +#define RTE_QEI_IDX_PORT 0 +#define RTE_QEI_IDX_PIN 25 +#define RTE_QEI_IDX_MUX 5 +#define RTE_QEI_IDX_PAD 0//no pad +#elif(RTE_QEI_IDX_PORT_ID == 1) +#define RTE_QEI_IDX_PORT 0 +#define RTE_QEI_IDX_PIN 46 +#define RTE_QEI_IDX_MUX 3 +#define RTE_QEI_IDX_PAD 10 +#elif(RTE_QEI_IDX_PORT_ID == 2) +#define RTE_QEI_IDX_PORT 0 +#define RTE_QEI_IDX_PIN 52 +#define RTE_QEI_IDX_MUX 5 +#define RTE_QEI_IDX_PAD 16 +#elif(RTE_QEI_IDX_PORT_ID == 3) +#define RTE_QEI_IDX_PORT 0 +#define RTE_QEI_IDX_PIN 64 +#define RTE_QEI_IDX_MUX 3 +#define RTE_QEI_IDX_PAD 22 +#elif(RTE_QEI_IDX_PORT_ID == 4) +#define RTE_QEI_IDX_PORT 0 +#define RTE_QEI_IDX_PIN 68 +#define RTE_QEI_IDX_MUX 3 +#define RTE_QEI_IDX_PAD 26 +#elif(RTE_QEI_IDX_PORT_ID == 5) +#define RTE_QEI_IDX_PORT 0 +#define RTE_QEI_IDX_PIN 72 +#define RTE_QEI_IDX_MUX 3 +#define RTE_QEI_IDX_PAD 30 +#elif(RTE_QEI_IDX_PORT_ID == 6) +#define RTE_QEI_IDX_PORT 0 +#define RTE_QEI_IDX_PIN 8 +#define RTE_QEI_IDX_MUX 5 +#define RTE_QEI_IDX_PAD 3 +#elif(RTE_QEI_IDX_PORT_ID == 7) +#define RTE_QEI_IDX_PORT 0 +#define RTE_QEI_IDX_PIN 31 +#define RTE_QEI_IDX_MUX 13 +#define RTE_QEI_IDX_PAD 9 +#else + #error "Invalid RTE_QEI_IDX_PIN Pin Configuration!" +#endif + + +//QEI_PHA <0=>GPIO_26 <1=>GPIO_47 <2=>GPIO_53 <3=>GPIO_65 <4=>GPIO_69 <5=>GPIO_73 <6=>GPIO_9 <7=>GPIO_32 +#ifndef CHIP_917_6x6 +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_QEI_PHA_PORT_ID 4 +#else +#define RTE_QEI_PHA_PORT_ID 5 +#endif +#if((RTE_QEI_PHA_PORT_ID == 7)||(RTE_QEI_PHA_PORT_ID == 6)) + #error "Invalid RTE_QEI_PHA_PIN pin Configuration!" +#endif +#endif +#ifdef CHIP_917_6x6 +#define RTE_QEI_PHA_PORT_ID 6 +#if((RTE_QEI_PHA_PORT_ID == 1)||(RTE_QEI_PHA_PORT_ID == 2)||(RTE_QEI_PHA_PORT_ID == 3)||(RTE_QEI_PHA_PORT_ID == 5)) + #error "Invalid RTE_QEI_PHA_PIN pin Configuration!" +#endif +#endif +#if(RTE_QEI_PHA_PORT_ID == 0) +#define RTE_QEI_PHA_PORT 0 +#define RTE_QEI_PHA_PIN 26 +#define RTE_QEI_PHA_MUX 5 +#define RTE_QEI_PHA_PAD 0//no pad +#elif(RTE_QEI_PHA_PORT_ID == 1) +#define RTE_QEI_PHA_PORT 0 +#define RTE_QEI_PHA_PIN 47 +#define RTE_QEI_PHA_MUX 3 +#define RTE_QEI_PHA_PAD 11 +#elif(RTE_QEI_PHA_PORT_ID == 2) +#define RTE_QEI_PHA_PORT 0 +#define RTE_QEI_PHA_PIN 53 +#define RTE_QEI_PHA_MUX 5 +#define RTE_QEI_PHA_PAD 17 +#elif(RTE_QEI_PHA_PORT_ID == 3) +#define RTE_QEI_PHA_PORT 0 +#define RTE_QEI_PHA_PIN 65 +#define RTE_QEI_PHA_MUX 3 +#define RTE_QEI_PHA_PAD 23 +#elif(RTE_QEI_PHA_PORT_ID == 4) +#define RTE_QEI_PHA_PORT 0 +#define RTE_QEI_PHA_PIN 69 +#define RTE_QEI_PHA_MUX 3 +#define RTE_QEI_PHA_PAD 27 +#elif(RTE_QEI_PHA_PORT_ID == 5) +#define RTE_QEI_PHA_PORT 0 +#define RTE_QEI_PHA_PIN 73 +#define RTE_QEI_PHA_MUX 3 +#define RTE_QEI_PHA_PAD 31 +#elif(RTE_QEI_PHA_PORT_ID == 6) +#define RTE_QEI_PHA_PORT 0 +#define RTE_QEI_PHA_PIN 9 +#define RTE_QEI_PHA_MUX 5 +#define RTE_QEI_PHA_PAD 4 +#elif(RTE_QEI_PHA_PORT_ID == 7) +#define RTE_QEI_PHA_PORT 0 +#define RTE_QEI_PHA_PIN 32 +#define RTE_QEI_PHA_MUX 13 +#define RTE_QEI_PHA_PAD 9 +#else + #error "Invalid RTE_QEI_PHA_PIN Pin Configuration!" +#endif + +//QEI_PHB <0=>GPIO_27 <1=>GPIO_48 <1=>GPIO_56 <1=>GPIO_66 <1=>GPIO_70 <1=>GPIO_74 <7=>GPIO_33 +#ifndef CHIP_917_6x6 +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_QEI_PHB_PORT_ID 5 +#else +#define RTE_QEI_PHB_PORT_ID 4 +#endif +#if((RTE_QEI_PHB_PORT_ID == 6) || (RTE_QEI_PHB_PORT_ID == 7)) + #error "Invalid RTE_QEI_PHB_PIN Configuration!" +#endif +#endif +#ifdef CHIP_917_6x6 +#define RTE_QEI_PHB_PORT_ID 6 +#if((RTE_QEI_PHB_PORT_ID == 1) || (RTE_QEI_PHB_PORT_ID == 2)||(RTE_QEI_PHB_PORT_ID == 3)||(RTE_QEI_PHB_PORT_ID == 5) ) + #error "Invalid RTE_QEI_PHB_PIN Configuration!" +#endif +#endif +#if(RTE_QEI_PHB_PORT_ID == 0) +#define RTE_QEI_PHB_PORT 0 +#define RTE_QEI_PHB_PIN 27 +#define RTE_QEI_PHB_MUX 5 +#define RTE_QEI_PHB_PAD 0//no pad +#elif(RTE_QEI_PHB_PORT_ID == 1) +#define RTE_QEI_PHB_PORT 0 +#define RTE_QEI_PHB_PIN 48 +#define RTE_QEI_PHB_MUX 3 +#define RTE_QEI_PHB_PAD 12 +#elif(RTE_QEI_PHB_PORT_ID == 2) +#define RTE_QEI_PHB_PORT 0 +#define RTE_QEI_PHB_PIN 56 +#define RTE_QEI_PHB_MUX 5 +#define RTE_QEI_PHB_PAD 20 +#elif(RTE_QEI_PHB_PORT_ID == 3) +#define RTE_QEI_PHB_PORT 0 +#define RTE_QEI_PHB_PIN 66 +#define RTE_QEI_PHB_MUX 3 +#define RTE_QEI_PHB_PAD 24 +#elif(RTE_QEI_PHB_PORT_ID == 4) +#define RTE_QEI_PHB_PORT 0 +#define RTE_QEI_PHB_PIN 70 +#define RTE_QEI_PHB_MUX 3 +#define RTE_QEI_PHB_PAD 28 +#elif(RTE_QEI_PHB_PORT_ID == 5) +#define RTE_QEI_PHB_PORT 0 +#define RTE_QEI_PHB_PIN 74 +#define RTE_QEI_PHB_MUX 3 +#define RTE_QEI_PHB_PAD 32 +#elif(RTE_QEI_PHB_PORT_ID == 6) +#define RTE_QEI_PHB_PORT 0 +#define RTE_QEI_PHB_PIN 10 +#define RTE_QEI_PHB_MUX 5 +#define RTE_QEI_PHB_PAD 5 +#elif(RTE_QEI_PHB_PORT_ID == 7) +#define RTE_QEI_PHB_PORT 0 +#define RTE_QEI_PHB_PIN 33 +#define RTE_QEI_PHB_MUX 13 +#define RTE_QEI_PHB_PAD 9 +#else + #error "Invalid RTE_QEI_PHB_PIN Pin Configuration!" +#endif + + +#endif diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_crc.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_crc.h new file mode 100644 index 000000000..773e20670 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_crc.h @@ -0,0 +1,89 @@ +/******************************************************************************* +* @file rsi_crc.h +* @brief +******************************************************************************* +* # License +* Copyright 2022 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +// Includes Files + +#include "rsi_ccp_common.h" +#include "base_types.h" + +#ifndef RSI_CRC_H +#define RSI_CRC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define DIN_WIDTH_32 31 +#define DIN_WIDTH_16 15 +#define DIN_WIDTH_8 7 + +// brief: Structure of CRC Calculation +typedef struct { + uint32_t crc; //Calculated CRC Value + uint32_t polynomial; //Polynomial Value for CRC Calculation + uint32_t + polyWidth : 5; //Number of bits/width of the polynomial has to be written here for the computation of final CRC + uint32_t lfsrVal; //lfsr Initialization value for CRC Calculation + uint32_t widthType : 3; //Data Width taken Variable. + //When width_type - 0 :Take the data width from either reg programmed or from cnt + //width_type -1 :Take the data width from Reg. + //width_type-2 : Take the data width from CNT. + uint32_t dinWidth : 5; //Valid number of bits in the input data in din_width_from_reg set mode + uint32_t numBytes; //Input data number of bytes + uint32_t aempty : 4; //Almost empty Threshold value. Max value is 15 + uint32_t afull : 4; //Almost Full Threshold value. Max value is 15 + uint32_t InputData; + uint32_t swapLfsr; + uint32_t swapDin; + uint32_t useUdma; + uint32_t inputSize; + uint32_t dataIn; + uint32_t bitWidth; + uint32_t lfsrState; +} RSI_CRC_PARAMS_T; + +// CRC FUNCTION PROTOTYPES +void crc_set_gen_control(CRC_Type *pCRC); + +uint32_t crc_get_gen_status(CRC_Type *pCRC); + +void crc_polynomial(CRC_Type *pCRC, RSI_CRC_PARAMS_T *pCRCParams); + +uint32_t crc_polynomial_width(CRC_Type *pCRC, RSI_CRC_PARAMS_T *pCRCParams); + +void crc_lfsr_init(CRC_Type *pCRC, RSI_CRC_PARAMS_T *pCRCParams); + +uint32_t crc_use_swapped_init(CRC_Type *pCRC, RSI_CRC_PARAMS_T *pCRCParams); + +uint32_t crc_set_data_width_type(CRC_Type *pCRC, RSI_CRC_PARAMS_T *pCRCParams); + +uint32_t crc_set_fifo_thresholds(CRC_Type *pCRC, RSI_CRC_PARAMS_T *pCRCParams); + +uint32_t crc_write_data(CRC_Type *pCRC, RSI_CRC_PARAMS_T *pCRCParams, uint32_t data); + +uint32_t monitor_crc_calc(CRC_Type *pCRC, RSI_CRC_PARAMS_T *pCRCParams); + +void crc_lfsr_dynamic_write(CRC_Type *pCRC, RSI_CRC_PARAMS_T *pCRCParams); + +void crc_reset_fifo(CRC_Type *pCRC); + +uint32_t crc_get_fifo_status(CRC_Type *pCRC); +#ifdef __cplusplus +} +#endif + +#endif // RSI_CRC_H diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_ct.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_ct.h new file mode 100644 index 000000000..35d55f344 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_ct.h @@ -0,0 +1,1076 @@ +/******************************************************************************* +* @file rsi_ct.h +* @brief +******************************************************************************* +* # License +* Copyright 2022 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +// Include Files + +#include "rsi_ccp_common.h" +#include "base_types.h" +#include "rsi_error.h" + +#ifndef RSI_CT_H +#define RSI_CT_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define RSI_CT_API_VERSION RSI_DRIVER_VERSION_MAJOR_MINOR(2, 00) // API version 0.1 +#define RSI_CT_DRV_VERSION RSI_DRIVER_VERSION_MAJOR_MINOR(00, 01) // driver version 0.1 + +#define CLK_ENABLE_SET_3_REG (*((uint32_t volatile *)(0x46000000 + 0x10))) +#define M4SS_CT_INTR_SEL (*((uint32_t volatile *)(0x46110000 + 0x10))) + +#define ENABLE 1 +#define DISABLE 0 + +#define LOW 0 +#define HIGH 1 + +#define INPUT_CNT 4 +#define OUTPUT_CNT 8 +#define COUNTERS_CNT 2 +#define EVENT_CNT 38 +#define DMA_MODE 1 + +//CT Interrupt Flags +#define RSI_CT_EVENT_INTR_0_l (1UL << 0) // Counter 0 Interrupt event interrupt flag +#define RSI_CT_EVENT_FIFO_0_FULL_l (1UL << 1) // FIFO full signal of Counter 0 interrupt flag +#define RSI_CT_EVENT_COUNTER_0_IS_ZERO_l (1UL << 2) // Counter 0 hit zero in active mode interrupt flag +#define RSI_CT_EVENT_COUNTER_0_IS_PEAK_l (1UL << 3) // Counter 0 hit peak (MATCH) in active mode interrupt flag +#define RSI_CT_EVENT_INTR_1_l (1UL << 16) // Counter 1 Interrupt event interrupt flag +#define RSI_CT_EVENT_FIFO_1_FULL_l (1UL << 17) // FIFO full signal of Counter 1 interrupt flag +#define RSI_CT_EVENT_COUNTER_1_IS_ZERO_l (1UL << 18) // Counter 1 hit zero in active mode interrupt flag +#define RSI_CT_EVENT_COUNTER_1_IS_PEAK_l (1UL << 19) // Counter 1 hit peak (MATCH) in active mode interrupt flag + +#define COUNTER_0 0 +#define COUNTER_1 1 +#define COUNTER_0_1 2 + +// CT Control Set Register Bits +#define COUNTER0_UP (0x1 << 4) +#define COUNTER0_DOWN (0x2 << 4) +#define COUNTER0_UP_DOWN (0x3 << 4) + +#define COUNTER1_UP (0x1 << 20) +#define COUNTER1_DOWN (0x2 << 20) +#define COUNTER1_UP_DOWN (0x3 << 20) + +#define COUNTER32_BITMODE (1UL << 0) // 32 bit Counter mode +#define SOFTRESET_COUNTER_0 (1UL << 1) // soft reset counter 0 +#define PERIODIC_ENCOUNTER_0 (1UL << 2) // Periodic/One shot counter 0 +#define COUNTER0_TRIG (1UL << 3) // trigger Counter 0 +#define COUNTER0_SYNC_TRIG (1UL << 6) // Sync trigger for counter 0 +#define BUF_REG0EN (1UL << 7) // Buffer enable for counter 0 +#define SOFTRESET_COUNTER_1 (1UL << 17) // soft reset counter 1 +#define PERIODIC_ENCOUNTER_1 (1UL << 18) // Periodic/One shot counter 1 +#define COUNTER1_TRIG (1UL << 19) // trigger Counter 1 +#define COUNTER1_SYNC_TRIG (1UL << 22) // Sync trigger for counter 1 +#define BUF_REG1EN (1UL << 23) // Buffer enable for counter 1 + +#define RISE_EDGE_MASK0 (1UL << 0) +#define RISE_EDGE_MASK1 (1UL << 1) +#define RISE_EDGE_MASK2 (1UL << 2) +#define RISE_EDGE_MASK3 (1UL << 3) + +#define FALL_EDGE_MASK0 (1UL << 4) +#define FALL_EDGE_MASK1 (1UL << 5) +#define FALL_EDGE_MASK2 (1UL << 6) +#define FALL_EDGE_MASK3 (1UL << 7) + +#define RFE_EDGE_MASK0 (1UL << 8) +#define RFE_EDGE_MASK1 (1UL << 9) +#define RFE_EDGE_MASK2 (1UL << 10) +#define RFE_EDGE_MASK3 (1UL << 11) + +#define LEVEL_LOW_MASK0 (1UL << 12) +#define LEVEL_LOW_MASK1 (1UL << 13) +#define LEVEL_LOW_MASK2 (1UL << 14) +#define LEVEL_LOW_MASK3 (1UL << 15) + +#define LEVEL_HIGH_MASK0 (1UL << 16) +#define LEVEL_HIGH_MASK1 (1UL << 17) +#define LEVEL_HIGH_MASK2 (1UL << 18) +#define LEVEL_HIGH_MASK3 (1UL << 19) + +// CT example defines +#define OUTPUT_OCU_0 (1UL << 0) // Counter 0 output OCU +#define OCU_DMA_0 (1UL << 4) // Counter 0 OCU DMA enable +#define OCU_8_MODE_0 (1UL << 5) // OCU using 16 bit mode +#define OUTPUT_OCU_1 (1UL << 16) // Counter 1output OCU +#define OCU_DMA_1 (1UL << 20) // Counter 1 OCU DMA enable +#define OCU_8_MODE_1 (1UL << 21) // OCU using 16 bit mode +#define MAKE_OUTPUT_0_HIGH_SEL_0 (0x2 << 6) +#define MAKE_OUTPUT_0_LOW_SEL_0 (0x3 << 9) +#define MAKE_OUTPUT_1_HIGH_SEL_1 (0x3 << 22) +#define MAKE_OUTPUT_1_LOW_SEL_1 (0x2 << 25) +#define OCU_SYNC_WITH_0 (0x1 << 1) +#define OCU_SYNC_WITH_1 (0x1 << 17) + +#define OUTPUT_0_TGL_0_MAX 7 // Counter 0 output OCU +#define OUTPUT_0_TGL_1_MAX 7 // Counter 0 OCU DMA enable +#define TGL_CNT_0_PEAK 0xFF // OCU using 16 bit mode +#define OUTPUT_1_TGL_0_MAX 7 // Counter 0 output OCU +#define OUTPUT_1_TGL_1_MAX 7 // Counter 0 OCU DMA enable +#define TGL_CNT_1_PEAK 0xFF + +#define MAX_PEAK_VALUE_0 0x1000 +#define MAX_PEAK_VLAUE_1 0x2000 + +#define UDMA_CHNL_0 0 +#define UDMA_CHNL_1 1 +#define UDMA_CHNL_2 2 +#define UDMA_CHNL_3 3 +#define UDMA_CHNL_4 4 +#define UDMA_CHNL_5 5 +#define UDMA_CHNL_6 6 +#define UDMA_CHNL_7 7 + +#define UDMA_CONTROL_TABLE_BASE_CHNL0 0x00000000 +#define UDMA_CONTROL_TABLE_BASE_CHNL1 0x00000010 +#define WFG_ON_PERIOD 0xFF + +#define USE_DMA 1 +#define NO_DMA 0 + +#define PERIODIC_EN_COUNTER_0_FRM_REG (1UL << 2) +#define PERIODIC_EN_COUNTER_1_FRM_REG (1UL << 18) +#define COUNTER_0_TRIG (1UL << 3) +#define COUNTER_1_TRIG (1UL << 19) +#define COUNTER_0_UP (0x1 << 4) +#define COUNTER_1_UP (0x1 << 20) + +#define MAKE_OUTPUT_0_TGL_SEL_1 1 + +#define AND_COUNTER0(valid, event) ((event << 0) | (valid << 8)) +#define AND_COUNTER1(valid, event) ((event << 16) | (valid << 24)) + +#define OR_COUNTER0(valid, event) ((event << 0) | (valid << 8)) +#define OR_COUNTER1(valid, event) ((event << 16) | (valid << 24)) + +typedef CT0_Type RSI_CT_T; +typedef CT_MUX_REG_Type RSI_CT_MUX_REG_T; + +/**============================================================================ + * @brief CT Driver Capabilities. + ============================================================================**/ + +typedef struct { + uint32_t NoOfInputs : 3; /*!< Number of Input signals */ + uint32_t NoOfOutputs : 4; /*!< Number of Output signlas */ + uint32_t NumOfCounters : 4; /*!< Number of Counters present in CT module */ + uint32_t NoOfEvents : 6; /*!< Number of Events can be generated by input events */ + uint32_t DMAIntf : 1; /*!< Supports DMA interface or not */ +} RSI_CT_CAPABILITIES_T; +/****** CT Events ******/ +#define CT_EVT_0 1 +#define CT_EVT_1 2 +#define CT_EVT_2 3 +#define CT_EVT_3 4 +#define CT_EVT_4 5 +#define CT_EVT_5 6 +#define CT_EVT_6 7 +#define CT_EVT_7 8 +#define CT_EVT_8 9 +#define CT_EVT_9 10 +#define CT_EVT_10 11 +#define CT_EVT_11 12 +#define CT_EVT_12 13 +#define CT_EVT_13 14 +#define CT_EVT_14 15 +#define CT_EVT_15 16 +#define CT_EVT_16 17 +#define CT_EVT_17 18 +#define CT_EVT_18 19 +#define CT_EVT_19 20 +#define CT_EVT_20 21 +#define CT_EVT_21 22 +#define CT_EVT_22 23 +#define CT_EVT_23 24 +#define CT_EVT_24 25 +#define CT_EVT_25 26 +#define CT_EVT_26 27 +#define CT_EVT_27 28 +#define CT_EVT_28 29 +#define CT_EVT_29 30 +#define CT_EVT_30 31 +#define CT_EVT_31 32 +#define CT_EVT_32 33 +#define CT_EVT_33 34 +#define CT_EVT_34 35 +#define CT_EVT_35 36 +#define CT_EVT_36 37 +#define CT_EVT_37 38 + +// CT Callback Flags +#define CT_INTR_0_l_CB 0x01 // Callback ID for Counter 0 Interrupt event +#define CT_FIFO_0_FULL_l_CB 0x02 // Callback ID for FIFO full signal of Counter 0 +#define CT_COUNTER_0_IS_ZERO_l_CB 0x03 // Callback ID for Counter 0 hit zero in active mode +#define CT_COUNTER_0_IS_PEAK_l_CB 0x04 // Callback ID for Counter 0 hit peak (MATCH) in active mode +#define CT_INTR_1_l_CB 0x05 // Callback ID for Counter 1 Interrupt event +#define CT_FIFO_1_FULL_l_CB 0x06 // Callback ID for FIFO full signal of Counter 1 +#define CT_COUNTER_1_IS_ZERO_l_CB 0x07 // Callback ID for Counter 1 hit zero in active mode +#define CT_COUNTER_1_IS_PEAK_l_CB 0x08 // Callback ID for Counter 1 hit peak (MATCH) in active mode +#define CT_OCU_DMA_EN_COUNTER0 0x09 // OCU DMA call back +#define CT_OCU_DMA_EN_COUNTER1 0x0A + +// OCU parameter structure +typedef struct OCU_PARAMS { + uint16_t CompareVal1_0; /*!< two thresholds for counter 0 */ + uint16_t CompareVal2_0; + uint16_t CompareVal1_1; + uint16_t CompareVal2_1; + uint16_t CompareNextVal1_0; /*!< two next threshols for counter 0 */ + uint16_t CompareNextVal2_0; + uint16_t CompareNextVal1_1; // next threshold for counter 1 + uint16_t CompareNextVal2_1; // next threshold for counter 1 + uint16_t SyncWith0; // Sync Value + uint16_t SyncWith1; +} OCU_PARAMS_T; + +// WFG control parameters structure +typedef struct WFG_PARAMS { + uint32_t output0_tgl0_sel; + uint32_t output0_tgl1_sel; + uint32_t tgl_cnt0_peak; + uint32_t output1_tgl0_sel; + uint32_t output1_tgl1_sel; + uint32_t tgl_cnt1_peak; +} WFG_PARAMS_T; + +// brief MCPWM Callback structure +typedef struct { + void (*cbFunc)(uint8_t event, uint8_t counterNum); // Call back function pointer +} RSI_CT_CALLBACK_T; + +// brief CT handle type +typedef void *RSI_CT_HANDLE_T; + +/*===================================================*/ +/** + * @fn void RSI_CT_Config(RSI_CT_T *pCT, boolean_t cfg) + * @brief This API is used to set the 32bit/ 16bit coutners + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] cfg : if cfg = 0 32bit Counter, cfg = 1 16bit counter + * @return none + */ +STATIC INLINE void RSI_CT_Config(RSI_CT_T *pCT, boolean_t cfg) +{ + // 32bit/16bit Counters + if (cfg == 1) { + pCT->CT_GEN_CTRL_SET_REG = (1 << 0); + } else { + pCT->CT_GEN_CTRL_RESET_REG = (1 << 0); + } +} + +/*===================================================*/ +/** + * @fn void RSI_CT_SetControl(RSI_CT_T *pCT, uint32_t value) + * @brief Programs General control register bit fields + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] value : This parameter can be the logical OR of the below parameters + - \ref COUNTER32_BITMODE : sets 32bit mode + - \ref SOFTRESET_COUNTER_0 : Resets coutner 0 + - \ref PERIODIC_ENCOUNTER_0 : sets periodic mode + - \ref COUNTER0_TRIG : starts counter 0 + - \ref COUNTER0_UP_DOWN : Counter 0 direction (0,1,2,3) + - \ref COUNTER0_SYNC_TRIG : This enables the counter 0 to run/active when sync is found. + - \ref BUF_REG0EN : Buffer will be enabled and in path for Counter 0 + - \ref SOFTRESET_COUNTER_1 : Resets Counter 1 + - \ref PERIODIC_ENCOUNTER_1 : sets periodic mode + - \ref COUNTER1_TRIG : starts counter 1 + - \ref COUNTER1_UP_DOWN : Counter 1 direction (0,1,2,3) + - \ref COUNTER1_SYNC_TRIG : This enables the counter 1 to run/active when sync is found. + - \ref BUF_REG1EN : Buffer will be enabled and in path for counter 1. + * @return none +*/ +STATIC INLINE void RSI_CT_SetControl(RSI_CT_T *pCT, uint32_t value) +{ + // Sets required control bits + pCT->CT_GEN_CTRL_SET_REG = value; +} + +/*===================================================*/ +/** + * @fn void RSI_CT_ClearControl(RSI_CT_T *pCT, uint32_t value) + * @brief This API is used to Reset the required control bits in general control set register + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] value : This parameter can be the logical OR of the required bit ,fields in CT Reset Control register as below. + - \ref COUNTER32_BITMODE : Sets 16bit mode + - \ref PERIODIC_ENCOUNTER_0 : Sets Counter_0 will be in single count mode. + - \ref COUNTER0_UP_DOWN : counter 0 to run in up/down/up-down/down-up directions (0,1,2,3) + - \ref BUF_REG0EN : Buffer will be disabled and in path and in path for Counter 0 + - \ref PERIODIC_ENCOUNTER_1 : sets Counter 1 will be in single count mode + - \ref COUNTER1_UP_DOWN : Counter 1 to run in up/down/up-down/down-up directions(0,1,2,3) + - \ref BUF_REG1EN : Buffer will be disabled and in path for counter 1. + * @return none + */ +STATIC INLINE void RSI_CT_ClearControl(RSI_CT_T *pCT, uint32_t value) +{ + // Resets required control bits + pCT->CT_GEN_CTRL_RESET_REG = value; +} + +/*===================================================*/ +/** + * @fn void RSI_CT_StartEventSelect(RSI_CT_T *pCT,uint32_t value) + * @brief This API is used to select the input event to start any counter + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] value : ORed value of Events for counter0 and counter1 + \n This parameter can be the logical OR of the event number for counter 0 and counter 1 + \n possible event numbers are 1 to 38 if 0 : No event is selected + * @return none + */ +STATIC INLINE void RSI_CT_StartEventSelect(RSI_CT_T *pCT, uint32_t value) +{ + pCT->CT_START_COUNTER_EVENT_SEL |= value; +} + +/*===================================================*/ +/** + * @fn void RSI_CT_StartEventConfig(RSI_CT_T *pCT,uint32_t andValue,uint32_t orValue) + * @brief This API is used to Configure AND/OR event for start counter operation + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] andValue : This parameter can be the logical OR of the below parameters. + - START_COUNTER_0_AND_EVENT : AND expression for AND event in start Counter_0 event, + possible values are 0x0 to 0xF. + - START_COUNTER_0_AND_VLD : Indicates which bits valid for considering AND event, + possible values are 0x0 to 0xF. + - START_COUNTER_1_AND_EVENT : AND expression for AND event in start Counter_1 event, + possible values are 0x0 to 0xF. + - START_COUNTER_1_AND_VLD : Indicates which bits valid for considering AND event, + possible values are 0x0 to 0xF. + * @param[in] orValue : This parameter can be the logical OR of the below parameters + - START_COUNTER_0_OR_EVENT : OR expression for OR event in start Counter_0 event, + possible values are 0x0 to 0xF. + - START_COUNTER_0_OR_VLD : Indicates which bits valid for considering OR event, + possible values are 0x0 to 0xF. + - START_COUNTER_1_OR_EVENT : OR expression for OR event in start Counter_1 event, + possible values are 0x0 to 0xF. + - START_COUNTER_1_OR_VLD : Indicates which bits valid for considering OR event, + possible values are 0x0 to 0xF. + * @return none + */ +STATIC INLINE void RSI_CT_StartEventConfig(RSI_CT_T *pCT, uint32_t andValue, uint32_t orValue) +{ + // AND Event configuration for counter start + pCT->CT_START_COUNTER_AND_EVENT |= andValue; + // OR Event configuration for counter start + pCT->CT_START_COUNTER_OR_EVENT |= orValue; +} + +/*===================================================*/ +/** + * @fn void RSI_CT_StopEventConfig(RSI_CT_T *pCT,uint32_t andValue,uint32_t orValue) + * @brief This API is used to Configure AND/OR event for stop counter operation + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] andValue : Stop Counter AND Event register value, this parameter can be the logical OR of the + - STOP_COUNTER_0_AND_EVENT : AND expression for AND event in stop Counter_0 event, + possible values are 0x0 to 0xF, + - STOP_COUNTER_0_AND_VLD : Indicates which bits valid for considering AND event, + possible values are 0x0 to 0xF + - STOP_COUNTER_1_AND_EVENT : AND expression for AND event in stop Counter_1 event, + possible values are 0x0 to 0xF, + - STOP_COUNTER_1_AND_VLD : Indicates which bits valid for considering AND event, + possible values are 0x0 to 0xF + * @param[in] orValue : Stop Counter OR Event register value,this parameter can be the logical OR of the + - STOP_COUNTER_0_OR_EVENT : OR expression for OR event in stop Counter_0 event, + possible values are 0x0 to 0xF, + - STOP_COUNTER_0_OR_VLD : Indicates which bits valid for considering OR event, + possible values are 0x0 to 0xF + - STOP_COUNTER_1_OR_EVENT : OR expression for OR event in stop Counter_1 event, + possible values are 0x0 to 0xF, + - STOP_COUNTER_1_OR_VLD : Indicates which bits valid for considering OR event, + possible values are 0x0 to 0xF + * @return none + */ +STATIC INLINE void RSI_CT_StopEventConfig(RSI_CT_T *pCT, uint32_t andValue, uint32_t orValue) +{ + // AND Event configuration for counter stop + pCT->CT_STOP_COUNTER_AND_EVENT |= andValue; + // OR Event configuration for counter stop + pCT->CT_STOP_COUNTER_OR_EVENT |= orValue; +} + +/*===================================================*/ +/** + * @fn void RSI_CT_ContinueEventConfig(RSI_CT_T *pCT,uint32_t andValue,uint32_t orValue) + * @brief This API is used to Configure AND/OR event for Continue operation + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] andValue : Continue Counter AND Event register value,this parameter can be the logical OR of the + - CONTINUE_COUNTER_0_AND_EVENT : AND expression for AND event in continue Counter_0 event, + possible values are 0x0 to 0xF, + - CONTINUE_COUNTER_0_AND_VLD : Indicates which bits valid for considering AND event, + possible values are 0x0 to 0xF + - CONTINUE_COUNTER_1_AND_EVENT : AND expression for AND event in continue Counter_1 event, + possible values are 0x0 to 0xF, + - CONTINUE_COUNTER_1_AND_VLD : Indicates which bits valid for considering AND event, + possible values are 0x0 to 0xF + * @param[in] orValue : Continue Counter OR Event register value,this parameter can be the logical OR of the + - CONTINUE_COUNTER_0_OR_EVENT : OR expression for OR event in continue Counter_0 event, + possible values are 0x0 to 0xF, + - CONTINUE_COUNTER_0_OR_VLD : Indicates which bits valid for considering OR event, + possible values are 0x0 to 0xF + - CONTINUE_COUNTER_1_OR_EVENT : OR expression for OR event in continue Counter_1 event, + possible values are 0x0 to 0xF, + - CONTINUE_COUNTER_1_OR_VLD : Indicates which bits valid for considering OR event, + possible values are 0x0 to 0xF + * @return none + */ +STATIC INLINE void RSI_CT_ContinueEventConfig(RSI_CT_T *pCT, uint32_t andValue, uint32_t orValue) +{ + // AND Event configuration for counter continue + pCT->CT_CONTINUE_COUNTER_AND_EVENT |= andValue; + // OR Event configuration for counter continue + pCT->CT_CONTINUE_COUNTER_OR_EVENT |= orValue; +} + +/*===================================================*/ +/** + * @fn void RSI_CT_HaltEventConfig(RSI_CT_T *pCT,uint32_t andValue,uint32_t orValue) + * @brief This API is used to Configure AND/OR event for Halt operation + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] andValue : Halt Counter AND Event register value,This parameter can be the logical OR of the + - HALT_COUNTER_0_AND_EVENT : AND expression for AND event in halt Counter_0 event, + possible values are 0x0 to 0xF, + - HALT_COUNTER_0_AND_VLD : Indicates which bits valid for considering AND event, + possible values are 0x0 to 0xF + - HALT_COUNTER_1_AND_EVENT : AND expression for AND event in halt Counter_1 event, + possible values are 0x0 to 0xF, + - HALT_COUNTER_1_AND_VLD : Indicates which bits valid for considering AND event, + possible values are 0x0 to 0xF + * @param[in] orValue : Halt Counter OR Event register value + \n This parameter can be the logical OR of the + - HALT_COUNTER_0_OR_EVENT : OR expression for OR event in halt Counter_0 event, + possible values are 0x0 to 0xF, + - HALT_COUNTER_0_OR_VLD : Indicates which bits valid for considering OR event, + possible values are 0x0 to 0xF + - HALT_COUNTER_1_OR_EVENT : OR expression for OR event in halt Counter_1 event, + possible values are 0x0 to 0xF, + - HALT_COUNTER_1_OR_VLD : Indicates which bits valid for considering OR event, + possible values are 0x0 to 0xF + * @return none + */ +STATIC INLINE void RSI_CT_HaltEventConfig(RSI_CT_T *pCT, uint32_t andValue, uint32_t orValue) +{ + // AND Event configuration for counter Halt + pCT->CT_HALT_COUNTER_AND_EVENT |= andValue; + // OR Event configuration for counter Halt + pCT->CT_HALT_COUNTER_OR_EVENT |= orValue; +} + +/*===================================================*/ +/** + * @fn void RSI_CT_IncrementEventConfig(RSI_CT_T *pCT,uint32_t andValue, uint32_t orValue) + * @brief This API is used to Configure AND/OR event for increment operation + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] andValue : Increment Counter AND Event register value,this parameter can be the logical OR of the + - INCREMENT_COUNTER_0_AND_EVENT : AND expression for AND event in increment Counter_0 event, + possible values are 0x0 to 0xF, + - INCREMENT_COUNTER_0_AND_VLD : Indicates which bits valid for considering AND event, + possible values are 0x0 to 0xF + - INCREMENT_COUNTER_1_AND_EVENT : AND expression for AND event in increment Counter_1 event, + possible values are 0x0 to 0xF, + - INCREMENT_COUNTER_1_AND_VLD : Indicates which bits valid for considering AND event, + possible values are 0x0 to 0xF + * @param[in] orValue : Increment Counter OR Event register value,this parameter can be the logical OR of the + - INCREMENT_COUNTER_0_OR_EVENT : OR expression for OR event in increment Counter_0 event, + possible values are 0x0 to 0xF, + - INCREMENT_COUNTER_0_OR_VLD : Indicates which bits valid for considering OR event, + possible values are 0x0 to 0xF + - INCREMENT_COUNTER_1_OR_EVENT : OR expression for OR event in increment Counter_1 event, + possible values are 0x0 to 0xF, + - INCREMENT_COUNTER_1_OR_VLD : Indicates which bits valid for considering OR event, + possible values are 0x0 to 0xF, + * @return none + */ +STATIC INLINE void RSI_CT_IncrementEventConfig(RSI_CT_T *pCT, uint32_t andValue, uint32_t orValue) +{ + // AND Event configuration for counter Increment + pCT->CT_INCREMENT_COUNTER_AND_EVENT |= andValue; + // OR Event configuration for counter Increment + pCT->CT_INCREMENT_COUNTER_OR_EVENT |= orValue; +} + +/*===================================================*/ +/** + * @fn void RSI_CT_CaptureEventConfig(RSI_CT_T *pCT,uint32_t andValue,uint32_t orValue) + * @brief This API is used to Configure AND/OR event for capture operation + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] andValue : Capture Counter AND Event register value,This parameter can be the logical OR of the + - CAPTURE_COUNTER_0_AND_EVENT : AND expression for AND event in capture Counter_0 event, + possible values are 0x0 to 0xF, + - CAPTURE_COUNTER_0_AND_VLD : Indicates which bits valid for considering AND event, + possible values are 0x0 to 0xF + - CAPTURE_COUNTER_1_AND_EVENT : AND expression for AND event in capture Counter_1 event, + possible values are 0x0 to 0xF, + - CAPTURE_COUNTER_1_AND_VLD : Indicates which bits valid for considering AND event, + possible values are 0x0 to 0xF + * @param[in] orValue : Capture Counter OR Event register value,This parameter can be the logical OR of the + - CAPTURE_COUNTER_0_OR_EVENT : OR expression for OR event in capture Counter_0 event, + possible values are 0x0 to 0xF, + - CAPTURE_COUNTER_0_OR_VLD : Indicates which bits valid for considering OR event, + possible values are 0x0 to 0xF + - CAPTURE_COUNTER_1_OR_EVENT : OR expression for OR event in capture Counter_1 event, + possible values are 0x0 to 0xF, + - CAPTURE_COUNTER_1_OR_VLD : Indicates which bits valid for considering OR event, + possible values are 0x0 to 0xF + * @return none +*/ +STATIC INLINE void RSI_CT_CaptureEventConfig(RSI_CT_T *pCT, uint32_t andValue, uint32_t orValue) +{ + + // AND Event configuration for counter Capture + pCT->CT_CAPTURE_COUNTER_AND_EVENT |= andValue; + // OR Event configuration for counter Capture + pCT->CT_CAPTURE_COUNTER_OR_EVENT |= orValue; +} + +/*===================================================*/ +/** + * @fn void RSI_CT_InterruptEventConfig(RSI_CT_T *pCT,uint32_t andValue,uint32_t orValue) + * @brief This API is used to Configure AND/OR event for interrupt operation. + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] andValue : Interrupt Counter AND Event register value,this parameter can be the logical OR of the + - INTR_COUNTER_0_AND_EVENT : AND expression for AND event in interrupt Counter_0 event, + possible values are 0x0 to 0xF, + - INTR_COUNTER_0_AND_VLD : Indicates which bits valid for considering AND event, + possible values are 0x0 to 0xF + - INTR_COUNTER_1_AND_EVENT : AND expression for AND event in capture Counter_1 event, + possible values are 0x0 to 0xF, + - INTR_COUNTER_1_AND_VLD : Indicates which bits valid for considering AND event, + possible values are 0x0 to 0xF + * @param[in] orValue : Capture Counter OR Event register value,this parameter can be the logical OR of the + - CAPTURE_COUNTER_0_OR_EVENT : OR expression for OR event in interrupt Counter_0 event, + possible values are 0x0 to 0xF, + - CAPTURE_COUNTER_0_OR_VLD : Indicates which bits valid for considering OR event, + possible values are 0x0 to 0xF + - CAPTURE_COUNTER_1_OR_EVENT : OR expression for OR event in interrupt Counter_1 event, + possible values are 0x0 to 0xF, + - CAPTURE_COUNTER_1_OR_VLD : Indicates which bits valid for considering OR event, + possible values are 0x0 to 0xF + * @return none + */ +STATIC INLINE void RSI_CT_InterruptEventConfig(RSI_CT_T *pCT, uint32_t andValue, uint32_t orValue) +{ + // AND Event configuration for counter Interrupt + pCT->CT_INTR_AND_EVENT |= andValue; + // OR Event configuration for counter Interrupt + pCT->CT_INTR_OR_EVENT_REG |= orValue; +} + +/*===================================================*/ +/** + * @fn void RSI_CT_OutputEventConfig( RSI_CT_T *pCT,uint32_t andValue,uint32_t orValue) + * @brief This API is used to Configure AND/OR event for output operation. + * @param[in] pCT Pointer to the CT instance register area + * @param[in] andValue : Output Counter AND Event register value,this parameter can be the logical OR of the + - OUTPUT_COUNTER_0_AND_EVENT : AND expression for AND event in output Counter_0 event, + possible values are 0x0 to 0xF, + - OUTPUT_COUNTER_0_AND_VLD : Indicates which bits valid for considering AND event, + possible values are 0x0 to 0xF + - OUTPUT_COUNTER_1_AND_EVENT : AND expression for AND event in output Counter_1 event, + possible values are 0x0 to 0xF, + - OUTPUT_COUNTER_1_AND_VLD : Indicates which bits valid for considering AND event, + possible values are 0x0 to 0xF + * @param[in] orValue : Output Counter OR Event register value,this parameter can be the logical OR of the + - OUTPUT_COUNTER_0_OR_EVENT : OR expression for OR event in output Counter_0 event, + possible values are 0x0 to 0xF, + - OUTPUT_COUNTER_0_OR_VLD : Indicates which bits valid for considering OR event, + possible values are 0x0 to 0xF + - OUTPUT_COUNTER_1_OR_EVENT : OR expression for OR event in output Counter_1 event, + possible values are 0x0 to 0xF, + - OUTPUT_COUNTER_1_OR_VLD : Indicates which bits valid for considering OR event, + possible values are 0x0 to 0xF + * @return none + */ +STATIC INLINE void RSI_CT_OutputEventConfig(RSI_CT_T *pCT, uint32_t andValue, uint32_t orValue) +{ + // AND Event configuration for counter Output + pCT->CT_OUTPUT_AND_EVENT_REG |= andValue; + // OR Event configuration for counter Output + pCT->CT_OUTPUT_OR_EVENT |= orValue; +} +/*===================================================*/ +/** + * @fn void RSI_CT_StopEventSelect(RSI_CT_T *pCT,uint32_t value) + * @brief This API is used to select the input event to stop counter + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] value : Stop Event select register value,this parameter can be the logical OR of the + - STOP_EVENT_SEL_0 :event number for counter 0 + - STOP_EVENT_SEL_1 :event number for counter 1 + - possible event numbers are 1 to 38 if 0 : No event is selected + * @return none + */ +STATIC INLINE void RSI_CT_StopEventSelect(RSI_CT_T *pCT, uint32_t value) +{ + // Event number to stop + pCT->CT_STOP_COUNTER_EVENT_SEL |= value; +} + +/*===================================================*/ +/** + * @fn void RSI_CT_ContinueEventSelect(RSI_CT_T *pCT,uint32_t value) + * @brief Configures event for Continue operation of Counter + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] value : Continue Event select register value,this parameter can be the logical OR of the + - CONTINUE_EVENT_SEL_0 :event number for counter 0 + - CONTINUE_EVENT_SEL_1 :event number for counter 1 + - possible event numbers are 1 to 38 if 0 : No event is selected + * @return none + */ +STATIC INLINE void RSI_CT_ContinueEventSelect(RSI_CT_T *pCT, uint32_t value) +{ + // Event number to continue + pCT->CT_CONTINUE_COUNTER_EVENT_SEL |= value; +} + +/*===================================================*/ +/** + * @fn void RSI_CT_HaltEventSelect(RSI_CT_T *pCT,uint32_t value) + * @brief Configures event for HALT operation of Counter + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] value : Halt Event select register value,this parameter can be the logical OR of the + - HALT_EVENT_SEL_0 :event number for counter 0 + - HALT_EVENT_SEL_1 :event number for counter 1 + - possible event numbers are 1 to 38 if 0 : No event is selected + * @return none + */ +STATIC INLINE void RSI_CT_HaltEventSelect(RSI_CT_T *pCT, uint32_t value) +{ + // Event number to Halt + pCT->CT_HALT_COUNTER_EVENT_SEL |= value; +} + +/*===================================================*/ +/** + * @fn void RSI_CT_IncrementEventSelect(RSI_CT_T *pCT,uint32_t value) + * @brief Configures event for Increment operation of Counter + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] value : Increment Event select register value,this parameter can be the logical OR of the + - INCREMENT_EVENT_SEL_0 :event number for counter 0 + - INCREMENT_EVENT_SEL_1 :event number for counter 1 + - possible event numbers are 1 to 38 if 0 : No event is selected + * @return none + */ +STATIC INLINE void RSI_CT_IncrementEventSelect(RSI_CT_T *pCT, uint32_t value) +{ + // Event number to Increment + pCT->CT_INCREMENT_COUNTER_EVENT_SEL |= value; +} + +/*===================================================*/ +/** + * @fn void RSI_CT_CaptureEventSelect(RSI_CT_T *pCT,uint32_t value) + * @brief This API is used to select the input event to capture counter value + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] value : Capture Event select register value,this parameter can be the logical OR of the + - CAPTURE_EVENT_SEL_0 :event number for counter 0 + - CAPTURE_EVENT_SEL_1 :event number for counter 1 + - possible event numbers are 1 to 38 if 0 : No event is selected + * @return none + */ +STATIC INLINE void RSI_CT_CaptureEventSelect(RSI_CT_T *pCT, uint32_t value) +{ + // Event number to capture + pCT->CT_CAPTURE_COUNTER_EVENT_SEL |= value; +} + +/*===================================================*/ +/** + * @fn void RSI_CT_OutputEventSelect(RSI_CT_T *pCT,uint32_t value) + * @brief This API is used to select the input event to output counter value + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] value : Output Event select register value,this parameter can be the logical OR of the + - OUTPUT_EVENT_SEL_0 :event number for counter 0 + - OUTPUT_EVENT_SEL_1 :event number for counter 1 + - possible event numbers are 1 to 38 if 0 : No event is selected + * @return none + */ +STATIC INLINE void RSI_CT_OutputEventSelect(RSI_CT_T *pCT, uint32_t value) +{ + // Event number to output event + pCT->CT_OUTPUT_EVENT_SEL |= value; +} + +/*===================================================*/ +/** + * @fn void RSI_CT_InterruptEventSelect(RSI_CT_T *pCT,uint32_t value) + * @brief This API is used to select the input event for interrupt + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] value : Output Event select register value,this parameter can be the logical OR of the + - INTR_EVENT_SEL_0 :event number for counter 0 + - INTR_EVENT_SEL_1 :event number for counter 1 + - possible event numbers are 1 to 38 if 0 : No event is selected + * @return none + */ +STATIC INLINE void RSI_CT_InterruptEventSelect(RSI_CT_T *pCT, uint32_t value) +{ + // Event number to interrupt + pCT->CT_INTR_EVENT_SEL |= value; +} + +/*===================================================*/ +/** + * @fn void RSI_CT_OutputEventADCTrigger(RSI_CT_MUX_REG_T *pCTmux,uint8_t output1,uint8_t output2) + * @brief This API is used to select one of the ADC trigger output + * @param[in] pCTmux : Pointer to the CT instance register area + * @param[in] output1 : output event for ADC trigger (0 to 31) + * @param[in] output2 : output event for ADC trigger (0 to 31) + * @return none + */ +STATIC INLINE void RSI_CT_OutputEventADCTrigger(RSI_CT_MUX_REG_T *pCTmux, uint8_t output1, uint8_t output2) +{ + // Sets the output pin number for ADC + pCTmux->CT_OUTPUT_EVENT1_ADC_SEL_b.OUTPUT_EVENT_ADC_SEL = (unsigned int)(output1 & 0x0F); + // Sets the output pin number for ADC + pCTmux->CT_OUTPUT_EVENT2_ADC_SEL_b.OUTPUT_EVENT_ADC_SEL = (unsigned int)(output2 & 0x0F); +} + +/*===================================================*/ +/** + * @fn void RSI_CT_SetCount(RSI_CT_T *pCT, uint32_t count) + * @brief Sets the Counter Initial value. + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] count : 32 bit Counter initial value,this parameter can be the logical OR of the + - \ref COUNTER_0 : Counter 0 load value ( 0x0 to 0xFFFF) + - \ref COUNTER_1 : Counter 1 load value ( 0x0 to 0xFFFF) + - possible values are 0x0 to 0xFFFFFFFF + * @return none + */ +STATIC INLINE void RSI_CT_SetCount(RSI_CT_T *pCT, uint32_t count) +{ + // Sets the Coutner start value + pCT->CT_COUNTER_REG |= count; +} + +/*===================================================*/ +/** + * @fn void RSI_CT_OCUConfigSet(RSI_CT_T *pCT, uint32_t value) + * @brief This API is used to set OCU control parameters + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] value : OCU control register value,this parameter can be the logical OR of the below parameters + - OUTPUT_IS_OCU_0 : sets Counter 0 output in OCU mode + - SYNC_WITH_0 : Indicates whether the other channel is in sync with this counter(0,1,2,3) + - OCU_DMA_MODE_0 : OCU DMA mode is active or not for counter-0 + - OCU_8_16_MODE_0 : 16 bits or only 8-bits of the counter-0 are used in OCU mode + - OUTPUT_IS_OCU_1 : sets Counter 1 output in OCU mode + - SYNC_WITH_1 : Indicates whether the other channel is in sync with this counter(0,1,2,3) + - OCU_DMA_MODE_1 : OCU DMA mode is active or not for counter-1 + - OCU_8_16_MODE_1 : 16 bits or only 8-bits of the counter-1 are used in OCU mode + * @return none + */ +STATIC INLINE void RSI_CT_OCUConfigSet(RSI_CT_T *pCT, uint32_t value) +{ + // OCU control parameters + pCT->CT_OCU_CTRL_REG |= value; +} + +/*===================================================*/ +/** + * @fn void RSI_CT_OCUConfigReset(RSI_CT_T *pCT, uint32_t value) + * @brief This API is used to set OCU control parameters + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] value : OCU control register value,this parameter can be the logical OR required bit. + * @return none + */ +STATIC INLINE void RSI_CT_OCUConfigReset(RSI_CT_T *pCT, uint32_t value) +{ + // OCU control parameters + pCT->CT_OCU_CTRL_REG &= ~(value); +} + +/*===================================================*/ +/** + * @fn void RSI_CT_InterruptEnable(RSI_CT_T *pCT, uint32_t unmaskFlags) + * @brief Enable the interrupts in State Configurable Timer. + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] unmaskFlags : CT Interrupt unmask register value,this parameter can be the logical OR of the + - INTR_0_l : interrupt event flag for counter 0 + - COUNTER_0_IS_ZERO_L : counter hit zero for counter 0 + - COUNTER_0_IS_PEAK_L : counter hit peak for counter 0 + - INTR_1_L : interrupt event flag for counter 1 + - COUNTER_0_IS_ZERO_L : counter hit zero for counter 1 + - COUNTER_0_IS_PEAK_L : counter hit peak for counter 1 + * @return none + */ +STATIC INLINE void RSI_CT_InterruptEnable(RSI_CT_T *pCT, uint32_t unmaskFlags) +{ + // multi channel VIC enable + M4SS_CT_INTR_SEL = 0xFFFFFFFF; + + // unmasks required interrupt flags + pCT->CT_INTER_UNMASK = unmaskFlags; +} + +/*===================================================*/ +/** + * @fn void RSI_CT_InterruptDisable(RSI_CT_T *pCT, uint32_t maskFlags) + * @brief Disable the interrupts in State Configurable Timer + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] maskFlags : CT Interrupt mask register value,this parameter can be the logical OR of the + - INTR_0_l : interrupt event flag for counter 0 + - COUNTER_0_IS_ZERO_L : counter hit zero for counter 0 + - COUNTER_0_IS_PEAK_L : counter hit peak for counter 0 + - INTR_1_L : interrupt event flag for counter 1 + - COUNTER_0_IS_ZERO_L : counter hit zero for counter 1 + - COUNTER_0_IS_PEAK_L : counter hit peak for counter 1 + * @return none + */ +STATIC INLINE void RSI_CT_InterruptDisable(RSI_CT_T *pCT, uint32_t maskFlags) +{ + // unmasks required interrupt flags + pCT->CT_INTR_MASK = maskFlags; +} + +/*===================================================*/ +/** + * @fn void RSI_CT_InterruptClear(RSI_CT_T *pCT,uint32_t clr_flags) + * @brief Clear the specified interrupt flag in State Configurable Timer + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] clr_flags : CT Interrupt Ack register value,this parameter can be the logical OR of the + - INTR_0_l : interrupt event flag for counter 0 + - COUNTER_0_IS_ZERO_L : counter hit zero for counter 0 + - COUNTER_0_IS_PEAK_L : counter hit peak for counter 0 + - INTR_1_L : interrupt event flag for counter 1 + - COUNTER_0_IS_ZERO_L : counter hit zero for counter 1 + - COUNTER_0_IS_PEAK_L : counter hit peak for counter 1 + * @return none + */ +STATIC INLINE void RSI_CT_InterruptClear(RSI_CT_T *pCT, uint32_t clrFlags) +{ + // Clears required interrupt flags + pCT->CT_INTR_ACK = clrFlags; +} + +/*===================================================*/ +/** + * @fn uint32_t RSI_CT_GetInterruptStatus(RSI_CT_T *pCT) + * @brief Clear the specified interrupt flag in State Configurable Timer + * @param[in] pCT : Pointer to the CT instance register area + * @return CT Interrupt status value + */ +STATIC INLINE uint32_t RSI_CT_GetInterruptStatus(RSI_CT_T *pCT) +{ + return (pCT->CT_INTR_STS); +} + +/*===================================================*/ +/** + * @fn void RSI_CT_EdgeLevelEventControl(RSI_CT_T *pCT,uint32_t value) + * @brief This API is used to control the input event generation to CT + * @param[in] pSCT : Pointer to the SCT instance register area + * @param[in] value : Mask value + * @return none + */ +STATIC INLINE void RSI_CT_EdgeLevelEventControl(RSI_CT_T *pCT, uint32_t value) +{ + //pCT ->RE_FE_RFE_LEV0_LEV1_EVENT_ENABLE_REG = value; + (void)pCT; + (void)value; +} + +/*===================================================*/ +/** + * @fn void RSI_CT_SetTimerMuxSelect( RSI_CT_MUX_REG_T *pCTMux,uint8_t timerIns ) + * @brief To Select Timer using mux. + * @param[in] pCTMux : Pointer to the CT Mux instance register area + * @param[in] timerIns : If 0 - Timer0 instance,if 1 - Timer1 instance + * @return none + */ +STATIC INLINE void RSI_CT_SetTimerMuxSelect(RSI_CT_MUX_REG_T *pCTMux, uint8_t timerIns) +{ + pCTMux->CT_MUX_SEL_0_REG = timerIns; + pCTMux->CT_MUX_SEL_1_REG = timerIns; +} + +/*===================================================*/ +/** + * @fn void RSI_CT_ResumeHaltEvent(RSI_CT_T *pCT,boolean_t counterNum) + * @brief To Resume the HALT operation of counter with I/O events + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] counterNum : Counter 0/1 + * @return none + */ +STATIC INLINE void RSI_CT_ResumeHaltEvent(RSI_CT_T *pCT, boolean_t counterNum) +{ + if (counterNum) { + pCT->CT_HALT_COUNTER_EVENT_SEL_b.RESUME_FROM_HALT_COUNTER_1 = 0x1; + } else { + pCT->CT_HALT_COUNTER_EVENT_SEL_b.RESUME_FROM_HALT_COUNTER_0 = 0x1; + } +} + +/*===================================================*/ +/** + * @fn rsi_error_t RSI_CT_PeripheralReset(RSI_CT_T *pCT,boolean_t counterNum) + * @brief This API is used to Reset any counter. + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] counterNum : Counter 0/1 + * @return none + */ +STATIC INLINE void RSI_CT_PeripheralReset(RSI_CT_T *pCT, boolean_t counterNum) +{ + if (counterNum) { + // Counter 1 reset + pCT->CT_GEN_CTRL_SET_REG = (1 << 17); + } else { + // Counter 0 reset + pCT->CT_GEN_CTRL_SET_REG = (1 << 1); + } +} + +/*===================================================*/ +/** + * @fn rsi_error_t RSI_CT_StartSoftwareTrig(RSI_CT_T *pCT,boolean_t counterNum) + * @brief Starts the Counter form software register + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] counterNum : Coutner 0/1 + * @return none + */ +STATIC INLINE void RSI_CT_StartSoftwareTrig(RSI_CT_T *pCT, boolean_t counterNum) +{ + // starts the required counter */ + if (counterNum) { + pCT->CT_GEN_CTRL_SET_REG = (1 << 19); + } else { + pCT->CT_GEN_CTRL_SET_REG = (1 << 3); + } +} + +/*===================================================*/ +/** + * @fn rsi_error_t RSI_CT_OCUModeSet(RSI_CT_T *pCT, boolean_t counterNum) + * @brief OCU mode configuration setting + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] counterNum : Coutner 0/1 + * @return none + */ +STATIC INLINE void RSI_CT_OCUModeSet(RSI_CT_T *pCT, boolean_t counterNum) +{ + if (counterNum) { + // set the output in OCU mode for counter 1 + pCT->CT_OCU_CTRL_REG_b.OUTPUT_1_IS_OCU = 1; + } else { + // set the output in OCU mode for counter 0 + pCT->CT_OCU_CTRL_REG_b.OUTPUT_IS_OCU_0 = 1; + } +} + +/*===================================================*/ +/** + * @fn void RSI_CT_SetMatchCount(RSI_CT_T *pCT, uint32_t value,boolean_t counterMode, boolean_t counterNum) + * @brief Sets the Match load value for counter 0 and counter 1 + * @param[in] pCT : Pointer to the SCT instance register area + * @param[in] value : Match register or match buffer register value,this parameter + \n can be the logical OR of the + - COUNTER_0_MATCH : Counter 0 match value ( 0x0 to 0xFFFF) + - COUNTER_1_MATCH : Counter 1 match value ( 0x0 to 0xFFFF) + * @param[in] counterMode : counterMode 0/1 + * @param[in] counterNum : Counter 0/1 + * @return none + */ +STATIC INLINE void RSI_CT_SetMatchCount(RSI_CT_T *pCT, uint32_t value, boolean_t counterMode, boolean_t counterNum) +{ + if (counterMode == 0) { + if (counterNum) { + + pCT->CT_MATCH_REG_b.COUNTER_1_MATCH = (uint16_t)value; + } else { + pCT->CT_MATCH_REG_b.COUNTER_0_MATCH = (uint16_t)value; + } + } else { + pCT->CT_MATCH_REG = (uint16_t)value; + } +} + +/*===================================================*/ +/** + * @fn uint16_t RSI_CT_CaptureRead(RSI_CT_T *pCT, boolean_t counterNum) + * @brief Gets the captured counter value + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] counterNum : Counter 0/1 + * @return Return counter value at the time of capture event occurs + */ +STATIC INLINE uint16_t RSI_CT_CaptureRead(RSI_CT_T *pCT, boolean_t counterNum) +{ + if (counterNum) { + return (pCT->CT_CAPTURE_REG_b.COUNTER_1_CAPTURE); + } else { + return (pCT->CT_CAPTURE_REG_b.COUNTER_0_CAPTURE); + } +} + +/*===================================================*/ +/** + * @fn uint32_t RSI_CT_GetCounter( RSI_CT_T *pCT,boolean_t counterNum,boolean_t mode ) + * @brief Gets the captured counter value + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] counterNum : Counter 0/1 + * @param[in] mode : mode 0/1 + * @return Return the counter value + */ +STATIC INLINE uint32_t RSI_CT_GetCounter(RSI_CT_T *pCT, boolean_t counterNum, boolean_t mode) +{ + if (mode) { + return (pCT->CT_COUNTER_REG); + } else { + if (counterNum) { + return (pCT->CT_COUNTER_REG_b.COUNTER1); + } else { + return (pCT->CT_COUNTER_REG_b.COUNTER0); + } + } +} + +/*===================================================*/ +/** + * @fn void RSI_CT_SetCounerSync( RSI_CT_T *pCT, uint8_t syncCounter,boolean_t counterNum) + * @brief Sets the captured counter value. + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] syncCounter : set the counter number to be in sync + * @param[in] counterNum : Counter 0/1 + * @return none + */ +STATIC INLINE void RSI_CT_SetCounerSync(RSI_CT_T *pCT, uint8_t syncCounter, boolean_t counterNum) +{ + if (counterNum) { + pCT->CT_OCU_CTRL_REG_b.SYNC_WITH_1 = (unsigned int)(syncCounter & 0x07); + } else { + pCT->CT_OCU_CTRL_REG_b.SYNC_WITH_0 = (unsigned int)(syncCounter & 0x07); + } +} + +// CT FUNCTION PROTOTYPES +void RSI_CT_Init(void); +void ct_ocu_high_Low_toggle_select(RSI_CT_T *pCT, boolean_t lowHigh, boolean_t counterNum, uint8_t outputSel); + +rsi_error_t ct_ocu_control(RSI_CT_T *pCT, + boolean_t counterNum, + boolean_t dmaEn, + OCU_PARAMS_T *pOCUparams, + RSI_CT_CALLBACK_T *pCB); + +rsi_error_t ct_wfg_control_config(RSI_CT_T *pCT, WFG_PARAMS_T ctrlReg); + +rsi_error_t ct_wfg_comapre_value_set(RSI_CT_T *pCT, boolean_t counterNum, OCU_PARAMS_T *pOCUparams); + +#ifdef __cplusplus +} +#endif + +#endif // RSI_CT_H diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_efuse.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_efuse.h new file mode 100644 index 000000000..b4fe7250b --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_efuse.h @@ -0,0 +1,120 @@ +/******************************************************************************* +* @file rsi_efuse.h +* @brief +******************************************************************************* +* # License +* Copyright 2022 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +// Includes Files + +#include "rsi_ccp_common.h" +#include "base_types.h" +#include "rsi_error.h" + +#ifndef RSI_EFUSE_H +#define RSI_EFUSE_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define TA_EFUSE_BASE_ADDR 0x40010000 +#define M4_EFUSE_BASE_ADDR 0x4600C000 + +#define TA_EFUSE_IO_BASE_ADDR (TA_EFUSE_BASE_ADDR + 0x2000) +#define M4_EFUSE_IO_BASE_ADDR (M4_EFUSE_BASE_ADDR + 0x2000) + +#define EFUSE_DA_ADDR_REG_OFFSET 0x00 +#define EFUSE_DA_CTRL_SET_REG_OFFSET 0x04 +#define EFUSE_DA_CTRL_CLEAR_REG_OFFSET 0x08 +#define EFUSE_CTRL_REG_OFFSET 0x0C +#define EFUSE_READ_ADDR_REG_OFFSET 0x10 +#define EFUSE_READ_DATA_REG_OFFSET 0x14 +#define EFUSE_STATUS_REG_OFFSET 0x18 +#define EFUSE_RD_TMNG_PARAM_REG_OFFSET 0x1C +#define EFUSE_DA_ADDR_REG_DEFAULT_OFFSET 0x2C +#define EFUSE_MEM_MAP_LENGTH_OFFSET 0x24 +#define EFUSE_DA_CLR_STROBE_REG_OFFSET 0x34 +#define EFUSE_CLK_ENABLE_SET_REG2_OFFSET 0x38 +#define EFUSE_CLK_ENABLE_CLEAR_REG2_OFFSET 0x3C + +#define TA_EFUSE_DA_ADDR_REG (*((uint16_t volatile *)(TA_EFUSE_BASE_ADDR + EFUSE_DA_ADDR_REG_OFFSET))) +#define TA_EFUSE_DA_CTRL_SET_REG (*((uint16_t volatile *)(TA_EFUSE_BASE_ADDR + EFUSE_DA_CTRL_SET_REG_OFFSET))) +#define TA_EFUSE_DA_CTRL_CLEAR_REG (*((uint16_t volatile *)(TA_EFUSE_BASE_ADDR + EFUSE_DA_CTRL_CLEAR_REG_OFFSET))) +#define TA_EFUSE_CTRL_REG (*((uint16_t volatile *)(TA_EFUSE_BASE_ADDR + EFUSE_CTRL_REG_OFFSET))) +#define TA_EFUSE_READ_ADDR_REG (*((uint16_t volatile *)(TA_EFUSE_BASE_ADDR + EFUSE_READ_ADDR_REG_OFFSET))) +#define TA_EFUSE_READ_DATA_REG (*((uint16_t volatile *)(TA_EFUSE_BASE_ADDR + EFUSE_READ_DATA_REG_OFFSET))) +#define TA_EFUSE_STATUS_REG (*((uint16_t volatile *)(TA_EFUSE_BASE_ADDR + EFUSE_STATUS_REG_OFFSET))) +#define TA_EFUSE_RD_TMNG_PARAM_REG (*((uint16_t volatile *)(TA_EFUSE_BASE_ADDR + EFUSE_RD_TMNG_PARAM_REG_OFFSET))) +#define TA_EFUSE_DA_ADDR_REG_DEFAULT (*((uint16_t volatile *)(TA_EFUSE_BASE_ADDR + EFUSE_DA_ADDR_REG_DEFAULT_OFFSET))) +#define TA_EFUSE_MEM_MAP_LENGTH (*((uint16_t volatile *)(TA_EFUSE_BASE_ADDR + EFUSE_MEM_MAP_LENGTH_OFFSET))) +#define TA_EFUSE_DA_CLR_STROBE_REG (*((uint16_t volatile *)(TA_EFUSE_BASE_ADDR + EFUSE_DA_CLR_STROBE_REG_OFFSET))) + +#define M4_EFUSE_DA_ADDR_REG (*((uint16_t volatile *)(M4_EFUSE_BASE_ADDR + EFUSE_DA_ADDR_REG_OFFSET))) +#define M4_EFUSE_DA_CTRL_SET_REG (*((uint16_t volatile *)(M4_EFUSE_BASE_ADDR + EFUSE_DA_CTRL_SET_REG_OFFSET))) +#define M4_EFUSE_DA_CTRL_CLEAR_REG (*((uint16_t volatile *)(M4_EFUSE_BASE_ADDR + EFUSE_DA_CTRL_CLEAR_REG_OFFSET))) +#define M4_EFUSE_CTRL_REG (*((uint16_t volatile *)(M4_EFUSE_BASE_ADDR + EFUSE_CTRL_REG_OFFSET))) +#define M4_EFUSE_READ_ADDR_REG (*((uint16_t volatile *)(M4_EFUSE_BASE_ADDR + EFUSE_READ_ADDR_REG_OFFSET))) +#define M4_EFUSE_READ_DATA_REG (*((uint16_t volatile *)(M4_EFUSE_BASE_ADDR + EFUSE_READ_DATA_REG_OFFSET))) +#define M4_EFUSE_STATUS_REG (*((uint16_t volatile *)(M4_EFUSE_BASE_ADDR + EFUSE_STATUS_REG_OFFSET))) +#define M4_EFUSE_RD_TMNG_PARAM_REG (*((uint16_t volatile *)(M4_EFUSE_BASE_ADDR + EFUSE_RD_TMNG_PARAM_REG_OFFSET))) +#define M4_EFUSE_DA_ADDR_REG_DEFAULT (*((uint16_t volatile *)(M4_EFUSE_BASE_ADDR + EFUSE_DA_ADDR_REG_DEFAULT_OFFSET))) +#define M4_EFUSE_MEM_MAP_LENGTH (*((uint16_t volatile *)(M4_EFUSE_BASE_ADDR + EFUSE_MEM_MAP_LENGTH_OFFSET))) +#define M4_EFUSE_DA_CLR_STROBE_REG (*((uint16_t volatile *)(M4_EFUSE_BASE_ADDR + EFUSE_DA_CLR_STROBE_REG_OFFSET))) + +#define EFUSE_CLK_BIT BIT(5) +#define EFUSE_PCLK_BIT BIT(19) +#define M4SS_CLK_ENABLE_SET_3_REG (*((volatile uint32_t *)(M4SS_CLK_PWR_CTRL_BASE_ADDR + 0x10))) + +// EFUSE_DA_CTRL_SET_REG +#define SET_LOAD_ENABLE BIT(3) +#define SET_CHIP_ENABLE BIT(1) +#define SET_PROGRAM_ENABLE BIT(0) + +#define READ_FSM_DONE BIT(15) + +// Address range for 32x8 eFUSE for M4SS +#define ADDRESS_MIN 0x00 // Start address +#define ADDRESS_MAX 0x31 // End address + +// Bit Positions range +#define BIT_POS_MIN 0x00 // Min Bit position +#define BIT_POS_MAX 0x07 // Max bit position + +void efuse_enable(EFUSE_Type *pstcEfuse); + +void efuse_Disable(EFUSE_Type *pstcEfuse); + +uint8_t efuse_read_data(EFUSE_Type *pstcEfuse); + +void efuse_write_addr(EFUSE_Type *pstcEfuse, uint16_t u16Addr); + +rsi_error_t efuse_get_addr(EFUSE_Type *pstcEfuse, uint16_t *u16AddrVal); + +rsi_error_t efuse_write_bit(EFUSE_Type *pstcEfuse, uint16_t u16Addr, uint8_t u8BitPos, uint32_t hold_time); + +rsi_error_t efuse_fsm_read_byte(EFUSE_Type *pstcEfuse, uint16_t u16Addr, uint8_t *pu8Byte, uint32_t SocClk); + +rsi_error_t efuse_mem_map_read_byte(EFUSE_Type *pstcEfuse, uint16_t u16Addr, uint8_t *pu8Byte, uint32_t SocClk); + +rsi_error_t efuse_mem_map_read_word(EFUSE_Type *pstcEfuse, uint16_t u16Addr, uint16_t *pu16Word, uint32_t SocClk); + +rsi_error_t efuse_direct_read_byte(EFUSE_Type *pstcEfuse, uint16_t u16Addr, uint8_t *pu8Byte, uint32_t hold_time); + +void efuse_write_address(EFUSE_Type *pstcEfuse, uint16_t u16Addr); + +#ifdef __cplusplus +} +#endif + +#endif // RSI_EFUSE_H diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_egpio.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_egpio.h new file mode 100644 index 000000000..47dad87e1 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_egpio.h @@ -0,0 +1,308 @@ +/******************************************************************************* +* @file rsi_egpio.h +* @brief +******************************************************************************* +* # License +* Copyright 2022 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +// Includes Files + +#include "rsi_ccp_common.h" +#include "base_types.h" + +#ifndef RSI_EGPIO_H +#define RSI_EGPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +// EGPIO numbers +#define GPIO0 0 // EGPIO number 0 +#define GPIO1 1 // EGPIO number 1 +#define GPIO2 2 // EGPIO number 2 +#define GPIO3 3 // EGPIO number 3 +#define GPIO4 4 // EGPIO number 4 +#define GPIO5 5 // EGPIO number 5 +#define GPIO6 6 // EGPIO number 6 +#define GPIO7 7 // EGPIO number 7 +#define GPIO8 8 // EGPIO number 8 +#define GPIO9 9 // EGPIO number 9 +#define GPIO10 10 // EGPIO number 10 +#define GPIO11 11 // EGPIO number 11 +#define GPIO12 12 // EGPIO number 12 +#define GPIO13 13 // EGPIO number 13 +#define GPIO14 14 // EGPIO number 14 +#define GPIO15 15 // EGPIO number 14 + +// EGPIO Ports(NOTE : Each ports consists of 16 GPIO pins numbered from (0 - 15)) +#define EGPIO_PORT0 0 // EGPIO port number 0 +#define EGPIO_PORT1 1 // EGPIO port number 1 +#define EGPIO_PORT2 2 // EGPIO port number 2 + +// EGPIO PIN INTERRUPTS +// NOTE : Total 8 pin interrupts are supported , these interrupts can be mapped to any of the GPIO ports +#define EGPIO_PIN_INTERRUPT0 0 // Select interrupt channel 0 +#define EGPIO_PIN_INTERRUPT1 1 // Select interrupt channel 1 +#define EGPIO_PIN_INTERRUPT2 2 // Select interrupt channel 2 +#define EGPIO_PIN_INTERRUPT3 3 // Select interrupt channel 3 +#define EGPIO_PIN_INTERRUPT4 4 // Select interrupt channel 4 +#define EGPIO_PIN_INTERRUPT5 5 // Select interrupt channel 5 +#define EGPIO_PIN_INTERRUPT6 6 // Select interrupt channel 6 +#define EGPIO_PIN_INTERRUPT7 7 // Select interrupt channel 7 + +// EGPIO GROUP INTERUPTS +// NOTE : Total 2 group interrupts are supported +#define EGPIO_GROUP_INTERRUPT0 0 // Select EGPIO Group interrupt channel 0 +#define EGPIO_GROUP_INTERRUPT1 1 // Select EGPIO Group interrupt channel 1 + +// Pin multiplexing +// NOTE : Each GPIO supports up to 8 multiplexing functions those can be selected by passing following macros into the pin mux function +#define EGPIO_PIN_MUX_MODE0 0U // Select pin mode 0 +#define EGPIO_PIN_MUX_MODE1 1U // Select pin mode 1 +#define EGPIO_PIN_MUX_MODE2 2U // Select pin mode 2 +#define EGPIO_PIN_MUX_MODE3 3U // Select pin mode 3 +#define EGPIO_PIN_MUX_MODE4 4U // Select pin mode 4 +#define EGPIO_PIN_MUX_MODE5 5U // Select pin mode 5 +#define EGPIO_PIN_MUX_MODE6 6U // Select pin mode 6 +#define EGPIO_PIN_MUX_MODE7 7U // Select pin mode 7 +#define EGPIO_PIN_MUX_MODE8 8U // Select pin mode 8 +#define EGPIO_PIN_MUX_MODE9 9U // Select pin mode 9 +#define EGPIO_PIN_MUX_MODE10 10U // Select pin mode 10 +#define EGPIO_PIN_MUX_MODE11 11U // Select pin mode 11 +#define EGPIO_PIN_MUX_MODE12 12U // Select pin function 12 +#define EGPIO_PIN_MUX_MODE13 13U // Select pin function 13 +#define EGPIO_PIN_MUX_MODE14 14U // Select pin function 14 +#define EGPIO_PIN_MUX_MODE15 15U // Select pin function 15 + +// interrupt clear flags +#define EGPIO_PIN_INT_CLR_FALLING BIT(2) // Falling edge interrupt clear +#define EGPIO_PIN_INT_CLR_RISING BIT(1) // Raising edge interrupt clear +#define INTERRUPT_STATUS_CLR BIT(0) // interrupts are cleared +#define WAKEUP_INTERRUPT BIT(1) + +// GPIO directions +#define EGPIO_CONFIG_DIR_INPUT 1U // Configure EGPIO as input mode +#define EGPIO_CONFIG_DIR_OUTPUT 0U // Configure EGPIO as output mode +#define NWPAON_MEM_HOST_ACCESS_CTRL_CLEAR (0x41300000 + 0x004) + +// MISC host +#define MISC_HOST (*(volatile uint32_t *)(0x46008000 + 0x0C)) + +// m4 PAD configuration defines + +#define PAD_CONFIG_REG(x) (*(volatile uint32_t *)(0x46004000 + 4 * x)) // REN enable bit(this should be enable) +#define PADSELECTION \ + (*(volatile uint32_t *)(0x41300000 + 0x610)) // PAD selection (0 t0 21) A value of 1 on this gives control to M4SS + +#ifdef SLI_SI917 +#define PADSELECTION_1 \ + (*(volatile uint32_t *)(0x41300000 + 0x618)) // PAD selection (22 to 33) A value of 1 on this gives control to M4SS +#endif +#define SDIO_CNTD_TO_TASS \ + (*(volatile uint32_t *)NWPAON_MEM_HOST_ACCESS_CTRL_CLEAR) // sdio connected to tass (0 for M4SS and 1 for TASS) + +// Ulp pad configuration defines +#define ULP_PAD_CONFIG_REG_0 (*(volatile uint32_t *)(0x2404A000 + 0x0)) +#define ULP_PAD_CONFIG_REG_1 (*(volatile uint32_t *)(0x2404A000 + 0x4)) +#define ULP_PAD_CONFIG_REG_2 (*(volatile uint32_t *)(0x2404A000 + 0x8)) + +// ulp_socgpio_n_mode +#define ULP_SOC_GPIO_MODE(x) (*(volatile uint32_t *)(0x24041400 + 4 * x)) // x= 0 to 15 + +// MISC host + +#define HOST_PADS_GPIO_MODE (*(volatile uint32_t *)(0x46008000 + 0x44)) + +// Ulp Ren enable +#define CLOCK_ENABLE (*(uint32_t *)(0x24041400 + 0x00)) + +typedef enum en_driver_state { + HiZ = 0, // 0 for HiZ (P1=0,P2=0) + Pullup = 1, // 1 for Pullup (P1=0,P2=1) + Pulldown = 2, // 2 for Pulldown (P1=1,P2=0) + Repeater = 3 // 3 for Repeater (P1=1,P2=1) +} en_driver_state_t; +typedef enum en_driver_strength_select { + two_milli_amps = 0, // 0 for two_milli_amps (E1=0,E2=0) + four_milli_amps = 1, // 1 for four_milli_amps (E1=0,E2=1) + eight_milli_amps = 2, // 2 for eight_milli_amps (E1=1,E2=0) + twelve_milli_amps = 3 // 3 for twelve_milli_amps(E1=1,E2=1) +} en_driver_strength_select_t; + +#define DDS_MASK 0xC0 // driver disabled state +#define DSS_MASK 0x3 // driver strength select +#define POS_MASK 0x4 // power on start +#define ST_MASK 0x8 // active high schmitt trigger +#define RE_MASK 0x10 // receiver enable +#define SR_MASK 0x20 // slew rate + +#define ULP_DDS_MASK_SET_1_AND_3 0xC0 // driver disabled state +#define ULP_DDS_MASK_SET_2_AND_4 0xC000 // driver disabled state +#define ULP_DSS_MASK_SET_1_AND_3 0x3 // driver strength select +#define ULP_DSS_MASK_SET_2_AND_4 0x300 // driver strength select +#define ULP_POS_MASK_SET_1_AND_3 0x4 // power on start +#define ULP_POS_MASK_SET_2_AND_4 0x400 // power on start +#define ULP_ST_MASK_SET_1_AND_3 0x8 // active high schmitt trigger +#define ULP_ST_MASK_SET_2_AND_4 0x800 // active high schmitt trigger +#define ULP_SR_MASK_SET_1_AND_3 0x20 // slew rate +#define ULP_SR_MASK_SET_2_AND_4 0x2000 // slew rate + +typedef enum en_ulp_driver_disable_state { + ulp_HiZ = 0, // 0 for HiZ (P1=0,P2=0) + ulp_Pullup = 1, // 1 for Pullup (P1=0,P2=1) + ulp_Pulldown = 2, // 2 for Pulldown (P1=1,P2=0) + ulp_Repeater = 3 // 3 for Repeater (P1=1,P2=1) +} en_ulp_driver_disable_state_t; +typedef enum en_ulp_driver_strength_select { + ulp_two_milli_amps = 0, // 0 for two_milli_amps (E1=0,E2=0) + ulp_four_milli_amps = 1, // 1 for four_milli_amps (E1=0,E2=1) + ulp_eight_milli_amps = 2, // 2 for eight_milli_amps (E1=1,E2=0) + ulp_twelve_milli_amps = 3 // 3 for twelve_milli_amps(E1=1,E2=1) +} en_ulp_driver_strength_select_t; + +void egpio_set_dir(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin, boolean_t dir); + +void egpio_set_pin(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin, uint8_t val); + +boolean_t egpio_get_pin(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); + +boolean_t egpio_get_dir(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); + +void egpio_pin_int_sel(EGPIO_Type *pEGPIO, uint8_t intCh, uint8_t port, uint8_t pin); + +void egpio_set_int_fall_edge_enable(EGPIO_Type *pEGPIO, uint8_t intCh); + +void egpio_set_int_fall_edge_disable(EGPIO_Type *pEGPIO, uint8_t intCh); + +void egpio_set_int_rise_edge_enable(EGPIO_Type *pEGPIO, uint8_t intCh); + +void egpio_set_int_rise_edge_disable(EGPIO_Type *pEGPIO, uint8_t intCh); + +void egpio_set_int_low_level_enable(EGPIO_Type *pEGPIO, uint8_t intCh); + +void egpio_int_mask(EGPIO_Type *pEGPIO, uint8_t intCh); + +void egpio_int_un_mask(EGPIO_Type *pEGPIO, uint8_t intCh); + +void egpio_set_int_low_level_disable(EGPIO_Type *pEGPIO, uint8_t intCh); + +void egpio_set_int_high_level_enable(EGPIO_Type *pEGPIO, uint8_t intCh); + +void egpio_set_int_high_level_disable(EGPIO_Type *pEGPIO, uint8_t intCh); + +uint8_t egpio_get_int_stat(EGPIO_Type *pEGPIO, uint8_t intCh); + +void egpio_int_clr(EGPIO_Type *pEGPIO, uint8_t intCh, uint8_t flags); + +void egpio_set_pin_mux(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin, uint8_t u8Mux); + +void egpio_ulp_soc_gpio_mode(ULPCLK_Type *pULPCLK, uint8_t gpio, uint8_t mode); + +void egpio_set_port_mask(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); + +void egpio_set_port_un_mask(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); + +void egpio_port_masked_load(EGPIO_Type *pEGPIO, uint8_t port, uint16_t u16Val); + +void egpio_set_port(EGPIO_Type *pEGPIO, uint8_t port, uint16_t val); + +void egpio_port_load(EGPIO_Type *pEGPIO, uint8_t port, uint16_t val); + +void egpio_word_load(EGPIO_Type *pEGPIO, uint8_t pin, uint16_t val); + +void egpio_clr_port(EGPIO_Type *pEGPIO, uint8_t port, uint16_t val); + +void egpio_toggle_port(EGPIO_Type *pEGPIO, uint8_t port, uint16_t val); + +uint16_t egpio_get_port(EGPIO_Type *pEGPIO, uint8_t port); + +void egpio_group_int_one_enable(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); + +void egpio_group_int_one_disable(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); + +void egpio_group_int_two_enable(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); + +void egpio_group_int_mask(EGPIO_Type *pEGPIO, uint8_t grpInt); + +void egpio_group_int_un_Mask(EGPIO_Type *pEGPIO, uint8_t grpInt); + +void egpio_group_int_enable(EGPIO_Type *pEGPIO, uint8_t grpInt); + +void egpio_group_int_disable(EGPIO_Type *pEGPIO, uint8_t grpInt); + +void egpio_group_int_level(EGPIO_Type *pEGPIO, uint8_t grpInt); + +void egpio_group_int_edge(EGPIO_Type *pEGPIO, uint8_t grpInt); + +void egpio_group_int_and(EGPIO_Type *pEGPIO, uint8_t grpInt); + +void egpio_group_int_or(EGPIO_Type *pEGPIO, uint8_t grpInt); + +uint32_t egpio_group_int_stat(EGPIO_Type *pEGPIO, uint8_t grpInt); + +void egpio_group_int_wkeup_Enable(EGPIO_Type *pEGPIO, uint8_t grpInt); + +void egpio_group_int_wkeup_disable(EGPIO_Type *pEGPIO, uint8_t grpInt); + +void egpio_group_int_clr(EGPIO_Type *pEGPIO, uint8_t grpInt, uint8_t u8ClrFlags); + +void egpio_group_int_two_disable(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); + +void egpio_set_group_int_one_pol(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin, uint8_t pol); + +void egpio_set_group_int_two_pol(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin, uint8_t pol); + +void egpio_host_pads_gpio_mode_enable(uint8_t u8GpioNum); + +void egpio_host_pads_gpio_mode_disable(uint8_t u8GpioNum); + +void egpio_pad_selection_enable(uint8_t padNum); + +void egpio_pad_selection_disable(uint8_t padNum); + +void egpio_pad_receiver_enable(uint8_t u8GpioNum); + +void egpio_pad_receiver_disable(uint8_t u8GpioNum); + +void egpio_pad_sdio_connected(void); + +void egpio_pad_driver_disable_state(uint8_t u8GpioNum, en_driver_state_t endstate); + +void egpio_pad_driver_strength_select(uint8_t u8GpioNum, en_driver_strength_select_t strength); + +void egpio_pad_power_on_start_enable(uint8_t u8GpioNum, uint8_t val); + +void egpio_pad_active_high_schmitt_trigger(uint8_t u8GpioNum, uint8_t val); + +void egpio_pad_slew_rate_controll(uint8_t u8GpioNum, uint8_t val); + +void egpio_ulp_pad_receiver_enable(uint8_t gpio); + +void egpio_ulp_pad_receiver_disable(uint8_t u8GpioNum); + +void egpio_ulp_pad_driver_disable_state(uint8_t u8GpioNum, en_ulp_driver_disable_state_t disablestate); + +void egpio_ulp_pad_driver_strength_select(uint8_t u8GpioNum, en_ulp_driver_strength_select_t strength); + +void egpio_ulp_pad_power_on_start_enable(uint8_t u8GpioNum, uint8_t val); + +void egpio_ulp_pad_active_high_schmitt_trigger(uint8_t u8GpioNum, uint8_t val); + +void egpio_ulp_pad_slew_rate_controll(uint8_t u8GpioNum, uint8_t val); + +#ifdef __cplusplus +} +#endif + +#endif // RSI_EGPIO_H diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_gpdma.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_gpdma.h new file mode 100644 index 000000000..2f2df2a37 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_gpdma.h @@ -0,0 +1,490 @@ +/******************************************************************************* +* @file rsi_gpdma.h +* @brief +******************************************************************************* +* # License +* Copyright 2022 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +// Includes Files + +#include "rsi_ccp_common.h" +#include "base_types.h" +#include "rsi_error.h" +#include "rsi_packing.h" + +#ifndef RSI_GPDMA_H +#define RSI_GPDMA_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define RSI_GPDMA_API_VERSION RSI_DRIVER_VERSION_MAJOR_MINOR(02, 00) // API version +#define RSI_GPDMA_DRV_VERSION RSI_DRIVER_VERSION_MAJOR_MINOR(00, 01) // driver version + +#define GPDMA_CHANNEL_NUM 7 + +// GPDMA Status Flags +#define GPDMA_STAT_HRESP_ERROR0 (1UL << 0) // Channel0 dma error +#define GPDMA_STAT_LINK_LIST_DONE0 (1UL << 1) // Channel0 link list fetch done status +#define GPDMA_STAT_PHRL_END_OF_XFER0 (1UL << 2) // Channel0 transfer done status +#define GPDMA_STAT_GPDMAC_ERROR0 (1UL << 3) // Channel0 Transfer size/burst size /h size mismatch/flow ctrl err status +#define GPDMA_STAT_HRESP_ERROR1 (1UL << 4) // Channel1 dma error +#define GPDMA_STAT_LINK_LIST_DONE1 (1UL << 5) // Channel1 link list fetch done status +#define GPDMA_STAT_PHRL_END_OF_XFER1 (1UL << 6) // Channel1 transfer done status +#define GPDMA_STAT_GPDMAC_ERROR1 (1UL << 7) // Channel1 Transfer size/burst size /h size mismatch/flow ctrl err status +#define GPDMA_STAT_HRESP_ERROR2 (1UL << 8) // Channel2 dma error +#define GPDMA_STAT_LINK_LIST_DONE2 (1UL << 9) // Channel2 link list fetch done status +#define GPDMA_STAT_PHRL_END_OF_XFER2 (1UL << 10) // Channel2 transfer done status +#define GPDMA_STAT_GPDMAC_ERROR2 (1UL << 11) // Channel2 Transfer size/burst size /h size mismatch/flow ctrl err status +#define GPDMA_STAT_HRESP_ERROR3 (1UL << 12) // Channel3 dma error +#define GPDMA_STAT_LINK_LIST_DONE3 (1UL << 13) // Channel3 link list fetch done status +#define GPDMA_STAT_PHRL_END_OF_XFER3 (1UL << 14) // Channel3 transfer done status +#define GPDMA_STAT_GPDMAC_ERROR3 (1UL << 15) // Channel3 Transfer size/burst size /h size mismatch/flow ctrl err status +#define GPDMA_STAT_HRESP_ERROR4 (1UL << 16) // Channel4 dma error +#define GPDMA_STAT_LINK_LIST_DONE4 (1UL << 17) // Channel4 link list fetch done status +#define GPDMA_STAT_PHRL_END_OF_XFER4 (1UL << 18) // Channel4 transfer done status +#define GPDMA_STAT_GPDMAC_ERROR4 (1UL << 19) // Channel4 Transfer size/burst size /h size mismatch/flow ctrl err status +#define GPDMA_STAT_HRESP_ERROR5 (1UL << 20) // Channel5 dma error +#define GPDMA_STAT_LINK_LIST_DONE5 (1UL << 21) // Channel5 link list fetch done status +#define GPDMA_STAT_PHRL_END_OF_XFER5 (1UL << 22) // Channel5 transfer done status +#define GPDMA_STAT_GPDMAC_ERROR5 (1UL << 23) // Channel5 Transfer size/burst size /h size mismatch/flow ctrl err status +#define GPDMA_STAT_HRESP_ERROR6 (1UL << 24) // Channel6 dma error +#define GPDMA_STAT_LINK_LIST_DONE6 (1UL << 25) // Channel6 link list fetch done status +#define GPDMA_STAT_PHRL_END_OF_XFER6 (1UL << 26) // Channel6 transfer done status +#define GPDMA_STAT_GPDMAC_ERROR6 (1UL << 27) // Channel6 Transfer size/burst size /h size mismatch/flow ctrl err status +#define GPDMA_STAT_HRESP_ERROR7 (1UL << 28) // Channel7 dma error +#define GPDMA_STAT_LINK_LIST_DONE7 (1UL << 29) // Channel7 link list fetch done status +#define GPDMA_STAT_PHRL_END_OF_XFER7 (1UL << 30) // Channel7 transfer done status +#define GPDMA_STAT_GPDMAC_ERROR7 (1UL << 31) // Channel7 Transfer size/burst size /h size mismatch/flow ctrl err status + +// GPDMA Event Flags +#define RSI_GPDMA_EVENT_HRESP_ERROR0 1 +#define RSI_GPDMA_EVENT_GPDMAC_LINK_LIST_DONE0 2 +#define RSI_GPDMA_EVENT_GPDMAC_PHRL_END_OF_XFER0 3 +#define RSI_GPDMA_EVENT_GPDMAC_ERROR0 4 +#define RSI_GPDMA_EVENT_HRESP_ERROR1 5 +#define RSI_GPDMA_EVENT_GPDMAC_LINK_LIST_DONE1 6 +#define RSI_GPDMA_EVENT_GPDMAC_PHRL_END_OF_XFER1 7 +#define RSI_GPDMA_EVENT_GPDMAC_ERROR1 8 +#define RSI_GPDMA_EVENT_HRESP_ERROR2 9 +#define RSI_GPDMA_EVENT_GPDMAC_LINK_LIST_DONE2 10 +#define RSI_GPDMA_EVENT_GPDMAC_PHRL_END_OF_XFER2 11 +#define RSI_GPDMA_EVENT_GPDMAC_ERROR2 12 +#define RSI_GPDMA_EVENT_HRESP_ERROR3 13 +#define RSI_GPDMA_EVENT_GPDMAC_LINK_LIST_DONE3 14 +#define RSI_GPDMA_EVENT_GPDMAC_PHRL_END_OF_XFER3 15 +#define RSI_GPDMA_EVENT_GPDMAC_ERROR3 16 +#define RSI_GPDMA_EVENT_HRESP_ERROR4 17 +#define RSI_GPDMA_EVENT_GPDMAC_LINK_LIST_DONE4 18 +#define RSI_GPDMA_EVENT_GPDMAC_PHRL_END_OF_XFER4 19 +#define RSI_GPDMA_EVENT_GPDMAC_ERROR4 20 +#define RSI_GPDMA_EVENT_HRESP_ERROR5 21 +#define RSI_GPDMA_EVENT_GPDMAC_LINK_LIST_DONE5 22 +#define RSI_GPDMA_EVENT_GPDMAC_PHRL_END_OF_XFER5 23 +#define RSI_GPDMA_EVENT_GPDMAC_ERROR5 24 +#define RSI_GPDMA_EVENT_HRESP_ERROR6 25 +#define RSI_GPDMA_EVENT_GPDMAC_LINK_LIST_DONE6 26 +#define RSI_GPDMA_EVENT_GPDMAC_PHRL_END_OF_XFER6 27 +#define RSI_GPDMA_EVENT_GPDMAC_ERROR6 28 +#define RSI_GPDMA_EVENT_HRESP_ERROR7 29 +#define RSI_GPDMA_EVENT_GPDMAC_LINK_LIST_DONE7 30 +#define RSI_GPDMA_EVENT_GPDMAC_PHRL_END_OF_XFER7 31 +#define RSI_GPDMA_EVENT_GPDMAC_ERROR7 32 + +#define MEMORY_MEMORY 0x0 +#define MEMORY_PERIPHERAL 0x1 +#define PERIPHERAL_MEMORY 0x2 +#define PERIPHERAL_PERIPHERAL 0x3 + +#define DMA_FLW_CTRL 0x0 +#define SRC_PERI_CTRL 0x1 +#define DST_PERI_CTRL 0x2 +#define SRC_DST_PERI_CTRL 0x3 + +#define MASTER0_FETCH_IFSEL 0x0 +#define MASTER1_FETCH_IFSEL 0x1 + +#define MASTER0_SEND_IFSEL 0x0 +#define MASTER1_SEND_IFSEL 0x1 + +#define SRC_8_DATA_WIDTH 0x0 +#define SRC_16_DATA_WIDTH 0x1 +#define SRC_32_DATA_WIDTH 0x2 + +#define DST_8_DATA_WIDTH 0x0 +#define DST_16_DATA_WIDTH 0x1 +#define DST_32_DATA_WIDTH 0x2 + +#define LINK_LIST_EN 0x1 +#define LINK_LIST_DIS 0x0 +#define LINK_MASTER_0_FTCH 0x0 +#define LINK_MASTER_1_FTCH 0x1 + +#define SRC_ADR_CONTIG_EN 0x1 +#define SRC_ADR_CONTIG_DIS 0x0 +#define DST_ADR_CONTIG_EN 0x1 +#define DST_ADR_CONTIG_DIS 0x0 + +#define RETRY_ON_ERR_EN 0x1 +#define RETRY_ON_ERR_DIS 0x0 + +#define SRC_FIFO_EN 0x1 +#define SRC_FIFO_DIS 0x0 + +#define DST_FIFO_EN 0x1 +#define DST_FIFO_DIS 0x0 + +#define MAX_TRANS_SIZE 4096 + +#define AHBBURST_SIZE_1 0x0 +#define AHBBURST_SIZE_4 0x1 +#define AHBBURST_SIZE_8 0x2 +#define AHBBURST_SIZE_16 0x3 +#define AHBBURST_SIZE_20 0x4 +#define AHBBURST_SIZE_24 0x5 +#define AHBBURST_SIZE_28 0x6 +#define AHBBURST_SIZE_32 0x7 + +#define AHBBURST_SIZE_MAX 0x7 +#define AHBBURST_SIZE_MIN 0x0 + +#define DST_BURST_SIZE_64 0x0 +#define DST_BURST_SIZE_1 0x1 +#define DST_BURST_SIZE_2 0x2 +#define DST_BURST_SIZE_3 0x3 +#define DST_BURST_SIZE_4 0x4 +#define DST_BURST_SIZE_5 0x5 +#define DST_BURST_SIZE_6 0x6 +#define DST_BURST_SIZE_7 0x7 +#define DST_BURST_SIZE_8 0x8 +#define DST_BURST_SIZE_9 0x9 +#define DST_BURST_SIZE_10 0x10 +#define DST_BURST_SIZE_11 0x11 +#define DST_BURST_SIZE_12 0x12 +#define DST_BURST_SIZE_13 0x13 +#define DST_BURST_SIZE_14 0x14 +#define DST_BURST_SIZE_15 0x15 +#define DST_BURST_SIZE_16 0x16 +#define DST_BURST_SIZE_17 0x17 +#define DST_BURST_SIZE_18 0x18 +#define DST_BURST_SIZE_MIN 0x0 +#define DST_BURST_SIZE_MAX 63 + +#define SRC_BURST_SIZE_64 0x0 +#define SRC_BURST_SIZE_1 0x1 +#define SRC_BURST_SIZE_2 0x2 +#define SRC_BURST_SIZE_3 0x3 +#define SRC_BURST_SIZE_4 0x4 +#define SRC_BURST_SIZE_5 0x5 +#define SRC_BURST_SIZE_6 0x6 +#define SRC_BURST_SIZE_7 0x7 +#define SRC_BURST_SIZE_8 0x8 +#define SRC_BURST_SIZE_9 0x9 +#define SRC_BURST_SIZE_10 0x10 +#define SRC_BURST_SIZE_11 0x11 +#define SRC_BURST_SIZE_12 0x12 +#define SRC_BURST_SIZE_13 0x13 +#define SRC_BURST_SIZE_14 0x14 +#define SRC_BURST_SIZE_15 0x15 +#define SRC_BURST_SIZE_16 0x16 +#define SRC_BURST_SIZE_17 0x17 +#define SRC_BURST_SIZE_18 0x18 +#define SRC_BURST_SIZE_MIN 0x0 +#define SRC_BURST_SIZE_MAX 63 + +#define DST_CHNL_ID_MIN 0x0 +#define DST_CHNL_ID_MAX 47 +#define SRC_CHNL_ID_MIN 0x0 +#define SRC_CHNL_ID_MAX 47 +#define DMA_PROT_EN 0x1 +#define DMA_PROT_DIS 0x0 +#define MEM_FILL_EN 0x1 +#define MEM_FILL_DIS 0x0 +#define MEM_FILL_ONE 0x1 +#define MEM_FILL_ZERO 0x0 +#define SRC_ALIGN_DIS 0x0 +#define SRC_ALIGN_EN 0x1 + +#define LINK_INTR_DIS 0x0 +#define LINK_INTR_ON 0x1 +#define DESC_FETCH_DONE_INTR 0 +#define TRANS_DONE_INTR 1 + +#define UNMASK_DESC_FETCH_INTR 0x0000FF +#define GPDMA_CHNL0 0 +#define GPDMA_CHNL1 1 +#define GPDMA_CHNL7 7 + +#define GPDMA_CHNL_0 0 +#define GPDMA_CHNL_1 1 +#define GPDMA_CHNL_2 2 +#define GPDMA_CHNL_3 3 + +#define XFER_SIZE_4K 4096 + +#define AHB_BURST_1 0x0 +#define AHB_BURST_4 0x1 +#define AHB_BURST_8 0x2 +#define AHB_BURST_16 0x3 +#define AHB_BURST_20 0x4 +#define AHB_BURST_24 0x5 +#define AHB_BURST_28 0x6 +#define AHB_BURST_32 0x7 + +#define SRC_BURST_64 0x00 +#define SRC_BURST_1 0x01 +#define SRC_BURST_16 0x10 +#define SRC_BURST_63 0x3F + +#define DST_BURST_64 0x00 +#define DST_BURST_1 0x01 +#define DST_BURST_16 0x10 +#define DST_BURST_63 0x3F + +#define FILL_ZEROS 0x0 +#define FILL_ONES 0x1 + +#define PRIO_LEVEL_4 0x3 +#define PRIO_LEVEL_3 0x2 +#define PRIO_LEVEL_2 0x1 +#define PRIO_LEVEL_1 0x0 + +#define MAX_CHANNELS 0x8 + +#define DESC_COUNT 4 +#define DESC_INDEX0 0 +#define DESC_INDEX1 1 +#define DESC_INDEX2 2 +#define DESC_INDEX3 3 + +#define FIFO_SIZE_MAX 512 + +#define NO_DST_CHNL_ID 0x0 +#define NO_SRC_CHNL_ID 0x0 + +#define HRESP_ERR 0 +#define GPDMAC_ERR 1 + +#define M4SS_GPDMA_INTR_SEL (*((uint32_t volatile *)(0x46110000 + 0x04))) +#define CLOCK_BASE 0x46000000 +#define CLK_ENABLE_SET_2_REG (*((uint32_t volatile *)(CLOCK_BASE + 0x08))) +#define CLK_ENABLE_SET_1_REG (*((uint32_t volatile *)(CLOCK_BASE + 0x00))) + +typedef GPDMA_G_Type RSI_GPDMAG_T; +typedef GPDMA_C_Type RSI_GPDMAC_T; + +// GPDMA Error flags +#define HRESP_ERR0 (1UL << 0) +#define HRESP_ERR1 (1UL << 4) +#define HRESP_ERR2 (1UL << 8) +#define HRESP_ERR3 (1UL << 12) +#define HRESP_ERR4 (1UL << 16) +#define HRESP_ERR5 (1UL << 20) +#define HRESP_ERR6 (1UL << 24) +#define HRESP_ERR7 (1UL << 28) +#define GPDMAC_ERR0 (1UL << 3) +#define GPDMAC_ERR1 (1UL << 7) +#define GPDMAC_ERR2 (1UL << 11) +#define GPDMAC_ERR3 (1UL << 15) +#define GPDMAC_ERR4 (1UL << 19) +#define GPDMAC_ERR5 (1UL << 23) +#define GPDMAC_ERR6 (1UL << 27) +#define GPDMAC_ERR7 (1UL << 31) + +// GPDMA transfer status flags +#define LINK_LIST_DONE0 (1UL << 1) +#define PHRL_END_OF_TFR0 (1UL << 2) +#define LINK_LIST_DONE1 (1UL << 5) +#define PHRL_END_OF_TFR1 (1UL << 6) +#define LINK_LIST_DONE2 (1UL << 9) +#define PHRL_END_OF_TFR2 (1UL << 10) +#define LINK_LIST_DONE3 (1UL << 13) +#define PHRL_END_OF_TFR3 (1UL << 14) +#define LINK_LIST_DONE04 (1UL << 17) +#define PHRL_END_OF_TFR4 (1UL << 18) +#define LINK_LIST_DONE5 (1UL << 21) +#define PHRL_END_OF_TFR5 (1UL << 22) +#define LINK_LIST_DONE6 (1UL << 25) +#define PHRL_END_OF_TFR6 (1UL << 26) +#define LINK_LIST_DONE7 (1UL << 29) +#define PHRL_END_OF_TFR7 (1UL << 30) + +// brief GPDMA Driver Capabilities. +typedef struct { + uint32_t noOfChannels : 4; // Total supporting channels + uint32_t noOfMasterInterfaces : 2; // No of master interfaces supported + uint32_t noOfPeriSupport : 7; // total supporting peripherals + uint32_t noOfPriorityLevels : 3; // No of priority levels + +} RSI_GPDMA_CAPABILITIES_T; + +// brief GPDMA Descriptor parameters. + +// brief chnl_ctrl_info +typedef PRE_PACK struct POST_PACK { + uint32_t transSize : 12; // Transfer lenght in bytes + uint32_t transType : 2; // Type of DMA transfer + uint32_t dmaFlwCtrl : 2; // Flow control type + uint32_t mastrIfFetchSel : 1; // Master controller select to fetch data + uint32_t mastrIfSendSel : 1; // Master controller select to send data + uint32_t destDataWidth : 2; // Destination data width + uint32_t srcDataWidth : 2; // Source data width + uint32_t srcAlign : 1; // Source Alignment + uint32_t linkListOn : 1; // Linked transfer on + uint32_t linkListMstrSel : 1; // Master controller select for link transfers + uint32_t srcAddContiguous : 1; // Source address contiguous + uint32_t dstAddContiguous : 1; // Destination address contiguous + uint32_t retryOnErr : 1; // Retry on error + uint32_t linkInterrupt : 1; // Link interrupt enable + uint32_t srcFifoMode : 1; // Source FIFO mode + uint32_t dstFifoMode : 1; // Destination FIFO mode + uint32_t reserved : 1; +} RSI_GPDMA_CHA_CONTROL_T; + +//brief Misc_chnl_ctrl_info +typedef PRE_PACK struct POST_PACK { + uint32_t ahbBurstSize : 3; // AHB Burst size + uint32_t destDataBurst : 6; // Destination data Burst size + uint32_t srcDataBurst : 6; // source data Burst size + uint32_t destChannelId : 6; // Dest channel ID + uint32_t srcChannelId : 6; // Source channel ID + uint32_t dmaProt : 3; + uint32_t memoryFillEn : 1; // Memory fill enable + uint32_t memoryOneFill : 1; // Memory fill with 1 or 0 +} RSI_GPDMA_MISC_CHA_CONTROL_T; + +//brief GPDMA controller handle type +typedef void *RSI_GPDMA_HANDLE_T; + +typedef PRE_PACK struct POST_PACK { + uint32_t *pNextLink; // Pointer to next descriptor link in a chain, NULL to end + void *src; // source address + void *dest; // destination address + RSI_GPDMA_CHA_CONTROL_T chnlCtrlConfig; // Channel control register paramter + RSI_GPDMA_MISC_CHA_CONTROL_T miscChnlCtrlConfig; // Channel control register paramter +} RSI_GPDMA_DESC_T; + +typedef void (*gpdmaTransferCompleteCB)(RSI_GPDMA_HANDLE_T gpdmaHandle, RSI_GPDMA_DESC_T *pTranDesc, uint32_t dmaCh); +typedef void (*gpdmaTransferDescFetchCompleteCB)(RSI_GPDMA_HANDLE_T gpdmaHandle, + RSI_GPDMA_DESC_T *pTranDesc, + uint32_t dmaCh); +typedef void (*gpdmaTransferHrespErrorCB)(RSI_GPDMA_HANDLE_T gpdmaHandle, RSI_GPDMA_DESC_T *pTranDesc, uint32_t dmaCh); +typedef void (*gpdmaTransferRpdmacErrorCB)(RSI_GPDMA_HANDLE_T gpdmaHandle, RSI_GPDMA_DESC_T *pTranDesc, uint32_t dmaCh); +typedef void (*gpdmaTransferErrorCB)(RSI_GPDMA_HANDLE_T gpdmaHandle, RSI_GPDMA_DESC_T *pTranDesc, uint32_t dmaCh); + +// @brief GPDMA controller callback IDs +typedef enum { + RSI_GPDMA_XFERCOMPLETE_CB = 0, // Callback ID for GPDMA transfer descriptor chain complete + RSI_GPDMA_XFERDESCFETCHCOMPLETE_CB, // Callback ID for GPDMA transfer descriptor complete + RSI_GPDMA_XFERHRESPERROR_CB, // Callback ID for GPDMA transfer error occurance + RSI_GPDMA_XFERGPDMACERROR_CB +} RSI_GPDMA_CALLBACK_T; + +// Private data structure used for the GPDMA controller driver, holds the driver and peripheral context +typedef struct { + void *pUserData; // Pointer to user data used by driver instance, use NULL if not used + RSI_GPDMAG_T *baseG; // GPDMA global registers base + RSI_GPDMAC_T *baseC; // GPDMA channel specific registers base + RSI_GPDMA_DESC_T *sramBase; // SRAM descriptor table (all channels) + gpdmaTransferCompleteCB gpdmaCompCB; // Transfer descriptor chain completion callback + gpdmaTransferDescFetchCompleteCB gpdmaDescFetchCompCB; // Transfer descriptor fetch completion callback + gpdmaTransferHrespErrorCB gpdmaHrespErrorCB; // Transfer error callback + gpdmaTransferRpdmacErrorCB gpdmaRpdmacErrorCB; // Transfer error callback + uint32_t dmaCh; // GPDMA channel +} GPDMA_DATACONTEXT_T; + +// GPDMA Init structure +typedef PRE_PACK struct POST_PACK { + void *pUserData; // Pointer to user data used by driver instance, use NULL if not used + uint32_t baseG; // Pointer to GPDMA global register instance + uint32_t baseC; // Pointer to GPDMA channel specific register instance + uint32_t sramBase; // Pointer to memory used for GPDMA descriptor storage, must be 512 byte aligned +} RSI_GPDMA_INIT_T; + +// brief GPDMA transfer channel setup structure (use this structure as const if possible) +typedef PRE_PACK struct POST_PACK { + uint32_t channelPrio; // Channel priority level + uint32_t descFetchDoneIntr; // Desc fetch done interrupt flag + uint32_t xferDoneIntr; // Transfer done interrupt flag + uint32_t hrespErr; // dma error flag + uint32_t gpdmacErr; // Transfer size/burst size /h size mismatch/flow ctrl err + uint32_t dmaCh; // Channel number +} RSI_GPDMA_CHA_CFG_T; + +/*===================================================*/ +/** + * @fn void RSI_GPDMA_FIFOConfig( RSI_GPDMA_HANDLE_T pHandle, uint8_t dmaCh, + uint32_t startAdr, uint32_t size ) + * @brief Set fifo configuration for data transmission. + * @param[in] pHandle : Pointer to driver context handle + * @param[in] dmaCh : DMA channel number(0-7) + * @param[in] startAdr : starting address for data transfer. + * @param[in] size : size of data transfer. + * @return none. + */ +STATIC INLINE void RSI_GPDMA_FIFOConfig(RSI_GPDMA_HANDLE_T pHandle, uint8_t dmaCh, uint32_t startAdr, uint32_t size) +{ + GPDMA_DATACONTEXT_T *pDrv = (GPDMA_DATACONTEXT_T *)pHandle; + pDrv->baseC->CHANNEL_CONFIG[dmaCh].FIFO_CONFIG_REGS_b.FIFO_STRT_ADDR = (unsigned int)(startAdr & 0x3F); + pDrv->baseC->CHANNEL_CONFIG[dmaCh].FIFO_CONFIG_REGS_b.FIFO_SIZE = (unsigned int)(size & 0x3F); +} + +// FUNCTION PROTOTYPES +RSI_DRIVER_VERSION_M4 RSI_GPDMA_GetVersion(void); + +RSI_GPDMA_CAPABILITIES_T RSI_GPDMA_GetCapabilities(void); + +uint32_t gpdma_get_mem_size(void); + +RSI_GPDMA_HANDLE_T gpdma_init(void *mem, const RSI_GPDMA_INIT_T *pInit); + +void gpdma_register_callback(RSI_GPDMA_HANDLE_T pHandle, uint32_t cbIndex, gpdmaTransferCompleteCB pCB); + +rsi_error_t gpdma_abort_channel(RSI_GPDMA_HANDLE_T pHandle, uint8_t dmaCh); + +rsi_error_t gpdma_setup_channel(RSI_GPDMA_HANDLE_T pHandle, RSI_GPDMA_CHA_CFG_T *pCfg); + +rsi_error_t gpdma_build_descriptors(RSI_GPDMA_HANDLE_T pHandle, + RSI_GPDMA_DESC_T *pXferCfg, + RSI_GPDMA_DESC_T *pDesc, + RSI_GPDMA_DESC_T *pDescPrev); + +rsi_error_t gpdma_setup_channelTransfer(RSI_GPDMA_HANDLE_T pHandle, uint8_t dmaCh, RSI_GPDMA_DESC_T *pDesc); + +void gpdma_interrupt_handler(RSI_GPDMA_HANDLE_T pHandle); + +void gpdma_deInit(RSI_GPDMA_HANDLE_T pHandle, RSI_GPDMA_CHA_CFG_T *pCfg); + +rsi_error_t gpdma_dma_channel_trigger(RSI_GPDMA_HANDLE_T pHandle, uint8_t dmaCh); + +uint32_t gpdma_channel_is_enabled(RSI_GPDMA_HANDLE_T pHandle, uint8_t dmaCh); + +rsi_error_t gpdma_interrupt_disable(RSI_GPDMA_HANDLE_T pHandle, RSI_GPDMA_CHA_CFG_T *pCfg); + +rsi_error_t gpdma_interrupt_enable(RSI_GPDMA_HANDLE_T pHandle, RSI_GPDMA_CHA_CFG_T *pCfg); + +rsi_error_t gpdma_error_status_clear(RSI_GPDMA_HANDLE_T pHandle, RSI_GPDMA_CHA_CFG_T *pCfg); + +uint32_t gpdma_get_error_status(RSI_GPDMA_HANDLE_T pHandle, RSI_GPDMA_CHA_CFG_T *pCfg); + +rsi_error_t gpdma_interrupt_clear(RSI_GPDMA_HANDLE_T pHandle, RSI_GPDMA_CHA_CFG_T *pCfg); + +uint32_t gpdma_interrupt_status(RSI_GPDMA_HANDLE_T pHandle, RSI_GPDMA_CHA_CFG_T *pCfg); + +uint8_t RSI_GPDMA_GetChannelActivity(RSI_GPDMA_HANDLE_T pHandle, uint8_t dmaCh); + +#ifdef __cplusplus +} +#endif +#endif //RSI_GPDMA_H diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_pwm.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_pwm.h new file mode 100644 index 000000000..1dfbbdbec --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_pwm.h @@ -0,0 +1,965 @@ +/******************************************************************************* +* @file rsi_pwm.h +* @brief +******************************************************************************* +* # License +* Copyright 2022 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +// Includes Files + +#include "rsi_ccp_common.h" +#include "base_types.h" +#include "rsi_error.h" + +#ifndef RSI_PWM_H +#define RSI_PWM_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define RSI_MCPWM_API_VERSION RSI_DRIVER_VERSION_MAJOR_MINOR(2, 00) // API version 0.1 +#define RSI_MCPWM_DRV_VERSION RSI_DRIVER_VERSION_MAJOR_MINOR(00, 01) // driver version 0.1 + +// MCPWM Interrupt Flags +#define RSI_MCPWM_EVENT_RISE_TIME_PERIOD_MATCH_CH0 \ + (1UL << 0) // Time base match for 0th channel without considering postscaler +#define RSI_MCPWM_EVENT_TIME_PERIOD_MATCH_CH0 (1UL << 1) // Time base match for 0th channel which considering postscaler +#define RSI_MCPWM_EVENT_FAULT_A (1UL << 2) // Fault A pin match +#define RSI_MCPWM_EVENT_FAULT_B (1UL << 3) // Fault B pin match +#define RSI_MCPWM_EVENT_RISE_TIME_PERIOD_MATCH_CH1 \ + (1UL << 4) // Time base match for 1st channel without considering postscaler +#define RSI_MCPWM_EVENT_TIME_PERIOD_MATCH_CH1 \ + (1UL << 5) // Time base match for 1st channel which considering postscaler +#define RSI_MCPWM_EVENT_RISE_TIME_PERIOD_MATCH_CH2 \ + (1UL << 6) // Time base match for 2nd channel without considering postscaler +#define RSI_MCPWM_EVENT_TIME_PERIOD_MATCH_CH2 (1UL << 7) // Time base match for 2nd channel which considering postscaler +#define RSI_MCPWM_EVENT_RISE_TIME_PERIOD_MATCH_CH3 \ + (1UL << 8) // Time base match for 3rd channel without considering postscaler +#define RSI_MCPWM_EVENT_TIME_PERIOD_MATCH_CH3 \ + (1UL << 9) // Time base match for 3rd channel without considering postscaler + +#define FLTA_MODE (1UL << 0) +#define FLTB_MODE (1UL << 1) +#define FLTA_ENABLE (1UL << 4) +#define FLTB_ENABLE (1UL << 8) + +// MCPWM Events +#define RISE_TIME_PERIOD_MATCH_CH0 0x0 // Event for 0th channel without considering postscaler +#define TIME_PERIOD_MATCH_CH0 0x1 // Event for 0th channel which considering postscaler +#define FAULT_A 0x2 // Fault A pin Event +#define FAULT_B 0x3 // Fault B pin Event +#define RISE_TIME_PERIOD_MATCH_CH1 0x4 // Event for 1st channel without considering postscaler +#define TIME_PERIOD_MATCH_CH1 0x5 // Event for 1st channel which considering postscaler +#define RISE_TIME_PERIOD_MATCH_CH2 0x6 // Event for 2nd channel without considering postscaler +#define TIME_PERIOD_MATCH_CH2 0x7 // Event for 2nd channel which considering postscaler +#define RISE_TIME_PERIOD_MATCH_CH3 0x8 // Event for 3rd channel without considering postscaler +#define TIME_PERIOD_MATCH_CH3 0x9 // Event for 3rd channel which considering postscaler + +#define COUNTER_A 0 +#define COUNTER_B 1 + +// PWM Example defines +#define PWM_CHNL_0 0 +#define PWM_CHNL_1 1 +#define PWM_CHNL_2 2 +#define PWM_CHNL_3 3 + +#define TMR_FREE_RUN_MODE 0x0 +#define TMR_SINGLE_EVENT_MODE 0x1 +#define TMR_DOWN_COUNT_MODE 0x2 +#define TMR_UP_DOWN_MODE 0x3 +#define TMR_UP_DOWN_DOUBLE_UPDATE 0x4 + +#define ONE_TIMER_FOR_EACH_CHNL 0 +#define ONE_TIMER_FOR_ALL_CHNL 1 + +#define TIME_PERIOD_PRESCALE_1 0x0 +#define TIME_PERIOD_PRESCALE_2 0x1 +#define TIME_PERIOD_PRESCALE_4 0x2 +#define TIME_PERIOD_PRESCALE_8 0x3 +#define TIME_PERIOD_PRESCALE_16 0x4 +#define TIME_PERIOD_PRESCALE_32 0x5 +#define TIME_PERIOD_PRESCALE_64 0x6 + +#define TIME_PERIOD_POSTSCALE_1_1 0x0 +#define TIME_PERIOD_POSTSCALE_1_2 0x1 +#define TIME_PERIOD_POSTSCALE_1_3 0x2 +#define TIME_PERIOD_POSTSCALE_1_4 0x3 +#define TIME_PERIOD_POSTSCALE_1_5 0x4 +#define TIME_PERIOD_POSTSCALE_1_6 0x5 +#define TIME_PERIOD_POSTSCALE_1_7 0x6 +#define TIME_PERIOD_POSTSCALE_1_8 0x7 +#define TIME_PERIOD_POSTSCALE_1_9 0x8 +#define TIME_PERIOD_POSTSCALE_1_10 0x9 +#define TIME_PERIOD_POSTSCALE_1_11 0xA +#define TIME_PERIOD_POSTSCALE_1_12 0xB +#define TIME_PERIOD_POSTSCALE_1_13 0xC +#define TIME_PERIOD_POSTSCALE_1_14 0xD +#define TIME_PERIOD_POSTSCALE_1_15 0xE +#define TIME_PERIOD_POSTSCALE_1_16 0xF + +#define TMR0_PERIOD 0x1500 +#define TMR1_PERIOD 0x1500 +#define TMR2_PERIOD 0x1500 +#define TMR3_PERIOD 0x1500 + +#define COUNTER_INIT_VAL 0 + +#define DUTYCYCLE_UPDATE_DIS0 (1 << 4) +#define DUTYCYCLE_UPDATE_DIS1 (1 << 5) +#define DUTYCYCLE_UPDATE_DIS2 (1 << 6) +#define DUTYCYCLE_UPDATE_DIS3 (1 << 7) + +#define IMD_UPDATE_EN0 (1 << 0) +#define IMD_UPDATE_EN1 (1 << 1) +#define IMD_UPDATE_EN2 (1 << 2) +#define IMD_UPDATE_EN3 (1 << 3) + +#define DUTYCYCLE_UPDATE_EN0 (1 << 4) +#define DUTYCYCLE_UPDATE_EN1 (1 << 5) +#define DUTYCYCLE_UPDATE_EN2 (1 << 6) +#define DUTYCYCLE_UPDATE_EN3 (1 << 7) + +#define IMD_UPDATE_DIS0 (1 << 0) +#define IMD_UPDATE_DIS1 (1 << 1) +#define IMD_UPDATE_DIS2 (1 << 2) +#define IMD_UPDATE_DIS3 (1 << 3) + +#define TMR0_DUTYCYCLE 0xA80 +#define TMR1_DUTYCYCLE 0xA80 +#define TMR2_DUTYCYCLE 0xA80 +#define TMR3_DUTYCYCLE 0xA80 + +#define COMPLEMENT 1 +#define INDEPENDENT 0 + +#define OUT_POL_H_HIGH (1 << 2) +#define OUT_POL_H_LOW (0 << 2) + +#define OUT_POL_L_HIGH (1 << 3) +#define OUT_POL_L_LOW (0 << 3) + +#define DT_SELECT_INACTIVE_CH0 (1 << 4) +#define DT_SELECT_INACTIVE_CH1 (1 << 5) +#define DT_SELECT_INACTIVE_CH2 (1 << 6) +#define DT_SELECT_INACTIVE_CH3 (1 << 7) + +#define DT_SELECT_ACTIVE_CH0 (1 << 0) +#define DT_SELECT_ACTIVE_CH1 (1 << 1) +#define DT_SELECT_ACTIVE_CH2 (1 << 2) +#define DT_SELECT_ACTIVE_CH3 (1 << 3) + +#define COUNTUP 0 +#define COUNTDOWN 1 +#define PWM_OUTPUT_L0 0 +#define PWM_OUTPUT_L1 1 +#define PWM_OUTPUT_L2 2 +#define PWM_OUTPUT_L3 3 +#define PWM_OUTPUT_H0 4 +#define PWM_OUTPUT_H1 5 +#define PWM_OUTPUT_H2 6 +#define PWM_OUTPUT_H3 7 + +#define PWM_OUTPUT_MIN 0 +#define PWM_OUTPUT_MAX 7 + +#define OVERRIDE_SYNC_EN 1 +#define OVERRIDE_SYNC_DIS 0 + +#define OV_VALUE_0 1 +#define OV_VALUE_1 0 + +#define DT_EN_CH0 (1 << 8) +#define DT_EN_CH1 (1 << 9) +#define DT_EN_CH2 (1 << 10) +#define DT_EN_CH3 (1 << 11) + +#define DT_DIS_CH0 (1 << 8) +#define DT_DIS_CH1 (1 << 9) +#define DT_DIS_CH2 (1 << 10) +#define DT_DIS_CH3 (1 << 11) + +typedef MCPWM_Type RSI_MCPWM_T; + +// brief MCPWM Status +typedef struct { + uint32_t counterDir; // Current Counter direction + uint32_t counterVal; // Counter current value +} RSI_MCPWM_STATUS_T; + +// brief MCPWM Driver Capabilities. +typedef struct { + uint32_t pwmOutputs : 4; // Number of PWM outputs + uint32_t faultPins : 2; // Number of fault input pins +} RSI_MCPWM_CAPABILITIES_T; + +// brief MCPWM Callback structure +typedef struct { + void (*cbFunc)(uint16_t flag); // Call back function pointer + +} RSI_MCPWM_CALLBACK_T; + +// brief MCPWM Special Event trigger configuration parameters. +typedef struct { + uint16_t svtPostscalar; // SVT PostScalar value + uint16_t svtCompareVal; // SVT compare value to generate trigger for A/D + uint8_t svtChannel; // channel to generate SVT +} RSI_MCPWM_SVT_CONFIG_T; + +// brief MCPWM DeadTime Configuration parameters. +typedef struct { + uint8_t counterSelect; // Selects coutner A/B for deadtime insertion + int8_t preScaleA; // PreScale for counter A + int8_t preScaleB; // PreScale for counter B + int8_t deadTimeA; // Deadtime for counter A + int8_t deadTimeB; // Deadtime for counter B +} RSI_MCPWM_DT_CONFIG_T; + +/*===================================================*/ +/** + * @fn rsi_error_t RSI_MCPWM_ReadCounter(RSI_MCPWM_T *pMCPWM,uint16_t *counterVal, + uint8_t chnlNum) + * @brief This API is used to read the counter current value + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @param[in] counterVal : counter value + * @param[in] chnlNum : Channel number(0 to 3) + * @return \ref ERROR_PWM_INVALID_CHNLNUM : If channel is invalid. + \n \ref RSI_OK : If process is done successfully. + */ +STATIC INLINE rsi_error_t RSI_MCPWM_ReadCounter(RSI_MCPWM_T *pMCPWM, uint16_t *counterVal, uint8_t chnlNum) +{ + // Gets Time period counter current value + switch (chnlNum) { + case PWM_CHNL_0: + *counterVal = (uint16_t)(pMCPWM->PWM_TIME_PRD_CNTR_VALUE_CH0); + break; + case PWM_CHNL_1: + *counterVal = (uint16_t)(pMCPWM->PWM_TIME_PRD_CNTR_VALUE_CH1); + break; + case PWM_CHNL_2: + *counterVal = (uint16_t)(pMCPWM->PWM_TIME_PRD_CNTR_VALUE_CH2); + break; + case PWM_CHNL_3: + *counterVal = (uint16_t)(pMCPWM->PWM_TIME_PRD_CNTR_VALUE_CH3); + break; + default: + return ERROR_PWM_INVALID_CHNLNUM; + } + return RSI_OK; +} + +/*===================================================*/ +/** + * @fn rsi_error_t RSI_MCPWM_GetCounterDir(RSI_MCPWM_T *pMCPWM,uint8_t *counterDir, + uint8_t chnlNum) + * @brief This API is used to get time period counter direction status of required MCPWM channel + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @param[in] chnlNum : Channel number(0 to 3) + * @param[out] counterDir : Counter direction as up/down counter. + * @return \ref ERROR_PWM_INVALID_CHNLNUM : If channel number is invalid. + \n \ref RSI_OK(0) : If process is done successfully. + */ +STATIC INLINE rsi_error_t RSI_MCPWM_GetCounterDir(RSI_MCPWM_T *pMCPWM, uint8_t *counterDir, uint8_t chnlNum) +{ + // Gets the counter direction + switch (chnlNum) { + case PWM_CHNL_0: + *counterDir = (uint8_t)(pMCPWM->PWM_TIME_PRD_STS_REG_CH0); + break; + case PWM_CHNL_1: + *counterDir = (uint8_t)(pMCPWM->PWM_TIME_PRD_STS_REG_CH1); + break; + case PWM_CHNL_2: + *counterDir = (uint8_t)(pMCPWM->PWM_TIME_PRD_STS_REG_CH2); + break; + case PWM_CHNL_3: + *counterDir = (uint8_t)(pMCPWM->PWM_TIME_PRD_STS_REG_CH3); + break; + default: + return ERROR_PWM_INVALID_CHNLNUM; + } + return RSI_OK; +} + +/*===================================================*/ +/** + * @fn void RSI_MCPWM_DeadTimeEnable(RSI_MCPWM_T *pMCPWM ,uint32_t flag) + * @brief Enables dead time insertion at rise edge or fall edge of any four channels + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @param[in] flag : This can be ORing of below values + - DT_EN_CH0 + - DT_EN_CH1 + - DT_EN_CH2 + - DT_EN_CH3 + * @return none + */ +STATIC INLINE void RSI_MCPWM_DeadTimeEnable(RSI_MCPWM_T *pMCPWM, uint32_t flag) +{ + pMCPWM->PWM_DEADTIME_CTRL_RESET_REG = flag; +} + +/*===================================================*/ +/** + * @fn void RSI_MCPWM_DeadTimeDisable(RSI_MCPWM_T *pMCPWM ,uint32_t flag) + * @brief This API is used to disable the dead time mode for the specified MCPWM generator. + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @param[in] flag : This can be ORing of below values + - DT_DIS_CH0 + - DT_DIS_CH1 + - DT_DIS_CH2 + - DT_DIS_CH3 + * @return none + */ +STATIC INLINE void RSI_MCPWM_DeadTimeDisable(RSI_MCPWM_T *pMCPWM, uint32_t flag) +{ + pMCPWM->PWM_DEADTIME_CTRL_SET_REG = flag; +} + +/*===================================================*/ +/** + * @fn void RSI_MCPWM_Dead_Time_Enable(RSI_MCPWM_T *pMCPWM ,uint32_t flag) + * @brief Enables dead time insertion at rise edge or fall edge of any four channels + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @param[in] flag : This can be ORing of below values + - DT_EN_CH0 + - DT_EN_CH1 + - DT_EN_CH2 + - DT_EN_CH3 + * @return none + */ +STATIC INLINE void RSI_MCPWM_Dead_Time_Enable(RSI_MCPWM_T *pMCPWM, uint32_t flag) +{ + pMCPWM->PWM_DEADTIME_CTRL_SET_REG = flag; +} + +/*===================================================*/ +/** + * @fn void RSI_MCPWM_Dead_Time_Disable(RSI_MCPWM_T *pMCPWM ,uint32_t flag) + * @brief This API is used to disable the dead time mode for the specified MCPWM generator. + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @param[in] flag : This can be ORing of below values + - DT_DIS_CH0 + - DT_DIS_CH1 + - DT_DIS_CH2 + - DT_DIS_CH3 + * @return none + */ +STATIC INLINE void RSI_MCPWM_Dead_Time_Disable(RSI_MCPWM_T *pMCPWM, uint32_t flag) +{ + pMCPWM->PWM_DEADTIME_CTRL_RESET_REG = flag; +} + +/*===================================================*/ +/** + * @fn void RSI_MCPWM_InterruptClear(RSI_MCPWM_T *pMCPWM, uint32_t clrFlag) + * @brief This API is used to clear the interrupts of MCPWM + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @param[in] clrFlag : This can be logical OR of the below parameters + - RISE_PWM_TIME_PERIOD_MATCH_CH0_ACK : Time base interrupt for 0th channel without considering postscaler + \n if bit is one then pwm time period match interrupt for 0th channel will + be cleared if bit zero then no effect. + - PWM_TIME_PRD_MATCH_INTR_CH0_ACK : Time base interrupt for 0th channel which + considering postscaler + \n if bit is one then pwm time period match interrupt for 0th channel will + be cleared if bit zero then no effect. + - FLT_A_INTR_ACK : Fault A pin interrupt + \n if bit is set pwm faultA interrupt will be cleared,if zero then ,no effect. + - FLT_A_INTR_ACK : Fault B pin interrupt + \n if bit is set pwm faultB interrupt will be cleared,if zero then ,no effect. + - RISE_PWM_TIME_PERIOD_MATCH_CH1_ACK : Time base interrupt for + 1th channel without considering postscaler + \n if bit is one then pwm time period match interrupt for 1th channel will + be cleared if bit zero then no effect. + - PWM_TIME_PRD_MATCH_INTR_CH1_ACK : Time base interrupt for 1th channel which + considering postscaler + \n if bit is one then pwm time period match interrupt for 1th channel will + be cleared if bit zero then no effect. + - RISE_PWM_TIME_PERIOD_MATCH_CH2_ACK : Time base interrupt for + 2nd channel without considering postscaler + \n if bit is one then pwm time period match interrupt for 1th channel will + be cleared if bit zero then no effect. + - PWM_TIME_PRD_MATCH_INTR_CH2_ACK : Time base interrupt for 2nd channel which + considering postscaler + \n if bit is one then pwm time period match interrupt for 2nd channel will + be cleared if bit zero then no effect. + - RISE_PWM_TIME_PERIOD_MATCH_CH3_ACK : Time base interrupt for + 3rd channel without considering postscaler + \n if bit is one then pwm time period match interrupt for 3rd channel will + be cleared if bit zero then no effect. + - PWM_TIME_PRD_MATCH_INTR_CH3_ACK : Time base interrupt for 3rd channel which + considering postscaler + \n if bit is one then pwm time period match interrupt for 3rd channel will + be cleared if bit zero then no effect. + + * @return none + */ +STATIC INLINE void RSI_MCPWM_InterruptClear(RSI_MCPWM_T *pMCPWM, uint32_t clrFlag) +{ + pMCPWM->PWM_INTR_ACK = clrFlag; +} + +/*===================================================*/ +/** + * @fn void RSI_MCPWM_InterruptEnable(RSI_MCPWM_T *pMCPWM, uint16_t flag) + * @brief This API is used to enable the interrupts of MCPWM + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @param[in] flag : flag value can be logical OR of the below parameters + - RISE_PWM_TIME_PERIOD_MATCH_CH0 : Time base interrupt for 0th channel without + considering postscaler + \n if bit is 1 then pwm time period match interrupt for 0th channel + will be cleared,if zero then no effect. + - PWM_TIME_PRD_MATCH_INTR_CH0 : Time base interrupt for 0th channel which + considering postscaler + \n if bit is 1 then pwm time period match interrupt for 0th channel + will be cleared if zero then no effect. + - FLT_A_INTR : Fault A pin interrupt + \n if bit is one then pwm faultA interrupt will be cleared if zero + then no effect. + - FLT_B_INTR : Fault B pin interrupt + \n if bit is one pwm faultB interrupt will be cleared if zero + then no effect. + - RISE_PWM_TIME_PERIOD_MATCH_CH1 : Time base interrupt for 1st channel without + considering postscaler + \n if bit is one pwm time period match interrupt for 1st channel + will be cleared if bit is zero no effect + - PWM_TIME_PRD_MATCH_INTR_CH1 : Time base interrupt for 1st channel which + considering postscaler + \n if bit is 1 then pwm time period match interrupt for 1st channel + will be cleared if zero then no effect. + - RISE_PWM_TIME_PERIOD_MATCH_CH2 : Time base interrupt for 2nd channel without + considering postscaler + \n if bit is one pwm time period match interrupt for 2nd channel + will be cleared if bit is zero no effect + - PWM_TIME_PRD_MATCH_INTR_CH2 : Time base interrupt for 2nd channel which + considering postscaler + \n if bit is one pwm time period match interrupt for 2nd channel + will be cleared if bit is zero no effect + - RISE_PWM_TIME_PERIOD_MATCH_CH3 : Time base interrupt for 3rd channel without + considering postscaler + \n if bit is one pwm time period match interrupt for 3rd channel + will be cleared if bit is zero no effect + - PWM_TIME_PRD_MATCH_INTR_CH3 : Time base interrupt for 3rd channel which considering + postscaler + \n if bit is one pwm time period match interrupt for 3rd channel + will be cleared if bit is zero no effect + * @return none + */ +STATIC INLINE void RSI_MCPWM_InterruptEnable(RSI_MCPWM_T *pMCPWM, uint16_t flag) +{ + pMCPWM->PWM_INTR_UNMASK = flag; +} + +/*===================================================*/ +/** + * @fn void RSI_MCPWM_InterruptDisable(RSI_MCPWM_T *pMCPWM, uint16_t flag) + * @brief This API is used to disable the interrupts of MCPWM + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @param[in] flag : flag value can be logical OR of the below parameters + - RISE_PWM_TIME_PERIOD_MATCH_CH0 : Time base interrupt for 0th channel without + considering postscaler + \n if bit is 1 then pwm time period match interrupt for 0th channel + will be cleared,if zero then no effect. + - PWM_TIME_PRD_MATCH_INTR_CH0 : Time base interrupt for 0th channel which + considering postscaler + \n if bit is 1 then pwm time period match interrupt for 0th channel + will be cleared if zero then no effect. + - FLT_A_INTR : Fault A pin interrupt + \n if bit is one then pwm faultA interrupt will be cleared if zero + then no effect. + - FLT_B_INTR : Fault B pin interrupt + \n if bit is one pwm faultB interrupt will be cleared if zero + then no effect. + - RISE_PWM_TIME_PERIOD_MATCH_CH1 : Time base interrupt for 1st channel without + considering postscaler + \n if bit is one pwm time period match interrupt for 1st channel + will be cleared if bit is zero no effect + - PWM_TIME_PRD_MATCH_INTR_CH1 : Time base interrupt for 1st channel which + considering postscaler + \n if bit is 1 then pwm time period match interrupt for 0th channel + will be cleared if zero then no effect. + - RISE_PWM_TIME_PERIOD_MATCH_CH2 : Time base interrupt for 2nd channel without + considering postscaler + \n if bit is one pwm time period match interrupt for 2nd channel + will be cleared if bit is zero no effect + - PWM_TIME_PRD_MATCH_INTR_CH2 : Time base interrupt for 2nd channel which + considering postscaler + \n if bit is one pwm time period match interrupt for 2nd channel + will be cleared if bit is zero no effect + - RISE_PWM_TIME_PERIOD_MATCH_CH3 : Time base interrupt for 3rd channel without + considering postscaler + \n if bit is one pwm time period match interrupt for 3rd channel + will be cleared if bit is zero no effect + - PWM_TIME_PRD_MATCH_INTR_CH3 : Time base interrupt for 3rd channel which considering + postscaler + \n if bit is one pwm time period match interrupt for 3rd channel + will be cleared if bit is zero no effect + * @return none + */ +STATIC INLINE void RSI_MCPWM_InterruptDisable(RSI_MCPWM_T *pMCPWM, uint16_t flag) +{ + pMCPWM->PWM_INTR_MASK = flag; +} + +/*===================================================*/ +/** + * @fn uint16_t RSI_PWM_GetInterruptStatus(RSI_MCPWM_T *pMCPWM, uint16_t flag) + * @brief This API is used to get the interrupt status of interrupt flags of MCPWM. + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @param[in] flag : Flag value + * @return Interrupt status of required interrupt flag + */ +STATIC INLINE uint16_t RSI_PWM_GetInterruptStatus(RSI_MCPWM_T *pMCPWM, uint16_t flag) +{ + return (uint16_t)(pMCPWM->PWM_INTR_STS & flag); +} + +/*===================================================*/ +/** + * @fn rsi_error_t RSI_MCPWM_DutyCycleControlSet(RSI_MCPWM_T *pMCPWM,uint32_t value,uint8_t chnlNum) + * @brief This API is used to set duty cycle control parameters for the required MCPWM channel + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @param[in] value : This can be logical OR of below parameters + - IMDT_DUTYCYCLE_UPDATE_EN : Enable to update the duty cycle immediately + - DUTYCYCLE_UPDATE_DISABLE : Duty cycle register updation disable + * @param[in] chnlNum : Channel number(0 to 3) + * @return ERROR_PWM_INVALID_CHNLNUM : If channel is invalid. + \n RSI_OK : If process is done successfully. + */ +STATIC INLINE rsi_error_t RSI_MCPWM_DutyCycleControlSet(RSI_MCPWM_T *pMCPWM, uint32_t value, uint8_t chnlNum) +{ + if (chnlNum <= PWM_CHNL_3) { + pMCPWM->PWM_DUTYCYCLE_CTRL_SET_REG = value; + } else { + return ERROR_PWM_INVALID_CHNLNUM; + } + return RSI_OK; +} + +/*===================================================*/ +/** + * @fn rsi_error_t RSI_MCPWM_DutyCycleControlReset(RSI_MCPWM_T *pMCPWM,uint32_t value, uint8_t chnlNum) + * @brief This API is used to reset the duty cycle control parameters of required MCPWM channel + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @param[in] value : This can be logical OR of below parameters + - IMDT_DUTYCYCLE_UPDATE_EN : Enable to update the duty cycle immediately + - DUTYCYCLE_UPDATE_DISABLE : Duty cycle register updation disable + * @param[in] chnlNum Channel number(0 to 3) + * @return \ref ERROR_PWM_INVALID_CHNLNUM : If channel number is invalid + \n \ref RSI_OK : If process is done successfully. + */ +STATIC INLINE rsi_error_t RSI_MCPWM_DutyCycleControlReset(RSI_MCPWM_T *pMCPWM, uint32_t value, uint8_t chnlNum) +{ + if (chnlNum <= PWM_CHNL_3) { + pMCPWM->PWM_DUTYCYCLE_CTRL_RESET_REG = value; + } else { + return ERROR_PWM_INVALID_CHNLNUM; + } + return RSI_OK; +} + +/*===================================================*/ +/** + * @fn rsi_error_t RSI_MCPWM_OutputOverrideEnable(RSI_MCPWM_T *pMCPWM, uint8_t pwmOutput) + * @brief This API is used to enable the output override operation of MCPWM + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @param[in] pwmOutput : Pwm output over ride,possible values are as below + - 0 : L0 + - 1 : L1 + - 2 : L2 + - 3 : L3 + - 4 : H0 + - 5 : H1 + - 6 : H2 + - 7 : H3 + * @return \ref ERROR_PWM_INVALID_ARG : If pwmOutput value is invalid + * \n \ref RSI_OK : If process is done successfully. + */ +STATIC INLINE rsi_error_t RSI_MCPWM_OutputOverrideEnable(RSI_MCPWM_T *pMCPWM, uint8_t pwmOutput) +{ + if (pwmOutput <= PWM_OUTPUT_MAX) { + pMCPWM->PWM_OP_OVERRIDE_ENABLE_SET_REG = (1 << pwmOutput); + } else { + return ERROR_PWM_INVALID_ARG; + } + return RSI_OK; +} + +/*===================================================*/ +/** + * @fn rsi_error_t RSI_MCPWM_OutputOverrideDisable(RSI_MCPWM_T *pMCPWM,uint8_t pwmOutput) + * @brief This API is used to disable the output override operation of MCPWM + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @param[in] pwmOutput : Pwm output over ride enable,possible values are as below + - 0 : L0 + - 1 : L1 + - 2 : L2 + - 3 : L3 + - 4 : H0 + - 5 : H1 + - 6 : H2 + - 7 : H3 + * @return \ref ERROR_PWM_INVALID_ARG : If pwmOutput value is invalid + * \n \ref RSI_OK : If process is done successfully. +*/ +STATIC INLINE rsi_error_t RSI_MCPWM_OutputOverrideDisable(RSI_MCPWM_T *pMCPWM, uint8_t pwmOutput) +{ + if (pwmOutput <= PWM_OUTPUT_MAX) { + pMCPWM->PWM_OP_OVERRIDE_ENABLE_RESET_REG = (1 << pwmOutput); + } else { + return ERROR_PWM_INVALID_ARG; + } + return RSI_OK; +} + +/*===================================================*/ +/** + * @fn void RSI_MCPWM_OverrideControlSet(RSI_MCPWM_T *pMCPWM,uint32_t value) + * @brief This API is used to set the override control parameter,output is synced with pwm time period depending on operating mode + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @param[in] value : if value is 1 then Output override is synced with pwm time period depending + \n on operating mode, if 0 then no effect. + * @return none + */ +STATIC INLINE void RSI_MCPWM_OverrideControlSet(RSI_MCPWM_T *pMCPWM, uint32_t value) +{ + pMCPWM->PWM_OP_OVERRIDE_CTRL_SET_REG = value; +} + +/*===================================================*/ +/** + * @fn void RSI_MCPWM_OverrideControlReSet(RSI_MCPWM_T *pMCPWM,uint32_t value) + * @brief This API is used to reset the output override sync control parameter. + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @param[in] value : if value is 1 then Output override is synced with pwm time period depending + \n on operating mode, if 0 then no effect. + * @return none + */ +STATIC INLINE void RSI_MCPWM_OverrideControlReSet(RSI_MCPWM_T *pMCPWM, uint32_t value) +{ + pMCPWM->PWM_OP_OVERRIDE_CTRL_RESET_REG = value; +} + +/*===================================================*/ +/** + * @fn void RSI_MCPWM_OverrideValueSet(RSI_MCPWM_T *pMCPWM,uint8_t pwmOutput,uint8_t value) + * @brief This API is used to set override value for the required output of MCPWM. + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @param[in] pwmOutput : PWM outputs are as below + - 0 : L0 + - 1 : L1 + - 2 : L2 + - 3 : L3 + - 4 : H0 + - 5 : H1 + - 6 : H2 + - 7 : H3 + * @param[in] value : override value can be 0 or 1 + * @return \ref ERROR_PWM_INVALID_ARG : If pwmOutput value is invalid + * \n \ref RSI_OK : If process is done successfully. + */ +STATIC INLINE rsi_error_t RSI_MCPWM_OverrideValueSet(RSI_MCPWM_T *pMCPWM, uint8_t pwmOutput, uint8_t value) +{ + if (pwmOutput <= PWM_OUTPUT_MAX) { + pMCPWM->PWM_OP_OVERRIDE_VALUE_SET_REG = (value << pwmOutput); + } else { + return ERROR_PWM_INVALID_ARG; + } + return RSI_OK; +} + +/*===================================================*/ +/** + * @fn rsi_error_t RSI_MCPWM_OverrideValueReSet(RSI_MCPWM_T *pMCPWM,uint8_t pwmOutput,uint8_t value) + * @brief This API is used to reset override value for the required output of MCPWM. + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @param[in] pwmOutput : PWM outputs are as below + - 0 : L0 + - 1 : L1 + - 2 : L2 + - 3 : L3 + - 4 : H0 + - 5 : H1 + - 6 : H2 + - 7 : H3 + * @param[in] value : override value can be 0 or 1 + * @return \ref ERROR_PWM_INVALID_ARG : If pwmOutput value is invalid + \n \ref RSI_OK : If process is done successfully. + */ +STATIC INLINE rsi_error_t RSI_MCPWM_OverrideValueReSet(RSI_MCPWM_T *pMCPWM, uint8_t pwmOutput, uint8_t value) +{ + if (pwmOutput <= PWM_OUTPUT_MAX) { + pMCPWM->PWM_OP_OVERRIDE_VALUE_RESET_REG = (value << pwmOutput); + } else { + return ERROR_PWM_INVALID_ARG; + } + return RSI_OK; +} + +/*===================================================*/ +/** + * @fn void RSI_MCPWM_FaultControlSet(RSI_MCPWM_T *pMCPWM,uint32_t value) + * @brief This API is used to set output fault override control parameters for required PWM output + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @param[in] value : This can be logical OR of below parameters + - FLT_A_MODE : if bit one then cycle by cycle by mode and zero then latched mode + - FLT_B_MODE : if bit one then cycle by cycle by mode and zero then latched mode + - OP_POLARITY_H Ouput polarity for high (H3, H2, H1, H0) side signals. + \n if bit 0 then in active low mode and 1 then active high mode. + - OP_POLARITY_L Ouput polarity for low (L3, L2, L1, L0) side signals. + \n if bit 0 then in active low mode and 1 then active high mode. + - FLT_A_ENABLE : enable fault A + - FLT_B_ENABLE : enable fault B + - COMPLEMENT_MODE : PWM I/O pair mode + \n if bit is 1 then PWM I/O pin pair is in the complementary output mode + \n if bit is 0 then PWM I/O pin pair is in the independent output mode + * @return none + */ +STATIC INLINE void RSI_MCPWM_FaultControlSet(RSI_MCPWM_T *pMCPWM, uint32_t value) +{ + pMCPWM->PWM_FLT_OVERRIDE_CTRL_SET_REG = value; +} + +/*===================================================*/ +/** + * @fn void RSI_MCPWM_FaultControlReSet(RSI_MCPWM_T *pMCPWM, uint32_t value) + * @brief This API is used to reset output fault override control parameters for required PWM output. + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @param[in] value : This can be logical OR of below parameters + - FLT_A_MODE : if bit one then cycle by cycle by mode and zero then latched mode + - FLT_B_MODE : if bit one then cycle by cycle by mode and zero then latched mode + - OP_POLARITY_H Ouput polarity for high (H3, H2, H1, H0) side signals. + \n if bit 0 then in active low mode and 1 then active high mode. + - OP_POLARITY_L Ouput polarity for low (L3, L2, L1, L0) side signals. + \n if bit 0 then in active low mode and 1 then active high mode. + - FLT_A_ENABLE : enable fault A + - FLT_B_ENABLE : enable fault B + - COMPLEMENT_MODE : PWM I/O pair mode + \n if bit is 1 then PWM I/O pin pair is in the complementary output mode + \n if bit is 0 then PWM I/O pin pair is in the independent output mode + * @return none + */ +STATIC INLINE void RSI_MCPWM_FaultControlReSet(RSI_MCPWM_T *pMCPWM, uint32_t value) +{ + pMCPWM->PWM_FLT_OVERRIDE_CTRL_RESET_REG = value; +} + +/*===================================================*/ +/** + * @fn void RSI_MCPWM_SpecialEventTriggerEnable(RSI_MCPWM_T *pMCPWM ) + * @brief This API is used to enable generation of special event trigger for required channel of MCPWM + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @return none + */ +STATIC INLINE void RSI_MCPWM_SpecialEventTriggerEnable(RSI_MCPWM_T *pMCPWM) +{ + pMCPWM->PWM_SVT_CTRL_SET_REG = (1 << 0); +} + +/*===================================================*/ +/** + * @fn void RSI_MCPWM_SpecialEventTriggerDisable(RSI_MCPWM_T *pMCPWM ) + * @brief This API is used to disable generation of special event trigger for required channel of MCPWM + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @return none + */ +STATIC INLINE void RSI_MCPWM_SpecialEventTriggerDisable(RSI_MCPWM_T *pMCPWM) +{ + pMCPWM->PWM_SVT_CTRL_RESET_REG = (1 << 0); +} + +/*===================================================*/ +/** + * @fn void RSI_MCPWM_DeadTimeControlSet(RSI_MCPWM_T *pMCPWM, uint32_t value ) + * @brief This API is used to set dead time control parameters for the reqired channel. + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @param[in] value : This can be logical OR of below parameters + - DEADTIME_SELECT_ACTIVE : Deadtime select bits for PWM going active + Possible values are as below if bit zero then use counter A , if one then use counter B + - DEADTIME_SELECT_INACTIVE : Deadtime select bits for PWM going inactive + Possible values are as below if bit zero then use counter A , if one then use counter B + * @return none + */ +STATIC INLINE void RSI_MCPWM_DeadTimeControlSet(RSI_MCPWM_T *pMCPWM, uint32_t value) +{ + pMCPWM->PWM_DEADTIME_CTRL_SET_REG = value; +} + +/*===================================================*/ +/** + * @fn void RSI_MCPWM_DeadTimeControlReSet(RSI_MCPWM_T *pMCPWM, uint32_t value ) + * @brief This API is used to reset dead time control for the MCPWM. + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @param[in] value : This can be logical OR of below parameters + - DEADTIME_SELECT_ACTIVE : Deadtime select bits for PWM going active + Possible values are as below if bit zero then use counter A , if one then use counter B + - DEADTIME_SELECT_INACTIVE : Deadtime select bits for PWM going inactive + Possible values are as below if bit zero then use counter A , if one then use counter B + * @return none + */ +STATIC INLINE void RSI_MCPWM_DeadTimeControlReSet(RSI_MCPWM_T *pMCPWM, uint32_t value) +{ + pMCPWM->PWM_DEADTIME_CTRL_RESET_REG = value; +} + +/*===================================================*/ +/** + * @fn rsi_error_t RSI_MCPWM_SetDutyCycle(RSI_MCPWM_T *pMCPWM, uint16_t dutyCycle, uint8_t chnlNum) + * @brief This API is used to set duty cycle for the required MCPWM channel. + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @param[in] dutyCycle : Duty cycle value + * @param[in] chnlNum : channel number(0 to 3) + * @return \ref ERROR_PWM_INVALID_ARG : If channel number is invalid + \n \ref RSI_OK : If process is done successfully. + */ +STATIC INLINE rsi_error_t RSI_MCPWM_SetDutyCycle(RSI_MCPWM_T *pMCPWM, uint16_t dutyCycle, uint8_t chnlNum) +{ + if (chnlNum <= PWM_CHNL_3) { + pMCPWM->PWM_DUTYCYCLE_REG_WR_VALUE_b[chnlNum].PWM_DUTYCYCLE_REG_WR_VALUE_CH = dutyCycle; + } else { + return ERROR_PWM_INVALID_ARG; + } + return RSI_OK; +} + +/*===================================================*/ +/** + * @fn void RSI_MCPWM_ExternalTriggerControl(RSI_MCPWM_T *pMCPWM,boolean_t enable) + * @brief This API is used to enable to use external trigger for base time counter increment or decrement of MCPWM + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @param[in] enable : If 0 then disable external trigger + \n If 1 then enable external trigger. + * @return none + */ +STATIC INLINE void RSI_MCPWM_ExternalTriggerControl(RSI_MCPWM_T *pMCPWM, boolean_t enable) +{ + pMCPWM->PWM_TIME_PRD_COMMON_REG_b.USE_EXT_TIMER_TRIG_FRM_REG = (unsigned int)(enable & 0x01); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_PWM_Channel_Reset_Disable(RSI_MCPWM_T *pMCPWM, uint8_t chnlNum) + * @brief This API is used to disable the reset for required channel of MCPWM. + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @param[in] chnlNum : Channel number(0 to 3) + * @return \ref ERROR_PWM_INVALID_CHNLNUM : If channel is invalid + * \n \ref RSI_OK : If process is done successfully. + */ +STATIC INLINE rsi_error_t RSI_PWM_Channel_Reset_Disable(RSI_MCPWM_T *pMCPWM, uint8_t chnlNum) +{ + // Resets operation of MCPWM channel + switch (chnlNum) { + case PWM_CHNL_0: + pMCPWM->PWM_TIME_PRD_CTRL_REG_CH0_b.PWM_SFT_RST = DISABLE; + break; + case PWM_CHNL_1: + pMCPWM->PWM_TIME_PRD_CTRL_REG_CH1_b.PWM_SFT_RST = DISABLE; + break; + case PWM_CHNL_2: + pMCPWM->PWM_TIME_PRD_CTRL_REG_CH2_b.PWM_SFT_RST = DISABLE; + break; + case PWM_CHNL_3: + pMCPWM->PWM_TIME_PRD_CTRL_REG_CH3_b.PWM_SFT_RST = DISABLE; + break; + default: + return ERROR_PWM_INVALID_CHNLNUM; + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_PWM_Counter_Reset_Disable(RSI_MCPWM_T *pMCPWM, uint8_t chnlNum) + * @brief This API is used to disable the counter reset for required channel of MCPWM + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @param[in] chnlNum : Channel number(0 to 3) + * @return \ref ERROR_PWM_INVALID_CHNLNUM : If channel number is invalid + * \n \ref RSI_OK : If process is done successfully + */ +STATIC INLINE rsi_error_t RSI_PWM_Counter_Reset_Disable(RSI_MCPWM_T *pMCPWM, uint8_t chnlNum) +{ + // resets counter operations + switch (chnlNum) { + case PWM_CHNL_0: + pMCPWM->PWM_TIME_PRD_CTRL_REG_CH0_b.PWM_TIME_PRD_CNTR_RST_FRM_REG = DISABLE; + break; + case PWM_CHNL_1: + pMCPWM->PWM_TIME_PRD_CTRL_REG_CH1_b.PWM_TIME_PRD_CNTR_RST_FRM_REG = DISABLE; + break; + case PWM_CHNL_2: + pMCPWM->PWM_TIME_PRD_CTRL_REG_CH2_b.PWM_TIME_PRD_CNTR_RST_FRM_REG = DISABLE; + break; + case PWM_CHNL_3: + pMCPWM->PWM_TIME_PRD_CTRL_REG_CH3_b.PWM_TIME_PRD_CNTR_RST_FRM_REG = DISABLE; + break; + default: + return ERROR_PWM_INVALID_CHNLNUM; + } + return RSI_OK; +} + +/*===================================================*/ +/** + * @fn void RSI_MCPWM_BaseTimerSelect(RSI_MCPWM_T *pMCPWM,uint8_t baseTime) + * @brief This API is used to select number of base timers as four base timers for four channels or one base timer for all channels of MCPWM + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @param[in] baseTime : if 0 then one base timer for each channel + \n if 1 then only one base timer for all channels + * @return none + */ +STATIC INLINE void RSI_MCPWM_BaseTimerSelect(RSI_MCPWM_T *pMCPWM, uint8_t baseTime) +{ + pMCPWM->PWM_TIME_PRD_COMMON_REG_b.PWM_TIME_PRD_USE_0TH_TIMER_ONLY = (unsigned int)(baseTime & 0x01); +} +// PWM FUNCTION PROTOTYPES +RSI_DRIVER_VERSION_M4 RSI_MCPWM_GetVersion(void); + +RSI_MCPWM_CAPABILITIES_T RSI_MCPWM_GetCapabilities(void); + +rsi_error_t mcpwm_counter_reset(RSI_MCPWM_T *pMCPWM, uint8_t chnlNum); + +rsi_error_t mcpwm_channel_reset(RSI_MCPWM_T *pMCPWM, uint8_t chnlNum); + +rsi_error_t mcpwm_start(RSI_MCPWM_T *pMCPWM, uint8_t chnlNum); + +rsi_error_t mcpwm_stop(RSI_MCPWM_T *pMCPWM, uint8_t chnlNum); + +rsi_error_t mcpwm_set_time_period(RSI_MCPWM_T *pMCPWM, uint8_t chnlNum, uint16_t period, uint16_t initVal); + +void mcpwm_special_event_trigger_config(RSI_MCPWM_T *pMCPWM, boolean_t svtDir, RSI_MCPWM_SVT_CONFIG_T *pMCPWMSVTConfig); + +rsi_error_t mcpwm_dead_time_value_set(RSI_MCPWM_T *pMCPWM, + RSI_MCPWM_DT_CONFIG_T *pMCPWMDeadTimeConfig, + uint8_t chnlNum); +rsi_error_t mcpwm_fault_avalue_set(RSI_MCPWM_T *pMCPWM, uint8_t pwmOutput, uint8_t value); + +rsi_error_t mcpwm_fault_bvalue_set(RSI_MCPWM_T *pMCPWM, uint8_t pwmOutput, uint8_t value); + +rsi_error_t mcpwm_set_base_timer_mode(RSI_MCPWM_T *pMCPWM, uint8_t mode, uint8_t chnlNum); + +rsi_error_t mcpwm_set_output_mode(RSI_MCPWM_T *pMCPWM, boolean_t mode, uint8_t chnlNum); + +void mcpwm_set_output_polarity(RSI_MCPWM_T *pMCPWM, boolean_t polL, boolean_t polH); + +void mcpwm_interrupt_handler(RSI_MCPWM_T *pMCPWM, RSI_MCPWM_CALLBACK_T *pCallBack); + +rsi_error_t mcpwm_period_control_config(RSI_MCPWM_T *pMCPWM, uint32_t postScale, uint32_t preScale, uint8_t chnlNum); +void SysTick_Handler(void); +uint32_t MCPWM_PercentageToTicks(uint8_t percent, uint8_t chnl_num); +void MCPWM_SetChannelPeriod(uint32_t freq); +void RSI_MCPWM_PinMux(); + +#ifdef __cplusplus +} +#endif +#endif // RSI_PWM_H diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_qspi.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_qspi.h new file mode 100644 index 000000000..5609811b5 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_qspi.h @@ -0,0 +1,678 @@ +/******************************************************************************* +* @file rsi_qspi.h +* @brief +******************************************************************************* +* # License +* Copyright 2022 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +// Include Files + +#include "rsi_ccp_common.h" +#include "base_types.h" +#include "stdint.h" +#include "rsi_qspi_proto.h" + +#ifndef RSI_QSPI_H +#define RSI_QSPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +// QSPI defines +#define TA_QSPI_BASE_ADDRESS 0x10000000 +#define M4_QSPI_BASE_ADDRESS 0x12000000 +#define M4_QSPI_2_BASE_ADDRESS 0x12040000 +#define TA_QSPI_AUTOM_CHIP0_ADDRESS 0x04000000 +#define M4_QSPI_AUTOM_CHIP0_ADDRESS 0x08000000 + +#define NWP_FSM_BASE_ADDR 0x41300000 +#define MCU_NPSS_BASE_ADDR 0x24048000 +#define MCU_FSM_BASE_ADDR MCU_NPSS_BASE_ADDR + 0x100 +#define M4_BBFF_STORAGE1 *(volatile uint32_t *)(MCU_NPSS_BASE_ADDR + 0x0580) +#define M4_BBFF_STORAGE2 *(volatile uint32_t *)(MCU_NPSS_BASE_ADDR + 0x0584) +#define MCURET_BOOTSTATUS_REG *(volatile uint32_t *)(MCU_NPSS_BASE_ADDR + 0x604) +#define TA_BBFF_STORAGE1 *(volatile uint32_t *)(NWP_FSM_BASE_ADDR + 0x580) +#define TA_BBFF_STORAGE2 *(volatile uint32_t *)(NWP_FSM_BASE_ADDR + 0x584) + +// This structure contains qspi registers +#ifndef SLI_SI917B0 +struct qspi_reg_s { + volatile uint32_t QSPI_CLK_CONFIG_REG; // qspi reg + volatile uint32_t QSPI_BUS_MODE_REG; // qspi reg + volatile uint32_t QSPI_AUTO_CTRL_CONFIG_1_REG; // qspi reg + volatile uint32_t QSPI_AUTO_CTRL_CONFIG_2_REG; // qspi reg + volatile uint32_t QSPI_MANUAL_CONFIG_REG; // qspi reg + volatile uint32_t QSPI_MANUAL_CONFIG_2_REG; // qspi reg + + volatile uint32_t RESERVED_1; // qspi reg + volatile uint32_t QSPI_FIFO_THRESHOLD_REG; // qspi reg + volatile uint32_t QSPI_STATUS_REG; // qspi reg + volatile uint32_t QSPI_INTR_MASK_REG; // qspi reg + volatile uint32_t QSPI_INTR_UNMASK_REG; // qspi reg + volatile uint32_t QSPI_INTR_STS_REG; // qspi reg + volatile uint32_t QSPI_INTR_ACK_REG; // qspi reg + volatile uint32_t QSPI_STS_MC_REG; // qspi reg + volatile uint32_t QSPI_AUTO_CONFIG_1_CSN1_REG; // qspi reg + volatile uint32_t QSPI_AUTO_CONFIG_2_CSN1_REG; // qspi reg + volatile uint32_t QSPI_MANUAL_RD_WR_DATA_REG; // qspi reg + volatile uint32_t RESERVED_2[15]; // qspi reg + volatile uint32_t QSPI_MANUAL_WRITE_DATA_2_REG; // qspi reg + volatile uint32_t RESERVED_3[3]; // qspi reg + volatile uint32_t QSPI_AUTO_CONFIG3; + volatile uint32_t QSPI_AUTO_CONFIG3_CSN1; + volatile uint32_t RESERVED_4[6]; // qspi reg + volatile uint32_t OCTA_SPI_BUS_CONTROLLER; // qspi reg :2c + volatile uint32_t QSPI_AUTO_BASE_ADDR_UNMASK_CSN0; + volatile uint32_t RESERVED_7[3]; // qspi reg + volatile uint32_t OCTA_SPI_BUS_CONTROLLER2; // qspi reg:31 +#ifdef SLI_SI917 + volatile uint32_t QSPI_AES_CONFIG; // qspi reg + volatile uint32_t QSPI_AES_KEY_IV_VALID; // qspi reg + volatile uint32_t QSPI_AES_IV1_0_3; // qspi reg + volatile uint32_t QSPI_AES_IV1_4_7; // qspi reg + volatile uint32_t QSPI_AES_IV1_8_B; // qspi reg + volatile uint32_t QSPI_AES_IV1_C_F; // qspi reg + volatile uint32_t RESERVED_8; // qspi reg +#else + volatile uint32_t QSPI_AES_KEY_0_3; // qspi reg + volatile uint32_t QSPI_AES_KEY_4_7; // qspi reg + volatile uint32_t QSPI_AES_KEY_8_B; // qspi reg + volatile uint32_t QSPI_AES_KEY_C_F; // qspi reg + volatile uint32_t QSPI_AES_NONCE_0_3; // qspi reg + volatile uint32_t QSPI_AES_NONCE_4_7; // qspi reg + volatile uint32_t QSPI_AES_NONCE_8_B; // qspi reg +#endif + volatile uint32_t QSPI_AES_SEC_SEG_ADDR[4 * 2]; // qspi reg + volatile uint32_t RESERVED_6[6]; // qspi reg + volatile uint32_t QSPI_SEMI_AUTO_ADDR_REG; + volatile uint32_t QSPI_SEMI_AUTO_MODE_CONFIG_REG; + volatile uint32_t QSPI_SEMI_AUTO_MODE_CONFIG2_REG; + volatile uint32_t QSPI_BUS_MODE2_REG; + volatile uint32_t QSPI_AES_SEC_KEY_FRM_KH; + volatile uint32_t QSPI_AUTO_CONITNUE_FETCH_CTRL_REG; // qspi reg +#ifdef SLI_SI917 + volatile uint32_t QSPI_AES_KEY1_0_3; // qspi reg + volatile uint32_t QSPI_AES_KEY1_4_7; // qspi reg + volatile uint32_t QSPI_AES_KEY1_8_B; // qspi reg + volatile uint32_t QSPI_AES_KEY1_C_F; // qspi reg + volatile uint32_t QSPI_AES_KEY1_10_13; // qspi reg + volatile uint32_t QSPI_AES_KEY1_14_17; // qspi reg + volatile uint32_t QSPI_AES_KEY1_18_1B; // qspi reg + volatile uint32_t QSPI_AES_KEY1_1C_1F; // qspi reg + volatile uint32_t QSPI_AES_KEY2_0_3; // qspi reg + volatile uint32_t QSPI_AES_KEY2_4_7; // qspi reg + volatile uint32_t QSPI_AES_KEY2_8_B; // qspi reg + volatile uint32_t QSPI_AES_KEY2_C_F; // qspi reg + volatile uint32_t QSPI_AES_KEY2_10_13; // qspi reg + volatile uint32_t QSPI_AES_KEY2_14_17; // qspi reg + volatile uint32_t QSPI_AES_KEY2_18_1B; // qspi reg + volatile uint32_t QSPI_AES_KEY2_1C_1F; // qspi reg + volatile uint32_t QSPI_AES_IV2_0_3; // qspi reg + volatile uint32_t QSPI_AES_IV2_4_7; // qspi reg + volatile uint32_t QSPI_AES_IV2_8_B; // qspi reg + volatile uint32_t QSPI_AES_IV2_C_F; // qspi reg + volatile uint32_t QSPI_AES_CTXOUT_IV1_0_3; // qspi reg + volatile uint32_t QSPI_AES_CTXOUT_IV1_4_7; // qspi reg + volatile uint32_t QSPI_AES_CTXOUT_IV1_8_B; // qspi reg + volatile uint32_t QSPI_AES_CTXOUT_IV1_C_F; // qspi reg + volatile uint32_t QSPI_AES_CTXOUT_IV2_0_3; // qspi reg + volatile uint32_t QSPI_AES_CTXOUT_IV2_4_7; // qspi reg + volatile uint32_t QSPI_AES_CTXOUT_IV2_8_B; // qspi reg + volatile uint32_t QSPI_AES_CTXOUT_IV2_C_F; // qspi reg +#endif +}; + +#else +struct qspi_reg_s { + volatile uint32_t QSPI_CLK_CONFIG_REG; // qspi reg 0x00 + volatile uint32_t QSPI_BUS_MODE_REG; // qspi reg 0x04 + volatile uint32_t QSPI_AUTO_CTRL_CONFIG_1_REG; // qspi reg 0x08 + volatile uint32_t QSPI_AUTO_CTRL_CONFIG_2_REG; // qspi reg 0x0C + volatile uint32_t QSPI_MANUAL_CONFIG_REG; // qspi reg 0x10 + volatile uint32_t QSPI_MANUAL_CONFIG_2_REG; // qspi reg 0x14 + + volatile uint32_t RESERVED_1; // qspi reg 0x18 + volatile uint32_t QSPI_FIFO_THRESHOLD_REG; // qspi reg 0x1c + volatile uint32_t QSPI_STATUS_REG; // qspi reg 0x20 + volatile uint32_t QSPI_INTR_MASK_REG; // qspi reg 0x24 + volatile uint32_t QSPI_INTR_UNMASK_REG; // qspi reg 0x28 + volatile uint32_t QSPI_INTR_STS_REG; // qspi reg 0x2C + volatile uint32_t QSPI_INTR_ACK_REG; // qspi reg 0x30 + volatile uint32_t QSPI_STS_MC_REG; // qspi reg 0x34 + volatile uint32_t QSPI_AUTO_CONFIG_1_CSN1_REG; // qspi reg 0x38 + volatile uint32_t QSPI_AUTO_CONFIG_2_CSN1_REG; // qspi reg 0x3C + volatile uint32_t QSPI_MANUAL_RD_WR_DATA_REG; // qspi reg 0x40 + volatile uint32_t RESERVED_2[15]; // qspi reg -0x7c + volatile uint32_t QSPI_MANUAL_WRITE_DATA_2_REG; // qspi reg 0x80 + volatile uint32_t RESERVED_3[3]; // qspi reg -0x8C + volatile uint32_t QSPI_AUTO_CONFIG3; // qspi reg 0x90 + volatile uint32_t QSPI_AUTO_CONFIG3_CSN1; // qspi reg 0x94 + volatile uint32_t RESERVED_4[2]; // qspi reg -0x9C + + volatile uint32_t QSPI_AUTO_BASE_ADDR_CSN0; // qspi reg 0xA0 + volatile uint32_t QSPI_AUTO_BASE_ADDR_CSN1; // qspi reg 0xA4 + + volatile uint32_t RESERVED_5[2]; // qspi reg -0xAC + + volatile uint32_t OCTA_SPI_BUS_CONTROLLER; // qspi reg 0xB0 + volatile uint32_t QSPI_AUTO_BASE_ADDR_UNMASK_CSN0; // qspi reg 0xB4 + + volatile uint32_t QSPI_AUTO_BASE_ADDR_UNMASK_CSN1; // qspi reg 0xB8 + + volatile uint32_t RESERVED_6[2]; // qspi reg -0xC0 + volatile uint32_t OCTA_SPI_BUS_CONTROLLER2; // qspi reg 0xC4 + + volatile uint32_t QSPI_AES_CONFIG; // qspi reg 0xC8 + volatile uint32_t QSPI_AES_KEY_IV_VALID; // qspi reg 0xCC + + volatile uint32_t QSPI_CMNFLASH_STS; // qspi reg 0xD0 + + volatile uint32_t QSPI_AES_LB_DATA_0_3; // qspi reg 0xD4 + volatile uint32_t QSPI_AES_LB_DATA_4_7; // qspi reg 0xD8 + volatile uint32_t QSPI_AES_LB_DATA_8_B; // qspi reg 0xDC + volatile uint32_t QSPI_AES_LB_DATA_C_F; // qspi reg 0xE0 + + volatile uint32_t QSPI_AES_SEC_SEG_ADDR[4 * 2]; // qspi reg -0x100 + + volatile uint32_t QSPI_SRAM_CTRL_CSN0_REG; // qspi reg 0x104 + volatile uint32_t QSPI_SRAM_CTRL_CSN1_REG; // qspi reg 0x108 + volatile uint32_t QSPI_SRAM_CTRL_CSN2_REG; // qspi reg 0x10C + volatile uint32_t QSPI_SRAM_CTRL_CSN3_REG; // qspi reg 0x110 + + volatile uint32_t CCMP_LBK_CTRL_REG; // qspi reg 0x114 + volatile uint32_t RESERVED_7; // qspi reg -0x118 + + volatile uint32_t QSPI_SEMI_AUTO_ADDR_REG; // qspi reg 0x11C + volatile uint32_t QSPI_SEMI_AUTO_MODE_CONFIG_REG; // qspi reg 0x120 + volatile uint32_t QSPI_SEMI_AUTO_MODE_CONFIG2_REG; // qspi reg 0x124 + volatile uint32_t QSPI_BUS_MODE2_REG; // qspi reg 0x128 + volatile uint32_t QSPI_AES_SEC_KEY_FRM_KH; // qspi reg 0x12C + volatile uint32_t QSPI_AUTO_CONITNUE_FETCH_CTRL_REG; // qspi reg 0x130 + + volatile uint32_t QSPI_AES_KEY1_0_3; // qspi reg 0x134 + volatile uint32_t QSPI_AES_KEY1_4_7; // qspi reg 0x138 + volatile uint32_t QSPI_AES_KEY1_8_B; // qspi reg 0x13C + volatile uint32_t QSPI_AES_KEY1_C_F; // qspi reg 0x140 + volatile uint32_t QSPI_AES_KEY1_10_13; // qspi reg 0x144 + volatile uint32_t QSPI_AES_KEY1_14_17; // qspi reg 0x148 + volatile uint32_t QSPI_AES_KEY1_18_1B; // qspi reg 0x14C + volatile uint32_t QSPI_AES_KEY1_1C_1F; // qspi reg 0x150 + volatile uint32_t QSPI_AES_KEY2_0_3; // qspi reg 0x154 + volatile uint32_t QSPI_AES_KEY2_4_7; // qspi reg 0x158 + volatile uint32_t QSPI_AES_KEY2_8_B; // qspi reg 0x15C + volatile uint32_t QSPI_AES_KEY2_C_F; // qspi reg 0x160 + volatile uint32_t QSPI_AES_KEY2_10_13; // qspi reg 0x164 + volatile uint32_t QSPI_AES_KEY2_14_17; // qspi reg 0x168 + volatile uint32_t QSPI_AES_KEY2_18_1B; // qspi reg 0x16C + volatile uint32_t QSPI_AES_KEY2_1C_1F; // qspi reg 0x170 + volatile uint32_t QSPI_AES_IV1_0_3; // qspi reg 0x174 + volatile uint32_t QSPI_AES_IV1_4_7; // qspi reg 0x178 + volatile uint32_t QSPI_AES_IV1_8_B; // qspi reg 0x17C + volatile uint32_t QSPI_AES_IV1_C_F; // qspi reg 0x180 + volatile uint32_t QSPI_LB_STATUS; // qspi reg 0x184 +}; +#endif + +#define XMAX(x, y) (((x) > (y)) ? (x) : (y)) +#define XMIN(x, y) (((x) < (y)) ? (x) : (y)) + +#define QSPI_BASE_ADDRESS 0x12000000 +#define QSPI_AUTOM_CHIP0_ADDRESS 0x08000000 +#define QSPI_AUTOM_CHIP1_ADDRESS 0x09000000 +#define PAD_CONFIGURATION_BASE_ADDR 0x41380000 +#define TASS_CLK_PWR_CTRL_BASE_ADDR 0x41400000 +#define GPIO_BASE_ADDR 0x40200000 +#define DMA_BASE_ADDR 0x21000000 +#define M4SS_CLK_PWR_CTRL_BASE_ADDR 0x46000000 +#define M4GPIO_BASE_ADDR 0x46130000 +#define M4PAD_CONFIGURATION_BASE_ADDR 0x46004000 +#define M4PAD_SELECTION_BASE_ADDR 0x41300000 + +#define MISC_CONFIGURATION_REG 0x46008000 +#define M4SS_QSPI_OCTA_MODE_CTRL *(volatile uint32_t *)(MISC_CONFIGURATION_REG + 0x1B4) +#define M4SS_QSPI_RX_DLL_TEST_REG *(volatile uint32_t *)(MISC_CONFIGURATION_REG + 0x1C0) +#define M4SS_QSPI_TX_DLL_TEST_REG *(volatile uint32_t *)(MISC_CONFIGURATION_REG + 0x1BC) + +#define qspi_ddr_data_0 0 +#define qspi_ddr_data_1 1 +#define qspi_ddr_data_2 2 +#define qspi_ddr_data_3 3 +#define qspi_ddr_data_4 4 +#define qspi_ddr_data_5 5 +#define qspi_ddr_data_6 6 +#define qspi_ddr_data_7 7 +#define qspi_ddr_csn 8 +#define qspi_ddr_clk 9 +#define qspi_ddr_dqs 10 +#define smih_wp 11 + +#define CHNL_21 21 +#define CHNL_20 20 + +// Qspi register defines + +// cmd len will be 8 bits +#define CMD_LEN 8 +// reg bit +#define RD_FIFO_EMPTY BIT(7) +// reg bit +#define Q_QSPI_BUSY BIT(0) +// QSPI_MANUAL_CONFIG_REG bits +#define FULL_DUPLEX_EN BIT(22) +#define TAKE_LEN_FRM_REG BIT(21) +#define HW_CTRL_MODE BIT(25) +#define READ_TRIGGER BIT(2) +#define WRITE_TRIGGER BIT(1) +#define CSN_ACTIVE BIT(0) + +// QSPI_MANUAL_CONFIG_2_REG bits +#define QSPI_LOOP_BACK_MODE_EN BIT(14) +#define QSPI_MANUAL_DDR_PHASSE BIT(15) +#define QSPI_DDR_CLK_EN BIT(16) + +// QSPI_CLK_CONFIG_REG bits +#define QSPI_DLL_CALIB BIT(28) +#define QSPI_DLL_TX_EN BIT(21) +#define QSPI_DLL_RX_EN BIT(19) + +// QSPI_AUTO_CTRL_CONFIG_1_REG bits +#define EXTRA_BYTE_EN BIT(18) + +// QSPI_AUTO_CTRL_CONFIG_2_REG bits +#define AUTO_RD_SWAP BIT(0) + +// QSPI_SEMI_AUTO_MODE_CONFIG2_REG +#define SEMI_AUTO_MODE_EN BIT(12) +#define QSPI_SEMI_AUTO_RD_BUSY BIT(13) + +#define _1BYTE 0 +#define _2BYTE 1 +#define _4BYTE 3 + +// QSPI_STATUS_REG bits +#define HW_CTRLD_QSPI_MODE_CTRL_SCLK BIT(14) +#define AUTO_MODE_ENABLED BIT(12) +#define QSPI_AUTO_MODE BIT(11) +#define AUTO_MODE_FSM_IDLE_SCLK BIT(10) +#define QSPI_MANUAL_RD_CNT BIT(9) +#define QSPI_FIFO_AEMPTY_RFIFO_S BIT(8) +#define QSPI_FIFO_EMPTY_RFIFO_S BIT(7) +#define QSPI_FIFO_AFULL_RFIFO BIT(6) +#define QSPI_FIFO_FULL_RFIFO BIT(5) +#define QSPI_FIFO_AEMPTY_WFIFO BIT(4) +#define QSPI_FIFO_EMPTY_WFIFO BIT(3) +#define QSPI_FIFO_AFULL_WFIFO_S BIT(2) +#define QSPI_FIFO_FULL_WFIFO_S BIT(1) +#define BUSY BIT(0) + +#define QSPI_FIFO_DEPTH 16 +#define QSPI_FIFO_AFULL_TH 3 +#define QSPI_FIFO_AEMPTY_TH 3 + +// QSPI_BUS_MODE_REG bits +#define AUTO_CSN_BASED_ADDR_ENABLE BIT(7) +#define AUTO_MODE BIT(6) +#define QSPI_WRAP_EN BIT(5) +#define QSPI_PREFETCH_EN BIT(4) +#define QSPI_ULTRA_HIGH_SPEED_MODE_EN BIT(0) + +// QSPI_AUTO_CONFIG3 bits +#define QSPI_RD_INST_CSN0_MSB 24 +#define QSPI_CMD_SIZE_16BIT_CSN0 BIT(18) +#define QSPI_ADR_SIZE_32BIT_AUTO_MODE BIT(19) + +// QSPI_MANUAL_WRITE_DATA_2_REG bits +#define USE_PREV_LEN BIT(7) + +// OCTA_SPI_BUS_CONTRLLER_2 bits +#define DUAL_FLASH_MODE BIT(3) + +// FLASH CMDS + +// Write enable cmd +#define WREN 0x06 +#define WREN2 0xF9 +// Write disable cmd +#define WRDI 0x04 +#define WRDI2 0xFB +// Read status reg cmd +#define RDSR 0x05 +#define RDSR2 0xFA +// chip erase cmd +#define CHIP_ERASE 0xC7 +// block erase cmd +#define BLOCK_ERASE 0xD8 +// sector erase cmd +#define SECTOR_ERASE 0x20 +// high speed rd cmd +#define HISPEED_READ 0x0B +// rd cmd +#define READ 0x03 +//write config2 +#define WCFG2 0x72 + +// SST25 specific cmds + +// Write status reg cmd +#define WRSR 0x01 +#define WRSR2 0xFE +// Enable Write status reg cmd +#define EWSR 0x50 +// Auto address incremental rd cmd +#define AAI 0xAF +// Byte program cmd +#define BYTE_PROGRAM 0x02 + +// SST26 specific cmds + +// Enable quad IO +#define EQIO 0x38 +// Reset quad IO +#define RSTQIO 0xFF +// Enable STR octa +#define OPI_ENABLE 0X01 +// Enable DDR octa +#define DOPI_ENABLE 0x02 +// wrap : set burst +#define SET_BURST 0xC0 +// wrap : read cmd +#define READ_BURST 0x0C +// Jump : page index read +#define READ_PI 0x08 +// Jump : Index read +#define READ_I 0x09 +// Jump : Block Index read +#define READ_BI 0x10 +// Page program cmd +#define PAGE_PROGRAM 0x02 +// write suspend cmd +#define Write_Suspend 0xB0 +// write resume cmd +#define Write_Resume 0x30 +// read block protection reg +#define RBPR 0x72 +// Write block protection reg +#define WBPR 0x42 +// Lockdown block protection reg +#define LBPR 0x8D + +// WINBOND + AT + MACRONIX specific cmds + +// fast read dual output +#define FREAD_DUAL_O 0x3B +// fast read quad output +#define FREAD_QUAD_O 0x6B + +#define FREAD_QUAD_O_EB 0xEB + +// WINBOND + MACRONIX specific cmds + +// fast read dual IO +#define FREAD_DUAL_IO 0xBB +// fast read quad IO +#define FREAD_QUAD_IO 0xEB + +// WINBOND specific cmds + +// Octal word read (A7-A0 must be 00) +#define OCTAL_WREAD 0xE3 +// Enable high performance cmd +#define HI_PERFMNC 0xA3 + +// ATMEL specific cmds + +// write config reg +#define WCON 0x3E +// read config reg +#define RCON 0x3F +// supported upto 100MHz +#define HI_FREQ_SPI_READ 0x1B + +#define ATMEL_QEN BIT(7) + +// MACRONIX specific write cmds + +// Address and data in quad +#define QUAD_PAGE_PROGRAM 0x38 +#define DDR_DATA 16 +#define DDR_EXTRA_BYTE 15 +#define DDR_DUMMY 14 +#define DDR_ADDR 13 +#define DDR_CMD 17 + +#define OCTA_DDR_READ 0xEE +#define OCTA_DDR_READ_CMD2 0x11 + +#define OCTA_SDR_READ 0xEC +#define OCTA_SDR_READ_CMD2 0x13 + +// ATMEL + WINBOND specific write cmds + +// Only data in quad mode +#define QUAD_IN_PAGE_PROGRAM 0x32 + +// ATMEL specific write cmds + +// Data in dual +#define DUAL_IN_PAGE_PROGRAM 0xA2 + +// MICRON specific cmds +#define RD_LOCK_REG 0xE8 +#define WR_LOCK_REG 0xE5 +#define RD_FLAG_STS_REG 0x70 +#define CLR_FLAG_STS_REG 0x50 +#define RD_NONVOL_CON_REG 0xB5 +#define WR_NONVOL_CON_REG 0xB1 +#define RD_VOL_CON_REG 0x85 +#define WR_VOL_CON_REG 0x81 +#define RD_ENHN_VOL_CON_REG 0x65 +#define WR_ENHN_VOL_CON_REG 0x61 +#define DIS_XIP BIT(3) +#define XIP_MODE 0 + +// ADESTO specific cmds + +#define STS_BYT2 0x31 +#define STS_CTRL 0x71 + +#define ADEST_PROTECT_CMD 0x36 +#define ADEST_UNPROTECT_CMD 0x39 + +// Defines for arguments + +// disable hw ctrl +#define DIS_HW_CTRL 1 +// donot disable hw ctrl +#define DNT_DIS_HW_CTRL 0 + +// 32bit hsize +#define _32BIT 3 +// 24bit hsize is not supported, so reserved +// reserved 2 +// 16bit hsize +#define _16BIT 1 +// 8bit hsize +#define _8BIT 0 + +// cmd len will be 8 bits +#define QSPI_8BIT_LEN 8 +// cmd + 1 byte len +#define QSPI_16BIT_LEN 16 +// cmd + 24bit addr len +#define QSPI_32BIT_LEN 0 + +// OCTA_SPI_BUS_CONTROLLER2 bits +// initialises NONCE +#define NONCE_INIT BIT(1) +// enables global security +#define EN_SECURITY BIT(2) +// enables of sec per segment +#define EN_SEG_SEC 12 +// enable qspi to use key from kh +#define EN_KH_KEY BIT(18) + +// QSPI AES SEC KEY FROM KH bits +// secure key loading interval +#define LOAD_SEC_KEY_FRM_KH BIT(0) + +// LIST OF MACRO USED + +// Macro to Deassert CS +#define DEASSERT_CSN qspi_reg->QSPI_MANUAL_CONFIG_REG = ((qspi_reg->QSPI_MANUAL_CONFIG_REG & (~0x1FFFU)) | 0x1) + +// Macro to check Quad mode +#define CHK_QUAD_MODE (spi_config->spi_config_1.data_mode == QUAD_MODE) +// Macro to check DUAL mode +#define CHK_DUAL_MODE (spi_config->spi_config_1.data_mode == DUAL_MODE) +#define CHK_OCTA_MODE (spi_config->spi_config_1.data_mode == OCTA_MODE) + +//#define IS_QSPI_IN_OCTA (((qspi_reg->QSPI_BUS_MODE_REG & 0x6) >> 1) == OCTA_MODE) + +// Macro to provide protection byte for SST +#define SST_PROTECTION ((spi_config->spi_config_2.protection == EN_WR_PROT) ? 0xFF : 0) +// Macro to provide protection byte for WB +#define WB_PROT ((spi_config->spi_config_2.protection == EN_WR_PROT) ? 0x1C00 : 0) +// Macro to provide protection byte for MX +#define MX_PROT ((spi_config->spi_config_2.protection == EN_WR_PROT) ? 0x3C : 0) +// Macro to provide protection byte for AT +#define AT_PROT ((spi_config->spi_config_2.protection == EN_WR_PROT) ? 0xC : 0) +// Macro to get the position for D2 line data +#define GET_POS \ + ((spi_config->spi_config_2.cs_no == CHIP_THREE) ? 30 \ + : (spi_config->spi_config_2.cs_no == CHIP_TWO) ? 26 \ + : (spi_config->spi_config_2.cs_no == CHIP_ONE) ? 14 \ + : 10) + +#define GET_POS_D7_D4 \ + ((spi_config->spi_config_2.cs_no == CHIP_THREE) ? 24 \ + : (spi_config->spi_config_2.cs_no == CHIP_TWO) ? 16 \ + : (spi_config->spi_config_2.cs_no == CHIP_ONE) ? 8 \ + : 0) +// Macro to mask the d3 and d2 data bits +#define MASK_D3_D2(_POS) ~(0x3 << _POS) +#define MASK_D7_D4(_POS) ~(0xf << _POS) +// for 0xEB 0xE3 and 0xBB, 7th bit will be high so check for it +#define HI_PERFORMANCE_REQ (spi_config->spi_config_1.read_cmd & BIT(7)) + +// Macro to trigger QSPI to read from flash +#ifdef CHIP_9118 +#define READ_4M_FLASH(_NUM_BYTES, _CS_NO, Hsize) \ + qspi_reg->QSPI_MANUAL_CONFIG_REG = (qspi_reg->QSPI_MANUAL_CONFIG_REG & ~0xF8387FFF) | READ_TRIGGER | (_CS_NO << 13) \ + | ((_NUM_BYTES & 0x3FF) << 3) | (((_NUM_BYTES >> 10) & 0x1F) << 27) \ + | ((spi_config->spi_config_3.ddr_mode_en == 1) ? (BIT(21) | (Hsize << 19)) : 0) +#else +#define READ_4M_FLASH(_NUM_BYTES, _CS_NO, Hsize) \ + qspi_reg->QSPI_MANUAL_CONFIG_REG = (qspi_reg->QSPI_MANUAL_CONFIG_REG & ~0xF8387FFF) | READ_TRIGGER | (_CS_NO << 13) \ + | ((_NUM_BYTES & 0x3FF) << 3) | (((_NUM_BYTES >> 10) & 0x1F) << 27) \ + | (Hsize << 19) + +#endif +// Macro to return A8 bit in case 9bit addressing is required +#define A8_BIT ((spi_config->spi_config_2.addr_width == _9BIT_ADDR) ? ((addr & BIT(8)) << 3) : 0) + +// Macro to RETURN QSPI_BUS_SIZE from manual regs +#define QSPI_MANUAL_BUS_SIZE(_CHIP_SELECT) \ + (_CHIP_SELECT == CHIP_ZERO) ? ((qspi_reg->QSPI_BUS_MODE_REG & 0x6) >> 1) \ + : ((qspi_reg->QSPI_MANUAL_CONFIG_2_REG >> (8 + ((_CHIP_SELECT - 1) * 2))) & 0x3) +#ifdef CHIP_9118 +#define QSPI_CMD_DDR_MODE \ + (spi_config->spi_config_2.cs_no ? (qspi_reg->QSPI_AUTO_CONFIG3_CSN1 & BIT(DDR_CMD)) \ + : (qspi_reg->QSPI_AUTO_CONFIG3 & BIT(DDR_CMD))) +#define QSPI_DATA_DDR_MODE \ + (spi_config->spi_config_2.cs_no ? (qspi_reg->QSPI_AUTO_CONFIG3_CSN1 & BIT(DDR_CMD)) \ + : (qspi_reg->QSPI_AUTO_CONFIG3 & BIT(DDR_DATA))) +#define QSPI_DUAL_FLASH_MODE (qspi_reg->OCTA_SPI_BUS_CONTROLLER2 & DUAL_FLASH_MODE) +#else +#define QSPI_CMD_DDR_MODE 0 +#define QSPI_DATA_DDR_MODE 0 +#define QSPI_DUAL_FLASH_MODE 0 +#endif +// Macro to compute address width for manual mode based upon the addressing specified +#define ADDR_LEN (spi_config->spi_config_2.addr_width ? (spi_config->spi_config_2.addr_width * 8) : 8) +#define QSPI_32BIT_ADDR 32 +#define QSPI_8BIT_ADDR 8 +// Macro to compute address width for auto mode based upon addressing specified +#define AUTO_ADDR_WIDTH (((spi_config->spi_config_2.addr_width + 1) & 0x1) << 1) + +// Macro to check whether the addr violates page boundary +#define ODD_PAGE_BOUNDARY (addr & (page_size - 1)) + +// EXTRA_BYTE is currently hardcoded to 0xA0 +#define EXTRA_BYTE ((spi_config->spi_config_1.continuous) ? 0xA0 : 0x00) + +// number of dummy bytes required by the flash during a wrap/burst read command +#define NUM_DUMMY_BYTES_WRAP 1 +#define PROT_FROM_TOP BIT(3) + +#define HIGH_PERF_MODE BIT(1) +#define HSIZE_IN_BITS ((hsize + 1) * 8) + +// QSPI AES Decryption Defines +#define KEY_LEN_128 16 +#define KEY_LEN_256 32 +#ifdef SLI_SI917 +#define CTR_MODE 0x04 +#define XTS_MODE 0x80 +#ifndef SLI_SI917B0 +#define IV_VALID (0xf << 16) +#define KEY1_VALID (0xf << 0) +#define KEY2_VALID (0xf << 8) +#else +#define LB_IV_VALID (0xf << 8) +#define KEY1_VALID_128 (0xf0 << 0) //128-bit +#define KEY2_VALID_128 (0xf0 << 12) //128-bit +#define KEY1_VALID_256 (0xff << 0) //256-bit +#define KEY2_VALID_256 (0xff << 12) //256-bit +#endif +#define DECRYPT_KEY_CAL BIT(9) +#define KEY_FLIP_FOR_REG_INTF BIT(10) +#define KEY_FLIP_FOR_KH_INTF BIT(11) +#define SR2_READ 0x35 +#define QUAD_EN BIT(1) +#define EN_STANDALONE_AES BIT(15) +#define FLIP_IN_LB BIT(13) +#define QSPI_AES_DIN_READY BIT(2) +#define QSPI_AES_DOUT_VALID BIT(1) +#ifdef SLI_SI917B0 +#define KEY_SIZE_MASK (0x40000) +#define KEY_SIZE_256 BIT(16) +#define QSPI_KEY_SIZE_256 BIT(16) + +#define DEFAULT_AES_CONFIG (0x80) +#define DEFAULT_AES_SEC_KEY_FRM_KH (0x9 << 1) +#define DEFAULT_AES_KEY_IV_VALID (0x00) +#endif + +//XMC Flash +#define SR3_READ 0x15 +#define SR1_WRITE 0x1 +#define SR2_WRITE 0x31 +#define SR3_WRITE 0x11 +#endif + +#ifdef __cplusplus +} +#endif +void initialise_m4_efuse_in_io_mode(); +void rsi_cmemcpy(uint8_t *dst, uint8_t *src, uint32_t len); +void RSI_QSPI_GPDMA_Init(uint32_t hsize, uint32_t ch_no, uint32_t mode); +void RSI_QSPI_GPDMA_ReadFromFifo(uint32_t src, uint32_t dst, uint32_t len, uint32_t ch_no); +void RSI_QSPI_ReadFromFifo(uint32_t udma_read, void *udmaHandle, void *gpdmaHandle, uint32_t ch_no); +void RSI_QSPI_AutoModeEn(qspi_reg_t *qspi_reg); +void RSI_QSPI_ConfigQspiDll(spi_config_t *spi_config, qspi_reg_t *qspi_reg); +void RSI_QSPI_TIMER_Config(void); +void qspi_semi_auto_mode_config(qspi_reg_t *qspi_reg, uint32_t addr, uint32_t hsize, uint32_t bsize, uint32_t length); +void RSI_QSPI_ProtectAdesto(spi_config_t *spi_config, qspi_reg_t *qspi_reg, uint32_t protection, uint32_t cs_no); + +#endif // RSI_QSPI_H diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_qspi_proto.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_qspi_proto.h new file mode 100644 index 000000000..c1fbf39bf --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_qspi_proto.h @@ -0,0 +1,674 @@ +/******************************************************************************* +* @file rsi_qspi_proto.h +* @brief +******************************************************************************* +* # License +* Copyright 2022 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +// Include Files + +#include "rsi_ccp_common.h" +#include "base_types.h" + +#ifndef QSPI_PROTO_H +#define QSPI_PROTO_H + +#ifdef __cplusplus +extern "C" { +#endif + +// GPIO register bit position related defines +#define GPIO_0_TO_5 0 +#define GPIO_6_TO_11 1 +#define GPIO_46_TO_51 2 +#define GPIO_52_TO_57 3 +#define GPIO_58_TO_63 4 +// TA OCTA/DUAL combinations +#define GPIO_0_AND_58 5 +#define GPIO_6_AND_58 6 +#define GPIO_46_AND_58 7 +// M4 OCTA/DUAL combinations +#define GPIO_0_AND_52 8 +#define GPIO_6_AND_52 9 +#define GPIO_46_AND_52 10 +#define NOT_USING 11 // Not applicable +#define GPIO_58_AND_52 12 +#define GPIO_DDR_PADS 13 + +#define M4SS_PAD_CONFIG_REG(x) *(volatile uint32_t *)(0x46004000 + 4 * (x)) // REN enable bit(this should be enable) +#define M4_DDR_PAD_CONFIG(x) *(volatile uint32_t *)(0x46006000 + ((x)*4)) +// Pad config(P2 P1) +// 00 - Hi-Z, 01 - Pullup, 10 - PullDown, 11 - Repeater +#define PAD_CONFIG_P2 BIT(7) +#define PAD_CONFIG_P1 BIT(6) + +#define PADSELECTION \ + (*(volatile uint32_t *)(0x41300000 + 0x610)) // PAD selection (0 t0 21) A value of 1 on this gives control to M4SS +// Note BIT(0) to BIT(7) are reserved for channel no +#define DEFAULT_DESC_MODE BIT(8) +#define USE_UDMA_MODE BIT(9) + +typedef enum qspi_mode_e { NONE = 0, READ_MODE, WRITE_MODE } qspi_mode_t; + +// Structure to qspi standalone encrypt/decrypt configs +typedef struct qspi_standalone_config_s { + uint8_t aes_mode; // AES mode + bool encrypt; // 0 = Encrypt, 1 = Decrypt + bool kh_enable; // 1 = Pick the key from keyholder, 0 = pass the key + uint32_t *iv; // flash offset where data stored + uint32_t *key1; // Pass key1 if kh_enable = 0 + uint32_t *key2; // Pass key1 if kh_enable = 0 and 32 byte key + uint32_t key_len; // Key len i.e 16 or 32 bytes + uint32_t flip_data; // writing 1 to this Flips the 32-bit endian for data in standalone mode +} qspi_standalone_config_t; + +extern qspi_mode_t qspi_mode_g; + +typedef struct qspi_reg_s qspi_reg_t; +// This structure members are used to configure qspi +typedef struct spi_config_1_s { + // QSPI operation modes, all modes are single, dual or quad + + uint32_t inst_mode : 2; // instruction will be sent in this mode + uint32_t addr_mode : 2; // addr will be sent in this mode + uint32_t data_mode : 2; // data will be sent/received in this mode + uint32_t dummy_mode : 2; // dummy bytes will be sent/received in this mode + uint32_t extra_byte_mode : 2; // extra bytes will be sent in this mode + // SPI mode +#define SINGLE_MODE 0 + // dual mode +#define DUAL_MODE 1 + // quad mode +#define QUAD_MODE 2 +#define OCTA_MODE 3 + + uint32_t prefetch_en : 1; // prefetch enable +// prefetch will be enabled +#define EN_PREFETCH 1 +// prefetch will be disabled +#define DIS_PREFETCH 0 + + uint32_t dummy_W_or_R : 1; // dummy writes or read select +// dummy's are read +#define DUMMY_READS 0 +// dummy's are written +#define DUMMY_WRITES 1 + + uint32_t extra_byte_en : 1; // Enable extra byte + // Extra byte will be enabled +#define EN_EXTRA_BYTE + // Extra byte will be disabled +#define DIS_EXTRA_BYTE + + uint32_t d3d2_data : 2; // Data on D3 and D2 line in SPI or DUAL mode + + uint32_t continuous : 1; // continuous mode select + // continuous mode is selected +#define CONTINUOUS 1 + // discontinuous mode is selected +#define DIS_CONTINUOUS 0 + + uint32_t read_cmd : 8; // read cmd to be used + + uint32_t flash_type : 4; // flash defines + // sst spi flash +#define FREAD_QUAD_O 0x6B + +#define FREAD_QUAD_O_EB 0xEB + +// WINBOND + MACRONIX specific cmds + +// fast read dual IO +#define FREAD_DUAL_IO 0xBB +// fast read quad IO +#define FREAD_QUAD_IO 0xEB +#define SST_SPI_FLASH 0 + // sst dual flash +#define SST_DUAL_FLASH 1 + // sst quad flash +#define SST_QUAD_FLASH 2 + // Winbond quad flash +#define WBOND_QUAD_FLASH 3 + // Atmel quad flash +#define AT_QUAD_FLASH 4 + // macronix quad flash +#define MX_QUAD_FLASH 5 + // cFeon quad flash +#define EON_QUAD_FLASH 6 + // Micron quad flash +#define MICRON_QUAD_FLASH 7 + // Giga Device flash +#define GIGA_DEVICE_FLASH 8 + // macronix octa flash +#define MX_OCTA_FLASH 9 + // Adesto octa flash +#define ADESTO_OCTA_FLASH 10 + +#ifdef SLI_SI917 + // Adesto quad flash +#define ADESTO_QUAD_FLASH 11 + //ISSI flash +#define ISSI_FLASH 12 + + //XMC fash +#define XMC_FLASH 13 + +#endif + uint32_t no_of_dummy_bytes : 4; // no_of_dummy_bytes to be used for read operations +} spi_config_1_t; + +// This structure members are used to configure qspi +typedef struct spi_config_2_s { + + uint32_t auto_mode : 1; // mode select +// Auto mode selection +#define EN_AUTO_MODE 1 + // Manual mode selection +#define EN_MANUAL_MODE 0 + + uint32_t cs_no : 2; // QSPI chip_select +// cs-0 +#define CHIP_ZERO 0 +// cs-1 +#define CHIP_ONE 1 +// cs-2 +#define CHIP_TWO 2 +// cs-3 +#define CHIP_THREE 3 + + uint32_t reserved1 : 1; // Jump Enable +// Enables jump +#define EN_JUMP 1 +// Disables jump +#define DIS_JUMP 0 + + uint32_t neg_edge_sampling : 1; // For High speed mode, sample at neg edge +// enables neg edge sampling +#define NEG_EDGE_SAMPLING 1 +// enables pos edge sampling +#define POS_EDGE_SAMPLING 0 + + uint32_t qspi_clk_en : 1; // qspi clk select +// full time clk will be provided +#define QSPI_FULL_TIME_CLK 1 +// dynamic clk gating will be enabled +#define QSPI_DYNAMIC_CLK 0 + + uint32_t protection : 2; // flash protection select +// enable write protection +#define EN_WR_PROT 2 +// remove write protection +#define REM_WR_PROT 1 +// no change to wr protection +#define DNT_REM_WR_PROT 0 + + uint32_t dma_mode : 1; // dma mode enable +// use dma only in manaul mode +#define DMA_MODE 1 +// dma will not be used +#define NO_DMA 0 + + uint32_t swap_en : 1; // swap enable for w/r +// swap will be enabled +#define SWAP 1 +// swap will be disabled +#define NO_SWAP 0 + + uint32_t full_duplex : 2; // full duplex mode select +// do nothing for full duplex +#define IGNORE_FULL_DUPLEX 2 +// enable full duplex +#define EN_FULL_DUPLEX 1 +// disable full duplex +#define DIS_FULL_DUPLEX 0 + + uint32_t wrap_len_in_bytes : 3; // wrap len to be used +// wrap is diabled +#define NO_WRAP 7 +// 8 byte wrap will be used +#define SST_8BYTE_WRAP 0 +// 16 byte wrap will be used +#define SST_16BYTE_WRAP 1 +// 32 byte wrap will be used +#define SST_32BYTE_WRAP 2 +// 64 byte wrap will be used +#define SST_64BYTE_WRAP 3 + +// 16 byte wrap will be used +#define MICRON_16BYTE_WRAP 0 +// 32 byte wrap will be used +#define MICRON_32BYTE_WRAP 1 +// 64 byte wrap will be used +#define MICRON_64BYTE_WRAP 2 + + uint32_t addr_width_valid : 1; + // mode 3 clk will be used + // mode 0 clk will be used + + uint32_t addr_width : 3; // addr width to used +// 32 bit addr is configured +#define _32BIT_ADDR 4 +// 24 bit addr is configured +#define _24BIT_ADDR 3 +// 16 bit addr is configured +#define _16BIT_ADDR 2 +// 9 bit addr is configured +#define _9BIT_ADDR 1 +// 8 bit addr is configured +#define _8BIT_ADDR 0 + +#define MANUAL_DUMMY_BYTE_OR_BIT_MODE BIT(25) +#define DUMMY_BYTE_OR_BIT_MODE BIT(0) + uint32_t dummy_cycles_for_controller : 2; + + uint32_t reserved2 : 6; + // uint32 jump_inst : 8; // Instruction to be used in case of jump + + uint32_t pinset_valid : 1; + + uint32_t flash_pinset : 4; // width of memory protection reg for sst flashes + +} spi_config_2_t; + +// This structure members are used to configure qspi +typedef struct spi_config_3_s { +#define CONTINUE_FETCH_EN BIT(12) +#define WORD_SWAP_EN 20 + uint32_t en_word_swap : 1; + uint32_t _16bit_cmd_valid : 1; + uint32_t _16bit_rd_cmd_msb : 8; + uint32_t xip_mode : 1; + uint32_t no_of_dummy_bytes_wrap : 4; // no_of_dummy_bytes to be used for wrap operations +#ifdef CHIP_9118 + uint32_t ddr_mode_en : 1; +#else + uint32_t reserved : 1; +#endif + uint32_t wr_cmd : 8; + uint32_t wr_inst_mode : 2; + uint32_t wr_addr_mode : 2; + uint32_t wr_data_mode : 2; + uint32_t dummys_4_jump : 2; // no_of_dummy_bytes in case of jump instruction +} spi_config_3_t; + +typedef struct spi_config_4_s { + uint32_t _16bit_wr_cmd_msb : 8; + uint32_t high_perf_mode_en : 1; //used for high performance mode not ddr + uint32_t qspi_loop_back_mode_en : 1; +#ifdef CHIP_9118 + uint32_t qspi_manual_ddr_phasse : 1; + uint32_t ddr_data_mode : 1; + uint32_t ddr_inst_mode : 1; + uint32_t ddr_addr_mode : 1; + uint32_t ddr_dummy_mode : 1; + uint32_t ddr_extra_byte : 1; +#else + uint32_t reserved : 1; + uint32_t reserved1 : 1; + uint32_t reserved2 : 1; + uint32_t reserved3 : 1; + uint32_t reserved4 : 1; + uint32_t reserved5 : 1; +#endif + uint32_t dual_flash_mode : 1; + uint32_t secondary_csn : 1; + uint32_t polarity_mode : 1; + uint32_t valid_prot_bits : 4; + uint32_t no_of_ms_dummy_bytes : 4; +#ifdef CHIP_9118 + uint32_t ddr_dll_en : 1; +#else + uint32_t reserved6 : 1; +#endif + uint32_t continue_fetch_en : 1; + uint32_t dma_write : 1; + uint32_t prot_top_bottom : 1; + uint32_t auto_csn_based_addr_en : 1; +} spi_config_4_t; +typedef struct spi_config_5_s { + uint32_t block_erase_cmd : 16; + uint32_t busy_bit_pos : 3; + uint32_t d7_d4_data : 4; + uint32_t dummy_bytes_for_rdsr : 4; + uint32_t reset_type : 5; +} spi_config_5_t; + +typedef struct spi_config_6_s { + uint32_t chip_erase_cmd : 16; + uint32_t sector_erase_cmd : 16; +} spi_config_6_t; + +typedef struct spi_config_7_s { + uint32_t status_reg_write_cmd : 16; + uint32_t status_reg_read_cmd : 16; +} spi_config_7_t; + +// This structure has two daughter structures to configure qspi +typedef struct spi_config_s { + spi_config_1_t spi_config_1; // daughter structure 1 + spi_config_2_t spi_config_2; // daughter structure 2 + spi_config_3_t spi_config_3; // daughter structure 3 + spi_config_4_t spi_config_4; // daughter structure 4 + spi_config_5_t spi_config_5; // daughter structure 5 + spi_config_6_t spi_config_6; // daughter structure 5 + spi_config_7_t spi_config_7; // daughter structure 5 +} spi_config_t; + +typedef const struct qspi_func_s qspi_func_t; + +struct qspi_func_s { + + void (*qspi_write_to_flash)(qspi_reg_t *qspi_reg, uint32_t len_in_bits, uint32_t cmd_addr_data, uint32_t cs_no); + + void (*qspi_switch_qspi2)(qspi_reg_t *qspi_reg, uint32_t mode, uint32_t cs_no); + + uint32_t (*qspi_wait_flash_status_Idle)(qspi_reg_t *qspi_reg, spi_config_t *spi_config, uint32_t wr_reg_delay_ms); + + void (*qspi_enable_status_reg_write)(qspi_reg_t *qspi_reg, + uint32_t flash_type, + spi_config_t *spi_config, + uint32_t cs_no); + + void (*qspi_status_reg_write)(qspi_reg_t *qspi_reg, + uint32_t write_value, + spi_config_t *spi_config, + uint32_t wr_reg_delay_ms); + + uint32_t (*qspi_flash_reg_read)(qspi_reg_t *qspi_reg, uint8_t reg_read_cmd, uint32_t cs_no, spi_config_t *spi_config); + + void (*qspi_flash_reg_write)(qspi_reg_t *qspi_reg, + uint32_t reg_write_cmd, + uint32_t reg_write_value, + uint32_t cs_no, + uint32_t wr_reg_delay_ms); + + void (*qspi_set_flash_mode)(qspi_reg_t *qspi_reg, + uint32_t data_mode, + uint32_t cs_no, + uint32_t ddr_en, + uint32_t flash_type); + + void (*qspi_config_qflash4_read)(qspi_reg_t *qspi_reg, spi_config_t *spi_config, uint32_t addr); + + void (*qspi_manual_read)(qspi_reg_t *qspi_reg, + spi_config_t *spi_config, + uint32_t addr, + uint8_t *data, + uint32_t hsize, + uint32_t len_in_bytes, + uint32_t dma_flags, + void *udmaHandle, + void *rpdmaHandle); + + void (*qspi_auto_init)(qspi_reg_t *qspi_reg, spi_config_t *spi_config); + + void (*qspi_auto_read)(uint32_t cs_no, + uint32_t addr, + uint8_t *data, + uint32_t hsize, + uint32_t len_in_bytes, + spi_config_t *spi_config, + uint32_t dma_flags); + + void (*qspi_flash_init)(qspi_reg_t *qspi_reg, spi_config_t *spi_config, uint32_t wr_reg_delay_ms); + + void (*qspi_spi_init)(qspi_reg_t *qspi_reg, + spi_config_t *spi_config, + uint32_t RSI_QSPI_FlashInit_req, + uint32_t wr_reg_delay_ms, + uint8_t fifo_thrsld); + + void (*qspi_spi_erase)(qspi_reg_t *qspi_reg, + spi_config_t *spi_config, + uint32_t erase_cmd, + uint32_t blk_sec_addr, + uint32_t dis_hw_ctrl, + uint32_t wr_reg_delay_ms); + + uint32_t (*qspi_spi_write)(qspi_reg_t *qspi_reg, + spi_config_t *spi_config, + uint32_t write_cmd, + uint32_t addr, + uint8_t *data, + uint32_t len_in_bytes, + uint16_t page_size, + uint32_t hsize, + uint32_t dis_hw_ctrl, + uint32_t wr_reg_delay_ms, + uint32_t check_en, + uint32_t dma_flags, + void *udmaHandle, + void *rpdmaHandle); + + void (*qspi_spi_read)(qspi_reg_t *qspi_reg, + spi_config_t *spi_config, + uint32_t addr, + uint8_t *data, + uint32_t hsize, + uint32_t len_in_bytes, + uint32_t dma_flags, + void *udmaHandle, + void *rpdmaHandle); + void (*RSI_QSPI_ConfigureQspiRead)(spi_config_t *spi_config, qspi_func_t *qspi_func); + + void (*RSI_QSPI_ConfigureQspiWrite)(spi_config_t *spi_config, qspi_func_t *qspi_func); + void (*qspi_usleep)(uint32_t delay_us); // function ptr for halting processor for delay (us) specified + + void (*qspi_write_block_protect)(qspi_reg_t *qspi_reg, + uint32_t protect, + uint32_t cs_no, + uint32_t num_prot_bytes, + uint32_t wr_reg_delay_ms); + +#ifdef SLI_SI917 +#ifdef SLI_SI917B0 + void (*qspi_qspiload_key)(qspi_reg_t *qspi_reg, + uint8_t mode, + uint32_t *key1, + uint32_t *key2, + uint32_t key_len, + uint32_t kh_enable); +#else + void (*qspi_qspiload_key)(qspi_reg_t *qspi_reg, uint8_t mode, uint32_t *key, uint32_t kh_enable); +#endif +#else + void (*qspi_qspiload_key)(qspi_reg_t *qspi_reg, uint32_t *key, uint32_t kh_enable); +#endif + void (*qspi_qspiload_nonce)(qspi_reg_t *qspi_reg, uint32_t *nonce); + void (*qspi_seg_sec_en)(qspi_reg_t *qspi_reg, uint32_t seg_no, uint32_t start_addr, uint32_t end_addr); + void (*qspi_status_control_reg_write)(spi_config_t *spi_config, + qspi_reg_t *qspi_reg, + uint16_t write_command, + uint32_t addr, + uint16_t write_value, + uint32_t cs_no, + uint32_t wr_reg_delay_ms); + void (*qspi_flash_protection)(spi_config_t *spi_config, + qspi_reg_t *qspi_reg, + uint32_t protection, + uint32_t wr_reg_delay_ms); + + void (*RSI_QSPI_ConfigQspiDll)(spi_config_t *spi_config, qspi_reg_t *qspi_reg); + + void (*RSI_QSPI_ResetFlash)(qspi_reg_t *qspi_reg, uint32_t cs_no); + + void (*RSI_QSPI_UpdateOperatingMode_and_ResetType)(qspi_reg_t *qspi_reg, uint32_t operating_mode); +}; + +// SPI API LIST + +uint32_t qspi_flash_reg_read(qspi_reg_t *qspi_reg, uint8_t reg_read_cmd, uint32_t cs_no, spi_config_t *spi_config); + +void qspi_status_reg_write(qspi_reg_t *qspi_reg, + uint32_t write_value, + spi_config_t *spi_config, + uint32_t wr_reg_delay_ms); + +void qspi_enable_status_reg_write(qspi_reg_t *qspi_reg, uint32_t flash_type, spi_config_t *spi_config, uint32_t cs_no); + +uint32_t qspi_wait_flash_status_Idle(qspi_reg_t *qspi_reg, spi_config_t *spi_config, uint32_t wr_reg_delay_ms); + +void qspi_spi_init(qspi_reg_t *qspi_reg, + spi_config_t *spi_config, + uint32_t flash_init_req, + uint32_t wr_reg_delay_ms, + uint8_t fifo_thrsld); +#define FLASH_INIT_REQ 1 +#define SKIP_FLASH_INIT 0 + +void qspi_spi_erase(qspi_reg_t *qspi_reg, + spi_config_t *spi_config, + uint32_t erase_cmd, + uint32_t blk_sec_addr, + uint32_t dis_hw_ctrl, + uint32_t wr_reg_delay_ms); +// chip erase cmd +#define CHIP_ERASE 0xC7 +// block erase cmd +#define BLOCK_ERASE 0xD8 +// sector erase cmd +#define SECTOR_ERASE 0x20 + +// disable hw ctrl +#define DIS_HW_CTRL 1 +// donot disable hw ctrl +#define DNT_DIS_HW_CTRL 0 + +// 32bit hsize +#define _32BIT 3 +// 24bit hsize is not supported, so reserved +// reserved 2 +// 16bit hsize +#define _16BIT 1 +// 8bit hsize +#define _8BIT 0 + +uint32_t qspi_spi_write(qspi_reg_t *qspi_reg, + spi_config_t *spi_config, + uint32_t write_cmd, + uint32_t addr, + uint8_t *data, + uint32_t len_in_bytes, + uint16_t page_size, + uint32_t hsize, + uint32_t dis_hw_ctrl, + uint32_t wr_reg_delay_ms, + uint32_t check_en, + uint32_t dma_flags, + void *udmaHandle, + void *rpdmaHandle); + +void qspi_spi_read(qspi_reg_t *qspi_reg, + spi_config_t *spi_config, + uint32_t addr, + uint8_t *data, + uint32_t hsize, + uint32_t len_in_bytes, + uint32_t dma_flags, + void *udmaHandle, + void *rpdmaHandle); + +uint32_t RSI_QSPI_Aes_Encrypt_Decrypt_Standalone(qspi_reg_t *qspi_reg, + qspi_standalone_config_t *configs, + uint32_t *in_data, + uint32_t *out_data, + uint32_t data_length); + +// ROM API Fuctions + +void qspi_write_block_protect(qspi_reg_t *qspi_reg, + uint32_t protect, + uint32_t cs_no, + uint32_t num_prot_bytes, + uint32_t wr_reg_delay_ms); +void qspi_usleep(uint32_t delay_us); // function ptr for halting processor for delay (us) specified +void qspi_auto_init(qspi_reg_t *qspi_reg, spi_config_t *spi_config); +void qspi_set_flash_mode(qspi_reg_t *qspi_reg, + uint32_t data_mode, + uint32_t cs_no, + uint32_t ddr_en, + uint32_t flash_type); + +void qspi_write_to_flash(qspi_reg_t *qspi_reg, uint32_t len_in_bits, uint32_t cmd_addr_data, uint32_t cs_no); + +void qspi_switch_qspi2(qspi_reg_t *qspi_reg, uint32_t mode, uint32_t cs_no); + +void qspi_flash_reg_write(qspi_reg_t *qspi_reg, + uint32_t reg_write_cmd, + uint32_t reg_write_value, + uint32_t cs_no, + uint32_t wr_reg_delay_ms); + +void qspi_config_qflash4_read(qspi_reg_t *qspi_reg, spi_config_t *spi_config, uint32_t addr); + +void qspi_manual_read(qspi_reg_t *qspi_reg, + spi_config_t *spi_config, + uint32_t addr, + uint8_t *data, + uint32_t hsize, + uint32_t len_in_bytes, + uint32_t dma_flags, + void *udmaHandle, + void *rpdmaHandle); + +void qspi_auto_read(uint32_t cs_no, + uint32_t addr, + uint8_t *data, + uint32_t hsize, + uint32_t len_in_bytes, + spi_config_t *spi_config, + uint32_t dma_flags); + +void qspi_flash_init(qspi_reg_t *qspi_reg, spi_config_t *spi_config, uint32_t wr_reg_delay_ms); + +#ifdef SLI_SI917 +#ifdef SLI_SI917B0 +void qspi_qspiload_key(qspi_reg_t *qspi_reg, + uint8_t mode, + uint32_t *key1, + uint32_t *key2, + uint32_t key_len, + uint32_t kh_enable); +#else +void qspi_qspiload_key(qspi_reg_t *qspi_reg, uint8_t mode, uint32_t *key, uint32_t kh_enable); +#endif +#else +void qspi_qspiload_key(qspi_reg_t *qspi_reg, uint32_t *key, uint32_t kh_enable); +#endif + +void qspi_qspiload_nonce(qspi_reg_t *qspi_reg, uint32_t *nonce); + +void qspi_seg_sec_en(qspi_reg_t *qspi_reg, uint32_t seg_no, uint32_t start_addr, uint32_t end_addr); +void qspi_status_control_reg_write(spi_config_t *spi_config, + qspi_reg_t *qspi_reg, + uint16_t write_command, + uint32_t addr, + uint16_t write_value, + uint32_t cs_no, + uint32_t wr_reg_delay_ms); +void qspi_flash_protection(spi_config_t *spi_config, + qspi_reg_t *qspi_reg, + uint32_t protection, + uint32_t wr_reg_delay_ms); + +void RSI_QSPI_ResetFlash(qspi_reg_t *qspi_reg, uint32_t cs_no); + +void RSI_QSPI_UpdateOperatingMode_and_ResetType(qspi_reg_t *qspi_reg, uint32_t operating_mode); + +extern spi_config_t spi_default_config; + +#ifdef __cplusplus +} +#endif + +#endif // QSPI_PROTO_H diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_rng.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_rng.h new file mode 100644 index 000000000..5b0f0d8c3 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_rng.h @@ -0,0 +1,43 @@ +/******************************************************************************* +* @file rsi_rng.h +* @brief +******************************************************************************* +* # License +* Copyright 2022 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +//Include Files + +#include "rsi_ccp_common.h" +#include "base_types.h" + +#ifndef RSI_RNG_H +#define RSI_RNG_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define RSI_RNG_TRUE_RANDOM 0 +#define RSI_RNG_PSEUDO_RANDOM 1 + +uint32_t rng_start(HWRNG_Type *pRNG, uint8_t rng_mode); +void rng_stop(HWRNG_Type *pRNG); +void rng_get_bytes(HWRNG_Type *pRNG, uint32_t *random_bytes, uint32_t number_of_bytes); + +#define HWRNG_CLK_ENABLE 0x400000 + +#ifdef __cplusplus +} +#endif + +#endif // RSI_RNG_H diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_timers.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_timers.h new file mode 100644 index 000000000..69ba02400 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_timers.h @@ -0,0 +1,357 @@ +/******************************************************************************* +* @file rsi_timers.h +* @brief +******************************************************************************* +* # License +* Copyright 2022 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +//Include Files + +#include "rsi_ccp_common.h" +#include "rsi_error.h" + +#ifndef RSI_TIMERS_H +#define RSI_TIMERS_H + +#ifdef __cplusplus +extern "C" { +#endif + +// LOCAL OR GLOBAL DEFINES + +#define RSI_TIMERS_API_VERSION RSI_DRIVER_VERSION_MAJOR_MINOR(2, 00) // API version 0.1 +#define RSI_TIMERS_DRV_VERSION RSI_DRIVER_VERSION_MAJOR_MINOR(00, 01) // driver version 0.1 + +#define MICRO_SEC_MODE 1 +#define _256_MICRO_SEC_MODE 2 +#define COUNTER_DOWN_MODE 0 + +// TIMERS Events +#define RSI_TIMERS_EVENT_TIMER0_TIMEOUT (1UL << 0) // Timer0 timeout interrupt +#define RSI_TIMERS_EVENT_TIMER1_TIMEOUT (1UL << 1) // Timer1 timeout interrupt +#define RSI_TIMERS_EVENT_TIMER2_TIMEOUT (1UL << 2) // Timer2 timeout interrupt +#define RSI_TIMERS_EVENT_TIMER3_TIMEOUT (1UL << 3) // Timer3 timeout interrupt + +#define TIMER_MODE 0x18 + +// Example defines +#define TIMER_0 0 +#define TIMER_1 1 +#define TIMER_2 2 +#define TIMER_3 3 + +#define ULP_TIMER_RF_REF_CLK 0 +#define ULP_TIMER_ULP_32KHZ_RO_CLK 1 +#define ULP_TIMER_ULP_32KHZ_RC_CLK 2 +#define ULP_TIMER_ULP_32KHZ_XTAL_CLK 3 +#define ULP_TIMER_ULP_32MHZ_RC_CLK 4 +#define ULP_TIMER_ULP_20MHZ_RO_CLK 5 +#define ULP_TIMER_SOC_CLK 6 + +#define ULP_TIMER_CLK_DIV_FACT 0 + +#define PERIODIC_TIMER 1 +#define ONESHOT_TIMER 0 + +typedef TIMERS_Type RSI_TIMERS_T; + +// brief TIMERS Driver Capabilities. +typedef struct { + uint32_t timerCount : 4; // Number of Timers + uint32_t microSecMode : 1; // supports Micro second mode +} RSI_TIMERS_CAPABILITIES_T; + +/// @brief Enumeration to represent ulp-timer direction +typedef enum { + DOWN_COUNTER, ///< For ULP Timer up-counting direction + UP_COUNTER, ///< For ULP Timer down-counting direction + LAST_DIRECTION, ///< Last member of enum for validation +} ulp_timer_dir_t; + +/*===================================================*/ +/** + * @fn rsi_error_t RSI_TIMERS_SetDirection(RSI_TIMERS_T *pTIMER, uint8_t timerNum, boolean_t countDir) + * @brief This API is used to set direction of the timer + * @param[in] pTIMER : Pointer to the TIMERS instance register area + * @param[in] timerNum : Timer number(0 to 3) + * @param[in] countDir : counter direction + * - \ref UP_COUNTER + * - \ref DOWN_COUNTER + * @return return the timer error code + */ +STATIC INLINE rsi_error_t RSI_TIMERS_SetDirection(RSI_TIMERS_T *pTIMER, uint8_t timerNum, ulp_timer_dir_t countDir) +{ + if (timerNum <= TIMER_3) { + if (countDir == UP_COUNTER) { + pTIMER->MATCH_CTRL[timerNum].MCUULP_TMR_CNTRL_b.COUNTER_UP = ENABLE; + } else if (countDir == DOWN_COUNTER) { + pTIMER->MATCH_CTRL[timerNum].MCUULP_TMR_CNTRL_b.COUNTER_UP = DISABLE; + } else { + return ERROR_INVAL_COUNTER_DIR; + } + } else { + return ERROR_INVAL_TIMER_NUM; + } + return RSI_OK; +} + +/*===================================================*/ +/** + * @fn uint32_t RSI_TIMERS_getDirection(RSI_TIMERS_T *pTIMER, uint8_t timerNum) + * @brief This API is used to get direction of the timer + * @param[in] pTIMER : Pointer to the TIMERS instance register area + * @param[in] timerNum : Timer number(0 to 3) + * + * @return countDir : counter direction + * - 1 for UP_COUNTER + * - 0 for DOWN_COUNTER + */ +STATIC INLINE uint32_t RSI_TIMERS_getDirection(RSI_TIMERS_T *pTIMER, uint8_t timerNum) +{ + uint8_t counterDir; + if (timerNum <= TIMER_3) { + counterDir = pTIMER->MATCH_CTRL[timerNum].MCUULP_TMR_CNTRL_b.COUNTER_UP; + return counterDir; + } else { + return ERROR_INVAL_TIMER_NUM; + } +} + +/*===================================================*/ +/** + * @fn uint32_t RSI_TIMERS_GetTimerMode(RSI_TIMERS_T *pTIMER, uint8_t timerNum) + * @brief This API is used to get the mode of timer + * @param[in] pTIMER : Pointer to the TIMERS instance register area + * @param[in] timerNum : Timer number(0 to 3) + * @return return the type of timer if valid timer else error code + */ +STATIC INLINE uint32_t RSI_TIMERS_GetTimerMode(RSI_TIMERS_T *pTIMER, uint8_t timerNum) +{ + if (timerNum <= TIMER_3) { + return (pTIMER->MATCH_CTRL[timerNum].MCUULP_TMR_CNTRL_b.TMR_MODE); + } else { + return ERROR_INVAL_TIMER_NUM; + } +} +/*===================================================*/ +/** + * @fn rsi_error_t RSI_TIMERS_TimerStart(RSI_TIMERS_T *pTIMER, uint8_t timerNum) + * @brief This API is used to start the timer + * @param[in] pTIMER : Pointer to the TIMERS instance register area + * @param[in] timerNum : Timer number(0 to 3) + * @return return the timer error code + */ +STATIC INLINE rsi_error_t RSI_TIMERS_TimerStart(RSI_TIMERS_T *pTIMER, uint8_t timerNum) +{ + if (timerNum <= TIMER_3) { + pTIMER->MATCH_CTRL[timerNum].MCUULP_TMR_CNTRL_b.TMR_START = ENABLE; + } else { + return ERROR_INVAL_TIMER_NUM; + } + return RSI_OK; +} + +/*===================================================*/ +/** + * @fn rsi_error_t RSI_TIMERS_TimerStop(RSI_TIMERS_T *pTIMER, uint8_t timerNum) + * @brief This API is used to stop the timer + * @param[in] pTIMER : Pointer to the TIMERS instance register area + * @param[in] timerNum : Timer number(0 to 3) + * @return return the timer error code + */ +STATIC INLINE rsi_error_t RSI_TIMERS_TimerStop(RSI_TIMERS_T *pTIMER, uint8_t timerNum) +{ + if (timerNum <= TIMER_3) { + pTIMER->MATCH_CTRL[timerNum].MCUULP_TMR_CNTRL_b.TMR_STOP = ENABLE; + } else { + return ERROR_INVAL_TIMER_NUM; + } + return RSI_OK; +} + +/*===================================================*/ +/** + * @fn rsi_error_t RSI_TIMERS_InterruptEnable(RSI_TIMERS_T *pTIMER , uint8_t timerNum) + * @brief This API is used to enable the timer interrupt + * @param[in] pTIMER : Pointer to the TIMERS instance register area + * @param[in] timerNum : Timer number(0 to 3) + * @return return the timer error code + */ +STATIC INLINE rsi_error_t RSI_TIMERS_InterruptEnable(RSI_TIMERS_T *pTIMER, uint8_t timerNum) +{ + if (timerNum <= TIMER_3) { + pTIMER->MATCH_CTRL[timerNum].MCUULP_TMR_CNTRL_b.TMR_INTR_ENABLE = ENABLE; + } else { + return ERROR_INVAL_TIMER_NUM; + } + return RSI_OK; +} + +/*===================================================*/ +/** + * @fn rsi_error_t RSI_TIMERS_InterruptDisable(RSI_TIMERS_T *pTIMER , uint8_t timerNum) + * @brief This API is used to disable the timer interrupt + * @param[in] pTIMER : Pointer to the TIMERS instance register area + * @param[in] timerNum : Timer number(0 to 3) + * @return return the timer error code + */ +STATIC INLINE rsi_error_t RSI_TIMERS_InterruptDisable(RSI_TIMERS_T *pTIMER, uint8_t timerNum) +{ + if (timerNum <= TIMER_3) { + pTIMER->MATCH_CTRL[timerNum].MCUULP_TMR_CNTRL_b.TMR_INTR_ENABLE = DISABLE; + } else { + return ERROR_INVAL_TIMER_NUM; + } + return RSI_OK; +} + +/*===================================================*/ +/** + * @fn rsi_error_t RSI_TIMERS_InterruptClear(RSI_TIMERS_T *pTIMER , uint8_t timerNum) + * @brief This API is used to clear the timer interrupt + * @param[in] pTIMER : Pointer to the TIMERS instance register area + * @param[in] timerNum : Timer number(0 to 3) + * @return return the timer error code + */ +STATIC INLINE rsi_error_t RSI_TIMERS_InterruptClear(RSI_TIMERS_T *pTIMER, uint8_t timerNum) +{ + if (timerNum <= TIMER_3) { + pTIMER->MATCH_CTRL[timerNum].MCUULP_TMR_CNTRL_b.TMR_INTR_CLR = ENABLE; + } else { + return ERROR_INVAL_TIMER_NUM; + } + return RSI_OK; +} + +/*===================================================*/ +/** + * @fn rsi_error_t RSI_TIMERS_SetMatch( RSI_TIMERS_T *pTIMER, uint8_t timerNum, uint32_t match) + * @brief This API is used to disable the timer interrupt + * @param[in] pTIMER : Pointer to the TIMERS instance register area + * @param[in] timerNum : Timer number(0 to 3) + * @param[in] match : delay time + * @return return the timer error code + */ +STATIC INLINE rsi_error_t RSI_TIMERS_SetMatch(RSI_TIMERS_T *pTIMER, uint8_t timerNum, uint32_t match) +{ + if (timerNum <= TIMER_3) { + pTIMER->MATCH_CTRL[timerNum].MCUULP_TMR_MATCH = match; + } else { + return ERROR_INVAL_TIMER_NUM; + } + return RSI_OK; +} + +/*===================================================*/ +/** + * @fn rsi_error_t RSI_TIMERS_InterruptStatus(RSI_TIMERS_T *pTIMER , uint8_t timerNum) + * @brief This API is used to get the timer interrupt status + * @param[in] pTIMER : Pointer to the TIMERS instance register area + * @param[in] timerNum : Timer number(0 to 3) + * @return return the timer interrupt status if valid timer else 0. + */ +STATIC INLINE uint8_t RSI_TIMERS_InterruptStatus(RSI_TIMERS_T *pTIMER, uint8_t timerNum) +{ + if (timerNum <= TIMER_3) { + return (uint8_t)(pTIMER->MCUULP_TMR_INTR_STAT & (1 << timerNum)); + } else { + return 0; + } +} + +/*===================================================*/ +/** + * @fn rsi_error_t RSI_TIMERS_SetTimerType( RSI_TIMERS_T *pTIMER, uint8_t timerType, uint8_t timerNum) + * @brief This API is used to set the timer type + * @param[in] pTIMER : Pointer to the TIMERS instance register area + * @param[in] timerType : timer type + * - \ref MICRO_SEC_MODE + * - \ref _256_MICRO_SEC_MODE + * - \ref COUNTER_DOWN_MODE + * @param[in] timerNum : Timer number(0 to 3) + * @return return the timer error code + */ +STATIC INLINE rsi_error_t RSI_TIMERS_SetTimerType(RSI_TIMERS_T *pTIMER, uint8_t timerType, uint8_t timerNum) +{ + if (timerNum <= TIMER_3) { + if ((timerType == MICRO_SEC_MODE) || (timerType == _256_MICRO_SEC_MODE) || (timerType == COUNTER_DOWN_MODE)) { + pTIMER->MATCH_CTRL[timerNum].MCUULP_TMR_CNTRL_b.TMR_TYPE = (unsigned int)(timerType & 0x03); + } else { + return ERROR_INVAL_TIMERTYPE; + } + } else { + return ERROR_INVAL_TIMER_NUM; + } + return RSI_OK; +} + +/*===================================================*/ +/** + * @fn rsi_error_t RSI_TIMERS_SetTimerMode(RSI_TIMERS_T *pTIMER, boolean_t mode,uint8_t timerNum) + * @brief This API is used to set the timer mode + * @param[in] pTIMER : Pointer to the TIMERS instance register area + * @param[in] mode : in which mode timer run + * - \ref PERIODIC_TIMER + * - \ref ONESHOT_TIMER + * @param[in] timerNum : Timer number(0 to 3) + * @return return the timer error code + */ +STATIC INLINE rsi_error_t RSI_TIMERS_SetTimerMode(RSI_TIMERS_T *pTIMER, boolean_t mode, uint8_t timerNum) +{ + if (timerNum <= TIMER_3) { + if ((mode == PERIODIC_TIMER) || (mode == ONESHOT_TIMER)) { + pTIMER->MATCH_CTRL[timerNum].MCUULP_TMR_CNTRL_b.TMR_MODE = (unsigned int)(mode & 0x01); + } else { + return ERROR_INVAL_TIMER_MODE; + } + } else { + return ERROR_INVAL_TIMER_NUM; + } + return RSI_OK; +} + +/*===================================================*/ +/** + * @fn uint32_t RSI_TIMERS_GetTimerType(RSI_TIMERS_T *pTIMER, uint8_t timerNum) + * @brief This API is used to get the type of timer + * @param[in] pTIMER : Pointer to the TIMERS instance register area + * @param[in] timerNum : Timer number(0 to 3) + * @return return the type of timer if valid timer else error code + */ +STATIC INLINE uint32_t RSI_TIMERS_GetTimerType(RSI_TIMERS_T *pTIMER, uint8_t timerNum) +{ + if (timerNum <= TIMER_3) { + return (pTIMER->MATCH_CTRL[timerNum].MCUULP_TMR_CNTRL_b.TMR_TYPE); + } else { + return ERROR_INVAL_TIMER_NUM; + } +} + +// TIMERS FUNCTION PROTOTYPES +RSI_DRIVER_VERSION_M4 RSI_TIMERS_GetVersion(void); + +RSI_TIMERS_CAPABILITIES_T RSI_TIMERS_GetCapabilities(void); + +rsi_error_t timers_microsec_timer_config(RSI_TIMERS_T *pTIMER, + uint8_t timerNum, + uint16_t integer, + uint8_t fractional, + uint8_t mode); +uint32_t timers_read_timer(RSI_TIMERS_T *pTIMER, uint8_t timerNum, boolean_t countDir); +void IRQ002_Handler(); + +#ifdef __cplusplus +} +#endif + +#endif // RSI_TIMERS_H diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_udma.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_udma.h new file mode 100644 index 000000000..b7a142ae1 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_udma.h @@ -0,0 +1,567 @@ +/******************************************************************************* +* @file rsi_udma.h +* @brief +******************************************************************************* +* # License +* Copyright 2022 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +//Include Files + +#include "rsi_ccp_common.h" +#include "rsi_error.h" +#include "rsi_packing.h" + +#ifndef RSI_UDMA_H +#define RSI_UDMA_H + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef UNUSED_PARAMETER +#define UNUSED_PARAMETER(x) (void)(x) +#endif // UNUSED_PARAMETER + +#define RSI_UDMA_DRV_VERSION RSI_DRIVER_VERSION_MAJOR_MINOR(02, 00) // driver version +#define RSI_UDMA_API_VERSION RSI_DRIVER_VERSION_MAJOR_MINOR(00, 01) // API version +#define UDMA_CHANNEL_NUM 32 + +#define M4SS_UDMA_INTR_SEL (*((uint32_t volatile *)(0x46110000 + 0x0C))) +#define ULP_DYN_CLK_CTRL_DIS_REG (*((uint32_t volatile *)(0x24041400 + 0xA0))) +#define ULP_UDMA_STATIC_CLK_EN (1UL << 17) +#define PERIPHERAL_UDMA_DMA_SEL (*((uint32_t volatile *)(0x46008000UL + 0x58))) + +#define UDMA_ATTR_USEBURST 0x1 +#define UDMA_ATTR_ALTSELECT 0x2 +#define UDMA_ATTR_HIGH_PRIORITY 0x4 +#define UDMA_ATTR_REQMASK 0x8 +#define UDMA_ATTR_ALL 0xF + +// DMA control modes + +#define CHNL0_INTR (1UL << 0) // Channel0 interrupt flag +#define CHNL1_INTR (1UL << 1) // Channel1 interrupt flag +#define CHNL2_INTR (1UL << 2) // Channel2 interrupt flag +#define CHNL3_INTR (1UL << 3) // Channel3 interrupt flag +#define CHNL4_INTR (1UL << 4) // Channel4 interrupt flag +#define CHNL5_INTR (1UL << 5) // Channel5 interrupt flag +#define CHNL6_INTR (1UL << 6) // Channel6 interrupt flag +#define CHNL7_INTR (1UL << 7) // Channel7 interrupt flag +#define CHNL8_INTR (1UL << 8) // Channel8 interrupt flag +#define CHNL9_INTR (1UL << 9) // Channel9 interrupt flag +#define CHNL10_INTR (1UL << 10) // Channel10 interrupt flag +#define CHNL11_INTR (1UL << 11) // Channel11 interrupt flag +#define CHNL12_INTR (1UL << 12) // Channel12 interrupt flag +#define CHNL13_INTR (1UL << 13) // Channel13 interrupt flag +#define CHNL14_INTR (1UL << 14) // Channel14 interrupt flag +#define CHNL15_INTR (1UL << 15) // Channel15 interrupt flag +#define CHNL16_INTR (1UL << 16) // Channel16 interrupt flag +#define CHNL17_INTR (1UL << 17) // Channel17 interrupt flag +#define CHNL18_INTR (1UL << 18) // Channel18 interrupt flag +#define CHNL19_INTR (1UL << 19) // Channel19 interrupt flag +#define CHNL20_INTR (1UL << 20) // Channel20 interrupt flag +#define CHNL21_INTR (1UL << 21) // Channel21 interrupt flag +#define CHNL22_INTR (1UL << 22) // Channel22 interrupt flag +#define CHNL23_INTR (1UL << 23) // Channel23 interrupt flag +#define CHNL24_INTR (1UL << 24) // Channel24 interrupt flag +#define CHNL25_INTR (1UL << 25) // Channel25 interrupt flag +#define CHNL26_INTR (1UL << 26) // Channel26 interrupt flag +#define CHNL27_INTR (1UL << 27) // Channel27 interrupt flag +#define CHNL28_INTR (1UL << 28) // Channel28 interrupt flag +#define CHNL29_INTR (1UL << 29) // Channel29 interrupt flag +#define CHNL30_INTR (1UL << 30) // Channel30 interrupt flag +#define CHNL31_INTR (1UL << 31) // Channel31 interrupt flag + +#define UDMA_MODE_STOP 0x0 +#define UDMA_MODE_BASIC 0x1 +#define UDMA_MODE_AUTO 0x2 +#define UDMA_MODE_PINGPONG 0x3 +#define UDMA_MODE_MEM_SCATTER_GATHER 0x4 +#define UDMA_MODE_MEM_ALT_SCATTER_GATHER 0x5 +#define UDMA_MODE_PER_SCATTER_GATHER 0x6 +#define UDMA_MODE_ALT_SELECT 0x1 +#define UDMA_SOFTWARE_TRIGG 0X2 + +#define UDMA_DST_INC_NONE 0x3 +#define UDMA_SRC_INC_NONE 0x3 + +#define UDMA_PRI_SELECT 0x00 +#define UDMA_ALT_SELECT 0x20 +#define UDMA_ULPALT_SELECT 0x10 + +#define UDMA_CHCTL_XFERSIZE_M 0x3FF +#define UDMA_CHCTL_XFERMODE_M 0x07 +#define UDMA_CHCTL_XFERSIZE_S 0x04 + +#define SRC_SIZE_32 0x2 +#define SRC_SIZE_16 0x1 +#define SRC_SIZE_8 0x0 + +#define DST_SIZE_32 0x2 +#define DST_SIZE_16 0x1 +#define DST_SIZE_8 0x0 + +#define SRC_INC_NONE 0x3 +#define SRC_INC_32 0x2 +#define SRC_INC_16 0x1 +#define SRC_INC_8 0x0 + +#define DST_INC_NONE 0x3 +#define DST_INC_32 0x2 +#define DST_INC_16 0x1 +#define DST_INC_8 0x0 + +#define ARBSIZE_1 0x00 +#define ARBSIZE_2 0x01 +#define ARBSIZE_4 0x02 +#define ARBSIZE_8 0x03 +#define ARBSIZE_16 0x04 +#define ARBSIZE_32 0x05 +#define ARBSIZE_64 0x06 +#define ARBSIZE_128 0x07 +#define ARBSIZE_256 0x08 +#define ARBSIZE_512 0x09 +#define ARBSIZE_1024 0x0A + +#define DMA_XFERS_1 0x0 +#define DMA_XFERS_2 0x1 +#define DMA_XFERS_3 0x2 +#define DMA_XFERS_4 0x3 +#define DMA_XFERS_5 0x4 +#define DMA_XFERS_6 0x5 +#define DMA_XFERS_7 0x6 +#define DMA_XFERS_8 0x7 +#define DMA_XFERS_9 0x8 +#define DMA_XFERS_10 0x9 +#define DMA_XFERS_11 0xA +#define DMA_XFERS_16 0xF +#define DMA_XFERS_31 0x1F +#define DMA_XFERS_101 0x64 +#define DMA_XFERS_256 0xFF +#define DMA_XFERS_1024 0x3FF + +#define USART0_ACK 0x1 +#define UART1_ACK 0x2 +#define UART3_ACK 0x3 +#define SSISLAVE_ACK 0x4 +#define SSIMASTER_ACK 0x5 +#define SSISLAVE1_ACK 0x6 +#define I2C_ACK 0x7 +#define CHNL_0 0 +#define CHNL_31 31 + +#define PRIMARY 0 +#define ALTERNATE 1 +#define CHNL_0 0 +#define CHNL_1 1 + +#define SRC_SIZE_32 0x2 +#define SRC_SIZE_16 0x1 +#define SRC_SIZE_8 0x0 + +#define DST_SIZE_32 0x2 +#define DST_SIZE_16 0x1 +#define DST_SIZE_8 0x0 + +#define SRC_INC_32 0x2 +#define SRC_INC_16 0x1 +#define SRC_INC_8 0x0 + +#define DST_INC_32 0x2 +#define DST_INC_16 0x1 +#define DST_INC_8 0x0 + +#define SRC_DST_SIZE_32 2 +#define SRC_DST_SIZE_16 1 +#define SRC_DTS_SIZE_8 0 + +#define MEM_SG 0 +#define PERI_SG 1 + +typedef UDMA0_Type RSI_UDMA_T; + +// brief RPDMA handle type +typedef void *RSI_UDMA_HANDLE_T; + +// brief UDMA Driver Capabilities. +typedef struct { + uint32_t noOfChannels; // Number of DMA channels + uint32_t maxNoOfTxferPerCycle; // Maximum number of transfers per DMA cycle +} RSI_UDMA_CAPABILITIES_T; + +// brief UDMA Channel Config structure +typedef struct { + uint32_t transferType : 3; // The operating mode of the DMA cycle + uint32_t + nextBurst : 1; // Used to force the channel to only respond to burst requests at the tail end of a scatter-gather transfer + uint32_t totalNumOfDMATrans : 10; // total number of DMA transfers that the DMA cycle contains + uint32_t rPower : 4; // Number of DMA transfers can occur before the controller rearbitrates + uint32_t srcProtCtrl : 3; // Performs control operation when the controller reads the source data + uint32_t dstProtCtrl : 3; // Performs control operation when the controller writes the destination data + uint32_t srcSize : 2; // Source data size + uint32_t srcInc : 2; // Source address increment + uint32_t dstSize : 2; // Destination data size + uint32_t dstInc : 2; // Destination address increment +} RSI_UDMA_CHA_CONFIG_DATA_T; + +// brief UDMA Control Structure. +typedef struct { + volatile void *pSrcEndAddr; // The ending source address of the data transfer + volatile void *pDstEndAddr; // The ending destination address of the data transfer + volatile RSI_UDMA_CHA_CONFIG_DATA_T vsUDMAChaConfigData1; // The Channel Config Structure + volatile uint32_t Spare; // An unused location +} RSI_UDMA_DESC_T; + +typedef void (*udmaTransferCompleteCB)(RSI_UDMA_HANDLE_T udmaHandle, RSI_UDMA_DESC_T *pTranDesc, uint32_t dmaCh); + +// brief RPDMA controller callback IDs +typedef enum { + ROM_UDMA_XFERCOMPLETE_CB = 0, // Callback ID for UDMA transfer descriptor chain complete +} ROM_UDMA_CALLBACK_T; + +// Private data structure used for the RPDMA controller driver, holds the driver and peripheral context +typedef struct { + void *pUserData; // Pointer to user data used by driver instance, use NULL if not used + RSI_UDMA_T *base; // UDMA base address + RSI_UDMA_DESC_T *sramBase; // SRAM descriptor table (all channels) + RSI_UDMA_DESC_T *desc; // descriptor structure + udmaTransferCompleteCB udmaCompCB; // Transfer complete callback + uint32_t dmaCh; +} RSI_UDMA_DATACONTEXT_T; + +// RPDMA Init structure +typedef PRE_PACK struct POST_PACK { + void *pUserData; // Pointer to user data used by driver instance, use NULL if not used + uint32_t base; // Pointer to RPDMA global register instance + uint32_t sramBase; // Pointer to memory used for RPDMA descriptor storage, must be 512 byte aligned +} RSI_UDMA_INIT_T; + +// brief RPDMA transfer channel setup structure (use this structure as const if possible) +typedef PRE_PACK struct POST_PACK { + uint32_t channelPrioHigh; // Channel priority level + uint32_t altStruct; // Primary or alternate control structure + uint32_t burstReq; // Burst request + uint32_t reqMask; // Mask channel request + uint32_t periphReq; // Peripheral request + uint32_t periAck; // dma ACK for peripheral + uint32_t dmaCh; +} RSI_UDMA_CHA_CFG_T; +/** @addtogroup SOC18 +* @{ +*/ + +/*===================================================*/ +/** + * @fn uint32_t RSI_UDMA_GetMemSize(void) + * @brief This API is used to Get memory size in bytes needed for UDMA controller driver context + * @return Size in bytes needed for the ROM driver + */ +STATIC INLINE uint32_t RSI_UDMA_GetMemSize(void) +{ + return sizeof(RSI_UDMA_DATACONTEXT_T); +} + +/*===================================================*/ +/** + * @fn void RSI_UDMA_RegisterCallback(RSI_UDMA_HANDLE_T pHandle, void *pCB) + * @brief Registers an DMA controller callback for a queue + * @param[in] pHandle : Pointer to driver context handle + * @param[in] pCB : Pointer to callback function + * @return none + */ +STATIC INLINE void RSI_UDMA_RegisterCallback(RSI_UDMA_HANDLE_T pHandle, udmaTransferCompleteCB pCB) +{ + RSI_UDMA_DATACONTEXT_T *pDrv = (RSI_UDMA_DATACONTEXT_T *)pHandle; + + pDrv->udmaCompCB = pCB; +} + +/*===================================================*/ +/** + * @fn void RSI_UDMA_UDMAEnable(RSI_UDMA_HANDLE_T pHandle) + * @brief This API is used to enable the UDMA interface + * @param[in] pHandle : Pointer to driver context handle + * @return none + */ +STATIC INLINE void RSI_UDMA_UDMAEnable(RSI_UDMA_HANDLE_T pHandle) +{ + RSI_UDMA_DATACONTEXT_T *pDrv = (RSI_UDMA_DATACONTEXT_T *)pHandle; + pDrv->base->DMA_CFG_b.MASTER_ENABLE = ENABLE; +} + +/*===================================================*/ +/** + * @fn void RSI_UDMA_UDMADisable(RSI_UDMA_HANDLE_T pHandle) + * @brief This API is used to disable the UDMA interface + * @param[in] pHandle : Pointer to driver context handle + * @return none + */ + +STATIC INLINE void RSI_UDMA_UDMADisable(RSI_UDMA_HANDLE_T pHandle) +{ + RSI_UDMA_DATACONTEXT_T *pDrv = (RSI_UDMA_DATACONTEXT_T *)pHandle; + + pDrv->base->DMA_CFG_b.MASTER_ENABLE = DISABLE; +} + +/*===================================================*/ +/** + * @fn uint8_t RSI_UDMA_ErrorStatusGet(RSI_UDMA_T *pUDMA) + * @brief This API is used to get the error status/sets the signal low of UDMA. + * @param[in] pUDMA : Pointer to the UDMA instance register area + * @return Returns error status as below + * - 0 : Error is LOW + * - 1 : Error is HIGH + */ +STATIC INLINE uint8_t RSI_UDMA_ErrorStatusGet(RSI_UDMA_T *pUDMA) +{ + return (pUDMA->ERR_CLR_b.ERR_CLR); +} +/*===================================================*/ +/** + * @fn void RSI_UDMA_ErrorStatusClear(RSI_UDMA_HANDLE_T pHandle) + * @brief This API is used to clear the errors of UDMA + * @param[in] pHandle : Pointer to driver context handle + * @return none + */ +STATIC INLINE void RSI_UDMA_ErrorStatusClear(RSI_UDMA_HANDLE_T pHandle) +{ + RSI_UDMA_DATACONTEXT_T *pDrv = (RSI_UDMA_DATACONTEXT_T *)pHandle; + pDrv->base->ERR_CLR_b.ERR_CLR = 0x1; +} + +/*===================================================*/ +/** + * @fn rsi_error_t RSI_UDMA_ChannelEnable(RSI_UDMA_HANDLE_T pHandle,uint8_t dmaCh) + * @brief This API is used to enable the required channel of UDMA + * @param[in] pHandle : Pointer to driver context handle + * @param[in] dmaCh : Channel number(1 to 32) + * @return RSI_OK if no errors occured, or an error code + */ +STATIC INLINE rsi_error_t RSI_UDMA_ChannelEnable(RSI_UDMA_HANDLE_T pHandle, uint8_t dmaCh) +{ + RSI_UDMA_DATACONTEXT_T *pDrv = (RSI_UDMA_DATACONTEXT_T *)pHandle; + if (dmaCh <= CHNL_31) { + // Enables required channel + pDrv->base->CHNL_ENABLE_SET = SET_BIT(dmaCh); + return RSI_OK; + } else { + return ERROR_UDMA_INVALIDCHNLNUM; + } +} + +/*===================================================*/ +/** + * @fn rsi_error_t RSI_UDMA_ChannelDisable(RSI_UDMA_HANDLE_T pHandle,uint8_t dmaCh) + * @brief This API is used to disable the required channel of UDMA + * @param[in] pHandle : Pointer to driver context handle + * @param[in] dmaCh : Channel number(1 to 32) + * @return RSI_OK if no errors occured, or an error code + */ +STATIC INLINE rsi_error_t RSI_UDMA_ChannelDisable(RSI_UDMA_HANDLE_T pHandle, uint8_t dmaCh) +{ + RSI_UDMA_DATACONTEXT_T *pDrv = (RSI_UDMA_DATACONTEXT_T *)pHandle; + if (dmaCh <= CHNL_31) { + // Disables required channel + pDrv->base->CHNL_ENABLE_CLR = SET_BIT(dmaCh); + return RSI_OK; + } else + return ERROR_UDMA_INVALIDCHNLNUM; +} + +/*===================================================*/ +/** + * @fn rsi_error_t RSI_UDMA_ChannelIsEnabled(RSI_UDMA_HANDLE_T pHandle, uint8_t dmaCh) + * @brief This API is used to check the required UDMA channel is enabled or not + * @param[in] pHandle : Pointer to driver context handle + * @param[in] dmaCh : Channel number(0 to 31) + * @return If process is successful then return RSI_OK else RSI_FAIL If requied channel is not enabled + */ +STATIC INLINE rsi_error_t RSI_UDMA_ChannelIsEnabled(RSI_UDMA_HANDLE_T pHandle, uint8_t dmaCh) +{ + RSI_UDMA_DATACONTEXT_T *pDrv = (RSI_UDMA_DATACONTEXT_T *)pHandle; + if (dmaCh <= CHNL_31) { + if (((pDrv->base->CHNL_ENABLE_SET) & SET_BIT(dmaCh)) != 0) { + return RSI_OK; + } else { + return RSI_FAIL; + } + } else { + return ERROR_UDMA_INVALIDCHNLNUM; + } +} + +/*===================================================*/ +/** + * @fn void *RSI_UDMA_GetControlBaseAddress(RSI_UDMA_HANDLE_T pHandle) + * @brief This API is used to get the UDMA control base address + * @param[in] pHandle : Pointer to driver context handle + * @return Control structure base pointer + */ +STATIC INLINE void *RSI_UDMA_GetControlBaseAddress(RSI_UDMA_HANDLE_T pHandle) +{ + RSI_UDMA_DATACONTEXT_T *pDrv = (RSI_UDMA_DATACONTEXT_T *)pHandle; + return ((void *)pDrv->base->CTRL_BASE_PTR); +} + +/*===================================================*/ +/** + * @fn void *RSI_UDMA_GetControlAlternateBase(RSI_UDMA_HANDLE_T pHandle) + * @brief This API is used to get the required UDMA channel alternate control base + * @param[in] pHandle : Pointer to driver context handle + * @return Alternate control structure base pointer + */ +STATIC INLINE void *RSI_UDMA_GetControlAlternateBase(RSI_UDMA_HANDLE_T pHandle) +{ + RSI_UDMA_DATACONTEXT_T *pDrv = (RSI_UDMA_DATACONTEXT_T *)pHandle; + return ((void *)pDrv->base->ALT_CTRL_BASE_PTR); +} + +/*===================================================*/ +/** + * @fn rsi_error_t RSI_UDMA_ChannelSoftwareTrigger(RSI_UDMA_HANDLE_T pHandle, uint8_t dmaCh) + * @brief This API is used to to generate a software UDMA request on the corresponding UDMA channel + * @param[in] pHandle : Pointer to driver context handle + * @param[in] dmaCh : channel number (0 to 31). + * @return return ERROR_UDMA_INVALID_ARG if channel is greater than 31 or channel is invalid , and on success return RSI_OK(0). + */ +STATIC INLINE rsi_error_t RSI_UDMA_ChannelSoftwareTrigger(RSI_UDMA_HANDLE_T pHandle, uint8_t dmaCh) +{ + RSI_UDMA_DATACONTEXT_T *pDrv = (RSI_UDMA_DATACONTEXT_T *)pHandle; + if (dmaCh <= CHNL_31) { + pDrv->base->CHNL_SW_REQUEST |= SET_BIT(dmaCh); + return RSI_OK; + } else + return ERROR_UDMA_INVALIDCHNLNUM; +} + +/*===================================================*/ +/** + * @fn rsi_error_t RSI_UDMA_InterruptClear(RSI_UDMA_HANDLE_T pHandle, uint8_t dmaCh) + * @brief This API is used to to generate a UDMA interrupt clear. + * @param[in] pHandle : Pointer to driver context handle + * @param[in] dmaCh : channel number (0 to 31). + * @return return ERROR_UDMA_INVALID_ARG if channel is greater than 31 or channel is invalid , + * and on success return RSI_OK(0). + */ +STATIC INLINE rsi_error_t RSI_UDMA_InterruptClear(RSI_UDMA_HANDLE_T pHandle, uint8_t dmaCh) +{ + RSI_UDMA_DATACONTEXT_T *pDrv = (RSI_UDMA_DATACONTEXT_T *)pHandle; + if (dmaCh <= CHNL_31) { + pDrv->base->UDMA_DONE_STATUS_REG = SET_BIT(dmaCh); + } else { + return ERROR_UDMA_INVALIDCHNLNUM; + } + return RSI_OK; +} + +/*===================================================*/ +/** + * @fn uint32_t RSI_UDMA_InterruptStatus(RSI_UDMA_HANDLE_T pHandle, uint8_t dmaCh) + * @brief Gets interrupt status of required channel. + * @param[in] pHandle : Pointer to driver context handle + * @param[in] dmaCh : Channel number(0 to 31),Possible values are as below + - \b 0 : Channel disable + - \b 1 : Channel enable + * @return Interrupt status of required channel + */ +STATIC INLINE uint32_t RSI_UDMA_InterruptStatus(RSI_UDMA_HANDLE_T pHandle, uint8_t dmaCh) +{ + uint32_t intr_stat = 0; + RSI_UDMA_DATACONTEXT_T *pDrv = (RSI_UDMA_DATACONTEXT_T *)pHandle; + + intr_stat = pDrv->base->UDMA_DONE_STATUS_REG; + return (intr_stat & SET_BIT(dmaCh)); +} + +/*===================================================*/ +/** + * @fn uint8_t RSI_UDMA_GetControllerEnableStatus(RSI_UDMA_HANDLE_T pHandle) + * @brief This API is used to get the enable status of controller + * @param[in] pHandle : Pointer to driver context handle + * @return If 1 controller is enabled ,if 0 controller is disabled + */ +STATIC INLINE uint8_t RSI_UDMA_GetControllerEnableStatus(RSI_UDMA_HANDLE_T pHandle) +{ + RSI_UDMA_DATACONTEXT_T *pDrv = (RSI_UDMA_DATACONTEXT_T *)pHandle; + return (pDrv->base->DMA_STATUS_b.MASTER_ENABLE); +} + +/*===================================================*/ +/** + * @fn uint32_t RSI_UDMA_GetControlState(RSI_UDMA_HANDLE_T pHandle) + * @brief This API is used to get the current state of the control state machine + * @param[in] pHandle : Pointer to driver context handle + * @return returns state of the control state machine + possible values are as below + - 0000 = idle + - 0001 = reading channel controller data + - 0010 = reading source data end pointer + - 0011 = reading destination data end pointer + - 0100 = reading source data + - 0101 = writing destination data + - 0110 = waiting for DMA request to clear + - 0111 = writing channel controller data + - 1000 = stalled + - 1001 = done + - 1010 = peripheral scatter-gather transition + - 1011-1111 = undefined. + */ +STATIC INLINE uint32_t RSI_UDMA_GetControlState(RSI_UDMA_HANDLE_T pHandle) +{ + RSI_UDMA_DATACONTEXT_T *pDrv = (RSI_UDMA_DATACONTEXT_T *)pHandle; + return (pDrv->base->DMA_STATUS_b.STATE); +} + +// FUNCTION PROTOTYPES +RSI_DRIVER_VERSION_M4 RSI_UDMA_GetVersion(void); + +RSI_UDMA_CAPABILITIES_T RSI_UDMA_GetCapabilities(void); + +RSI_UDMA_HANDLE_T udma_init(void *mem, const RSI_UDMA_INIT_T *pInit); + +uint32_t udma_get_channel_transfer_mode(RSI_UDMA_HANDLE_T pHandle, RSI_UDMA_CHA_CFG_T *pCfg); + +rsi_error_t udma_setup_channel_transfer(RSI_UDMA_HANDLE_T pHandle, + RSI_UDMA_CHA_CFG_T *pCfg, + RSI_UDMA_CHA_CONFIG_DATA_T vsUdmaChaConfigData, + void *pSrcAddr, + void *pDstAddr); + +rsi_error_t udma_set_channel_scatter_gather_transfer(RSI_UDMA_HANDLE_T pHandle, + uint8_t dmaCh, + uint32_t taskCount, + void *pTaskList, + uint32_t transferType); + +uint32_t udma_get_channel_transfer_length(RSI_UDMA_HANDLE_T pHandle, + RSI_UDMA_CHA_CFG_T *pCfg, + RSI_UDMA_CHA_CONFIG_DATA_T vsUDMAChaConfigData); + +rsi_error_t udma_setup_channel(RSI_UDMA_HANDLE_T pHandle, RSI_UDMA_CHA_CFG_T *pCfg); + +void udma_deInit(RSI_UDMA_HANDLE_T pHandle, RSI_UDMA_CHA_CFG_T *pCfg); + +void udma_interrupt_handler(RSI_UDMA_HANDLE_T pHandle); + +rsi_error_t udma_interrupt_enable(RSI_UDMA_HANDLE_T pHandle, uint8_t dmaCh); +rsi_error_t RSI_UDMA_ChannelControlsDisable(RSI_UDMA_HANDLE_T pHandle, RSI_UDMA_CHA_CFG_T *pCfg); +void RSI_UDMA_SetSingleRequest(RSI_UDMA_HANDLE_T pHandle); +void RSI_UDMA_AckEnable(RSI_UDMA_HANDLE_T pHandle, uint32_t peripheral); + +#ifdef __cplusplus +} +#endif + +#endif // RSI_UDMA_H +/** @} */ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_udma_wrapper.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_udma_wrapper.h new file mode 100644 index 000000000..496235d12 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_udma_wrapper.h @@ -0,0 +1,79 @@ +/******************************************************************************* +* @file rsi_udma_wrapper.h +* @brief +******************************************************************************* +* # License +* Copyright 2022 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ +/**=========================================================================== + * @brief This files contains functions prototypes releated to UDMA peripheral + * @section Description : + * This file contains the list of function prototypes for the UDMA and low level function definations + * Following are list of API's which need to be defined in this file. +============================================================================**/ + +// Include Files + +#include "rsi_ccp_common.h" +#include "rsi_error.h" +#include "rsi_packing.h" +#include "UDMA.h" + +#ifndef RSI_UDMA_WRAPPER_H +#define RSI_UDMA_WRAPPER_H + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef UNUSED_PARAMETER +#define UNUSED_PARAMETER(x) (void)(x) +#endif // UNUSED_PARAMETER + +typedef struct { + uint32_t SrcAddr; + uint32_t DestAddr; + uint32_t Size; + uint32_t Cnt; + UDMA_SignalEvent_t cb_event; +} UDMA_Channel_Info; + +RSI_UDMA_HANDLE_T uDMAx_Initialize(UDMA_RESOURCES *udma, + RSI_UDMA_DESC_T *UDMA_Table, + RSI_UDMA_HANDLE_T udmaHandle, + uint32_t *mem); +int32_t uDMAx_Uninitialize(UDMA_RESOURCES *udma); +int32_t uDMAx_ChannelConfigure(UDMA_RESOURCES *udma, + uint8_t ch, + uint32_t src_addr, + uint32_t dest_addr, + uint32_t size, + RSI_UDMA_CHA_CONFIG_DATA_T control, + RSI_UDMA_CHA_CFG_T *config, + UDMA_SignalEvent_t cb_event, + UDMA_Channel_Info *chnl_info, + RSI_UDMA_HANDLE_T udmaHandle); +int32_t uDMAx_ChannelEnable(uint8_t ch, UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle); +int32_t uDMAx_DMAEnable(UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle); +int32_t uDMAx_ChannelDisable(uint8_t ch, UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle); +uint32_t uDMAx_ChannelGetCount(uint8_t ch, + RSI_UDMA_CHA_CONFIG_DATA_T control, + RSI_UDMA_CHA_CFG_T config, + UDMA_RESOURCES *udma, + RSI_UDMA_HANDLE_T udmaHandle); +void uDMAx_IRQHandler(UDMA_RESOURCES *udma, RSI_UDMA_DESC_T *UDMA_Table, UDMA_Channel_Info *chnl_info); + +#ifdef __cplusplus +} +#endif + +#endif // RSI_UDMA_WRAPPER_H diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_packing.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_packing.h new file mode 100644 index 000000000..71f37181f --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_packing.h @@ -0,0 +1,27 @@ +/******************************************************************************* +* @file rsi_packing.h +* @brief +******************************************************************************* +* # License +* Copyright 2020 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +#ifndef __PACKING_H_ +#define __PACKING_H_ + +#define PRE_PACK /* Nothing */ +#define POST_PACK /* Nothing */ +#ifndef ALIGNED +#define ALIGNED(n) /* Nothing */ +#endif + +#endif /* __PACKING_H_ */ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_clks.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_clks.h new file mode 100644 index 000000000..c0d7971d7 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_clks.h @@ -0,0 +1,1675 @@ +/******************************************************************************* +* @file rsi_rom_clks.h +* @brief +******************************************************************************* +* # License +* Copyright 2020 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ +/************************************************************************* + * + */ + +//Includes + +/** + * @defgroup RSI_SPECIFIC_DRIVERS SoC Device-Specific Drivers + * @ingroup SOC + * @section Description + * RSI specific drivers are unique to a specific device. RSI specific drivers may use an IP driver as it's base driver or a custom implementation if that + * peripheral or IP on the chip is unique (ie, clocking) + */ + +/** + * \ingroup RSI_SPECIFIC_DRIVERS + */ + +/** + * \defgroup RSI_CHIP_CLOCK_DRIVERS + * @{ + * + */ + +/** + * \defgroup RSI_M4SS_CLOCK_DRIVERS M4SS CLOCK + * @{ + * + */ + +#ifndef __RSI_ROM_CLK_H_ +#define __RSI_ROM_CLK_H_ + +#include "rsi_ccp_user_config.h" +#include "rsi_packing.h" +#if defined(A11_ROM) +#include "rsi_rom_table_si91x.h" +#else +#include "rsi_rom_table_RS1xxxx.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @fn STATIC INLINE boolean_t RSI_CLK_CheckPllLock(PLL_TYPE_T pllType) + * @brief This API is used to check the lock status of pll + * @param[in] pllType : To select the soc_pll, intf_pll and i2s_pll. See # PLL_TYPE_T for more info + * \n structure member is below. + * - SOC_PLL : soc_pll clk + * - INTF_PLL : intf_pll clk + * - I2S_PLL : i2s_pll clk + * @return return 1 then for lock status high(enable) and return 0 then for lock status low(disable) + * + */ +STATIC INLINE boolean_t RSI_CLK_CheckPllLock(PLL_TYPE_T pllType) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_check_pll_lock(pllType); +#else + return clk_check_pll_lock(pllType); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_SocPllClkEnable(boolean_t clkEnable) + * @brief This API is used to enable the SoC-PLL output clock + * @param[in] clkEnable : Enum value to enable or disable the clock + * - Enable : Enables clock + * - Disable : Disables clock + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_SocPllClkEnable(boolean_t clkEnable) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_soc_pll_clk_enable(clkEnable); +#else + return clk_soc_pll_clk_enable(clkEnable); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_SetSocPllFreq(M4CLK_Type *pCLK,uint32_t socPllFreq,uint32_t pllRefClk) + * @brief This API is used to set the Soc PLL clock to particular frequency + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] socPllFreq : Frequency value in Mhz for Soc_Pll_Clk . + * @param[in] pllRefClk : Frequency value in Mhz for Reference clk. Please refer # NOTE + * @return returns zero \ref RSI_OK on success ,on failure return error code. + * @note Only 1Mhz steps applicable to the this API, 0.96Mhz steps are not supported + */ +STATIC INLINE rsi_error_t RSI_CLK_SetSocPllFreq(M4CLK_Type *pCLK, uint32_t socPllFreq, uint32_t pllRefClk) +{ + rsi_error_t ret = (rsi_error_t)0; + system_clocks.soc_pll_clock = socPllFreq; + + if (pllRefClk == 32000000UL) { + /* Selecting the PLL reference clock */ + /* 0 - XTAL_CLK, 1 - Reserved, 2 - RC_32MHZ_CLK, 3 - Reserved */ + PLL_REF_CLK_CONFIG_REG |= (0x02 << 14); // Selecting the 32 MHz RC as SOC-PLL reference clock + } + + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG9) = 0xD900; +#if defined(CLOCK_ROMDRIVER_PRESENT) + ret = ROMAPI_M4SS_CLK_API->clk_set_soc_pll_freq(pCLK, socPllFreq, pllRefClk); +#else + + ret = clk_set_soc_pll_freq(pCLK, socPllFreq, pllRefClk); +#endif + if (ret != RSI_OK) { + return ret; + } else { + socPllFreq /= 1000000; + /*if SOC PLL frequency is greater than 90Mhz */ + if (socPllFreq < 90) { + /* Change the power state from PS4 to PS3 */ + RSI_PS_PowerStateChangePs4toPs3(); + /* Configure DCDC to give lower output voltage */ + RSI_PS_SetDcDcToLowerVoltage(); + } + if ((socPllFreq > 90) && (!(BATT_FF->MCU_PMU_LDO_CTRL_CLEAR & MCU_SOC_LDO_LVL))) { + /* Change the power state from PS3 to PS4 */ + RSI_PS_SetDcDcToHigerVoltage(); + /* Configure DCDC to give higher output voltage.*/ + RSI_PS_PowerStateChangePs3toPs4(); + } + } + return RSI_OK; +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_SocPllSetFreqDiv(M4CLK_Type *pCLK , boolean_t clk_en,uint16_t + * divFactor,uint16_t nFactor,uint16_t mFactor,uint16_t fCwf, + * uint16_t dcofixsel,uint16_t ldoprog) + * @brief This API is used to configure the SOC PLL clock frequency + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] clk_en : To enable the soc_pll_clk output enable + * @param[in] divFactor : PLL post division factor + * @param[in] nFactor : N factor of PLL + * @param[in] mFactor : M factor of PLL + * @param[in] fCwf : Fractional Frequency Control Word. For below 200MHz fcwF is 0 and above 200Mhz if the frequency is odd program FCW_F as 8192 + * @param[in] dcofixsel : Dco Fixed Ring select. Please refer # Note + * @param[in] ldoprog : SOCPLL LDO output voltage select. Please refer # Note + * @return returns zero \ref RSI_OK (0) on success ,on failure return error code. + * @note For <= 200Mhz ---> ldo_prog =4 and dco_fix_sel=1 + * - For 201-250Mhz ---> ldo_prog =5 and dco_fix_sel=0 + * - For >=251Mhz ---> ldo_prog =5 and dco_fix_sel=2 + */ +STATIC INLINE rsi_error_t RSI_CLK_SocPllSetFreqDiv(M4CLK_Type *pCLK, + boolean_t clk_en, + uint16_t divFactor, + uint16_t nFactor, + uint16_t mFactor, + uint16_t fCwf, + uint16_t dcofixsel, + uint16_t ldoprog) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API + ->clk_soc_pll_set_freq_div(pCLK, clk_en, divFactor, nFactor, mFactor, fCwf, dcofixsel, ldoprog); +#else + return clk_soc_pll_set_freq_div(pCLK, clk_en, divFactor, nFactor, mFactor, fCwf, dcofixsel, ldoprog); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_SocPllClkSet(M4CLK_Type *pCLK) + * @brief This API is used to Enables the SoC-PLL + * @param[in] pCLK : Pointer to the pll register instance + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_SocPllClkSet(M4CLK_Type *pCLK) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_soc_pll_clk_set(pCLK); +#else + return clk_soc_pll_clk_set(pCLK); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_SocPllClkBypassEnable(boolean_t clkEnable) + * @brief This API is used to enable bypass clock + * @param[in] clkEnable : Enum value to enable or disable the clock + * - Enable (1) : Enables bypass clock + * - Disable (0) : Disables bypass clock + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_SocPllClkBypassEnable(boolean_t clkEnable) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_soc_pll_clk_bypass_enable(clkEnable); +#else + return clk_soc_pll_clk_bypass_enable(clkEnable); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_SocPllClkReset() + * @brief This API is used to Reset the Soc_pll_clk + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_SocPllClkReset() +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_soc_pll_clk_reset(); +#else + return clk_soc_pll_clk_reset(); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_SocPllPdEnable(boolean_t en) + * @brief This API is used to enable the PdEnable(power down) + * @param[in] en : Enable or disable the PdEnable + * - Enable : Enables bypass clock + * - Disable : Disables bypass clock + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_SocPllPdEnable(boolean_t en) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_soc_pll_pd_enable(en); +#else + return clk_soc_pll_pd_enable(en); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_SocPllTurnOff() + * @brief This API is used to TurnOff the SOC_PLL + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_SocPllTurnOff() +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_soc_pll_turn_off(); +#else + return clk_soc_pll_turn_off(); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_SocPllTurnOn() + * @brief This API is used to TurnOn the SOC_PLL + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_SocPllTurnOn() +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_soc_pll_turn_on(); +#else + return clk_soc_pll_turn_on(); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_I2sPllClkEnable(boolean_t clkEnable) + * @brief This API is used to enable the I2s_PLL output clock + * @param[in] clkEnable : Enum value to enable or disable the clock + * - Enable(1) : Enables clock for i2s + * - Disable(0) : Disables clock for i2s + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_I2sPllClkEnable(boolean_t clkEnable) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_i2s_pll_clk_enable(clkEnable); +#else + return clk_i2s_pll_clk_enable(clkEnable); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_I2sPllClkBypassEnable(boolean_t clkEnable) + * @brief This API is used to enable bypass clock + * @param[in] clkEnable : Enum value to enable or disable the clock + * - Enable : Enables bypass clock for i2s + * - Disable : Disables bypass clock for i2s + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_I2sPllClkBypassEnable(boolean_t clkEnable) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_i2s_pll_clk_bypass_enable(clkEnable); +#else + return clk_i2s_pll_clk_bypass_enable(clkEnable); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_I2sPllPdEnable(boolean_t en) + * @brief This API is used to enable the PdEnable(power down) + * @param[in] en : Enable or disable the PdEnable + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_I2sPllPdEnable(boolean_t en) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_i2s_pll_pd_enable(en); +#else + return clk_i2s_pll_pd_enable(en); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_I2sPllTurnOff() + * @brief This API is used to TurnOff the I2s_PLL + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_I2sPllTurnOff() +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_i2s_pll_turn_off(); +#else + return clk_i2s_pll_turn_off(); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_I2sPllTurnOn() + * @brief This API is used to TurnOn the I2s_PLL + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_I2sPllTurnOn() +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_i2s_pll_turn_on(); +#else + return clk_i2s_pll_turn_on(); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_SetI2sPllFreq(M4CLK_Type *pCLK,uint32_t i2sPllFreq, uint32_t fXtal) + * @brief This API is used to set the I2s_pll clock to particular frequency + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] i2sPllFreq : Frequency value in Mhz for I2S_PLL Clk . + * @param[in] fXtal : Frequency value in Mhz for crystal oscillator frequency. + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_SetI2sPllFreq(M4CLK_Type *pCLK, uint32_t i2sPllFreq, uint32_t fXtal) +{ + system_clocks.i2s_pll_clock = i2sPllFreq; + SPI_MEM_MAP_PLL(I2S_PLL_CTRL_REG9) = 0xD900; +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_set_i2s_pll_freq(pCLK, i2sPllFreq, fXtal); +#else + return clk_set_i2s_pll_freq(pCLK, i2sPllFreq, fXtal); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_I2sPllSetFreqDiv(M4CLK_Type *pCLK,uint16_t u16DivFactor1, + * uint16_t u16DivFactor2,uint16_t nFactor,uint16_t mFactor, + * uint16_t fcwF) + * @brief This API is used to divide I2s_PLL Clock + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] u16DivFactor1 : Post Division factor1. See user manual for more info. + * @param[in] u16DivFactor2 : Post Division factor2. See user manual for more info. + * @param[in] nFactor : N factor for PLL. See user manual for more info. + * @param[in] mFactor : M factor for PLL. See user manual for more info. + * @param[in] fcwF : Fractional Frequency Control Word. + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_I2sPllSetFreqDiv(M4CLK_Type *pCLK, + uint16_t u16DivFactor1, + uint16_t u16DivFactor2, + uint16_t nFactor, + uint16_t mFactor, + uint16_t fcwF) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_i2s_pll_set_freq_div(pCLK, u16DivFactor1, u16DivFactor2, nFactor, mFactor, fcwF); +#else + return clk_i2s_pll_set_freq_div(pCLK, u16DivFactor1, u16DivFactor2, nFactor, mFactor, fcwF); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_I2sPllClkSet(M4CLK_Type *pCLK) + * @brief This API is used to set the I2s_pll_clk + * @param[in] pCLK : Pointer to the pll register instance + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_I2sPllClkSet(M4CLK_Type *pCLK) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_i2s_pll_clk_set(pCLK); +#else + return clk_i2s_pll_clk_set(pCLK); + ; +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_I2sPllClkReset() + * @brief This API is used to reset the I2s_pll_clk + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_I2sPllClkReset() +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_i2s_pll_clk_reset(); +#else + return clk_i2s_pll_clk_reset(); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_IntfPllClkEnable(boolean_t clkEnable) + * @brief This API is used to enable the Intf_PLL output clock + * @param[in] clkEnable : Enum value to enable or disable the clock + * - Enable(1) : Enables clock + * - Disable(0) : Disables clock + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_IntfPllClkEnable(boolean_t clkEnable) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_intf_pll_clk_enable(clkEnable); +#else + return clk_intf_pll_clk_enable(clkEnable); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_IntfPllPdEnable(boolean_t en) + * @brief This API is used to enable the PdEnable(power down) + * @param[in] en : Enable or disable the PdEnable + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_IntfPllPdEnable(boolean_t en) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_intf_pll_pd_enable(en); +#else + return clk_intf_pll_pd_enable(en); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_IntfPLLTurnOff() + * @brief This API is used to TurnOff the Intf_PLL + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_IntfPLLTurnOff() +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_intf_pll_turn_off(); +#else + return clk_intf_pll_turn_off(); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_SetIntfPllFreq(M4CLK_Type *pCLK,uint32_t intfPllFreq,uint32_t pllRefClk) + * @brief This API is used to set the INTFPLL clock to particular frequency + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] intfPllFreq : Frequency value in Mhz for INTFPLL Clk . + * @param[in] pllRefClk : Frequency value in Mhz for Reference clk. Please refer # NOTE + * @return returns zero \ref RSI_OK on success ,on failure return error code. + * @note Only 1Mhz steps applicable to the this API, 0.96Mhz steps are not supported + */ +STATIC INLINE rsi_error_t RSI_CLK_SetIntfPllFreq(M4CLK_Type *pCLK, uint32_t intfPllFreq, uint32_t pllRefClk) +{ + rsi_error_t error = (rsi_error_t)0; + system_clocks.intf_pll_clock = intfPllFreq; + + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG9) = 0xD900; +#if defined(CLOCK_ROMDRIVER_PRESENT) + error = ROMAPI_M4SS_CLK_API->clk_set_intf_pll_freq(pCLK, intfPllFreq, pllRefClk); +#else + error = clk_set_intf_pll_freq(pCLK, intfPllFreq, pllRefClk); +#endif + if (error != RSI_OK) { + return error; + } else { + /*if SOC PLL frequency is greater than 90Mhz */ + if (intfPllFreq < 90) { + /* Change the power state from PS4 to PS3 */ + RSI_PS_PowerStateChangePs4toPs3(); + /* Configure DCDC to give lower output voltage */ + RSI_PS_SetDcDcToLowerVoltage(); + } + if ((intfPllFreq > 90) && (!(BATT_FF->MCU_PMU_LDO_CTRL_CLEAR & MCU_SOC_LDO_LVL))) { + /* Change the power state from PS3 to PS4 */ + RSI_PS_SetDcDcToHigerVoltage(); + /* Configure DCDC to give higher output voltage.*/ + RSI_PS_PowerStateChangePs3toPs4(); + } + } + return RSI_OK; +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_IntfPllSetFreqDiv(M4CLK_Type *pCLK , boolean_t clk_en, + * uint16_t divFactor,uint16_t nFactor,uint16_t mFactor, + * uint16_t fcwF,uint16_t dcoFixSel,uint16_t ldoProg) + * @brief This API is used to divide the Intf PLL clock frequency + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] clk_en : Enble the intf_pll_clk output enale + * @param[in] divFactor : PLL post division factor ,see user for more info + * @param[in] nFactor : N factor of PLL , see user manual for more info + * @param[in] mFactor : M factor of PLL , see user manual for more info + * @param[in] fcwF : Fractional Frequency Control Word. For below 200MHz fcwF is 0 and above 200Mhz if the frequency is odd program FCW_F as 8192 + * @param[in] dcoFixSel : Dco Fixed Ring select. Please refer # Note + * @param[in] ldoProg : INTFPLL LDO output voltage select. Please refer # Note + * @return returns zero \ref RSI_OK on success ,on failure return error code. + * @note For <= 200Mhz ---> ldo_prog =4 and dco_fix_sel=1 + * - For 201-250Mhz ---> ldo_prog =5 and dco_fix_sel=0 + * - For >=251Mhz ---> ldo_prog =5 and dco_fix_sel=2 + */ +STATIC INLINE rsi_error_t RSI_CLK_IntfPllSetFreqDiv(M4CLK_Type *pCLK, + boolean_t clk_en, + uint16_t divFactor, + uint16_t nFactor, + uint16_t mFactor, + uint16_t fcwF, + uint16_t dcoFixSel, + uint16_t ldoProg) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API + ->clk_intf_pll_set_freq_div(pCLK, clk_en, divFactor, nFactor, mFactor, fcwF, dcoFixSel, ldoProg); +#else + return clk_intf_pll_set_freq_div(pCLK, clk_en, divFactor, nFactor, mFactor, fcwF, dcoFixSel, ldoProg); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_IntfPLLClkBypassEnable(boolean_t clkEnable) + * @brief This API is used to enable bypass clock + * @param[in] clkEnable : is enum value to enable or disable the clock + * - Enable : Enables bypass clock + * - Disable : Disables bypass clock + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_IntfPLLClkBypassEnable(boolean_t clkEnable) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_intf_pll_clk_bypass_enable(clkEnable); +#else + return clk_intf_pll_clk_bypass_enable(clkEnable); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_IntfPLLTurnOn() + * @brief This API is used to TurnOn the Intf_PLL + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_IntfPLLTurnOn() +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_intf_pll_turn_on(); +#else + return clk_intf_pll_turn_on(); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_IntfPllClkReset() + * @brief This API is used to Reset the Intf_pll_clk + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_IntfPllClkReset() +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_intf_pll_clk_reset(); +#else + return clk_intf_pll_clk_reset(); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_IntfPllClkSet(M4CLK_Type *pCLK) + * @brief This API is used to Enables the Intf-PLL + * @param[in] pCLK : Pointer to the pll register instance + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_IntfPllClkSet(M4CLK_Type *pCLK) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_intf_pll_clk_set(pCLK); +#else + return clk_intf_pll_clk_set(pCLK); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_PeripheralClkEnable1(M4CLK_Type *pCLK ,uint32_t flags) + * @brief This API is used to enable the peripheral clocks for SET1 register + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] flags : ORed values of peripheral bits to be enbled. + * - \ref USART1_PCLK_ENABLE + * - \ref USART1_SCLK_ENABLE + * - \ref USART2_PCLK_ENABLE + * - \ref USART2_SCLK_ENABLE + * - \ref CT_CLK_ENABLE + * - \ref CT_PCLK_ENABLE + * - \ref ICACHE_CLK_ENABLE + * - \ref ICACHE_CLK_2X_ENABLE + * - \ref GPDMA_HCLK_ENABLE + * - \ref SOC_PLL_SPI_CLK_ENABLE + * - \ref IID_CLK_ENABLE + * - \ref SDIO_SYS_HCLK_ENABLE + * - \ref CRC_CLK_ENABLE_M4 + * - \ref M4SS_UM_CLK_STATIC_EN + * - \ref ETH_HCLK_ENABLE + * - \ref HWRNG_PCLK_ENABLE + * - \ref GNSS_MEM_CLK_ENABLE + * - \ref CCI_PCLK_ENABLE + * - \ref CCI_HCLK_ENABLE + * - \ref CCI_CLK_ENABLE + * - \ref MASK_HOST_CLK_WAIT_FIX + * - \ref MASK31_HOST_CLK_CNT + * - \ref SD_MEM_INTF_CLK_ENABLE + * - \ref MASK_HOST_CLK_AVAILABLE_FIX + * @return returns zero \ref RSI_OK on success ,on failure return error code. + * + * @b Example + * - RSI_Clk_PeripheralClkEnable1(&M4CLK ,(USART1_PCLK_ENABLE | USART1_SCLK_ENABLE )); + */ +STATIC INLINE rsi_error_t RSI_CLK_PeripheralClkEnable1(M4CLK_Type *pCLK, uint32_t flags) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_peripheral_clk_enable1(pCLK, flags); +#else + return clk_peripheral_clk_enable1(pCLK, flags); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_PeripheralClkDisable1(M4CLK_Type *pCLK ,uint32_t flags) + * @brief This API is used to disable the peripheral clocks for CLR1 register + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] flags : ORed values of peripheral bits to be enbled. + * - \ref USART1_PCLK_ENABLE + * - \ref USART1_SCLK_ENABLE + * - \ref USART2_PCLK_ENABLE + * - \ref USART2_SCLK_ENABLE + * - \ref CT_CLK_ENABLE + * - \ref CT_PCLK_ENABLE + * - \ref ICACHE_CLK_ENABLE + * - \ref ICACHE_CLK_2X_ENABLE + * - \ref GPDMA_HCLK_ENABLE + * - \ref SOC_PLL_SPI_CLK_ENABLE + * - \ref IID_CLK_ENABLE + * - \ref SDIO_SYS_HCLK_ENABLE + * - \ref CRC_CLK_ENABLE_M4 + * - \ref M4SS_UM_CLK_STATIC_EN + * - \ref ETH_HCLK_ENABLE + * - \ref HWRNG_PCLK_ENABLE + * - \ref GNSS_MEM_CLK_ENABLE + * - \ref CCI_PCLK_ENABLE + * - \ref CCI_HCLK_ENABLE + * - \ref CCI_CLK_ENABLE + * - \ref MASK_HOST_CLK_WAIT_FIX + * - \ref MASK31_HOST_CLK_CNT + * - \ref SD_MEM_INTF_CLK_ENABLE + * - \ref MASK_HOST_CLK_AVAILABLE_FIX + * @return returns zero \ref RSI_OK on success ,on failure return error code. + * + * @b Example + * - RSI_Clk_PeripheralClkDisable1(&M4CLK ,(USART1_PCLK_ENABLE | USART1_SCLK_ENABLE )); + */ +STATIC INLINE rsi_error_t RSI_CLK_PeripheralClkDisable1(M4CLK_Type *pCLK, uint32_t flags) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_peripheral_clk_disable1(pCLK, flags); +#else + return clk_peripheral_clk_disable1(pCLK, flags); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_PeripheralClkEnable2(M4CLK_Type *pCLK ,uint32_t flags) + * @brief This API is used to enable the peripheral clocks for SET2 register + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] flags : ORed values of peripheral bits to be enabled. + * - \ref GEN_SPI_MST1_HCLK_ENABLE + * - \ref CAN1_PCLK_ENABLE + * - \ref CAN1_CLK_ENABLE + * - \ref UDMA_HCLK_ENABLE + * - \ref I2C_BUS_CLK_ENABLE + * - \ref I2C_2_BUS_CLK_ENABLE + * - \ref SSI_SLV_PCLK_ENABLE + * - \ref SSI_SLV_SCLK_ENABLE + * - \ref QSPI_CLK_ENABLE + * - \ref QSPI_HCLK_ENABLE + * - \ref I2SM_INTF_SCLK_ENABLE + * - \ref I2SM_PCLK_ENABLE + * - \ref QE_PCLK_ENABLE + * - \ref MCPWM_PCLK_ENABLE + * - \ref SGPIO_PCLK_ENABLE + * - \ref EGPIO_PCLK_ENABLE + * - \ref ARM_CLK_ENABLE + * - \ref SSI_MST_PCLK_ENABLE + * - \ref SSI_MST_SCLK_ENABLE + * - \ref MEM2_CLK_ENABLE + * - \ref MEM_CLK_ULP_ENABLE + * - \ref ROM_CLK_ENABLE + * - \ref PLL_INTF_CLK_ENABLE + * - \ref SEMAPHORE_CLK_ENABLE + * - \ref TOT_CLK_ENABLE + * - \ref RMII_SOFT_RESET + * @return returns zero \ref RSI_OK on success ,on failure return error code. + * + * @b Example + * - RSI_Clk_PeripheralClkEnable2(M4CLK ,(GEN_SPI_MST1_HCLK_ENABLE | SSI_MST_PCLK_ENABLE)); + */ +STATIC INLINE rsi_error_t RSI_CLK_PeripheralClkEnable2(M4CLK_Type *pCLK, uint32_t flags) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_peripheral_clk_enable2(pCLK, flags); +#else + return clk_peripheral_clk_enable2(pCLK, flags); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_PeripheralClkDisable2(M4CLK_Type *pCLK ,uint32_t flags) + * @brief This API is used to disable the peripheral clocks for CLR2 register + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] flags : ORed values of peripheral bits to be enabled. + * - \ref GEN_SPI_MST1_HCLK_ENABLE + * - \ref CAN1_PCLK_ENABLE + * - \ref CAN1_CLK_ENABLE + * - \ref UDMA_HCLK_ENABLE + * - \ref I2C_BUS_CLK_ENABLE + * - \ref I2C_2_BUS_CLK_ENABLE + * - \ref SSI_SLV_PCLK_ENABLE + * - \ref SSI_SLV_SCLK_ENABLE + * - \ref QSPI_CLK_ENABLE + * - \ref QSPI_HCLK_ENABLE + * - \ref I2SM_INTF_SCLK_ENABLE + * - \ref I2SM_PCLK_ENABLE + * - \ref QE_PCLK_ENABLE + * - \ref MCPWM_PCLK_ENABLE + * - \ref SGPIO_PCLK_ENABLE + * - \ref EGPIO_PCLK_ENABLE + * - \ref ARM_CLK_ENABLE + * - \ref SSI_MST_PCLK_ENABLE + * - \ref SSI_MST_SCLK_ENABLE + * - \ref MEM2_CLK_ENABLE + * - \ref MEM_CLK_ULP_ENABLE + * - \ref ROM_CLK_ENABLE + * - \ref PLL_INTF_CLK_ENABLE + * - \ref SEMAPHORE_CLK_ENABLE + * - \ref TOT_CLK_ENABLE + * - \ref RMII_SOFT_RESET + * @return returns zero \ref RSI_OK on success ,on failure return error code. + * + * @b Example + * - RSI_Clk_PeripheralClkDisable2(M4CLK ,(GEN_SPI_MST1_HCLK_ENABLE | SSI_MST_PCLK_ENABLE)); + */ +STATIC INLINE rsi_error_t RSI_CLK_PeripheralClkDisable2(M4CLK_Type *pCLK, uint32_t flags) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_peripheral_clk_disable2(pCLK, flags); +#else + return clk_peripheral_clk_disable2(pCLK, flags); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_PeripheralClkEnable3(M4CLK_Type *pCLK ,uint32_t flags) + * @brief This API is used to enable the peripheral clocks for SET3 register + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] flags : ORed values of peripheral bits to be enabled. + * - \ref BUS_CLK_ENABLE + * - \ref M4_CORE_CLK_ENABLE + * - \ref CM_BUS_CLK_ENABLE + * - \ref MISC_CONFIG_PCLK_ENABLE + * - \ref EFUSE_CLK_ENABLE + * - \ref ICM_CLK_ENABLE + * - \ref MEM1_CLK_ENABLE + * - \ref MEM3_CLK_ENABLE + * - \ref USB_PHY_CLK_IN_ENABLE + * - \ref QSPI_CLK_ONEHOT_ENABLE + * - \ref QSPI_M4_SOC_SYNC + * - \ref EGPIO_CLK_ENABLE + * - \ref I2C_CLK_ENABLE + * - \ref I2C_2_CLK_ENABLE + * - \ref EFUSE_PCLK_ENABLE + * - \ref SGPIO_PCLK_ENABLE + * - \ref TASS_M4SS_64K_SWITCH_CLK_ENABLE + * - \ref TASS_M4SS_128K_SWITCH_CLK_ENABLE + * - \ref TASS_M4SS_SDIO_SWITCH_CLK_ENABLE + * - \ref TASS_M4SS_USB_SWITCH_CLK_ENABLE + * - \ref ROM_MISC_STATIC_ENABLE + * - \ref M4_SOC_CLK_FOR_OTHER_ENABLE + * - \ref ICACHE_ENABLE + * @return returns zero \ref RSI_OK on success ,on failure return error code. + * + * @b Example + * - RSI_Clk_PeripheralClkEnable3(M4CLK ,(M4_SOC_CLK_FOR_OTHER_ENABLE | ROM_MISC_STATIC_ENABLE)); + */ +STATIC INLINE rsi_error_t RSI_CLK_PeripheralClkEnable3(M4CLK_Type *pCLK, uint32_t flags) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_peripheral_clk_enable3(pCLK, flags); +#else + return clk_peripheral_clk_enable3(pCLK, flags); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_PeripheralClkDisable3(M4CLK_Type *pCLK ,uint32_t flags) + * @brief This API is used to disable the peripheral clocks for CLR3 register + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] flags : ORed values of peripheral bits to be enbled. + * - \ref BUS_CLK_ENABLE + * - \ref M4_CORE_CLK_ENABLE + * - \ref CM_BUS_CLK_ENABLE + * - \ref MISC_CONFIG_PCLK_ENABLE + * - \ref EFUSE_CLK_ENABLE + * - \ref ICM_CLK_ENABLE + * - \ref MEM1_CLK_ENABLE + * - \ref MEM3_CLK_ENABLE + * - \ref USB_PHY_CLK_IN_ENABLE + * - \ref QSPI_CLK_ONEHOT_ENABLE + * - \ref QSPI_M4_SOC_SYNC + * - \ref EGPIO_CLK_ENABLE + * - \ref I2C_CLK_ENABLE + * - \ref I2C_2_CLK_ENABLE + * - \ref EFUSE_PCLK_ENABLE + * - \ref SGPIO_PCLK_ENABLE + * - \ref TASS_M4SS_64K_SWITCH_CLK_ENABLE + * - \ref TASS_M4SS_128K_SWITCH_CLK_ENABLE + * - \ref TASS_M4SS_SDIO_SWITCH_CLK_ENABLE + * - \ref TASS_M4SS_USB_SWITCH_CLK_ENABLE + * - \ref ROM_MISC_STATIC_ENABLE + * - \ref M4_SOC_CLK_FOR_OTHER_ENABLE + * - \ref ICACHE_ENABLE + * @return returns zero \ref RSI_OK on success ,on failure return error code. + * + * @b Example + * - RSI_Clk_PeripheralClkDisable3(M4CLK ,(M4_SOC_CLK_FOR_OTHER_ENABLE | ROM_MISC_STATIC_ENABLE)); + */ +STATIC INLINE rsi_error_t RSI_CLK_PeripheralClkDisable3(M4CLK_Type *pCLK, uint32_t flags) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_peripheral_clk_disable3(pCLK, flags); +#else + return clk_peripheral_clk_disable3(pCLK, flags); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_DynamicClkGateDisable(M4CLK_Type *pCLK ,uint32_t flags) + * @brief This API is used to disable the dynamic clock gate for peripherals + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] flags : ORed value of the register bits + * - \ref SDIO_SYS_HCLK_DYN_CTRL_DISABLE + * - \ref BUS_CLK_DYN_CTRL_DISABLE + * - \ref GPDMA_HCLK_DYN_CTRL_DISABLE + * - \ref EGPIO_PCLK_DYN_CTRL_DISABLE + * - \ref SGPIO_PCLK_DYN_CTRL_DISABLE + * - \ref TOT_CLK_DYN_CTRL_DISABLE + * - \ref HWRNG_PCLK_DYN_CTRL_DISABLE + * - \ref USART1_SCLK_DYN_CTRL_DISABLE + * - \ref USART1_PCLK_DYN_CTRL_DISABLE + * - \ref USART2_SCLK_DYN_CTRL_DISABLE + * - \ref USART2_PCLK_DYN_CTRL_DISABLE + * - \ref SSI_SLV_SCLK_DYN_CTRL_DISABLE + * - \ref SSI_SLV_PCLK_DYN_CTRL_DISABLE + * - \ref I2SM_INTF_SCLK_DYN_CTRL_DISABLE + * - \ref SEMAPHORE_CLK_DYN_CTRL_DISABLE + * - \ref ARM_CLK_DYN_CTRL_DISABLE + * - \ref SSI_MST_SCLK_DYN_CTRL_DISABLE + * - \ref MEM1_CLK_DYN_CTRL_DISABLE + * - \ref MEM2_CLK_DYN_CTRL_DISABLE + * - \ref MEM_CLK_ULP_DYN_CTRL_DISABLE + * - \ref MEM_CLK_ULP_DYN_CTRL_DISABLE + * - \ref SSI_MST_PCLK_DYN_CTRL_DISABLE + * - \ref ICACHE_DYN_GATING_DISABLE + * - \ref CCI_PCLK_DYN_CTRL_DISABLE + * - \ref MISC_CONFIG_PCLK_DYN_CTRL_DISABLE + * @return returns zero \ref RSI_OK on success ,on failure return error code. + * + * @b Example + * - RSI_Clk_DynamicClkGateDisable(M4CLK , (SDIO_SYS_HCLK_DYN_CTRL_DISABLE | BUS_CLK_DYN_CTRL_DISABLE)); + */ +STATIC INLINE rsi_error_t RSI_CLK_DynamicClkGateDisable(M4CLK_Type *pCLK, uint32_t flags) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_dynamic_clk_gate_disable(pCLK, flags); +#else + return clk_dynamic_clk_gate_disable(pCLK, flags); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_DynamicClkGateDisable2(M4CLK_Type *pCLK ,uint32_t flags) + * @brief This API is used to disable the dynamic clock gate for peripherals + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] flags : ORed value of the register bits + * - \ref SOC_PLL_SPI_CLK_DYN_CTRL_DISABLE + * - \ref I2C_BUS_DYN_CTRL_DISABLE + * - \ref I2C_2_BUS_CLK_DYN_CTRL_DISABLE + * - \ref CT_PCLK_DYN_CTRL_DISABLE + * - \ref CAN1_PCLK_DYN_CTRL_DISABLE + * - \ref EFUSE_CLK_DYN_CTRL_DISABLE + * - \ref EFUSE_PCLK_DYN_CTRL_DISABLE + * - \ref PWR_CTRL_CLK_DYN_CTRL_DISABLE + * @return returns zero \ref RSI_OK on success ,on failure return error code. + * + * @b Example + * - RSI_CLK_DynamicClkGateDisable2(M4CLK , (EFUSE_CLK_DYN_CTRL_DISABLE | EFUSE_PCLK_DYN_CTRL_DISABLE)); + */ +STATIC INLINE rsi_error_t RSI_CLK_DynamicClkGateDisable2(M4CLK_Type *pCLK, uint32_t flags) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_dynamic_clk_gate_disable2(pCLK, flags); +#else + return clk_dynamic_clk_gate_disable2(pCLK, flags); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_DynamicClkGateEnable(M4CLK_Type *pCLK ,uint32_t flags) + * @brief This API is used to enable the dynamic clock gate for peripherals + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] flags : ORed value of the register bits + * - \ref SDIO_SYS_HCLK_DYN_CTRL_DISABLE + * - \ref BUS_CLK_DYN_CTRL_DISABLE + * - \ref GPDMA_HCLK_DYN_CTRL_DISABLE + * - \ref EGPIO_PCLK_DYN_CTRL_DISABLE + * - \ref SGPIO_PCLK_DYN_CTRL_DISABLE + * - \ref TOT_CLK_DYN_CTRL_DISABLE + * - \ref HWRNG_PCLK_DYN_CTRL_DISABLE + * - \ref USART1_SCLK_DYN_CTRL_DISABLE + * - \ref USART1_PCLK_DYN_CTRL_DISABLE + * - \ref USART2_SCLK_DYN_CTRL_DISABLE + * - \ref USART2_PCLK_DYN_CTRL_DISABLE + * - \ref SSI_SLV_SCLK_DYN_CTRL_DISABLE + * - \ref SSI_SLV_PCLK_DYN_CTRL_DISABLE + * - \ref I2SM_INTF_SCLK_DYN_CTRL_DISABLE + * - \ref SEMAPHORE_CLK_DYN_CTRL_DISABLE + * - \ref ARM_CLK_DYN_CTRL_DISABLE + * - \ref SSI_MST_SCLK_DYN_CTRL_DISABLE + * - \ref MEM1_CLK_DYN_CTRL_DISABLE + * - \ref MEM2_CLK_DYN_CTRL_DISABLE + * - \ref MEM_CLK_ULP_DYN_CTRL_DISABLE + * - \ref MEM_CLK_ULP_DYN_CTRL_DISABLE + * - \ref SSI_MST_PCLK_DYN_CTRL_DISABLE + * - \ref ICACHE_DYN_GATING_DISABLE + * - \ref CCI_PCLK_DYN_CTRL_DISABLE + * - \ref MISC_CONFIG_PCLK_DYN_CTRL_DISABLE + * @return returns zero \ref RSI_OK on success ,on failure return error code. + * + * @b Example + * - RSI_Clk_DynamicClkGateEnable(M4CLK , (SDIO_SYS_HCLK_DYN_CTRL_DISABLE | BUS_CLK_DYN_CTRL_DISABLE)); + */ +STATIC INLINE rsi_error_t RSI_CLK_DynamicClkGateEnable(M4CLK_Type *pCLK, uint32_t flags) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_dynamic_clk_gate_enable(pCLK, flags); +#else + return clk_dynamic_clk_gate_enable(pCLK, flags); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_DynamicClkGateEnable2(M4CLK_Type *pCLK ,uint32_t flags) + * @brief This API is used to enable the dynamic clock gate for peripherals + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] flags : ORed value of the register bits + * - \ref SOC_PLL_SPI_CLK_DYN_CTRL_DISABLE + * - \ref I2C_BUS_DYN_CTRL_DISABLE + * - \ref I2C_2_BUS_CLK_DYN_CTRL_DISABLE + * - \ref CT_PCLK_DYN_CTRL_DISABLE + * - \ref CAN1_PCLK_DYN_CTRL_DISABLE + * - \ref EFUSE_CLK_DYN_CTRL_DISABLE + * - \ref EFUSE_PCLK_DYN_CTRL_DISABLE + * - \ref PWR_CTRL_CLK_DYN_CTRL_DISABLE + * @return returns zero \ref RSI_OK on success ,on failure return error code. + * + * @b Example + * - RSI_Clk_DynamicClkGateEnable2(M4CLK , (EFUSE_CLK_DYN_CTRL_DISABLE | EFUSE_PCLK_DYN_CTRL_DISABLE)); + */ +STATIC INLINE rsi_error_t RSI_CLK_DynamicClkGateEnable2(M4CLK_Type *pCLK, uint32_t flags) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_dynamic_clk_gate_enable2(pCLK, flags); +#else + return clk_dynamic_clk_gate_enable2(pCLK, flags); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_ULPSS_EnableRefClks(REF_CLK_ENABLE_T enable, SRC_TYPE_T srcType,cdDelay delayFn) + * @brief This API is used to enable the ULP reference clocks and provide delay for clock starting + * @param[in] enable : To enable the particular reference clock. See \ref REF_CLK_ENABLE_T for more info + * @param[in] srcType : To select the pheripheral clock or processor clk. See \ref SRC_TYPE_T for more info + * @param[in] delayFn : Call back fuction used to create delay by using loops or timers in application code + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_ULPSS_EnableRefClks(REF_CLK_ENABLE_T enable, SRC_TYPE_T srcType, cdDelay delayFn) +{ +#if defined(A11_ROM) && defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->ulpss_enable_ref_clks(enable, srcType, delayFn); +#else + return ulpss_enable_ref_clks(enable, srcType, delayFn); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_ULPSS_DisableRefClks(REF_CLK_ENABLE_T clk_type) + * @brief This API is used to disable the ULP reference clocks + * @param[in] clk_type : To enable the particular reference clock. See \ref REF_CLK_ENABLE_T for more info + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_ULPSS_DisableRefClks(REF_CLK_ENABLE_T clk_type) +{ +#if defined(A11_ROM) && defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->ulpss_disable_ref_clks(clk_type); +#else + return ulpss_disable_ref_clks(clk_type); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_M4ssRefClkConfig(M4CLK_Type *pCLK ,M4SS_REF_CLK_SEL_T clkSource) + * @brief This API is used to configure the m4ss_ref clocks + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] clkSource : Enum values of different M4 ref source clocks \ref M4SS_REF_CLK_SEL_T + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_M4ssRefClkConfig(M4CLK_Type *pCLK, M4SS_REF_CLK_SEL_T clkSource) +{ + return clk_m4ss_ref_clk_config(pCLK, clkSource); +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_M4SocClkConfig(M4CLK_Type *pCLK ,M4_SOC_CLK_SRC_SEL_T clkSource , + uint32_t divFactor) + * @brief This API is used to configure the m4_soc clocks + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] clkSource : Enum values of different SOC source clocks.See #M4_SOC_CLK_SRC_SEL_T and NOTE for more info + * @param[in] divFactor : division value for M4SOC clock + * @return returns zero \ref RSI_OK on success ,on failure return error code. + * @note For using UlpRefClk clksource need to configure M4ssRefClk frequency. For that need to call \ref RSI_CLK_M4ssRefClkConfig Api first + * - For using SocPllCLK clksource need to configure SocPll frequency. For that need to call \ref RSI_CLK_SetSocPllFreq Api first + * - For using IntfPllCLK clksource need to configure IntfPll frequency. For that need to call \ref RSI_CLK_SetIntfPllFreq Api first + * - For using Sleep clksource need to configure Sleep Clock. For that need to call \ref RSI_CLK_SlpClkConfig Api first + */ +STATIC INLINE rsi_error_t RSI_CLK_M4SocClkConfig(M4CLK_Type *pCLK, M4_SOC_CLK_SRC_SEL_T clkSource, uint32_t divFactor) +{ + return clk_m4_soc_clk_config(pCLK, clkSource, divFactor); +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_QspiClkConfig(M4CLK_Type *pCLK ,QSPI_CLK_SRC_SEL_T clkSource,boolean_t swalloEn, + boolean_t OddDivEn,uint32_t divFactor) + * @brief This API is used to configure the Qspi clocks + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] clkSource : Enum valuse for Qspi clock sources to be selected. + see possible Qspi clock sources at \ref QSPI_CLK_SRC_SEL_T + * @param[in] swalloEn : To enable or disable the swallo functionality. See user manual for more info + * - 1 : swalloEn enabled + * - 0 : swalloEn disabled + * @param[in] OddDivEn : To enable or disable the odd div functionality. See user manual for more info + * - 1 : OddDivEn enabled + * - 0 : OddDivEn disabled + * @param[in] divFactor : Division value for Qspi Clock + * @return returns zero \ref RSI_OK on success ,on failure return error code. + * @note For using UlpRefClk clksource need to configure M4ssRefClk frequency. + \n For that need to call \ref RSI_CLK_M4ssRefClkConfig Api first + */ +STATIC INLINE rsi_error_t RSI_CLK_QspiClkConfig(M4CLK_Type *pCLK, + QSPI_CLK_SRC_SEL_T clkSource, + boolean_t swalloEn, + boolean_t OddDivEn, + uint32_t divFactor) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_qspi_clk_config(pCLK, clkSource, swalloEn, OddDivEn, divFactor); +#else + return clk_qspi_clk_config(pCLK, clkSource, swalloEn, OddDivEn, divFactor); +#endif +} +#ifdef SLI_SI917B0 + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_Qspi2ClkConfig(M4CLK_Type *pCLK ,QSPI_CLK_SRC_SEL_T clkSource,boolean_t swalloEn, + boolean_t OddDivEn,uint32_t divFactor) + * @brief This API is used to configure the Qspi clocks + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] clkSource : Enum valuse for Qspi clock sources to be selected. + see possible Qspi clock sources at \ref QSPI_CLK_SRC_SEL_T + * @param[in] swalloEn : To enable or disable the swallo functionality. See user manual for more info + * - 1 : swalloEn enabled + * - 0 : swalloEn disabled + * @param[in] OddDivEn : To enable or disable the odd div functionality. See user manual for more info + * - 1 : OddDivEn enabled + * - 0 : OddDivEn disabled + * @param[in] divFactor : Division value for Qspi Clock + * @return returns zero \ref RSI_OK on success ,on failure return error code. + * @note For using UlpRefClk clksource need to configure M4ssRefClk frequency. + \n For that need to call \ref RSI_CLK_M4ssRefClkConfig Api first + */ +STATIC INLINE rsi_error_t RSI_CLK_Qspi2ClkConfig(M4CLK_Type *pCLK, + QSPI_CLK_SRC_SEL_T clkSource, + boolean_t swalloEn, + boolean_t OddDivEn, + uint32_t divFactor) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_qspi_2_clk_config(pCLK, clkSource, swalloEn, OddDivEn, divFactor); +#else + return clk_qspi_2_clk_config(pCLK, clkSource, swalloEn, OddDivEn, divFactor); +#endif +} +#endif +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_UsartClkConfig(M4CLK_Type *pCLK ,CLK_ENABLE_T clkType,boolean_t FracDivEn, + EN_USART_T enUsart,USART_CLK_SRC_SEL_T clkSource,uint32_t divFactor) + * @brief This API is used to configure the Usart clocks + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] clkType : Boolean value to enable or disable clock mode + * - 1 Enable : Enables the Usart clock + * - 0 Disable: Disables the Usart clock + * @param[in] FracDivEn : To enable or disable Fractional Division functionality + * - 1 : FracDivEn enabled + * - 0 : FracDivEn disabled + * @param[in] enUsart : Enum values for different Usart instances see possible bypass clock sources at \ref EN_USART_T + * @param[in] clkSource : Enum values for Usart clock sources to be selected. see possible Usart clock sources at #USART_CLK_SRC_SEL_T + * @param[in] divFactor is the division value for Usart Clock + * @return returns zero \ref RSI_OK on success ,on failure return error code. + * @note For using UlpRefClk clksource need to configure M4ssRefClk frequency. For that need to call #ROM_CLK_M4ssRefClkConfig Api first + */ +STATIC INLINE rsi_error_t RSI_CLK_UsartClkConfig(M4CLK_Type *pCLK, + CLK_ENABLE_T clkType, + boolean_t FracDivEn, + EN_USART_T enUsart, + USART_CLK_SRC_SEL_T clkSource, + uint32_t divFactor) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_usart_clk_config(pCLK, clkType, FracDivEn, enUsart, clkSource, divFactor); +#else + return clk_usart_clk_config(pCLK, clkType, FracDivEn, enUsart, clkSource, divFactor); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_SsiMstClkConfig(M4CLK_Type *pCLK ,CLK_ENABLE_T clkType , + SSI_MST_CLK_SRC_SEL_T clkSource ,uint32_t divFactor) + * @brief This API is used to configure the SSI clocks + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] clkType : Enum value to select static clock or dynamic clock. See #CLK_ENABLE_T for more info. + * @param[in] clkSource : Enum values for SSI clock sources to be selected. see possible SSI clock sources at #SSI_MST_CLK_SRC_SEL_T + * @param[in] divFactor : is the division value for SSI Clock + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_SsiMstClkConfig(M4CLK_Type *pCLK, + CLK_ENABLE_T clkType, + SSI_MST_CLK_SRC_SEL_T clkSource, + uint32_t divFactor) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_ssi_mst_clk_config(pCLK, clkType, clkSource, divFactor); +#else + return clk_ssi_mst_clk_config(pCLK, clkType, clkSource, divFactor); +#endif +} + +#ifdef CHIP_9118 +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_SdMemClkConfig(M4CLK_Type *pCLK ,boolean_t swalloEn ,SDMEM_CLK_SRC_SEL_T clkSource , + uint32_t divFactor) + * @brief This API is used to configure the SdMem clocks + * @param[in] pCLK : Pointer to pll register instance + * @param[in] swalloEn : Enable or disable the swallo functionality + * - 1 : swalloEn enabled + * - 0 : swalloEn disabled + * @param[in] clkSource : Enum values for SdMem clock sources to be selected. see possible SdMem clock sources at #SDMEM_CLK_SRC_SEL_T + * @param[in] divFactor : Division value for SdMem Clock + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_SdMemClkConfig(M4CLK_Type *pCLK, + boolean_t swalloEn, + SDMEM_CLK_SRC_SEL_T clkSource, + uint32_t divFactor) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_sd_mem_clk_config(pCLK, swalloEn, clkSource, divFactor); +#else + return clk_sd_mem_clk_config(pCLK, swalloEn, clkSource, divFactor); +#endif +} +#endif + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_CtClkConfig(M4CLK_Type *pCLK ,CT_CLK_SRC_SEL_T clkSource ,uint32_t divFactor, + CLK_ENABLE_T clkType) + * @brief This API is used to configure the CT clocks + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] clkSource : Enum values for CT clock sources to be selected. see possible CT clock + sources at \ref CT_CLK_SRC_SEL_T + * @param[in] divFactor : Division value for CT Clock + * @param[in] clkType : Enum value to select static clock or dynamic clock. See \ref CLK_ENABLE_T for more info. + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_CtClkConfig(M4CLK_Type *pCLK, + CT_CLK_SRC_SEL_T clkSource, + uint32_t divFactor, + CLK_ENABLE_T clkType) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_ct_clk_config(pCLK, clkSource, divFactor, clkType); +#else + return clk_ct_clk_config(pCLK, clkSource, divFactor, clkType); +#endif +} + +#ifdef CHIP_9118 +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_CciClkConfig(M4CLK_Type *pCLK ,CCI_CLK_SRC_SEL_T clkSource ,uint32_t divFactor, + CLK_ENABLE_T clkType) + * @brief This API is used to configure the CCI clocks + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] clkSource : Enum values for CCI clock sources to be selected. see possible CCI clock sources at #CCI_CLK_SRC_SEL_T + * @param[in] divFactor : Division value for CCI Clock + * @param[in] clkType : Enum value to select static clock or dynamic clock. See #CLK_ENABLE_T for more info. + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_CciClkConfig(M4CLK_Type *pCLK, + CCI_CLK_SRC_SEL_T clkSource, + uint32_t divFactor, + CLK_ENABLE_T clkType) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_cci_clk_config(pCLK, clkSource, divFactor, clkType); +#else + return clk_cci_clk_config(pCLK, clkSource, divFactor, clkType); +#endif +} +#endif + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_I2sClkConfig(M4CLK_Type *pCLK ,I2S_CLK_SRC_SEL_T clkSource , + uint32_t divFactor) + * @brief This API is used to configure the I2S clocks + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] clkSource : Enum valuse for I2S clock sources to be selected. see possible I2S clock sources at #I2S_CLK_SRC_SEL_T + * @param[in] divFactor : Division value for I2S Clock + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_I2sClkConfig(M4CLK_Type *pCLK, I2S_CLK_SRC_SEL_T clkSource, uint32_t divFactor) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_i2s_clk_config(pCLK, clkSource, divFactor); +#else + return clk_i2s_clk_config(pCLK, clkSource, divFactor); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_McuClkOutConfig(M4CLK_Type *pCLK ,MCU_CLKOUT_SRC_SEL_T clkSource , + uint32_t divFactor) + * @brief This API is used to configure the McuClkOut clocks + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] clkSource : Enum values of MCU_CLKOUT. See possible mcu_clk sources at #MCU_CLKOUT_SRC_SEL_T + * @param[in] divFactor : Division value for McuClkOut Clock + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_McuClkOutConfig(M4CLK_Type *pCLK, MCU_CLKOUT_SRC_SEL_T clkSource, uint32_t divFactor) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_mcu_clk_cut_config(pCLK, clkSource, divFactor); +#else + return clk_mcu_clk_cut_config(pCLK, clkSource, divFactor); +#endif +} + +#ifdef CHIP_9118 +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_CanClkConfig(M4CLK_Type *pCLK , uint32_t divFactor,CLK_ENABLE_T clkType) + * @brief This API is used to configure the Can clocks + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] divFactor : Division value for Can Clock + * @param[in] clkType : Enum value to select static clock or dynamic clock. See #CLK_ENABLE_T for more info. + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_CanClkConfig(M4CLK_Type *pCLK, uint32_t divFactor, CLK_ENABLE_T clkType) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_can_clk_config(pCLK, divFactor, clkType); +#else + return clk_can_clk_config(pCLK, divFactor, clkType); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_EthernetClkConfig(M4CLK_Type *pCLK ,boolean_t swalloEn ,ETHERNET_CLK_SRC_SEL_T clkSource, + uint32_t divFactor) + * @brief This API is used to configure the PLL_INTF clocks + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] swalloEn : Enable or disable the swallo functionality + * - 1 : Swallo enabled + * - 0 : Swallo disabled + * @param[in] clkSource : Enum values for PLL_Intf clock sources to be selected. see possible PLl clock sources at #ETHERNET_CLK_SRC_SEL_T + * @param[in] divFactor : PLL_INTF clock division value + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_EthernetClkConfig(M4CLK_Type *pCLK, + boolean_t swalloEn, + ETHERNET_CLK_SRC_SEL_T clkSource, + uint32_t divFactor) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_ethernet_clk_config(pCLK, swalloEn, clkSource, divFactor); +#else + return clk_ethernet_clk_config(pCLK, swalloEn, clkSource, divFactor); +#endif +} +#endif + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_M4SocClkDiv(M4CLK_Type *pCLK ,uint32_t divFactor) + * @brief This API is used to divide the M4soc clock + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] divFactor : M4Soc clock division value + * @return returns 0 on success + * \n Error code on failure + */ +STATIC INLINE rsi_error_t RSI_CLK_M4SocClkDiv(M4CLK_Type *pCLK, uint32_t divFactor) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_m4_soc_clk_div(pCLK, divFactor); +#else + return clk_m4_soc_clk_div(pCLK, divFactor); +#endif +} + +/** + * @fn RSI_CLK_QspiClkDiv(M4CLK_Type *pCLK , boolean_t u8SwallowEn , + boolean_t u8OddDivEn , uint32_t divFactor ) + * @brief This API is used to divide the QSPI clock + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] u8SwallowEn : To enable or disable the swallo functionality + * - 1 : Swallo enabled + * - 0 : Swallo disabled + * @param[in] u8OddDivEn : To enable or disable the odd division functionality + * - 1 : Odd division enabled + * - 0 : Odd division disabled + * @param[in] divFactor : QSPI clock division value + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_QspiClkDiv(M4CLK_Type *pCLK, + boolean_t u8SwallowEn, + boolean_t u8OddDivEn, + uint32_t divFactor) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_qspi_clk_div(pCLK, u8SwallowEn, u8OddDivEn, divFactor); +#else + return clk_qspi_clk_div(pCLK, u8SwallowEn, u8OddDivEn, divFactor); + ; +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_CtClkDiv(M4CLK_Type *pCLK , uint32_t divFactor) + * @brief This API is used to divide the CT clock + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] divFactor : CT clock division value + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_CtClkDiv(M4CLK_Type *pCLK, uint32_t divFactor) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_ct_clk_div(pCLK, divFactor); +#else + return clk_ct_clk_div(pCLK, divFactor); + ; +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_SsiMstClkDiv(M4CLK_Type *pCLK , uint32_t divFactor ) + * @brief This API is used to divide the SSI clock + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] divFactor : SSI clock division value + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_SsiMstClkDiv(M4CLK_Type *pCLK, uint32_t divFactor) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_ssi_mst_clk_div(pCLK, divFactor); +#else + return clk_ssi_mst_clk_div(pCLK, divFactor); + ; +#endif +} + +#ifdef CHIP_9118 +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_CciClkDiv(M4CLK_Type *pCLK , uint32_t divFactor ) + * @brief This API is used to divide the CCI clock + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] divFactor : CCI clock division value + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_CciClkDiv(M4CLK_Type *pCLK, uint32_t divFactor) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_cci_clk_div(pCLK, divFactor); +#else + return clk_cci_clk_div(pCLK, divFactor); + ; +#endif +} +#endif + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_I2sClkDiv(M4CLK_Type *pCLK , uint32_t divFactor ) + * @brief This API is used to divide the I2S clock + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] divFactor : I2S clock division value + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_I2sClkDiv(M4CLK_Type *pCLK, uint32_t divFactor) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_i2s_clk_div(pCLK, divFactor); +#else + return clk_i2s_clk_div(pCLK, divFactor); + ; +#endif +} + +#ifdef CHIP_9118 +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_SdmemClkDiv(M4CLK_Type *pCLK , boolean_t u8SwallowEn , uint32_t divFactor) + * @brief This API is used to divide the SDMEM clock + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] u8SwallowEn : To enable or disable the swallo functionality + * - 1 : Swallo enabled + * - 0 : Swallo disabled + * @param[in] divFactor : SDMEM clock division value + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_SdmemClkDiv(M4CLK_Type *pCLK, boolean_t u8SwallowEn, uint32_t divFactor) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_sd_mem_clk_div(pCLK, u8SwallowEn, divFactor); +#else + return clk_sd_mem_clk_div(pCLK, u8SwallowEn, divFactor); +#endif +} +#endif + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_UsartClkDiv(M4CLK_Type *pCLK , EN_USART_T EN_USART_T , + uint8_t u8FracDivEn, uint32_t divFactor) + * @brief This API is used to divide the USART/UART clock + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] EN_USART_T : Enum of uart numbers. See #EN_USART_T for more info + * @param[in] u8FracDivEn : To enable or disable fractional division feature + * - 1 : Clock Swallo type divider is selected + * - 0 : Fractional Divider typed is selected + * @param[in] divFactor : USART/UART clock division value + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_UsartClkDiv(M4CLK_Type *pCLK, + EN_USART_T EN_USART, + uint8_t u8FracDivEn, + uint32_t divFactor) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_usart_clk_div(pCLK, EN_USART, u8FracDivEn, divFactor); +#else + return clk_usart_clk_div(pCLK, EN_USART, u8FracDivEn, divFactor); +#endif +} + +/** + * @fn uint32_t RSI_CLK_SlpClkCalibConfig(M4CLK_Type *pCLK , uint8_t clkCycles) + * @brief This API is used to calibrate the sleep clock + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] clkCycles : These bits are used to program the number of clock cycles over which + clock calibration is to be done. + * - 00 => 1 Cycle + * - 01 => 2 Cycles + * - 10 => 3 Cycles + * - 11 => 4 Cycles + * @return Returns the calibration duration. + */ +STATIC INLINE uint32_t RSI_CLK_SlpClkCalibConfig(M4CLK_Type *pCLK, uint8_t clkCycles) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_slp_clk_calib_config(pCLK, clkCycles); +#else + return clk_slp_clk_calib_config(pCLK, clkCycles); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_GspiClkConfig(M4CLK_Type *pCLK ,GSPI_CLK_SRC_SEL_T clkSel ) + * @brief This API is used to configure the GSPI Clocks + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] clkSel : Enum values to select the clock sources. See possible values at \ref GSPI_CLK_SRC_SEL_T + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_GspiClkConfig(M4CLK_Type *pCLK, GSPI_CLK_SRC_SEL_T clkSel) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_gspi_clk_config(pCLK, clkSel); +#else + return clk_gspi_clk_config(pCLK, clkSel); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_SlpClkConfig(M4CLK_Type *pCLK , SLEEP_CLK_SRC_SEL_T clkSrc) + * @brief This API is used to configure the SLEEP Clocks + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] clkSrc : Enum values to select the clock sources for sleep clock. See \ref SLEEP_CLK_SRC_SEL_T for more info + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_SlpClkConfig(M4CLK_Type *pCLK, SLEEP_CLK_SRC_SEL_T clkSrc) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_slp_clk_config(pCLK, clkSrc); +#else + return clk_slp_clk_config(pCLK, clkSrc); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_I2CClkConfig(M4CLK_Type *pCLK , boolean_t clkEnable,EN_I2C_T enI2C) + * @brief This API is used to configure the I2C clock + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] clkEnable : Boolean value to enable or disable clock mode + * - 1 clkEnable : Enables the I2C clock + * - 0 Disable : Disables the I2C clock + * @param[in] enI2C : Enum values. See \ref EN_I2C_T for more infomation + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_I2CClkConfig(M4CLK_Type *pCLK, boolean_t clkEnable, EN_I2C_T enI2C) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_i2c_clk_config(pCLK, clkEnable, enI2C); +#else + return clk_i2c_clk_config(pCLK, clkEnable, enI2C); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_XtalClkConfig(uint8_t xtalPin) + * @brief This API is used to configure the Xtal clock + * @param[in] xtalPin : Pin number of NPSS_GPIO. Possible values are 0,1,2,3,4 + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_XtalClkConfig(uint8_t xtalPin) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_xtal_clk_config(xtalPin); +#else + return clk_xtal_clk_config(xtalPin); +#endif +} + +#ifdef CHIP_9118 +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_USBClkConfig(M4CLK_Type *pCLK ,USB_CLK_SRC_SEL_T clkSource ,uint16_t divFactor) + * @brief This API is used to configure the USB clock + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] clkSource : Different clock sources for USB_PHY_CLK. See #USB_CLK_SRC_SEL_T for more info + * @param[in] divFactor : USB clock division value + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_USBClkConfig(M4CLK_Type *pCLK, USB_CLK_SRC_SEL_T clkSource, uint16_t divFactor) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_usb_clk_config(pCLK, clkSource, divFactor); +#else + return clk_usb_clk_config(pCLK, clkSource, divFactor); +#endif +} +#endif + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_PeripheralClkEnable(M4CLK_Type *pCLK ,PERIPHERALS_CLK_T module,CLK_ENABLE_T clkType) + * @brief This API is used to enable the particular clock + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] module : To select particular pheripheral. + * @param[in] clkType : To select the clock as dynamic or static clock. + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_PeripheralClkEnable(M4CLK_Type *pCLK, PERIPHERALS_CLK_T module, CLK_ENABLE_T clkType) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_peripheral_clk_enable(pCLK, module, clkType); +#else + return clk_peripheral_clk_enable(pCLK, module, clkType); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_PeripheralClkDisable(M4CLK_Type *pCLK ,PERIPHERALS_CLK_T module) + * @brief This API is used to disable the particular clock + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] module : To select particular peripheral. + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_PeripheralClkDisable(M4CLK_Type *pCLK, PERIPHERALS_CLK_T module) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_peripheral_clk_disable(pCLK, module); +#else + return clk_peripheral_clk_disable(pCLK, module); +#endif +} + +/** + *@fn void RSI_CLK_SocPllLockConfig(boolean_t manual_lock , boolean_t bypass_manual_lock , uint8_t mm_count_limit) + *@brief This API is used to configure the SOC-PLL lock settings + *@param[in] manual_lock : Enable for manual mode phase lock generation + *@param[in] bypass_manual_lock : Bypass signal for phase detector logic + *@param[in] mm_count_limit : Lock count limit in manual mode phase lock generation + */ +STATIC INLINE void RSI_CLK_SocPllLockConfig(boolean_t manual_lock, boolean_t bypass_manual_lock, uint8_t mm_count_limit) +{ +#if defined(A11_ROM) && defined(CLOCK_ROMDRIVER_PRESENT) + ROMAPI_M4SS_CLK_API->clk_config_pll_lock(manual_lock, bypass_manual_lock, mm_count_limit); +#else + clk_config_pll_lock(manual_lock, bypass_manual_lock, mm_count_limit); +#endif +} + +/** + *@fn STATIC INLINE void RSI_CLK_SocPllRefClkConfig(uint8_t ref_clk_src) + *@brief This API is used to configure SOC-PLL config + *@param[in] ref_clk_src : Reference clock to be programmed. + */ +STATIC INLINE void RSI_CLK_SocPllRefClkConfig(uint8_t ref_clk_src) +{ +#if defined(A11_ROM) && defined(CLOCK_ROMDRIVER_PRESENT) + ROMAPI_M4SS_CLK_API->clk_config_pll_ref_clk(ref_clk_src); +#else + clk_config_pll_ref_clk(ref_clk_src); +#endif +} + +#ifdef __cplusplus +} +#endif + +#endif //__RSI_ROM_CLK_H_ + +/*@} end of RSI_M4SS_CLOCK_DRIVERS */ + +/* @} end of RSI_CHIP_CLOCK_DRIVERS */ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_egpio.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_egpio.h new file mode 100644 index 000000000..2f7e37bfe --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_egpio.h @@ -0,0 +1,1201 @@ +/******************************************************************************* +* @file rsi_rom_egpio.h +* @brief +******************************************************************************* +* # License +* Copyright 2020 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +//Includes + +#ifndef __RSI_ROM_EGPIO_H__ +#define __RSI_ROM_EGPIO_H__ + +/** + * \ingroup RSI_SPECIFIC_DRIVERS + * \defgroup EGPIO_DRIVER + * @{ + * + */ +#ifdef __cplusplus +extern "C" { +#endif + +#include "rsi_ccp_user_config.h" +#include "rsi_packing.h" +#include "rsi_egpio.h" +#if defined(A11_ROM) +#include "rsi_rom_table_si91x.h" +#else +#include "rsi_rom_table_RS1xxxx.h" +#endif +/** @addtogroup SOC11 +* @{ +*/ + +/** + * @fn STATIC INLINE void RSI_EGPIO_SetDir(EGPIO_Type *pEGPIO ,uint8_t port,uint8_t pin, boolean_t dir) + * @brief This API is used to set the EGPIO direction(Direction of the GPIO pin. '1' for INPUT, '0' for OUTPUT) + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] port : GPIO port number + * @param[in] pin : GPIO pin number + * @param[in] dir : boolean type pin direction + * \n '0' : Output + * \n '1' : Input + * @return None + */ +STATIC INLINE void RSI_EGPIO_SetDir(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin, boolean_t dir) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_set_dir(pEGPIO, port, pin, dir); +#else + egpio_set_dir(pEGPIO, port, pin, dir); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_SetPin(EGPIO_Type *pEGPIO ,uint8_t port,uint8_t pin , uint8_t val) + * @brief This API is used to set the GPIO pin value.It Loads 0th bit on to the pin on write & + * reads the value on pin on read into 0th bit + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] port : GPIO port number + * @param[in] pin : GPIO pin number + * @param[in] val : value to be set for the pin + * \n '0' : Logic on Pin + * \n '1' : Logic on Pin + * @return None + */ +STATIC INLINE void RSI_EGPIO_SetPin(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin, uint8_t val) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_set_pin(pEGPIO, port, pin, val); +#else + egpio_set_pin(pEGPIO, port, pin, val); +#endif +} + +/** + * @fn STATIC INLINE boolean_t RSI_EGPIO_GetPin(EGPIO_Type *pEGPIO ,uint8_t port,uint8_t pin) + * @brief This API is used get the GPIO pin status. + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] port : GPIO port number + * @param[in] pin : GPIO pin number + * @return returns Pin status + */ +STATIC INLINE boolean_t RSI_EGPIO_GetPin(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin) +{ +#if defined(ROMDRIVER_PRESENT) + return ROMAPI_EGPIO_API->egpio_get_pin(pEGPIO, port, pin); +#else + return egpio_get_pin(pEGPIO, port, pin); +#endif +} + +/** + * @fn STATIC INLINE boolean_t RSI_EGPIO_GetDir(EGPIO_Type *pEGPIO,uint8_t port ,uint8_t pin) + * @brief This API is used to Get the Direction GPIO(Direction of the GPIO pin. '1' for INPUT,and '0'for OUTPUT) + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] port : GPIO port number + * @param[in] pin : GPIO pin number + * @return returns the GPIO direction value + */ +STATIC INLINE boolean_t RSI_EGPIO_GetDir(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin) +{ +#if defined(ROMDRIVER_PRESENT) + return ROMAPI_EGPIO_API->egpio_get_dir(pEGPIO, port, pin); +#else + return egpio_get_dir(pEGPIO, port, pin); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_PinIntSel(EGPIO_Type *pEGPIO ,uint8_t intCh ,uint8_t port , uint8_t pin) + * @brief This API is used to select the pin for interrupt generation + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] intCh : GPIO pin interrupt channel number (0 to 7) + * @param[in] port : GPIO port number + * @param[in] pin : GPIO pin number + * @return None + */ +STATIC INLINE void RSI_EGPIO_PinIntSel(EGPIO_Type *pEGPIO, uint8_t intCh, uint8_t port, uint8_t pin) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_pin_int_sel(pEGPIO, intCh, port, pin); +#else + egpio_pin_int_sel(pEGPIO, intCh, port, pin); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_SetIntFallEdgeEnable(EGPIO_Type *pEGPIO ,uint8_t intCh) + * @brief This API is used to set the pin interrupt mode configuration + * \n(enables interrupt generation when falling edge is detected on pin '1' for intr enabled and '0' for disabled) + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] intCh : GPIO pin interrupt channel number (0 to 7) + * @return None + */ +STATIC INLINE void RSI_EGPIO_SetIntFallEdgeEnable(EGPIO_Type *pEGPIO, uint8_t intCh) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_set_int_fall_edge_enable(pEGPIO, intCh); +#else + egpio_set_int_fall_edge_enable(pEGPIO, intCh); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_SetIntFallEdgeDisable(EGPIO_Type *pEGPIO ,uint8_t intCh) + * @brief This API to used to set the pin interrupt mode configuration + * \n(enables interrupt generation when falling edge is detected on pin '1' for intr enabled and '0' for disabled) + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] intCh : GPIO pin interrupt channel number (0 to 7) + * @return None + */ +STATIC INLINE void RSI_EGPIO_SetIntFallEdgeDisable(EGPIO_Type *pEGPIO, uint8_t intCh) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_set_int_fall_edge_disable(pEGPIO, intCh); +#else + egpio_set_int_fall_edge_disable(pEGPIO, intCh); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_SetIntRiseEdgeEnable(EGPIO_Type *pEGPIO ,uint8_t intCh) + * @brief This API to used to set the pin interrupt mode configuration + * \n(enables interrupt generation when rising edge is detected on pin '1' for intr enabled and '0' for disabled) + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] intCh : GPIO pin interrupt channel number (0 to 7) + * @return None + */ +STATIC INLINE void RSI_EGPIO_SetIntRiseEdgeEnable(EGPIO_Type *pEGPIO, uint8_t intCh) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_set_int_rise_edge_enable(pEGPIO, intCh); +#else + egpio_set_int_rise_edge_enable(pEGPIO, intCh); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_SetIntRiseEdgeDisable(EGPIO_Type *pEGPIO ,uint8_t intCh) + * @brief This API to used to set the pin interrupt mode configuration + * \n(enables interrupt generation when rising edge is detected on pin '1' for intr enabled '0' for disabled) + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] intCh : GPIO pin interrupt channel number (0 to 7) + * @return None + */ +STATIC INLINE void RSI_EGPIO_SetIntRiseEdgeDisable(EGPIO_Type *pEGPIO, uint8_t intCh) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_set_int_rise_edge_disable(pEGPIO, intCh); +#else + egpio_set_int_rise_edge_disable(pEGPIO, intCh); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_SetIntLowLevelEnable(EGPIO_Type *pEGPIO ,uint8_t intCh) + * @brief This API is used to set the pin interrupt mode configuration + * \n (enables interrupt generation when pin level is 0, '1' for intr enabled, '0' for disabled) + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] intCh : GPIO pin interrupt channel number (0 to 7) + * @return None + */ +STATIC INLINE void RSI_EGPIO_SetIntLowLevelEnable(EGPIO_Type *pEGPIO, uint8_t intCh) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_set_int_low_level_enable(pEGPIO, intCh); +#else + egpio_set_int_low_level_enable(pEGPIO, intCh); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_IntMask(EGPIO_Type *pEGPIO ,uint8_t intCh) + * @brief This API is used to set the pin interrupt mode configuration + * \n(Masks the interrupt. Interrupt will still be seen in status register when enabled + * '1' for intr masked '0' for intr unmasked) + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] intCh : GPIO pin interrupt channel number (0 to 7) + * @return None + */ +STATIC INLINE void RSI_EGPIO_IntMask(EGPIO_Type *pEGPIO, uint8_t intCh) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_int_mask(pEGPIO, intCh); +#else + egpio_int_mask(pEGPIO, intCh); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_IntUnMask(EGPIO_Type *pEGPIO ,uint8_t intCh) + * @brief This API is used to used to set the pin interrupt mode configuration + * \n(UnMasks the interrupt. + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] intCh : GPIO pin interrupt channel number (0 to 7) + * @return None + */ +STATIC INLINE void RSI_EGPIO_IntUnMask(EGPIO_Type *pEGPIO, uint8_t intCh) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_int_un_mask(pEGPIO, intCh); +#else + egpio_int_un_mask(pEGPIO, intCh); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_SetIntLowLevelDisable(EGPIO_Type *pEGPIO ,uint8_t intCh) + * @brief This API is used to set the pin interrupt mode configuration + * \n(enables interrupt generation when pin level is 0 ,'1' for intr enabled '0' for disabled) + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] intCh : GPIO pin interrupt channel number (0 to 7) + * @return None + */ +STATIC INLINE void RSI_EGPIO_SetIntLowLevelDisable(EGPIO_Type *pEGPIO, uint8_t intCh) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_set_int_low_level_disable(pEGPIO, intCh); +#else + egpio_set_int_low_level_disable(pEGPIO, intCh); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_SetIntHighLevelEnable(EGPIO_Type *pEGPIO ,uint8_t intCh) + * @brief This API used to set the pin interrupt mode configuration + * \n(enables interrupt generation when pin level is 1, '1' for intr enabled '0' for disabled) + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] intCh : GPIO pin interrupt channel number (0 to 7) + * @return None + */ +STATIC INLINE void RSI_EGPIO_SetIntHighLevelEnable(EGPIO_Type *pEGPIO, uint8_t intCh) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_set_int_high_level_enable(pEGPIO, intCh); +#else + egpio_set_int_high_level_enable(pEGPIO, intCh); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_SetIntHighLevelDisable(EGPIO_Type *pEGPIO ,uint8_t intCh) + * @brief This API is used to used to set the pin interrupt mode configuration + \n(disables interrupt generation when pin level is 1 ,'1' for intr enabled '0' for disabled) + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] intCh : GPIO pin interrupt channel number (0 to 7) + * @return None + */ +STATIC INLINE void RSI_EGPIO_SetIntHighLevelDisable(EGPIO_Type *pEGPIO, uint8_t intCh) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_set_int_high_level_disable(pEGPIO, intCh); +#else + egpio_set_int_high_level_disable(pEGPIO, intCh); +#endif +} + +/** + * @fn uint8_t RSI_EGPIO_GetIntStat(EGPIO_Type *pEGPIO ,uint8_t intCh) + * @brief This API is used to get the pin interrupt status register + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] intCh : GPIO pin interrupt channel number (0 to 7) + * @return returns the interrupt status register + */ +STATIC INLINE uint8_t RSI_EGPIO_GetIntStat(EGPIO_Type *pEGPIO, uint8_t intCh) +{ +#if defined(ROMDRIVER_PRESENT) + return ROMAPI_EGPIO_API->egpio_get_int_stat(pEGPIO, intCh); +#else + return egpio_get_int_stat(pEGPIO, intCh); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_IntClr(EGPIO_Type *pEGPIO ,uint8_t intCh , uint8_t flags) + * @brief This API is used to clear the pin interrupt in status register + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] intCh : GPIO pin interrupt channel number (0 to 7) + * @param[in] flags : GPIO pin interrupt channel number (0 to 7) + \n 2- \ref EGPIO_PIN_INT_CLR_FALLING + \n 1- \ref EGPIO_PIN_INT_CLR_RISING + \n 0- \ref INTERRUPT_STATUS_CLR + * @return None + */ +STATIC INLINE void RSI_EGPIO_IntClr(EGPIO_Type *pEGPIO, uint8_t intCh, uint8_t flags) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_int_clr(pEGPIO, intCh, flags); +#else + egpio_int_clr(pEGPIO, intCh, flags); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_SetPinMux(EGPIO_Type *pEGPIO ,uint8_t port , uint8_t pin , uint8_t mux) + * @brief This API to used to set pin multiplexing + * \n(GPIO Pin Mode. Ranges 000 -> Mode 0 to 111 -> Mode 7 Used for GPIO Pin Muxing) + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] port : GPIO port number + * @param[in] pin : GPIO pin number + * @param[in] mux : pin function value + * \n possible values for this parameter are the following + * - \ref EGPIO_PIN_MUX_MODE0 : Select pin mode 0 + * - \ref EGPIO_PIN_MUX_MODE1 : Select pin mode 1 + * - \ref EGPIO_PIN_MUX_MODE2 : Select pin mode 2 + * - \ref EGPIO_PIN_MUX_MODE3 : Select pin mode 3 + * - \ref EGPIO_PIN_MUX_MODE4 : Select pin mode 4 + * - \ref EGPIO_PIN_MUX_MODE5 : Select pin mode 5 + * - \ref EGPIO_PIN_MUX_MODE6 : Select pin mode 6 + * - \ref EGPIO_PIN_MUX_MODE7 : Select pin mode 7 + * - \ref EGPIO_PIN_MUX_MODE8 : Select pin mode 8 + * - \ref EGPIO_PIN_MUX_MODE9 : Select pin mode 9 + * - \ref EGPIO_PIN_MUX_MODE10 : Select pin mode 10 + * - \ref EGPIO_PIN_MUX_MODE11 : Select pin mode 11 + * - \ref EGPIO_PIN_MUX_MODE12 : Select pin mode 12 + * - \ref EGPIO_PIN_MUX_MODE13 : Select pin mode 13 + * - \ref EGPIO_PIN_MUX_MODE14 : Select pin mode 14 + * - \ref EGPIO_PIN_MUX_MODE15 : Select pin mode 15 + * @return None + */ +STATIC INLINE void RSI_EGPIO_SetPinMux(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin, uint8_t mux) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_set_pin_mux(pEGPIO, port, pin, mux); +#else + egpio_set_pin_mux(pEGPIO, port, pin, mux); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_UlpSocGpioMode(ULPCLK_Type *pULPCLK,uint8_t gpio,uint8_t mode) + * @brief This API is used set ulp soc gpio mode + * \n(Gpio pin mode,ranges 000 -> Mode 0 to 111 -> Mode 7 Used for GPIO Pin Muxing ) + * @param[in] pULPCLK : Pointer to the ULP register instance + * @param[in] gpio : Gpio number + * @param[in] mode : GPIO mode + * \n possible values for this parameter are the following + * - \ref EGPIO_PIN_MUX_MODE0 : Select pin mode 0 + * - \ref EGPIO_PIN_MUX_MODE1 : Select pin mode 1 + * - \ref EGPIO_PIN_MUX_MODE2 : Select pin mode 2 + * - \ref EGPIO_PIN_MUX_MODE3 : Select pin mode 3 + * - \ref EGPIO_PIN_MUX_MODE4 : Select pin mode 4 + * - \ref EGPIO_PIN_MUX_MODE5 : Select pin mode 5 + * - \ref EGPIO_PIN_MUX_MODE6 : Select pin mode 6 + * - \ref EGPIO_PIN_MUX_MODE7 : Select pin mode 7 + * @return None + */ +STATIC INLINE void RSI_EGPIO_UlpSocGpioMode(ULPCLK_Type *pULPCLK, uint8_t gpio, uint8_t mode) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_ulp_soc_gpio_mode(pULPCLK, gpio, mode); +#else + egpio_ulp_soc_gpio_mode(pULPCLK, gpio, mode); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_SetPortMask(EGPIO_Type *pEGPIO ,uint8_t port,uint8_t pin) + * @brief This API is used to set the EGPIO port mask. When set, pin is masked when written/read through PORT MASK REG. + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] port : GPIO port number + * @param[in] pin : GPIO pin number + * @return None + */ +STATIC INLINE void RSI_EGPIO_SetPortMask(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_set_port_mask(pEGPIO, port, pin); +#else + egpio_set_port_mask(pEGPIO, port, pin); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_SetPortUnMask(EGPIO_Type *pEGPIO ,uint8_t port,uint8_t pin) + * @brief This API is used to set the EGPIO port unmask. When set, pin is masked when written/read through PORT MASK REG. + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] port : GPIO port number + * @param[in] pin : GPIO pin number + * @return None + */ +STATIC INLINE void RSI_EGPIO_SetPortUnMask(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_set_port_un_mask(pEGPIO, port, pin); +#else + egpio_set_port_un_mask(pEGPIO, port, pin); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_PortMaskedLoad(EGPIO_Type *pEGPIO ,uint8_t port, uint16_t val) + * @brief This API is used to set the EGPIO port mask load. When set, pin is masked when written/read through PORT MASK REG. + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] port : GPIO port number + * @param[in] val : Port value to be set + * @return None + */ +STATIC INLINE void RSI_EGPIO_PortMaskedLoad(EGPIO_Type *pEGPIO, uint8_t port, uint16_t val) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_port_masked_load(pEGPIO, port, val); +#else + egpio_port_masked_load(pEGPIO, port, val); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_SetPort(EGPIO_Type *pEGPIO ,uint8_t port , uint16_t val) + * @brief This API is used to set the port value. + * Sets the pin when corresponding bit is high. Writing zero has no effect + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] port : Port number to the EGPIO register instance + * @param[in] val : Port value to be set + * @return None + */ +STATIC INLINE void RSI_EGPIO_SetPort(EGPIO_Type *pEGPIO, uint8_t port, uint16_t val) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_set_port(pEGPIO, port, val); +#else + egpio_set_port(pEGPIO, port, val); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_PortLoad(EGPIO_Type *pEGPIO ,uint8_t port , uint16_t val) + * @brief This API is used to load the port value. + * Loads the value on to pin on write. And reads the value of load register on read + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] port : Port number to the EGPIO register instance + * @param[in] val : Port value to be set + * @return None + */ +STATIC INLINE void RSI_EGPIO_PortLoad(EGPIO_Type *pEGPIO, uint8_t port, uint16_t val) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_port_load(pEGPIO, port, val); +#else + egpio_port_load(pEGPIO, port, val); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_WordLoad(EGPIO_Type *pEGPIO ,uint8_t pin , uint16_t val) + * @brief This API is used to load the port value. + * Loads 1 on the pin when any of the bit in load value is 1. On read pass the bit status into all bits. + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] pin : pin number to the EGPIO register instance + * @param[in] val : Port value to be set + * @return None + */ +STATIC INLINE void RSI_EGPIO_WordLoad(EGPIO_Type *pEGPIO, uint8_t pin, uint16_t val) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_word_load(pEGPIO, pin, val); +#else + egpio_word_load(pEGPIO, pin, val); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_ClrPort(EGPIO_Type *pEGPIO ,uint8_t port , uint16_t val) + * @brief This API is used to clear the port value. + * Clears the pin when corresponding bit is high. Writing zero has no effect. + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] port : Port number + * @param[in] val : Port value to be clear + * @return None + */ +STATIC INLINE void RSI_EGPIO_ClrPort(EGPIO_Type *pEGPIO, uint8_t port, uint16_t val) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_clr_port(pEGPIO, port, val); +#else + egpio_clr_port(pEGPIO, port, val); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_TogglePort(EGPIO_Type *pEGPIO ,uint8_t port , uint16_t val) + * @brief This API is used to toggle the port. + * Toggles the pin when corresponding bit is high. Writing zero has not effect. + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] port : Port number + * @param[in] val : Port value to be toggle + * @return None + */ +STATIC INLINE void RSI_EGPIO_TogglePort(EGPIO_Type *pEGPIO, uint8_t port, uint16_t val) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_toggle_port(pEGPIO, port, val); +#else + egpio_toggle_port(pEGPIO, port, val); +#endif +} + +/** + * @fn STATIC INLINE uint16_t RSI_EGPIO_GetPort(EGPIO_Type *pEGPIO ,uint8_t port) + * @brief This API is used to used to get the EGPIO port value. + * Reads the value on GPIO pins irrespective of the pin mode. + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] port : Port number to be read + * @return port value + */ +STATIC INLINE uint16_t RSI_EGPIO_GetPort(EGPIO_Type *pEGPIO, uint8_t port) +{ +#if defined(ROMDRIVER_PRESENT) + return ROMAPI_EGPIO_API->egpio_get_port(pEGPIO, port); +#else + return egpio_get_port(pEGPIO, port); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_GroupIntOneEnable(EGPIO_Type *pEGPIO,uint8_t port,uint8_t pin) + * @brief This API is used to enable the group interrupt one , When set, + * the corresponding GPIO pin is selected for group interrupt 1 generation + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] port : GPIO port number + * @param[in] pin : GPIO pin number + * @return None + */ +STATIC INLINE void RSI_EGPIO_GroupIntOneEnable(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_group_int_one_enable(pEGPIO, port, pin); +#else + egpio_group_int_one_enable(pEGPIO, port, pin); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_GroupIntOneDisable(EGPIO_Type *pEGPIO,uint8_t port,uint8_t pin) + * @brief This API is used to disable the group interrupt one + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] port : GPIO port number + * @param[in] pin : GPIO pin number + * @return None + */ +STATIC INLINE void RSI_EGPIO_GroupIntOneDisable(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_group_int_one_disable(pEGPIO, port, pin); +#else + egpio_group_int_one_disable(pEGPIO, port, pin); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_GroupIntTwoEnable(EGPIO_Type *pEGPIO,uint8_t port,uint8_t pin) + * @brief This API is used to enable the group interrupt Two , When set, + * the corresponding GPIO pin is selected for group interrupt 2 generation + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] port : GPIO port number + * @param[in] pin : GPIO pin number + * @return None + */ +STATIC INLINE void RSI_EGPIO_GroupIntTwoEnable(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_group_int_two_enable(pEGPIO, port, pin); +#else + egpio_group_int_two_enable(pEGPIO, port, pin); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_GroupIntMask(EGPIO_Type *pEGPIO ,uint8_t grpInt) + * @brief This API is used to configure the group interrupts(1-mask,0-unmask) + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] grpInt : Group interrupt number + * @return None + */ +STATIC INLINE void RSI_EGPIO_GroupIntMask(EGPIO_Type *pEGPIO, uint8_t grpInt) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_group_int_mask(pEGPIO, grpInt); +#else + egpio_group_int_mask(pEGPIO, grpInt); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_GroupIntUnMask(EGPIO_Type *pEGPIO ,uint8_t grpInt) + * @brief This API is used to configure the group interrupts(1-mask,0-unmask) + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] grpInt : Group interrupt number + * @return None + */ +STATIC INLINE void RSI_EGPIO_GroupIntUnMask(EGPIO_Type *pEGPIO, uint8_t grpInt) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_group_int_un_Mask(pEGPIO, grpInt); +#else + egpio_group_int_un_Mask(pEGPIO, grpInt); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_GroupIntEnable(EGPIO_Type *pEGPIO ,uint8_t grpInt) + * @brief This API is used to configure the group interrupts(1-enable, 0-disable) + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] grpInt : Group interrupt number + * @return None + */ +STATIC INLINE void RSI_EGPIO_GroupIntEnable(EGPIO_Type *pEGPIO, uint8_t grpInt) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_group_int_enable(pEGPIO, grpInt); +#else + egpio_group_int_enable(pEGPIO, grpInt); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_GroupIntDisable(EGPIO_Type *pEGPIO ,uint8_t grpInt) + * @brief This API is used to configure the group interrupts(1-enable, 0-disable) + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] grpInt : Group interrupt number + * @return None + */ +STATIC INLINE void RSI_EGPIO_GroupIntDisable(EGPIO_Type *pEGPIO, uint8_t grpInt) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_group_int_disable(pEGPIO, grpInt); +#else + egpio_group_int_disable(pEGPIO, grpInt); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_GroupIntLevel(EGPIO_Type *pEGPIO ,uint8_t grpInt) + * @brief This API is used to configure the group interrupts(0-level,1-edge) + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] grpInt : Group interrupt number + * @return None + */ +STATIC INLINE void RSI_EGPIO_GroupIntLevel(EGPIO_Type *pEGPIO, uint8_t grpInt) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_group_int_level(pEGPIO, grpInt); +#else + egpio_group_int_level(pEGPIO, grpInt); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_GroupIntEdge(EGPIO_Type *pEGPIO ,uint8_t grpInt) + * @brief This API is used to configure the group interrupts(0-level,1-edge) + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] grpInt : Group interrupt number + * @return None + */ +STATIC INLINE void RSI_EGPIO_GroupIntEdge(EGPIO_Type *pEGPIO, uint8_t grpInt) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_group_int_edge(pEGPIO, grpInt); +#else + egpio_group_int_edge(pEGPIO, grpInt); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_GroupIntAnd(EGPIO_Type *pEGPIO ,uint8_t grpInt) + * @brief This API is used to configure the group interrupts(0-AND ,1-Or) + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] grpInt : Group interrupt number + * @return None + */ +STATIC INLINE void RSI_EGPIO_GroupIntAnd(EGPIO_Type *pEGPIO, uint8_t grpInt) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_group_int_and(pEGPIO, grpInt); +#else + egpio_group_int_and(pEGPIO, grpInt); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_GroupIntOr(EGPIO_Type *pEGPIO ,uint8_t grpInt) + * @brief This API is used to configure the group interrupts(0- AND , 1-Or) + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] grpInt : Group interrupt number + * @return None + */ +STATIC INLINE void RSI_EGPIO_GroupIntOr(EGPIO_Type *pEGPIO, uint8_t grpInt) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_group_int_or(pEGPIO, grpInt); +#else + egpio_group_int_or(pEGPIO, grpInt); +#endif +} + +/** + * @fn STATIC INLINE uint32_t RSI_EGPIO_GroupIntStat(EGPIO_Type *pEGPIO ,uint8_t grpInt) + * @brief This API to used to get the group interrupt status + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] grpInt : Group interrupt number + * @return returns the group interrupt status register + */ +STATIC INLINE uint32_t RSI_EGPIO_GroupIntStat(EGPIO_Type *pEGPIO, uint8_t grpInt) +{ +#if defined(ROMDRIVER_PRESENT) + return ROMAPI_EGPIO_API->egpio_group_int_stat(pEGPIO, grpInt); +#else + return egpio_group_int_stat(pEGPIO, grpInt); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_GroupIntWkeUpEnable(EGPIO_Type *pEGPIO ,uint8_t grpInt) + * @brief This API to used to Enable the group interrupt wakeup interrupt + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] grpInt : Group interrupt number + * @return None + */ +STATIC INLINE void RSI_EGPIO_GroupIntWkeUpEnable(EGPIO_Type *pEGPIO, uint8_t grpInt) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_group_int_wkeup_Enable(pEGPIO, grpInt); +#else + egpio_group_int_wkeup_Enable(pEGPIO, grpInt); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_GroupIntWkeUpDisable(EGPIO_Type *pEGPIO ,uint8_t grpInt) + * @brief This API to used to Disable the group interrupt wakeup interrupt + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] grpInt : Group interrupt number + * @return None + */ +STATIC INLINE void RSI_EGPIO_GroupIntWkeUpDisable(EGPIO_Type *pEGPIO, uint8_t grpInt) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_group_int_wkeup_disable(pEGPIO, grpInt); +#else + egpio_group_int_wkeup_disable(pEGPIO, grpInt); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_GroupIntClr(EGPIO_Type *pEGPIO ,uint8_t grpInt , uint8_t flags) + * @brief This API is used to used to clear the group interrupt status + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] grpInt : Group interrupt number + * @param[in] flags : clear flags + * @return None + */ +STATIC INLINE void RSI_EGPIO_GroupIntClr(EGPIO_Type *pEGPIO, uint8_t grpInt, uint8_t flags) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_group_int_clr(pEGPIO, grpInt, flags); +#else + egpio_group_int_clr(pEGPIO, grpInt, flags); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_GroupIntTwoDisable(EGPIO_Type *pEGPIO ,uint8_t port ,uint8_t pin) + * @brief This API is used to used to disable the group interrupt two + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] port : PORT number + * @param[in] pin : PIN number + * @return None + */ +STATIC INLINE void RSI_EGPIO_GroupIntTwoDisable(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_group_int_two_disable(pEGPIO, port, pin); +#else + egpio_group_int_two_disable(pEGPIO, port, pin); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_SetGroupIntOnePol(EGPIO_Type *pEGPIO ,uint8_t port , uint8_t pin , uint8_t pol) + * @brief This API is used to set the group polarity of interrupt one. + * Decides the active value of the pin to be considered for group interrupt 1 generation when enabled + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] port : PORT number + * @param[in] pin : PIN number + * @param[in] pol : Polarity of interrupt + * \n '0' : group interrupt gets generated when GPIO input pin status is '0'. + * \n '1' : group interrupt gets generated when GPIO input pin status is '1' + * @return None + */ +STATIC INLINE void RSI_EGPIO_SetGroupIntOnePol(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin, uint8_t pol) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_set_group_int_one_pol(pEGPIO, port, pin, pol); +#else + egpio_set_group_int_one_pol(pEGPIO, port, pin, pol); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_SetGroupIntTwoPol(EGPIO_Type *pEGPIO ,uint8_t port,uint8_t pin , uint8_t pol) + * @brief This API is used to set the group polarity of interrupt two. + * Decides the active value of the pin to be considered for group interrupt 2 generation when enabled + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] port : PORT number + * @param[in] pin : PIN number + * @param[in] pol : Polarity of interrupt + * \n '0' : group interrupt gets generated when GPIO input pin status is '0'. + * \n '1' : group interrupt gets generated when GPIO input pin status is '1'. + * @return None + */ +STATIC INLINE void RSI_EGPIO_SetGroupIntTwoPol(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin, uint8_t pol) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_set_group_int_two_pol(pEGPIO, port, pin, pol); +#else + egpio_set_group_int_two_pol(pEGPIO, port, pin, pol); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_HostPadsGpioModeEnable(uint8_t u8GpioNum) + * @brief This API is used to select the host pad gpios(25 to 30) + * @param[in] u8GpioNum : PAD number to be use + * @return None + */ +STATIC INLINE void RSI_EGPIO_HostPadsGpioModeEnable(uint8_t u8GpioNum) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_host_pads_gpio_mode_enable(u8GpioNum); +#else + egpio_host_pads_gpio_mode_enable(u8GpioNum); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_HostPadsGpioModeDisable(uint8_t u8GpioNum) + * @brief This API is used to deselect the host pad gpios(25 to 30) + * @param[in] u8GpioNum : PAD number to be use + * @return None + */ +STATIC INLINE void RSI_EGPIO_HostPadsGpioModeDisable(uint8_t u8GpioNum) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_host_pads_gpio_mode_disable(u8GpioNum); +#else + egpio_host_pads_gpio_mode_disable(u8GpioNum); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_PadSelectionEnable(uint8_t padNum) + * @brief This API is used to select the pad(0 to 21) + * @param[in] padNum : PAD number to be use + * @return None + */ +STATIC INLINE void RSI_EGPIO_PadSelectionEnable(uint8_t padNum) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_pad_selection_enable(padNum); +#else + egpio_pad_selection_enable(padNum); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_PadSelectionDisable(uint8_t padNum) + * @brief This API is used to deselect the pad(0 to 21) + * @param[in] padNum : PAD number to be use + * @return None + */ +STATIC INLINE void RSI_EGPIO_PadSelectionDisable(uint8_t padNum) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_pad_selection_disable(padNum); +#else + egpio_pad_selection_disable(padNum); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_PadReceiverEnable(uint8_t u8GpioNum) + * @brief This API is used to enable the receiver enable bit(REN) + * @param[in] u8GpioNum : GPIO num to be use + * @return None + */ +STATIC INLINE void RSI_EGPIO_PadReceiverEnable(uint8_t u8GpioNum) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_pad_receiver_enable(u8GpioNum); +#else + egpio_pad_receiver_enable(u8GpioNum); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_PadReceiverDisable(uint8_t u8GpioNum) + * @brief This API is used to Disable the receiver enable bit(REN) + * @param[in] u8GpioNum : GPIO num to be use + * @return None + */ +STATIC INLINE void RSI_EGPIO_PadReceiverDisable(uint8_t u8GpioNum) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_pad_receiver_disable(u8GpioNum); +#else + egpio_pad_receiver_disable(u8GpioNum); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_PadSdioConnected(void) + * @brief This API is used to use the SDIO pins(25 to 30) in M4 or TA (0 for M4SS and 1 for TASS) + * @return None + */ +STATIC INLINE void RSI_EGPIO_PadSdioConnected(void) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_pad_sdio_connected(); +#else + egpio_pad_sdio_connected(); +#endif +} + +/** + * @fn void RSI_EGPIO_PadDriverDisableState(uint8_t u8GpioNum , en_driver_state_t endstate) + * @brief This API is used to control the Driver disabled state control + * @param[in] u8GpioNum : GPIO number to be use + * @param[in] endstate : the value to be passed + * \n possible values are + * \n - 0 for \ref HiZ (P1=0,P2=0) + * \n - 1 for \ref Pullup (P1=0,P2=1) + * \n - 2 for \ref Pulldown (P1=1,P2=0) + * \n - 3 for \ref Repeater (P1=1,P2=1) + * @return None + */ +STATIC INLINE void RSI_EGPIO_PadDriverDisableState(uint8_t u8GpioNum, en_driver_state_t endstate) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_pad_driver_disable_state(u8GpioNum, endstate); +#else + egpio_pad_driver_disable_state(u8GpioNum, endstate); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_PadDriverStrengthSelect(uint8_t u8GpioNum , en_driver_strength_select_t strength) + * @brief This API is used to select Drive strength + * @param[in] u8GpioNum : GPIO number to be use + * @param[in] strength : Drive strength selector(E1,E2) + * \n possible values are + * \n - 0 for \ref two_milli_amps (E1=0,E2=0) + * \n - 1 for \ref four_milli_amps (E1=0,E2=1) + * \n - 2 for \ref eight_milli_amps (E1=1,E2=0) + * \n - 3 for \ref twelve_milli_amps(E1=1,E2=1) + * @return None + */ +STATIC INLINE void RSI_EGPIO_PadDriverStrengthSelect(uint8_t u8GpioNum, en_driver_strength_select_t strength) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_pad_driver_strength_select(u8GpioNum, strength); +#else + egpio_pad_driver_strength_select(u8GpioNum, strength); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_PadPowerOnStartEnable(uint8_t u8GpioNum ,uint8_t val) + * @brief This API is used to select Power on Start enable + * @param[in] u8GpioNum : GPIO number to be use + * @param[in] val : POS = 1 : Enables active pull down for invalid power; + * \n : POS = 0 : Active pull down capability disabled . + * \n When one of the power supplies is invalid and active high POS is set to 1, + * \n AD is pulled to weak 0. When POS is set to 0, PAD remains in a high-Z state. : Default 0 + * @return None + */ +STATIC INLINE void RSI_EGPIO_PadPowerOnStartEnable(uint8_t u8GpioNum, uint8_t val) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_pad_power_on_start_enable(u8GpioNum, val); +#else + egpio_pad_power_on_start_enable(u8GpioNum, val); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_PadActiveHighSchmittTrigger(uint8_t u8GpioNum ,uint8_t val) + * @brief Active high Schmitt trigger (Hysteresis) select; + * \n SMT=0 for No hysteresis; Default value for reset is 1'b1 and others is 1'b0 + * @param[in] u8GpioNum : GPIO number to be use + * @param[in] val : SMT=0 : No hysteresis; Default value for reset is 1'b1 and others is 1'b0 + * @return None + */ +STATIC INLINE void RSI_EGPIO_PadActiveHighSchmittTrigger(uint8_t u8GpioNum, uint8_t val) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_pad_active_high_schmitt_trigger(u8GpioNum, val); +#else + egpio_pad_active_high_schmitt_trigger(u8GpioNum, val); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_PadSlewRateControll(uint8_t u8GpioNum ,uint8_t val) + * @brief this API is used to control the slew rate + * @param[in] u8GpioNum : GPIO number to be use + * @param[in] val : slew rate + * \n - SR = 0 : Slow (half frequency) + \n - SR = 1 : Fast ,Default 1 + * @return None + */ +STATIC INLINE void RSI_EGPIO_PadSlewRateControll(uint8_t u8GpioNum, uint8_t val) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_pad_slew_rate_controll(u8GpioNum, val); +#else + egpio_pad_slew_rate_controll(u8GpioNum, val); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_UlpPadReceiverEnable(uint8_t u8GpioNum) + * @brief This API is used to enable the REN for ULP + * @param[in] u8GpioNum : GPIO number to be used + * @return None + */ +STATIC INLINE void RSI_EGPIO_UlpPadReceiverEnable(uint8_t u8GpioNum) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_ulp_pad_receiver_enable(u8GpioNum); +#else + egpio_ulp_pad_receiver_enable(u8GpioNum); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_UlpPadReceiverDisable(uint8_t u8GpioNum) + * @brief This API is used to enable the REN for ULP + * @param[in] u8GpioNum : GPIO number to be used + * @return None + */ +STATIC INLINE void RSI_EGPIO_UlpPadReceiverDisable(uint8_t u8GpioNum) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_ulp_pad_receiver_disable(u8GpioNum); +#else + egpio_ulp_pad_receiver_disable(u8GpioNum); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_UlpPadDriverDisableState(uint8_t u8GpioNum , en_ulp_driver_disable_state_t disablestate) + * @brief This API is used to control the Driver disabled state control + * @param[in] u8GpioNum : GPIO number to be use + * @param[in] disablestate : the value to be passed + * \n possible values are + * \n - 0 for \ref HiZ (P1=0,P2=0) + * \n - 1 for \ref Pullup (P1=0,P2=1) + * \n - 2 for \ref Pulldown (P1=1,P2=0) + * \n - 3 for \ref Repeater (P1=1,P2=1) + * @return None + */ +STATIC INLINE void RSI_EGPIO_UlpPadDriverDisableState(uint8_t u8GpioNum, en_ulp_driver_disable_state_t disablestate) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_ulp_pad_driver_disable_state(u8GpioNum, disablestate); +#else + egpio_ulp_pad_driver_disable_state(u8GpioNum, disablestate); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_UlpPadDriverStrengthSelect(uint8_t u8GpioNum , en_ulp_driver_strength_select_t strength) + * @brief this API is used to select Drive strength + * @param[in] u8GpioNum : GPIO number to be use + * @param[in] strength : Drive strength selector(E1,E2) + * \n possible values are + * \n - 0 for \ref two_milli_amps (E1=0,E2=0) + * \n - 1 for \ref four_milli_amps (E1=0,E2=1) + * \n - 2 for \ref eight_milli_amps (E1=1,E2=0) + * \n - 3 for \ref twelve_milli_amps(E1=1,E2=1) + * @return None + */ +STATIC INLINE void RSI_EGPIO_UlpPadDriverStrengthSelect(uint8_t u8GpioNum, en_ulp_driver_strength_select_t strength) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_ulp_pad_driver_strength_select(u8GpioNum, strength); +#else + egpio_ulp_pad_driver_strength_select(u8GpioNum, strength); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_UlpPadPowerOnStartEnable(uint8_t u8GpioNum ,uint8_t val ) + * @brief Power-on-Start enable; + * @param[in] u8GpioNum : GPIO number to be use + * @param[in] val : POS = 1 : Enables active pull down for invalid power; + * \n : POS = 0 : Active pull down capability disabled . + * \n When one of the power supplies is invalid and active high POS is set to 1, + *PAD is pulled to weak 0. When POS is set to 0, PAD remains in a high Z state. : Default 0 + * @return None + */ +STATIC INLINE void RSI_EGPIO_UlpPadPowerOnStartEnable(uint8_t u8GpioNum, uint8_t val) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_ulp_pad_power_on_start_enable(u8GpioNum, val); +#else + egpio_ulp_pad_power_on_start_enable(u8GpioNum, val); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_UlpPadActiveHighSchmittTrigger(uint8_t u8GpioNum ,uint8_t val ) + * @brief Active high Schmitt trigger (Hysteresis) select; + * @param[in] u8GpioNum : GPIO number to be use + * @param[in] val : SMT=0 : No hysteresis; Default value for reset is 1'b1 and others is 1'b0 + * @return None + */ +STATIC INLINE void RSI_EGPIO_UlpPadActiveHighSchmittTrigger(uint8_t u8GpioNum, uint8_t val) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_ulp_pad_active_high_schmitt_trigger(u8GpioNum, val); +#else + egpio_ulp_pad_active_high_schmitt_trigger(u8GpioNum, val); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_UlpPadSlewRateControll(uint8_t u8GpioNum ,uint8_t val ) + * @brief Slew Rate Control + * @param[in] u8GpioNum : GPIO number to be use + * @param[in] val : slew rate + * \n - SR = 0 : Slow (half frequency); SR = 1 for Fast , Default 1 + * @return None + */ +STATIC INLINE void RSI_EGPIO_UlpPadSlewRateControll(uint8_t u8GpioNum, uint8_t val) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_ulp_pad_slew_rate_controll(u8GpioNum, val); +#else + egpio_ulp_pad_slew_rate_controll(u8GpioNum, val); +#endif +} + +#ifdef __cplusplus +} +#endif + +#endif /*__RSI_ROM_EGPIO_H__*/ +/** @} */ +/* @}end of RSI_EGPIO_DRIVERS */ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_table_si91x.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_table_si91x.h new file mode 100644 index 000000000..6175e4ff1 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_table_si91x.h @@ -0,0 +1,1100 @@ +/******************************************************************************* +* @file rsi_rom_table_si91x.h +* @brief +******************************************************************************* +* # License +* Copyright 2020 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +/** + * Includes + */ +#ifndef __RSI_ROM_TABLE_RS9116_H__ +#define __RSI_ROM_TABLE_RS9116_H__ +#include "rsi_ccp_user_config.h" +#if defined(A11_ROM) +#include +#include "rsi_error.h" +#include "rsi_timers.h" +#include "rsi_ulpss_clk.h" +#include "rsi_pll.h" +#include "rsi_power_save.h" +#include "rsi_egpio.h" +#include "rsi_crc.h" +#include "rsi_ulpss_clk.h" +#include "rsi_qspi_proto.h" +#include "rsi_qspi.h" +#include "rsi_rng.h" +#include "rsi_gpdma.h" +#include "rsi_ct.h" +#include "rsi_timers.h" +#include "rsi_udma.h" +#include "rsi_reg_spi.h" +#include "rsi_processor_sensor.h" +#include "rsi_retention.h" +#include "rsi_temp_sensor.h" +#include "rsi_time_period.h" +#include "rsi_wwdt.h" +#include "rsi_ipmu.h" +#ifndef SLI_SI917B0 +#include "rsi_efuse.h" +#include "rsi_pwm.h" +#endif +#include "rsi_udma_wrapper.h" +#include "UDMA.h" +#include "USART.h" +#include "GSPI.h" +#include "SAI.h" +#include "I2C.h" +#include "SPI.h" +#ifdef __cplusplus +extern "C" { +#endif +/* @brief ROM indirect function structure */ + +///////////////////EGPIO////////////////////////// +typedef struct { + void (*egpio_set_dir)(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin, boolean_t dir); + void (*egpio_set_pin)(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin, uint8_t val); + boolean_t (*egpio_get_pin)(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); + boolean_t (*egpio_get_dir)(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); + void (*egpio_pin_int_sel)(EGPIO_Type *pEGPIO, uint8_t intCh, uint8_t port, uint8_t pin); + void (*egpio_set_int_fall_edge_enable)(EGPIO_Type *pEGPIO, uint8_t intCh); + void (*egpio_set_int_fall_edge_disable)(EGPIO_Type *pEGPIO, uint8_t intCh); + void (*egpio_set_int_rise_edge_enable)(EGPIO_Type *pEGPIO, uint8_t intCh); + void (*egpio_set_int_rise_edge_disable)(EGPIO_Type *pEGPIO, uint8_t intCh); + void (*egpio_set_int_low_level_enable)(EGPIO_Type *pEGPIO, uint8_t intCh); + void (*egpio_int_mask)(EGPIO_Type *pEGPIO, uint8_t intCh); + void (*egpio_int_un_mask)(EGPIO_Type *pEGPIO, uint8_t intCh); + void (*egpio_set_int_low_level_disable)(EGPIO_Type *pEGPIO, uint8_t intCh); + void (*egpio_set_int_high_level_enable)(EGPIO_Type *pEGPIO, uint8_t intCh); + void (*egpio_set_int_high_level_disable)(EGPIO_Type *pEGPIO, uint8_t intCh); + uint8_t (*egpio_get_int_stat)(EGPIO_Type *pEGPIO, uint8_t intCh); + void (*egpio_int_clr)(EGPIO_Type *pEGPIO, uint8_t intCh, uint8_t flags); + void (*egpio_set_pin_mux)(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin, uint8_t mux); + void (*egpio_ulp_soc_gpio_mode)(ULPCLK_Type *pULPCLK, uint8_t gpio, uint8_t mode); + void (*egpio_set_port_mask)(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); + void (*egpio_set_port_un_mask)(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); + void (*egpio_port_masked_load)(EGPIO_Type *pEGPIO, uint8_t port, uint16_t val); + void (*egpio_set_port)(EGPIO_Type *pEGPIO, uint8_t port, uint16_t val); + void (*egpio_port_load)(EGPIO_Type *pEGPIO, uint8_t port, uint16_t val); + void (*egpio_word_load)(EGPIO_Type *pEGPIO, uint8_t pin, uint16_t val); + void (*egpio_clr_port)(EGPIO_Type *pEGPIO, uint8_t port, uint16_t val); + void (*egpio_toggle_port)(EGPIO_Type *pEGPIO, uint8_t port, uint16_t val); + uint16_t (*egpio_get_port)(EGPIO_Type *pEGPIO, uint8_t port); + void (*egpio_group_int_one_enable)(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); + void (*egpio_group_int_one_disable)(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); + void (*egpio_group_int_two_enable)(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); + void (*egpio_group_int_mask)(EGPIO_Type *pEGPIO, uint8_t grpInt); + void (*egpio_group_int_un_Mask)(EGPIO_Type *pEGPIO, uint8_t grpInt); + void (*egpio_group_int_enable)(EGPIO_Type *pEGPIO, uint8_t grpInt); + void (*egpio_group_int_disable)(EGPIO_Type *pEGPIO, uint8_t grpInt); + void (*egpio_group_int_level)(EGPIO_Type *pEGPIO, uint8_t grpInt); + void (*egpio_group_int_edge)(EGPIO_Type *pEGPIO, uint8_t grpInt); + void (*egpio_group_int_and)(EGPIO_Type *pEGPIO, uint8_t grpInt); + void (*egpio_group_int_or)(EGPIO_Type *pEGPIO, uint8_t grpInt); + uint32_t (*egpio_group_int_stat)(EGPIO_Type *pEGPIO, uint8_t grpInt); + void (*egpio_group_int_wkeup_Enable)(EGPIO_Type *pEGPIO, uint8_t grpInt); + void (*egpio_group_int_wkeup_disable)(EGPIO_Type *pEGPIO, uint8_t grpInt); + void (*egpio_group_int_clr)(EGPIO_Type *pEGPIO, uint8_t grpInt, uint8_t flags); + void (*egpio_group_int_two_disable)(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); + void (*egpio_set_group_int_one_pol)(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin, uint8_t pol); + void (*egpio_set_group_int_two_pol)(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin, uint8_t pol); + void (*egpio_host_pads_gpio_mode_enable)(uint8_t u8GpioNum); + void (*egpio_host_pads_gpio_mode_disable)(uint8_t u8GpioNum); + void (*egpio_pad_selection_enable)(uint8_t padNum); + void (*egpio_pad_selection_disable)(uint8_t padNum); + void (*egpio_pad_receiver_enable)(uint8_t u8GpioNum); + void (*egpio_pad_receiver_disable)(uint8_t u8GpioNum); + void (*egpio_pad_sdio_connected)(void); + void (*egpio_pad_driver_disable_state)(uint8_t u8GpioNum, en_driver_state_t endstate); + void (*egpio_pad_driver_strength_select)(uint8_t u8GpioNum, en_driver_strength_select_t strength); + void (*egpio_pad_power_on_start_enable)(uint8_t u8GpioNum, uint8_t val); + void (*egpio_pad_active_high_schmitt_trigger)(uint8_t u8GpioNum, uint8_t val); + void (*egpio_pad_slew_rate_controll)(uint8_t u8GpioNum, uint8_t val); + void (*egpio_ulp_pad_receiver_enable)(uint8_t u8GpioNum); + void (*egpio_ulp_pad_receiver_disable)(uint8_t u8GpioNum); + void (*egpio_ulp_pad_driver_disable_state)(uint8_t u8GpioNum, en_ulp_driver_disable_state_t disablestate); + void (*egpio_ulp_pad_driver_strength_select)(uint8_t u8GpioNum, en_ulp_driver_strength_select_t strength); + void (*egpio_ulp_pad_power_on_start_enable)(uint8_t u8GpioNum, uint8_t val); + void (*egpio_ulp_pad_active_high_schmitt_trigger)(uint8_t u8GpioNum, uint8_t val); + void (*egpio_ulp_pad_slew_rate_controll)(uint8_t u8GpioNum, uint8_t val); +} ROM_EGPIO_API_T; +///////////////////EGPIO END////////////////////////// + +/** @brief CRC ROM indirect function structure */ +typedef PRE_PACK struct POST_PACK { + void (*crc_set_gen_control)(CRC_Type *pCRC); + uint32_t (*crc_get_gen_status)(CRC_Type *pCRC); + void (*crc_polynomial)(CRC_Type *pCRC, RSI_CRC_PARAMS_T *pCRC_Params); + uint32_t (*crc_polynomial_width)(CRC_Type *pCRC, RSI_CRC_PARAMS_T *pCRC_Params); + void (*crc_lfsr_init)(CRC_Type *pCRC, RSI_CRC_PARAMS_T *pCRC_Params); + uint32_t (*crc_use_swapped_init)(CRC_Type *pCRC, RSI_CRC_PARAMS_T *pCRC_Params); + uint32_t (*crc_set_data_width_type)(CRC_Type *pCRC, RSI_CRC_PARAMS_T *pCRC_Params); + uint32_t (*crc_set_fifo_thresholds)(CRC_Type *pCRC, RSI_CRC_PARAMS_T *pCRC_Params); + uint32_t (*crc_write_data)(CRC_Type *pCRC, RSI_CRC_PARAMS_T *pCRCParams, uint32_t data); + uint32_t (*monitor_crc_calc)(CRC_Type *pCRC, RSI_CRC_PARAMS_T *pCRC_Params); + void (*crc_lfsr_dynamic_write)(CRC_Type *pCRC, RSI_CRC_PARAMS_T *pCRCParams); + void (*crc_reset_fifo)(CRC_Type *pCRC); + uint32_t (*crc_get_fifo_status)(CRC_Type *pCRC); +} ROM_CRC_API_T; +//////////////CRC END///////////////////////////// + +/** @brief RNG ROM indirect function structure */ +typedef PRE_PACK struct POST_PACK { + uint32_t (*rng_start)(HWRNG_Type *pRNG, uint8_t rngMode); + void (*rng_stop)(HWRNG_Type *pRNG); + void (*rng_get_bytes)(HWRNG_Type *pRNG, uint32_t *randomBytes, uint32_t numberOfBytes); +} ROM_RNG_API_T; +///////////////RNG END////////////////// +#ifndef SLI_SI917B0 +/* @brief ROM indirect function structure */ +typedef PRE_PACK struct POST_PACK { + void (*efuse_enable)(EFUSE_Type *pstcEfuse); + void (*efuse_Disable)(EFUSE_Type *pstcEfuse); + uint8_t (*efuse_read_data)(EFUSE_Type *pstcEfuse); + void (*efuse_write_addr)(EFUSE_Type *pstcEfuse, uint16_t u16Addr); + rsi_error_t (*efuse_write_bit)(EFUSE_Type *pstcEfuse, uint16_t u16Addr, uint8_t u8BitPos, uint32_t hold_time); + rsi_error_t (*efuse_fsm_read_byte)(EFUSE_Type *pstcEfuse, uint16_t u16Addr, uint8_t *pu8Byte, uint32_t SocClk); + rsi_error_t (*efuse_mem_map_read_byte)(EFUSE_Type *pstcEfuse, uint16_t u16Addr, uint8_t *pu8Byte, uint32_t SocClk); + rsi_error_t (*efuse_mem_map_read_word)(EFUSE_Type *pstcEfuse, uint16_t u16Addr, uint16_t *pu16Word, uint32_t SocClk); +} ROM_EFUSE_API_T; +///////////////EFUSE END////////////////// +#endif +typedef PRE_PACK struct POST_PACK { + void (*qspi_write_to_flash)(qspi_reg_t *qspi_reg, uint32_t len_in_bits, uint32_t cmd_addr_data, uint32_t cs_no); + void (*qspi_switch_qspi2)(qspi_reg_t *qspi_reg, uint32_t mode, uint32_t cs_no); + uint32_t (*qspi_wait_flash_status_Idle)(qspi_reg_t *qspi_reg, spi_config_t *spi_config, uint32_t wr_reg_delay_ms); + void (*qspi_enable_status_reg_write)(qspi_reg_t *qspi_reg, + uint32_t flash_type, + spi_config_t *spi_config, + uint32_t cs_no); + void (*qspi_status_reg_write)(qspi_reg_t *qspi_reg, + uint32_t write_value, + spi_config_t *spi_config, + uint32_t wr_reg_delay_ms); + uint32_t (*qspi_flash_reg_read)(qspi_reg_t *qspi_reg, uint8_t reg_read_cmd, uint32_t cs_no, spi_config_t *spi_config); + void (*qspi_flash_reg_write)(qspi_reg_t *qspi_reg, + uint32_t reg_write_cmd, + uint32_t reg_write_value, + uint32_t cs_no, + uint32_t wr_reg_delay_ms); + void (*qspi_set_flash_mode)(qspi_reg_t *qspi_reg, + uint32_t data_mode, + uint32_t cs_no, + uint32_t ddr_en, + uint32_t flash_type); + void (*qspi_config_qflash4_read)(qspi_reg_t *qspi_reg, spi_config_t *spi_config, uint32_t addr); + void (*qspi_manual_read)(qspi_reg_t *qspi_reg, + spi_config_t *spi_config, + uint32_t addr, + uint8_t *data, + uint32_t hsize, + uint32_t len_in_bytes, + uint32_t manual_udma_read, + void *udmaHandle, + void *gpdmaHandle); + void (*qspi_auto_init)(qspi_reg_t *qspi_reg, spi_config_t *spi_config); + void (*qspi_auto_read)(uint32_t cs_no, + uint32_t addr, + uint8_t *data, + uint32_t hsize, + uint32_t len_in_bytes, + spi_config_t *spi_config, + uint32_t dma_flags); + void (*qspi_flash_init)(qspi_reg_t *qspi_reg, spi_config_t *spi_config, uint32_t wr_reg_delay_ms); + void (*qspi_spi_init)(qspi_reg_t *qspi_reg, + spi_config_t *spi_config, + uint32_t flash_init_req, + uint32_t wr_reg_delay_ms, + uint8_t fifo_thrsld); + void (*qspi_spi_erase)(qspi_reg_t *qspi_reg, + spi_config_t *spi_config, + uint32_t erase_cmd, + uint32_t blk_sec_addr, + uint32_t dis_hw_ctrl, + uint32_t wr_reg_delay_ms); + uint32_t (*qspi_spi_write)(qspi_reg_t *qspi_reg, + spi_config_t *spi_config, + uint32_t write_cmd, + uint32_t addr, + uint8_t *data, + uint32_t len_in_bytes, + uint16_t page_size, + uint32_t hsize, + uint32_t dis_hw_ctrl, + uint32_t wr_reg_delay_ms, + uint32_t check_en, + uint32_t udma_enable, + void *udmaHandle, + void *gpdmaHandle); + void (*qspi_spi_read)(qspi_reg_t *qspi_reg, + spi_config_t *spi_config, + uint32_t addr, + uint8_t *data, + uint32_t hsize, + uint32_t len_in_bytes, + uint32_t manual_udma_read, + void *udmaHandle, + void *gpdmaHandle); + void (*qspi_usleep)(uint32_t delay_us); //!< function ptr for halting processor for delay (us) specified + void (*qspi_write_block_protect)(qspi_reg_t *qspi_reg, + uint32_t protect, + uint32_t cs_no, + uint32_t num_prot_bytes, + uint32_t wr_reg_delay_ms); +#ifdef SLI_SI917 +#ifdef SLI_SI917B0 + void (*qspi_qspiload_key)(qspi_reg_t *qspi_reg, + uint8_t mode, + uint32_t *key1, + uint32_t *key2, + uint32_t key_len, + uint32_t kh_enable); +#else + void (*qspi_qspiload_key)(qspi_reg_t *qspi_reg, uint8_t mode, uint32_t *key, uint32_t kh_enable); +#endif +#else + void (*qspi_qspiload_key)(qspi_reg_t *qspi_reg, uint32_t *key, uint32_t kh_enable); +#endif + void (*qspi_qspiload_nonce)(qspi_reg_t *qspi_reg, uint32_t *nonce); + void (*qspi_seg_sec_en)(qspi_reg_t *qspi_reg, uint32_t seg_no, uint32_t start_addr, uint32_t end_addr); + void (*qspi_status_control_reg_write)(spi_config_t *spi_config, + qspi_reg_t *qspi_reg, + uint16_t write_command, + uint32_t addr, + uint16_t write_value, + uint32_t cs_no, + uint32_t wr_reg_delay_ms); + void (*qspi_flash_protection)(spi_config_t *spi_config, + qspi_reg_t *qspi_reg, + uint32_t protection, + uint32_t wr_reg_delay_ms); + void (*RSI_QSPI_ConfigQspiDll)(spi_config_t *spi_config, qspi_reg_t *qspi_reg); + void (*RSI_QSPI_ResetFlash)(qspi_reg_t *qspi_reg, uint32_t cs_no); + void (*RSI_QSPI_UpdateOperatingMode_and_ResetType)(qspi_reg_t *qspi_reg, uint32_t operating_mode); +} ROM_QSPI_API_T; +//////////////////////////QSPI END////////////////////////// + +/** @brief TIMERS ROM indirect function structure */ +typedef PRE_PACK struct POST_PACK { + RSI_UDMA_HANDLE_T (*udma_init)(void *mem, const RSI_UDMA_INIT_T *pInit); + + uint32_t (*udma_get_channel_transfer_mode)(RSI_UDMA_HANDLE_T pHandle, RSI_UDMA_CHA_CFG_T *pCfg); + rsi_error_t (*udma_setup_channel_transfer)(RSI_UDMA_HANDLE_T pHandle, + RSI_UDMA_CHA_CFG_T *pCfg, + RSI_UDMA_CHA_CONFIG_DATA_T vsUdmaChaConfigData, + void *pSrcAddr, + void *pDstAddr); + + rsi_error_t (*udma_set_channel_scatter_gather_transfer)(RSI_UDMA_HANDLE_T pHandle, + uint8_t dmaCh, + uint32_t taskCount, + void *pTaskList, + uint32_t transferType); + + uint32_t (*udma_get_channel_transfer_length)(RSI_UDMA_HANDLE_T pHandle, + RSI_UDMA_CHA_CFG_T *pCfg, + RSI_UDMA_CHA_CONFIG_DATA_T vsUDMAChaConfigData); + + rsi_error_t (*udma_setup_channel)(RSI_UDMA_HANDLE_T pHandle, RSI_UDMA_CHA_CFG_T *pCfg); + + void (*udma_deInit)(RSI_UDMA_HANDLE_T pHandle, RSI_UDMA_CHA_CFG_T *pCfg); + + void (*udma_interrupt_handler)(RSI_UDMA_HANDLE_T pHandle); + + rsi_error_t (*udma_interrupt_enable)(RSI_UDMA_HANDLE_T pHandle, uint8_t dmaCh); + +} ROM_UDMA_API_T; + +//////////////////////////UDMA END////////////////////////// + +//////////////////////////UDMA WRAPPERS ////////////////////////// +typedef PRE_PACK struct POST_PACK { + RSI_UDMA_HANDLE_T(*uDMAx_Initialize) + (UDMA_RESOURCES *udma, RSI_UDMA_DESC_T *UDMA_Table, RSI_UDMA_HANDLE_T udmaHandle, uint32_t *mem); + int32_t (*uDMAx_Uninitialize)(UDMA_RESOURCES *udma); + int32_t (*uDMAx_ChannelConfigure)(UDMA_RESOURCES *udma, + uint8_t ch, + uint32_t src_addr, + uint32_t dest_addr, + uint32_t size, + RSI_UDMA_CHA_CONFIG_DATA_T control, + RSI_UDMA_CHA_CFG_T *config, + UDMA_SignalEvent_t cb_event, + UDMA_Channel_Info *chnl_info, + RSI_UDMA_HANDLE_T udmaHandle); + int32_t (*uDMAx_ChannelEnable)(uint8_t ch, UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle); + int32_t (*uDMAx_DMAEnable)(UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle); + int32_t (*uDMAx_ChannelDisable)(uint8_t ch, UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle); + uint32_t (*uDMAx_ChannelGetCount)(uint8_t ch, + RSI_UDMA_CHA_CONFIG_DATA_T control, + RSI_UDMA_CHA_CFG_T config, + UDMA_RESOURCES *udma, + RSI_UDMA_HANDLE_T udmaHandle); + void (*uDMAx_IRQHandler)(UDMA_RESOURCES *udma, RSI_UDMA_DESC_T *UDMA_Table, UDMA_Channel_Info *chnl_info); + +} ROM_UDMA_WRAPPER_API_T; +//////////////////////////UDMA WRAPPERS END////////////////////////// +#ifndef SLI_SI917B0 +typedef PRE_PACK struct POST_PACK { + rsi_error_t (*mcpwm_counter_reset)(RSI_MCPWM_T *pMCPWM, uint8_t chnlNum); + + rsi_error_t (*mcpwm_channel_reset)(RSI_MCPWM_T *pMCPWM, uint8_t chnlNum); + + rsi_error_t (*mcpwm_start)(RSI_MCPWM_T *pMCPWM, uint8_t chnlNum); + + rsi_error_t (*mcpwm_stop)(RSI_MCPWM_T *pMCPWM, uint8_t chnlNum); + + rsi_error_t (*mcpwm_set_time_period)(RSI_MCPWM_T *pMCPWM, uint8_t chnlNum, uint16_t period, uint16_t initVal); + + void (*mcpwm_special_event_trigger_config)(RSI_MCPWM_T *pMCPWM, + boolean_t svtDir, + RSI_MCPWM_SVT_CONFIG_T *pMCPWMSVTConfig); + + rsi_error_t (*mcpwm_dead_time_value_set)(RSI_MCPWM_T *pMCPWM, + RSI_MCPWM_DT_CONFIG_T *pMCPWMDeadTimeConfig, + uint8_t chnlNum); + + rsi_error_t (*mcpwm_period_control_config)(RSI_MCPWM_T *pMCPWM, + uint32_t postScale, + uint32_t preScale, + uint8_t chnlNum); + + rsi_error_t (*mcpwm_fault_avalue_set)(RSI_MCPWM_T *pMCPWM, uint8_t pwmOutput, uint8_t value); + + rsi_error_t (*mcpwm_fault_bvalue_set)(RSI_MCPWM_T *pMCPWM, uint8_t pwmOutput, uint8_t value); + + rsi_error_t (*mcpwm_set_base_timer_mode)(RSI_MCPWM_T *pMCPWM, uint8_t mode, uint8_t chnlNum); + + rsi_error_t (*mcpwm_set_output_mode)(RSI_MCPWM_T *pMCPWM, boolean_t mode, uint8_t chnlNum); + + void (*mcpwm_set_output_polarity)(RSI_MCPWM_T *pMCPWM, boolean_t polL, boolean_t polH); + + void (*mcpwm_interrupt_handler)(RSI_MCPWM_T *pMCPWM, RSI_MCPWM_CALLBACK_T *pCallBack); + +} ROM_MCPWM_API_T; +#endif +////////////MCPWM END/////////////////////// + +/* RPDMA Function Pointer Table */ +typedef PRE_PACK struct POST_PACK { + uint32_t (*gpdma_get_mem_size)(void); + + RSI_GPDMA_HANDLE_T (*gpdma_init)(void *mem, const RSI_GPDMA_INIT_T *pInit); + + void (*gpdma_register_callback)(RSI_GPDMA_HANDLE_T pHandle, uint32_t cbIndex, gpdmaTransferCompleteCB pCB); + + rsi_error_t (*gpdma_abort_channel)(RSI_GPDMA_HANDLE_T pHandle, uint8_t dmaCh); + + rsi_error_t (*gpdma_setup_channel)(RSI_GPDMA_HANDLE_T pHandle, RSI_GPDMA_CHA_CFG_T *pCfg); + + rsi_error_t (*gpdma_build_descriptors)(RSI_GPDMA_HANDLE_T pHandle, + RSI_GPDMA_DESC_T *pXferCfg, + RSI_GPDMA_DESC_T *pDesc, + RSI_GPDMA_DESC_T *pDescPrev); + + rsi_error_t (*gpdma_setup_channelTransfer)(RSI_GPDMA_HANDLE_T pHandle, uint8_t dmaCh, RSI_GPDMA_DESC_T *pDesc); + + void (*gpdma_interrupt_handler)(RSI_GPDMA_HANDLE_T pHandle); + + void (*gpdma_deInit)(RSI_GPDMA_HANDLE_T pHandle, RSI_GPDMA_CHA_CFG_T *pCfg); + + rsi_error_t (*gpdma_dma_channel_trigger)(RSI_GPDMA_HANDLE_T pHandle, uint8_t dmaCh); + + uint32_t (*gpdma_channel_is_enabled)(RSI_GPDMA_HANDLE_T pHandle, uint8_t dmaCh); + + rsi_error_t (*gpdma_interrupt_disable)(RSI_GPDMA_HANDLE_T pHandle, RSI_GPDMA_CHA_CFG_T *pCfg); + + rsi_error_t (*gpdma_interrupt_enable)(RSI_GPDMA_HANDLE_T pHandle, RSI_GPDMA_CHA_CFG_T *pCfg); + + rsi_error_t (*gpdma_error_status_clear)(RSI_GPDMA_HANDLE_T pHandle, RSI_GPDMA_CHA_CFG_T *pCfg); + + uint32_t (*gpdma_get_error_status)(RSI_GPDMA_HANDLE_T pHandle, RSI_GPDMA_CHA_CFG_T *pCfg); + + rsi_error_t (*gpdma_interrupt_clear)(RSI_GPDMA_HANDLE_T pHandle, RSI_GPDMA_CHA_CFG_T *pCfg); + + uint32_t (*gpdma_interrupt_status)(RSI_GPDMA_HANDLE_T pHandle, RSI_GPDMA_CHA_CFG_T *pCfg); + +} ROM_RPDMA_API_T; +///////////////////////////GPDMA END///////////////////// + +/** @brief TIMERS ROM indirect function structure */ +typedef PRE_PACK struct POST_PACK { + rsi_error_t (*timers_microsec_timer_config)(RSI_TIMERS_T *pTIMER, + uint8_t timerNum, + uint16_t integer, + uint8_t fractional, + uint8_t mode); + uint32_t (*timers_read_timer)(RSI_TIMERS_T *pTIMER, uint8_t timerNum, boolean_t countDir); +} ROM_TIMERS_API_T; + +////////////////////////////TIMERS END/////////////////////// + +//USART +typedef PRE_PACK struct POST_PACK { + int32_t (*USART_Initialize)(ARM_USART_SignalEvent_t cb_event, + USART_RESOURCES *usart, + UDMA_RESOURCES *udma, + RSI_UDMA_DESC_T *UDMA_Table, + RSI_UDMA_HANDLE_T *udmaHandle, + uint32_t *mem); + int32_t (*USART_Uninitialize)(USART_RESOURCES *usart, UDMA_RESOURCES *udma); + int32_t (*USART_PowerControl)(ARM_POWER_STATE state, + USART_RESOURCES *usart, + UDMA_RESOURCES *udma, + RSI_UDMA_HANDLE_T udmaHandle); + int32_t (*USART_SetBaudrate)(uint32_t baudrate, uint32_t baseClk, USART_RESOURCES *usart); + int32_t (*USART_Send_Data)(const void *data, + uint32_t num, + USART_RESOURCES *usart, + UDMA_RESOURCES *udma, + UDMA_Channel_Info *chnl_info, + RSI_UDMA_HANDLE_T udmaHandle); + int32_t (*USART_Receive_Data)(const void *data, + uint32_t num, + USART_RESOURCES *usart, + UDMA_RESOURCES *udma, + UDMA_Channel_Info *chnl_info, + RSI_UDMA_HANDLE_T udmaHandle); + int32_t (*USART_Transfer)(const void *data_out, + void *data_in, + uint32_t num, + USART_RESOURCES *usart, + UDMA_RESOURCES *udma, + UDMA_Channel_Info *chnl_info, + RSI_UDMA_HANDLE_T udmaHandle); + uint32_t (*USART_GetTxCount)(USART_RESOURCES *usart); + uint32_t (*USART_GetRxCount)(USART_RESOURCES *usart); + int32_t (*USART_Control)(uint32_t control, + uint32_t arg, + uint32_t baseClk, + USART_RESOURCES *usart, + UDMA_RESOURCES *udma, + RSI_UDMA_HANDLE_T udmaHandle); + ARM_USART_STATUS (*USART_GetStatus)(USART_RESOURCES *usart); + int32_t (*USART_SetModemControl)(ARM_USART_MODEM_CONTROL control, USART_RESOURCES *usart); + ARM_USART_MODEM_STATUS (*USART_GetModemStatus)(USART_RESOURCES *usart); + void (*UartIrqHandler)(USART_RESOURCES *usart); + void (*USART_UDMA_Tx_Event)(uint32_t event, uint8_t dmaCh, USART_RESOURCES *usart); + void (*USART_UDMA_Rx_Event)(uint32_t event, uint8_t dmaCh, USART_RESOURCES *usart); +} ROM_USART_API_T; +//////////////////////USART END//////////////////// + +//GPSI +typedef PRE_PACK struct POST_PACK { + int32_t (*GSPI_Initialize)(ARM_SPI_SignalEvent_t cb_event, + const GSPI_RESOURCES *gspi, + UDMA_RESOURCES *udma, + RSI_UDMA_DESC_T *UDMA_Table, + RSI_UDMA_HANDLE_T *udmaHandle, + uint32_t *mem); + int32_t (*GSPI_Uninitialize)(const GSPI_RESOURCES *gspi, UDMA_RESOURCES *udma); + int32_t (*GSPI_PowerControl)(ARM_POWER_STATE state, const GSPI_RESOURCES *gspi); +#ifdef SLI_SI917B0 + int32_t (*GSPI_Control)(uint32_t control, + uint32_t arg, + const GSPI_RESOURCES *gspi, + uint32_t base_clock, + uint8_t spi_slavenumber); +#else + int32_t (*GSPI_Control)(uint32_t control, uint32_t arg, const GSPI_RESOURCES *gspi, uint32_t base_clock); +#endif + int32_t (*GSPI_Send)(const void *data, + uint32_t num, + const GSPI_RESOURCES *gspi, + UDMA_RESOURCES *udma, + UDMA_Channel_Info *chnl_info, + RSI_UDMA_HANDLE_T udmaHandle); + int32_t (*GSPI_Receive)(void *data, + uint32_t num, + const GSPI_RESOURCES *gspi, + UDMA_RESOURCES *udma, + UDMA_Channel_Info *chnl_info, + RSI_UDMA_HANDLE_T udmaHandle); + int32_t (*GSPI_Transfer)(const void *data_out, + void *data_in, + uint32_t num, + const GSPI_RESOURCES *gspi, + UDMA_RESOURCES *udma, + UDMA_Channel_Info *chnl_info, + RSI_UDMA_HANDLE_T udmaHandle); + uint32_t (*GSPI_GetDataCount)(const GSPI_RESOURCES *gspi); + void (*GSPI_UDMA_Tx_Event)(uint32_t event, uint8_t dmaCh, GSPI_RESOURCES *gspi); + void (*GSPI_UDMA_Rx_Event)(uint32_t event, uint8_t dmaCh, GSPI_RESOURCES *gspi); + void (*GSPI_IRQHandler)(const GSPI_RESOURCES *gspi); +} ROM_GSPI_API_T; +////////////////////////////GSPI END////////////////////////// + +//i2s +typedef PRE_PACK struct POST_PACK { + int32_t (*I2S_Initialize)(ARM_SAI_SignalEvent_t cb_event, + I2S_RESOURCES *i2s, + UDMA_RESOURCES *udma, + RSI_UDMA_DESC_T *UDMA_Table, + RSI_UDMA_HANDLE_T *udmaHandle, + uint32_t *mem); + int32_t (*I2S_Uninitialize)(I2S_RESOURCES *i2s, UDMA_RESOURCES *udma); + int32_t (*I2S_PowerControl)(ARM_POWER_STATE state, + I2S_RESOURCES *i2s, + UDMA_RESOURCES *udma, + RSI_UDMA_HANDLE_T udmaHandle); + int32_t (*I2S_Send)(const void *data, + uint32_t num, + I2S_RESOURCES *i2s, + UDMA_RESOURCES *udma, + UDMA_Channel_Info *chnl_info, + RSI_UDMA_HANDLE_T udmaHandle); + int32_t (*I2S_Receive)(void *data, + uint32_t num, + I2S_RESOURCES *i2s, + UDMA_RESOURCES *udma, + UDMA_Channel_Info *chnl_info, + RSI_UDMA_HANDLE_T udmaHandle); + uint32_t (*I2S_GetTxCount)(I2S_RESOURCES *i2s); + uint32_t (*I2S_GetRxCount)(I2S_RESOURCES *i2s); + int32_t (*I2S_Control)(uint32_t control, + uint32_t arg1, + uint32_t arg2, + I2S_RESOURCES *i2s, + UDMA_RESOURCES *udma, + RSI_UDMA_HANDLE_T udmaHandle); + ARM_SAI_STATUS (*I2S_GetStatus)(I2S_RESOURCES *i2s); + void (*I2S_IRQHandler)(I2S_RESOURCES *i2s); + void (*I2S_UDMA_Tx_Event)(uint32_t event, uint8_t dmaCh, I2S_RESOURCES *i2s); + void (*I2S_UDMA_Rx_Event)(uint32_t event, uint8_t dmaCh, I2S_RESOURCES *i2s); +} ROM_I2S_API_T; +////////////////////////////I2S END//////////////////////// + +//I2C +typedef PRE_PACK struct POST_PACK { + int32_t (*I2Cx_Initialize)(ARM_I2C_SignalEvent_t cb_event, I2C_RESOURCES *i2c); + int32_t (*I2Cx_Uninitialize)(I2C_RESOURCES *i2c); + int32_t (*I2Cx_PowerControl)(ARM_POWER_STATE state, I2C_RESOURCES *i2c); + int32_t ( + *I2Cx_MasterTransmit)(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending, I2C_RESOURCES *i2c); + int32_t (*I2Cx_MasterReceive)(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending, I2C_RESOURCES *i2c); + int32_t (*I2Cx_SlaveTransmit)(const uint8_t *data, uint32_t num, I2C_RESOURCES *i2c); + int32_t (*I2Cx_SlaveReceive)(uint8_t *data, uint32_t num, I2C_RESOURCES *i2c); + int32_t (*I2Cx_GetDataCount)(I2C_RESOURCES *i2c); + int32_t (*I2Cx_Control)(uint32_t control, uint32_t arg, I2C_RESOURCES *i2c, uint32_t clock); + ARM_I2C_STATUS (*I2Cx_GetStatus)(I2C_RESOURCES *i2c); + uint32_t (*I2Cx_MasterHandler)(I2C_RESOURCES *i2c); + uint32_t (*I2Cx_SlaveHandler)(I2C_RESOURCES *i2c); + void (*I2Cx_IRQHandler)(I2C_RESOURCES *i2c); +} ROM_I2C_API_T; +///////////////////I2C END///////////////// +#if 0 +typedef PRE_PACK struct POST_PACK + { + void (* rsi_arm_offset_f32_opt)(int32_t *pSrc, int32_t scale, int32_t *pDst,uint32_t length,uint16_t inBank, uint16_t outBank ); + + void (* rsi_arm_offset_q7_opt)( q7_t *pSrc, q7_t scale, q7_t *pDst, uint32_t length,uint16_t inBank, uint16_t outBank); + + void (* rsi_arm_offset_q15_opt)( q15_t *pSrc, q15_t scale, q15_t *pDst, uint32_t length,uint16_t inBank, uint16_t outBank); + + void (* rsi_arm_offset_q31_opt)( q31_t *pSrc, q31_t scale, q31_t *pDst, uint32_t length,uint16_t inBank, uint16_t outBank); + + void (* rsi_fim_scalar_sub_q7)(q7_t *pSrc,q7_t scale,q7_t *pDst, uint32_t blockSize,uint16_t inBank, uint16_t outBank); + + void (* rsi_fim_scalar_sub_q31)(q31_t *pSrc,q31_t scale,q31_t *pDst, uint32_t blockSize,uint16_t inBank, uint16_t outBank); + + void (* rsi_fim_scalar_sub_f32)( int32_t *pSrc, int32_t scale,int32_t *pDst, uint32_t length,uint16_t inBank, uint16_t outBank); + + void (* rsi_arm_scale_f32_opt)( int32_t *pSrc,int32_t scale,int32_t *pDst, uint32_t length,uint16_t inBank, uint16_t outBank); + + void (* rsi_arm_scale_q7_opt)( q7_t *pSrc,q7_t scaleFract,int8_t shift,q7_t *pDst,uint32_t blockSize,uint16_t inBank, uint16_t outBank); + + void (* rsi_arm_scale_q15_opt)( q15_t *pSrc, q15_t scaleFract, int8_t shift, q15_t *pDst,uint32_t blockSize,uint16_t inBank, uint16_t outBank); + + void (* rsi_arm_scale_q31_opt)( q31_t * pSrc,q31_t scaleFract, int8_t shift,q31_t * pDst,uint32_t blockSize,uint16_t inBank, uint16_t outBank); + + void (* rsi_fim_scalar_mul_q15)(q15_t *pSrc,q15_t *scale,uint32_t blockSize, typ_data_t typ_data,uint16_t inBank, uint16_t outBank ); + + void (* rsi_arm_add_f32_opt)( int32_t *pSrcA, int32_t *pSrcB,uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); + + void (* rsi_arm_add_q7_opt)( q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); + + void (* rsi_arm_add_q15_opt)( q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); + + void (* rsi_arm_add_q31_opt)( q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); + + void (* rsi_fim_vector_add_q15)(q15_t *pIn1, q15_t *pIn2,q15_t *pDst,uint32_t blockSize, typ_data_t typ_data,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); + + void (* rsi_arm_sub_f32_opt)(int32_t *pSrcA, int32_t *pSrcB,int32_t *pDst, uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); + + void (* rsi_arm_sub_q7_opt)( q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); + + void (* rsi_arm_sub_q15_opt)( q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst,uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); + + void (*rsi_arm_sub_q31_opt)( q31_t *pSrcA, q31_t *pSrcB,q31_t *pDst, uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); + + void (* rsi_fim_read_data)( uint32_t bank,uint32_t length,volatile void *pDst, uint8_t data_type,typ_data_t type_data); + + void (* rsi_fim_vector_sub_q15)( q15_t *pIn1, q15_t *pIn2,q15_t *pDst,uint32_t blockSize,typ_data_t typ_data,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); + + void (* rsi_arm_mult_f32_opt)( int32_t *pIn1,int32_t *pIn2, uint32_t SatTruncRound,uint32_t length,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); + + void (* rsi_arm_mult_q7_opt)( q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); + + void (* rsi_arm_mult_q15_opt)( q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); + + void (* rsi_arm_mult_q31_opt)(q31_t *pSrcA,q31_t *pSrcB,q31_t *pDst,uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); + + void (* rsi_fim_vector_mul_q15)( q15_t *pIn1, q15_t *pIn2,q15_t *pDst,uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); + + void (* rsi_arm_cmplx_mult_real_q15_opt)(q15_t *pSrcCmplx,q15_t *pSrcReal,q15_t *pDst,uint32_t numSamples,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); + + void (* rsi_arm_cmplx_mult_cmplx_q15_opt)(q15_t * pSrcA,q15_t * pSrcB,q15_t *pDst,uint32_t numSamples,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); + + void (* rsi_arm_cmplx_mag_squared_q15_opt)(q15_t *pSrc,q15_t *pDst,uint32_t numSamples,uint16_t inBank, uint16_t outBank); + + void (* rsi_fim_absSqr_q7)( q7_t *pSrc,uint32_t length,uint16_t inBank, uint16_t outBank); + + void (* rsi_fim_absSqr_q15)( q15_t *pSrc, uint32_t length,uint16_t inBank, uint16_t outBank); + + void (* rsi_fim_absSqr_q31)( q31_t *pSrc,uint32_t length,uint16_t inBank, uint16_t outBank); + + void (* rsi_fim_absSqr_f32)(int32_t *pSrc, uint32_t length,uint16_t inBank, uint16_t outBank); + + rsi_error_t (* rsi_arm_mat_mult_f32_opt)( const arm_matrix_instance_f32_opt *pSrcA, + const arm_matrix_instance_f32_opt *pSrcB,arm_matrix_instance_f32_opt *pDst,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); + + rsi_error_t (* rsi_arm_mat_mult_q31_opt)( const arm_matrix_instance_q31_opt * pSrcA,const arm_matrix_instance_q31_opt * pSrcB, + arm_matrix_instance_q31_opt * pDst,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); + + rsi_error_t (* rsi_arm_mat_mult_q15_opt)( const arm_matrix_instance_q15_opt * pSrcA, + const arm_matrix_instance_q15_opt * pSrcB,arm_matrix_instance_q15_opt * pDst,q15_t * pState + ,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); + + void (* rsi_arm_fir_init_f32_opt)( arm_fir_instance_f32_opt *S, uint16_t numTaps,int32_t *pCoeffs, int32_t *pState, + uint32_t blockSize); + + void (* rsi_arm_fir_f32_opt)( arm_fir_instance_f32_opt *S, int32_t *pSrc, int32_t *pDst, + uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); + + void (* rsi_arm_fir_init_q31_opt)( arm_fir_instance_q31_opt *S,uint16_t numTaps,q31_t *pCoeffs, + q31_t *pState, uint32_t blockSize); + + void (* rsi_arm_fir_q31_opt)( arm_fir_instance_q31_opt *S, q31_t *pSrc,q31_t *pDst, uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); + + void (* rsi_arm_fir_init_q15_opt)( arm_fir_instance_q15_opt *S,uint16_t numTaps,q15_t *pCoeffs, + q15_t *pState, uint32_t blockSize); + + void (* rsi_arm_fir_q15_opt)( arm_fir_instance_q15_opt *S, q15_t *pSrc,q15_t *pDst, uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); + + void (* rsi_arm_fir_init_q7_opt)( arm_fir_instance_q7_opt *S,uint16_t numTaps,q7_t *pCoeffs, + q7_t *pState, uint32_t blockSize); + + void (* rsi_arm_fir_q7_opt)( arm_fir_instance_q7_opt *S, q7_t *pSrc,q7_t *pDst, + uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); + + void (* rsi_fim_interrupt_handler)(volatile FIM_Type *ptFim); + + void (* rsi_arm_fir_interpolate_f32_opt)( const arm_fir_interpolate_instance_f32_opt * S, int32_t * pSrc, + int32_t * pDst,uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); + + arm_status (* rsi_arm_fir_interpolate_init_f32_opt)( arm_fir_interpolate_instance_f32_opt * S, + uint8_t L, uint16_t numTaps, int32_t * pCoeffs, + int32_t * pState,uint32_t blockSize ); + + arm_status (* rsi_arm_fir_interpolate_init_q15_opt)( arm_fir_interpolate_instance_q15_opt * S,uint8_t L, + uint16_t numTaps,q15_t * pCoeffs,q15_t * pState, + uint32_t blockSize ); + + arm_status (* rsi_arm_fir_interpolate_init_q31_opt)( arm_fir_interpolate_instance_q31_opt *S, uint8_t L, + uint16_t numTaps,q31_t * pCoeffs, q31_t * pState, + uint32_t blockSize ); + + void (* rsi_arm_fir_interpolate_q15_opt)( arm_fir_interpolate_instance_q15_opt * S,q15_t * pSrc,q15_t *pDst, + uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); + + + void (* rsi_arm_fir_interpolate_q31_opt)( const arm_fir_interpolate_instance_q31_opt * S, q31_t * pSrc, + q31_t * pDst, uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); + }ROM_FIM_API_T; + +/////////////////////FIM END////////////////////// +#endif +typedef PRE_PACK struct POST_PACK { + void (*ct_ocu_high_Low_toggle_select)(RSI_CT_T *pCT, boolean_t lowHigh, boolean_t counterNum, uint8_t outputSel); + rsi_error_t (*ct_wfg_control_config)(RSI_CT_T *pCT, WFG_PARAMS_T ctrlReg); + rsi_error_t (*ct_ocu_control)(RSI_CT_T *pCT, + boolean_t counterNum, + boolean_t dmaEn, + OCU_PARAMS_T *pOCUparams, + RSI_CT_CALLBACK_T *pCB); + + rsi_error_t (*ct_wfg_comapre_value_set)(RSI_CT_T *pCT, boolean_t counterNum, OCU_PARAMS_T *pOCUparams); +} ROM_CT_API_T; + +///////////////////////CT END/////////////////////////////////// +/** @brief SPI master ROM indirect function structure */ +typedef PRE_PACK struct POST_PACK { + void (*ps_clr_wkp_up_status)(uint32_t wakeUpIntrClear); + void (*ps_bg_ldo_config)(uint8_t ldo_0p6_ctrl, uint8_t ldo_0p6_lp_mode); + void (*ps_configure_trim_values)(uint16_t lf_ro_trim, + uint16_t lf_rc_trim, + uint16_t hf_ro_trim, + uint16_t hf_rc_trim, + uint16_t bg_ptat_trim, + uint16_t bg_trim); + void (*ps_wireless_shutdown)(void); + uint32_t (*RSI_SelectTaBootOption)(uint32_t option); + void (*RSI_GotoSleepWithRetention)(uint32_t stack_address, + uint32_t jump_cb_address, + uint32_t vector_offset, + uint32_t mode); + void (*RSI_WakeupWirelessProcessor)(void); +} ROM_PWR_API_T; +///////////////////////POWERSAVE END/////////////////////////// + +typedef PRE_PACK struct POST_PACK { + rsi_error_t (*ulpss_clock_config)(M4CLK_Type *pCLK, boolean_t clkEnable, uint16_t divFactor, boolean_t oddDivFactor); + + rsi_error_t (*ulpss_ulp_peri_clk_enable)(ULPCLK_Type *pULPCLK, uint32_t u32Flags); + + rsi_error_t (*ulpss_ulp_peri_clk_disable)(ULPCLK_Type *pULPCLK, uint32_t u32Flags); + + rsi_error_t (*ulpss_ulp_dyn_clk_enable)(ULPCLK_Type *pULPCLK, uint32_t u32Flags); + + rsi_error_t (*ulpss_ulp_dyn_clk_disable)(ULPCLK_Type *pULPCLK, uint32_t u32Flags); + + rsi_error_t (*ulpss_ulp_ssi_clk_config)(ULPCLK_Type *pULPCLK, + CLK_ENABLE_T clkType, + ULP_SSI_CLK_SELECT_T clkSource, + uint16_t divFactor); + + rsi_error_t (*ulpss_ulp_i2s_clk_config)(ULPCLK_Type *pULPCLK, ULP_I2S_CLK_SELECT_T clkSource, uint16_t divFactor); + + rsi_error_t (*ulpss_ulp_uar_clk_config)(ULPCLK_Type *pULPCLK, + CLK_ENABLE_T clkType, + boolean_t bFrClkSel, + ULP_UART_CLK_SELECT_T clkSource, + uint16_t divFactor); + + rsi_error_t (*ulpss_time_clk_disable)(ULPCLK_Type *pULPCLK); + rsi_error_t (*ulpss_time_clk_config)(ULPCLK_Type *pULPCLK, + CLK_ENABLE_T clkType, + boolean_t bTmrSync, + ULP_TIMER_CLK_SELECT_T clkSource, + uint8_t skipSwitchTime); + + rsi_error_t (*ulpss_aux_clk_config)(ULPCLK_Type *pULPCLK, CLK_ENABLE_T clkType, ULP_AUX_CLK_SELECT_T clkSource); + + rsi_error_t (*ulpss_vad_clk_config)(ULPCLK_Type *pULPCLK, + ULP_VAD_CLK_SELECT_T clkSource, + ULP_VAD_FCLK_SELECT_T FclkSource, + uint16_t divFactor); + + rsi_error_t (*ulpss_touch_clk_config)(ULPCLK_Type *pULPCLK, ULP_TOUCH_CLK_SELECT_T clkSource, uint16_t divFactor); + + rsi_error_t (*ulpss_slp_sensor_clk_config)(ULPCLK_Type *pULPCLK, boolean_t clkEnable, uint32_t divFactor); + + rsi_error_t (*ulpss_peripheral_enable)(ULPCLK_Type *pULPCLK, ULPPERIPHERALS_CLK_T module, CLK_ENABLE_T clkType); + + rsi_error_t (*ulpss_peripheral_disable)(ULPCLK_Type *pULPCLK, ULPPERIPHERALS_CLK_T module); + +} ROM_ULPSS_CLK_API_T; + +////////////////////////////ULPSS CLOCKS END///////////////////////////////// + +typedef PRE_PACK struct POST_PACK { + boolean_t (*clk_check_pll_lock)(PLL_TYPE_T pllType); + rsi_error_t (*clk_soc_pll_clk_enable)(boolean_t clkEnable); + rsi_error_t (*clk_set_soc_pll_freq)(M4CLK_Type *pCLK, uint32_t socPllFreq, uint32_t pllRefClk); + rsi_error_t (*clk_soc_pll_set_freq_div)(M4CLK_Type *pCLK, + boolean_t clk_en, + uint16_t divFactor, + uint16_t nFactor, + uint16_t mFactor, + uint16_t fcwF, + uint16_t dcoFixSel, + uint16_t ldoProg); + rsi_error_t (*clk_soc_pll_clk_set)(M4CLK_Type *pCLK); + rsi_error_t (*clk_soc_pll_clk_bypass_enable)(boolean_t clkEnable); + rsi_error_t (*clk_soc_pll_clk_reset)(void); + rsi_error_t (*clk_soc_pll_pd_enable)(boolean_t en); + rsi_error_t (*clk_soc_pll_turn_off)(void); + rsi_error_t (*clk_soc_pll_turn_on)(void); + rsi_error_t (*clk_i2s_pll_clk_enable)(boolean_t clkEnable); + rsi_error_t (*clk_i2s_pll_clk_bypass_enable)(boolean_t clkEnable); + rsi_error_t (*clk_i2s_pll_pd_enable)(boolean_t en); + rsi_error_t (*clk_i2s_pll_turn_off)(void); + rsi_error_t (*clk_i2s_pll_turn_on)(void); + rsi_error_t (*clk_set_i2s_pll_freq)(M4CLK_Type *pCLK, uint32_t i2sPllFreq, uint32_t fXtal); + rsi_error_t (*clk_i2s_pll_set_freq_div)(M4CLK_Type *pCLK, + uint16_t u16DivFactor1, + uint16_t u16DivFactor2, + uint16_t nFactor, + uint16_t mFactor, + uint16_t fcwF); + rsi_error_t (*clk_i2s_pll_clk_set)(M4CLK_Type *pCLK); + rsi_error_t (*clk_i2s_pll_clk_reset)(void); + rsi_error_t (*clk_intf_pll_clk_enable)(boolean_t clkEnable); + rsi_error_t (*clk_intf_pll_pd_enable)(boolean_t en); + rsi_error_t (*clk_intf_pll_turn_off)(void); + rsi_error_t (*clk_set_intf_pll_freq)(M4CLK_Type *pCLK, uint32_t intfPllFreq, uint32_t pllRefClk); + rsi_error_t (*clk_intf_pll_set_freq_div)(M4CLK_Type *pCLK, + boolean_t clk_en, + uint16_t divFactor, + uint16_t nFactor, + uint16_t mFactor, + uint16_t fcwF, + uint16_t dcoFixSel, + uint16_t ldoProg); + rsi_error_t (*clk_intf_pll_clk_bypass_enable)(boolean_t clkEnable); + rsi_error_t (*clk_intf_pll_turn_on)(void); + rsi_error_t (*clk_intf_pll_clk_reset)(void); + rsi_error_t (*clk_intf_pll_clk_set)(M4CLK_Type *pCLK); + rsi_error_t (*clk_peripheral_clk_enable1)(M4CLK_Type *pCLK, uint32_t flags); + rsi_error_t (*clk_peripheral_clk_disable1)(M4CLK_Type *pCLK, uint32_t flags); + rsi_error_t (*clk_peripheral_clk_enable2)(M4CLK_Type *pCLK, uint32_t flags); + rsi_error_t (*clk_peripheral_clk_disable2)(M4CLK_Type *pCLK, uint32_t flags); + rsi_error_t (*clk_peripheral_clk_enable3)(M4CLK_Type *pCLK, uint32_t flags); + rsi_error_t (*clk_peripheral_clk_disable3)(M4CLK_Type *pCLK, uint32_t flags); + rsi_error_t (*clk_dynamic_clk_gate_disable)(M4CLK_Type *pCLK, uint32_t flags); + rsi_error_t (*clk_dynamic_clk_gate_disable2)(M4CLK_Type *pCLK, uint32_t flags); + rsi_error_t (*clk_dynamic_clk_gate_enable)(M4CLK_Type *pCLK, uint32_t flags); + rsi_error_t (*clk_dynamic_clk_gate_enable2)(M4CLK_Type *pCLK, uint32_t flags); + rsi_error_t (*ulpss_enable_ref_clks)(REF_CLK_ENABLE_T enable, SRC_TYPE_T srcType, cdDelay delayFn); + rsi_error_t (*ulpss_disable_ref_clks)(REF_CLK_ENABLE_T clk_type); + rsi_error_t (*clk_qspi_clk_config)(M4CLK_Type *pCLK, + QSPI_CLK_SRC_SEL_T clkSource, + boolean_t swalloEn, + boolean_t OddDivEn, + uint32_t divFactor); + rsi_error_t (*clk_usart_clk_config)(M4CLK_Type *pCLK, + CLK_ENABLE_T clkType, + boolean_t FracDivEn, + EN_USART_T EN_USART_T, + USART_CLK_SRC_SEL_T clkSource, + uint32_t divFactor); + rsi_error_t (*clk_ssi_mst_clk_config)(M4CLK_Type *pCLK, + CLK_ENABLE_T clkType, + SSI_MST_CLK_SRC_SEL_T clkSource, + uint32_t divFactor); +#ifndef SLI_SI917 + rsi_error_t (*clk_sd_mem_clk_config)(M4CLK_Type *pCLK, + boolean_t swalloEn, + SDMEM_CLK_SRC_SEL_T clkSource, + uint32_t divFactor); +#endif + rsi_error_t (*clk_ct_clk_config)(M4CLK_Type *pCLK, + CT_CLK_SRC_SEL_T clkSource, + uint32_t divFactor, + CLK_ENABLE_T clkType); +#ifndef SLI_SI917 + rsi_error_t (*clk_cci_clk_config)(M4CLK_Type *pCLK, + CCI_CLK_SRC_SEL_T clkSource, + uint32_t divFactor, + CLK_ENABLE_T clkType); +#endif + rsi_error_t (*clk_i2s_clk_config)(M4CLK_Type *pCLK, I2S_CLK_SRC_SEL_T clkSource, uint32_t divFactor); + rsi_error_t (*clk_mcu_clk_cut_config)(M4CLK_Type *pCLK, MCU_CLKOUT_SRC_SEL_T clkSource, uint32_t divFactor); +#ifndef SLI_SI917 + rsi_error_t (*clk_can_clk_config)(M4CLK_Type *pCLK, uint32_t divFactor, CLK_ENABLE_T clkType); + rsi_error_t (*clk_ethernet_clk_config)(M4CLK_Type *pCLK, + boolean_t swalloEn, + ETHERNET_CLK_SRC_SEL_T clkSource, + uint32_t divFactor); +#endif + rsi_error_t (*clk_m4_soc_clk_div)(M4CLK_Type *pCLK, uint32_t divFactor); + rsi_error_t (*clk_qspi_clk_div)(M4CLK_Type *pCLK, boolean_t u8SwallowEn, boolean_t u8OddDivEn, uint32_t divFactor); + rsi_error_t (*clk_ct_clk_div)(M4CLK_Type *pCLK, uint32_t divFactor); + rsi_error_t (*clk_ssi_mst_clk_div)(M4CLK_Type *pCLK, uint32_t divFactor); +#ifndef SLI_SI917 + rsi_error_t (*clk_cci_clk_div)(M4CLK_Type *pCLK, uint32_t divFactor); +#endif + rsi_error_t (*clk_i2s_clk_div)(M4CLK_Type *pCLK, uint32_t divFactor); +#ifndef SLI_SI917 + rsi_error_t (*clk_sd_mem_clk_div)(M4CLK_Type *pCLK, boolean_t u8SwallowEn, uint32_t divFactor); +#endif + rsi_error_t (*clk_usart_clk_div)(M4CLK_Type *pCLK, EN_USART_T EN_USART_T, uint8_t u8FracDivEn, uint32_t divFactor); + uint32_t (*clk_slp_clk_calib_config)(M4CLK_Type *pCLK, uint8_t clkCycles); + rsi_error_t (*clk_gspi_clk_config)(M4CLK_Type *pCLK, GSPI_CLK_SRC_SEL_T clkSel); + rsi_error_t (*clk_slp_clk_config)(M4CLK_Type *pCLK, SLEEP_CLK_SRC_SEL_T clkSrc); + rsi_error_t (*clk_i2c_clk_config)(M4CLK_Type *pCLK, boolean_t clkEnable, EN_I2C_T enI2C); + rsi_error_t (*clk_xtal_clk_config)(uint8_t xtalPin); +#ifndef SLI_SI917 + rsi_error_t (*clk_usb_clk_config)(M4CLK_Type *pCLK, USB_CLK_SRC_SEL_T clkSource, uint16_t divFactor); +#endif + rsi_error_t (*clk_peripheral_clk_enable)(M4CLK_Type *pCLK, PERIPHERALS_CLK_T module, CLK_ENABLE_T clkType); + rsi_error_t (*clk_peripheral_clk_disable)(M4CLK_Type *pCLK, PERIPHERALS_CLK_T module); + void (*clk_config_pll_lock)(boolean_t manual_lock, boolean_t bypass_manual_lock, uint8_t mm_count_limit); + void (*clk_config_pll_ref_clk)(uint8_t ref_clk_src); +#ifdef SLI_SI917B0 + rsi_error_t (*clk_qspi_2_clk_config)(M4CLK_Type *pCLK, + QSPI_CLK_SRC_SEL_T clkSource, + boolean_t swalloEn, + boolean_t OddDivEn, + uint32_t divFactor); +#endif +} ROM_M4SS_CLK_API_T; + +//////////////////////////M4 CLOCKS END/////////////////////// + +///////////////SSI///////////////////////////////// +typedef PRE_PACK struct POST_PACK { + int32_t (*SPI_Initialize)(ARM_SPI_SignalEvent_t cb_event, + const SPI_RESOURCES *spi, + UDMA_RESOURCES *udma, + RSI_UDMA_DESC_T *UDMA_Table, + RSI_UDMA_HANDLE_T *udmaHandle, + uint32_t *mem); + int32_t (*SPI_Uninitialize)(const SPI_RESOURCES *spi, UDMA_RESOURCES *udma); + int32_t (*SPI_PowerControl)(ARM_POWER_STATE state, const SPI_RESOURCES *spi); + int32_t (*SPI_Send)(const void *data, + uint32_t num, + const SPI_RESOURCES *spi, + UDMA_RESOURCES *udma, + UDMA_Channel_Info *chnl_info, + RSI_UDMA_HANDLE_T udmaHandle); + int32_t (*SPI_Receive)(void *data, + uint32_t num, + const SPI_RESOURCES *spi, + UDMA_RESOURCES *udma, + UDMA_Channel_Info *chnl_info, + RSI_UDMA_HANDLE_T udmaHandle); + int32_t (*SPI_Transfer)(const void *data_out, + void *data_in, + uint32_t num, + const SPI_RESOURCES *spi, + UDMA_RESOURCES *udma, + UDMA_Channel_Info *chnl_info, + RSI_UDMA_HANDLE_T udmaHandle); + uint32_t (*SPI_GetDataCount)(const SPI_RESOURCES *spi); +#ifdef SLI_SI917B0 + int32_t (*SPI_Control)(uint32_t control, + uint32_t arg, + const SPI_RESOURCES *spi, + uint32_t base_clock, + uint8_t spi_slavenumber); +#else + int32_t (*SPI_Control)(uint32_t control, uint32_t arg, const SPI_RESOURCES *spi, uint32_t base_clock); +#endif + ARM_SPI_STATUS (*SPI_GetStatus)(const SPI_RESOURCES *spi); + void (*SPI_UDMA_Tx_Event)(uint32_t event, uint8_t dmaCh, SPI_RESOURCES *spi); + void (*SPI_UDMA_Rx_Event)(uint32_t event, uint8_t dmaCh, SPI_RESOURCES *spi); + void (*SPI_IRQHandler)(const SPI_RESOURCES *spi); +} ROM_SSI_API_T; +//////////////////SSI END////////////////////////// + +typedef struct { + const ROM_EGPIO_API_T *pEGPIOROM; /*!< EGPIO driver API function table base address */ + const ROM_TIMERS_API_T *pTIMERSROM; /*!< TIMERS driver API function table base address */ + const ROM_UDMA_API_T *pUDMAROM; /*!< UDMA driver API function table base address */ + const ROM_UDMA_WRAPPER_API_T *pUDMAWRAPPERROM; + const ROM_CT_API_T *pCTROM; /*!< SCT driver API function table base address */ + const ROM_RPDMA_API_T *pRPDMAROM; + const ROM_PWR_API_T *pPWR; + const ROM_M4SS_CLK_API_T *pM4SSCLK; + const ROM_ULPSS_CLK_API_T *pULPSSCLK; + const ROM_QSPI_API_T *pQSPIROM; +#ifndef SLI_SI917B0 + const ROM_EFUSE_API_T *pEFUSEROM; +#endif + const ROM_CRC_API_T *pCRCROM; + const ROM_RNG_API_T *pRNGROM; +#ifndef SLI_SI917B0 + const ROM_MCPWM_API_T *pMCPWMROM; +#endif + const ROM_USART_API_T *pUSARTROM; + const ROM_GSPI_API_T *pGSPIROM; + const ROM_I2S_API_T *pI2SROM; + const ROM_I2C_API_T *pI2CROM; +#ifdef CHIP_9118 + const struct ROM_WL_API_S *pWLROM; +#endif +#ifdef SLI_SI917 + const ROM_SSI_API_T *pSSIROM; +#endif +} RSI_ROM_API_T; + +/*ROM base address */ +#define RSI_ROM_API_BASE_LOC (0x00300100) + +#define RSI_ROM_API ((RSI_ROM_API_T *)RSI_ROM_API_BASE_LOC) +/* Pointer to EGPIO peripheral driver functions in ROM */ +#define ROMAPI_EGPIO_API ((RSI_ROM_API)->pEGPIOROM) + +/* Pointer to Timers peripheral driver functions in ROM */ +#define ROMAPI_TIMER_API ((RSI_ROM_API)->pTIMERSROM) + +/* Pointer to UDMA peripheral driver functions in ROM */ +#define ROMAPI_UDMA_API ((RSI_ROM_API)->pUDMAROM) + +#define ROMAPI_UDMA_WRAPPER_API ((RSI_ROM_API)->pUDMAWRAPPERROM) + +/* Pointer to SCT peripheral driver functions in ROM */ +#define ROMAPI_CT_API ((RSI_ROM_API)->pCTROM) + +/* Pointer to RPDMA peripheral driver functions in ROM */ +#define ROMAPI_GPDMA_API ((RSI_ROM_API)->pRPDMAROM) + +/* Pointer to POWER driver functions in ROM */ +#define ROMAPI_PWR_API ((RSI_ROM_API)->pPWR) + +/* Pointer to M4SS CLOCKS driver functions in ROM */ +#define ROMAPI_M4SS_CLK_API ((RSI_ROM_API)->pM4SSCLK) + +/*ULP clocks*/ +#define ROMAPI_ULPSS_CLK_API ((RSI_ROM_API)->pULPSSCLK) + +/* Pointer to QSPI peripheral driver functions in ROM */ +#define ROMAPI_QSPI_API ((RSI_ROM_API)->pQSPIROM) + +#ifndef SLI_SI917B0 +/* Pointer to EFUSE driver functions in ROM */ +#define ROMAPI_EFUSE_API ((RSI_ROM_API)->pEFUSEROM) +#endif + +/* Pointer to CRC peripheral driver functions in ROM */ +#define ROMAPI_CRC_API ((RSI_ROM_API)->pCRCROM) + +/* Pointer to RNG peripheral driver functions in ROM */ +#define ROMAPI_RNG_API ((RSI_ROM_API)->pRNGROM) + +#ifndef SLI_SI917B0 +/* Pointer to MCPWM peripheral driver functions in ROM */ +#define ROMAPI_MCPWM_API ((RSI_ROM_API)->pMCPWMROM) +#endif + +/* Pointer to USART peripheral driver functions in ROM */ +#define ROMAPI_USART_API ((RSI_ROM_API)->pUSARTROM) + +/* Pointer to GSPI peripheral driver functions in ROM */ +#define ROMAPI_GSPI_API ((RSI_ROM_API)->pGSPIROM) + +/* Pointer to I2S peripheral driver functions in ROM */ +#define ROMAPI_I2S_API ((RSI_ROM_API)->pI2SROM) + +/* Pointer to I2C peripheral driver functions in ROM */ +#define ROMAPI_I2C_API ((RSI_ROM_API)->pI2CROM) + +#ifdef CHIP_9118 +/* Pointer to WIRELESS driver functions in ROM */ +#define ROMAPI_WL ((RSI_ROM_API)->pWLROM) +#endif + +#ifdef SLI_SI917 +/* Pointer to SSI driver functions in ROM */ +#define ROMAPI_SSI_API ((RSI_ROM_API)->pSSIROM) +#endif + +#ifdef __cplusplus +} +#endif + +#endif + +#endif /* __RSI_ROM_TABLE_RS9116_H__ */ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_ulpss_clk.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_ulpss_clk.h new file mode 100644 index 000000000..e50b9e4d8 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_ulpss_clk.h @@ -0,0 +1,667 @@ +/******************************************************************************* +* @file rsi_rom_ulpss_clk.h +* @brief +******************************************************************************* +* # License +* Copyright 2020 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ +/************************************************************************* + * + */ + +// Includes + +#ifndef __RSI_ROM_ULPSS_CLK_H__ +#define __RSI_ROM_ULPSS_CLK_H__ + +#include "rsi_rom_egpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \ingroup RSI_SPECIFIC_DRIVERS + */ + +/** + * \defgroup RSI_CHIP_CLOCK_DRIVERS CLOCK + * @{ + * + */ + +/** + * \defgroup RSI_ULPSS_CLOCK_DRIVERS ULPSS CLOCK + * @{ + * + */ +#include "rsi_ccp_user_config.h" +#include "rsi_packing.h" +#include "rsi_ulpss_clk.h" +#if defined(A11_ROM) +#include "rsi_rom_table_si91x.h" +#else +#include "rsi_rom_table_RS1xxxx.h" +#endif + +/** + * @fn STATIC INLINE rsi_error_t RSI_ULPSS_RefClkConfig(ULPSS_REF_CLK_SEL_T clkSource) + * @brief This API is used to select the ULPSS processor ref clk configuration + * @param[in] clkSource : Enum values of clock source to select as ulp processor ref clock.Please refer #ULPSS_REF_CLK_SEL_T + * @return returns 0 \ref RSI_OK on success ,Error code on failure + */ +STATIC INLINE rsi_error_t RSI_ULPSS_RefClkConfig(ULPSS_REF_CLK_SEL_T clkSource) +{ + return ulpss_ref_clk_config(clkSource); +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_ULPSS_ClockConfig(M4CLK_Type *pCLK, boolean_t clkEnable,uint16_t divFactor,boolean_t oddDivFactor) + * @brief This API is used to select the ULPSS processor clock source when input is soc clk source which is greater than 100MHz + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] clkEnable : is to enable or disable the ulpss_soc clock + * - Enable 1: Enables the clock + * - Disable 0: Disables the clock + * @param[in] divFactor : To divide the clock, ensure that oddDivFactor is 0 then divFactor must be even value or else odd value + * @param[in] oddDivFactor : Selects the type of divider for m4_soc_clk_2ulpss + * - 0 => Clock Divider(even) is selected + * - 1 => Odd Divider is selected + * @return returns 0 \ref RSI_OK on success ,Error code on failure + */ +STATIC INLINE rsi_error_t RSI_ULPSS_ClockConfig(M4CLK_Type *pCLK, + boolean_t clkEnable, + uint16_t divFactor, + boolean_t oddDivFactor) +{ +#if defined(ULPSS_CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_ULPSS_CLK_API->ulpss_clock_config(pCLK, clkEnable, divFactor, oddDivFactor); +#else + return ulpss_clock_config(pCLK, clkEnable, divFactor, oddDivFactor); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_ULPSS_UlpProcClkConfig(ULPCLK_Type *pULPCLK , + ULP_PROC_CLK_SELECT_T clkSource, + uint16_t divFactor,cdDelay delayFn) + * @brief This API is used to configure the ULPSS processor clock source + * @param[in] pULPCLK : Pointer to the ulp clock register instance + * @param[in] clkSource : Enum values of clock source to select as processor clock.Please refer #ULP_PROC_CLK_SELECT_T and refer NOTE + * @param[in] divFactor : To divide the clock + * @param[in] delayFn : delay enable parameter is 1 for enable 0 for not enable. + * @return returns 0 \ref RSI_OK on success ,Error code on failure + * @note + * In order to enable the XTAL CLK source need to configure the NPSS_GPIO pins + * - which can be done through RSI_CLK_XtalClkConfig(uint8_t xtalPin) API i.e we need to call that API first + * - In order to enable the soc CLK source need to configure the Ulpss soc Clk from M4 soc clk + * - please refer RSI_ULPSS_ClockConfig(M4CLK_Type *pCLK,boolean_t clkEnable,uint16_t divFactor,boolean_t oddDivFactor); + */ +STATIC INLINE rsi_error_t RSI_ULPSS_UlpProcClkConfig(ULPCLK_Type *pULPCLK, + ULP_PROC_CLK_SELECT_T clkSource, + uint16_t divFactor, + cdDelay delayFn) +{ + return ulpss_ulp_proc_clk_config(pULPCLK, clkSource, divFactor, delayFn); +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_ULPSS_UlpPeriClkEnable(ULPCLK_Type *pULPCLK , uint32_t u32Flags) + * @brief This API is used to enable different pheriheral clocks in ULPSS + * @param[in] pULPCLK : Pointer to the ulp clock register instance + * @param[in] u32Flags : Ored value of the clock enable bits of particular peripheral + * - \ref Possible values for this parameter are + * - \ref ULPSS_TASS_QUASI_SYNC + * - \ref ULPSS_M4SS_SLV_SEL + * - \ref AUX_SOC_EXT_TRIG_2_SEL + * - \ref AUX_SOC_EXT_TRIG_1_SEL + * - \ref AUX_ULP_EXT_TRIG_2_SEL + * - \ref AUX_ULP_EXT_TRIG_1_SEL + * - \ref TIMER_PCLK_EN + * - \ref EGPIO_PCLK_ENABLE + * - \ref EGPIO_PCLK_DYN_CTRL_DISABLE + * - \ref CLK_ENABLE_ULP_MEMORIES + * - \ref VAD_CLK_EN + * - \ref FIM_CLK_EN + * - \ref REG_ACCESS_SPI_CLK_EN + * - \ref EGPIO_CLK_EN + * - \ref CLK_ENABLE_TIMER + * - \ref VAD_PCLK_ENABLE + * - \ref FIM_PCLK_ENABLE + * - \ref SCLK_ENABLE_UART + * - \ref PCLK_ENABLE_UART + * - \ref SCLK_ENABLE_SSI_MASTER + * - \ref PCLK_ENABLE_SSI_MASTER + * - \ref CLK_ENABLE_I2S + * - \ref PCLK_ENABLE_I2C + * - \ref RELEASE_SOFT_RESET + * - \ref PCM_FSYNC_START + * - \ref PCM_ENABLE + * @return returns 0 \ref RSI_OK on success ,Error code on failure + */ +STATIC INLINE rsi_error_t RSI_ULPSS_UlpPeriClkEnable(ULPCLK_Type *pULPCLK, uint32_t u32Flags) +{ +#if defined(ULPSS_CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_ULPSS_CLK_API->ulpss_ulp_peri_clk_enable(pULPCLK, u32Flags); +#else + return ulpss_ulp_peri_clk_enable(pULPCLK, u32Flags); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_ULPSS_UlpPeriClkDisable(ULPCLK_Type *pULPCLK , uint32_t u32Flags) + * @brief This API is used to disable different peripheral clocks in ULPSS + * @param[in] pULPCLK : Pointer to the ulp clock register instance + * @param[in] u32Flags is to Ored value of the clock enable bits of particular peripheral + * \n Possible values for this parameter are + * - \ref ULPSS_TASS_QUASI_SYNC + * - \ref ULPSS_M4SS_SLV_SEL + * - \ref AUX_SOC_EXT_TRIG_2_SEL + * - \ref AUX_SOC_EXT_TRIG_1_SEL + * - \ref AUX_ULP_EXT_TRIG_2_SEL + * - \ref AUX_ULP_EXT_TRIG_1_SEL + * - \ref TIMER_PCLK_EN + * - \ref EGPIO_PCLK_ENABLE + * - \ref EGPIO_PCLK_DYN_CTRL_DISABLE + * - \ref CLK_ENABLE_ULP_MEMORIES + * - \ref VAD_CLK_EN + * - \ref FIM_CLK_EN + * - \ref REG_ACCESS_SPI_CLK_EN + * - \ref EGPIO_CLK_EN + * - \ref CLK_ENABLE_TIMER + * - \ref VAD_PCLK_ENABLE + * - \ref FIM_PCLK_ENABLE + * - \ref SCLK_ENABLE_UART + * - \ref PCLK_ENABLE_UART + * - \ref SCLK_ENABLE_SSI_MASTER + * - \ref PCLK_ENABLE_SSI_MASTER + * - \ref CLK_ENABLE_I2S + * - \ref PCLK_ENABLE_I2C + * - \ref RELEASE_SOFT_RESET + * - \ref PCM_FSYNC_START + * - \ref PCM_ENABLE + * @return returns 0 \ref RSI_OK on success ,Error code on failure + */ +STATIC INLINE rsi_error_t RSI_ULPSS_UlpPeriClkDisable(ULPCLK_Type *pULPCLK, uint32_t u32Flags) +{ +#if defined(ULPSS_CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_ULPSS_CLK_API->ulpss_ulp_peri_clk_disable(pULPCLK, u32Flags); +#else + return ulpss_ulp_peri_clk_disable(pULPCLK, u32Flags); +#endif +} +/** + * @fn STATIC INLINE rsi_error_t RSI_ULPSS_UlpDynClkEnable(ULPCLK_Type *pULPCLK , uint32_t u32Flags) + * @brief This API is used to enable different peripheral clocks in ULPSS + * @param[in] pULPCLK : Pointer to the ulp clock register instance + * @param[in] u32Flags : Ored value of the clock enable bits of particular peripheral + * \n Possible values for this parameter are + * - \ref ULPSS_TASS_QUASI_SYNC + * - \ref ULPSS_M4SS_SLV_SEL + * - \ref AUX_SOC_EXT_TRIG_2_SEL + * - \ref AUX_SOC_EXT_TRIG_1_SEL + * - \ref AUX_ULP_EXT_TRIG_2_SEL + * - \ref AUX_ULP_EXT_TRIG_1_SEL + * - \ref TIMER_PCLK_EN + * - \ref EGPIO_PCLK_ENABLE + * - \ref EGPIO_PCLK_DYN_CTRL_DISABLE + * - \ref CLK_ENABLE_ULP_MEMORIES + * - \ref VAD_CLK_EN + * - \ref FIM_CLK_EN + * - \ref REG_ACCESS_SPI_CLK_EN + * - \ref EGPIO_CLK_EN + * - \ref CLK_ENABLE_TIMER + * - \ref VAD_PCLK_ENABLE + * - \ref FIM_PCLK_ENABLE + * - \ref SCLK_ENABLE_UART + * - \ref PCLK_ENABLE_UART + * - \ref SCLK_ENABLE_SSI_MASTER + * - \ref PCLK_ENABLE_SSI_MASTER + * - \ref CLK_ENABLE_I2S + * - \ref PCLK_ENABLE_I2C + * - \ref RELEASE_SOFT_RESET + * - \ref PCM_FSYNC_START + * - \ref PCM_ENABLE + * @return returns 0 \ref RSI_OK on success ,Error code on failure + */ +STATIC INLINE rsi_error_t RSI_ULPSS_UlpDynClkEnable(ULPCLK_Type *pULPCLK, uint32_t u32Flags) +{ +#if defined(ULPSS_CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_ULPSS_CLK_API->ulpss_ulp_dyn_clk_enable(pULPCLK, u32Flags); +#else + return ulpss_ulp_dyn_clk_enable(pULPCLK, u32Flags); +#endif +} +/** + * @fn STATIC INLINE rsi_error_t RSI_ULPSS_UlpDynClkDisable(ULPCLK_Type *pULPCLK , uint32_t u32Flags) + * @brief This API is used to disable different peripheral clocks in ULPSS + * @param[in] pULPCLK : Pointer to the ulp clock register instance + * @param[in] u32Flags : is to Ored value of the clock enable bits of particular peripheral + * \n Possible values for this parameter are + * - \ref ULPSS_TASS_QUASI_SYNC + * - \ref ULPSS_M4SS_SLV_SEL + * - \ref AUX_SOC_EXT_TRIG_2_SEL + * - \ref AUX_SOC_EXT_TRIG_1_SEL + * - \ref AUX_ULP_EXT_TRIG_2_SEL + * - \ref AUX_ULP_EXT_TRIG_1_SEL + * - \ref TIMER_PCLK_EN + * - \ref EGPIO_PCLK_ENABLE + * - \ref EGPIO_PCLK_DYN_CTRL_DISABLE + * - \ref CLK_ENABLE_ULP_MEMORIES + * - \ref VAD_CLK_EN + * - \ref FIM_CLK_EN + * - \ref REG_ACCESS_SPI_CLK_EN + * - \ref EGPIO_CLK_EN + * - \ref CLK_ENABLE_TIMER + * - \ref VAD_PCLK_ENABLE + * - \ref FIM_PCLK_ENABLE + * - \ref SCLK_ENABLE_UART + * - \ref PCLK_ENABLE_UART + * - \ref SCLK_ENABLE_SSI_MASTER + * - \ref PCLK_ENABLE_SSI_MASTER + * - \ref CLK_ENABLE_I2S + * - \ref PCLK_ENABLE_I2C + * - \ref RELEASE_SOFT_RESET + * - \ref PCM_FSYNC_START + * - \ref PCM_ENABLE + * @return returns 0 \ref RSI_OK on success ,Error code on failure + */ +STATIC INLINE rsi_error_t RSI_ULPSS_UlpDynClkDisable(ULPCLK_Type *pULPCLK, uint32_t u32Flags) +{ +#if defined(ULPSS_CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_ULPSS_CLK_API->ulpss_ulp_dyn_clk_disable(pULPCLK, u32Flags); +#else + return ulpss_ulp_dyn_clk_disable(pULPCLK, u32Flags); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_ULPSS_UlpSsiClkConfig(ULPCLK_Type *pULPCLK ,CLK_ENABLE_T clkType , + ULP_SSI_CLK_SELECT_T clkSource, + uint16_t divFactor) + * @brief This API is used to configure the SSI clock source + * @param[in] pULPCLK : Pointer to the ulp clock register instance + * @param[in] clkType : To select the clock as dynamic or static clock. See the #CLK_ENABLE_T for more info + * @param[in] clkSource : Value of clock source to select as Ulp SSI clock. Please refer #ULP_SSI_CLK_SELECT_T for more info + * - 0: \ref_clk (output of dynamic clock mux for different possible ref_clk sources) + * - 1: \ref ulp_32khz_ro_clk + * - 2: \ref ulp_32khz_rc_clk + * - 3: \ref ulp_32khz_xtal_clk #refer NOTE + * - 4: \ref ulp_32mhz_rc_clk + * - 5: \ref ulp_20mhz_ro_clk + * - 6: \ref soc_clk #refer NOTE + * @param[in] divFactor : To divide the clock + * @return returns 0 \ref RSI_OK on success ,Error code on failure + * @note There are two \ref XTAL Clk sources one is Internal and external \ref XTAL clk source. In order to enable the external XTAL clk source need to configure the \ref NPSS_GPIO pins + * - which can be done through RSI_CLK_XtalClkConfig(uint8_t xtalPin) API i.e we need to call that API first + * - In order to enable the soc CLK source need to configure the Ulpss soc Clk from M4 soc clk + * - please refer \ref RSI_ULPSS_ClockConfig(M4CLK_Type *pCLK,boolean_t clkEnable,uint16_t divFactor,boolean_t oddDivFactor); + */ + +STATIC INLINE rsi_error_t RSI_ULPSS_UlpSsiClkConfig(ULPCLK_Type *pULPCLK, + CLK_ENABLE_T clkType, + ULP_SSI_CLK_SELECT_T clkSource, + uint16_t divFactor) +{ +#if defined(ULPSS_CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_ULPSS_CLK_API->ulpss_ulp_ssi_clk_config(pULPCLK, clkType, clkSource, divFactor); +#else + return ulpss_ulp_ssi_clk_config(pULPCLK, clkType, clkSource, divFactor); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_ULPSS_UlpI2sClkConfig(ULPCLK_Type *pULPCLK, + ULP_I2S_CLK_SELECT_T clkSource , + uint16_t divFactor) + * @brief This API is used to configure the I2S clock source + * @param[in] pULPCLK : Pointer to the ulp clock register instance + * @param[in] clkSource : Value of clock source to select as I2S clock. Please refer #ULP_SSI_CLK_SELECT_T for more info + * - 0: \ref ref_clk (output of dynamic clock mux for different possible ref_clk sources) + * - 1: \ref ulp_32khz_ro_clk + * - 2: \ref ulp_32khz_rc_clk + * - 3: \ref ulp_32khz_xtal_clk #refer NOTE + * - 4: \ref ulp_32mhz_rc_clk + * - 5: \ref ulp_20mhz_ro_clk + * - 6: \ref soc_clk #refer NOTE + * - 7: \ref ulp_doubler_clk + * - 8: \ref I2S PLL + * @param[in] divFactor : To divide the clock + * @return returns 0 \ref RSI_OK on success ,Error code on failure + * @note There are two XTAL Clk sources one is Internal and external XTAL clk source. In order to enable the external XTAL clk source need to configure the NPSS_GPIO pins + * - which can be done through RSI_CLK_XtalClkConfig(uint8_t xtalPin) API i.e we need to call that API first + * - In order to enable the soc CLK source need to configure the Ulpss soc Clk from M4 soc clk + * - please refer RSI_ULPSS_ClockConfig(M4CLK_Type *pCLK,boolean_t clkEnable,uint16_t divFactor,boolean_t oddDivFactor); + */ +STATIC INLINE rsi_error_t RSI_ULPSS_UlpI2sClkConfig(ULPCLK_Type *pULPCLK, + ULP_I2S_CLK_SELECT_T clkSource, + uint16_t divFactor) +{ +#if defined(ULPSS_CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_ULPSS_CLK_API->ulpss_ulp_i2s_clk_config(pULPCLK, clkSource, divFactor); +#else + return ulpss_ulp_i2s_clk_config(pULPCLK, clkSource, divFactor); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_ULPSS_UlpUartClkConfig(ULPCLK_Type *pULPCLK,CLK_ENABLE_T clkType, + boolean_t bFrClkSel,ULP_UART_CLK_SELECT_T clkSource , + uint16_t divFactor) + * @brief This API is used to configure the UART clock source + * @param[in] pULPCLK : Pointer to the ulp clock register instance + * @param[in] clkType : To select the clock as dynamic or static clock. See the #CLK_ENABLE_T for more info + * @param[in] bFrClkSel : To enable or disable ulp uart clk selection + * - 1: Fractional Divider output is selected + * - 0: Swallow Divider output is selected + * @param[in] clkSource : Value of clock source to select as processor clock + * - 0: \ref ref_clk (output of dynamic clock mux for different possible ref_clk sources) + * - 1: \ref ulp_32khz_ro_clk + * - 2: \ref ulp_32khz_rc_clk + * - 3: \ref ulp_32khz_xtal_clk #refer NOTE + * - 4: \ref ulp_32mhz_rc_clk + * - 5: \ref ulp_20mhz_ro_clk + * - 6: \ref soc_clk #refer NOTE + * @param[in] divFactor : To divide the clock + * @return returns 0 \ref RSI_OK on success ,Error code on failure + * @note There are two XTAL Clk sources one is Internal and external XTAL clk source. In order to enable the external XTAL clk source need to configure the NPSS_GPIO pins + * - which can be done through RSI_CLK_XtalClkConfig(uint8_t xtalPin) API i.e we need to call that API first + * - In order to enable the soc CLK source need to configure the Ulpss soc Clk from M4 soc clk + * - please refer RSI_ULPSS_ClockConfig(M4CLK_Type *pCLK,boolean_t clkEnable,uint16_t divFactor,boolean_t oddDivFactor); + */ +STATIC INLINE rsi_error_t RSI_ULPSS_UlpUartClkConfig(ULPCLK_Type *pULPCLK, + CLK_ENABLE_T clkType, + boolean_t bFrClkSel, + ULP_UART_CLK_SELECT_T clkSource, + uint16_t divFactor) +{ +#if defined(ULPSS_CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_ULPSS_CLK_API->ulpss_ulp_uar_clk_config(pULPCLK, clkType, bFrClkSel, clkSource, divFactor); +#else + return ulpss_ulp_uar_clk_config(pULPCLK, clkType, bFrClkSel, clkSource, divFactor); +#endif +} +/** + * @fn STATIC INLINE rsi_error_t RSI_ULPSS_TimerClkConfig(ULPCLK_Type *pULPCLK ,CLK_ENABLE_T clkType, + boolean_t bTmrSync ,ULP_TIMER_CLK_SELECT_T clkSource, + uint8_t skipSwitchTime) + * @brief This API is used to configure the timer clock source + * @param[in] pULPCLK : Pointer to the ulp clock register instance + * @param[in] clkType : To select the clock as dynamic or static clock. See the #CLK_ENABLE_T for more info + * @param[in] bTmrSync : To enable Ulp timer in synchronous mode to ULPSS pclk + * - 1: Enables + * - 0: Disables + * @param[in] clkSource : Value of clock source to select as Timer clock. Please refer #ULP_TIMER_CLK_SELECT_T for possible values + * - 0: \ref ref_clk (output of dynamic clock mux for different possible ref_clk sources) + * - 1: \ref ulp_32khz_ro_clk + * - 2: \ref ulp_32khz_rc_clk + * - 3: \ref ulp_32khz_xtal_clk #refer NOTE + * - 4: \ref ulp_32mhz_rc_clk + * - 5: \ref ulp_20mhz_ro_clk + * - 6: \ref soc_clk #refer NOTE + * - 7: \ref ulp_doubler_clk + * @param[in] skipSwitchTime : To skip the switching of timer clk. + * - 1 : Wait for switching timer clk + * - 0 : Skip waiting for switching timer clk + * @return returns 0 \ref RSI_OK on success ,Error code on failure + * @note There are two XTAL Clk sources one is Internal and external XTAL clk source. In order to enable the external XTAL clk source need to configure the NPSS_GPIO pins + * - which can be done through RSI_CLK_XtalClkConfig(uint8_t xtalPin) API i.e we need to call that API first + * - In order to enable the soc CLK source need to configure the Ulpss soc Clk from M4 soc clk + * - please refer RSI_ULPSS_ClockConfig(M4CLK_Type *pCLK,boolean_t clkEnable,uint16_t divFactor,boolean_t oddDivFactor); + */ +STATIC INLINE rsi_error_t RSI_ULPSS_TimerClkConfig(ULPCLK_Type *pULPCLK, + CLK_ENABLE_T clkType, + boolean_t bTmrSync, + ULP_TIMER_CLK_SELECT_T clkSource, + uint8_t skipSwitchTime) +{ +#if defined(ULPSS_CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_ULPSS_CLK_API->ulpss_time_clk_config(pULPCLK, clkType, bTmrSync, clkSource, skipSwitchTime); +#else + return ulpss_time_clk_config(pULPCLK, clkType, bTmrSync, clkSource, skipSwitchTime); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_ULPSS_TimerClkDisable(ULPCLK_Type *pULPCLK ) + * @brief This API is used to disable the timer clock source + * @param[in] pULPCLK : Pointer to the ulp clock register instance + * @return returns 0 \ref RSI_OK on success ,Error code on failure + */ +STATIC INLINE rsi_error_t RSI_ULPSS_TimerClkDisable(ULPCLK_Type *pULPCLK) +{ +#if defined(CHIP_9118) && defined(A11_ROM) && defined(ULPSS_CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_ULPSS_CLK_API->ulpss_time_clk_disable(pULPCLK); +#else + return ulpss_time_clk_disable(pULPCLK); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_ULPSS_AuxClkConfig(ULPCLK_Type *pULPCLK , + CLK_ENABLE_T clkType, + ULP_AUX_CLK_SELECT_T clkSource + ) + * @brief This API is used to configure the AUX clock source + * @param[in] pULPCLK : Pointer to the ulp clock register instance + * @param[in] clkType : To select the clock as dynamic or static clock. See the #CLK_ENABLE_T for more info + * @param[in] clkSource : Value of clock source to select as AUX clock. Please refer #ULP_AUX_CLK_SELECT_T for more info + * - 0: \ref ref_clk (output of dynamic clock mux for different possible ref_clk sources) + * - 1: \ref ulp_32khz_ro_clk + * - 2: \ref ulp_32khz_rc_clk + * - 3: \ref ulp_32khz_xtal_clk #refer NOTE + * - 4: \ref ulp_32mhz_rc_clk + * - 5: \ref ulp_20mhz_ro_clk + * - 6: \ref soc_clk #refer NOTE + * - 7: \ref ulp_doubler_clk + * - 8: \ref I2S PLL + * @return returns 0 \ref RSI_OK on success ,Error code on failure + * @note - There are two XTAL Clk sources one is Internal and external XTAL clk source. In order to enable the external XTAL clk source need to configure the NPSS_GPIO pins + * - which can be done through RSI_CLK_XtalClkConfig(uint8_t xtalPin) API i.e we need to call that API first + * - In order to enable the soc CLK source need to configure the Ulpss soc Clk from M4 soc clk + * - please refer RSI_ULPSS_ClockConfig(M4CLK_Type *pCLK,boolean_t clkEnable,uint16_t divFactor,boolean_t oddDivFactor); + */ +STATIC INLINE rsi_error_t RSI_ULPSS_AuxClkConfig(ULPCLK_Type *pULPCLK, + CLK_ENABLE_T clkType, + ULP_AUX_CLK_SELECT_T clkSource) +{ +#if defined(ULPSS_CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_ULPSS_CLK_API->ulpss_aux_clk_config(pULPCLK, clkType, clkSource); +#else + return ulpss_aux_clk_config(pULPCLK, clkType, clkSource); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_ULPSS_VadClkConfig(ULPCLK_Type *pULPCLK , + ULP_VAD_CLK_SELECT_T clkSource , + ULP_VAD_FCLK_SELECT_T FclkSource , + uint16_t divFactor) + * @brief This API is used to configure the VAD clock source + * @param[in] pULPCLK : Pointer to the ulp clock register instance + * @param[in] clkSource : Value of clock source to select as vad clock. Please refer #ULP_VAD_CLK_SELECT_T for more info + * - 0: \ref ulp_32khz_ro_clk + * - 1: \ref ulp_32khz_rc_clk + * - 2: \ref ulp_32khz_xtal_clk #refer NOTE + * \n NOTE: In order to enable the XTAL CLK source need to configure the NPSS_GPIO pins + * \n which can be done through RSI_CLK_XtalClkConfig(uint8_t xtalPin) API i.e we need to call that API first + * @param[in] FclkSource : Ulp vad Fast clock select. Please refer #ULP_VAD_FCLK_SELECT_T for more info + * - 0: ulpss processor clock #refer NOTE + * - 1: \ref ref_clk (output of dynamic clock mux for different possible ref_clk sources) + * - 2: \ref ulp_32mhz_rc_clk + * - 3: \ref ulp_20mhz_ro_clk + * - 4: \ref soc_clk #refer NOTE + * @param[in] divFactor : To divide the clock + * @return returns 0 \ref RSI_OK on success ,Error code on failure + * @note - There are two XTAL Clk sources one is Internal and external XTAL clk source. In order to enable the external XTAL clk source need to configure the NPSS_GPIO pins + * - which can be done through RSI_CLK_XtalClkConfig(uint8_t xtalPin) API i.e we need to call that API first + * - In order to enable the soc CLK source need to configure the Ulpss soc Clk from M4 soc clk + * - please refer RSI_ULPSS_ClockConfig(M4CLK_Type *pCLK,boolean_t clkEnable,uint16_t divFactor,boolean_t oddDivFactor); + * - In order to enable the ulpss processor clock source need to configure the + * - RSI_ULPSS_UlpProcClkConfig(ULPCLK_Type *pULPCLK ,boolean_t clkEnable,uint8_t clkSource,uint16_t divFactor,delayMs cbDelay ) + */ +STATIC INLINE rsi_error_t RSI_ULPSS_VadClkConfig(ULPCLK_Type *pULPCLK, + ULP_VAD_CLK_SELECT_T clkSource, + ULP_VAD_FCLK_SELECT_T FclkSource, + uint16_t divFactor) +{ +#if defined(ULPSS_CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_ULPSS_CLK_API->ulpss_vad_clk_config(pULPCLK, clkSource, FclkSource, divFactor); +#else + return ulpss_vad_clk_config(pULPCLK, clkSource, FclkSource, divFactor); +#endif +} +/** + * @fn STATIC INLINE rsi_error_t RSI_ULPSS_TouchClkConfig(ULPCLK_Type *pULPCLK ,ULP_TOUCH_CLK_SELECT_T clkSource , + uint16_t divFactor ) + * @brief This API is used to configure the Touch clock source + * @param[in] pULPCLK : Pointer to the ulp clock register instance + * @param[in] clkSource : Value of clock source to select as Touch clock. Please refer #ULP_TOUCH_CLK_SELECT_T for more info. + * - 0: \ref ref_clk (output of dynamic clock mux for different possible ref_clk sources) + * - 1: \ref ulp_32khz_ro_clk + * - 2: \ref ulp_32khz_rc_clk + * - 3: \ref ulp_32khz_xtal_clk #refer NOTE + * - 4: \ref ulp_32mhz_rc_clk + * - 5: \ref ulp_20mhz_ro_clk + * - 6: \ref soc_clk #refer NOTE + * @param[in] divFactor : To divide the clock + * @return returns 0 \ref RSI_OK on success ,Error code on failure + * @note There are two XTAL Clk sources one is Internal and external XTAL clk source. In order to enable the external XTAL clk source need to configure the NPSS_GPIO pins + * - which can be done through RSI_CLK_XtalClkConfig(uint8_t xtalPin) API i.e we need to call that API first + * - In order to enable the soc CLK source need to configure the Ulpss soc Clk from M4 soc clk + * - please refer RSI_ULPSS_ClockConfig(M4CLK_Type *pCLK,boolean_t clkEnable,uint16_t divFactor,boolean_t oddDivFactor); + */ +STATIC INLINE rsi_error_t RSI_ULPSS_TouchClkConfig(ULPCLK_Type *pULPCLK, + ULP_TOUCH_CLK_SELECT_T clkSource, + uint16_t divFactor) +{ +#if defined(ULPSS_CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_ULPSS_CLK_API->ulpss_touch_clk_config(pULPCLK, clkSource, divFactor); +#else + return ulpss_touch_clk_config(pULPCLK, clkSource, divFactor); +#endif +} +/** + * @fn STATIC INLINE rsi_error_t RSI_ULPSS_SlpSensorClkConfig(ULPCLK_Type *pULPCLK , boolean_t clkEnable ,uint32_t divFactor) + * @brief This API is used to configure the sleep sensor clock source + * @param[in] pULPCLK : Pointer to the ulp clock register instance + * @param[in] clkEnable : To enable or disable the sleep sensor clock + * - Enable 1: Enables the clock + * - Disable 0: Disables the clock + * @param[in] divFactor : To divide the clock + * @return returns 0 \ref RSI_OK on success ,Error code on failure + * @note In order to enable the XTAL CLK source need to configure the NPSS_GPIO pins + * - which can be done through RSI_CLK_XtalClkConfig(uint8_t xtalPin) API i.e we need to call that API first + */ +STATIC INLINE rsi_error_t RSI_ULPSS_SlpSensorClkConfig(ULPCLK_Type *pULPCLK, boolean_t clkEnable, uint32_t divFactor) +{ +#if defined(ULPSS_CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_ULPSS_CLK_API->ulpss_slp_sensor_clk_config(pULPCLK, clkEnable, divFactor); +#else + return ulpss_slp_sensor_clk_config(pULPCLK, clkEnable, divFactor); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_ULPSS_PeripheralEnable(ULPCLK_Type *pULPCLK, + ULPPERIPHERALS_CLK_T module,CLK_ENABLE_T clkType) + * @brief This API is used to enable the particular ULP peripherial Clock + * @param[in] pULPCLK : Pointer to the ulp clock register instance + * @param[in] module : To select particular ulp pheripheral. See \ref ULPPERIPHERALS_ENABLE_T for more info. + * @param[in] clkType :To select the clock as dynamic or static clock. See the #CLK_ENABLE_T for more info + * @return returns 0 \ref RSI_OK on success ,Error code on failure + */ +STATIC INLINE rsi_error_t RSI_ULPSS_PeripheralEnable(ULPCLK_Type *pULPCLK, + ULPPERIPHERALS_CLK_T module, + CLK_ENABLE_T clkType) +{ +#if defined(ULPSS_CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_ULPSS_CLK_API->ulpss_peripheral_enable(pULPCLK, module, clkType); +#else + return ulpss_peripheral_enable(pULPCLK, module, clkType); +#endif +} +/** + * @fn STATIC INLINE rsi_error_t RSI_ULPSS_PeripheralDisable(ULPCLK_Type *pULPCLK, ULPPERIPHERALS_CLK_T module) + * @brief This API is used to Disable the particular ULP peripherial Clock + * @param[in] pULPCLK : Pointer to the ulp clock register instance + * @param[in] module : To select particular ulp pheripheral. \ref ULPPERIPHERALS_DISABLE_T for more info. + * @return returns 0 \ref RSI_OK on success ,Error code on failure + */ +STATIC INLINE rsi_error_t RSI_ULPSS_PeripheralDisable(ULPCLK_Type *pULPCLK, ULPPERIPHERALS_CLK_T module) +{ +#if defined(ULPSS_CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_ULPSS_CLK_API->ulpss_peripheral_disable(pULPCLK, module); +#else + return ulpss_peripheral_disable(pULPCLK, module); +#endif +} + +rsi_error_t RSI_ULPSS_RefClkConfig(ULPSS_REF_CLK_SEL_T clkSource); + +rsi_error_t RSI_ULPSS_ClockConfig(M4CLK_Type *pCLK, boolean_t clkEnable, uint16_t divFactor, boolean_t oddDivFactor); + +rsi_error_t RSI_ULPSS_UlpProcClkConfig(ULPCLK_Type *pULPCLK, + ULP_PROC_CLK_SELECT_T clkSource, + uint16_t divFactor, + cdDelay delayFn); + +rsi_error_t RSI_ULPSS_UlpPeriClkEnable(ULPCLK_Type *pULPCLK, uint32_t u32Flags); + +rsi_error_t RSI_ULPSS_UlpPeriClkDisable(ULPCLK_Type *pULPCLK, uint32_t u32Flags); + +rsi_error_t RSI_ULPSS_UlpDynClkEnable(ULPCLK_Type *pULPCLK, uint32_t u32Flags); + +rsi_error_t RSI_ULPSS_UlpDynClkDisable(ULPCLK_Type *pULPCLK, uint32_t u32Flags); + +rsi_error_t RSI_ULPSS_UlpSsiClkConfig(ULPCLK_Type *pULPCLK, + CLK_ENABLE_T clkType, + ULP_SSI_CLK_SELECT_T clkSource, + uint16_t divFactor); + +rsi_error_t RSI_ULPSS_UlpI2sClkConfig(ULPCLK_Type *pULPCLK, ULP_I2S_CLK_SELECT_T clkSource, uint16_t divFactor); + +rsi_error_t RSI_ULPSS_UlpUartClkConfig(ULPCLK_Type *pULPCLK, + CLK_ENABLE_T clkType, + boolean_t bFrClkSel, + ULP_UART_CLK_SELECT_T clkSource, + uint16_t divFactor); + +rsi_error_t RSI_ULPSS_TimerClkConfig(ULPCLK_Type *pULPCLK, + CLK_ENABLE_T clkType, + boolean_t bTmrSync, + ULP_TIMER_CLK_SELECT_T clkSource, + uint8_t skipSwitchTime); + +rsi_error_t RSI_ULPSS_AuxClkConfig(ULPCLK_Type *pULPCLK, CLK_ENABLE_T clkType, ULP_AUX_CLK_SELECT_T clkSource); + +rsi_error_t RSI_ULPSS_VadClkConfig(ULPCLK_Type *pULPCLK, + ULP_VAD_CLK_SELECT_T clkSource, + ULP_VAD_FCLK_SELECT_T FclkSource, + uint16_t divFactor); + +rsi_error_t RSI_ULPSS_TouchClkConfig(ULPCLK_Type *pULPCLK, ULP_TOUCH_CLK_SELECT_T clkSource, uint16_t divFactor); + +rsi_error_t RSI_ULPSS_SlpSensorClkConfig(ULPCLK_Type *pULPCLK, boolean_t clkEnable, uint32_t divFactor); + +rsi_error_t RSI_ULPSS_PeripheralEnable(ULPCLK_Type *pULPCLK, ULPPERIPHERALS_CLK_T module, CLK_ENABLE_T clkType); + +rsi_error_t RSI_ULPSS_PeripheralDisable(ULPCLK_Type *pULPCLK, ULPPERIPHERALS_CLK_T module); + +#ifdef __cplusplus +} +#endif + +#endif /*__RSI_ROM_ULPSS_CLK_H__*/ + +/*@} end of RSI_ULPSS_CLOCK_DRIVERS */ + +/* @} end ofRSI_CHIP_CLOCK_DRIVERS */ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_ipmu.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_ipmu.h new file mode 100644 index 000000000..6394456d3 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_ipmu.h @@ -0,0 +1,817 @@ +/******************************************************************************* +* @file rsi_ipmu.h +* @brief +******************************************************************************* +* # License +* Copyright 2020 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +/** + * Includes + */ +#ifndef __RSI_IPMU_H__ +#define __RSI_IPMU_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#define AT_EFUSE_DATA_1P19 +#include "rsi_ccp_common.h" +#include "rsi_error.h" + +/****************************************************** + * * Macros + * ******************************************************/ +#define RET_LDO_VOL_DECREASE 1 +#define RET_LDO_TRIM_VALUE_CHECK 2 + +#define REG_GSPI_BASE 0x24050000 +#define NPSS_BASE_ADDR 0x24048000 +#define NPSS_NWP_BASE_ADDR 0x41300000 +#define MCURET_BOOTSTATUS (volatile uint32_t *)(NPSS_BASE_ADDR + 0x604) +#define MCU_BBFF_STORAGE1_ADDR (volatile uint32_t *)(NPSS_NWP_BASE_ADDR + 0x580) +#define TA_MANF_DATA_BASE_ADDR 0x04000000 +#define MCU_MANF_DATA_BASE_ADDR 0x08000000 +#define TA_FLASH 1 + +/*IPMU power gates */ +#define CMP_NPSS_PG_ENB BIT(16) /*Power gate enable for BOD CORE*/ +#define ULP_ANG_CLKS_PG_ENB BIT(15) /*Power gate enable for CLKS CORE*/ +#define ULP_ANG_PWRSUPPLY_PG_ENB BIT(14) /*Power gate enable for BG SPI*/ +#define WURX_PG_ENB BIT(13) /*Power gate enable for WURX*/ +#define WURX_CORR_PG_ENB BIT(12) /*Power gate enable for WURX CORRELATION BLOCK*/ +#define AUXADC_PG_ENB BIT(11) /*Power gate enable for AUXADC*/ +#define AUXADC_BYPASS_ISO_GEN BIT(10) /*power gate bypass for AUXADC*/ +#define AUXADC_ISOLATION_ENABLE BIT(9) /*power gate isolation for AUXADC*/ +#define AUXDAC_PG_ENB BIT(8) /*Power gate enable for AUXDAC*/ +#define AUXDAC_BYPASS_ISO_GEN BIT(7) /*power gate bypass for AUXDAC*/ +#define AUXDAC_ISOLATION_ENABLE BIT(6) /*power gate isolation for AUXDAC*/ +#define AUX_SUPPLY_ISOLATION_ENABLE BIT(5) /*Given to analog peripherals indicating the supply state*/ +#define PMU_ANA_BYPASS_PWRGATE_EN_N BIT(4) /*To ON or OFF analog blocks in PMU when pwr manager is bypassed*/ +#define PMU_SPI_BYPASS_ISO_GEN BIT(3) /*Bypass power manager for PMU_SPI*/ +#define PMU_SPI_ISOLATION_ENABLE BIT(2) /*Bypass isoaltion enable signal for PMU_SPI isoaltion cells*/ +#define PMU_BUCK_BYPASS_ISO_GEN BIT(1) /*Bypass power manager for PMU BUCK*/ +#define PMU_BUCK_BYPASS_ISOLATION_ENABLE BIT(0) /*Bypass isoaltion enable signal for PMU_BUCK isoaltion cells*/ + +/*IPMU configuration defines*/ +#define LATCH_TOP_SPI BIT(4) +#define LATCH_TRANSPARENT_HF BIT(3) +#define LATCH_TRANSPARENT_LF BIT(2) + +/*BG_SCDC_PROG_REG_1 defines*/ +#define REF_SEL_LP_DCDC 0xFFFFFC7F + +/*Registers */ +#define BG_SCDC_PROG_REG_1 0x127 +#define SELECT_BG_CLK 0x144 +#define BG_SCDC_PROG_REG_2 0x128 +//#define WURX_CORR_CALIB_REG 0x088 +#define POWERGATE_REG_WRITE 0x142 +//#define ULPCLKS_REFCLK_REG 0x106 +//#define WURX_CORR_CALIB_REG 0x088 + +#define GSPI_CTRL_REG1 *(volatile uint32_t *)(REG_GSPI_BASE + 0x02) +#define SPI_ACTIVE BIT(8) + +#define POSITION_BITS_MASK 0x1F +#define LSB_POSITION 22 +#define MSB_POSITION 27 +#define MAX_BIT_LEN 22 + +#define ULPCLKS_32KRC_CLK_REG_ADDR 0x103 + +#define ENABLE_CALIB_DOMAIN 0x005200 +#define SELECT_RO_CALIB 0x002310 +#define TRIM_VALUE_BITS 0x0003f800 +#define MASK_TRIM_VALUE_WRITE_BITS 0x1FC000 +#define ULPCLKS_TRIM_SEL_REG_DEFAULT 0x005a14 + +#define MAX_RESP_BUF_FOR_IAP 3 + +#define BASE_OFFSET_BB_RF_IN_FLASH 424 + +#define PMU_SPI_BASE_ADDR 0x24050000 + +//! PMU +#define PMU_SPI_DIRECT_ACCESS(_x) *(volatile uint32_t *)(PMU_SPI_BASE_ADDR + 0x8000 + ((_x) << 2)) +//! IPMU +#define PMU_DIRECT_ACCESS(_x) *(volatile uint32_t *)(PMU_SPI_BASE_ADDR + 0xA000 + ((_x) << 2)) +#define PMU_SPI 1 + +#define RC_CLK_MODE 1 + +#define XTAL_SEL 1 + +#define TS_SLOPE_SET_OFFSET 0x04 +#define PMU_1P3_CTRL_REG_OFFSET 0x1D0 +#define PMU_PFM_REG_OFFSET 0x1D1 +#define PMU_ADC_REG_OFFSET 0x1D2 +#define PMU_PID_REG1_OFFSET 0x1D3 +#define PMU_PTAT_REG_OFFSET 0x1D5 +#define PMU_LDO_REG_OFFSET 0x1D6 +#define PMU_PWRTRAIN_REG_OFFSET 0x1D8 +#define PMU_TESTMUX_REG1_OFFSET 0x1D9 +#define PMU_TEST_MODES_OFFSET 0x1DA +#define SPARE_REG_1_OFFSET 0x1DC +#define SPARE_REG_2_OFFSET 0x1DD +#define BYPASS_CURR_CTRL_REG_OFFSET 0x1DE +#define SPARE_REG_3_OFFSET 0x1DF + +#ifdef CHIP_9118 +//FLASH OFFSET +#define __CALIB_DATA_OFFSET_ 1024 +#define IPMU_VALUES_OFFSET (__CALIB_DATA_OFFSET_ + 168) +#define DUAL_FLASH_IPMU_VALUES_OFFSET MCU_MANF_DATA_BASE_ADDR +#endif + +#ifdef SLI_SI917 +#if (((defined SLI_SI917) || (defined CHIP_917_6x6)) && (defined SLI_SI917B0)) +#ifdef SLI_SI91X_MCU_4MB_LITE_IMAGE +#define PACKAGE_TYPE_VALUES_OFFSET_COMMON_FLASH 0x8160292 +#define SILICON_REV_VALUES_OFFSET_COMMON_FLASH 0x8160293 +#define COMMON_FLASH_IPMU_VALUES_OFFSET 0x8160258 +#else +#define PACKAGE_TYPE_VALUES_OFFSET_COMMON_FLASH 0x81F0292 +#define SILICON_REV_VALUES_OFFSET_COMMON_FLASH 0x81F0293 +#define COMMON_FLASH_IPMU_VALUES_OFFSET 0x81F0258 +#endif +#define PACKAGE_TYPE_VALUES_OFFSET_DUAL_FLASH 0x800059B +#define SILICON_REV_VALUES_OFFSET_DUAL_FLASH 0x800059C +#define DUAL_FLASH_IPMU_VALUES_OFFSET 0x8000561 +#endif +#if ((defined SLI_SI917) && (!(defined SLI_SI917B0))) +#define PACKAGE_TYPE_VALUES_OFFSET_COMMON_FLASH 0x82001DE +#define SILICON_REV_VALUES_OFFSET_COMMON_FLASH 0x82001DF +#define COMMON_FLASH_IPMU_VALUES_OFFSET 0x82001A4 +#define COMMON_FLASH_IPMU_VALUES ((efuse_ipmu_t *)(COMMON_FLASH_IPMU_VALUES_OFFSET)) + +#define PACKAGE_TYPE_VALUES_OFFSET_DUAL_FLASH 0x80004E0 +#define SILICON_REV_VALUES_OFFSET_DUAL_FLASH 0x80004E1 +#define DUAL_FLASH_IPMU_VALUES_OFFSET 0x80004A6 +#define DUAL_FLASH_IPMU_VALUES ((efuse_ipmu_t *)(DUAL_FLASH_IPMU_VALUES_OFFSET)) +#endif +#define IPMU_VALUES_OFFSET 0 +#endif +#define HP_LDO_MODE 1 +#define SCDC_MODE 0 +#ifdef ENABLE_1P8V +#define IPMU_MODE_VALUE HP_LDO_MODE +#else +#define IPMU_MODE_VALUE SCDC_MODE +#endif + +#ifdef SLI_SI91X_MCU_COMMON_FLASH_MODE +#define MANF_DATA_BASE_ADDR COMMON_FLASH_IPMU_VALUES_OFFSET +#else +#define MANF_DATA_BASE_ADDR DUAL_FLASH_IPMU_VALUES_OFFSET +#endif + +/* After changes */ +#define MAGIC_WORD 0x5a + +#define NWP_AHB_ADDR 0x41300000 +#define ULP_TASS_MISC_CONFIG_REG 0x24041400 +#define AUX_BASE_ADDR 0x24043800 +#define TEMP_SENSOR_BASE_ADDRESS 0x24048500 +#define TS_NOMINAL_SETTINGS_OFFSET 0x08 +#define DIRECT 2 + +#define MASK_BITS(A, B) (((1U << A) - 1) << B) +#define ULP_SPI 0 +#define ULPCLKS_DOUBLER_XTAL_REG_OFFSET 0x101 +#define ULPCLKS_32KRO_CLK_REG_OFFSET 0x102 +#define ULPCLKS_32KRC_CLK_REG_OFFSET 0x103 +#define ULPCLKS_32MRC_CLK_REG_OFFSET 0x104 +#define ULPCLKS_HF_RO_CLK_REG_OFFSET 0x105 +#define ULPCLKS_REFCLK_REG_ADDR 0x106 +#define ULPCLKS_TRIM_SEL_REG_ADDR 0x107 +#define ULPCLKS_CALIB_REG_ADDR 0x10A +#define ULPCLKS_CALIB_REF_REG 0x10B +#define ULPCLKS_CALIB_DONE_REG_ADDR 0x10C +#define ULPCLKS_32KXTAL_CLK_REG_OFFSET 0x10E +#define BG_SCDC_PROG_REG_1_OFFSET 0x127 +#define iPMU_SPARE_REG1_OFFSET 0x140 +#ifdef SLI_SI917 +#define BG_SCDC_PROG_REG_3_ADDR 0x12B +#endif + +#define HF_RC_CLK_MODE 1 +#define MCU_PWR_CTRL_BASE_ADDR 0x24048400 +#define MCU_PMU_LDO_CTRL_CLEAR_REG_1 *(volatile uint32 *)(MCU_PWR_CTRL_BASE_ADDR + 0x6C) +#define TEMP_SENSOR_BASE_ADDRESS 0x24048500 +#define MCU_FSM_BASE_ADDRESS 0x24048100 + +//! ULP SPI (0x2405A000) +#define ULPCLKS_ADAPTIVE_REG_OFFSET 0x100 +#define ULPCLKS_DOUBLER_XTAL_REG_OFFSET 0x101 +#define ULPCLKS_32KRO_CLK_REG_OFFSET 0x102 +#define ULPCLKS_32KRC_CLK_REG_OFFSET 0x103 +#define ULPCLKS_32MRC_CLK_REG_OFFSET 0x104 +#define ULPCLKS_HF_RO_CLK_REG_OFFSET 0x105 +#define ULPCLKS_REF_CLK_REG_OFFSET 0x106 +#define ULPCLKS_TRIM_SEL_REG_OFFSET 0x107 +#define ULPCLKS_32KXTAL_CLK_REG_OFFSET 0x10E +#define BG_SLEEP_TIMER_REG_OFFSET 0x125 +#define SCDC_CTRL_REG_0_OFFSET 0x126 +#define BG_SCDC_PROG_REG_1_OFFSET 0x127 +#define BG_SCDC_PROG_REG_2_OFFSET 0x128 +#define BG_LDO_REG_OFFSET 0x129 +#define BG_SCDC_READ_BACK_OFFSET 0x12A +#define BG_BLACKOUT_REG_OFFSET 0x12B +#define iPMU_SPARE_REG1_OFFSET 0x140 +#define iPMU_SPARE_REG2_OFFSET 0x141 +#define POWERGATE_REG_WRITE_OFFSET 0x142 +#define SELECT_BG_CLK_OFFSET 0x144 +#define BOD_TEST_PG_VBATT_STATUS_REG_OFFSET 0x1E3 +#define POWERGATE_REG_READ_OFFSET 0x342 + +//! PMU SPI (0x24058000) +#define PMU_1P3_CTRL_REG_OFFSET 0x1D0 +#define PMU_PFM_REG_OFFSET 0x1D1 +#define PMU_ADC_REG_OFFSET 0x1D2 +#define PMU_PID_REG1_OFFSET 0x1D3 +#define PMU_PTAT_REG_OFFSET 0x1D5 +#define PMU_LDO_REG_OFFSET 0x1D6 +#define PMU_PWRTRAIN_REG_OFFSET 0x1D8 +#define PMU_TESTMUX_REG1_OFFSET 0x1D9 +#define PMU_TEST_MODES_OFFSET 0x1DA +#define SPARE_REG_1_OFFSET 0x1DC +#define SPARE_REG_2_OFFSET 0x1DD +#define BYPASS_CURR_CTRL_REG_OFFSET 0x1DE +#define SPARE_REG_3_OFFSET 0x1DF +#define PMU_FREQ_MODE_REG 0x1CE +#define LOW_FREQ_PWM BIT(2) +#define MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_OFFSET 0x20 +#define MCU_FSM_PMU_STATUS_REG_OFFSET 0x40 + +//! NWP_PMU_CTRLS defines +#define scdcdc_lp_mode_en BIT(0) +#define bgpmu_sleep_en BIT(1) +#define standby_dc1p3 BIT(19) + +#define MCU_AON_BASE_ADDR 0x24048000 +#define MCU_FSM_PMU_CTRL *(volatile uint32 *)(MCU_AON_BASE_ADDR + 0x140) +#define MCUAON_GEN_CTRLS_REG *(volatile uint32 *)(MCU_AON_BASE_ADDR + 0x14) +#define MCUAON_SHELF_MODE *(volatile uint32 *)(MCU_AON_BASE_ADDR + 0x10) + +//! MCUAON_GEN_CTRLS register defines +#define NPSS_SUPPLY_0P9_BIT BIT(17) +#define ENABLE_PDO_BIT BIT(16) + +#define NWP_AHB_ADDR 0x41300000 +#define ULP_DIRECT_ACCESS(_x) *(uint32 *)(NWP_AHB_ADDR + (_x)) +#define NWPAON_POR_CTRL_BITS_REG 0x3C +#define NWP_FSM_FIRST_BOOTUP 0x0120 + +//! NWP_FSM_FIRST_BOOTUP defines +#define nwp_ulp_32khz_xtal_clk_en BIT(18) +#define nwp_ulp_32mhz_rc_clk_en BIT(19) +#define nwp_ulp_20mhz_ring_osc_clk_en BIT(20) +#define nwp_ulp_doubler_clk_en BIT(21) + +#define TASS_PWR_CTRL_BASE_ADDR 0x41300400 +#define TASS_FSM_CTRL_BYPASS *(volatile uint32 *)(TASS_PWR_CTRL_BASE_ADDR + 0x1C) +//! TASS_FSM_CTRL_BYPASS defines +#define ta_xtal_en_40MHz_bypass_cntrl BIT(0) +#define ta_xtal_en_40MHz_bypass BIT(1) +#define ta_pmu_shut_down_bypass_cntrl BIT(2) +#define ta_pmu_shut_down_bypass BIT(3) +#define ta_buck_boost_enable_bypass_cntrl BIT(4) +#define ta_buck_boost_enable_bypass BIT(5) + +//! ULPCLKS_ADAPTIVE_REG defines +#define adapt_powergate_en BIT(3) + +//! ULPCLKS_DOUBLER_XTAL_REG defines +#define doubler_en BIT(21) + +//! ULPCLKS_32MRC_CLK_REG defines +#define rc_32mhz_en BIT(21) + +//! ULPCLKS_HF_RO_CLK_REG defines +#define ro_hf_en BIT(21) + +//! ULPCLKS_TRIM_SEL_REG defines +#define calib_powergate_en BIT(9) + +//! ULPCLKS_32KXTAL_CLK_REG defines +#define xtal_32khz_en BIT(21) + +#define pass_clk_40m_buffer_enable BIT(15) + +//! iPMU_SPARE_REG2 defines +#define wurx_lvl_shift_en BIT(20) +#define wurx_pg_en_1 BIT(21) + +//! POWERGATE_REG_WRITE defines +#define auxdac_pg_enb BIT(8) +#define auxadc_pg_enb BIT(11) +#define wurx_corr_pg_enb BIT(12) +#define wurx_pg_enb BIT(13) +#define ulp_ang_pwrsupply_pg_enb BIT(14) +#define ulp_ang_clks_pg_enb BIT(15) +#define cmp_npss_pg_enb BIT(16) + +#define IPMU_HIGH_POWER_MODE 0 +#define IPMU_LOW_POWER_MODE 1 + +//! SELECT_BG_CLK defines +#define latch_transparent_lf BIT(2) +#define latch_transparent_hf BIT(3) +#define latch_top_spi BIT(4) + +//! PMU_PFM_REG defines +#define ext_pfm_en1p3 BIT(17) + +//! PMU_PTAT_REG defines +#define test_pfm_mode1p3 BIT(4) + +//! PMU_LDO_REG defines +#define LDOSOC_DEFAULT_MODE_EN BIT(5) + +//! PMU_PWRTRAIN_REG defines +#define BYPASS_LDORF_CTRL BIT(2) + +//! BOD_TEST_PG_VBATT_STATUS_REG defines +#define bod_pwrgate_en_n_ulp_button_calib BIT(15) + +//! MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP defines +#define mcu_ulp_32khz_xtal_clk_en BIT(18) +#define mcu_ulp_32mhz_rc_clk_en BIT(19) +#define mcu_ulp_20mhz_ring_osc_clk_en BIT(20) +#define mcu_ulp_doubler_clk_en BIT(21) + +//! NWPAON_POR_CTRL_BITS defines +#define poc_cntrl_reg_0 BIT(0) + +#define MCU_FSM_DIRECT_ACCESS(_x) *(volatile uint32 *)(MCU_FSM_BASE_ADDRESS + (_x)) + +#define TEMP_SENSOR_BJT *(volatile uint32 *)(0x240439E0) +#define temp_sens_en BIT(0) + +#define TS_SLOPE_SET_OFFSET 0x04 +#define TS_NOMINAL_SETTINGS_OFFSET 0x08 + +//! BG_SCDC_PROG_REG_2 defines +#define scdcdc_sel BIT(21) +#define testmode_0_en BIT(20) + +//! SCDC_CTRL_REG_0 defines +#define ext_cap_en BIT(21) + +//! PMU_LDO_REG defines +#define LDORF_DEFAULT_MODE_EN BIT(11) + +#define LS_SHIFT 22 +#define MS_SHIFT 27 +#define IPMU_DATAMASK 0x3fffff + +#define mcu_dcdc_lvl BIT(18) +#define mcu_soc_ldo_lvl BIT(17) + +/*32khz rc clock define */ +#define RC_TRIM_VALUE_LF 0x7F0 +#define RO_TRIM_VALUE_LF 0x1F0 +#define MASK32KRO_TRIM_VALUE_WRITE_BITS 0x1F0000 +#define MASK32KRC_TRIM_VALUE_WRITE_BITS 0x1FC000 +#define TRIM_MSB_32MHZ 20 +#define TRIM_LSB_32MHZ 14 +#define PARTICULAR_FREQ_MIN 10 +#define PARTICULAR_FREQ_MAX 100 +#define MIN_DIFF_FREQ 3 + +/* 64khz rc clock define */ +#define ENABLE_32KHZ_CLOCK_TRIM 0x40F03000 +#define NPSS_REF_CLOCK_40MSOC 0x41A48000 +#define NUMBER_HIGH_FRQ_CLOCK 0x42C4E390 +#define LOW_FREQ_CLOCK_CAL 0x42B24210 +#define ORIGINAL_REF_VALUE_AFTER_CAL 0x42C9C590 + +/****************************************************** + * * Structures + * ******************************************************/ + +//! This structure contains format for retention_boot_status_word_0 +typedef struct retention_boot_status_word_s { +#define SDIO_USB_WITH_TA 3 +#define SDIO_WITH_TA_USB_WITH_M4 2 +#define SDIO_WITH_M4_USB_WITH_TA 1 +#define SDIO_USB_WITH_M4 0 + uint32_t m4_present : 1; + uint32_t m4_flash_present : 1; + uint32_t m4_flash_pinset : 4; + uint32_t m4_flash_address_width_valid : 1; + uint32_t m4_flash_address_width : 2; + uint32_t select_host_inf_with_m4_valid : 1; + uint32_t select_host_inf_with_m4 : 2; + uint32_t m4_secure_boot_enable : 1; + uint32_t m4_encrypt_firmware : 1; + uint32_t host_if_with_ta : 1; + uint32_t mcu_wdt_hw_timer : 1; +#ifdef CHIP_9118 +#define NONE_MODE 0 +#define NLINK 1 +#define WISECONNECT 2 +#define WCPLUS 3 +#define MCU 4 +#define WISEMCU 5 +#define ACCELARATOR 6 +#define WC_SIMULATANEOUS 7 +#endif +#ifdef SLI_SI917 +//! Product modes +#define WISEMCU 0 +#define WCPLUS 3 +#define ACCELARATOR 4 +#define WISECONNECT 6 +#define NLINK 7 +#define MCU 0xF // not supported +#endif + uint32_t product_mode : 4; + uint32_t m4_flash_type : 4; + uint32_t m4_dual_flash : 1; + uint32_t m4_csum : 1; + uint32_t wise_aoc_mode : 1; + uint32_t wise_aoc_from_m4_rom : 1; + uint32_t m4_image_format : 1; + uint32_t clean_ulp_wakeup : 1; +#define M4_IMAGE_VALID_IND BIT(30) + uint32_t m4_image_valid : 1; + uint32_t reserved : 1; /* one bit is reserved for hardware */ +} retention_boot_status_word_t; + +/* This structure contains format for efuse_dword0 */ +typedef struct npss_boot_status_word_0_s { + //! Data from EFUSE + uint32_t usb_fsel_valid : 1; + uint32_t mems_ref_clk_as_usb_phy_clk : 1; + uint32_t modem_pll_as_usb_phy_clk : 1; + uint32_t usb_phy_clk_fsel_external : 1; + uint32_t usb_fsel : 3; + uint32_t bypass_usb_detection : 1; + //! Data derived by bootloder + uint32_t host_sel_valid : 1; + uint32_t host_sel : 3; + uint32_t ta_flash_present : 1; + uint32_t ta_flash_pinset : 4; + uint32_t ta_flash_address_width_valid : 1; + uint32_t ta_flash_address_width : 2; + uint32_t ta_flash_type : 4; + // uint32_t ta_dual_flash : 1; + uint32_t fips_enable : 1; + uint32_t usb_fclk_div_factor : 2; +#define BBFF_DATA_VALID BIT(27) + uint32_t bbff_data_valid : 1; + //! Bits configured by FW +#define NWP_SOFT_RESET BIT(28) + uint32_t soft_reset : 1; +#define FACTORY_RESET BIT(29) + uint32_t factory_reset : 1; +#define TAMPER_RECOVERY BIT(30) + uint32_t tamper_recovery : 1; + uint32_t reserved : 1; +} npss_boot_status_word0_t; + +#ifdef CHIP_9118 +typedef struct efuse_ipmu_s { + uint32_t trim_0p5na1 : 1; + uint32_t trim_0p5na2 : 1; + uint32_t bg_r_vdd_ulp : 4; + uint32_t bg_r_ptat_vdd_ulp : 3; + uint32_t resbank_trim : 2; + uint32_t trim_sel : 7; + uint32_t del_2x_sel : 6; + uint32_t freq_trim : 5; + uint32_t coarse_trim_16k : 2; + uint32_t fine_trim_16k : 7; + uint32_t coarse_trim_64k : 2; + uint32_t fine_trim_64k : 7; + uint32_t coarse_trim_32k : 2; + uint32_t fine_trim_32k : 7; + uint32_t xtal1_trim_32k : 4; + uint32_t xtal2_trim_32k : 4; + uint32_t trim_ring_osc : 7; + uint32_t vbatt_status_1 : 6; + uint32_t str_temp_slope : 10; + uint32_t f2_nominal : 10; + uint32_t str_nominal_temp : 7; + uint32_t str_bjt_temp_sense_off : 16; + uint32_t str_bjt_temp_sense_slope : 16; +#ifndef AT_EFUSE_DATA_1P19 + uint32_t reserved1 : 20; +#endif + +#ifdef AT_EFUSE_DATA_1P19 + uint32_t trim_sel_20Mhz : 7; // Trim value for 20mzh rc + uint32_t ro_32khz_00_trim : 5; + uint32_t scdc_dcdc_trim : 3; + uint32_t scdc_hpldo_trim : 3; + uint32_t reserved1 : 2; +#endif + uint32_t ldo_ctrl : 4; +#ifndef AT_EFUSE_DATA_1P19 + uint32_t reserved2 : 16; +#endif +#ifdef AT_EFUSE_DATA_1P19 + uint32_t vbg_tsbjt_efuse : 12; + uint32_t retn_ldo_lptrim : 3; + uint32_t reserved2 : 1; +#endif + uint32_t auxadc_offset_diff : 12; + uint32_t auxadc_invgain_diff : 16; + uint32_t auxadc_offset_single : 12; + uint32_t auxadc_invgain_single : 16; + uint32_t set_vref1p3 : 4; + +#ifndef AT_EFUSE_DATA_1P19 + uint32_t set_vref_isense1p3 : 2; + uint32_t set_vref_adc : 2; + uint32_t vtrim_ldosoc : 2; +#endif + +#ifdef AT_EFUSE_DATA_1P19 + uint32_t reserved13 : 6; +#endif + + uint32_t trim_r1_resistorladder : 4; +#ifndef AT_EFUSE_DATA_1P19 + uint32_t enable_undershoot_reduction : 1; + uint32_t select_vref_comp : 2; +#endif + +#ifdef AT_EFUSE_DATA_1P19 + uint32_t retn_ldo_hptrim : 3; +#endif + +#ifndef AT_EFUSE_DATA_1P19 + uint32_t pwr_gd_threshold_sel : 1; + uint32_t sel_overshoot_control : 1; + uint32_t ptat_load_ctrl : 3; + uint32_t ctrl_soc : 4; + uint32_t pt_gate_ctrl : 3; + uint32_t default_mode_ctrl : 1; + uint32_t ptat_load_enable : 1; + uint32_t ldosoc_outputpulldown_sel : 1; + uint32_t ldosoc_outputpulldown : 1; +#endif + +#ifdef AT_EFUSE_DATA_1P19 + uint32_t reserved12 : 16; +#endif + + uint32_t scale_soc_ldo_vref : 1; + +#ifndef AT_EFUSE_DATA_1P19 + uint32_t ctrl_rf : 4; + uint32_t default_mode : 1; + uint32_t test_ldopulldown_sel : 1; + uint32_t test_ldopulldown : 1; + uint32_t drive_n : 2; + uint32_t drive_p : 2; + uint32_t deadtime_ctrl_n2p : 4; + uint32_t deadtime_ctrl_p2n : 4; + uint32_t revi_offset_prog : 3; + uint32_t tran_lo_ctr : 2; + uint32_t tran_hi_ctr : 2; + uint32_t tran_und_shoot_ctr : 3; +#endif + +#ifdef AT_EFUSE_DATA_1P19 + uint32_t reserved11 : 7; + uint32_t reserved10 : 12; + uint32_t reserved9 : 10; +#endif + + uint32_t dpwm_freq_trim : 4; + +#ifndef AT_EFUSE_DATA_1P19 + uint32_t pfmro_freq_trim : 3; + uint32_t test_revi_delay : 1; + uint32_t sel_sleep_nmos_ctrl : 1; + uint32_t p_1p3 : 13; + uint32_t i_steady_state1p3 : 13; + uint32_t d_1p3 : 15; + uint32_t i_soft_start1p3 : 13; + uint32_t dither_en1p3 : 1; + uint32_t auto_mode_tran_disable : 1; +#endif + +#ifdef AT_EFUSE_DATA_1P19 + uint32_t reserved73 : 1; + uint32_t reserved74 : 13; + uint32_t reserved75 : 13; + uint32_t reserved76 : 15; + uint32_t reserved77 : 13; + uint32_t reserved78 : 1; + uint32_t reserved79 : 1; +#endif + + uint32_t pfm_pon_time_sel : 4; + +#ifndef AT_EFUSE_DATA_1P19 + uint32_t pfm_non_time_sel : 3; + uint32_t pwm_cont_prog : 3; + uint32_t pfm_clk_up_del_sel : 3; + uint32_t pwm_to_pfm_pulse_count_prog : 2; + uint32_t pfm_to_pwm_pulse_count_prog : 2; + uint32_t pfm_to_pwm_cur_prog : 3; + uint32_t pwm_to_pfm_cur_prog : 3; + uint32_t max_duty_cycle_threshold : 3; + uint32_t min_duty_cycle_threshold : 3; + uint32_t bypass_pfm_to_pwm_counter_1 : 1; + uint32_t no_of_pfm_clk : 4; + uint32_t adc_op_thresh_sel : 2; +#endif + +#ifdef AT_EFUSE_DATA_1P19 + uint32_t reserved6; + uint32_t reserved31 : 3; + uint32_t reserved32 : 3; + uint32_t reserved33 : 3; + uint32_t reserved34 : 2; + uint32_t reserved35 : 2; + uint32_t reserved36 : 3; + uint32_t reserved37 : 3; + uint32_t reserved38 : 3; + uint32_t reserved39 : 3; + uint32_t reserved40 : 1; + uint32_t reserved41 : 4; + uint32_t reserved42 : 2; +#endif + uint32_t reserved3 : 4; + uint32_t reserved4[2]; + uint16_t reserved5; + +} __attribute__((__packed__)) efuse_ipmu_t; +#endif + +#ifdef SLI_SI917 +typedef struct efuse_ipmu_s { + uint32_t trim_0p5na1 : 1; + uint32_t bg_r_vdd_ulp : 5; + uint32_t bg_r_ptat_vdd_ulp : 3; + uint32_t reserved20 : 2; //Removed in RS9117 + uint32_t trim_sel : 7; + uint32_t del_2x_sel : 6; + uint32_t freq_trim : 5; + uint32_t coarse_trim_16k : 2; + uint32_t fine_trim_16k : 7; + uint32_t coarse_trim_64k : 2; + uint32_t fine_trim_64k : 7; + uint32_t coarse_trim_32k : 2; + uint32_t fine_trim_32k : 7; + uint32_t xtal1_trim_32k : 4; + uint32_t xtal2_trim_32k : 4; + uint32_t trim_ring_osc : 7; + uint32_t vbatt_status_1 : 6; + uint32_t str_temp_slope : 10; + uint32_t f2_nominal : 10; + uint32_t str_nominal_temp : 7; + uint32_t str_bjt_temp_sense_off : 16; + uint32_t str_bjt_temp_sense_slope : 16; + uint32_t trim_sel_20Mhz : 7; // Trim value for 20mzh rc + uint32_t ro_32khz_00_trim : 5; + uint32_t scdc_dcdc_trim : 3; + uint32_t scdc_hpldo_trim : 3; + uint32_t reserved1 : 2; + uint32_t ldo_ctrl : 4; + uint32_t vbg_tsbjt_efuse : 12; + uint32_t retn_ldo_lptrim : 3; + uint32_t reserved2 : 1; + uint32_t auxadc_offset_diff : 12; + uint32_t auxadc_invgain_diff : 16; + uint32_t auxadc_offset_single : 12; + uint32_t auxadc_invgain_single : 16; + uint32_t set_vref1p3 : 4; + uint32_t reserved13 : 6; + uint32_t trim_r1_resistorladder : 4; + uint32_t retn_ldo_hptrim : 3; + uint32_t reserved12 : 16; + uint32_t scale_soc_ldo_vref : 1; + uint32_t reserved11 : 7; + uint32_t reserved10 : 12; + uint32_t reserved9 : 10; + uint32_t dpwm_freq_trim : 4; + uint32_t reserved73 : 32; // 73 and 74 togther as 50 + uint32_t reserved74 : 18; // + uint32_t scdc_clk_freq : 5; + uint32_t reserved7 : 6; + uint32_t buck_ind_efuse : 4; + uint32_t reserved31 : 32; // 31,32 and 33 togther as 80 + uint32_t reserved32 : 32; + uint32_t reserved33 : 16; +} __attribute__((__packed__)) efuse_ipmu_t; +#endif + +/* Clock trim APL structure */ +typedef enum INPUT_CLOCK { + ulp_ref_clk = 0, + ulp_20mhz_ringosc_clk = 2, + sleep_clk = 8, + soc_pll_clk = 6 + +} INPUT_CLOCK_T; + +typedef enum SLEEP_CLOCK { khz_rc_clk = 0x0, khz_xtal_clk = 0x1, khz_ro_clk = 0x3, none = 0x233 } SLEEP_CLOCK_T; + +/****************************************************** + * * Global Variables + * ******************************************************/ + +/****************************************************** + * * Function Declarations + * ******************************************************/ +/** + * \ingroup RSI_SPECIFIC_DRIVERS + * \defgroup RSI_IPMU_DRIVERS RSI:RS1xxxx IPMU + * @{ + * + */ +rsi_error_t RSI_IPMU_Xtal2bias_Efuse(void); +rsi_error_t RSI_IPMU_Xtal1bias_Efuse(void); +uint32_t RSI_IPMU_Delvbe_Tsbjt_Efuse(void); +rsi_error_t RSI_IPMU_Dpwmfreq_TrimEfuse(void); +rsi_error_t RSI_IPMU_Ldosoc_TrimEfuse(void); +rsi_error_t RSI_IPMU_Buck_TrimEfuse(void); +rsi_error_t RSI_IPMU_POCbias_Efuse(void); +rsi_error_t RSI_IPMU_Blackout_TrimEfuse(void); +rsi_error_t RSI_IPMU_Bg_TrimEfuse(void); +uint32_t RSI_IPMU_Auxadcgain_SeEfuse(void); +uint32_t RSI_IPMU_Auxadcoff_SeEfuse(void); +uint32_t RSI_IPMU_Auxadcoff_DiffEfuse(void); +uint32_t RSI_IPMU_Auxadcgain_DiffEfuse(void); +uint32_t RSI_IPMU_Vbg_Tsbjt_Efuse(void); +uint32_t RSI_IPMU_RO_TsEfuse(void); +rsi_error_t RSI_IPMU_Vbattstatus_TrimEfuse(void); +rsi_error_t RSI_IPMU_RC32khz_TrimEfuse(void); +rsi_error_t RSI_IPMU_RC64khz_TrimEfuse(void); +rsi_error_t RSI_IPMU_RC16khz_TrimEfuse(void); +rsi_error_t RSI_IPMU_RO32khz_TrimEfuse(void); +rsi_error_t RSI_IPMU_M20roOsc_TrimEfuse(void); +rsi_error_t RSI_IPMU_DBLR32M_TrimEfuse(void); +rsi_error_t RSI_IPMU_M20rcOsc_TrimEfuse(void); +rsi_error_t RSI_IPMU_PMUCommonConfig(void); +rsi_error_t RSI_IPMU_M32rc_OscTrimEfuse(void); +void RSI_IPMU_PowerGateSet(uint32_t mask_vlaue); +void RSI_IPMU_PowerGateClr(uint32_t mask_vlaue); +rsi_error_t RSI_IPMU_CommonConfig(void); +void RSI_IPMU_ClockMuxSel(uint8_t bg_pmu_clk); +uint32_t RSI_IPMU_32MHzClkClib(void); +rsi_error_t RSI_IPMU_ProgramConfigData(uint32_t *config); +void RSI_IPMU_InitCalibData(void); +void RSI_IPMU_UpdateIpmuCalibData_efuse(efuse_ipmu_t *ipmu_calib_data); +uint32_t RSI_APB_ProgramConfigData(uint32_t *config); +uint32_t RSI_IPMU_RO_TsConfig(void); +void RSI_Configure_DCDC_LowerVoltage(void); +void RSI_IPMU_32KHzRCClkClib(void); +void RSI_IPMU_32KHzROClkClib(void); +rsi_error_t RSI_IPMU_PocbiasCurrent11(void); +rsi_error_t RSI_IPMU_RO32khzTrim00Efuse(void); +rsi_error_t RSI_IPMU_RetnHP_Volttrim_Efuse(void); +rsi_error_t RSI_IPMU_PocbiasCurrent(void); +void RSI_IPMU_RetnLdoHpmode(void); +void RSI_IPMU_RetnLdoLpmode(void); +void RSI_IPMU_Retn_Voltage_Reduction(void); +void RSI_IPMU_Retn_Voltage_To_Default(void); +void RSI_IPMU_Set_Higher_Pwm_Ro_Frequency_Mode_to_PMU(void); +rsi_error_t RSI_IPMU_RetnLdo0p75(void); +rsi_error_t RSI_IPMU_RetnLdoVoltsel(void); +void RSI_IPMU_64KHZ_RCClktrim(void); +void RSI_IPMU_20M_ROClktrim(uint8_t clkfreq); +uint32_t RSI_Clks_Calibration(INPUT_CLOCK_T inputclk, SLEEP_CLOCK_T sleep_clk_type); +uint32_t RSI_Clks_Trim32MHzRC(uint32_t freq); +void RSI_IPMU_SCDC_Enable(void); +void RSI_IPMU_HP_LDO_Enable(void); +void RSI_Ipmu_Init(void); +void RSI_Configure_Ipmu_Mode(void); +void ipmu_init(void); +void configure_ipmu_mode(uint32_t mode); +uint32_t init_ipmu_calib_data(uint32_t m4_present); +void update_ipmu_data(uint32_t reg_addr, uint32_t reg_type, uint32_t data, uint32_t mask); +void update_efuse_system_configs(int data, uint32_t config_ptr[]); +rsi_error_t RSI_IPMU_BOD_ClksCommonconfig1(void); +rsi_error_t RSI_IPMU_BOD_ClksCommonconfig2(void); +rsi_error_t RSI_IPMU_Hpldo_volt_trim_efuse(void); +rsi_error_t RSI_IPMU_Scdc_volt_trim_efuse(void); +void RSI_IPMU_Reconfig_to_SCDCDC(void); +rsi_error_t RSI_IPMU_Lp_scdc_extcapmode(void); +rsi_error_t RSI_IPMU_BOD_Cmphyst(void); +/** + * @} end of RSI_IPMU_DRIVERS + */ +/* @} end of RSI_IPMU_DRIVERS */ + +#ifdef __cplusplus +} +#endif +#endif // RSI_IPMU_H diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_pll.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_pll.h new file mode 100644 index 000000000..39a82ddf3 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_pll.h @@ -0,0 +1,841 @@ +/******************************************************************************* +* @file rsi_pll.h +* @brief +******************************************************************************* +* # License +* Copyright 2020 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +/** + * Includes + */ +#ifndef __RSI_PLL_H__ +#define __RSI_PLL_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "rsi_ccp_common.h" +#include "rsi_error.h" +#include "rsi_ipmu.h" +#include "rsi_reg_spi.h" + +#define MISC_CFG_MISC_CTRL (*((uint32_t volatile *)(MISC_CONFIG_BASE + 0x14))) + +typedef void (*cdDelay)(uint32_t delay); + +#define CCI_SYNC_MODE BIT(16) /* Enables CCI_SYNC_MODE */ +/*M4 Clock configuration base address */ + +/*SET Reg 1 SET / CLR*/ +#define USART1_PCLK_ENABLE BIT(0) /* Enables USART1_PCLK_ENABLE */ +#define USART1_SCLK_ENABLE BIT(1) /* Enables USART1_SCLK_ENABLE */ +#define USART2_PCLK_ENABLE BIT(2) /* Enables USART2_PCLK_ENABLE */ +#define USART2_SCLK_ENABLE BIT(3) /* Enables USART2_SCLK_ENABLE */ +#ifdef SLI_SI917B0 +#define QSPI_2_CLK_ENABLE BIT(4) /* Enables QSPI_CLK_ENABLE */ +#define QSPI_2_HCLK_ENABLE BIT(5) /* Enables QSPI_HCLK_ENABLE */ +#define QSPI_2_M4_SOC_SYNC BIT(6) /* Enables QSPI_M4_SOC_SYNC */ +#define QSPI_2_CLK_ONEHOT_ENABLE BIT(7) /* Enables QSPI_CLK_ONEHOT_ENABLE */ +#endif +#define CT_CLK_ENABLE BIT(9) /* Enables CT_CLK_ENABLE */ +#define CT_PCLK_ENABLE BIT(10) /* Enables CT_PCLK_ENABLE */ +#define ICACHE_CLK_ENABLE BIT(11) /* Enables ICACHE_CLK_ENABLE */ +#define ICACHE_CLK_2X_ENABLE BIT(12) /* Enables ICACHE_CLK_2X_ENABLE */ +#define RPDMA_HCLK_ENABLE BIT(13) /* Enables RPDMA_HCLK_ENABLE */ +#define SOC_PLL_SPI_CLK_ENABLE BIT(14) /* Enables SOC_PLL_SPI_CLK_ENABLE */ +#define IID_CLK_ENABLE BIT(16) /* Enables IID_CLK_ENABLE */ +#define SDIO_SYS_HCLK_ENABLE BIT(17) /* Enables SDIO_SYS_HCLK_ENABLE */ +#define CRC_CLK_ENABLE_M4 BIT(18) /* Enables CRC_CLK_ENABLE_M4 */ +#define M4SS_UM_CLK_STATIC_EN BIT(19) /* Enables M4SS_UM_CLK_STATIC_EN */ +#define ETH_HCLK_ENABLE BIT(21) /* Enables ETH_HCLK_ENABLE */ +#define HWRNG_PCLK_ENABLE BIT(22) /* Enables HWRNG_PCLK_ENABLE */ +#define GNSS_MEM_CLK_ENABLE BIT(23) /* Enables GNSS_MEM_CLK_ENABLE */ +#define CCI_PCLK_ENABLE BIT(24) /* Enables CCI_PCLK_ENABLE */ +#define CCI_HCLK_ENABLE BIT(25) /* Enables CCI_HCLK_ENABLE */ +#define CCI_CLK_ENABLE BIT(26) /* Enables CCI_CLK_ENABLE */ +#define MASK_HOST_CLK_WAIT_FIX BIT(27) /* Enables MASK_HOST_CLK_WAIT_FIX */ +#define MASK31_HOST_CLK_CNT BIT(28) /* Enables MASK31_HOST_CLK_CNT */ +#define SD_MEM_INTF_CLK_ENABLE \ + BIT(29) /* Static Clock gating Enable for sd_mem_intf clk1'b1 => Clock is enabled1'b0 => Invalid*/ +#define MASK_HOST_CLK_AVAILABLE_FIX BIT(30) /* Enables MASK_HOST_CLK_AVAILABLE_FIX */ +#define ULPSS_CLK_ENABLE BIT(31) /* Enables ULPSS_CLK_ENABLE */ + +/*SER Reg2 SET / CLR*/ +#define GEN_SPI_MST1_HCLK_ENABLE BIT(0) /* Enables GEN_SPI_MST1_HCLK_ENABLE */ +#define CAN1_PCLK_ENABLE BIT(2) /* Enables CAN1_PCLK_ENABLE */ +#define CAN1_CLK_ENABLE BIT(3) /* Enables CAN1_CLK_ENABLE */ +#define UDMA_HCLK_ENABLE BIT(6) /* Enables UDMA_HCLK_ENABLE */ +#define I2C_BUS_CLK_ENABLE BIT(7) /* Enables I2C_1_BUS_CLK_ENABLE */ +#define I2C_2_BUS_CLK_ENABLE BIT(8) /* Enables I2C_2_BUS_CLK_ENABLE */ +#define SSI_SLV_PCLK_ENABLE BIT(9) /* Enables SSI_SLV_PCLK_ENABLE */ +#define SSI_SLV_SCLK_ENABLE BIT(10) /* Enables SSI_SLV_SCLK_ENABLE */ +#define QSPI_CLK_ENABLE BIT(11) /* Enables QSPI_CLK_ENABLE */ +#define QSPI_HCLK_ENABLE BIT(12) /* Enables QSPI_HCLK_ENABLE */ +#define I2SM_SCLK_ENABLE BIT(13) /* Enables I2SM_SCLK_ENABLE */ +#define I2SM_INTF_SCLK_ENABLE BIT(14) /* Enables I2SM_INTF_SCLK_ENABLE */ +#define I2SM_PCLK_ENABLE BIT(15) /* Enables I2SM_PCLK_ENABLE */ +#define QE_PCLK_ENABLE BIT(17) /* Enables QE_PCLK_ENABLE */ +#define MCPWM_PCLK_ENABLE BIT(18) /* Enables MCPWM_PCLK_ENABLE */ +#define SGPIO_PCLK_ENABLE BIT(20) /* Enables SGPIO_PCLK_ENABLE */ +#define EGPIO_PCLK_ENABLE BIT(21) /* Enables EGPIO_PCLK_ENABLE */ +#define ARM_CLK_ENABLE BIT(22) /* Enables ARM_CLK_ENABLE */ +#define SSI_MST_PCLK_ENABLE BIT(23) /* Enables SSI_MST_PCLK_ENABLE */ +#define SSI_MST_SCLK_ENABLE BIT(24) /* Enables SSI_MST_SCLK_ENABLE */ +#define MEM2_CLK_ENABLE BIT(25) /* Enables MEM2_CLK_ENABLE */ +#define MEM_CLK_ULP_ENABLE BIT(26) /* Enables MEM_CLK_ULP_ENABLE */ +#define ROM_CLK_ENABLE BIT(27) /* Enables ROM_CLK_ENABLE */ +#define PLL_INTF_CLK_ENABLE BIT(28) /* Enables PLL_INTF_CLK_ENABLE */ +#define SEMAPHORE_CLK_ENABLE BIT(29) /* Enables SEMAPHORE_CLK_ENABLE */ +#define TOT_CLK_ENABLE BIT(30) /* Enables TOT_CLK_ENABLE */ +#define RMII_SOFT_RESET BIT(31) /* Enables RMII_SOFT_RESET */ + +/*SET Reg 3 SET / CLR*/ +#define BUS_CLK_ENABLE BIT(0) /* Enables BUS_CLK_ENABLE */ +#define M4_CORE_CLK_ENABLE BIT(1) /* Enables M4_CORE_CLK_ENABLE */ +#define CM_BUS_CLK_ENABLE BIT(2) /* Enables CM_BUS_CLK_ENABLE */ +#define MISC_CONFIG_PCLK_ENABLE BIT(4) /* Enables MISC_CONFIG_PCLK_ENABLE */ +#define EFUSE_CLK_ENABLE BIT(5) /* Enables EFUSE_CLK_ENABLE */ +#define ICM_CLK_ENABLE BIT(6) /* Enables ICM_CLK_ENABLE */ +#define MEM1_CLK_ENABLE BIT(7) /* Enables MEM1_CLK_ENABLE */ +#define MEM3_CLK_ENABLE BIT(8) /* Enables MEM3_CLK_ENABLE */ +#define USB_PHY_CLK_IN_ENABLE BIT(12) /* Enables USB_PHY_CLK_IN_ENABLE */ +#define QSPI_CLK_ONEHOT_ENABLE BIT(13) /* Enables QSPI_CLK_ONEHOT_ENABLE */ +#define QSPI_M4_SOC_SYNC BIT(14) /* Enables QSPI_M4_SOC_SYNC */ +#define EGPIO_CLK_ENABLE BIT(16) /* Enables EGPIO_CLK_ENABLE */ +#define I2C_CLK_ENABLE BIT(17) /* Enables I2C_CLK_ENABLE */ +#define I2C_2_CLK_ENABLE BIT(18) /* Enables I2C_2_CLK_ENABLE */ +#define EFUSE_PCLK_ENABLE BIT(19) /* Enables EFUSE_PCLK_ENABLE */ +#define SGPIO_CLK_ENABLE BIT(20) /* Enables SGPIO_CLK_ENABLE */ +#define TASS_M4SS_64K_SWITCH_CLK_ENABLE BIT(21) /* Enables TASS_M4SS_64K_SWITCH_CLK_ENABLE */ +#define TASS_M4SS_128K_SWITCH_CLK_ENABLE BIT(22) /* Enables TASS_M4SS_128K_SWITCH_CLK_ENABLE */ +#define TASS_M4SS_SDIO_SWITCH_CLK_ENABLE BIT(23) /* Enables TASS_M4SS_SDIO_SWITCH_CLK_ENABLE */ +#define TASS_M4SS_USB_SWITCH_CLK_ENABLE BIT(24) /* Enables TASS_M4SS_USB_SWITCH_CLK_ENABLE */ +#define ROM_MISC_STATIC_ENABLE BIT(25) /* Enables ROM_MISC_STATIC_ENABLE */ +#define M4_SOC_CLK_FOR_OTHER_ENABLE BIT(26) /* Enables M4_SOC_CLK_FOR_OTHER_ENABLE */ +#define ICACHE_ENABLE BIT(27) /* Enables ICACHE_ENABLE */ + +/*DYN_CLK_GATE_DISABLE_REG */ + +#define SDIO_SYS_HCLK_DYN_CTRL_DISABLE BIT(0) /* Enables SDIO_SYS_HCLK_DYN_CTRL_DISABLE */ +#define BUS_CLK_DYN_CTRL_DISABLE BIT(1) /* Enables BUS_CLK_DYN_CTRL_DISABLE */ +#define GPDMA_HCLK_DYN_CTRL_DISABLE BIT(4) /* Enables GPDMA_HCLK_DYN_CTRL_DISABLE */ +#define EGPIO_PCLK_DYN_CTRL_DISABLE BIT(5) /* Enables EGPIO_PCLK_DYN_CTRL_DISABLE */ +#define SGPIO_PCLK_DYN_CTRL_DISABLE BIT(6) /* Enables SGPIO_PCLK_DYN_CTRL_DISABLE */ +#define TOT_CLK_DYN_CTRL_DISABLE BIT(7) /* Enables TOT_CLK_DYN_CTRL_DISABLE */ +#define HWRNG_PCLK_DYN_CTRL_DISABLE BIT(8) /* Enables HWRNG_PCLK_DYN_CTRL_DISABLE */ +#define USART1_SCLK_DYN_CTRL_DISABLE BIT(9) /* Enables USART1_SCLK_DYN_CTRL_DISABLE */ +#define USART1_PCLK_DYN_CTRL_DISABLE BIT(10) /* Enables USART1_PCLK_DYN_CTRL_DISABLE */ +#define USART2_SCLK_DYN_CTRL_DISABLE BIT(11) /* Enables USART2_SCLK_DYN_CTRL_DISABLE */ +#define USART2_PCLK_DYN_CTRL_DISABLE BIT(12) /* Enables USART2_PCLK_DYN_CTRL_DISABLE */ +#define SSI_SLV_SCLK_DYN_CTRL_DISABLE BIT(15) /* Enables SSI_SLV_SCLK_DYN_CTRL_DISABLE */ +#define SSI_SLV_PCLK_DYN_CTRL_DISABLE BIT(16) /* Enables SSI_SLV_PCLK_DYN_CTRL_DISABLE */ +#define I2SM_INTF_SCLK_DYN_CTRL_DISABLE BIT(18) /* Enables I2SM_INTF_SCLK_DYN_CTRL_DISABLE */ +#define SEMAPHORE_CLK_DYN_CTRL_DISABLE BIT(19) /* Enables SEMAPHORE_CLK_DYN_CTRL_DISABLE */ +#define ARM_CLK_DYN_CTRL_DISABLE BIT(20) /* Enables ARM_CLK_DYN_CTRL_DISABLE */ +#define SSI_MST_SCLK_DYN_CTRL_DISABLE BIT(21) /* Enables SSI_MST_SCLK_DYN_CTRL_DISABLE */ +#define MEM1_CLK_DYN_CTRL_DISABLE BIT(22) /* Enables MEM1_CLK_DYN_CTRL_DISABLE */ +#define MEM2_CLK_DYN_CTRL_DISABLE BIT(23) /* Enables MEM2_CLK_DYN_CTRL_DISABLE */ +#define MEM_CLK_ULP_DYN_CTRL_DISABLE BIT(24) /* Enables MEM_CLK_ULP_DYN_CTRL_DISABLE */ +#define MEM3_CLK_DYN_CTRL_DISABLE BIT(25) /* Enables MEM3_CLK_DYN_CTRL_DISABLE */ +#define SSI_MST_PCLK_DYN_CTRL_DISABLE BIT(28) /* Enables SSI_MST_PCLK_DYN_CTRL_DISABLE */ +#define ICACHE_DYN_GATING_DISABLE BIT(29) /* Enables ICACHE_DYN_GATING_DISABLE */ +#define CCI_PCLK_DYN_CTRL_DISABLE BIT(30) /* Enables CCI_PCLK_DYN_CTRL_DISABLE */ +#define MISC_CONFIG_PCLK_DYN_CTRL_DISABLE BIT(31) /* Enables MISC_CONFIG_PCLK_DYN_CTRL_DISABLE */ + +/*DYN_CLK_GATE_DISABLE_REG2 */ +#define SOC_PLL_SPI_CLK_DYN_CTRL_DISABLE BIT(0) /* Enables SOC_PLL_SPI_CLK_DYN_CTRL_DISABLE */ +#define I2C_BUS_DYN_CTRL_DISABLE BIT(1) /* Enables I2C_BUS_DYN_CTRL_DISABLE */ +#define I2C_2_BUS_CLK_DYN_CTRL_DISABLE BIT(2) /* Enables I2C_2_BUS_CLK_DYN_CTRL_DISABLE */ +#define CT_PCLK_DYN_CTRL_DISABLE BIT(3) /* Enables SCT_PCLK_DYN_CTRL_DISABLE */ +#define CAN1_PCLK_DYN_CTRL_DISABLE BIT(4) /* Enables CAN1_PCLK_DYN_CTRL_DISABLE */ +#define I2SM_PCLK_DYN_CTRL_DISABLE BIT(5) /* Enables I2SM_PCLK_DYN_CTRL_DISABLE */ +#define EFUSE_CLK_DYN_CTRL_DISABLE BIT(6) /* Enables EFUSE_CLK_DYN_CTRL_DISABLE */ +#define EFUSE_PCLK_DYN_CTRL_DISABLE BIT(7) /* Enables EFUSE_PCLK_DYN_CTRL_DISABLE */ +#define PWR_CTRL_CLK_DYN_CTRL_DISABLE BIT(8) /* Enables PWR_CTRL_CLK_DYN_CTRL_DISABLE */ + +/*SOC_Pll Clock frequency checks */ +#define SOC_PLL_MIN_FREQUECY 1000000 /* Minimum frequency for SOC_PLL*/ +#define SOC_PLL_MAX_FREQUECY 300000000 /* Maximum frequency for SOC_PLL*/ + +/*SOC_Pll Clock frequency checks */ +#define INTF_PLL_MIN_FREQUECY 1000000 /* Minimum frequency for SOC_PLL*/ +#define INTF_PLL_MAX_FREQUECY 300000000 /* Maximum frequency for SOC_PLL*/ + +#define I2S_DCO_FREQ1 73728000 /* i2s_dco_freq1*/ +#define I2S_DCO_FREQ2 67737600 /* i2s_dco_freq2*/ + +/*SOCPLL_MACRO_REG_ACCESS*/ +#define SOCPLLMACROREG1 0x00 /* Address for SOCPLLMACROREG1 register Access*/ +#define SOCPLLMACROREG2 0x01 /* Address for SOCPLLMACROREG2 register Access*/ +#define SOCPLLMACROREG3 0x02 /* Address for SOCPLLMACROREG3 register Access*/ +#define SOCPLLMACROREG4 0x03 /* Address for SOCPLLMACROREG4 register Access*/ +#define SOCPLLMACROREG5 0x04 /* Address for SOCPLLMACROREG5 register Access*/ + +/*SOCPLLMACROREG*/ +#define LDO_PROG_SOCPLL (0xE000) /* Mask value for LDO_PROG_SOCPLL*/ +#define LDO_PROG_INTFPLL (0x1C00) /* Mask value for LDO_PROG_INTFPLL*/ +#define LDO_PROG_I2SPLL (0x0380) /* Mask value for LDO_PROG_I2SPLL*/ + +/* SOC_PLL_REG_ACCESS */ +#define SOC_PLL_500_CTRL_REG1 0x10 /* Address for SOC_PLL_500_CTRL_REG1 register Access*/ +#define SOC_PLL_500_CTRL_REG2 0x11 /* Address for SOC_PLL_500_CTRL_REG2 register Access*/ +#define SOC_PLL_500_CTRL_REG3 0x12 /* Address for SOC_PLL_500_CTRL_REG3 register Access*/ +#define SOC_PLL_500_CTRL_REG4 0x13 /* Address for SOC_PLL_500_CTRL_REG4 register Access*/ +#define SOC_PLL_500_CTRL_REG5 0x14 /* Address for SOC_PLL_500_CTRL_REG5 register Access*/ +#define SOC_PLL_500_CTRL_REG6 0x15 /* Address for SOC_PLL_500_CTRL_REG6 register Access*/ +#define SOC_PLL_500_CTRL_REG7 0x16 /* Address for SOC_PLL_500_CTRL_REG7 register Access*/ +#define SOC_PLL_500_CTRL_REG8 0x17 /* Address for SOC_PLL_500_CTRL_REG8 register Access*/ +#define SOC_PLL_500_CTRL_REG9 0x18 /* Address for SOC_PLL_500_CTRL_REG9 register Access*/ +#define SOC_PLL_500_CTRL_REG10 0x19 /* Address for SOC_PLL_500_CTRL_REG10 register Access*/ +#define SOC_PLL_500_CTRL_REG11 0x1A /* Address for SOC_PLL_500_CTRL_REG11 register Access*/ +#define SOC_PLL_500_CTRL_REG12 0x1B /* Address for SOC_PLL_500_CTRL_REG12 register Access*/ +#define SOC_PLL_500_CTRL_REG13 0x1C /* Address for SOC_PLL_500_CTRL_REG13 register Access*/ + +/* INTF_PLL_REG_ACCESS */ +#define INTF_PLL_500_CTRL_REG1 0x20 /* Address for INTF_PLL_500_CTRL_REG1 register Access*/ +#define INTF_PLL_500_CTRL_REG2 0x21 /* Address for INTF_PLL_500_CTRL_REG2 register Access*/ +#define INTF_PLL_500_CTRL_REG3 0x22 /* Address for INTF_PLL_500_CTRL_REG3 register Access*/ +#define INTF_PLL_500_CTRL_REG4 0x23 /* Address for INTF_PLL_500_CTRL_REG4 register Access*/ +#define INTF_PLL_500_CTRL_REG5 0x24 /* Address for INTF_PLL_500_CTRL_REG5 register Access*/ +#define INTF_PLL_500_CTRL_REG6 0x25 /* Address for INTF_PLL_500_CTRL_REG6 register Access*/ +#define INTF_PLL_500_CTRL_REG7 0x26 /* Address for INTF_PLL_500_CTRL_REG7 register Access*/ +#define INTF_PLL_500_CTRL_REG8 0x27 /* Address for INTF_PLL_500_CTRL_REG8 register Access*/ +#define INTF_PLL_500_CTRL_REG9 0x28 /* Address for INTF_PLL_500_CTRL_REG9 register Access*/ +#define INTF_PLL_500_CTRL_REG10 0x29 /* Address for INTF_PLL_500_CTRL_REG10 register Access*/ +#define INTF_PLL_500_CTRL_REG11 0x2A /* Address for INTF_PLL_500_CTRL_REG11 register Access*/ +#define INTF_PLL_500_CTRL_REG12 0x2B /* Address for INTF_PLL_500_CTRL_REG12 register Access*/ +#define INTF_PLL_500_CTRL_REG13 0x2C /* Address for INTF_PLL_500_CTRL_REG13 register Access*/ + +/* I2S_PLL_REG_ACCESS */ +#define I2S_PLL_CTRL_REG1 0x30 /* Address for I2S_PLL_CTRL_REG1 register Access*/ +#define I2S_PLL_CTRL_REG2 0x31 /* Address for I2S_PLL_CTRL_REG2 register Access*/ +#define I2S_PLL_CTRL_REG3 0x32 /* Address for I2S_PLL_CTRL_REG3 register Access*/ +#define I2S_PLL_CTRL_REG4 0x33 /* Address for I2S_PLL_CTRL_REG4 register Access*/ +#define I2S_PLL_CTRL_REG5 0x34 /* Address for I2S_PLL_CTRL_REG5 register Access*/ +#define I2S_PLL_CTRL_REG6 0x35 /* Address for I2S_PLL_CTRL_REG6 register Access*/ +#define I2S_PLL_CTRL_REG7 0x36 /* Address for I2S_PLL_CTRL_REG7 register Access*/ +#define I2S_PLL_CTRL_REG8 0x37 /* Address for I2S_PLL_CTRL_REG8 register Access*/ +#define I2S_PLL_CTRL_REG9 0x38 /* Address for I2S_PLL_CTRL_REG9 register Access*/ +#define I2S_PLL_CTRL_REG10 0x39 /* Address for I2S_PLL_CTRL_REG10 register Access*/ +#define I2S_PLL_CTRL_REG11 0x3A /* Address for I2S_PLL_CTRL_REG11 register Access*/ +#define I2S_PLL_CTRL_REG12 0x3B /* Address for I2S_PLL_CTRL_REG12 register Access*/ +#define I2S_PLL_CTRL_REG13 0x3C /* Address for I2S_PLL_CTRL_REG13 register Access*/ + +/* AFE_PLL_CTRL_REG_REG_ACCESS */ +#define AFEPLLCTRLREG1 0x07 /* Address for AFEPLLCTRLREG1 register Access*/ +#define AFEPLLCTRLREG2 0x08 /* Address for AFEPLLCTRLREG1 register Access*/ + +#define MEMS_REF_CLK_ENABLE BIT(6) + +/*SOC_PLL_500_CTRL_REG1/INTF_PLL_500_CTRL_REG1/I2S_PLL_CTRL_REG_1 */ +#define DCO_FIX_SEL_MASK (0x0003) /* Mask value for DCO_FIX_SEL_MASK*/ +#define PLL_500_BYPASS BIT(2) /* Enables PLL_500_BYPASS */ +#define PLL_500_CLK_ENABLE BIT(3) /* Enables PLL_500_CLK_ENABLE */ +#define PLL_500_PD BIT(4) /* Enables PLL_500_PD */ +#define PLL_500_RST BIT(5) /* Enables PLL_500_RST */ +#define PLL_500_M_MASK (0xFFC0) /* Mask value for PLL_500_M_MASK*/ +/*I2S_PLL_CTRL_REG_1*/ +#define I2S_PLL_CLK_ENABLE BIT(2) /* Enables I2S_PLL_CLK_ENABLE */ +#define I2S_PLL_BYPASS BIT(3) /* Enables I2S_PLL_BYPASS */ + +/*SOC_PLL_500_CTRL_REG2/INTF_PLL_500_CTRL_REG 2 */ +#define PLL_500_N_MASK (0x01F8) /* Mask value for PLL_500_N_MASK*/ +#define PLL_500_P_MASK (0xFE00) /* Mask value for PLL_500_P_MASK*/ + +/*I2S_PLL_CTRL_REG_2*/ +#define N_DIV_MASK (0x00FE) /* Mask value for N_DIV_MASK*/ +#define P_DIV2_MASK (0x0700) /* Mask value for P_DIV2_MASK*/ +#define P_DIV1_MASK (0xF800) /* Mask value for P_DIV1_MASK*/ + +/*SOC_PLL_500_CTRL_REG3/INTF_PLL_500_CTRL_REG_3/ I2S_PLL_CTRL_REG_3 */ +#define FCW_F_MASK (0xFFFC) /* Mask value for FCW_F_MASK*/ + +/*SOC_PLL_500_CTRL_REG_4/INTF_PLL_500_CTRL_REG_4 */ +#define LDO_BY_PASS BIT(1) /* Enables LDO_BY_PASS */ +#define SD_CLK_SEL_MASK (0x000C) /* Mask value for SD_CLK_SEL_MASK*/ +#define SD_LEN BIT(4) /* Enables SD_LEN */ +#define FILTER_TYPE BIT(5) /* Enables FILTER_TYPE */ +#define BETA_MASK (0x07C0) /* Mask value for BETA_MASK*/ +#define ALPHA_MASK (0xF800) /* Mask value for ALPHA_MASK*/ +/*SOC_PLL_500_CTRL_REG_5/INTF_PLL_500_CTRL_REG_5/ I2S_PLL_CTRL_REG_5 */ +#define LOCK_LIMIT_MASK (0x3FFF) /* Mask value for LOCK_LIMIT_MASK*/ +#define ENABLE_PHASE_LOCK_DETECT BIT(14) /* Enables ENABLE_PHASE_LOCK_DETECT */ +#define ENABLE_FREQ_LOCK_DETECT BIT(15) /* Enables ENABLE_FREQ_LOCK_DETECT */ +/*SOC_PLL_500_CTRL_REG_6/INTF_PLL_500_CTRL_REG_6/ I2S_PLL_CTRL_REG_6 */ +#define RETIMER_COUNT_MASK (0x00F0) /* Mask value for RETIMER_COUNT_MASK*/ +#define TDC_PWRSAV_COUNT_MASK (0x7F00) /* Mask value for TDC_PWRSAV_COUNT_MASK*/ +#define TDC_PWRSAV_EN BIT(15) /* Enables TDC_PWRSAV_EN */ + +/*SOC_PLL_500_CTRL_REG_7/INTF_PLL_500_CTRL_REG_7/ I2S_PLL_CTRL_REG_7*/ +#define SPI_INP_RD_EN BIT(4) /* Enables SPI_INP_RD_EN */ +#define OCW_MANUAL_MASK (0xFFE0) /* Mask value for OCW_MANUAL_MASK */ +#define DCO_TESTMODE BIT(15) /* Enables DCO_TESTMODE */ + +/*SOC_PLL_500_CTRL_REG_8/INTF_PLL_500_CTRL_REG_8/I2S_PLL_CTRL_REG_8 */ +#define ISOLATION_ENABLE BIT(0) /* Enables ISOLATION_ENABLE */ +#define BYPASS_ISO_GEN BIT(1) /* Enables BYPASS_ISO_GEN */ +#define BYPASS_LOCK_FLAG BIT(2) /* Enables BYPASS_LOCK_FLAG */ +#define BYPASS_PWR_GOOD BIT(3) /* Enables BYPASS_PWR_GOOD */ +#define LOCK_COUNT_LIMIT_FREQ_MASK (0x00F0) /* Mask value for LOCK_COUNT_LIMIT_FREQ_MASK */ +#define LOCK_COUNT_LIMIT_PHASE_MASK (0xFF00) /* Mask value for LOCK_COUNT_LIMIT_PHASE_MASK*/ + +/*SOC_PLL_500_CTRL_REG_9/INTF_PLL_500_CTRL_REG_9/ I2S_PLL_CTRL_REG_9 */ +#define MM_COUNT_LIMIT_MASK (0x3FC0) /* Mask value for MM_COUNT_LIMIT_MASK */ +#define BYPASS_LOCK_PLL BIT(14) /* Enables BYPASS_LOCK_PLL */ +#define MANUAL_LOCK_ENABLE BIT(15) /* Enables MANUAL_LOCK_ENABLE */ + +/*SOC_PLL_500_CTRL_REG_10/INTF_PLL_500_CTRL_REG_10/ I2S_PLL_CTRL_REG_10 */ +#define CKR_TEST_EN BIT(3) /* Enables CKR_TEST_EN */ +#define SELOUT_SA_RETIMER BIT(4) /* Enables SELOUT_SA_RETIMER */ +#define EN_STD_RETIMER BIT(5) /* Enables EN_STD_RETIMER */ +#define EN_SA_RETIMER BIT(6) /* Enables EN_SA_RETIMER */ +#define RETIMER_PWRSAV_COUNT2_MASK (0x0780) /* Mask value for RETIMER_PWRSAV_COUNT2_MASK */ +#define RETIMER_PWRSAV_COUNT1_MASK (0x7800) /* Mask value for RETIMER_PWRSAV_COUNT1_MASK */ +#define RETIMER_PWRSAV_EN BIT(15) /* Enables RETIMER_PWRSAV_EN */ + +/*SOC_PLL_500_CTRL_REG_11/INTF_PLL_500_CTRL_REG_11/ I2S_PLL_CTRL_REG_11 */ +#define PU_SD_DIV BIT(1) /* Enables PU_SD_DIV */ +#define PU_POST_DIV BIT(2) /* Enables PU_POST_DIV */ +#define PU_INP_DIV BIT(3) /* Enables PU_INP_DIV */ +#define PU_INDO BIT(4) /* Enables PU_INDO */ +#define PU_RETIMER BIT(5) /* Enables PU_RETIMER */ +#define PU_TDC BIT(6) /* Enables PU_TDC */ +#define PU_DCO BIT(7) /* Enables PU_DCO */ +#define PU_DIGITAL_TOP BIT(8) /* Enables PU_DIGITAL_TOP */ +#define RESETN_SD_DIV BIT(9) /* Enables RESETN_SD_DIV */ +#define RESETN_INP_DIV BIT(10) /* Enables RESETN_INP_DIV */ +#define RESETN_POST_DIV BIT(11) /* Enables RESETN_POST_DIV */ +#define RESETN_RETIMER BIT(12) /* Enables RESETN_RETIMER */ +#define RESETN_LOCK_DETECT BIT(13) /* Enables RESETN_LOCK_DETECT */ +#define RESETN_LOOP BIT(14) /* Enables RESETN_LOOP */ +#define RESETN_TDC BIT(15) /* Enables RESETN_TDC */ + +/*SOC_PLL_500_CTRL_REG_12/INTF_PLL_500_CTRL_REG_12/ I2S_PLL_CTRL_REG_12 */ +#define DELTF_MASK (0x003E) /* Mask value for DELTF_MASK */ +#define DELTR_MASK (0x07C0) /* Mask value for DELTR_MASK */ +#define TV_MASK (0XF800) /* Mask value for TV_MASK */ + +/*SOC_PLL_500_CTRL_REG_13/INTF_PLL_500_CTRL_REG_13/ I2S_PLL_CTRL_REG_13*/ +#define OCW_MASK (0x3FF0) /* Mask value for OCW_MASK */ +#define LOCK_FLAG_PHASE BIT(14) /* Enables LOCK_FLAG_PHASE */ +#define LOCK_FLAG_FREQ BIT(15) /* Enables LOCK_FLAG_FREQ */ + +/*SOC Clock division factor checks */ +#define SOC_MAX_CLK_DIVISION_FACTOR 63 /* Maximum division factor value for SOC clock*/ +#define SOC_MIN_CLK_DIVISION_FACTOR 0 /* Minimum division factor value for SOC clock*/ + +/*SDMEM Clock division factor checks */ +#define SDMEM_MAX_CLK_DIVISION_FACTOR 63 /* Maximum division factor value for SD_MEM clock*/ +#define SDMEM_MIN_CLK_DIVISION_FACTOR 0 /* Minimum division factor value for SD_MEM clock*/ + +/*CT Clock division factor checks */ +#define CT_MAX_CLK_DIVISION_FACTOR 63 /* Maximum division factor value for CT clock*/ +#define CT_MIN_CLK_DIVISION_FACTOR 0 /* Minimum division factor value for CT clock*/ + +/*I2S Clock division factor checks */ +#define I2S_MAX_CLK_DIVISION_FACTOR 63 /* Maximum division factor value for I2S clock*/ +#define I2S_MIN_CLK_DIVISION_FACTOR 0 /* Minimum division factor value for I2S clock*/ + +/*USB Clock division factor checks */ +#define USB_MAX_CLK_DIVISION_FACTOR 3 /* Maximum division factor value for USB clock*/ +#define USB_MIN_CLK_DIVISION_FACTOR 0 /* Minimum division factor value for USB clock*/ + +/*CAN Clock division factor checks */ +#define CAN_MAX_CLK_DIVISION_FACTOR 255 /* Maximum division factor value for CAN clock*/ +#define CAN_MIN_CLK_DIVISION_FACTOR 0 /* Minimum division factor value for CAN clock*/ + +/*I2S Clock division factor checks */ +#define MCU_CLKOUT_MAX_CLK_DIVISION_FACTOR 63 /* Maximum division factor value for MCU_CLKOUT clock*/ +#define MCU_CLKOUT_MIN_CLK_DIVISION_FACTOR 0 /* Minimum division factor value for MCU_CLKOUT clock*/ +#define MCU_CLKOUT_SEL_MAX 15 /* Maximum Seletion value for MCU_CLKOUT clock source*/ + +/*QSPI Clock Division factor checks */ +#define QSPI_MAX_CLK_DIVISION_FACTOR 63 /* Maximum division factor value for QSPI clock*/ +#define QSPI_MIN_CLK_DIVISION_FACTOR 0 /* Minimum division factor value for QSPI clock*/ + +/*USART Clock Division factor checks */ +#define USART_MAX_CLK_DIVISION_FACTOR 15 /* Maximum division factor value for USART clock*/ +#define USART_MIN_CLK_DIVISION_FACTOR 0 /* Minimum division factor value for USART clock*/ + +/*SSI Clock Division factor checks */ +#define SSI_MAX_CLK_DIVISION_FACTOR 15 /* Maximum division factor value for SSI clock*/ +#define SSI_MIN_CLK_DIVISION_FACTOR 0 /* Minimum division factor value for SSI clock*/ + +/*CCI Clock Division factor checks */ +#define CCI_MAX_CLK_DIVISION_FACTOR 15 /* Maximum division factor value for CCI clock*/ +#define CCI_MIN_CLK_DIVISION_FACTOR 0 /* Minimum division factor value for CCI clock*/ + +/*PLL_INTF Clock Division factor checks */ +#define PLL_INTF_MAX_CLK_DIVISION_FACTOR 15 /* Maximum division factor value for PLL_INTF clock*/ +#define PLL_INTF_MIN_CLK_DIVISION_FACTOR 0 /* Minimum division factor value for PLL_INTF clock*/ + +/*Sleep Clock selection checks */ +#define SLP_MAX_SEL 3 /* Maximum Seletion value for Sleep clock source*/ +#define SLP_MIN_SEL 0 /* Minimum Seletion value for Sleep clock source*/ + +#define MAX_SLP_CYCLES 3 /* Maximum Cycles for Sleep clock*/ +#define MIN_SLP_CYCLES 0 /* Minimum Cycles for Sleep clock*/ + +#define MISC_CFG_MISC_CTRL1 (*((uint32_t volatile *)(MISC_CONFIG_BASE + 0x44))) /* address of MISC_CFG_MISC_CTRL1 */ +#define I2S_MASTER_SLAVE_MODE (1 << 23) /* Sets I2S/I2S PCM master mode */ + +#define MCU_ULP_40MHZ_CLK_EN_TRUN_ON_DELAY 10 /* delay to enable the ULP 40MHZ CLK*/ +#define MCU_ULP_DOUBLER_CLK_EN_TRUN_ON_DELAY 10 /* delay to enable the ULP DOUBLER CLK*/ +#define MCU_ULP_20MHZ_RING_OSC_CLK_EN_TRUN_ON_DELAY 10 /* delay to enable the ULP 20MHZ_RING_OSC CLK*/ +#define MCU_ULP_32MHZ_RC_CLK_EN_TRUN_ON_DELAY 2 /* delay to enable the ULP 32MHZ_RC CLK*/ +#define MCU_ULP_32KHZ_XTAL_CLK_EN_TRUN_ON_DELAY_1 500 /* delay to enable the ULP 32KHZ_XTAL CLK*/ +#define MCU_ULP_32KHZ_XTAL_CLK_EN_TRUN_ON_DELAY_2 1500 /* delay to enable the ULP 32KHZ_XTAL CLK*/ +#define MCU_ULP_32KHZ_RO_CLK_EN_TRUN_ON_DELAY 250 /* delay to enable the ULP 32KHZ_RO CLK*/ +#define MCU_ULP_32KHZ_RC_CLK_EN_TRUN_ON_DELAY 150 /* delay to enable the ULP 32KHZ_RC CLK*/ + +/** + *@brief Reference clock selection + **/ +typedef enum REF_CLK_ENABLE { + MCU_ULP_40MHZ_CLK_EN, /*!< Enables ULP_40MHZ_CLK when it is passed */ + MCU_ULP_DOUBLER_CLK_EN, /*!< Enables ULP_DOUBLER_CLK when it is passed */ + MCU_ULP_20MHZ_RING_OSC_CLK_EN, /*!< Enables ULP_20MHZ_RING_OSC_CLK when it is passed */ + MCU_ULP_32MHZ_RC_CLK_EN, /*!< Enables ULP_32MHZ_RC_CLK when it is passed */ + MCU_ULP_32KHZ_XTAL_CLK_EN, /*!< Enables ULP_32KHZ_XTAL_CLK when it is passed */ + MCU_ULP_32KHZ_RO_CLK_EN, /*!< Enables ULP_32KHZ_RO_CLK when it is passed */ + MCU_ULP_32KHZ_RC_CLK_EN /*!< Enables ULP_32KHZ_RC_CLK when it is passed */ +} REF_CLK_ENABLE_T; +/** + *@brief list of peripherals, particular clock that to be enabled + **/ +typedef enum PERIPHERALS_CLK { + USART1_CLK, /*!< Enables or Disables USART1 Peripheral clock when it is passed */ + USART2_CLK, /*!< Enables or Disables USART2 Master Peripheral clock when it is passed */ + SSIMST_CLK, /*!< Enables or Disables SSI Master Peripheral clock when it is passed */ + SSISLAVE_CLK, /*!< Enables or Disables SSI Slave Peripheral clock when it is passed */ + CT_CLK, /*!< Enables or Disables CT Peripheral clock when it is passed */ + SD_MEM_CLK, /*!< Enables or Disables SD_MEM Peripheral clock when it is passed */ + CCI_CLK, /*!< Enables or Disables CCI Peripheral clock when it is passed */ + QSPI_CLK, /*!< Enables or Disables QSPI Peripheral clock when it is passed */ + RPDMA_CLK, /*!< Enables or Disables RPDMA Peripheral clock when it is passed */ + UDMA_CLK, /*!< Enables or Disables UDMA Peripheral clock when it is passed */ + PWM_CLK, /*!< Enables or Disables PWM Peripheral clock when it is passed */ + CAN_CLK, /*!< Enables or Disables CAN Peripheral clock when it is passed */ + GSPI_CLK, /*!< Enables or Disables GSPI Peripheral clock when it is passed */ + EGPIO_CLK, /*!< Enables or Disables EGPIO Peripheral clock when it is passed */ + ETHERNET_CLK, /*!< Enables or Disables ETHERNET Peripheral clock when it is passed */ + MCUCLKOUT_CLK, /*!< Enables or Disables MCUCLKOUT Peripheral clock when it is passed */ + HWRNG_CLK, /*!< Enables or Disables HWRNG Peripheral clock when it is passed */ + I2SM_CLK, /*!< Enables or Disables I2SM Peripheral clock when it is passed */ +#ifdef SLI_SI917B0 + QSPI_2_CLK, /*!< Enables or Disables QSPI 2 Peripheral clock when it is passed */ +#endif +} PERIPHERALS_CLK_T; + +/** + *@brief PLL selection types + **/ +typedef enum PLL_TYPE { + SOC_PLL, /*!Copyright 2020 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +/** + * Includes + */ + +#ifndef __RSI_POWER_SAVE_H__ +#define __RSI_POWER_SAVE_H__ + +#include "rsi_error.h" +#include "base_types.h" +#include "rsi_ccp_common.h" +#include "rsi_reg_spi.h" +#include "rsi_ipmu.h" +#include "rsi_system_config.h" +#include "rsi_ccp_user_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/*M4SS peripheral power gates */ +/* M4SS_PWRCTRL_SET_REG Bits ((NPSS MCU(MCU DM POWER CTRL FF's Domain))*/ +#define M4SS_PWRGATE_ULP_EXT_ROM BIT(22) +#define M4SS_PWRGATE_ULP_M4_CORE BIT(18) +#define M4SS_PWRGATE_ULP_IID BIT(14) +#define M4SS_PWRGATE_ULP_SDIO_SPI BIT(11) +#define M4SS_PWRGATE_ULP_RPDMA BIT(9) +#if defined(SLI_SI917) +#define M4SS_PWRGATE_ULP_EFUSE_PERI BIT(4) +#define M4SS_PWRGATE_ULP_QSPI_ICACHE BIT(13) +#define M4SS_PWRGATE_ULP_M4_DEBUG_FPU BIT(17) +#else +#define M4SS_PWRGATE_ULP_EFUSE BIT(4) +#define M4SS_PWRGATE_ULP_QSPI BIT(13) +#define M4SS_PWRGATE_ULP_M4_DEBUG BIT(17) +#endif +#if defined(CHIP_9118) +#define M4SS_PWRGATE_ULP_M4_FPU BIT(16) +#define M4SS_PWRGATE_ULP_ICACHE BIT(15) +#define M4SS_PWRGATE_ULP_ETHERNET BIT(12) +#define M4SS_PWRGATE_ULP_USB BIT(10) +#define M4SS_PWRGATE_ULP_PERI1 BIT(8) +#define M4SS_PWRGATE_ULP_PERI2 BIT(7) +#define M4SS_PWRGATE_ULP_PERI3 BIT(6) +#define M4SS_PWRGATE_ULP_CCI BIT(5) +#define M4SS_PWRGATE_ULP_SD_MEM BIT(2) +#endif + +/*ULPSS Peripheral power gate */ +/* ULPSS_PWRCTRL_SET_REG bits (NPSS MCU(MCU DM POWER CTRL FF's Domain))*/ +#define ULPSS_PWRGATE_ULP_MISC BIT(18) +#define ULPSS_PWRGATE_ULP_CAP BIT(19) +#if defined(CHIP_9118) +#define ULPSS_PWRGATE_ULP_VAD BIT(20) +#endif +#define ULPSS_PWRGATE_ULP_UART BIT(21) +#define ULPSS_PWRGATE_ULP_SSI BIT(22) +#define ULPSS_PWRGATE_ULP_I2S BIT(23) +#define ULPSS_PWRGATE_ULP_I2C BIT(24) +#define ULPSS_PWRGATE_ULP_AUX BIT(25) +#define ULPSS_PWRGATE_ULP_IR BIT(26) +#define ULPSS_PWRGATE_ULP_UDMA BIT(27) +#define ULPSS_PWRGATE_ULP_FIM BIT(28) + +/*NPSS Peripheral power gates */ +/*MCUAON_NPSS_PWRCTRL_SET_REG Bits (MCU AON Domain)*/ +#define SLPSS_PWRGATE_ULP_NWPAPB_MCU_CTRL BIT(16) +#define SLPSS_PWRGATE_ULP_TIMEPERIOD BIT(10) +#define SLPSS_PWRGATE_ULP_MCUSTORE3 BIT(9) +#define SLPSS_PWRGATE_ULP_MCUSTORE2 BIT(8) +#define SLPSS_PWRGATE_ULP_MCUSTORE1 BIT(7) +#define SLPSS_PWRGATE_ULP_MCUTS BIT(6) +#define SLPSS_PWRGATE_ULP_MCUPS BIT(5) +#define SLPSS_PWRGATE_ULP_MCUWDT BIT(4) +#define SLPSS_PWRGATE_ULP_MCURTC BIT(3) +#define SLPSS_PWRGATE_ULP_MCUFSM BIT(2) +#define SLPSS_PWRGATE_ULP_MCUBFFS BIT(1) + +/*Power supply controls*/ +/*MCU_FSM_CRTL_PDM_AND_ENABLES_b(0x24) Reg Bits (MCU FSM )*/ +#define ENABLE_WDT_IN_SLEEP BIT(0) +#define ENABLE_WURX_DETECTION BIT(1) +#define RESET_MCU_BBF_DM_EN BIT(2) +#define DISABLE_TURNOFF_SRAM_PERI BIT(3) +#define ENABLE_SRAM_DS_CTRL BIT(4) +#define POWER_ENABLE_FSM_PERI BIT(16) +#define POWER_ENABLE_TIMESTAMPING BIT(17) +#define POWER_ENABLE_DEEPSLEEP_TIMER BIT(18) +#define POWER_ENABLE_RETENTION_DM BIT(19) + +/*Wake up sources configuration*/ +/*MCU_FSM_CRTL_PDM_AND_ENABLES_b(0x24) Reg Bits (MCU FSM )*/ +#define WDT_INTR_BASED_WAKEUP BIT(29) +#define MSEC_BASED_WAKEUP BIT(28) +#define SEC_BASED_WAKEUP BIT(27) +#define ALARM_BASED_WAKEUP BIT(26) +#define SDCSS_BASED_WAKEUP BIT(25) +#define ULPSS_BASED_WAKEUP BIT(24) +#ifndef SLI_SI917B0 +#define WAKEIF_BASED_WAKEUP BIT(22) +#else +#define SYSRTC_BASED_WAKEUP BIT(22) +#endif +#define COMPR_BASED_WAKEUP BIT(21) +#define GPIO_BASED_WAKEUP BIT(20) +#define M4_PROCS_BASED_WAKEUP BIT(19) +#define WIRELESS_BASED_WAKEUP BIT(18) +#define HOST_BASED_WAKEUP BIT(17) +#define DST_BASED_WAKEUP BIT(16) +#define WIC_BASED_WAKEUP BIT(23) + +/*RAM retention controls */ +/*MCU FSM SLEEP CTRLS AND WAKEUP MODE Reg(0x0) (MCU FSM)*/ +#define M4ULP_RAM16K_RETENTION_MODE_EN BIT(7) +#define ULPSS_RAM_RETENTION_MODE_EN BIT(6) +#define TA_RAM_RETENTION_MODE_EN BIT(5) +#define M4ULP_RAM_RETENTION_MODE_EN BIT(4) +#define M4SS_RAM_RETENTION_MODE_EN BIT(3) /* reserved in 917 */ +#define HPSRAM_RET_ULP_MODE_EN BIT(2) + +/*RAM banks power gate controls*/ +/* M4_SRAM_PWRCTRL_SET_REG1 reg bits((NPSS MCU(MCU DM POWER CTRL FF's Domain)) */ +#if defined(CHIP_9118) +/*These banks typically used in M4SS high power mode */ +#define RAM_BANK_0 BIT(0) /*!< RAM BANK 0 SIZE : 16K*/ +#define RAM_BANK_1 BIT(1) /*!< RAM BANK 1 SIZE : 32K*/ +#define RAM_BANK_2 BIT(2) /*!< RAM BANK 2 SIZE : 16K*/ +/*Typically used in M4 ULP mode*/ +/*m4ulp_ram16k_retention_mode_en*/ +#define RAM_BANK_3 BIT(3) /*!< RAM BANK 3 SIZE : 4K*/ +#define RAM_BANK_4 BIT(4) /*!< RAM BANK 4 SIZE : 4K*/ +#define RAM_BANK_5 BIT(5) /*!< RAM BANK 4 SIZE : 4K*/ +#define RAM_BANK_6 BIT(6) /*!< RAM BANK 4 SIZE : 4K*/ +#define RAM_BANK_7 BIT(7) /*!< RAM BANK 4 SIZE : 32K*/ +#define RAM_BANK_8 BIT(8) /*!< RAM BANK 4 SIZE : 64K*/ +#define RAM_BANK_9 BIT(9) /*!< RAM BANK 4 SIZE : 16K*/ +/*typically these banks are used in TASS */ +#define RAM_BANK_10 BIT(16) /*!< RAM BANK 4 SIZE : 16K*/ +#define RAM_BANK_11 BIT(17) /*!< RAM BANK 4 SIZE : 32K*/ +#define RAM_BANK_12 BIT(18) /*!< RAM BANK 4 SIZE : 80K*/ +#define RAM_BANK_13 BIT(19) /*!< RAM BANK 4 SIZE : 64K*/ +#else +/*These banks typically used in M4SS high power mode */ +#define RAM_BANK_0 BIT(0) /*!< 4KB (Bank1 of first 192k chunk)*/ +#define RAM_BANK_1 BIT(1) /*!< 4KB (Bank2 of first 192k chunk)*/ +#define RAM_BANK_2 BIT(2) /*!< 4KB (Bank3 of first 192k chunk)*/ +#define RAM_BANK_3 BIT(3) /*!< 4KB (Bank4 of first 192k chunk)*/ +#define RAM_BANK_4 BIT(4) /*!< 16KB (Bank 5 of first 192k chunk)*/ +#define RAM_BANK_5 BIT(5) /*!< 32KB (Bank 6-7 of first 192k chunk*/ +#define RAM_BANK_6 BIT(6) /*!< 64KB (Bank 8-11 of first 192k chunk)*/ +#define RAM_BANK_7 BIT(7) /*!< 64KB (Bank 12-15 of first 192k chunk)*/ +#define RAM_BANK_8 BIT(8) /*!< 64KB (Bank 1-4 of second 64k chunk)*/ +#define RAM_BANK_9 BIT(9) /*!< 64KB (Bank 1-4 of third 64k chunk)*/ +#endif + +/*ULPSS RAM banks power gates */ +/*ULPSS _RAM_PWRCTRL_SET_REG1 bits (NPSS MCU(MCU DM POWER CTRL FF's Domain)*/ +#define ULPSS_2K_BANK_0 BIT(0) +#define ULPSS_2K_BANK_1 BIT(1) +#define ULPSS_2K_BANK_2 BIT(2) +#define ULPSS_2K_BANK_3 BIT(3) +#if defined(CHIP_9118) +#define ULPSS_2K_BANK_4 BIT(4) +#define ULPSS_2K_BANK_5 BIT(5) +#define ULPSS_2K_BANK_6 BIT(6) +#define ULPSS_2K_BANK_7 BIT(7) +#endif + +/*Controls the PMU off delay time*/ +#define PMU_LDO_OFF_DELAY 31U + +/*LP control reg */ +#define M4LP_CTRL_REG *((volatile uint32_t *)(0x24041424)) +#define ULP_M4_CORE_CLK_ENABLE BIT(2) + +/*NPSS INTERRUPT */ +#ifndef NPSS_INTR_BASE +#define NPSS_INTR_BASE 0x12080000 +#endif // NPSS_INTR_BASE +#ifndef NPSS_INTR_MASK_SET_REG +#define NPSS_INTR_MASK_SET_REG (*(volatile uint32_t *)(NPSS_INTR_BASE + 0x00)) +#endif // NPSS_INTR_MASK_SET_REG +#ifndef NPSS_INTR_MASK_CLR_REG +#define NPSS_INTR_MASK_CLR_REG (*(volatile uint32_t *)(NPSS_INTR_BASE + 0x04)) +#endif // NPSS_INTR_MASK_CLR_REG +#ifndef NPSS_INTR_CLEAR_REG +#define NPSS_INTR_CLEAR_REG (*(volatile uint32_t *)(NPSS_INTR_BASE + 0x08)) +#endif // NPSS_INTR_CLEAR_REG +#ifndef NPSS_INTR_STATUS_REG +#define NPSS_INTR_STATUS_REG (*(volatile uint32_t *)(NPSS_INTR_BASE + 0x0C)) +#endif // NPSS_INTR_STATUS_REG +#define M4_ULP_SLP_STATUS_REG (*(volatile uint32_t *)(NPSS_INTR_BASE + 0x1C)) +#define MCU_ULP_WAKEUP BIT(0) /* To check whether it is first boot up or Wake up */ +#define NWPAON_POR_CTRL_BITS *(volatile uint32_t *)(0x41300000 + 0x3C) +#define POC_CNTRL_REG_0 BIT(0) + +/*NPSS interrupt numbers*/ +#define NPSS_TO_MCU_WDT_INTR BIT(0) +#define NPSS_TO_MCU_GPIO_INTR_0 BIT(1) +#define NPSS_TO_MCU_GPIO_INTR_1 BIT(2) +#define NPSS_TO_MCU_GPIO_INTR_2 BIT(3) +#define NPSS_TO_MCU_GPIO_INTR_3 BIT(4) +#define NPSS_TO_MCU_GPIO_INTR_4 BIT(5) + +#define NPSS_TO_MCU_CMP_INTR_1 BIT(6) +#define NPSS_TO_MCU_CMP_INTR_2 BIT(7) +#define NPSS_TO_MCU_CMP_INTR_3 BIT(8) +#define NPSS_TO_MCU_CMP_INTR_4 BIT(9) + +#define NPSS_TO_MCU_RFWAKEUP_INTR BIT(10) + +#define NPSS_TO_MCU_BOD_INTR BIT(11) +#define NPSS_TO_MCU_BUTTON_INTR BIT(12) + +#define NPSS_TO_MCU_SDC_INTR BIT(13) +#define NPSS_TO_MCU_WIRELESS_INTR BIT(14) +#define NPSS_TO_MCU_WAKEUP_INTR BIT(15) +#define NPSS_TO_MCU_ALARM_INTR BIT(16) +#define NPSS_TO_MCU_SEC_INTR BIT(17) +#define NPSS_TO_MCU_MSEC_INTR BIT(18) +#define NPSS_TO_MCU_PROCESSOR_INTR BIT(19) +#define NPSS_TO_MCU_HOST_INTR BIT(20) +#define NPSS_TO_MCU_DST_INTR BIT(21) + +#define ENABLE_NEGEDGE_ULP BIT(1) +#define ULP_MODE_SWITCHED_NPSS BIT(3) +#define ULP_MODE_AFTR_CLK_SW BIT(2) + +/*wake up status register */ +/*MCU_FSM_WAKEUP_STATUS_REG Reg(0x38) (MCU FSM)*/ +#define CDBG_POWER_UP_REQUEST_WAKEUP BIT(6) +#define WATCH_DOG_WINDOW_RESET_INTERRUPT BIT(5) +#define WWD_RESET_LOOKUP_WAKEUP BIT(4) +#define WATCHDOG_RESET_INTERRUPT BIT(3) +#define HOST_BASED_WAKEUP_S BIT(2) +#define TIMEOUT_WAKEUP BIT(1) +#define WAKEUP_INDICATION BIT(0) + +/*wake up status clear register */ +/*MCU_FSM_WAKEUP_STATUS_CLEAR Reg(0x3C) (MCU FSM)*/ +#define MCU_WAKEUP_INTERRUPT BIT(11) +#define RF_WAKEUP_CLEAR BIT(10) +#define COMP6_BASED_WAKEUP_STATUS_CLEAR BIT(9) +#define COMP5_BASED_WAKEUP_STATUS_CLEAR BIT(8) +#define COMP4_BASED_WAKEUP_STATUS_CLEAR BIT(7) +#define COMP3_BASED_WAKEUP_STATUS_CLEAR BIT(6) +#define COMP2_BASED_WAKEUP_STATUS_CLEAR BIT(5) +#define COMP1_BASED_WAKEUP_STATUS_CLEAR BIT(4) +#define RTC_ALARM_BASED_WAKEUP_STATUS_CLEAR BIT(3) +#define RTC_SEC_BASED_STATUS_CLEAR BIT(2) +#define MILLI_SEC_BASED_STATUS_CLEAR BIT(1) +#define WWD_INTERRUPT_STATUS_CLEAR BIT(0) + +/*PMU status configuration bits */ +/* MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE Reg bits (0x0)(MCU FSM)*/ +#define PMU_STS_DCDC_ON BIT(10) +#define PMU_STS_FLASH_LDO_ON BIT(9) +#define PMU_STS_SOC_LDO_ON BIT(8) + +/*PMU */ +//#define STANDBY_DC1P3_R BIT(19) +#define STANDBY_LDOSOC_R BIT(18) +#define STANDBY_LDORF_R BIT(17) +#define BGPMU_SLEEP_EN_R BIT(16) + +/*Retention sleep configurations*/ +#ifdef SLI_SI917B0 + +//!PSRAM only initialized upon wakeup and it branches to PSRAM +#define SL_SI91X_MCU_WAKEUP_PSRAM_MODE 1 + +//!PSRAM and FLASH both will be initialized upon wake up,BIT4 refers to program flash upon wakeup +#define RSI_WAKEUP_FROM_FLASH_MODE (0x1 | (BIT(4))) +#else +#define RSI_WAKEUP_FROM_FLASH_MODE 1 +#endif +#define RSI_WAKEUP_WITH_OUT_RETENTION 2 +#define RSI_WAKEUP_WITH_RETENTION 3 +#define RSI_WAKEUP_WITH_RETENTION_WO_ULPSS_RAM 4 +#define RSI_WAKEUP_WO_RETENTION_WO_ULPSS_RAM 5 + +//!Retention ram content ulp memory start ,end addresses for power save retention sleep cases +#define RETEN_RAM_CONTENT_START_LOCATION (*(volatile uint32_t *)(0x24061F00)) +#define RETEN_RAM_CONTENT_END_LOCATION (*(volatile uint32_t *)(0x24061FCC)) +#define RETEN_RAM_CONTENT_WAKEUP_FLASH_BIT_LOCATION (*(volatile uint32_t *)(0x24061FC8)) + +#define ICACHE2_ADDR_TRANSLATE_1_REG *(volatile uint32_t *)(0x20280000 + 0x24) // ICACHE address register +#ifndef MISC_CFG_SRAM_REDUNDANCY_CTRL +#define MISC_CFG_SRAM_REDUNDANCY_CTRL *(volatile uint32_t *)(0x46008000 + 0x18) // Misc config register +#endif +#ifndef MISC_CONFIG_MISC_CTRL1 +#define MISC_CONFIG_MISC_CTRL1 *(volatile uint32_t *)(0x46008000 + 0x44) // Misc control register +#endif +#define P2P_STATUS_REGISTER *(volatile uint32_t *)(0x46008000 + 0x174) // P2P status register +#define M4SS_P2P_INTR_SET_REGISTER *(volatile uint32_t *)(0x46008000 + 0x16C) // P2P interrupt set register + +typedef enum FSM_CLK { FSM_NO_CLOCK = 0, FSM_20MHZ_RO = 1, FSM_32MHZ_RC = 2, FSM_40MHZ_XTAL = 4 } FSM_CLK_T; + +typedef enum AON_CLK { KHZ_RO_CLK_SEL = 1, KHZ_RC_CLK_SEL = 2, KHZ_XTAL_CLK_SEL = 4 } AON_CLK_T; + +/*Ship modes*/ +typedef enum SHUT_DOWN_WKP_MODE { + NPSS_GPIO_2_BASED = 0, + NPSS_GPIO_1_BASED = 1, + NPSS_GPIO_2_AND_3_BASED = 2, + NPSS_GPIO_2_OR_3_BASED = 3, +} SHUT_DOWN_WKP_MODE_T; + +/// @brief Peri efuse power state +typedef enum { POWER_DOWN, POWER_UP } peri_efuse_power_state_t; + +/*m4ss context switch top ULP mode selection */ +typedef enum ULP_MODE { ULP_MCU_MODE = 1, UULP_MCU_MODE = 3 } ULP_MODE_T; + +/*NPSS Comparator selection*/ +typedef enum NPSS_COMPARATOR { + NPSS_CMP_1, + NPSS_CMP_2, + NPSS_CMP_3, + NPSS_CMP_4, + NPSS_CMP_5, +} NPSS_COMPARATOR_T; + +#define _SOC_LDO 3 +#define MCU_SOC_LDO_LVL BIT(17) +#define MCU_DCDC_LVL BIT(18) + +/*Select value for ULPSS RAM Power MUX*/ +#define PWR_MUX_SEL_ULPSSRAM_SOC_LDO 3 +#define PWR_MUX_SEL_ULPSSRAM_SCDC_0_9 1 +#define PWR_MUX_SEL_ULPSSRAM_SCDC_0_6 0 + +/*Select value for M4 ULP RAM Power MUX*/ +#define PWR_MUX_SEL_M4_ULP_RAM_SOC_LDO 3 +#define PWR_MUX_SEL_M4_ULP_RAM_SCDC_0_9 1 +#define PWR_MUX_SEL_M4_ULP_RAM_SCDC_0_6 0 + +/*Select value for M4 ULP RAM 16K Power MUX*/ +#define PWR_MUX_SEL_M4_ULP_RAM16K_SOC_LDO 3 +#define PWR_MUX_SEL_M4_ULP_RAM16K_SCDC_0_9 1 +#define PWR_MUX_SEL_M4_ULP_RAM16K_SCDC_0_6 0 + +/*Select value for M4 ULP (Cortex Core)Power MUX*/ +#define PWR_MUX_SEL_M4ULP_SOC_LDO 3 +#define PWR_MUX_SEL_M4ULP_SCDC_0_9 1 +#define PWR_MUX_SEL_M4ULP_SCDC_0_6 0 + +/*Select value for ULPSS (Peripherals)Power MUX*/ +#define PWR_MUX_SEL_ULPSS_SOC_LDO 1 +#define PWR_MUX_SEL_ULPSS_SCDC_0_9 0 + +/*BG SAMPLE ENABLE AND DISABLE /ENABLE MACROS*/ +#define ENABLE_BG_SAMPLE_ENABLE 1 +#define DISABLE_BG_SAMPLE_ENABLE 0 + +/*DC DC ENABLE AND DISABLE /ENABLE MACROS*/ +#define ENABLE_DC_DC_ENABLE 1 +#define DISABLE_DC_DC_ENABLE 0 + +/*SOC LDO ENABLE AND DISABLE /ENABLE MACROS*/ +#define ENABLE_SOCLDO_ENABLE 1 +#define DISABLE_SOCLDO_ENABLE 0 + +/*STAND BY ENABLE AND DISABLE /ENABLE MACROS*/ +#define ENABLE_STANDBYDC 1 +#define DISABLE_STANDBYDC 0 + +/* TA 192K RAM RETENTION MODE ENABLE in PS2 */ +#define ENABLE_TA192K_RAM_RET 1 +#define DISABLE_TA192K_RAM_RET 0 + +/* M4 64K RAM RETENTION MODE ENABLE in PS2 */ +#define ENABLE_M464K_RAM_RET 1 +#define DISABLE_M464K_RAM_RET 0 + +#define NWP_FSM_CLOCKS_SELECT *(volatile uint32_t *)0x41300114 +#define ENABLE_RO_32KHz_N_RO_20MHz 0x9 + +#define NWP_FSM_CLK_EN_AND_FIRST_BOOTUP *(volatile uint32_t *)0x41300120 +#define DISABLE_ULP_CLKS 0x790000 + +#define NWPAON_NPSS_PWRCTRL_CLEAR_REG *(volatile uint32_t *)0x4130000C +#define PWRGATE_EN_N_ULP_NWPDOMAINS 0x78 + +#define STANDBY_DC1P3 BIT(19) +#define BGPMU_SLEEP_EN BIT(1) +#define SCDCDC_LP_MODE_EN BIT(0) +#define NWP_PMU_CTRLS *(volatile uint32_t *)0x41300140 + +#define TASS_REF_CLOCK_SELECT *(volatile uint32_t *)0x41300110 +#define TASS_REF_CLK_CLEANER_OFF BIT(22) +#define TASS_REF_CLK_CLEANER_ON BIT(23) + +#define TASS_PMU_LDO_CTRL_CLEAR *(volatile uint32_t *)0x41300424 +#define TASS_SOC_LDO_LVL BIT(17) +#define TASS_DCDC_LVL BIT(18) + +#define RF_AFE_PWR_CTRL_REG *(volatile uint32_t *)0x41300480 +#define RF2G_SHUTDOWN BIT(5) + +#define RF_AFE_PWR_CTRL_REG *(volatile uint32_t *)0x41300480 +#define RF2G_PG_EN BIT(7) +#define AFE_PG_EN BIT(1) + +#define TASS_M4SS_CRTL_SET_REG *(volatile uint32_t *)0x41300470 +#define TASS_CTRL_SOCPLL_SPI_PG_EN BIT(20) + +#define MODEM_BAND1_PWRCTRL_CLEAR_REG *(volatile uint32_t *)0x41300408 +#define MODEM_EXT_PWRGATE_EN_N_ULP_BBP_WLAN_GAINLUT BIT(28) +#define MODEM_EXT_PWRGATE_EN_N_ULP_BBP_TXPPLUT BIT(24) +#define MODEM_EXT_PWRGATE_EN_N_ULP_PPE_SHARED BIT(20) +#define MODEM_EXT_PWRGATE_EN_N_ULP_PPE_IMDM BIT(16) + +#define MODEM_ZBBT_PWRCTRL_CLEAR_REG *(volatile uint32_t *)0x41300418 +#define MODEM_EXT_PWRGATE_EN_N_ULP_BBP_ZBBT_GAINLUT BIT(4) + +#define NWP_RTC_TIMER_CLOCK_PERIOD_SOC *(volatile uint32_t *)(0x41300204) +#define RTC_TIMER_CLK_PERIOD_VALUE 0x003E7FFF + +#define SPI_RTC_TIMER_CLK_PERIOD_APPLIED BIT(31) + +#define NWP_FSM_SLEEP_WAKEUP_MODES *(volatile uint32_t *)0x41300100 +#define COUNT_TICK_ENABLE 0x1 +#ifdef SLI_SI917B0 +#define MCURET_BOOTSTATUS_REG *(volatile uint32_t *)(MCU_NPSS_BASE_ADDR + 0x604) +#define KEY_SIZE_IN_DWORDS 8 + +#define RSI_WAKE_FROM_FLASH_CB_START_ADDR 0x24061F00 + +#define STACK_AND_CB_ADDR_PRESENT_IN_BBFF BIT(20) + +#define RSI_WAKE_FROM_FLASH_JUMP_ADDR 0x24061F28 + +#define STACK_AND_CB_ADDR_BIT_NO 12 +#define QSPI_KEY_SIZE_256 BIT(16) +#define PSRAM_SEC_EN BIT(23) +#define KEY_LENGTH BIT(11) +#define PSRAM_SEC_EN BIT(23) +#define M4SS_PSRAM_QSPI_BASE_ADDRESS 0x12040000 +#endif + +#define MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE_REG *(volatile uint32 *)(0x24048100 + 0x0) +#define LDO_FLASH_ON BIT(9) +#define PMU_DCDC_ON BIT(10) + +/** @addtogroup SOC2 +* @{ +*/ +/** + * @fn STATIC INLINE rsi_error_t ps_power_state_change_ps4tops2( ULP_MODE_T enCtxSel , + * uint8_t PwrMuxSelUlpssRam , + * uint8_t pwrMuxSelM4UlpRam , + * uint8_t pwrMuxSelM4UlpRam16K , + * uint8_t pwrMuxSelM4Ulp , + * uint8_t pwrMuxSelUlpss , + * uint8_t bgSampleEnable , + * uint8_t dcDcEnable , + * uint8_t socLdoEnable , + * uint8_t standByDc + * ) + * @brief This API is used to used to change the power transition state from Power save state 4/3 to power save state 2 + * @param[in] enCtxSel : is Select enum for the context top ULP mode + * \n 00, 10 - \ref HP-MCU/LP-MCU Mode + * \n 01 - \ref ULP-MCU Mode + * \n 11 - \ref UULP-MCU Mode + * \n (1st 16K of M4 RAM is dedicated to IM, + * \n 2nd 16K of M4 RAM is dedicated to DM) + * @param[in] pwrMuxSelM4UlpRam : Select value for M4 ULP RAM Power MUX + * \n 3 \ref SOC LDO + * \n 1 \ref SCDCDC 0.9 + * \n 0 \ref SCDCDC 0.6 + * @param[in] PwrMuxSelUlpssRam :Select value for ULPSS RAM Power MUX + * \n 3 \ref SOC LDO + * \n 1 \ref SCDCDC 0.9 + * \n 0 \ref SCDCDC 0.6 + * @param[in] pwrMuxSelM4UlpRam16K : is Select value for M4 ULP RAM 16K Power MUX + * \n 3 \ref SOC LDO + * \n 1 \ref SCDCDC 0.9 + * \n 0 \ref SCDCDC 0.6 + * @param[in] pwrMuxSelM4Ulp : is Select value for M4 ULP (Peripherals + CORTEX Core )Power MUX + * \n 3 \ref SOC LDO + * \n 1 \ref SCDCDC 0.9 + * \n 0 \ref SCDCDC 0.6 + * @param[in] pwrMuxSelUlpss : is Select value for ULPSS(Peripherals) Power MUX + * \n 1 \ref SOC LDO + * \n 0 \ref SCDCDC 0.9 + * @param[in] bgSampleEnable : Value to enable or disable the bg Sample + * \n 0 :Disable + * \n 1 :Enale + * @param[in] dcDcEnable : Value to enable or disable the dcDcEnable + * \n 0 :Disable + * \n 1 :Enale + * @param[in] socLdoEnable : Value to enable or disable the socLdoEnable + * \n 0 :Disable + * \n 1 :Enale + * @param[in] standByDc : Value to enable or disable the standByDc + * \n 0 :Disable + * \n 1 :Enale + * @return returns 0 \ref RSI_OK on success,return error code on error + */ +STATIC INLINE rsi_error_t ps_power_state_change_ps4tops2(ULP_MODE_T enCtxSel, + uint8_t PwrMuxSelUlpssRam, + uint8_t pwrMuxSelM4UlpRam, + uint8_t pwrMuxSelM4UlpRam16K, + uint8_t pwrMuxSelM4Ulp, + uint8_t pwrMuxSelUlpss, + uint8_t bgSampleEnable, + uint8_t dcDcEnable, + uint8_t socLdoEnable, + uint8_t standByDc) +{ + volatile int x = 0; + + /*return error if this function is called from PS2*/ + if (M4_ULP_SLP_STATUS_REG & ULP_MODE_SWITCHED_NPSS) { + return ERROR_PS_INVALID_STATE; + } + + /*Static clock enable m4 core in ULP mode*/ + M4LP_CTRL_REG |= ULP_M4_CORE_CLK_ENABLE; + + /*flushes the transactions in the Bridge before transition to PS2 state*/ + x = (int)ULPCLK->ULP_TA_CLK_GEN_REG; + /*Select the MCU mode*/ + MCU_FSM->MCU_FSM_PERI_CONFIG_REG_b.M4SS_CONTEXT_SWITCH_TOP_ULP_MODE = enCtxSel; + + /*Avoid the junk system bus access*/ + for (x = 0; x < 10; x++) { + __ASM("NOP"); + } + /* + Indicates the status of functional switching to ULP Mode operation + 0 - PS4 state + 1 - PS2 state + */ + do { + /*wait for status of functional switching to ULP Mode operation*/ + x++; + } while ((M4_ULP_SLP_STATUS_REG & ULP_MODE_AFTR_CLK_SW) != ULP_MODE_AFTR_CLK_SW); + + /*Select value for ULPSS RAM Power Mux*/ + MCU_FSM->MCU_FSM_POWER_CTRL_AND_DELAY_b.POWER_MUX_SEL_ULPSS_RAM = (unsigned int)(PwrMuxSelUlpssRam & 0x3); + /*Select value for M4 ULP RAM Power Mux*/ + MCU_FSM->MCU_FSM_POWER_CTRL_AND_DELAY_b.POWER_MUX_SEL_M4_ULP_RAM = (unsigned int)(pwrMuxSelM4UlpRam & 0x3); + /*Select value for M4 ULP RAM 16K Power Mux*/ + MCU_FSM->MCU_FSM_POWER_CTRL_AND_DELAY_b.POWER_MUX_SEL_M4_ULP_RAM_16K = (unsigned int)(pwrMuxSelM4UlpRam16K & 0x3); + /*Select value for M4 ULP (Peripherals + Cortex Core )Power Mux*/ + MCU_FSM->MCU_FSM_POWER_CTRL_AND_DELAY_b.POWER_MUX_SEL_M4_ULP = (unsigned int)(pwrMuxSelM4Ulp & 0x3); + /*Select value for ULPSS(Peripherals) Power Mux*/ + MCU_FSM->MCU_FSM_POWER_CTRL_AND_DELAY_b.POWER_MUX_SEL_ULPSS = (unsigned int)(pwrMuxSelUlpss & 0x1); + + /*update the SOC LDO*/ + MCU_FSM->MCU_FSM_POWER_CTRL_AND_DELAY_b.FSM_PERI_SOC_LDO_EN = (unsigned int)(socLdoEnable & 0x1); + + if (socLdoEnable == 1) { + MCU_FSM->MCU_FSM_POWER_CTRL_AND_DELAY_b.FSM_PERI_DCDC_EN = 1; + MCU_FSM->MCU_FSM_PERI_CONFIG_REG_b.BGPMU_SAMPLING_EN_R = 0; + } + + else { + MCU_FSM->MCU_FSM_POWER_CTRL_AND_DELAY_b.FSM_PERI_DCDC_EN = (unsigned int)(socLdoEnable & 0x1); + } + + if (dcDcEnable == 1) { + MCU_FSM->MCU_FSM_POWER_CTRL_AND_DELAY_b.FSM_PERI_DCDC_EN = (unsigned int)(dcDcEnable & 0x1); + MCU_FSM->MCU_FSM_PERI_CONFIG_REG_b.BGPMU_SAMPLING_EN_R = 0; + } else { + MCU_FSM->MCU_FSM_POWER_CTRL_AND_DELAY_b.FSM_PERI_DCDC_EN = (unsigned int)(dcDcEnable & 0x1); + MCU_FSM->MCU_FSM_PERI_CONFIG_REG_b.BGPMU_SAMPLING_EN_R = (unsigned int)(bgSampleEnable & 0x1); + } + + if ((socLdoEnable == 0) && (dcDcEnable == 1)) { + MCU_FSM->MCU_FSM_PMU_STATUS_REG_b.STANDBY_DC1P3_R = (unsigned int)(standByDc & 0x1); + } + /*Set the LDO turn off delay*/ + + /*PMU off delay */ + MCU_FSM->MCU_FSM_POWER_CTRL_AND_DELAY_b.PS2_PMU_LDO_OFF_DELAY = PMU_LDO_OFF_DELAY; + +#ifndef SLI_SI917 + /*Bridge clock disable*/ + ULPCLK->ULP_TA_CLK_GEN_REG_b.ULP2M4_A2A_BRDG_CLK_EN_b = 0; +#endif + + /*Set ulp mode isolation */ + BATT_FF->M4_ULP_MODE_CONFIG = (BATT_FF->M4_ULP_MODE_CONFIG | 0x3F); + + /* Setting RETN_LDO voltage to 0.75V */ + RSI_IPMU_RetnLdo0p75(); + + /* enabling the RETN_LDO HP MODE */ + RSI_IPMU_RetnLdoHpmode(); + + /*Enable the ULP mode */ + MCU_FSM->MCU_FSM_PERI_CONFIG_REG_b.ULP_MCU_MODE_EN = 1; + + /* Wait for Status bit indicating Physical transition from PS2 to PS4*/ + do { + /*wait for status of Physical switching to ULP Mode operation*/ + x++; + } while ((M4_ULP_SLP_STATUS_REG & ULP_MODE_SWITCHED_NPSS) != ULP_MODE_SWITCHED_NPSS); + + return RSI_OK; +} + +/** + * @fn STATIC INLINE rsi_error_t ps_power_state_change_ps2_to_Ps4(uint32_t PmuBuckTurnOnWaitTime , uint32_t SocLdoTurnOnWaitTime) + * @brief This API is used to change the power state from PS2 to PS4 + * @param[in] PmuBuckTurnOnWaitTime : PMU buck time + * @param[in] SocLdoTurnOnWaitTime : soc ldo turn on time + * @return returns 0 \ref RSI_OK on success,return error code on error + */ +STATIC INLINE rsi_error_t ps_power_state_change_ps2_to_Ps4(uint32_t PmuBuckTurnOnWaitTime, + uint32_t SocLdoTurnOnWaitTime) +{ + uint8_t x; + /*Return if this is issues in PS4 state */ + if (!(M4_ULP_SLP_STATUS_REG & ULP_MODE_SWITCHED_NPSS)) { + return ERROR_PS_INVALID_STATE; + } +#ifdef CHIP_9118 + /*Disables clock to ULP-M4SS AHB-AHB Bridge since the MCU is in PS2 state logically*/ + ULPCLK->ULP_TA_CLK_GEN_REG_b.ULP2M4_A2A_BRDG_CLK_EN_b = 0; +#endif + /*Select value for ULPSS RAM Power Mux*/ + MCU_FSM->MCU_FSM_POWER_CTRL_AND_DELAY_b.POWER_MUX_SEL_ULPSS_RAM = _SOC_LDO; + /*Select value for M4 ULP RAM Power Mux*/ + MCU_FSM->MCU_FSM_POWER_CTRL_AND_DELAY_b.POWER_MUX_SEL_M4_ULP_RAM = _SOC_LDO; + /*Select value for M4 ULP RAM 16K Power Mux*/ + MCU_FSM->MCU_FSM_POWER_CTRL_AND_DELAY_b.POWER_MUX_SEL_M4_ULP_RAM_16K = _SOC_LDO; + /*Select value for M4 ULP (Peripherals + Cortex Core )Power Mux*/ + MCU_FSM->MCU_FSM_POWER_CTRL_AND_DELAY_b.POWER_MUX_SEL_M4_ULP = _SOC_LDO; + /*Select value for ULPSS(Peripherals) Power Mux*/ + MCU_FSM->MCU_FSM_POWER_CTRL_AND_DELAY_b.POWER_MUX_SEL_ULPSS = 0x01; + + MCU_FSM->MCU_FSM_POWER_CTRL_AND_DELAY_b.PG4_BUCK_ON_DELAY = (unsigned int)(PmuBuckTurnOnWaitTime & 0xF); + MCU_FSM->MCU_FSM_POWER_CTRL_AND_DELAY_b.PS4_SOCLDO_ON_DELAY = (unsigned int)(SocLdoTurnOnWaitTime & 0xF); + + MCU_FSM->MCU_FSM_PMU_STATUS_REG_b.STANDBY_DC1P3_R = 0; + + /*Disable the ULP mode */ + MCU_FSM->MCU_FSM_PERI_CONFIG_REG_b.ULP_MCU_MODE_EN = 0; + // NOTE : nopes issue issue is fixed by adding this bit + /* Wait for Status bit indicating Physical transition from PS2 to PS4*/ + /*Avoid the junk system bus access*/ + for (x = 0; x < 10; x++) { + __ASM("NOP"); + } + + while ((M4_ULP_SLP_STATUS_REG & ULP_MODE_SWITCHED_NPSS)) + ; + + /*Disable ulp mode isolation */ + BATT_FF->M4_ULP_MODE_CONFIG = (uint32_t)((BATT_FF->M4_ULP_MODE_CONFIG) & (uint32_t)(~(0x3F))); + +#ifndef SLI_SI917 + /*Disables clock to ULP-M4SS AHB-AHB Bridge since the MCU is in PS2 state logically*/ + ULPCLK->ULP_TA_CLK_GEN_REG_b.ULP2M4_A2A_BRDG_CLK_EN_b = 1; +#endif + + /*Select the MCU mode*/ + MCU_FSM->MCU_FSM_PERI_CONFIG_REG_b.M4SS_CONTEXT_SWITCH_TOP_ULP_MODE = 0; + // NOTE : nopes issue issue is fixed by adding this bit + /* Wait for Status bit indicating Functional transition from PS4 to PS2*/ + while ((M4_ULP_SLP_STATUS_REG & ULP_MODE_AFTR_CLK_SW)) + ; + + /* Setting RETN_LDO voltage to 0.7V */ + RSI_IPMU_RetnLdoVoltsel(); + + /* enabling the RETN_LDO LP MODE */ + RSI_IPMU_RetnLdoLpmode(); +#ifndef SLI_SI917 + M4CLK->CLK_ENABLE_SET_REG1_b.M4SS_UM_CLK_STATIC_EN_b = 0x1; +#endif + for (x = 0; x < 200; x++) { + __ASM("NOP"); + } +#ifndef SLI_SI917 + M4CLK->CLK_ENABLE_CLR_REG1_b.M4SS_UM_CLK_STATIC_EN_b = 0x1; +#endif + return RSI_OK; +} +/** + * \ingroup RSI_SPECIFIC_DRIVERS + * \defgroup RSI_POWER_SAVE + * @{ + * + */ +/** + * @fn STATIC INLINE void RSI_PS_PowerStateChangePs4toPs3(void) + * @brief This API is used to Change the power state from PS4 to PS3 + * \n + * \ref MCU_PMU_LDO_CTRL_CLEAR + */ +STATIC INLINE void RSI_PS_PowerStateChangePs4toPs3(void) +{ + //FIXME: programming SOC LDO voltage high/low values who needs to program? + /*Clear the MCU_SOC_LDO_LVL */ + BATT_FF->MCU_PMU_LDO_CTRL_CLEAR = MCU_SOC_LDO_LVL; +} + +/** + * @fn STATIC INLINE void RSI_PS_SetDcDcToHigerVoltage(void) + * @brief This API is used configure DCDC to give higher output voltage. + * \n + * \ref MCU_PMU_LDO_CTRL_SET + */ +STATIC INLINE void RSI_PS_SetDcDcToHigerVoltage(void) +{ + BATT_FF->MCU_PMU_LDO_CTRL_SET = MCU_DCDC_LVL; +} + +/** + * @fn STATIC INLINE void RSI_PS_SetDcDcToLowerVoltage(void) + * @brief This API is used configure DCDC to give lower output voltage. + * \n + * \ref MCU_PMU_LDO_CTRL_CLEAR + */ +STATIC INLINE void RSI_PS_SetDcDcToLowerVoltage(void) +{ + BATT_FF->MCU_PMU_LDO_CTRL_CLEAR = MCU_DCDC_LVL; +} + +/** + * @fn STATIC INLINE void RSI_PS_PowerStateChangePs3toPs4(void) + * @brief This API is used to Change the power state from PS3 to PS4 + * \n + * \ref MCU_PMU_LDO_CTRL_SET + */ +STATIC INLINE void RSI_PS_PowerStateChangePs3toPs4(void) +{ + BATT_FF->MCU_PMU_LDO_CTRL_SET = MCU_SOC_LDO_LVL; + return; +} + +/** + * @fn STATIC INLINE void RSI_PS_M4ssPeriPowerDown(uint32_t mask) + * @brief This API is used to power gate the M4SS peripherals + * @param[in] mask OR'ed value of the power gates + * \n + * \ref M4SS_PWRCTRL_CLEAR_REG + * @return none + */ +STATIC INLINE void RSI_PS_M4ssPeriPowerDown(uint32_t mask) +{ + BATT_FF->M4SS_PWRCTRL_CLEAR_REG = mask; +} + +/** + * @fn STATIC INLINE void RSI_PS_M4ssPeriPowerUp(uint32_t mask) + * @brief This API is used to un power gate the M4SS peripherals + * @param[in] mask OR'ed value of the power gates + * \n + * \ref M4SS_PWRCTRL_SET_REG + * @return none + */ +STATIC INLINE void RSI_PS_M4ssPeriPowerUp(uint32_t mask) +{ + BATT_FF->M4SS_PWRCTRL_SET_REG = mask; +} + +/** + * @fn STATIC INLINE void sl_si91x_peri_efuse_power_control(bool power_up) + * @brief This API is used to power gate the PERI_EFUSE power domain, This power domain contains the different M4SS peripherals those are + * SPI/SSI Master, I2C, USART, Micro-DMA Controller, UART, SPI/SSI Slave, Generic-SPI Master, Config Timer, Random-Number Generator, + * CRC Accelerator, SIO, I2C, I2S Master/Slave, QEI, MCPWM ,EFUSE and MVP + * @param[in] power_up 1 - Power Up the EFUSE Peri Power domain + * 0 - Power Down the EFUSE Peri power domain + * @return none + */ +STATIC INLINE void sl_si91x_peri_efuse_power_state_control(peri_efuse_power_state_t power_up) +{ + if (power_up) { + RSI_PS_M4ssPeriPowerUp(M4SS_PWRGATE_ULP_EFUSE_PERI); + } else { + RSI_PS_M4ssPeriPowerDown(M4SS_PWRGATE_ULP_EFUSE_PERI); + } +} + +/** + * @fn STATIC INLINE void RSI_PS_M4ss_Tass_Ctrl_Clear(uint32_t mask) + * @brief This API is used to clear the M4SS TASS controls + * @param[in] mask OR'ed value of the power gates + * \n + * \ref M4SS_TASS_CTRL_CLEAR_REG + * @return none + */ +STATIC INLINE void RSI_PS_M4ss_Tass_Ctrl_Clear(uint32_t mask) +{ + BATT_FF->M4SS_TASS_CTRL_CLEAR_REG = mask; +} + +/** + * @fn STATIC INLINE void RSI_PS_UlpssPeriPowerDown(uint32_t mask) + * @brief This API is used to power gate the ULPSS peripherals + * @param[in] mask OR'ed value of the power gates + * \n + * \ref ULPSS_PWRCTRL_CLEAR_REG + * @return none + */ +STATIC INLINE void RSI_PS_UlpssPeriPowerDown(uint32_t mask) +{ + BATT_FF->ULPSS_PWRCTRL_CLEAR_REG = mask; +} + +/** + * @fn STATIC INLINE void RSI_PS_UlpssPeriPowerUp(uint32_t mask) + * @brief This API is used to un power gate the ULPSS peripherals + * @param[in] mask OR'ed value of the power domains + * \n + * \ref ULPSS_PWRCTRL_SET_REG + * @return none + */ +STATIC INLINE void RSI_PS_UlpssPeriPowerUp(uint32_t mask) +{ + BATT_FF->ULPSS_PWRCTRL_SET_REG = mask; +} + +/** + * @fn STATIC INLINE void RSI_PS_NpssPeriPowerUp(uint32_t mask) + * @brief This API is used to un power gate the NPSS peripherals + * @param[in] mask OR'ed value of the power domains + * \n + * \ref MCUAON_NPSS_PWRCTRL_SET_REG + * @return none + */ +STATIC INLINE void RSI_PS_NpssPeriPowerUp(uint32_t mask) +{ + MCU_AON->MCUAON_NPSS_PWRCTRL_SET_REG = mask; +} + +/** + * @fn STATIC INLINE void RSI_PS_NpssPeriPowerDown(uint32_t mask) + * @brief This API is used to power gate the NPSS peripherals + * @param[in] mask OR'ed value of the power domains + * \n + * \ref MCUAON_NPSS_PWRCTRL_CLEAR_REG + * @return none + */ +STATIC INLINE void RSI_PS_NpssPeriPowerDown(uint32_t mask) +{ + MCU_AON->MCUAON_NPSS_PWRCTRL_CLEAR_REG = mask; +} + +/** + * @fn STATIC INLINE void RSI_PS_M4ssRamBanksPowerDown(uint32_t mask) + * @brief This API is used to power gate the M4SS RAM Banks + * @param[in] mask OR'ed value of the RAM power gates + * \n + * \ref M4_SRAM_PWRCTRL_CLEAR_REG1 + * @return none + */ +STATIC INLINE void RSI_PS_M4ssRamBanksPowerDown(uint32_t mask) +{ + BATT_FF->M4_SRAM_PWRCTRL_CLEAR_REG1 = mask; +} + +/** + * @fn STATIC INLINE void RSI_PS_M4ssRamBanksPowerUp(uint32_t mask) + * @brief This API is used to un power gate the M4SS RAM Banks + * @param[in] mask OR'ed value of the RAM power gates + * \n + * \ref M4_SRAM_PWRCTRL_SET_REG1 + * @return none + */ +STATIC INLINE void RSI_PS_M4ssRamBanksPowerUp(uint32_t mask) +{ + BATT_FF->M4_SRAM_PWRCTRL_SET_REG1 = mask; +} + +/** + * @fn STATIC INLINE uint32_t RSI_PS_M4ssRamBanksGetPowerSts(void) + * @brief This API is used to get the power gate status of M4SS RAM Banks + * \ref M4_SRAM_PWRCTRL_SET_REG1 + * @return Ored bits of M4_SRAM_PWRCTRL_SET_REG1 reg + */ +STATIC INLINE uint32_t RSI_PS_M4ssRamBanksGetPowerSts(void) +{ + return BATT_FF->M4_SRAM_PWRCTRL_SET_REG1; +} + +/** + * @fn STATIC INLINE void RSI_PS_M4ssRamBanksPeriPowerDown(uint32_t mask) + * @brief This API is used to power gate the M4SS RAM Banks periphery domain + * @param[in] mask OR'ed value of the RAM power gates + * \n + * \ref M4_SRAM_PWRCTRL_CLEAR_REG1 + * @return none + */ +STATIC INLINE void RSI_PS_M4ssRamBanksPeriPowerDown(uint32_t mask) +{ + BATT_FF->M4_SRAM_PWRCTRL_CLEAR_REG2 = mask; +} + +/** + * @fn STATIC INLINE void RSI_PS_M4ssRamBanksPeriPowerUp(uint32_t mask) + * @brief This API is used to un-power gate the M4SS RAM Banks periphery domain + * @param[in] mask OR'ed value of the RAM power gates + * \n + * \ref M4_SRAM_PWRCTRL_SET_REG1 + * @return none + */ +STATIC INLINE void RSI_PS_M4ssRamBanksPeriPowerUp(uint32_t mask) +{ + BATT_FF->M4_SRAM_PWRCTRL_SET_REG2 = mask; +} + +/** + * @fn STATIC INLINE uint32_t RSI_PS_M4ssRamBanksGetPeriPowerSts(void) + * @brief This API is used to get the power gate status of M4SS RAM Banks periphery domain + * \ref M4_SRAM_PWRCTRL_SET_REG1 + * @return Ored bits of M4_SRAM_PWRCTRL_SET_REG2 register. + */ +STATIC INLINE uint32_t RSI_PS_M4ssRamBanksGetPeriPowerSts(void) +{ + return BATT_FF->M4_SRAM_PWRCTRL_SET_REG2; +} +/** + * @fn STATIC INLINE void RSI_PS_UlpssRamBanksPeriPowerDown(uint32_t mask) + * @brief This API is used to power gate the ULPSS RAM Banks periphery domain + * @param[in] mask OR'ed value of the RAM power gates + * \n + * \ref M4_SRAM_PWRCTRL_CLEAR_REG1 + * @return none + */ +STATIC INLINE void RSI_PS_UlpssRamBanksPeriPowerDown(uint32_t mask) +{ + BATT_FF->ULPSS_RAM_PWRCTRL_CLEAR_REG3 = mask; +} + +/** + * @fn STATIC INLINE void RSI_PS_UlpssRamBanksPeriPowerUp(uint32_t mask) + * @brief This API is used to un-power gate the ULPSS RAM Banks periphery domain + * @param[in] mask OR'ed value of the RAM power gates + * \n + * \ref M4_SRAM_PWRCTRL_SET_REG1 + * @return none + */ +STATIC INLINE void RSI_PS_UlpssRamBanksPeriPowerUp(uint32_t mask) +{ + BATT_FF->ULPSS_RAM_PWRCTRL_SET_REG3 = mask; +} + +/** + * @fn STATIC INLINE void RSI_PS_SetRamRetention(uint32_t ramRetention) + * @brief This API is used to set the RAM retention enable for the RAM during sleep + * @param[in] ramRetention OR'ed value of the RAM retention bits + * \n + * \ref MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE + * @return none + */ +STATIC INLINE void RSI_PS_SetRamRetention(uint32_t ramRetention) +{ + MCU_FSM->MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE |= ramRetention; +} + +/** + * @fn STATIC INLINE void RSI_PS_ClrRamRetention(uint32_t ramRetention) + * @brief This API is used to clear the RAM retention enable for the RAM during sleep + * @param[in] ramRetention OR'ed value of the RAM retention bits + * \n + * \ref MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE + * @return none + */ +STATIC INLINE void RSI_PS_ClrRamRetention(uint32_t ramRetention) +{ + MCU_FSM->MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE &= ~ramRetention; +} + +/** + * @fn STATIC INLINE void RSI_PS_UlpssRamBanksPowerDown(uint32_t mask) + * @brief This API is used to power gate the ULPSS RAM Banks + * @param[in] mask OR'ed value of the RAM power gates + * \n + * \ref ULPSS_RAM_PWRCTRL_CLEAR_REG1 + * @return none + */ +STATIC INLINE void RSI_PS_UlpssRamBanksPowerDown(uint32_t mask) +{ + BATT_FF->ULPSS_RAM_PWRCTRL_CLEAR_REG1 = mask; +} + +/** + * @fn STATIC INLINE void RSI_PS_UlpssRamBanksPowerUp(uint32_t mask) + * @brief This API is used to un power gate the ULPSS RAM Banks + * @param[in] mask OR'ed value of the RAM power gates + * \n + * \ref ULPSS_RAM_PWRCTRL_SET_REG1 + * @return none + */ +STATIC INLINE void RSI_PS_UlpssRamBanksPowerUp(uint32_t mask) +{ + BATT_FF->ULPSS_RAM_PWRCTRL_SET_REG1 = mask; +} + +/** + * @fn STATIC INLINE void RSI_PS_SetWkpSources(uint32_t wakeUpsrcMask) + * @brief This API is used to set the wake up source to wake up from deep sleep + * @param[in] wakeUpsrcMask OR'ed value of the wake up sources + * \n + * \ref MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE + * @return none + */ +STATIC INLINE void RSI_PS_SetWkpSources(uint32_t wakeUpsrcMask) +{ + MCU_FSM->MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE |= wakeUpsrcMask; +} + +/** + * @fn STATIC INLINE void RSI_PS_ClrWkpSources(uint32_t wakeUpsrcMask) + * @brief This API is used to clear the wake up source + * @param[in] wakeUpsrcMask OR'ed value of the wake up sources + * \ref MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE + * @return none + */ +STATIC INLINE void RSI_PS_ClrWkpSources(uint32_t wakeUpsrcMask) +{ + MCU_FSM->MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE &= ~wakeUpsrcMask; +} + +/** + * @fn STATIC INLINE uint32_t RSI_PS_GetWkpSources(void) + * @brief This API is used to get the wake up source + * @return register bits of wake up sources + */ +STATIC INLINE uint32_t RSI_PS_GetWkpSources(void) +{ + return MCU_FSM->MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE; +} + +/** + * @fn STATIC INLINE void RSI_PS_EnableFirstBootUp(boolean_t enable) + * @brief This API is used to SET and CLEAR the First boot up bit + * @param[in] enable : + * \ref MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b 0: disable the first boot , + * \ref MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b 1: enable the first boot up + * @return none + */ +STATIC INLINE void RSI_PS_EnableFirstBootUp(boolean_t enable) +{ + MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b.FIRST_BOOTUP_MCU_N_b = (unsigned int)(enable & 0x01); +} + +/** + * @fn STATIC INLINE void RSI_PS_PowerSupplyEnable(uint32_t mask) + * @brief This API is used to enable the supply to some NPSS peripherals + * @param[in] mask 0: disable the first boot , 1: enable the first boot up + * @return none + */ +STATIC INLINE void RSI_PS_PowerSupplyEnable(uint32_t mask) +{ + MCU_FSM->MCU_FSM_CRTL_PDM_AND_ENABLES |= mask; +} + +/** + * @fn STATIC INLINE void RSI_PS_PowerSupplyDisable(uint32_t mask) + * @brief This API is used to disable the supply to some NPSS peripherals + * @param[in] mask 0: disable the first boot , 1: enable the first boot up + * \ref MCU_FSM_CRTL_PDM_AND_ENABLES + * @return none + */ +STATIC INLINE void RSI_PS_PowerSupplyDisable(uint32_t mask) +{ + MCU_FSM->MCU_FSM_CRTL_PDM_AND_ENABLES &= ~mask; +} + +/** + * @fn STATIC INLINE void RSI_PS_FsmHfClkSel(FSM_CLK_T fsmHfClk) + * @brief This API is used to configure the FSM high frequency clock + * @param[in] fsmHfClk : enum value of the high frequency clock sources + * \ref MCU_FSM_CLKS_REG_b + * @return none + */ +STATIC INLINE void RSI_PS_FsmHfClkSel(FSM_CLK_T fsmHfClk) +{ + MCU_FSM->MCU_FSM_CLKS_REG_b.HF_FSM_CLK_SELECT = fsmHfClk; + //FIXME:wait logic cross check + while (MCU_FSM->MCU_FSM_CLKS_REG_b.HF_FSM_CLK_SWITCHED_SYNC != 1) + ; +} + +/** + * @fn STATIC INLINE void RSI_PS_FsmHfFreqConfig(uint32_t freq) + * @brief This API is used to configure the FSM high frequency clock range + * @param[in] freq : frequency in MHz pass 2 if it is 2MHz + * @return none + */ +STATIC INLINE void RSI_PS_FsmHfFreqConfig(uint32_t freq) +{ + MCU_FSM->MCU_FSM_CLKS_REG_b.HF_FSM_CLK_FREQ = (unsigned int)(freq & 0x3F); +} + +/** + * @fn STATIC INLINE void RSI_PS_FsmLfClkSel(AON_CLK_T fsmLfClk) + * @brief This API is used to configure the FSM low frequency clock + * @param[in] fsmLfClk enum value of the low frequency clock sources + * \ref MCUAON_KHZ_CLK_SEL_POR_RESET_STATUS_b + * @return none + */ +STATIC INLINE void RSI_PS_FsmLfClkSel(AON_CLK_T fsmLfClk) +{ + MCU_AON->MCUAON_KHZ_CLK_SEL_POR_RESET_STATUS_b.AON_KHZ_CLK_SEL = fsmLfClk; + //FIXME:wait logic check if it is working RTC blocked mode + while (MCU_AON->MCUAON_KHZ_CLK_SEL_POR_RESET_STATUS_b.AON_KHZ_CLK_SEL_CLOCK_SWITCHED != 1) + ; +} + +/** + * @fn STATIC INLINE void RSI_PS_PmuGoodTimeDurationConfig(uint8_t pmuDuration) + * @brief This API is used to configure the PMU good time. + * @param[in] pmuDuration (0 to 31) are possible value is applied in power of 2. + * @return none + */ +STATIC INLINE void RSI_PS_PmuGoodTimeDurationConfig(uint8_t pmuDuration) +{ +#ifdef CHIP_9118 + MCU_FSM->MCU_FSM_XTAL_AND_PMU_GOOD_COUNT_REG_b.MCUFSM_PMU_POWERGOOD_DURATION_COUNT = + (unsigned int)(pmuDuration & 0x1F); +#endif +#ifdef SLI_SI917 + MCU_FSM->MCU_FSM_XTAL_AND_PMU_GOOD_COUNT_REG_b.MCUFSM_PMU_POWERGOOD_DURATION_COUNT = + (unsigned int)(pmuDuration & 0x7F); +#endif +} + +/** + * @fn STATIC INLINE void RSI_PS_XtalGoodTimeDurationConfig(uint8_t xtalDuration) + * @brief This API is used to configure the XTAL good time. + * @param[in] xtalDuration (0 to 31) are possible value is applied in power of 2. + * \ref MCU_FSM_XTAL_AND_PMU_GOOD_COUNT_REG_b + * @return none + */ +STATIC INLINE void RSI_PS_XtalGoodTimeDurationConfig(uint8_t xtalDuration) +{ +#ifdef CHIP_9118 + MCU_FSM->MCU_FSM_XTAL_AND_PMU_GOOD_COUNT_REG_b.MCUFSM_XTAL_GOODTIME_DURATION_COUNT = + (unsigned int)(xtalDuration & 0x1F); +#endif +#ifdef SLI_SI917 + MCU_FSM->MCU_FSM_XTAL_AND_PMU_GOOD_COUNT_REG_b.MCUFSM_XTAL_GOODTIME_DURATION_COUNT = + (unsigned int)(xtalDuration & 0x7F); +#endif +} + +/** + * @fn STATIC INLINE void RSI_PS_Ps2PmuLdoOffDelayConfig(uint8_t ldoOffDelay) + * @brief This API is used to configure LDO off delay + * @param[in] ldoOffDelay (0 to 31) are possible value is applied in power of 2. + * @return none + */ +STATIC INLINE void RSI_PS_Ps2PmuLdoOffDelayConfig(uint8_t ldoOffDelay) +{ + MCU_FSM->MCU_FSM_POWER_CTRL_AND_DELAY_b.PS2_PMU_LDO_OFF_DELAY = (unsigned int)(ldoOffDelay & 0x1F); +} + +/** + * @fn STATIC INLINE void RSI_PS_Ps4PmuLdoOnDelayConfig(uint8_t ldoOnDelay) + * @brief This API is used to configure LDO on delay + * @param[in] ldoOnDelay (0 to 31) are possible value is applied in power of 2. + * \ref MCU_FSM_POWER_CTRL_AND_DELAY_b + * @return none + */ +STATIC INLINE void RSI_PS_Ps4PmuLdoOnDelayConfig(uint8_t ldoOnDelay) +{ + MCU_FSM->MCU_FSM_POWER_CTRL_AND_DELAY_b.PS4_SOCLDO_ON_DELAY = (unsigned int)(ldoOnDelay & 0xF); +} + +/** + * @fn STATIC INLINE void RSI_PS_Ps4PmuBuckOnDelayConfig(uint8_t pmuBuckOnDelay) + * @brief This API is used to configure buck on delay + * @param[in] pmuBuckOnDelay (0 to 31) are possible value is applied in power of 2. + * \ref MCU_FSM_POWER_CTRL_AND_DELAY_b + * @return none + */ +STATIC INLINE void RSI_PS_Ps4PmuBuckOnDelayConfig(uint8_t pmuBuckOnDelay) +{ + MCU_FSM->MCU_FSM_POWER_CTRL_AND_DELAY_b.PG4_BUCK_ON_DELAY = (unsigned int)(pmuBuckOnDelay & 0xF); +} + +/** + * @fn STATIC INLINE uint32_t RSI_PS_GetWkpUpStatus(void) + * @brief This API is used to get the wake up/ NPSS interrupt status + * \ref NPSS_INTR_STATUS_REG + * @return register bits of NPSS interrupt status register + * @return wakeup/NPSS intr status + */ +STATIC INLINE uint32_t RSI_PS_GetWkpUpStatus(void) +{ + return NPSS_INTR_STATUS_REG; +} + +/** + * @fn STATIC INLINE uint32_t RSI_PS_GetComnIntrSts(void) + * @brief This API is used to get the wake up/ NPSS common interrupt status + * @return register bits of NPSS interrupt status register + * \ref MCU_FSM_WAKEUP_STATUS_REG + * @return wake up/NPSS common inrerrupt status + */ +STATIC INLINE uint32_t RSI_PS_GetComnIntrSts(void) +{ + return MCU_FSM->MCU_FSM_WAKEUP_STATUS_REG; +} + +/** + * @fn STATIC INLINE void RSI_PS_NpssIntrUnMask(uint32_t mask) + * @brief This API is used to un mask the NPSS interrupts + * @param[in] mask is OR'ed value of the NPSS interrupt bits + * \ref NPSS_INTR_MASK_CLR_REG + * @return none + */ +STATIC INLINE void RSI_PS_NpssIntrUnMask(uint32_t mask) +{ + NPSS_INTR_MASK_CLR_REG = mask; +} + +/** + * @fn STATIC INLINE void RSI_PS_NpssIntrMask(uint32_t mask) + * @brief This API is used to mask the NPSS interrupts + * @param[in] mask is OR'ed value of the NPSS interrupt bits + * \ref NPSS_INTR_MASK_SET_REG + * @return none + */ +STATIC INLINE void RSI_PS_NpssIntrMask(uint32_t mask) +{ + NPSS_INTR_MASK_SET_REG = mask; +} + +/** + * @fn STATIC INLINE void RSI_PS_EnableLpSleep(boolean_t lpSleep) + * @brief This API is used to enable/disable the lp sleep mode + * @param[in] lpSleep 1:enable lp sleep , 0 : disable lp sleep + * \ref MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE_b + * @return none + */ +STATIC INLINE void RSI_PS_EnableLpSleep(boolean_t lpSleep) +{ + MCU_FSM->MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE_b.LP_SLEEP_MODE_b = (unsigned int)(lpSleep & 0x1); +} + +/** + *@fn STATIC INLINE void RSI_PS_SkipXtalWaitTime(boolean_t val) + *@brief This API is used to skip the XTAL wait time + *@param[in] val 1: skip XTAL wait time + * 0 Do not skip XTAL wait time + * \ref MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE_b + * @return none + */ +STATIC INLINE void RSI_PS_SkipXtalWaitTime(boolean_t val) +{ + /*if package_type value is 5(M7DB) then don't skip xtal wait time */ + if (package_type != 0x5) { + MCU_FSM->MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE_b.SKIP_XTAL_WAIT_TIME = (unsigned int)(val & 0x1); + } +} +/** + *@fn STATIC INLINE void RSI_PS_UlpToDcDcMode(void) + *@brief This API is configures SC-DCDC from LDO to DCDC Mode + * @return none + */ +STATIC INLINE void RSI_PS_UlpToDcDcMode(void) +{ + ULP_SPI_MEM_MAP(0x126) = 0x3E002F; + ULP_SPI_MEM_MAP(0x128) = 0x200020; +} + +/** + *@fn STATIC INLINE void RSI_PS_LatchCntrlSet(uint32_t val) + *@brief This API is used to set the latch configurations + * @return none + */ +STATIC INLINE void RSI_PS_LatchCntrlSet(uint32_t val) +{ + ULP_SPI_MEM_MAP(SELECT_BG_CLK) |= val; +} + +/** + *@fn STATIC INLINE void RSI_PS_LatchCntrlClr(uint32_t val) + *@brief This API is used to clear the latch configurations + * @return none + */ +STATIC INLINE void RSI_PS_LatchCntrlClr(uint32_t val) +{ + ULP_SPI_MEM_MAP(SELECT_BG_CLK) &= ~val; +} + +/** + *@fn STATIC INLINE void RSI_PS_BodPwrGateButtonCalibEnable(void) + *@brief This API is used to enable the power-gate enable signal for button calib and vbatt status checking block + * @return none + */ +STATIC INLINE void RSI_PS_BodPwrGateButtonCalibEnable(void) +{ + ULP_SPI_MEM_MAP(0x1E3) |= (BIT(15)); +} + +/** + *@fn STATIC INLINE void RSI_PS_BodPwrGateButtonCalibDisable(void) + *@brief This API is used to disable the power-gate enable signal for button calib and vbatt status checking block + * @return none + */ +STATIC INLINE void RSI_PS_BodPwrGateButtonCalibDisable(void) +{ + ULP_SPI_MEM_MAP(0x1E3) &= ~(BIT(15)); +} + +/** + *@fn STATIC INLINE void RSI_PS_XtalEnable(void) + *@brief This API is used to enable the XTAL + *@return none + */ +STATIC INLINE void RSI_PS_XtalEnable(void) +{ + *(volatile uint32_t *)0x41300480 |= (BIT(10)); +} + +/** + *@fn STATIC INLINE void RSI_PS_XtalDisable(void) + *@brief This API is used to disable the XTAL + *@return none + */ +STATIC INLINE void RSI_PS_XtalDisable(void) +{ + *(volatile uint32_t *)0x41300480 &= ~(BIT(10)); +} + +/** + *@fn STATIC INLINE void RSI_PS_QspiDllDomainEnable(void) + *@brief This API is used to enable the power to the QSPI-DLL module + *@return none + */ +STATIC INLINE void RSI_PS_QspiDllDomainEnable(void) +{ + *(volatile uint32_t *)0x24048484 |= (BIT(2) | BIT(6)); +} + +/** + *@fn STATIC INLINE void RSI_PS_QspiDllDomainDisable(void) + *@brief This API is used to disable the power to the QSPI-DLL module + *@return none + */ +STATIC INLINE void RSI_PS_QspiDllDomainDisable(void) +{ + *(volatile uint32_t *)0x24048484 &= ~(BIT(2) | BIT(6)); +} + +/** + *@fn STATIC INLINE void RSI_PS_LdoSocDefaultModeEnable(void) + *@brief This API is used to enable the SOC LDO default mode (Set high for 1.1 V (default mode)) + *@return none + */ +STATIC INLINE void RSI_PS_LdoSocDefaultModeEnable(void) +{ + PMU_SPI_MEM_MAP(0x1D6) |= (BIT(5)); +} + +/** + *@fn STATIC INLINE void RSI_PS_LdoSocDefaultModeDisable(void) + *@brief This API is used to disable the SOC LDO default mode + *@return none + */ +STATIC INLINE void RSI_PS_LdoSocDefaultModeDisable(void) +{ + PMU_SPI_MEM_MAP(0x1D6) &= ~(BIT(5)); +} + +/** + *@fn void RSI_PS_BypassLdoRfEnable(void) + *@brief This API is used to enable bypass of LDO-RF enable and control bits to control from outside + *@return none + */ +STATIC INLINE void RSI_PS_BypassLdoRfEnable(void) +{ + PMU_SPI_MEM_MAP(0x1D8) |= BIT(2); +} + +/** + *@fn STATIC INLINE void RSI_PS_FlashLdoEnable(void) + *@brief This API is used to flash LDO enable. + *@return none + */ +STATIC INLINE void RSI_PS_FlashLdoEnable(void) +{ + BATT_FF->MCU_PMU_LDO_CTRL_SET = BIT(0); +} + +/** + *@fn STATIC INLINE void RSI_PS_FlashLdoDisable(void) + *@brief This API is used to disable flash LDO. + *@return none + */ +STATIC INLINE void RSI_PS_FlashLdoDisable(void) +{ + BATT_FF->MCU_PMU_LDO_CTRL_CLEAR = BIT(0); +} + +/** + *@fn void RSI_PS_BypassLdoRfDisable(void) + *@brief This API is used to disable bypass of LDO-RF enable and control bits to control from outside(i.e internal logic) + *@return none + */ +STATIC INLINE void RSI_PS_BypassLdoRfDisable(void) +{ + PMU_SPI_MEM_MAP(0x1D8) &= ~BIT(2); +} + +/** + *@fn STATIC INLINE void RSI_PS_SocPllSpiDisable(void) + *@brief This API is used to disable the Soc-PLL SPI PG + *@return none + */ +STATIC INLINE void RSI_PS_SocPllSpiDisable(void) +{ + BATT_FF->PLLCCI_PWRCTRL_REG_b.SOCPLL_SPI_PG_EN = 0U; +} + +/** + *@fn STATIC INLINE void RSI_PS_SocPllVddIsoEnable(void) + *@brief This API is used to enable the Soc-PLL ISO VDD + *@return none + */ +STATIC INLINE void RSI_PS_SocPllVddIsoEnable(void) +{ + BATT_FF->PLLCCI_PWRCTRL_REG_b.SOCPLL_ISO_ENABLE = 1U; +} + +/** + *@fn STATIC INLINE void RSI_PS_SocPllVddIsoDiable(void) + *@brief This API is used to disable the Soc-PLL ISO VDD + *@return none + */ +STATIC INLINE void RSI_PS_SocPllVddIsoDiable(void) +{ + BATT_FF->PLLCCI_PWRCTRL_REG_b.SOCPLL_ISO_ENABLE = 0U; +} + +/** + *@fn STATIC INLINE void RSI_PS_SocPllSpiEnable(void) + *@brief This API is used to enable the Soc-PLL SPI PG + *@return none + */ +STATIC INLINE void RSI_PS_SocPllSpiEnable(void) +{ + BATT_FF->PLLCCI_PWRCTRL_REG_b.SOCPLL_SPI_PG_EN = 1U; +} + +/** + *@fn STATIC INLINE void RSI_ConfigBuckBoost(uint8_t cntrl , uint8_t enable) + *@brief This API is used to control the buck boost + *@param[in] cntrl 0: Software controlled 1: Hardware controlled. + *@param[in] enable 0: Disabled if controlled by software(cntrl = 0) 1: Enabled if controlled by software(cntrl = 1) + *@return none + */ +STATIC INLINE void RSI_ConfigBuckBoost(uint8_t cntrl, uint8_t enable) +{ + BATT_FF->MCU_FSM_CTRL_BYPASS_b.MCU_BUCK_BOOST_ENABLE_BYPASS = (unsigned int)((enable & 0x1) & 0x01); + BATT_FF->MCU_FSM_CTRL_BYPASS_b.MCU_BUCK_BOOST_ENABLE_BYPASS_CTRL = (unsigned int)((cntrl & 0x1) & 0x01); +} + +/** + *@fn STATIC INLINE void RSI_ConfigPmuShutDown(uint8_t cntrl , uint8_t enable) + *@brief This API is used to control the pmu shut down mode + *@param[in] cntrl 0: Software controlled 1: Hardware controlled. + *@param[in] enable 0: Disabled if controlled by software(cntrl = 0) 1: Enabled if controlled by software(cntrl = 1) + *@return none + */ +STATIC INLINE void RSI_ConfigPmuShutDown(uint8_t cntrl, uint8_t enable) +{ + BATT_FF->MCU_FSM_CTRL_BYPASS_b.MCU_PMU_SHUT_DOWN_BYPASS = (unsigned int)((enable & 0x1) & 0x01); + BATT_FF->MCU_FSM_CTRL_BYPASS_b.MCU_PMU_SHUT_DOWN_BYPASS_CTRL = (unsigned int)((cntrl & 0x1) & 0x01); +} + +/** + *@fn STATIC INLINE void RSI_ChangeTassRefClock(void) + *@brief This API is used to change the TASS reference clock to 32MHz RC , This API is used only in MCU mode , should not be used in WiSeMCU mode. + *@return none + */ +STATIC INLINE void RSI_ChangeTassRefClock(void) +{ + *(volatile uint32_t *)0x41300110 = (1 << 23) | (1 << 16) | (1 << 4) | 1; +} + +/** + *@fn STATIC INLINE void RSI_SetRegSpiDivision(uint8_t div) + *@brief This API is used to change the reg access SPI clock division factor. + *@return none + */ +STATIC INLINE void RSI_SetRegSpiDivision(uint8_t div) +{ + *(volatile uint32_t *)(REG_SPI_BASE_ADDR_ULP + 0x00) &= (uint32_t)(~(0xF)); + *(volatile uint32_t *)(REG_SPI_BASE_ADDR_ULP + 0x00) |= div; +} + +/** + *@fn STATIC INLINE void RSI_ConfigXtal(uint8_t cntrl , uint8_t enable) + *@brief This API is used to control the Xtal + *@param[in] cntrl 0: Software controlled 1: Hardware controlled. + *@param[in] enable 0: Disabled if controlled by software(cntrl = 0) 1: Enabled if controlled by software(cntrl = 1) + *@return none + */ +STATIC INLINE void RSI_ConfigXtal(uint8_t cntrl, uint8_t enable) +{ + BATT_FF->MCU_FSM_CTRL_BYPASS_b.MCU_XTAL_EN_40MHZ_BYPASS = (unsigned int)((enable & 0x1) & 0x01); + BATT_FF->MCU_FSM_CTRL_BYPASS_b.MCU_XTAL_EN_40MHZ_BYPASS_CTRL = (unsigned int)((cntrl & 0x1) & 0x01); +} + +/** + *@fn STATIC INLINE void RSI_PS_PmuUltraSleepConfig(boolean_t en) + *@brief This API is used to enable the 'NPSS_PMU_STANDBY' + *@param[in] en 1: enable the 'NPSS_PMU_STANDBY' + * en 0: disable the 'NPSS_PMU_STANDBY' + *@return none + */ +STATIC INLINE void RSI_PS_PmuUltraSleepConfig(boolean_t en) +{ + MCU_FSM->MCU_FSM_PMU_STATUS_REG_b.STANDBY_DC1P3_R = (unsigned int)(en & 0x01); +} + +/** + *@fn STATIC INLINE void RSI_PS_PmuSetConfig(uint32_t mask) + *@brief This API is used to enable/set the PMU status + *@param[in] mask : Ored values of PMU status bits + * \n Following are the possible parameters for this parameter + * \n PMU_STS_DCDC_ON + * \n PMU_STS_FLASH_LDO_ON + * \n PMU_STS_SOC_LDO_ON + *@return none + */ +STATIC INLINE void RSI_PS_PmuSetConfig(uint32_t mask) +{ + MCU_FSM->MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE |= mask; +} + +/** + *@fn STATIC INLINE void RSI_PS_PmuClrConfig(uint32_t mask) + *@brief This API is used to disable/clear the PMU status + *@param[in] mask : Ored values of PMU status bits + * \n Following are the possible parameters for this parameter + * \n PMU_STS_DCDC_ON + * \n PMU_STS_FLASH_LDO_ON + * \n PMU_STS_SOC_LDO_ON + *@return none + */ +STATIC INLINE void RSI_PS_PmuClrConfig(uint32_t mask) +{ + MCU_FSM->MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE &= ~mask; +} + +/** + *@fn void RSI_PS_AnalogPeriPtatEnable(void) + *@brief This API is used to enable the ptat currents to analog peripherals + * @return execution status + */ +STATIC INLINE uint32_t RSI_PS_AnalogPeriPtatEnable(void) +{ + return RSI_IPMU_ProgramConfigData(ana_perif_ptat_common_config1); +} + +/** + *@fn void RSI_PS_AnalogPeriPtatDisable(void) + *@brief This API is used to disable the ptat currents to analog peripherals + *@return execution status + */ +STATIC INLINE uint32_t RSI_PS_AnalogPeriPtatDisable(void) +{ + return RSI_IPMU_ProgramConfigData(ana_perif_ptat_common_config2); +} + +/** + *@fn void RSI_PS_BodClksPtatEnable(void) + *@brief This API is used to enable the ptat currents to clocks and bod(cmp_npss) + *@return execution status + */ +STATIC INLINE uint32_t RSI_PS_BodClksPtatEnable(void) +{ + return RSI_IPMU_ProgramConfigData(ipmu_bod_clks_common_config1); +} + +/** + *@fn void RSI_PS_BodClksPtatDisable(void) + *@brief This API is used to disable the ptat currents to clocks and bod(cmp_npss) + *@return execution status + */ +STATIC INLINE uint32_t RSI_PS_BodClksPtatDisable(void) +{ + return RSI_IPMU_ProgramConfigData(ipmu_bod_clks_common_config2); +} + +/** + *@fn void RSI_PS_PS4SetRegisters(void) + *@brief This API is used configure the registers for clock more than 120 MHz in PS4 + *@return none + */ +STATIC INLINE void RSI_PS_PS4SetRegisters(void) +{ + // Configure the prefetch and registering when SOC clock is more than 120Mhz + ICACHE2_ADDR_TRANSLATE_1_REG = BIT(21); // Icache registering when clk freq more than 120 + // When set, enables registering in M4-TA AHB2AHB. This will have performance penalty. This has to be set above 100MHz + MISC_CFG_SRAM_REDUNDANCY_CTRL = BIT(4); + MISC_CONFIG_MISC_CTRL1 |= BIT(4); // Enable Register ROM as clock frequency is 200 Mhz +} + +/** + *@fn void RSI_PS_PS2UpdateClockVariable(void) + *@brief This API is used update the global clock variable after clock setting in PS2 + *@return none + */ +STATIC INLINE void RSI_PS_PS2UpdateClockVariable(void) +{ + // Updates the system clock. + system_clocks.rc_32mhz_clock = 20000000; + // Updating the systemcoreclock variable. + SystemCoreClock = 20000000; +} + +/** + *@fn void RSI_PS_WakeupTAandProgramFlash(void) + *@brief This API is used wakeup the TA and program the flash + *@return none + */ +STATIC INLINE void RSI_PS_WakeupTAandProgramFlash(void) +{ + if (!(P2P_STATUS_REGISTER & BIT(3))) { + //!wakeup TA + P2P_STATUS_REGISTER |= BIT(0); + //!wait for TA active + while (!(P2P_STATUS_REGISTER & BIT(3))) + ; + } + //! Request TA to program flash + //! raise an interrupt to TA register + M4SS_P2P_INTR_SET_REGISTER = BIT(4); + P2P_STATUS_REGISTER = BIT(0); + + while (!(P2P_STATUS_REGISTER & BIT(3))) + ; +} + +/** + *@fn void RSI_PS_SetMCUActiveStatus(void) + *@brief This API is used set the active status of mcu after wakeup + *@return none + */ +STATIC INLINE void RSI_PS_SetMCUActiveStatus(void) +{ + P2P_STATUS_REGISTER = BIT(1); +} + +/** + *@fn void RSI_PS_IsPS2State(void) + *@brief This API is used to check is current state is PS2 or not + *@return true if PS2 state false if not + */ +STATIC INLINE boolean_t RSI_PS_IsPS2State(void) +{ + return (M4_ULP_SLP_STATUS_REG & ULP_MODE_SWITCHED_NPSS); +} + +/** @} */ + +/* @} end of RSI_POWER_SAVE */ + +void ps_clr_wkp_up_status(uint32_t wakeUpIntrClear); + +void ps_bg_ldo_config(uint8_t ldo_0p6_ctrl, uint8_t ldo_0p6_lp_mode); + +void ps_configure_trim_values(uint16_t lf_ro_trim, + uint16_t lf_rc_trim, + uint16_t hf_ro_trim, + uint16_t hf_rc_trim, + uint16_t bg_ptat_trim, + uint16_t bg_trim); + +void ps_wireless_shutdown(void); + +/*End of file not truncated*/ +#ifdef __cplusplus +} +#endif + +#endif /*__RSI_POWER_SAVE_H__*/ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_processor_sensor.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_processor_sensor.h new file mode 100644 index 000000000..e5497c5b8 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_processor_sensor.h @@ -0,0 +1,51 @@ +/******************************************************************************* +* @file rsi_processor_sensor.h +* @brief +******************************************************************************* +* # License +* Copyright 2020 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +/** + * Includes + */ + +#ifndef __RSI_PROCESSOR_SENSOR_H__ +#define __RSI_PROCESSOR_SENSOR_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \ingroup RSI_SPECIFIC_DRIVERS + * \defgroup RSI_PROCESSOR_SENSOR RSI:RS1xxxx PROCESSOR_SENSOR + * @{ + * + */ +#include "rsi_ccp_common.h" + +rsi_error_t RSI_ProSense_Enable(MCU_ProcessSensor_Type *pstcProcessSensor, boolean_t bEN); +uint32_t RSI_ProSense_Read(MCU_ProcessSensor_Type *pstcProcessSensor); +uint32_t RSI_ProSense_GetNumCycles(MCU_ProcessSensor_Type *pstcProcessSensor); +rsi_error_t RSI_ProSense_ClkEnable(MCU_ProcessSensor_Type *pstcProcessSensor, boolean_t bEN); +rsi_error_t RSI_ProSense_RingClkStart(MCU_ProcessSensor_Type *pstcProcessSensor, boolean_t bEN); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /*__RSI_PROCESSOR_SENSOR_H__*/ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_reg_spi.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_reg_spi.h new file mode 100644 index 000000000..2fb1d57af --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_reg_spi.h @@ -0,0 +1,88 @@ +/******************************************************************************* +* @file rsi_reg_spi.h +* @brief +******************************************************************************* +* # License +* Copyright 2020 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +/** + * Includes + */ +#ifndef __RSI_REG_SPI_H__ +#define __RSI_REG_SPI_H__ + +#ifdef __cplusplus +extern "C" { +#endif +/** + * \cond HIDDEN_SYMBOLS + */ + +#define REG_SPI_BASE_ADDR_ULP 0x24050000 +#define REG_SPI_BASE_ADDR_PLL 0x46180000 +#define TASS_AFE_REG_ACC_MEM_MAP_BASE_ADDR 0x41138000 + +#include "rsi_ccp_common.h" + +/*Register memory mapped reg read write*/ + +/*REG ADDRESS : Address of a target register ULP*/ +#define ULP_SPI_MEM_MAP(REG_ADR) (*((uint32_t volatile *)(REG_SPI_BASE_ADDR_ULP + (0xa000 + (REG_ADR * 4))))) + +/*REG ADDRESS : Address of a target register PMU*/ +#define PMU_SPI_MEM_MAP(REG_ADR) (*((uint32_t volatile *)(REG_SPI_BASE_ADDR_ULP + (0x00008000 + (REG_ADR * 4))))) + +/*Memory mapped SPI for M4 PLL configuration */ +#define SPI_MEM_MAP_PLL(REG_ADR) (*((uint16_t volatile *)(REG_SPI_BASE_ADDR_PLL + 0x00008000 + (REG_ADR << 2)))) + +/*Memory mapped SPI for PLL_480 configuration */ +#define TASS_PLL_CTRL_SET_REG(REG_ADR) (*((uint16_t volatile *)(TASS_AFE_REG_ACC_MEM_MAP_BASE_ADDR + (REG_ADR << 2)))) + +/*Configuration parameters*/ +#define GSPI_RF_N_ULP BIT(12) +#define GSPI_ACTIVE BIT(8) +#define GSPI_TRIG BIT(7) +#define GSPI_READ BIT(6) +#define GSPI_DATA_FIFO GSPI_DATA_REG0 +#define READ_INDICATION BIT(15) +#define ADDR_DATA_LEN 31 + +/*GSPI Configuration*/ +typedef struct stc_reg_spi_config { + uint16_t u16GspiClockRatio; + uint16_t u16GspiCsbSetupTime; + uint16_t u16GspiCsbHoldTime; + uint16_t u16GspiCsbHighTime; + boolean_t bGspiSpiMode; + boolean_t bGspiClockPhase; + boolean_t bGspiAfeIpmun; + boolean_t bDmaMode; + boolean_t bDma32_48Bitn; +} stc_reg_spi_config_t; + +/*Target selection*/ +typedef enum en_select_target { PmuBlock = 0, UlpBlock = 1 } en_select_target_t; + +/*Base address assignment */ +#define REG_SPI_ULP (*((REG_SPI_Type_T *)REG_SPI_BASE_ADDR_ULP)) /*Memory map for ULPSS Reg access SPI*/ +#define REG_SPI_PLL (*((REG_SPI_Type_T *)REG_SPI_BASE_ADDR_PLL)) /*Memory map for ULPSS Reg access SPI*/ + +/** + * \endcond + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__RSI_REG_SPI_H__*/ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_retention.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_retention.h new file mode 100644 index 000000000..fe5116553 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_retention.h @@ -0,0 +1,313 @@ +/******************************************************************************* +* @file rsi_retention.h +* @brief +******************************************************************************* +* # License +* Copyright 2020 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +/** + * Includes + */ + +#ifndef __RSI_RETENTION_H__ +#define __RSI_RETENTION_H__ +#include "rsi_ccp_common.h" +#include "rsi_power_save.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/*NPSS GPIO PIN MUX VALEUS*/ +#define NPSS_GPIO_STATUS (*(volatile uint32_t *)(NPSS_INTR_BASE + 0x14)) +#define NPSS_GPIO_CONFIG_REG (*(volatile uint32_t *)(NPSS_INTR_BASE + 0x10)) + +/*NPSS GPIO PIN MUX VALEUS*/ +#define NPSSGPIO_PIN_MUX_MODE0 0 +#define NPSSGPIO_PIN_MUX_MODE1 1 +#define NPSSGPIO_PIN_MUX_MODE2 2 +#define NPSSGPIO_PIN_MUX_MODE3 3 +#define NPSSGPIO_PIN_MUX_MODE4 4 +#define NPSSGPIO_PIN_MUX_MODE5 5 +#define NPSSGPIO_PIN_MUX_MODE6 6 +#define NPSSGPIO_PIN_MUX_MODE7 7 +/*@note : Please refer to pin MUX excel to configure in desired mode + * */ +/*EDGE INTERRUPT MODE */ +#define RISING_EDGE 0 +#define FALLING_EDGE 1 +#define BOTH_FALL_RISE_EDGE 3 + +/*NPSS GPIO pin interrupt edge configuration */ +#define NPSS_INTR_RISING_EDGE 1 +#define NPSS_INTR_FALLING_EDGE 0 + +/*NPSS GPIO pin direction */ +#define NPSS_GPIO_DIR_INPUT 1 +#define NPSS_GPIO_DIR_OUTPUT 0 + +/*NPSS GPIO pin interrupt levels*/ +#define NPSS_GPIO_INTR_HIGH 1 +#define NPSS_GPIO_INTR_LOW 0 + +/*NPSS GPIO pin defines */ +#define NPSS_GPIO_0 0 +#define NPSS_GPIO_1 1 +#define NPSS_GPIO_2 2 +#define NPSS_GPIO_3 3 +#define NPSS_GPIO_4 4 + +/*NPSS GPIO Interrupt defines */ +#define NPSS_GPIO_0_INTR BIT(0) +#define NPSS_GPIO_1_INTR BIT(1) +#define NPSS_GPIO_2_INTR BIT(2) +#define NPSS_GPIO_3_INTR BIT(3) +#define NPSS_GPIO_4_INTR BIT(4) + +/** + * \ingroup RSI_SPECIFIC_DRIVERS + * \defgroup RSI_NPSSGPIO RSI:RS1xxxx NPSSGPIO + * @{ + * + */ + +/** +* @brief This API is used to set the NPSS GPIO pin MUX (mode) + *@param[in] pin: is NPSS GPIO pin number (0...4) + *@param[in] mux : is NPSS GPIO MUX value + *@return : none + * */ +STATIC INLINE void RSI_NPSSGPIO_SetPinMux(uint8_t pin, uint8_t mux) +{ + MCU_RET->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_MODE = (unsigned int)(mux & 0x07); +} + +/** + * @fn void RSI_NPSSGPIO_InputBufferEn(uint8_t pin , boolean_t enable) +* @brief This API is used to enable/disable NPSS GPIO input buffer + *@param[in] pin: is NPSS GPIO pin number (0...4) + *@param[in] enable: is enable / disable NPSS GPIO input buffer + * 1- Enable + * 0- Disable + *@return : none + * */ +STATIC INLINE void RSI_NPSSGPIO_InputBufferEn(uint8_t pin, boolean_t enable) +{ + MCU_RET->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_REN = (unsigned int)(enable & 0x01); +} + +/** + * @brief This API is used to set the direction of the NPSS GPIO + *@param[in] pin: is NPSS GPIO pin number (0...4) + *@param[in] dir: is direction value (Input / Output) + * 1- Input Direction + * 0- Output Direction + *@return : none + * */ +STATIC INLINE void RSI_NPSSGPIO_SetDir(uint8_t pin, boolean_t dir) +{ + MCU_RET->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_OEN = (unsigned int)(dir & 0x01); +} + +/** + * @brief This API is used to Get the direction of the NPSS GPIO + *@param[in] pin: is NPSS GPIO pin number (0...4) + * @return : returns the GPIO pin direction + * */ +STATIC INLINE boolean_t RSI_NPSSGPIO_GetDir(uint8_t pin) +{ + return MCU_RET->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_OEN; +} + +/** + * @brief This API is used to set the NPSS GPIO pin value + *@param[in] pin: is NPSS GPIO pin number (0...4) + *@param[in] val: is NPSS GPIO pin value 0 or 1 + * @return none + */ +STATIC INLINE void RSI_NPSSGPIO_SetPin(uint8_t pin, boolean_t val) +{ + MCU_RET->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_OUT = (unsigned int)(val & 0x01); +} + +/** + * @brief This API is used to Get the NPSS GPIO pin value + *@param[in] pin: is NPSS GPIO pin number (0...4) + * @return returns the pin logical state of pin + */ +STATIC INLINE boolean_t RSI_NPSSGPIO_GetPin(uint8_t pin) +{ + return (NPSS_GPIO_STATUS >> pin) & 0x01; +} + +/** +* @brief This API is used to select NPSS GPIO wake up detection when in sleep + *@param[in] pin: is NPSS GPIO pin number (0...4) + *@param[in] level :Gpio polarity to wake up from sleep + * 1 - When signal is High + * 0 - When signal is Low + *@return : none + * */ +STATIC INLINE void RSI_NPSSGPIO_SetPolarity(uint8_t pin, boolean_t level) +{ + MCU_RET->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_POLARITY = (unsigned int)(level & 0x01); +} + +/** + * @brief This API is used to set the GPIO to wake from deep sleep + * @param[in] npssGpioPinIntr: OR'ed values of the NPSS GPIO interrupts + * @return none + */ +STATIC INLINE void RSI_NPSSGPIO_SetWkpGpio(uint8_t npssGpioPinIntr) +{ + MCU_FSM->GPIO_WAKEUP_REGISTER |= npssGpioPinIntr; +} + +/** + * @brief This API is used to clear the GPIO to wake from deep sleep + * @param[in] npssGpioPinIntr: OR'ed values of the NPSS GPIO interrupts + * @return none + */ +STATIC INLINE void RSI_NPSSGPIO_ClrWkpGpio(uint8_t npssGpioPinIntr) +{ + MCU_FSM->GPIO_WAKEUP_REGISTER &= ~npssGpioPinIntr; +} + +/** + * @brief This API is used to mask the NPSS GPIO interrupt + * @param[in] npssGpioPinIntr: OR'ed values of the NPSS GPIO interrupts + * @return none + */ +STATIC INLINE void RSI_NPSSGPIO_IntrMask(uint8_t npssGpioPinIntr) +{ + NPSS_INTR_MASK_SET_REG = (npssGpioPinIntr << 1); +} + +/** + * @brief This API is used to un mask the NPSS GPIO interrupt + * @param[in] npssGpioPinIntr: OR'ed values of the NPSS GPIO interrupts + * @return none + */ +STATIC INLINE void RSI_NPSSGPIO_IntrUnMask(uint8_t npssGpioPinIntr) +{ + NPSS_INTR_MASK_CLR_REG = (npssGpioPinIntr << 1); +} + +/** + * @brief This API is used to un mask the NPSS GPIO interrupt + * @param[in] npssGpioPinIntr: OR'ed values of the NPSS GPIO interrupts + * @return none + */ +STATIC INLINE void RSI_NPSSGPIO_SetIntFallEdgeEnable(uint8_t npssGpioPinIntr) +{ + NPSS_GPIO_CONFIG_REG |= (npssGpioPinIntr << 8); +} + +/** + * @brief This API is used to un mask the NPSS GPIO interrupt + * @param[in] npssGpioPinIntr: OR'ed values of the NPSS GPIO interrupts + * @return none + */ +STATIC INLINE void RSI_NPSSGPIO_ClrIntFallEdgeEnable(uint8_t npssGpioPinIntr) +{ + NPSS_GPIO_CONFIG_REG &= (uint32_t)(~(npssGpioPinIntr << 8)); +} + +/** + * @brief This API is used to Set the rise edge interrupt detection for NPSS GPIO + * @param[in] npssGpioPinIntr: OR'ed values of the NPSS GPIO interrupts + * @return none + */ +STATIC INLINE void RSI_NPSSGPIO_SetIntRiseEdgeEnable(uint8_t npssGpioPinIntr) +{ + NPSS_GPIO_CONFIG_REG |= (npssGpioPinIntr << 0); +} + +/** + * @brief This API is used to Enable rise edge interrupt detection for NPSS GPIO + * @param[in] npssGpioPinIntr: OR'ed values of the NPSS GPIO interrupts + * @return none + */ +STATIC INLINE void RSI_NPSSGPIO_ClrIntRiseEdgeEnable(uint8_t npssGpioPinIntr) +{ + NPSS_GPIO_CONFIG_REG &= (uint32_t)(~(npssGpioPinIntr << 0)); +} + +/** + * @brief This API is used to un mask the NPSS GPIO interrupt + * @param[in] npssGpioPinIntr: OR'ed values of the NPSS GPIO interrupts + * @return none + */ +STATIC INLINE void RSI_NPSSGPIO_SetIntLevelHighEnable(uint8_t npssGpioPinIntr) +{ + NPSS_GPIO_CONFIG_REG |= (npssGpioPinIntr << 24); +} + +/** + * @brief This API is used to un mask the NPSS GPIO interrupt + * @param[in] npssGpioPinIntr: OR'ed values of the NPSS GPIO interrupts + * @return none + */ +STATIC INLINE void RSI_NPSSGPIO_ClrIntLevelHighEnable(uint8_t npssGpioPinIntr) +{ + NPSS_GPIO_CONFIG_REG &= (uint32_t)(~(npssGpioPinIntr << 24)); +} + +/** + * @brief This API is used to un mask the NPSS GPIO interrupt + * @param[in] npssGpioPinIntr: OR'ed values of the NPSS GPIO interrupts + * @return none + */ +STATIC INLINE void RSI_NPSSGPIO_SetIntLevelLowEnable(uint8_t npssGpioPinIntr) +{ + NPSS_GPIO_CONFIG_REG |= (npssGpioPinIntr << 16); +} + +/** + * @brief This API is used clear the interrupt low level enable + * @param[in] npssGpioPinIntr: OR'ed values of the NPSS GPIO interrupts + * @return none + */ +STATIC INLINE void RSI_NPSSGPIO_ClrIntLevelLowEnable(uint8_t npssGpioPinIntr) +{ + NPSS_GPIO_CONFIG_REG &= (uint32_t)(~(npssGpioPinIntr << 16)); +} + +/** + * @brief This API is used to clear NPSS GPIO interrupt + * @param[in] npssGpioPinIntr: OR'ed values of the NPSS GPIO interrupts + * @return none + */ +STATIC INLINE void RSI_NPSSGPIO_ClrIntr(uint8_t npssGpioPinIntr) +{ + NPSS_INTR_CLEAR_REG = (npssGpioPinIntr << 1); +} + +/** + * @brief This API is used to get the NPSS GPIO interrupt status + * @return returns the GPIO status + */ +STATIC INLINE uint8_t RSI_NPSSGPIO_GetIntrStatus(void) +{ + return (NPSS_INTR_STATUS_REG >> 1) & 0x1F; +} +/* + *@} + */ + +#ifdef __cplusplus +} +#endif + +/*End of file not truncated*/ +#endif /*__RSI_RETENTION_H__*/ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_temp_sensor.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_temp_sensor.h new file mode 100644 index 000000000..883a52fca --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_temp_sensor.h @@ -0,0 +1,69 @@ +/******************************************************************************* +* @file rsi_temp_sensor.h +* @brief +******************************************************************************* +* # License +* Copyright 2020 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +/** + * Includes + */ +#ifndef __RSI_TEMP_SENSOR_H__ +#define __RSI_TEMP_SENSOR_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \ingroup RSI_SPECIFIC_DRIVERS + * \defgroup RSI_TEMP_SENSORS RSI:RS1xxxx TS + * @brief + * @{ + * + */ +#include "rsi_ccp_common.h" + +void RSI_TS_SetCntFreez(MCU_TEMP_Type *pstcTempSens, uint32_t u32CountFreez); +void RSI_TS_RefClkSel(MCU_TEMP_Type *pstcTempSens, boolean_t bRefClk); +void RSI_TS_Enable(MCU_TEMP_Type *pstcTempSens, boolean_t bEn); + +/** + * @} + */ +void RSI_TS_Config(MCU_TEMP_Type *pstcTempSens, uint32_t u32Nomial); +/** + * \ingroup RSI_SPECIFIC_DRIVERS + * \defgroup RSI_TEMP_SENSORS RSI:RS1xxxx TEMPERARTURE SENSOR + * @brief + * @{ + * + */ +uint32_t RSI_TS_ReadTemp(MCU_TEMP_Type *pstcTempSens); +uint32_t RSI_TS_GetRefClkCnt(MCU_TEMP_Type *pstcTempSens); +uint32_t RSI_TS_GetPtatClkCnt(MCU_TEMP_Type *pstcTempSens); +void RSI_TS_LoadBjt(MCU_TEMP_Type *pstcTempSens, uint8_t temp); +void RSI_TS_RoBjtEnable(MCU_TEMP_Type *pstcTempSens, boolean_t enable); +void RSI_Periodic_TempUpdate(TIME_PERIOD_Type *temp, uint8_t enable, uint8_t trigger_time); + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +/*End of file not truncated */ +#endif /**__RSI_TEMP_SENSOR_H__*/ + +/* @}end of group RSI_TEMP_SENSORS */ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_time_period.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_time_period.h new file mode 100644 index 000000000..f1e92ab26 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_time_period.h @@ -0,0 +1,68 @@ +/******************************************************************************* +* @file rsi_time_period.h +* @brief +******************************************************************************* +* # License +* Copyright 2020 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +/** + * Includes + */ + +#ifndef __RSI_TIME_PERIOD_H__ +#define __RSI_TIME_PERIOD_H__ +#include "rsi_ccp_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +rsi_error_t RSI_TIMEPERIOD_TimerClkSel(TIME_PERIOD_Type *pstcTimePeriod, uint32_t u32TimePeriod); +rsi_error_t RSI_TIMEPERIOD_RCCalibration(TIME_PERIOD_Type *pstcTimePeriod, + uint32_t u32TimePeriodRefClk, + uint32_t u32XtalSettle, + uint16_t u16RcClkCnt, + boolean_t bPeriodicCalibEn, + uint8_t u8PeriodicCalibRate, + boolean_t bTemperatureCalibEn, + uint8_t u8TemperatureVal, + uint8_t u8AverageFactor); +uint32_t RSI_TIMEPERIOD_RCCalibTimePeriodRead(TIME_PERIOD_Type *pstcTimePeriod); +uint32_t RSI_TIMEPERIOD_ROCalibTimePeriodRead(TIME_PERIOD_Type *pstcTimePeriod); +rsi_error_t RSI_TIMEPERIOD_XTAL32KHzCalibration(TIME_PERIOD_Type *pstcTimePeriod, + uint32_t u32TimePeriodRefClk, + uint32_t u32XtalSettle, + uint16_t u16RcClkCnt, + boolean_t bPeriodicCalibEn, + uint8_t u8PeriodicCalibRate, + boolean_t bTemperatureCalibEn, + uint8_t u8TemperatureVal, + uint8_t u8AverageFactor); +rsi_error_t RSI_TIMEPERIOD_ROCalibration(TIME_PERIOD_Type *pstcTimePeriod, + uint8_t u8RefClkSrc, + uint32_t u32XtalSettle, + uint16_t u16RoClkCnt, + boolean_t bPeriodicCalibEn, + uint8_t u8PeriodicCalibRate, + uint8_t u8AverageFactor + +); +rsi_error_t RSI_TIMEPERIOD_LowPwrTrigSelEn(TIME_PERIOD_Type *pstcTimePeriod, boolean_t bEn); +rsi_error_t RSI_TIMEPERIOD_VbatTrigSel(TIME_PERIOD_Type *pstcTimePeriod, uint8_t u8Time); + +#ifdef __cplusplus +} +#endif + +/*End of file not truncated*/ +#endif /*__RSI_TIME_PERIOD_H__*/ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_ulpss_clk.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_ulpss_clk.h new file mode 100644 index 000000000..2a6016275 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_ulpss_clk.h @@ -0,0 +1,347 @@ +/******************************************************************************* +* @file rsi_ulpss_clk.h +* @brief +******************************************************************************* +* # License +* Copyright 2020 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +/** + * Includes + */ + +#ifndef __RSI_ULPSS_CLK_H__ +#define __RSI_ULPSS_CLK_H__ + +#include "rsi_ccp_common.h" +#include "rsi_error.h" +#include "rsi_pll.h" +#include "rsi_ulpss_clk.h" +#include "rsi_power_save.h" + +/*requied delays for turn on the clocks in micro seconds*/ +#define MCU_ULP_40MHZ_CLK_EN_TRUN_ON_DELAY 10 /* delay to enable the ULP 40MHZ CLK*/ +#define MCU_ULP_DOUBLER_CLK_EN_TRUN_ON_DELAY 10 /* delay to enable the ULP DOUBLER CLK*/ +#define MCU_ULP_20MHZ_RING_OSC_CLK_EN_TRUN_ON_DELAY 10 /* delay to enable the ULP 20MHZ_RING_OSC CLK*/ +#define MCU_ULP_32MHZ_RC_CLK_EN_TRUN_ON_DELAY 2 /* delay to enable the ULP 32MHZ_RC CLK*/ +#define MCU_ULP_32KHZ_XTAL_CLK_EN_TRUN_ON_DELAY_1 500 /* delay to enable the ULP 32KHZ_XTAL CLK*/ +#define MCU_ULP_32KHZ_XTAL_CLK_EN_TRUN_ON_DELAY_2 1500 /* delay to enable the ULP 32KHZ_XTAL CLK*/ +#define MCU_ULP_32KHZ_RO_CLK_EN_TRUN_ON_DELAY 250 /* delay to enable the ULP 32KHZ_RO CLK*/ +#define MCU_ULP_32KHZ_RC_CLK_EN_TRUN_ON_DELAY 150 /* delay to enable the ULP 32KHZ_RC CLK*/ + +/*Clock enable Bits */ +#define TOUCH_SENSOR_PCLK_ENABLE BIT(31) /* Enables TOUCH_SENSOR_PCLK_ENABLE */ +#define FIM_AHB_CLK_ENABLE BIT(30) /* Enables FIM_AHB_CLK_ENABLE */ +#define ULPSS_TASS_QUASI_SYNC BIT(27) /* Enables ULPSS_TASS_QUASI_SYNC */ +#define ULPSS_M4SS_SLV_SEL BIT(26) /* Enables ULPSS_M4SS_SLV_SEL */ +#define AUX_SOC_EXT_TRIG_2_SEL BIT(25) /* Enables TOUCH_SENSOR_PCLK_ENABLE */ +#define AUX_SOC_EXT_TRIG_1_SEL BIT(24) /* Enables AUX_SOC_EXT_TRIG_1_SEL */ +#define AUX_ULP_EXT_TRIG_2_SEL BIT(23) /* Enables AUX_ULP_EXT_TRIG_2_SEL */ +#define AUX_ULP_EXT_TRIG_1_SEL BIT(22) /* Enables AUX_ULP_EXT_TRIG_1_SEL */ +#define TIMER_PCLK_EN BIT(21) /* Enables TIMER_PCLK_EN */ +#define EGPIO_PCLK_EN BIT(20) /* Enables EGPIO_PCLK_EN */ +#define EGPIO_PCLK_DYN_CTRL_DISABLE_ULP BIT(19) /* Enables EGPIO_PCLK_DYN_CTRL_DISABLE_ULP */ +#define CLK_ENABLE_ULP_MEMORIES BIT(18) /* Enables CLK_ENABLE_ULP_MEMORIES */ +#define VAD_CLK_EN BIT(17) /* Enables VAD_CLK_EN */ +#define FIM_CLK_EN BIT(16) /* Enables FIM_CLK_EN */ +#define REG_ACCESS_SPI_CLK_EN BIT(15) /* Enables REG_ACCESS_SPI_CLK_EN */ +#define EGPIO_CLK_EN BIT(14) /* Enables EGPIO_CLK_EN */ +#define CLK_ENABLE_TIMER BIT(13) /* Enables CLK_ENABLE_TIMER */ +#define VAD_PCLK_ENABLE BIT(12) /* Enables VAD_PCLK_ENABLE */ +#define FIM_PCLK_ENABLE BIT(11) /* Enables FIM_PCLK_ENABLE */ +#define SCLK_ENABLE_UART BIT(10) /* Enables SCLK_ENABLE_UART */ +#define PCLK_ENABLE_UART BIT(9) /* Enables PCLK_ENABLE_UART */ +#define SCLK_ENABLE_SSI_MASTER BIT(8) /* Enables SCLK_ENABLE_SSI_MASTER */ +#define PCLK_ENABLE_SSI_MASTER BIT(7) /* Enables PCLK_ENABLE_SSI_MASTER */ +#define CLK_ENABLE_I2S BIT(6) /* Enables CLK_ENABLE_I2S */ +#define PCLK_ENABLE_I2C BIT(5) /* Enables PCLK_ENABLE_I2C */ +#define IR_PCLK_EN BIT(4) /* Enables IR_PCLK_EN */ +#define PCM_FSYNC_START BIT(1) /* Enables PCM_FSYNC_START */ +#define PCM_ENABLE BIT(0) /* Enables PCM_ENABLE */ + +#define I2C_PCLK_DYN_CTRL_DISABLE BIT(0) /* Enables PCM_ENABLE */ +#define I2S_CLK_DYN_CTRL_DISABLE BIT(1) +#define ULP_SSI_MST_PCLK_DYN_CTRL_DISABLE BIT(2) +#define ULP_SSI_MST_SCLK_DYN_CTRL_DISABLE BIT(3) +#define UART_CLK_DYN_CTRL_DISABLE BIT(4) +#define UART_SCLK_DYN_CTRL_DISABLE BIT(5) +#define ULP_TIMER_PCLK_DYN_CTRL_DISABLE BIT(6) +#define ULP_TIMER_SCLK_DYN_CTRL_DISABLE BIT(7) +#define REG_ACCESS_SPI_CLK_DYN_CTRL_DISABLE BIT(8) +#define FIM_CLK_DYN_CTRL_DISABLE BIT(9) +#define VAD_CLK_DYN_CTRL_DISABLE BIT(10) +#define AUX_PCLK_EN BIT(11) +#define AUX_CLK_EN BIT(12) +#define AUX_MEM_EN BIT(13) +#define AUX_PCLK_DYN_CTRL_DISABLE BIT(14) +#define AUX_CLK_DYN_CTRL_DISABLE BIT(15) +#define AUX_CLK_MEM_DYN_CTRL_DISABLE BIT(16) +#define UDMA_CLK_ENABLE BIT(17) +#define IR_CLK_ENABLE BIT(18) +#define IR_CLK_DYN_CTRL_DISABLE BIT(19) + +/*ULP PROCESSOR CLOCK */ +#define ULP_PROC_MAX_SEL 7 /* Maximum Seletion value for ulp processor clock source*/ +#define ULP_PROC_MIN_SEL 0 /* Minimum Seletion value for ulp processor clock source*/ +#define ULP_PROC_MAX_DIVISOIN_FACTOR 255 /* Maximum division factor value for ulp processor clock*/ +#define ULP_PROC_MIN_DIVISOIN_FACTOR 0 /* Minimum division factor value for ulp processor clock*/ + +/*ULP SSI CLOCK*/ +#define ULP_SSI_MAX_SEL 6 /* Maximum Seletion value for ulp SSI clock source*/ +#define ULP_SSI_MIN_SEL 0 /* Minimum Seletion value for ulp SSI clock source*/ +#define ULP_SSI_MAX_DIVISION_FACTOR 127 /* Maximum division factor value for ulp SSI clock*/ +#define ULP_SSI_MIN_DIVISION_FACTOR 0 /* Minimum division factor value for ulp SSI clock*/ + +/*ULP I2S CLOCK*/ +#define ULP_I2S_MAX_SEL 8 /* Maximum Seletion value for ulp I2S clock source*/ +#define ULP_I2S_MIN_SEL 0 /* Minimum Seletion value for ulp I2S clock source*/ +#define ULP_I2S_MAX_DIVISION_FACTOR 255 /* Maximum division factor value for ulp SSI clock*/ +#define ULP_I2S_MIN_DIVISION_FACTOR 0 /* Minimum division factor value for ulp SSI clock*/ + +/*ULP UART CLOCK*/ +#define ULP_UART_MAX_SEL 7 /* Maximum Seletion value for ulp Uart clock source*/ +#define ULP_UART_MIN_SEL 0 /* Minimum Seletion value for ulp Uart clock source*/ +#define ULP_UART_MAX_DIVISION_FACTOR 7 /* Maximum division factor value for ulp Uart clock*/ +#define ULP_UART_MIN_DIVISION_FACTOR 0 /* Minimum division factor value for ulp Uart clock*/ + +/*ULP AUX CLOCK*/ +#define ULP_AUX_MAX_SEL 8 /* Maximum Seletion value for ulp Aux clock source*/ +#define ULP_AUX_MIN_SEL 0 /* Minimum Seletion value for ulp Aux clock source*/ +#define ULP_AUX_MAX_DIVISION_FACTOR 255 /* Maximum division factor value for ulp Aux clock*/ +#define ULP_AUX_MIN_DIVISION_FACTOR 0 /* Minimum division factor value for ulp Aux clock*/ + +/*ULP TIMER CLOCK*/ +#define ULP_TIMER_MAX_SEL 6 /* Maximum Seletion value for ulp Timer clock source*/ +#define ULP_TIMER_MIN_SEL 0 /* Minimum Seletion value for ulp Tiemer clock source*/ + +/*ULP VAD CLOCK*/ +#define ULP_VAD_MAX_SEL 8 /* Maximum Seletion value for ulp Vad clock source*/ +#define ULP_VAD_MIN_SEL 0 /* Minimum Seletion value for ulp Vad clock source*/ +#define ULP_VAD_FCLK_MAX_SEL 8 /* Maximum Seletion value for ulp Vad fclock source*/ +#define ULP_VAD_FCLK_MIN_SEL 0 /* Minimum Seletion value for ulp Vad fclock source*/ +#define ULP_VAD_MAX_DIVISION_FACTOR 255 /* Maximum division factor value for ulp Vad clock*/ +#define ULP_VAD_MIN_DIVISION_FACTOR 0 /* Minimum division factor value for ulp Vad clock*/ + +/*ULP TOUCH CLOCK*/ +#define ULP_TOUCH_MAX_SEL 6 /* Maximum Seletion value for ulp Touch clock source*/ +#define ULP_TOUCH_MIN_SEL 0 /* Minimum Seletion value for ulp Touch clock source*/ +#define ULP_TOUCH_MAX_DIVISION_FACTOR 255 /* Maximum division factor value for ulp Touch clock*/ +#define ULP_TOUCH_MIN_DIVISION_FACTOR 0 /* Minimum division factor value for ulp Touch clock*/ + +/*ULP SLEEP SENSOR */ +#define ULP_SLP_SENSOR_MAX_DIVISION_FACTOR 255 /* Maximum division factor value for ulp Sleep sensor clock*/ +#define ULP_SLP_SENSOR_MIN_DIVISION_FACTOR 0 /* Minimum division factor value for ulp Sleep sensor clock*/ +/** + *@brief ulpss Reference Input clock source selection + **/ +typedef enum ULPSS_REF_CLK_SEL { + ULPSS_REF_BYP_CLK = 1, /*!< REF_BYP_CLK selection*/ + ULPSS_ULP_32MHZ_RC_CLK = 2, /*!< ULP_32MHZ_RC_CLK selection*/ + ULPSS_RF_REF_CLK = 3, /*!< RF_REF_CLK selection*/ + ULPSS_MEMS_REF_CLK = 4, /*!< MEMS_REF_CLK selection*/ + ULPSS_ULP_20MHZ_RINGOSC_CLK = 5, /*!< ULP_20MHZ_RINGOSC_CLK selection*/ + ULPSS_ULP_DOUBLER_CLK = 6, /*!< ULP_DOUBLER_CLK selection*/ +} ULPSS_REF_CLK_SEL_T; +/** +*@brief Different possible ref_clk sources for Ulp_proc_clk +**/ +typedef enum ULP_PROC_CLK_SELECT { + ULP_PROC_REF_CLK, /*!< ULP_REF_CLK selection*/ + ULP_PROC_ULP_32KHZ_RO_CLK, /*!< ULP_32KHZ_RO_CLK selection*/ + ULP_PROC_ULP_32KHZ_RC_CLK, /*!< ULP_32KHZ_RC_CLK selection*/ + ULP_PROC_ULP_32KHZ_XTAL_CLK, /*!< ULP_32KHZ_XTAL_CLK selection*/ + ULP_PROC_ULP_32MHZ_RC_CLK, /*!< ULP_32MHZ_RC_CLK selection*/ + ULP_PROC_ULP_20MHZ_RO_CLK, /*!< ULP_20MHZ_RO_CLK selection*/ + ULP_PROC_SOC_CLK, /*!< SOC_CLK selection*/ + ULP_PROC_ULP_DOUBLER_CLK /*!< ULP_DOUBLER_CLK selection*/ +} ULP_PROC_CLK_SELECT_T; +/** +*@brief Different possible input clk sources for Ulp_SSI_clk +**/ +typedef enum ULP_SSI_CLK_SELECT { + + ULP_SSI_REF_CLK, /*!< ULP_REF_CLK selection*/ + ULP_SSI_ULP_32KHZ_RO_CLK, /*!< ULP_32KHZ_RO_CLK selection*/ + ULP_SSI_ULP_32KHZ_RC_CLK, /*!< ULP_32KHZ_RC_CLK selection*/ + ULP_SSI_ULP_32KHZ_XTAL_CLK, /*!< ULP_32KHZ_XTAL_CLK selection*/ + ULP_SSI_ULP_32MHZ_RC_CLK, /*!< ULP_32MHZ_RC_CLK selection*/ + ULP_SSI_ULP_20MHZ_RO_CLK, /*!< ULP_20MHZ_RO_CLK selection*/ + ULP_SSI_SOC_CLK, /*!< SOC_CLK selection*/ +} ULP_SSI_CLK_SELECT_T; +/** +*@brief Different possible input clk sources for Ulp_I2S_clk +**/ +typedef enum ULP_I2S_CLK_SELECT { + + ULP_I2S_REF_CLK, /*!< ULP_REF_CLK selection*/ + ULP_I2S_ULP_32KHZ_RO_CLK, /*!< ULP_32KHZ_RO_CLK selection*/ + ULP_I2S_ULP_32KHZ_RC_CLK, /*!< ULP_32KHZ_RC_CLK selection*/ + ULP_I2S_ULP_32KHZ_XTAL_CLK, /*!< ULP_32KHZ_XTAL_CLK selection*/ + ULP_I2S_ULP_32MHZ_RC_CLK, /*!< ULP_32MHZ_RC_CLK selection*/ + ULP_I2S_ULP_20MHZ_RO_CLK, /*!< ULP_20MHZ_RO_CLK selection*/ + ULP_I2S_SOC_CLK, /*!< SOC_CLK selection*/ + ULP_I2S_ULP_DOUBLER_CLK, /*!< ULP_DOUBLER_CLK selection*/ + ULP_I2S_PLL_CLK /*!< I2s_PLL_CLK selection*/ + +} ULP_I2S_CLK_SELECT_T; +/** +*@brief Different possible input clk sources for Ulp_Uart_clk +**/ +typedef enum ULP_UART_CLK_SELECT { + + ULP_UART_REF_CLK, /*!< ULP_REF_CLK selection*/ + ULP_UART_ULP_32KHZ_RO_CLK, /*!< ULP_32KHZ_RO_CLK selection*/ + ULP_UART_ULP_32KHZ_RC_CLK, /*!< ULP_32KHZ_RC_CLK selection*/ + ULP_UART_ULP_32KHZ_XTAL_CLK, /*!< ULP_32KHZ_XTAL_CLK selection*/ + ULP_UART_ULP_32MHZ_RC_CLK, /*!< ULP_32MHZ_RC_CLK selection*/ + ULP_UART_ULP_20MHZ_RO_CLK, /*!< ULP_20MHZ_RO_CLK selection*/ + ULP_UART_SOC_CLK, /*!< SOC_CLK selection*/ + ULP_UART_ULP_DOUBLER_CLK, /*!< ULP_DOUBLER_CLK selection*/ +} ULP_UART_CLK_SELECT_T; +/** +*@brief Different possible input clk sources for Ulp_Timer_clk +**/ +typedef enum ULP_TIMER_CLK_SELECT { + + ULP_TIMER_REF_CLK, /*!< ULP_REF_CLK selection*/ + ULP_TIMER_32KHZ_RO_CLK, /*!< ULP_32KHZ_RO_CLK selection*/ + ULP_TIMER_32KHZ_RC_CLK, /*!< ULP_32KHZ_RC_CLK selection*/ + ULP_TIMER_32KHZ_XTAL_CLK, /*!< ULP_32KHZ_XTAL_CLK selection*/ + ULP_TIMER_32MHZ_RC_CLK, /*!< ULP_32MHZ_RC_CLK selection*/ + ULP_TIMER_20MHZ_RO_CLK, /*!< ULP_20MHZ_RO_CLK selection*/ + ULP_TIMER_ULP_SOC_CLK, /*!< SOC_CLK selection*/ +} ULP_TIMER_CLK_SELECT_T; +/** +*@brief Different possible input clk sources for Ulp_AUX_clk +**/ +typedef enum ULP_AUX_CLK_SELECT { + + ULP_AUX_REF_CLK, /*!< ULP_REF_CLK selection*/ + ULP_AUX_32KHZ_RO_CLK, /*!< ULP_32KHZ_RO_CLK selection*/ + ULP_AUX_32KHZ_RC_CLK, /*!< ULP_32KHZ_RC_CLK selection*/ + ULP_AUX_32KHZ_XTAL_CLK, /*!< ULP_32KHZ_XTAL_CLK selection*/ + ULP_AUX_32MHZ_RC_CLK, /*!< ULP_32MHZ_RC_CLK selection*/ + ULP_AUX_20MHZ_RO_CLK, /*!< ULP_20MHZ_RO_CLK selection*/ + ULP_AUX_ULP_SOC_CLK, /*!< SOC_CLK selection*/ + ULP_AUX_ULP_DOUBLER_CLK, /*!< ULP_DOUBLER_CLK selection*/ + ULP_AUX_I2S_PLL_CLK /*!< I2s_PLL_CLK selection*/ +} ULP_AUX_CLK_SELECT_T; +/** +*@brief Different possible input clk sources for Ulp_Vad_clk +**/ +typedef enum ULP_VAD_CLK_SELECT { + + ULP_VAD_32KHZ_RO_CLK, /*!< ULP_32KHZ_RO_CLK selection*/ + ULP_VAD_32KHZ_RC_CLK, /*!< ULP_32KHZ_RC_CLK selection*/ + ULP_VAD_32KHZ_XTAL_CLK, /*!< ULP_32KHZ_XTAL_CLK selection*/ +} ULP_VAD_CLK_SELECT_T; +/** +*@brief Different possible input clk sources for Ulp_Vad_fclk +**/ +typedef enum ULP_VAD_FCLK_SELECT { + + ULP_VAD_ULP_PROCESSOR_CLK, /*!< ULP_PROCESSOR_CLK selection*/ + ULP_VAD_REF_CLK, /*!< ULP_REF_CLK selection*/ + ULP_VAD_32MHZ_RC_CLK, /*!< ULP_32MHZ_RC_CLK selection*/ + ULP_VAD_20MHZ_RO_CLK, /*!< ULP_20MHZ_RO_CLK selection*/ + ULP_VAD_ULP_SOC_CLK, /*!< SOC_CLK selection*/ +} ULP_VAD_FCLK_SELECT_T; +/** +*@brief Different possible input clk sources for Ulp_Touch_clk +**/ +typedef enum ULP_TOUCH_CLK_SELECT { + + ULP_TOUCH_REF_CLK, /*!< ULP_REF_CLK selection*/ + ULP_TOUCH_32KHZ_RO_CLK, /*!< ULP_32KHZ_RO_CLK selection*/ + ULP_TOUCH_32KHZ_RC_CLK, /*!< ULP_32KHZ_RC_CLK selection*/ + ULP_TOUCH_32KHZ_XTAL_CLK, /*!< ULP_32KHZ_XTAL_CLK selection*/ + ULP_TOUCH_32MHZ_RC_CLK, /*!< ULP_32MHZ_RC_CLK selection*/ + ULP_TOUCH_20MHZ_RO_CLK, /*!< ULP_20MHZ_RO_CLK selection*/ + ULP_TOUCH_ULP_SOC_CLK /*!< SOC_CLK selection*/ + +} ULP_TOUCH_CLK_SELECT_T; + +/** +*@brief list of peripherals, particular ulp clock that to be disabled +**/ +typedef enum ULPPERIPHERALS_CLK { + ULP_I2C_CLK, /*!< Enables or Disables ULP_I2C Peripheral clock when it is passed */ + ULP_EGPIO_CLK, /*!< Enables or Disables Ulp_Egpio Peripheral clock when it is passed */ + ULP_AUX_CLK, /*!< Enables or Disables Ulp_Aux Peripheral clock when it is passed */ + ULP_FIM_CLK, /*!< Enables or Disables Ulp_Fim Peripheral clock when it is passed */ + ULP_VAD_CLK, /*!< Enables or Disables Ulp_Vad Peripheral clock when it is passed */ + ULP_TIMER_CLK, /*!< Enables or Disables Ulp_Timer Peripheral clock when it is passed */ + ULP_UDMA_CLK, /*!< Enables or Disables Ulp_Udma Peripheral clock when it is passed */ + ULP_TOUCH_CLK, /*!< Enables or Disables Ulp_Touch Peripheral clock when it is passed */ + ULP_UART_CLK, /*!< Enables or Disables Ulp_Uart Peripheral clock when it is passed */ + ULP_SSI_CLK, /*!< Enables or Disables Ulp_SSI Peripheral clock when it is passed */ + ULP_I2S_CLK, /*!< Enables or Disables Ulp_I2S Peripheral clock when it is passed */ +} ULPPERIPHERALS_CLK_T; + +rsi_error_t ulpss_ulp_proc_clk_config(ULPCLK_Type *pULPCLK, + ULP_PROC_CLK_SELECT_T clkSource, + uint16_t divFactor, + cdDelay delayFn); +rsi_error_t ulpss_ref_clk_config(ULPSS_REF_CLK_SEL_T clkSource); + +rsi_error_t ulpss_clock_config(M4CLK_Type *pCLK, boolean_t clkEnable, uint16_t divFactor, boolean_t oddDivFactor); + +rsi_error_t ulpss_ulp_proc_clk_config(ULPCLK_Type *pULPCLK, + ULP_PROC_CLK_SELECT_T clkSource, + uint16_t divFactor, + cdDelay delayFn); + +rsi_error_t ulpss_ulp_peri_clk_enable(ULPCLK_Type *pULPCLK, uint32_t u32Flags); + +rsi_error_t ulpss_ulp_peri_clk_disable(ULPCLK_Type *pULPCLK, uint32_t u32Flags); + +rsi_error_t ulpss_ulp_dyn_clk_enable(ULPCLK_Type *pULPCLK, uint32_t u32Flags); + +rsi_error_t ulpss_ulp_dyn_clk_disable(ULPCLK_Type *pULPCLK, uint32_t u32Flags); + +rsi_error_t ulpss_ulp_ssi_clk_config(ULPCLK_Type *pULPCLK, + CLK_ENABLE_T clkType, + ULP_SSI_CLK_SELECT_T clkSource, + uint16_t divFactor); + +rsi_error_t ulpss_ulp_i2s_clk_config(ULPCLK_Type *pULPCLK, ULP_I2S_CLK_SELECT_T clkSource, uint16_t divFactor); + +rsi_error_t ulpss_ulp_uar_clk_config(ULPCLK_Type *pULPCLK, + CLK_ENABLE_T clkType, + boolean_t bFrClkSel, + ULP_UART_CLK_SELECT_T clkSource, + uint16_t divFactor); + +rsi_error_t ulpss_time_clk_config(ULPCLK_Type *pULPCLK, + CLK_ENABLE_T clkType, + boolean_t bTmrSync, + ULP_TIMER_CLK_SELECT_T clkSource, + uint8_t skipSwitchTime); + +rsi_error_t ulpss_aux_clk_config(ULPCLK_Type *pULPCLK, CLK_ENABLE_T clkType, ULP_AUX_CLK_SELECT_T clkSource); + +rsi_error_t ulpss_vad_clk_config(ULPCLK_Type *pULPCLK, + ULP_VAD_CLK_SELECT_T clkSource, + ULP_VAD_FCLK_SELECT_T FclkSource, + uint16_t divFactor); + +rsi_error_t ulpss_touch_clk_config(ULPCLK_Type *pULPCLK, ULP_TOUCH_CLK_SELECT_T clkSource, uint16_t divFactor); + +rsi_error_t ulpss_slp_sensor_clk_config(ULPCLK_Type *pULPCLK, boolean_t clkEnable, uint32_t divFactor); + +rsi_error_t ulpss_peripheral_enable(ULPCLK_Type *pULPCLK, ULPPERIPHERALS_CLK_T module, CLK_ENABLE_T clkType); + +rsi_error_t ulpss_peripheral_disable(ULPCLK_Type *pULPCLK, ULPPERIPHERALS_CLK_T module); + +rsi_error_t ulpss_time_clk_disable(ULPCLK_Type *pULPCLK); + +#endif /*__RSI_ULPSS_CLK_H__*/ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_wwdt.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_wwdt.h new file mode 100644 index 000000000..3079e7776 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_wwdt.h @@ -0,0 +1,208 @@ +/******************************************************************************* +* @file rsi_wwdt.h +* @brief +******************************************************************************* +* # License +* Copyright 2020 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +/** + * Includes + */ +#ifndef __RSI_WDT_H__ +#define __RSI_WDT_H__ + +#ifdef __cplusplus +extern "C" { +#endif +#include "rsi_ccp_common.h" +#include "base_types.h" +#include "rsi_power_save.h" + +#ifndef UNUSED_PARAMETER +#define UNUSED_PARAMETER(x) (void)(x) +#endif // UNUSED_PARAMETER + +#define WDT_SYSTEM_RESET_TIMER 0x3 +#define WDT_INTERRUPT_TIMER 0x1 +#define WDT_IRQHandler IRQ020_Handler /*!MCU_WWD_WINDOW_TIMER_b.WINDOW_TIMER = (unsigned int)(u8WindowTimerVal & 0x0F); +} + +/** + * @fn void RSI_WWDT_ConfigIntrTimer(MCU_WDT_Type *pstcWDT , uint16_t u16IntrTimerVal) + * @brief This API is used to configure the interrupt timer of the watch dog timer + * @param[in] pstcWDT : pointer to the WDT register instance + * @param[in] u16IntrTimerVal : interrupt timer value + * @return None + */ +STATIC INLINE void RSI_WWDT_ConfigIntrTimer(MCU_WDT_Type *pstcWDT, uint16_t u16IntrTimerVal) +{ + pstcWDT->MCU_WWD_INTERRUPT_TIMER_b.WWD_INTERRUPT_TIMER = (unsigned int)(u16IntrTimerVal & 0x1F); +} + +/** + * @fn void RSI_WWDT_ConfigSysRstTimer(MCU_WDT_Type *pstcWDT , uint16_t u16SysRstVal) + * @brief This API is used to configure the system reset timer of the watch dog timer + * @param[in] pstcWDT : pointer to the WDT register instance + * @param[in] u16SysRstVal : reset value + * @return NONE + */ +STATIC INLINE void RSI_WWDT_ConfigSysRstTimer(MCU_WDT_Type *pstcWDT, uint16_t u16SysRstVal) +{ + pstcWDT->MCU_WWD_SYSTEM_RESET_TIMER_b.WWD_SYSTEM_RESET_TIMER = (unsigned int)(u16SysRstVal & 0x1F); +} + +/** + * @fn void RSI_WWDT_Disable(MCU_WDT_Type *pstcWDT) + * @brief This API is used to Disable the Watch dog timer + * @param[in] pstcWDT :pointer to the WDT register instance + * @return None + */ +STATIC INLINE void RSI_WWDT_Disable(MCU_WDT_Type *pstcWDT) +{ + /*0xF0 to Disable the watch dog */ + pstcWDT->MCU_WWD_MODE_AND_RSTART_b.WWD_MODE_EN_STATUS = 0xF0; +} + +/** + * @fn void RSI_WWDT_ReStart(MCU_WDT_Type *pstcWDT) + * @brief This API is used to restart the Watch dog timer + * @param[in] pstcWDT :pointer to the WDT register instance + * @return None + */ +STATIC INLINE void RSI_WWDT_ReStart(MCU_WDT_Type *pstcWDT) +{ + pstcWDT->MCU_WWD_MODE_AND_RSTART_b.WWD_MODE_RSTART = 1U; +} + +/** + * @fn void RSI_WWDT_IntrUnMask(void) + * @brief This API is used to unmask the Watch dog timer + * @return None + */ +STATIC INLINE void RSI_WWDT_IntrUnMask(void) +{ + NPSS_INTR_MASK_CLR_REG = NPSS_TO_MCU_WDT_INTR; +} + +/** + * @fn void RSI_WWDT_IntrMask(void) + * @brief This API is used to mask the Watch dog timer + * @return None + */ +STATIC INLINE void RSI_WWDT_IntrMask(void) +{ + NPSS_INTR_MASK_SET_REG = NPSS_TO_MCU_WDT_INTR; +} + +/** + * @fn void RSI_WWDT_SysRstOnProcLockEnable(MCU_WDT_Type *pstcWDT) + * @brief This API is used to enable Watch dog timer to reset system on processor stuck + * @return None + */ +STATIC INLINE void RSI_WWDT_SysRstOnProcLockEnable(MCU_WDT_Type *pstcWDT) +{ + pstcWDT->MCU_WWD_ARM_STUCK_EN_b.PROCESSOR_STUCK_RESET_EN = ENABLE; +} + +/** + * @fn void RSI_WWDT_SysRstOnProcLockDisable(MCU_WDT_Type *pstcWDT) + * @brief This API is used to disable Watch dog timer to reset system on processor stuck + * @return None + */ +STATIC INLINE void RSI_WWDT_SysRstOnProcLockDisable(MCU_WDT_Type *pstcWDT) +{ + pstcWDT->MCU_WWD_ARM_STUCK_EN_b.PROCESSOR_STUCK_RESET_EN = DISABLE; +} + +/** + * @fn void RSI_WWDT_GetProcLockSignal(MCU_WDT_Type *pstcWDT) + * @brief This API is used to read signal for processor stuck reset enable + * @return None + */ +STATIC INLINE uint8_t RSI_WWDT_GetProcLockRstEnableSignal(MCU_WDT_Type *pstcWDT) +{ + if (pstcWDT->MCU_WWD_ARM_STUCK_EN_b.PROCESSOR_STUCK_RESET_EN_) { + return 1; + } else { + return 0; + } +} + +/** + * @fn uint16_t RSI_WWDT_GetIntrTime(MCU_WDT_Type *pstcWDT) + * @brief This API is used to read the interrupt time of the watch dog timer + * @param[in] pstcWDT : pointer to the WDT register instance + * @return uint8_t : interrupt timer value + */ +STATIC INLINE uint8_t RSI_WWDT_GetIntrTime(MCU_WDT_Type *pstcWDT) +{ + uint8_t interrupt_time; + interrupt_time = pstcWDT->MCU_WWD_INTERRUPT_TIMER_b.WWD_INTERRUPT_TIMER; + return interrupt_time; +} + +/** + * @fn uint16_t RSI_WWDT_GetSysRstTime(MCU_WDT_Type *pstcWDT) + * @brief This API is used to read the system reset time of the watch dog timer + * @param[in] pstcWDT : pointer to the WDT register instance + * @return uint8_t : system reset timer value + */ +STATIC INLINE uint8_t RSI_WWDT_GetSysRstTime(MCU_WDT_Type *pstcWDT) +{ + uint8_t system_reset_time; + system_reset_time = pstcWDT->MCU_WWD_SYSTEM_RESET_TIMER_b.WWD_SYSTEM_RESET_TIMER; + return system_reset_time; +} + +/** + * @fn uint8_t RSI_WWDT_GetWindowTime(MCU_WDT_Type *pstcWDT) + * @brief This API is used to read the system reset time of the watch dog timer + * @param[in] pstcWDT : pointer to the WDT register instance + * @return uint8_t : system reset timer value + */ +STATIC INLINE uint8_t RSI_WWDT_GetWindowTime(MCU_WDT_Type *pstcWDT) +{ + uint8_t window_time; + window_time = pstcWDT->MCU_WWD_WINDOW_TIMER_b.WINDOW_TIMER; + return window_time; +} +// Function prototypes +void RSI_WWDT_IntrClear(void); + +uint8_t RSI_WWDT_GetIntrStatus(void); + +void RSI_WWDT_DeInit(MCU_WDT_Type *pstcWDT); + +void RSI_WWDT_Start(MCU_WDT_Type *pstcWDT); + +void RSI_WWDT_Init(MCU_WDT_Type *pstcWDT); +void IRQ020_Handler(void); + +#ifdef __cplusplus +} +#endif + +/*End of file not truncated*/ +#endif /*__RSI_WDT_H__*/ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_ipmu.c b/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_ipmu.c new file mode 100644 index 000000000..e661bd069 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_ipmu.c @@ -0,0 +1,1661 @@ +/******************************************************************************* +* @file rsi_ipmu.c +* @brief +******************************************************************************* +* # License +* Copyright 2020 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +/** + * Includes + */ +#include "rsi_system_config.h" +#include "rsi_ipmu.h" +#include "rsi_pll.h" +#include "rsi_ulpss_clk.h" + +/** + * @fn void RSI_IPMU_UpdateIpmuCalibData_efuse(efuse_ipmu_t *ipmu_calib_data) + * @brief This function prepares the data from the ipmu calib structure content and writes to each specific register + * @param[in] ipmu_calib_data : pointer of calibrate data + * @return none + */ +void RSI_IPMU_UpdateIpmuCalibData_efuse(efuse_ipmu_t *ipmu_calib_data) +{ + uint32_t data = 0, value = 0; + uint32_t mask = 0; + /* over writing the efuse arrays */ + +#ifdef CHIP_9118 + /* POC_BIAS_EFUSE */ + data = (ipmu_calib_data->trim_0p5na1 | ipmu_calib_data->trim_0p5na2 << 1); + mask = MASK_BITS(22, 0); + value = poc_bias_efuse[2]; + value &= ~mask; + value |= data; + poc_bias_efuse[2] = value; +#endif + +#ifdef SLI_SI917 + /* POC_BIAS_EFUSE */ + data = (ipmu_calib_data->trim_0p5na1); + mask = MASK_BITS(22, 0); + value = poc_bias_efuse[2]; + value &= ~mask; + value |= data; + poc_bias_efuse[2] = value; +#endif + +#ifdef CHIP_9118 + /* BG_TRIM_EFUSE */ + data = (ipmu_calib_data->bg_r_vdd_ulp | ipmu_calib_data->bg_r_ptat_vdd_ulp << 3); + mask = MASK_BITS(22, 0); + value = bg_trim_efuse[4]; + value &= ~mask; + value |= data; + bg_trim_efuse[4] = value; +#endif + +#ifdef SLI_SI917 + /* BG_TRIM_EFUSE */ + data = (ipmu_calib_data->bg_r_ptat_vdd_ulp); + mask = MASK_BITS(22, 0); + value = bg_trim_efuse[2]; + value &= ~mask; + value |= data; + bg_trim_efuse[2] = value; + + /* BG_TRIM_EFUSE */ + data = (ipmu_calib_data->bg_r_vdd_ulp); + mask = MASK_BITS(22, 0); + value = bg_trim_efuse[4]; + value &= ~mask; + value |= data; + bg_trim_efuse[4] = value; +#endif + +#ifdef CHIP_9118 + /* POC2 ( blackout_trim_efuse )*/ + data = (ipmu_calib_data->resbank_trim); + mask = MASK_BITS(22, 0); + value = blackout_trim_efuse[2]; + value &= ~mask; + value |= data; + blackout_trim_efuse[2] = value; +#endif + + /* M32RC_EFUSE */ + data = ipmu_calib_data->trim_sel; + mask = MASK_BITS(22, 0); + value = m32rc_osc_trim_efuse[2]; + value &= ~mask; + value |= data; + m32rc_osc_trim_efuse[2] = value; + + /* dblr_32m_trim_efuse */ + data = ipmu_calib_data->del_2x_sel; + mask = MASK_BITS(22, 0); + value = dblr_32m_trim_efuse[2]; + value &= ~mask; + value |= data; + dblr_32m_trim_efuse[2] = value; + + /* ro_32khz_trim_efuse */ + data = ipmu_calib_data->freq_trim; + mask = MASK_BITS(22, 0); + value = ro_32khz_trim_efuse[2]; + value &= ~mask; + value |= data; + ro_32khz_trim_efuse[2] = value; + + /* rc_16khz_trim_efuse */ + data = (uint32_t)(ipmu_calib_data->coarse_trim_16k | ipmu_calib_data->fine_trim_16k << 2); + mask = MASK_BITS(22, 0); + value = rc_16khz_trim_efuse[2]; + value &= ~mask; + value |= data; + rc_16khz_trim_efuse[2] = value; + + /* rc_64khz_trim_efuse */ + data = (uint32_t)(ipmu_calib_data->coarse_trim_64k | ipmu_calib_data->fine_trim_64k << 2); + mask = MASK_BITS(22, 0); + value = rc_64khz_trim_efuse[2]; + value &= ~mask; + value |= data; + rc_64khz_trim_efuse[2] = value; + + /* xtal1_bias_efuse */ + data = (ipmu_calib_data->xtal1_trim_32k); + mask = MASK_BITS(22, 0); + value = xtal1_bias_efuse[2]; + value &= ~mask; + value |= data; + xtal1_bias_efuse[2] = value; + + /* xtal2_bias_efuse */ + data = (ipmu_calib_data->xtal2_trim_32k); + mask = MASK_BITS(22, 0); + value = xtal2_bias_efuse[2]; + value &= ~mask; + value |= data; + xtal2_bias_efuse[2] = value; + +#ifndef AT_EFUSE_DATA_1P19 + /* m20rc_osc_trim_efuse */ + data = ((ipmu_calib_data->reserved1) & 0x7F); + mask = MASK_BITS(22, 0); + value = m20rc_osc_trim_efuse[2]; + value &= ~mask; + value |= data; + m20rc_osc_trim_efuse[2] = value; +#endif + +#ifdef AT_EFUSE_DATA_1P19 + /* m20rc_osc_trim_efuse */ + data = (ipmu_calib_data->trim_sel_20Mhz); + ; + mask = MASK_BITS(22, 0); + value = m20rc_osc_trim_efuse[2]; + value &= ~mask; + value |= data; + m20rc_osc_trim_efuse[2] = value; +#endif + + /*m20ro_osc_trim_efuse */ + data = (ipmu_calib_data->trim_ring_osc); + mask = MASK_BITS(22, 0); + value = m20ro_osc_trim_efuse[2]; + value &= ~mask; + value |= data; + m20ro_osc_trim_efuse[2] = value; + + /* vbatt_status_trim_efuse */ + data = (ipmu_calib_data->vbatt_status_1); + mask = MASK_BITS(22, 0); + value = vbatt_status_trim_efuse[2]; + value &= ~mask; + value |= data; + vbatt_status_trim_efuse[2] = value; + + /* ro_ts_efuse */ + data = (ipmu_calib_data->f2_nominal); + mask = MASK_BITS(22, 0); + value = ro_ts_efuse[2]; + value &= ~mask; + value |= data; + ro_ts_efuse[2] = value; + + /* ro_tempsense_config */ + data = (ipmu_calib_data->str_temp_slope); + mask = MASK_BITS(22, 0); + value = ro_tempsense_config[2]; + value &= ~mask; + value |= data; + ro_tempsense_config[2] = value; + +#ifdef AT_EFUSE_DATA_1P19 + /*BJT temperature sensor efuse value update*/ + /* delvbe_ts_efuse*/ + data = (ipmu_calib_data->str_bjt_temp_sense_off); + mask = MASK_BITS(22, 0); + value = delvbe_tsbjt_efuse[2]; + value &= ~mask; + value |= data; + delvbe_tsbjt_efuse[2] = value; + + /* vbg_ts_efuse */ + data = (ipmu_calib_data->vbg_tsbjt_efuse); + mask = MASK_BITS(22, 0); + value = vbg_tsbjt_efuse[2]; + value &= ~mask; + value |= data; + vbg_tsbjt_efuse[2] = value; +#endif + + /* retn_ldo_lptrim */ + data = (ipmu_calib_data->retn_ldo_lptrim); + mask = MASK_BITS(22, 0); + value = retnLP_volt_trim_efuse[2]; + value &= ~mask; + value |= data; + retnLP_volt_trim_efuse[2] = value; + + /* auxadc_off_diff_efuse */ + data = (ipmu_calib_data->auxadc_offset_diff); + mask = MASK_BITS(22, 0); + value = auxadc_off_diff_efuse[2]; + value &= ~mask; + value |= data; + auxadc_off_diff_efuse[2] = value; + + /* auxadc_gain_diff_efuse */ + data = (ipmu_calib_data->auxadc_invgain_diff); + mask = MASK_BITS(22, 0); + value = auxadc_gain_diff_efuse[2]; + value &= ~mask; + value |= data; + auxadc_gain_diff_efuse[2] = value; + + /* auxadc_off_se_efuse */ + data = (ipmu_calib_data->auxadc_offset_single); + mask = MASK_BITS(22, 0); + value = auxadc_off_se_efuse[2]; + value &= ~mask; + value |= data; + auxadc_off_se_efuse[2] = value; + + /* auxadc_gain_se_efuse */ + data = (ipmu_calib_data->auxadc_invgain_single); + mask = MASK_BITS(22, 0); + value = auxadc_gain_se_efuse[2]; + value &= ~mask; + value |= data; + auxadc_gain_se_efuse[2] = value; + + /* rc_32khz_trim_efuse */ + data = (uint32_t)(ipmu_calib_data->coarse_trim_32k | ipmu_calib_data->fine_trim_32k << 2); + mask = MASK_BITS(22, 0); + value = rc_32khz_trim_efuse[2]; + value &= ~mask; + value |= data; + rc_32khz_trim_efuse[2] = value; + +#ifndef AT_EFUSE_DATA_1P19 + /*If the 13 bits of WuRx(i.e.reserved1) in E-Fuse are zeros, + then overwrite this structure with the contents from RO32K_EFUSE*/ + if (!((ipmu_calib_data->reserved1) >> 7)) { + ro_32khz_trim00_efuse[2] = ro_32khz_trim_efuse[2]; + } else { + /*then write the contents of the (reserved1) last 5 bits + allotted to RO32K_00 */ + data = ((ipmu_calib_data->reserved1) & (0xF80)); + mask = MASK_BITS(22, 0); + value = ro_32khz_trim00_efuse[2]; + value &= ~mask; + value |= data; + ro_32khz_trim00_efuse[2] = value; + } +#endif + +#ifdef AT_EFUSE_DATA_1P19 + + /*If the 13 bits of WuRx(i.e.reserved1) in E-Fuse are zeros, + then overwrite this structure with the contents from RO32K_EFUSE*/ + if (!(ipmu_calib_data->ro_32khz_00_trim)) { + ro_32khz_trim00_efuse[2] = ro_32khz_trim_efuse[2]; + } else { + /*then write the contents of the (reserved1) last 5 bits + allotted to RO32K_00 */ + data = (ipmu_calib_data->ro_32khz_00_trim); + mask = MASK_BITS(22, 0); + value = ro_32khz_trim00_efuse[2]; + value &= ~mask; + value |= data; + ro_32khz_trim00_efuse[2] = value; + } +#endif + + /* buck_trim_efuse = set_vref1p3 */ + data = ((ipmu_calib_data->set_vref1p3)); + mask = MASK_BITS(22, 0); + value = buck_trim_efuse[2]; + value &= ~mask; + value |= data; + buck_trim_efuse[2] = value; + + /* ldosoc_trim_efuse = trim_r1_resistorladder */ + data = ((ipmu_calib_data->trim_r1_resistorladder)); + mask = MASK_BITS(22, 0); + value = ldosoc_trim_efuse[2]; + value &= ~mask; + value |= data; + ldosoc_trim_efuse[2] = value; + + /* dpwm_freq_trim_efuse = dpwm_freq_trim*/ + data = ((ipmu_calib_data->dpwm_freq_trim)); + mask = MASK_BITS(22, 0); + value = dpwm_freq_trim_efuse[2]; + value &= ~mask; + value |= data; + dpwm_freq_trim_efuse[2] = value; + +#ifdef AT_EFUSE_DATA_1P19 + /* scdc_hpldo_trim */ + data = ((ipmu_calib_data->scdc_hpldo_trim)); + mask = MASK_BITS(22, 0); + value = hpldo_volt_trim_efuse[2]; + value &= ~mask; + value |= data; + hpldo_volt_trim_efuse[2] = value; + + /* scdc_dcdc_trim */ + data = ((ipmu_calib_data->scdc_dcdc_trim)); + mask = MASK_BITS(22, 0); + value = scdc_volt_trim_efuse[2]; + value &= ~mask; + value |= data; + scdc_volt_trim_efuse[2] = value; +#endif + + return; +} + +/*==============================================*/ +/** + * @fn void RSI_IPMU_InitCalibData(void) + * @brief This function checks for magic byte in efuse/flash, copies the content if valid data present and calls to update the ipmu registers + * @return none + */ +void RSI_IPMU_InitCalibData(void) +{ + efuse_ipmu_t global_ipmu_calib_data; +#ifdef CHIP_9118 + uint8_t *calib_data_read_adr = NULL; + + /* Read the MCU boot status register */ + volatile retention_boot_status_word_t *retention_reg = (retention_boot_status_word_t *)MCURET_BOOTSTATUS; + /* Read the TA BBFFs storage register */ + volatile npss_boot_status_word0_t *npss_boot_status = (npss_boot_status_word0_t *)MCU_BBFF_STORAGE1_ADDR; + + if (retention_reg->product_mode == MCU) { + calib_data_read_adr = (uint8_t *)(MCU_MANF_DATA_BASE_ADDR); + } + if (retention_reg->product_mode == WISEMCU) { + if (npss_boot_status->ta_flash_present) { + calib_data_read_adr = (uint8_t *)(TA_MANF_DATA_BASE_ADDR); + } else { + calib_data_read_adr = (uint8_t *)(MCU_MANF_DATA_BASE_ADDR); + } + } + + /* Checks the Calibration values are present at MCU flash */ + if ((*(uint32_t *)(calib_data_read_adr + IPMU_VALUES_OFFSET)) == 0x00) { + //NO CALIB DATA. Return + return; + } + /* Checks the `Calibration values are present at MCU flash */ + if ((*(uint32_t *)(calib_data_read_adr + IPMU_VALUES_OFFSET)) == 0xFFFFFFFF) { + //NO CALIB DATA. Return + return; + } + + memcpy((void *)&global_ipmu_calib_data, (void *)(calib_data_read_adr + IPMU_VALUES_OFFSET), sizeof(efuse_ipmu_t)); + //rsi_cmd_m4_ta_secure_handshake(2,0,NULL,sizeof(efuse_ipmu_t),(uint8_t *)&global_ipmu_calib_data); +#endif + +#ifdef SLI_SI917 +#ifdef SLI_SI91X_MCU_COMMON_FLASH_MODE + /* Checks the Calibration values are present at MCU flash */ + if ((*(uint32_t *)(COMMON_FLASH_IPMU_VALUES_OFFSET)) == 0x00) { + //NO CALIB DATA. Return + return; + } + memcpy((void *)&global_ipmu_calib_data, (void *)(COMMON_FLASH_IPMU_VALUES_OFFSET), sizeof(efuse_ipmu_t)); +#else + /* Checks the Calibration values are present at MCU flash */ + if ((*(uint32_t *)(DUAL_FLASH_IPMU_VALUES_OFFSET)) == 0x00) { + //NO CALIB DATA. Return + return; + } + memcpy((void *)&global_ipmu_calib_data, (void *)(DUAL_FLASH_IPMU_VALUES_OFFSET), sizeof(efuse_ipmu_t)); +#endif +#endif + + //Dummy read + (void)PMU_SPI_DIRECT_ACCESS(PMU_PFM_REG_OFFSET); + + RSI_IPMU_UpdateIpmuCalibData_efuse(&global_ipmu_calib_data); + + //Dummy read + (void)PMU_SPI_DIRECT_ACCESS(PMU_PFM_REG_OFFSET); +} + +/*==============================================*/ +/** + * @brief This function Initialize IPMU and MCU FSM blocks + * @param void + * @return void + */ +void RSI_Ipmu_Init(void) +{ + ipmu_init(); +} + +/** + * @brief This function configures chip supply mode + * @param void + * @return void + */ +void RSI_Configure_Ipmu_Mode(void) +{ + configure_ipmu_mode(IPMU_MODE_VALUE); +} +void update_efuse_system_configs(int data, uint32_t config_ptr[]) +{ + uint32_t mask = 0, value = 0; + mask = MASK_BITS(22, 0); + value = config_ptr[2]; + value &= ~mask; + value |= (uint32_t)data; + config_ptr[2] = value; +} +/** + * @brief This function configures the Lower voltage level for DC-DC to 1.25V based on the DC-DC Trim value(for 1.35V) obtained from Calibration + * @return none + */ + +void RSI_Configure_DCDC_LowerVoltage(void) +{ + uint32_t pmu_1p2_ctrl_word, bypass_curr_ctrl_data; + + bypass_curr_ctrl_data = PMU_SPI_DIRECT_ACCESS(PMU_1P3_CTRL_REG_OFFSET); + pmu_1p2_ctrl_word = ((bypass_curr_ctrl_data >> 17) & 0xF) - 2; + bypass_curr_ctrl_data = PMU_SPI_DIRECT_ACCESS(BYPASS_CURR_CTRL_REG_OFFSET); + bypass_curr_ctrl_data &= (uint32_t)(~(0xF << 5)); + PMU_SPI_DIRECT_ACCESS(BYPASS_CURR_CTRL_REG_OFFSET) = (bypass_curr_ctrl_data | (pmu_1p2_ctrl_word << 5)); +} + +/*==============================================*/ +/** + * @fn void RSI_IPMU_PowerGateSet(uint32_t mask_vlaue) + * @brief This API is used to power-up the IPMU peripherals. + * @param[in] mask_vlaue : Ored value of peripheral power gate defines + * Possible values for this parameter are the following + * CMP_NPSS_PG_ENB + * ULP_ANG_CLKS_PG_ENB + * ULP_ANG_PWRSUPPLY_PG_ENB + * WURX_PG_ENB + * WURX_CORR_PG_ENB + * AUXADC_PG_ENB + * AUXADC_BYPASS_ISO_GEN + * AUXADC_ISOLATION_ENABLE + * AUXDAC_PG_ENB + * @return none + */ + +void RSI_IPMU_PowerGateSet(uint32_t mask_vlaue) +{ + uint32_t impuPowerGate = 0; + impuPowerGate = ULP_SPI_MEM_MAP(POWERGATE_REG_WRITE); + while (GSPI_CTRL_REG1 & SPI_ACTIVE) + ; + impuPowerGate = (impuPowerGate >> 5); + impuPowerGate |= mask_vlaue; + ULP_SPI_MEM_MAP(POWERGATE_REG_WRITE) = impuPowerGate; + while (GSPI_CTRL_REG1 & SPI_ACTIVE) + ; + /*Dummy read*/ + impuPowerGate = ULP_SPI_MEM_MAP(POWERGATE_REG_WRITE); + return; +} + +/*==============================================*/ +/** + * @fn void RSI_IPMU_PowerGateClr(uint32_t mask_vlaue) + * @brief This API is used to power-down the IPMU peripherals. + * @param[in] mask_vlaue : Ored value of peripheral power gate defines + * Possible values for this parameter are the following + * CMP_NPSS_PG_ENB + * ULP_ANG_CLKS_PG_ENB + * ULP_ANG_PWRSUPPLY_PG_ENB + * WURX_PG_ENB + * WURX_CORR_PG_ENB + * AUXADC_PG_ENB + * AUXADC_BYPASS_ISO_GEN + * AUXADC_ISOLATION_ENABLE + * AUXDAC_PG_ENB + * @return none + */ + +void RSI_IPMU_PowerGateClr(uint32_t mask_vlaue) +{ + uint32_t impuPowerGate = 0; + + if (mask_vlaue & (WURX_CORR_PG_ENB | WURX_PG_ENB)) { + ULP_SPI_MEM_MAP(0x141) &= ~BIT(20); + ULP_SPI_MEM_MAP(0x141) &= ~BIT(21); + } + + impuPowerGate = ULP_SPI_MEM_MAP(POWERGATE_REG_WRITE); + while (GSPI_CTRL_REG1 & SPI_ACTIVE) + ; + impuPowerGate = (impuPowerGate >> 5); + impuPowerGate &= ~mask_vlaue; + ULP_SPI_MEM_MAP(POWERGATE_REG_WRITE) = impuPowerGate; + while (GSPI_CTRL_REG1 & SPI_ACTIVE) + ; + return; +} + +/*==============================================*/ +/** + * @fn void RSI_IPMU_ClockMuxSel(uint8_t bg_pmu_clk) + * @brief This API is used to select clock to the BG-PMU + * @param[in] bg_pmu_clk : Selects the clock source to the BG-PMU module + * 1: RO 32KHz clock + * 2: MCU FSM clock + * @return none + */ + +void RSI_IPMU_ClockMuxSel(uint8_t bg_pmu_clk) +{ + bg_pmu_clk = (bg_pmu_clk - 1); + ULP_SPI_MEM_MAP(SELECT_BG_CLK) &= ~(BIT(0) | BIT(1)); + while (GSPI_CTRL_REG1 & SPI_ACTIVE) + ; + ULP_SPI_MEM_MAP(SELECT_BG_CLK) |= BIT(bg_pmu_clk); + while (GSPI_CTRL_REG1 & SPI_ACTIVE) + ; + return; +} + +/*==============================================*/ +/** + * @fn uint32_t RSI_IPMU_32MHzClkClib(void) + * @brief This API is used to auto calibrate the 32MHz RC clock + * @return trim value on success + */ + +uint32_t RSI_IPMU_32MHzClkClib(void) +{ + volatile int i, trim_value = 0; + /*Enables RC 32MHz clock and*/ + ULP_SPI_MEM_MAP(0x104) = (0x3FFFFF & 0x41368000); + /*Enable XTAL 40MHz clock through NPSS*/ + *(volatile uint32_t *)0x41300120 |= BIT(22); + i = 1000000; + while (i--) + ; + /*Selects NPSS reference clock to be CLK-40M_SOC*/ + ULP_SPI_MEM_MAP(0x106) = (0x3FFFFF & 0x41A48000); + /*Change spi trim select to 0*/ + ULP_SPI_MEM_MAP(0x107) = (0x3FFFFF & 0x41C04A14); + /*Pointing clks test out 1 to RC 32M clock*/ + ULP_SPI_MEM_MAP(0x10D) = (0x3FFFFF & 0x43600000); + /*Pointing clks test out to IPMU_TEST_OUT_0 = SOC[8] in mode 5*/ + ULP_SPI_MEM_MAP(0x143) = (0x3FFFFF & 0x50C00610); + /*Enable the high frequency clock calibration + * Enable the clock gate for npss ref clk + * Select the RC32M clock to calibrate + * */ + ULP_SPI_MEM_MAP(0x10A) = (0x3FFFFF & 0x42922290); + i = 100000; + while (i--) + ; + do { + /*wait for calibration done indication*/ + } while ((!(ULP_SPI_MEM_MAP(0x30C))) & BIT(20)); + /*Calibrated trim value*/ + trim_value = (int)ULP_SPI_MEM_MAP(0x30C); + trim_value = (trim_value >> 11); + trim_value = (trim_value & 0x7F); + /*Programming the calibrated trim to SPI register.*/ + ULP_SPI_MEM_MAP(0x104) |= (uint32_t)(trim_value << 14); + /*pointing the trim select to SPI*/ + ULP_SPI_MEM_MAP(0x107) = (0x3FFFFF & 0x41C05A14); + return (uint32_t)trim_value; +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_ProgramConfigData(uint32_t *config) + * @brief This API is used to program the any mcu configuration structure + * @param[in] config : pointer configuration + * @return RSI_OK on success + */ + +rsi_error_t RSI_IPMU_ProgramConfigData(uint32_t *config) +{ + volatile uint32_t index = 0, program_len = 0, reg_addr = 0; + volatile uint32_t reg_write_data = 0, clear_cnt = 0, cnt = 0; + volatile uint32_t reg_read_data = 0, write_mask = 0, write_bit_pos = 0; + volatile uint8_t msb = 0, lsb = 0; + + if (config == NULL) { + return INVALID_PARAMETERS; + } + /*Compute the number of entries in the array to program*/ + program_len = config[index]; + if (program_len == 0U) { + return INVALID_PARAMETERS; + } + for (index = 0; index < program_len; index++) { + reg_addr = config[(2U * index) + 1]; + reg_write_data = config[(2U * (index + 1))]; + + lsb = ((reg_write_data >> LSB_POSITION) & POSITION_BITS_MASK); + msb = ((reg_write_data >> MSB_POSITION) & POSITION_BITS_MASK); + + clear_cnt = (msb - lsb) + 1U; + /*MSB and LSB position counts validation */ + if (clear_cnt > MAX_BIT_LEN) { + // Return error + return INVALID_PARAMETERS; + } + /*Read register*/ + reg_read_data = *(volatile uint32_t *)reg_addr; + cnt = lsb; + write_mask = 0; + write_bit_pos = 0; + do { + reg_read_data &= ~BIT(cnt); + write_mask |= BIT(write_bit_pos); + cnt++; + write_bit_pos++; + } while (cnt < (clear_cnt + lsb)); + reg_write_data &= (write_mask); + /*Write to the hardware register*/ + reg_write_data = (reg_read_data | (reg_write_data << lsb)); + *(volatile uint32_t *)reg_addr = reg_write_data; + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn uint32_t RSI_APB_ProgramConfigData(uint32_t *config) + * @brief This API is used to program the any mcu configuration structure + * @param[in] config : pointer configuration + * @return reg_write_data on success. + */ + +uint32_t RSI_APB_ProgramConfigData(uint32_t *config) +{ + volatile uint32_t index = 0, program_len = 0, reg_addr = 0; + volatile uint32_t clear_cnt = 0, cnt = 0; + volatile uint32_t reg_write_data = 0, reg_read_data = 0, write_mask = 0, write_bit_pos = 0; + volatile uint8_t msb = 0, lsb = 0; + (void)reg_addr; + + if (config == NULL) { + return INVALID_PARAMETERS; + } + /*Compute the number of entries in the array to program*/ + program_len = config[index]; + if (program_len == 0U) { + return INVALID_PARAMETERS; + } + for (index = 0; index < program_len; index++) { + + reg_write_data = config[(2U * (index + 1))]; + + lsb = ((reg_write_data >> LSB_POSITION) & POSITION_BITS_MASK); + msb = ((reg_write_data >> MSB_POSITION) & POSITION_BITS_MASK); + + clear_cnt = (msb - lsb) + 1U; + /*MSB and LSB position counts validation */ + if (clear_cnt > MAX_BIT_LEN) { + // Return error + return INVALID_PARAMETERS; + } + cnt = lsb; + write_mask = 0; + write_bit_pos = 0; + do { + //reg_read_data &= ~BIT(cnt); + write_mask |= BIT(write_bit_pos); + cnt++; + write_bit_pos++; + } while (cnt < (clear_cnt + lsb)); + reg_write_data &= (write_mask); + /*Write to the hardware register*/ + reg_write_data = (reg_read_data | (reg_write_data << lsb)); + } + return reg_write_data; +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_CommonConfig(void) + * @brief This API is used to program the default system start-up IPMU hardware programming. + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_CommonConfig(void) +{ + return RSI_IPMU_ProgramConfigData(ipmu_common_config); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_PMUCommonConfig(void) + * @brief This API is used to program the default system start-up PMU hardware programming. + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_PMUCommonConfig(void) +{ + return RSI_IPMU_ProgramConfigData(pmu_common_config); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_PocbiasCurrent(void) + * @brief This API is used to Decreasing the bias current of RETN_LDO . + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_PocbiasCurrent(void) +{ + return RSI_IPMU_ProgramConfigData(poc_bias_current); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_PocbiasCurrent11(void) + * @brief This API is used to increasing the bias current of RETN_LDO . + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_PocbiasCurrent11(void) +{ + return RSI_IPMU_ProgramConfigData(poc_bias_current_11); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_RO32khzTrim00Efuse(void) + * @brief This API is used to trim to 32Khz RO . + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_RO32khzTrim00Efuse(void) +{ + return RSI_IPMU_ProgramConfigData(ro_32khz_trim00_efuse); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_RetnLdoVoltsel(void) + * @brief This API is used to setting RETN_LDO voltage to 0.7V. + * @return RSI_IPMU_ProgramConfigData on success . + */ + +rsi_error_t RSI_IPMU_RetnLdoVoltsel(void) +{ + return RSI_IPMU_ProgramConfigData(retn_ldo_voltsel); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_RetnLdo0p75(void) + * @brief This API is used to setting RETN_LDO voltage to 0.75V . + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_RetnLdo0p75(void) +{ + return RSI_IPMU_ProgramConfigData(retn_ldo_0p75); +} + +/*==============================================*/ +/** + * @fn void RSI_IPMU_RetnLdoLpmode(void) + * @brief This API is used to program enabling the RETN_LDO LP MODE . + * @return none + */ + +void RSI_IPMU_RetnLdoLpmode(void) +{ + RSI_IPMU_ProgramConfigData(retn_ldo_lpmode); + RSI_IPMU_ProgramConfigData(retnLP_volt_trim_efuse); +} + +/*==============================================*/ +/** + * @fn void RSI_IPMU_Retn_Voltage_Reduction(void) + * @brief This API is used to reduce the RETN_LDO voltage by 0.05V. + * @return none + */ + +void RSI_IPMU_Retn_Voltage_Reduction(void) +{ + uint32_t value, mask; + value = retnLP_volt_trim_efuse[2]; + mask = MASK_BITS(3, 0); + value &= mask; + if (value < RET_LDO_TRIM_VALUE_CHECK) { + retnLP_volt_trim_efuse[2] += RET_LDO_VOL_DECREASE; + } +} + +/*==============================================*/ +/** + * @fn void RSI_IPMU_Retn_Voltage_To_Default(void) + * @brief This API is used to change the RETN_LDO voltage to 0.8V. + * @return none + */ + +void RSI_IPMU_Retn_Voltage_To_Default(void) +{ + uint32_t mask; + mask = MASK_BITS(22, 0); + retnLP_volt_trim_efuse[2] &= ~mask; +} + +/*==============================================*/ +/** + * @fn void RSI_IPMU_Set_Higher_Pwm_Ro_Frequency_Mode_to_PMU(void) + * @brief This API is used to enable Higher Pwm Ro Frequency Mode for PMU. + * @return none + */ + +void RSI_IPMU_Set_Higher_Pwm_Ro_Frequency_Mode_to_PMU(void) +{ + PMU_SPI_MEM_MAP(PMU_FREQ_MODE_REG) &= ~(LOW_FREQ_PWM); +} +/*==============================================*/ +/** + * @fn void RSI_IPMU_RetnLdoHpmode(void) + * @brief This API is used to program enabling the RETN_LDO HP MODE . + * @return none + */ + +void RSI_IPMU_RetnLdoHpmode(void) +{ + RSI_IPMU_ProgramConfigData(retn_ldo_hpmode); + RSI_IPMU_ProgramConfigData(retnHP_volt_trim_efuse); +} +/** + * @fn void RSI_IPMU_SCDC_Enable(void) + * @brief This API is used to enable SCDC mode . + * @return none + */ +void RSI_IPMU_SCDC_Enable(void) +{ + RSI_IPMU_ProgramConfigData(ipmu_scdc_enable); +} +/** + * @fn void RSI_IPMU_HP_LDO_Enable(void) + * @brief This API is used to enable LDO mode . + * @return none + */ +void RSI_IPMU_HP_LDO_Enable(void) +{ + RSI_IPMU_ProgramConfigData(hp_ldo_voltsel); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_M32rc_OscTrimEfuse(void) + * @brief This API is used to program the trim value for 32Mhz RC oscillator . + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_M32rc_OscTrimEfuse(void) +{ + system_clocks.rc_32mhz_clock = DEFAULT_32MHZ_RC_CLOCK; + + if (system_clocks.m4_ref_clock_source == ULP_32MHZ_RC_CLK) { + system_clocks.m4ss_ref_clk = DEFAULT_32MHZ_RC_CLOCK; + } + if (system_clocks.ulp_ref_clock_source == ULPSS_ULP_32MHZ_RC_CLK) { + system_clocks.ulpss_ref_clk = DEFAULT_32MHZ_RC_CLOCK; + } + + return RSI_IPMU_ProgramConfigData(m32rc_osc_trim_efuse); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_M20rcOsc_TrimEfuse(void) + * @brief This API is used to program the trim value for 20Mhz RC oscillator . + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_M20rcOsc_TrimEfuse(void) +{ + system_clocks.rc_32mhz_clock = 20000000; + if (system_clocks.m4_ref_clock_source == ULP_32MHZ_RC_CLK) { + system_clocks.m4ss_ref_clk = 20000000; + } + if (system_clocks.ulp_ref_clock_source == ULPSS_ULP_32MHZ_RC_CLK) { + system_clocks.ulpss_ref_clk = 20000000; + } + return RSI_IPMU_ProgramConfigData(m20rc_osc_trim_efuse); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_DBLR32M_TrimEfuse(void) + * @brief This API is used to program DBLR 32MHz trim value . + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_DBLR32M_TrimEfuse(void) +{ + system_clocks.doubler_clock = 32000000; + return RSI_IPMU_ProgramConfigData(dblr_32m_trim_efuse); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_M20roOsc_TrimEfuse(void) + * @brief This API is used to program the trim value for 20Mhz RO oscillator . + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_M20roOsc_TrimEfuse(void) +{ + system_clocks.ro_20mhz_clock = DEFAULT_20MHZ_RO_CLOCK; + if (system_clocks.m4_ref_clock_source == ULP_20MHZ_RINGOSC_CLK) { + system_clocks.m4ss_ref_clk = DEFAULT_20MHZ_RO_CLOCK; + } + if (system_clocks.ulp_ref_clock_source == ULPSS_ULP_20MHZ_RINGOSC_CLK) { + system_clocks.ulpss_ref_clk = DEFAULT_20MHZ_RO_CLOCK; + } + return RSI_IPMU_ProgramConfigData(m20ro_osc_trim_efuse); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_RO32khz_TrimEfuse(void) + * @brief This API is used to program the trim value for 32KHz RO oscillator . + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_RO32khz_TrimEfuse(void) +{ + system_clocks.ro_32khz_clock = DEFAULT_32KHZ_RO_CLOCK; + + return RSI_IPMU_ProgramConfigData(ro_32khz_trim_efuse); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_RC16khz_TrimEfuse(void) + * @brief This API is used to program the trim value for 16KHz RC oscillator . + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_RC16khz_TrimEfuse(void) +{ + system_clocks.rc_32khz_clock = 16000; + return RSI_IPMU_ProgramConfigData(rc_16khz_trim_efuse); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_RC64khz_TrimEfuse(void) + * @brief This API is used to program the trim value for 64KHz RC oscillator . + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_RC64khz_TrimEfuse(void) +{ + system_clocks.rc_32khz_clock = 64000; + return RSI_IPMU_ProgramConfigData(rc_64khz_trim_efuse); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_RC32khz_TrimEfuse(void) + * @brief This API is used to program the trim value for 32KHz RC oscillator . + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_RC32khz_TrimEfuse(void) +{ + system_clocks.rc_32khz_clock = 32000; + return RSI_IPMU_ProgramConfigData(rc_32khz_trim_efuse); +} + +/*==============================================*/ +/** + * @fn uint32_t RSI_IPMU_RO_TsEfuse() + * @brief This API is used to program the nominal_count . + * @return RSI_APB_ProgramConfigData on success. + */ + +uint32_t RSI_IPMU_RO_TsEfuse() +{ + return RSI_APB_ProgramConfigData(ro_ts_efuse); +} + +/*==============================================*/ +/** + * @fn uint32_t RSI_IPMU_RO_TsConfig(void) + * @brief This API is used to program the RO Temp sensor slope . + * @return RSI_APB_ProgramConfigData on success. + */ + +uint32_t RSI_IPMU_RO_TsConfig(void) +{ + return RSI_APB_ProgramConfigData(ro_tempsense_config); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_Vbattstatus_TrimEfuse(void) + * @brief This API is used to program the trim value for Vbatt status . + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_Vbattstatus_TrimEfuse(void) +{ + return RSI_IPMU_ProgramConfigData(vbatt_status_trim_efuse); +} + +/*==============================================*/ +/** + * @fn uint32_t RSI_IPMU_Vbg_Tsbjt_Efuse(void) + * @brief This API is used to program the BG voltage for BJT temperature sensor + * @return RSI_APB_ProgramConfigData on success. + */ + +uint32_t RSI_IPMU_Vbg_Tsbjt_Efuse(void) +{ + return RSI_APB_ProgramConfigData(vbg_tsbjt_efuse); +} + +/*==============================================*/ +/** + * @fn uint32_t RSI_IPMU_Auxadcoff_DiffEfuse(void) + * @brief This API is used to program The offset value for AUX ADC differential mode . + * @return RSI_APB_ProgramConfigData on success. + */ + +uint32_t RSI_IPMU_Auxadcoff_DiffEfuse(void) +{ + return RSI_APB_ProgramConfigData(auxadc_off_diff_efuse); +} + +/*==============================================*/ +/** + * @fn uint32_t RSI_IPMU_Auxadcgain_DiffEfuse(void) + * @brief This API is used to program The gain value for AUX ADC differential mode . + * @return RSI_APB_ProgramConfigData on success. + */ +uint32_t RSI_IPMU_Auxadcgain_DiffEfuse(void) +{ + return RSI_APB_ProgramConfigData(auxadc_gain_diff_efuse); +} + +/*==============================================*/ +/** + * @fn uint32_t RSI_IPMU_Auxadcoff_SeEfuse(void) + * @brief This API is used to program The offset value for AUX ADC single ended mode . + * @return RSI_APB_ProgramConfigData on success. + */ + +uint32_t RSI_IPMU_Auxadcoff_SeEfuse(void) +{ + return RSI_APB_ProgramConfigData(auxadc_off_se_efuse); + ; +} + +/*==============================================*/ +/** + * @fn uint32_t RSI_IPMU_Auxadcgain_SeEfuse(void) + * @brief This API is used to program The gain value for AUX ADC single mode . + * @return RSI_APB_ProgramConfigData on success. + */ + +uint32_t RSI_IPMU_Auxadcgain_SeEfuse(void) +{ + return RSI_APB_ProgramConfigData(auxadc_gain_se_efuse); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_Bg_TrimEfuse(void) + * @brief This API is used to program BG trim value. + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_Bg_TrimEfuse(void) +{ + return RSI_IPMU_ProgramConfigData(bg_trim_efuse); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_Blackout_TrimEfuse(void) + * @brief This API is used to program BLACKOUT thresholds . + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_Blackout_TrimEfuse(void) +{ + return RSI_IPMU_ProgramConfigData(blackout_trim_efuse); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_POCbias_Efuse(void) + * @brief This API is used to program the poc bias. + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_POCbias_Efuse(void) +{ + return RSI_IPMU_ProgramConfigData(poc_bias_efuse); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_Buck_TrimEfuse(void) + * @brief This API is used to program BUCK value . + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_Buck_TrimEfuse(void) +{ + return RSI_IPMU_ProgramConfigData(buck_trim_efuse); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_Ldosoc_TrimEfuse(void) + * @brief This API is used to program LDO SOC value . + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_Ldosoc_TrimEfuse(void) +{ + return RSI_IPMU_ProgramConfigData(ldosoc_trim_efuse); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_Dpwmfreq_TrimEfuse(void) + * @brief This API is used to program DPWM frequency value . + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_Dpwmfreq_TrimEfuse(void) +{ + return RSI_IPMU_ProgramConfigData(dpwm_freq_trim_efuse); +} + +/*==============================================*/ +/** + * @fn uint32_t RSI_IPMU_Delvbe_Tsbjt_Efuse(void) + * @brief This API is used to program the offset voltage + * @return RSI_APB_ProgramConfigData on success. + */ + +uint32_t RSI_IPMU_Delvbe_Tsbjt_Efuse(void) +{ + return RSI_APB_ProgramConfigData(delvbe_tsbjt_efuse); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_Xtal1bias_Efuse(void) + * @brief This API is used to program Xtal bias value . + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_Xtal1bias_Efuse(void) +{ + return RSI_IPMU_ProgramConfigData(xtal1_bias_efuse); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_Xtal2bias_Efuse(void) + * @brief This API is used to program Xtal2 bias value . + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_Xtal2bias_Efuse(void) +{ + return RSI_IPMU_ProgramConfigData(xtal2_bias_efuse); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_RetnHP_Volttrim_Efuse(void) + * @brief This API is used to program the HP retention voltage . + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_RetnHP_Volttrim_Efuse(void) +{ + return RSI_IPMU_ProgramConfigData(retnHP_volt_trim_efuse); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_BOD_ClksCommonconfig1(void) + * @brief This API is used to enable bias currents to BOD. + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_BOD_ClksCommonconfig1(void) +{ + return RSI_IPMU_ProgramConfigData(ipmu_bod_clks_common_config1); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_BOD_ClksCommonconfig2(void) + * @brief This API is used to disable bias currents to BOD. + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_BOD_ClksCommonconfig2(void) +{ + return RSI_IPMU_ProgramConfigData(ipmu_bod_clks_common_config2); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_Hpldo_volt_trim_efuse(void) + * @brief This API is used to set the LDO to the correct voltage based on E-Fuse. + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_Hpldo_volt_trim_efuse(void) +{ + return RSI_IPMU_ProgramConfigData(hpldo_volt_trim_efuse); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_Scdc_volt_trim_efuse(void)) + * @brief This API is used to set the SC-DCDC to the corrrect voltage based on E-Fuse. + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_Scdc_volt_trim_efuse(void) +{ + return RSI_IPMU_ProgramConfigData(scdc_volt_trim_efuse); +} + +/*==============================================*/ +/** + * @fn void RSI_IPMU_Reconfig_to_SCDCDC(void) + * @brief This API is used to the LDO has to be re-configured into SC-DCDC mode. + * @return none + */ + +void RSI_IPMU_Reconfig_to_SCDCDC(void) +{ + RSI_IPMU_ProgramConfigData(scdc_volt_sel1); + RSI_IPMU_ProgramConfigData(scdc_volt_trim_efuse); + RSI_IPMU_ProgramConfigData(scdc_volt_sel2); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_Lp_scdc_extcapmode(void) + * @brief This API is used to SCDC into the external CAP mode. + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_Lp_scdc_extcapmode(void) +{ + return RSI_IPMU_ProgramConfigData(lp_scdc_extcapmode); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_BOD_Cmphyst(void) + * @brief This API is used to set the comparator hysteresis. + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_BOD_Cmphyst(void) +{ + return RSI_IPMU_ProgramConfigData(bod_cmp_hyst); +} + +/*==============================================*/ +/** + * @fn void RSI_IPMU_32KHzROClkClib(void) + * @brief This API is used to calibrate the 32Khz RO clock to 32khz frequency . + * @return none + */ + +void RSI_IPMU_32KHzROClkClib(void) +{ + uint32_t ro32k_trim = 0, no_of_tst_clk_khz_ro = 0; + + /*Do until clock should be 32KHz */ + do { + /* CLK40M buffer circuit will be ON */ + ULP_SPI_MEM_MAP(ULPCLKS_REFCLK_REG_ADDR) |= BIT(21); + /* Off controls for clock cleaner are taken from NPSS */ + ULP_SPI_MEM_MAP(ULPCLKS_REFCLK_REG_ADDR) &= ~BIT(16); + /* RO 32KHz clock enable */ + ULP_SPI_MEM_MAP(ULPCLKS_32KRO_CLK_REG_OFFSET) |= BIT(21); + /* calibrated trim goes to the block */ + ULP_SPI_MEM_MAP(ULPCLKS_32KRO_CLK_REG_OFFSET) &= ~(BIT(15)); + /* Enable the clock gate for npss ref clk &wait for 1us*/ + /* 32KHz RO clock calibration */ + /* Binary search calibration enable signal for low frequency clocks RO and RC */ + ULP_SPI_MEM_MAP(ULPCLKS_CALIB_REG_ADDR) |= (BIT(4) | BIT(15) | BIT(21)); + /* wait till bit 21 becomes 1 Indicates calibration done indication*/ + while (!(ULP_SPI_MEM_MAP(ULPCLKS_CALIB_DONE_REG_ADDR) & BIT(21))) + ; + /* Read calibrated trim value after low frequency calibration done */ + ro32k_trim = ((ULP_SPI_MEM_MAP(ULPCLKS_CALIB_DONE_REG_ADDR) & RO_TRIM_VALUE_LF) >> 4); + /*Mask the bits where the trim value need to write */ + ULP_SPI_MEM_MAP(ULPCLKS_32KRO_CLK_REG_OFFSET) &= (uint32_t)(~(MASK32KRO_TRIM_VALUE_WRITE_BITS)); + ; + /* Programming the calibrated trim to SPI register. */ + ULP_SPI_MEM_MAP(ULPCLKS_32KRO_CLK_REG_OFFSET) |= (ro32k_trim << 16); + /* trim given from spi goes to the block */ + ULP_SPI_MEM_MAP(ULPCLKS_32KRO_CLK_REG_OFFSET) |= (BIT(15)); + /* Measures MHz RC clock Clock Frequency */ + no_of_tst_clk_khz_ro = RSI_Clks_Calibration(sleep_clk, khz_ro_clk); + no_of_tst_clk_khz_ro /= 1000; + /* Check if it is less than a particular value */ + if (no_of_tst_clk_khz_ro < PARTICULAR_FREQ_MIN) { + ULP_SPI_MEM_MAP(iPMU_SPARE_REG1_OFFSET) |= (BIT(18) | BIT(19)); + } + /* Check if it is greater than a particular value */ + if (no_of_tst_clk_khz_ro > PARTICULAR_FREQ_MAX) { + ULP_SPI_MEM_MAP(iPMU_SPARE_REG1_OFFSET) &= ~((BIT(18) | BIT(19))); + } + } while ((no_of_tst_clk_khz_ro < PARTICULAR_FREQ_MIN) || (no_of_tst_clk_khz_ro > PARTICULAR_FREQ_MAX)); + + return; +} + +/*==============================================*/ +/** + * @fn void RSI_IPMU_32KHzRCClkClib(void) + * @brief This API is used to calibrate the 32Khz RC clock to 32khz frequency. + * @return none + */ + +void RSI_IPMU_32KHzRCClkClib(void) +{ + uint32_t rc32k_trim = 0, no_of_tst_clk_khz_rc = 0; + + /*Do until clock should be 32KHz */ + do { + /* CLK40M buffer circuit will be ON */ + ULP_SPI_MEM_MAP(ULPCLKS_REFCLK_REG_ADDR) |= BIT(21); + /* Off controls for clock cleaner are taken from NPSS */ + ULP_SPI_MEM_MAP(ULPCLKS_REFCLK_REG_ADDR) &= ~(BIT(16)); + /* RC 32KHz clock enable */ + ULP_SPI_MEM_MAP(ULPCLKS_32KRC_CLK_REG_OFFSET) |= BIT(21); + /* calibrated trim goes to the block (changes spi_trim select to 0) */ + ULP_SPI_MEM_MAP(ULPCLKS_32KRC_CLK_REG_OFFSET) &= ~(BIT(11)); + /* Enable the clock gate for npss ref clk &wait for 1us*/ + /* 32KHz RC clock calibration */ + /* Binary search calibration enable signal for low frequency clocks RO and RC */ + ULP_SPI_MEM_MAP(ULPCLKS_CALIB_REG_ADDR) |= (BIT(4) | BIT(14) | BIT(21)); + /* wait till bit 21 becomes 1 Indicates calibration done indication*/ + while (!(ULP_SPI_MEM_MAP(ULPCLKS_CALIB_DONE_REG_ADDR) & BIT(21))) + ; + /* Read calibrated trim value after low frequency calibration done */ + rc32k_trim = ((ULP_SPI_MEM_MAP(ULPCLKS_CALIB_DONE_REG_ADDR) & RC_TRIM_VALUE_LF) >> 4); + /*Mask the bits where the trim value need to write */ + ULP_SPI_MEM_MAP(ULPCLKS_32KRC_CLK_REG_OFFSET) &= (uint32_t)(~(MASK32KRC_TRIM_VALUE_WRITE_BITS)); + ; + /* Programming the calibrated trim to SPI register. */ + ULP_SPI_MEM_MAP(ULPCLKS_32KRC_CLK_REG_OFFSET) |= (rc32k_trim << 14); + /*pointing the trim select to SPI */ + ULP_SPI_MEM_MAP(ULPCLKS_32KRC_CLK_REG_OFFSET) |= (BIT(11)); + /* Measures MHz RC clock Clock Frequency */ + no_of_tst_clk_khz_rc = RSI_Clks_Calibration(sleep_clk, khz_rc_clk); + no_of_tst_clk_khz_rc /= 1000; + /* Check if it is less than a particular value */ + if (no_of_tst_clk_khz_rc < PARTICULAR_FREQ_MIN) { + ULP_SPI_MEM_MAP(ULPCLKS_32KRC_CLK_REG_OFFSET) |= (BIT(12) | BIT(13)); + } + /* Check if it is greater than a particular value */ + if (no_of_tst_clk_khz_rc > PARTICULAR_FREQ_MAX) { + ULP_SPI_MEM_MAP(ULPCLKS_32KRC_CLK_REG_OFFSET) &= ~((BIT(12) | BIT(13))); + } + } while ((no_of_tst_clk_khz_rc < PARTICULAR_FREQ_MIN) || (no_of_tst_clk_khz_rc > PARTICULAR_FREQ_MAX)); + + return; +} + +/*==============================================*/ +/** + * @fn uint32_t RSI_Clks_Trim32MHzRC(uint32_t freq) + * @brief This API is used to trim 32MHz RC clock to required frequency + * @param[in] freq : Input is to get required frequency from 13MHz to 32MHz. + * @return trim value for required MHz RC frequency which we can reserve for further usage . + */ + +uint32_t RSI_Clks_Trim32MHzRC(uint32_t freq) +{ + volatile uint32_t no_oftst_clk_f = 0, no_oftst_clk = 0, i = 0, reg_read = 0, trim_value = 0; + + system_clocks.rc_32mhz_clock = (freq); + + if (system_clocks.m4_ref_clock_source == ULP_32MHZ_RC_CLK) { + system_clocks.m4ss_ref_clk = (freq); + } + if (system_clocks.ulp_ref_clock_source == ULPSS_ULP_32MHZ_RC_CLK) { + system_clocks.ulpss_ref_clk = (freq); + } + + /*Multiple the input frequency value with 10 e.g:20MHz as 200 */ + freq *= 10; + + /* Measures MHz RC clock Clock Frequency */ + no_oftst_clk = RSI_Clks_Calibration(ulp_ref_clk, none); + no_oftst_clk = no_oftst_clk_f / 100000; + /* Trims MHz RC clock to required frequency */ + if (!(no_oftst_clk == (freq))) { + reg_read = ULP_SPI_MEM_MAP(ULPCLKS_32MRC_CLK_REG_OFFSET); + /* Clears Trim bits(14-20) for RC 32MHz clock */ + reg_read &= (uint32_t)(~(0x7F << TRIM_LSB_32MHZ)); + ULP_SPI_MEM_MAP(ULPCLKS_32MRC_CLK_REG_OFFSET) = (reg_read); + /* check's from 20 bit to 14 bit */ + for (i = TRIM_MSB_32MHZ; i >= TRIM_LSB_32MHZ; i--) { + /* Measures MHz RC clock Clock Frequency */ + no_oftst_clk_f = RSI_Clks_Calibration(ulp_ref_clk, none); + /*To get in three digit of Measured frequency value in MHz e.g:20MHz as 200 */ + no_oftst_clk = no_oftst_clk_f / 100000; + /* Halt the process for less than 0.3MHZ even */ + if ((freq) - (no_oftst_clk) < MIN_DIFF_FREQ) { + break; + } + /*Check whether the acquired frequency is higher than required frequency + If higher then clear the previous bit and set the present bit */ + if (no_oftst_clk >= (freq)) { + ULP_SPI_MEM_MAP(ULPCLKS_32MRC_CLK_REG_OFFSET) &= ~(BIT(i + 1)); + ULP_SPI_MEM_MAP(ULPCLKS_32MRC_CLK_REG_OFFSET) |= BIT(i); + } + /* If lesser set the present bit */ + else { + ULP_SPI_MEM_MAP(ULPCLKS_32MRC_CLK_REG_OFFSET) |= BIT(i); + } + } + } + /* Trim bits(14-20) value for RC 32MHz clock */ + trim_value = ULP_SPI_MEM_MAP(ULPCLKS_32MRC_CLK_REG_OFFSET); + trim_value &= (0x7F << TRIM_LSB_32MHZ); + trim_value = trim_value >> TRIM_LSB_32MHZ; + + return trim_value; +} + +/*==============================================*/ +/** + * @fn void RSI_IPMU_20M_ROClktrim(uint8_t clkfreq) + * @brief This API is used to trim the 20Mhz RO clock to required frequency. + * @param[in] clkfreq : Input is to get required frequency from 1MHz to 50MHz. + * @return none + */ + +void RSI_IPMU_20M_ROClktrim(uint8_t clkfreq) +{ + volatile uint32_t ro50m_trim = 0; + system_clocks.doubler_clock = (clkfreq * 1000000 * 2); + + system_clocks.ro_20mhz_clock = (clkfreq * 1000000); + + if (system_clocks.m4_ref_clock_source == ULP_20MHZ_RINGOSC_CLK) { + system_clocks.m4ss_ref_clk = (clkfreq * 1000000); + } + if (system_clocks.ulp_ref_clock_source == ULPSS_ULP_20MHZ_RINGOSC_CLK) { + system_clocks.ulpss_ref_clk = (clkfreq * 1000000); + } + /* CLK40M buffer circuit will be ON */ + ULP_SPI_MEM_MAP(ULPCLKS_REFCLK_REG_ADDR) |= BIT(21); + /* Off controls for clock cleaner are taken from NPSS */ + ULP_SPI_MEM_MAP(ULPCLKS_REFCLK_REG_ADDR) &= ~BIT(16); + + if (clkfreq > 10) { + /* select input to High frequency RO */ + ULP_SPI_MEM_MAP(ULPCLKS_HF_RO_CLK_REG_OFFSET) |= BIT(13); + } else { + /*select input to Low frequency RO */ + ULP_SPI_MEM_MAP(ULPCLKS_HF_RO_CLK_REG_OFFSET) &= ~BIT(13); + } + /* Enable the 50MHZ RO clock */ + ULP_SPI_MEM_MAP(ULPCLKS_HF_RO_CLK_REG_OFFSET) |= BIT(21) | BIT(12); + /* powergate enable for calibration domain */ + ULP_SPI_MEM_MAP(ULPCLKS_TRIM_SEL_REG_ADDR) = ENABLE_CALIB_DOMAIN; + /* Mask the bits to write required frequency for High frequency RO clock */ + ULP_SPI_MEM_MAP(ULPCLKS_TRIM_SEL_REG_ADDR) &= (uint32_t)(~(0x3F)); + /*It writes that at what frequency the ROMhz need to be trim */ + ULP_SPI_MEM_MAP(ULPCLKS_TRIM_SEL_REG_ADDR) |= clkfreq; + /* Select the RO50M clock to calibrate */ + ULP_SPI_MEM_MAP(ULPCLKS_CALIB_REG_ADDR) = SELECT_RO_CALIB; + /* Waiting for calibration done indication */ + while (!(ULP_SPI_MEM_MAP(ULPCLKS_CALIB_DONE_REG_ADDR) & BIT(20))) + ; + /* Reading calibrated trim value */ + ro50m_trim = ((ULP_SPI_MEM_MAP(ULPCLKS_CALIB_DONE_REG_ADDR) & TRIM_VALUE_BITS) >> 11); + // ro50m_trim = (ro50m_trim >> 11); + /*Mask the bits where the trim value need to write */ + ULP_SPI_MEM_MAP(ULPCLKS_HF_RO_CLK_REG_OFFSET) &= (uint32_t)(~(MASK_TRIM_VALUE_WRITE_BITS)); + /* Programming the calibrated trim to SPI register. */ + ULP_SPI_MEM_MAP(ULPCLKS_HF_RO_CLK_REG_OFFSET) |= (ro50m_trim << 14); + /* pointing the trim select to SPI i.e write default values to that register */ + ULP_SPI_MEM_MAP(ULPCLKS_TRIM_SEL_REG_ADDR) = ULPCLKS_TRIM_SEL_REG_DEFAULT; + /* CLK40M buffer circuit will be OFF */ + ULP_SPI_MEM_MAP(ULPCLKS_REFCLK_REG_ADDR) &= ~BIT(21); + /* ON controls for clock cleaner are taken from NPSS */ + ULP_SPI_MEM_MAP(ULPCLKS_REFCLK_REG_ADDR) |= BIT(16); + /* Disable the 50MHZ RO clock */ + ULP_SPI_MEM_MAP(ULPCLKS_HF_RO_CLK_REG_OFFSET) &= ~BIT(21); + + return; +} + +/*==============================================*/ +/** + * @fn uint32_t RSI_Clks_Calibration(INPUT_CLOCK_T inputclk, SLEEP_CLOCK_T sleep_clk_type) + * @brief This API is used for Clock Frequency measurement . + * @param[in] inputclk : Select the clock to be calibrated. + * - /ref INPUT_CLOCK_T + * @param[in] sleep_clk_type : Select the type of Khz clock(RO,RC, XTAL) if it is sleep clock. + * - /ref SLEEP_CLOCK_T + * @return Clock Frequency in Hz . + */ + +uint32_t RSI_Clks_Calibration(INPUT_CLOCK_T inputclk, SLEEP_CLOCK_T sleep_clk_type) +{ + volatile uint32_t no_oftst_clk = 0; + + if (inputclk > 10) { + return INVALID_PARAMETERS; + } + + if (inputclk == sleep_clk) { + if (sleep_clk_type == khz_rc_clk) { + M4CLK->CLK_CONFIG_REG4_b.SLEEP_CLK_SEL = khz_rc_clk; + } + if (sleep_clk_type == khz_ro_clk) { + M4CLK->CLK_CONFIG_REG4_b.SLEEP_CLK_SEL = khz_ro_clk; + } + if (sleep_clk_type == khz_xtal_clk) { + M4CLK->CLK_CONFIG_REG4_b.SLEEP_CLK_SEL = khz_xtal_clk; + } + } + /*Change test clock */ + // M4CLK->CLK_CALIB_CTRL_REG1_b.CC_CHANGE_TEST_CLK_b = 0x1; + /* Select the clock to be calibrated*/ + M4CLK->CLK_CALIB_CTRL_REG1_b.CC_CLKIN_SEL_b = (inputclk); + /* number of ref clock cycles to be considered for calibrating */ + M4CLK->CLK_CALIB_CTRL_REG2_b.CC_NUM_REF_CLKS = 39062; + /* Reset change test clock */ + // M4CLK->CLK_CALIB_CTRL_REG1_b.CC_CHANGE_TEST_CLK_b = 0x0; + /* Start clock calibration */ + M4CLK->CLK_CALIB_CTRL_REG1_b.CC_START_b = 0x1; + /* Wait until the clock calibration done */ + while (!(M4CLK->CLK_CALIB_STS_REG1_b.CC_DONE_b)) + ; + + if ((M4CLK->CLK_CALIB_STS_REG1_b.CC_ERROR_b)) { + M4CLK->CLK_CALIB_CTRL_REG1_b.CC_SOFT_RST_b = 0x1; + } + + /*If cc_error is not set then the clock calibration is done. */ + if (!(M4CLK->CLK_CALIB_STS_REG1_b.CC_ERROR_b)) { + /* number of test clock cycles occurred for the specified number + of ref_clock cycles*/ + no_oftst_clk = M4CLK->CLK_CALIB_STS_REG2_b.CC_NUM_TEST_CLKS; + } + + return no_oftst_clk; +} + +/*==============================================*/ +/** + * @fn void RSI_IPMU_64KHZ_RCClktrim(void) + * @brief This API is used to trim the 64khz RC clock. + * @return none + */ + +void RSI_IPMU_64KHZ_RCClktrim(void) +{ + uint32_t i, status = 0; + + system_clocks.rc_32khz_clock = (64000); + + /*Enables RC clock and changes spi_trim select to 0*/ + ULP_SPI_MEM_MAP(ULPCLKS_32KRC_CLK_REG_ADDR) = ENABLE_32KHZ_CLOCK_TRIM; + + /* Enable XTAL clock from NPSS */ + *(volatile uint32_t *)0x41300120 |= BIT(22); + + /* wait for 1ms */ + for (i = 0; i < 10000; i++) { + ; + } + + /* Selects NPSS reference clock to be CLK-40M_SOC */ + ULP_SPI_MEM_MAP(ULPCLKS_REFCLK_REG_ADDR) = NPSS_REF_CLOCK_40MSOC; + + /* Select number of reference cycles to 625(No of clocks of high frequency clocks in 1 cycle of 16KHz clock Default value is 1250)*/ + ULP_SPI_MEM_MAP(ULPCLKS_CALIB_REF_REG) = NUMBER_HIGH_FRQ_CLOCK; + + /* Pointing RC32KHz clock to NPSS_TESTMODE 0 */ + *(volatile uint32_t *)0x24048610 = BIT(25) | BIT(28); + + /*Configure NPSS_GPIO_0 in mode 6 */ + *(volatile uint32_t *)0x24048610 = (0x0000000E); + + /*Enable the low frequency clock calibration,enable the clock gate for npss ref clk and select the RC32K clock to calibrate */ + ULP_SPI_MEM_MAP(ULPCLKS_CALIB_REG_ADDR) = LOW_FREQ_CLOCK_CAL; + + /* wait for 1us */ + for (i = 0; i < 100; i++) { + ; + } + + /* wait till bit 21 becomes 1 Indicates calibration done indication*/ + while (!(ULP_SPI_MEM_MAP(0x30C) & BIT(21))) + ; + + /* Calibrated trim value and write the calibrated trim into EFUSE */ + status = (ULP_SPI_MEM_MAP(0x30C) >> 4) & (0x7F); + status = ((status << 14) | BIT(11)); + ULP_SPI_MEM_MAP(ULPCLKS_32KRC_CLK_REG_ADDR) |= status; + + /*Restore the original value of reference cycles once calibration is done */ + ULP_SPI_MEM_MAP(ULPCLKS_CALIB_REF_REG) = ORIGINAL_REF_VALUE_AFTER_CAL; +} diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_pll.c b/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_pll.c new file mode 100644 index 000000000..d60af0016 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_pll.c @@ -0,0 +1,3415 @@ +/******************************************************************************* +* @file rsi_pll.c +* @brief +******************************************************************************* +* # License +* Copyright 2020 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ +/************************************************************************* + * + */ + +// Includes + +#include "rsi_ccp_user_config.h" +#include +#include "rsi_rom_clks.h" +#ifndef PLL_ROMDRIVER_PRESENT +/** @addtogroup SOC3 +* @{ +*/ +/*==============================================*/ +/** + * @fn boolean_t clk_check_pll_lock(PLL_TYPE_T pllType) + * @brief This API is used to check the lock status of pll + * @param[in] pllType : PLL type + * @return Enable on success + * Disable on failure + */ + +boolean_t clk_check_pll_lock(PLL_TYPE_T pllType) +{ + uint16_t lock = 0; + + if (pllType == SOC_PLL) { + lock = SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG13) >> 14; + if (lock & 1) { + return Enable; + } else { + return Disable; + } + } else if (pllType == INFT_PLL) { + lock = SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG13) >> 14; + if (lock & 1) { + return Enable; + } else { + return Disable; + } + } else { + lock = SPI_MEM_MAP_PLL(I2S_PLL_CTRL_REG13) >> 14; + if (lock & 1) { + return Enable; + } else { + return Disable; + } + } +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_soc_pll_clk_enable(boolean_t clkEnable) + * @brief This API is used to enable SoC-PLL output clock + * @param[in] clkEnable : enable the clock for SoC-PLL output clock + * @return RSI_OK on success + */ + +rsi_error_t clk_soc_pll_clk_enable(boolean_t clkEnable) +{ + if (clkEnable == Enable) { + /*Enable SoC-PLL*/ + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG1) |= PLL_500_CLK_ENABLE; + } else { + /*Disable SoC-PLL*/ + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG1) &= (uint16_t)(~(PLL_500_CLK_ENABLE)); + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_set_soc_pll_freq(M4CLK_Type *pCLK, uint32_t socPllFreq, uint32_t pllRefClk) + * @brief This API is used to set the Soc PLL clock to particular frequency + * @param[in] pCLK : pointer to the processor clock source + * @param[in] socPllFreq : SoC PLL frequency for Soc PLL clock to particular frequency + * @param[in] pllRefClk : PLL reference clock for Soc PLL clock to particular frequency + * @return RSI_OK on success + */ + +rsi_error_t clk_set_soc_pll_freq(M4CLK_Type *pCLK, uint32_t socPllFreq, uint32_t pllRefClk) +{ + uint16_t shiftFac = 0; + uint16_t socPllMulFac = 0; + uint16_t dcoFreq = 0; + uint16_t reg = 0; + uint16_t socPllDivFac = 0; + uint16_t socreg1 = 0x31c9, socreg3 = 0, socPllTvRead = 0; + + /*parameter validation*/ + + if ((pCLK == NULL) || (socPllFreq < SOC_PLL_MIN_FREQUECY) || (socPllFreq > SOC_PLL_MAX_FREQUECY)) { + return INVALID_PARAMETERS; + } + socPllFreq = (socPllFreq / 1000000); + pllRefClk = (pllRefClk / 1000000); + + if ((MCU_RET->CHIP_CONFIG_MCU_READ_b.LIMIT_M4_FREQ_110MHZ_b == 1) || (M4_BBFF_STORAGE1 & BIT(10))) { + if (socPllFreq >= 201) { + /*New table*/ + /* Program PLL to 200Mhz */ + /* Call low level API with m,n,p values for 200Mhz configuration. */ + clk_soc_pll_set_freq_div(pCLK, 1, 0, 39, 199, 0, 1, 1); + return ERROR_INVALID_INPUT_FREQUENCY; + } else { + /* Derive the m,n,p values as per the newer table*/ + /* program PLL with derived values */ + /* Wait for PLL lock*/ + if (socPllFreq < 2) { + shiftFac = 7; + } else if (socPllFreq < 3) { + shiftFac = 6; + } else if (socPllFreq < 6) { + shiftFac = 5; + } else if (socPllFreq < 12) { + shiftFac = 4; + } else if (socPllFreq < 23) { + shiftFac = 3; + } else if (socPllFreq < 46) { + shiftFac = 2; + } else if (socPllFreq < 91) { + shiftFac = 1; + } else { + shiftFac = 0; + } + + socPllDivFac = (uint16_t)((1 << shiftFac) - 1); + + socPllMulFac = (uint16_t)(((socPllDivFac + 1) * socPllFreq) - 1); + + /*RESET PLL*/ + clk_soc_pll_clk_reset(); + + reg = SPI_MEM_MAP_PLL(SOCPLLMACROREG3); + reg = reg << 1; /* according to RTL bug SOCPLLMACROREG3 (read issue) will shift to one left shift */ + reg &= (uint16_t)(~(LDO_PROG_SOCPLL)); + reg |= 1 << 13; + + SPI_MEM_MAP_PLL(SOCPLLMACROREG3) = reg; + + socreg1 &= (uint16_t)(~(DCO_FIX_SEL_MASK)); + /*writing the value into the dco_fix_sel=1*/ + socreg1 |= 1; + + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG2) = (uint16_t)(((socPllDivFac) << 9) | ((pllRefClk - 1) << 3)); + socreg1 &= (uint16_t)(~(PLL_500_M_MASK)); + socreg1 |= (uint16_t)((socPllMulFac << 6) | PLL_500_CLK_ENABLE); /* m factor */ + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG1) = socreg1; + + /*Enable */ + clk_soc_pll_clk_set(pCLK); /* wait for lock */ + /* Set and clear(read modify write) PLL500CTRLREG7 BIT[4] : TV value will be latched */ + + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG7) |= SPI_INP_RD_EN; + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG7) &= (uint16_t)(~(SPI_INP_RD_EN)); + + /* Read the TV value from PLL500CTRLREG12 BIT[15 : 11]*/ + socPllTvRead = (SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG12) & 0xF800) >> 11; + + if (socPllTvRead <= (M4_BBFF_STORAGE1 & 0x001F)) { + /*New table*/ + /* Program PLL to 200Mhz */ + /* Call low level API with m,n,p values for 200Mhz configuration. */ + clk_soc_pll_set_freq_div(pCLK, 1, 0, 39, 199, 0, 1, 1); + return ERROR_INVALID_INPUT_FREQUENCY; + + } else { + /*Program the required frequency by user*/ + return RSI_OK; + } + } + } else { + /*Older table*/ + if (socPllFreq < 2) { + shiftFac = 7; + } else if (socPllFreq < 4) { + shiftFac = 6; + } else if (socPllFreq < 8) { + shiftFac = 5; + } else if (socPllFreq < 16) { + shiftFac = 4; + } else if (socPllFreq < 32) { + shiftFac = 3; + } else if (socPllFreq < 64) { + shiftFac = 2; + } else if (socPllFreq < 127) { + shiftFac = 1; + } else { + shiftFac = 0; + } + dcoFreq = (uint16_t)(socPllFreq << shiftFac); + socPllMulFac = (uint16_t)((socPllFreq << shiftFac) - 1); + socPllDivFac = (uint16_t)((1 << shiftFac) - 1); + + /*RESET PLL*/ + clk_soc_pll_clk_reset(); + + if (socPllFreq >= 201) { + if ((socPllFreq % 2) == 0) { + socreg3 &= (uint16_t)(~(FCW_F_MASK)); + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG3) = socreg3; + } else { + socreg3 |= (8192 << 2); + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG3) = socreg3; + } + } + if (dcoFreq >= 251) { + /*clearing the two bits i.e dco_fix_sel*/ + socreg1 &= (uint16_t)(~(DCO_FIX_SEL_MASK)); + /*writing the value into the dco_fix_sel=2*/ + socreg1 |= 2; + reg = SPI_MEM_MAP_PLL(SOCPLLMACROREG3); + reg = reg << 1; /* according to RTL bug SOCPLLMACROREG3 (read issue) will shift to one left shift*/ + reg &= (uint16_t)(~(LDO_PROG_SOCPLL)); + reg |= 5 << 13; + SPI_MEM_MAP_PLL(SOCPLLMACROREG3) = reg; + socPllMulFac = ((dcoFreq / 2) - 1); + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG2) = (uint16_t)(((socPllDivFac) << 9) | ((pllRefClk - 1) << 3)); + socreg1 &= (uint16_t)(~(PLL_500_M_MASK)); + socreg1 |= (uint16_t)((socPllMulFac << 6) | PLL_500_CLK_ENABLE); /* m factor */ + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG1) = socreg1; + } else if ((dcoFreq >= 201) && (dcoFreq <= 250)) { + socreg1 &= (uint16_t)(~(DCO_FIX_SEL_MASK)); + reg = SPI_MEM_MAP_PLL(SOCPLLMACROREG3); + reg = reg << 1; /* according to RTL bug SOCPLLMACROREG3 (read issue) will shift to one left shift*/ + reg &= (uint16_t)(~(LDO_PROG_SOCPLL)); + reg |= 5 << 13; + SPI_MEM_MAP_PLL(SOCPLLMACROREG3) = reg; + socPllMulFac = ((dcoFreq / 2) - 1); + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG2) = (uint16_t)(((socPllDivFac) << 9) | ((pllRefClk - 1) << 3)); + socreg1 &= (uint16_t)(~(PLL_500_M_MASK)); + socreg1 |= (uint16_t)((socPllMulFac << 6) | PLL_500_CLK_ENABLE); /* m factor */ + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG1) = socreg1; + } else { + socreg3 &= (uint16_t)(~(FCW_F_MASK)); + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG3) = socreg3; + socreg1 &= (uint16_t)(~(DCO_FIX_SEL_MASK)); + socreg1 |= 1; + reg = SPI_MEM_MAP_PLL(SOCPLLMACROREG3); + reg = reg << 1; /* according to RTL bug SOCPLLMACROREG3 (read issue) will shift to one left shift*/ + reg &= (uint16_t)(~(LDO_PROG_SOCPLL)); + reg |= 4 << 13; + SPI_MEM_MAP_PLL(SOCPLLMACROREG3) = reg; + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG2) = (uint16_t)(((socPllDivFac) << 9) | ((pllRefClk - 1) << 3)); + socreg1 &= (uint16_t)(~(PLL_500_M_MASK)); + socreg1 |= (uint16_t)((socPllMulFac << 6) | PLL_500_CLK_ENABLE); // m factor + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG1) = socreg1; + } + /*Enable */ + clk_soc_pll_clk_set(pCLK); + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_soc_pll_set_freq_div(M4CLK_Type *pCLK, + * boolean_t clk_en, + * uint16_t divFactor, + * uint16_t nFactor, + * uint16_t mFactor, + * uint16_t fcwF, + * uint16_t dcoFixSel, + * uint16_t ldoProg) + * @brief This API is used to configure the SOC PLL clock frequency + * @param[in] pCLK : pointer to the processor clock source + * @param[in] clk_en : enable the clock for SOC PLL clock frequency + * @param[in] divFactor : division factor for SOC PLL clock frequency + * @param[in] nFactor : n number of factor for SOC PLL clock frequency + * @param[in] mFactor : m number of factor for SOC PLL clock frequency + * @param[in] fcwF : frequency for SOC PLL clock frequency + * @param[in] dcoFixSel : fixed select for SOC PLL clock frequency + * @param[in] ldoProg : ldo program for SOC PLL clock frequency + * @return RSI_OK on success + */ + +rsi_error_t clk_soc_pll_set_freq_div(M4CLK_Type *pCLK, + boolean_t clk_en, + uint16_t divFactor, + uint16_t nFactor, + uint16_t mFactor, + uint16_t fcwF, + uint16_t dcoFixSel, + uint16_t ldoProg) +{ + uint16_t socreg1 = 0x31c9, socreg3 = 0, reg = 0, socPllTvRead = 0; + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + /*RESET PLL*/ + clk_soc_pll_clk_reset(); + if ((MCU_RET->CHIP_CONFIG_MCU_READ_b.LIMIT_M4_FREQ_110MHZ_b == 1) || (M4_BBFF_STORAGE1 & BIT(10))) { + if (clk_en) { + socreg3 &= (uint16_t)(~(FCW_F_MASK)); + socreg3 = fcwF << 2; + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG3) = socreg3; + socreg1 &= (uint16_t)(~(DCO_FIX_SEL_MASK)); + socreg1 |= 1; + reg = SPI_MEM_MAP_PLL(SOCPLLMACROREG3); + reg = reg << 1; /* according to RTL bug SOCPLLMACROREG3 (read issue) will shift to one left shift*/ + reg &= (uint16_t)(~(LDO_PROG_SOCPLL)); + reg |= 1 << 13; + SPI_MEM_MAP_PLL(SOCPLLMACROREG3) = reg; + socreg1 |= PLL_500_CLK_ENABLE; + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG2) = (uint16_t)(((divFactor) << 9) | (nFactor << 3)); + socreg1 &= (uint16_t)(~(PLL_500_M_MASK)); + socreg1 |= (uint16_t)(((mFactor << 6) | PLL_500_CLK_ENABLE)); + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG1) = socreg1; + } else { + socreg1 &= (uint16_t)(~PLL_500_CLK_ENABLE); /*soc_pll_clk o/p disable */ + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG1) = socreg1; + } + + /*wait for lock */ + clk_soc_pll_clk_set(pCLK); + /* Set and clear(read modify write) PLL500CTRLREG7 BIT[4] : TV value will be latched */ + + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG7) |= SPI_INP_RD_EN; + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG7) &= (uint16_t)(~(SPI_INP_RD_EN)); + + /* Read the TV value from PLL500CTRLREG12 BIT[15 : 11]*/ + socPllTvRead = (SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG12) & 0xF800) >> 11; + + if ((socPllTvRead <= (M4_BBFF_STORAGE1 & 0x001F)) && (divFactor == 0)) { + /*RESET PLL*/ + clk_soc_pll_clk_reset(); + return ERROR_INVALID_INPUT_FREQUENCY; + } else { + /*Program the required frequency by user*/ + return RSI_OK; + } + } else { + if (clk_en) { + socreg3 &= (uint16_t)(~(FCW_F_MASK)); + socreg3 = fcwF << 2; + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG3) = socreg3; + socreg1 &= (uint16_t)(~(DCO_FIX_SEL_MASK)); + socreg1 |= dcoFixSel; + reg = SPI_MEM_MAP_PLL(SOCPLLMACROREG3); + reg = reg << 1; // according to RTL bug SOCPLLMACROREG3 (read issue) will shift to one left shift + reg &= (uint16_t)(~(LDO_PROG_SOCPLL)); + reg |= (uint16_t)(ldoProg << 13); + SPI_MEM_MAP_PLL(SOCPLLMACROREG3) = reg; + socreg1 |= PLL_500_CLK_ENABLE; + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG2) = (uint16_t)(((divFactor) << 9) | (nFactor << 3)); + socreg1 &= (uint16_t)(~(PLL_500_M_MASK)); + socreg1 |= (uint16_t)((mFactor << 6) | PLL_500_CLK_ENABLE); + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG1) = socreg1; + } else { + socreg1 &= (uint16_t)(~PLL_500_CLK_ENABLE); // soc_pll_clk o/p disable + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG1) = socreg1; + } + + /*Enable */ + clk_soc_pll_clk_set(pCLK); + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_soc_pll_clk_set(M4CLK_Type *pCLK) + * @brief This API is used to Enables the SoC-PLL + * @param[in] pCLK : pointer to the processor clock source + * @return RSI_OK on success + */ + +rsi_error_t clk_soc_pll_clk_set(M4CLK_Type *pCLK) +{ + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG11) = 0xFFFF; + /*Wait for lock*/ + while ((pCLK->PLL_STAT_REG_b.SOCPLL_LOCK) != 1) + ; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_soc_pll_clk_bypass_enable(boolean_t clkEnable) + * @brief This API is used to Enable bypass clock + * @param[in] clkEnable : enable the clock + * @return RSI_OK on success + */ + +rsi_error_t clk_soc_pll_clk_bypass_enable(boolean_t clkEnable) +{ + if (clkEnable == Enable) { + /*Enable PLL clock*/ + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG1) |= PLL_500_BYPASS; + } else { + /*Disable PLL clock*/ + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG1) &= (uint16_t)(~(PLL_500_BYPASS)); + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_soc_pll_clk_reset(void) + * @brief This API is used to Reset the Soc_pll_clk + * @return RSI_OK on success + */ + +rsi_error_t clk_soc_pll_clk_reset(void) +{ + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG11) = 0x01FF; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_soc_pll_pd_enable(boolean_t en) + * @brief This API is used to Enable the PdEnable(power down) + * @param[in] en : enable + * @return RSI_OK on success + */ + +rsi_error_t clk_soc_pll_pd_enable(boolean_t en) +{ + if (en == Enable) { + /*Enable power down*/ + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG1) |= PLL_500_PD; + } else { + /*Disable power down*/ + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG1) &= (uint16_t)(~(PLL_500_PD)); + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_soc_pll_turn_off(void) + * @brief This API is used to TurnOff the SOC_PLL + * @return RSI_OK on success + */ + +rsi_error_t clk_soc_pll_turn_off(void) +{ + uint16_t socreg1 = 0x31c9; + /*Set PLL PD Bit*/ + socreg1 |= PLL_500_PD; + socreg1 |= PLL_500_RST; + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG1) = socreg1; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_soc_pll_turn_on(void) + * @brief This API is used to TurnOn the SOC_PLL + * @return RSI_OK on success + */ + +rsi_error_t clk_soc_pll_turn_on(void) +{ + uint16_t socreg1 = 0x31c9; + /*Disable power down */ + socreg1 &= (uint16_t)(~(PLL_500_RST)); + socreg1 &= (uint16_t)(~(PLL_500_PD)); + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG1) = socreg1; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_i2s_pll_clk_enable(boolean_t clkEnable) + * @brief This API is used to Enable the I2s_PLL output clock + * @param[in] clkEnable : enable the clock for I2s_PLL output clock + * @return RSI_OK on success + */ + +rsi_error_t clk_i2s_pll_clk_enable(boolean_t clkEnable) +{ + if (clkEnable == Enable) { + /*Enable SoC-PLL*/ + SPI_MEM_MAP_PLL(I2S_PLL_CTRL_REG1) |= PLL_500_CLK_ENABLE; + } else { + /*Disable SoC-PLL*/ + SPI_MEM_MAP_PLL(I2S_PLL_CTRL_REG1) &= (uint16_t)(~(PLL_500_CLK_ENABLE)); + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_i2s_pll_clk_bypass_enable(boolean_t clkEnable) + * @brief This API is used to Enable bypass clock + * @param[in] clkEnable : enable the clock for bypass clock + * @return RSI_OK on success + */ + +rsi_error_t clk_i2s_pll_clk_bypass_enable(boolean_t clkEnable) +{ + if (clkEnable == Enable) { + /*Enable PLL clock*/ + SPI_MEM_MAP_PLL(I2S_PLL_CTRL_REG1) |= PLL_500_BYPASS; + } else { + /*Disable PLL clock*/ + SPI_MEM_MAP_PLL(I2S_PLL_CTRL_REG1) &= (uint16_t)(~(PLL_500_BYPASS)); + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_i2s_pll_pd_enable(boolean_t en) + * @brief This API is used to Enable the PdEnable(power down) + * @param[in] en : enable + * @return RSI_OK on success + */ + +rsi_error_t clk_i2s_pll_pd_enable(boolean_t en) +{ + if (en == Enable) { + /*Enable power down*/ + SPI_MEM_MAP_PLL(I2S_PLL_CTRL_REG1) |= PLL_500_PD; + } else { + /*Disable power down*/ + SPI_MEM_MAP_PLL(I2S_PLL_CTRL_REG1) &= (uint16_t)(~(PLL_500_PD)); + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_i2s_pll_turn_off(void) + * @brief This API is used to TurnOff the I2s_PLL + * @return RSI_OK on success + */ + +rsi_error_t clk_i2s_pll_turn_off(void) +{ + uint16_t i2sreg1 = 0x1244; + /*Set PLL PD Bit*/ + i2sreg1 |= PLL_500_PD; + i2sreg1 |= PLL_500_RST; + SPI_MEM_MAP_PLL(I2S_PLL_CTRL_REG1) |= i2sreg1; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_i2s_pll_turn_on(void) + * @brief This API is used to TurnOn the I2s_PLL + * @return RSI_OK on success + */ + +rsi_error_t clk_i2s_pll_turn_on(void) +{ + uint16_t i2sreg1 = 0x1244; + i2sreg1 &= (uint16_t)(~(PLL_500_PD)); + i2sreg1 &= (uint16_t)(~(PLL_500_RST)); + SPI_MEM_MAP_PLL(I2S_PLL_CTRL_REG1) = i2sreg1; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_set_i2s_pll_freq(M4CLK_Type *pCLK, uint32_t i2sPllFreq, uint32_t fXtal) + * @brief This API is used to set the I2s_pll clock to particular frequency + * @param[in] pCLK : pointer to the processor clock source + * @param[in] i2sPllFreq : PLL clock of I2S for particular frequency + * @param[in] fXtal : frequency oscillator for particular frequency + * @return RSI_OK on success + */ + +rsi_error_t clk_set_i2s_pll_freq(M4CLK_Type *pCLK, uint32_t i2sPllFreq, uint32_t fXtal) +{ + uint16_t p_div = 0, u16DivFactor1 = 0, u16DivFactor2 = 0, N = 0, M = 0, FCW_F = 0; + uint32_t fref = 0, Fdco; + float g; + double FCW, frac; + uint16_t i2sreg1 = 0x1244, i2sreg2 = 0x5850, i2sreg3 = 0xba60; + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + + if (!((fXtal == 9600000) || (fXtal == 19200000) || (fXtal == 38400000))) { + fref = 1000000; /* One Mega herz steps*/ + } else { + fref = 960000; /* 0.96 Mega herz steps*/ + } + /*Calculating p_div value*/ + g = ((float)I2S_DCO_FREQ1 / (float)i2sPllFreq); + if (g - (int)g == 0) /*checking the integer value or not*/ + { + p_div = (uint16_t)(g); + Fdco = I2S_DCO_FREQ1; + } else { + p_div = (uint16_t)(I2S_DCO_FREQ2 / i2sPllFreq); + Fdco = I2S_DCO_FREQ2; + } + N = (uint16_t)(fXtal / fref); /*calculating N value*/ + /*deriving M and FCW_F value*/ + FCW = (float)Fdco / (float)fref; + M = (uint16_t)FCW; + frac = (FCW - M); + FCW_F = (uint16_t)((frac)*pow(2, 14)); + if (Fdco == I2S_DCO_FREQ1) { + FCW_F = (FCW_F + 1); + } + /*deriving the p_div1 and p_div2 values from p_div value*/ + /*From the refernce of PLL Programming table*/ + if (p_div >= 288) { + u16DivFactor2 = 4; + u16DivFactor1 = ((p_div >> 4) - 1); + } else if ((p_div >= 96) && (p_div <= 144)) { + u16DivFactor2 = 3; + u16DivFactor1 = ((p_div >> 3) - 1); + } else if (p_div == 72) { + u16DivFactor2 = 2; + u16DivFactor1 = ((p_div >> 2) - 1); + } else if ((p_div >= 36) && (p_div <= 48)) { + u16DivFactor2 = 1; + u16DivFactor1 = ((p_div >> 1) - 1); + } else { + u16DivFactor2 = 0; + u16DivFactor1 = (p_div - 1); + } + /*RESET PLL*/ + clk_i2s_pll_clk_reset(); + i2sreg2 &= (uint16_t)(~(N_DIV_MASK)); + i2sreg2 |= (uint16_t)((N << 1)); + i2sreg3 &= (uint16_t)(~(FCW_F_MASK)); + i2sreg3 |= (uint16_t)(FCW_F << 2); + i2sreg1 &= (uint16_t)(~(PLL_500_M_MASK)); + i2sreg1 |= (uint16_t)(M << 6); + i2sreg2 &= (uint16_t)(~(0xff00)); + i2sreg2 |= (uint16_t)((u16DivFactor1 << 11) | (u16DivFactor2 << 8)); + i2sreg1 &= (uint16_t)(~PLL_500_PD); + i2sreg1 &= (uint16_t)(~PLL_500_RST); + i2sreg1 |= PLL_500_BYPASS; + SPI_MEM_MAP_PLL(I2S_PLL_CTRL_REG1) = i2sreg1; + SPI_MEM_MAP_PLL(I2S_PLL_CTRL_REG2) = i2sreg2; + SPI_MEM_MAP_PLL(I2S_PLL_CTRL_REG3) = i2sreg3; + clk_i2s_pll_clk_set(pCLK); + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_i2s_pll_set_freq_div(M4CLK_Type *pCLK, + * uint16_t u16DivFactor1, + * uint16_t u16DivFactor2, + * uint16_t nFactor, + * uint16_t mFactor, + * uint16_t fcwF) + * @brief This API is used to divide I2s_PLL Clock + * @param[in] pCLK : pointer to the processor clock source + * @param[in] u16DivFactor1 : division factor of 1 + * @param[in] u16DivFactor2 : division factor of 2 + * @param[in] nFactor : n number of factor for I2s_PLL Clock + * @param[in] mFactor : m number of factor for I2s_PLL Clock + * @param[in] fcwF : frequency for for I2s_PLL Clock + * @return RSI_OK on success + */ + +rsi_error_t clk_i2s_pll_set_freq_div(M4CLK_Type *pCLK, + uint16_t u16DivFactor1, + uint16_t u16DivFactor2, + uint16_t nFactor, + uint16_t mFactor, + uint16_t fcwF) +{ + uint16_t i2sreg1 = 0x1244, i2sreg2 = 0x5850, i2sreg3 = 0xba60; + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + clk_i2s_pll_clk_reset(); + if (u16DivFactor1) { + i2sreg2 &= (uint16_t)(~(N_DIV_MASK)); + i2sreg2 |= (uint16_t)(nFactor << 1); + i2sreg3 &= (uint16_t)(~(FCW_F_MASK)); + i2sreg3 |= (uint16_t)(fcwF << 2); + i2sreg1 &= (uint16_t)(~(PLL_500_M_MASK)); + i2sreg1 |= (uint16_t)(mFactor << 6); + i2sreg2 &= (uint16_t)(~(0xff00)); + i2sreg2 |= (uint16_t)((u16DivFactor1 << 11) | (u16DivFactor2 << 8)); + i2sreg1 &= (uint16_t)~PLL_500_PD; + i2sreg1 &= (uint16_t)(~PLL_500_RST); + i2sreg1 |= PLL_500_BYPASS; + SPI_MEM_MAP_PLL(I2S_PLL_CTRL_REG1) = i2sreg1; + SPI_MEM_MAP_PLL(I2S_PLL_CTRL_REG2) = i2sreg2; + SPI_MEM_MAP_PLL(I2S_PLL_CTRL_REG3) = i2sreg3; + } + clk_i2s_pll_clk_set(pCLK); + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_i2s_pll_clk_set(M4CLK_Type *pCLK) + * @brief This API is used to set the I2s_pll_clk + * @param[in] pCLK : pointer to the processor clock source + * @return RSI_OK on success + */ + +rsi_error_t clk_i2s_pll_clk_set(M4CLK_Type *pCLK) +{ + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + SPI_MEM_MAP_PLL(I2S_PLL_CTRL_REG11) = 0xFFFF; + while ((pCLK->PLL_STAT_REG_b.I2SPLL_LOCK) != 1) + ; /* checking for pll lck */ + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_i2s_pll_clk_reset(void) + * @brief This API is used to set the I2s_pll_clk + * @return RSI_OK on success + */ + +rsi_error_t clk_i2s_pll_clk_reset(void) +{ + SPI_MEM_MAP_PLL(I2S_PLL_CTRL_REG11) = 0x01FF; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_intf_pll_clk_enable(boolean_t clkEnable) + * @brief This API is used to Enable the Intf_PLL output clock + * @param[in] clkEnable : enable the clock + * @return RSI_OK on success + */ + +rsi_error_t clk_intf_pll_clk_enable(boolean_t clkEnable) +{ + if (clkEnable == Enable) { + /*Enable SoC-PLL*/ + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG1) |= PLL_500_CLK_ENABLE; + } else { + /*Disable SoC-PLL*/ + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG1) &= (uint16_t)(~(PLL_500_CLK_ENABLE)); + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_intf_pll_pd_enable(boolean_t en) + * @brief This API is used to Enable the PdEnable(power down) + * @param[in] en : enable + * @return RSI_OK on success + */ + +rsi_error_t clk_intf_pll_pd_enable(boolean_t en) +{ + if (en == Enable) { + /*Enable power down*/ + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG1) |= PLL_500_PD; + } else { + /*Disable power down*/ + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG1) &= (uint16_t)(~(PLL_500_PD)); + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_intf_pll_turn_off(void) + * @brief This API is used to TurnOff the Intf_PLL + * @return RSI_OK on success + */ + +rsi_error_t clk_intf_pll_turn_off(void) +{ + uint16_t intfreg1 = 0x31c9; + /*Set PLL PD Bit*/ + intfreg1 |= PLL_500_PD; + /* setting the bit reset */ + intfreg1 |= PLL_500_RST; + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG1) = intfreg1; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_set_intf_pll_freq(M4CLK_Type *pCLK, uint32_t intfPllFreq, uint32_t pllRefClk) + * @brief This API is used to set the INTFPLL clock to particular frequency + * @param[in] pCLK : pointer to the processor clock source + * @param[in] intfPllFreq : input frequency of PLL frequency + * @param[in] pllRefClk : PLL reference clock + * @return RSI_OK on success + */ + +rsi_error_t clk_set_intf_pll_freq(M4CLK_Type *pCLK, uint32_t intfPllFreq, uint32_t pllRefClk) +{ + uint16_t shiftFac = 0; + uint16_t intfPllMulFac = 0; + uint16_t intfPllDivFac = 0; + uint16_t reg = 0; + uint16_t dcoFreq = 0; + uint16_t intfreg1 = 0x31c9, intfreg3 = 0, intfPllTvRead = 0; + + /*Parameter validation */ + if ((pCLK == NULL) || (intfPllFreq < INTF_PLL_MIN_FREQUECY) || (intfPllFreq > INTF_PLL_MAX_FREQUECY)) { + return INVALID_PARAMETERS; + } + intfPllFreq = (intfPllFreq / 1000000); + pllRefClk = (pllRefClk / 1000000); + + if ((MCU_RET->CHIP_CONFIG_MCU_READ_b.LIMIT_M4_FREQ_110MHZ_b == 1) || (M4_BBFF_STORAGE1 & BIT(10))) { + if (intfPllFreq >= 201) { + /*New table*/ + /* Program PLL to 200Mhz */ + /* Call low level API with m,n,p values for 200Mhz configuration. */ + clk_intf_pll_set_freq_div(pCLK, 1, 0, 39, 199, 0, 1, 1); + return ERROR_INVALID_INPUT_FREQUENCY; + } else { + /* Derive the m,n,p values as per the newer table*/ + /* program PLL with derived values */ + /* Wait for PLL lock*/ + if (intfPllFreq < 2) { + shiftFac = 7; + } else if (intfPllFreq < 3) { + shiftFac = 6; + } else if (intfPllFreq < 6) { + shiftFac = 5; + } else if (intfPllFreq < 12) { + shiftFac = 4; + } else if (intfPllFreq < 23) { + shiftFac = 3; + } else if (intfPllFreq < 46) { + shiftFac = 2; + } else if (intfPllFreq < 91) { + shiftFac = 1; + } else { + shiftFac = 0; + } + + intfPllDivFac = (uint16_t)((1 << shiftFac) - 1); + + intfPllMulFac = (uint16_t)(((intfPllDivFac + 1) * intfPllFreq) - 1); + + /*RESET PLL*/ + clk_intf_pll_clk_reset(); + + reg = SPI_MEM_MAP_PLL(SOCPLLMACROREG3); + reg = reg << 1; /* according to RTL bug SOCPLLMACROREG3 (read issue) will shift to one left shift */ + reg &= (uint16_t)(~(LDO_PROG_INTFPLL)); + reg |= 1 << 10; + + SPI_MEM_MAP_PLL(SOCPLLMACROREG3) = reg; + + intfreg1 &= (uint16_t)(~(DCO_FIX_SEL_MASK)); + /*writing the value into the dco_fix_sel=1*/ + intfreg1 |= 1; + + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG2) = (uint16_t)(((intfPllDivFac) << 9) | ((pllRefClk - 1) << 3)); + intfreg1 &= (uint16_t)(~(PLL_500_M_MASK)); + intfreg1 |= (uint16_t)((intfPllMulFac << 6) | PLL_500_CLK_ENABLE); /* m factor */ + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG1) = intfreg1; + + /*Enable */ + clk_intf_pll_clk_set(pCLK); + /* Set and clear(read modify write) INTFPLL500CTRLREG7 BIT[4] : TV value will be latched */ + + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG7) |= SPI_INP_RD_EN; + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG7) &= (uint16_t)(~(SPI_INP_RD_EN)); + /* Read the TV value from INTFPLL500CTRLREG12 BIT[15 : 11]*/ + intfPllTvRead = (SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG12) & 0xF800) >> 11; + + if (intfPllTvRead <= ((M4_BBFF_STORAGE1 & 0x03E0) >> 5)) { + /*New table*/ + /* Program PLL to 200Mhz */ + /* Call low level API with m,n,p values for 200Mhz configuration.*/ + clk_intf_pll_set_freq_div(pCLK, 1, 0, 39, 199, 0, 1, 1); + return ERROR_INVALID_INPUT_FREQUENCY; + + } else { + /*Program the required frequency by user*/ + return RSI_OK; + } + } + + } else { /* older table */ + if (intfPllFreq < 2) { + shiftFac = 7; + } else if (intfPllFreq < 4) { + shiftFac = 6; + } else if (intfPllFreq < 8) { + shiftFac = 5; + } else if (intfPllFreq < 16) { + shiftFac = 4; + } else if (intfPllFreq < 32) { + shiftFac = 3; + } else if (intfPllFreq < 64) { + shiftFac = 2; + } else if (intfPllFreq < 127) { + shiftFac = 1; + } else { + shiftFac = 0; + } + dcoFreq = (uint16_t)(intfPllFreq << shiftFac); + intfPllMulFac = (uint16_t)((intfPllFreq << shiftFac) - 1); + intfPllDivFac = (uint16_t)((1 << shiftFac) - 1); + /*RESET PLL*/ + clk_intf_pll_clk_reset(); + if (intfPllFreq >= 201) { + if ((intfPllFreq % 2) == 0) { + intfreg3 &= (uint16_t)(~(FCW_F_MASK)); + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG3) = intfreg3; + } else { + intfreg3 |= (8192 << 2); + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG3) = intfreg3; + } + } + + if (dcoFreq >= 251) { + + intfreg1 &= (uint16_t)(~(DCO_FIX_SEL_MASK)); + /*writing the value into the dco_fix_sel=2*/ + intfreg1 |= 2; + reg = SPI_MEM_MAP_PLL(SOCPLLMACROREG3); + reg = reg << 1; + reg &= (uint16_t)(~(LDO_PROG_INTFPLL)); + reg |= 5 << 10; + SPI_MEM_MAP_PLL(SOCPLLMACROREG3) = reg; + intfPllMulFac = ((dcoFreq / 2) - 1); + intfreg1 |= PLL_500_CLK_ENABLE; /* soc_pll_clk o/p en */ + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG2) = (uint16_t)((intfPllDivFac << 9) | ((pllRefClk - 1) << 3)); + intfreg1 &= (uint16_t)(~(PLL_500_M_MASK)); + intfreg1 |= (uint16_t)((intfPllMulFac << 6) | PLL_500_CLK_ENABLE); /* m factor */ + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG1) = intfreg1; + } else if ((dcoFreq >= 201) && (dcoFreq <= 250)) { + intfreg1 &= (uint16_t)(~(DCO_FIX_SEL_MASK)); + reg = SPI_MEM_MAP_PLL(SOCPLLMACROREG3); + reg = reg << 1; /* according to RTL bug SOCPLLMACROREG3 (read issue) will shift to one left shift */ + reg &= (uint16_t)(~(LDO_PROG_INTFPLL)); + reg |= 5 << 10; + SPI_MEM_MAP_PLL(SOCPLLMACROREG3) = reg; + intfPllMulFac = ((dcoFreq / 2) - 1); + intfreg1 |= PLL_500_CLK_ENABLE; /* soc_pll_clk o/p en */ + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG2) = (uint16_t)((intfPllDivFac << 9) | ((pllRefClk - 1) << 3)); + intfreg1 &= (uint16_t)(~(PLL_500_M_MASK)); + intfreg1 |= (uint16_t)((intfPllMulFac << 6) | PLL_500_CLK_ENABLE); /* m factor */ + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG1) = intfreg1; + } else { + intfreg3 &= (uint16_t)(~(FCW_F_MASK)); + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG3) = intfreg3; + intfreg1 &= (uint16_t)(~(DCO_FIX_SEL_MASK)); + intfreg1 |= 1; + reg = SPI_MEM_MAP_PLL(SOCPLLMACROREG3); + reg = reg << 1; + reg &= (uint16_t)(~(LDO_PROG_INTFPLL)); + reg |= 4 << 10; + SPI_MEM_MAP_PLL(SOCPLLMACROREG3) = reg; + intfreg1 |= PLL_500_CLK_ENABLE; /* soc_pll_clk o/p en */ + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG2) = (uint16_t)((intfPllDivFac << 9) | ((pllRefClk - 1) << 3)); + intfreg1 &= (uint16_t)(~(PLL_500_M_MASK)); + intfreg1 |= (uint16_t)(((intfPllMulFac << 6) | PLL_500_CLK_ENABLE)); /* m factor */ + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG1) = intfreg1; + } + /*Enable */ + + clk_intf_pll_clk_set(pCLK); + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_intf_pll_set_freq_div(M4CLK_Type *pCLK, + * boolean_t clk_en, + * uint16_t divFactor, + * uint16_t nFactor, + * uint16_t mFactor, + * uint16_t fcwF, + * uint16_t dcoFixSel, + * uint16_t ldoProg) + * @brief This API is used to divide the Intf PLL clock frequency + * @param[in] pCLK : pointer to the processor clock source + * @param[in] clk_en : enable the clock for Intf PLL clock frequency + * @param[in] divFactor : division factor for Intf PLL clock frequency + * @param[in] nFactor : n number of factor for Intf PLL clock frequency + * @param[in] mFactor : m number of factor for Intf PLL clock frequency + * @param[in] fcwF : frequency for Intf PLL clock frequency + * @param[in] dcoFixSel : fixed select for Intf PLL clock frequency + * @param[in] ldoProg : ldo program for Intf PLL clock frequency + * @return RSI_OK on success + */ + +rsi_error_t clk_intf_pll_set_freq_div(M4CLK_Type *pCLK, + boolean_t clk_en, + uint16_t divFactor, + uint16_t nFactor, + uint16_t mFactor, + uint16_t fcwF, + uint16_t dcoFixSel, + uint16_t ldoProg) +{ + uint16_t intfreg1 = 0x31c9, intfreg3 = 0, reg = 0, intfPllTvRead = 0; + + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + /*RESET PLL*/ + clk_intf_pll_clk_reset(); + if ((MCU_RET->CHIP_CONFIG_MCU_READ_b.LIMIT_M4_FREQ_110MHZ_b == 1) || (M4_BBFF_STORAGE1 & BIT(10))) { + if (clk_en) { + intfreg3 &= (uint16_t)(~(FCW_F_MASK)); + intfreg3 = fcwF << 2; + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG3) = intfreg3; + intfreg1 &= (uint16_t)(~(DCO_FIX_SEL_MASK)); + intfreg1 |= 1; + reg = SPI_MEM_MAP_PLL(SOCPLLMACROREG3); + reg = reg << 1; /* according to RTL bug SOCPLLMACROREG3 (read issue) will shift to one left shift */ + reg &= (uint16_t)(~(LDO_PROG_INTFPLL)); + reg |= 1 << 10; + SPI_MEM_MAP_PLL(SOCPLLMACROREG3) = reg; + intfreg1 |= PLL_500_CLK_ENABLE; /* soc_pll_clk o/p en */ + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG2) = (uint16_t)((divFactor << 9) | (nFactor << 3)); + intfreg1 &= (uint16_t)(~(PLL_500_M_MASK)); + intfreg1 |= (uint16_t)((mFactor << 6) | PLL_500_CLK_ENABLE); /* m factor */ + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG1) = intfreg1; + } else { + intfreg1 &= (uint16_t)(~PLL_500_CLK_ENABLE); + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG1) = intfreg1; /* soc_pll_clk o/p disable */ + } + /*Enable */ + clk_intf_pll_clk_set(pCLK); + /* Set and clear(read modify write) PLL500CTRLREG7 BIT[4] : TV value will be latched */ + + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG7) |= SPI_INP_RD_EN; + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG7) &= (uint16_t)(~(SPI_INP_RD_EN)); + + /* Read the TV value from PLL500CTRLREG12 BIT[15 : 11] */ + intfPllTvRead = (SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG12) & 0xF800) >> 11; + + if ((intfPllTvRead <= ((M4_BBFF_STORAGE1 & 0x03E0) >> 5)) && (divFactor == 0)) { + /*RESET PLL*/ + clk_intf_pll_clk_reset(); + return ERROR_INVALID_INPUT_FREQUENCY; + } else { + /*Program the required frequency by user*/ + return RSI_OK; + } + } else { + if (clk_en) { + intfreg3 &= (uint16_t)(~(FCW_F_MASK)); + intfreg3 = fcwF << 2; + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG3) = intfreg3; + intfreg1 &= (uint16_t)(~(DCO_FIX_SEL_MASK)); + intfreg1 |= dcoFixSel; + reg = SPI_MEM_MAP_PLL(SOCPLLMACROREG3); + reg = reg << 1; /* according to RTL bug SOCPLLMACROREG3 (read issue) will shift to one left shift */ + reg &= (uint16_t)(~(LDO_PROG_INTFPLL)); + reg |= (uint16_t)(ldoProg << 10); + SPI_MEM_MAP_PLL(SOCPLLMACROREG3) = reg; + intfreg1 |= PLL_500_CLK_ENABLE; /* soc_pll_clk o/p en */ + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG2) = (uint16_t)((divFactor << 9) | (nFactor << 3)); + intfreg1 &= (uint16_t)(~(PLL_500_M_MASK)); + intfreg1 |= (uint16_t)((mFactor << 6) | PLL_500_CLK_ENABLE); /* m factor */ + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG1) = intfreg1; + } else { + intfreg1 &= (uint16_t)(~PLL_500_CLK_ENABLE); + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG1) = intfreg1; /* soc_pll_clk o/p disable */ + } + /*Enable */ + clk_intf_pll_clk_set(pCLK); + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_intf_pll_clk_bypass_enable(boolean_t clkEnable) + * @brief This API is used to Enable bypass clock + * @param[in] clkEnable : enable the clock + * @return RSI_OK on success + */ + +rsi_error_t clk_intf_pll_clk_bypass_enable(boolean_t clkEnable) +{ + if (clkEnable == Enable) { + /*Enable PLL clock*/ + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG1) |= PLL_500_BYPASS; + } else { + /*Disable PLL clock*/ + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG1) &= (uint16_t)(~(PLL_500_BYPASS)); + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_intf_pll_turn_on() + * @brief This API is used to TurnOn the Intf_PLL + * @return RSI_OK on success + */ + +rsi_error_t clk_intf_pll_turn_on() +{ + uint16_t intfreg1 = 0x31c9; + + intfreg1 &= (uint16_t)(~PLL_500_PD); /* clearing pd */ + intfreg1 &= (uint16_t)(~PLL_500_RST); /* clearing reset */ + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG1) = intfreg1; + + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_intf_pll_clk_reset(void) + * @brief This API is used to Reset the Intf_PLL + * @return RSI_OK on success + */ + +rsi_error_t clk_intf_pll_clk_reset(void) +{ + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG11) = 0x01FF; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_intf_pll_clk_set(M4CLK_Type *pCLK) + * @brief This API is used to Enable the Intf_PLL + * @param[in] pCLK : pointer to the processor clock source + * @return RSI_OK on success + */ + +rsi_error_t clk_intf_pll_clk_set(M4CLK_Type *pCLK) +{ + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG11) = 0xFFFF; + while ((pCLK->PLL_STAT_REG_b.INTFPLL_LOCK) != 1) + ; // checking for pll lck + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_peripheral_clk_enable1(M4CLK_Type *pCLK, uint32_t flags) + * @brief This API is used to Enable the peripheral cloks for SET1 register + * @param[in] pCLK : pointer to the processor clock source + * @param[in] flags : flags for SET1 register + * @return RSI_OK on success + */ + +rsi_error_t clk_peripheral_clk_enable1(M4CLK_Type *pCLK, uint32_t flags) +{ + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + pCLK->CLK_ENABLE_SET_REG1 = flags; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_peripheral_clk_disable1(M4CLK_Type *pCLK, uint32_t flags) + * @brief This API is used to disable the peripheral cloks for CLR1 register + * @param[in] pCLK : pointer to the processor clock source + * @param[in] flags : flags for CLR1 register + * @return RSI_OK on success + */ + +rsi_error_t clk_peripheral_clk_disable1(M4CLK_Type *pCLK, uint32_t flags) +{ + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + pCLK->CLK_ENABLE_CLEAR_REG1 = flags; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_peripheral_clk_enable2(M4CLK_Type *pCLK, uint32_t flags) + * @brief This API is used to Enable the peripheral cloks for SET2 register + * @param[in] pCLK : pointer to the processor clock source + * @param[in] flags : flags for SET2 register + * @return RSI_OK on success + */ + +rsi_error_t clk_peripheral_clk_enable2(M4CLK_Type *pCLK, uint32_t flags) +{ + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + pCLK->CLK_ENABLE_SET_REG2 = flags; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_peripheral_clk_disable2(M4CLK_Type *pCLK, uint32_t flags) + * @brief This API is used to disable the peripheral cloks for CLR2 register + * @param[in] pCLK : pointer to the processor clock source + * @param[in] flags : flags for CLR2 register + * @return RSI_OK on success + */ + +rsi_error_t clk_peripheral_clk_disable2(M4CLK_Type *pCLK, uint32_t flags) +{ + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + pCLK->CLK_ENABLE_CLEAR_REG2 = flags; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_peripheral_clk_enable3(M4CLK_Type *pCLK, uint32_t flags) + * @brief This API is used to Enable the peripheral cloks for SET3 register + * @param[in] pCLK : pointer to the processor clock source + * @param[in] flags : flags for SET3 register + * @return RSI_OK on success + */ + +rsi_error_t clk_peripheral_clk_enable3(M4CLK_Type *pCLK, uint32_t flags) +{ + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + pCLK->CLK_ENABLE_SET_REG3 = flags; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_peripheral_clk_disable3(M4CLK_Type *pCLK, uint32_t flags) + * @brief This API is used to disable the peripheral cloks for CLR3 register + * @param[in] pCLK : pointer to the processor clock source + * @param[in] flags : flags for CLR3 register + * @return RSI_OK on success + */ + +rsi_error_t clk_peripheral_clk_disable3(M4CLK_Type *pCLK, uint32_t flags) +{ + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + pCLK->CLK_ENABLE_CLEAR_REG3 = flags; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_dynamic_clk_gate_disable(M4CLK_Type *pCLK, uint32_t flags) + * @brief This API is used to disable the dynamic clock gate for peripherals + * @param[in] pCLK : pointer to the processor clock source + * @param[in] flags : flags for dynamic clock gate of peripherals + * @return RSI_OK on success + */ + +rsi_error_t clk_dynamic_clk_gate_disable(M4CLK_Type *pCLK, uint32_t flags) +{ + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + pCLK->DYN_CLK_GATE_DISABLE_REG = (pCLK->DYN_CLK_GATE_DISABLE_REG) & (0xFFFFFFFF & ~flags); + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_dynamic_clk_gate_disable2(M4CLK_Type *pCLK, uint32_t flags) + * @brief This API is used to disable the dynamic clock gate for peripherals + * @param[in] pCLK : pointer to the processor clock source + * @param[in] flags : flags for dynamic clock gate of peripherals + * @return RSI_OK on success + */ + +rsi_error_t clk_dynamic_clk_gate_disable2(M4CLK_Type *pCLK, uint32_t flags) +{ + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + pCLK->DYN_CLK_GATE_DISABLE_REG2 = (pCLK->DYN_CLK_GATE_DISABLE_REG2) & (0xFFFFFFFF & ~flags); + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_dynamic_clk_gate_enable(M4CLK_Type *pCLK, uint32_t flags) + * @brief This API is used to enable the dynamic clock gate for peripherals + * @param[in] pCLK : pointer to the processor clock source + * @param[in] flags : flags for dynamic clock gate of peripherals + * @return RSI_OK on success + */ + +rsi_error_t clk_dynamic_clk_gate_enable(M4CLK_Type *pCLK, uint32_t flags) +{ + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + pCLK->DYN_CLK_GATE_DISABLE_REG = (pCLK->DYN_CLK_GATE_DISABLE_REG | flags) & 0xFFFFFFFF; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_dynamic_clk_gate_enable2(M4CLK_Type *pCLK, uint32_t flags) + * @brief This API is used to enable the dynamic clock gate for peripherals + * @param[in] pCLK : pointer to the processor clock source + * @param[in] flags : flags for dynamic clock gate of peripherals + * @return RSI_OK on success + */ + +rsi_error_t clk_dynamic_clk_gate_enable2(M4CLK_Type *pCLK, uint32_t flags) +{ + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + pCLK->DYN_CLK_GATE_DISABLE_REG2 = (pCLK->DYN_CLK_GATE_DISABLE_REG2 | flags) & 0xFFFFFFFF; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_qspi_clk_config(M4CLK_Type *pCLK, + * QSPI_CLK_SRC_SEL_T clkSource, + * boolean_t swalloEn, + * boolean_t OddDivEn, + * uint32_t divFactor) + * @brief This API is used to configure the Qspi clocks + * @param[in] pCLK : pointer to the processor clock source + * @param[in] clkSource : clock source for configure the Qspi clocks + * @param[in] swalloEn : enable for Qspi clocks + * @param[in] oddDivEn : enable for Qspi clocks + * @param[in] divFactor : division factor for Qspi clocks + * @return clock spi on success + */ + +rsi_error_t clk_qspi_clk_config(M4CLK_Type *pCLK, + QSPI_CLK_SRC_SEL_T clkSource, + boolean_t swalloEn, + boolean_t OddDivEn, + uint32_t divFactor) +{ + + rsi_error_t errorCode = RSI_OK; + /*Parameter validation */ + if ((pCLK == NULL) || (divFactor > QSPI_MAX_CLK_DIVISION_FACTOR)) { + return INVALID_PARAMETERS; + } + + /*disabling the clocks*/ + clk_peripheral_clk_disable(pCLK, QSPI_CLK); + /*Select clock MUX*/ + switch (clkSource) { + case QSPI_ULPREFCLK: + pCLK->CLK_CONFIG_REG1_b.QSPI_CLK_SEL = 0x00; + break; + + case QSPI_MODELPLLCLK2: + /*Check clock is present is or not before switching*/ + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, MODEM_PLL_CLK_PRESENT)) { + errorCode = ERROR_CLOCK_NOT_ENABLED; + break; + } + /*Update the clock MUX*/ + pCLK->CLK_CONFIG_REG1_b.QSPI_CLK_SEL = 0x02; + break; + + case QSPI_INTFPLLCLK: + /*Check clock is present is or not before switching*/ + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, INTF_PLL_CLK_PRESENT)) { + errorCode = ERROR_CLOCK_NOT_ENABLED; + break; + } /*Update the clock MUX*/ + pCLK->CLK_CONFIG_REG1_b.QSPI_CLK_SEL = 0x01; + break; + + case QSPI_SOCPLLCLK: + /*Check clock is present is or not before switching*/ + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, SOC_PLL_CLK_PRESENT)) { + errorCode = ERROR_CLOCK_NOT_ENABLED; + break; + } + pCLK->CLK_CONFIG_REG1_b.QSPI_CLK_SEL = 0x03; + break; + + case M4_SOCCLKNOSWLSYNCCLKTREEGATED: + /*incase of qspi in sync with soc*/ + pCLK->CLK_ENABLE_SET_REG3 = QSPI_M4_SOC_SYNC; + break; + + default: + errorCode = INVALID_PARAMETERS; + break; + } + if (errorCode == RSI_OK) { + /*wait for QSPI clock switched */ + while ((pCLK->PLL_STAT_REG_b.QSPI_CLK_SWITCHED) != 1) + ; + + /*update the division factor */ + pCLK->CLK_CONFIG_REG1_b.QSPI_CLK_DIV_FAC = (unsigned int)(divFactor & 0x3F); + /*Specifies whether QSPI clock is in sync with Soc clock. + Before enabling this make sure that qspi_clk_onehot_enable is 1\92b0 to enable glitch free switching*/ + /*Enable the QSPI clock*/ + if (swalloEn) { + pCLK->CLK_CONFIG_REG1_b.QSPI_CLK_SWALLOW_SEL = 1; + } else { + pCLK->CLK_CONFIG_REG1_b.QSPI_CLK_SWALLOW_SEL = 0; + } + if (OddDivEn) { + pCLK->CLK_CONFIG_REG2_b.QSPI_ODD_DIV_SEL = 1; + } else { + pCLK->CLK_CONFIG_REG2_b.QSPI_ODD_DIV_SEL = 0; + } + } + clk_peripheral_clk_enable(pCLK, QSPI_CLK, ENABLE_STATIC_CLK); + return errorCode; +} +#ifdef SLI_SI917B0 +/*==============================================*/ +/** + * @fn rsi_error_t clk_qspi_2_clk_config(M4CLK_Type *pCLK, + * QSPI_CLK_SRC_SEL_T clkSource, + * boolean_t swalloEn, + * boolean_t OddDivEn, + * uint32_t divFactor) + * @brief This API is used to configure the Qspi clocks + * @param[in] pCLK : pointer to the processor clock source + * @param[in] clkSource : clock source for configure the Qspi clocks + * @param[in] swalloEn : enable for Qspi clocks + * @param[in] oddDivEn : enable for Qspi clocks + * @param[in] divFactor : division factor for Qspi clocks + * @return clock spi on success + */ + +rsi_error_t clk_qspi_2_clk_config(M4CLK_Type *pCLK, + QSPI_CLK_SRC_SEL_T clkSource, + boolean_t swalloEn, + boolean_t OddDivEn, + uint32_t divFactor) +{ + + rsi_error_t errorCode = RSI_OK; + /*Parameter validation */ + if ((pCLK == NULL) || (divFactor > QSPI_MAX_CLK_DIVISION_FACTOR)) { + return INVALID_PARAMETERS; + } + + /*disabling the clocks*/ + clk_peripheral_clk_disable(pCLK, QSPI_2_CLK); + /*Select clock MUX*/ + switch (clkSource) { + case QSPI_ULPREFCLK: + pCLK->CLK_CONFIG_REG6_b.QSPI_2_CLK_SEL = 0x00; + break; + + case QSPI_MODELPLLCLK2: + /*Check clock is present is or not before switching*/ + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, MODEM_PLL_CLK_PRESENT)) { + errorCode = ERROR_CLOCK_NOT_ENABLED; + break; + } + /*Update the clock MUX*/ + pCLK->CLK_CONFIG_REG6_b.QSPI_2_CLK_SEL = 0x02; + break; + + case QSPI_INTFPLLCLK: + /*Check clock is present is or not before switching*/ + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, INTF_PLL_CLK_PRESENT)) { + errorCode = ERROR_CLOCK_NOT_ENABLED; + break; + } /*Update the clock MUX*/ + pCLK->CLK_CONFIG_REG6_b.QSPI_2_CLK_SEL = 0x01; + break; + + case QSPI_SOCPLLCLK: + /*Check clock is present is or not before switching*/ + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, SOC_PLL_CLK_PRESENT)) { + errorCode = ERROR_CLOCK_NOT_ENABLED; + break; + } + pCLK->CLK_CONFIG_REG6_b.QSPI_2_CLK_SEL = 0x03; + break; + + case M4_SOCCLKNOSWLSYNCCLKTREEGATED: + /*incase of qspi in sync with soc*/ + pCLK->CLK_ENABLE_SET_REG1 = QSPI_2_M4_SOC_SYNC; + break; + + default: + errorCode = INVALID_PARAMETERS; + break; + } + if (errorCode == RSI_OK) { + /*wait for QSPI clock switched */ + while ((pCLK->PLL_STAT_REG_b.QSPI_2_CLK_SWITCHED) != 1) + ; + + /*update the division factor */ + pCLK->CLK_CONFIG_REG6_b.QSPI_2_CLK_DIV_FAC = (unsigned int)(divFactor & 0x3F); + /*Specifies whether QSPI clock is in sync with Soc clock. + Before enabling this make sure that qspi_clk_onehot_enable is 1\92b0 to enable glitch free switching*/ + /*Enable the QSPI clock*/ + if (swalloEn) { + pCLK->CLK_CONFIG_REG6_b.QSPI_2_CLK_SWALLOW_SEL = 1; + } else { + pCLK->CLK_CONFIG_REG6_b.QSPI_2_CLK_SWALLOW_SEL = 0; + } + if (OddDivEn) { + pCLK->CLK_CONFIG_REG6_b.QSPI_2_ODD_DIV_SEL = 1; + } else { + pCLK->CLK_CONFIG_REG6_b.QSPI_2_ODD_DIV_SEL = 0; + } + } + clk_peripheral_clk_enable(pCLK, QSPI_2_CLK, ENABLE_STATIC_CLK); + return errorCode; +} +#endif +/*==============================================*/ +/** +* @fn rsi_error_t clk_ssi_mst_clk_config(M4CLK_Type *pCLK, +* CLK_ENABLE_T clkType, +* SSI_MST_CLK_SRC_SEL_T clkSource, +* uint32_t divFactor) +* @brief This API is used to configure the SSI clocks +* @param[in] pCLK : pointer to the processor clock source +* @param[in] clkType : clock type for SSI clocks +* @param[in] clkSource : cource clock for SSI clocks +* @param[in] divFactor : division factor for SSI clocks +* @return RSI_OK on success +*/ + +rsi_error_t clk_ssi_mst_clk_config(M4CLK_Type *pCLK, + CLK_ENABLE_T clkType, + SSI_MST_CLK_SRC_SEL_T clkSource, + uint32_t divFactor) +{ + /*Parameter validation */ + if ((pCLK == NULL) || (divFactor > SSI_MAX_CLK_DIVISION_FACTOR)) { + return INVALID_PARAMETERS; + } + + /*Disable the clock */ + clk_peripheral_clk_disable(pCLK, SSIMST_CLK); + /*Master mode */ + switch (clkSource) { + case SSI_ULPREFCLK: + pCLK->CLK_CONFIG_REG1_b.SSI_MST_SCLK_SEL = 0x00; + break; + + case SSI_SOCPLLCLK: + /*Check clock is present is or not before switching*/ + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, SOC_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + pCLK->CLK_CONFIG_REG1_b.SSI_MST_SCLK_SEL = 0x01; + break; + + case SSI_MODEMPLLCLK1: + + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, MODEM_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + pCLK->CLK_CONFIG_REG1_b.SSI_MST_SCLK_SEL = 0x02; + break; + + case SSI_INTFPLLCLK: + /*Check clock is present is or not before switching*/ + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, INTF_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + pCLK->CLK_CONFIG_REG1_b.SSI_MST_SCLK_SEL = 0x03; + break; + + case SSI_MODELPLLCLK2: + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, MODEM_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + pCLK->CLK_CONFIG_REG1_b.SSI_MST_SCLK_SEL = 0x04; + break; + + case M4_SOCCLKFOROTHERCLKS: + pCLK->CLK_ENABLE_SET_REG3 = M4_SOC_CLK_FOR_OTHER_ENABLE; + pCLK->CLK_CONFIG_REG1_b.SSI_MST_SCLK_SEL = 0x05; + break; + + default: + return INVALID_PARAMETERS; + } + /*wait for clock switch */ + while ((pCLK->PLL_STAT_REG_b.SSI_MST_SCLK_SWITCHED) != 1) + ; + /*division factor */ + pCLK->CLK_CONFIG_REG1_b.SSI_MST_SCLK_DIV_FAC = (unsigned int)(divFactor & 0x0F); + /*Enable the SSI clock */ + clk_peripheral_clk_enable(pCLK, SSIMST_CLK, clkType); + return RSI_OK; +} +#ifndef SLI_SI917 + +/*==============================================*/ +/** + * @fn rsi_error_t clk_sd_mem_clk_config(M4CLK_Type *pCLK, boolean_t swalloEn, SDMEM_CLK_SRC_SEL_T clkSource, uint32_t divFactor) + * @brief This API is used to configure the SdMem clocks + * @param[in] pCLK : pointer to the processor clock source + * @param[in] swalloEn : enable for SdMem clocks + * @param[in] clkSource : clock source for SdMem clocks + * @param[in] divFactor : division factor for SdMem clocks + * @return RSI_OK on success + */ + +rsi_error_t clk_sd_mem_clk_config(M4CLK_Type *pCLK, + boolean_t swalloEn, + SDMEM_CLK_SRC_SEL_T clkSource, + uint32_t divFactor) +{ + /*Parameter validation */ + if ((pCLK == NULL) || (divFactor > SDMEM_MAX_CLK_DIVISION_FACTOR)) { + return INVALID_PARAMETERS; + } + + /*Disable the SDMEM clock*/ + clk_peripheral_clk_disable(pCLK, SD_MEM_CLK); + switch (clkSource) { + case SDMEM_SOCPLLCLK: + /*Check clock is present or not before switching*/ + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, SOC_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + pCLK->SD_MEM_CLOCK_REG_b.SD_MEM_INTF_CLK_SEL = 0x00; + break; + + case SDMEM_MODEMPLLCLK1: + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, MODEM_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + pCLK->SD_MEM_CLOCK_REG_b.SD_MEM_INTF_CLK_SEL = 0x01; + break; + + case SDMEM_INTFPLLCLK: + /*Check clock is present is or not before switching*/ + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, INTF_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + pCLK->SD_MEM_CLOCK_REG_b.SD_MEM_INTF_CLK_SEL = 0x02; + break; + + case M4_SOCCLKFOROTHERCLKSSDMEM: + pCLK->CLK_ENABLE_SET_REG3 = M4_SOC_CLK_FOR_OTHER_ENABLE; + pCLK->SD_MEM_CLOCK_REG_b.SD_MEM_INTF_CLK_SEL = 0x03; + break; + + default: + return INVALID_PARAMETERS; + } + /*wait for SD mem clock switch */ + while ((pCLK->PLL_STAT_REG_b.SD_MEM_INTF_CLK_SWITCHED) != 1) + ; + /*Update the division factor */ + pCLK->SD_MEM_CLOCK_REG_b.SD_MEM_INTF_CLK_DIV_FAC = divFactor; + if (swalloEn) { + pCLK->SD_MEM_CLOCK_REG_b.SD_MEM_INTF_CLK_SWALLOW_SEL = 1; + } else { + pCLK->SD_MEM_CLOCK_REG_b.SD_MEM_INTF_CLK_SWALLOW_SEL = 0; + } + /*Enable SD memory clock */ + clk_peripheral_clk_enable(pCLK, SD_MEM_CLK, ENABLE_STATIC_CLK); + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_cci_clk_config(M4CLK_Type *pCLK, CCI_CLK_SRC_SEL_T clkSource, uint32_t divFactor, CLK_ENABLE_T clkType) + * @brief This API is used to configure the CCI clocks + * @param[in] pCLK : pointer to the processor clock source + * @param[in] clkSource : source clock for configure the CCI clocks + * @param[in] clkType : clock type for configure the CCI clocks + * @param[in] divFactor : division factor for configure the CCI clocks + * @return RSI_OK on success + */ + +rsi_error_t clk_cci_clk_config(M4CLK_Type *pCLK, CCI_CLK_SRC_SEL_T clkSource, uint32_t divFactor, CLK_ENABLE_T clkType) +{ + /*Parameter validation */ + if ((pCLK == NULL) || (divFactor > CCI_MAX_CLK_DIVISION_FACTOR)) { + return INVALID_PARAMETERS; + } + /*Enable CCI clock */ + clk_peripheral_clk_disable(pCLK, CCI_CLK); + /*cci_sync_mode_enable_for_ams = 0 */ + MISC_CFG_MISC_CTRL &= ~CCI_SYNC_MODE; + switch (clkSource) { + case CCI_M4_SOC_CLK_FOR_OTHER_CLKS: + pCLK->CLK_ENABLE_SET_REG3 = M4_SOC_CLK_FOR_OTHER_ENABLE; + pCLK->CLK_CONFIG_REG4_b.CCI_CLK_SEL = 0x00; + break; + + case CCI_INTF_PLL_CLK: + /*Check clock is present is or not before switching*/ + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, INTF_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + pCLK->CLK_CONFIG_REG4_b.CCI_CLK_SEL = 0x01; + break; + + case CCI_M4_SOC_CLK_NO_SWL_SYNC_CLK_TREE: + /*cci_sync_mode_enable_for_ams = 1*/ + MISC_CFG_MISC_CTRL |= CCI_SYNC_MODE; + break; + default: + return INVALID_PARAMETERS; + } + /*update the division factor */ + pCLK->CLK_CONFIG_REG2_b.CCI_CLK_DIV_FAC = divFactor; + /*Enable the CCI clock */ + clk_peripheral_clk_enable(pCLK, CCI_CLK, clkType); + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_can_clk_config(M4CLK_Type *pCLK, uint32_t divFactor, CLK_ENABLE_T clkType) + * @brief This API is used to configure the Can clocks + * @param[in] pCLK : pointer to the processor clock source + * @param[in] divFactor : division factor for configure the Can clocks + * @param[in] clkType : clock type for configure the Can clocks + * @return RSI_OK on success + */ + +rsi_error_t clk_can_clk_config(M4CLK_Type *pCLK, uint32_t divFactor, CLK_ENABLE_T clkType) +{ + if ((pCLK == NULL) || (divFactor > CAN_MAX_CLK_DIVISION_FACTOR)) { + return INVALID_PARAMETERS; + } + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + clk_peripheral_clk_disable(pCLK, CAN_CLK); + + pCLK->CLK_CONFIG_REG3_b.CAN1_CLK_DIV_FAC = divFactor; + + /*Disable the clock*/ + clk_peripheral_clk_enable(pCLK, CAN_CLK, clkType); + + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_ethernet_clk_config(M4CLK_Type *pCLK, + * boolean_t swalloEn, + * ETHERNET_CLK_SRC_SEL_T clkSource, + * uint32_t divFactor) + * @brief This API is used to configure the PLL_INTF clock + * @param[in] pCLK : pointer to the processor clock source + * @param[in] swalloEn : enable for PLL_INTF clock + * @param[in] clkSource : clock source for PLL_INTF clock + * @param[in] divFactor : division factor for PLL_INTF clock + * @return RSI_OK on success + */ + +rsi_error_t clk_ethernet_clk_config(M4CLK_Type *pCLK, + boolean_t swalloEn, + ETHERNET_CLK_SRC_SEL_T clkSource, + uint32_t divFactor) +{ + /*Parameter validation */ + if ((pCLK == NULL) || (divFactor > PLL_INTF_MAX_CLK_DIVISION_FACTOR)) { + return INVALID_PARAMETERS; + } + /*Disable Ethernet clock*/ + pCLK->CLK_ENABLE_CLEAR_REG2 = PLL_INTF_CLK_ENABLE; + if (clkSource == ETH_INTF_PLL_CLK) { + /*Check clock is present is or not before switching*/ + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, INTF_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + pCLK->CLK_CONFIG_REG1_b.PLL_INTF_CLK_SEL = 0; + } else { + /*Check clock is present or not before switching*/ + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, SOC_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + pCLK->CLK_CONFIG_REG1_b.PLL_INTF_CLK_SEL = 1; + } + while ((pCLK->PLL_STAT_REG_b.PLL_INTF_CLK_SWITCHED) != 1) + ; + /*Update the division factor */ + pCLK->CLK_CONFIG_REG1_b.PLL_INTF_CLK_DIV_FAC = divFactor; + if (swalloEn) { + pCLK->CLK_CONFIG_REG1_b.PLL_INTF_CLK_SWALLOW_SEL = 1; + } else { + pCLK->CLK_CONFIG_REG1_b.PLL_INTF_CLK_SWALLOW_SEL = 0; + } + pCLK->CLK_ENABLE_SET_REG2 = PLL_INTF_CLK_ENABLE; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_cci_clk_div(M4CLK_Type *pCLK, uint32_t divFactor) + * @brief This API is used to divide the CCI clock + * @param[in] pCLK : pointer to the processor clock source + * @param[in] divFactor : division factor for CCI clock + * @return RSI_OK on success + */ + +rsi_error_t clk_cci_clk_div(M4CLK_Type *pCLK, uint32_t divFactor) +{ + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + pCLK->CLK_CONFIG_REG2_b.CCI_CLK_DIV_FAC = divFactor; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_sd_mem_clk_div(M4CLK_Type *pCLK, boolean_t u8SwallowEn, uint32_t divFactor) + * @brief This API is used to divide the SDMEM clock + * @param[in] pCLK : pointer to the processor clock source + * @param[in] u8SwallowEn : enable for SDMEM clock + * @param[in] divFactor : division factor for SDMEM clock + * @return RSI_OK on success + */ + +rsi_error_t clk_sd_mem_clk_div(M4CLK_Type *pCLK, boolean_t u8SwallowEn, uint32_t divFactor) +{ + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + + if (u8SwallowEn) { + pCLK->SD_MEM_CLOCK_REG_b.SD_MEM_INTF_CLK_SWALLOW_SEL = 1; + } else { + pCLK->SD_MEM_CLOCK_REG_b.SD_MEM_INTF_CLK_SWALLOW_SEL = 0; + } + + /*SDMEM division selection */ + pCLK->SD_MEM_CLOCK_REG_b.SD_MEM_INTF_CLK_DIV_FAC = divFactor; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_usb_clk_config(M4CLK_Type *pCLK, USB_CLK_SRC_SEL_T clkSource, uint16_t divFactor) + * @brief This API is used to configure the USB clock + * @param[in] pCLK : pointer to the processor clock source + * @param[in] clkSource : source clock + * @param[in] divFactor : division factor + * @return RSI_OK on success + */ + +rsi_error_t clk_usb_clk_config(M4CLK_Type *pCLK, USB_CLK_SRC_SEL_T clkSource, uint16_t divFactor) +{ + /*Parameter validation */ + if ((pCLK == NULL) || (divFactor > USB_MAX_CLK_DIVISION_FACTOR)) { + return INVALID_PARAMETERS; + } + /*clock Disable */ + pCLK->CLK_ENABLE_CLEAR_REG3 = USB_PHY_CLK_IN_ENABLE; + switch (clkSource) { + case USB_MEMS_REF_CLK: + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, MODEM_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + /*mems_ref_clk from Modem PLL*/ + TASS_PLL_CTRL_SET_REG(AFEPLLCTRLREG1) |= MEMS_REF_CLK_ENABLE; + pCLK->CLK_CONFIG_REG5_b.USB_CLK_SEL = 0x00; + break; + + case USB_REFERENCE_CLK: + /*Reference clock*/ + pCLK->CLK_CONFIG_REG5_b.USB_CLK_SEL = 0x01; + break; + case USB_PLL_CLK: + /* usb_pll_clk from Modem PLL */ + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, MODEM_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + pCLK->CLK_CONFIG_REG5_b.USB_CLK_SEL = 0x02; + break; + default: + return INVALID_PARAMETERS; + } + /*Program the division factor */ + pCLK->CLK_CONFIG_REG6_b.USB_PHY_CLK_DIV_FAC = divFactor; + /*clock Enable */ + pCLK->CLK_ENABLE_SET_REG3 = USB_PHY_CLK_IN_ENABLE; + return RSI_OK; +} +#endif + +/*==============================================*/ +/** + * @fn rsi_error_t clk_ct_clk_config(M4CLK_Type *pCLK, CT_CLK_SRC_SEL_T clkSource, uint32_t divFactor, CLK_ENABLE_T clkType) + * @brief This API is used to configure the CT clocks + * @param[in] pCLK : pointer to the processor clock source + * @param[in] clkSource : source clock for CT clocks + * @param[in] clkType : source clock for CT clocks + * @param[in] divFactor : division factor for CT clocks + * @return RSI_OK on success + */ + +rsi_error_t clk_ct_clk_config(M4CLK_Type *pCLK, CT_CLK_SRC_SEL_T clkSource, uint32_t divFactor, CLK_ENABLE_T clkType) +{ + /*Parameter validation */ + if ((pCLK == NULL) || (divFactor > CT_MAX_CLK_DIVISION_FACTOR)) { + return INVALID_PARAMETERS; + } + /*Disable SCT clock*/ + clk_peripheral_clk_disable(pCLK, CT_CLK); + switch (clkSource) { + case CT_ULPREFCLK: + pCLK->CLK_CONFIG_REG5_b.CT_CLK_SEL = 0x00; + break; + + case CT_INTFPLLCLK: + /*Check clock is present is or not before switching*/ + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, INTF_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + pCLK->CLK_CONFIG_REG5_b.CT_CLK_SEL = 0x01; + break; + + case CT_SOCPLLCLK: + /*Check clock is present is or not before switching*/ + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, SOC_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + pCLK->CLK_CONFIG_REG5_b.CT_CLK_SEL = 0x02; + break; + + case M4_SOCCLKFOROTHERCLKSCT: + pCLK->CLK_ENABLE_SET_REG3 = M4_SOC_CLK_FOR_OTHER_ENABLE; + pCLK->CLK_CONFIG_REG5_b.CT_CLK_SEL = 0x03; + break; + default: + return INVALID_PARAMETERS; + } + /*wait for SCT switched */ + while ((pCLK->PLL_STAT_REG_b.CT_CLK_SWITCHED) != 1) + ; + /*Program the division factor */ + pCLK->CLK_CONFIG_REG5_b.CT_CLK_DIV_FAC = (unsigned int)(divFactor & 0x3F); + clk_peripheral_clk_enable(pCLK, CT_CLK, clkType); + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_i2s_clk_config(M4CLK_Type *pCLK, I2S_CLK_SRC_SEL_T clkSource, uint32_t divFactor) + * @brief This API is used to configure the I2S clocks + * @param[in] pCLK : pointer to the processor clock source + * @param[in] clkSource : source clock + * @param[in] divFactor : division factor + * @return RSI_OK on success + */ + +rsi_error_t clk_i2s_clk_config(M4CLK_Type *pCLK, I2S_CLK_SRC_SEL_T clkSource, uint32_t divFactor) +{ + /*Parameter validation */ + if ((pCLK == NULL) || (divFactor > I2S_MAX_CLK_DIVISION_FACTOR)) { + return INVALID_PARAMETERS; + } + /*Disable the I2S clock */ + clk_peripheral_clk_disable(pCLK, I2SM_CLK); + MISC_CFG_MISC_CTRL1 |= I2S_MASTER_SLAVE_MODE; + if (clkSource == I2S_PLLCLK) { + /*Check clock is present is or not before switching*/ + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, I2S_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + pCLK->CLK_CONFIG_REG5_b.I2S_CLK_SEL = 0; + } else { + pCLK->CLK_ENABLE_SET_REG3 = M4_SOC_CLK_FOR_OTHER_ENABLE; + pCLK->CLK_CONFIG_REG5_b.I2S_CLK_SEL = 1; + } + + /*Wait for I2S clock switch*/ + while ((pCLK->PLL_STAT_REG_b.I2S_CLK_SWITCHED) != 1) + ; + /*update the division factor */ + pCLK->CLK_CONFIG_REG5_b.I2S_CLK_DIV_FAC = (unsigned int)(divFactor & 0x3F); + /*enable the clock*/ + clk_peripheral_clk_enable(pCLK, I2SM_CLK, ENABLE_STATIC_CLK); + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_mcu_clk_cut_config(M4CLK_Type *pCLK, MCU_CLKOUT_SRC_SEL_T clkSource, uint32_t divFactor) + * @brief This API is used to configure the McuClkOut clocks + * @param[in] pCLK : pointer to the processor clock source + * @param[in] clkSource : source clock + * @param[in] divFactor : division factor + * @return RSI_OK on success + */ + +rsi_error_t clk_mcu_clk_cut_config(M4CLK_Type *pCLK, MCU_CLKOUT_SRC_SEL_T clkSource, uint32_t divFactor) +{ + /*Parameter validation */ + if ((pCLK == NULL) || (divFactor >= MCU_CLKOUT_MAX_CLK_DIVISION_FACTOR)) { + return INVALID_PARAMETERS; + } + clk_peripheral_clk_disable(pCLK, MCUCLKOUT_CLK); + /*clock out mux select */ + /*apply division factor */ + pCLK->CLK_CONFIG_REG3_b.MCU_CLKOUT_DIV_FAC = (unsigned int)(divFactor & 0x3F); + switch (clkSource) { + case MCUCLKOUT_ULP_32MHZ_RC_CLK: + pCLK->CLK_CONFIG_REG3_b.MCU_CLKOUT_SEL = 0x01; + break; + + case MCUCLKOUT_RF_REF_CLK: + pCLK->CLK_CONFIG_REG3_b.MCU_CLKOUT_SEL = 0x02; + break; + + case MCUCLKOUT_MEMS_REF_CLK: + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, MODEM_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + TASS_PLL_CTRL_SET_REG(AFEPLLCTRLREG1) |= MEMS_REF_CLK_ENABLE; + pCLK->CLK_CONFIG_REG3_b.MCU_CLKOUT_SEL = 0x03; + break; + + case MCUCLKOUT_ULP_20MHZ_RINGOSC_CLK: + ulpss_enable_ref_clks(MCU_ULP_20MHZ_RING_OSC_CLK_EN, ULP_PERIPHERAL_CLK, 0); + pCLK->CLK_CONFIG_REG3_b.MCU_CLKOUT_SEL = 0x04; + break; + + case MCUCLKOUT_ULP_DOUBLER_CLK: + ulpss_enable_ref_clks(MCU_ULP_DOUBLER_CLK_EN, ULP_PERIPHERAL_CLK, 0); + pCLK->CLK_CONFIG_REG3_b.MCU_CLKOUT_SEL = 0x05; + break; + + case MCUCLKOUT_ULP_32KHZ_RC_CLK: + ulpss_enable_ref_clks(MCU_ULP_32KHZ_RC_CLK_EN, ULP_PERIPHERAL_CLK, 0); + pCLK->CLK_CONFIG_REG3_b.MCU_CLKOUT_SEL = 0x07; + break; + + case MCUCLKOUT_ULP_32KHZ_XTAL_CLK: + ulpss_enable_ref_clks(MCU_ULP_32KHZ_XTAL_CLK_EN, ULP_PERIPHERAL_CLK, 0); + pCLK->CLK_CONFIG_REG3_b.MCU_CLKOUT_SEL = 0x08; + break; + + case MCUCLKOUT_ULP_32KHZ_RO_CLK: + ulpss_enable_ref_clks(MCU_ULP_32KHZ_RO_CLK_EN, ULP_PERIPHERAL_CLK, 0); + pCLK->CLK_CONFIG_REG3_b.MCU_CLKOUT_SEL = 0x09; + break; + + case MCUCLKOUT_INTF_PLL_CLK: + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, INTF_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + pCLK->CLK_CONFIG_REG3_b.MCU_CLKOUT_SEL = 0x0A; + break; + + case MCUCLKOUT_MODEM_PLL_CLK1: + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, MODEM_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + pCLK->CLK_CONFIG_REG3_b.MCU_CLKOUT_SEL = 0x0B; + break; + + case MCUCLKOUT_MODEM_PLL_CLK2: + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, MODEM_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + pCLK->CLK_CONFIG_REG3_b.MCU_CLKOUT_SEL = 0x0C; + break; + + case MCUCLKOUT_SOC_PLL_CLK: + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, SOC_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + pCLK->CLK_CONFIG_REG3_b.MCU_CLKOUT_SEL = 0x0D; + break; + + case MCUCLKOUT_I2S_PLL_CLK: + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, I2S_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + pCLK->CLK_CONFIG_REG3_b.MCU_CLKOUT_SEL = 0x0E; + break; + + case MCUCLKOUT_USB_PLL_CLK: + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, MODEM_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + pCLK->CLK_CONFIG_REG3_b.MCU_CLKOUT_SEL = 0x0F; + break; + + default: + return INVALID_PARAMETERS; + } + clk_peripheral_clk_enable(pCLK, MCUCLKOUT_CLK, ENABLE_STATIC_CLK); + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_m4_soc_clk_div(M4CLK_Type *pCLK, uint32_t divFactor) + * @brief This API is used to divide the M4soc clock + * @param[in] pCLK : pointer to the processor clock source + * @param[in] divFactor : division factor + * @return RSI_OK on success + */ + +rsi_error_t clk_m4_soc_clk_div(M4CLK_Type *pCLK, uint32_t divFactor) +{ + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + pCLK->CLK_CONFIG_REG5_b.M4_SOC_CLK_DIV_FAC = (unsigned int)(divFactor & 0x3F); + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_qspi_clk_div(M4CLK_Type *pCLK, boolean_t u8SwallowEn, boolean_t u8OddDivEn, uint32_t divFactor) + * @brief This API is used to divide the QSPI clock + * @param[in] pCLK : pointer to the processor clock source + * @param[in] u8SwallowEn : enable + * @param[in] u8OddDivEn : odd division enable + * @param[in] divFactor : division factor + * @return RSI_OK on success + */ + +rsi_error_t clk_qspi_clk_div(M4CLK_Type *pCLK, boolean_t u8SwallowEn, boolean_t u8OddDivEn, uint32_t divFactor) +{ + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + if (u8SwallowEn) { + pCLK->CLK_CONFIG_REG1_b.QSPI_CLK_SWALLOW_SEL = 1; + } else { + pCLK->CLK_CONFIG_REG1_b.QSPI_CLK_SWALLOW_SEL = 0; + } + if (u8OddDivEn) { + pCLK->CLK_CONFIG_REG2_b.QSPI_ODD_DIV_SEL = 1; + } else { + pCLK->CLK_CONFIG_REG2_b.QSPI_ODD_DIV_SEL = 0; + } + pCLK->CLK_CONFIG_REG1_b.QSPI_CLK_DIV_FAC = (unsigned int)(divFactor & 0x3F); + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_ct_clk_div(M4CLK_Type *pCLK, uint32_t divFactor) + * @brief This API is used to divide the CT clock + * @param[in] pCLK : pointer to the processor clock source + * @param[in] divFactor : division factor + * @return RSI_OK on success + */ + +rsi_error_t clk_ct_clk_div(M4CLK_Type *pCLK, uint32_t divFactor) +{ + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + pCLK->CLK_CONFIG_REG5_b.CT_CLK_DIV_FAC = (unsigned int)(divFactor & 0x3F); + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_ssi_mst_clk_div(M4CLK_Type *pCLK, uint32_t divFactor) + * @brief This API is used to divide the SSI clock + * @param[in] pCLK : pointer to the processor clock source + * @param[in] divFactor : division factor + * @return RSI_OK on success + */ + +rsi_error_t clk_ssi_mst_clk_div(M4CLK_Type *pCLK, uint32_t divFactor) +{ + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + pCLK->CLK_CONFIG_REG1_b.SSI_MST_SCLK_DIV_FAC = (unsigned int)(divFactor & 0x0F); + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_i2s_clk_div(M4CLK_Type *pCLK, uint32_t divFactor) + * @brief This API is used to divide the I2S clock + * @param[in] pCLK : pointer to the processor clock source + * @param[in] divFactor : division factor + * @return RSI_OK on success + */ + +rsi_error_t clk_i2s_clk_div(M4CLK_Type *pCLK, uint32_t divFactor) +{ + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + pCLK->CLK_CONFIG_REG5_b.I2S_CLK_DIV_FAC = (unsigned int)(divFactor & 0x3F); + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_usart_clk_div(M4CLK_Type *pCLK, EN_USART_T enUsart, boolean_t u8FracDivEn, uint32_t divFactor) + * @brief This API is used to divide the USART/UART clock + * @param[in] pCLK : pointer to the processor clock source + * @param[in] enUsart : enable UART + * @param[in] u8FracDivEn : fractional divison enable + * @param[in] divFactor : division factor + * @return RSI_OK on success + */ + +rsi_error_t clk_usart_clk_div(M4CLK_Type *pCLK, EN_USART_T enUsart, boolean_t u8FracDivEn, uint32_t divFactor) +{ + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + if (enUsart == USART1) { + if (u8FracDivEn) { + pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_FRAC_SEL = 1; + } else { + pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_FRAC_SEL = 0; + } + pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_DIV_FAC = (unsigned int)(divFactor & 0x0F); + } else { + if (u8FracDivEn) { + pCLK->CLK_CONFIG_REG2_b.USART2_SCLK_FRAC_SEL = 1; + } else { + pCLK->CLK_CONFIG_REG2_b.USART2_SCLK_FRAC_SEL = 0; + } + pCLK->CLK_CONFIG_REG2_b.USART2_SCLK_DIV_FAC = (unsigned int)(divFactor & 0x0F); + } + + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_xtal_clk_config(uint8_t xtalPin) + * @brief This API is used to configure the Xtal clock + * @param[in] xtalPin : oscillator pin + * @return RSI_OK on success + */ + +rsi_error_t clk_xtal_clk_config(uint8_t xtalPin) +{ + if (xtalPin > 4) { + return INVALID_PARAMETERS; + } + switch (xtalPin) { + case 1: + MCU_RET->NPSS_GPIO_CNTRL[xtalPin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_MODE = 3; + MCU_RET->NPSS_GPIO_CNTRL[xtalPin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_REN = 1; + break; + //2 + + case 2: + MCU_RET->NPSS_GPIO_CNTRL[xtalPin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_MODE = 4; + MCU_RET->NPSS_GPIO_CNTRL[xtalPin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_REN = 1; + break; + + case 3: + MCU_RET->NPSS_GPIO_CNTRL[xtalPin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_MODE = 5; + MCU_RET->NPSS_GPIO_CNTRL[xtalPin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_REN = 1; + break; + + case 4: + MCU_RET->NPSS_GPIO_CNTRL[xtalPin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_MODE = 6; + MCU_RET->NPSS_GPIO_CNTRL[xtalPin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_REN = 1; + break; + } + // enables the XTAL clock + MCU_AON->MCUAON_GEN_CTRLS_b.XTAL_CLK_FROM_GPIO = 1; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_slp_clk_config(M4CLK_Type *pCLK, SLEEP_CLK_SRC_SEL_T clkSrc) + * @brief This API is used to calibrate the sleep clock + * @param[in] pCLK : pointer to the processor clock source + * @param[in] clkEnable : enable the clock + * @param[in] clkSrc : source clock + * @return RSI_OK on success + */ + +rsi_error_t clk_slp_clk_config(M4CLK_Type *pCLK, SLEEP_CLK_SRC_SEL_T clkSrc) +{ + /*Parameter validation */ + if ((pCLK == NULL) || (clkSrc > SLP_MAX_SEL)) { + return INVALID_PARAMETERS; + } + switch (clkSrc) { + case SLP_ULP_32KHZ_RC_CLK: + /*Enable clock*/ + MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b.MCU_ULP_32KHZ_RC_CLK_EN_b = 1; + pCLK->CLK_CONFIG_REG4_b.SLEEP_CLK_SEL = clkSrc; + break; + case SLP_ULP_32KHZ_XTAL_CLK: + /*Enable clock*/ + /*NOTE: In order to enable the Xtal clk source need to configure the NPSS_GPIO pins + which can be done through clk_xtal_clk_config(uint8_t xtalPin) API i.e we need to call that API first*/ + MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b.MCU_ULP_32KHZ_XTAL_CLK_EN_b = 1; + pCLK->CLK_CONFIG_REG4_b.SLEEP_CLK_SEL = clkSrc; + break; + + case SLP_CLK_GATED: + /* default value i.e, clock is gated*/ + pCLK->CLK_CONFIG_REG4_b.SLEEP_CLK_SEL = clkSrc; + break; + + case SLP_ULP_32KHZ_RO_CLK: + /*Enable clock*/ + MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b.MCU_ULP_32KHZ_RO_CLK_EN_b = 1; + pCLK->CLK_CONFIG_REG4_b.SLEEP_CLK_SEL = clkSrc; + break; + + default: + return INVALID_PARAMETERS; + } + while ((pCLK->PLL_STAT_REG_b.SLEEP_CLK_SWITCHED) != 1) + ; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn uint32_t clk_slp_clk_calib_config(M4CLK_Type *pCLK, uint8_t clkCycles) + * @brief This API is used to calibrate the sleep clock + * @param[in] pCLK : pointer to the processor clock source + * @param[in] clkCycles : clock cycle + * @return pCLK on success + */ + +uint32_t clk_slp_clk_calib_config(M4CLK_Type *pCLK, uint8_t clkCycles) +{ + if (((pCLK == NULL) || (clkCycles > MAX_SLP_CYCLES))) { + return INVALID_PARAMETERS; + } + pCLK->SLEEP_CALIB_REG_b.SLP_CALIB_CYCLES = (unsigned int)(clkCycles & 0x03); + /*Start the sleep clock */ + pCLK->SLEEP_CALIB_REG_b.SLP_CALIB_START_b = 1; + /*wait for calib done*/ + while (pCLK->SLEEP_CALIB_REG_b.SLP_CALIB_DONE_b != 1) + ; + /*Return the value */ + return pCLK->SLEEP_CALIB_REG_b.SLP_CALIB_DURATION_b; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_gspi_clk_config(M4CLK_Type *pCLK, GSPI_CLK_SRC_SEL_T clkSel) + * @brief This API is used to configure the GSPI Clocks + * @param[in] pCLK : pointer to the processor clock source + * @param[in] clkSel : clock select + * @return RSI_OK on success + */ + +rsi_error_t clk_gspi_clk_config(M4CLK_Type *pCLK, GSPI_CLK_SRC_SEL_T clkSel) +{ + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + /*Disable the clocks*/ + pCLK->CLK_CONFIG_REG1_b.GEN_SPI_MST1_SCLK_SEL = 0x07; + /*Without this clk enabled, div_fac and mux select for sclk cannot be programmed) */ + pCLK->CLK_ENABLE_SET_REG2 = GEN_SPI_MST1_HCLK_ENABLE; + + switch (clkSel) { + case GSPI_M4_SOC_CLK_FOR_OTHER_CLKS: + /*M4 SOC Clock for others enable*/ + pCLK->CLK_ENABLE_SET_REG3 = M4_SOC_CLK_FOR_OTHER_ENABLE; + pCLK->CLK_CONFIG_REG1_b.GEN_SPI_MST1_SCLK_SEL = 0x00; + break; + + case GSPI_ULP_REF_CLK: + pCLK->CLK_CONFIG_REG1_b.GEN_SPI_MST1_SCLK_SEL = 0x01; + break; + + case GSPI_SOC_PLL_CLK: + /*Check clock is present is or not before switching*/ + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, SOC_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + pCLK->CLK_CONFIG_REG1_b.GEN_SPI_MST1_SCLK_SEL = 0x02; + break; + + case GSPI_MODEM_PLL_CLK2: + /*Check clock is present is or not before switching*/ + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, MODEM_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + pCLK->CLK_CONFIG_REG1_b.GEN_SPI_MST1_SCLK_SEL = 0x03; + break; + + case GSPI_INTF_PLL_CLK: + /*Check clock is present is or not before switching*/ + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, INTF_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + pCLK->CLK_CONFIG_REG1_b.GEN_SPI_MST1_SCLK_SEL = 0x04; + break; + } + /*Wait for GSPI switched */ + while ((pCLK->PLL_STAT_REG_b.GEN_SPI_MST1_SCLK_SWITCHED) != 1) + ; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_i2c_clk_config(M4CLK_Type *pCLK, boolean_t clkEnable, EN_I2C_T enI2C) + * @brief This API is used to configure the I2C clock + * @param[in] pCLK : pointer to the processor clock source + * @param[in] clkEnable : module for I2C clock + * @param[in] enI2C : enable I2C bus for I2C clock + * @return RSI_OK on success + */ + +rsi_error_t clk_i2c_clk_config(M4CLK_Type *pCLK, boolean_t clkEnable, EN_I2C_T enI2C) +{ + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + if (enI2C == I2C1_INSTAN) { + if (clkEnable) { + /*I2C 1 bus clock enable*/ + pCLK->CLK_ENABLE_SET_REG2 = I2C_BUS_CLK_ENABLE; + /*I2C clk enable */ + pCLK->CLK_ENABLE_SET_REG3 = I2C_CLK_ENABLE; + } else { + /*I2C bus clock disable*/ + pCLK->CLK_ENABLE_CLEAR_REG2 = I2C_BUS_CLK_ENABLE; + /*I2C clk disable */ + pCLK->CLK_ENABLE_CLEAR_REG3 = I2C_CLK_ENABLE; + } + } else { + if (clkEnable) { + /*I2C2 bus clock enable*/ + pCLK->CLK_ENABLE_SET_REG2 = I2C_2_BUS_CLK_ENABLE; + /*I2C2 clk enable */ + pCLK->CLK_ENABLE_SET_REG3 = I2C_2_CLK_ENABLE; + } else { + /*I2C2 bus clock disable*/ + pCLK->CLK_ENABLE_CLEAR_REG2 = I2C_2_BUS_CLK_ENABLE; + /*I2C2 clk disable */ + pCLK->CLK_ENABLE_CLEAR_REG3 = I2C_2_CLK_ENABLE; + } + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_peripheral_clk_enable(M4CLK_Type *pCLK, PERIPHERALS_CLK_T module, CLK_ENABLE_T clkType) + * @brief This API is used to enable the particular clock + * @param[in] pCLK : pointer to the processor clock source + * @param[in] module : module for particular clock + * @param[in] clkType : clock type for particular clock + * @return RSI_OK on success + */ + +rsi_error_t clk_peripheral_clk_enable(M4CLK_Type *pCLK, PERIPHERALS_CLK_T module, CLK_ENABLE_T clkType) +{ + /*valid parameter check*/ + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + switch (module) { + case USART1_CLK: + if (clkType == ENABLE_STATIC_CLK) { + pCLK->CLK_ENABLE_SET_REG1 = (USART1_SCLK_ENABLE | USART1_PCLK_ENABLE); + } else { + pCLK->CLK_ENABLE_CLEAR_REG1 = (USART1_SCLK_ENABLE | USART1_PCLK_ENABLE); + pCLK->DYN_CLK_GATE_DISABLE_REG_b.USART1_SCLK_DYN_CTRL_DISABLE_b = 0; + pCLK->DYN_CLK_GATE_DISABLE_REG_b.USART1_PCLK_DYN_CTRL_DISABLE_b = 0; + } + break; + case USART2_CLK: + if (clkType == ENABLE_STATIC_CLK) { + pCLK->CLK_ENABLE_SET_REG1 = (USART2_SCLK_ENABLE | USART2_PCLK_ENABLE); + } else { + pCLK->CLK_ENABLE_CLEAR_REG1 = (USART2_SCLK_ENABLE | USART2_PCLK_ENABLE); + pCLK->DYN_CLK_GATE_DISABLE_REG_b.USART2_SCLK_DYN_CTRL_DISABLE_b = 0; + pCLK->DYN_CLK_GATE_DISABLE_REG_b.USART2_PCLK_DYN_CTRL_DISABLE_b = 0; + } + break; + case SSIMST_CLK: + pCLK->CLK_ENABLE_SET_REG3 = M4_SOC_CLK_FOR_OTHER_ENABLE; + if (clkType == ENABLE_STATIC_CLK) { + pCLK->CLK_ENABLE_SET_REG2 = (SSI_MST_SCLK_ENABLE | SSI_MST_PCLK_ENABLE); + } else { + pCLK->CLK_ENABLE_CLEAR_REG2 = (SSI_MST_SCLK_ENABLE | SSI_MST_PCLK_ENABLE); + pCLK->DYN_CLK_GATE_DISABLE_REG_b.SSI_MST_SCLK_DYN_CTRL_DISABLE_b = 0; + pCLK->DYN_CLK_GATE_DISABLE_REG_b.SSI_MST_PCLK_DYN_CTRL_DISABLE_b = 0; + } + break; + case SSISLAVE_CLK: + pCLK->CLK_ENABLE_SET_REG3 = M4_SOC_CLK_FOR_OTHER_ENABLE; + if (clkType == ENABLE_STATIC_CLK) { + pCLK->CLK_ENABLE_SET_REG2 = (SSI_SLV_SCLK_ENABLE | SSI_SLV_PCLK_ENABLE); + } else { + pCLK->CLK_ENABLE_CLEAR_REG2 = (SSI_SLV_SCLK_ENABLE | SSI_SLV_PCLK_ENABLE); + pCLK->DYN_CLK_GATE_DISABLE_REG_b.SSI_SLV_SCLK_DYN_CTRL_DISABLE_b = 0; + pCLK->DYN_CLK_GATE_DISABLE_REG_b.SSI_SLV_PCLK_DYN_CTRL_DISABLE_b = 0; + } + break; + + case CT_CLK: + pCLK->CLK_ENABLE_SET_REG1 = CT_CLK_ENABLE; + if (clkType == ENABLE_STATIC_CLK) { + pCLK->CLK_ENABLE_SET_REG1 = CT_PCLK_ENABLE; + } else { + pCLK->CLK_ENABLE_CLEAR_REG1 = CT_PCLK_ENABLE; + pCLK->DYN_CLK_GATE_DISABLE_REG2_b.CT_PCLK_DYN_CTRL_DISABLE_b = 0; + } + break; +#ifndef SLI_SI917 + case SD_MEM_CLK: + pCLK->CLK_ENABLE_SET_REG1 = SD_MEM_INTF_CLK_ENABLE; + break; + + case CCI_CLK: + pCLK->CLK_ENABLE_SET_REG1 = (CCI_CLK_ENABLE | CCI_HCLK_ENABLE); + pCLK->CLK_ENABLE_SET_REG3 = M4_SOC_CLK_FOR_OTHER_ENABLE; + if (clkType == ENABLE_STATIC_CLK) { + pCLK->CLK_ENABLE_SET_REG1 = CCI_PCLK_ENABLE; + } else { + pCLK->CLK_ENABLE_CLEAR_REG1 = CCI_PCLK_ENABLE; + pCLK->DYN_CLK_GATE_DISABLE_REG_b.CCI_PCLK_DYN_CTRL_DISABLE_b = 0; + } + break; + case CAN_CLK: + /*Enable the clock */ + pCLK->CLK_ENABLE_SET_REG2 = CAN1_CLK_ENABLE; + pCLK->CLK_ENABLE_SET_REG3 = M4_SOC_CLK_FOR_OTHER_ENABLE; + if (clkType == ENABLE_STATIC_CLK) { + pCLK->CLK_ENABLE_SET_REG2 = CAN1_PCLK_ENABLE; + } else { + pCLK->CLK_ENABLE_CLEAR_REG2 = CAN1_PCLK_ENABLE; + pCLK->DYN_CLK_GATE_DISABLE_REG2_b.CAN1_PCLK_DYN_CTRL_DISABLE_b = 0; + } + break; +#endif + case QSPI_CLK: + pCLK->CLK_ENABLE_SET_REG2 = (QSPI_CLK_ENABLE | QSPI_HCLK_ENABLE); + pCLK->CLK_ENABLE_SET_REG3 = QSPI_CLK_ONEHOT_ENABLE; + break; +#ifdef SLI_SI917B0 + case QSPI_2_CLK: + pCLK->CLK_ENABLE_SET_REG1 = (QSPI_2_CLK_ENABLE | QSPI_2_HCLK_ENABLE); + pCLK->CLK_ENABLE_SET_REG1 = QSPI_2_CLK_ONEHOT_ENABLE; + break; +#endif + case RPDMA_CLK: + pCLK->CLK_ENABLE_SET_REG1 = RPDMA_HCLK_ENABLE; + break; + case UDMA_CLK: + pCLK->CLK_ENABLE_SET_REG2 = UDMA_HCLK_ENABLE; + break; + case PWM_CLK: + pCLK->CLK_ENABLE_SET_REG2 = MCPWM_PCLK_ENABLE; + break; + case GSPI_CLK: + pCLK->CLK_ENABLE_SET_REG3 = M4_SOC_CLK_FOR_OTHER_ENABLE; + pCLK->CLK_ENABLE_SET_REG2 = GEN_SPI_MST1_HCLK_ENABLE; + break; + case EGPIO_CLK: + pCLK->CLK_ENABLE_SET_REG3 = EGPIO_CLK_ENABLE; + pCLK->CLK_ENABLE_SET_REG2 = EGPIO_PCLK_ENABLE; + break; + case ETHERNET_CLK: + pCLK->CLK_ENABLE_SET_REG3 = M4_SOC_CLK_FOR_OTHER_ENABLE; + pCLK->CLK_ENABLE_SET_REG1 = ETH_HCLK_ENABLE; + break; + case MCUCLKOUT_CLK: + pCLK->CLK_CONFIG_REG3_b.MCU_CLKOUT_ENABLE = 1; + break; + case HWRNG_CLK: + pCLK->CLK_ENABLE_SET_REG1 = HWRNG_PCLK_ENABLE; + break; + case I2SM_CLK: + pCLK->CLK_ENABLE_SET_REG2 = (I2SM_INTF_SCLK_ENABLE | I2SM_SCLK_ENABLE | I2SM_PCLK_ENABLE | I2SM_SCLK_ENABLE); + break; + default: + return INVALID_PARAMETERS; + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_peripheral_clk_disable(M4CLK_Type *pCLK, PERIPHERALS_CLK_T module) + * @brief This API is used to disable the particular clock + * @param[in] pCLK : pointer to the processor clock source + * @param[in] module : module + * @return RSI_OK on success + */ + +rsi_error_t clk_peripheral_clk_disable(M4CLK_Type *pCLK, PERIPHERALS_CLK_T module) +{ + /*valid parameter check*/ + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + switch (module) { + case USART1_CLK: + pCLK->CLK_ENABLE_CLEAR_REG1 = (USART1_SCLK_ENABLE | USART1_PCLK_ENABLE); + pCLK->DYN_CLK_GATE_DISABLE_REG_b.USART1_SCLK_DYN_CTRL_DISABLE_b = 1; + pCLK->DYN_CLK_GATE_DISABLE_REG_b.USART1_PCLK_DYN_CTRL_DISABLE_b = 1; + break; + case USART2_CLK: + pCLK->CLK_ENABLE_CLEAR_REG1 = (USART2_SCLK_ENABLE | USART2_PCLK_ENABLE); + pCLK->DYN_CLK_GATE_DISABLE_REG_b.USART2_SCLK_DYN_CTRL_DISABLE_b = 1; + pCLK->DYN_CLK_GATE_DISABLE_REG_b.USART2_PCLK_DYN_CTRL_DISABLE_b = 1; + break; + case SSIMST_CLK: + pCLK->CLK_ENABLE_CLEAR_REG2 = SSI_MST_SCLK_ENABLE; + pCLK->DYN_CLK_GATE_DISABLE_REG_b.SSI_MST_SCLK_DYN_CTRL_DISABLE_b = 1; + break; + case SSISLAVE_CLK: + pCLK->CLK_ENABLE_CLEAR_REG2 = (SSI_SLV_SCLK_ENABLE | SSI_SLV_PCLK_ENABLE); + pCLK->DYN_CLK_GATE_DISABLE_REG_b.SSI_SLV_SCLK_DYN_CTRL_DISABLE_b = 1; + pCLK->DYN_CLK_GATE_DISABLE_REG_b.SSI_SLV_PCLK_DYN_CTRL_DISABLE_b = 1; + break; + case CT_CLK: + pCLK->CLK_ENABLE_CLEAR_REG1 = CT_CLK_ENABLE; + break; + case SD_MEM_CLK: + pCLK->CLK_ENABLE_CLEAR_REG1 = SD_MEM_INTF_CLK_ENABLE; + break; + case CCI_CLK: + pCLK->CLK_ENABLE_CLEAR_REG1 = CCI_CLK_ENABLE; + pCLK->CLK_ENABLE_CLEAR_REG3 = M4_SOC_CLK_FOR_OTHER_ENABLE; + break; + case QSPI_CLK: + pCLK->CLK_ENABLE_CLEAR_REG2 = QSPI_CLK_ENABLE; + pCLK->CLK_ENABLE_CLEAR_REG3 = (QSPI_CLK_ONEHOT_ENABLE | QSPI_M4_SOC_SYNC); + break; +#ifdef SLI_SI917B0 + case QSPI_2_CLK: + pCLK->CLK_ENABLE_CLEAR_REG1 = QSPI_2_CLK_ENABLE; + pCLK->CLK_ENABLE_CLEAR_REG1 = (QSPI_2_CLK_ONEHOT_ENABLE | QSPI_2_M4_SOC_SYNC); + break; +#endif + case RPDMA_CLK: + pCLK->CLK_ENABLE_CLEAR_REG1 = RPDMA_HCLK_ENABLE; + break; + case UDMA_CLK: + pCLK->CLK_ENABLE_CLEAR_REG2 = UDMA_HCLK_ENABLE; + break; + case PWM_CLK: + pCLK->CLK_ENABLE_CLEAR_REG2 = MCPWM_PCLK_ENABLE; + break; + case CAN_CLK: + pCLK->CLK_ENABLE_CLEAR_REG2 = CAN1_CLK_ENABLE; + break; + case GSPI_CLK: + pCLK->CLK_ENABLE_CLEAR_REG2 = GEN_SPI_MST1_HCLK_ENABLE; + break; + case EGPIO_CLK: + pCLK->CLK_ENABLE_CLEAR_REG2 = EGPIO_PCLK_ENABLE; + pCLK->CLK_ENABLE_CLEAR_REG3 = EGPIO_CLK_ENABLE; + break; + case ETHERNET_CLK: + pCLK->CLK_ENABLE_CLEAR_REG1 = ETH_HCLK_ENABLE; + break; + case MCUCLKOUT_CLK: + pCLK->CLK_CONFIG_REG3_b.MCU_CLKOUT_ENABLE = 0; + break; + case HWRNG_CLK: + pCLK->CLK_ENABLE_CLEAR_REG1 = HWRNG_PCLK_ENABLE; + break; + case I2SM_CLK: +#ifndef SLI_SI917 + pCLK->DYN_CLK_GATE_DISABLE_REG_b.I2SM_INTF_SCLK_DYN_CTRL_DISABLE_b = 1; +#endif + pCLK->CLK_ENABLE_CLEAR_REG2 = (I2SM_INTF_SCLK_ENABLE | I2SM_SCLK_ENABLE); + break; + default: + return INVALID_PARAMETERS; + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn void clk_config_pll_ref_clk(uint8_t ref_clk_src) + * @brief This API is used to Configures the PLL lock configurations + * @param[in] ref_clk_src : reference clock source + * @return none + */ + +void clk_config_pll_ref_clk(uint8_t ref_clk_src) +{ + uint32_t reg_read = 0; + reg_read = SPI_MEM_MAP_PLL(SOCPLLMACROREG2); + reg_read &= (uint16_t)(~((0x3 << 14))); + reg_read |= (ref_clk_src << 14U); + SPI_MEM_MAP_PLL(SOCPLLMACROREG2) = (uint16_t)reg_read; +} +#endif //PLL_ROMDRIVER_PRESENT + +#if !defined(CHIP_9118) || !defined(A11_ROM) || !defined(PLL_ROMDRIVER_PRESENT) + +/*==============================================*/ +/** + * @fn void clk_config_pll_lock(boolean_t manual_lock, boolean_t bypass_manual_lock, uint8_t mm_count_limit) + * @brief This API is used to Configures the PLL lock configurations + * @param[in] manual_clock : manual clock + * @param[in] bypass_manual_clock : bypass manual clock + * @param[in] mm_count_limit : count limit + * @return none + */ + +void clk_config_pll_lock(boolean_t manual_lock, boolean_t bypass_manual_lock, uint8_t mm_count_limit) +{ + uint32_t reg_read = 0; + reg_read = SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG9); + reg_read &= ~((0xFF << 6) | BIT(15) | BIT(14)); + reg_read |= (uint32_t)((manual_lock << 15U) | (bypass_manual_lock << 14U) | (mm_count_limit << 6U)); + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG9) = (uint16_t)reg_read; +} +#endif + +/*==============================================*/ +/** + * @fn uint32_t RSI_CLK_CheckPresent(M4CLK_Type *pCLK ,CLK_PRESENT_T clkPresent) + * @brief This API is used to enable the dynamic clock gate for peripherals + * @param[in] pCLK : Pointer to the pll register instance \ref M4CLK_Type + * @param[in] clkPresent : structure variable of CLK_PRESENT_T , \ref CLK_PRESENT_T + * @return zero on success + * RSI_OK on error error code + * ERROR_CLOCK_NOT_ENABLED + */ + +uint32_t RSI_CLK_CheckPresent(M4CLK_Type *pCLK, CLK_PRESENT_T clkPresent) +{ + uint32_t errorReturn = 0; + switch (clkPresent) { + case SOC_PLL_CLK_PRESENT: + if (pCLK->PLL_STAT_REG_b.SOCPLL_LOCK == 1) { + errorReturn = RSI_OK; + } else { + errorReturn = ERROR_CLOCK_NOT_ENABLED; + } + break; + case INTF_PLL_CLK_PRESENT: + if (pCLK->PLL_STAT_REG_b.INTFPLL_LOCK == 1) { + errorReturn = RSI_OK; + } else { + errorReturn = ERROR_CLOCK_NOT_ENABLED; + } + break; + case I2S_PLL_CLK_PRESENT: + if (pCLK->PLL_STAT_REG_b.I2SPLL_LOCK == 1) { + errorReturn = RSI_OK; + } else { + errorReturn = ERROR_CLOCK_NOT_ENABLED; + } + break; + case MODEM_PLL_CLK_PRESENT: + if (pCLK->PLL_STAT_REG_b.MODEMPLL_LOCK == 1) { + errorReturn = RSI_OK; + } else { + errorReturn = ERROR_CLOCK_NOT_ENABLED; + } + break; + } + return errorReturn; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_m4ss_ref_clk_config(M4CLK_Type *pCLK, M4SS_REF_CLK_SEL_T clkSource) + * @brief This API is used to configure the m4ss_ref clocks + * @param[in] pCLK is pointer to the processor clock source + * @param[in] clkSource is source clock + * @return RSI_OK on success + */ + +rsi_error_t clk_m4ss_ref_clk_config(M4CLK_Type *pCLK, M4SS_REF_CLK_SEL_T clkSource) +{ + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + switch (clkSource) { + case ULP_32MHZ_RC_BYP_CLK: + MCU_FSM->MCU_FSM_REF_CLK_REG_b.M4SS_REF_CLK_SEL = 0x01; + system_clocks.m4_ref_clock_source = ULP_32MHZ_RC_BYP_CLK; + system_clocks.m4ss_ref_clk = system_clocks.byp_rc_ref_clock; + break; + case ULP_32MHZ_RC_CLK: + MCU_FSM->MCU_FSM_REF_CLK_REG_b.M4SS_REF_CLK_SEL = 0x02; + system_clocks.m4_ref_clock_source = ULP_32MHZ_RC_CLK; + system_clocks.m4ss_ref_clk = system_clocks.rc_32mhz_clock; + break; + case RF_REF_CLK: + MCU_FSM->MCU_FSM_REF_CLK_REG_b.M4SS_REF_CLK_SEL = 0x03; + system_clocks.m4_ref_clock_source = RF_REF_CLK; + system_clocks.m4ss_ref_clk = system_clocks.rf_ref_clock; + break; + case MEMS_REF_CLK: + TASS_PLL_CTRL_SET_REG(AFEPLLCTRLREG1) = MEMS_REF_CLK_ENABLE; + MCU_FSM->MCU_FSM_REF_CLK_REG_b.M4SS_REF_CLK_SEL = 0x04; + system_clocks.m4_ref_clock_source = MEMS_REF_CLK; + system_clocks.m4ss_ref_clk = system_clocks.mems_ref_clock; + break; + case ULP_20MHZ_RINGOSC_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_20MHZ_RING_OSC_CLK_EN, ULP_PERIPHERAL_CLK, 0); + MCU_FSM->MCU_FSM_REF_CLK_REG_b.M4SS_REF_CLK_SEL = 0x05; + system_clocks.m4_ref_clock_source = ULP_20MHZ_RINGOSC_CLK; + system_clocks.m4ss_ref_clk = system_clocks.ro_20mhz_clock; + break; + case ULP_DOUBLER_CLK: + /*6: ulp_doubler_clk*/ + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_DOUBLER_CLK_EN, ULP_PERIPHERAL_CLK, 0); + MCU_FSM->MCU_FSM_REF_CLK_REG_b.M4SS_REF_CLK_SEL = 0x06; + system_clocks.m4_ref_clock_source = ULP_DOUBLER_CLK; + system_clocks.m4ss_ref_clk = system_clocks.doubler_clock; + break; + default: + return INVALID_PARAMETERS; + } + /*wait for clock switched*/ + while ((pCLK->PLL_STAT_REG_b.ULP_REF_CLK_SWITCHED) != 1) + ; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t ulpss_disable_ref_clks(REF_CLK_ENABLE_T clk_type) + * @brief This API is used to enable the ULP reference clocks and provide delay for clock starting + * @param[in] clk_Type : clock type + * @return RSI_OK on success + */ + +rsi_error_t ulpss_disable_ref_clks(REF_CLK_ENABLE_T clk_type) +{ + /*Select clock source*/ + switch (clk_type) { + case MCU_ULP_40MHZ_CLK_EN: + /*Cleaners are disabled */ + *(volatile uint32_t *)0x2404811C |= (BIT(7) | BIT(23)); + *(volatile uint32_t *)0x2404811C &= ~(BIT(8) | BIT(24)); /////// API with XTAL Clock disabled /////// + MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b.MCU_ULP_40MHZ_CLK_EN_b = 0; + break; + + case MCU_ULP_DOUBLER_CLK_EN: + MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b.MCU_ULP_DOUBLER_CLK_EN_b = 0; + break; + + case MCU_ULP_20MHZ_RING_OSC_CLK_EN: + MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b.MCU_ULP_20MHZ_RING_OSC_CLK_EN_b = 0; + break; + + case MCU_ULP_32MHZ_RC_CLK_EN: + MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b.MCU_ULP_32MHZ_RC_CLK_EN_b = 0; + break; + + case MCU_ULP_32KHZ_XTAL_CLK_EN: + MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b.MCU_ULP_32KHZ_XTAL_CLK_EN_b = 0; + break; + case MCU_ULP_32KHZ_RO_CLK_EN: + MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b.MCU_ULP_32KHZ_RO_CLK_EN_b = 0; + break; + + case MCU_ULP_32KHZ_RC_CLK_EN: + MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b.MCU_ULP_32KHZ_RC_CLK_EN_b = 0; + break; + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_m4_soc_clk_config(M4CLK_Type *pCLK, M4_SOC_CLK_SRC_SEL_T clkSource, uint32_t divFactor) + * @brief This API is used to configure the m4_soc clocks + * @param[in] pCLK : pointer to the processor clock source + * @param[in] clkSource : source clock + * @param[in] divFactor : division factor + * @return RSI_OK on success + */ + +rsi_error_t clk_m4_soc_clk_config(M4CLK_Type *pCLK, M4_SOC_CLK_SRC_SEL_T clkSource, uint32_t divFactor) +{ + /*check valid parameters*/ + if ((pCLK == NULL) || (divFactor >= SOC_MAX_CLK_DIVISION_FACTOR)) { + return INVALID_PARAMETERS; + } + + /*Added for MCU 100 MHz variant mode setting + * Clock will be max/2 in this mode*/ + if (MCU_RET->CHIP_CONFIG_MCU_READ_b.LIMIT_M4_FREQ_110MHZ_b == 1) { + divFactor = divFactor / 2; + } + /*Selects one of the clock sources for M4 SoC clock*/ + switch (clkSource) { + case M4_ULPREFCLK: + /*Update the clock MUX*/ + pCLK->CLK_CONFIG_REG5_b.M4_SOC_CLK_SEL = clkSource; + SystemCoreClock = system_clocks.m4ss_ref_clk; + break; + + case M4_SOCPLLCLK: + /*Check clock is present is or not before switching*/ + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, SOC_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + /*Update the clock MUX*/ + pCLK->CLK_CONFIG_REG5_b.M4_SOC_CLK_SEL = clkSource; + SystemCoreClock = system_clocks.soc_pll_clock; + break; + + case M4_MODEMPLLCLK1: + /*Check clock is present is or not before switching*/ + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, MODEM_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + /*Update the clock MUX*/ + pCLK->CLK_CONFIG_REG5_b.M4_SOC_CLK_SEL = clkSource; + SystemCoreClock = system_clocks.modem_pll_clock; + break; + + case M4_INTFPLLCLK: + /*Check clock is present is or not before switching*/ + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, INTF_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } /*Update the clock MUX*/ + pCLK->CLK_CONFIG_REG5_b.M4_SOC_CLK_SEL = clkSource; + SystemCoreClock = system_clocks.intf_pll_clock; + break; + + case M4_SLEEPCLK: + /*Check clock is present is or not before switching*/ + if (ULPCLK->M4LP_CTRL_REG_b.ULP_M4_CORE_CLK_ENABLE_b == 1) { + /*Update the clock MUX*/ + pCLK->CLK_CONFIG_REG5_b.M4_SOC_CLK_SEL = clkSource; + } else { + /*If clock is not presented return the error */ + return ERROR_CLOCK_NOT_ENABLED; + } + SystemCoreClock = system_clocks.sleep_clock; + break; + default: + return INVALID_PARAMETERS; + } + /*wait for clock switched*/ + while ((pCLK->PLL_STAT_REG_b.M4_SOC_CLK_SWITCHED) != 1) + ; + /*update the division factor */ + pCLK->CLK_CONFIG_REG5_b.M4_SOC_CLK_DIV_FAC = (unsigned int)(divFactor & 0x3F); + + if (divFactor) { + SystemCoreClock /= divFactor; + } + system_clocks.soc_clock = SystemCoreClock; + return RSI_OK; +} + +#if defined(CHIP_9118) || !defined(A11_ROM) || !defined(PLL_ROMDRIVER_PRESENT) + +/*==============================================*/ +/** + * @fn rsi_error_t clk_usart_clk_config(M4CLK_Type *pCLK, + * CLK_ENABLE_T clkType, + * boolean_t FracDivEn, + * EN_USART_T enUsart, + * USART_CLK_SRC_SEL_T clkSource, + * uint32_t divFactor) + * @brief This API is used to configure the Usart clocks + * @param[in] pCLK : pointer to the processor clock source + * @param[in] clkType : enable the clock + * @param[in] FracDivEn : fractional clock divider + * @param[in] enUsart : used for enable Usart + * @param[in] clkSource: clock source + * @param[in] divFactor : division factor + * @return RSI_OK on success + */ + +rsi_error_t clk_usart_clk_config(M4CLK_Type *pCLK, + CLK_ENABLE_T clkType, + boolean_t FracDivEn, + EN_USART_T enUsart, + USART_CLK_SRC_SEL_T clkSource, + uint32_t divFactor) +{ + + /*Parameter validation */ + if ((pCLK == NULL) || (divFactor > USART_MAX_CLK_DIVISION_FACTOR)) { + return INVALID_PARAMETERS; + } + + /*Disable the USART clock*/ + if (enUsart == USART1) { + RSI_CLK_PeripheralClkDisable(pCLK, USART1_CLK); + } else { + RSI_CLK_PeripheralClkDisable(pCLK, USART2_CLK); + } + /*Select clock MUX*/ + switch (clkSource) { + case USART_ULPREFCLK: + if (enUsart == USART1) { + /*select the MUX for the USART 1*/ + pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_SEL = 0x00; + /*Wait for the clock MUX switch status */ + while ((pCLK->PLL_STAT_REG_b.USART1_SCLK_SWITCHED) != 1) + ; + /*Update the division factor */ + pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_DIV_FAC = (unsigned int)(divFactor & 0x0F); + /*fractional clock divider select */ + if (FracDivEn) { + pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_FRAC_SEL = 0; + } else { + pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_FRAC_SEL = 1; + } + } else if (enUsart == USART2) { + /*select the MUX for the USART 1*/ + pCLK->CLK_CONFIG_REG2_b.USART2_SCLK_SEL = 0x00; + /*Wait for the clock MUX switch status */ + while ((pCLK->PLL_STAT_REG_b.USART2_SCLK_SWITCHED) != 1) + ; + /*fractional clock divider select */ + /*Update the division factor */ + pCLK->CLK_CONFIG_REG2_b.USART2_SCLK_DIV_FAC = (unsigned int)(divFactor & 0x0F); + + if (FracDivEn) { + pCLK->CLK_CONFIG_REG2_b.USART2_SCLK_FRAC_SEL = 0; + } else { + pCLK->CLK_CONFIG_REG2_b.USART2_SCLK_FRAC_SEL = 1; + } + } + break; + + case USART_MODELPLLCLK2: + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, MODEM_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + if (enUsart == USART1) { + /*select the MUX for the USART 1*/ + pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_SEL = 0x02; + /*Wait for the clock MUX switch status */ + while ((pCLK->PLL_STAT_REG_b.USART1_SCLK_SWITCHED) != 1) + ; + /*Update the division factor */ + pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_DIV_FAC = (unsigned int)(divFactor & 0x0F); + /*fractional clock divider select */ + if (FracDivEn) { + pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_FRAC_SEL = 0; + } else { + pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_FRAC_SEL = 1; + } + } else if (enUsart == USART2) { + /*select the MUX for the USART 1*/ + pCLK->CLK_CONFIG_REG2_b.USART2_SCLK_SEL = 0x02; + /*Wait for the clock MUX switch status */ + while ((pCLK->PLL_STAT_REG_b.USART2_SCLK_SWITCHED) != 1) + ; + /*fractional clock divider select */ + /*Update the division factor */ + pCLK->CLK_CONFIG_REG2_b.USART2_SCLK_DIV_FAC = (unsigned int)(divFactor & 0x0F); + if (FracDivEn) { + pCLK->CLK_CONFIG_REG2_b.USART2_SCLK_FRAC_SEL = 0; + } else { + pCLK->CLK_CONFIG_REG2_b.USART2_SCLK_FRAC_SEL = 1; + } + } + break; + + case USART_INTFPLLCLK: + /*Check clock is present is or not before switching*/ + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, INTF_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + if (enUsart == USART1) { + /*select the MUX for the USART 1*/ + pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_SEL = 0x03; + /*Wait for the clock MUX switch status */ + while ((pCLK->PLL_STAT_REG_b.USART1_SCLK_SWITCHED) != 1) + ; + /*fractional clock divider select */ + /*Update the division factor */ + pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_DIV_FAC = (unsigned int)(divFactor & 0x0F); + if (FracDivEn) { + pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_FRAC_SEL = 0; + } else { + pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_FRAC_SEL = 1; + } + } else if (enUsart == USART2) { + /*select the MUX for the USART 1*/ + pCLK->CLK_CONFIG_REG2_b.USART2_SCLK_SEL = 0x03; + /*Wait for the clock MUX switch status */ + while ((pCLK->PLL_STAT_REG_b.USART2_SCLK_SWITCHED) != 1) + ; + /*Update the division factor */ + pCLK->CLK_CONFIG_REG2_b.USART2_SCLK_DIV_FAC = (unsigned int)(divFactor & 0x0F); + + /*fractional clock divider select */ + if (FracDivEn) { + pCLK->CLK_CONFIG_REG2_b.USART2_SCLK_FRAC_SEL = 0; + } else { + pCLK->CLK_CONFIG_REG2_b.USART2_SCLK_FRAC_SEL = 1; + } + } + break; + + case USART_SOCPLLCLK: + /*Check clock is present is or not before switching*/ + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, SOC_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + if (enUsart == USART1) { + /*select the MUX for the USART 1*/ + pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_SEL = 0x01; + /*Wait for the clock MUX switch status */ + while ((pCLK->PLL_STAT_REG_b.USART1_SCLK_SWITCHED) != 1) + ; + /*Update the division factor */ + pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_DIV_FAC = (unsigned int)(divFactor & 0x0F); + /*fractional clock divider select */ + if (FracDivEn) { + pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_FRAC_SEL = 0; + } else { + pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_FRAC_SEL = 1; + } + } else if (enUsart == USART2) { + /*select the MUX for the USART 1*/ + pCLK->CLK_CONFIG_REG2_b.USART2_SCLK_SEL = 0x01; + /*Wait for the clock MUX switch status */ + while ((pCLK->PLL_STAT_REG_b.USART2_SCLK_SWITCHED) != 1) + ; + /*Update the division factor */ + pCLK->CLK_CONFIG_REG2_b.USART2_SCLK_DIV_FAC = (unsigned int)(divFactor & 0x0F); + /*fractional clock divider select */ + if (FracDivEn) { + pCLK->CLK_CONFIG_REG2_b.USART2_SCLK_FRAC_SEL = 0; + } else { + pCLK->CLK_CONFIG_REG2_b.USART2_SCLK_FRAC_SEL = 1; + } + } + break; + + case M4_SOCCLKFOROTHERCLOCKS: + + if (enUsart == USART1) { + /*select the MUX for the USART 1*/ + pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_SEL = 0x04; + pCLK->CLK_ENABLE_SET_REG3 = M4_SOC_CLK_FOR_OTHER_ENABLE; + /*Wait for the clock MUX switch status */ + while ((pCLK->PLL_STAT_REG_b.USART1_SCLK_SWITCHED) != 1) + ; + /*Update the division factor */ + pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_DIV_FAC = (unsigned int)(divFactor & 0x0F); + /*fractional clock divider select */ + if (FracDivEn) { + pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_FRAC_SEL = 0; + } else { + pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_FRAC_SEL = 1; + } + } else if (enUsart == USART2) { + /*select the MUX for the USART 1*/ + pCLK->CLK_CONFIG_REG2_b.USART2_SCLK_SEL = 0x04; + pCLK->CLK_ENABLE_SET_REG3 = M4_SOC_CLK_FOR_OTHER_ENABLE; + /*Wait for the clock MUX switch status */ + while ((pCLK->PLL_STAT_REG_b.USART2_SCLK_SWITCHED) != 1) + ; + /*Update the division factor */ + pCLK->CLK_CONFIG_REG2_b.USART2_SCLK_DIV_FAC = (unsigned int)(divFactor & 0x0F); + /*fractional clock divider select */ + if (FracDivEn) { + pCLK->CLK_CONFIG_REG2_b.USART2_SCLK_FRAC_SEL = 0; + } else { + pCLK->CLK_CONFIG_REG2_b.USART2_SCLK_FRAC_SEL = 1; + } + } + break; + default: + return INVALID_PARAMETERS; + } + /*Enable USART clock */ + if (enUsart == USART1) { + RSI_CLK_PeripheralClkEnable(pCLK, USART1_CLK, clkType); + } else { + RSI_CLK_PeripheralClkEnable(pCLK, USART2_CLK, clkType); + } + return RSI_OK; +} +#endif + +/*==============================================*/ +/** +* @fn rsi_error_t ulpss_enable_ref_clks(REF_CLK_ENABLE_T enable, SRC_TYPE_T srcType, cdDelay delayFn) +* @brief This API is used to enable the ULP reference clocks and provide delay for clock starting +* @param[in] enable : enable +* @param[in] srcType : source type +* @param[in] delayFn : delay function +* @return RSI_OK on success +*/ + +rsi_error_t ulpss_enable_ref_clks(REF_CLK_ENABLE_T enable, SRC_TYPE_T srcType, cdDelay delayFn) +{ + /*Select clock source*/ + switch (enable) { + case MCU_ULP_40MHZ_CLK_EN: + if (MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b.MCU_ULP_40MHZ_CLK_EN_b == 1) { + /*Clock is enabled by default*/ + /*Do Nothing*/ + } else { + /*Enable the clock source */ + MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b.MCU_ULP_40MHZ_CLK_EN_b = 1; + } + /*Wait for the time out only in case of ULP processor clock configuration */ + if (srcType == ULP_PROCESSOR_CLK) { + /*wait for clock source is enabled*/ + _usdelay(MCU_ULP_40MHZ_CLK_EN_TRUN_ON_DELAY, delayFn); + } + /*Cleaners are Enabled */ + *(volatile uint32_t *)0x2404811C &= ~(BIT(7) | BIT(23)); /////// API with XTAL Clock disabled /////// + *(volatile uint32_t *)0x2404811C |= (BIT(8) | BIT(24)); /////// API with XTAL Clock disabled /////// + break; + case MCU_ULP_DOUBLER_CLK_EN: + if (MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b.MCU_ULP_DOUBLER_CLK_EN_b == 1) { + /*Clock is enabled by default*/ + /*Do Nothing*/ + } else { + /*NOTE : 320Mhz RC is interdependent on Doubler clock*/ + MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b.MCU_ULP_20MHZ_RING_OSC_CLK_EN_b = 1; + /*Enable the clock source */ + MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b.MCU_ULP_DOUBLER_CLK_EN_b = 1; + } + if (srcType == ULP_PROCESSOR_CLK) { + /*wait for clock source is enabled*/ + _usdelay(MCU_ULP_DOUBLER_CLK_EN_TRUN_ON_DELAY, delayFn); + } + break; + + case MCU_ULP_20MHZ_RING_OSC_CLK_EN: + if (MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b.MCU_ULP_20MHZ_RING_OSC_CLK_EN_b == 1) { + /*Clock is enabled by default*/ + /*Do Nothing*/ + } else { + /*Enable the clock source */ + MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b.MCU_ULP_20MHZ_RING_OSC_CLK_EN_b = 1; + } + if (srcType == ULP_PROCESSOR_CLK) { + /*wait for clock source is enabled*/ + _usdelay(MCU_ULP_20MHZ_RING_OSC_CLK_EN_TRUN_ON_DELAY, delayFn); + } + break; + case MCU_ULP_32MHZ_RC_CLK_EN: + if (MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b.MCU_ULP_32MHZ_RC_CLK_EN_b == 1) { + /*Clock is enabled by default*/ + /*Do Nothing*/ + } else { + /*Enable the clock*/ + MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b.MCU_ULP_32MHZ_RC_CLK_EN_b = 1; + } + if (srcType == ULP_PROCESSOR_CLK) { + /*wait for clock source is enabled*/ + _usdelay(MCU_ULP_32MHZ_RC_CLK_EN_TRUN_ON_DELAY, delayFn); + } + break; + case MCU_ULP_32KHZ_XTAL_CLK_EN: + if (MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b.MCU_ULP_32KHZ_XTAL_CLK_EN_b == 1) { + /*Clock is enabled by default*/ + /*Do Nothing*/ + } else { + /*Program the IPMU structure*/ + //RSI_IPMU_ProgramConfigData(xtal1_khz_fast_start_en); + + /*Enable the clock source from NPSS*/ + MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b.MCU_ULP_32KHZ_XTAL_CLK_EN_b = 1; + + /*Wait for 0.5 sec delay*/ + _usdelay(MCU_ULP_32KHZ_XTAL_CLK_EN_TRUN_ON_DELAY_1, delayFn); + + /*Program the IPMU structure*/ + // RSI_IPMU_ProgramConfigData(xtal1_khz_fast_start_disable); + + /*wait for clock source is enabled for 1.5sec*/ + _usdelay(MCU_ULP_32KHZ_XTAL_CLK_EN_TRUN_ON_DELAY_2, delayFn); + } + break; + + case MCU_ULP_32KHZ_RO_CLK_EN: + if (MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b.MCU_ULP_32KHZ_RO_CLK_EN_b == 1) { + /*Clock is enabled by default*/ + /*Do Nothing*/ + } else { + /*Enable the clock source */ + MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b.MCU_ULP_32KHZ_RO_CLK_EN_b = 1; + } + if (srcType == ULP_PROCESSOR_CLK) { + /*wait for clock source is enabled*/ + _usdelay(MCU_ULP_32KHZ_RO_CLK_EN_TRUN_ON_DELAY, delayFn); + } + break; + case MCU_ULP_32KHZ_RC_CLK_EN: + if (MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b.MCU_ULP_32KHZ_RC_CLK_EN_b == 1) { + /*Clock is enabled by default*/ + /*Do Nothing*/ + } else { + /*Enable the clock source */ + MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b.MCU_ULP_32KHZ_RC_CLK_EN_b = 1; + } + if (srcType == ULP_PROCESSOR_CLK) { + /*wait for clock source is enabled*/ + _usdelay(MCU_ULP_32KHZ_RC_CLK_EN_TRUN_ON_DELAY, delayFn); + } + break; + } + return RSI_OK; +} +/** @} */ + +/* ROM API Structure +const ROM_M4SS_CLK_API_T m4ssclk_api = { + &clk_check_pll_lock, + &clk_soc_pll_clk_enable, + &clk_set_soc_pll_freq, + &clk_soc_pll_set_freq_div, + &clk_soc_pll_clk_set, + &clk_soc_pll_clk_bypass_enable, + &clk_soc_pll_clk_reset, + &clk_soc_pll_pd_enable, + &clk_soc_pll_turn_off, + &clk_soc_pll_turn_on, + &clk_i2s_pll_clk_enable, + &clk_i2s_pll_clk_bypass_enable, + &clk_i2s_pll_pd_enable, + &clk_i2s_pll_turn_off, + &clk_i2s_pll_turn_on, + &clk_set_i2s_pll_freq, + &clk_i2s_pll_set_freq_div, + &clk_i2s_pll_clk_set, + &clk_i2s_pll_clk_reset, + &clk_intf_pll_clk_enable, + &clk_intf_pll_pd_enable, + &clk_intf_pll_turn_off, + &clk_set_intf_pll_freq, + &clk_intf_pll_set_freq_div, + &clk_intf_pll_clk_bypass_enable, + &clk_intf_pll_turn_on, + &clk_intf_pll_clk_reset, + &clk_intf_pll_clk_set, + &clk_peripheral_clk_enable1, + &clk_peripheral_clk_disable1, + &clk_peripheral_clk_enable2, + &clk_peripheral_clk_disable2, + &clk_peripheral_clk_enable3, + &clk_peripheral_clk_disable3, + &clk_dynamic_clk_gate_disable, + &clk_dynamic_clk_gate_disable2, + &clk_dynamic_clk_gate_enable, + &clk_dynamic_clk_gate_enable2, + &ulpss_enable_ref_clks, + &ulpss_disable_ref_clks, + &clk_qspi_clk_config, + &clk_usart_clk_config, + &clk_ssi_mst_clk_config, + #ifndef SLI_SI917 + &clk_sd_mem_clk_config, + #endif + &clk_ct_clk_config, + #ifndef SLI_SI917 + &clk_cci_clk_config, + #endif + &clk_i2s_clk_config, + &clk_mcu_clk_cut_config, + #ifndef SLI_SI917 + &clk_can_clk_config, + &clk_ethernet_clk_config, + #endif + &clk_m4_soc_clk_div, + &clk_qspi_clk_div, + &clk_ct_clk_div, + &clk_ssi_mst_clk_div, + &clk_cci_clk_div, + &clk_i2s_clk_div, + #ifndef SLI_SI917 + &clk_sd_mem_clk_div, + #endif + &clk_usart_clk_div, + &clk_slp_clk_calib_config, + &clk_gspi_clk_config, + &clk_slp_clk_config, + &clk_i2c_clk_config, + &clk_xtal_clk_config, + &clk_usb_clk_config, + &clk_peripheral_clk_enable, + &clk_peripheral_clk_disable, + &clk_config_pll_lock, + &clk_config_pll_ref_clk, +}; +*/ + +/*End of file not truncated*/ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_ulpss_clk.c b/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_ulpss_clk.c new file mode 100644 index 000000000..cbfe748b8 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_ulpss_clk.c @@ -0,0 +1,1180 @@ +/******************************************************************************* +* @file rsi_ulpss_clk.c +* @brief +******************************************************************************* +* # License +* Copyright 2020 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ +/************************************************************************* + * + */ + +// Includes + +#include "rsi_ccp_user_config.h" +#include "rsi_rom_ulpss_clk.h" +#ifndef ULPSS_CLOCK_ROMDRIVER_PRESENT +/** @addtogroup SOC3 +* @{ +*/ +/*==============================================*/ +/** + * @fn rsi_error_t ulpss_clock_config(M4CLK_Type *pCLK, boolean_t clkEnable, uint16_t divFactor, boolean_t oddDivFactor) + * @brief This API is used to select the ULPSS processor clock source when input is soc clk source which is greater than 100MHz + * @param[in] pCLK : pointer to the processor clock source + * @param[in] clkEnable : clock enable for clock source + * @param[in] divFactor : division factor for clock to configure Reg 4 + * @param[in] oddDivFactor : odd divison factor for clock to configure Reg 5 + * @return RSI_OK on success + */ + +rsi_error_t ulpss_clock_config(M4CLK_Type *pCLK, boolean_t clkEnable, uint16_t divFactor, boolean_t oddDivFactor) +{ + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + if (clkEnable == Enable) { + pCLK->CLK_CONFIG_REG4_b.ULPSS_CLK_DIV_FAC = (unsigned int)(divFactor & 0x3F); + pCLK->CLK_CONFIG_REG5_b.ULPSS_ODD_DIV_SEL = (unsigned int)(oddDivFactor & 0x01); + pCLK->CLK_ENABLE_SET_REG1 = ULPSS_CLK_ENABLE; + } else { + pCLK->CLK_ENABLE_CLEAR_REG1 = ULPSS_CLK_ENABLE; + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t ulpss_ulp_peri_clk_enable(ULPCLK_Type *pULPCLK, uint32_t u32Flags) + * @brief This API is used to enable different peripherial clocks in ULPSS + * @param[in] pULPCLK : pointer to the processor ULP clock + * @param[in] u32Flags : flags for perpheral clocks + * @return RSI_OK on success + */ + +rsi_error_t ulpss_ulp_peri_clk_enable(ULPCLK_Type *pULPCLK, uint32_t u32Flags) +{ + if (pULPCLK == NULL) { + return INVALID_PARAMETERS; + } + pULPCLK->ULP_MISC_SOFT_SET_REG = (pULPCLK->ULP_MISC_SOFT_SET_REG | u32Flags) & 0xFFFFFFFF; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t ulpss_ulp_peri_clk_disable(ULPCLK_Type *pULPCLK, uint32_t u32Flags) + * @brief This API is used to disable different peripherial clocks in ULPSS + * @param[in] pULPCLK : pointer to the processor ULP clock source + * @param[in] u32Flags : flags for peripheral clocks + * @return RSI_OK on success + */ + +rsi_error_t ulpss_ulp_peri_clk_disable(ULPCLK_Type *pULPCLK, uint32_t u32Flags) +{ + if (pULPCLK == NULL) { + return INVALID_PARAMETERS; + } + pULPCLK->ULP_MISC_SOFT_SET_REG = (pULPCLK->ULP_MISC_SOFT_SET_REG & ~u32Flags) & 0xFFFFFFFF; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t ulpss_ulp_dyn_clk_enable(ULPCLK_Type *pULPCLK, uint32_t u32Flags) + * @brief This API is used to enable different dynamic clocks in ULPSS + * @param[in] pULPCLK : pointer to the processor ULP clock source + * @param[in] u32Flags : flags for dynamic clocks + * @return RSI_OK on success + */ + +rsi_error_t ulpss_ulp_dyn_clk_enable(ULPCLK_Type *pULPCLK, uint32_t u32Flags) +{ + if (pULPCLK == NULL) { + return INVALID_PARAMETERS; + } + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE = (pULPCLK->ULP_DYN_CLK_CTRL_DISABLE | u32Flags) & 0xFFFFFFFF; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t ulpss_ulp_dyn_clk_disable(ULPCLK_Type *pULPCLK, uint32_t u32Flags) + * @brief This API is used to disable different dynamic clocks in ULPSS + * @param[in] pULPCLK : pointer to the processor ULP clock source + * @param[in] u32Flags : flags for dynamic clocks + * @return RSI_OK on success + */ + +rsi_error_t ulpss_ulp_dyn_clk_disable(ULPCLK_Type *pULPCLK, uint32_t u32Flags) +{ + if (pULPCLK == NULL) { + return INVALID_PARAMETERS; + } + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE = (pULPCLK->ULP_DYN_CLK_CTRL_DISABLE & ~u32Flags) & 0xFFFFFFFF; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t ulpss_ulp_ssi_clk_config(ULPCLK_Type *pULPCLK, + * CLK_ENABLE_T clkType, + * ULP_SSI_CLK_SELECT_T clkSource, + * uint16_t divFactor) + * @brief This API is used to configure the SSI clock source + * @param[in] pULPCLK : pointer to the processor ULP clock source + * @param[in] clkType : clock type for SSI clock source + * @param[in] clkSource : clock source for ULP SSI + * @param[in] divFactor : divison factor for ULP SSI + * @return RSI_OK on success + */ + +rsi_error_t ulpss_ulp_ssi_clk_config(ULPCLK_Type *pULPCLK, + CLK_ENABLE_T clkType, + ULP_SSI_CLK_SELECT_T clkSource, + uint16_t divFactor) +{ + /*Parameter validation */ + if ((pULPCLK == NULL) || (divFactor > ULP_SSI_MAX_DIVISION_FACTOR) || (clkSource > ULP_SSI_MAX_SEL)) { + return INVALID_PARAMETERS; + } + + ulpss_peripheral_disable(pULPCLK, ULP_SSI_CLK); + /*Select */ + switch (clkSource) { + /*0: ref_clk (output of dynamic clock MUX for different possible ref_clk sources)*/ + case ULP_SSI_REF_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_40MHZ_CLK_EN, ULP_PERIPHERAL_CLK, 0); + /*Select clock MUX */ + pULPCLK->ULP_I2C_SSI_CLK_GEN_REG_b.ULP_SSI_CLK_SEL = clkSource; + break; + /*1: ulp_32khz_ro_clk */ + case ULP_SSI_ULP_32KHZ_RO_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_32KHZ_RO_CLK_EN, ULP_PERIPHERAL_CLK, 0); + /*Select clock MUX */ + pULPCLK->ULP_I2C_SSI_CLK_GEN_REG_b.ULP_SSI_CLK_SEL = clkSource; + break; + /*2: ulp_32khz_rc_clk*/ + case ULP_SSI_ULP_32KHZ_RC_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_32KHZ_RC_CLK_EN, ULP_PERIPHERAL_CLK, 0); + /*Select clock MUX */ + pULPCLK->ULP_I2C_SSI_CLK_GEN_REG_b.ULP_SSI_CLK_SEL = clkSource; + break; + /*3: ulp_32khz_xtal_clk*/ + case ULP_SSI_ULP_32KHZ_XTAL_CLK: + /*Enable clock*/ + /*NOTE: In order to enable the Xtal clk source need to configure the NPSS_GPIO pins + which can be done through clk_xtal_clk_config(uint8_t xtalPin) API i.e we need to call that API first*/ + ulpss_enable_ref_clks(MCU_ULP_32KHZ_XTAL_CLK_EN, ULP_PERIPHERAL_CLK, 0); + pULPCLK->ULP_I2C_SSI_CLK_GEN_REG_b.ULP_SSI_CLK_SEL = clkSource; + break; + /*4: ulp_32mhz_rc_clk*/ + case ULP_SSI_ULP_32MHZ_RC_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_32MHZ_RC_CLK_EN, ULP_PERIPHERAL_CLK, 0); + /*Select clock MUX */ + pULPCLK->ULP_I2C_SSI_CLK_GEN_REG_b.ULP_SSI_CLK_SEL = clkSource; + break; + /*5: ulp_20mhz_ro_clk*/ + case ULP_SSI_ULP_20MHZ_RO_CLK: + ulpss_enable_ref_clks(MCU_ULP_20MHZ_RING_OSC_CLK_EN, ULP_PERIPHERAL_CLK, 0); + /*Select clock MUX */ + pULPCLK->ULP_I2C_SSI_CLK_GEN_REG_b.ULP_SSI_CLK_SEL = clkSource; + break; + case ULP_SSI_SOC_CLK: + /*6: soc_clk*/ + pULPCLK->ULP_I2C_SSI_CLK_GEN_REG_b.ULP_SSI_CLK_SEL = clkSource; + break; + + default: + return INVALID_PARAMETERS; + } + + /*Wait for clock switched */ + while ((pULPCLK->CLOCK_STAUS_REG_b.CLOCK_SWITCHED_SSI_b != 1)) + ; + + /*Update the division factor */ + pULPCLK->ULP_I2C_SSI_CLK_GEN_REG_b.ULP_SSI_CLK_DIV_FACTOR = (unsigned int)(divFactor & 0x7F); + + ulpss_peripheral_enable(pULPCLK, ULP_SSI_CLK, clkType); + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t ulpss_ulp_i2s_clk_config(ULPCLK_Type *pULPCLK, ULP_I2S_CLK_SELECT_T clkSource, uint16_t divFactor) + * @brief This API is used to configure the I2S clock source + * @param[in] pULPCLK : pointer to the processor ULP clock source + * @param[in] clkType : clock type for ULP I2S + * @param[in] clkSource : clock source for ULP I2S + * @param[in] divFactor : divison factor for ULP I2S + * @return RSI_OK on success + */ + +rsi_error_t ulpss_ulp_i2s_clk_config(ULPCLK_Type *pULPCLK, ULP_I2S_CLK_SELECT_T clkSource, uint16_t divFactor) +{ + /*Parameter validation */ + if ((pULPCLK == NULL) || (divFactor > ULP_I2S_MAX_DIVISION_FACTOR) || (clkSource > ULP_I2S_MAX_SEL)) { + return INVALID_PARAMETERS; + } + ulpss_peripheral_disable(pULPCLK, ULP_I2S_CLK); + /*Select */ + switch (clkSource) { + /*0: ref_clk (output of dynamic clock MUX for different possible ref_clk sources)*/ + case ULP_I2S_REF_CLK: + /*Select clock MUX */ + pULPCLK->ULP_I2S_CLK_GEN_REG_b.ULP_I2S_CLK_SEL_b = clkSource; + break; + /*1: ulp_32khz_ro_clk */ + case ULP_I2S_ULP_32KHZ_RO_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_32KHZ_RO_CLK_EN, ULP_PERIPHERAL_CLK, 0); + /*Select clock MUX */ + pULPCLK->ULP_I2S_CLK_GEN_REG_b.ULP_I2S_CLK_SEL_b = clkSource; + break; + /*2: ulp_32khz_rc_clk*/ + case ULP_I2S_ULP_32KHZ_RC_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_32KHZ_RC_CLK_EN, ULP_PERIPHERAL_CLK, 0); + /*Select clock MUX */ + pULPCLK->ULP_I2S_CLK_GEN_REG_b.ULP_I2S_CLK_SEL_b = clkSource; + break; + /*3: ulp_32khz_xtal_clk*/ + case ULP_I2S_ULP_32KHZ_XTAL_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_32KHZ_XTAL_CLK_EN, ULP_PERIPHERAL_CLK, 0); + pULPCLK->ULP_I2S_CLK_GEN_REG_b.ULP_I2S_CLK_SEL_b = clkSource; + break; + /*4: ulp_32mhz_rc_clk*/ + case ULP_I2S_ULP_32MHZ_RC_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_32MHZ_RC_CLK_EN, ULP_PERIPHERAL_CLK, 0); + /*Select clock MUX */ + pULPCLK->ULP_I2S_CLK_GEN_REG_b.ULP_I2S_CLK_SEL_b = clkSource; + break; + /*5: ulp_20mhz_ro_clk*/ + case ULP_I2S_ULP_20MHZ_RO_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_20MHZ_RING_OSC_CLK_EN, ULP_PERIPHERAL_CLK, 0); + /*Select clock MUX */ + pULPCLK->ULP_I2S_CLK_GEN_REG_b.ULP_I2S_CLK_SEL_b = clkSource; + break; + case ULP_I2S_SOC_CLK: + /*6: soc_clk*/ + pULPCLK->ULP_I2S_CLK_GEN_REG_b.ULP_I2S_CLK_SEL_b = clkSource; + break; + case ULP_I2S_ULP_DOUBLER_CLK: + /*7: ulp_doubler_clk*/ + ulpss_enable_ref_clks(MCU_ULP_DOUBLER_CLK_EN, ULP_PERIPHERAL_CLK, 0); + /*Select clock MUX */ + pULPCLK->ULP_I2S_CLK_GEN_REG_b.ULP_I2S_CLK_SEL_b = clkSource; + break; + + case ULP_I2S_PLL_CLK: + /*I2s clock*/ + if (M4CLK->PLL_STAT_REG_b.I2SPLL_LOCK == 0) { + return ERROR_CLOCK_NOT_ENABLED; + } + /*NOTE: this clock source is not valid in PS2 state. PLL is turned off in PS2*/ + M4CLK->CLK_CONFIG_REG5_b.I2S_CLK_SEL = 0; + /*Select clock MUX */ + pULPCLK->ULP_I2S_CLK_GEN_REG_b.ULP_I2S_CLK_SEL_b = clkSource; + break; + default: + return INVALID_PARAMETERS; + } + + /*Wait for clock switched */ + while ((pULPCLK->CLOCK_STAUS_REG_b.CLOCK_SWITCHED_I2S_CLK_b != 1U)) + ; + + /*Set the division factor */ + pULPCLK->ULP_I2S_CLK_GEN_REG_b.ULP_I2S_CLKDIV_FACTOR = (uint8_t)divFactor; + + ulpss_peripheral_enable(pULPCLK, ULP_I2S_CLK, ENABLE_STATIC_CLK); + + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t ulpss_ulp_uar_clk_config(ULPCLK_Type *pULPCLK, + * CLK_ENABLE_T clkType, + * boolean_t bFrClkSel, + * ULP_UART_CLK_SELECT_T clkSource, + * uint16_t divFactor) + * @brief This API is used to configure the UART clock source + * @param[in] pULPCLK : pointer to the processor ULP clock source + * @param[in] clkType : clock type for UART + * @param[in] bFrClkSel : fractional clock select for ULP UART + * @param[in] clkSource : clock source for ULP UART + * @param[in] divFactor : divison factor for ULP UART + * @return RSI_OK on success + */ + +rsi_error_t ulpss_ulp_uar_clk_config(ULPCLK_Type *pULPCLK, + CLK_ENABLE_T clkType, + boolean_t bFrClkSel, + ULP_UART_CLK_SELECT_T clkSource, + uint16_t divFactor) +{ + /*Parameter validation */ + if ((pULPCLK == NULL) || (divFactor > ULP_UART_MAX_DIVISION_FACTOR) || (clkSource > ULP_UART_MAX_SEL)) { + return INVALID_PARAMETERS; + } + ulpss_peripheral_disable(pULPCLK, ULP_UART_CLK); + /*UART Fractional clock select */ + pULPCLK->ULP_UART_CLK_GEN_REG_b.ULP_UART_FRAC_CLK_SEL_b = (unsigned int)(bFrClkSel & 0x01); + + /*Select */ + switch (clkSource) { + /*0: ref_clk (output of dynamic clock MUX for different possible ref_clk sources)*/ + case ULP_UART_REF_CLK: + /*Configure the ULPSS reference clock from NPSS clock MUX this is common for all these Sources */ + /*Select clock MUX */ + pULPCLK->ULP_UART_CLK_GEN_REG_b.ULP_UART_CLK_SEL = clkSource; + break; + /*1: ulp_32khz_ro_clk */ + case ULP_UART_ULP_32KHZ_RO_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_32KHZ_RO_CLK_EN, ULP_PERIPHERAL_CLK, 0); + /*Select clock MUX */ + pULPCLK->ULP_UART_CLK_GEN_REG_b.ULP_UART_CLK_SEL = clkSource; + break; + /*2: ulp_32khz_rc_clk*/ + case ULP_UART_ULP_32KHZ_RC_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_32KHZ_RC_CLK_EN, ULP_PERIPHERAL_CLK, 0); + /*Select clock MUX */ + pULPCLK->ULP_UART_CLK_GEN_REG_b.ULP_UART_CLK_SEL = clkSource; + break; + /*3: ulp_32khz_xtal_clk*/ + case ULP_UART_ULP_32KHZ_XTAL_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_32KHZ_XTAL_CLK_EN, ULP_PERIPHERAL_CLK, 0); + pULPCLK->ULP_UART_CLK_GEN_REG_b.ULP_UART_CLK_SEL = clkSource; + break; + /*4: ulp_32mhz_rc_clk*/ + case ULP_UART_ULP_32MHZ_RC_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_32MHZ_RC_CLK_EN, ULP_PERIPHERAL_CLK, 0); + /*Select clock MUX */ + pULPCLK->ULP_UART_CLK_GEN_REG_b.ULP_UART_CLK_SEL = clkSource; + break; + /*5: ulp_20mhz_ro_clk*/ + case ULP_UART_ULP_20MHZ_RO_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_20MHZ_RING_OSC_CLK_EN, ULP_PERIPHERAL_CLK, 0); + /*Select clock MUX */ + pULPCLK->ULP_UART_CLK_GEN_REG_b.ULP_UART_CLK_SEL = clkSource; + break; + case ULP_UART_SOC_CLK: + /*6: soc_clk*/ + pULPCLK->ULP_UART_CLK_GEN_REG_b.ULP_UART_CLK_SEL = clkSource; + break; + case ULP_UART_ULP_DOUBLER_CLK: + /*7: ulp_doubler_clk*/ + ulpss_enable_ref_clks(MCU_ULP_DOUBLER_CLK_EN, ULP_PERIPHERAL_CLK, 0); + /*Select clock MUX */ + pULPCLK->ULP_UART_CLK_GEN_REG_b.ULP_UART_CLK_SEL = clkSource; + break; + default: + return INVALID_PARAMETERS; + } + + /*Wait for clock switched */ + while ((pULPCLK->CLOCK_STAUS_REG_b.CLOCK_SWITCHED_UART_CLK_b != 1U)) + ; + + pULPCLK->ULP_UART_CLK_GEN_REG_b.ULP_UART_CLKDIV_FACTOR = (unsigned int)(divFactor & 0x07); + + ulpss_peripheral_enable(pULPCLK, ULP_UART_CLK, clkType); + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t ulpss_time_clk_config(ULPCLK_Type *pULPCLK, + * CLK_ENABLE_T clkType, + * boolean_t bTmrSync, + * ULP_TIMER_CLK_SELECT_T clkSource, + * uint8_t skipSwitchTime) + * @brief This API is used to configure the timer clock source + * @param[in] pULPCLK : pointer to the processor ULP clock source + * @param[in] clkType : clock type for timer + * @param[in] bTmrSync : Timer Synchronisation for ULP timer + * @param[in] clkSource : clock source for ULP timer + * @param[in] skipSwitchTime : wait for clock switched for ULP timer + * @return RSI_OK on success + */ + +rsi_error_t ulpss_time_clk_config(ULPCLK_Type *pULPCLK, + CLK_ENABLE_T clkType, + boolean_t bTmrSync, + ULP_TIMER_CLK_SELECT_T clkSource, + uint8_t skipSwitchTime) +{ + /*Parameter validation */ + if ((pULPCLK == NULL) || (clkSource > ULP_TIMER_MAX_SEL)) { + return INVALID_PARAMETERS; + } + /*Timer PCLK enable */ + ulpss_peripheral_disable(pULPCLK, ULP_TIMER_CLK); + + if (bTmrSync) { + /*Enable m4 core clock*/ + pULPCLK->ULP_TIMER_CLK_GEN_REG_b.ULP_TIMER_IN_SYNC_b = 1; + } else { + pULPCLK->ULP_TIMER_CLK_GEN_REG_b.ULP_TIMER_IN_SYNC_b = 0; + } + /*clock select*/ + switch (clkSource) { + case ULP_TIMER_REF_CLK: + /*Select clock MUX */ + pULPCLK->ULP_TIMER_CLK_GEN_REG_b.ULP_TIMER_CLK_SEL = clkSource; + break; + /*1: ulp_32khz_ro_clk */ + case ULP_TIMER_32KHZ_RO_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_32KHZ_RO_CLK_EN, ULP_PERIPHERAL_CLK, 0); + /*Select clock MUX */ + pULPCLK->ULP_TIMER_CLK_GEN_REG_b.ULP_TIMER_CLK_SEL = clkSource; + break; + /*2: ulp_32khz_rc_clk*/ + case ULP_TIMER_32KHZ_RC_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_32KHZ_RC_CLK_EN, ULP_PERIPHERAL_CLK, 0); + /*Select clock MUX */ + pULPCLK->ULP_TIMER_CLK_GEN_REG_b.ULP_TIMER_CLK_SEL = clkSource; + break; + /*3: ulp_32khz_xtal_clk*/ + case ULP_TIMER_32KHZ_XTAL_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_32KHZ_XTAL_CLK_EN, ULP_PERIPHERAL_CLK, 0); + + pULPCLK->ULP_TIMER_CLK_GEN_REG_b.ULP_TIMER_CLK_SEL = clkSource; + break; + /*4: ulp_32mhz_rc_clk*/ + case ULP_TIMER_32MHZ_RC_CLK: + ulpss_enable_ref_clks(MCU_ULP_32MHZ_RC_CLK_EN, ULP_PERIPHERAL_CLK, 0); + + pULPCLK->ULP_TIMER_CLK_GEN_REG_b.ULP_TIMER_CLK_SEL = clkSource; + break; + /*5: ulp_20mhz_ro_clk*/ + case ULP_TIMER_20MHZ_RO_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_20MHZ_RING_OSC_CLK_EN, ULP_PERIPHERAL_CLK, 0); + /*Select clock MUX */ + pULPCLK->ULP_TIMER_CLK_GEN_REG_b.ULP_TIMER_CLK_SEL = clkSource; + break; + case ULP_TIMER_ULP_SOC_CLK: + /*6: soc_clk*/ + pULPCLK->ULP_TIMER_CLK_GEN_REG_b.ULP_TIMER_CLK_SEL = clkSource; + break; + default: + return INVALID_PARAMETERS; + } + if (skipSwitchTime == 1) { + /*Wait for clock switched */ + while ((pULPCLK->CLOCK_STAUS_REG_b.CLOCK_SWITCHED_TIMER_b != 1U)) + ; + } + ulpss_peripheral_enable(pULPCLK, ULP_TIMER_CLK, clkType); + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t ulpss_aux_clk_config(ULPCLK_Type *pULPCLK, CLK_ENABLE_T clkType, ULP_AUX_CLK_SELECT_T clkSource) + * @brief This API is used to configure the AUX clock source + * @param[in] pULPCLK : pointer to the processor ULP clock source + * @param[in] clkType : clock type for AUX + * @param[in] clkSource : clock source for AUX + * @return RSI_OK on success + */ + +rsi_error_t ulpss_aux_clk_config(ULPCLK_Type *pULPCLK, CLK_ENABLE_T clkType, ULP_AUX_CLK_SELECT_T clkSource) +{ + /*Parameter validation */ + if ((pULPCLK == NULL) || (clkSource > ULP_AUX_MAX_SEL)) { + return INVALID_PARAMETERS; + } + ulpss_peripheral_disable(pULPCLK, ULP_AUX_CLK); + + /*select clock MUX */ + + /*Select */ + switch (clkSource) { + /*0: ref_clk (output of dynamic clock MUX for different possible ref_clk sources)*/ + case ULP_AUX_REF_CLK: + /*Select clock MUX */ + pULPCLK->ULP_AUXADC_CLK_GEN_REG_b.ULP_AUX_CLK_SEL = clkSource; + break; + /*1: ulp_32khz_ro_clk */ + case ULP_AUX_32KHZ_RO_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_32KHZ_RO_CLK_EN, ULP_PERIPHERAL_CLK, 0); + /*Select clock MUX */ + pULPCLK->ULP_AUXADC_CLK_GEN_REG_b.ULP_AUX_CLK_SEL = clkSource; + break; + /*2: ulp_32khz_rc_clk*/ + case ULP_AUX_32KHZ_RC_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_32KHZ_RC_CLK_EN, ULP_PERIPHERAL_CLK, 0); + /*Select clock MUX */ + pULPCLK->ULP_AUXADC_CLK_GEN_REG_b.ULP_AUX_CLK_SEL = clkSource; + break; + /*3: ulp_32khz_xtal_clk*/ + case ULP_AUX_32KHZ_XTAL_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_32KHZ_XTAL_CLK_EN, ULP_PERIPHERAL_CLK, 0); + pULPCLK->ULP_AUXADC_CLK_GEN_REG_b.ULP_AUX_CLK_SEL = clkSource; + break; + /*4: ulp_32mhz_rc_clk*/ + case ULP_AUX_32MHZ_RC_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_32MHZ_RC_CLK_EN, ULP_PERIPHERAL_CLK, 0); + /*Select clock MUX */ + pULPCLK->ULP_AUXADC_CLK_GEN_REG_b.ULP_AUX_CLK_SEL = clkSource; + break; + /*5: ulp_20mhz_ro_clk*/ + case ULP_AUX_20MHZ_RO_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_20MHZ_RING_OSC_CLK_EN, ULP_PERIPHERAL_CLK, 0); + /*Select clock MUX */ + pULPCLK->ULP_AUXADC_CLK_GEN_REG_b.ULP_AUX_CLK_SEL = clkSource; + break; + case ULP_AUX_ULP_SOC_CLK: + /*6: soc_clk*/ + pULPCLK->ULP_AUXADC_CLK_GEN_REG_b.ULP_AUX_CLK_SEL = clkSource; + break; + case ULP_AUX_ULP_DOUBLER_CLK: + /*7: ulp_doubler_clk*/ + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_DOUBLER_CLK_EN, ULP_PERIPHERAL_CLK, 0); + /*Select clock MUX */ + pULPCLK->ULP_AUXADC_CLK_GEN_REG_b.ULP_AUX_CLK_SEL = clkSource; + break; + case ULP_AUX_I2S_PLL_CLK: + /*8: i2s_pll_clk*/ + if (M4CLK->PLL_STAT_REG_b.I2SPLL_LOCK == 0) { + return ERROR_CLOCK_NOT_ENABLED; + } + /*Enable clock*/ + M4CLK->CLK_CONFIG_REG5_b.I2S_CLK_SEL = 0; + /*Select clock MUX */ + pULPCLK->ULP_AUXADC_CLK_GEN_REG_b.ULP_AUX_CLK_SEL = clkSource; + break; + default: + return INVALID_PARAMETERS; + } + + /*wait for clock switched */ + while ((pULPCLK->CLOCK_STAUS_REG_b.CLOCK_SWITCHED_AUXADC_b != 1U)) + ; + + ulpss_peripheral_enable(pULPCLK, ULP_AUX_CLK, clkType); + + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t ulpss_vad_clk_config(ULPCLK_Type *pULPCLK, + * ULP_VAD_CLK_SELECT_T clkSource, + * ULP_VAD_FCLK_SELECT_T FclkSource, + * uint16_t divFactor) + * @brief This API is used to configure the VAD clock source + * @param[in] pULPCLK : pointer to the processor ULP clock source + * @param[in] clkSource : clock source for ULP VAD + * @param[in] FclkSource : fast clock cource for ULP VAD + * @param[in] divFactor : divison factor for ULP VAD + * @return RSI_OK on success + */ + +rsi_error_t ulpss_vad_clk_config(ULPCLK_Type *pULPCLK, + ULP_VAD_CLK_SELECT_T clkSource, + ULP_VAD_FCLK_SELECT_T FclkSource, + uint16_t divFactor) +{ + /*Parameter validation */ + if (((pULPCLK == NULL) || (divFactor >= ULP_VAD_MAX_DIVISION_FACTOR) || (clkSource > ULP_VAD_MAX_SEL) + || (FclkSource > ULP_VAD_FCLK_MAX_SEL))) { + return INVALID_PARAMETERS; + } + + ulpss_peripheral_disable(pULPCLK, ULP_VAD_CLK); + /*Select the VAD clock MUX */ + switch (clkSource) { + case ULP_VAD_32KHZ_RO_CLK: + pULPCLK->ULP_VAD_CLK_GEN_REG_b.ULP_VAD_CLK_SEL = clkSource; + break; + case ULP_VAD_32KHZ_RC_CLK: + /*1:ulp_32khz_rc_clk */ + ulpss_enable_ref_clks(MCU_ULP_32KHZ_RC_CLK_EN, ULP_PERIPHERAL_CLK, 0); + pULPCLK->ULP_VAD_CLK_GEN_REG_b.ULP_VAD_CLK_SEL = clkSource; + break; + case ULP_VAD_32KHZ_XTAL_CLK: + /*2: ulp_32khz_xtal_clk*/ + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_32KHZ_XTAL_CLK_EN, ULP_PERIPHERAL_CLK, 0); + pULPCLK->ULP_VAD_CLK_GEN_REG_b.ULP_VAD_CLK_SEL = clkSource; + break; + default: + return INVALID_PARAMETERS; + } + /*Select the VAD Fast clock MUX */ + switch (FclkSource) { + case ULP_VAD_ULP_PROCESSOR_CLK: + /* ulpss processor clock */ + pULPCLK->ULP_VAD_CLK_GEN_REG_b.ULP_VAD_FCLK_SEL = FclkSource; + break; + case ULP_VAD_REF_CLK: + /*1: ref_clk */ + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_40MHZ_CLK_EN, ULP_PERIPHERAL_CLK, 0); + pULPCLK->ULP_VAD_CLK_GEN_REG_b.ULP_VAD_FCLK_SEL = FclkSource; + break; + case ULP_VAD_32MHZ_RC_CLK: + /*2: ulp_32mhz_rc_clk*/ + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_32MHZ_RC_CLK_EN, ULP_PERIPHERAL_CLK, 0); + pULPCLK->ULP_VAD_CLK_GEN_REG_b.ULP_VAD_FCLK_SEL = FclkSource; + break; + case ULP_VAD_20MHZ_RO_CLK: + /*3: ulp_20mhz_ro_clk*/ + ulpss_enable_ref_clks(MCU_ULP_20MHZ_RING_OSC_CLK_EN, ULP_PERIPHERAL_CLK, 0); + pULPCLK->ULP_VAD_CLK_GEN_REG_b.ULP_VAD_FCLK_SEL = FclkSource; + break; + case ULP_VAD_ULP_SOC_CLK: + /*4: soc_clk*/ + // M4CLK->CLK_ENABLE_SET_REG1_b.ULPSS_CLK_ENABLE_b = 1; + pULPCLK->ULP_VAD_CLK_GEN_REG_b.ULP_VAD_FCLK_SEL = FclkSource; + break; + default: + return INVALID_PARAMETERS; + } + + /*wait for clock switched */ + while ((pULPCLK->CLOCK_STAUS_REG_b.CLOCK_SWITCHED_FCLK_VAD_b != 1U)) + ; + while ((pULPCLK->CLOCK_STAUS_REG_b.CLOCK_SWITCHED_SCLK_VAD_b != 1U)) + ; + while ((pULPCLK->CLOCK_STAUS_REG_b.CLOCK_SWITCHED_VAD_b != 1U)) + ; + /*Set VAD clock division factor */ + pULPCLK->ULP_VAD_CLK_GEN_REG_b.ULP_VAD_CLKDIV_FACTOR = (uint8_t)divFactor; + + ulpss_peripheral_enable(pULPCLK, ULP_VAD_CLK, ENABLE_STATIC_CLK); + + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t ulpss_touch_clk_config(ULPCLK_Type *pULPCLK, ULP_TOUCH_CLK_SELECT_T clkSource, uint16_t divFactor) + * @brief This API is used to configure the Touch clock source + * @param[in] pULPCLK : pointer to the processor ULP clock source + * @param[in] clkSource : clock source for ULP Touch + * @param[in] divFactor : divison factor for ULP Touch + * @return RSI_OK on success + */ + +rsi_error_t ulpss_touch_clk_config(ULPCLK_Type *pULPCLK, ULP_TOUCH_CLK_SELECT_T clkSource, uint16_t divFactor) +{ + /*Parameter validation */ + if ((pULPCLK == NULL) || (divFactor > ULP_TOUCH_MAX_DIVISION_FACTOR) || (clkSource > ULP_TOUCH_MAX_SEL)) { + return INVALID_PARAMETERS; + } + ulpss_peripheral_disable(pULPCLK, ULP_TOUCH_CLK); + + /*Select */ + switch (clkSource) { + /*0: ref_clk (output of dynamic clock MUX for different possible ref_clk sources)*/ + case ULP_TOUCH_REF_CLK: + /*Select clock MUX */ + pULPCLK->ULP_TOUCH_CLK_GEN_REG_b.ULP_TOUCH_CLK_SEL = clkSource; + break; + /*1: ulp_32khz_ro_clk */ + case ULP_TOUCH_32KHZ_RO_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_32KHZ_RO_CLK_EN, ULP_PERIPHERAL_CLK, 0); + /*Select clock MUX */ + pULPCLK->ULP_TOUCH_CLK_GEN_REG_b.ULP_TOUCH_CLK_SEL = clkSource; + break; + /*2: ulp_32khz_rc_clk*/ + case ULP_TOUCH_32KHZ_RC_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_32KHZ_RC_CLK_EN, ULP_PERIPHERAL_CLK, 0); + /*Select clock MUX */ + pULPCLK->ULP_TOUCH_CLK_GEN_REG_b.ULP_TOUCH_CLK_SEL = clkSource; + break; + /*3: ulp_32khz_xtal_clk*/ + case ULP_TOUCH_32KHZ_XTAL_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_32KHZ_XTAL_CLK_EN, ULP_PERIPHERAL_CLK, 0); + pULPCLK->ULP_TOUCH_CLK_GEN_REG_b.ULP_TOUCH_CLK_SEL = clkSource; + break; + /*4: ulp_32mhz_rc_clk*/ + case ULP_TOUCH_32MHZ_RC_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_32MHZ_RC_CLK_EN, ULP_PERIPHERAL_CLK, 0); + /*Select clock MUX */ + pULPCLK->ULP_TOUCH_CLK_GEN_REG_b.ULP_TOUCH_CLK_SEL = clkSource; + break; + /*5: ulp_20mhz_ro_clk*/ + case ULP_TOUCH_20MHZ_RO_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_20MHZ_RING_OSC_CLK_EN, ULP_PERIPHERAL_CLK, 0); + /*Select clock MUX */ + pULPCLK->ULP_TOUCH_CLK_GEN_REG_b.ULP_TOUCH_CLK_SEL = clkSource; + break; + case ULP_TOUCH_ULP_SOC_CLK: + /*6: soc_clk*/ + pULPCLK->ULP_TOUCH_CLK_GEN_REG_b.ULP_TOUCH_CLK_SEL = clkSource; + break; + + default: + return INVALID_PARAMETERS; + } + + /*Wait for clock switched */ + while ((pULPCLK->CLOCK_STAUS_REG_b.CLOCK_SWITCHED_TOUCH_SENSOR_b) != 1) + ; + + /*Program the division factor */ + pULPCLK->ULP_TOUCH_CLK_GEN_REG_b.ULP_TOUCH_CLKDIV_FACTOR = (uint8_t)divFactor; + + ulpss_peripheral_enable(pULPCLK, ULP_TOUCH_CLK, ENABLE_STATIC_CLK); + + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t ulpss_slp_sensor_clk_config(ULPCLK_Type *pULPCLK, boolean_t clkEnable, uint32_t divFactor) + * @brief This API is used to configure the sleep sensor clock source + * @param[in] pULPCLK : pointer to the processor ULP clock source + * @param[in] clkEnable : enable clock for ULP sleep sensor + * @param[in] divFactor : divison factor for ULP sleep sensor + * @return RSI_OK on success + */ + +rsi_error_t ulpss_slp_sensor_clk_config(ULPCLK_Type *pULPCLK, boolean_t clkEnable, uint32_t divFactor) +{ + /*Parameter validation */ + if ((pULPCLK == NULL) || (divFactor > ULP_SLP_SENSOR_MAX_DIVISION_FACTOR)) { + return INVALID_PARAMETERS; + } + if (clkEnable) { + /*Enable sleep sensor clock */ + pULPCLK->SLP_SENSOR_CLK_REG_b.ENABLE_b = 1; + } else { + /*Disable sleep sensor clock */ + pULPCLK->SLP_SENSOR_CLK_REG_b.ENABLE_b = 0; + } + /*Apply division factor*/ + pULPCLK->SLP_SENSOR_CLK_REG_b.DIVISON_FACTOR = (uint8_t)divFactor; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t ulpss_peripheral_enable(ULPCLK_Type *pULPCLK, ULPPERIPHERALS_CLK_T module, CLK_ENABLE_T clkType) + * @brief This API is used to enable the particular ULP perpheral Clock + * @param[in] pULPCLK : pointer to the processor ULP clock source + * @param[in] module : module for ULP peripheral Clock + * @param[in] clkType : clock type for ULP peripheral Clock + * @return RSI_OK on success + */ + +rsi_error_t ulpss_peripheral_enable(ULPCLK_Type *pULPCLK, ULPPERIPHERALS_CLK_T module, CLK_ENABLE_T clkType) +{ + if (pULPCLK == NULL) { + return INVALID_PARAMETERS; + } + switch (module) { + case ULP_I2C_CLK: + pULPCLK->ULP_I2C_SSI_CLK_GEN_REG_b.ULP_I2C_CLK_EN_b = 1; + pULPCLK->ULP_MISC_SOFT_SET_REG_b.PCLK_ENABLE_I2C_b = 1; + break; + case ULP_EGPIO_CLK: + pULPCLK->ULP_MISC_SOFT_SET_REG_b.EGPIO_CLK_EN_b = 1; + pULPCLK->ULP_MISC_SOFT_SET_REG_b.EGPIO_PCLK_ENABLE_b = 1; + break; + case ULP_AUX_CLK: + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.AUX_CLK_EN_b = 1; + + if (clkType == ENABLE_STATIC_CLK) { + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.AUX_PCLK_EN_b = 1; + pULPCLK->ULP_AUXADC_CLK_GEN_REG_b.ULP_AUX_CLK_EN_b = 1; + } else { + /**Static enable **/ + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.AUX_PCLK_EN_b = 0; + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.AUX_CLK_DYN_CTRL_DISABLE_b = 0; + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.AUX_PCLK_DYN_CTRL_DISABLE_b = 0; + } + break; + case ULP_FIM_CLK: + pULPCLK->ULP_MISC_SOFT_SET_REG_b.FIM_PCLK_ENABLE_b = 1; + if (clkType == ENABLE_STATIC_CLK) { + pULPCLK->ULP_MISC_SOFT_SET_REG_b.FIM_CLK_EN_b = 1; + } else { + pULPCLK->ULP_MISC_SOFT_SET_REG_b.FIM_CLK_EN_b = 0; + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.FIM_CLK_DYN_CTRL_DISABLE_b = 0; + } + break; + case ULP_VAD_CLK: + pULPCLK->ULP_MISC_SOFT_SET_REG_b.VAD_CLK_EN_b = 1; + pULPCLK->ULP_VAD_CLK_GEN_REG_b.ULP_VAD_CLK_EN_b = 1; + pULPCLK->ULP_VAD_CLK_GEN_REG_b.ULP_VAD_FCLK_EN = 1; + pULPCLK->ULP_MISC_SOFT_SET_REG_b.VAD_PCLK_ENABLE_b = 1; + break; + case ULP_TIMER_CLK: + pULPCLK->ULP_MISC_SOFT_SET_REG_b.CLK_ENABLE_TIMER_b = 1; + if (clkType == ENABLE_STATIC_CLK) { + pULPCLK->ULP_MISC_SOFT_SET_REG_b.TIMER_PCLK_EN_b = 1; + } else { + pULPCLK->ULP_MISC_SOFT_SET_REG_b.TIMER_PCLK_EN_b = 0; + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.TIMER_PCLK_DYN_CTRL_DISABLE_b = 0; + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.TIMER_SCLK_DYN_CTRL_DISABLE_b = 0; + } + break; + case ULP_UDMA_CLK: + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.UDMA_CLK_ENABLE_b = 1; + break; + case ULP_TOUCH_CLK: + pULPCLK->ULP_TOUCH_CLK_GEN_REG_b.ULP_TOUCH_CLK_EN_b = 1; + break; + case ULP_UART_CLK: + if (clkType == ENABLE_STATIC_CLK) { + pULPCLK->ULP_MISC_SOFT_SET_REG_b.PCLK_ENABLE_UART_b = 1; + pULPCLK->ULP_MISC_SOFT_SET_REG_b.SCLK_ENABLE_UART_b = 1; + } else { + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.UART_CLK_DYN_CTRL_DISABLE_b = 0; + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.UART_SCLK_DYN_CTRL_DISABLE_b = 0; + pULPCLK->ULP_MISC_SOFT_SET_REG_b.PCLK_ENABLE_UART_b = 0; + pULPCLK->ULP_MISC_SOFT_SET_REG_b.SCLK_ENABLE_UART_b = 0; + } + break; + case ULP_SSI_CLK: + pULPCLK->ULP_I2C_SSI_CLK_GEN_REG_b.ULP_SSI_CLK_EN_b = 1; + pULPCLK->ULP_MISC_SOFT_SET_REG_b.SCLK_ENABLE_SSI_MASTER_b = 1; + if (clkType == ENABLE_STATIC_CLK) { + pULPCLK->ULP_MISC_SOFT_SET_REG_b.PCLK_ENABLE_SSI_MASTER_b = 1; + } else { + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.SSI_MST_PCLK_DYN_CTRL_DISABLE_b = 0; + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.SSI_MST_SCLK_DYN_CTRL_DISABLE_b = 0; + pULPCLK->ULP_MISC_SOFT_SET_REG_b.PCLK_ENABLE_SSI_MASTER_b = 0; + } + break; + case ULP_I2S_CLK: + /*ULPSS I2S master*/ + pULPCLK->ULP_I2S_CLK_GEN_REG_b.ULP_I2S_CLK_EN_b = 1; + pULPCLK->ULP_MISC_SOFT_SET_REG_b.CLK_ENABLE_I2S_b = 1; + pULPCLK->ULP_I2S_CLK_GEN_REG_b.ULP_I2S_PCLK_EN_b = 1; + break; + + default: + return INVALID_PARAMETERS; + } + return RSI_OK; +} +#endif + +/*==============================================*/ +/** + * @fn rsi_error_t ulpss_peripheral_disable(ULPCLK_Type *pULPCLK, ULPPERIPHERALS_CLK_T module) + * @brief This API is used to Disable the particulat ULP perpheral Clock + * @param[in] pULPCLK : pointer to the processor ULP clock source + * @param[in] module : module for ULP peripheral Clock + * @return RSI_OK on success + */ + +rsi_error_t ulpss_peripheral_disable(ULPCLK_Type *pULPCLK, ULPPERIPHERALS_CLK_T module) +{ + if (pULPCLK == NULL) { + return INVALID_PARAMETERS; + } + switch (module) { + case ULP_I2C_CLK: + pULPCLK->ULP_I2C_SSI_CLK_GEN_REG_b.ULP_I2C_CLK_EN_b = 0; + pULPCLK->ULP_MISC_SOFT_SET_REG_b.PCLK_ENABLE_I2C_b = 0; + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.I2C_PCLK_DYN_CTRL_DISABLE_b = 1; + break; + case ULP_EGPIO_CLK: + pULPCLK->ULP_MISC_SOFT_SET_REG_b.EGPIO_CLK_EN_b = 0; + pULPCLK->ULP_MISC_SOFT_SET_REG_b.EGPIO_PCLK_ENABLE_b = 0; + pULPCLK->ULP_MISC_SOFT_SET_REG_b.EGPIO_PCLK_DYN_CTRL_DISABLE_b = 1; + break; + case ULP_AUX_CLK: + pULPCLK->ULP_AUXADC_CLK_GEN_REG_b.ULP_AUX_CLK_EN_b = 0; + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.AUX_CLK_EN_b = 0; + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.AUX_PCLK_EN_b = 0; + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.AUX_CLK_DYN_CTRL_DISABLE_b = 1; + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.AUX_PCLK_DYN_CTRL_DISABLE_b = 1; + break; + case ULP_FIM_CLK: + pULPCLK->ULP_MISC_SOFT_SET_REG_b.FIM_CLK_EN_b = 0; + pULPCLK->ULP_MISC_SOFT_SET_REG_b.FIM_PCLK_ENABLE_b = 0; + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.FIM_CLK_DYN_CTRL_DISABLE_b = 1; + break; + case ULP_VAD_CLK: + pULPCLK->ULP_MISC_SOFT_SET_REG_b.VAD_CLK_EN_b = 0; + pULPCLK->ULP_MISC_SOFT_SET_REG_b.VAD_PCLK_ENABLE_b = 0; + pULPCLK->ULP_VAD_CLK_GEN_REG_b.ULP_VAD_CLK_EN_b = 0; + pULPCLK->ULP_VAD_CLK_GEN_REG_b.ULP_VAD_FCLK_EN = 0; + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.VAD_CLK_DYN_CTRL_DISABLE_b = 1; + break; + case ULP_TIMER_CLK: + pULPCLK->ULP_MISC_SOFT_SET_REG_b.TIMER_PCLK_EN_b = 0; + pULPCLK->ULP_MISC_SOFT_SET_REG_b.CLK_ENABLE_TIMER_b = 0; + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.TIMER_PCLK_DYN_CTRL_DISABLE_b = 1; + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.TIMER_SCLK_DYN_CTRL_DISABLE_b = 1; + break; + case ULP_UDMA_CLK: + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.UDMA_CLK_ENABLE_b = 0; + break; + case ULP_TOUCH_CLK: + pULPCLK->ULP_TOUCH_CLK_GEN_REG_b.ULP_TOUCH_CLK_EN_b = 0; + break; + case ULP_UART_CLK: + pULPCLK->ULP_MISC_SOFT_SET_REG_b.PCLK_ENABLE_UART_b = 0; + pULPCLK->ULP_MISC_SOFT_SET_REG_b.SCLK_ENABLE_UART_b = 0; + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.UART_SCLK_DYN_CTRL_DISABLE_b = 1; + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.UART_CLK_DYN_CTRL_DISABLE_b = 1; + break; + case ULP_SSI_CLK: + pULPCLK->ULP_MISC_SOFT_SET_REG_b.SCLK_ENABLE_SSI_MASTER_b = 0; + pULPCLK->ULP_MISC_SOFT_SET_REG_b.PCLK_ENABLE_SSI_MASTER_b = 0; + pULPCLK->ULP_I2C_SSI_CLK_GEN_REG_b.ULP_SSI_CLK_EN_b = 0; + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.SSI_MST_PCLK_DYN_CTRL_DISABLE_b = 1; + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.SSI_MST_SCLK_DYN_CTRL_DISABLE_b = 1; + break; + case ULP_I2S_CLK: + pULPCLK->ULP_MISC_SOFT_SET_REG_b.CLK_ENABLE_I2S_b = 0; + pULPCLK->ULP_I2S_CLK_GEN_REG_b.ULP_I2S_PCLK_EN_b = 0; + pULPCLK->ULP_I2S_CLK_GEN_REG_b.ULP_I2S_CLK_EN_b = 0; + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.I2S_CLK_DYN_CTRL_DISABLE_b = 1; + pULPCLK->ULP_I2S_CLK_GEN_REG_b.ULP_I2S_PCLK_DYN_CTRL_DISABLE_b = 1; + pULPCLK->ULP_I2S_CLK_GEN_REG_b.ULP_I2S_SCLK_DYN_CTRL_DISABLE_b = 1; + break; + default: + return INVALID_PARAMETERS; + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t ulpss_time_clk_disable(ULPCLK_Type *pULPCLK) + * @brief This API is used to disable the timer clock + * @param[in] pULPCLK : pointer to the processor ULP clock source + * @return ulpss_peripheral_disable on success + */ + +rsi_error_t ulpss_time_clk_disable(ULPCLK_Type *pULPCLK) +{ + pULPCLK->ULP_TIMER_CLK_GEN_REG_b.ULP_TIMER_CLK_SEL = 0xF; + return ulpss_peripheral_disable(pULPCLK, ULP_TIMER_CLK); +} + +/*==============================================*/ +/** + * @fn rsi_error_t ulpss_ref_clk_config(ULPSS_REF_CLK_SEL_T clkSource) + * @brief This API is used to select the ULPSS processor ref clk configuration + * @param[in] clkSource : clock source for ULPSS processor reference clock select + * @return RSI_OK on success + */ + +rsi_error_t ulpss_ref_clk_config(ULPSS_REF_CLK_SEL_T clkSource) +{ + + switch (clkSource) { + case ULPSS_REF_BYP_CLK: + MCU_FSM->MCU_FSM_REF_CLK_REG_b.ULPSS_REF_CLK_SEL_b = 0x01; + system_clocks.ulp_ref_clock_source = ULPSS_REF_BYP_CLK; + system_clocks.ulpss_ref_clk = system_clocks.byp_rc_ref_clock; + break; + case ULPSS_ULP_32MHZ_RC_CLK: + MCU_FSM->MCU_FSM_REF_CLK_REG_b.ULPSS_REF_CLK_SEL_b = 0x02; + system_clocks.ulp_ref_clock_source = ULPSS_ULP_32MHZ_RC_CLK; + system_clocks.ulpss_ref_clk = system_clocks.rc_32mhz_clock; + break; + case ULPSS_RF_REF_CLK: + MCU_FSM->MCU_FSM_REF_CLK_REG_b.ULPSS_REF_CLK_SEL_b = 0x03; + system_clocks.ulp_ref_clock_source = ULPSS_RF_REF_CLK; + system_clocks.ulpss_ref_clk = system_clocks.rf_ref_clock; + break; + case ULPSS_MEMS_REF_CLK: + TASS_PLL_CTRL_SET_REG(AFEPLLCTRLREG1) = MEMS_REF_CLK_ENABLE; + MCU_FSM->MCU_FSM_REF_CLK_REG_b.ULPSS_REF_CLK_SEL_b = 0x04; + system_clocks.ulp_ref_clock_source = ULPSS_MEMS_REF_CLK; + system_clocks.ulpss_ref_clk = system_clocks.mems_ref_clock; + break; + case ULPSS_ULP_20MHZ_RINGOSC_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_20MHZ_RING_OSC_CLK_EN, ULP_PERIPHERAL_CLK, 0); + MCU_FSM->MCU_FSM_REF_CLK_REG_b.ULPSS_REF_CLK_SEL_b = 0x05; + system_clocks.ulp_ref_clock_source = ULPSS_ULP_20MHZ_RINGOSC_CLK; + system_clocks.ulpss_ref_clk = system_clocks.ro_20mhz_clock; + break; + case ULPSS_ULP_DOUBLER_CLK: + /*7: ulp_doubler_clk*/ + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_DOUBLER_CLK_EN, ULP_PERIPHERAL_CLK, 0); + MCU_FSM->MCU_FSM_REF_CLK_REG_b.ULPSS_REF_CLK_SEL_b = 0x06; + system_clocks.ulp_ref_clock_source = ULPSS_ULP_DOUBLER_CLK; + system_clocks.ulpss_ref_clk = system_clocks.doubler_clock; + break; + default: + return INVALID_PARAMETERS; + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t ulpss_ulp_proc_clk_config(ULPCLK_Type *pULPCLK, + * ULP_PROC_CLK_SELECT_T clkSource, + * uint16_t divFactor, + * cdDelay delayFn) + * @brief This API is used to configure the ULPSS processor clock source + * @param[in] pULPCLK : pointer to the processor ULP clock source + * @param[in] clkSource : clock source for ULPSS processor clock select + * @param[in] divFactor : divison factor for processor clock source + * @param[in] delayFn : delay functionfor processor clock source + * @return RSI_OK on success + */ + +rsi_error_t ulpss_ulp_proc_clk_config(ULPCLK_Type *pULPCLK, + ULP_PROC_CLK_SELECT_T clkSource, + uint16_t divFactor, + cdDelay delayFn) +{ + /*Parameter validation */ + if ((pULPCLK == NULL) || (divFactor > ULP_PROC_MAX_DIVISOIN_FACTOR) || (clkSource > ULP_PROC_MAX_SEL)) { + return INVALID_PARAMETERS; + } + + /*Select */ + switch (clkSource) { + + case ULP_PROC_REF_CLK: + /*Select clock MUX */ + RSI_SetRegSpiDivision(0U); + pULPCLK->ULP_TA_CLK_GEN_REG_b.ULP_PROC_CLK_SEL = clkSource; + SystemCoreClock = system_clocks.ulpss_ref_clk; + break; + + case ULP_PROC_ULP_32KHZ_RO_CLK: + /*Enable clock*/ + RSI_SetRegSpiDivision(0U); + ulpss_enable_ref_clks(MCU_ULP_32KHZ_RO_CLK_EN, ULP_PROCESSOR_CLK, delayFn); + /*Select clock MUX */ + pULPCLK->ULP_TA_CLK_GEN_REG_b.ULP_PROC_CLK_SEL = clkSource; + SystemCoreClock = system_clocks.ro_32khz_clock; + break; + + case ULP_PROC_ULP_32KHZ_RC_CLK: + /*Enable clock*/ + RSI_SetRegSpiDivision(0U); + ulpss_enable_ref_clks(MCU_ULP_32KHZ_RC_CLK_EN, ULP_PROCESSOR_CLK, delayFn); + SystemCoreClock = system_clocks.rc_32khz_clock; + /*Select clock MUX */ + pULPCLK->ULP_TA_CLK_GEN_REG_b.ULP_PROC_CLK_SEL = clkSource; + break; + + case ULP_PROC_ULP_32KHZ_XTAL_CLK: + /*Enable clock*/ + RSI_SetRegSpiDivision(0U); + ulpss_enable_ref_clks(MCU_ULP_32KHZ_XTAL_CLK_EN, ULP_PROCESSOR_CLK, delayFn); + pULPCLK->ULP_TA_CLK_GEN_REG_b.ULP_PROC_CLK_SEL = clkSource; + SystemCoreClock = system_clocks.xtal_32khz_clock; + break; + + case ULP_PROC_ULP_32MHZ_RC_CLK: + /*Enable clock*/ + RSI_SetRegSpiDivision(0U); + ulpss_enable_ref_clks(MCU_ULP_32MHZ_RC_CLK_EN, ULP_PROCESSOR_CLK, delayFn); + /*Select clock MUX */ + pULPCLK->ULP_TA_CLK_GEN_REG_b.ULP_PROC_CLK_SEL = clkSource; + SystemCoreClock = system_clocks.rc_32mhz_clock; + break; + + case ULP_PROC_ULP_20MHZ_RO_CLK: + /*Enable clock*/ + RSI_SetRegSpiDivision(0U); + ulpss_enable_ref_clks(MCU_ULP_20MHZ_RING_OSC_CLK_EN, ULP_PROCESSOR_CLK, delayFn); + /*Select clock MUX */ + pULPCLK->ULP_TA_CLK_GEN_REG_b.ULP_PROC_CLK_SEL = clkSource; + SystemCoreClock = system_clocks.ro_20mhz_clock; + break; + + case ULP_PROC_SOC_CLK: + /*6: soc_clk*/ + RSI_SetRegSpiDivision(2U); + pULPCLK->ULP_TA_CLK_GEN_REG_b.ULP_PROC_CLK_SEL = clkSource; + SystemCoreClock = system_clocks.soc_clock; + break; + + case ULP_PROC_ULP_DOUBLER_CLK: + /*Enable clock*/ + RSI_SetRegSpiDivision(0U); + ulpss_enable_ref_clks(MCU_ULP_DOUBLER_CLK_EN, ULP_PROCESSOR_CLK, delayFn); + /*Select clock MUX */ + pULPCLK->ULP_TA_CLK_GEN_REG_b.ULP_PROC_CLK_SEL = clkSource; + SystemCoreClock = system_clocks.doubler_clock; + break; + default: + return INVALID_PARAMETERS; + } + while (pULPCLK->CLOCK_STAUS_REG_b.CLOCK_SWITCHED_PROC_CLK_b != 1) + ; + /*update the division factor */ + pULPCLK->ULP_TA_CLK_GEN_REG_b.ULP_PROC_CLK_DIV_FACTOR = (char)divFactor; + /*clock Enable */ + pULPCLK->ULP_TA_CLK_GEN_REG_b.ULP2M4_A2A_BRDG_CLK_EN_b = 1; + + if (divFactor) { + SystemCoreClock = (SystemCoreClock / divFactor); + } + system_clocks.soc_clock = SystemCoreClock; + return RSI_OK; +} +/** @} */ + +/*ROM API structure +const ROM_ULPSS_CLK_API_T ulpssclk_api = { + &ulpss_clock_config , + &ulpss_ulp_peri_clk_enable, + &ulpss_ulp_peri_clk_disable, + &ulpss_ulp_dyn_clk_enable, + &ulpss_ulp_dyn_clk_disable, + &ulpss_ulp_ssi_clk_config, + &ulpss_ulp_i2s_clk_config, + &ulpss_ulp_uar_clk_config, + &ulpss_time_clk_disable, + &ulpss_time_clk_config, + &ulpss_aux_clk_config, + &ulpss_vad_clk_config, + &ulpss_touch_clk_config, + &ulpss_slp_sensor_clk_config, + &ulpss_peripheral_enable, + &ulpss_peripheral_disable +}; + */ +/*End of file not truncated*/ From ee25903adf4fdf5c084efb3885e4a5d5fdac0124 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C3=A9r=C3=B4me=20Pouiller?= Date: Wed, 24 Jul 2024 15:34:52 +0200 Subject: [PATCH 02/62] modules: hal_silabs: fix missing si91x_mvp.h file Origin: Silicon Labs WiSeConnect SDK License: MSLA URL: https://github.com/siliconlabs/wiseconnect commit: e97a0ed00ddda347a8a39e8276f470e1c5fea469 Purpose: Fix compilation error --- .../si91x/mcu/core/chip/inc/si91x_mvp.h | 1604 +++++++++++++++++ 1 file changed, 1604 insertions(+) create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/si91x_mvp.h diff --git a/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/si91x_mvp.h b/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/si91x_mvp.h new file mode 100644 index 000000000..38ef63e4a --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/si91x_mvp.h @@ -0,0 +1,1604 @@ +/**************************************************************************/ /** + * @file + * @brief SI91X MVP register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef SI91X_MVP_H +#define SI91X_MVP_H +#define MVP_HAS_SET_CLEAR + +/******************************************************************************/ +/**************************************************************************/ /** + * @brief SI91X MVP Register Declaration. + *****************************************************************************/ + +/** MVP PERF Register Group Declaration. */ +typedef struct { + __IM uint32_t CNT; /**< Run Counter */ +} MVP_PERF_TypeDef; + +/** MVP ARRAYST Register Group Declaration. */ +typedef struct { + __IOM uint32_t INDEXSTATE; /**< Index State */ +} MVP_ARRAYST_TypeDef; + +/** MVP LOOPST Register Group Declaration. */ +typedef struct { + __IOM uint32_t STATE; /**< Loop State */ +} MVP_LOOPST_TypeDef; + +/** MVP ALU Register Group Declaration. */ +typedef struct { + __IOM uint32_t REGSTATE; /**< ALU Rn Register */ +} MVP_ALU_TypeDef; + +/** MVP ARRAY Register Group Declaration. */ +typedef struct { + __IOM uint32_t ADDRCFG; /**< Array Base Address */ + __IOM uint32_t DIM0CFG; /**< Dimension 0 Configuration */ + __IOM uint32_t DIM1CFG; /**< Dimension 1 Configuration */ + __IOM uint32_t DIM2CFG; /**< Dimension 2 Configuration */ +} MVP_ARRAY_TypeDef; + +/** MVP LOOP Register Group Declaration. */ +typedef struct { + __IOM uint32_t CFG; /**< Loop Configuration */ + __IOM uint32_t RST; /**< Loop Reset */ +} MVP_LOOP_TypeDef; + +/** MVP INSTR Register Group Declaration. */ +typedef struct { + __IOM uint32_t CFG0; /**< Instruction Configuration Word 0 */ + __IOM uint32_t CFG1; /**< Instruction Configuration Word 1 */ + __IOM uint32_t CFG2; /**< Instruction Configuration Word 2 */ +} MVP_INSTR_TypeDef; + +/** MVP Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP Version */ + __IOM uint32_t EN; /**< Enable */ + __IOM uint32_t SWRST; /**< Software Reset */ + __IOM uint32_t CFG; /**< Configuration */ + __IM uint32_t STATUS; /**< Status */ + MVP_PERF_TypeDef PERF[2U]; /**< */ + __IOM uint32_t IF; /**< Interrupt Flags */ + __IOM uint32_t IEN; /**< Interrupt Enables */ + __IM uint32_t FAULTSTATUS; /**< Fault Status */ + __IM uint32_t FAULTADDR; /**< Fault Address */ + __IOM uint32_t PROGRAMSTATE; /**< Program State */ + MVP_ARRAYST_TypeDef ARRAYST[5U]; /**< */ + MVP_LOOPST_TypeDef LOOPST[8U]; /**< */ + MVP_ALU_TypeDef ALU[8U]; /**< */ + MVP_ARRAY_TypeDef ARRAY[5U]; /**< */ + MVP_LOOP_TypeDef LOOP[8U]; /**< */ + MVP_INSTR_TypeDef INSTR[8U]; /**< */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED0[34U]; /**< Reserved for future use */ + __IOM uint32_t DEBUGEN; /**< Debug Enable Register */ + __IOM uint32_t DEBUGSTEPCNT; /**< Debug Step Register */ + __IM uint32_t LOAD0ADDR; /**< Array Address State */ + __IM uint32_t LOAD1ADDR; /**< Array Address State */ + __IM uint32_t STOREADDR; /**< Array Address State */ + uint32_t RESERVED1[891U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + __IOM uint32_t EN_SET; /**< Enable */ + __IOM uint32_t SWRST_SET; /**< Software Reset */ + __IOM uint32_t CFG_SET; /**< Configuration */ + __IM uint32_t STATUS_SET; /**< Status */ + MVP_PERF_TypeDef PERF_SET[2U]; /**< */ + __IOM uint32_t IF_SET; /**< Interrupt Flags */ + __IOM uint32_t IEN_SET; /**< Interrupt Enables */ + __IM uint32_t FAULTSTATUS_SET; /**< Fault Status */ + __IM uint32_t FAULTADDR_SET; /**< Fault Address */ + __IOM uint32_t PROGRAMSTATE_SET; /**< Program State */ + MVP_ARRAYST_TypeDef ARRAYST_SET[5U]; /**< */ + MVP_LOOPST_TypeDef LOOPST_SET[8U]; /**< */ + MVP_ALU_TypeDef ALU_SET[8U]; /**< */ + MVP_ARRAY_TypeDef ARRAY_SET[5U]; /**< */ + MVP_LOOP_TypeDef LOOP_SET[8U]; /**< */ + MVP_INSTR_TypeDef INSTR_SET[8U]; /**< */ + __IOM uint32_t CMD_SET; /**< Command Register */ + uint32_t RESERVED2[34U]; /**< Reserved for future use */ + __IOM uint32_t DEBUGEN_SET; /**< Debug Enable Register */ + __IOM uint32_t DEBUGSTEPCNT_SET; /**< Debug Step Register */ + __IM uint32_t LOAD0ADDR_SET; /**< Array Address State */ + __IM uint32_t LOAD1ADDR_SET; /**< Array Address State */ + __IM uint32_t STOREADDR_SET; /**< Array Address State */ + uint32_t RESERVED3[891U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + __IOM uint32_t EN_CLR; /**< Enable */ + __IOM uint32_t SWRST_CLR; /**< Software Reset */ + __IOM uint32_t CFG_CLR; /**< Configuration */ + __IM uint32_t STATUS_CLR; /**< Status */ + MVP_PERF_TypeDef PERF_CLR[2U]; /**< */ + __IOM uint32_t IF_CLR; /**< Interrupt Flags */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enables */ + __IM uint32_t FAULTSTATUS_CLR; /**< Fault Status */ + __IM uint32_t FAULTADDR_CLR; /**< Fault Address */ + __IOM uint32_t PROGRAMSTATE_CLR; /**< Program State */ + MVP_ARRAYST_TypeDef ARRAYST_CLR[5U]; /**< */ + MVP_LOOPST_TypeDef LOOPST_CLR[8U]; /**< */ + MVP_ALU_TypeDef ALU_CLR[8U]; /**< */ + MVP_ARRAY_TypeDef ARRAY_CLR[5U]; /**< */ + MVP_LOOP_TypeDef LOOP_CLR[8U]; /**< */ + MVP_INSTR_TypeDef INSTR_CLR[8U]; /**< */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + uint32_t RESERVED4[34U]; /**< Reserved for future use */ + __IOM uint32_t DEBUGEN_CLR; /**< Debug Enable Register */ + __IOM uint32_t DEBUGSTEPCNT_CLR; /**< Debug Step Register */ + __IM uint32_t LOAD0ADDR_CLR; /**< Array Address State */ + __IM uint32_t LOAD1ADDR_CLR; /**< Array Address State */ + __IM uint32_t STOREADDR_CLR; /**< Array Address State */ + uint32_t RESERVED5[891U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ + __IOM uint32_t EN_TGL; /**< Enable */ + __IOM uint32_t SWRST_TGL; /**< Software Reset */ + __IOM uint32_t CFG_TGL; /**< Configuration */ + __IM uint32_t STATUS_TGL; /**< Status */ + MVP_PERF_TypeDef PERF_TGL[2U]; /**< */ + __IOM uint32_t IF_TGL; /**< Interrupt Flags */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enables */ + __IM uint32_t FAULTSTATUS_TGL; /**< Fault Status */ + __IM uint32_t FAULTADDR_TGL; /**< Fault Address */ + __IOM uint32_t PROGRAMSTATE_TGL; /**< Program State */ + MVP_ARRAYST_TypeDef ARRAYST_TGL[5U]; /**< */ + MVP_LOOPST_TypeDef LOOPST_TGL[8U]; /**< */ + MVP_ALU_TypeDef ALU_TGL[8U]; /**< */ + MVP_ARRAY_TypeDef ARRAY_TGL[5U]; /**< */ + MVP_LOOP_TypeDef LOOP_TGL[8U]; /**< */ + MVP_INSTR_TypeDef INSTR_TGL[8U]; /**< */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + uint32_t RESERVED6[34U]; /**< Reserved for future use */ + __IOM uint32_t DEBUGEN_TGL; /**< Debug Enable Register */ + __IOM uint32_t DEBUGSTEPCNT_TGL; /**< Debug Step Register */ + __IM uint32_t LOAD0ADDR_TGL; /**< Array Address State */ + __IM uint32_t LOAD1ADDR_TGL; /**< Array Address State */ + __IM uint32_t STOREADDR_TGL; /**< Array Address State */ +} MVP_TypeDef; +/** @} End of group SI91X_MVP */ + +/**************************************************************************/ /** + *****************************************************************************/ + +/* Bit fields for MVP IPVERSION */ +#define _MVP_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for MVP_IPVERSION */ +#define _MVP_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for MVP_IPVERSION */ +#define _MVP_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for MVP_IPVERSION */ +#define _MVP_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for MVP_IPVERSION */ +#define _MVP_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for MVP_IPVERSION */ +#define MVP_IPVERSION_IPVERSION_DEFAULT \ + (_MVP_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_IPVERSION */ + +/* Bit fields for MVP EN */ +#define _MVP_EN_RESETVALUE 0x00000000UL /**< Default value for MVP_EN */ +#define _MVP_EN_MASK 0x00000003UL /**< Mask for MVP_EN */ +#define MVP_EN_EN (0x1UL << 0) /**< Enable */ +#define _MVP_EN_EN_SHIFT 0 /**< Shift value for MVP_EN */ +#define _MVP_EN_EN_MASK 0x1UL /**< Bit mask for MVP_EN */ +#define _MVP_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_EN */ +#define MVP_EN_EN_DEFAULT (_MVP_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_EN */ +#define MVP_EN_DISABLING (0x1UL << 1) /**< Disablement Busy Status */ +#define _MVP_EN_DISABLING_SHIFT 1 /**< Shift value for MVP_DISABLING */ +#define _MVP_EN_DISABLING_MASK 0x2UL /**< Bit mask for MVP_DISABLING */ +#define _MVP_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_EN */ +#define MVP_EN_DISABLING_DEFAULT (_MVP_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_EN */ + +/* Bit fields for MVP SWRST */ +#define _MVP_SWRST_RESETVALUE 0x00000000UL /**< Default value for MVP_SWRST */ +#define _MVP_SWRST_MASK 0x00000003UL /**< Mask for MVP_SWRST */ +#define MVP_SWRST_SWRST (0x1UL << 0) /**< Software Reset Command */ +#define _MVP_SWRST_SWRST_SHIFT 0 /**< Shift value for MVP_SWRST */ +#define _MVP_SWRST_SWRST_MASK 0x1UL /**< Bit mask for MVP_SWRST */ +#define _MVP_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_SWRST */ +#define MVP_SWRST_SWRST_DEFAULT (_MVP_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_SWRST */ +#define MVP_SWRST_RESETTING (0x1UL << 1) /**< Software Reset Busy Status */ +#define _MVP_SWRST_RESETTING_SHIFT 1 /**< Shift value for MVP_RESETTING */ +#define _MVP_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for MVP_RESETTING */ +#define _MVP_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_SWRST */ +#define MVP_SWRST_RESETTING_DEFAULT \ + (_MVP_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_SWRST */ + +/* Bit fields for MVP CFG */ +#define _MVP_CFG_RESETVALUE 0x00000000UL /**< Default value for MVP_CFG */ +#define _MVP_CFG_MASK 0x00FF000FUL /**< Mask for MVP_CFG */ +#define MVP_CFG_PERFCNTEN (0x1UL << 0) /**< Performance Counter Enable */ +#define _MVP_CFG_PERFCNTEN_SHIFT 0 /**< Shift value for MVP_PERFCNTEN */ +#define _MVP_CFG_PERFCNTEN_MASK 0x1UL /**< Bit mask for MVP_PERFCNTEN */ +#define _MVP_CFG_PERFCNTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CFG */ +#define MVP_CFG_PERFCNTEN_DEFAULT (_MVP_CFG_PERFCNTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_CFG */ +#define MVP_CFG_OUTCOMPRESSDIS (0x1UL << 1) /**< ALU Output Stream Compression Disable */ +#define _MVP_CFG_OUTCOMPRESSDIS_SHIFT 1 /**< Shift value for MVP_OUTCOMPRESSDIS */ +#define _MVP_CFG_OUTCOMPRESSDIS_MASK 0x2UL /**< Bit mask for MVP_OUTCOMPRESSDIS */ +#define _MVP_CFG_OUTCOMPRESSDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CFG */ +#define MVP_CFG_OUTCOMPRESSDIS_DEFAULT \ + (_MVP_CFG_OUTCOMPRESSDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_CFG */ +#define MVP_CFG_INCACHEDIS (0x1UL << 2) /**< ALU Input Word Cache Disable */ +#define _MVP_CFG_INCACHEDIS_SHIFT 2 /**< Shift value for MVP_INCACHEDIS */ +#define _MVP_CFG_INCACHEDIS_MASK 0x4UL /**< Bit mask for MVP_INCACHEDIS */ +#define _MVP_CFG_INCACHEDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CFG */ +#define MVP_CFG_INCACHEDIS_DEFAULT \ + (_MVP_CFG_INCACHEDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_CFG */ +#define MVP_CFG_LOOPERRHALTDIS (0x1UL << 3) /**< Loop Error Halt Disable */ +#define _MVP_CFG_LOOPERRHALTDIS_SHIFT 3 /**< Shift value for MVP_LOOPERRHALTDIS */ +#define _MVP_CFG_LOOPERRHALTDIS_MASK 0x8UL /**< Bit mask for MVP_LOOPERRHALTDIS */ +#define _MVP_CFG_LOOPERRHALTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CFG */ +#define MVP_CFG_LOOPERRHALTDIS_DEFAULT \ + (_MVP_CFG_LOOPERRHALTDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_SHIFT 16 /**< Shift value for MVP_PERF0CNTSEL */ +#define _MVP_CFG_PERF0CNTSEL_MASK 0xF0000UL /**< Bit mask for MVP_PERF0CNTSEL */ +#define _MVP_CFG_PERF0CNTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_RUN 0x00000000UL /**< Mode RUN for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_CMD 0x00000001UL /**< Mode CMD for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_STALL 0x00000002UL /**< Mode STALL for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_NOOP 0x00000003UL /**< Mode NOOP for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_ALUACTIVE 0x00000004UL /**< Mode ALUACTIVE for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_PIPESTALL 0x00000005UL /**< Mode PIPESTALL for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_IOFENCESTALL 0x00000006UL /**< Mode IOFENCESTALL for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_LOAD0STALL 0x00000007UL /**< Mode LOAD0STALL for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_LOAD1STALL 0x00000008UL /**< Mode LOAD1STALL for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_STORESTALL 0x00000009UL /**< Mode STORESTALL for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_BUSSTALL 0x0000000AUL /**< Mode BUSSTALL for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_LOAD0AHBSTALL 0x0000000BUL /**< Mode LOAD0AHBSTALL for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_LOAD1AHBSTALL 0x0000000CUL /**< Mode LOAD1AHBSTALL for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_LOAD0FENCESTALL 0x0000000DUL /**< Mode LOAD0FENCESTALL for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_LOAD1FENCESTALL 0x0000000EUL /**< Mode LOAD1FENCESTALL for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_DEFAULT \ + (_MVP_CFG_PERF0CNTSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_RUN (_MVP_CFG_PERF0CNTSEL_RUN << 16) /**< Shifted mode RUN for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_CMD (_MVP_CFG_PERF0CNTSEL_CMD << 16) /**< Shifted mode CMD for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_STALL (_MVP_CFG_PERF0CNTSEL_STALL << 16) /**< Shifted mode STALL for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_NOOP (_MVP_CFG_PERF0CNTSEL_NOOP << 16) /**< Shifted mode NOOP for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_ALUACTIVE \ + (_MVP_CFG_PERF0CNTSEL_ALUACTIVE << 16) /**< Shifted mode ALUACTIVE for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_PIPESTALL \ + (_MVP_CFG_PERF0CNTSEL_PIPESTALL << 16) /**< Shifted mode PIPESTALL for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_IOFENCESTALL \ + (_MVP_CFG_PERF0CNTSEL_IOFENCESTALL << 16) /**< Shifted mode IOFENCESTALL for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_LOAD0STALL \ + (_MVP_CFG_PERF0CNTSEL_LOAD0STALL << 16) /**< Shifted mode LOAD0STALL for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_LOAD1STALL \ + (_MVP_CFG_PERF0CNTSEL_LOAD1STALL << 16) /**< Shifted mode LOAD1STALL for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_STORESTALL \ + (_MVP_CFG_PERF0CNTSEL_STORESTALL << 16) /**< Shifted mode STORESTALL for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_BUSSTALL \ + (_MVP_CFG_PERF0CNTSEL_BUSSTALL << 16) /**< Shifted mode BUSSTALL for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_LOAD0AHBSTALL \ + (_MVP_CFG_PERF0CNTSEL_LOAD0AHBSTALL << 16) /**< Shifted mode LOAD0AHBSTALL for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_LOAD1AHBSTALL \ + (_MVP_CFG_PERF0CNTSEL_LOAD1AHBSTALL << 16) /**< Shifted mode LOAD1AHBSTALL for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_LOAD0FENCESTALL \ + (_MVP_CFG_PERF0CNTSEL_LOAD0FENCESTALL << 16) /**< Shifted mode LOAD0FENCESTALL for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_LOAD1FENCESTALL \ + (_MVP_CFG_PERF0CNTSEL_LOAD1FENCESTALL << 16) /**< Shifted mode LOAD1FENCESTALL for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_SHIFT 20 /**< Shift value for MVP_PERF1CNTSEL */ +#define _MVP_CFG_PERF1CNTSEL_MASK 0xF00000UL /**< Bit mask for MVP_PERF1CNTSEL */ +#define _MVP_CFG_PERF1CNTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_RUN 0x00000000UL /**< Mode RUN for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_CMD 0x00000001UL /**< Mode CMD for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_STALL 0x00000002UL /**< Mode STALL for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_NOOP 0x00000003UL /**< Mode NOOP for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_ALUACTIVE 0x00000004UL /**< Mode ALUACTIVE for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_PIPESTALL 0x00000005UL /**< Mode PIPESTALL for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_IOFENCESTALL 0x00000006UL /**< Mode IOFENCESTALL for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_LOAD0STALL 0x00000007UL /**< Mode LOAD0STALL for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_LOAD1STALL 0x00000008UL /**< Mode LOAD1STALL for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_STORESTALL 0x00000009UL /**< Mode STORESTALL for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_BUSSTALL 0x0000000AUL /**< Mode BUSSTALL for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_LOAD0AHBSTALL 0x0000000BUL /**< Mode LOAD0AHBSTALL for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_LOAD1AHBSTALL 0x0000000CUL /**< Mode LOAD1AHBSTALL for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_LOAD0FENCESTALL 0x0000000DUL /**< Mode LOAD0FENCESTALL for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_LOAD1FENCESTALL 0x0000000EUL /**< Mode LOAD1FENCESTALL for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_DEFAULT \ + (_MVP_CFG_PERF1CNTSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_RUN (_MVP_CFG_PERF1CNTSEL_RUN << 20) /**< Shifted mode RUN for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_CMD (_MVP_CFG_PERF1CNTSEL_CMD << 20) /**< Shifted mode CMD for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_STALL (_MVP_CFG_PERF1CNTSEL_STALL << 20) /**< Shifted mode STALL for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_NOOP (_MVP_CFG_PERF1CNTSEL_NOOP << 20) /**< Shifted mode NOOP for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_ALUACTIVE \ + (_MVP_CFG_PERF1CNTSEL_ALUACTIVE << 20) /**< Shifted mode ALUACTIVE for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_PIPESTALL \ + (_MVP_CFG_PERF1CNTSEL_PIPESTALL << 20) /**< Shifted mode PIPESTALL for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_IOFENCESTALL \ + (_MVP_CFG_PERF1CNTSEL_IOFENCESTALL << 20) /**< Shifted mode IOFENCESTALL for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_LOAD0STALL \ + (_MVP_CFG_PERF1CNTSEL_LOAD0STALL << 20) /**< Shifted mode LOAD0STALL for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_LOAD1STALL \ + (_MVP_CFG_PERF1CNTSEL_LOAD1STALL << 20) /**< Shifted mode LOAD1STALL for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_STORESTALL \ + (_MVP_CFG_PERF1CNTSEL_STORESTALL << 20) /**< Shifted mode STORESTALL for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_BUSSTALL \ + (_MVP_CFG_PERF1CNTSEL_BUSSTALL << 20) /**< Shifted mode BUSSTALL for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_LOAD0AHBSTALL \ + (_MVP_CFG_PERF1CNTSEL_LOAD0AHBSTALL << 20) /**< Shifted mode LOAD0AHBSTALL for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_LOAD1AHBSTALL \ + (_MVP_CFG_PERF1CNTSEL_LOAD1AHBSTALL << 20) /**< Shifted mode LOAD1AHBSTALL for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_LOAD0FENCESTALL \ + (_MVP_CFG_PERF1CNTSEL_LOAD0FENCESTALL << 20) /**< Shifted mode LOAD0FENCESTALL for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_LOAD1FENCESTALL \ + (_MVP_CFG_PERF1CNTSEL_LOAD1FENCESTALL << 20) /**< Shifted mode LOAD1FENCESTALL for MVP_CFG */ + +/* Bit fields for MVP STATUS */ +#define _MVP_STATUS_RESETVALUE 0x00000004UL /**< Default value for MVP_STATUS */ +#define _MVP_STATUS_MASK 0x00000007UL /**< Mask for MVP_STATUS */ +#define MVP_STATUS_RUNNING (0x1UL << 0) /**< Running Status */ +#define _MVP_STATUS_RUNNING_SHIFT 0 /**< Shift value for MVP_RUNNING */ +#define _MVP_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for MVP_RUNNING */ +#define _MVP_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_STATUS */ +#define MVP_STATUS_RUNNING_DEFAULT \ + (_MVP_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_STATUS */ +#define MVP_STATUS_PAUSED (0x1UL << 1) /**< Paused Status */ +#define _MVP_STATUS_PAUSED_SHIFT 1 /**< Shift value for MVP_PAUSED */ +#define _MVP_STATUS_PAUSED_MASK 0x2UL /**< Bit mask for MVP_PAUSED */ +#define _MVP_STATUS_PAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_STATUS */ +#define MVP_STATUS_PAUSED_DEFAULT (_MVP_STATUS_PAUSED_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_STATUS */ +#define MVP_STATUS_IDLE (0x1UL << 2) /**< Idle Status */ +#define _MVP_STATUS_IDLE_SHIFT 2 /**< Shift value for MVP_IDLE */ +#define _MVP_STATUS_IDLE_MASK 0x4UL /**< Bit mask for MVP_IDLE */ +#define _MVP_STATUS_IDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MVP_STATUS */ +#define MVP_STATUS_IDLE_DEFAULT (_MVP_STATUS_IDLE_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_STATUS */ + +/* Bit fields for MVP PERFCNT */ +#define _MVP_PERFCNT_RESETVALUE 0x00000000UL /**< Default value for MVP_PERFCNT */ +#define _MVP_PERFCNT_MASK 0x00FFFFFFUL /**< Mask for MVP_PERFCNT */ +#define _MVP_PERFCNT_COUNT_SHIFT 0 /**< Shift value for MVP_COUNT */ +#define _MVP_PERFCNT_COUNT_MASK 0xFFFFFFUL /**< Bit mask for MVP_COUNT */ +#define _MVP_PERFCNT_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_PERFCNT */ +#define MVP_PERFCNT_COUNT_DEFAULT (_MVP_PERFCNT_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_PERFCNT */ + +/* Bit fields for MVP IF */ +#define _MVP_IF_RESETVALUE 0x00000000UL /**< Default value for MVP_IF */ +#define _MVP_IF_MASK 0x1F0FFDFFUL /**< Mask for MVP_IF */ +#define MVP_IF_PROGDONE (0x1UL << 0) /**< Program Done Interrupt Flags */ +#define _MVP_IF_PROGDONE_SHIFT 0 /**< Shift value for MVP_PROGDONE */ +#define _MVP_IF_PROGDONE_MASK 0x1UL /**< Bit mask for MVP_PROGDONE */ +#define _MVP_IF_PROGDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_PROGDONE_DEFAULT (_MVP_IF_PROGDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP0DONE (0x1UL << 1) /**< Loop Done Interrupt Flag */ +#define _MVP_IF_LOOP0DONE_SHIFT 1 /**< Shift value for MVP_LOOP0DONE */ +#define _MVP_IF_LOOP0DONE_MASK 0x2UL /**< Bit mask for MVP_LOOP0DONE */ +#define _MVP_IF_LOOP0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP0DONE_DEFAULT (_MVP_IF_LOOP0DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP1DONE (0x1UL << 2) /**< Loop Done Interrupt Flag */ +#define _MVP_IF_LOOP1DONE_SHIFT 2 /**< Shift value for MVP_LOOP1DONE */ +#define _MVP_IF_LOOP1DONE_MASK 0x4UL /**< Bit mask for MVP_LOOP1DONE */ +#define _MVP_IF_LOOP1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP1DONE_DEFAULT (_MVP_IF_LOOP1DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP2DONE (0x1UL << 3) /**< Loop Done Interrupt Flag */ +#define _MVP_IF_LOOP2DONE_SHIFT 3 /**< Shift value for MVP_LOOP2DONE */ +#define _MVP_IF_LOOP2DONE_MASK 0x8UL /**< Bit mask for MVP_LOOP2DONE */ +#define _MVP_IF_LOOP2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP2DONE_DEFAULT (_MVP_IF_LOOP2DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP3DONE (0x1UL << 4) /**< Loop Done Interrupt Flag */ +#define _MVP_IF_LOOP3DONE_SHIFT 4 /**< Shift value for MVP_LOOP3DONE */ +#define _MVP_IF_LOOP3DONE_MASK 0x10UL /**< Bit mask for MVP_LOOP3DONE */ +#define _MVP_IF_LOOP3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP3DONE_DEFAULT (_MVP_IF_LOOP3DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP4DONE (0x1UL << 5) /**< Loop Done Interrupt Flag */ +#define _MVP_IF_LOOP4DONE_SHIFT 5 /**< Shift value for MVP_LOOP4DONE */ +#define _MVP_IF_LOOP4DONE_MASK 0x20UL /**< Bit mask for MVP_LOOP4DONE */ +#define _MVP_IF_LOOP4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP4DONE_DEFAULT (_MVP_IF_LOOP4DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP5DONE (0x1UL << 6) /**< Loop Done Interrupt Flag */ +#define _MVP_IF_LOOP5DONE_SHIFT 6 /**< Shift value for MVP_LOOP5DONE */ +#define _MVP_IF_LOOP5DONE_MASK 0x40UL /**< Bit mask for MVP_LOOP5DONE */ +#define _MVP_IF_LOOP5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP5DONE_DEFAULT (_MVP_IF_LOOP5DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP6DONE (0x1UL << 7) /**< Loop Done Interrupt Flag */ +#define _MVP_IF_LOOP6DONE_SHIFT 7 /**< Shift value for MVP_LOOP6DONE */ +#define _MVP_IF_LOOP6DONE_MASK 0x80UL /**< Bit mask for MVP_LOOP6DONE */ +#define _MVP_IF_LOOP6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP6DONE_DEFAULT (_MVP_IF_LOOP6DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP7DONE (0x1UL << 8) /**< Loop Done Interrupt Flag */ +#define _MVP_IF_LOOP7DONE_SHIFT 8 /**< Shift value for MVP_LOOP7DONE */ +#define _MVP_IF_LOOP7DONE_MASK 0x100UL /**< Bit mask for MVP_LOOP7DONE */ +#define _MVP_IF_LOOP7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP7DONE_DEFAULT (_MVP_IF_LOOP7DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_ALUNAN (0x1UL << 10) /**< Not-a-Number Interrupt Flag */ +#define _MVP_IF_ALUNAN_SHIFT 10 /**< Shift value for MVP_ALUNAN */ +#define _MVP_IF_ALUNAN_MASK 0x400UL /**< Bit mask for MVP_ALUNAN */ +#define _MVP_IF_ALUNAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_ALUNAN_DEFAULT (_MVP_IF_ALUNAN_DEFAULT << 10) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_R0POSREAL (0x1UL << 11) /**< R0 non-zero Interrupt Flag */ +#define _MVP_IF_R0POSREAL_SHIFT 11 /**< Shift value for MVP_R0POSREAL */ +#define _MVP_IF_R0POSREAL_MASK 0x800UL /**< Bit mask for MVP_R0POSREAL */ +#define _MVP_IF_R0POSREAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_R0POSREAL_DEFAULT (_MVP_IF_R0POSREAL_DEFAULT << 11) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_ALUOF (0x1UL << 12) /**< ALU Overflow on result */ +#define _MVP_IF_ALUOF_SHIFT 12 /**< Shift value for MVP_ALUOF */ +#define _MVP_IF_ALUOF_MASK 0x1000UL /**< Bit mask for MVP_ALUOF */ +#define _MVP_IF_ALUOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_ALUOF_DEFAULT (_MVP_IF_ALUOF_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_ALUUF (0x1UL << 13) /**< ALU Underflow on result */ +#define _MVP_IF_ALUUF_SHIFT 13 /**< Shift value for MVP_ALUUF */ +#define _MVP_IF_ALUUF_MASK 0x2000UL /**< Bit mask for MVP_ALUUF */ +#define _MVP_IF_ALUUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_ALUUF_DEFAULT (_MVP_IF_ALUUF_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_STORECONVERTOF (0x1UL << 14) /**< Overflow during array store */ +#define _MVP_IF_STORECONVERTOF_SHIFT 14 /**< Shift value for MVP_STORECONVERTOF */ +#define _MVP_IF_STORECONVERTOF_MASK 0x4000UL /**< Bit mask for MVP_STORECONVERTOF */ +#define _MVP_IF_STORECONVERTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_STORECONVERTOF_DEFAULT \ + (_MVP_IF_STORECONVERTOF_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_STORECONVERTUF (0x1UL << 15) /**< Underflow during array store conversion */ +#define _MVP_IF_STORECONVERTUF_SHIFT 15 /**< Shift value for MVP_STORECONVERTUF */ +#define _MVP_IF_STORECONVERTUF_MASK 0x8000UL /**< Bit mask for MVP_STORECONVERTUF */ +#define _MVP_IF_STORECONVERTUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_STORECONVERTUF_DEFAULT \ + (_MVP_IF_STORECONVERTUF_DEFAULT << 15) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_STORECONVERTINF (0x1UL << 16) /**< Infinity encountered during array store conversion*/ +#define _MVP_IF_STORECONVERTINF_SHIFT 16 /**< Shift value for MVP_STORECONVERTINF */ +#define _MVP_IF_STORECONVERTINF_MASK 0x10000UL /**< Bit mask for MVP_STORECONVERTINF */ +#define _MVP_IF_STORECONVERTINF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_STORECONVERTINF_DEFAULT \ + (_MVP_IF_STORECONVERTINF_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_STORECONVERTNAN (0x1UL << 17) /**< NaN encountered during array store conversion*/ +#define _MVP_IF_STORECONVERTNAN_SHIFT 17 /**< Shift value for MVP_STORECONVERTNAN */ +#define _MVP_IF_STORECONVERTNAN_MASK 0x20000UL /**< Bit mask for MVP_STORECONVERTNAN */ +#define _MVP_IF_STORECONVERTNAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_STORECONVERTNAN_DEFAULT \ + (_MVP_IF_STORECONVERTNAN_DEFAULT << 17) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_PERFCNT0 (0x1UL << 18) /**< Run Count Overflow Interrupt Flag */ +#define _MVP_IF_PERFCNT0_SHIFT 18 /**< Shift value for MVP_PERFCNT0 */ +#define _MVP_IF_PERFCNT0_MASK 0x40000UL /**< Bit mask for MVP_PERFCNT0 */ +#define _MVP_IF_PERFCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_PERFCNT0_DEFAULT (_MVP_IF_PERFCNT0_DEFAULT << 18) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_PERFCNT1 (0x1UL << 19) /**< Stall Count Overflow Interrupt Flag */ +#define _MVP_IF_PERFCNT1_SHIFT 19 /**< Shift value for MVP_PERFCNT1 */ +#define _MVP_IF_PERFCNT1_MASK 0x80000UL /**< Bit mask for MVP_PERFCNT1 */ +#define _MVP_IF_PERFCNT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_PERFCNT1_DEFAULT (_MVP_IF_PERFCNT1_DEFAULT << 19) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOPFAULT (0x1UL << 24) /**< Loop Fault Interrupt Flag */ +#define _MVP_IF_LOOPFAULT_SHIFT 24 /**< Shift value for MVP_LOOPFAULT */ +#define _MVP_IF_LOOPFAULT_MASK 0x1000000UL /**< Bit mask for MVP_LOOPFAULT */ +#define _MVP_IF_LOOPFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOPFAULT_DEFAULT (_MVP_IF_LOOPFAULT_DEFAULT << 24) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_BUSERRFAULT (0x1UL << 25) /**< Bus Error Fault Interrupt Flag */ +#define _MVP_IF_BUSERRFAULT_SHIFT 25 /**< Shift value for MVP_BUSERRFAULT */ +#define _MVP_IF_BUSERRFAULT_MASK 0x2000000UL /**< Bit mask for MVP_BUSERRFAULT */ +#define _MVP_IF_BUSERRFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_BUSERRFAULT_DEFAULT \ + (_MVP_IF_BUSERRFAULT_DEFAULT << 25) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_BUSALIGNFAULT (0x1UL << 26) /**< Bus Alignment Fault Interrupt Flag */ +#define _MVP_IF_BUSALIGNFAULT_SHIFT 26 /**< Shift value for MVP_BUSALIGNFAULT */ +#define _MVP_IF_BUSALIGNFAULT_MASK 0x4000000UL /**< Bit mask for MVP_BUSALIGNFAULT */ +#define _MVP_IF_BUSALIGNFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_BUSALIGNFAULT_DEFAULT \ + (_MVP_IF_BUSALIGNFAULT_DEFAULT << 26) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_ALUFAULT (0x1UL << 27) /**< ALU Fault Interrupt Flag */ +#define _MVP_IF_ALUFAULT_SHIFT 27 /**< Shift value for MVP_ALUFAULT */ +#define _MVP_IF_ALUFAULT_MASK 0x8000000UL /**< Bit mask for MVP_ALUFAULT */ +#define _MVP_IF_ALUFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_ALUFAULT_DEFAULT (_MVP_IF_ALUFAULT_DEFAULT << 27) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_ARRAYFAULT (0x1UL << 28) /**< Array Fault Interrupt Flag */ +#define _MVP_IF_ARRAYFAULT_SHIFT 28 /**< Shift value for MVP_ARRAYFAULT */ +#define _MVP_IF_ARRAYFAULT_MASK 0x10000000UL /**< Bit mask for MVP_ARRAYFAULT */ +#define _MVP_IF_ARRAYFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_ARRAYFAULT_DEFAULT (_MVP_IF_ARRAYFAULT_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_IF */ + +/* Bit fields for MVP IEN */ +#define _MVP_IEN_RESETVALUE 0x00000000UL /**< Default value for MVP_IEN */ +#define _MVP_IEN_MASK 0x1F0FFDFFUL /**< Mask for MVP_IEN */ +#define MVP_IEN_PROGDONE (0x1UL << 0) /**< Program Done Interrupt Enable */ +#define _MVP_IEN_PROGDONE_SHIFT 0 /**< Shift value for MVP_PROGDONE */ +#define _MVP_IEN_PROGDONE_MASK 0x1UL /**< Bit mask for MVP_PROGDONE */ +#define _MVP_IEN_PROGDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_PROGDONE_DEFAULT (_MVP_IEN_PROGDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP0DONE (0x1UL << 1) /**< Loop Done Interrupt Enable */ +#define _MVP_IEN_LOOP0DONE_SHIFT 1 /**< Shift value for MVP_LOOP0DONE */ +#define _MVP_IEN_LOOP0DONE_MASK 0x2UL /**< Bit mask for MVP_LOOP0DONE */ +#define _MVP_IEN_LOOP0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP0DONE_DEFAULT (_MVP_IEN_LOOP0DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP1DONE (0x1UL << 2) /**< Loop Done Interrupt Enable */ +#define _MVP_IEN_LOOP1DONE_SHIFT 2 /**< Shift value for MVP_LOOP1DONE */ +#define _MVP_IEN_LOOP1DONE_MASK 0x4UL /**< Bit mask for MVP_LOOP1DONE */ +#define _MVP_IEN_LOOP1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP1DONE_DEFAULT (_MVP_IEN_LOOP1DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP2DONE (0x1UL << 3) /**< Loop Done Interrupt Enable */ +#define _MVP_IEN_LOOP2DONE_SHIFT 3 /**< Shift value for MVP_LOOP2DONE */ +#define _MVP_IEN_LOOP2DONE_MASK 0x8UL /**< Bit mask for MVP_LOOP2DONE */ +#define _MVP_IEN_LOOP2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP2DONE_DEFAULT (_MVP_IEN_LOOP2DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP3DONE (0x1UL << 4) /**< Loop Done Interrupt Enable */ +#define _MVP_IEN_LOOP3DONE_SHIFT 4 /**< Shift value for MVP_LOOP3DONE */ +#define _MVP_IEN_LOOP3DONE_MASK 0x10UL /**< Bit mask for MVP_LOOP3DONE */ +#define _MVP_IEN_LOOP3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP3DONE_DEFAULT (_MVP_IEN_LOOP3DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP4DONE (0x1UL << 5) /**< Loop Done Interrupt Enable */ +#define _MVP_IEN_LOOP4DONE_SHIFT 5 /**< Shift value for MVP_LOOP4DONE */ +#define _MVP_IEN_LOOP4DONE_MASK 0x20UL /**< Bit mask for MVP_LOOP4DONE */ +#define _MVP_IEN_LOOP4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP4DONE_DEFAULT (_MVP_IEN_LOOP4DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP5DONE (0x1UL << 6) /**< Loop Done Interrupt Enable */ +#define _MVP_IEN_LOOP5DONE_SHIFT 6 /**< Shift value for MVP_LOOP5DONE */ +#define _MVP_IEN_LOOP5DONE_MASK 0x40UL /**< Bit mask for MVP_LOOP5DONE */ +#define _MVP_IEN_LOOP5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP5DONE_DEFAULT (_MVP_IEN_LOOP5DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP6DONE (0x1UL << 7) /**< Loop Done Interrupt Enable */ +#define _MVP_IEN_LOOP6DONE_SHIFT 7 /**< Shift value for MVP_LOOP6DONE */ +#define _MVP_IEN_LOOP6DONE_MASK 0x80UL /**< Bit mask for MVP_LOOP6DONE */ +#define _MVP_IEN_LOOP6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP6DONE_DEFAULT (_MVP_IEN_LOOP6DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP7DONE (0x1UL << 8) /**< Loop Done Interrupt Enable */ +#define _MVP_IEN_LOOP7DONE_SHIFT 8 /**< Shift value for MVP_LOOP7DONE */ +#define _MVP_IEN_LOOP7DONE_MASK 0x100UL /**< Bit mask for MVP_LOOP7DONE */ +#define _MVP_IEN_LOOP7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP7DONE_DEFAULT (_MVP_IEN_LOOP7DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_ALUNAN (0x1UL << 10) /**< Not-a-Number Interrupt Enable */ +#define _MVP_IEN_ALUNAN_SHIFT 10 /**< Shift value for MVP_ALUNAN */ +#define _MVP_IEN_ALUNAN_MASK 0x400UL /**< Bit mask for MVP_ALUNAN */ +#define _MVP_IEN_ALUNAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_ALUNAN_DEFAULT (_MVP_IEN_ALUNAN_DEFAULT << 10) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_R0POSREAL (0x1UL << 11) /**< R0 Non-Zero Interrupt Enable */ +#define _MVP_IEN_R0POSREAL_SHIFT 11 /**< Shift value for MVP_R0POSREAL */ +#define _MVP_IEN_R0POSREAL_MASK 0x800UL /**< Bit mask for MVP_R0POSREAL */ +#define _MVP_IEN_R0POSREAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_R0POSREAL_DEFAULT (_MVP_IEN_R0POSREAL_DEFAULT << 11) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_ALUOF (0x1UL << 12) /**< ALU Overflow Interrupt Enable */ +#define _MVP_IEN_ALUOF_SHIFT 12 /**< Shift value for MVP_ALUOF */ +#define _MVP_IEN_ALUOF_MASK 0x1000UL /**< Bit mask for MVP_ALUOF */ +#define _MVP_IEN_ALUOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_ALUOF_DEFAULT (_MVP_IEN_ALUOF_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_ALUUF (0x1UL << 13) /**< ALU Underflow Interrupt Enable */ +#define _MVP_IEN_ALUUF_SHIFT 13 /**< Shift value for MVP_ALUUF */ +#define _MVP_IEN_ALUUF_MASK 0x2000UL /**< Bit mask for MVP_ALUUF */ +#define _MVP_IEN_ALUUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_ALUUF_DEFAULT (_MVP_IEN_ALUUF_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_STORECONVERTOF (0x1UL << 14) /**< Store conversion Overflow Interrupt Enable */ +#define _MVP_IEN_STORECONVERTOF_SHIFT 14 /**< Shift value for MVP_STORECONVERTOF */ +#define _MVP_IEN_STORECONVERTOF_MASK 0x4000UL /**< Bit mask for MVP_STORECONVERTOF */ +#define _MVP_IEN_STORECONVERTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_STORECONVERTOF_DEFAULT \ + (_MVP_IEN_STORECONVERTOF_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_STORECONVERTUF (0x1UL << 15) /**< Store Conversion Underflow Interrupt Enable */ +#define _MVP_IEN_STORECONVERTUF_SHIFT 15 /**< Shift value for MVP_STORECONVERTUF */ +#define _MVP_IEN_STORECONVERTUF_MASK 0x8000UL /**< Bit mask for MVP_STORECONVERTUF */ +#define _MVP_IEN_STORECONVERTUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_STORECONVERTUF_DEFAULT \ + (_MVP_IEN_STORECONVERTUF_DEFAULT << 15) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_STORECONVERTINF (0x1UL << 16) /**< Store Conversion Infinity Interrupt Enable */ +#define _MVP_IEN_STORECONVERTINF_SHIFT 16 /**< Shift value for MVP_STORECONVERTINF */ +#define _MVP_IEN_STORECONVERTINF_MASK 0x10000UL /**< Bit mask for MVP_STORECONVERTINF */ +#define _MVP_IEN_STORECONVERTINF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_STORECONVERTINF_DEFAULT \ + (_MVP_IEN_STORECONVERTINF_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_STORECONVERTNAN (0x1UL << 17) /**< Store Conversion NaN Interrupt Enable */ +#define _MVP_IEN_STORECONVERTNAN_SHIFT 17 /**< Shift value for MVP_STORECONVERTNAN */ +#define _MVP_IEN_STORECONVERTNAN_MASK 0x20000UL /**< Bit mask for MVP_STORECONVERTNAN */ +#define _MVP_IEN_STORECONVERTNAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_STORECONVERTNAN_DEFAULT \ + (_MVP_IEN_STORECONVERTNAN_DEFAULT << 17) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_PERFCNT0 (0x1UL << 18) /**< Perf Counter 0 Overflow Interrupt Enable */ +#define _MVP_IEN_PERFCNT0_SHIFT 18 /**< Shift value for MVP_PERFCNT0 */ +#define _MVP_IEN_PERFCNT0_MASK 0x40000UL /**< Bit mask for MVP_PERFCNT0 */ +#define _MVP_IEN_PERFCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_PERFCNT0_DEFAULT (_MVP_IEN_PERFCNT0_DEFAULT << 18) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_PERFCNT1 (0x1UL << 19) /**< Perf Counter 1 Overflow Interrupt Enable */ +#define _MVP_IEN_PERFCNT1_SHIFT 19 /**< Shift value for MVP_PERFCNT1 */ +#define _MVP_IEN_PERFCNT1_MASK 0x80000UL /**< Bit mask for MVP_PERFCNT1 */ +#define _MVP_IEN_PERFCNT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_PERFCNT1_DEFAULT (_MVP_IEN_PERFCNT1_DEFAULT << 19) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOPFAULT (0x1UL << 24) /**< Loop Fault Interrupt Enable */ +#define _MVP_IEN_LOOPFAULT_SHIFT 24 /**< Shift value for MVP_LOOPFAULT */ +#define _MVP_IEN_LOOPFAULT_MASK 0x1000000UL /**< Bit mask for MVP_LOOPFAULT */ +#define _MVP_IEN_LOOPFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOPFAULT_DEFAULT (_MVP_IEN_LOOPFAULT_DEFAULT << 24) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_BUSERRFAULT (0x1UL << 25) /**< Bus Error Fault Interrupt Enable */ +#define _MVP_IEN_BUSERRFAULT_SHIFT 25 /**< Shift value for MVP_BUSERRFAULT */ +#define _MVP_IEN_BUSERRFAULT_MASK 0x2000000UL /**< Bit mask for MVP_BUSERRFAULT */ +#define _MVP_IEN_BUSERRFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_BUSERRFAULT_DEFAULT \ + (_MVP_IEN_BUSERRFAULT_DEFAULT << 25) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_BUSALIGNFAULT (0x1UL << 26) /**< Bus Alignment Fault Interrupt Enable */ +#define _MVP_IEN_BUSALIGNFAULT_SHIFT 26 /**< Shift value for MVP_BUSALIGNFAULT */ +#define _MVP_IEN_BUSALIGNFAULT_MASK 0x4000000UL /**< Bit mask for MVP_BUSALIGNFAULT */ +#define _MVP_IEN_BUSALIGNFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_BUSALIGNFAULT_DEFAULT \ + (_MVP_IEN_BUSALIGNFAULT_DEFAULT << 26) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_ALUFAULT (0x1UL << 27) /**< ALU Input Fault Interrupt Enable */ +#define _MVP_IEN_ALUFAULT_SHIFT 27 /**< Shift value for MVP_ALUFAULT */ +#define _MVP_IEN_ALUFAULT_MASK 0x8000000UL /**< Bit mask for MVP_ALUFAULT */ +#define _MVP_IEN_ALUFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_ALUFAULT_DEFAULT (_MVP_IEN_ALUFAULT_DEFAULT << 27) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_ARRAYFAULT (0x1UL << 28) /**< Array Fault Interrupt Enable */ +#define _MVP_IEN_ARRAYFAULT_SHIFT 28 /**< Shift value for MVP_ARRAYFAULT */ +#define _MVP_IEN_ARRAYFAULT_MASK 0x10000000UL /**< Bit mask for MVP_ARRAYFAULT */ +#define _MVP_IEN_ARRAYFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_ARRAYFAULT_DEFAULT \ + (_MVP_IEN_ARRAYFAULT_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_IEN */ + +/* Bit fields for MVP FAULTSTATUS */ +#define _MVP_FAULTSTATUS_RESETVALUE 0x00000000UL /**< Default value for MVP_FAULTSTATUS */ +#define _MVP_FAULTSTATUS_MASK 0x000F3707UL /**< Mask for MVP_FAULTSTATUS */ +#define _MVP_FAULTSTATUS_FAULTPC_SHIFT 0 /**< Shift value for MVP_FAULTPC */ +#define _MVP_FAULTSTATUS_FAULTPC_MASK 0x7UL /**< Bit mask for MVP_FAULTPC */ +#define _MVP_FAULTSTATUS_FAULTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_FAULTSTATUS */ +#define MVP_FAULTSTATUS_FAULTPC_DEFAULT \ + (_MVP_FAULTSTATUS_FAULTPC_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_FAULTSTATUS */ +#define _MVP_FAULTSTATUS_FAULTARRAY_SHIFT 8 /**< Shift value for MVP_FAULTARRAY */ +#define _MVP_FAULTSTATUS_FAULTARRAY_MASK 0x700UL /**< Bit mask for MVP_FAULTARRAY */ +#define _MVP_FAULTSTATUS_FAULTARRAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_FAULTSTATUS */ +#define MVP_FAULTSTATUS_FAULTARRAY_DEFAULT \ + (_MVP_FAULTSTATUS_FAULTARRAY_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_FAULTSTATUS */ +#define _MVP_FAULTSTATUS_FAULTBUS_SHIFT 12 /**< Shift value for MVP_FAULTBUS */ +#define _MVP_FAULTSTATUS_FAULTBUS_MASK 0x3000UL /**< Bit mask for MVP_FAULTBUS */ +#define _MVP_FAULTSTATUS_FAULTBUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_FAULTSTATUS */ +#define _MVP_FAULTSTATUS_FAULTBUS_NONE 0x00000000UL /**< Mode NONE for MVP_FAULTSTATUS */ +#define _MVP_FAULTSTATUS_FAULTBUS_LOAD0STREAM 0x00000001UL /**< Mode LOAD0STREAM for MVP_FAULTSTATUS */ +#define _MVP_FAULTSTATUS_FAULTBUS_LOAD1STREAM 0x00000002UL /**< Mode LOAD1STREAM for MVP_FAULTSTATUS */ +#define _MVP_FAULTSTATUS_FAULTBUS_STORESTREAM 0x00000003UL /**< Mode STORESTREAM for MVP_FAULTSTATUS */ +#define MVP_FAULTSTATUS_FAULTBUS_DEFAULT \ + (_MVP_FAULTSTATUS_FAULTBUS_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_FAULTSTATUS */ +#define MVP_FAULTSTATUS_FAULTBUS_NONE \ + (_MVP_FAULTSTATUS_FAULTBUS_NONE << 12) /**< Shifted mode NONE for MVP_FAULTSTATUS */ +#define MVP_FAULTSTATUS_FAULTBUS_LOAD0STREAM \ + (_MVP_FAULTSTATUS_FAULTBUS_LOAD0STREAM << 12) /**< Shifted mode LOAD0STREAM for MVP_FAULTSTATUS*/ +#define MVP_FAULTSTATUS_FAULTBUS_LOAD1STREAM \ + (_MVP_FAULTSTATUS_FAULTBUS_LOAD1STREAM << 12) /**< Shifted mode LOAD1STREAM for MVP_FAULTSTATUS*/ +#define MVP_FAULTSTATUS_FAULTBUS_STORESTREAM \ + (_MVP_FAULTSTATUS_FAULTBUS_STORESTREAM << 12) /**< Shifted mode STORESTREAM for MVP_FAULTSTATUS*/ +#define _MVP_FAULTSTATUS_FAULTLOOP_SHIFT 16 /**< Shift value for MVP_FAULTLOOP */ +#define _MVP_FAULTSTATUS_FAULTLOOP_MASK 0xF0000UL /**< Bit mask for MVP_FAULTLOOP */ +#define _MVP_FAULTSTATUS_FAULTLOOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_FAULTSTATUS */ +#define MVP_FAULTSTATUS_FAULTLOOP_DEFAULT \ + (_MVP_FAULTSTATUS_FAULTLOOP_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_FAULTSTATUS */ + +/* Bit fields for MVP FAULTADDR */ +#define _MVP_FAULTADDR_RESETVALUE 0x00000000UL /**< Default value for MVP_FAULTADDR */ +#define _MVP_FAULTADDR_MASK 0xFFFFFFFFUL /**< Mask for MVP_FAULTADDR */ +#define _MVP_FAULTADDR_FAULTADDR_SHIFT 0 /**< Shift value for MVP_FAULTADDR */ +#define _MVP_FAULTADDR_FAULTADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MVP_FAULTADDR */ +#define _MVP_FAULTADDR_FAULTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_FAULTADDR */ +#define MVP_FAULTADDR_FAULTADDR_DEFAULT \ + (_MVP_FAULTADDR_FAULTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_FAULTADDR */ + +/* Bit fields for MVP PROGRAMSTATE */ +#define _MVP_PROGRAMSTATE_RESETVALUE 0x00000000UL /**< Default value for MVP_PROGRAMSTATE */ +#define _MVP_PROGRAMSTATE_MASK 0x00000007UL /**< Mask for MVP_PROGRAMSTATE */ +#define _MVP_PROGRAMSTATE_PC_SHIFT 0 /**< Shift value for MVP_PC */ +#define _MVP_PROGRAMSTATE_PC_MASK 0x7UL /**< Bit mask for MVP_PC */ +#define _MVP_PROGRAMSTATE_PC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_PROGRAMSTATE */ +#define MVP_PROGRAMSTATE_PC_DEFAULT \ + (_MVP_PROGRAMSTATE_PC_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_PROGRAMSTATE */ + +/* Bit fields for MVP ARRAYINDEXSTATE */ +#define _MVP_ARRAYINDEXSTATE_RESETVALUE 0x00000000UL /**< Default value for MVP_ARRAYINDEXSTATE */ +#define _MVP_ARRAYINDEXSTATE_MASK 0x3FFFFFFFUL /**< Mask for MVP_ARRAYINDEXSTATE */ +#define _MVP_ARRAYINDEXSTATE_DIM0INDEX_SHIFT 0 /**< Shift value for MVP_DIM0INDEX */ +#define _MVP_ARRAYINDEXSTATE_DIM0INDEX_MASK 0x3FFUL /**< Bit mask for MVP_DIM0INDEX */ +#define _MVP_ARRAYINDEXSTATE_DIM0INDEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYINDEXSTATE */ +#define MVP_ARRAYINDEXSTATE_DIM0INDEX_DEFAULT \ + (_MVP_ARRAYINDEXSTATE_DIM0INDEX_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_ARRAYINDEXSTATE*/ +#define _MVP_ARRAYINDEXSTATE_DIM1INDEX_SHIFT 10 /**< Shift value for MVP_DIM1INDEX */ +#define _MVP_ARRAYINDEXSTATE_DIM1INDEX_MASK 0xFFC00UL /**< Bit mask for MVP_DIM1INDEX */ +#define _MVP_ARRAYINDEXSTATE_DIM1INDEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYINDEXSTATE */ +#define MVP_ARRAYINDEXSTATE_DIM1INDEX_DEFAULT \ + (_MVP_ARRAYINDEXSTATE_DIM1INDEX_DEFAULT << 10) /**< Shifted mode DEFAULT for MVP_ARRAYINDEXSTATE*/ +#define _MVP_ARRAYINDEXSTATE_DIM2INDEX_SHIFT 20 /**< Shift value for MVP_DIM2INDEX */ +#define _MVP_ARRAYINDEXSTATE_DIM2INDEX_MASK 0x3FF00000UL /**< Bit mask for MVP_DIM2INDEX */ +#define _MVP_ARRAYINDEXSTATE_DIM2INDEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYINDEXSTATE */ +#define MVP_ARRAYINDEXSTATE_DIM2INDEX_DEFAULT \ + (_MVP_ARRAYINDEXSTATE_DIM2INDEX_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_ARRAYINDEXSTATE*/ + +/* Bit fields for MVP LOOPSTATE */ +#define _MVP_LOOPSTATE_RESETVALUE 0x00000000UL /**< Default value for MVP_LOOPSTATE */ +#define _MVP_LOOPSTATE_MASK 0x000713FFUL /**< Mask for MVP_LOOPSTATE */ +#define _MVP_LOOPSTATE_CNT_SHIFT 0 /**< Shift value for MVP_CNT */ +#define _MVP_LOOPSTATE_CNT_MASK 0x3FFUL /**< Bit mask for MVP_CNT */ +#define _MVP_LOOPSTATE_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPSTATE */ +#define MVP_LOOPSTATE_CNT_DEFAULT (_MVP_LOOPSTATE_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_LOOPSTATE */ +#define MVP_LOOPSTATE_ACTIVE (0x1UL << 12) /**< Loop Active */ +#define _MVP_LOOPSTATE_ACTIVE_SHIFT 12 /**< Shift value for MVP_ACTIVE */ +#define _MVP_LOOPSTATE_ACTIVE_MASK 0x1000UL /**< Bit mask for MVP_ACTIVE */ +#define _MVP_LOOPSTATE_ACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPSTATE */ +#define MVP_LOOPSTATE_ACTIVE_DEFAULT \ + (_MVP_LOOPSTATE_ACTIVE_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_LOOPSTATE */ +#define _MVP_LOOPSTATE_PCBEGIN_SHIFT 16 /**< Shift value for MVP_PCBEGIN */ +#define _MVP_LOOPSTATE_PCBEGIN_MASK 0x70000UL /**< Bit mask for MVP_PCBEGIN */ +#define _MVP_LOOPSTATE_PCBEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPSTATE */ +#define MVP_LOOPSTATE_PCBEGIN_DEFAULT \ + (_MVP_LOOPSTATE_PCBEGIN_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_LOOPSTATE */ + +/* Bit fields for MVP ALUREGSTATE */ +#define _MVP_ALUREGSTATE_RESETVALUE 0x00000000UL /**< Default value for MVP_ALUREGSTATE */ +#define _MVP_ALUREGSTATE_MASK 0xFFFFFFFFUL /**< Mask for MVP_ALUREGSTATE */ +#define _MVP_ALUREGSTATE_FREAL_SHIFT 0 /**< Shift value for MVP_FREAL */ +#define _MVP_ALUREGSTATE_FREAL_MASK 0xFFFFUL /**< Bit mask for MVP_FREAL */ +#define _MVP_ALUREGSTATE_FREAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ALUREGSTATE */ +#define MVP_ALUREGSTATE_FREAL_DEFAULT \ + (_MVP_ALUREGSTATE_FREAL_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_ALUREGSTATE */ +#define _MVP_ALUREGSTATE_FIMAG_SHIFT 16 /**< Shift value for MVP_FIMAG */ +#define _MVP_ALUREGSTATE_FIMAG_MASK 0xFFFF0000UL /**< Bit mask for MVP_FIMAG */ +#define _MVP_ALUREGSTATE_FIMAG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ALUREGSTATE */ +#define MVP_ALUREGSTATE_FIMAG_DEFAULT \ + (_MVP_ALUREGSTATE_FIMAG_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_ALUREGSTATE */ + +/* Bit fields for MVP ARRAYADDRCFG */ +#define _MVP_ARRAYADDRCFG_RESETVALUE 0x00000000UL /**< Default value for MVP_ARRAYADDRCFG */ +#define _MVP_ARRAYADDRCFG_MASK 0xFFFFFFFFUL /**< Mask for MVP_ARRAYADDRCFG */ +#define _MVP_ARRAYADDRCFG_BASE_SHIFT 0 /**< Shift value for MVP_BASE */ +#define _MVP_ARRAYADDRCFG_BASE_MASK 0xFFFFFFFFUL /**< Bit mask for MVP_BASE */ +#define _MVP_ARRAYADDRCFG_BASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYADDRCFG */ +#define MVP_ARRAYADDRCFG_BASE_DEFAULT \ + (_MVP_ARRAYADDRCFG_BASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_ARRAYADDRCFG */ + +/* Bit fields for MVP ARRAYDIM0CFG */ +#define _MVP_ARRAYDIM0CFG_RESETVALUE 0x00002000UL /**< Default value for MVP_ARRAYDIM0CFG */ +#define _MVP_ARRAYDIM0CFG_MASK 0x0FFF73FFUL /**< Mask for MVP_ARRAYDIM0CFG */ +#define _MVP_ARRAYDIM0CFG_SIZE_SHIFT 0 /**< Shift value for MVP_SIZE */ +#define _MVP_ARRAYDIM0CFG_SIZE_MASK 0x3FFUL /**< Bit mask for MVP_SIZE */ +#define _MVP_ARRAYDIM0CFG_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM0CFG */ +#define MVP_ARRAYDIM0CFG_SIZE_DEFAULT \ + (_MVP_ARRAYDIM0CFG_SIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_ARRAYDIM0CFG */ +#define _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT 12 /**< Shift value for MVP_BASETYPE */ +#define _MVP_ARRAYDIM0CFG_BASETYPE_MASK 0x3000UL /**< Bit mask for MVP_BASETYPE */ +#define _MVP_ARRAYDIM0CFG_BASETYPE_DEFAULT 0x00000002UL /**< Mode DEFAULT for MVP_ARRAYDIM0CFG */ +#define _MVP_ARRAYDIM0CFG_BASETYPE_UINT8 0x00000000UL /**< Mode UINT8 for MVP_ARRAYDIM0CFG */ +#define _MVP_ARRAYDIM0CFG_BASETYPE_INT8 0x00000001UL /**< Mode INT8 for MVP_ARRAYDIM0CFG */ +#define _MVP_ARRAYDIM0CFG_BASETYPE_BINARY16 0x00000002UL /**< Mode BINARY16 for MVP_ARRAYDIM0CFG */ +#define _MVP_ARRAYDIM0CFG_BASETYPE_RESERVED 0x00000003UL /**< Mode RESERVED for MVP_ARRAYDIM0CFG */ +#define MVP_ARRAYDIM0CFG_BASETYPE_DEFAULT \ + (_MVP_ARRAYDIM0CFG_BASETYPE_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_ARRAYDIM0CFG */ +#define MVP_ARRAYDIM0CFG_BASETYPE_UINT8 \ + (_MVP_ARRAYDIM0CFG_BASETYPE_UINT8 << 12) /**< Shifted mode UINT8 for MVP_ARRAYDIM0CFG */ +#define MVP_ARRAYDIM0CFG_BASETYPE_INT8 \ + (_MVP_ARRAYDIM0CFG_BASETYPE_INT8 << 12) /**< Shifted mode INT8 for MVP_ARRAYDIM0CFG */ +#define MVP_ARRAYDIM0CFG_BASETYPE_BINARY16 \ + (_MVP_ARRAYDIM0CFG_BASETYPE_BINARY16 << 12) /**< Shifted mode BINARY16 for MVP_ARRAYDIM0CFG */ +#define MVP_ARRAYDIM0CFG_COMPLEX (0x1UL << 14) /**< Complex Data Type */ +#define _MVP_ARRAYDIM0CFG_COMPLEX_SHIFT 14 /**< Shift value for MVP_COMPLEX */ +#define _MVP_ARRAYDIM0CFG_COMPLEX_MASK 0x4000UL /**< Bit mask for MVP_COMPLEX */ +#define _MVP_ARRAYDIM0CFG_COMPLEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM0CFG */ +#define _MVP_ARRAYDIM0CFG_COMPLEX_SCALAR 0x00000000UL /**< Mode SCALAR for MVP_ARRAYDIM0CFG */ +#define _MVP_ARRAYDIM0CFG_COMPLEX_COMPLEX 0x00000001UL /**< Mode COMPLEX for MVP_ARRAYDIM0CFG */ +#define MVP_ARRAYDIM0CFG_COMPLEX_DEFAULT \ + (_MVP_ARRAYDIM0CFG_COMPLEX_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_ARRAYDIM0CFG */ +#define MVP_ARRAYDIM0CFG_COMPLEX_SCALAR \ + (_MVP_ARRAYDIM0CFG_COMPLEX_SCALAR << 14) /**< Shifted mode SCALAR for MVP_ARRAYDIM0CFG */ +#define MVP_ARRAYDIM0CFG_COMPLEX_COMPLEX \ + (_MVP_ARRAYDIM0CFG_COMPLEX_COMPLEX << 14) /**< Shifted mode COMPLEX for MVP_ARRAYDIM0CFG */ +#define _MVP_ARRAYDIM0CFG_STRIDE_SHIFT 16 /**< Shift value for MVP_STRIDE */ +#define _MVP_ARRAYDIM0CFG_STRIDE_MASK 0xFFF0000UL /**< Bit mask for MVP_STRIDE */ +#define _MVP_ARRAYDIM0CFG_STRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM0CFG */ +#define MVP_ARRAYDIM0CFG_STRIDE_DEFAULT \ + (_MVP_ARRAYDIM0CFG_STRIDE_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_ARRAYDIM0CFG */ + +/* Bit fields for MVP ARRAYDIM1CFG */ +#define _MVP_ARRAYDIM1CFG_RESETVALUE 0x00000000UL /**< Default value for MVP_ARRAYDIM1CFG */ +#define _MVP_ARRAYDIM1CFG_MASK 0x0FFF03FFUL /**< Mask for MVP_ARRAYDIM1CFG */ +#define _MVP_ARRAYDIM1CFG_SIZE_SHIFT 0 /**< Shift value for MVP_SIZE */ +#define _MVP_ARRAYDIM1CFG_SIZE_MASK 0x3FFUL /**< Bit mask for MVP_SIZE */ +#define _MVP_ARRAYDIM1CFG_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM1CFG */ +#define MVP_ARRAYDIM1CFG_SIZE_DEFAULT \ + (_MVP_ARRAYDIM1CFG_SIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_ARRAYDIM1CFG */ +#define _MVP_ARRAYDIM1CFG_STRIDE_SHIFT 16 /**< Shift value for MVP_STRIDE */ +#define _MVP_ARRAYDIM1CFG_STRIDE_MASK 0xFFF0000UL /**< Bit mask for MVP_STRIDE */ +#define _MVP_ARRAYDIM1CFG_STRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM1CFG */ +#define MVP_ARRAYDIM1CFG_STRIDE_DEFAULT \ + (_MVP_ARRAYDIM1CFG_STRIDE_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_ARRAYDIM1CFG */ + +/* Bit fields for MVP ARRAYDIM2CFG */ +#define _MVP_ARRAYDIM2CFG_RESETVALUE 0x00000000UL /**< Default value for MVP_ARRAYDIM2CFG */ +#define _MVP_ARRAYDIM2CFG_MASK 0x0FFF03FFUL /**< Mask for MVP_ARRAYDIM2CFG */ +#define _MVP_ARRAYDIM2CFG_SIZE_SHIFT 0 /**< Shift value for MVP_SIZE */ +#define _MVP_ARRAYDIM2CFG_SIZE_MASK 0x3FFUL /**< Bit mask for MVP_SIZE */ +#define _MVP_ARRAYDIM2CFG_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM2CFG */ +#define MVP_ARRAYDIM2CFG_SIZE_DEFAULT \ + (_MVP_ARRAYDIM2CFG_SIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_ARRAYDIM2CFG */ +#define _MVP_ARRAYDIM2CFG_STRIDE_SHIFT 16 /**< Shift value for MVP_STRIDE */ +#define _MVP_ARRAYDIM2CFG_STRIDE_MASK 0xFFF0000UL /**< Bit mask for MVP_STRIDE */ +#define _MVP_ARRAYDIM2CFG_STRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM2CFG */ +#define MVP_ARRAYDIM2CFG_STRIDE_DEFAULT \ + (_MVP_ARRAYDIM2CFG_STRIDE_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_ARRAYDIM2CFG */ + +/* Bit fields for MVP LOOPCFG */ +#define _MVP_LOOPCFG_RESETVALUE 0x00000000UL /**< Default value for MVP_LOOPCFG */ +#define _MVP_LOOPCFG_MASK 0x777773FFUL /**< Mask for MVP_LOOPCFG */ +#define _MVP_LOOPCFG_NUMITERS_SHIFT 0 /**< Shift value for MVP_NUMITERS */ +#define _MVP_LOOPCFG_NUMITERS_MASK 0x3FFUL /**< Bit mask for MVP_NUMITERS */ +#define _MVP_LOOPCFG_NUMITERS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_NUMITERS_DEFAULT \ + (_MVP_LOOPCFG_NUMITERS_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY0INCRDIM0 (0x1UL << 12) /**< Increment Dimension 0 */ +#define _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT 12 /**< Shift value for MVP_ARRAY0INCRDIM0 */ +#define _MVP_LOOPCFG_ARRAY0INCRDIM0_MASK 0x1000UL /**< Bit mask for MVP_ARRAY0INCRDIM0 */ +#define _MVP_LOOPCFG_ARRAY0INCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY0INCRDIM0_DEFAULT \ + (_MVP_LOOPCFG_ARRAY0INCRDIM0_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY0INCRDIM1 (0x1UL << 13) /**< Increment Dimension 1 */ +#define _MVP_LOOPCFG_ARRAY0INCRDIM1_SHIFT 13 /**< Shift value for MVP_ARRAY0INCRDIM1 */ +#define _MVP_LOOPCFG_ARRAY0INCRDIM1_MASK 0x2000UL /**< Bit mask for MVP_ARRAY0INCRDIM1 */ +#define _MVP_LOOPCFG_ARRAY0INCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY0INCRDIM1_DEFAULT \ + (_MVP_LOOPCFG_ARRAY0INCRDIM1_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY0INCRDIM2 (0x1UL << 14) /**< Increment Dimension 2 */ +#define _MVP_LOOPCFG_ARRAY0INCRDIM2_SHIFT 14 /**< Shift value for MVP_ARRAY0INCRDIM2 */ +#define _MVP_LOOPCFG_ARRAY0INCRDIM2_MASK 0x4000UL /**< Bit mask for MVP_ARRAY0INCRDIM2 */ +#define _MVP_LOOPCFG_ARRAY0INCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY0INCRDIM2_DEFAULT \ + (_MVP_LOOPCFG_ARRAY0INCRDIM2_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY1INCRDIM0 (0x1UL << 16) /**< Increment Dimension 0 */ +#define _MVP_LOOPCFG_ARRAY1INCRDIM0_SHIFT 16 /**< Shift value for MVP_ARRAY1INCRDIM0 */ +#define _MVP_LOOPCFG_ARRAY1INCRDIM0_MASK 0x10000UL /**< Bit mask for MVP_ARRAY1INCRDIM0 */ +#define _MVP_LOOPCFG_ARRAY1INCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY1INCRDIM0_DEFAULT \ + (_MVP_LOOPCFG_ARRAY1INCRDIM0_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY1INCRDIM1 (0x1UL << 17) /**< Increment Dimension 1 */ +#define _MVP_LOOPCFG_ARRAY1INCRDIM1_SHIFT 17 /**< Shift value for MVP_ARRAY1INCRDIM1 */ +#define _MVP_LOOPCFG_ARRAY1INCRDIM1_MASK 0x20000UL /**< Bit mask for MVP_ARRAY1INCRDIM1 */ +#define _MVP_LOOPCFG_ARRAY1INCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY1INCRDIM1_DEFAULT \ + (_MVP_LOOPCFG_ARRAY1INCRDIM1_DEFAULT << 17) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY1INCRDIM2 (0x1UL << 18) /**< Increment Dimension 2 */ +#define _MVP_LOOPCFG_ARRAY1INCRDIM2_SHIFT 18 /**< Shift value for MVP_ARRAY1INCRDIM2 */ +#define _MVP_LOOPCFG_ARRAY1INCRDIM2_MASK 0x40000UL /**< Bit mask for MVP_ARRAY1INCRDIM2 */ +#define _MVP_LOOPCFG_ARRAY1INCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY1INCRDIM2_DEFAULT \ + (_MVP_LOOPCFG_ARRAY1INCRDIM2_DEFAULT << 18) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY2INCRDIM0 (0x1UL << 20) /**< Increment Dimension 0 */ +#define _MVP_LOOPCFG_ARRAY2INCRDIM0_SHIFT 20 /**< Shift value for MVP_ARRAY2INCRDIM0 */ +#define _MVP_LOOPCFG_ARRAY2INCRDIM0_MASK 0x100000UL /**< Bit mask for MVP_ARRAY2INCRDIM0 */ +#define _MVP_LOOPCFG_ARRAY2INCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY2INCRDIM0_DEFAULT \ + (_MVP_LOOPCFG_ARRAY2INCRDIM0_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY2INCRDIM1 (0x1UL << 21) /**< Increment Dimension 1 */ +#define _MVP_LOOPCFG_ARRAY2INCRDIM1_SHIFT 21 /**< Shift value for MVP_ARRAY2INCRDIM1 */ +#define _MVP_LOOPCFG_ARRAY2INCRDIM1_MASK 0x200000UL /**< Bit mask for MVP_ARRAY2INCRDIM1 */ +#define _MVP_LOOPCFG_ARRAY2INCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY2INCRDIM1_DEFAULT \ + (_MVP_LOOPCFG_ARRAY2INCRDIM1_DEFAULT << 21) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY2INCRDIM2 (0x1UL << 22) /**< Increment Dimension 2 */ +#define _MVP_LOOPCFG_ARRAY2INCRDIM2_SHIFT 22 /**< Shift value for MVP_ARRAY2INCRDIM2 */ +#define _MVP_LOOPCFG_ARRAY2INCRDIM2_MASK 0x400000UL /**< Bit mask for MVP_ARRAY2INCRDIM2 */ +#define _MVP_LOOPCFG_ARRAY2INCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY2INCRDIM2_DEFAULT \ + (_MVP_LOOPCFG_ARRAY2INCRDIM2_DEFAULT << 22) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY3INCRDIM0 (0x1UL << 24) /**< Increment Dimension 0 */ +#define _MVP_LOOPCFG_ARRAY3INCRDIM0_SHIFT 24 /**< Shift value for MVP_ARRAY3INCRDIM0 */ +#define _MVP_LOOPCFG_ARRAY3INCRDIM0_MASK 0x1000000UL /**< Bit mask for MVP_ARRAY3INCRDIM0 */ +#define _MVP_LOOPCFG_ARRAY3INCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY3INCRDIM0_DEFAULT \ + (_MVP_LOOPCFG_ARRAY3INCRDIM0_DEFAULT << 24) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY3INCRDIM1 (0x1UL << 25) /**< Increment Dimension 1 */ +#define _MVP_LOOPCFG_ARRAY3INCRDIM1_SHIFT 25 /**< Shift value for MVP_ARRAY3INCRDIM1 */ +#define _MVP_LOOPCFG_ARRAY3INCRDIM1_MASK 0x2000000UL /**< Bit mask for MVP_ARRAY3INCRDIM1 */ +#define _MVP_LOOPCFG_ARRAY3INCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY3INCRDIM1_DEFAULT \ + (_MVP_LOOPCFG_ARRAY3INCRDIM1_DEFAULT << 25) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY3INCRDIM2 (0x1UL << 26) /**< Increment Dimension 2 */ +#define _MVP_LOOPCFG_ARRAY3INCRDIM2_SHIFT 26 /**< Shift value for MVP_ARRAY3INCRDIM2 */ +#define _MVP_LOOPCFG_ARRAY3INCRDIM2_MASK 0x4000000UL /**< Bit mask for MVP_ARRAY3INCRDIM2 */ +#define _MVP_LOOPCFG_ARRAY3INCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY3INCRDIM2_DEFAULT \ + (_MVP_LOOPCFG_ARRAY3INCRDIM2_DEFAULT << 26) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY4INCRDIM0 (0x1UL << 28) /**< Increment Dimension 0 */ +#define _MVP_LOOPCFG_ARRAY4INCRDIM0_SHIFT 28 /**< Shift value for MVP_ARRAY4INCRDIM0 */ +#define _MVP_LOOPCFG_ARRAY4INCRDIM0_MASK 0x10000000UL /**< Bit mask for MVP_ARRAY4INCRDIM0 */ +#define _MVP_LOOPCFG_ARRAY4INCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY4INCRDIM0_DEFAULT \ + (_MVP_LOOPCFG_ARRAY4INCRDIM0_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY4INCRDIM1 (0x1UL << 29) /**< Increment Dimension 1 */ +#define _MVP_LOOPCFG_ARRAY4INCRDIM1_SHIFT 29 /**< Shift value for MVP_ARRAY4INCRDIM1 */ +#define _MVP_LOOPCFG_ARRAY4INCRDIM1_MASK 0x20000000UL /**< Bit mask for MVP_ARRAY4INCRDIM1 */ +#define _MVP_LOOPCFG_ARRAY4INCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY4INCRDIM1_DEFAULT \ + (_MVP_LOOPCFG_ARRAY4INCRDIM1_DEFAULT << 29) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY4INCRDIM2 (0x1UL << 30) /**< Increment Dimension 2 */ +#define _MVP_LOOPCFG_ARRAY4INCRDIM2_SHIFT 30 /**< Shift value for MVP_ARRAY4INCRDIM2 */ +#define _MVP_LOOPCFG_ARRAY4INCRDIM2_MASK 0x40000000UL /**< Bit mask for MVP_ARRAY4INCRDIM2 */ +#define _MVP_LOOPCFG_ARRAY4INCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY4INCRDIM2_DEFAULT \ + (_MVP_LOOPCFG_ARRAY4INCRDIM2_DEFAULT << 30) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ + +/* Bit fields for MVP LOOPRST */ +#define _MVP_LOOPRST_RESETVALUE 0x00000000UL /**< Default value for MVP_LOOPRST */ +#define _MVP_LOOPRST_MASK 0x77777000UL /**< Mask for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY0RESETDIM0 (0x1UL << 12) /**< Reset Dimension 0 */ +#define _MVP_LOOPRST_ARRAY0RESETDIM0_SHIFT 12 /**< Shift value for MVP_ARRAY0RESETDIM0 */ +#define _MVP_LOOPRST_ARRAY0RESETDIM0_MASK 0x1000UL /**< Bit mask for MVP_ARRAY0RESETDIM0 */ +#define _MVP_LOOPRST_ARRAY0RESETDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY0RESETDIM0_DEFAULT \ + (_MVP_LOOPRST_ARRAY0RESETDIM0_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY0RESETDIM1 (0x1UL << 13) /**< Reset Dimension 1 */ +#define _MVP_LOOPRST_ARRAY0RESETDIM1_SHIFT 13 /**< Shift value for MVP_ARRAY0RESETDIM1 */ +#define _MVP_LOOPRST_ARRAY0RESETDIM1_MASK 0x2000UL /**< Bit mask for MVP_ARRAY0RESETDIM1 */ +#define _MVP_LOOPRST_ARRAY0RESETDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY0RESETDIM1_DEFAULT \ + (_MVP_LOOPRST_ARRAY0RESETDIM1_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY0RESETDIM2 (0x1UL << 14) /**< Reset Dimension 2 */ +#define _MVP_LOOPRST_ARRAY0RESETDIM2_SHIFT 14 /**< Shift value for MVP_ARRAY0RESETDIM2 */ +#define _MVP_LOOPRST_ARRAY0RESETDIM2_MASK 0x4000UL /**< Bit mask for MVP_ARRAY0RESETDIM2 */ +#define _MVP_LOOPRST_ARRAY0RESETDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY0RESETDIM2_DEFAULT \ + (_MVP_LOOPRST_ARRAY0RESETDIM2_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY1RESETDIM0 (0x1UL << 16) /**< Reset Dimension 0 */ +#define _MVP_LOOPRST_ARRAY1RESETDIM0_SHIFT 16 /**< Shift value for MVP_ARRAY1RESETDIM0 */ +#define _MVP_LOOPRST_ARRAY1RESETDIM0_MASK 0x10000UL /**< Bit mask for MVP_ARRAY1RESETDIM0 */ +#define _MVP_LOOPRST_ARRAY1RESETDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY1RESETDIM0_DEFAULT \ + (_MVP_LOOPRST_ARRAY1RESETDIM0_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY1RESETDIM1 (0x1UL << 17) /**< Reset Dimension 1 */ +#define _MVP_LOOPRST_ARRAY1RESETDIM1_SHIFT 17 /**< Shift value for MVP_ARRAY1RESETDIM1 */ +#define _MVP_LOOPRST_ARRAY1RESETDIM1_MASK 0x20000UL /**< Bit mask for MVP_ARRAY1RESETDIM1 */ +#define _MVP_LOOPRST_ARRAY1RESETDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY1RESETDIM1_DEFAULT \ + (_MVP_LOOPRST_ARRAY1RESETDIM1_DEFAULT << 17) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY1RESETDIM2 (0x1UL << 18) /**< Reset Dimension 2 */ +#define _MVP_LOOPRST_ARRAY1RESETDIM2_SHIFT 18 /**< Shift value for MVP_ARRAY1RESETDIM2 */ +#define _MVP_LOOPRST_ARRAY1RESETDIM2_MASK 0x40000UL /**< Bit mask for MVP_ARRAY1RESETDIM2 */ +#define _MVP_LOOPRST_ARRAY1RESETDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY1RESETDIM2_DEFAULT \ + (_MVP_LOOPRST_ARRAY1RESETDIM2_DEFAULT << 18) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY2RESETDIM0 (0x1UL << 20) /**< Reset Dimension 0 */ +#define _MVP_LOOPRST_ARRAY2RESETDIM0_SHIFT 20 /**< Shift value for MVP_ARRAY2RESETDIM0 */ +#define _MVP_LOOPRST_ARRAY2RESETDIM0_MASK 0x100000UL /**< Bit mask for MVP_ARRAY2RESETDIM0 */ +#define _MVP_LOOPRST_ARRAY2RESETDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY2RESETDIM0_DEFAULT \ + (_MVP_LOOPRST_ARRAY2RESETDIM0_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY2RESETDIM1 (0x1UL << 21) /**< Reset Dimension 1 */ +#define _MVP_LOOPRST_ARRAY2RESETDIM1_SHIFT 21 /**< Shift value for MVP_ARRAY2RESETDIM1 */ +#define _MVP_LOOPRST_ARRAY2RESETDIM1_MASK 0x200000UL /**< Bit mask for MVP_ARRAY2RESETDIM1 */ +#define _MVP_LOOPRST_ARRAY2RESETDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY2RESETDIM1_DEFAULT \ + (_MVP_LOOPRST_ARRAY2RESETDIM1_DEFAULT << 21) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY2RESETDIM2 (0x1UL << 22) /**< Reset Dimension 2 */ +#define _MVP_LOOPRST_ARRAY2RESETDIM2_SHIFT 22 /**< Shift value for MVP_ARRAY2RESETDIM2 */ +#define _MVP_LOOPRST_ARRAY2RESETDIM2_MASK 0x400000UL /**< Bit mask for MVP_ARRAY2RESETDIM2 */ +#define _MVP_LOOPRST_ARRAY2RESETDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY2RESETDIM2_DEFAULT \ + (_MVP_LOOPRST_ARRAY2RESETDIM2_DEFAULT << 22) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY3RESETDIM0 (0x1UL << 24) /**< Reset Dimension 0 */ +#define _MVP_LOOPRST_ARRAY3RESETDIM0_SHIFT 24 /**< Shift value for MVP_ARRAY3RESETDIM0 */ +#define _MVP_LOOPRST_ARRAY3RESETDIM0_MASK 0x1000000UL /**< Bit mask for MVP_ARRAY3RESETDIM0 */ +#define _MVP_LOOPRST_ARRAY3RESETDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY3RESETDIM0_DEFAULT \ + (_MVP_LOOPRST_ARRAY3RESETDIM0_DEFAULT << 24) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY3RESETDIM1 (0x1UL << 25) /**< Reset Dimension 1 */ +#define _MVP_LOOPRST_ARRAY3RESETDIM1_SHIFT 25 /**< Shift value for MVP_ARRAY3RESETDIM1 */ +#define _MVP_LOOPRST_ARRAY3RESETDIM1_MASK 0x2000000UL /**< Bit mask for MVP_ARRAY3RESETDIM1 */ +#define _MVP_LOOPRST_ARRAY3RESETDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY3RESETDIM1_DEFAULT \ + (_MVP_LOOPRST_ARRAY3RESETDIM1_DEFAULT << 25) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY3RESETDIM2 (0x1UL << 26) /**< Reset Dimension 2 */ +#define _MVP_LOOPRST_ARRAY3RESETDIM2_SHIFT 26 /**< Shift value for MVP_ARRAY3RESETDIM2 */ +#define _MVP_LOOPRST_ARRAY3RESETDIM2_MASK 0x4000000UL /**< Bit mask for MVP_ARRAY3RESETDIM2 */ +#define _MVP_LOOPRST_ARRAY3RESETDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY3RESETDIM2_DEFAULT \ + (_MVP_LOOPRST_ARRAY3RESETDIM2_DEFAULT << 26) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY4RESETDIM0 (0x1UL << 28) /**< Reset Dimension 0 */ +#define _MVP_LOOPRST_ARRAY4RESETDIM0_SHIFT 28 /**< Shift value for MVP_ARRAY4RESETDIM0 */ +#define _MVP_LOOPRST_ARRAY4RESETDIM0_MASK 0x10000000UL /**< Bit mask for MVP_ARRAY4RESETDIM0 */ +#define _MVP_LOOPRST_ARRAY4RESETDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY4RESETDIM0_DEFAULT \ + (_MVP_LOOPRST_ARRAY4RESETDIM0_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY4RESETDIM1 (0x1UL << 29) /**< Reset Dimension 1 */ +#define _MVP_LOOPRST_ARRAY4RESETDIM1_SHIFT 29 /**< Shift value for MVP_ARRAY4RESETDIM1 */ +#define _MVP_LOOPRST_ARRAY4RESETDIM1_MASK 0x20000000UL /**< Bit mask for MVP_ARRAY4RESETDIM1 */ +#define _MVP_LOOPRST_ARRAY4RESETDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY4RESETDIM1_DEFAULT \ + (_MVP_LOOPRST_ARRAY4RESETDIM1_DEFAULT << 29) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY4RESETDIM2 (0x1UL << 30) /**< Reset Dimension 2 */ +#define _MVP_LOOPRST_ARRAY4RESETDIM2_SHIFT 30 /**< Shift value for MVP_ARRAY4RESETDIM2 */ +#define _MVP_LOOPRST_ARRAY4RESETDIM2_MASK 0x40000000UL /**< Bit mask for MVP_ARRAY4RESETDIM2 */ +#define _MVP_LOOPRST_ARRAY4RESETDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY4RESETDIM2_DEFAULT \ + (_MVP_LOOPRST_ARRAY4RESETDIM2_DEFAULT << 30) /**< Shifted mode DEFAULT for MVP_LOOPRST */ + +/* Bit fields for MVP INSTRCFG0 */ +#define _MVP_INSTRCFG0_RESETVALUE 0x00000000UL /**< Default value for MVP_INSTRCFG0 */ +#define _MVP_INSTRCFG0_MASK 0x70F7F7F7UL /**< Mask for MVP_INSTRCFG0 */ +#define _MVP_INSTRCFG0_ALUIN0REGID_SHIFT 0 /**< Shift value for MVP_ALUIN0REGID */ +#define _MVP_INSTRCFG0_ALUIN0REGID_MASK 0x7UL /**< Bit mask for MVP_ALUIN0REGID */ +#define _MVP_INSTRCFG0_ALUIN0REGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN0REGID_DEFAULT \ + (_MVP_INSTRCFG0_ALUIN0REGID_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN0REALZERO (0x1UL << 4) /**< Real Zero */ +#define _MVP_INSTRCFG0_ALUIN0REALZERO_SHIFT 4 /**< Shift value for MVP_ALUIN0REALZERO */ +#define _MVP_INSTRCFG0_ALUIN0REALZERO_MASK 0x10UL /**< Bit mask for MVP_ALUIN0REALZERO */ +#define _MVP_INSTRCFG0_ALUIN0REALZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN0REALZERO_DEFAULT \ + (_MVP_INSTRCFG0_ALUIN0REALZERO_DEFAULT << 4) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN0REALNEGATE (0x1UL << 5) /**< Real Negate */ +#define _MVP_INSTRCFG0_ALUIN0REALNEGATE_SHIFT 5 /**< Shift value for MVP_ALUIN0REALNEGATE */ +#define _MVP_INSTRCFG0_ALUIN0REALNEGATE_MASK 0x20UL /**< Bit mask for MVP_ALUIN0REALNEGATE */ +#define _MVP_INSTRCFG0_ALUIN0REALNEGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN0REALNEGATE_DEFAULT \ + (_MVP_INSTRCFG0_ALUIN0REALNEGATE_DEFAULT << 5) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN0IMAGZERO (0x1UL << 6) /**< Imaginary Not Zero */ +#define _MVP_INSTRCFG0_ALUIN0IMAGZERO_SHIFT 6 /**< Shift value for MVP_ALUIN0IMAGZERO */ +#define _MVP_INSTRCFG0_ALUIN0IMAGZERO_MASK 0x40UL /**< Bit mask for MVP_ALUIN0IMAGZERO */ +#define _MVP_INSTRCFG0_ALUIN0IMAGZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN0IMAGZERO_DEFAULT \ + (_MVP_INSTRCFG0_ALUIN0IMAGZERO_DEFAULT << 6) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN0IMAGNEGATE (0x1UL << 7) /**< Imaginary Negate */ +#define _MVP_INSTRCFG0_ALUIN0IMAGNEGATE_SHIFT 7 /**< Shift value for MVP_ALUIN0IMAGNEGATE */ +#define _MVP_INSTRCFG0_ALUIN0IMAGNEGATE_MASK 0x80UL /**< Bit mask for MVP_ALUIN0IMAGNEGATE */ +#define _MVP_INSTRCFG0_ALUIN0IMAGNEGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN0IMAGNEGATE_DEFAULT \ + (_MVP_INSTRCFG0_ALUIN0IMAGNEGATE_DEFAULT << 7) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define _MVP_INSTRCFG0_ALUIN1REGID_SHIFT 8 /**< Shift value for MVP_ALUIN1REGID */ +#define _MVP_INSTRCFG0_ALUIN1REGID_MASK 0x700UL /**< Bit mask for MVP_ALUIN1REGID */ +#define _MVP_INSTRCFG0_ALUIN1REGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN1REGID_DEFAULT \ + (_MVP_INSTRCFG0_ALUIN1REGID_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN1REALZERO (0x1UL << 12) /**< Real Zero */ +#define _MVP_INSTRCFG0_ALUIN1REALZERO_SHIFT 12 /**< Shift value for MVP_ALUIN1REALZERO */ +#define _MVP_INSTRCFG0_ALUIN1REALZERO_MASK 0x1000UL /**< Bit mask for MVP_ALUIN1REALZERO */ +#define _MVP_INSTRCFG0_ALUIN1REALZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN1REALZERO_DEFAULT \ + (_MVP_INSTRCFG0_ALUIN1REALZERO_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN1REALNEGATE (0x1UL << 13) /**< Real Negate */ +#define _MVP_INSTRCFG0_ALUIN1REALNEGATE_SHIFT 13 /**< Shift value for MVP_ALUIN1REALNEGATE */ +#define _MVP_INSTRCFG0_ALUIN1REALNEGATE_MASK 0x2000UL /**< Bit mask for MVP_ALUIN1REALNEGATE */ +#define _MVP_INSTRCFG0_ALUIN1REALNEGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN1REALNEGATE_DEFAULT \ + (_MVP_INSTRCFG0_ALUIN1REALNEGATE_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN1IMAGZERO (0x1UL << 14) /**< Imaginary Not Zero */ +#define _MVP_INSTRCFG0_ALUIN1IMAGZERO_SHIFT 14 /**< Shift value for MVP_ALUIN1IMAGZERO */ +#define _MVP_INSTRCFG0_ALUIN1IMAGZERO_MASK 0x4000UL /**< Bit mask for MVP_ALUIN1IMAGZERO */ +#define _MVP_INSTRCFG0_ALUIN1IMAGZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN1IMAGZERO_DEFAULT \ + (_MVP_INSTRCFG0_ALUIN1IMAGZERO_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN1IMAGNEGATE (0x1UL << 15) /**< Imaginary Negate */ +#define _MVP_INSTRCFG0_ALUIN1IMAGNEGATE_SHIFT 15 /**< Shift value for MVP_ALUIN1IMAGNEGATE */ +#define _MVP_INSTRCFG0_ALUIN1IMAGNEGATE_MASK 0x8000UL /**< Bit mask for MVP_ALUIN1IMAGNEGATE */ +#define _MVP_INSTRCFG0_ALUIN1IMAGNEGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN1IMAGNEGATE_DEFAULT \ + (_MVP_INSTRCFG0_ALUIN1IMAGNEGATE_DEFAULT << 15) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define _MVP_INSTRCFG0_ALUIN2REGID_SHIFT 16 /**< Shift value for MVP_ALUIN2REGID */ +#define _MVP_INSTRCFG0_ALUIN2REGID_MASK 0x70000UL /**< Bit mask for MVP_ALUIN2REGID */ +#define _MVP_INSTRCFG0_ALUIN2REGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN2REGID_DEFAULT \ + (_MVP_INSTRCFG0_ALUIN2REGID_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN2REALZERO (0x1UL << 20) /**< Real Zero */ +#define _MVP_INSTRCFG0_ALUIN2REALZERO_SHIFT 20 /**< Shift value for MVP_ALUIN2REALZERO */ +#define _MVP_INSTRCFG0_ALUIN2REALZERO_MASK 0x100000UL /**< Bit mask for MVP_ALUIN2REALZERO */ +#define _MVP_INSTRCFG0_ALUIN2REALZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN2REALZERO_DEFAULT \ + (_MVP_INSTRCFG0_ALUIN2REALZERO_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN2REALNEGATE (0x1UL << 21) /**< Real Negate */ +#define _MVP_INSTRCFG0_ALUIN2REALNEGATE_SHIFT 21 /**< Shift value for MVP_ALUIN2REALNEGATE */ +#define _MVP_INSTRCFG0_ALUIN2REALNEGATE_MASK 0x200000UL /**< Bit mask for MVP_ALUIN2REALNEGATE */ +#define _MVP_INSTRCFG0_ALUIN2REALNEGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN2REALNEGATE_DEFAULT \ + (_MVP_INSTRCFG0_ALUIN2REALNEGATE_DEFAULT << 21) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN2IMAGZERO (0x1UL << 22) /**< Imaginary Not Zero */ +#define _MVP_INSTRCFG0_ALUIN2IMAGZERO_SHIFT 22 /**< Shift value for MVP_ALUIN2IMAGZERO */ +#define _MVP_INSTRCFG0_ALUIN2IMAGZERO_MASK 0x400000UL /**< Bit mask for MVP_ALUIN2IMAGZERO */ +#define _MVP_INSTRCFG0_ALUIN2IMAGZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN2IMAGZERO_DEFAULT \ + (_MVP_INSTRCFG0_ALUIN2IMAGZERO_DEFAULT << 22) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN2IMAGNEGATE (0x1UL << 23) /**< Imaginary Negate */ +#define _MVP_INSTRCFG0_ALUIN2IMAGNEGATE_SHIFT 23 /**< Shift value for MVP_ALUIN2IMAGNEGATE */ +#define _MVP_INSTRCFG0_ALUIN2IMAGNEGATE_MASK 0x800000UL /**< Bit mask for MVP_ALUIN2IMAGNEGATE */ +#define _MVP_INSTRCFG0_ALUIN2IMAGNEGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN2IMAGNEGATE_DEFAULT \ + (_MVP_INSTRCFG0_ALUIN2IMAGNEGATE_DEFAULT << 23) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define _MVP_INSTRCFG0_ALUOUTREGID_SHIFT 28 /**< Shift value for MVP_ALUOUTREGID */ +#define _MVP_INSTRCFG0_ALUOUTREGID_MASK 0x70000000UL /**< Bit mask for MVP_ALUOUTREGID */ +#define _MVP_INSTRCFG0_ALUOUTREGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUOUTREGID_DEFAULT \ + (_MVP_INSTRCFG0_ALUOUTREGID_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ + +/* Bit fields for MVP INSTRCFG1 */ +#define _MVP_INSTRCFG1_RESETVALUE 0x00000000UL /**< Default value for MVP_INSTRCFG1 */ +#define _MVP_INSTRCFG1_MASK 0x3FFFFFFFUL /**< Mask for MVP_INSTRCFG1 */ +#define _MVP_INSTRCFG1_ISTREAM0REGID_SHIFT 0 /**< Shift value for MVP_ISTREAM0REGID */ +#define _MVP_INSTRCFG1_ISTREAM0REGID_MASK 0x7UL /**< Bit mask for MVP_ISTREAM0REGID */ +#define _MVP_INSTRCFG1_ISTREAM0REGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM0REGID_DEFAULT \ + (_MVP_INSTRCFG1_ISTREAM0REGID_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM0LOAD (0x1UL << 3) /**< Load register */ +#define _MVP_INSTRCFG1_ISTREAM0LOAD_SHIFT 3 /**< Shift value for MVP_ISTREAM0LOAD */ +#define _MVP_INSTRCFG1_ISTREAM0LOAD_MASK 0x8UL /**< Bit mask for MVP_ISTREAM0LOAD */ +#define _MVP_INSTRCFG1_ISTREAM0LOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM0LOAD_DEFAULT \ + (_MVP_INSTRCFG1_ISTREAM0LOAD_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYID_SHIFT 4 /**< Shift value for MVP_ISTREAM0ARRAYID */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYID_MASK 0x70UL /**< Bit mask for MVP_ISTREAM0ARRAYID */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM0ARRAYID_DEFAULT \ + (_MVP_INSTRCFG1_ISTREAM0ARRAYID_DEFAULT << 4) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM0 (0x1UL << 7) /**< Increment Array Dimension 0 */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM0_SHIFT 7 /**< Shift value for MVP_ISTREAM0ARRAYINCRDIM0 */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM0_MASK 0x80UL /**< Bit mask for MVP_ISTREAM0ARRAYINCRDIM0 */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM0_DEFAULT \ + (_MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM0_DEFAULT << 7) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM1 (0x1UL << 8) /**< Increment Array Dimension 1 */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM1_SHIFT 8 /**< Shift value for MVP_ISTREAM0ARRAYINCRDIM1 */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM1_MASK 0x100UL /**< Bit mask for MVP_ISTREAM0ARRAYINCRDIM1 */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM1_DEFAULT \ + (_MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM1_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM2 (0x1UL << 9) /**< Increment Array Dimension 2 */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM2_SHIFT 9 /**< Shift value for MVP_ISTREAM0ARRAYINCRDIM2 */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM2_MASK 0x200UL /**< Bit mask for MVP_ISTREAM0ARRAYINCRDIM2 */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM2_DEFAULT \ + (_MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM2_DEFAULT << 9) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define _MVP_INSTRCFG1_ISTREAM1REGID_SHIFT 10 /**< Shift value for MVP_ISTREAM1REGID */ +#define _MVP_INSTRCFG1_ISTREAM1REGID_MASK 0x1C00UL /**< Bit mask for MVP_ISTREAM1REGID */ +#define _MVP_INSTRCFG1_ISTREAM1REGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM1REGID_DEFAULT \ + (_MVP_INSTRCFG1_ISTREAM1REGID_DEFAULT << 10) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM1LOAD (0x1UL << 13) /**< Load register */ +#define _MVP_INSTRCFG1_ISTREAM1LOAD_SHIFT 13 /**< Shift value for MVP_ISTREAM1LOAD */ +#define _MVP_INSTRCFG1_ISTREAM1LOAD_MASK 0x2000UL /**< Bit mask for MVP_ISTREAM1LOAD */ +#define _MVP_INSTRCFG1_ISTREAM1LOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM1LOAD_DEFAULT \ + (_MVP_INSTRCFG1_ISTREAM1LOAD_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYID_SHIFT 14 /**< Shift value for MVP_ISTREAM1ARRAYID */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYID_MASK 0x1C000UL /**< Bit mask for MVP_ISTREAM1ARRAYID */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM1ARRAYID_DEFAULT \ + (_MVP_INSTRCFG1_ISTREAM1ARRAYID_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM0 (0x1UL << 17) /**< Increment Array Dimension 0 */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM0_SHIFT 17 /**< Shift value for MVP_ISTREAM1ARRAYINCRDIM0 */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM0_MASK 0x20000UL /**< Bit mask for MVP_ISTREAM1ARRAYINCRDIM0 */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM0_DEFAULT \ + (_MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM0_DEFAULT << 17) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM1 (0x1UL << 18) /**< Increment Array Dimension 1 */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM1_SHIFT 18 /**< Shift value for MVP_ISTREAM1ARRAYINCRDIM1 */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM1_MASK 0x40000UL /**< Bit mask for MVP_ISTREAM1ARRAYINCRDIM1 */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM1_DEFAULT \ + (_MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM1_DEFAULT << 18) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM2 (0x1UL << 19) /**< Increment Array Dimension 2 */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM2_SHIFT 19 /**< Shift value for MVP_ISTREAM1ARRAYINCRDIM2 */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM2_MASK 0x80000UL /**< Bit mask for MVP_ISTREAM1ARRAYINCRDIM2 */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM2_DEFAULT \ + (_MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM2_DEFAULT << 19) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define _MVP_INSTRCFG1_OSTREAMREGID_SHIFT 20 /**< Shift value for MVP_OSTREAMREGID */ +#define _MVP_INSTRCFG1_OSTREAMREGID_MASK 0x700000UL /**< Bit mask for MVP_OSTREAMREGID */ +#define _MVP_INSTRCFG1_OSTREAMREGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_OSTREAMREGID_DEFAULT \ + (_MVP_INSTRCFG1_OSTREAMREGID_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_OSTREAMSTORE (0x1UL << 23) /**< Store to Register */ +#define _MVP_INSTRCFG1_OSTREAMSTORE_SHIFT 23 /**< Shift value for MVP_OSTREAMSTORE */ +#define _MVP_INSTRCFG1_OSTREAMSTORE_MASK 0x800000UL /**< Bit mask for MVP_OSTREAMSTORE */ +#define _MVP_INSTRCFG1_OSTREAMSTORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_OSTREAMSTORE_DEFAULT \ + (_MVP_INSTRCFG1_OSTREAMSTORE_DEFAULT << 23) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define _MVP_INSTRCFG1_OSTREAMARRAYID_SHIFT 24 /**< Shift value for MVP_OSTREAMARRAYID */ +#define _MVP_INSTRCFG1_OSTREAMARRAYID_MASK 0x7000000UL /**< Bit mask for MVP_OSTREAMARRAYID */ +#define _MVP_INSTRCFG1_OSTREAMARRAYID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_OSTREAMARRAYID_DEFAULT \ + (_MVP_INSTRCFG1_OSTREAMARRAYID_DEFAULT << 24) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_OSTREAMARRAYINCRDIM0 (0x1UL << 27) /**< Increment Array Dimension 0 */ +#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM0_SHIFT 27 /**< Shift value for MVP_OSTREAMARRAYINCRDIM0 */ +#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM0_MASK 0x8000000UL /**< Bit mask for MVP_OSTREAMARRAYINCRDIM0 */ +#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_OSTREAMARRAYINCRDIM0_DEFAULT \ + (_MVP_INSTRCFG1_OSTREAMARRAYINCRDIM0_DEFAULT << 27) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_OSTREAMARRAYINCRDIM1 (0x1UL << 28) /**< Increment Array Dimension 1 */ +#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM1_SHIFT 28 /**< Shift value for MVP_OSTREAMARRAYINCRDIM1 */ +#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM1_MASK 0x10000000UL /**< Bit mask for MVP_OSTREAMARRAYINCRDIM1 */ +#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_OSTREAMARRAYINCRDIM1_DEFAULT \ + (_MVP_INSTRCFG1_OSTREAMARRAYINCRDIM1_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_OSTREAMARRAYINCRDIM2 (0x1UL << 29) /**< Increment Array Dimension 2 */ +#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM2_SHIFT 29 /**< Shift value for MVP_OSTREAMARRAYINCRDIM2 */ +#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM2_MASK 0x20000000UL /**< Bit mask for MVP_OSTREAMARRAYINCRDIM2 */ +#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_OSTREAMARRAYINCRDIM2_DEFAULT \ + (_MVP_INSTRCFG1_OSTREAMARRAYINCRDIM2_DEFAULT << 29) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ + +/* Bit fields for MVP INSTRCFG2 */ +#define _MVP_INSTRCFG2_RESETVALUE 0x00000000UL /**< Default value for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_MASK 0x9FF0FFFFUL /**< Mask for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP0BEGIN (0x1UL << 0) /**< Loop Begin */ +#define _MVP_INSTRCFG2_LOOP0BEGIN_SHIFT 0 /**< Shift value for MVP_LOOP0BEGIN */ +#define _MVP_INSTRCFG2_LOOP0BEGIN_MASK 0x1UL /**< Bit mask for MVP_LOOP0BEGIN */ +#define _MVP_INSTRCFG2_LOOP0BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP0BEGIN_DEFAULT \ + (_MVP_INSTRCFG2_LOOP0BEGIN_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP0END (0x1UL << 1) /**< Loop End */ +#define _MVP_INSTRCFG2_LOOP0END_SHIFT 1 /**< Shift value for MVP_LOOP0END */ +#define _MVP_INSTRCFG2_LOOP0END_MASK 0x2UL /**< Bit mask for MVP_LOOP0END */ +#define _MVP_INSTRCFG2_LOOP0END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP0END_DEFAULT \ + (_MVP_INSTRCFG2_LOOP0END_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP1BEGIN (0x1UL << 2) /**< Loop Begin */ +#define _MVP_INSTRCFG2_LOOP1BEGIN_SHIFT 2 /**< Shift value for MVP_LOOP1BEGIN */ +#define _MVP_INSTRCFG2_LOOP1BEGIN_MASK 0x4UL /**< Bit mask for MVP_LOOP1BEGIN */ +#define _MVP_INSTRCFG2_LOOP1BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP1BEGIN_DEFAULT \ + (_MVP_INSTRCFG2_LOOP1BEGIN_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP1END (0x1UL << 3) /**< Loop End */ +#define _MVP_INSTRCFG2_LOOP1END_SHIFT 3 /**< Shift value for MVP_LOOP1END */ +#define _MVP_INSTRCFG2_LOOP1END_MASK 0x8UL /**< Bit mask for MVP_LOOP1END */ +#define _MVP_INSTRCFG2_LOOP1END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP1END_DEFAULT \ + (_MVP_INSTRCFG2_LOOP1END_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP2BEGIN (0x1UL << 4) /**< Loop Begin */ +#define _MVP_INSTRCFG2_LOOP2BEGIN_SHIFT 4 /**< Shift value for MVP_LOOP2BEGIN */ +#define _MVP_INSTRCFG2_LOOP2BEGIN_MASK 0x10UL /**< Bit mask for MVP_LOOP2BEGIN */ +#define _MVP_INSTRCFG2_LOOP2BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP2BEGIN_DEFAULT \ + (_MVP_INSTRCFG2_LOOP2BEGIN_DEFAULT << 4) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP2END (0x1UL << 5) /**< Loop End */ +#define _MVP_INSTRCFG2_LOOP2END_SHIFT 5 /**< Shift value for MVP_LOOP2END */ +#define _MVP_INSTRCFG2_LOOP2END_MASK 0x20UL /**< Bit mask for MVP_LOOP2END */ +#define _MVP_INSTRCFG2_LOOP2END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP2END_DEFAULT \ + (_MVP_INSTRCFG2_LOOP2END_DEFAULT << 5) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP3BEGIN (0x1UL << 6) /**< Loop Begin */ +#define _MVP_INSTRCFG2_LOOP3BEGIN_SHIFT 6 /**< Shift value for MVP_LOOP3BEGIN */ +#define _MVP_INSTRCFG2_LOOP3BEGIN_MASK 0x40UL /**< Bit mask for MVP_LOOP3BEGIN */ +#define _MVP_INSTRCFG2_LOOP3BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP3BEGIN_DEFAULT \ + (_MVP_INSTRCFG2_LOOP3BEGIN_DEFAULT << 6) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP3END (0x1UL << 7) /**< Loop End */ +#define _MVP_INSTRCFG2_LOOP3END_SHIFT 7 /**< Shift value for MVP_LOOP3END */ +#define _MVP_INSTRCFG2_LOOP3END_MASK 0x80UL /**< Bit mask for MVP_LOOP3END */ +#define _MVP_INSTRCFG2_LOOP3END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP3END_DEFAULT \ + (_MVP_INSTRCFG2_LOOP3END_DEFAULT << 7) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP4BEGIN (0x1UL << 8) /**< Loop Begin */ +#define _MVP_INSTRCFG2_LOOP4BEGIN_SHIFT 8 /**< Shift value for MVP_LOOP4BEGIN */ +#define _MVP_INSTRCFG2_LOOP4BEGIN_MASK 0x100UL /**< Bit mask for MVP_LOOP4BEGIN */ +#define _MVP_INSTRCFG2_LOOP4BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP4BEGIN_DEFAULT \ + (_MVP_INSTRCFG2_LOOP4BEGIN_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP4END (0x1UL << 9) /**< Loop End */ +#define _MVP_INSTRCFG2_LOOP4END_SHIFT 9 /**< Shift value for MVP_LOOP4END */ +#define _MVP_INSTRCFG2_LOOP4END_MASK 0x200UL /**< Bit mask for MVP_LOOP4END */ +#define _MVP_INSTRCFG2_LOOP4END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP4END_DEFAULT \ + (_MVP_INSTRCFG2_LOOP4END_DEFAULT << 9) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP5BEGIN (0x1UL << 10) /**< Loop Begin */ +#define _MVP_INSTRCFG2_LOOP5BEGIN_SHIFT 10 /**< Shift value for MVP_LOOP5BEGIN */ +#define _MVP_INSTRCFG2_LOOP5BEGIN_MASK 0x400UL /**< Bit mask for MVP_LOOP5BEGIN */ +#define _MVP_INSTRCFG2_LOOP5BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP5BEGIN_DEFAULT \ + (_MVP_INSTRCFG2_LOOP5BEGIN_DEFAULT << 10) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP5END (0x1UL << 11) /**< Loop End */ +#define _MVP_INSTRCFG2_LOOP5END_SHIFT 11 /**< Shift value for MVP_LOOP5END */ +#define _MVP_INSTRCFG2_LOOP5END_MASK 0x800UL /**< Bit mask for MVP_LOOP5END */ +#define _MVP_INSTRCFG2_LOOP5END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP5END_DEFAULT \ + (_MVP_INSTRCFG2_LOOP5END_DEFAULT << 11) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP6BEGIN (0x1UL << 12) /**< Loop Begin */ +#define _MVP_INSTRCFG2_LOOP6BEGIN_SHIFT 12 /**< Shift value for MVP_LOOP6BEGIN */ +#define _MVP_INSTRCFG2_LOOP6BEGIN_MASK 0x1000UL /**< Bit mask for MVP_LOOP6BEGIN */ +#define _MVP_INSTRCFG2_LOOP6BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP6BEGIN_DEFAULT \ + (_MVP_INSTRCFG2_LOOP6BEGIN_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP6END (0x1UL << 13) /**< Loop End */ +#define _MVP_INSTRCFG2_LOOP6END_SHIFT 13 /**< Shift value for MVP_LOOP6END */ +#define _MVP_INSTRCFG2_LOOP6END_MASK 0x2000UL /**< Bit mask for MVP_LOOP6END */ +#define _MVP_INSTRCFG2_LOOP6END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP6END_DEFAULT \ + (_MVP_INSTRCFG2_LOOP6END_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP7BEGIN (0x1UL << 14) /**< Loop Begin */ +#define _MVP_INSTRCFG2_LOOP7BEGIN_SHIFT 14 /**< Shift value for MVP_LOOP7BEGIN */ +#define _MVP_INSTRCFG2_LOOP7BEGIN_MASK 0x4000UL /**< Bit mask for MVP_LOOP7BEGIN */ +#define _MVP_INSTRCFG2_LOOP7BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP7BEGIN_DEFAULT \ + (_MVP_INSTRCFG2_LOOP7BEGIN_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP7END (0x1UL << 15) /**< Loop End */ +#define _MVP_INSTRCFG2_LOOP7END_SHIFT 15 /**< Shift value for MVP_LOOP7END */ +#define _MVP_INSTRCFG2_LOOP7END_MASK 0x8000UL /**< Bit mask for MVP_LOOP7END */ +#define _MVP_INSTRCFG2_LOOP7END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP7END_DEFAULT \ + (_MVP_INSTRCFG2_LOOP7END_DEFAULT << 15) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_SHIFT 20 /**< Shift value for MVP_ALUOP */ +#define _MVP_INSTRCFG2_ALUOP_MASK 0x1FF00000UL /**< Bit mask for MVP_ALUOP */ +#define _MVP_INSTRCFG2_ALUOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_NOOP 0x00000000UL /**< Mode NOOP for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_CLEAR 0x00000001UL /**< Mode CLEAR for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_COPY 0x00000041UL /**< Mode COPY for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_SWAP 0x00000042UL /**< Mode SWAP for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_DBL 0x00000043UL /**< Mode DBL for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_FANA 0x00000044UL /**< Mode FANA for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_FANB 0x00000045UL /**< Mode FANB for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_RELU2 0x00000046UL /**< Mode RELU2 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_NRELU2 0x00000047UL /**< Mode NRELU2 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_INC2 0x00000048UL /**< Mode INC2 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_DEC2 0x00000049UL /**< Mode DEC2 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_ADDR 0x0000004AUL /**< Mode ADDR for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MAX 0x0000004BUL /**< Mode MAX for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MIN 0x0000004CUL /**< Mode MIN for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_RSQR2B 0x00000124UL /**< Mode RSQR2B for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_ADDC 0x0000014EUL /**< Mode ADDC for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MAX2A 0x00000153UL /**< Mode MAX2A for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MIN2A 0x00000154UL /**< Mode MIN2A for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_XREALC2 0x0000015EUL /**< Mode XREALC2 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_XIMAGC2 0x0000015FUL /**< Mode XIMAGC2 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_ADDR2B 0x00000161UL /**< Mode ADDR2B for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MAX2B 0x00000162UL /**< Mode MAX2B for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MIN2B 0x00000163UL /**< Mode MIN2B for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MULC 0x0000018DUL /**< Mode MULC for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MULR2A 0x00000197UL /**< Mode MULR2A for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MULR2B 0x00000198UL /**< Mode MULR2B for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_ADDR4 0x0000019AUL /**< Mode ADDR4 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MAX4 0x0000019BUL /**< Mode MAX4 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MIN4 0x0000019CUL /**< Mode MIN4 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_SQRMAGC2 0x0000019DUL /**< Mode SQRMAGC2 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_PRELU2B 0x000001A0UL /**< Mode PRELU2B for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MACC 0x000001CDUL /**< Mode MACC for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_AACC 0x000001CEUL /**< Mode AACC for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_ELU2A 0x000001CFUL /**< Mode ELU2A for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_ELU2B 0x000001D0UL /**< Mode ELU2B for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_IFR2A 0x000001D1UL /**< Mode IFR2A for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_IFR2B 0x000001D2UL /**< Mode IFR2B for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MAXAC2 0x000001D3UL /**< Mode MAXAC2 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MINAC2 0x000001D4UL /**< Mode MINAC2 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_CLIP2A 0x000001D5UL /**< Mode CLIP2A for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_CLIP2B 0x000001D6UL /**< Mode CLIP2B for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MACR2A 0x000001D7UL /**< Mode MACR2A for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MACR2B 0x000001D8UL /**< Mode MACR2B for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_IFC 0x000001D9UL /**< Mode IFC for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_DEFAULT \ + (_MVP_INSTRCFG2_ALUOP_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_NOOP (_MVP_INSTRCFG2_ALUOP_NOOP << 20) /**< Shifted mode NOOP for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_CLEAR (_MVP_INSTRCFG2_ALUOP_CLEAR << 20) /**< Shifted mode CLEAR for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_COPY (_MVP_INSTRCFG2_ALUOP_COPY << 20) /**< Shifted mode COPY for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_SWAP (_MVP_INSTRCFG2_ALUOP_SWAP << 20) /**< Shifted mode SWAP for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_DBL (_MVP_INSTRCFG2_ALUOP_DBL << 20) /**< Shifted mode DBL for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_FANA (_MVP_INSTRCFG2_ALUOP_FANA << 20) /**< Shifted mode FANA for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_FANB (_MVP_INSTRCFG2_ALUOP_FANB << 20) /**< Shifted mode FANB for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_RELU2 (_MVP_INSTRCFG2_ALUOP_RELU2 << 20) /**< Shifted mode RELU2 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_NRELU2 \ + (_MVP_INSTRCFG2_ALUOP_NRELU2 << 20) /**< Shifted mode NRELU2 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_INC2 (_MVP_INSTRCFG2_ALUOP_INC2 << 20) /**< Shifted mode INC2 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_DEC2 (_MVP_INSTRCFG2_ALUOP_DEC2 << 20) /**< Shifted mode DEC2 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_ADDR (_MVP_INSTRCFG2_ALUOP_ADDR << 20) /**< Shifted mode ADDR for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MAX (_MVP_INSTRCFG2_ALUOP_MAX << 20) /**< Shifted mode MAX for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MIN (_MVP_INSTRCFG2_ALUOP_MIN << 20) /**< Shifted mode MIN for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_RSQR2B \ + (_MVP_INSTRCFG2_ALUOP_RSQR2B << 20) /**< Shifted mode RSQR2B for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_ADDC (_MVP_INSTRCFG2_ALUOP_ADDC << 20) /**< Shifted mode ADDC for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MAX2A (_MVP_INSTRCFG2_ALUOP_MAX2A << 20) /**< Shifted mode MAX2A for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MIN2A (_MVP_INSTRCFG2_ALUOP_MIN2A << 20) /**< Shifted mode MIN2A for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_XREALC2 \ + (_MVP_INSTRCFG2_ALUOP_XREALC2 << 20) /**< Shifted mode XREALC2 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_XIMAGC2 \ + (_MVP_INSTRCFG2_ALUOP_XIMAGC2 << 20) /**< Shifted mode XIMAGC2 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_ADDR2B \ + (_MVP_INSTRCFG2_ALUOP_ADDR2B << 20) /**< Shifted mode ADDR2B for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MAX2B (_MVP_INSTRCFG2_ALUOP_MAX2B << 20) /**< Shifted mode MAX2B for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MIN2B (_MVP_INSTRCFG2_ALUOP_MIN2B << 20) /**< Shifted mode MIN2B for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MULC (_MVP_INSTRCFG2_ALUOP_MULC << 20) /**< Shifted mode MULC for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MULR2A \ + (_MVP_INSTRCFG2_ALUOP_MULR2A << 20) /**< Shifted mode MULR2A for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MULR2B \ + (_MVP_INSTRCFG2_ALUOP_MULR2B << 20) /**< Shifted mode MULR2B for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_ADDR4 (_MVP_INSTRCFG2_ALUOP_ADDR4 << 20) /**< Shifted mode ADDR4 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MAX4 (_MVP_INSTRCFG2_ALUOP_MAX4 << 20) /**< Shifted mode MAX4 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MIN4 (_MVP_INSTRCFG2_ALUOP_MIN4 << 20) /**< Shifted mode MIN4 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_SQRMAGC2 \ + (_MVP_INSTRCFG2_ALUOP_SQRMAGC2 << 20) /**< Shifted mode SQRMAGC2 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_PRELU2B \ + (_MVP_INSTRCFG2_ALUOP_PRELU2B << 20) /**< Shifted mode PRELU2B for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MACC (_MVP_INSTRCFG2_ALUOP_MACC << 20) /**< Shifted mode MACC for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_AACC (_MVP_INSTRCFG2_ALUOP_AACC << 20) /**< Shifted mode AACC for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_ELU2A (_MVP_INSTRCFG2_ALUOP_ELU2A << 20) /**< Shifted mode ELU2A for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_ELU2B (_MVP_INSTRCFG2_ALUOP_ELU2B << 20) /**< Shifted mode ELU2B for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_IFR2A (_MVP_INSTRCFG2_ALUOP_IFR2A << 20) /**< Shifted mode IFR2A for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_IFR2B (_MVP_INSTRCFG2_ALUOP_IFR2B << 20) /**< Shifted mode IFR2B for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MAXAC2 \ + (_MVP_INSTRCFG2_ALUOP_MAXAC2 << 20) /**< Shifted mode MAXAC2 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MINAC2 \ + (_MVP_INSTRCFG2_ALUOP_MINAC2 << 20) /**< Shifted mode MINAC2 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_CLIP2A \ + (_MVP_INSTRCFG2_ALUOP_CLIP2A << 20) /**< Shifted mode CLIP2A for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_CLIP2B \ + (_MVP_INSTRCFG2_ALUOP_CLIP2B << 20) /**< Shifted mode CLIP2B for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MACR2A \ + (_MVP_INSTRCFG2_ALUOP_MACR2A << 20) /**< Shifted mode MACR2A for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MACR2B \ + (_MVP_INSTRCFG2_ALUOP_MACR2B << 20) /**< Shifted mode MACR2B for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_IFC (_MVP_INSTRCFG2_ALUOP_IFC << 20) /**< Shifted mode IFC for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ENDPROG (0x1UL << 31) /**< End of Program */ +#define _MVP_INSTRCFG2_ENDPROG_SHIFT 31 /**< Shift value for MVP_ENDPROG */ +#define _MVP_INSTRCFG2_ENDPROG_MASK 0x80000000UL /**< Bit mask for MVP_ENDPROG */ +#define _MVP_INSTRCFG2_ENDPROG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ENDPROG_DEFAULT \ + (_MVP_INSTRCFG2_ENDPROG_DEFAULT << 31) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ + +/* Bit fields for MVP CMD */ +#define _MVP_CMD_RESETVALUE 0x00000000UL /**< Default value for MVP_CMD */ +#define _MVP_CMD_MASK 0x0000000FUL /**< Mask for MVP_CMD */ +#define MVP_CMD_START (0x1UL << 0) /**< Start Command */ +#define _MVP_CMD_START_SHIFT 0 /**< Shift value for MVP_START */ +#define _MVP_CMD_START_MASK 0x1UL /**< Bit mask for MVP_START */ +#define _MVP_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CMD */ +#define MVP_CMD_START_DEFAULT (_MVP_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_CMD */ +#define MVP_CMD_HALT (0x1UL << 1) /**< Halt Command */ +#define _MVP_CMD_HALT_SHIFT 1 /**< Shift value for MVP_HALT */ +#define _MVP_CMD_HALT_MASK 0x2UL /**< Bit mask for MVP_HALT */ +#define _MVP_CMD_HALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CMD */ +#define MVP_CMD_HALT_DEFAULT (_MVP_CMD_HALT_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_CMD */ +#define MVP_CMD_STEP (0x1UL << 2) /**< Step Command */ +#define _MVP_CMD_STEP_SHIFT 2 /**< Shift value for MVP_STEP */ +#define _MVP_CMD_STEP_MASK 0x4UL /**< Bit mask for MVP_STEP */ +#define _MVP_CMD_STEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CMD */ +#define MVP_CMD_STEP_DEFAULT (_MVP_CMD_STEP_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_CMD */ +#define MVP_CMD_INIT (0x1UL << 3) /**< Initialization Command/Qualifier */ +#define _MVP_CMD_INIT_SHIFT 3 /**< Shift value for MVP_INIT */ +#define _MVP_CMD_INIT_MASK 0x8UL /**< Bit mask for MVP_INIT */ +#define _MVP_CMD_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CMD */ +#define MVP_CMD_INIT_DEFAULT (_MVP_CMD_INIT_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_CMD */ + +/* Bit fields for MVP DEBUGEN */ +#define _MVP_DEBUGEN_RESETVALUE 0x00000000UL /**< Default value for MVP_DEBUGEN */ +#define _MVP_DEBUGEN_MASK 0x7003FDFEUL /**< Mask for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP0DONE (0x1UL << 1) /**< Enable Breakpoint on Loop Done */ +#define _MVP_DEBUGEN_BKPTLOOP0DONE_SHIFT 1 /**< Shift value for MVP_BKPTLOOP0DONE */ +#define _MVP_DEBUGEN_BKPTLOOP0DONE_MASK 0x2UL /**< Bit mask for MVP_BKPTLOOP0DONE */ +#define _MVP_DEBUGEN_BKPTLOOP0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP0DONE_DEFAULT \ + (_MVP_DEBUGEN_BKPTLOOP0DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP1DONE (0x1UL << 2) /**< Enable Breakpoint on Loop Done */ +#define _MVP_DEBUGEN_BKPTLOOP1DONE_SHIFT 2 /**< Shift value for MVP_BKPTLOOP1DONE */ +#define _MVP_DEBUGEN_BKPTLOOP1DONE_MASK 0x4UL /**< Bit mask for MVP_BKPTLOOP1DONE */ +#define _MVP_DEBUGEN_BKPTLOOP1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP1DONE_DEFAULT \ + (_MVP_DEBUGEN_BKPTLOOP1DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP2DONE (0x1UL << 3) /**< Enable Breakpoint on Loop Done */ +#define _MVP_DEBUGEN_BKPTLOOP2DONE_SHIFT 3 /**< Shift value for MVP_BKPTLOOP2DONE */ +#define _MVP_DEBUGEN_BKPTLOOP2DONE_MASK 0x8UL /**< Bit mask for MVP_BKPTLOOP2DONE */ +#define _MVP_DEBUGEN_BKPTLOOP2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP2DONE_DEFAULT \ + (_MVP_DEBUGEN_BKPTLOOP2DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP3DONE (0x1UL << 4) /**< Enable Breakpoint on Loop Done */ +#define _MVP_DEBUGEN_BKPTLOOP3DONE_SHIFT 4 /**< Shift value for MVP_BKPTLOOP3DONE */ +#define _MVP_DEBUGEN_BKPTLOOP3DONE_MASK 0x10UL /**< Bit mask for MVP_BKPTLOOP3DONE */ +#define _MVP_DEBUGEN_BKPTLOOP3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP3DONE_DEFAULT \ + (_MVP_DEBUGEN_BKPTLOOP3DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP4DONE (0x1UL << 5) /**< Enable Breakpoint on Loop Done */ +#define _MVP_DEBUGEN_BKPTLOOP4DONE_SHIFT 5 /**< Shift value for MVP_BKPTLOOP4DONE */ +#define _MVP_DEBUGEN_BKPTLOOP4DONE_MASK 0x20UL /**< Bit mask for MVP_BKPTLOOP4DONE */ +#define _MVP_DEBUGEN_BKPTLOOP4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP4DONE_DEFAULT \ + (_MVP_DEBUGEN_BKPTLOOP4DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP5DONE (0x1UL << 6) /**< Enable Breakpoint on Loop Done */ +#define _MVP_DEBUGEN_BKPTLOOP5DONE_SHIFT 6 /**< Shift value for MVP_BKPTLOOP5DONE */ +#define _MVP_DEBUGEN_BKPTLOOP5DONE_MASK 0x40UL /**< Bit mask for MVP_BKPTLOOP5DONE */ +#define _MVP_DEBUGEN_BKPTLOOP5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP5DONE_DEFAULT \ + (_MVP_DEBUGEN_BKPTLOOP5DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP6DONE (0x1UL << 7) /**< Enable Breakpoint on Loop Done */ +#define _MVP_DEBUGEN_BKPTLOOP6DONE_SHIFT 7 /**< Shift value for MVP_BKPTLOOP6DONE */ +#define _MVP_DEBUGEN_BKPTLOOP6DONE_MASK 0x80UL /**< Bit mask for MVP_BKPTLOOP6DONE */ +#define _MVP_DEBUGEN_BKPTLOOP6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP6DONE_DEFAULT \ + (_MVP_DEBUGEN_BKPTLOOP6DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP7DONE (0x1UL << 8) /**< Enable Breakpoint on Loop Done */ +#define _MVP_DEBUGEN_BKPTLOOP7DONE_SHIFT 8 /**< Shift value for MVP_BKPTLOOP7DONE */ +#define _MVP_DEBUGEN_BKPTLOOP7DONE_MASK 0x100UL /**< Bit mask for MVP_BKPTLOOP7DONE */ +#define _MVP_DEBUGEN_BKPTLOOP7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP7DONE_DEFAULT \ + (_MVP_DEBUGEN_BKPTLOOP7DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTALUNAN (0x1UL << 10) /**< Enable Breakpoint on ALUNAN */ +#define _MVP_DEBUGEN_BKPTALUNAN_SHIFT 10 /**< Shift value for MVP_BKPTALUNAN */ +#define _MVP_DEBUGEN_BKPTALUNAN_MASK 0x400UL /**< Bit mask for MVP_BKPTALUNAN */ +#define _MVP_DEBUGEN_BKPTALUNAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTALUNAN_DEFAULT \ + (_MVP_DEBUGEN_BKPTALUNAN_DEFAULT << 10) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTR0POSREAL (0x1UL << 11) /**< Enable Breakpoint on R0POSREAL */ +#define _MVP_DEBUGEN_BKPTR0POSREAL_SHIFT 11 /**< Shift value for MVP_BKPTR0POSREAL */ +#define _MVP_DEBUGEN_BKPTR0POSREAL_MASK 0x800UL /**< Bit mask for MVP_BKPTR0POSREAL */ +#define _MVP_DEBUGEN_BKPTR0POSREAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTR0POSREAL_DEFAULT \ + (_MVP_DEBUGEN_BKPTR0POSREAL_DEFAULT << 11) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTALUOF (0x1UL << 12) /**< Enable Breakpoint on ALUOF */ +#define _MVP_DEBUGEN_BKPTALUOF_SHIFT 12 /**< Shift value for MVP_BKPTALUOF */ +#define _MVP_DEBUGEN_BKPTALUOF_MASK 0x1000UL /**< Bit mask for MVP_BKPTALUOF */ +#define _MVP_DEBUGEN_BKPTALUOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTALUOF_DEFAULT \ + (_MVP_DEBUGEN_BKPTALUOF_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTALUUF (0x1UL << 13) /**< Enable Breakpoint on ALUUF */ +#define _MVP_DEBUGEN_BKPTALUUF_SHIFT 13 /**< Shift value for MVP_BKPTALUUF */ +#define _MVP_DEBUGEN_BKPTALUUF_MASK 0x2000UL /**< Bit mask for MVP_BKPTALUUF */ +#define _MVP_DEBUGEN_BKPTALUUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTALUUF_DEFAULT \ + (_MVP_DEBUGEN_BKPTALUUF_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTSTORECONVERTOF (0x1UL << 14) /**< Enable Breakpoint on STORECONVERTOF */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTOF_SHIFT 14 /**< Shift value for MVP_BKPTSTORECONVERTOF */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTOF_MASK 0x4000UL /**< Bit mask for MVP_BKPTSTORECONVERTOF */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTSTORECONVERTOF_DEFAULT \ + (_MVP_DEBUGEN_BKPTSTORECONVERTOF_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTSTORECONVERTUF (0x1UL << 15) /**< Enable Breakpoint on STORECONVERTUF */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTUF_SHIFT 15 /**< Shift value for MVP_BKPTSTORECONVERTUF */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTUF_MASK 0x8000UL /**< Bit mask for MVP_BKPTSTORECONVERTUF */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTSTORECONVERTUF_DEFAULT \ + (_MVP_DEBUGEN_BKPTSTORECONVERTUF_DEFAULT << 15) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTSTORECONVERTINF (0x1UL << 16) /**< Enable Breakpoint on STORECONVERTINF */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTINF_SHIFT 16 /**< Shift value for MVP_BKPTSTORECONVERTINF */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTINF_MASK 0x10000UL /**< Bit mask for MVP_BKPTSTORECONVERTINF */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTINF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTSTORECONVERTINF_DEFAULT \ + (_MVP_DEBUGEN_BKPTSTORECONVERTINF_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTSTORECONVERTNAN (0x1UL << 17) /**< Enable Breakpoint on STORECONVERTNAN */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTNAN_SHIFT 17 /**< Shift value for MVP_BKPTSTORECONVERTNAN */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTNAN_MASK 0x20000UL /**< Bit mask for MVP_BKPTSTORECONVERTNAN */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTNAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTSTORECONVERTNAN_DEFAULT \ + (_MVP_DEBUGEN_BKPTSTORECONVERTNAN_DEFAULT << 17) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_DEBUGSTEPCNTEN (0x1UL << 28) /**< Debug Step Count Enable */ +#define _MVP_DEBUGEN_DEBUGSTEPCNTEN_SHIFT 28 /**< Shift value for MVP_DEBUGSTEPCNTEN */ +#define _MVP_DEBUGEN_DEBUGSTEPCNTEN_MASK 0x10000000UL /**< Bit mask for MVP_DEBUGSTEPCNTEN */ +#define _MVP_DEBUGEN_DEBUGSTEPCNTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_DEBUGSTEPCNTEN_DEFAULT \ + (_MVP_DEBUGEN_DEBUGSTEPCNTEN_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_DEBUGBKPTALLEN (0x1UL << 29) /**< Trigger Breakpoint when ALL conditions match*/ +#define _MVP_DEBUGEN_DEBUGBKPTALLEN_SHIFT 29 /**< Shift value for MVP_DEBUGBKPTALLEN */ +#define _MVP_DEBUGEN_DEBUGBKPTALLEN_MASK 0x20000000UL /**< Bit mask for MVP_DEBUGBKPTALLEN */ +#define _MVP_DEBUGEN_DEBUGBKPTALLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_DEBUGBKPTALLEN_DEFAULT \ + (_MVP_DEBUGEN_DEBUGBKPTALLEN_DEFAULT << 29) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_DEBUGBKPTANYEN (0x1UL << 30) /**< Enable Breakpoint when ANY conditions match */ +#define _MVP_DEBUGEN_DEBUGBKPTANYEN_SHIFT 30 /**< Shift value for MVP_DEBUGBKPTANYEN */ +#define _MVP_DEBUGEN_DEBUGBKPTANYEN_MASK 0x40000000UL /**< Bit mask for MVP_DEBUGBKPTANYEN */ +#define _MVP_DEBUGEN_DEBUGBKPTANYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_DEBUGBKPTANYEN_DEFAULT \ + (_MVP_DEBUGEN_DEBUGBKPTANYEN_DEFAULT << 30) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ + +/* Bit fields for MVP DEBUGSTEPCNT */ +#define _MVP_DEBUGSTEPCNT_RESETVALUE 0x00000000UL /**< Default value for MVP_DEBUGSTEPCNT */ +#define _MVP_DEBUGSTEPCNT_MASK 0x00FFFFFFUL /**< Mask for MVP_DEBUGSTEPCNT */ +#define _MVP_DEBUGSTEPCNT_DEBUGSTEPCNT_SHIFT 0 /**< Shift value for MVP_DEBUGSTEPCNT */ +#define _MVP_DEBUGSTEPCNT_DEBUGSTEPCNT_MASK 0xFFFFFFUL /**< Bit mask for MVP_DEBUGSTEPCNT */ +#define _MVP_DEBUGSTEPCNT_DEBUGSTEPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGSTEPCNT */ +#define MVP_DEBUGSTEPCNT_DEBUGSTEPCNT_DEFAULT \ + (_MVP_DEBUGSTEPCNT_DEBUGSTEPCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_DEBUGSTEPCNT */ + +/* Bit fields for MVP LOAD0ADDR */ +#define _MVP_LOAD0ADDR_RESETVALUE 0x00000000UL /**< Default value for MVP_LOAD0ADDR */ +#define _MVP_LOAD0ADDR_MASK 0xFFFFFFFFUL /**< Mask for MVP_LOAD0ADDR */ +#define _MVP_LOAD0ADDR_ADDR_SHIFT 0 /**< Shift value for MVP_ADDR */ +#define _MVP_LOAD0ADDR_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MVP_ADDR */ +#define _MVP_LOAD0ADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOAD0ADDR */ +#define MVP_LOAD0ADDR_ADDR_DEFAULT \ + (_MVP_LOAD0ADDR_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_LOAD0ADDR */ + +/* Bit fields for MVP LOAD1ADDR */ +#define _MVP_LOAD1ADDR_RESETVALUE 0x00000000UL /**< Default value for MVP_LOAD1ADDR */ +#define _MVP_LOAD1ADDR_MASK 0xFFFFFFFFUL /**< Mask for MVP_LOAD1ADDR */ +#define _MVP_LOAD1ADDR_ADDR_SHIFT 0 /**< Shift value for MVP_ADDR */ +#define _MVP_LOAD1ADDR_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MVP_ADDR */ +#define _MVP_LOAD1ADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOAD1ADDR */ +#define MVP_LOAD1ADDR_ADDR_DEFAULT \ + (_MVP_LOAD1ADDR_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_LOAD1ADDR */ + +/* Bit fields for MVP STOREADDR */ +#define _MVP_STOREADDR_RESETVALUE 0x00000000UL /**< Default value for MVP_STOREADDR */ +#define _MVP_STOREADDR_MASK 0xFFFFFFFFUL /**< Mask for MVP_STOREADDR */ +#define _MVP_STOREADDR_ADDR_SHIFT 0 /**< Shift value for MVP_ADDR */ +#define _MVP_STOREADDR_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MVP_ADDR */ +#define _MVP_STOREADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_STOREADDR */ +#define MVP_STOREADDR_ADDR_DEFAULT \ + (_MVP_STOREADDR_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_STOREADDR */ + +#endif /* SI91X_MVP_H */ From e758ba3864715d288888fb763d107981ca848b76 Mon Sep 17 00:00:00 2001 From: Aksel Skauge Mellbye Date: Thu, 8 Aug 2024 12:51:19 +0200 Subject: [PATCH 03/62] wiseconnect: Add common flash mode config Origin: Silicon Labs WiSeConnect SDK License: MSLA URL: https://github.com/siliconlabs/wiseconnect commit: e97a0ed00ddda347a8a39e8276f470e1c5fea469 Purpose: Enable common flash boards Signed-off-by: Aksel Skauge Mellbye --- .../mcu/core/chip/src/rsi_deepsleep_soc.c | 694 ++++++++++++++++++ 1 file changed, 694 insertions(+) create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/core/chip/src/rsi_deepsleep_soc.c diff --git a/wiseconnect/components/device/silabs/si91x/mcu/core/chip/src/rsi_deepsleep_soc.c b/wiseconnect/components/device/silabs/si91x/mcu/core/chip/src/rsi_deepsleep_soc.c new file mode 100644 index 000000000..b54375dcd --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/core/chip/src/rsi_deepsleep_soc.c @@ -0,0 +1,694 @@ +/******************************************************************************* +* @file rsi_deepsleep_soc.c +* @brief +******************************************************************************* +* # License +* Copyright 2020 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +/** + * Includes + */ +#include "rsi_ccp_common.h" +#include "rsi_power_save.h" +#include "rsi_temp_sensor.h" +#ifdef DEBUG_UART +#include "rsi_debug.h" +#endif + +void fpuInit(void); +#define NWPAON_MEM_HOST_ACCESS_CTRL_CLEAR_1 (*(volatile uint32_t *)(0x41300000 + 0x4)) +#define NWPAON_MEM_HOST_ACCESS_CTRL_SET_1 (*(volatile uint32_t *)(0x41300000 + 0x0)) +#define M4SS_TASS_CTRL_SET_REG (*(volatile uint32_t *)(0x24048400 + 0x34)) +#define M4SS_TASS_CTRL_CLEAR_REG (*(volatile uint32_t *)(0x24048400 + 0x38)) +#define M4SS_TASS_CTRL_CLR_REG (*(volatile uint32_t *)(0x24048400 + 0x38)) +#define MAX_NVIC_REGS 4 // Max Interrupts register +#define MAX_IPS 240 // Max Interrupt Priority registers +#define MAX_SHP 12 //Max System Handlers Priority registers + +#ifdef SLI_SI91X_MCU_4MB_LITE_IMAGE +#define MBR_MAGIC_WORD (*(volatile uint32_t *)(0x8160000)) +#else +#define MBR_MAGIC_WORD (*(volatile uint32_t *)(0x81F0000)) +#endif + +#define SL_SCDC_SLEEP 1 +#define SL_SCDC_ACTIVE 0 + +/* MACRO definition for External LDO Handle, the user must provide the definition for External LDO ON/OFF Handle*/ +#ifndef EXTERNAL_LDO_HANDLE +/*If User Handle definition is not available keep a Null Definition*/ +#define EXTERNAL_LDO_HANDLE +#endif + +extern void set_scdc(uint32_t Deepsleep); + +#ifdef SLI_SI91X_MCU_ENABLE_PSRAM_FEATURE +#include "sl_si91x_psram_config.h" +#if PSRAM_HALF_SLEEP_SUPPORTED != FALSE +extern sl_psram_return_type_t sl_si91x_psram_sleep(void); +extern sl_psram_return_type_t sl_si91x_psram_wakeup(void); +#endif +#endif + +uint32_t nvic_enable[MAX_NVIC_REGS] = { 0 }; +uint8_t nvic_ip_reg[MAX_IPS] = { 0 }; +uint8_t scs_shp_reg[MAX_SHP] = { 0 }; +volatile uint32_t msp_value, psp_value, control_reg_val; + +volatile uint32_t sl_magic_word_value = 0; + +#if defined(SLI_SI91X_MCU_ENABLE_RAM_BASED_EXECUTION) +extern char ram_vector[SI91X_VECTOR_TABLE_ENTRIES]; +#endif + +/** + * @fn void RSI_Save_Context(void) + * @brief This function is to save Stack pointer value and Control registers. + * + */ +void RSI_Save_Context(void) +{ + msp_value = __get_MSP(); + psp_value = __get_PSP(); + control_reg_val = __get_CONTROL(); +} +/** + * @fn void RSI_Restore_Context(void) + * @brief This function is to Restore Stack pointer value and Control registers. + * + */ +#ifdef SLI_SI91X_ENABLE_OS +STATIC INLINE void RSI_Restore_Context(void) +{ + __set_CONTROL(control_reg_val); + __set_PSP(psp_value); + __set_MSP(msp_value); +} +#endif +#if defined(__CC_ARM) /*------------------ARM CC Compiler -----------------*/ +/** + * @fn __asm void RSI_PS_SaveCpuContext(void) + * @brief This API is used to save the CPU status register into RAM, this API should be used when sleep with RET is required + * @return none + */ +__asm void RSI_PS_SaveCpuContext(void) +{ + IMPORT __sp; + PUSH{ r0 }; + PUSH{ r1 }; + PUSH{ r2 }; + PUSH{ r3 }; + PUSH{ r4 }; + PUSH{ r5 }; + PUSH{ r6 }; + PUSH{ r7 }; + PUSH{ r8 }; + PUSH{ r9 }; + PUSH{ r10 }; + PUSH{ r11 }; + PUSH{ r12 }; + PUSH{ r14 }; + LDR r0, = __sp; + MRS r1, msp; + STR r1, [r0]; + WFI; +} + +/** + * @fn void RSI_PS_RestoreCpuContext(void) + * @brief This API is used to restore the current CPU processing content from (POP) stack + * @return none + */ +__asm void RSI_PS_RestoreCpuContext(void) +{ + IMPORT __sp; + LDR r0, = __sp; + LDR sp, [r0, #0]; + POP{ r14 }; + POP{ r12 }; + POP{ r11 }; + POP{ r10 }; + POP{ r9 }; + POP{ r8 }; + POP{ r7 }; + POP{ r6 }; + POP{ r5 }; + POP{ r4 }; + POP{ r3 }; + POP{ r2 }; + POP{ r1 }; + POP{ r0 }; + BX LR; +} +#endif /*------------------ARM CC Compiler -----------------*/ + +#if defined(__GNUC__) /*------------------ GNU Compiler ---------------------*/ + +/** + * @fn void RSI_PS_SaveCpuContext(void) + * @brief This API is used to save the CPU status register into RAM, this API should be used when sleep with RET is required + * @return none + */ +void RSI_PS_SaveCpuContext(void) +{ + __asm("push {r0}"); + __asm("push {r1}"); + __asm("push {r2}"); + __asm("push {r3}"); + __asm("push {r4}"); + __asm("push {r5}"); + __asm("push {r6}"); + __asm("push {r7}"); + __asm("push {r8}"); + __asm("push {r9}"); + __asm("push {r10}"); + __asm("push {r11}"); + __asm("push {r12}"); + __asm("push {r14}"); + + /*R13 Stack pointer */ + __asm("mov %0, sp\n\t" : "=r"(__sp)); + __asm("WFI"); +} + +/** + * @fn void RSI_PS_RestoreCpuContext(void) + * @brief This API is used to restore the current CPU processing content from (POP) stack + * @return none + */ +void RSI_PS_RestoreCpuContext(void) +{ + __asm("ldr r0 , =__sp"); + __asm("ldr sp , [r0 , #0]"); + __asm("pop {r14}"); + __asm("pop {r12}"); + __asm("pop {r11}"); + __asm("pop {r10}"); + __asm("pop {r9}"); + __asm("pop {r8}"); + __asm("pop {r7}"); + __asm("pop {r6}"); + __asm("pop {r5}"); + __asm("pop {r4}"); + __asm("pop {r3}"); + __asm("pop {r2}"); + __asm("pop {r1}"); + __asm("pop {r0}"); +} +#endif /*------------------ GNU Compiler ---------------------*/ + +#if defined(__ICCARM__) /*------------------ IAR Compiler ---------------------*/ +/** + * @fn void RSI_PS_SaveCpuContext(void) + * @brief This API is used to save the CPU status register into RAM, this API should be used when sleep with RET is required + * @return none + */ +void RSI_PS_SaveCpuContext(void) +{ + __asm("push {r0}"); + __asm("push {r1}"); + __asm("push {r2}"); + __asm("push {r3}"); + __asm("push {r4}"); + __asm("push {r5}"); + __asm("push {r6}"); + __asm("push {r7}"); + __asm("push {r8}"); + __asm("push {r9}"); + __asm("push {r10}"); + __asm("push {r11}"); + __asm("push {r12}"); + __asm("push {r14}"); + + /*R13 Stack pointer */ + __asm("mov %0, sp\n\t" : "=r"(__sp)); + __asm("WFI"); +} + +/** + * @fn void RSI_PS_RestoreCpuContext(void) + * @brief This API is used to restore the current CPU processing content from (POP) stack + * @return none + */ +void RSI_PS_RestoreCpuContext(void) +{ + __asm("ldr r0 , =__sp"); + __asm("ldr sp , [r0 , #0]"); + __asm("pop {r14}"); + __asm("pop {r12}"); + __asm("pop {r11}"); + __asm("pop {r10}"); + __asm("pop {r9}"); + __asm("pop {r8}"); + __asm("pop {r7}"); + __asm("pop {r6}"); + __asm("pop {r5}"); + __asm("pop {r4}"); + __asm("pop {r3}"); + __asm("pop {r2}"); + __asm("pop {r1}"); + __asm("pop {r0}"); +} +#endif /*------------------ IAR Compiler ---------------------*/ + +#ifdef SLI_SI91X_MCU_COMMON_FLASH_MODE +/** + * @fn void RSI_Set_Cntrls_To_M4(void) + * @brief This API is used to set m4ss_ref_clk_mux_ctrl ,tass_ref_clk_mux_ctrl, AON domain power supply controls + * form TA to M4 + * + * + * @return none + */ +void RSI_Set_Cntrls_To_M4(void) +{ + volatile uint8_t delay; +#ifdef SLI_SI917B0 + //!take TASS ref clock control to M4 + MCUAON_CONTROL_REG4 &= ~(MCU_TASS_REF_CLK_SEL_MUX_CTRL); +#else + /* m4ss_ref_clk_mux_ctrl and tass_ref_clk_mux_ctr in M4 Control */ + NWPAON_MEM_HOST_ACCESS_CTRL_CLEAR_1 = (M4SS_REF_CLK_MUX_CTRL | TASS_REF_CLK_MUX_CTRL); +#endif + /* M4SS controlling Power supply for TASS AON domain */ + BATT_FF->M4SS_TASS_CTRL_SET_REG_b.M4SS_CTRL_TASS_AON_PWRGATE_EN = ENABLE; + /* M4SS controlling Power supply for TASS AON domains isolation enable in bypass mode*/ + BATT_FF->M4SS_TASS_CTRL_SET_REG_b.M4SS_CTRL_TASS_AON_DISABLE_ISOLATION_BYPASS = ENABLE; + /* M4SS controlling Power supply for TASS AON domains reset pin in bypass mode. */ + M4SS_TASS_CTRL_CLR_REG = M4SS_CTRL_TASS_AON_PWR_DMN_RST_BYPASS_BIT; + for (delay = 0; delay < 10; delay++) { + __ASM("NOP"); + } +} +/** + * @fn void RSI_Set_Cntrls_To_TA(void) + * @brief This API is used to set m4ss_ref_clk_mux_ctrl ,tass_ref_clk_mux_ctrl ,AON domain power supply controls + * form M4 to TA + * + * + * @return none + */ +void RSI_Set_Cntrls_To_TA(void) +{ + /* tass_ref_clk_mux_ctr in TA Control */ + NWPAON_MEM_HOST_ACCESS_CTRL_SET_1 = TASS_REF_CLK_MUX_CTRL; +} +#endif + +/** + * @fn rsi_error_t RSI_PS_EnterDeepSleep(SLEEP_TYPE_T sleepType , uint8_t lf_clk_mode) + * @brief This is the common API to keep the system in sleep state. from all possible active states. + * @param[in] sleepType : selects the retention or non retention mode of processor. refer 'SLEEP_TYPE_T'. + * SLEEP_WITH_RETENTION : When this is used, user must configure the which RAMs to be retained during sleep by using the 'RSI_PS_SetRamRetention()' function. + * @param[in] lf_clk_mode : This parameter is used to switch the processor clock from high frequency clock to low-frequency clock. This is used in some critical power save cases. + * 0: 'DISABLE_LF_MODE' Normal mode of operation , recommended in most of the applications. + * 1: 'LF_32_KHZ_RC' Processor clock is configured to low-frequency RC clock + * 2: 'LF_32_KHZ_XTAL' Processor clock is configured to low-frequency XTAL clock + * 3: 'EXTERNAL_CAP_MODE' Switches the supply to internal cap mode 0.95V. + * @par note + \n User must ensure the selected clocks are active before selecting the 'LF_32_KHZ_RC' and 'LF_32_KHZ_XTAL' clocks to the processor using this API. + * @return Returns the execution status. + */ +rsi_error_t RSI_PS_EnterDeepSleep(SLEEP_TYPE_T sleepType, uint8_t lf_clk_mode) +{ + volatile int var = 0, enable_sdcss_based_wakeup = 0, enable_m4ulp_retention = 0, Temp; + uint32_t ipmuDummyRead = 0, m4ulp_ram_core_status = 0, m4ulp_ram_peri_status = 0, disable_pads_ctrl = 0, + ulp_proc_clk = 0; + volatile uint8_t in_ps2_state = 0, x = 0; + sl_p2p_intr_status_bkp_t p2p_intr_status_bkp; + + /*Save the NVIC registers */ + for (var = 0; var < MAX_NVIC_REGS; ++var) { + nvic_enable[var] = NVIC->ISER[var]; + } + /* Save the Interrupt Priority Register */ + for (var = 0; var < MAX_IPS; ++var) { + nvic_ip_reg[var] = NVIC->IP[var]; + } + /* Save the System Handlers Priority Registers */ + for (var = 0; var < MAX_SHP; ++var) { + scs_shp_reg[var] = SCB->SHP[var]; + } + /*store the NPSS interrupt mask clear status*/ + npssIntrState = NPSS_INTR_MASK_CLR_REG; + + /*Clear AUX and DAC pg enables */ + if (!((MCU_FSM->MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE_b.SDCSS_BASED_WAKEUP_b) + || (MCU_FSM->MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE_b.ULPSS_BASED_WAKEUP_b))) { + RSI_IPMU_PowerGateClr(AUXDAC_PG_ENB | AUXADC_PG_ENB); + } + /*Check the PS2 state or not*/ + if (M4_ULP_SLP_STATUS_REG & ULP_MODE_SWITCHED_NPSS) { + + in_ps2_state = 1U; + + if (!((MCU_FSM->MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE_b.SDCSS_BASED_WAKEUP_b) + || (MCU_FSM->MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE_b.ULPSS_BASED_WAKEUP_b))) { + disable_pads_ctrl = (ULP_SPI_MEM_MAP(0x141) & BIT(11)); // ULP PADS PDO Status + ULP_SPI_MEM_MAP(0x141) &= ~(BIT(11)); // ULP PADS PDO OFF + enable_sdcss_based_wakeup = 1; + RSI_PS_SetWkpSources(SDCSS_BASED_WAKEUP); + } + + if (!(MCU_FSM->MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE_b.M4ULP_RAM_RETENTION_MODE_EN_b)) { + enable_m4ulp_retention = 1; + m4ulp_ram_core_status = RSI_PS_M4ssRamBanksGetPowerSts(); + m4ulp_ram_peri_status = RSI_PS_M4ssRamBanksGetPeriPowerSts(); + RSI_PS_M4ssRamBanksPowerDown(RAM_BANK_7 | RAM_BANK_8 | RAM_BANK_9); + RSI_PS_M4ssRamBanksPeriPowerDown(RAM_BANK_7 | RAM_BANK_8 | RAM_BANK_9); +#ifdef CHIP_9118 + RSI_PS_SetRamRetention(M4ULP_RAM_RETENTION_MODE_EN); +#endif + } + } + /*Move to LP mode */ + RSI_IPMU_RetnLdoLpmode(); + if (sleepType == SLEEP_WITHOUT_RETENTION) { + /*POC1 */ + RSI_IPMU_PocbiasCurrent(); + /*RO32K_00_EFUSE. */ + RSI_IPMU_RO32khzTrim00Efuse(); + /*RETN1 */ + RSI_IPMU_RetnLdoLpmode(); + /*RETN0 */ + RSI_IPMU_RetnLdoVoltsel(); + } + + if (!((in_ps2_state) && (MCU_FSM->MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE_b.ULPSS_BASED_WAKEUP_b))) { +#if (XTAL_CAP_MODE == POWER_TARN_CONDITIONAL_USE) + if (lf_clk_mode & BIT(4)) { + RSI_PS_NpssPeriPowerUp(SLPSS_PWRGATE_ULP_MCUTS); + /*configure the slope,nominal temperature and f2_nominal*/ + RSI_TS_Config(MCU_TEMP, 25); + /*disable the bjt based temp sensor*/ + RSI_TS_RoBjtEnable(MCU_TEMP, 0); + /*Enable the RO based temp sensor*/ + RSI_TS_Enable(MCU_TEMP, 1); + /*update the temperature periodically*/ + RSI_Periodic_TempUpdate(TIME_PERIOD, 1, 0); + /*read the temperature*/ + Temp = (int)RSI_TS_ReadTemp(MCU_TEMP); + if (Temp > 45) { + // disable the XTAL CAP mode + RSI_IPMU_ProgramConfigData(lp_scdc_extcapmode); + } + } +#endif + +#if (XTAL_CAP_MODE == POWER_TARN_ALWAYS_USE) + // disable the XTAL CAP mode + RSI_IPMU_ProgramConfigData(lp_scdc_extcapmode); +#endif + } + + if (!((lf_clk_mode == HF_MHZ_RO))) { + /*Clear IPMU BITS*/ + RSI_PS_LatchCntrlClr(LATCH_TOP_SPI | LATCH_TRANSPARENT_HF | LATCH_TRANSPARENT_LF); + } + + ipmuDummyRead = MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP; + + /*Update the SCB with Deep sleep BIT */ + SCB->SCR = 0x4; + + if (in_ps2_state) { + /*Read processor clock */ + ulp_proc_clk = ULPCLK->ULP_TA_CLK_GEN_REG_b.ULP_PROC_CLK_SEL; + + /*LF processor clock configuration */ + switch (lf_clk_mode & 0x7) { + case DISABLE_LF_MODE: + /*Do nothing*/ + break; + case LF_32_KHZ_RC: + ULPCLK->ULP_TA_CLK_GEN_REG_b.ULP_PROC_CLK_SEL = 2U; + break; + case LF_32_KHZ_XTAL: + ULPCLK->ULP_TA_CLK_GEN_REG_b.ULP_PROC_CLK_SEL = 3U; + break; + case HF_MHZ_RO: + ULPCLK->ULP_TA_CLK_GEN_REG_b.ULP_PROC_CLK_SEL = 5U; + break; + default: + return INVALID_PARAMETERS; + } + /* HF processor clock */ + } + + /* Before sleep,Reduce the SCDC voltage by one value */ + set_scdc(SL_SCDC_SLEEP); + +#ifdef SLI_SI91X_MCU_ENABLE_PSRAM_FEATURE +#if (defined SLI_SI91X_MCU_INTERNAL_LDO_FOR_PSRAM) + RSI_PS_M4ssPeriPowerUp(M4SS_PWRGATE_ULP_EFUSE_PERI); + if (sleepType == SLEEP_WITH_RETENTION) { + //!enable flash LDO and PMU DCDC ON in M4 for PSRAM with retention + MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE_REG |= (LDO_FLASH_ON | PMU_DCDC_ON); +#if PSRAM_HALF_SLEEP_SUPPORTED != FALSE + /* Put PSRAM device to sleep */ + sl_si91x_psram_sleep(); +#endif + } +#elif (defined SLI_SI91X_MCU_EXTERNAL_LDO_FOR_PSRAM) +#if PSRAM_HALF_SLEEP_SUPPORTED != FALSE + if (sleepType == SLEEP_WITH_RETENTION) { + /* Put PSRAM device to sleep */ + sl_si91x_psram_sleep(); + } else { + /* External LDO handle for PSRAM */ + EXTERNAL_LDO_HANDLE; + } +#endif +#endif +#endif + +#ifdef SLI_SI91X_ENABLE_OS + /* Save Stack pointer value and Control registers */ + RSI_Save_Context(); +#endif + /* Take backup before going to PowerSave */ + p2p_intr_status_bkp.tass_p2p_intr_mask_clr_bkp = TASS_P2P_INTR_MASK_CLR; + p2p_intr_status_bkp.m4ss_p2p_intr_set_reg_bkp = M4SS_P2P_INTR_SET_REG; + +#if ((defined SLI_SI91X_MCU_COMMON_FLASH_MODE) && (!(defined(RAM_COMPILATION)))) + /* Reset M4_USING_FLASH bit before going to sleep */ + M4SS_P2P_INTR_CLR_REG = M4_USING_FLASH; + /*Before M4 is going to deep sleep , set m4ss_ref_clk_mux_ctrl ,tass_ref_clk_mux_ctr, AON domain power supply controls form M4 to TA */ +#ifdef SLI_SI917B0 + MCUAON_CONTROL_REG4 |= (MCU_TASS_REF_CLK_SEL_MUX_CTRL); + MCUAON_CONTROL_REG4; +#else + NWPAON_MEM_HOST_ACCESS_CTRL_SET_1 = TASS_REF_CLK_MUX_CTRL; +#endif +#endif + /*Enter sleep with retention*/ + if (sleepType == SLEEP_WITH_RETENTION) { + /*If retention mode is enabled save the CPU context*/ + RSI_PS_SaveCpuContext(); + } else { + /*Clear RAM retentions*/ + RSI_PS_ClrRamRetention(M4ULP_RAM16K_RETENTION_MODE_EN | TA_RAM_RETENTION_MODE_EN | M4ULP_RAM_RETENTION_MODE_EN + | M4SS_RAM_RETENTION_MODE_EN); + /*do not save CPU context and go to deep sleep */ + __asm("WFI"); + } + +#ifdef SLI_SI91X_MCU_COMMON_FLASH_MODE + /* if flash is not initialised ,then raise a request to TA */ + if (!(in_ps2_state) && !(M4SS_P2P_INTR_SET_REG & M4_USING_FLASH)) { + //!check TA wokeup or not + if (!(P2P_STATUS_REG & TA_IS_ACTIVE)) { + //!wakeup TA + P2P_STATUS_REG |= M4_WAKEUP_TA; + + //!wait for TA active + while (!(P2P_STATUS_REG & TA_IS_ACTIVE)) + ; + } + //!Check for TA_USING flash bit + if (!(TASS_P2P_INTR_CLEAR_REG & TA_USING_FLASH)) { + //! Request TA to program flash + //! raise an interrupt to TA register + M4SS_P2P_INTR_SET_REG = PROGRAM_COMMON_FLASH; + + //!Wait for TA using flash bit + while (!(TASS_P2P_INTR_CLEAR_REG & TA_USING_FLASH)) + ; + } + M4SS_P2P_INTR_SET_REG = M4_USING_FLASH; + } +#endif + +#ifdef SLI_SI91X_MCU_ENABLE_PSRAM_FEATURE +#if PSRAM_HALF_SLEEP_SUPPORTED != FALSE + /* Exit PSRAM device from sleep */ + sl_si91x_psram_wakeup(); +#endif +#endif + +#ifdef SLI_SI91X_ENABLE_OS + /* Restore Stack pointer value and Control registers */ + RSI_Restore_Context(); +#endif + /*Restore the default value to the processor clock */ + if ((in_ps2_state)) { + ULPCLK->ULP_TA_CLK_GEN_REG_b.ULP_PROC_CLK_SEL = (unsigned int)(ulp_proc_clk & 0xF); + } + +#if ((defined SLI_SI91X_MCU_COMMON_FLASH_MODE) && (!(defined(RAM_COMPILATION)))) + /* Before TA is going to power save mode, set m4ss_ref_clk_mux_ctrl ,tass_ref_clk_mux_ctrl ,AON domain power supply controls form TA to M4 */ + RSI_Set_Cntrls_To_M4(); +#endif + +// READ_MBR_MAGIC_WORD_ON_WAKEUP +#ifdef SLI_SI91X_MCU_COMMON_FLASH_MODE + if (!(in_ps2_state)) { + //!Poll for flash magic word + while (MBR_MAGIC_WORD != 0x5A5A) { + sl_magic_word_value++; + } + } +#endif + +#ifndef SL_SI91X_NPSS_GPIO_BTN_HANDLER + //NPSS GPIO-2(Button) interrupt clr reg(GPIO_NPSS_INTERRUPT_CLEAR_REG) + (*(volatile uint32_t *)(0x12080000UL + 0x08)) = 0x08; + + //NPSS GPIO-2(Button) low-level interrupt enable(GPIO_NPSS_GPIO_CONFIG_REG) + (*(volatile uint32_t *)(0x12080000UL + 0x10)) = BIT(18); +#endif + /* After wake-up, Set the SCDC voltage to the actual value*/ + /* As this function is located in flash accessing this fucntion only after getting controls*/ + set_scdc(SL_SCDC_ACTIVE); + + /*Update the REG Access SPI division factor to increase the SPI read/write speed*/ + if (lf_clk_mode == HF_MHZ_RO) { + RSI_SetRegSpiDivision(0U); + } else { + RSI_SetRegSpiDivision(1U); + } + /*IPMU dummy read to make IPMU block out of RESET*/ + ipmuDummyRead = ULP_SPI_MEM_MAP(0x144); + // After Wakeup + if (!((in_ps2_state) && (MCU_FSM->MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE_b.ULPSS_BASED_WAKEUP_b))) { +#if (XTAL_CAP_MODE == POWER_TARN_CONDITIONAL_USE) + if (lf_clk_mode & BIT(4)) { + // disable the XTAL CAP mode + RSI_PS_NpssPeriPowerUp(SLPSS_PWRGATE_ULP_MCUTS); + /*configure the slope,nominal temperature and f2_nominal*/ + RSI_TS_Config(MCU_TEMP, 25); + /*disable the bjt based temp sensor*/ + RSI_TS_RoBjtEnable(MCU_TEMP, 0); + /*Enable the RO based temp sensor*/ + RSI_TS_Enable(MCU_TEMP, 1); + /*update the temperature periodically*/ + RSI_Periodic_TempUpdate(TIME_PERIOD, 1, 0); + /*read the temperature*/ + Temp = (int)RSI_TS_ReadTemp(MCU_TEMP); + if (Temp > 45) { + //SCDC0 + RSI_IPMU_ProgramConfigData(scdc_volt_sel1); + RSI_IPMU_ProgramConfigData(scdc_volt_trim_efuse); + //SCDC0_1 + RSI_IPMU_ProgramConfigData(scdc_volt_sel2); + } + } +#endif + +#if (XTAL_CAP_MODE == POWER_TARN_ALWAYS_USE) + // disable the XTAL CAP mode + //SCDC0 + RSI_IPMU_ProgramConfigData(scdc_volt_sel1); + RSI_IPMU_ProgramConfigData(scdc_volt_trim_efuse); + //SCDC0_1 + RSI_IPMU_ProgramConfigData(scdc_volt_sel2); +#endif + } + if (!(lf_clk_mode == HF_MHZ_RO)) { + /*Spare register write sequence*/ + ipmuDummyRead = ULP_SPI_MEM_MAP(0x1C1); + ULP_SPI_MEM_MAP(0x141) = ipmuDummyRead; + + ipmuDummyRead = ULP_SPI_MEM_MAP(0x1C0); + ULP_SPI_MEM_MAP(0x140) = ipmuDummyRead; + RSI_PS_LatchCntrlSet(LATCH_TOP_SPI); + } + if (in_ps2_state) { + /*Come out of LP mode */ + /* enabling the RETN_LDO HP MODE */ + RSI_IPMU_RetnLdoHpmode(); + } + if (sleepType == SLEEP_WITHOUT_RETENTION) { + /* Increasing the bias current of RETN_LDO */ + RSI_IPMU_PocbiasCurrent11(); + RSI_IPMU_RO32khz_TrimEfuse(); + /* enabling the RETN_LDO HP MODE */ + RSI_IPMU_RetnLdoHpmode(); + } + /*I2S-PLL Bypass*/ + *(volatile uint32_t *)(0x24041400 + 0x3C) |= BIT(0); + + if (enable_sdcss_based_wakeup) { + RSI_PS_ClrWkpSources(SDCSS_BASED_WAKEUP); + enable_sdcss_based_wakeup = 0; + } + if (enable_m4ulp_retention) { + RSI_PS_M4ssRamBanksPowerUp(m4ulp_ram_core_status); + RSI_PS_M4ssRamBanksPeriPowerUp(m4ulp_ram_peri_status); + enable_m4ulp_retention = 0; + } + if (disable_pads_ctrl) { + ULP_SPI_MEM_MAP(0x141) |= (BIT(11)); // ULP PADS PDO ON + disable_pads_ctrl = 0; + } + for (x = 0; x < 200; x++) { + __ASM("NOP"); + } + + /* powerup FPU domain*/ + RSI_PS_M4ssPeriPowerUp(M4SS_PWRGATE_ULP_M4_DEBUG_FPU); + + /*Initialize floating point unit */ + fpuInit(); + +#ifdef DEBUG_UART + /*Initialize UART after wake up*/ + DEBUGINIT(); +#endif + +#if defined(SLI_SI91X_MCU_ENABLE_RAM_BASED_EXECUTION) + //passing the ram vector address to VTOR register + SCB->VTOR = (uint32_t)ram_vector; +#endif + + /* Restore NPSS INTERRUPTS*/ + NPSS_INTR_MASK_CLR_REG = ~npssIntrState; + + /* Restore P2P register values from backup */ + TASS_P2P_INTR_MASK_CLR = ~p2p_intr_status_bkp.tass_p2p_intr_mask_clr_bkp; + M4SS_P2P_INTR_SET_REG = p2p_intr_status_bkp.m4ss_p2p_intr_set_reg_bkp; + + /* Restore the Interrupt Priority Register */ + for (var = 0; var < MAX_IPS; ++var) { + NVIC->IP[var] = nvic_ip_reg[var]; + } + /* Restore the System Handlers Priority Registers */ + for (var = 0; var < MAX_SHP; ++var) { + SCB->SHP[var] = scs_shp_reg[var]; + } + /* Restore the NVIC registers */ + for (var = 0; var < MAX_NVIC_REGS; ++var) { + NVIC->ISER[var] = nvic_enable[var]; + } + return RSI_OK; +} From 099e813ab9b3db32f8b35937a42f9db982e3874e Mon Sep 17 00:00:00 2001 From: Aksel Skauge Mellbye Date: Thu, 8 Aug 2024 12:52:08 +0200 Subject: [PATCH 04/62] wiseconnect: Add clock manager Origin: Silicon Labs WiSeConnect SDK License: MSLA URL: https://github.com/siliconlabs/wiseconnect commit: e97a0ed00ddda347a8a39e8276f470e1c5fea469 Purpose: Enable clock configuration Signed-off-by: Aksel Skauge Mellbye --- .../inc/sl_si91x_clock_manager.h | 97 ++++++++ .../src/sl_si91x_clock_manager.c | 219 ++++++++++++++++++ 2 files changed, 316 insertions(+) create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/drivers/service/clock_manager/inc/sl_si91x_clock_manager.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/drivers/service/clock_manager/src/sl_si91x_clock_manager.c diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/service/clock_manager/inc/sl_si91x_clock_manager.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/service/clock_manager/inc/sl_si91x_clock_manager.h new file mode 100644 index 000000000..c5ca4de31 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/service/clock_manager/inc/sl_si91x_clock_manager.h @@ -0,0 +1,97 @@ +/************************************************************************************ + * @file sl_si91x_clock_manager.h + * @brief Clock Manager Service API implementation + ************************************************************************************ + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ************************************************************************************ + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ************************************************************************************/ + +#ifndef SL_CLOCK_MANAGER_H +#define SL_CLOCK_MANAGER_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "sl_status.h" +#include "rsi_pll.h" + +/************************************************************************************ + * @addtogroup CLOCK-MANAGER Clock Manager + * @ingroup SI91X_SERVICE_APIS + * @{ + ************************************************************************************/ +// ----------------------------------------------------------------------------------- +// GLOBAL DEFINES / MACROS +// ----------------------------------------------------------------------------------- +#define PLL_REF_CLK_VAL_RC_32MHZ ((uint32_t)(32000000)) // PLL reference clock frequency value of RC_32MHZ_CLK +#define PLL_REF_CLK_VAL_XTAL ((uint32_t)(40000000)) // PLL reference clock frequency value of XTAL_CLK + +// ----------------------------------------------------------------------------------- +// DATA TYPES +// ----------------------------------------------------------------------------------- +typedef M4_SOC_CLK_SRC_SEL_T sl_si91x_m4_soc_clk_src_sel_t; +// ----------------------------------------------------------------------------------- +// GLOBAL FUNCTION PROTOTYPES +// ----------------------------------------------------------------------------------- +/** + * @fn sl_status_t sl_si91x_clock_manager_m4_set_core_clk(M4_SOC_CLK_SRC_SEL_T clk_source, + uint32_t pll_freq) + * @brief This API is used to configure the m4_soc clock + * @param[in] pCLK: Pointer to the pll register instance + * @param[in] clk_source: Enum values of different Core source clocks. See #M4_SOC_CLK_SRC_SEL_T and NOTE for more info + * @param[in] pll_freq: M4 Core Frequency value (in MHz) to set + * @param[in] div_factor: Division value for M4 Core clock + * @return returns zero \ref RSI_OK on success, corresponding error code on failure + * @note For using UlpRefClk clksource need to configure M4ssRefClk frequency. For that need to call \ref RSI_CLK_M4ssRefClkConfig Api first + * - For using SocPllCLK clksource need to configure SocPll frequency. For that need to call \ref RSI_CLK_SetSocPllFreq Api first + * - For using IntfPllCLK clksource need to configure IntfPll frequency. For that need to call \ref RSI_CLK_SetIntfPllFreq Api first + * - For using Sleep clksource need to configure Sleep Clock. For that need to call \ref RSI_CLK_SlpClkConfig Api first + */ +sl_status_t sl_si91x_clock_manager_m4_set_core_clk(M4_SOC_CLK_SRC_SEL_T clk_source, uint32_t pll_freq); + +/** + * @fn sl_status_t sl_si91x_clock_manager_set_pll_freq(PLL_TYPE_T pll_type, uint32_t pll_freq, uint32_t pll_ref_clk) + * @brief This API is used to set the selected PLL clock to desired frequency + * @param[in] pll_type: PLL type to configure + * @return returns zero \ref RSI_OK on success, corresponding error code on failure + */ +sl_status_t sl_si91x_clock_manager_set_pll_freq(PLL_TYPE_T pll_type, uint32_t pll_freq, uint32_t pll_ref_clk); + +/** + * @fn sl_si91x_m4_soc_clk_src_sel_t sl_si91x_clock_manager_m4_get_core_clk_src_freq(uint32_t *core_clock) + * @brief This API is used to read the currently active m4_soc clock source and frequency + * @param[in] core_clock: Pointer to fill core clock frequency + * @return returns the currently active core clock source of type sl_si91x_m4_soc_clk_src_sel_t + */ +sl_si91x_m4_soc_clk_src_sel_t sl_si91x_clock_manager_m4_get_core_clk_src_freq(uint32_t *core_clock); + +/// @} end group CLOCK-MANAGER ******************************************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* SL_CLOCK_MANAGER_H */ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/service/clock_manager/src/sl_si91x_clock_manager.c b/wiseconnect/components/device/silabs/si91x/mcu/drivers/service/clock_manager/src/sl_si91x_clock_manager.c new file mode 100644 index 000000000..b233c3531 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/service/clock_manager/src/sl_si91x_clock_manager.c @@ -0,0 +1,219 @@ +/************************************************************************************ + * @file sl_si91x_clock_manager.c + * @brief Clock Manager Service API implementation + ************************************************************************************ + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ************************************************************************************ + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ************************************************************************************/ + +#include "sl_si91x_clock_manager.h" +#include "rsi_rom_clks.h" + +/************************************************************************************ + ************************* DEFINES / MACROS *************************************** + ************************************************************************************/ +#define MANUAL_LOCK 1 // Manual lock enable +#define BYPASS_MANUAL_LOCK 1 // Bypass manual lock enable +#define SOC_PLL_MM_COUNT_LIMIT 0xA4 // Soc pll count limit +#define DIVISION_FACTOR 0 // Division factor +#define QSPI_ODD_DIV_ENABLE 0 // Odd division enable for QSPI clock +#define QSPI_SWALLO_ENABLE 0 // Swallo enable for QSPI clock +#define QSPI_DIVISION_FACTOR 0 // Division factor for QSPI clock +/************************************************************************************ + ************************* LOCAL VARIABLES **************************************** + ************************************************************************************/ + +/************************************************************************************ + ************************* LOCAL TYPE DEFINITIONS ********************************* + ************************************************************************************/ + +/************************************************************************************ + ************************* LOCAL FUNCTION PROTOTYPES ****************************** + ************************************************************************************/ +static sl_status_t convert_rsi_to_sl_error_code(rsi_error_t error); +/************************************************************************************ + ************************* GLOBAL FUNCTION DEFINITIONS **************************** + ************************************************************************************/ + +/** + * @fn sl_status_t sl_si91x_clock_manager_m4_set_core_clk(M4_SOC_CLK_SRC_SEL_T clk_source, + uint32_t pll_freq) + * @brief This API is used to configure the m4_soc clocks + * @param[in] clk_source: Enum values of different Core source clocks. See #M4_SOC_CLK_SRC_SEL_T and NOTE for more info + * @param[in] pll_freq: M4 Core Frequency value (in MHz) to set + * @return returns zero \ref RSI_OK on success, corresponding error code on failure + * @note For using UlpRefClk clksource need to configure M4ssRefClk frequency. For that need to call \ref RSI_CLK_M4ssRefClkConfig Api first + * - For using SocPllCLK clksource need to configure SocPll frequency. For that need to call \ref RSI_CLK_SetSocPllFreq Api first + * - For using IntfPllCLK clksource need to configure IntfPll frequency. For that need to call \ref RSI_CLK_SetIntfPllFreq Api first + * - For using Sleep clksource need to configure Sleep Clock. For that need to call \ref RSI_CLK_SlpClkConfig Api first + */ +sl_status_t sl_si91x_clock_manager_m4_set_core_clk(M4_SOC_CLK_SRC_SEL_T clk_source, uint32_t pll_freq) +{ + M4CLK_Type *pCLK = M4CLK; + uint32_t div_factor = DIVISION_FACTOR; + rsi_error_t error_status = RSI_OK; + sl_status_t status; + + // PLL reference clock set to XTAL_CLK by default + uint32_t pll_ref_clk = PLL_REF_CLK_VAL_XTAL; + + // Validating for correct Clock Source input + if (clk_source > M4_SLEEPCLK) { + status = SL_STATUS_INVALID_PARAMETER; + return status; + } + + // Changing M4SOC clock to M4_ULPREFCLK + error_status = RSI_CLK_M4SocClkConfig(pCLK, M4_ULPREFCLK, 0); + status = convert_rsi_to_sl_error_code(error_status); + if (status != SL_STATUS_OK) { + return status; + } + + if (clk_source == M4_INTFPLLCLK) { + // RSI API to set INTF PLL clock frequency + error_status = sl_si91x_clock_manager_set_pll_freq(INFT_PLL, pll_freq, pll_ref_clk); + } else if (clk_source == M4_SOCPLLCLK) { + // RSI API to set SOC PLL clock frequency + error_status = sl_si91x_clock_manager_set_pll_freq(SOC_PLL, pll_freq, pll_ref_clk); + } + + // The error status is converted to the SL error code + status = convert_rsi_to_sl_error_code(error_status); + if (status != SL_STATUS_OK) { + return status; + } + + // RSI API to set M4 SOC clock is called and the status is converted to the SL error code. + error_status = RSI_CLK_M4SocClkConfig(pCLK, clk_source, div_factor); + status = convert_rsi_to_sl_error_code(error_status); + if (status != SL_STATUS_OK) { + return status; + } + + return status; +} + +/** + * @fn sl_status_t sl_si91x_clock_manager_set_pll_freq(PLL_TYPE_T pll_type, uint32_t pll_freq, uint32_t pll_ref_clk) + * @brief This API is used to set the selected PLL clock to particular frequency + * @param[in] pll_type: PLL type to configure + * @return returns zero \ref RSI_OK on success, corresponding error code on failure + */ +sl_status_t sl_si91x_clock_manager_set_pll_freq(PLL_TYPE_T pll_type, uint32_t pll_freq, uint32_t pll_ref_clk) +{ + M4CLK_Type *pCLK = M4CLK; + rsi_error_t error_status = RSI_OK; + sl_status_t status; + + switch (pll_type) { + case SOC_PLL: + // Configure SOC-PLL lock settings before configuring SOC PLL clock + RSI_CLK_SocPllLockConfig(MANUAL_LOCK, BYPASS_MANUAL_LOCK, SOC_PLL_MM_COUNT_LIMIT); + + // RSI API to set SOC PLL clock frequency + error_status = RSI_CLK_SetSocPllFreq(pCLK, pll_freq, pll_ref_clk); + break; + + case INFT_PLL: + // RSI API to set INTF PLL clock frequency + error_status = RSI_CLK_SetIntfPllFreq(pCLK, pll_freq, pll_ref_clk); + break; + + case I2S_PLL: + // RSI API to set I2S PLL clock frequency + error_status = RSI_CLK_SetI2sPllFreq(pCLK, pll_freq, pll_ref_clk); + break; + + default: + break; + } + + status = convert_rsi_to_sl_error_code(error_status); + return status; +} + +/** + * @fn sl_si91x_m4_soc_clk_src_sel_t sl_si91x_clock_manager_m4_get_core_clk_src_freq(uint32_t *core_clock) + * @brief This API is used to read the currently active m4_soc clock source and frequency + * @param[in] core_clock: Pointer to fill core clock frequency + * @return returns the currently active core clock source of type sl_si91x_m4_soc_clk_src_sel_t + */ +sl_si91x_m4_soc_clk_src_sel_t sl_si91x_clock_manager_m4_get_core_clk_src_freq(uint32_t *core_clock) +{ + M4CLK_Type *pCLK = M4CLK; + sl_si91x_m4_soc_clk_src_sel_t clk_src; + + // return currently active core clock frequency via the pointer by reference + *core_clock = system_clocks.soc_clock; + + // read currently active core clock source + clk_src = pCLK->CLK_CONFIG_REG5_b.M4_SOC_CLK_SEL; + + return clk_src; +} +/******************************************************************************* + * To validate the RSI error code + * While calling the RSI APIs, it returns the RSI Error codes. + * This function converts the RSI error codes into SL error codes. + * It takes argument as RSI error type and returns the SL error type. + * It has a single switch statement which is mapped with the SL error code and + * after successful conversion it breaks the switch statement. + * If the error code is not listed, by default is SL_STATUS_FAIL. + ******************************************************************************/ +static sl_status_t convert_rsi_to_sl_error_code(rsi_error_t error) +{ + sl_status_t status; + switch (error) { + case RSI_OK: + status = SL_STATUS_OK; + break; + case INVALID_PARAMETERS: + status = SL_STATUS_INVALID_PARAMETER; + break; + case ERROR_INVALID_INPUT_FREQUENCY: + status = SL_STATUS_INVALID_PARAMETER; + break; + case ERROR_CLOCK_NOT_ENABLED: + status = SL_STATUS_NOT_INITIALIZED; + break; + case INVALID_SAMPLING_RATE: + status = SL_STATUS_INVALID_RANGE; + break; + case INVALID_SAMPLE_LENGTH: + status = SL_STATUS_INVALID_COUNT; + break; + case ERROR_ADC_INVALID_ARG: + status = SL_STATUS_INVALID_PARAMETER; + break; + case ERROR_PS_INVALID_STATE: + status = SL_STATUS_INVALID_PARAMETER; + break; + default: + status = SL_STATUS_FAIL; + break; + } + return status; +} From 4226c2cbe27484af626062c29ae30c38adf95bbd Mon Sep 17 00:00:00 2001 From: Aksel Skauge Mellbye Date: Fri, 23 Aug 2024 17:08:55 +0200 Subject: [PATCH 05/62] wiseconnect: Add gpio driver Origin: Silicon Labs WiSeConnect SDK License: Zlib URL: https://github.com/siliconlabs/wiseconnect commit: e97a0ed00ddda347a8a39e8276f470e1c5fea469 Purpose: Enable gpio driver Signed-off-by: Aksel Skauge Mellbye --- .../drivers/unified_api/inc/sl_driver_gpio.h | 811 +++++++ .../unified_api/inc/sl_si91x_driver_gpio.h | 1175 ++++++++++ .../unified_api/src/sl_si91x_driver_gpio.c | 2069 +++++++++++++++++ .../inc/sl_si91x_gpio.h | 1004 ++++++++ .../inc/sl_si91x_gpio_common.h | 406 ++++ .../inc/sl_si91x_peripheral_gpio.h | 811 +++++++ .../src/sl_si91x_peripheral_gpio.c | 1320 +++++++++++ 7 files changed, 7596 insertions(+) create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_driver_gpio.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_driver_gpio.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_driver_gpio.c create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/inc/sl_si91x_gpio.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/inc/sl_si91x_gpio_common.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/inc/sl_si91x_peripheral_gpio.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/src/sl_si91x_peripheral_gpio.c diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_driver_gpio.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_driver_gpio.h new file mode 100644 index 000000000..2c1eef94e --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_driver_gpio.h @@ -0,0 +1,811 @@ +/***************************************************************************/ /** + * @file sl_driver_gpio.h + * @brief sl driver gpio header file + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licenser of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be miss represented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * miss represented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_DRIVER_GPIO_H +#define SL_DRIVER_GPIO_H + +#if !defined(GPIO_PRESENT) +#include "sl_status.h" +#include "sl_si91x_peripheral_gpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************/ /** + * @addtogroup GPIO General-Purpose Input-Output + * @ingroup SI91X_PERIPHERAL_APIS + * @{ + * + ******************************************************************************/ +/******************************************************************************* + *************************** DEFINES / MACROS ******************************** + ******************************************************************************/ +#define GPIO_MAX_OUTPUT_VALUE 1 // GPIO output maximum value +#define MAX_GROUP_INT 2 // Maximum number of group interrupts +#define GPIO_PORT_MAX_VALUE 5 // Maximum number of GPIO ports +#define MAX_UULP_INT 5 // Maximum number of UULP interrupts +#define ULP_MAX_MODE 10 // Maximum ULP mode + +#define GPIO_MAX_INTR_VALUE 8 // Maximum number of M4 GPIO pin interrupts +#define PORTD_PIN_MAX_VALUE 9 // Port D maximum(0-9) number of GPIO pins +#define ULP_PIN_MAX_VALUE 11 // Port E maximum(0-11) number of GPIO pins +#define UULP_PIN_MAX_VALUE 5 // Port F maximum(0-4) number of GPIO pins +#define MAX_ULP_INTR 8 // Maximum number of ULP interrupts +#define MAX_MODE 15 // Maximum M4 GPIO mode +#define PORTA_PIN_MAX_VALUE 57 // GPIO pin maximum(0-63) value for SL_GPIO_PORT_A of HP instance +#define PORT_PIN_MAX_VALUE 15 // GPIO pin maximum(0-15) value for SL_GPIO_PORT_B, SL_GPIO_PORT_C of HP instance +#define GPIO_FLAGS_MAX_VALUE 0x0F // GPIO flags maximum value + +#define PAD_SELECT_9 9 // GPIO PAD selection number +#define UULP_PORT 5 // Refers to port for UULP instance +#define GPIO_MAX_PORT_PINS 0xFFFF // Refers to maximum no. of pins port can support + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ +///@brief structure to hold parameters of GPIO port and pin numbers. +typedef struct { + sl_gpio_port_t port; + uint8_t pin; +} sl_gpio_t; + +typedef struct { + sl_gpio_t port_pin; + sl_si91x_gpio_direction_t direction; +} sl_si91x_gpio_pin_config_t; + +/******************************************************************************* + ******************************** Local Variables ************************** + ******************************************************************************/ +///@brief GPIO interrupt callback function pointer. +typedef void (*sl_gpio_irq_callback_t)(uint32_t flag); + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +/*******************************************************************************/ /** + * @brief Clear one or more pending GPIO interrupts. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_pad_selection(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_pad_receiver(), for HP instance + * - \ref sl_gpio_driver_set_pin_mode() + * - \ref sl_si91x_gpio_driver_set_pin_direction() + * + * @param[in] flags - Bitwise logic OR of GPIO interrupt sources to clear. + * @return returns status 0 + * - \ref SL_STATUS_OK (0X000) - Success + * + ******************************************************************************/ +STATIC __INLINE sl_status_t sl_gpio_driver_clear_interrupts(uint32_t flags) +{ + sl_gpio_clear_interrupts(flags); + return SL_STATUS_OK; +} + +/***************************************************************************/ /** + * @brief Configure the GPIO pin interrupt. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_set_configuration() + * - \ref sl_si91x_gpio_driver_set_pin_direction() + * @param[in] gpio - Pointer to the structure of type \ref sl_gpio_t + * @param[in] int_no - Specifies the interrupt number to trigger (0 to 7). + * @param[in] flags - Interrupt configuration flags \ref sl_gpio_interrupt_flag_t + * @param[in] gpio_callback - IRQ callback function pointer \ref sl_gpio_irq_callback_t + * @param[out] avl_intr_no - Pointer to the available interrupt number. + SL_GPIO_INTERRUPT_UNAVAILABLE (0xFF) no available interrupt + * @return The following values are returned: + * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument + * - \ref SL_STATUS_NULL_POINTER (0x0022) - The parameter is a null pointer + * - \ref SL_STATUS_OK (0X000) - Success + * - \ref SL_STATUS_BUSY (0x0004) - Interrupt is busy and cannot carry out the requested operation + ******************************************************************************/ +sl_status_t sl_gpio_driver_configure_interrupt(sl_gpio_t *gpio, + uint32_t int_no, + sl_gpio_interrupt_flag_t flags, + sl_gpio_irq_callback_t gpio_callback, + uint32_t *avl_intr_no); + +/***************************************************************************/ /** + * @brief Configure the GPIO group interrupts for HP,ULP instances. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_set_configuration() + * - \ref sl_si91x_gpio_driver_set_pin_direction() + * @param[in] configuration - Pointer to the structure of type \ref sl_si91x_gpio_group_interrupt_config_t + * @param[in] gpio_callback - IRQ callback function pointer \ref sl_gpio_irq_callback_t + * @return The following values are returned: + * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument + * - \ref SL_STATUS_NULL_POINTER (0x0022) - The parameter is a null pointer + * - \ref SL_STATUS_OK (0X000) - Success + * - \ref SL_STATUS_BUSY (0x0004) - Interrupt is busy and cannot carry out the requested operation + ******************************************************************************/ +sl_status_t sl_gpio_configure_group_interrupt(sl_si91x_gpio_group_interrupt_config_t *configuration, + sl_gpio_irq_callback_t gpio_callback); + +/***************************************************************************/ /** + * @brief Set the pin mode for a GPIO pin in HP (or) ULP instance. + * @details By default mode-0 is set and GPIO pin acts as normal GPIO. + * If a GPIO pin to be used for some alternate modes, the respective mode is to be + * selected. For more information about modes present for different + * instances, please refer PIN MUX section in HRM. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_clock, for HP instance + * - \ref sl_si91x_gpio_driver_enable_pad_receiver(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver(), for ULP instance + * Use the corresponding pad receiver API for corresponding GPIO instance. + * @param[in] gpio - Pointer to the structure of type \ref sl_gpio_t. + * Please refer to below table for description of each port and pins available. + * | GPIO Instance | GPIO Port | GPIO Pin Number | + * |---------------------------------------------|-----------------------|-------------------| + * | | SL_GPIO_PORT_A | (0-15) | + * | HP (High Power) GPIO Instance | SL_GPIO_PORT_B | (16-31) | + * | | SL_GPIO_PORT_C | (32-47) | + * | | SL_GPIO_PORT_D | (48-57) | + * |---------------------------------------------|-----------------------|-------------------| + * | ULP (Ultra Low Power) GPIO Instance | SL_GPIO_ULP_PORT | (0-11) | + * |---------------------------------------------|-----------------------|-------------------| + * | UULP (Ultra Ultra Low Power) GPIO Instance | SL_GPIO_UULP_PORT | (0-4) | + * |---------------------------------------------|-----------------------|-------------------| + * PORT_A can also be a single port to access all GPIO (0-57) pins available in HP domain, instead + * of using PORT B,C,D. (57-63)pins are reserved. + * @param[in] mode - The desired pin mode. + * @param[in] output_value - A value to set for the pin in the GPIO register. + * The GPIO setting is important for some input mode configurations. + * @return The following values are returned: + * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument + * - \ref SL_STATUS_NULL_POINTER (0x0022) - The parameter is a null pointer + * - \ref SL_STATUS_OK (0X000) - Success + ******************************************************************************/ +sl_status_t sl_gpio_driver_set_pin_mode(sl_gpio_t *gpio, sl_gpio_mode_t mode, uint32_t output_value); + +/***************************************************************************/ /** + * @brief Get the pin mode (alternate function) of a GPIO for either HP instance (or) ULP instance as per the port number. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_clock, for HP instance + * - \ref sl_si91x_gpio_driver_enable_pad_receiver(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver(), for ULP instance + * Use the corresponding pad receiver API for the corresponding GPIO instance. + * \ref sl_gpio_driver_set_pin_mode(); + * @param[in] gpio - Pointer to the structure of type \ref sl_gpio_t + * @param[out] mode - The desired pin mode. + * @return The following values are returned: + * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is invalid argument + * - \ref SL_STATUS_NULL_POINTER (0x0022) - The parameter is null pointer + * - \ref SL_STATUS_OK (0X000) - Success + * + ******************************************************************************/ +sl_status_t sl_gpio_driver_get_pin_mode(sl_gpio_t *gpio, sl_gpio_mode_t *mode); + +/******************************************************************************* + * @brief Initializes the GPIO driver by clearing all the interrupts (HP, ULP, and NPSS instance) and callback function pointers with NULL. + * @param none + * @return returns status 0, + * - \ref SL_STATUS_OK (0X000) - Success + * + ******************************************************************************/ +sl_status_t sl_gpio_driver_init(void); + +/******************************************************************************* + * @brief De-Initializes the GPIO driver by disabling clocks (HP and ULP instance) and callback function pointers. + * @param none + * @return returns status 0, + * - \ref SL_STATUS_OK (0X000) - Success + * + ******************************************************************************/ +sl_status_t sl_gpio_driver_deinit(void); + +/*******************************************************************************/ /** + * @brief Unregister GPIO driver. + * @param[in] gpio_instance - Instances of type \ref sl_si91x_gpio_instances_t + * @param[in] gpio_intr - GPIO interrupts of type \ref sl_si91x_gpio_intr_t + * @param[in] flag - GPIO interrupt flag Max range is 8. + * @return The following values are returned: + * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument + * - \ref SL_STATUS_OK (0X000) - Success + * + ******************************************************************************/ +sl_status_t sl_gpio_driver_unregister(sl_si91x_gpio_instances_t gpio_instance, + sl_si91x_gpio_intr_t gpio_intr, + uint8_t flag); + +/*******************************************************************************/ /** + * @brief Validating port and pin of GPIO. + * @param[in] gpio - Pointer to the structure of type \ref sl_gpio_t + * @return The following values are returned: + * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument + * - \ref SL_STATUS_OK (0X000) - Success + * + ******************************************************************************/ +STATIC __INLINE sl_status_t sl_gpio_validation(sl_gpio_t *gpio) +{ + // Check if gpio port value exceeds maximum allowed value. Return error code for invalid parameter + if (gpio->port > GPIO_PORT_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + // Checks if the port is Port A. If true, checks if the pin value exceeds + // the maximum allowable value for Port A. Returns an invalid parameter status code if true + if (gpio->port == SL_GPIO_PORT_A) { + if (gpio->pin > PORTA_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Checks if the port is either Port B or Port C. If true, checks if the pin value exceeds + // the maximum allowable value for these ports. Returns an invalid parameter status code if true. + if ((gpio->port == SL_GPIO_PORT_B) || (gpio->port == SL_GPIO_PORT_C)) { + if (gpio->pin > PORT_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Checks if the port is Port D. If true, checks if the pin value exceeds the maximum allowable + // value for Port D. Returns an invalid parameter status code if true. + if (gpio->port == SL_GPIO_PORT_D) { + if (gpio->pin > PORTD_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Check if the GPIO port is the Ultra-Low Power GPIO port. + if (gpio->port == SL_GPIO_ULP_PORT) { + // Check if the GPIO pin exceeds the maximum allowed values. + if (gpio->pin > ULP_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Check if the GPIO port is the Ultra-Ultra Low Power GPIO port. + if (gpio->port == SL_GPIO_UULP_PORT) { + // Check if the GPIO pin exceeds the maximum allowed values. + if (gpio->pin > UULP_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + return SL_STATUS_OK; +} + +/***************************************************************************/ /** + * @brief Set a single pin in GPIO configuration register to 1. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_pad_selection(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_pad_receiver(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver(), for ULP instance + * Use the corresponding pad receiver API for corresponding GPIO instance. + * - \ref sl_gpio_driver_set_pin_mode(); + * - \ref sl_si91x_gpio_driver_set_pin_direction(); + * + * @param[in] gpio - Pointer to the structure of type \ref sl_gpio_t + * @return The following values are returned: + * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument + * - \ref SL_STATUS_NULL_POINTER (0x0022) - The parameter is a null pointer + * - \ref SL_STATUS_OK (0X000) - Success + * + ******************************************************************************/ +STATIC __INLINE sl_status_t sl_gpio_driver_set_pin(sl_gpio_t *gpio) +{ + sl_status_t status; + // Check if gpio pointer is NULL + if (gpio == NULL) { + return SL_STATUS_NULL_POINTER; + } + status = sl_gpio_validation(gpio); + if (status != SL_STATUS_OK) { + return status; + } + // Set GPIO pin output + sl_gpio_set_pin_output(gpio->port, gpio->pin); + return SL_STATUS_OK; +} + +/***************************************************************************/ /** + * @brief Clear a single pin in the GPIO configuration register to 0. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_pad_selection(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_pad_receiver(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver(); for ULP instance + * Use the corresponding pad receiver API for the corresponding GPIO instance. + * - \ref sl_gpio_driver_set_pin_mode(); + * - \ref sl_si91x_gpio_driver_set_pin_direction(); + * + * @param[in] gpio - Pointer to the structure of type \ref sl_gpio_t + * @return returns status 0 if successful, + * else error code as follow. + * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument + * - \ref SL_STATUS_NULL_POINTER (0x0022) - The parameter is a null pointer + * - \ref SL_STATUS_OK (0X000) - Success + * + ******************************************************************************/ +STATIC __INLINE sl_status_t sl_gpio_driver_clear_pin(sl_gpio_t *gpio) +{ + sl_status_t status; + // Check if gpio pointer is NULL. Return error code for NULL pointer + if (gpio == NULL) { + return SL_STATUS_NULL_POINTER; + } + status = sl_gpio_validation(gpio); + if (status != SL_STATUS_OK) { + return status; + } + // Clear GPIO pin output + sl_gpio_clear_pin_output(gpio->port, gpio->pin); + return SL_STATUS_OK; +} + +/***************************************************************************/ /** + * @brief Toggle a single pin in GPIO port register. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_pad_selection(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_pad_receiver(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver(), for ULP instance + * Use the corresponding pad receiver API for the corresponding GPIO instance. + * - \ref sl_gpio_driver_set_pin_mode() + * - \ref sl_si91x_gpio_driver_set_pin_direction() + * + * @param[in] gpio - Pointer to the structure of type \ref sl_gpio_t + * @return returns status 0 if successful, + * else error code as follow. + * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument + * - \ref SL_STATUS_NULL_POINTER (0x0022) - The parameter is a null pointer + * - \ref SL_STATUS_OK (0X000) - Success + * + ******************************************************************************/ +STATIC __INLINE sl_status_t sl_gpio_driver_toggle_pin(sl_gpio_t *gpio) +{ + sl_status_t status; + // Check if gpio pointer is NULL. Return error code for NULL pointer + if (gpio == NULL) { + return SL_STATUS_NULL_POINTER; + } + status = sl_gpio_validation(gpio); + if (status != SL_STATUS_OK) { + return status; + } + // Toggles GPIO pin + sl_gpio_toggle_pin_output(gpio->port, gpio->pin); + return SL_STATUS_OK; +} + +/***************************************************************************/ /** + * @brief Read the pin value for a single pin in a GPIO port. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_pad_selection(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_pad_receiver(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver(), for ULP instance + * Use the corresponding pad receiver API for the corresponding GPIO instance. + * - \ref sl_gpio_driver_set_pin_mode() + * - \ref sl_si91x_gpio_driver_set_pin_direction() + * + * @param[in] gpio - Pointer to the structure of type \ref sl_gpio_t + * @param[out] pin_value - Gets the gpio pin value + * @return returns status 0 if successful, + * else error code as follow. + * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument + * - \ref SL_STATUS_NULL_POINTER (0x0022) - The parameter is a null pointer + * - \ref SL_STATUS_OK (0X000) - Success + * + ******************************************************************************/ +STATIC __INLINE sl_status_t sl_gpio_driver_get_pin(sl_gpio_t *gpio, uint8_t *pin_value) +{ + sl_status_t status; + // Check if gpio pointer is NULL. Return error code for NULL pointer + if (gpio == NULL) { + return SL_STATUS_NULL_POINTER; + } + status = sl_gpio_validation(gpio); + if (status != SL_STATUS_OK) { + return status; + } + // Get GPIO pin input + *pin_value = sl_gpio_get_pin_input(gpio->port, gpio->pin); + return SL_STATUS_OK; +} + +/***************************************************************************/ /** + * @brief Set bits GPIO data out register to 1. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_pad_selection(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_pad_receiver(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver(), for ULP instance + * Use the corresponding pad receiver API for the corresponding GPIO instance. + * - \ref sl_gpio_driver_set_pin_mode(); + * - \ref sl_si91x_gpio_driver_set_pin_direction(); + * + * @param[in] port - The port to associate with the pin. + * HP instance - PORT 0,1,2,3 + * ULP instance - PORT 4 + * @param[in] pins - The GPIO pins in a Port that are set to 1 (1 to 65535 in decimal (or) 0xFFFF in hex). + * If we want to set pins(maximum of (0-15)pins) in a port, it can set all pins at a time. + * @return returns status 0 if successful, + * else error code as follow. + * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument + * - \ref SL_STATUS_OK (0X000) - Success + * + ******************************************************************************/ +STATIC __INLINE sl_status_t sl_gpio_driver_set_port(sl_gpio_port_t port, uint32_t pins) +{ + // Check if gpio port value exceeds maximum allowed value. Return error code for invalid parameter + if ((port > GPIO_PORT_MAX_VALUE) || (pins > GPIO_MAX_PORT_PINS)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Set GPIO port output + sl_gpio_set_port_output(port, pins); + return SL_STATUS_OK; +} + +/***************************************************************************/ /** + * @brief Set bits in configuration register for a port to 0. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_pad_selection(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_pad_receiver(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver(), for ULP instance + * Use the corresponding pad receiver API for the corresponding GPIO instance. + * - \ref sl_gpio_driver_set_pin_mode() + * - \ref sl_si91x_gpio_driver_set_pin_direction() + * + * @param[in] port - The port to associate with the pin. + * HP instance - PORT A,B,C,D + * ULP instance - PORT 4 + * @param[in] pins - The GPIO pins in a Port that are set to 0 (1 to 65535 in decimal (or) 0xFFFF in hex). + * If we want to clear pins(maximum of (0-15)pins) in a port, it can clear all pins at a time. + * @return returns status 0 if successful, + * else error code as follow. + * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument + * - \ref SL_STATUS_OK (0X000) - Success + * + ******************************************************************************/ +STATIC __INLINE sl_status_t sl_gpio_driver_clear_port(sl_gpio_port_t port, uint32_t pins) +{ + // Check if gpio port value exceeds maximum allowed value. Return error code for invalid parameter + if ((port > GPIO_PORT_MAX_VALUE) || (pins > GPIO_MAX_PORT_PINS)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Clear GPIO port output + sl_gpio_clear_port_output(port, pins); + return SL_STATUS_OK; +} + +/***************************************************************************/ /** + * @brief Get the current setting for a GPIO configuration register. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_pad_selection(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_pad_receiver(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver(), for ULP instance + * Use the corresponding pad receiver API for the corresponding GPIO instance. + * - \ref sl_gpio_driver_set_pin_mode() + * - \ref sl_si91x_gpio_driver_set_pin_direction() + * + * @param[in] port - The port to associate with the pin. + * HP instance - PORT A,B,C,D + * ULP instance - PORT 4 + * @param[out] port_value - Gets the gpio port value + * @return returns status 0 if successful, + * else error code as follow. + * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument + * - \ref SL_STATUS_OK (0X000) - Success + * + ******************************************************************************/ +STATIC __INLINE sl_status_t sl_gpio_driver_get_port_output(sl_gpio_port_t port, uint32_t *port_value) +{ + // Check if gpio port value exceeds maximum allowed value. Return error code for invalid parameter + if (port > GPIO_PORT_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + // Get GPIO port output + *port_value = sl_gpio_get_port_output(port); + return SL_STATUS_OK; +} + +/***************************************************************************/ /** + * @brief Get the current setting for a pin in a GPIO configuration register. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_pad_selection(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_pad_receiver(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver(), for ULP instance + * Use the corresponding pad receiver API for the corresponding GPIO instance. + * - \ref sl_gpio_driver_set_pin_mode() + * - \ref sl_si91x_gpio_driver_set_pin_direction() + * + * @param[in] gpio - Pointer to the structure of type \ref sl_gpio_t + * @return The GPIO pin value + * '0' - Low\n + * '1' - High\n + ******************************************************************************/ +STATIC __INLINE uint8_t sl_gpio_driver_get_pin_output(sl_gpio_t *gpio) +{ + sl_status_t status; + uint8_t pin_output = 0; + // Check if gpio pointer is NULL. Return error code for NULL pointer + if (gpio == NULL) { + return SL_STATUS_NULL_POINTER; + } + status = sl_gpio_validation(gpio); + if (status != SL_STATUS_OK) { + return status; + } + // Get GPIO pin output + pin_output = sl_gpio_get_pin_output(gpio->port, gpio->pin); + return pin_output; +} + +/*******************************************************************************/ /** + * @brief Set the GPIO port configuration register. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_pad_selection(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_pad_receiver(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver(), for ULP instance + * - + * Use the corresponding pad receiver API for the corresponding GPIO instance. + * - \ref sl_gpio_driver_set_pin_mode(); + * - \ref sl_si91x_gpio_driver_set_pin_direction(); + * + * @param[in] port - The port to associate with the pin. + * HP instance - PORT A,B,C,D + * ULP instance - PORT 4 + * @param[in] val - Value to write to the port configuration register. + * @param[in] mask - Mask indicating which bits to modify. + * @return returns status 0 if successful, + * else error code as follow. + * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument + * - \ref SL_STATUS_OK (0X000) - Success + * + ******************************************************************************/ +STATIC __INLINE sl_status_t sl_gpio_driver_set_port_output_value(sl_gpio_port_t port, uint32_t val, uint32_t mask) +{ + // Check if gpio port value exceeds maximum allowed value. Return error code for invalid parameter + if (port > GPIO_PORT_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + // Set GPIO port output value + sl_gpio_set_port_output_value(port, val, mask); + return SL_STATUS_OK; +} + +/******************************************************************************* + * @brief Set slewrate for pins on an HP instance GPIO port. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_pad_selection(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_pad_receiver(), for HP instance + * + * @param[in] port - The GPIO port to configure. + * @param[in] slewrate - The slewrate to configure for the pins on this GPIO port. + * @param[in] slewrate_alt - The slewrate to configure for the pins using alternate modes on this GPIO port. + * @return returns status 0 if successful, + * else error code as follow. + * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument + * - \ref SL_STATUS_OK (0X000) - Success + * + ******************************************************************************/ +STATIC __INLINE sl_status_t sl_gpio_driver_set_slew_rate(sl_gpio_port_t port, uint32_t slewrate, uint32_t slewrate_alt) +{ + // Check if gpio port value exceeds maximum allowed value. Return error code for invalid parameter + if (port > GPIO_PORT_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + // Set GPIO slew rate + sl_gpio_set_slew_rate(port, slewrate, slewrate_alt); + return SL_STATUS_OK; +} + +/*******************************************************************************/ /** + * @brief Read the port value for GPIO. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_pad_selection(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_pad_receiver(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver(), for ULP instance + * - + * Use the corresponding pad receiver API for the corresponding GPIO instance. + * - \ref sl_gpio_driver_set_pin_mode() + * - \ref sl_si91x_gpio_driver_set_pin_direction() + * + * @param[in] port - The port to associate with the pin. + * HP instance - PORT A,B,C,D + * ULP instance - PORT 4 + * @return The GPIO pin value + * '0' - Low\n + * '1' - High\n + ******************************************************************************/ +STATIC __INLINE uint32_t sl_gpio_driver_get_port_input(sl_gpio_port_t port) +{ + uint32_t port_input = 0; + // Check if gpio port value exceeds maximum allowed value. Return error code for invalid parameter + if (port > GPIO_PORT_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + // Get GPIO port input + port_input = sl_gpio_get_port_input(port); + return port_input; +} + +/******************************************************************************* + * @brief Toggle the selected pin values in the GPIO port register. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_pad_selection(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_pad_receiver(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver(), for ULP instance + * Use the corresponding pad receiver API for the corresponding GPIO instance. + * - \ref sl_gpio_driver_set_pin_mode() + * - \ref sl_si91x_gpio_driver_set_pin_direction() + * + * @param[in] port - The port to associate with the pin. + * HP instance - PORT A,B,C,D + * ULP instance - PORT 4 + * @param[in] pins - Port pins to toggle. Ranges from (1 to 65535 in decimal (or) 0xFFFF in hex). + * @return returns status 0 if successful, + * else error code as follow. + * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument + * - \ref SL_STATUS_OK (0X000) - Success + * + ******************************************************************************/ +STATIC __INLINE sl_status_t sl_gpio_driver_toggle_port_output(sl_gpio_port_t port, uint32_t pins) +{ + // Check if gpio port value exceeds maximum allowed value. Return error code for invalid parameter + if ((port > GPIO_PORT_MAX_VALUE) || (pins > GPIO_MAX_PORT_PINS)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Toggle GPIO port output + sl_gpio_toggle_port_output(port, pins); + return SL_STATUS_OK; +} + +/******************************************************************************* + * @brief Enable the selected GPIO pin interrupt with the configured interrupt type (Level or Edge). + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_pad_selection(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_pad_receiver(), for HP instance + * - \ref sl_gpio_driver_set_pin_mode() + * - \ref sl_si91x_gpio_driver_set_pin_direction() + * + * @param[in] flags - GPIO interrupt sources to enable. + * @return returns status 0 + * - \ref SL_STATUS_OK (0X000) - Success + * + ******************************************************************************/ +STATIC __INLINE sl_status_t sl_gpio_driver_enable_interrupts(uint32_t flags) +{ + sl_gpio_enable_interrupts(flags); + return SL_STATUS_OK; +} + +/******************************************************************************* + * @brief Disable the selected GPIO pin interrupt with the configured interrupt type (Level or Edge). + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_pad_selection(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_pad_receiver(), for HP instance + * - \ref sl_gpio_driver_set_pin_mode() + * - \ref sl_si91x_gpio_driver_set_pin_direction() + * + * @param[in] flags - GPIO interrupt sources to disable. + * @return returns status 0 + * - \ref SL_STATUS_OK (0X000) - Success + * + ******************************************************************************/ +STATIC __INLINE sl_status_t sl_gpio_driver_disable_interrupts(uint32_t flags) +{ + sl_gpio_disable_interrupts(flags); + return SL_STATUS_OK; +} + +/******************************************************************************* + * @brief Set the selected GPIO pin interrupt with the configured interrupt type (Level or Edge). + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_pad_selection(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_pad_receiver(), for HP instance + * - \ref sl_gpio_driver_set_pin_mode() + * - \ref sl_si91x_gpio_driver_set_pin_direction() + * + * @param[in] flags - GPIO interrupt sources to set to pending. + * @return returns status 0 + * - \ref SL_STATUS_OK (0X000) - Success + * + ******************************************************************************/ +STATIC __INLINE sl_status_t sl_gpio_driver_set_interrupts(uint32_t flags) +{ + sl_gpio_set_interrupts(flags); + return SL_STATUS_OK; +} + +/*******************************************************************************/ /** + * @brief Get the pending GPIO interrupts. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_pad_selection(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_pad_receiver(), for HP instance + * - \ref sl_gpio_driver_set_pin_mode() + * - \ref sl_si91x_gpio_driver_set_pin_direction() + * + * @param none + * @return Pending GPIO Pin interrupt numbers. + ******************************************************************************/ +STATIC __INLINE uint32_t sl_gpio_driver_get_pending_interrupts(void) +{ + uint32_t status; + status = sl_gpio_get_pending_interrupts(); + return status; +} + +/*******************************************************************************/ /** + * @brief Get the enabled GPIO interrupts. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_pad_selection(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_pad_receiver(), for HP instance + * - \ref sl_gpio_driver_set_pin_mode() + * - \ref sl_si91x_gpio_driver_set_pin_direction() + * + * @param none + * @return Enabled GPIO pin interrupt numbers. + ******************************************************************************/ +STATIC __INLINE uint32_t sl_gpio_driver_get_enabled_interrupts(void) +{ + uint32_t status; + status = sl_gpio_get_enabled_interrupts(); + return status; +} + +/*******************************************************************************/ /** + * @brief Get the enabled and pending GPIO interrupt flags. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_pad_selection(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_pad_receiver(), for HP instance + * - \ref sl_gpio_driver_set_pin_mode() + * - \ref sl_si91x_gpio_driver_set_pin_direction() + * @param none + * @return Enabled GPIO pending interrupts. + ******************************************************************************/ +STATIC __INLINE uint32_t sl_gpio_driver_get_enabled_pending_interrupts(void) +{ + uint32_t status; + status = sl_gpio_get_enabled_pending_interrupts(); + return status; +} + +/** @} (end addtogroup GPIO) */ + +#ifdef __cplusplus +} +#endif + +#endif ///< GPIO_PRESENT +#endif ///< SL_DRIVER_GPIO_H diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_driver_gpio.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_driver_gpio.h new file mode 100644 index 000000000..0459819db --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_driver_gpio.h @@ -0,0 +1,1175 @@ +/***************************************************************************/ /** + * @file sl_si91x_driver_gpio.h + * @brief sl si91x driver gpio header file + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licenser of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be miss represented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * miss represented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_SI91X_DRIVER_GPIO_H +#define SL_SI91X_DRIVER_GPIO_H + +#if !defined(GPIO_PRESENT) +#include "sl_status.h" +#include "sl_driver_gpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************/ /** + * @addtogroup GPIO General-Purpose Input-Output + * @ingroup SI91X_PERIPHERAL_APIS + * @{ + * + ******************************************************************************/ +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +/***************************************************************************/ /** + * @brief Configuration of the GPIO based on port and pin. + * @details Port A,B,C,D are considered for HP instance, ULP PORT is considered for ULP instance + * UULP PORT is considered for UULP instance. The configuration of GPIO pin like + * which GPIO pin and port are to be passed through the structure. By default mode is taken + * as mode0, which is normal GPIO selection. + * @param[in] pin_config - Structure containing the configuration information. + * @return None + *******************************************************************************/ +sl_status_t sl_gpio_set_configuration(sl_si91x_gpio_pin_config_t pin_config); + +/***************************************************************************/ /** + * @brief Set the direction for a GPIO pin. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_pad_selection(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_pad_receiver(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver(), for ULP instance + * Use corresponding pad receiver API for corresponding GPIO instance. + * @param[in] port - The port to associate with the pin. + * HP instance - PORT A,B,C,D + * ULP instance - ULP PORT + * @param[in] pin - The pin number on the port. + * HP instance has total 57 GPIO pins. Port A, B, C has 16 pins each. + * Port D has 9 pins. + * ULP instance has total 12 pins. + * @param[in] direction - pin direction of type \ref sl_si91x_gpio_direction_t + * - '0' - Output + * - '1' - Input + * + * @return returns status 0 if successful, + * else error code as follow. + * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument + * - \ref SL_STATUS _OK (0X000) - Success + * + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_set_pin_direction(uint8_t port, uint8_t pin, sl_si91x_gpio_direction_t direction); + +/***************************************************************************/ /** + * @brief Get the direction of a selected GPIO pin. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_pad_selection(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_pad_receiver(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver(), for ULP instance + * Use corresponding pad receiver API for corresponding GPIO instance. + * - \ref sl_si91x_gpio_driver_set_pin_direction() + * - \ref sl_si91x_gpio_driver_get_pin_direction() + * + * @param[in] port - The port to associate with the pin. + * HP instance - PORT A,B,C,D + * ULP instance - ULP PORT + * @param[in] pin - The pin number on the port. + * HP instance has total 57 GPIO pins. Port A, B, C has 16 pins each. + * Port D has 9 pins. + * ULP instance has total 12 pins. + * @return Returns the direction of the pin. + * - '0' - Output + * - '1' - Input + * + ******************************************************************************/ +uint8_t sl_si91x_gpio_driver_get_pin_direction(uint8_t port, uint8_t pin); + +/***************************************************************************/ /** + * @brief Enable the receiver enable bit in the PAD configuration register for reading the GPIO pin status. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_pad_selection(), for HP instance + * + * @param[in] gpio_num - GPIO pin number to be use. + * @return returns status 0 if successful, + * else error code as follow. + * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument + * - \ref SL_STATUS _OK (0X000) - Success + * + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_enable_pad_receiver(uint8_t gpio_num); + +/***************************************************************************/ /** + * @brief Disable the receiver enable bit in the PAD configuration register. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_pad_selection(), for HP instance + * + * @param[in] gpio_num - GPIO pin number to be use. + * @return returns status 0 if successful, + * else error code as follow. + * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument + * - \ref SL_STATUS _OK (0X000) - Success + * + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_disable_pad_receiver(uint8_t gpio_num); + +/***************************************************************************/ /** + * @brief Enable the pad selection bit in the PAD selection register. + * @pre Pre-condition: + * - \ref sl_si91x_gpio_driver_enable_clock() + * @param[in] gpio_padnum - PAD number to be use + * @return returns status 0 if successful, + * else error code as follow. + * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument + * - \ref SL_STATUS _OK (0X000) - Success + * + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_enable_pad_selection(uint8_t gpio_padnum); + +/***************************************************************************/ /** + * @brief Enable the host pad selection bit in the PAD selection register. + * @pre Pre-condition: + * - \ref sl_si91x_gpio_driver_enable_clock() + * @param[in] gpio_num - GPIO pin number to be used + * @return returns status 0 if successful, + * else error code as follow. + * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument + * - \ref SL_STATUS _OK (0X000) - Success + * + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_enable_host_pad_selection(uint8_t gpio_num); + +/***************************************************************************/ /** + * @brief Select the drive strength for an HP instance GPIO pin. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_clock + * - \ref sl_si91x_gpio_driver_enable_pad_receiver() + * @param[in] gpio_num - GPIO pin number to be use + * @param[in] strength - Drive strength selector(E1,E2) of type + * \ref sl_si91x_gpio_driver_strength_select_t + * possible values are + * - 0, for two_milli_amps (E1=0,E2=0) + * - 1, for four_milli_amps (E1=0,E2=1) + * - 2, for eight_milli_amps (E1=1,E2=0) + * - 3, for twelve_milli_amps(E1=1,E2=1) + * + * @return returns status 0 if successful, + * else error code as follow. + * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument + * - \ref SL_STATUS _OK (0X000) - Success + * + ******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_select_pad_driver_strength(uint8_t gpio_num, + sl_si91x_gpio_driver_strength_select_t strength); + +/***************************************************************************/ /** + * @brief Select the Driver disabled state control for an HP instance GPIO pin. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_clock + * - \ref sl_si91x_gpio_driver_enable_pad_receiver() + * @param[in] gpio_num - GPIO pin number to be use + * @param[in] disable_state - driver disable state of type + * \ref sl_si91x_gpio_driver_disable_state_t + * possible values are + * + * - 0, for HiZ (P1=0,P2=0) + * - 1, for Pull-up (P1=0,P2=1) + * - 2, for Pull-down (P1=1,P2=0) + * - 3, for Repeater (P1=1,P2=1) + * + * @return returns status 0 if successful, + * else error code as follow. + * \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument + * \ref SL_STATUS _OK (0X000) - Success + * + ******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_select_pad_driver_disable_state(uint8_t gpio_num, + sl_si91x_gpio_driver_disable_state_t disable_state); + +/***************************************************************************/ /** + * @brief Select AND/OR type of the group interrupt. If multiple interrupts + * on same port (or) different are to be generated, then use this API. + * Example: Consider port A: pin 2,3 and port D: pin 1,2 for interrupt generation. + * Choose OR, any of the selected pin condition triggers the group interrupt generation + * Choose AND, all the selected pin conditions should match to trigger group interrupt generation + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_clock, for HP instance + * - \ref sl_si91x_gpio_driver_enable_pad_receiver(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver(), for ULP instance + * Use the corresponding pad receiver API for the corresponding GPIO instance. + * - \ref sl_gpio_driver_set_pin_mode() + + * - \ref sl_si91x_gpio_driver_set_pin_direction() + * - \ref sl_si91x_gpio_driver_configure_ulp_group_interrupt(), for HP instance + * - \ref sl_si91x_gpio_driver_configure_ulp_group_interrupt, for ULP instance + * Use corresponding group interrupt configuration API for corresponding GPIO instance. + * @param[in] port - The port to associate with the pin. + * HP instance - PORT A,B,C,D + * ULP instance - ULP PORT + * @param[in] group_interrupt - Group interrupt number of type + * \ref sl_si91x_group_interrupt_t + * @param[in] and_or - AND/OR of GPIO group interrupts of type + * \ref sl_si91x_gpio_and_or_t + * - '0' - AND + * - '1' - OR + * + * @return returns status 0 if successful, + * else error code as follow. + * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument + * - \ref SL_STATUS _OK (0X000) - Success + * + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_select_group_interrupt_and_or(uint8_t port, + sl_si91x_group_interrupt_t group_interrupt, + sl_si91x_gpio_and_or_t and_or); + +/***************************************************************************/ /** + * @brief Clear the selected group interrupt status value. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_clock + * - \ref sl_si91x_gpio_driver_enable_pad_receiver() + * - \ref sl_gpio_driver_set_pin_mode() + * - \ref sl_si91x_gpio_driver_set_pin_direction() + * - \ref sl_si91x_gpio_driver_configure_ulp_group_interrupt() + * @param[in] group_interrupt - Group interrupt number of type + * \ref sl_si91x_group_interrupt_t + * @return returns status 0 if successful, + * else error code as follow. + * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is invalid argument + * - \ref SL_STATUS _OK (0X000) - Success + * + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_clear_group_interrupt(sl_si91x_group_interrupt_t group_interrupt); + +/***************************************************************************/ /** + * @brief Get the current status of the selected group interrupt. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_clock, for HP instance + * - \ref sl_si91x_gpio_driver_enable_pad_receiver(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver(), for ULP instance + * Use corresponding pad receiver API for corresponding GPIO instance. + * - \ref sl_gpio_driver_set_pin_mode(), + * - \ref sl_si91x_gpio_driver_set_pin_direction() + * - \ref sl_si91x_gpio_driver_configure_ulp_group_interrupt(), for HP instance + * - \ref sl_si91x_gpio_driver_configure_ulp_group_interrupt, for ULP instance + * Use the corresponding group interrupt configuration API for the corresponding GPIO instance. + * @param[in] port - The port to associate with the pin. + * HP instance - PORT A,B,C,D + * ULP instance - ULP PORT + * @param[in] group_interrupt - Group interrupt number of type (0 to 1) + * \ref sl_si91x_group_interrupt_t + * @return returns the group interrupt status register + * - 1, when interrupt is enabled + * - 0, when interrupt is disabled + * + ******************************************************************************/ +uint32_t sl_si91x_gpio_driver_get_group_interrupt_status(uint8_t port, sl_si91x_group_interrupt_t group_interrupt); + +/***************************************************************************/ /** + * @brief Configure the group interrupt as a wake up source across sleep wakeups. + * @param[in] port - The port to associate with the pin. + * HP instance - PORT A,B,C,D + * ULP instance - ULP PORT + * @param[in] group_interrupt - Group interrupt number of type + * \ref sl_si91x_group_interrupt_t + * @param[in] flags - GPIO group interrupt wake up flag of type + * \ref sl_si91x_gpio_wakeup_t + * - '1' - enable + * - '0' - disable + * + * @return returns status 0 if successful, + * else error code as follow. + * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument + * - \ref SL_STATUS _OK (0X000) - Success + * + ******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_select_group_interrupt_wakeup(uint8_t port, + sl_si91x_group_interrupt_t group_interrupt, + sl_si91x_gpio_wakeup_t flags); + +/***************************************************************************/ /** + * @brief Configure the MCU HP instance group interrupts with trigger type (level/edge), polarity (high/low), interrupt type (and/or) + * and register the callback function for interrupts. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_clock + * - \ref sl_si91x_gpio_driver_enable_pad_receiver() + * - \ref sl_gpio_driver_set_pin_mode() + * - \ref sl_si91x_gpio_driver_set_pin_direction() + * @param[in] configuration - configuration pointer to + * \ref sl_si91x_gpio_group_interrupt_config_t structure + * @param[in] gpio_callback - IRQ function pointer + * @return returns status 0 if successful, + * else error code as follow. + * - \ref SL_STATUS_NULL_POINTER (0x0022) - The parameter is null pointer + * - \ref SL_STATUS _OK (0X000) - Success + * + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_configure_group_interrupt(sl_si91x_gpio_group_interrupt_config_t *configuration, + sl_gpio_irq_callback_t gpio_callback); + +/***************************************************************************/ /** + * @brief Get the configured polarity of group interrupt. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_clock, for HP instance + * - \ref sl_si91x_gpio_driver_enable_pad_receiver(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver(), for ULP instance + * Use corresponding pad receiver API for corresponding GPIO instance. + * - \ref sl_gpio_driver_set_pin_mode() + * - \ref sl_si91x_gpio_driver_set_pin_direction() + * - \ref sl_si91x_gpio_driver_configure_ulp_group_interrupt(), for HP instance + * - \ref sl_si91x_gpio_driver_configure_ulp_group_interrupt, for ULP instance + * Use the corresponding group interrupt configuration API for the corresponding GPIO instance. + * @param[in] group_interrupt - GPIO group interrupt number of type + * \ref sl_si91x_group_interrupt_t + * @param[in] port - The port to associate with the pin. + * HP instance - PORT A,B,C,D + * ULP instance - ULP PORT + * @param[in] pin - The pin number on the port. + * HP instance has total 57 GPIO pins. Port 0, 1, 2 has 16 pins each. + * Port 3 has 9 pins. + * ULP instance has total 12 pins. + * @return returns group interrupt polarity + * - 1, when GPIO pin status is HIGH + * - 0, when GPIO pin status is LOW + * + ******************************************************************************/ +uint8_t sl_si91x_gpio_driver_get_group_interrupt_polarity(sl_si91x_group_interrupt_t group_interrupt, + uint8_t port, + uint8_t pin); + +/***************************************************************************/ /** + * @brief Configure the polarity to a selected group interrupt which decides the active value of the pin to be + * considered for group interrupt generation. + * '0' – group interrupt gets generated when gpio input pin status is LOW + * '1' – group interrupt gets generated when gpio input pin status is HIGH + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_clock, for HP instance + * - \ref sl_si91x_gpio_driver_enable_pad_receiver(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver(), for ULP instance + * Use the corresponding pad receiver API for the corresponding GPIO instance. + * - \ref sl_gpio_driver_set_pin_mode() + * - \ref sl_si91x_gpio_driver_set_pin_direction() + * - \ref sl_si91x_gpio_driver_configure_ulp_group_interrupt(), for HP instance + * - \ref sl_si91x_gpio_driver_configure_ulp_group_interrupt, for ULP instance + * Use the corresponding group interrupt configuration API for the corresponding GPIO instance. + * @param[in] group_interrupt - GPIO group interrupt number of type + * \ref sl_si91x_group_interrupt_t + * @param[in] port - The port to associate with the pin. + * HP instance - PORT A,B,C,D + * ULP instance - ULP PORT + * @param[in] pin - The pin number on the port. + * HP instance has total 57 GPIO pins. Port A, B, C has 16 pins each. + * Port D has 9 pins. + * ULP instance has total 12 pins. + * @param[in] polarity - polarity of GPIO group interrupt of type + * \ref sl_si91x_gpio_polarity_t + * - 1, group interrupt gets generated when GPIO pin status is '1' + * - 0, group interrupt gets generated when GPIO pin status is '0' + * + * @return returns status 0 if successful, + * else error code as follow. + * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument + * - \ref SL_STATUS _OK (0X000) - Success + * + ******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_set_group_interrupt_polarity(sl_si91x_group_interrupt_t group_interrupt, + uint8_t port, + uint8_t pin, + sl_si91x_gpio_polarity_t polarity); + +/***************************************************************************/ /** + * @brief Get the configured level/edge event for the selected group interrupt. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_clock, for HP instance + * - \ref sl_si91x_gpio_driver_enable_pad_receiver(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver(), for ULP instance + * Use corresponding pad receiver API for corresponding GPIO instance. + * - \ref sl_gpio_driver_set_pin_mode(), + * - \ref sl_si91x_gpio_driver_set_pin_direction(), + * - \ref sl_si91x_gpio_driver_configure_ulp_group_interrupt(), for HP instance + * - \ref sl_si91x_gpio_driver_configure_ulp_group_interrupt, for ULP instance + * Use the corresponding group interrupt configuration API for the corresponding GPIO instance. + * @param[in] port - The port to associate with the pin. + * HP instance - PORT A,B,C,D + * ULP instance - ULP PORT + * @param[in] group_interrupt - GPIO group interrupt number of type + * \ref sl_si91x_group_interrupt_t + * @return returns group interrupt level_edge + * - 1, for Edge + * - 0, for Level + * + ******************************************************************************/ +uint8_t sl_si91x_gpio_driver_get_group_interrupt_level_edge(uint8_t port, sl_si91x_group_interrupt_t group_interrupt); + +/***************************************************************************/ /** + * @brief Set the level/edge event for the selected group interrupt. + * '1' Triggers interrupt generation when configured edge is detected on pin + * '0' Triggers interrupt generation when configured level is detected on pin + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_clock, for HP instance + * - \ref sl_si91x_gpio_driver_enable_pad_receiver(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver(), for ULP instance + * Use the corresponding pad receiver API for the corresponding GPIO instance. + * - \ref sl_gpio_driver_set_pin_mode() + * - \ref sl_si91x_gpio_driver_set_pin_direction() + * - \ref sl_si91x_gpio_driver_configure_ulp_group_interrupt(), for HP instance + * - \ref sl_si91x_gpio_driver_configure_ulp_group_interrupt, for ULP instance + * Use the corresponding group interrupt configuration API for the corresponding GPIO instance. + * @param[in] port - The port to associate with the pin. + * - HP instance - PORT A,B,C,D + * - ULP instance - ULP PORT + * @param[in] group_interrupt - GPIO group interrupt number of type + * \ref sl_si91x_group_interrupt_t + * @param[in] level_edge - GPIO level edge group interrupt of type + * \ref sl_si91x_gpio_level_edge_t + * - 1, for Edge + * - 0, for Level + * + * @return returns status 0 if successful, + * else error code as follow. + * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument + * - \ref SL_STATUS _OK (0X000) - Success + * + ******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_set_group_interrupt_level_edge(uint8_t port, + sl_si91x_group_interrupt_t group_interrupt, + sl_si91x_gpio_level_edge_t level_edge); + +/***************************************************************************/ /** + * @brief Unmask the selected group interrupt to enable interrupt clearing upon generation. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_clock, for HP instance + * - \ref sl_si91x_gpio_driver_enable_pad_receiver(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver(), for ULP instance + * Use corresponding pad receiver API for corresponding GPIO instance. + * - \ref sl_gpio_driver_set_pin_mode() + * - \ref sl_si91x_gpio_driver_set_pin_direction() + * - \ref sl_si91x_gpio_driver_configure_ulp_group_interrupt(), for HP instance + * - \ref sl_si91x_gpio_driver_configure_ulp_group_interrupt, for ULP instance + * Use the corresponding group interrupt configuration API for the corresponding GPIO instance. + * @param[in] port - The port to associate with the pin. + * HP instance - PORT A,B,C,D + * ULP instance - ULP PORT + * @param[in] group_interrupt - GPIO group interrupt number of type + * \ref sl_si91x_group_interrupt_t + * @return returns status 0 if successful, + * else error code as follow. + * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument + * - \ref SL_STATUS _OK (0X000) - Success + * + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_unmask_group_interrupt(uint8_t port, sl_si91x_group_interrupt_t group_interrupt); + +/***************************************************************************/ /** + * @brief Mask the selected group interrupt. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_clock, for HP instance + * - \ref sl_si91x_gpio_driver_enable_pad_receiver(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver(), for ULP instance + * Use the corresponding pad receiver API for the corresponding GPIO instance. + * - \ref sl_gpio_driver_set_pin_mode() + * - \ref sl_si91x_gpio_driver_set_pin_direction() + * @param[in] port - The port to associate with the pin. + * - HP instance - PORT A,B,C,D + * - ULP instance - ULP PORT + * @param[in] group_interrupt - GPIO group interrupt number of type + * \ref sl_si91x_group_interrupt_t + * @return returns status 0 if successful, + * else error code as follow. + * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument + * - \ref SL_STATUS _OK (0X000) - Success + * + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_mask_group_interrupt(uint8_t port, sl_si91x_group_interrupt_t group_interrupt); + +/***************************************************************************/ /** + * @brief Disable the clock for either the HP or ULP instance of the GPIO Peripheral. + * @param[in] clock - Selects M4 clock or ULP clock of type + * \ref sl_si91x_gpio_select_clock_t + * - 0, for M4 GPIO CLK + * - 1, for ULP GPIO CLK + * + * @return returns status 0 if successful, + * else error code as follow. + * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument + * - \ref SL_STATUS _OK (0X000) - Success + * + ******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_disable_clock(sl_si91x_gpio_select_clock_t clock); + +/***************************************************************************/ /** + * @brief Enable the clock for either the HP or ULP instance of the GPIO peripheral. + * @param[in] clock - Selects M4 clock or ULP clock of type + * \ref sl_si91x_gpio_select_clock_t + * - 0, for M4 GPIO CLK + * - 1, for ULP GPIO CLK + * + * @return returns status 0 if successful, + * else error code as follow. + * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument + * - \ref SL_STATUS _OK (0X000) - Success + * + ******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_enable_clock(sl_si91x_gpio_select_clock_t clock); + +/***************************************************************************/ /** + * @brief Enable the selected group interrupts for either the HP or ULP instance of the GPIO peripheral. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_clock, for HP instance + * - \ref sl_si91x_gpio_driver_enable_pad_receiver(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver(), for ULP instance + * Use the corresponding pad receiver API for the corresponding GPIO instance. + * - \ref sl_gpio_driver_set_pin_mode() + * - \ref sl_si91x_gpio_driver_set_pin_direction() + * - \ref sl_si91x_gpio_driver_configure_ulp_group_interrupt(), for HP instance + * - \ref sl_si91x_gpio_driver_configure_ulp_group_interrupt, for ULP instance + * Use the corresponding group interrupt configuration API for the corresponding GPIO instance. + * @param[in] group_interrupt - GPIO group interrupt number of type + * \ref sl_si91x_group_interrupt_t + * @param[in] port - The port to associate with the pin. + * - HP instance - PORT A,B,C,D + * - ULP instance - ULP PORT + * @param[in] pin - The pin number on the port. + * HP instance has total 57 GPIO pins. Port A, B, C has 16 pins each. + * Port D has 9 pins. + * ULP instance has total 12 pins. + * @return returns status 0 if successful, + * else error code as follow. + * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument + * - \ref SL_STATUS _OK (0X000) - Success + * +*******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_enable_group_interrupt(sl_si91x_group_interrupt_t group_interrupt, + uint8_t port, + uint8_t pin); + +/***************************************************************************/ /** + * @brief Disable the selected group interrupts for either the HP or ULP instance of the GPIO peripheral. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_clock, for HP instance + * - \ref sl_si91x_gpio_driver_enable_pad_receiver(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver(), for ULP instance + * Use the corresponding pad receiver API for the corresponding GPIO instance. + * + * - \ref sl_gpio_driver_set_pin_mode() + * - \ref sl_si91x_gpio_driver_set_pin_direction() + * - \ref sl_si91x_gpio_driver_set_pin_direction() + * - \ref sl_si91x_gpio_driver_configure_ulp_group_interrupt(), for HP instance + * - \ref sl_si91x_gpio_driver_configure_ulp_group_interrupt, for ULP instance + * Use the corresponding group interrupt configuration API for the corresponding GPIO instance. + * @param[in] group_interrupt - GPIO group interrupt number of type + * \ref sl_si91x_group_interrupt_t + * @param[in] port - The port to associate with the pin. + * HP instance - PORT A,B,C,D + * ULP instance - ULP PORT + * @param[in] pin - The pin number on the port. + * HP instance has total 57 GPIO pins. Port A, B, C has 16 pins each. + * Port D has 9 pins. + * ULP instance has total 12 pins. + * @return returns status 0 if successful, + * else error code as follow. + * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument + * - \ref SL_STATUS _OK (0X000) - Success + * +*******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_disable_group_interrupt(sl_si91x_group_interrupt_t group_interrupt, + uint8_t port, + uint8_t pin); + +/***************************************************************************/ /** + * @brief Select the slew rate for the ULP instance of the GPIO peripheral. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver() + * + * @param[in] gpio_num - GPIO pin number to be use + * @param[in] slew_rate - slew rate of type \ref sl_si91x_gpio_slew_rate_t + * - '0' - Slow + * - '1' - Fast + * + * @return returns status 0 if successful, + * else error code as follow. + * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument + * - \ref SL_STATUS _OK (0X000) - Success + * + ******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_select_ulp_pad_slew_rate(uint8_t gpio_num, sl_si91x_gpio_slew_rate_t slew_rate); + +/***************************************************************************/ /** + * @brief Select the drive strength for the ULP instance of the GPIO peripheral. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver() + * + * @param[in] gpio_num - GPIO pin number to be use + * @param[in] strength - Drive strength selector(E1,E2) of type + * \ref sl_si91x_gpio_driver_strength_select_t + * - 0, for two_milli_amps (E1=0,E2=0) + * - 1, for four_milli_amps (E1=0,E2=1) + * - 2, for eight_milli_amps (E1=1,E2=0) + * - 3, for twelve_milli_amps(E1=1,E2=1) + * + * @return returns status 0 if successful, + * else error code as follow. + * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument + * - \ref SL_STATUS _OK (0X000) - Success + * + ******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_select_ulp_pad_driver_strength(uint8_t gpio_num, + sl_si91x_gpio_driver_strength_select_t strength); + +/***************************************************************************/ /** + * @brief Select the driver-disabled state control for the ULP instance of the GPIO peripheral. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver() + * + * @param[in] gpio_num - GPIO pin number to be use + * @param[in] disable_state - driver disable state of type + * \ref sl_si91x_gpio_driver_disable_state_t + * - 0, for HiZ (P1=0,P2=0) + * - 1, for Pull up (P1=0,P2=1) + * - 2, for Pull down (P1=1,P2=0) + * - 3, for Repeater (P1=1,P2=1) + * + * @return returns status 0 if successful, + * else error code as follow. + * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument + * - \ref SL_STATUS _OK (0X000) - Success + * + ******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_select_ulp_pad_driver_disable_state( + uint8_t gpio_num, + sl_si91x_gpio_driver_disable_state_t disable_state); + +/***************************************************************************/ /** + * @brief Disable the receiver enable bit for the ULP instance of the GPIO peripheral. + * @pre Pre-condition: + * - \ref sl_si91x_gpio_driver_enable_clock() + * @param[in] gpio_num - GPIO pin number to be used + * @return returns status 0 if successful, + * else error code as follow. + * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument + * - \ref SL_STATUS _OK (0X000) - Success + * + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_disable_ulp_pad_receiver(uint8_t gpio_num); + +/***************************************************************************/ /** + * @brief Enable the receiver enable bit for the ULP instance of the GPIO peripheral. + * @pre Pre-condition: + * - \ref sl_si91x_gpio_driver_enable_clock() + * @param[in] gpio_num - GPIO pin number to be used + * @return returns status 0 if successful, + * else error code as follow. + * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument + * - \ref SL_STATUS _OK (0X000) - Success + * + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_enable_ulp_pad_receiver(uint8_t gpio_num); + +/***************************************************************************/ /** + * @brief Configure the MCU ULP instance pin interrupts with the trigger type (level/edge) + * and register the callback function for interrupts. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver() + * - \ref sl_gpio_driver_set_pin_mode() + * - \ref sl_si91x_gpio_driver_set_pin_direction() + * @param[in] int_no - The interrupt number to trigger. + * @param[in] flags - Interrupt configuration flags of type + * \ref sl_si91x_gpio_interrupt_config_flag_t + * @param[in] pin - GPIO pin number (0 to 11) + * @param[in] gpio_callback - IRQ function pointer + * @return returns status 0 if successful, + * else error code as follow. + * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument + * - \ref SL_STATUS_NULL_POINTER (0x0022) - The parameter is null pointer + * - \ref SL_STATUS _OK (0X000) - Success + * + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_configure_ulp_pin_interrupt(uint8_t int_no, + sl_si91x_gpio_interrupt_config_flag_t flags, + sl_si91x_gpio_pin_ulp_t pin, + sl_gpio_irq_callback_t gpio_callback); + +/***************************************************************************/ /** + * @brief Set the NPSS GPIO pin MUX (mode) to the selected mode. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_select_uulp_npss_receiver() + * + * @param[in] pin - NPSS GPIO pin number(0...4) of type + * \ref sl_si91x_uulp_npss_mode_t + * @param[in] mode - NPSS GPIO MUX value (0 to 10) + * @return returns status 0 if successful, + * else error code as follow. + * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument + * - \ref SL_STATUS _OK (0X000) - Success + * + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_set_uulp_npss_pin_mux(uint8_t pin, sl_si91x_uulp_npss_mode_t mode); + +/***************************************************************************/ /** + * @brief Enable/disable the NPSS GPIO Input Buffer. + * @pre Pre-condition: + * - \ref sl_si91x_gpio_driver_enable_clock() + * @param[in] pin - is NPSS GPIO pin number (0...4) + * @param[in] receiver - is enable/disable NPSS GPIO receiver of type + * \ref sl_si91x_gpio_receiver_t + * - '1' - Enable + * - '0' - Disable + * + * @return returns status 0 if successful, + * else error code as follow. + * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument + * - \ref SL_STATUS _OK (0X000) - Success + * + ******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_select_uulp_npss_receiver(uint8_t pin, sl_si91x_gpio_receiver_t receiver); + +/***************************************************************************/ /** + * @brief Set the direction for the selected NPSS GPIO. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_select_uulp_npss_receiver() + * - \ref sl_si91x_gpio_driver_set_uulp_npss_pin_mux() + * @param[in] pin - is NPSS GPIO pin number (0...4) + * @param[in] direction - is direction value (Input / Output) of type + * \ref sl_si91x_gpio_direction_t + * - '1' - Input Direction + * - '0' - Output Direction + * + * @return returns status 0 if successful, + * else error code as follow. + * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument + * - \ref SL_STATUS _OK (0X000) - Success + * + ******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_set_uulp_npss_direction(uint8_t pin, sl_si91x_gpio_direction_t direction); + +/***************************************************************************/ /** + * @brief Get the direction of the selected NPSS GPIO. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_select_uulp_npss_receiver() + * - \ref sl_si91x_gpio_driver_set_uulp_npss_pin_mux() + * - \ref sl_si91x_gpio_driver_set_uulp_npss_direction() + * + * @param[in] pin - is NPSS GPIO pin number(0...4) + * @return returns the GPIO pin direction + * - 1, Input Direction + * - 0, Output Direction + *******************************************************************************/ +uint8_t sl_si91x_gpio_driver_get_uulp_npss_direction(uint8_t pin); + +/***************************************************************************/ /** + * @brief Control(set or clear) the NPSS GPIO pin value. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_select_uulp_npss_receiver() + * - \ref sl_si91x_gpio_driver_set_uulp_npss_pin_mux() + * - \ref sl_si91x_gpio_driver_set_uulp_npss_direction() + * @param[in] pin - is NPSS GPIO pin number (0...4) of type + * \ref sl_si91x_gpio_pin_value_t + * @param[in] pin_value - is NPSS GPIO pin value + * - '0' - Output + * - '1' - Input + * + * @return returns status 0 if successful, + * else error code as follow. + * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument + * - \ref SL_STATUS _OK (0X000) - Success + * + ******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_set_uulp_npss_pin_value(uint8_t pin, sl_si91x_gpio_pin_value_t pin_value); + +/***************************************************************************/ /** + * @brief Read the status of the selected NPSS GPIO pin value. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_select_uulp_npss_receiver() + * - \ref sl_si91x_gpio_driver_set_uulp_npss_pin_mux() + * - \ref sl_si91x_gpio_driver_set_uulp_npss_direction() + * - \ref sl_si91x_gpio_driver_set_uulp_npss_pin_value() + * @param[in] pin - is NPSS GPIO pin number (0...4) + * @return returns the pin logical state of pin + * - '0' - Output + * - '1' - Input + * + ******************************************************************************/ +uint8_t sl_si91x_gpio_driver_get_uulp_npss_pin(uint8_t pin); + +/***************************************************************************/ /** + * @brief Select the NPSS GPIO polarity for generating the interrupt. + * @pre Pre-condition: + * - \ref sl_si91x_gpio_driver_enable_clock() + * @param[in] pin - is NPSS GPIO pin number (0...4) + * @param[in] polarity - GPIO polarity + * \ref sl_si91x_gpio_polarity_t + * - '1' - High + * - '0' - Low + * + * @return returns status 0 if successful, + * else error code as follow. + * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument + * - \ref SL_STATUS _OK (0X000) - Success + * + ******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_select_uulp_npss_polarity(uint8_t pin, sl_si91x_gpio_polarity_t polarity); + +/***************************************************************************/ /** + * @brief Set the NPSS GPIO interrupt as a wake up source across sleep wakeups. + * @pre Pre-condition: + * - \ref sl_si91x_gpio_driver_enable_clock() + * @param[in] npssgpio_interrupt - OR'ed values of the NPSS GPIO interrupts + * @return returns status 0 if successful, + * else error code as follow. + * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument + * - \ref SL_STATUS _OK (0X000) - Success + * + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_set_uulp_npss_wakeup_interrupt(uint8_t npssgpio_interrupt); + +/***************************************************************************/ /** + * @brief Clear the UULP NPSS GPIO Interrupt as a wake up source. + * @pre Pre-condition: + * - \ref sl_si91x_gpio_driver_enable_clock() + * @param[in] npssgpio_interrupt - OR'ed values of the NPSS GPIO interrupts + * @return returns status 0 if successful, + * else error code as follow. + * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument + * - \ref SL_STATUS _OK (0X000) - Success + * + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_clear_uulp_npss_wakeup_interrupt(uint8_t npssgpio_interrupt); + +/***************************************************************************/ /** + * @brief Mask the selected NPSS GPIO interrupt. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_set_uulp_pad_configuration() + * - \ref sl_si91x_gpio_driver_select_uulp_npss_receiver() + * - \ref sl_si91x_gpio_driver_set_uulp_npss_pin_mux() + * - \ref sl_si91x_gpio_driver_set_uulp_npss_direction() + * @param[in] npssgpio_interrupt - OR'ed values of the NPSS GPIO interrupts + * @return returns status 0 if successful, + * else error code as follow. + * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument + * - \ref SL_STATUS _OK (0X000) - Success + * + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_mask_uulp_npss_interrupt(uint8_t npssgpio_interrupt); + +/***************************************************************************/ /** + * @brief Unmask the selected NPSS GPIO interrupt. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_set_uulp_pad_configuration() + * - \ref sl_si91x_gpio_driver_select_uulp_npss_receiver() + * - \ref sl_si91x_gpio_driver_set_uulp_npss_pin_mux() + * - \ref sl_si91x_gpio_driver_set_uulp_npss_direction() + * @param[in] npssgpio_interrupt - OR'ed values of the NPSS GPIO interrupts + * @return returns status 0 if successful, + * else error code as follow. + * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument + * - \ref SL_STATUS _OK (0X000) - Success + * + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_unmask_uulp_npss_interrupt(uint8_t npssgpio_interrupt); + +/***************************************************************************/ /** + * @brief Clear the selected NPSS GPIO interrupt. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_set_uulp_pad_configuration() + * - \ref sl_si91x_gpio_driver_select_uulp_npss_receiver() + * - \ref sl_si91x_gpio_driver_set_uulp_npss_pin_mux() + * - \ref sl_si91x_gpio_driver_set_uulp_npss_direction() + * - \ref sl_si91x_gpio_configure_uulp_interrupt() + * @param[in] npssgpio_interrupt - OR'ed values of the NPSS GPIO interrupts + * @return returns status 0 if successful, + * else error code as follow. + * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument + * - \ref SL_STATUS _OK (0X000) - Success + * + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_clear_uulp_interrupt(uint8_t npssgpio_interrupt); + +/***************************************************************************/ /** + * @brief Get the current status of all the NPSS GPIO interrupt status. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_set_uulp_pad_configuration() + * - \ref sl_si91x_gpio_driver_select_uulp_npss_receiver() + * - \ref sl_si91x_gpio_driver_set_uulp_npss_pin_mux() + * - \ref sl_si91x_gpio_driver_set_uulp_npss_direction() + * - \ref sl_si91x_gpio_configure_uulp_interrupt() + * + * @param none + * @return returns the UULP INTR status. + * - 1, interrupt has been raised + * - 0, interrupt is masked or not raised + * + ******************************************************************************/ +uint8_t sl_si91x_gpio_driver_get_uulp_interrupt_status(void); + +/***************************************************************************/ /** + * @brief Get the selected ULP instance GPIO pin interrupt status. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver() + * - \ref sl_gpio_driver_set_pin_mode() + * - \ref sl_si91x_gpio_driver_set_pin_direction() + * - \ref sl_si91x_gpio_configure_ulp_pin_interrupt() + * @param[in] flags : ULP GPIO interrupt sources status. + * @return returns the ULP INTR status. + * 1, interrupt has been raised + * 0, interrupt is masked or not raised + ******************************************************************************/ +uint32_t sl_si91x_gpio_driver_get_ulp_interrupt_status(uint32_t flags); + +/***************************************************************************/ /** + * @brief Clear the selected ULP instance GPIO pin interrupts. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver() + * - \ref sl_gpio_driver_set_pin_mode() + * - \ref sl_si91x_gpio_driver_set_pin_direction() + * - \ref sl_si91x_gpio_configure_ulp_pin_interrupt() + * @param[in] flags : ULP GPIO interrupt sources to clear. + * @return returns status 0 if successful, + * else error code as follow. + * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument + * - \ref SL_STATUS _OK (0X000) - Success + * + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_clear_ulp_interrupt(uint32_t flags); + +/***************************************************************************/ /** + * @brief Clear the selected ULP instance group interrupt. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver() + * - \ref sl_gpio_driver_set_pin_mode() + * - \ref sl_si91x_gpio_driver_set_pin_direction() + * - \ref sl_si91x_gpio_driver_configure_ulp_group_interrupt() + * + * Use the corresponding group interrupt configuration API for the corresponding GPIO instance. + * @param[in] group_interrupt - Group interrupt number of type + * \ref sl_si91x_group_interrupt_t + * @return returns status 0 if successful, + * else error code as follow. + * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument + * - \ref SL_STATUS _OK (0X000) - Success + * + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_clear_ulp_group_interrupt(sl_si91x_group_interrupt_t group_interrupt); + +/***************************************************************************/ /** + * @brief Configure the UULP GPIO pin interrupt with interrupt type level or edge and registers callback function for interrupts. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_set_uulp_pad_configuration() + * - \ref sl_si91x_gpio_driver_select_uulp_npss_receiver() + * - \ref sl_si91x_gpio_driver_set_uulp_npss_pin_mux() + * - \ref sl_si91x_gpio_driver_set_uulp_npss_direction() + * @param[in] flags - Interrupt configuration flags of type + * \ref sl_si91x_gpio_interrupt_config_flag_t + * @param[in] npssgpio_interrupt - NPSS GPIO input number (0 to 4) + * @param[in] gpio_callback - IRQ function pointer + * @return returns status 0 if successful, + * else error code as follow. + * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument + * - \ref SL_STATUS_NULL_POINTER (0x0022) - The parameter is null pointer + * - \ref SL_STATUS _OK (0X000) - Success + * + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_configure_uulp_interrupt(sl_si91x_gpio_interrupt_config_flag_t flags, + uint8_t npssgpio_interrupt, + sl_gpio_irq_callback_t gpio_callback); + +/***************************************************************************/ /** + * @brief Configure the MCU ULP instance group interrupts with trigger type (level/edge), polarity (high/low), interrupt type (and/or) + * and register the callback function for interrupts. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver() + * - \ref sl_gpio_driver_set_pin_mode() + * - \ref sl_si91x_gpio_driver_set_pin_direction() + * @param[in] configuration - configuration pointer to + * \ref sl_si91x_gpio_group_interrupt_config_t structure + * @param[in] gpio_callback - IRQ function pointer + * @return returns status 0 if successful, + * else error code as follow. + * - \ref SL_STATUS_NULL_POINTER (0x0022) - The parameter is a null pointer + * - \ref SL_STATUS _OK (0X000) - Success + * + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_configure_ulp_group_interrupt(sl_si91x_gpio_group_interrupt_config_t *configuration, + sl_gpio_irq_callback_t gpio_callback); + +/***************************************************************************/ /** + * @brief Toggle the selected UULP pin status. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_select_uulp_npss_receiver() + * - \ref sl_si91x_gpio_driver_set_uulp_npss_pin_mux() + * - \ref sl_si91x_gpio_driver_set_uulp_npss_direction() + * @param[in] pin - UULP pin number to toggle + * @return returns status 0 if successful, + * else error code as follow. + * - \ref SL_STATUS_INVALID_PARAMETER (0x0021) - The parameter is an invalid argument + * - \ref SL_STATUS _OK (0X000) - Success + * + ******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_toggle_uulp_npss_pin(uint8_t pin); + +/***************************************************************************/ /** + * @brief Configure the UULP GPIO pin mode, receiver enable, direction and polarity settings. + * @pre Pre-condition: + * - \ref sl_si91x_gpio_driver_enable_clock() + * @param[in] pad_config : PAD configuration pointer to \ref uulp_pad_config_t structure + * @return returns status 0 if successful, + * else error code as follow. + * - \ref SL_STATUS_NULL_POINTER (0x0022) - The parameter is a null pointer + * - \ref SL_STATUS _OK (0X000) - Success + * + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_set_uulp_pad_configuration(uulp_pad_config_t *pad_config); + +/***************************************************************************/ /** +* @brief Get the release, SQA, and development version numbers of the GPIO peripheral. +* @param none +* @return returns structure of type \ref sl_si91x_gpio_version_t +*******************************************************************************/ +sl_si91x_gpio_version_t sl_si91x_gpio_driver_get_version(void); + +/** @} (end addtogroup GPIO) */ + +// ******** THE REST OF THE FILE IS DOCUMENTATION ONLY !*********************** +/// @addtogroup GPIO General-Purpose Input-Output +/// @{ +/// +/// @details +/// +/// @n @section GPIO_Intro Introduction +/// The GPIO (General Purpose Input/Output) driver provides a comprehensive set of functions to +/// configure and control the GPIO pins. The GPIO pins can be used for various purposes such as reading +/// digital signals, controlling external devices, generating interrupts, etc. The GPIO driver simplifies the process of interacting +/// with GPIO pins, making it easier to integrate GPIO functionality into the application. +/// +/// @n @section GPIO_Config Configuration +/// +/// @li To configure the GPIO driver, identify the GPIO instance and pins you want to configure. Set the direction of each pin +/// as either input or output. Then, if needed, set the drive strength for the pins to ensure they can +/// handle the required current. Set the GPIO mux/mode and pad selection if needed. Configure any interrupt settings, such as trigger type (level or edge) and +/// interrupt polarity (high or low). If interrupts are used, register the appropriate callback functions to handle them. +/// +/// @li Additionally, make sure to enable the GPIO clock for the selected instance to ensure the GPIO peripheral operates correctly. +/// +/// +/// @li These steps are necessary for the GPIO pins to function correctly and trigger interrupts as required by the application. +/// The respective APIs for the same functionality will change depending on the GPIO in use i.e. Ultra Ultra Low Power (UULP), Ultra Low Power (ULP), or High Power (HP). +/// +/// @n @section GPIO_Usage Usage +/// +/// @li For UULP GPIOs, common functions include: +/// +/// 1. @ref sl_gpio_driver_configure_interrupt +/// 2. @ref sl_gpio_driver_toggle_pin +/// 3. @ref sl_gpio_driver_get_pin +/// 4. @ref sl_gpio_driver_clear_pin +/// 5. @ref sl_gpio_driver_set_pin +/// 6. @ref sl_gpio_set_configuration +/// +/// @li To set the pin MUX mode, @ref sl_si91x_gpio_driver_set_uulp_npss_pin_mux can be used. +/// For enabling or disabling the input buffer, use @ref sl_si91x_gpio_driver_select_uulp_npss_receiver. Additionally, +/// set pin direction with @ref sl_si91x_gpio_driver_set_uulp_npss_direction. Also, use @ref sl_gpio_set_pin to set the pin value. +/// For configuring UULP pin interrupts @ref sl_gpio_configure_pin_interrupt +/// +/// @li For ULP GPIOs, some of the common functions include: +/// +/// 1. @ref sl_gpio_driver_configure_interrupt +/// 2. @ref sl_gpio_driver_toggle_pin +/// 3. @ref sl_gpio_driver_get_pin +/// 4. @ref sl_gpio_driver_clear_pin +/// 5. @ref sl_gpio_driver_set_pin +/// 6. @ref sl_gpio_set_configuration +/// +/// @li With @ref sl_si91x_gpio_driver_select_ulp_pad_slew_rate, set the slew rate for ULP GPIO pins. With @ref sl_si91x_gpio_driver_select_ulp_pad_driver_strength +/// choose the drive strength. To manage the receiver, @ref sl_si91x_gpio_driver_enable_ulp_pad_receiver and for disabling and enabling the receiver +/// @ref sl_si91x_gpio_driver_enable_ulp_pad_receiver can be used, respectively. For configuring ULP pin interrupts, @ref sl_gpio_configure_pin_interrupt +/// can be used to set up pin interrupts with defined trigger types (level/edge). For configuring ULP group interrupts, @ref sl_si91x_gpio_driver_configure_ulp_group_interrupt, +/// more than '1' gpio pin can be considered for group interrupts. +/// +/// @li For HP GPIOs, some of the common functions include: +/// +/// 1. @ref sl_gpio_set_configuration +/// 2. @ref sl_gpio_driver_set_pin +/// 3. @ref sl_gpio_driver_clear_pin +/// 4. @ref sl_gpio_driver_get_pin +/// 5. @ref sl_gpio_driver_toggle_pin +/// 6. @ref sl_gpio_driver_configure_interrupt +/// +/// @li To configure a GPIO pin, first, use @ref sl_si91x_gpio_driver_set_pin_direction to set its direction. +/// To enable the receiver for reading the pin status, use @ref sl_si91x_gpio_driver_enable_pad_receiver. +/// For selecting the pad, use @ref sl_si91x_gpio_driver_enable_pad_selection. To configure group interrupts for the MCU HP instance, +/// use @ref sl_si91x_gpio_driver_configure_group_interrupt. Make sure to enable the clock for HP or ULP instances, +/// using @ref sl_si91x_gpio_driver_enable_clock. To configure HP pin interrupts @ref sl_gpio_configure_pin_interrupt +/// +/// @li There is also an alternate API for configuring GPIO pin straight forward(without configuring mode, direction, pad, clock etc., using separate APIs), by providing +/// information to structure members. Please refer to @ref sl_gpio_set_configuration. +/// +/// @li Other APIs can be referred to in the API Documentation. +/// +/// @} end group GPIO ********************************************************/ + +#ifdef __cplusplus +} +#endif + +#endif ///< GPIO_PRESENT +#endif ///< SL_SI91X_DRIVER_GPIO_H diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_driver_gpio.c b/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_driver_gpio.c new file mode 100644 index 000000000..d02720eb6 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_driver_gpio.c @@ -0,0 +1,2069 @@ +/******************************************************************************* + * @file sl_si91x_driver_gpio.c + * @brief General Purpose IO (GPIO) driver API. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licenser of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be miss represented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * miss represented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_si91x_driver_gpio.h" +#include +#include "sl_status.h" +/******************************************************************************* + *************************** DEFINES / MACROS ******************************** + ******************************************************************************/ +#define GPIO_RELEASE_VERSION 0 // GPIO Release version +#define GPIO_MAJOR_VERSION 0 // GPIO SQA version +#define GPIO_MINOR_VERSION 2 // GPIO Developer version +#define GPIO_DIRECTION_MAX_VALUE 1 // GPIO maximum direction set value +#define GPIO_CLOCK_MAX_VAL 1 // Validating clock for GPIO instance +#define GPIO_GROUP_INTERRUPT_MAX_VALUE 1 // Maximum number of GPIO group interrupts +#define GPIO_LEVEL_EDGE_MAX_VALUE 1 // GPIO maximum level edge value +#define GPIO_POLARITY_MAX_VALUE 1 // GPIO maximum polarity value +#define GPIO_AND_OR_MAX_VALUE 1 // GPIO maximum AND_OR value +#define GPIO_SLEW_RATE_MAX_VALUE 1 // GPIO maximum SLEW RATE value +#define GPIO_RECEIVER_MAX_VALUE 1 // GPIO maximum receiver value +#define GPIO_PIN_VALUE_MAX_VALUE 1 // GPIO maximum pin value +#define GPIO_STRENGTH_MAX_VAL 3 // GPIO maximum strength value +#define GPIO_DISABLE_STATE_MAX_VAL 3 // GPIO maximum disable state value +#define GPIO_UULP_MAX_PIN_NUM 5 // GPIO UULP maximum pin number +#define GPIO_MODE_MAX_VALUE 7 // GPIO maximum MODE value +#define GPIO_INTERRUPT_MAX_VALUE 7 // GPIO interrupt maximum value +#define GPIO_ULP_INTERRUPT_MAX_VALUE 7 // GPIO interrupt maximum value +#define GPIO_ULP_MAX_PIN_NUM 11 // GPIO ULP maximum pin number +#define GPIO_NPSSGPIO_INTERRUPT_VALUE_MAX_VALUE 16 // NPSSGPIO maximum value +#define GPIO_NPSS_WAKEUP_MAX_VALUE 4 //NPSSGPIO maximum value +#define GPIO_NPSS_PIN_MAX_VALUE 4 //NPSSGPIO pin maximum value +#define GPIO_MAX_PAD_NUM 34 // GPIO maximum pad number +#define GPIO_MAX_PIN_NUM 57 // Maximum number of GPIO pins in m4 instance + +#define ULP_GPIO_INTERRUPT_PRIORITY 18 // Priority 18 for ulp pin interrupt +#define GPIO_INTERRUPT_PRIOPRITY0 52 // Priority 52 for m4 pin interrupt 0 +#define GPIO_INTERRUPT_PRIOPRITY1 53 // Priority 53 for m4 pin interrupt 1 +#define GPIO_INTERRUPT_PRIOPRITY2 54 // Priority 54 for m4 pin interrupt 2 +#define GPIO_INTERRUPT_PRIOPRITY3 55 // Priority 55 for m4 pin interrupt 3 +#define GPIO_INTERRUPT_PRIOPRITY4 56 // Priority 56 for m4 pin interrupt 4 +#define GPIO_INTERRUPT_PRIOPRITY5 57 // Priority 57 for m4 pin interrupt 5 +#define GPIO_INTERRUPT_PRIOPRITY6 58 // Priority 58 for m4 pin interrupt 6 +#define GPIO_INTERRUPT_PRIOPRITY7 59 // Priority 59 for m4 pin interrupt 7 + +#define GPIO_PAD_SELECT_NO_PAD 0 // GPIO PAD selection number 0 +#define GPIO_PAD_SELECT_1 1 // GPIO PAD selection number 1 +#define GPIO_PAD_SELECT_2 2 // GPIO PAD selection number 2 +#define GPIO_PAD_SELECT_3 3 // GPIO PAD selection number 3 +#define GPIO_PAD_SELECT_4 4 // GPIO PAD selection number 4 +#define GPIO_PAD_SELECT_5 5 // GPIO PAD selection number 5 +#define GPIO_PAD_SELECT_6 6 // GPIO PAD selection number 6 +#define GPIO_PAD_SELECT_7 7 // GPIO PAD selection number 7 +#define GPIO_PAD_SELECT_8 8 // GPIO PAD selection number 8 +#define GPIO_PAD_SELECT_9 9 // GPIO PAD selection number 9 +#define GPIO_PAD_SELECT_10 10 // GPIO PAD selection number 10 +#define GPIO_PAD_SELECT_11 11 // GPIO PAD selection number 11 +#define GPIO_PAD_SELECT_12 12 // GPIO PAD selection number 12 +#define GPIO_PAD_SELECT_13 13 // GPIO PAD selection number 13 +#define GPIO_PAD_SELECT_14 14 // GPIO PAD selection number 14 +#define GPIO_PAD_SELECT_15 15 // GPIO PAD selection number 15 +#define GPIO_PAD_SELECT_16 16 // GPIO PAD selection number 16 +#define GPIO_PAD_SELECT_17 17 // GPIO PAD selection number 17 +#define GPIO_PAD_SELECT_18 18 // GPIO PAD selection number 18 +#define GPIO_PAD_SELECT_19 19 // GPIO PAD selection number 19 +#define GPIO_PAD_SELECT_20 20 // GPIO PAD selection number 20 +#define GPIO_PAD_SELECT_21 21 // GPIO PAD selection number 21 +#define GPIO_PAD_SELECT_22 22 // GPIO PAD selection number 22 +#define GPIO_PAD_SELECT_23 23 // GPIO PAD selection number 23 +#define GPIO_PAD_SELECT_24 24 // GPIO PAD selection number 24 +#define GPIO_PAD_SELECT_25 25 // GPIO PAD selection number 25 +#define GPIO_PAD_SELECT_26 26 // GPIO PAD selection number 26 +#define GPIO_PAD_SELECT_27 27 // GPIO PAD selection number 27 +#define GPIO_PAD_SELECT_28 28 // GPIO PAD selection number 28 +#define GPIO_PAD_SELECT_29 29 // GPIO PAD selection number 29 +#define GPIO_PAD_SELECT_30 30 // GPIO PAD selection number 30 +#define GPIO_PAD_SELECT_31 31 // GPIO PAD selection number 31 +#define GPIO_PAD_SELECT_32 32 // GPIO PAD selection number 32 +#define GPIO_PAD_SELECT_33 33 // GPIO PAD selection number 33 +#define OUTPUT_VALUE 1 // GPIO output value +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +///@brief structure to hold GPIO interrupt configurations +typedef struct { + uint8_t gpio_priority[8]; + uint8_t gpio_nvic[8]; +} sl_gpio_intr_configure_t; + +/******************************************************************************* + *************************** LOCAL VARIABLES ********************************* + ******************************************************************************/ + +const sl_gpio_intr_configure_t intr_config = { { GPIO_INTERRUPT_PRIOPRITY0, + GPIO_INTERRUPT_PRIOPRITY1, + GPIO_INTERRUPT_PRIOPRITY2, + GPIO_INTERRUPT_PRIOPRITY3, + GPIO_INTERRUPT_PRIOPRITY4, + GPIO_INTERRUPT_PRIOPRITY5, + GPIO_INTERRUPT_PRIOPRITY6, + GPIO_INTERRUPT_PRIOPRITY7 }, + { PININT0_NVIC_NAME, + PININT1_NVIC_NAME, + PININT2_NVIC_NAME, + PININT3_NVIC_NAME, + PININT4_NVIC_NAME, + PININT5_NVIC_NAME, + PININT6_NVIC_NAME, + PININT7_NVIC_NAME } }; +// The m4_gpio_pad array refers to PAD selected for particular GPIO pin. For example GPIO_0 selects GPIO_PAD_SELECT_NO_PAD. +// GPIO_6 selects GPIO_PAD_SELECT_1, GPIO_7 selects GPIO_PAD_SELECT_2 and so on. +static const uint8_t m4_gpio_pad[76] = { + GPIO_PAD_SELECT_NO_PAD, GPIO_PAD_SELECT_NO_PAD, GPIO_PAD_SELECT_NO_PAD, GPIO_PAD_SELECT_NO_PAD, + GPIO_PAD_SELECT_NO_PAD, GPIO_PAD_SELECT_NO_PAD, GPIO_PAD_SELECT_1, GPIO_PAD_SELECT_2, + GPIO_PAD_SELECT_3, GPIO_PAD_SELECT_4, GPIO_PAD_SELECT_5, GPIO_PAD_SELECT_6, + GPIO_PAD_SELECT_7, GPIO_PAD_SELECT_NO_PAD, GPIO_PAD_SELECT_NO_PAD, GPIO_PAD_SELECT_8, + GPIO_PAD_SELECT_NO_PAD, GPIO_PAD_SELECT_NO_PAD, GPIO_PAD_SELECT_NO_PAD, GPIO_PAD_SELECT_NO_PAD, + GPIO_PAD_SELECT_NO_PAD, GPIO_PAD_SELECT_NO_PAD, GPIO_PAD_SELECT_NO_PAD, GPIO_PAD_SELECT_NO_PAD, + GPIO_PAD_SELECT_NO_PAD, GPIO_PAD_SELECT_25, GPIO_PAD_SELECT_26, GPIO_PAD_SELECT_27, + GPIO_PAD_SELECT_28, GPIO_PAD_SELECT_29, GPIO_PAD_SELECT_30, GPIO_PAD_SELECT_9, + GPIO_PAD_SELECT_9, GPIO_PAD_SELECT_9, GPIO_PAD_SELECT_9, GPIO_PAD_SELECT_NO_PAD, + GPIO_PAD_SELECT_NO_PAD, GPIO_PAD_SELECT_NO_PAD, GPIO_PAD_SELECT_NO_PAD, GPIO_PAD_SELECT_NO_PAD, + GPIO_PAD_SELECT_NO_PAD, GPIO_PAD_SELECT_NO_PAD, GPIO_PAD_SELECT_NO_PAD, GPIO_PAD_SELECT_NO_PAD, + GPIO_PAD_SELECT_NO_PAD, GPIO_PAD_SELECT_NO_PAD, GPIO_PAD_SELECT_10, GPIO_PAD_SELECT_11, + GPIO_PAD_SELECT_12, GPIO_PAD_SELECT_13, GPIO_PAD_SELECT_14, GPIO_PAD_SELECT_15, + GPIO_PAD_SELECT_16, GPIO_PAD_SELECT_17, GPIO_PAD_SELECT_18, GPIO_PAD_SELECT_19, + GPIO_PAD_SELECT_20, GPIO_PAD_SELECT_21, GPIO_PAD_SELECT_NO_PAD, GPIO_PAD_SELECT_NO_PAD, + GPIO_PAD_SELECT_NO_PAD, GPIO_PAD_SELECT_NO_PAD, GPIO_PAD_SELECT_NO_PAD, GPIO_PAD_SELECT_NO_PAD, + GPIO_PAD_SELECT_22, GPIO_PAD_SELECT_23, GPIO_PAD_SELECT_24, GPIO_PAD_SELECT_25, + GPIO_PAD_SELECT_26, GPIO_PAD_SELECT_27, GPIO_PAD_SELECT_28, GPIO_PAD_SELECT_29, + GPIO_PAD_SELECT_30, GPIO_PAD_SELECT_31, GPIO_PAD_SELECT_32, GPIO_PAD_SELECT_33 +}; + +static uint8_t ulp_gpio_pad[12] = { GPIO_PAD_SELECT_22, GPIO_PAD_SELECT_23, GPIO_PAD_SELECT_24, GPIO_PAD_SELECT_25, + GPIO_PAD_SELECT_26, GPIO_PAD_SELECT_27, GPIO_PAD_SELECT_28, GPIO_PAD_SELECT_29, + GPIO_PAD_SELECT_30, GPIO_PAD_SELECT_31, GPIO_PAD_SELECT_32, GPIO_PAD_SELECT_33 }; +/******************************************************************************* + ***********************  Global function Prototypes *************************** + ******************************************************************************/ +void PIN_IRQ0_Handler(void); +void PIN_IRQ1_Handler(void); +void PIN_IRQ2_Handler(void); +void PIN_IRQ3_Handler(void); +void PIN_IRQ4_Handler(void); +void PIN_IRQ5_Handler(void); +void PIN_IRQ6_Handler(void); +void PIN_IRQ7_Handler(void); +void GRP_IRQ0_Handler(void); +void GRP_IRQ1_Handler(void); +void UULP_PIN_IRQ_Handler(void); +void ULP_PIN_IRQ_Handler(void); +void ULP_GROUP_IRQ_Handler(void); + +/******************************************************************************* + ************************ GLOBAL FUNCTIONS ************************** + ******************************************************************************/ +sl_gpio_irq_callback_t gpio_callback_function_pointer[GPIO_MAX_INTR_VALUE]; +sl_gpio_irq_callback_t gpio_group_int_callback_fptr[MAX_GROUP_INT]; +sl_gpio_irq_callback_t gpio_ulp_pin_int_callback_fptr[GPIO_MAX_INTR_VALUE]; +sl_gpio_irq_callback_t gpio_ulp_group_int_callback_fptr[MAX_GROUP_INT]; +sl_gpio_irq_callback_t gpio_uulp_pin_int_callback_fptr[MAX_UULP_INT]; + +/******************************************************************************* + * @brief This API is used for GPIO pin configuration to set the direction, mode, + * pin and port, clock. + ******************************************************************************/ +sl_status_t sl_gpio_set_configuration(sl_si91x_gpio_pin_config_t pin_config) +{ + sl_status_t status; + switch (pin_config.port_pin.port) { + case SL_GPIO_PORT_A: + case SL_GPIO_PORT_B: + case SL_GPIO_PORT_C: + case SL_GPIO_PORT_D: + // Check if the GPIO pad is selected and it's not NO PAD. + if (m4_gpio_pad[(pin_config.port_pin.port * MAX_GPIO_PORT_PIN) + pin_config.port_pin.pin] + != GPIO_PAD_SELECT_NO_PAD) { + // Check if the GPIO pad is selected and not PAD_SELECT_9. + if (m4_gpio_pad[(pin_config.port_pin.port * MAX_GPIO_PORT_PIN) + pin_config.port_pin.pin] != PAD_SELECT_9) { + if ((pin_config.port_pin.pin >= HOST_PAD_MIN && pin_config.port_pin.pin <= HOST_PAD_MAX) + || ((pin_config.port_pin.port == SL_GPIO_PORT_B && pin_config.port_pin.pin >= GPIO_PIN_NUMBER9) + && (pin_config.port_pin.port == SL_GPIO_PORT_B && pin_config.port_pin.pin <= GPIO_PIN_NUMBER14))) { + status = sl_si91x_gpio_driver_enable_host_pad_selection( + m4_gpio_pad[(pin_config.port_pin.port * MAX_GPIO_PORT_PIN) + pin_config.port_pin.pin]); + if (status != SL_STATUS_OK) { + return status; + } + } else { + status = sl_si91x_gpio_driver_enable_pad_selection( + m4_gpio_pad[(pin_config.port_pin.port * MAX_GPIO_PORT_PIN) + pin_config.port_pin.pin]); + if (status != SL_STATUS_OK) { + return status; + } + } + } + } + // Enable the pad receiver for the pin. It will enable the pad for respective GPIO pin + if (pin_config.port_pin.port == SL_GPIO_PORT_A) { + status = sl_si91x_gpio_driver_enable_pad_receiver(pin_config.port_pin.pin); + if (status != SL_STATUS_OK) { + return status; + } + } else { + status = sl_si91x_gpio_driver_enable_pad_receiver((pin_config.port_pin.port * MAX_GPIO_PORT_PIN) + + pin_config.port_pin.pin); + if (status != SL_STATUS_OK) { + return status; + } + } + // Set pin mode for the pin. By default mode 0 is set, which is a normal GPIO + status = sl_gpio_driver_set_pin_mode(&pin_config.port_pin, (sl_gpio_mode_t)SL_GPIO_MODE_0, OUTPUT_VALUE); + if (status != SL_STATUS_OK) { + return status; + } + sl_si91x_gpio_set_pin_direction(pin_config.port_pin.port, + pin_config.port_pin.pin, + (sl_si91x_gpio_direction_t)pin_config.direction); + break; + default: + break; + } + // Check if the GPIO port is the Ultra-Low Power GPIO port. + if (pin_config.port_pin.port == SL_GPIO_ULP_PORT) { + // Enable pad selection for the pin. + status = sl_si91x_gpio_driver_enable_pad_selection(ulp_gpio_pad[pin_config.port_pin.pin]); + if (status != SL_STATUS_OK) { + return status; + } + // Enable ulp pad receiver for the pin. It will enable the pad for respective GPIO pin + status = sl_si91x_gpio_driver_enable_ulp_pad_receiver(pin_config.port_pin.pin); + if (status != SL_STATUS_OK) { + return status; + } + // Set ulp pin mode for the pin. By default mode 0 is set, which is a normal GPIO + status = sl_gpio_driver_set_pin_mode(&pin_config.port_pin, (sl_gpio_mode_t)SL_GPIO_MODE_0, OUTPUT_VALUE); + if (status != SL_STATUS_OK) { + return status; + } + sl_si91x_gpio_set_pin_direction(pin_config.port_pin.port, + pin_config.port_pin.pin, + (sl_si91x_gpio_direction_t)pin_config.direction); + } + // Check if the GPIO port is the Ultra-Ultra Low Power GPIO port. + if (pin_config.port_pin.port == SL_GPIO_UULP_PORT) { + // Enable uulp pad receiver for the pin. + status = sl_si91x_gpio_driver_select_uulp_npss_receiver(pin_config.port_pin.pin, SET); + if (status != SL_STATUS_OK) { + return status; + } + // Set uulp pin mode for the pin. By default mode 0 is set, which is a normal GPIO + status = sl_si91x_gpio_driver_set_uulp_npss_pin_mux(pin_config.port_pin.pin, + (sl_si91x_uulp_npss_mode_t)NPSS_GPIO_PIN_MUX_MODE0); + if (status != SL_STATUS_OK) { + return status; + } + sl_si91x_gpio_set_uulp_npss_direction(pin_config.port_pin.pin, (sl_si91x_gpio_direction_t)pin_config.direction); + } + return SL_STATUS_OK; +} + +/******************************************************************************* + * @brief This API is used to configure the pin interrupt in 3 instance. + * To configure the interrupt, first GPIO initialization must be done. + * The actions to be performed in GPIO initialization are: + * - Enable the M4/ULP clock based on GPIO instance. + * - Select PAD selection for GPIO instance. + * - Enable PAD receiver for GPIO pin number, whether GPIO pin is selected as + * output/input. + * - Set pin mode and direction of the GPIO pin. + ******************************************************************************/ +sl_status_t sl_gpio_driver_configure_interrupt(sl_gpio_t *gpio, + uint32_t int_no, + sl_gpio_interrupt_flag_t flags, + sl_gpio_irq_callback_t gpio_callback, + uint32_t *avl_intr_no) +{ + sl_status_t status; + (void)avl_intr_no; + // Check if gpio pointer and gpio_callback pointer is NULL + if ((gpio == NULL) || (gpio_callback == NULL)) { + // Return error code for NULL pointer + return SL_STATUS_NULL_POINTER; + } + // Check if flags exceed maximum allowed value + if (flags > GPIO_FLAGS_MAX_VALUE) { + // Return error code for invalid parameter + return SL_STATUS_INVALID_PARAMETER; + } + status = sl_gpio_validation(gpio); + if (status != SL_STATUS_OK) { + return status; + } + switch (gpio->port) { + case SL_GPIO_PORT_A: + case SL_GPIO_PORT_B: + case SL_GPIO_PORT_C: + case SL_GPIO_PORT_D: + // Check if the interrupt number exceeds the maximum allowed value. + if (int_no > GPIO_MAX_INTR_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + // Check if a callback function is already registered for the given interrupt number. + if (gpio_callback_function_pointer[int_no] != NULL) { + return SL_STATUS_BUSY; + } + // Enable the NVIC for the GPIO interrupt and set its priority. + NVIC_EnableIRQ(intr_config.gpio_nvic[int_no]); + NVIC_SetPriority(intr_config.gpio_nvic[int_no], intr_config.gpio_priority[int_no]); + // Assign the callback function pointer for the specified interrupt number. + gpio_callback_function_pointer[int_no] = gpio_callback; + // Configure the GPIO interrupt. + sl_gpio_configure_interrupt(gpio->port, gpio->pin, int_no, flags); + break; + default: + break; + } + // Check if the GPIO port is the Ultra-Low Power GPIO port. + if (gpio->port == SL_GPIO_ULP_PORT) { + // Check if the GPIO pin or interrupt number exceeds the maximum allowed values. + if (int_no > GPIO_ULP_INTERRUPT_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + // Check if a callback function is already registered for the given Ultra-Low Power GPIO interrupt number. + if (gpio_ulp_pin_int_callback_fptr[int_no] != NULL) { + return SL_STATUS_BUSY; + } + // Enable the NVIC for the Ultra-Low Power GPIO pin interrupt and set its priority. + NVIC_EnableIRQ(ULP_PININT0_NVIC_NAME); + NVIC_SetPriority(ULP_PININT0_NVIC_NAME, ULP_GPIO_INTERRUPT_PRIORITY); + // Assign the callback function pointer for the specified Ultra-Low Power GPIO interrupt number. + gpio_ulp_pin_int_callback_fptr[int_no] = gpio_callback; + // Configure the Ultra-Low Power GPIO pin interrupt. + sl_si91x_gpio_configure_ulp_pin_interrupt((uint8_t)int_no, (sl_si91x_gpio_interrupt_config_flag_t)flags, gpio->pin); + } + // Check if the GPIO port is the Ultra-Ultra Low Power GPIO port. + if (gpio->port == SL_GPIO_UULP_PORT) { + // Check if the GPIO pin or interrupt number exceeds the maximum allowed values. + if (int_no > GPIO_NPSS_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + // Check if a callback function is already registered for the given Ultra-Ultra Low Power GPIO interrupt number. + if (gpio_uulp_pin_int_callback_fptr[int_no] != NULL) { + return SL_STATUS_BUSY; + } + // Assign the callback function pointer for the specified Ultra-Ultra Low Power GPIO interrupt number. + gpio_uulp_pin_int_callback_fptr[int_no] = gpio_callback; + // Configure the Ultra-Ultra Low Power GPIO interrupt. + sl_si91x_gpio_configure_uulp_interrupt((sl_si91x_gpio_interrupt_config_flag_t)flags, (uint8_t)int_no); + } + return SL_STATUS_OK; +} + +/******************************************************************************* + * @brief This API is used to configure the group interrupts in 3 instance. + * To configure the interrupt, first GPIO initialization must be done. + * The actions to be performed in GPIO initialization are: + * - Enable the M4/ULP clock based on GPIO instance. + * - Select PAD selection for GPIO instance. + * - Enable PAD receiver for GPIO pin number, whether GPIO pin is selected as + * output/input. + * - Set pin mode and direction of the GPIO pin. + ******************************************************************************/ +sl_status_t sl_gpio_configure_group_interrupt(sl_si91x_gpio_group_interrupt_config_t *configuration, + sl_gpio_irq_callback_t gpio_callback) +{ + // Check if configuration pointer and gpio_callback pointer is NULL. + if ((configuration == NULL) || (gpio_callback == NULL)) { + // Return error code for NULL pointer + return SL_STATUS_NULL_POINTER; + } + for (uint8_t i = 0; i < configuration->grp_interrupt_cnt; i++) { + switch (configuration->grp_interrupt_port[i]) { + case SL_GPIO_PORT_A: + case SL_GPIO_PORT_B: + case SL_GPIO_PORT_C: + case SL_GPIO_PORT_D: + // Check if a callback function is already registered for the given GPIO interrupt number. + if (gpio_group_int_callback_fptr[configuration->grp_interrupt] != NULL) { + return SL_STATUS_BUSY; + } + // Assign the callback function pointer for the specified GPIO interrupt number. + gpio_group_int_callback_fptr[configuration->grp_interrupt] = gpio_callback; + // Configure the GPIO group interrupt. + sl_si91x_gpio_configure_group_interrupt(configuration); + break; + default: + break; + } + if (configuration->grp_interrupt_port[i] == SL_GPIO_ULP_PORT) { + // Check if a callback function is already registered for the given GPIO interrupt number. + if (gpio_ulp_group_int_callback_fptr[configuration->grp_interrupt] != NULL) { + return SL_STATUS_BUSY; + } + // Assign the callback function pointer for the specified ULP GPIO interrupt number. + gpio_ulp_group_int_callback_fptr[configuration->grp_interrupt] = gpio_callback; + // Configure the GPIO ULP group interrupt. + sl_si91x_gpio_configure_ulp_group_interrupt(configuration); + } + } + return SL_STATUS_OK; +} + +/******************************************************************************* + * @brief This API is used for GPIO HP, ULP instances to set pin mode. + * - If GPIO HP instance is considered, the following actions are performed: + * - To set the pin mode in GPIO HP instance, GPIO initialization needs to + * be done first. + * - The actions to be performed in GPIO initialization are: + * - Enable the M4 clock of GPIO HP instance. + * - Select PAD selection of the GPIO HP instance. + * - Enable PAD receiver for GPIO pin number, whether GPIO pin is + * selected as output/input. + * @note: Select HP GPIO pins for HP instances(6 to 57). Do not use + * GPIO pin number(0 to 5) in HP instance as these are used for other + * functionality. + * - If GPIO ULP instance is considered, the following actions are performed: + * - To set the pin mode in GPIO ULP instance, GPIO initialization needs to + * be done first. + * - The actions to be performed in GPIO initialization are: + * - Enable the ULP clock of GPIO ULP instance. + * - Enable ULP PAD receiver for GPIO pin number, whether GPIO pin is + * selected as output/input. + * @note: Select ULP GPIO pins for ULP instances(0 to 11). + ******************************************************************************/ +sl_status_t sl_gpio_driver_set_pin_mode(sl_gpio_t *gpio, sl_gpio_mode_t mode, uint32_t output_value) +{ + sl_status_t status; + // Check if the GPIO pointer is NULL. + if (gpio == NULL) { + return SL_STATUS_NULL_POINTER; + } + status = sl_gpio_validation(gpio); + if (status != SL_STATUS_OK) { + return status; + } + // Check if the mode or output value exceeds the maximum allowed values. + if ((mode > MAX_MODE) || (output_value > GPIO_MAX_OUTPUT_VALUE)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Set the mode for the GPIO pin. + sl_gpio_set_pin_mode(gpio->port, gpio->pin, mode, output_value); + return SL_STATUS_OK; +} + +/******************************************************************************* + * @brief This API is used for GPIO HP, ULP instances to get pin mode. + * - If GPIO HP instance is considered, the following actions are performed: + * - To get the pin status in GPIO HP instance, GPIO initialization needs + * to be done first. + * - The actions to be performed in GPIO initialization are: + * - Enable the M4 clock of GPIO HP instance. + * - Select PAD selection of the GPIO HP instance. + * - Enable PAD receiver for GPIO pin number, whether GPIO pin is + * selected as output/input. + * - Set pin mode and direction of the GPIO pin. + * - Get the pin mode of GPIO pin. + * @note: Select HP GPIO pins for HP instances(6 to 57). Do not + * use GPIO pin number(0 to 5) in HP instance as these are used for other + * functionality. + * - If GPIO ULP instance is considered, the following actions are + * performed: + * - To get the pin mode in GPIO ULP instance, GPIO initialization needs + * to be done first. + * - The actions to be performed in GPIO initialization are: + * - Enable the ULP clock of GPIO ULP instance. + * - Enable ULP PAD receiver for GPIO pin number, whether GPIO pin is + * selected as output/input. + * - Set pin mode and direction of the GPIO pin. + * - Get the pin mode of GPIO pin. + * @note: Select ULP GPIO pins for ULP instances(ULP_GPIO_0 to + * ULP_GPIO_11). + ******************************************************************************/ +sl_status_t sl_gpio_driver_get_pin_mode(sl_gpio_t *gpio, sl_gpio_mode_t *mode) +{ + sl_status_t status; + // Check if the GPIO pointer and mode pointer is NULL. + if ((gpio == NULL) || (mode == NULL)) { + return SL_STATUS_NULL_POINTER; + } + status = sl_gpio_validation(gpio); + if (status != SL_STATUS_OK) { + return status; + } + // Get the mode for the GPIO pin. + *mode = sl_gpio_get_pin_mode(gpio->port, gpio->pin); + return SL_STATUS_OK; +} + +/******************************************************************************* + * Initialization of GPIO driver. + ******************************************************************************/ +sl_status_t sl_gpio_driver_init(void) +{ + uint32_t flag; + sl_status_t status; + GPIO_NPSS_GPIO_CONFIG_REG = CLR; //By default making all the interrupts zero. + for (flag = 0; flag < GPIO_MAX_INTR_VALUE; flag++) { + sl_gpio_driver_clear_interrupts(flag); + gpio_callback_function_pointer[flag] = NULL; + } + for (flag = 0; flag < MAX_GROUP_INT; flag++) { + sl_si91x_gpio_driver_clear_group_interrupt(flag); + gpio_group_int_callback_fptr[flag] = NULL; + } + for (flag = 0; flag < MAX_UULP_INT; flag++) { + sl_si91x_gpio_driver_clear_uulp_interrupt((uint8_t)flag); + gpio_uulp_pin_int_callback_fptr[flag] = NULL; + } + for (flag = 0; flag < GPIO_MAX_INTR_VALUE; flag++) { + sl_si91x_gpio_driver_clear_ulp_interrupt((uint8_t)flag); + gpio_ulp_pin_int_callback_fptr[flag] = NULL; + } + for (flag = 0; flag < MAX_GROUP_INT; flag++) { + sl_si91x_gpio_driver_clear_ulp_group_interrupt(flag); + gpio_ulp_group_int_callback_fptr[flag] = NULL; + } + status = sl_si91x_gpio_driver_enable_clock((sl_si91x_gpio_select_clock_t)M4CLK_GPIO); // Enable GPIO M4_CLK + if (status != SL_STATUS_OK) { + return status; + } + status = sl_si91x_gpio_driver_enable_clock((sl_si91x_gpio_select_clock_t)ULPCLK_GPIO); // Enable GPIO ULP_CLK + if (status != SL_STATUS_OK) { + return status; + } + return SL_STATUS_OK; +} + +/******************************************************************************* +* Get the release, SQA, and development version numbers of the GPIO peripheral. +*******************************************************************************/ +sl_si91x_gpio_version_t sl_si91x_gpio_driver_get_version(void) +{ + sl_si91x_gpio_version_t version; + version = sl_si91x_gpio_get_version(); + return version; +} + +/******************************************************************************* + * Indicate UULP GPIO PAD configuration. + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_set_uulp_pad_configuration(uulp_pad_config_t *pad_config) +{ + // Check if the pad configuration pointer is NULL. + if (pad_config == NULL) { + return SL_STATUS_NULL_POINTER; + } + // Set the UULP pad configuration. + sl_si91x_gpio_set_uulp_pad_configuration(pad_config); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instances to set pin direction. + * - If GPIO HP instance is considered, the following actions are performed: + * - To set the pin direction in GPIO HP instance, GPIO initialization + * needs to be done first. + * - The actions to be performed in GPIO initialization are: + * - Enable the M4 clock of GPIO HP instance. + * - Select PAD selection of the GPIO HP instance. + * - Enable PAD receiver for GPIO pin number, whether GPIO pin is + * selected as output/input. + * - Set pin mode and direction of the GPIO pin. + * @note: Select HP GPIO pins for HP instances(6 to 57). Do not + * use GPIO pin number(0 to 5) in HP instance as these are used for other + * functionality. + * - If GPIO ULP instance is considered, the following actions are + * performed: + * - To set the pin direction in GPIO ULP instance, GPIO initialization + * needs to be done first. + * - The actions to be performed in GPIO initialization are: + * - Enable the ULP clock of GPIO ULP instance. + * - Enable ULP PAD receiver for GPIO pin number, whether GPIO pin is + * selected as output/input. + * - Set pin mode and direction of the GPIO pin. + * @note: Select ULP GPIO pins for ULP instances(0 to 11). + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_set_pin_direction(uint8_t port, uint8_t pin, sl_si91x_gpio_direction_t direction) +{ + // Check if the GPIO port and direction exceeds the maximum allowed value. Returns an invalid parameter if true + if ((port > GPIO_PORT_MAX_VALUE) || (direction > GPIO_DIRECTION_MAX_VALUE)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Checks if the port is Port A. If true, checks if the pin value exceeds + // the maximum allowable value for Port A. Returns an invalid parameter status code if true + if (port == SL_GPIO_PORT_A) { + if (pin > PORTA_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Checks if the port is either Port B or Port C. If true, checks if the pin value exceeds + // the maximum allowable value for these ports. Returns an invalid parameter status code if true. + if ((port == SL_GPIO_PORT_B) || (port == SL_GPIO_PORT_C)) { + if (pin > PORT_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Checks if the port is Port D. If true, checks if the pin value exceeds the maximum allowable + // value for Port D. Returns an invalid parameter status code if true. + if (port == SL_GPIO_PORT_D) { + if (pin > PORTD_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Check if the GPIO port is the Ultra-Low Power GPIO port and if the pin exceeds the maximum allowed values. + if (port == SL_GPIO_ULP_PORT) { + if (pin > ULP_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Check if the GPIO port is the Ultra Ultra-Low Power GPIO port and if the pin exceeds the maximum allowed values. + if (port == SL_GPIO_UULP_PORT) { + if (pin > UULP_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Set GPIO pin direction + sl_si91x_gpio_set_pin_direction(port, pin, direction); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instances to get pin direction. + * - If GPIO HP instance is considered, the following actions are performed: + * - To get the pin direction in GPIO HP instance, GPIO initialization + * needs to be done first. + * - The actions to be performed in GPIO initialization are: + * - Enable the M4 clock of GPIO HP instance. + * - Select PAD selection of the GPIO HP instance. + * - Enable PAD receiver for GPIO pin number, whether GPIO pin is + * selected as output/input. + * - Set pin mode and direction of the GPIO pin. + * - Get the pin direction of the GPIO pin. + * @note: Select HP GPIO pins for HP instances(6 to 57). Do not + * use GPIO pin number(0 to 5) in HP instance as these are used for other + * functionality. + * - If GPIO ULP instance is considered, the following actions are + * performed: + * - To get the pin direction in GPIO ULP instance, GPIO initialization + * needs to be done first. + * - The actions to be performed in GPIO initialization are: + * - Enable the ULP clock of GPIO ULP instance. + * - Enable ULP PAD receiver for GPIO pin number, whether GPIO pin is + * selected as output/input. + * - Set pin mode and direction of the GPIO pin. + * - Get the pin direction of the GPIO pin. + * @note: Select ULP GPIO pins for ULP instances(0 to 11). + ******************************************************************************/ +uint8_t sl_si91x_gpio_driver_get_pin_direction(uint8_t port, uint8_t pin) +{ + uint8_t direction; + // Check if the GPIO port exceeds the maximum allowed value. Returns an invalid parameter if true + if (port > GPIO_PORT_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + // Checks if the port is Port A. If true, checks if the pin value exceeds + // the maximum allowable value for Port A. Returns an invalid parameter status code if true + if (port == SL_GPIO_PORT_A) { + if (pin > PORTA_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Checks if the port is either Port B or Port C. If true, checks if the pin value exceeds + // the maximum allowable value for these ports. Returns an invalid parameter status code if true. + if ((port == SL_GPIO_PORT_B) || (port == SL_GPIO_PORT_C)) { + if (pin > PORT_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Checks if the port is Port D. If true, checks if the pin value exceeds the maximum allowable + // value for Port D. Returns an invalid parameter status code if true. + if (port == SL_GPIO_PORT_D) { + if (pin > PORTD_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Check if the GPIO port is the Ultra-Low Power GPIO port and if the pin exceeds the maximum allowed values. + if (port == SL_GPIO_ULP_PORT) { + if (pin > ULP_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Get pin direction for GPIO pin + direction = sl_si91x_gpio_get_pin_direction(port, pin); + return direction; +} + +/******************************************************************************* + * This API is used to enable PAD receiver in GPIO HP instance. + * The actions to be performed for enabling PAD are: + * - Enable the M4 clock of GPIO HP instance. + * - Select PAD selection of the GPIO HP instance. + * - Enable PAD receiver for GPIO pin number, whether GPIO pin is + * selected as output/input. + * @note: Select HP GPIO pins for HP instances(6 to 57). Do not + * use GPIO pin number(0 to 5) in HP instance as these are used for other + * functionality. + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_enable_pad_receiver(uint8_t gpio_num) +{ + // Check if the GPIO pin number exceeds the maximum allowed value. + if (gpio_num > GPIO_MAX_PIN_NUM) { + return SL_STATUS_INVALID_PARAMETER; + } + // Enable the pad receiver for the GPIO pin. + sl_si91x_gpio_enable_pad_receiver(gpio_num); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used to disable PAD receiver in GPIO HP instance. + * The actions to be performed for disabling PAD are: + * - Enable the M4 clock of GPIO HP instance. + * - Select PAD selection of the GPIO HP instance. + * - Disable PAD receiver for GPIO pin number, whether GPIO pin is + * selected as output/input. + * @note: Select HP GPIO pins for HP instances(6 to 57). Do not + * use GPIO pin number(0 to 5) in HP instance as these are used for other + * functionality. + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_disable_pad_receiver(uint8_t gpio_num) +{ + // Check if the GPIO pin number exceeds the maximum allowed value. + if (gpio_num > GPIO_MAX_PIN_NUM) { + return SL_STATUS_INVALID_PARAMETER; + } + // Disable the pad receiver for the GPIO pin. + sl_si91x_gpio_disable_pad_receiver(gpio_num); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used to enable PAD selection in GPIO HP instance. + * The actions to be performed for enable PAD selection are: + * - Enable the M4 clock of GPIO HP instance. + * - Select PAD selection of the GPIO HP instance. + * @note: PAD number(25 to 30) are used for HOST PAD selection. + * Do not use PAD number-9 as it is used for other functionality. + * @note: Select HP GPIO pins for HP instances(GPIO_6 to GPIO_57). Do not + * use GPIO pin number(0 to 5) in HP instance as these are used for other + * functionality. + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_enable_pad_selection(uint8_t gpio_padnum) +{ + // Check if the GPIO pad number exceeds the maximum allowed value. + if (gpio_padnum > GPIO_MAX_PAD_NUM) { + return SL_STATUS_INVALID_PARAMETER; + } + // Enable pad selection for the GPIO pad. + sl_si91x_gpio_enable_pad_selection(gpio_padnum); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used to enable HOST PAD selection in GPIO HP instance. + * @note: GPIO pin number(25 to 30) are used for HOST PAD selection. + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_enable_host_pad_selection(uint8_t gpio_num) +{ + // Check if the GPIO pin number exceeds the maximum allowed value. + if (gpio_num >= HOST_PAD_MIN && gpio_num <= HOST_PAD_MAX) { + return SL_STATUS_INVALID_PARAMETER; + } + // Enable host pad selection for the GPIO pin. + sl_si91x_gpio_enable_host_pad_selection(gpio_num); + return SL_STATUS_OK; +} + +/******************************************************************************* + * To select the PAD driver strength in GPIO HP instance, GPIO + *initialization needs to be done first. + * - The actions to be performed in GPIO initialization are: + * - Enable the M4 clock of GPIO HP instance. + * - Select PAD selection of the GPIO HP instance. + * - Enable PAD receiver for GPIO pin number, whether GPIO pin is + * selected as output/input. + * - Set pin mode and direction of the GPIO pin. + * - Select the PAD driver strength of type @ref + * sl_si91x_gpio_driver_strength_select_t. + * @note: Select HP GPIO pins for HP instances(6 to 57). Do not + * use GPIO pin number(0 to 5) in HP instance as these are used for other + * functionality. + ******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_select_pad_driver_strength(uint8_t gpio_num, + sl_si91x_gpio_driver_strength_select_t strength) +{ + // Check if GPIO pin number or strength value exceeds the maximum allowed. + if ((gpio_num > GPIO_MAX_PIN_NUM) || (strength > GPIO_STRENGTH_MAX_VAL)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Select the pad driver strength for the GPIO pin. + sl_si91x_gpio_select_pad_driver_strength(gpio_num, strength); + return SL_STATUS_OK; +} + +/******************************************************************************* + * To select the PAD driver disable state in GPIO HP instance, GPIO + *initialization needs to be done first. + * - The actions to be performed in GPIO initialization are: + * - Enable the M4 clock of GPIO HP instance. + * - Select PAD selection of the GPIO HP instance. + * - Enable PAD receiver for GPIO pin number, whether GPIO pin is + * selected as output/input. + * - Set pin mode and direction of the GPIO pin. + * - Select the PAD driver disable state of type @ref + * sl_si91x_gpio_driver_disable_state_t. + * @note: Select HP GPIO pins for HP instances(6 to 57). Do not + * use GPIO pin number(0 to 5) in HP instance as these are used for other + * functionality. + ******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_select_pad_driver_disable_state(uint8_t gpio_num, + sl_si91x_gpio_driver_disable_state_t disable_state) +{ + // Check if GPIO pin number or disable state value exceeds the maximum allowed. + if ((gpio_num > GPIO_MAX_PIN_NUM) || (disable_state > GPIO_DISABLE_STATE_MAX_VAL)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Select the pad driver disable state for the GPIO pin. + sl_si91x_gpio_select_pad_driver_disable_state(gpio_num, disable_state); + return SL_STATUS_OK; +} + +/******************************************************************************* + * The GPIO pins to work in different instances, requires this clock. + * For GPIO HP instance, enable M4 clock of type @ref + * sl_si91x_gpio_select_clock_t. For GPIO ULP/UULP instances, enable ULP + * clock of type + * @ref sl_si91x_gpio_select_clock_t + ******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_enable_clock(sl_si91x_gpio_select_clock_t clock) +{ + // Check if clock value exceeds the maximum allowed. + if (clock > GPIO_CLOCK_MAX_VAL) { + return SL_STATUS_INVALID_PARAMETER; + } + // Enable the clock. + sl_si91x_gpio_enable_clock(clock); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API disables the M4/ ULP clock of GPIO instances. + * For GPIO HP instance, disable M4 clock of type @ref + * sl_si91x_gpio_select_clock_t. For GPIO ULP/UULP instances, disable ULP + * clock of type + * @ref sl_si91x_gpio_select_clock_t + ******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_disable_clock(sl_si91x_gpio_select_clock_t clock) +{ + // Check if clock value exceeds the maximum allowed. + if (clock > GPIO_CLOCK_MAX_VAL) { + return SL_STATUS_INVALID_PARAMETER; + } + // Disable the clock. + sl_si91x_gpio_disable_clock(clock); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instances. + * It is used to enable the group interrupts. + * @note: We are calling this API, inside the group interrupt + * configuration API's + * @ref sl_si91x_gpio_driver_configure_group_interrupt(), used for HP + * instance, + * @ref sl_si91x_gpio_driver_configure_ulp_group_interrupt(), used for ULP + * instance. + * @note: Select HP GPIO pins for HP instances(6 to 57). Do not + * use GPIO pin number(0 to 5) in HP instance as these are used for other + * functionality. + * @note: Select ULP GPIO pins for ULP instances(0 to 11). + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_enable_group_interrupt(sl_si91x_group_interrupt_t group_interrupt, + uint8_t port, + uint8_t pin) +{ + // Check if group interrupt or port value exceeds the maximum allowed. + if ((group_interrupt > GPIO_GROUP_INTERRUPT_MAX_VALUE) || (port > GPIO_PORT_MAX_VALUE)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Checks if the port is Port A. If true, checks if the pin value exceeds + // the maximum allowable value for Port A. Returns an invalid parameter status code if true + if (port == SL_GPIO_PORT_A) { + if (pin > PORTA_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Checks if the port is either Port B or Port C. If true, checks if the pin value exceeds + // the maximum allowable value for these ports. Returns an invalid parameter status code if true. + if ((port == SL_GPIO_PORT_B) || (port == SL_GPIO_PORT_C)) { + if (pin > PORT_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Checks if the port is Port D. If true, checks if the pin value exceeds the maximum allowable + // value for Port D. Returns an invalid parameter status code if true. + if (port == SL_GPIO_PORT_D) { + if (pin > PORTD_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Check if the GPIO port is the Ultra-Low Power GPIO port and if the pin exceeds the maximum allowed values. + if (port == SL_GPIO_ULP_PORT) { + if (pin > ULP_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Enable GPIO group interrupt for selected GPIO port pin + sl_si91x_gpio_enable_group_interrupt(group_interrupt, port, pin); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instances. + * It is used to disable the group interrupts. + * @note: Select HP GPIO pins for HP instances(6 to 57). Do not + * use GPIO pin number(0 to 5) in HP instance as these are used for other + * functionality. + * @note: Select ULP GPIO pins for ULP instances(0 to 11). + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_disable_group_interrupt(sl_si91x_group_interrupt_t group_interrupt, + uint8_t port, + uint8_t pin) +{ + // Check if group interrupt or port value exceeds the maximum allowed. + if ((group_interrupt > GPIO_GROUP_INTERRUPT_MAX_VALUE) || (port > GPIO_PORT_MAX_VALUE)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Checks if the port is Port A. If true, checks if the pin value exceeds + // the maximum allowable value for Port A. Returns an invalid parameter status code if true + if (port == SL_GPIO_PORT_A) { + if (pin > PORTA_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Checks if the port is either Port B or Port C. If true, checks if the pin value exceeds + // the maximum allowable value for these ports. Returns an invalid parameter status code if true. + if ((port == SL_GPIO_PORT_B) || (port == SL_GPIO_PORT_C)) { + if (pin > PORT_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Checks if the port is Port D. If true, checks if the pin value exceeds the maximum allowable + // value for Port D. Returns an invalid parameter status code if true. + if (port == SL_GPIO_PORT_D) { + if (pin > PORTD_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Check if the GPIO port is the Ultra-Low Power GPIO port and if the pin exceeds the maximum allowed values. + if (port == SL_GPIO_ULP_PORT) { + if (pin > ULP_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Disable GPIO group interrupt for selected GPIO port pin + sl_si91x_gpio_disable_group_interrupt(group_interrupt, port, pin); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instances. + * It is used to mask the group interrupts. + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_mask_group_interrupt(uint8_t port, sl_si91x_group_interrupt_t group_interrupt) +{ + // Check if group interrupt or port value exceeds the maximum allowed. + if ((port > GPIO_PORT_MAX_VALUE) || (group_interrupt > GPIO_GROUP_INTERRUPT_MAX_VALUE)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Mask group interrupt for port + sl_si91x_gpio_mask_group_interrupt(port, group_interrupt); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instances. + * It is used to unmask the group interrupts. + * @note: We are calling this API, inside the group interrupt + * configuration API's + * @ref sl_si91x_gpio_driver_configure_group_interrupt(), used for HP + * instance, + * @ref sl_si91x_gpio_driver_configure_ulp_group_interrupt(), used for ULP + * instance. + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_unmask_group_interrupt(uint8_t port, sl_si91x_group_interrupt_t group_interrupt) +{ + // Check if group interrupt or port value exceeds the maximum allowed. + if ((port > GPIO_PORT_MAX_VALUE) || (group_interrupt > GPIO_GROUP_INTERRUPT_MAX_VALUE)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Unmask group interrupt for port + sl_si91x_gpio_unmask_group_interrupt(port, group_interrupt); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instances. + * It is used to set level/edge event of group interrupt. + * @note: We are calling this API, inside the group interrupt + * configuration API's + * @ref sl_si91x_gpio_driver_configure_group_interrupt(), used for HP + * instance, + * @ref sl_si91x_gpio_driver_configure_ulp_group_interrupt(), used for ULP + * instance. + ******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_set_group_interrupt_level_edge(uint8_t port, + sl_si91x_group_interrupt_t group_interrupt, + sl_si91x_gpio_level_edge_t level_edge) +{ + // Check if group interrupt or port value or level edge exceeds the maximum allowed. + if ((port > GPIO_PORT_MAX_VALUE) || (group_interrupt > GPIO_GROUP_INTERRUPT_MAX_VALUE) + || (level_edge > GPIO_LEVEL_EDGE_MAX_VALUE)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Set group interrupt level/edge event + sl_si91x_gpio_set_group_interrupt_level_edge(port, group_interrupt, level_edge); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instances. + * It is used to get level/edge event of group interrupt. + ******************************************************************************/ +uint8_t sl_si91x_gpio_driver_get_group_interrupt_level_edge(uint8_t port, sl_si91x_group_interrupt_t group_interrupt) +{ + // Check if group interrupt or port value exceeds the maximum allowed. + uint8_t level_edge; + if ((port > GPIO_PORT_MAX_VALUE) || (group_interrupt > GPIO_GROUP_INTERRUPT_MAX_VALUE)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Get group interrupt level/edge event + level_edge = sl_si91x_gpio_get_group_interrupt_level_edge(port, group_interrupt); + return level_edge; +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instances. + * It is used to set polarity of group interrupt. + * @note: We are calling this API, inside the group interrupt + * configuration API's + * @ref sl_si91x_gpio_driver_configure_group_interrupt(), used for HP + * instance, + * @ref sl_si91x_gpio_driver_configure_ulp_group_interrupt(), used for ULP + * instance. + * @note: Select HP GPIO pins for HP instances(6 to 57). Do not + * use GPIO pin number(0 to 5) in HP instance as these are used for other + * functionality. + * @note: Select ULP GPIO pins for ULP instances(0 to 11). + ******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_set_group_interrupt_polarity(sl_si91x_group_interrupt_t group_interrupt, + uint8_t port, + uint8_t pin, + sl_si91x_gpio_polarity_t polarity) +{ + // Check if group interrupt or port value or polarity exceeds the maximum allowed. + if ((group_interrupt > GPIO_GROUP_INTERRUPT_MAX_VALUE) || (polarity > GPIO_POLARITY_MAX_VALUE) + || (port > GPIO_PORT_MAX_VALUE)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Checks if the port is Port A. If true, checks if the pin value exceeds + // the maximum allowable value for Port A. Returns an invalid parameter status code if true + if (port == SL_GPIO_PORT_A) { + if (pin > PORTA_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Checks if the port is either Port B or Port C. If true, checks if the pin value exceeds + // the maximum allowable value for these ports. Returns an invalid parameter status code if true. + if ((port == SL_GPIO_PORT_B) || (port == SL_GPIO_PORT_C)) { + if (pin > PORT_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Checks if the port is Port D. If true, checks if the pin value exceeds the maximum allowable + // value for Port D. Returns an invalid parameter status code if true. + if (port == SL_GPIO_PORT_D) { + if (pin > PORTD_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Check if the GPIO port is the Ultra-Low Power GPIO port and if the pin exceeds the maximum allowed values. + if (port == SL_GPIO_ULP_PORT) { + if (pin > ULP_PIN_MAX_VALUE) { + // Returns invalid parameter status code if pin > ULP_PIN_MAX_VALUE + return SL_STATUS_INVALID_PARAMETER; + } + } + // Set group interrupt polarity for GPIO port pin + sl_si91x_gpio_set_group_interrupt_polarity(group_interrupt, port, pin, polarity); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instances. + * It is used to get polarity of group interrupt . + * @note: Select HP GPIO pins for HP instances(6 to 57). Do not use + * GPIO pin number(0 to 5) in HP instance as these are used for other functionality. + * @note: Select ULP GPIO pins for ULP instances(0 to 11). + ******************************************************************************/ +uint8_t sl_si91x_gpio_driver_get_group_interrupt_polarity(sl_si91x_group_interrupt_t group_interrupt, + uint8_t port, + uint8_t pin) +{ + uint8_t polarity = 0; + // Check if group interrupt or port value exceeds the maximum allowed. + if ((group_interrupt > GPIO_GROUP_INTERRUPT_MAX_VALUE) || (port > GPIO_PORT_MAX_VALUE)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Checks if the port is Port A. If true, checks if the pin value exceeds + // the maximum allowable value for Port A. Returns an invalid parameter status code if true + if (port == SL_GPIO_PORT_A) { + if (pin > PORTA_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Checks if the port is either Port B or Port C. If true, checks if the pin value exceeds + // the maximum allowable value for these ports. Returns an invalid parameter status code if true. + if ((port == SL_GPIO_PORT_B) || (port == SL_GPIO_PORT_C)) { + if (pin > PORT_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Checks if the port is Port D. If true, checks if the pin value exceeds the maximum allowable + // value for Port D. Returns an invalid parameter status code if true. + if (port == SL_GPIO_PORT_D) { + if (pin > PORTD_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Check if the GPIO port is the Ultra-Low Power GPIO port and if the pin exceeds the maximum allowed values. + if (port == SL_GPIO_ULP_PORT) { + if (pin > ULP_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Get group interrupt polarity for GPIO port pin + polarity = sl_si91x_gpio_get_group_interrupt_polarity(group_interrupt, port, pin); + return polarity; +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instances. + * It is used to select and/or event of group interrupt. + * @example: Consider two GPIO pins for group interrupts. + * - If AND event is selected then both GPIO pins, interrupt should be + * generated to do specific task. + * - If OR event is selected then any one GPIO pin, interrupt + * generation should be enough to do specific task. + * @note: We are calling this API, inside the group interrupt + * configuration API's + * @ref sl_si91x_gpio_driver_configure_group_interrupt(), used for HP + * instance, + * @ref sl_si91x_gpio_driver_configure_ulp_group_interrupt(), used for ULP + * instance. + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_select_group_interrupt_and_or(uint8_t port, + sl_si91x_group_interrupt_t group_interrupt, + sl_si91x_gpio_and_or_t and_or) +{ + // Check if group interrupt or port value or and_or exceeds the maximum allowed. + if ((port > GPIO_PORT_MAX_VALUE) || (group_interrupt > GPIO_GROUP_INTERRUPT_MAX_VALUE) + || (and_or > GPIO_AND_OR_MAX_VALUE)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Select group interrupt AND/OR event + sl_si91x_gpio_select_group_interrupt_and_or(port, group_interrupt, and_or); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used in GPIO HP instance to configure group interrupts. + * It has configuration pointer of type @ref + * sl_si91x_gpio_group_interrupt_config_t structure. GPIO HP instance has + * total 4 ports. Port-A, B, C has 16 pins each. Port-D has 9 pins. While + * configuring group interrupts, one can select random ports and pins for + * group interrupt. + * @example 1: + * - If port 1 is selected, any group of pins(0 to 16) can be selected for + * group interrupt. + * - Same applied for other ports also. + * @example 2: + * - Once can select port B, pin 7 and port C, pin 3 as a group for + * interrupt generation. + * - One should assign group count of how many pins are passed. + * For more clarification look into group interrupt configuration + * structure + * @ref sl_si91x_gpio_driver_group_interrupt_config_t. + * @note: Do not use Port A, GPIO pin number(0 to 5) in HP instance + * as these are used for other functionality. + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_configure_group_interrupt(sl_si91x_gpio_group_interrupt_config_t *configuration, + sl_gpio_irq_callback_t gpio_callback) +{ + // Check if configuration pointer and gpio_callback pointer is NULL. + if ((configuration == NULL) || (gpio_callback == NULL)) { + // Return error code for NULL pointer + return SL_STATUS_NULL_POINTER; + } + // Check if a callback function is already registered for the given GPIO interrupt number. + if (gpio_group_int_callback_fptr[configuration->grp_interrupt] != NULL) { + return SL_STATUS_BUSY; + } + // Assign the callback function pointer for the specified GPIO interrupt number. + gpio_group_int_callback_fptr[configuration->grp_interrupt] = gpio_callback; + // Configure the GPIO group interrupt. + sl_si91x_gpio_configure_group_interrupt(configuration); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used to configure the pin interrupt in GPIO ULP instance. + * There are total 12 pin interrupts in this instance. + * To configure the interrupt, first ULP GPIO initialization must be done. + * The actions to be performed in ULP GPIO initialization are: + * - Enable the ULP clock of GPIO ULP instance. + * - Enable ULP PAD receiver for GPIO pin number, whether GPIO pin is + * selected as output/input. + * - Set pin mode and direction of the GPIO pin. + * @note: Select ULP GPIO pins for ULP instances(0 to 11). + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_configure_ulp_pin_interrupt(uint8_t int_no, + sl_si91x_gpio_interrupt_config_flag_t flags, + sl_si91x_gpio_pin_ulp_t pin, + sl_gpio_irq_callback_t gpio_callback) +{ + // Check if gpio_callback pointer is NULL. + if (gpio_callback == NULL) { + // Return error code for NULL pointer + return SL_STATUS_NULL_POINTER; + } + // Check if interrupt number or flags or pin exceeds the maximum allowed. + if ((int_no > GPIO_ULP_INTERRUPT_MAX_VALUE) || (flags > GPIO_FLAGS_MAX_VALUE) || (pin > ULP_PIN_MAX_VALUE)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Check if a callback function is already registered for the given GPIO interrupt number. + if (gpio_ulp_pin_int_callback_fptr[int_no] != NULL) { + return SL_STATUS_BUSY; + } + // Enable the NVIC for the GPIO interrupt and set its priority. + NVIC_EnableIRQ(ULP_PININT0_NVIC_NAME); + NVIC_SetPriority(ULP_PININT0_NVIC_NAME, ULP_GPIO_INTERRUPT_PRIORITY); + // Assign the callback function pointer for the specified ULP GPIO interrupt number. + gpio_ulp_pin_int_callback_fptr[int_no] = gpio_callback; + // Configure the GPIO ULP pin interrupt. + sl_si91x_gpio_configure_ulp_pin_interrupt(int_no, flags, pin); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used in GPIO ULP instance to configure group interrupts. + * It has configuration pointer of type @ref + * sl_si91x_gpio_group_interrupt_config_t structure. ULP GPIO domain has + * only one port and calling as Port 4 in program which has maximum of 12 + * pins. While configuring group interrupts, one can select random pins + * which are allocated for ULP port. + * - One should assign group count of how many pins are passed. + * For more clarification look into group interrupt configuration + * structure + * @ref sl_si91x_gpio_group_interrupt_config_t. + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_configure_ulp_group_interrupt(sl_si91x_gpio_group_interrupt_config_t *configuration, + sl_gpio_irq_callback_t gpio_callback) +{ + // Check if configuration pointer and gpio_callback pointer is NULL. + if ((configuration == NULL) || (gpio_callback == NULL)) { + // Return error code for NULL pointer + return SL_STATUS_NULL_POINTER; + } + // Check if a callback function is already registered for the given GPIO interrupt number. + if (gpio_ulp_group_int_callback_fptr[configuration->grp_interrupt] != NULL) { + return SL_STATUS_BUSY; + } + // Assign the callback function pointer for the specified ULP GPIO interrupt number. + gpio_ulp_group_int_callback_fptr[configuration->grp_interrupt] = gpio_callback; + // Configure the GPIO ULP group interrupt. + sl_si91x_gpio_configure_ulp_group_interrupt(configuration); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used for GPIO HP instance. + * It is used to clear group interrupt. + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_clear_group_interrupt(sl_si91x_group_interrupt_t group_interrupt) +{ + // Check if group_interrupt exceeds the maximum allowed. + if (group_interrupt > GPIO_GROUP_INTERRUPT_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + // Clear GPIO group interrupt + sl_si91x_gpio_clear_group_interrupt(group_interrupt); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instance. + * It is used to get status of group interrupt generated. + ******************************************************************************/ +uint32_t sl_si91x_gpio_driver_get_group_interrupt_status(uint8_t port, sl_si91x_group_interrupt_t group_interrupt) +{ + uint32_t status; + // Check if group_interrupt or port exceeds the maximum allowed. + if ((port > GPIO_PORT_MAX_VALUE) || (group_interrupt > GPIO_GROUP_INTERRUPT_MAX_VALUE)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Get GPIO group interrupt status + status = sl_si91x_gpio_get_group_interrupt_status(port, group_interrupt); + return status; +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instance. + * It is used to select group interrupt wakeup. + ******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_select_group_interrupt_wakeup(uint8_t port, + sl_si91x_group_interrupt_t group_interrupt, + sl_si91x_gpio_wakeup_t flags) +{ + // Check if group_interrupt or port exceeds the maximum allowed. + if ((port > GPIO_PORT_MAX_VALUE) || (group_interrupt > GPIO_GROUP_INTERRUPT_MAX_VALUE) + || (flags > GPIO_FLAGS_MAX_VALUE)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Select GPIO group interrupt wakeup + sl_si91x_gpio_select_group_interrupt_wakeup(port, group_interrupt, flags); + return SL_STATUS_OK; +} + +/******************************************************************************* + * To enable ULP PAD receiver in GPIO ULP instance, ULP GPIO + * initialization needs to be done first. + * - The actions to be performed in ULP GPIO initialization are: + * - Enable the ULP clock of GPIO ULP instance. + * - Enable ULP PAD receiver for GPIO pin number, whether GPIO pin is + * selected as output/input. + * @note: Select ULP GPIO pins for ULP instances(ULP_GPIO_0 to + * ULP_GPIO_11). + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_enable_ulp_pad_receiver(uint8_t gpio_num) +{ + // Check if gpio_num exceeds the maximum allowed + if (gpio_num > GPIO_ULP_MAX_PIN_NUM) { + return SL_STATUS_INVALID_PARAMETER; + } + // Enable ULP GPIO pad receiver + sl_si91x_gpio_enable_ulp_pad_receiver(gpio_num); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used to disable the ULP PAD receiver. + * @note: Select ULP GPIO pins for ULP instances(ULP_GPIO_0 to + * ULP_GPIO_11). + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_disable_ulp_pad_receiver(uint8_t gpio_num) +{ + // Check if gpio_num exceeds the maximum allowed + if (gpio_num > GPIO_ULP_MAX_PIN_NUM) { + return SL_STATUS_INVALID_PARAMETER; + } + // Disable ULP GPIO pad receiver + sl_si91x_gpio_disable_ulp_pad_receiver(gpio_num); + return SL_STATUS_OK; +} + +/******************************************************************************* + * To select the ULP PAD driver disable state in GPIO ULP instance, ULP + * GPIO initialization needs to be done first. + * - The actions to be performed in ULP GPIO initialization are: + * - Enable the ULP clock of GPIO ULP instance. + * - Enable ULP PAD receiver for GPIO pin number, whether GPIO pin is + * selected as output/input. + * - Set pin mode and direction of the GPIO pin. + * - Select the PAD driver disable state of type @ref + * sl_si91x_gpio_driver_disable_state_t. + * @note: Select ULP GPIO pins for ULP instances(0 to 11). + ******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_select_ulp_pad_driver_disable_state(uint8_t gpio_num, + sl_si91x_gpio_driver_disable_state_t disable_state) +{ + // Check if gpio_num or disable_state exceeds the maximum allowed + if ((gpio_num > GPIO_ULP_MAX_PIN_NUM) || (disable_state > GPIO_DISABLE_STATE_MAX_VAL)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Select ULP GPIO pad driver disable state + sl_si91x_gpio_select_ulp_pad_driver_disable_state(gpio_num, disable_state); + return SL_STATUS_OK; +} + +/******************************************************************************* + * To select the ULP PAD driver strength in GPIO ULP instance, ULP GPIO + *initialization needs to be done first. + * - The actions to be performed in ULP GPIO initialization are: + * - Enable the ULP clock of GPIO ULP instance. + * - Enable ULP PAD receiver for GPIO pin number, whether GPIO pin is + * selected as output/input. + * - Set pin mode and direction of the GPIO pin. + * - Select the PAD driver strength of type @ref + * sl_si91x_gpio_driver_strength_select_t. + * @note: Select ULP GPIO pins for ULP instances(0 to 11). + ******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_select_ulp_pad_driver_strength(uint8_t gpio_num, + sl_si91x_gpio_driver_strength_select_t strength) +{ + // Check if gpio_num or strength exceeds the maximum allowed + if ((gpio_num > GPIO_ULP_MAX_PIN_NUM) || (strength > GPIO_STRENGTH_MAX_VAL)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Select ULP GPIO pad driver strength + sl_si91x_gpio_select_ulp_pad_driver_strength(gpio_num, strength); + return SL_STATUS_OK; +} + +/******************************************************************************* + * To select the ULP PAD slew rate in GPIO ULP instance, ULP GPIO + * initialization needs to be done first. + * - The actions to be performed in ULP GPIO initialization are: + * - Enable the ULP clock of GPIO ULP instance. + * - Enable ULP PAD receiver for GPIO pin number, whether GPIO pin is + * selected as output/input. + * - Set pin mode and direction of the GPIO pin. + * - Select the PAD slew rate of type @ref sl_si91x_gpio_slew_rate_t. + * @note: Select ULP GPIO pins for ULP instances(0 to 11). + ******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_select_ulp_pad_slew_rate(uint8_t gpio_num, sl_si91x_gpio_slew_rate_t slew_rate) +{ + // Check if gpio_num or slew_rate exceeds the maximum allowed + if ((gpio_num > GPIO_ULP_MAX_PIN_NUM) || (slew_rate > GPIO_SLEW_RATE_MAX_VALUE)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Select ULP GPIO pad slew rate + sl_si91x_gpio_select_ulp_pad_slew_rate(gpio_num, slew_rate); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used to select the UULP mode in NPSS GPIO control register. + * Few actions are required to be performed before setting the mode, + * - Enable the ULP clock using @ref sl_si91x_gpio_driver_enable_clock() API. + * - Select UULP NPSS receiver for UULP GPIO pin. + * @note: Select UULP GPIO pins for UULP instances(0 to 4). + ******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_set_uulp_npss_pin_mux(uint8_t pin, sl_si91x_uulp_npss_mode_t mode) +{ + // Check if pin or mode exceeds the maximum allowed + if ((pin > GPIO_UULP_MAX_PIN_NUM) || (mode > GPIO_MODE_MAX_VALUE)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Set UULP GPIO pin mode + sl_si91x_gpio_set_uulp_npss_pin_mux(pin, mode); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used to enable receiver bit in NPSS GPIO control register. + * Enable the ULP clock using @ref sl_si91x_gpio_driver_enable_clock() API, + * before using this API. + * @note: Select UULP GPIO pins for UULP instances(0 to 4). + ******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_select_uulp_npss_receiver(uint8_t pin, sl_si91x_gpio_receiver_t receiver) +{ + // Check if pin or receiver exceeds the maximum allowed + if ((pin > GPIO_UULP_MAX_PIN_NUM) || (receiver > GPIO_RECEIVER_MAX_VALUE)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Select UULP GPIO receiver + sl_si91x_gpio_select_uulp_npss_receiver(pin, receiver); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used to select the UULP direction in NPSS GPIO control + * register. Few actions are required to be performed before setting the + * direction, + * - Enable the ULP clock using @ref sl_si91x_gpio_driver_enable_clock() API. + * - Select UULP NPSS receiver for UULP GPIO pin. + * - Select UULP NPSS direction for UULP GPIO pin. + * - Set the mode of the GPIO pin. + * @note: Select UULP GPIO pins for UULP instances(0 to 4). + ******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_set_uulp_npss_direction(uint8_t pin, sl_si91x_gpio_direction_t direction) +{ + // Check if pin or direction exceeds the maximum allowed + if ((pin > GPIO_UULP_MAX_PIN_NUM) || (direction > GPIO_DIRECTION_MAX_VALUE)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Set UULP GPIO direction + sl_si91x_gpio_set_uulp_npss_direction(pin, direction); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used to get the UULP direction in NPSS GPIO control + * register. Few actions are required to be performed before setting the + * direction, + * - Enable the ULP clock using @ref sl_si91x_gpio_driver_enable_clock() API. + * - Select UULP NPSS receiver for UULP GPIO pin. + * - Set the mode of the GPIO pin. + * - Set the direction of the GPIO pin. + * - Get the direction of the GPIO pin. + * @note: Select UULP GPIO pins for UULP instances(0 to 4). + *******************************************************************************/ +uint8_t sl_si91x_gpio_driver_get_uulp_npss_direction(uint8_t pin) +{ + uint8_t direction; + // Check if pin exceeds the maximum allowed + if (pin > GPIO_UULP_MAX_PIN_NUM) { + return SL_STATUS_INVALID_PARAMETER; + } + // Get UULP GPIO direction + direction = sl_si91x_gpio_get_uulp_npss_direction(pin); + return direction; +} + +/******************************************************************************* + * This API is used to select the UULP pin value in NPSS GPIO control + * register. Few actions are required to be performed before setting the + * direction, + * - Enable the ULP clock using @ref sl_si91x_gpio_driver_enable_clock() API. + * - Select UULP NPSS receiver for UULP GPIO pin. + * - Set the mode of the GPIO pin. + * - Set the direction of the GPIO pin. + * - Select the GPIO pin value. + * @note: Select UULP GPIO pins for UULP instances(0 to 4). + ******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_set_uulp_npss_pin_value(uint8_t pin, sl_si91x_gpio_pin_value_t pin_value) +{ + // Check if pin or pin_value exceeds the maximum allowed + if ((pin > GPIO_UULP_MAX_PIN_NUM) || (pin_value > GPIO_PIN_VALUE_MAX_VALUE)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Set UULP GPIO pin value + sl_si91x_gpio_set_uulp_npss_pin_value(pin, pin_value); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used to toggle the UULP pin. + * Few actions are required to be performed before setting the direction, + * - Enable the ULP clock using @ref sl_si91x_gpio_driver_enable_clock() API. + * - Select UULP NPSS receiver for UULP GPIO pin. + * - Set the mode of the GPIO pin. + * - Set the direction of the GPIO pin. + * - Toggle the UULP GPIO pin. + * @note: Select UULP GPIO pins for UULP instances(0 to 4). + ******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_toggle_uulp_npss_pin(uint8_t pin) +{ + // Check if pin exceeds the maximum allowed + if (pin > GPIO_UULP_MAX_PIN_NUM) { + return SL_STATUS_INVALID_PARAMETER; + } + // Toggle UULP GPIO pin + sl_si91x_gpio_toggle_uulp_npss_pin(pin); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used to get the UULP pin value in NPSS GPIO control + * register. Few actions are required to be performed before setting the + * direction, + * - Enable the ULP clock using @ref sl_si91x_gpio_driver_enable_clock() API. + * - Select UULP NPSS receiver for UULP GPIO pin. + * - Set the mode of the GPIO pin. + * - Set the direction of the GPIO pin. + * - Select the GPIO pin value. + * - Get the GPIO pin value. + * @note: Select UULP GPIO pins for UULP instances(0 to 4). + ******************************************************************************/ +uint8_t sl_si91x_gpio_driver_get_uulp_npss_pin(uint8_t pin) +{ + uint8_t uulp_pin; + // Check if pin exceeds the maximum allowed + if (pin > GPIO_UULP_MAX_PIN_NUM) { + return SL_STATUS_INVALID_PARAMETER; + } + // Get UULP GPIO pin + uulp_pin = sl_si91x_gpio_get_uulp_npss_pin(pin); + return uulp_pin; +} + +/******************************************************************************* + * This API is used to select polarity of the UULP GPIO to be considered + when used as a wakeup source from any of the Sleep States. + ******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_select_uulp_npss_polarity(uint8_t pin, sl_si91x_gpio_polarity_t polarity) +{ + // Check if pin or polarity exceeds the maximum allowed + if ((pin > GPIO_UULP_MAX_PIN_NUM) || (polarity > GPIO_POLARITY_MAX_VALUE)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Select UULP GPIO polarity + sl_si91x_gpio_select_uulp_npss_polarity(pin, polarity); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used to set the UULP NPSS GPIO to wakeup interrupt + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_set_uulp_npss_wakeup_interrupt(uint8_t npssgpio_interrupt) +{ + // Check if npssgpio_interrupt exceeds the maximum allowed + if (npssgpio_interrupt > GPIO_NPSS_WAKEUP_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + // Set UULP GPIO wakeup interrupt + sl_si91x_gpio_set_uulp_npss_wakeup_interrupt(npssgpio_interrupt); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used to clear the UULP NPSS GPIO to wakeup interrupt + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_clear_uulp_npss_wakeup_interrupt(uint8_t npssgpio_interrupt) +{ + // Check if npssgpio_interrupt exceeds the maximum allowed + if (npssgpio_interrupt > GPIO_NPSS_WAKEUP_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + // Clear UULP GPIO wakeup interrupt + sl_si91x_gpio_clear_uulp_npss_wakeup_interrupt(npssgpio_interrupt); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used to mask the UULP NPSS GPIO interrupt. + * Few actions are required to be performed before interrupt mask is + * performed, + * - Enable the ULP clock using @ref sl_si91x_gpio_driver_enable_clock() API. + * - Select the . + * @note: All the UULP interrupts are masked by default. + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_mask_uulp_npss_interrupt(uint8_t npssgpio_interrupt) +{ + // Check if npssgpio_interrupt exceeds the maximum allowed + if (npssgpio_interrupt > GPIO_NPSSGPIO_INTERRUPT_VALUE_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + // Mask UULP GPIO interrupt + sl_si91x_gpio_mask_uulp_npss_interrupt(npssgpio_interrupt); + return SL_STATUS_OK; +} + +/******************************************************************************* + * Get the NPSS GPIO interrupt status. + ******************************************************************************/ +uint8_t sl_si91x_gpio_driver_get_uulp_interrupt_status(void) +{ + uint8_t status; + status = sl_si91x_gpio_get_uulp_interrupt_status(); + return status; +} + +/******************************************************************************* + * Get the ULP GPIO interrupt status. + ******************************************************************************/ +uint32_t sl_si91x_gpio_driver_get_ulp_interrupt_status(uint32_t flags) +{ + uint32_t status; + status = sl_si91x_gpio_get_ulp_interrupt_status(flags); + return status; +} + +/******************************************************************************* + * This API is used to un-mask the UULP NPSS GPIO interrupt. + * Few actions are required to be performed before interrupt un-mask is + * performed, + * - Enable the ULP clock using @ref sl_si91x_gpio_driver_enable_clock() API. + * - Set UULP PAD configuration register. + * - Select UULP NPSS receiver for UULP GPIO pin. + * - Set the mode of the GPIO pin. + * - Set the direction of the GPIO pin. + * - Un-mask interrupt by setting corresponding bit in register. + * @note: All the UULP interrupts are masked by default. + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_unmask_uulp_npss_interrupt(uint8_t npssgpio_interrupt) +{ + // Check if npssgpio_interrupt exceeds the maximum allowed + if (npssgpio_interrupt > GPIO_NPSSGPIO_INTERRUPT_VALUE_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + // Unmask UULP GPIO interrupt + sl_si91x_gpio_unmask_uulp_npss_interrupt(npssgpio_interrupt); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used to clear the UULP interrupt. + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_clear_uulp_interrupt(uint8_t npssgpio_interrupt) +{ + // Check if npssgpio_interrupt exceeds the maximum allowed + if (npssgpio_interrupt > GPIO_NPSSGPIO_INTERRUPT_VALUE_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + // Clear UULP GPIO interrupt + sl_si91x_gpio_clear_uulp_interrupt(npssgpio_interrupt); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used to configure the pin interrupt in GPIO UULP instance. + * There are total 5 pin interrupts in this instance. + * To configure the interrupt, first UULP GPIO initialization must be + * done. The actions to be performed in UULP GPIO initialization are: + * - Enable the ULP clock using @ref sl_si91x_gpio_driver_enable_clock() API. + * - Set UULP PAD configuration register. + * - Select UULP NPSS receiver for UULP GPIO pin. + * - Set the mode of the GPIO pin. + * - Set the direction of the GPIO pin. + * - Configure the UULP pin interrupt. + * Enable the IRQ handler. + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_configure_uulp_interrupt(sl_si91x_gpio_interrupt_config_flag_t flags, + uint8_t npssgpio_interrupt, + sl_gpio_irq_callback_t gpio_callback) +{ + // Check if gpio_callback pointer is NULL + if (gpio_callback == NULL) { + return SL_STATUS_NULL_POINTER; + } + // Check if a callback function is already registered for the given interrupt number. + if (gpio_uulp_pin_int_callback_fptr[npssgpio_interrupt] != NULL) { + return SL_STATUS_BUSY; + } + // Check if npssgpio_interrupt or flags exceeds the maximum allowed + if ((flags > GPIO_FLAGS_MAX_VALUE) || (npssgpio_interrupt > GPIO_NPSS_PIN_MAX_VALUE)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Assign the callback function pointer for the specified interrupt number. + gpio_uulp_pin_int_callback_fptr[npssgpio_interrupt] = gpio_callback; + // Configure the UULP GPIO interrupt. + sl_si91x_gpio_configure_uulp_interrupt(flags, npssgpio_interrupt); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used to clear one (or) more pending ULP GPIO interrupts. + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_clear_ulp_interrupt(uint32_t flags) +{ + // Check if flags exceeds the maximum allowed. + if (flags > GPIO_FLAGS_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + // Clears ULP GPIO pin interrupt + sl_si91x_gpio_clear_ulp_interrupt(flags); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used to clear the ULP group interrupts. + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_clear_ulp_group_interrupt(sl_si91x_group_interrupt_t group_interrupt) +{ + // Check if group interrupt exceeds the maximum allowed. + if (group_interrupt > GPIO_GROUP_INTERRUPT_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + // Clears ULP GPIO group interrupt + sl_si91x_gpio_clear_ulp_group_interrupt(group_interrupt); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API handles GPIO pin interrupt 0 request + ******************************************************************************/ +void PIN_IRQ0_Handler(void) +{ + sl_gpio_driver_clear_interrupts(PIN_INTR_0); + gpio_callback_function_pointer[PIN_INTR_0](PIN_INTR_0); +} + +/******************************************************************************* + * This API handles GPIO pin interrupt 1 request + ******************************************************************************/ +void PIN_IRQ1_Handler(void) +{ + sl_gpio_driver_clear_interrupts(PIN_INTR_1); + gpio_callback_function_pointer[PIN_INTR_1](PIN_INTR_1); +} + +/******************************************************************************* + * This API handles GPIO pin interrupt 2 request + ******************************************************************************/ +void PIN_IRQ2_Handler(void) +{ + sl_gpio_driver_clear_interrupts(PIN_INTR_2); + gpio_callback_function_pointer[PIN_INTR_2](PIN_INTR_2); +} + +/******************************************************************************* + * This API handles GPIO pin interrupt 3 request + ******************************************************************************/ +void PIN_IRQ3_Handler(void) +{ + sl_gpio_driver_clear_interrupts(PIN_INTR_3); + gpio_callback_function_pointer[PIN_INTR_3](PIN_INTR_3); +} + +/******************************************************************************* + * This API handles GPIO pin interrupt 4 request + ******************************************************************************/ +void PIN_IRQ4_Handler(void) +{ + sl_gpio_driver_clear_interrupts(PIN_INTR_4); + gpio_callback_function_pointer[PIN_INTR_4](PIN_INTR_4); +} + +/******************************************************************************* + * This API handles GPIO pin interrupt 5 request + ******************************************************************************/ +void PIN_IRQ5_Handler(void) +{ + sl_gpio_driver_clear_interrupts(PIN_INTR_5); + gpio_callback_function_pointer[PIN_INTR_5](PIN_INTR_5); +} + +/******************************************************************************* + * This API handles GPIO pin interrupt 6 request + ******************************************************************************/ +void PIN_IRQ6_Handler(void) +{ + sl_gpio_driver_clear_interrupts(PIN_INTR_6); + gpio_callback_function_pointer[PIN_INTR_6](PIN_INTR_6); +} + +/******************************************************************************* + * This API handles GPIO pin interrupt 7 request + ******************************************************************************/ +void PIN_IRQ7_Handler(void) +{ +// A temporary fix (delay of 46 micro seconds) to supress dual interrupts with rising edge. +#ifdef SL_SI91x_DUAL_INTERRUPTS_ERRATA + for (int i = 0; i < 1000; i++) + __asm__("nop;"); +#endif // SL_SI91x_DUAL_INTERRUPTS_ERRATA + + sl_gpio_driver_clear_interrupts(PIN_INTR_7); + gpio_callback_function_pointer[PIN_INTR_7](PIN_INTR_7); +} +/******************************************************************************* + * This API handles GPIO Group interrupt 0 request + ******************************************************************************/ +void GRP_IRQ0_Handler(void) +{ + sl_si91x_gpio_driver_clear_group_interrupt(GROUP_INT_1); + gpio_group_int_callback_fptr[GROUP_INT_1](GROUP_INT_1); +} + +/******************************************************************************* + * This API handles GPIO Group interrupt 1 request + ******************************************************************************/ +void GRP_IRQ1_Handler(void) +{ + sl_si91x_gpio_driver_clear_group_interrupt(GROUP_INT_2); + gpio_group_int_callback_fptr[GROUP_INT_2](GROUP_INT_2); +} + +/******************************************************************************* + * This API handles UULP GPIO pin interrupt 0 request + ******************************************************************************/ +void UULP_PIN_IRQ_Handler(void) +{ + uint32_t flag = 0; + if ((sl_si91x_gpio_driver_get_uulp_interrupt_status() & UULP_INTR_1) != UULP_MASK) { + sl_si91x_gpio_driver_clear_uulp_interrupt(UULP_INTR_1); + flag = PIN_INTR_0; + } + if ((sl_si91x_gpio_driver_get_uulp_interrupt_status() & UULP_INTR_2) != UULP_MASK) { + sl_si91x_gpio_driver_clear_uulp_interrupt(UULP_INTR_2); + flag = PIN_INTR_1; + } + if ((sl_si91x_gpio_driver_get_uulp_interrupt_status() & UULP_INTR_3) != UULP_MASK) { + sl_si91x_gpio_driver_clear_uulp_interrupt(UULP_INTR_3); + flag = PIN_INTR_2; + } + if ((sl_si91x_gpio_driver_get_uulp_interrupt_status() & UULP_INTR_4) != UULP_MASK) { + sl_si91x_gpio_driver_clear_uulp_interrupt(UULP_INTR_4); + flag = PIN_INTR_3; + } + if ((sl_si91x_gpio_driver_get_uulp_interrupt_status() & UULP_INTR_5) != UULP_MASK) { + sl_si91x_gpio_driver_clear_uulp_interrupt(UULP_INTR_5); + flag = PIN_INTR_4; + } + gpio_uulp_pin_int_callback_fptr[flag](flag); +} + +/******************************************************************************* + * This API handles ULP GPIO OR'ed pin interrupt request + ******************************************************************************/ +void ULP_PIN_IRQ_Handler(void) +{ + uint32_t flag = 0; + if ((sl_si91x_gpio_driver_get_ulp_interrupt_status(ULP_PIN_INTR_0)) == ULP_STATUS) { + sl_si91x_gpio_driver_clear_ulp_interrupt(ULP_PIN_INTR_0); + flag = ULP_PIN_INTR_0; + } + if ((sl_si91x_gpio_driver_get_ulp_interrupt_status(ULP_PIN_INTR_1)) == ULP_STATUS) { + sl_si91x_gpio_driver_clear_ulp_interrupt(ULP_PIN_INTR_1); + flag = ULP_PIN_INTR_1; + } + if ((sl_si91x_gpio_driver_get_ulp_interrupt_status(ULP_PIN_INTR_2)) == ULP_STATUS) { + sl_si91x_gpio_driver_clear_ulp_interrupt(ULP_PIN_INTR_2); + flag = ULP_PIN_INTR_2; + } + if ((sl_si91x_gpio_driver_get_ulp_interrupt_status(ULP_PIN_INTR_3)) == ULP_STATUS) { + sl_si91x_gpio_driver_clear_ulp_interrupt(ULP_PIN_INTR_3); + flag = ULP_PIN_INTR_3; + } + if ((sl_si91x_gpio_driver_get_ulp_interrupt_status(ULP_PIN_INTR_4)) == ULP_STATUS) { + sl_si91x_gpio_driver_clear_ulp_interrupt(ULP_PIN_INTR_4); + flag = ULP_PIN_INTR_4; + } + if ((sl_si91x_gpio_driver_get_ulp_interrupt_status(ULP_PIN_INTR_5)) == ULP_STATUS) { + sl_si91x_gpio_driver_clear_ulp_interrupt(ULP_PIN_INTR_5); + flag = ULP_PIN_INTR_5; + } + if ((sl_si91x_gpio_driver_get_ulp_interrupt_status(ULP_PIN_INTR_6)) == ULP_STATUS) { + sl_si91x_gpio_driver_clear_ulp_interrupt(ULP_PIN_INTR_6); + flag = ULP_PIN_INTR_6; + } + if ((sl_si91x_gpio_driver_get_ulp_interrupt_status(ULP_PIN_INTR_7)) == ULP_STATUS) { + sl_si91x_gpio_driver_clear_ulp_interrupt(ULP_PIN_INTR_7); + flag = ULP_PIN_INTR_7; + } + gpio_ulp_pin_int_callback_fptr[flag](flag); +} + +/******************************************************************************* + * This API handles ULP GPIO group interrupt request + ******************************************************************************/ +void ULP_GROUP_IRQ_Handler(void) +{ + uint32_t flag = 0; + if (sl_si91x_gpio_get_group_interrupt_status(SL_GPIO_ULP_PORT, GROUP_INT_1) == ULP_STATUS) { + sl_si91x_gpio_driver_clear_ulp_group_interrupt(GROUP_INT_1); + flag = GROUP_INT_1; + } + if (sl_si91x_gpio_get_group_interrupt_status(SL_GPIO_ULP_PORT, GROUP_INT_2) == ULP_STATUS) { + sl_si91x_gpio_driver_clear_ulp_group_interrupt(GROUP_INT_2); + flag = GROUP_INT_2; + } + gpio_ulp_group_int_callback_fptr[flag](flag); +} + +/******************************************************************************* + * De-Initialization of GPIO driver. + ******************************************************************************/ +sl_status_t sl_gpio_driver_deinit(void) +{ + sl_status_t status; + uint8_t flag; + do { + for (flag = 0; flag < GPIO_MAX_INTR_VALUE; flag++) { + gpio_callback_function_pointer[flag] = NULL; + } + for (flag = 0; flag < MAX_GROUP_INT; flag++) { + gpio_group_int_callback_fptr[flag] = NULL; + } + for (flag = 0; flag < MAX_UULP_INT; flag++) { + gpio_uulp_pin_int_callback_fptr[flag] = NULL; + } + for (flag = 0; flag < GPIO_MAX_INTR_VALUE; flag++) { + gpio_ulp_pin_int_callback_fptr[flag] = NULL; + } + for (flag = 0; flag < MAX_GROUP_INT; flag++) { + gpio_ulp_group_int_callback_fptr[flag] = NULL; + } + status = sl_si91x_gpio_driver_disable_clock(M4CLK_GPIO); // Disables M4 GPIO clock + if (status != SL_STATUS_OK) { + return status; + } + status = sl_si91x_gpio_driver_disable_clock(ULPCLK_GPIO); // Disables ULP GPIO clock + if (status != SL_STATUS_OK) { + return status; + } + } while (false); + return SL_STATUS_OK; +} + +/******************************************************************************* + * Unregister GPIO interrupts + ******************************************************************************/ +sl_status_t sl_gpio_driver_unregister(sl_si91x_gpio_instances_t gpio_instance, + sl_si91x_gpio_intr_t gpio_intr, + uint8_t flag) +{ + if (gpio_instance >= GPIO_INSTANCE_LAST) { + // Returns invalid parameter status code if gpio_instance > GPIO_INSTANCE_LAST + return SL_STATUS_INVALID_PARAMETER; + } + switch (gpio_instance) { + case M4_GPIO_INSTANCE: + switch (gpio_intr) { + case GPIO_PIN_INTERRUPT: + if (flag > GPIO_MAX_INTR_VALUE) { + // Returns invalid parameter status code if flag > GPIO_MAX_INTR_VALUE + return SL_STATUS_INVALID_PARAMETER; + } + gpio_callback_function_pointer[flag] = NULL; + break; + case GPIO_GROUP_INTERRUPT: + if (flag > MAX_GROUP_INT) { + // Returns invalid parameter status code if flag > MAX_GROUP_INT + return SL_STATUS_INVALID_PARAMETER; + } + gpio_group_int_callback_fptr[flag] = NULL; + break; + } + break; + case ULP_GPIO_INSTANCE: + switch (gpio_intr) { + case GPIO_PIN_INTERRUPT: + if (flag > GPIO_MAX_INTR_VALUE) { + // Returns invalid parameter status code if flag > GPIO_MAX_INTR_VALUE + return SL_STATUS_INVALID_PARAMETER; + } + gpio_ulp_pin_int_callback_fptr[flag] = NULL; + break; + case GPIO_GROUP_INTERRUPT: + if (flag > MAX_GROUP_INT) { + // Returns invalid parameter status code if flag > MAX_GROUP_INT + return SL_STATUS_INVALID_PARAMETER; + } + gpio_ulp_group_int_callback_fptr[flag] = NULL; + break; + } + break; + case UULP_GPIO_INSTANCE: + if (flag > MAX_UULP_INT) { + // Returns invalid parameter status code if flag > GPIO_MAX_INTR_VALUE + return SL_STATUS_INVALID_PARAMETER; + } + gpio_uulp_pin_int_callback_fptr[flag] = NULL; + break; + case GPIO_INSTANCE_LAST: + break; + default: + break; + } + return SL_STATUS_OK; +} diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/inc/sl_si91x_gpio.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/inc/sl_si91x_gpio.h new file mode 100644 index 000000000..ba4c4ce61 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/inc/sl_si91x_gpio.h @@ -0,0 +1,1004 @@ +/***************************************************************************/ /** + * @file sl_si91x_gpio.h + * @brief General Purpose IO(GPIO) API implementation + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licenser of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be mis-represented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * mis-represented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_SI91X_GPIO_PERIPHERAL_H +#define SL_SI91X_GPIO_PERIPHERAL_H + +#ifdef __cplusplus +extern "C" { +#endif + +//// Includes +#include "sl_si91x_gpio_common.h" + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ +///@brief NPSS GPIO PIN MUX +typedef enum { + NPSS_GPIO_PIN_MUX_MODE0, ///< NPSS Pin MUX Mode 0 + NPSS_GPIO_PIN_MUX_MODE1, ///< NPSS Pin MUX Mode 1 + NPSS_GPIO_PIN_MUX_MODE2, ///< NPSS Pin MUX Mode 2 + NPSS_GPIO_PIN_MUX_MODE3, ///< NPSS Pin MUX Mode 3 + NPSS_GPIO_PIN_MUX_MODE4, ///< NPSS Pin MUX Mode 4 + NPSS_GPIO_PIN_MUX_MODE5, ///< NPSS Pin MUX Mode 5 + NPSS_GPIO_PIN_MUX_MODE6, ///< NPSS Pin MUX Mode 6 + NPSS_GPIO_PIN_MUX_MODE7, ///< NPSS Pin MUX Mode 7 + NPSS_GPIO_PIN_MUX_MODE8, ///< NPSS Pin MUX Mode 8 + NPSS_GPIO_PIN_MUX_MODE9, ///< NPSS Pin MUX Mode 9 + NPSS_GPIO_PIN_MUX_MODE10, ///< NPSS Pin MUX Mode 10 +} sl_si91x_uulp_npss_mode_t; + +///@brief GPIO group interrupts +typedef enum { + GROUP_INT_1 = 0, ///< GPIO group interrupt 1 + GROUP_INT_2 = 1, ///< GPIO group interrupt 2 +} sl_si91x_group_interrupt_t; + +///@brief GPIO Interrupt Configurations. +typedef enum { + SL_GPIO_INTERRUPT_LEVEL_HIGH = (1 << 0), ///< interrupt when pin level is '1' + SL_GPIO_INTERRUPT_LEVEL_LOW = (1 << 1), ///< interrupt when pin level is '0' + SL_GPIO_INTERRUPT_RISE_EDGE = (1 << 2), ///< interrupt when rising edge is detected + SL_GPIO_INTERRUPT_FALL_EDGE = (1 << 3), ///< interrupt when falling edge is detected +} sl_si91x_gpio_interrupt_config_flag_t; + +///@brief GPIO driver disable state +typedef enum { + GPIO_HZ = 0, ///< 0 for Hi-impedance (P1=0,P2=0) + GPIO_PULLUP, ///< 1 for Pull up (P1=0,P2=1) + GPIO_PULLDOWN, ///< 2 for Pull down(P1=1,P2=0) + GPIO_REPEATER ///< 3 for Repeater (P1=1,P2=1) +} sl_si91x_gpio_driver_disable_state_t; + +///@brief GPIO driver strength select +typedef enum { + GPIO_TWO_MILLI_AMPS = 0, ///< 0 for two_milli_amps (E1=0,E2=0) + GPIO_FOUR_MILLI_AMPS, ///< 1 for four_milli_amps (E1=0,E2=1) + GPIO_EIGHT_MILLI_AMPS, ///< 2 for eight_milli_amps (E1=1,E2=0) + GPIO_TWELVE_MILLI_AMPS ///< 3 for twelve_milli_amps(E1=1,E2=1) +} sl_si91x_gpio_driver_strength_select_t; + +///@brief HP/ULP GPIO clock select +typedef enum { + M4CLK_GPIO = 0, ///< 0 for HP GPIO clock + ULPCLK_GPIO = 1 ///< 1 for ULP GPIO clock +} sl_si91x_gpio_select_clock_t; + +///@brief Direction of the GPIO pin enum +typedef enum { + GPIO_OUTPUT = 0, ///< GPIO direction output + GPIO_INPUT = 1, ///< GPIO direction input +} sl_si91x_gpio_direction_t; + +///@brief UULP GPIO PAD select enum +typedef enum { + GPIO_PAD_M4 = 0, ///< GPIO M4 PAD selection + GPIO_PAD_TA = 1, ///< GPIO TA PAD selection +} sl_si91x_gpio_uulp_pad_t; + +///@brief AND/OR of the GPIO group interrupt +typedef enum { + GPIO_AND = 0, ///< GPIO AND group interrupt + GPIO_OR = 1, ///< GPIO OR group interrupt +} sl_si91x_gpio_and_or_t; + +///@brief GPIO group interrupt wakeup flag +typedef enum { + GPIO_FLAG_DS = 0, ///< wakeup flag disable + GPIO_FLAG_EN = 1, ///< wakeup flag enable +} sl_si91x_gpio_wakeup_t; + +///@brief GPIO polarity enum +typedef enum { + GPIO_POLARITY_0 = 0, ///< GPIO polarity 0 + GPIO_POLARITY_1 = 1, ///< GPIO polarity 1 +} sl_si91x_gpio_polarity_t; + +///@brief GPIO level edge select +typedef enum { + GPIO_LEVEL = 0, ///< GPIO level trigger + GPIO_EDGE = 1, ///< GPIO edge trigger +} sl_si91x_gpio_level_edge_t; + +///@brief GPIO slew rate select +typedef enum { + GPIO_SR_LOW = 0, ///< GPIO slew rate low + GPIO_SR_HIGH = 1, ///< GPIO slew rate high +} sl_si91x_gpio_slew_rate_t; + +///@brief GPIO pin set/clear +typedef enum { + GPIO_PIN_CLEAR = 0, ///< GPIO clear pin + GPIO_PIN_SET = 1, ///< GPIO set pin +} sl_si91x_gpio_pin_value_t; + +///@brief NPSS GPIO input buffer +typedef enum { + GPIO_RECEIVER_DS = 0, ///< receiver disable + GPIO_RECEIVER_EN = 1, ///< receiver enable +} sl_si91x_gpio_receiver_t; + +///@brief UULP GPIO PAD configuration register fields +typedef struct { + uint8_t gpio_padnum; ///< UULP GPIO pin number + sl_si91x_uulp_npss_mode_t mode; ///< UULP GPIO mode + sl_si91x_gpio_receiver_t receiver; ///< UULP GPIO PAD receiver + sl_si91x_gpio_direction_t direction; ///< UULP GPIO direction of PAD + sl_si91x_gpio_pin_value_t output; ///< UULP GPIO value driven on PAD + sl_si91x_gpio_uulp_pad_t pad_select; ///< UULP GPIO PAD selection + sl_si91x_gpio_polarity_t polarity; ///< UULP GPIO Polarity +} uulp_pad_config_t; + +///@brief GPIO Group Interrupt Configuration. It selects random ports and pins. +typedef struct { + sl_si91x_group_interrupt_t grp_interrupt; ///< configure group interrupt + uint8_t grp_interrupt_cnt; ///< Count of group interrupt pins + uint8_t grp_interrupt_port[MAX_GPIO_PIN_INT]; ///< ports used for group interrupts + uint8_t grp_interrupt_pin[MAX_GPIO_PIN_INT]; ///< pins used for group interrupts + uint8_t grp_interrupt_pol[MAX_GPIO_PIN_INT]; ///< polarity used for interrupts + sl_si91x_gpio_level_edge_t level_edge; ///< configure level or edge trigger + sl_si91x_gpio_and_or_t and_or; ///< AND/OR ing of interrupts +} sl_si91x_gpio_group_interrupt_config_t; + +///@brief GPIO pin numbers +typedef enum { + GPIO_PIN_NUMBER0 = 0, ///< GPIO pin number 0 + GPIO_PIN_NUMBER1 = 1, ///< GPIO pin number 1 + GPIO_PIN_NUMBER2 = 2, ///< GPIO pin number 2 + GPIO_PIN_NUMBER3 = 3, ///< GPIO pin number 3 + GPIO_PIN_NUMBER4 = 4, ///< GPIO pin number 4 + GPIO_PIN_NUMBER5 = 5, ///< GPIO pin number 5 + GPIO_PIN_NUMBER6 = 6, ///< GPIO pin number 6 + GPIO_PIN_NUMBER7 = 7, ///< GPIO pin number 7 + GPIO_PIN_NUMBER8 = 8, ///< GPIO pin number 8 + GPIO_PIN_NUMBER9 = 9, ///< GPIO pin number 9 + GPIO_PIN_NUMBER10 = 10, ///< GPIO pin number 10 + GPIO_PIN_NUMBER11 = 11, ///< GPIO pin number 11 + GPIO_PIN_NUMBER12 = 12, ///< GPIO pin number 12 + GPIO_PIN_NUMBER13 = 13, ///< GPIO pin number 13 + GPIO_PIN_NUMBER14 = 14, ///< GPIO pin number 14 + GPIO_PIN_NUMBER15 = 15, ///< GPIO pin number 15 +} sl_si91x_gpio_pin_t; + +///@brief GPIO ULP pin numbers +typedef enum { + ULP_GPIO_PIN_0 = 0, ///< ULP GPIO pin number 0 + ULP_GPIO_PIN_1 = 1, ///< ULP GPIO pin number 1 + ULP_GPIO_PIN_2 = 2, ///< ULP GPIO pin number 2 + ULP_GPIO_PIN_3 = 3, ///< ULP GPIO pin number 3 + ULP_GPIO_PIN_4 = 4, ///< ULP GPIO pin number 4 + ULP_GPIO_PIN_5 = 5, ///< ULP GPIO pin number 5 + ULP_GPIO_PIN_6 = 6, ///< ULP GPIO pin number 6 + ULP_GPIO_PIN_7 = 7, ///< ULP GPIO pin number 7 + ULP_GPIO_PIN_8 = 8, ///< ULP GPIO pin number 8 + ULP_GPIO_PIN_9 = 9, ///< ULP GPIO pin number 9 + ULP_GPIO_PIN_10 = 10, ///< ULP GPIO pin number 10 + ULP_GPIO_PIN_11 = 11, ///< ULP GPIO pin number 11 +} sl_si91x_gpio_pin_ulp_t; + +///@brief GPIO instances +typedef enum { + M4_GPIO_INSTANCE = 1, ///< 1 for HP GPIO + ULP_GPIO_INSTANCE = 2, ///< 2 for ULP GPIO + UULP_GPIO_INSTANCE = 3, ///< 3 for UULP GPIO + GPIO_INSTANCE_LAST, ///< Last enum for validating +} sl_si91x_gpio_instances_t; + +///@brief GPIO interrupt type +typedef enum { + GPIO_PIN_INTERRUPT, ///< 0 for GPIO pin interrupt + GPIO_GROUP_INTERRUPT, ///< 1 for GPIO group interrupt +} sl_si91x_gpio_intr_t; + +/// @brief Structure to hold the versions of peripheral API +typedef struct { + uint8_t release; ///< Release version number + uint8_t major; ///< SQA version number + uint8_t minor; ///< Development version number +} sl_si91x_gpio_version_t; + +// ----------------------------------------------------------------------------- +// Prototypes +/***************************************************************************/ /** + * @brief Set the direction for a GPIO pin from the selected port. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n + * Use corresponding pad receiver API for corresponding GPIO instance. + * @param[in] port - The port to associate with the pin. + * HP instance - PORT 0,1,2,3 + * ULP instance - PORT 4 + * @param[in] pin - The pin number on the port. + * HP instance has total 57 GPIO pins. Port 0, 1, 2 has 16 pins each. + * Port 3 has 9 pins. + * ULP instance has total 12 pins. + * @param[in] direction - pin direction of type \ref sl_si91x_gpio_direction_t + * '0' - Output\n + * '1' - Input\n + * @return None +*******************************************************************************/ +void sl_si91x_gpio_set_pin_direction(uint8_t port, uint8_t pin, sl_si91x_gpio_direction_t direction); + +/***************************************************************************/ /** + * @brief Get the direction of a GPIO pin from selected port. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_enable_pad_selection, for HP instance \n + * \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n + * Use corresponding pad receiver API for corresponding GPIO instance. \n + * \ref sl_si91x_gpio_set_pin_direction() \n + * \ref sl_si91x_gpio_get_pin_direction() \n + * @param[in] port - The port to associate with the pin. + * HP instance - PORT 0,1,2,3 + * ULP instance - PORT 4 + * @param[in] pin - The pin number on the port. + * HP instance has total 57 GPIO pins. Port 0, 1, 2 has 16 pins each. + * Port 3 has 9 pins. + * ULP instance has total 12 pins. + * @return Returns the direction of the pin. + * '0' - Output\n + * '1' - Input\n + ******************************************************************************/ +uint8_t sl_si91x_gpio_get_pin_direction(uint8_t port, uint8_t pin); + +/***************************************************************************/ /** + * @brief Enable the receiver enable bit in the PAD configuration register. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * @param[in] gpio_num - GPIO pin number to be use. + * @return None +*******************************************************************************/ +void sl_si91x_gpio_enable_pad_receiver(uint8_t gpio_num); + +/***************************************************************************/ /** + * @brief Disable the receiver enable bit in the PAD configuration register. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * @param[in] gpio_num - GPIO pin number to be use. + * @return None +*******************************************************************************/ +void sl_si91x_gpio_disable_pad_receiver(uint8_t gpio_num); + +/***************************************************************************/ /** + * @brief Select the pad enable for HP instance of GPIO pins + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @param[in] gpio_padnum - PAD number to be use(0 to 21). + * @return None +*******************************************************************************/ +void sl_si91x_gpio_enable_pad_selection(uint8_t gpio_padnum); + +/***************************************************************************/ /** + * @brief Select the host pad enable for HP instance of GPIO pins + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @param[in] gpio_num - GPIO pin number(25 to 30). + * @return None +*******************************************************************************/ +void sl_si91x_gpio_enable_host_pad_selection(uint8_t gpio_num); + +/***************************************************************************/ /** + * @brief Select drive strength of a GPIO pin for selected port. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_enable_pad_selection() \n + * \ref sl_si91x_gpio_enable_pad_receiver() \n + * @param[in] gpio_num - GPIO pin number to be use + * @param[in] strength - Drive strength selector(E1,E2) of type + * \ref sl_si91x_gpio_driver_strength_select_t + * possible values are + * 0, for two_milli_amps (E1=0,E2=0)\n + * 1, for four_milli_amps (E1=0,E2=1)\n + * 2, for eight_milli_amps (E1=1,E2=0)\n + * 3, for twelve_milli_amps(E1=1,E2=1)\n + * @return None + ******************************************************************************/ +void sl_si91x_gpio_select_pad_driver_strength(uint8_t gpio_num, sl_si91x_gpio_driver_strength_select_t strength); + +/***************************************************************************/ /** + * @brief Select the Driver disabled state control of a HP instance GPIO pin. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_enable_pad_selection() \n + * \ref sl_si91x_gpio_enable_pad_receiver() \n + * @param[in] gpio_num - GPIO pin number to be use + * @param[in] disable_state - driver disable state of type + * \ref sl_si91x_gpio_driver_disable_state_t + * possible values are + * 0, for HiZ (P1=0,P2=0)\n + * 1, for Pull-up (P1=0,P2=1)\n + * 2, for Pull-down (P1=1,P2=0)\n + * 3, for Repeater (P1=1,P2=1)\n + * @return None + ******************************************************************************/ +void sl_si91x_gpio_select_pad_driver_disable_state(uint8_t gpio_num, + sl_si91x_gpio_driver_disable_state_t disable_state); + +/***************************************************************************/ /** + * @brief Select AND/OR of the group interrupt. If multiple interrupts + * on same port (or) different are to be generated, then use this API. + * Example: Consider port 0: pin 2,3 and port 3: pin 1,2 for interrupt generation. + * Choose OR, any of the selected pin is fine for group interrupt generation + * Choose AND, all the selected pins are necessary for group interrupt generation + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n + * Use corresponding pad receiver API for corresponding GPIO instance. + * \ref sl_gpio_set_pin_mode() \n + * \ref sl_si91x_gpio_set_pin_direction() \n + * \ref sl_si91x_gpio_configure_group_interrupt(), for HP instance \n + * \ref sl_si91x_gpio_configure_ulp_group_interrupt, for ULP instance \n + * Use corresponding group interrupt configuration API for corresponding GPIO instance. + * @param[in] port - The port to associate with the pin. + * HP instance - PORT 0,1,2,3 + * ULP instance - PORT 4 + * @param[in] group_interrupt - Group interrupt number of type + * \ref sl_si91x_group_interrupt_t + * @param[in] and_or - AND/OR of GPIO group interrupts of type + * \ref sl_si91x_gpio_and_or_t + * '0' - AND\n + * '1' - OR\n + * @return None +*******************************************************************************/ +void sl_si91x_gpio_select_group_interrupt_and_or(uint8_t port, + sl_si91x_group_interrupt_t group_interrupt, + sl_si91x_gpio_and_or_t and_or); + +/***************************************************************************/ /** + * @brief Clear the selected group interrupt status for HP instance GPIO pins. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_enable_pad_selection() \n + * \ref sl_si91x_gpio_enable_pad_receiver() \n + * \ref sl_gpio_set_pin_mode() \n + * \ref sl_si91x_gpio_set_pin_direction() \n + * \ref sl_si91x_gpio_configure_group_interrupt() \n + * @param[in] group_interrupt - Group interrupt number of type + * \ref sl_si91x_group_interrupt_t + * @return None +*******************************************************************************/ +void sl_si91x_gpio_clear_group_interrupt(sl_si91x_group_interrupt_t group_interrupt); + +/***************************************************************************/ /** + * @brief Get the group interrupt status of selected instance. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n + * Use corresponding pad receiver API for corresponding GPIO instance. \n + * \ref sl_gpio_set_pin_mode(), + * \ref sl_si91x_gpio_set_pin_direction() \n + * \ref sl_si91x_gpio_configure_group_interrupt(), for HP instance \n + * \ref sl_si91x_gpio_configure_ulp_group_interrupt, for ULP instance \n + * Use corresponding group interrupt configuration API for corresponding GPIO instance. + * @param[in] port - The port to associate with the pin. + * HP instance - PORT 0,1,2,3 + * ULP instance - PORT 4 + * @param[in] group_interrupt - Group interrupt number of type + * \ref sl_si91x_group_interrupt_t + * @return returns the group interrupt status register + * 1, when interrupt is enabled\n + * 0, when interrupt is disabled\n + ******************************************************************************/ +uint32_t sl_si91x_gpio_get_group_interrupt_status(uint8_t port, sl_si91x_group_interrupt_t group_interrupt); + +/***************************************************************************/ /** + * @brief Configure the group interrupt as a wake up source across sleep wakeups. + * @param[in] port - The port to associate with the pin. + * HP instance - PORT 0,1,2,3 + * ULP instance - PORT 4 + * @param[in] group_interrupt - Group interrupt number of type + * \ref sl_si91x_group_interrupt_t + * @param[in] flags - GPIO group interrupt wake up flag of type + * \ref sl_si91x_gpio_wakeup_t + * '1' - enable\n + * '0' - disable\n + * @return None + ******************************************************************************/ +void sl_si91x_gpio_select_group_interrupt_wakeup(uint8_t port, + sl_si91x_group_interrupt_t group_interrupt, + sl_si91x_gpio_wakeup_t flags); + +/***************************************************************************/ /** + * @brief Configure the MCU HP instance group interrupts with trigger type(level/edge), polarity(high/low),interrupt type(and/or) + * and register the callback function for interrupts. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_enable_pad_selection() \n + * \ref sl_si91x_gpio_enable_pad_receiver() \n + * \ref sl_gpio_set_pin_mode() \n + * \ref sl_si91x_gpio_set_pin_direction() \n + * @param[in] configuration - configuration pointer to + * \ref sl_si91x_gpio_group_interrupt_config_t structure + * @return None +*******************************************************************************/ +void sl_si91x_gpio_configure_group_interrupt(sl_si91x_gpio_group_interrupt_config_t *configuration); + +/***************************************************************************/ /** + * @brief Get the polarity of selected group interrupt of a HP instance GPIO. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n + * Use corresponding pad receiver API for corresponding GPIO instance. \n + * \ref sl_gpio_set_pin_mode() \n + * \ref sl_si91x_gpio_set_pin_direction() \n + * \ref sl_si91x_gpio_configure_group_interrupt(), for HP instance \n + * \ref sl_si91x_gpio_configure_ulp_group_interrupt, for ULP instance \n + * Use corresponding group interrupt configuration API for corresponding GPIO instance. + * @param[in] group_interrupt - GPIO group interrupt number of type + * \ref sl_si91x_group_interrupt_t + * @param[in] port - The port to associate with the pin. + * HP instance - PORT 0,1,2,3 + * ULP instance - PORT 4 + * @param[in] pin - The pin number on the port. + * HP instance has total 57 GPIO pins. Port 0, 1, 2 has 16 pins each. + * Port 3 has 9 pins. + * ULP instance has total 12 pins. + * @return returns group interrupt polarity + * 1, when GPIO pin status is '1'\n + * 0, when GPIO pin status is '0'\n + ******************************************************************************/ +uint8_t sl_si91x_gpio_get_group_interrupt_polarity(sl_si91x_group_interrupt_t group_interrupt, + uint8_t port, + uint8_t pin); + +/***************************************************************************/ /** + * @brief Configure the polarity of selected group interrupt for HP instance GPIO . + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n + * Use corresponding pad receiver API for corresponding GPIO instance. \n + * \ref sl_gpio_set_pin_mode() \n + * \ref sl_si91x_gpio_set_pin_direction() \n + * \ref sl_si91x_gpio_configure_group_interrupt(), for HP instance \n + * \ref sl_si91x_gpio_configure_ulp_group_interrupt, for ULP instance \n + * Use corresponding group interrupt configuration API for corresponding GPIO instance. + * @param[in] group_interrupt - GPIO group interrupt number of type + * \ref sl_si91x_group_interrupt_t + * @param[in] port - The port to associate with the pin. + * HP instance - PORT 0,1,2,3 + * ULP instance - PORT 4 + * @param[in] pin - The pin number on the port. + * HP instance has total 57 GPIO pins. Port 0, 1, 2 has 16 pins each. + * Port 3 has 9 pins. + * ULP instance has total 12 pins. + * @param[in] polarity - polarity of GPIO group interrupt of type + * \ref sl_si91x_gpio_polarity_t + * 1, group interrupt gets generated when GPIO pin status is '1'\n + * 0, group interrupt gets generated when GPIO pin status is '0'\n + * @return None + ******************************************************************************/ +void sl_si91x_gpio_set_group_interrupt_polarity(sl_si91x_group_interrupt_t group_interrupt, + uint8_t port, + uint8_t pin, + sl_si91x_gpio_polarity_t polarity); + +/***************************************************************************/ /** + * @brief Get the level/edge event status of selected group interrupt. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n + * Use corresponding pad receiver API for corresponding GPIO instance. \n + * \ref sl_gpio_set_pin_mode(), \n + * \ref sl_si91x_gpio_set_pin_direction(), \n + * \ref sl_si91x_gpio_configure_group_interrupt(), for HP instance \n + * \ref sl_si91x_gpio_configure_ulp_group_interrupt, for ULP instance \n + * Use corresponding group interrupt configuration API for corresponding GPIO instance. + * @param[in] port - The port to associate with the pin. + * HP instance - PORT 0,1,2,3 + * ULP instance - PORT 4 + * @param[in] group_interrupt - GPIO group interrupt number of type + * \ref sl_si91x_group_interrupt_t + * @return returns group interrupt level_edge + * 1, for Edge\n + * 0, for Level\n + ******************************************************************************/ +uint8_t sl_si91x_gpio_get_group_interrupt_level_edge(uint8_t port, sl_si91x_group_interrupt_t group_interrupt); + +/***************************************************************************/ /** + * @brief Set the level/edge event of group interrupt. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n + * Use corresponding pad receiver API for corresponding GPIO instance. \n + * \ref sl_gpio_set_pin_mode() \n + * \ref sl_si91x_gpio_set_pin_direction() \n + * \ref sl_si91x_gpio_configure_group_interrupt(), for HP instance \n + * \ref sl_si91x_gpio_configure_ulp_group_interrupt, for ULP instance \n + * Use corresponding group interrupt configuration API for corresponding GPIO instance. + * @param[in] port - The port to associate with the pin. + * HP instance - PORT 0,1,2,3 + * ULP instance - PORT 4 + * @param[in] group_interrupt - GPIO group interrupt number of type + * \ref sl_si91x_group_interrupt_t + * @param[in] level_edge - GPIO level edge group interrupt of type + * \ref sl_si91x_gpio_level_edge_t + * 1, for Edge\n + * 0, for Level\n + * @return None + ******************************************************************************/ +void sl_si91x_gpio_set_group_interrupt_level_edge(uint8_t port, + sl_si91x_group_interrupt_t group_interrupt, + sl_si91x_gpio_level_edge_t level_edge); + +/***************************************************************************/ /** + * @brief Unmask the selected group interrupt to enable interrupt clearing upon generation. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n + * Use corresponding pad receiver API for corresponding GPIO instance. \n + * \ref sl_gpio_set_pin_mode() \n + * \ref sl_si91x_gpio_set_pin_direction() \n + * \ref sl_si91x_gpio_configure_group_interrupt(), for HP instance \n + * \ref sl_si91x_gpio_configure_ulp_group_interrupt, for ULP instance \n + * Use corresponding group interrupt configuration API for corresponding GPIO instance. + * @param[in] port - The port to associate with the pin. + * HP instance - PORT 0,1,2,3 + * ULP instance - PORT 4 + * @param[in] group_interrupt - GPIO group interrupt number of type + * \ref sl_si91x_group_interrupt_t + * @return None +*******************************************************************************/ +void sl_si91x_gpio_unmask_group_interrupt(uint8_t port, sl_si91x_group_interrupt_t group_interrupt); + +/***************************************************************************/ /** + * @brief Mask the selected group interrupts. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n + * Use corresponding pad receiver API for corresponding GPIO instance. \n + * \ref sl_gpio_set_pin_mode() \n + * \ref sl_si91x_gpio_set_pin_direction() \n + * @param[in] port - The port to associate with the pin. + * HP instance - PORT 0,1,2,3 + * ULP instance - PORT 4 + * @param[in] group_interrupt - GPIO group interrupt number of type + * \ref sl_si91x_group_interrupt_t + * @return None + *******************************************************************************/ +void sl_si91x_gpio_mask_group_interrupt(uint8_t port, sl_si91x_group_interrupt_t group_interrupt); + +/***************************************************************************/ /** + * @brief Disable the clock for either HP or ULP instance of GPIO Peripheral. + * @param[in] clock - Selects M4 clock or ULP clock of type + * \ref sl_si91x_gpio_select_clock_t + * 0, for M4 GPIO CLK\n + * 1, for ULP GPIO CLK\n + * @return None + ******************************************************************************/ +void sl_si91x_gpio_disable_clock(sl_si91x_gpio_select_clock_t clock); + +/***************************************************************************/ /** + * @brief Enable the clock for either HP or ULP instance of GPIO peripheral. + * @param[in] clock - Selects M4 clock or ULP clock of type + * \ref sl_si91x_gpio_select_clock_t + * 0, for M4 GPIO CLK\n + * 1, for ULP GPIO CLK\n + * @return None + ******************************************************************************/ +void sl_si91x_gpio_enable_clock(sl_si91x_gpio_select_clock_t clock); + +/***************************************************************************/ /** + * @brief Enable the selected group interrupts for either HP or ULP instance of GPIO peripheral. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n + * Use corresponding pad receiver API for corresponding GPIO instance. \n + * \ref sl_gpio_set_pin_mode() \n + * \ref sl_si91x_gpio_set_pin_direction() \n + * \ref sl_si91x_gpio_configure_group_interrupt(), for HP instance \n + * \ref sl_si91x_gpio_configure_ulp_group_interrupt, for ULP instance \n + * Use corresponding group interrupt configuration API for corresponding GPIO instance. + * @param[in] group_interrupt - GPIO group interrupt number of type + * \ref sl_si91x_group_interrupt_t + * @param[in] port - The port to associate with the pin. + * HP instance - PORT 0,1,2,3 + * ULP instance - PORT 4 + * @param[in] pin - The pin number on the port. + * HP instance has total 57 GPIO pins. Port 0, 1, 2 has 16 pins each. + * Port 3 has 9 pins. + * ULP instance has total 12 pins. + * @return None +*******************************************************************************/ +void sl_si91x_gpio_enable_group_interrupt(sl_si91x_group_interrupt_t group_interrupt, uint8_t port, uint8_t pin); + +/***************************************************************************/ /** + * @brief Disable the selected group interrupts for either HP or ULP instance of GPIO peripheral. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n + * Use corresponding pad receiver API for corresponding GPIO instance. \n + * \ref sl_gpio_set_pin_mode() \n + * \ref sl_si91x_gpio_set_pin_direction() \n + * \ref sl_si91x_gpio_configure_group_interrupt(), for HP instance \n + * \ref sl_si91x_gpio_configure_ulp_group_interrupt, for ULP instance \n + * Use corresponding group interrupt configuration API for corresponding GPIO instance. + * @param[in] group_interrupt - GPIO group interrupt number of type + * \ref sl_si91x_group_interrupt_t + * @param[in] port - The port to associate with the pin. + * HP instance - PORT 0,1,2,3 + * ULP instance - PORT 4 + * @param[in] pin - The pin number on the port. + * HP instance has total 57 GPIO pins. Port 0, 1, 2 has 16 pins each. + * Port 3 has 9 pins. + * ULP instance has total 12 pins. + * + * @return None +*******************************************************************************/ +void sl_si91x_gpio_disable_group_interrupt(sl_si91x_group_interrupt_t group_interrupt, uint8_t port, uint8_t pin); + +/***************************************************************************/ /** + * @brief Select the slew rate for the ULP instance of GPIO peripheral. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_enable_ulp_pad_receiver() \n + * @param[in] gpio_num - GPIO pin number to be use + * @param[in] slew_rate - slew rate of type \ref sl_si91x_gpio_slew_rate_t + * '0' - Slow\n + * '1' - Fast\n + * @return None + ******************************************************************************/ +void sl_si91x_gpio_select_ulp_pad_slew_rate(uint8_t gpio_num, sl_si91x_gpio_slew_rate_t slew_rate); + +/***************************************************************************/ /** + * @brief Select the drive strength for the ULP instance of GPIO peripheral. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_enable_ulp_pad_receiver() \n + * @param[in] gpio_num - GPIO pin number to be use + * @param[in] strength - Drive strength selector(E1,E2) of type + * \ref sl_si91x_gpio_driver_strength_select_t + * 0, for two_milli_amps (E1=0,E2=0)\n + * 1, for four_milli_amps (E1=0,E2=1)\n + * 2, for eight_milli_amps (E1=1,E2=0)\n + * 3, for twelve_milli_amps(E1=1,E2=1)\n + * @return None + ******************************************************************************/ +void sl_si91x_gpio_select_ulp_pad_driver_strength(uint8_t gpio_num, sl_si91x_gpio_driver_strength_select_t strength); + +/***************************************************************************/ /** + * @brief Select the driver-disabled state control for the ULP instance of GPIO peripheral. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_enable_ulp_pad_receiver() \n + * @param[in] gpio_num - GPIO pin number to be use + * @param[in] disable_state - driver disable state of type + * \ref sl_si91x_gpio_driver_disable_state_t + * 0, for HiZ (P1=0,P2=0)\n + * 1, for Pull up (P1=0,P2=1)\n + * 2, for Pull down (P1=1,P2=0)\n + * 3, for Repeater (P1=1,P2=1)\n + * @return None + ******************************************************************************/ +void sl_si91x_gpio_select_ulp_pad_driver_disable_state(uint8_t gpio_num, + sl_si91x_gpio_driver_disable_state_t disable_state); + +/***************************************************************************/ /** + * @brief Disable the receiver enable bit for the ULP instance of GPIO peripheral. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @param[in] gpio_num - GPIO pin number to be used + * @return None +*******************************************************************************/ +void sl_si91x_gpio_disable_ulp_pad_receiver(uint32_t gpio_num); + +/***************************************************************************/ /** + * @brief Enable the receiver enable bit for the ULP instance of GPIO peripheral. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @param[in] gpio_num - GPIO pin number to be used + * @return None +*******************************************************************************/ +void sl_si91x_gpio_enable_ulp_pad_receiver(uint8_t gpio_num); + +/***************************************************************************/ /** + * @brief Configure the MCU ULP instance pin interrupts with trigger type(level/edge) + * and register the callback function for interrupts. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_enable_ulp_pad_receiver() \n + * \ref sl_gpio_set_pin_mode() \n + * \ref sl_si91x_gpio_set_pin_direction() \n + * @param[in] interrupt_no - The interrupt number to trigger. + * @param[in] flags - Interrupt configuration flags of type + * \ref sl_si91x_gpio_interrupt_config_flag_t + * @param[in] pin - GPIO pin number + * @return None +*******************************************************************************/ +void sl_si91x_gpio_configure_ulp_pin_interrupt(uint8_t interrupt_no, + sl_si91x_gpio_interrupt_config_flag_t flags, + sl_si91x_gpio_pin_ulp_t pin); + +/***************************************************************************/ /** + * @brief Set the NPSS GPIO pin MUX(mode) to selected mode. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_select_uulp_npss_receiver() \n + * @param[in] pin - NPSS GPIO pin number(0 to 4) of type + * \ref sl_si91x_uulp_npss_mode_t + * @param[in] mode - NPSS GPIO MUX value + * @return none +*******************************************************************************/ +void sl_si91x_gpio_set_uulp_npss_pin_mux(uint8_t pin, sl_si91x_uulp_npss_mode_t mode); + +/***************************************************************************/ /** + * @brief Enable/disable the NPSS GPIO Input Buffer. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @param[in] pin - is NPSS GPIO pin number (0 to 4) + * @param[in] receiver - is enable/disable NPSS GPIO receiver of type + * \ref sl_si91x_gpio_receiver_t + * '1' - Enable\n + * '0' - Disable\n + * @return None + ******************************************************************************/ +void sl_si91x_gpio_select_uulp_npss_receiver(uint8_t pin, sl_si91x_gpio_receiver_t receiver); + +/***************************************************************************/ /** + * @brief Set the direction for the selected NPSS GPIO. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_select_uulp_npss_receiver() \n + * \ref sl_si91x_gpio_set_uulp_npss_pin_mux() \n + * @param[in] pin - is NPSS GPIO pin number (0 to 4) + * @param[in] direction - is direction value (Input / Output) of type + * \ref sl_si91x_gpio_direction_t + * '1' - Input Direction\n + * '0' - Output Direction\n + * @return None + ******************************************************************************/ +void sl_si91x_gpio_set_uulp_npss_direction(uint8_t pin, sl_si91x_gpio_direction_t direction); + +/***************************************************************************/ /** + * @brief Get the direction of the selected NPSS GPIO. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_select_uulp_npss_receiver() \n + * \ref sl_si91x_gpio_set_uulp_npss_pin_mux() \n + * \ref sl_si91x_gpio_set_uulp_npss_direction() \n + * @param[in] pin - is NPSS GPIO pin number(0...4) + * @return returns the GPIO pin direction + * - 1, Input Direction + * - 0, Output Direction +*******************************************************************************/ +uint8_t sl_si91x_gpio_get_uulp_npss_direction(uint8_t pin); + +/***************************************************************************/ /** + * @brief Control(set or clear) the NPSS GPIO pin value. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_select_uulp_npss_receiver() \n + * \ref sl_si91x_gpio_set_uulp_npss_pin_mux() \n + * \ref sl_si91x_gpio_set_uulp_npss_direction() \n + * @param[in] pin - is NPSS GPIO pin number (0...4) of type + * \ref sl_si91x_gpio_pin_value_t + * @param[in] pin_value - is NPSS GPIO pin value + * '1' - SET \n + * '0' - CLEAR \n + * @return None + ******************************************************************************/ +void sl_si91x_gpio_set_uulp_npss_pin_value(uint8_t pin, sl_si91x_gpio_pin_value_t pin_value); + +/***************************************************************************/ /** + * @brief Read the status of selected NPSS GPIO pin value. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_select_uulp_npss_receiver() \n + * \ref sl_si91x_gpio_set_uulp_npss_pin_mux() \n + * \ref sl_si91x_gpio_set_uulp_npss_direction() \n + * \ref sl_si91x_gpio_set_uulp_npss_pin_value() \n + * @param[in] pin - is NPSS GPIO pin number (0 to 4) + * @return returns the pin logical state of pin + * '0' - LOW \n + * '1' - HIGH \n + ******************************************************************************/ +uint8_t sl_si91x_gpio_get_uulp_npss_pin(uint8_t pin); + +/***************************************************************************/ /** + * @brief Select the NPSS GPIO polarity for generating interrupt. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @param[in] pin - is NPSS GPIO pin number (0 to 4) + * @param[in] polarity - GPIO polarity + * \ref sl_si91x_gpio_polarity_t + * '1' - High\n + * '0' - Low\n + * @return None + ******************************************************************************/ +void sl_si91x_gpio_select_uulp_npss_polarity(uint8_t pin, sl_si91x_gpio_polarity_t polarity); + +/***************************************************************************/ /** + * @brief Set the NPSS GPIO interrupt as a wake up source across sleep wakeups. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @param[in] npssgpio_interrupt - NPSS GPIO pin number (0 to 4) + * @return none +*******************************************************************************/ +void sl_si91x_gpio_set_uulp_npss_wakeup_interrupt(uint8_t npssgpio_interrupt); + +/***************************************************************************/ /** + * @brief Clear the UULP NPSS GPIO Interrupt as wake up source. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @param[in] npssgpio_interrupt - NPSS GPIO pin number (0 to 4) + * @return none +*******************************************************************************/ +void sl_si91x_gpio_clear_uulp_npss_wakeup_interrupt(uint8_t npssgpio_interrupt); + +/***************************************************************************/ /** + * @brief Mask the selected NPSS GPIO interrupt. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_set_uulp_pad_configuration() \n + * \ref sl_si91x_gpio_select_uulp_npss_receiver() \n + * \ref sl_si91x_gpio_set_uulp_npss_pin_mux() \n + * \ref sl_si91x_gpio_set_uulp_npss_direction() \n + * @param[in] npssgpio_interrupt - NPSS GPIO pin number (0 to 4) + * @return none +*******************************************************************************/ +void sl_si91x_gpio_mask_uulp_npss_interrupt(uint8_t npssgpio_interrupt); + +/***************************************************************************/ /** + * @brief Unmask the selected NPSS GPIO interrupt. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_set_uulp_pad_configuration() \n + * \ref sl_si91x_gpio_select_uulp_npss_receiver() \n + * \ref sl_si91x_gpio_set_uulp_npss_pin_mux() \n + * \ref sl_si91x_gpio_set_uulp_npss_direction() \n + * @param[in] npssgpio_interrupt - NPSS GPIO pin number (0 to 4) + * @return none +*******************************************************************************/ +void sl_si91x_gpio_unmask_uulp_npss_interrupt(uint8_t npssgpio_interrupt); + +/***************************************************************************/ /** + * @brief Clear the selected NPSS GPIO interrupt. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_set_uulp_pad_configuration() \n + * \ref sl_si91x_gpio_select_uulp_npss_receiver() \n + * \ref sl_si91x_gpio_set_uulp_npss_pin_mux() \n + * \ref sl_si91x_gpio_set_uulp_npss_direction() \n + * \ref sl_si91x_gpio_configure_uulp_interrupt() \n + * @param[in] npssgpio_interrupt - NPSS GPIO pin number (0 to 4) + * @return none +*******************************************************************************/ +void sl_si91x_gpio_clear_uulp_interrupt(uint8_t npssgpio_interrupt); + +/***************************************************************************/ /** + * @brief Get the current status of all the NPSS GPIO interrupt status. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_set_uulp_pad_configuration() \n + * \ref sl_si91x_gpio_select_uulp_npss_receiver() \n + * \ref sl_si91x_gpio_set_uulp_npss_pin_mux() \n + * \ref sl_si91x_gpio_set_uulp_npss_direction() \n + * \ref sl_si91x_gpio_configure_uulp_interrupt() \n + * @param[in] None + * @return returns the UULP INTR status. + * 1, interrupt has been raised\n + * 0, interrupt is masked or not raised\n + ******************************************************************************/ +uint8_t sl_si91x_gpio_get_uulp_interrupt_status(void); + +/***************************************************************************/ /** + * @brief Get the selected ULP instance GPIO pin interrupt status. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_enable_ulp_pad_receiver() \n + * \ref sl_gpio_set_pin_mode() \n + * \ref sl_si91x_gpio_set_pin_direction() \n + * \ref sl_si91x_gpio_configure_ulp_pin_interrupt() \n + * @param[in] flags : ULP GPIO interrupt sources. + * @return returns the ULP INTR status. + * 1, interrupt has been raised\n + * 0, interrupt is masked or not raised\n + ******************************************************************************/ +uint32_t sl_si91x_gpio_get_ulp_interrupt_status(uint32_t flags); + +/***************************************************************************/ /** + * @brief Clear the selected ULP instance GPIO pin interrupts. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_enable_ulp_pad_receiver() \n + * \ref sl_gpio_set_pin_mode() \n + * \ref sl_si91x_gpio_set_pin_direction() \n + * \ref sl_si91x_gpio_configure_ulp_pin_interrupt() \n + * @param[in] flags : ULP GPIO interrupt sources to clear. + * @return None +*******************************************************************************/ +void sl_si91x_gpio_clear_ulp_interrupt(uint32_t flags); + +/***************************************************************************/ /** + * @brief Clear the selected ULP instance group interrupt. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_enable_ulp_pad_receiver() \n + * \ref sl_gpio_set_pin_mode() \n + * \ref sl_si91x_gpio_set_pin_direction() \n + * \ref sl_si91x_gpio_configure_ulp_group_interrupt() \n + * Use corresponding group interrupt configuration API for corresponding GPIO instance. + * @param[in] group_interrupt - Group interrupt number of type + * \ref sl_si91x_group_interrupt_t + * @return None +*******************************************************************************/ +void sl_si91x_gpio_clear_ulp_group_interrupt(sl_si91x_group_interrupt_t group_interrupt); + +/***************************************************************************/ /** +* @brief Configure the UULP GPIO pin interrupt with interrupt type level or edge and registers callback function for interrupts. +* @pre \ref sl_si91x_gpio_enable_clock() \n +* \ref sl_si91x_gpio_set_uulp_pad_configuration() \n +* \ref sl_si91x_gpio_select_uulp_npss_receiver() \n +* \ref sl_si91x_gpio_set_uulp_npss_pin_mux() \n +* \ref sl_si91x_gpio_set_uulp_npss_direction() \n +* @param[in] flags - Interrupt configuration flags of type +* \ref sl_si91x_gpio_interrupt_config_flag_t +* @param[in] npssgpio_interrupt - NPSS GPIO pin number(0 to 4) +* @return None +*******************************************************************************/ +void sl_si91x_gpio_configure_uulp_interrupt(sl_si91x_gpio_interrupt_config_flag_t flags, uint8_t npssgpio_interrupt); + +/***************************************************************************/ /** + * @brief Configure the MCU ULP instance group interrupts with trigger type(level/edge), polarity(high/low),interrupt type(and/or) + * and register the callback function for interrupts. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_enable_ulp_pad_receiver() \n + * \ref sl_gpio_set_pin_mode() \n + * \ref sl_si91x_gpio_set_pin_direction() \n + * @param[in] configuration - configuration pointer to + * \ref sl_si91x_gpio_group_interrupt_config_t structure + * @return None +*******************************************************************************/ +void sl_si91x_gpio_configure_ulp_group_interrupt(sl_si91x_gpio_group_interrupt_config_t *configuration); + +/***************************************************************************/ /** + * @brief Verify assumptions and print message if the assumption is false. + * @param[in] file - File name + * @param[in] line - Line number + * @return None + ******************************************************************************/ +void sl_assert_failed(uint8_t *file, uint32_t line); + +/***************************************************************************/ /** + * Toggle the selected UULP pin status. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_select_uulp_npss_receiver() \n + * \ref sl_si91x_gpio_set_uulp_npss_pin_mux() \n + * \ref sl_si91x_gpio_set_uulp_npss_direction() \n + * @param[in] pin - UULP pin number to toggle + * @return None + ******************************************************************************/ +void sl_si91x_gpio_toggle_uulp_npss_pin(uint8_t pin); + +/***************************************************************************/ /** + * @brief Indicate UULP GPIO PAD configuration. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @param[in] pad_config : PAD configuration pointer to \ref uulp_pad_config_t structure + * @return None +*******************************************************************************/ +void sl_si91x_gpio_set_uulp_pad_configuration(uulp_pad_config_t *pad_config); + +/***************************************************************************/ /** + * @brief Get the release, SQA, and development version numbers of the GPIO peripheral. + * @param[in] None + * @return returns structure of type \ref sl_si91x_gpio_version_t +*******************************************************************************/ +sl_si91x_gpio_version_t sl_si91x_gpio_get_version(void); + +/** @} (end addtogroup GPIO) */ + +#ifdef __cplusplus +} +#endif + +#endif ///< SL_SI91X_GPIO_PERIPHERAL_H +/**************************************************************************************************/ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/inc/sl_si91x_gpio_common.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/inc/sl_si91x_gpio_common.h new file mode 100644 index 000000000..9e695318a --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/inc/sl_si91x_gpio_common.h @@ -0,0 +1,406 @@ +/***************************************************************************/ /** + * @file sl_si91x_gpio_common.h + * @brief General Purpose IO (GPIO) API implementation + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licenser of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be mis-represented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * mis-represented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + * ******************************************************************************/ +#ifndef SL_SI91X_GPIO_COMMONH +#define SL_SI91X_GPIO_COMMONH + +#ifdef __cplusplus +extern "C" { +#endif + +//// Includes +/// +#include "si91x_device.h" +/***************************************************************************/ /** + * @addtogroup GPIO + * @ingroup SI91X_PERIPHERAL_APIS + * @{ + * + ******************************************************************************/ +/******************************************************************************* + *************************** Defines / Macros ******************************** + ******************************************************************************/ +#define PAD_REG_BASE 0x46004000UL ///< PAD configuration register base address +#define NPSS_INT_BASE 0x12080000UL ///< UULP INTR base address +#define ULP_PAD_REG_BASE 0x2404A000UL ///< ULP PAD configuration base address + +#define GPIO ((EGPIO_Type *)EGPIO_BASE) ///< MCU HP base address +#define ULP_GPIO ((EGPIO_Type *)EGPIO1_BASE) ///< MCU ULP base address +#define UULP_GPIO_FSM ((MCU_FSM_Type *)MCU_FSM_BASE) ///< SLEEP FSM base address +#define UULP_GPIO ((MCU_RET_Type *)MCU_RET_BASE) ///< MCU retention base address + +#define PAD_REG(x) ((PAD_CONFIG_Type *)(PAD_REG_BASE + (4 * x))) ///< PAD configuration register for GPIO_n(n = 0 t0 63) +#define ULP_PAD_CONFIG0_REG ((ULP_PAD_CONFIG_Type0 *)(ULP_PAD_REG_BASE + 0x0)) ///< ULP PAD configuration register 0 +#define ULP_PAD_CONFIG1_REG ((ULP_PAD_CONFIG_Type1 *)(ULP_PAD_REG_BASE + 0x4)) ///< ULP PAD configuration register 1 +#define ULP_PAD_CONFIG2_REG ((ULP_PAD_CONFIG_Type2 *)(ULP_PAD_REG_BASE + 0x8)) ///< ULP PAD configuration register 2 + +#define UULP_PAD_CONFIG_REG(x) \ + ((UULP_PAD_CONFIG_Type *)(0x2404861C + 4 * x)) ///< UULP V_bat PAD configuration base address +#define PADSELECTION \ + (*(volatile uint32_t *)(0x41300000 + 0x610)) ///< PAD selection (0 to 21) A value of 1 on this gives control to M4SS +#define PADSELECTION_1 \ + (*(volatile uint32_t *)(0x41300000 + 0x618)) ///< PAD selection (22 to 33) A value of 1 on this gives control to M4SS +#define HOST_PADS_GPIO_MODE (*(volatile uint32_t *)(0x46008000 + 0x44)) ///< MISC host base address +#define ULP_PAD_CONFIG_REG (*(volatile uint32_t *)(0x2404A008)) ///< ULP PAD register + +#define GPIO_NPSS_INTERRUPT_MASK_SET_REG \ + (*(volatile uint32_t *)(NPSS_INT_BASE + 0x00)) ///< NPSS mask set register base address +#define GPIO_NPSS_INTERRUPT_MASK_CLR_REG \ + (*(volatile uint32_t *)(NPSS_INT_BASE + 0x04)) ///< NPSS mask clear register base address +#define GPIO_NPSS_INTERRUPT_CLEAR_REG \ + (*(volatile uint32_t *)(NPSS_INT_BASE + 0x08)) ///< NPSS clear register base address +#define GPIO_NPSS_INTERRUPT_STATUS_REG \ + (*(volatile uint32_t *)(NPSS_INT_BASE + 0x0C)) ///< NPSS status register base address +#define GPIO_NPSS_GPIO_CONFIG_REG \ + (*(volatile uint32_t *)(NPSS_INT_BASE + 0x10)) ///< NPSS GPIO configuration register base address +#define UULP_GPIO_STATUS (*(volatile uint32_t *)(NPSS_INT_BASE + 0x14)) ///< UULP GPIO status base address +#define GPIO_25_30_CONFIG_REG (*(volatile uint32_t *)(0X46008000 + 0x0C)) ///< GPIO(25-30) pin configuration register + +#define CLR 0 +#define SET 1 + +#define SL_DEBUG_ASSERT + +#define NIBBLE_SHIFT 4 ///< Nibble shift for interrupt +#define BYTE_SHIFT 8 ///< Byte shift for interrupt +#define WORD_SHIFT 16 ///< Word shift for interrupt +#define LSB_WORD_MASK 0x00FF ///< GPIO LSB word mask +#define LSB_NIBBLE_MASK 0x0F ///< GPIO LSB nibble mask + +#define MAX_GPIO_PORT_PIN 16 ///< GPIO maximum port pins +#define HOST_PAD 12 ///< GPIO Host PAD + +#define GPIO_PA_COUNT 16 ///< GPIO port A maximum pins +#define GPIO_PB_COUNT 16 ///< GPIO port B maximum pins +#define GPIO_PC_COUNT 16 ///< GPIO port C maximum pins +#define GPIO_PD_COUNT 9 ///< GPIO port D maximum pins +#define GPIO_PE_COUNT 12 ///< GPIO port E maximum pins + +#define GPIO_PA_MASK 0xFFFFUL ///< GPIO port A mask +#define GPIO_PB_MASK 0xFFFFUL ///< GPIO port B mask +#define GPIO_PC_MASK 0xFFFFUL ///< GPIO port C mask +#define GPIO_PD_MASK 0x01FFUL ///< GPIO port D mask + +#define SL_PERIPHERAL_CLK M4CLK ///< GPIO instance clock + +#define UNUSED_VAR(expr) ((void)(expr)) + +#define GPIO_PA_PIN_MAX_VALIDATE 75 ///< GPIO port A maximum pins to validate +#define GPIO_PB_PIN_MAX_VALIDATE 59 ///< GPIO port B maximum pins to validate +#define GPIO_PC_PIN_MAX_VALIDATE 43 ///< GPIO port C maximum pins to validate +#define GPIO_PD_PIN_MAX_VALIDATE 27 ///< GPIO port D maximum pins to validate + +#ifdef SL_DEBUG_ASSERT +#define SL_GPIO_ASSERT(expr) ((expr) ? (void)0U : sl_assert_failed((uint8_t *)__FILE__, __LINE__)) +#else +#define SL_GPIO_ASSERT(expr) ((void)(expr)) +#endif + +#define SL_GPIO_VALIDATE_STRENGTH(strength) (strength > 3 ? 0 : 1) ///< Validate driver strength +#define SL_GPIO_VALIDATE_PARAMETER(value) (value > 1 ? 0 : 1) ///< Validate GPIO parameters +#define SL_GPIO_VALIDATE_DISABLE_STATE(disable_state) (disable_state > 3 ? 0 : 1) ///< Validate driver disable state +#define SL_GPIO_VALIDATE_PAD(pad_num) ((pad_num > 34) && (pad_num < 1) ? 0 : 1) ///< Validate GPIO HP pad selection +#define SL_GPIO_VALIDATE_PIN(pin_num) ((pin_num > 63) ? 0 : 1) ///< Validate GPIO HP pin number +#define SL_GPIO_VALIDATE_FLAG(flag) ((flag > 0x0F) ? 0 : 1) ///< Validate GPIO flags +#define SL_GPIO_VALIDATE_ULP_INTR(ulp_intr) ((ulp_intr > 12) ? 0 : 1) ///< Validate ULP interrupts +#define SL_GPIO_VALIDATE_ULP_PIN(pin_num) ((pin_num > 12) ? 0 : 1) ///< Validate ULP pins +#define SL_GPIO_VALIDATE_UULP_PIN(pin_num) ((pin_num) > 5 ? 0 : 1) ///< Validate UULP pins +#define SL_GPIO_VALIDATE_MODE_PARAMETER(mode) ((mode) > 10 ? 0 : 1) ///< Validate UULP, ULP mode +#define SL_GPIO_VALIDATE_UULP_INTR(interrupt) ((interrupt) > 16 ? 0 : 1) ///< Validate UULP interrupt +#define SL_GPIO_VALIDATE_PORT(port) ((port) > 5 ? 0 : 1) ///< Validate GPIO port +#define SL_GPIO_VALIDATE_MODE(mode) ((mode) > 15 ? 0 : 1) ///< Validate GPIO mode +#define SL_GPIO_VALIDATE_INTR(interrupt) ((interrupt > 8) ? 0 : 1) ///< Validate GPIO interrupt +///< Validate GPIO port and pin +#define SL_GPIO_NDEBUG_PORT_PIN(port, pin) \ + (port == 0 ? ((pin > GPIO_PA_PIN_MAX_VALIDATE) ? 0 : 1) \ + : port == 1 ? ((pin > GPIO_PB_PIN_MAX_VALIDATE) ? 0 : 1) \ + : port == 2 ? ((pin > GPIO_PC_PIN_MAX_VALIDATE) ? 0 : 1) \ + : port == 3 ? ((pin > GPIO_PD_PIN_MAX_VALIDATE) ? 0 : 1) \ + : 0) + +#define SL_GPIO_VALIDATE_ULP_PORT_PIN(port, pin) (port == 4 ? ((pin > 11) ? 0 : 1) : 0) ///< Validate ULP port and pin +#define SL_GPIO_VALIDATE_UULP_PORT_PIN(port, pin) (port == 5 ? ((pin > 5) ? 0 : 1) : 0) ///< Validate UULP port and pin + +#define GRP_IRQ0_Handler IRQ050_Handler ///< GPIO Group Interrupt 0 +#define GRP_IRQ1_Handler IRQ051_Handler ///< GPIO Group Interrupt 1 + +#define PIN_IRQ0_Handler IRQ052_Handler ///< GPIO Pin Interrupt 0 +#define PIN_IRQ1_Handler IRQ053_Handler ///< GPIO Pin Interrupt 1 +#define PIN_IRQ2_Handler IRQ054_Handler ///< GPIO Pin Interrupt 2 +#define PIN_IRQ3_Handler IRQ055_Handler ///< GPIO Pin Interrupt 3 +#define PIN_IRQ4_Handler IRQ056_Handler ///< GPIO Pin Interrupt 4 +#define PIN_IRQ5_Handler IRQ057_Handler ///< GPIO Pin Interrupt 5 +#define PIN_IRQ6_Handler IRQ058_Handler ///< GPIO Pin Interrupt 6 +#define PIN_IRQ7_Handler IRQ059_Handler ///< GPIO Pin Interrupt 7 + +#define UULP_PIN_IRQ_Handler IRQ021_Handler ///< UULP Pin Interrupt 0 + +#define ULP_PIN_IRQ_Handler IRQ018_Handler ///< ULP Pin Interrupt +#define ULP_GROUP_IRQ_Handler IRQ019_Handler ///< ULP Group Interrupt + +#define PIN_INTR_0 0 ///< HP GPIO pin interrupt 0 +#define PIN_INTR_1 1 ///< HP GPIO pin interrupt 1 +#define PIN_INTR_2 2 ///< HP GPIO pin interrupt 2 +#define PIN_INTR_3 3 ///< HP GPIO pin interrupt 3 +#define PIN_INTR_4 4 ///< HP GPIO pin interrupt 4 +#define PIN_INTR_5 5 ///< HP GPIO pin interrupt 5 +#define PIN_INTR_6 6 ///< HP GPIO pin interrupt 6 +#define PIN_INTR_7 7 ///< HP GPIO pin interrupt 7 + +#define UULP_MASK 0x00 ///< UULP GPIO pin mask +#define ULP_STATUS 0x01 ///< ULP GPIO pin status +#define UULP_INTR_1 0x01 ///< UULP GPIO pin interrupt 1 +#define UULP_INTR_2 0x02 ///< UULP GPIO pin interrupt 2 +#define UULP_INTR_3 0x04 ///< UULP GPIO pin interrupt 3 +#define UULP_INTR_4 0x08 ///< UULP GPIO pin interrupt 4 +#define UULP_INTR_5 0x10 ///< UULP GPIO pin interrupt 5 + +#define ULP_PIN_INTR_0 0 ///< ULP GPIO pin interrupt 0 +#define ULP_PIN_INTR_1 1 ///< ULP GPIO pin interrupt 1 +#define ULP_PIN_INTR_2 2 ///< ULP GPIO pin interrupt 2 +#define ULP_PIN_INTR_3 3 ///< ULP GPIO pin interrupt 3 +#define ULP_PIN_INTR_4 4 ///< ULP GPIO pin interrupt 4 +#define ULP_PIN_INTR_5 5 ///< ULP GPIO pin interrupt 5 +#define ULP_PIN_INTR_6 6 ///< ULP GPIO pin interrupt 6 +#define ULP_PIN_INTR_7 7 ///< ULP GPIO pin interrupt 7 + +#define ULP_GROUP_INTR_0 0 ///< ULP GPIO group interrupt 0 +#define ULP_GROUP_INTR_1 1 ///< ULP GPIO group interrupt 1 + +#define MAX_GPIO_PIN_INT 8 ///< Maximum HP GPIO pin interrupts + +#define PININT0_NVIC_NAME EGPIO_PIN_0_IRQn ///< HP GPIO pin interrupt 0 number +#define PININT1_NVIC_NAME EGPIO_PIN_1_IRQn ///< HP GPIO pin interrupt 1 number +#define PININT2_NVIC_NAME EGPIO_PIN_2_IRQn ///< HP GPIO pin interrupt 2 number +#define PININT3_NVIC_NAME EGPIO_PIN_3_IRQn ///< HP GPIO pin interrupt 3 number +#define PININT4_NVIC_NAME EGPIO_PIN_4_IRQn ///< HP GPIO pin interrupt 4 number +#define PININT5_NVIC_NAME EGPIO_PIN_5_IRQn ///< HP GPIO pin interrupt 5 number +#define PININT6_NVIC_NAME EGPIO_PIN_6_IRQn ///< HP GPIO pin interrupt 6 number +#define PININT7_NVIC_NAME EGPIO_PIN_7_IRQn ///< HP GPIO pin interrupt 7 number + +#define GROUP_0_INTERRUPT_NAME EGPIO_GROUP_0_IRQn ///< HP GPIO group interrupt 1 number +#define GROUP_1_INTERRUPT_NAME EGPIO_GROUP_1_IRQn ///< HP GPIO group interrupt 2 number + +#define ULP_PININT0_NVIC_NAME ULP_EGPIO_PIN_IRQn ///< ULP GPIO pin interrupt number +#define ULP_GROUP_INTERRUPT_NAME ULP_EGPIO_GROUP_IRQn ///< ULP GPIO group interrupt number + +#define UULP_PININT_NVIC_NAME NPSS_TO_MCU_GPIO_INTR_IRQn ///< UULP GPIO pin interrupt number + +#define SL_GPIO_GROUP_INTERRUPT_OR 1 ///< GPIO group interrupt AND/OR +#define SL_GPIO_GROUP_INTERRUPT_WAKEUP 4 ///< GPIO group interrupt wakeup +#define SL_GPIO_ULP_PORT 4 ///< ULP GPIO port number +#define SL_GPIO_UULP_PORT 5 ///< Initializing UULP GPIO port value +#define SL_ULP_GPIO_PORT 4 ///< Refers to ULP Port + +#define _MODE0 0 ///< GPIO mode 0 +#define _MODE1 1 ///< GPIO mode 1 +#define _MODE2 2 ///< GPIO mode 2 +#define _MODE3 3 ///< GPIO mode 3 +#define _MODE4 4 ///< GPIO mode 4 +#define _MODE5 5 ///< GPIO mode 5 +#define _MODE6 6 ///< GPIO mode 6 +#define _MODE7 7 ///< GPIO mode 7 +#define _MODE8 8 ///< GPIO mode 8 +#define _MODE9 9 ///< GPIO mode 9 +#define _MODE10 10 ///< GPIO mode 10 +#define _MODE14 14 ///< GPIO mode 14 + +#define _GPIO_P_MODEL_MODE0_DISABLED 0x00000000UL ///< Mode DISABLED for GPIO_P_MODEL +#define _GPIO_P_MODEL_MODE0_INPUT 0x00000001UL ///< Mode INPUT for GPIO_P_MODEL +#define _GPIO_P_MODEL_MODE0_INPUTPULL 0x00000002UL ///< Mode INPUTPULL for GPIO_P_MODEL +#define _GPIO_P_MODEL_MODE0_INPUTPULLFILTER 0x00000003UL ///< Mode INPUTPULLFILTER for GPIO_P_MODEL +#define _GPIO_P_MODEL_MODE0_PUSHPULL 0x00000004UL ///< Mode PUSHPULL for GPIO_P_MODEL +#define _GPIO_P_MODEL_MODE0_PUSHPULLALT 0x00000005UL ///< Mode PUSHPULLALT for GPIO_P_MODEL +#define _GPIO_P_MODEL_MODE0_WIREDOR 0x00000006UL ///< Mode WIREDOR for GPIO_P_MODEL +#define _GPIO_P_MODEL_MODE0_WIREDORPULLDOWN 0x00000007UL ///< Mode WIREDORPULLDOWN for GPIO_P_MODEL +#define _GPIO_P_MODEL_MODE0_WIREDAND 0x00000008UL ///< Mode WIREDAND for GPIO_P_MODEL +#define _GPIO_P_MODEL_MODE0_WIREDANDFILTER 0x00000009UL ///< Mode WIREDANDFILTER for GPIO_P_MODEL +#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUP 0x0000000AUL ///< Mode WIREDANDPULLUP for GPIO_P_MODEL +#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER 0x0000000BUL ///< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL +#define _GPIO_P_MODEL_MODE0_WIREDANDALT 0x0000000CUL ///< Mode WIREDANDALT for GPIO_P_MODEL +#define _GPIO_P_MODEL_MODE0_WIREDANDALTFILTER 0x0000000DUL ///< Mode WIREDANDALTFILTER for GPIO_P_MODEL +#define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP 0x0000000EUL ///< Mode WIREDANDALTPULLUP for GPIO_P_MODEL +#define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER 0x0000000FUL ///< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL + +#define GPIO_P_MODEL_MODE0_DISABLED (_GPIO_P_MODEL_MODE0_DISABLED << 0) ///< Shifted mode DISABLED for GPIO_P_MODEL +#define GPIO_P_MODEL_MODE0_INPUT (_GPIO_P_MODEL_MODE0_INPUT << 0) ///< Shifted mode INPUT for GPIO_P_MODEL +#define GPIO_P_MODEL_MODE0_INPUTPULL (_GPIO_P_MODEL_MODE0_INPUTPULL << 0) ///< Shifted mode INPUTPULL for GPIO_P_MODEL +#define GPIO_P_MODEL_MODE0_INPUTPULLFILTER \ + (_GPIO_P_MODEL_MODE0_INPUTPULLFILTER << 0) ///< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL +#define GPIO_P_MODEL_MODE0_PUSHPULL (_GPIO_P_MODEL_MODE0_PUSHPULL << 0) ///< Shifted mode PUSHPULL for GPIO_P_MODEL +#define GPIO_P_MODEL_MODE0_PUSHPULLALT \ + (_GPIO_P_MODEL_MODE0_PUSHPULLALT << 0) ///< Shifted mode PUSHPULLALT for GPIO_P_MODEL +#define GPIO_P_MODEL_MODE0_WIREDOR (_GPIO_P_MODEL_MODE0_WIREDOR << 0) ///< Shifted mode WIREDOR for GPIO_P_MODEL +#define GPIO_P_MODEL_MODE0_WIREDORPULLDOWN \ + (_GPIO_P_MODEL_MODE0_WIREDORPULLDOWN << 0) ///< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL +#define GPIO_P_MODEL_MODE0_WIREDAND (_GPIO_P_MODEL_MODE0_WIREDAND << 0) ///< Shifted mode WIREDAND for GPIO_P_MODEL +#define GPIO_P_MODEL_MODE0_WIREDANDFILTER \ + (_GPIO_P_MODEL_MODE0_WIREDANDFILTER << 0) ///< Shifted mode WIREDANDFILTER for GPIO_P_MODEL +#define GPIO_P_MODEL_MODE0_WIREDANDPULLUP \ + (_GPIO_P_MODEL_MODE0_WIREDANDPULLUP << 0) ///< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL +#define GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER \ + (_GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER << 0) ///< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL +#define GPIO_P_MODEL_MODE0_WIREDANDALT \ + (_GPIO_P_MODEL_MODE0_WIREDANDALT << 0) ///< Shifted mode WIREDANDALT for GPIO_P_MODEL +#define GPIO_P_MODEL_MODE0_WIREDANDALTFILTER \ + (_GPIO_P_MODEL_MODE0_WIREDANDALTFILTER << 0) ///< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL +#define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP \ + (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP << 0) ///< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL +#define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER \ + (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER << 0) ///< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL + +#define GPIO_PAD_0 0 ///< GPIO PAD number 0 +#define GPIO_PAD_3 3 ///< GPIO PAD number 3 +#define GPIO_PAD_4 4 ///< GPIO PAD number 4 +#define GPIO_PAD_7 7 ///< GPIO PAD number 7 +#define GPIO_PAD_8 8 ///< GPIO PAD number 8 + +#define HOST_PAD_SELECT 12 ///< GPIO Host PAD selection +#define PAD_SELECT 22 ///< GPIO PAD number 22 +#define HOST_PAD_MIN 25 ///< GPIO Host PAD number 25 +#define HOST_PAD_MAX 30 ///< GPIO Host PAD number 30 + +#define PRIORITY_19 19 ///< GPIO ulp group Interrupt priority +#define PRIORITY_21 21 ///< GPIO uulp group Interrupt priority +#define PRIORITY_50 50 ///< GPIO m4 group 0 Interrupt priority +#define PRIORITY_51 51 ///< GPIO m4 group 1 Interrupt priority + +#define ULP_PORT_NUM 0 ///< GPIO ULP port number +#define UULP_PIN_MASK 0x1F ///< GPIO UULP pin mask + +#define BIT_0 0 ///< GPIO bit 0 in configuration register +#define BIT_8 8 ///< GPIO bit 8 in configuration register +#define BIT_16 16 ///< GPIO bit 16 in configuration register +#define BIT_24 24 ///< GPIO bit 24 in configuration register + +#define PORT_MASK 0xFFFF ///< GPIO port mask +#define INTR_CLR 0x07 ///< GPIO interrupt clear +#define INTERRUPT_MASK 0x0F ///< GPIO interrupt mask +#define MASK_CTRL 0x03 +#define MASK_INTR 0x01 ///< GPIO interrupt mask + +/** =========================================================================================================================== **/ +/** ================ GPIO ==================**/ +/** =========================================================================================================================== **/ +///@brief HP GPIO PAD configuration register fields +typedef struct { + union { + __IOM uint32_t PAD_CONFIG_REG; ///< (@ 0x46004000) GPIO PAD configuration register + + struct { + __IOM uint32_t PADCONFIG_E1_E2 : 2; ///< [1..0] Drive strength selector + __IOM uint32_t PADCONFIG_POS : 1; ///< [2..2] Power-on-Start enable + __IOM uint32_t PADCONFIG_SMT : 1; ///< [3..3] Active high Schmitt trigger (Hysteresis) select + __IOM uint32_t PADCONFIG_REN : 1; ///< [4..4] Active high receiver enable + __IOM uint32_t PADCONFIG_SR : 1; ///< [5..5] Slew Rate Control + __IOM uint32_t PADCONFIG_P1_P2 : 2; ///< [7..6] Driver disabled state control + __IOM uint32_t RESERVED1 : 24; ///< [31..8] Reserved1 + } GPIO_PAD_CONFIG_REG_b; + }; +} PAD_CONFIG_Type; + +///@brief UULP GPIO PAD configuration register fields +typedef struct { + union { + __IOM uint32_t UULP_PAD_CONFIG_REG; ///< (@ 0x2404861C) UULP VBAT GPIO configuration register + + struct { + __IOM uint32_t GPIO_MODE : 3; ///< [2..0] GPIO Mode for UULP_VBAT_GPIO_n(n=0:4) + __IOM uint32_t GPIO_REN : 1; ///< [3..3] Receiver of PAD enable + __IOM uint32_t GPIO_OEN : 1; ///< [4..4] Direction of PAD + __IOM uint32_t GPIO_OUTPUT : 1; ///< [5..5] Value driven on PAD in OUTPUT mode + __IOM uint32_t GPIO_PAD_SELECT : 1; ///< [6..6] PAD selection between M4,TA + __IOM uint32_t RESERVED : 1; ///< [7..7] Reserved + __IOM uint32_t GPIO_POLARITY : 1; ///< [8..8] Polarity of UULP GPIO + __IOM uint32_t RESERVED1 : 23; ///< [31..9] Reserved1 + } UULP_GPIO_PAD_CONFIG_REG_b; + }; +} UULP_PAD_CONFIG_Type; + +///@brief ULP GPIO PAD configuration register0 fields +typedef struct { + union { + __IOM uint32_t ULP_PAD_CONFIG_REG0; + + struct { + __IOM uint32_t PADCONFIG_E1_E2_1 : 2; ///< [1..0] Drive strength selector for ULP_GPIO_0 - ULP_GPIO_3 + __IOM uint32_t PADCONFIG_POS_1 : 1; ///< [2..2] Power on start enable for ULP_GPIO_0 - ULP_GPIO_3 + __IOM uint32_t PADCONFIG_SMT_1 : 1; ///< [3..3] Active high schmitt trigger for ULP_GPIO_0 - ULP_GPIO_3 + __IOM uint32_t RESERVED : 1; ///< [4..4] Reserved + __IOM uint32_t PADCONFIG_SR_1 : 1; ///< [5..5] Slew rate control for ULP_GPIO_0 - ULP_GPIO_3 + __IOM uint32_t PADCONFIG_P1_P2_1 : 2; ///< [7..6] Driver disabled state control for ULP_GPIO_0 - ULP_GPIO_3 + __IOM uint32_t PADCONFIG_E1_E2_2 : 2; ///< [9..8] Drive strength selector for ULP_GPIO_4 - ULP_GPIO_7 + __IOM uint32_t PADCONFIG_POS_2 : 1; ///< [10..10] Power on start enable for ULP_GPIO_4 - ULP_GPIO_7 + __IOM uint32_t PADCONFIG_SMT_2 : 1; ///< [11..11] Active high schmitt trigger for ULP_GPIO_4 - ULP_GPIO_7 + __IOM uint32_t RESERVED1 : 1; ///< [12..12] Reserved1 + __IOM uint32_t PADCONFIG_SR_2 : 1; ///< [13..13] Slew rate control for ULP_GPIO_4 - ULP_GPIO_7 + __IOM uint32_t PADCONFIG_P1_P2_2 : 2; ///< [15..14] Driver disabled state control for ULP_GPIO_4 - ULP_GPIO_7 + __IOM uint32_t RESERVED2 : 16; ///< [31..16] Reserved2 + } ULP_GPIO_PAD_CONFIG_REG_0; + }; +} ULP_PAD_CONFIG_Type0; + +///@brief ULP GPIO PAD configuration register1 fields +typedef struct { + union { + __IOM uint32_t ULP_PAD_CONFIG_REG1; + + struct { + __IOM uint32_t PADCONFIG_E1_E2_1 : 2; ///< [1..0] Drive strength selector for ULP_GPIO_8 - ULP_GPIO_11 + __IOM uint32_t PADCONFIG_POS_1 : 1; ///< [2..2] Power on start enable for ULP_GPIO_8 - ULP_GPIO_11 + __IOM uint32_t PADCONFIG_SMT_1 : 1; ///< [3..3] Active high schmitt trigger for ULP_GPIO_8 - ULP_GPIO_11 + __IOM uint32_t RESERVED : 1; ///< [4..4] Reserved + __IOM uint32_t PADCONFIG_SR_1 : 1; ///< [5..5] Slew rate control for ULP_GPIO_8 - ULP_GPIO_11 + __IOM uint32_t PADCONFIG_P1_P2_1 : 2; ///< [7..6] Driver disabled state control for ULP_GPIO_8 - ULP_GPIO_11 + __IOM uint32_t RESERVED1 : 8; ///< [15..8] Reserved1 + __IOM uint32_t RESERVED2 : 16; ///< [31..16] Reserved2 + } ULP_GPIO_PAD_CONFIG_REG_1; + }; +} ULP_PAD_CONFIG_Type1; + +///@brief ULP GPIO PAD configuration register2 fields +typedef struct { + union { + __IOM uint32_t ULP_PAD_CONFIG_REG2; + + struct { + __IOM uint32_t PADCONFIG_REN : 12; ///< [11..0] Active high receiver enable for ULP_GPIO_11 - ULP_GPIO_0 + __IOM uint32_t RESERVED : 20; ///< [31..12] Reserved + } ULP_GPIO_PAD_CONFIG_REG_2; + }; +} ULP_PAD_CONFIG_Type2; + +/** @} (end addtogroup GPIO) */ + +#ifdef __cplusplus +} +#endif + +#endif ///< SL_SI91X_GPIO_COMMONH + /**************************************************************************************************/ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/inc/sl_si91x_peripheral_gpio.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/inc/sl_si91x_peripheral_gpio.h new file mode 100644 index 000000000..2fcb2fc46 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/inc/sl_si91x_peripheral_gpio.h @@ -0,0 +1,811 @@ +/***************************************************************************/ /** + * @file sl_si91x_peripheral_gpio.h + * @brief General Purpose IO (GPIO) peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licenser of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be miss represented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * miss represented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_PERIPHERAL_GPIO_H +#define SL_PERIPHERAL_GPIO_H + +#if !defined(GPIO_PRESENT) +#include "sl_si91x_gpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************/ /** + * @addtogroup GPIO-PERIPHERAL-DRIVER GPIO Peripheral Driver + * @ingroup SI91X_PERIPHERAL_APIS + * @{ + * + ******************************************************************************/ +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ +#define _GPIO_PORT_A_PIN_COUNT GPIO_PA_COUNT ///< GPIO port A maximum pins +#define _GPIO_PORT_B_PIN_COUNT GPIO_PB_COUNT ///< GPIO port B maximum pins +#define _GPIO_PORT_C_PIN_COUNT GPIO_PC_COUNT ///< GPIO port C maximum pins +#define _GPIO_PORT_D_PIN_COUNT GPIO_PD_COUNT ///< GPIO port D maximum pins +#define _GPIO_PORT_E_PIN_COUNT 0 +#define _GPIO_PORT_F_PIN_COUNT 0 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 + +#define _GPIO_PORT_A_PIN_MASK (GPIO_PA_MASK) ///< GPIO port A pin mask +#define _GPIO_PORT_B_PIN_MASK (GPIO_PB_MASK) ///< GPIO port B pin mask +#define _GPIO_PORT_C_PIN_MASK (GPIO_PC_MASK) ///< GPIO port C pin mask +#define _GPIO_PORT_D_PIN_MASK (GPIO_PD_MASK) ///< GPIO port D pin mask +#define _GPIO_PORT_E_PIN_MASK 0x0000UL +#define _GPIO_PORT_F_PIN_MASK 0x0000UL +#define _GPIO_PORT_G_PIN_MASK 0x0000UL +#define _GPIO_PORT_H_PIN_MASK 0x0000UL +#define _GPIO_PORT_I_PIN_MASK 0x0000UL +#define _GPIO_PORT_J_PIN_MASK 0x0000UL +#define _GPIO_PORT_K_PIN_MASK 0x0000UL + +///< GPIO pins selection for selected port +#define _GPIO_PORT_SIZE(port) \ + ((port) == 0 ? _GPIO_PORT_A_PIN_COUNT \ + : (port) == 1 ? _GPIO_PORT_B_PIN_COUNT \ + : (port) == 2 ? _GPIO_PORT_C_PIN_COUNT \ + : (port) == 3 ? _GPIO_PORT_D_PIN_COUNT \ + : (port) == 4 ? _GPIO_PORT_E_PIN_COUNT \ + : (port) == 5 ? _GPIO_PORT_F_PIN_COUNT \ + : (port) == 6 ? _GPIO_PORT_G_PIN_COUNT \ + : (port) == 7 ? _GPIO_PORT_H_PIN_COUNT \ + : (port) == 8 ? _GPIO_PORT_I_PIN_COUNT \ + : (port) == 9 ? _GPIO_PORT_J_PIN_COUNT \ + : (port) == 10 ? _GPIO_PORT_K_PIN_COUNT \ + : 0) + +///< GPIO pins mask for selected port +#define _GPIO_PORT_MASK(port) \ + (((int)port) == 0 ? _GPIO_PORT_A_PIN_MASK \ + : ((int)port) == 1 ? _GPIO_PORT_B_PIN_MASK \ + : ((int)port) == 2 ? _GPIO_PORT_C_PIN_MASK \ + : ((int)port) == 3 ? _GPIO_PORT_D_PIN_MASK \ + : ((int)port) == 4 ? _GPIO_PORT_E_PIN_MASK \ + : ((int)port) == 5 ? _GPIO_PORT_F_PIN_MASK \ + : ((int)port) == 6 ? _GPIO_PORT_G_PIN_MASK \ + : ((int)port) == 7 ? _GPIO_PORT_H_PIN_MASK \ + : ((int)port) == 8 ? _GPIO_PORT_I_PIN_MASK \ + : ((int)port) == 9 ? _GPIO_PORT_J_PIN_MASK \ + : ((int)port) == 10 ? _GPIO_PORT_K_PIN_MASK \ + : 0UL) + +#define SL_GPIO_PORT_VALID(port) (_GPIO_PORT_MASK(port) != 0x0UL) ///< Validation of GPIO port. + +#define SL_GPIO_PORT_PIN_VALID(port, pin) \ + ((((_GPIO_PORT_MASK(port)) >> (pin)) & 0x1UL) == 0x1UL) ///< Validating GPIO port and pin + +#define GPIO_PIN_MAX 15 ///< Highest GPIO pin number. + +///@brief Highest GPIO port number. +#if (_GPIO_PORT_K_PIN_COUNT > 0) +#define GPIO_PORT_MAX 10 +#elif (_GPIO_PORT_J_PIN_COUNT > 0) +#define GPIO_PORT_MAX 9 +#elif (_GPIO_PORT_I_PIN_COUNT > 0) +#define GPIO_PORT_MAX 8 +#elif (_GPIO_PORT_H_PIN_COUNT > 0) +#define GPIO_PORT_MAX 7 +#elif (_GPIO_PORT_G_PIN_COUNT > 0) +#define GPIO_PORT_MAX 6 +#elif (_GPIO_PORT_F_PIN_COUNT > 0) +#define GPIO_PORT_MAX 5 +#elif (_GPIO_PORT_E_PIN_COUNT > 0) +#define GPIO_PORT_MAX 4 +#elif (_GPIO_PORT_D_PIN_COUNT > 0) +#define GPIO_PORT_MAX 3 +#else +#error "Max GPIO port number is undefined for this part." +#endif + +#define GPIO_EXTINTNO_MAX 15 ///< Highest EXT GPIO interrupt number. + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +///@brief GPIO ports IDs. +typedef enum { +#if (_GPIO_PORT_A_PIN_COUNT > 0) + SL_GPIO_PORT_A = 0, ///< GPIO Port A +#endif +#if (_GPIO_PORT_B_PIN_COUNT > 0) + SL_GPIO_PORT_B = 1, ///< GPIO Port B +#endif +#if (_GPIO_PORT_C_PIN_COUNT > 0) + SL_GPIO_PORT_C = 2, ///< GPIO Port C +#endif +#if (_GPIO_PORT_D_PIN_COUNT > 0) + SL_GPIO_PORT_D = 3, ///< GPIO Port D +#endif +#if (_GPIO_PORT_E_PIN_COUNT > 0) + SL_GPIO_PORT_E = 4, +#endif +#if (_GPIO_PORT_F_PIN_COUNT > 0) + SL_GPIO_PORT_F = 5, +#endif +#if (_GPIO_PORT_G_PIN_COUNT > 0) + SL_GPIO_PORT_G = 6, +#endif +#if (_GPIO_PORT_H_PIN_COUNT > 0) + SL_GPIO_PORT_H = 7, +#endif +#if (_GPIO_PORT_I_PIN_COUNT > 0) + SL_GPIO_PORT_I = 8, +#endif +#if (_GPIO_PORT_J_PIN_COUNT > 0) + SL_GPIO_PORT_J = 9, +#endif +#if (_GPIO_PORT_K_PIN_COUNT > 0) + SL_GPIO_PORT_K = 10, +#endif +} sl_gpio_port_t; + +///@brief GPIO Pin Modes. +typedef enum { + SL_GPIO_MODE_0 = _MODE0, ///< Pin MUX GPIO Mode 0. + SL_GPIO_MODE_1 = _MODE1, ///< Pin MUX GPIO Mode 1. + SL_GPIO_MODE_2 = _MODE2, ///< Pin MUX GPIO Mode 2. + SL_GPIO_MODE_3 = _MODE3, ///< Pin MUX GPIO Mode 3. + SL_GPIO_MODE_4 = _MODE4, ///< Pin MUX GPIO Mode 4. + SL_GPIO_MODE_5 = _MODE5, ///< Pin MUX GPIO Mode 5. + SL_GPIO_MODE_6 = _MODE6, ///< Pin MUX GPIO Mode 6. + SL_GPIO_MODE_7 = _MODE7, ///< Pin MUX GPIO Mode 7. + SL_GPIO_MODE_8 = _MODE8, ///< Pin MUX GPIO Mode 8. + SL_GPIO_MODE_9 = _MODE9, ///< Pin MUX GPIO Mode 9. + SL_GPIO_MODE_10 = _MODE10, ///< Pin MUX GPIO Mode 10. + SL_GPIO_MODE_14 = _MODE14, ///< Pin MUX GPIO Mode 14. + SL_GPIO_MODE_DISABLED = _GPIO_P_MODEL_MODE0_DISABLED, ///< Input disabled. Pull-up if DOUT is set. + SL_GPIO_MODE_INPUT = _GPIO_P_MODEL_MODE0_INPUT, ///< Input enabled. Filter if DOUT is set. + SL_GPIO_MODE_INPUT_PULL = _GPIO_P_MODEL_MODE0_INPUTPULL, ///< Input enabled. DOUT determines pull direction. + SL_GPIO_MODE_INPUT_PULL_FILTER = + _GPIO_P_MODEL_MODE0_INPUTPULLFILTER, ///< Input enabled with filter. DOUT determines pull direction. + SL_GPIO_MODE_PUSH_PULL = _GPIO_P_MODEL_MODE0_PUSHPULL, ///< Push-pull output. + SL_GPIO_MODE_PUSH_PULL_ALTERNATE = _GPIO_P_MODEL_MODE0_PUSHPULLALT, ///< Push-pull using alternate control. + SL_GPIO_MODE_WIRED_OR = _GPIO_P_MODEL_MODE0_WIREDOR, ///< Wired-or output. + SL_GPIO_MODE_WIRED_OR_PULL_DOWN = _GPIO_P_MODEL_MODE0_WIREDORPULLDOWN, ///< Wired-or output with pull-down. + SL_GPIO_MODE_WIRED_AND = _GPIO_P_MODEL_MODE0_WIREDAND, ///< Open-drain output. + SL_GPIO_MODE_WIRED_AND_FILTER = _GPIO_P_MODEL_MODE0_WIREDANDFILTER, ///< Open-drain output with filter. + SL_GPIO_MODE_WIRED_AND_PULLUP = _GPIO_P_MODEL_MODE0_WIREDANDPULLUP, ///< Open-drain output with pull-up. + SL_GPIO_MODE_WIRED_AND_PULLUP_FILTER = + _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER, ///< Open-drain output with filter and pull-up. + SL_GPIO_MODE_WIRED_AND_ALTERNATE = _GPIO_P_MODEL_MODE0_WIREDANDALT, ///< Open-drain output using alternate control. + SL_GPIO_MODE_WIRED_AND_ALTERNATE_FILTER = + _GPIO_P_MODEL_MODE0_WIREDANDALTFILTER, ///< Open-drain output using alternate control with filter. + SL_GPIO_MODE_WIRED_AND_ALTERNATE_PULLUP = + _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP, ///< Open-drain output using alternate control with pull-up. + SL_GPIO_MODE_WIRED_AND_ALTERNATE_PULLUP_FILTER = + _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER, ///< Open-drain output using alternate control with filter and pull-up. +} sl_gpio_mode_t; + +///@brief GPIO Interrupt Configurations. +typedef enum { + SL_GPIO_INTERRUPT_DISABLE = 0, ///< disable the interrupt + SL_GPIO_INTERRUPT_ENABLE = (1 << 0), ///< enable the interrupt + SL_GPIO_INTERRUPT_HIGH = (1 << 0), ///< interrupt when pin level is '1' + SL_GPIO_INTERRUPT_LOW = (1 << 1), ///< interrupt when pin level is '0' + SL_GPIO_INTERRUPT_RISING_EDGE = (1 << 2), ///< interrupt when rising edge is detected + SL_GPIO_INTERRUPT_FALLING_EDGE = (1 << 3), ///< interrupt when falling edge is detected + SL_GPIO_INTERRUPT_RISE_FALL_EDGE = (1 << 4), ///< interrupt when rising and falling edge is detected +} sl_gpio_interrupt_flag_t; + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +/***************************************************************************/ /** + * @brief Configure the MCU HP instance pin interrupts with trigger type(level/edge) + * and register the callback function for interrupts. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * @pre \ref sl_gpio_set_pin_mode() \n + * @pre \ref sl_si91x_gpio_set_pin_direction() \n + * @param[in] port - The port to associate with the pin. + * HP instance - PORT 0,1,2,3 + * ULP instance - PORT 4 + * @param[in] pin - The pin number on the port. + * HP instance has total 57 GPIO pins. Port 0, 1, 2 has 16 pins each. + * Port 3 has 9 pins. + * ULP instance has total 12 pins. + * @param[in] int_no - The interrupt number to trigger. + * @param[in] flags - Interrupt configuration flags + * @return None + ******************************************************************************/ +void sl_gpio_configure_interrupt(sl_gpio_port_t port, uint8_t pin, uint32_t int_no, sl_gpio_interrupt_flag_t flags); + +/***************************************************************************/ /** + * @brief Set the pin mode (alternate function) of a GPIO for either HP instance (or) ULP instance as per the port number. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n + * Use corresponding pad receiver API for corresponding GPIO instance. + * @param[in] port - The port to associate with the pin. + * HP instance - PORT 0,1,2,3 + * ULP instance - PORT 4 + * @param[in] pin - The pin number on the port. + * HP instance has total 57 GPIO pins. Port 0, 1, 2 has 16 pins each. + * Port 3 has 9 pins. + * ULP instance has total 12 pins. + * @param[in] mode - The desired pin mode. + * @param[in] output_value - A value to set for the pin in the GPIO register. + * The GPIO setting is important for some input mode configurations. + * @return None + ******************************************************************************/ +void sl_gpio_set_pin_mode(sl_gpio_port_t port, uint8_t pin, sl_gpio_mode_t mode, uint32_t output_value); + +/***************************************************************************/ /** + * @brief Get the pin mode (alternate function) of a GPIO for either HP instance or ULP instance as per the port number. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n + * Use corresponding pad receiver API for corresponding GPIO instance. + * @pre \ref sl_gpio_set_pin_mode(); + * @param[in] port - The port to associate with the pin. + * HP instance - PORT 0,1,2,3 + * ULP instance - PORT 4 + * @param[in] pin - The pin number on the port. + * HP instance has total 57 GPIO pins. Port 0, 1, 2 has 16 pins each. + * Port 3 has 9 pins. + * ULP instance has total 12 pins. + * @return returns Pin status + * '0' - Output + * '1' - Input + ******************************************************************************/ +sl_gpio_mode_t sl_gpio_get_pin_mode(sl_gpio_port_t port, uint8_t pin); + +/***************************************************************************/ /** + * @brief Set a single GPIO pin of a GPIO port with 1. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n + * Use corresponding pad receiver API for corresponding GPIO instance. \n + * @pre \ref sl_gpio_set_pin_mode(); \n + * @pre \ref sl_si91x_gpio_set_pin_direction(); \n + * @param[in] port - The port to associate with the pin. + * HP instance - PORT 0,1,2,3 + * ULP instance - PORT 4 + * @param[in] pin - The pin number on the port. + * HP instance has total 57 GPIO pins. Port 0, 1, 2 has 16 pins each. + * Port 3 has 9 pins. + * ULP instance has total 12 pins. + * @return None + ******************************************************************************/ +static __INLINE void sl_gpio_set_pin_output(sl_gpio_port_t port, uint8_t pin) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port)); + if ((port == SL_GPIO_PORT_A) || (port == SL_GPIO_PORT_B) || (port == SL_GPIO_PORT_C) || (port == SL_GPIO_PORT_D)) { + SL_GPIO_ASSERT(SL_GPIO_NDEBUG_PORT_PIN(port, pin)); + GPIO->PIN_CONFIG[(port * MAX_GPIO_PORT_PIN) + pin].BIT_LOAD_REG = SET; + } else if (port == SL_GPIO_ULP_PORT) { + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_ULP_PORT_PIN(port, pin)); + ULP_GPIO->PIN_CONFIG[pin].BIT_LOAD_REG = SET; + } else { + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_UULP_PORT_PIN(port, pin)); + // Set pin in UULP GPIO instance by controlling pin value + UULP_GPIO->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_OUT = SET; + } +} + +/***************************************************************************/ /** + * @brief Set the selected bits value of GPIO data out register to 1. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n + * Use corresponding pad receiver API for corresponding GPIO instance. \n + * @pre \ref sl_gpio_set_pin_mode(); \n + * @pre \ref sl_si91x_gpio_set_pin_direction(); \n + * @param[in] port - The port to associate with the pin. + * HP instance - PORT 0,1,2,3 + * ULP instance - PORT 4 + * @param[in] pins - The GPIO pins in a port are set to 1's. + * @return None + ******************************************************************************/ +static __INLINE void sl_gpio_set_port_output(sl_gpio_port_t port, uint32_t pins) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port)); + if (port == SL_GPIO_ULP_PORT) { + ULP_GPIO->PORT_CONFIG[SL_GPIO_PORT_A].PORT_SET_REG = (pins); + } else { + GPIO->PORT_CONFIG[port].PORT_SET_REG = (pins); + } +} + +/***************************************************************************/ /** + * @brief Set GPIO port value with the selected mask bits. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n + * Use corresponding pad receiver API for corresponding GPIO instance. \n + * @pre \ref sl_gpio_set_pin_mode(); \n + * @pre \ref sl_si91x_gpio_set_pin_direction(); \n + * @param[in] port - The port to associate with the pin. + * HP instance - PORT 0,1,2,3 + * ULP instance - PORT 4 + * @param[in] val - Value to write to port configuration register. + * @param[in] mask - Mask indicating which bits to modify. + * @return None + ******************************************************************************/ +static __INLINE void sl_gpio_set_port_output_value(sl_gpio_port_t port, uint32_t val, uint32_t mask) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port)); + if (port == SL_GPIO_ULP_PORT) { + ULP_GPIO->PORT_CONFIG[SL_GPIO_PORT_A].PORT_SET_REG = (ULP_GPIO->PORT_CONFIG[port].PORT_SET_REG & ~mask) + | (val & mask); + } else { + GPIO->PORT_CONFIG[port].PORT_SET_REG = (GPIO->PORT_CONFIG[port].PORT_SET_REG & ~mask) | (val & mask); + } +} + +/***************************************************************************/ /** + * @brief Set slewrate for pins on a GPIO port. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * @param[in] port - The GPIO port to configure. + * @param[in] slewrate - The slewrate to configure for pins on this GPIO port. + * @param[in] slewrate_alt - The slewrate to configure for pins using alternate modes on this GPIO port. + * @return None + ******************************************************************************/ +static __INLINE void sl_gpio_set_slew_rate(sl_gpio_port_t port, uint32_t slewrate, uint32_t slewrate_alt) +{ + UNUSED_VAR(slewrate_alt); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port)); + for (uint8_t i = (port * MAX_GPIO_PORT_PIN); i < (MAX_GPIO_PORT_PIN * (port + 1)); i++) { + PAD_REG(i)->GPIO_PAD_CONFIG_REG_b.PADCONFIG_SR = (sl_si91x_gpio_slew_rate_t)slewrate; + } +} + +/***************************************************************************/ /** + * @brief Clear a single pin in GPIO configuration register to 0. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_ulp_pad_receiver(); for ULP instance \n + * Use corresponding pad receiver API for corresponding GPIO instance. \n + * @pre \ref sl_gpio_set_pin_mode(); \n + * @pre \ref sl_si91x_gpio_set_pin_direction(); \n + * @param[in] port - The port to associate with the pin. + * HP instance - PORT 0,1,2,3 + * ULP instance - PORT 4 + * @param[in] pin - The pin to set. + * @return None + ******************************************************************************/ +static __INLINE void sl_gpio_clear_pin_output(sl_gpio_port_t port, uint8_t pin) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port)); + if ((port == SL_GPIO_PORT_A) || (port == SL_GPIO_PORT_B) || (port == SL_GPIO_PORT_C) || (port == SL_GPIO_PORT_D)) { + SL_GPIO_ASSERT(SL_GPIO_NDEBUG_PORT_PIN(port, pin)); + GPIO->PIN_CONFIG[(port * MAX_GPIO_PORT_PIN) + pin].BIT_LOAD_REG = CLR; + } else if (port == SL_GPIO_ULP_PORT) { + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_ULP_PORT_PIN(port, pin)); + ULP_GPIO->PIN_CONFIG[pin].BIT_LOAD_REG = CLR; + } else { + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_UULP_PORT_PIN(port, pin)); + // Set pin in UULP GPIO instance by controlling pin value + UULP_GPIO->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_OUT = CLR; + } +} + +/***************************************************************************/ /** + * @brief Clear bits in configuration register for a port to 0. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n + * Use corresponding pad receiver API for corresponding GPIO instance. \n + * @pre \ref sl_gpio_set_pin_mode() \n + * @pre \ref sl_si91x_gpio_set_pin_direction() \n + * @param[in] port - The port to associate with the pin. + * HP instance - PORT 0,1,2,3 + * ULP instance - PORT 4 + * @param[in] pins - The GPIO pins in a port to clear. + * @return None + ******************************************************************************/ +static __INLINE void sl_gpio_clear_port_output(sl_gpio_port_t port, uint32_t pins) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port)); + if (port == SL_GPIO_ULP_PORT) { + ULP_GPIO->PORT_CONFIG[SL_GPIO_PORT_A].PORT_CLEAR_REG = (pins); + } else { + GPIO->PORT_CONFIG[port].PORT_CLEAR_REG = (pins); + } +} + +/***************************************************************************/ /** + * @brief Read the pin value for a single pin in a GPIO port. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n + * Use corresponding pad receiver API for corresponding GPIO instance. \n + * @pre \ref sl_gpio_set_pin_mode() \n + * @pre \ref sl_si91x_gpio_set_pin_direction() \n + * @param[in] port - The port to associate with the pin. + * HP instance - PORT 0,1,2,3 + * ULP instance - PORT 4 + * @param[in] pin - The pin number on the port. + * HP instance has total 57 GPIO pins. Port 0, 1, 2 has 16 pins each. + * Port 3 has 9 pins. + * ULP instance has total 12 pins. + * @return The GPIO pin value + * '0' - Output\n + * '1' - Input\n + ******************************************************************************/ +static __INLINE uint8_t sl_gpio_get_pin_input(sl_gpio_port_t port, uint8_t pin) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port)); + if ((port == SL_GPIO_PORT_A) || (port == SL_GPIO_PORT_B) || (port == SL_GPIO_PORT_C) || (port == SL_GPIO_PORT_D)) { + SL_GPIO_ASSERT(SL_GPIO_NDEBUG_PORT_PIN(port, pin)); + return (uint8_t)GPIO->PIN_CONFIG[(port * MAX_GPIO_PORT_PIN) + pin].BIT_LOAD_REG; + } else if (port == SL_GPIO_ULP_PORT) { + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_ULP_PORT_PIN(port, pin)); + return (uint8_t)ULP_GPIO->PIN_CONFIG[pin].BIT_LOAD_REG; + } else { + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_UULP_PORT_PIN(port, pin)); + // Read pin status in UULP GPIO instance + return (UULP_GPIO_STATUS >> pin) & MASK_INTR; + } +} + +/***************************************************************************/ /** + * @brief Get the current pin value of selected pin in a GPIO port. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n + * Use corresponding pad receiver API for corresponding GPIO instance. \n + * @pre \ref sl_gpio_set_pin_mode() \n + * @pre \ref sl_si91x_gpio_set_pin_direction() \n + * @param[in] port - The port to associate with the pin. + * HP instance - PORT 0,1,2,3 + * ULP instance - PORT 4 + * @param[in] pin - The pin to get setting for. + * @return The GPIO pin value + * '0' - Output\n + * '1' - Input\n + ******************************************************************************/ +static __INLINE uint8_t sl_gpio_get_pin_output(sl_gpio_port_t port, uint8_t pin) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port)); + if (port == SL_GPIO_ULP_PORT) { + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_ULP_PORT_PIN(port, pin)); + return (uint8_t)ULP_GPIO->PIN_CONFIG[pin].BIT_LOAD_REG; + } else { + SL_GPIO_ASSERT(SL_GPIO_NDEBUG_PORT_PIN(port, pin)); + return (uint8_t)GPIO->PIN_CONFIG[(port * MAX_GPIO_PORT_PIN) + pin].BIT_LOAD_REG; + } +} + +/***************************************************************************/ /** + * @brief Read the port value for GPIO port. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n + * Use corresponding pad receiver API for corresponding GPIO instance. \n + * @pre \ref sl_gpio_set_pin_mode() \n + * @pre \ref sl_si91x_gpio_set_pin_direction() \n + * @param[in] port - The port to associate with the pin. + * HP instance - PORT 0,1,2,3 + * ULP instance - PORT 4 + * @return The pin values of the GPIO port. + ******************************************************************************/ +static __INLINE uint32_t sl_gpio_get_port_input(sl_gpio_port_t port) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port)); + if (port == SL_GPIO_ULP_PORT) { + return ULP_GPIO->PORT_CONFIG[SL_GPIO_PORT_A].PORT_READ_REG & PORT_MASK; + } else { + return GPIO->PORT_CONFIG[port].PORT_READ_REG & PORT_MASK; + } +} + +/***************************************************************************/ /** + * @brief Get the current pin values of a selected GPIO Port register. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n + * Use corresponding pad receiver API for corresponding GPIO instance. \n + * @pre \ref sl_gpio_set_pin_mode() \n + * @pre \ref sl_si91x_gpio_set_pin_direction() \n + * @param[in] port - The port to associate with the pin. + * HP instance - PORT 0,1,2,3 + * ULP instance - PORT 4 + * @return The port value for the requested port. + ******************************************************************************/ +static __INLINE uint32_t sl_gpio_get_port_output(sl_gpio_port_t port) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port)); + if (port == SL_GPIO_ULP_PORT) { + return (ULP_GPIO->PORT_CONFIG[SL_GPIO_PORT_A].PORT_READ_REG & PORT_MASK); + } else { + return (GPIO->PORT_CONFIG[port].PORT_READ_REG & PORT_MASK); + } +} + +/***************************************************************************/ /** + * @brief Toggle a single pin in selected GPIO port register. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n + * Use corresponding pad receiver API for corresponding GPIO instance. \n + * @pre \ref sl_gpio_set_pin_mode() \n + * @pre \ref sl_si91x_gpio_set_pin_direction() \n + * @param[in] port - The port to associate with the pin. + * HP instance - PORT 0,1,2,3 + * ULP instance - PORT 4 + * @param[in] pin - The pin number on the port. + * HP instance has total 57 GPIO pins. Port 0, 1, 2 has 16 pins each. + * Port 3 has 9 pins. + * ULP instance has total 12 pins. + * @return None + ******************************************************************************/ +static __INLINE void sl_gpio_toggle_pin_output(sl_gpio_port_t port, uint8_t pin) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port)); + if ((port == SL_GPIO_PORT_A) || (port == SL_GPIO_PORT_B) || (port == SL_GPIO_PORT_C) || (port == SL_GPIO_PORT_D)) { + SL_GPIO_ASSERT(SL_GPIO_NDEBUG_PORT_PIN(port, pin)); + GPIO->PIN_CONFIG[(port * MAX_GPIO_PORT_PIN) + pin].BIT_LOAD_REG ^= SET; + } else if (port == SL_GPIO_ULP_PORT) { + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_ULP_PORT_PIN(port, pin)); + ULP_GPIO->PIN_CONFIG[pin].BIT_LOAD_REG ^= SET; + } else { + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_UULP_PORT_PIN(port, pin)); + // Set or Clear pin in UULP GPIO instance by controlling pin value + UULP_GPIO->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_OUT ^= SET; + } +} + +/***************************************************************************/ /** + * @brief Toggle selected pins in GPIO port register. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n + * Use corresponding pad receiver API for corresponding GPIO instance. \n + * @pre \ref sl_gpio_set_pin_mode() \n + * @pre \ref sl_si91x_gpio_set_pin_direction() \n + * @param[in] port - The port to associate with the pin. + * HP instance - PORT 0,1,2,3 + * ULP instance - PORT 4 + * @param[in] pins - Port pins to toggle. + * @return None + ******************************************************************************/ +static __INLINE void sl_gpio_toggle_port_output(sl_gpio_port_t port, uint32_t pins) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port)); + if (port == SL_GPIO_ULP_PORT) { + ULP_GPIO->PORT_CONFIG[SL_GPIO_PORT_A].PORT_TOGGLE_REG = pins; + } else { + GPIO->PORT_CONFIG[port].PORT_TOGGLE_REG = pins; + } +} + +/***************************************************************************/ /** + * @brief Enable MCU HP instance GPIO pin interrupts. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * @pre \ref sl_gpio_set_pin_mode() \n + * @pre \ref sl_si91x_gpio_set_pin_direction() \n + * @param[in] flags - GPIO interrupt sources to enable. + * @return None + ******************************************************************************/ +static __INLINE void sl_gpio_enable_interrupts(uint32_t flags) +{ + uint16_t intch, int_flag; + intch = (uint16_t)((flags >> WORD_SHIFT) & LSB_WORD_MASK); + int_flag = (uint16_t)(flags & INTERRUPT_MASK); + if ((int_flag & SL_GPIO_INTERRUPT_RISE_EDGE) == SL_GPIO_INTERRUPT_RISE_EDGE) { + GPIO->INTR[intch].GPIO_INTR_CTRL_b.RISE_EDGE_ENABLE = SET; + } + if ((int_flag & SL_GPIO_INTERRUPT_FALL_EDGE) == SL_GPIO_INTERRUPT_FALL_EDGE) { + GPIO->INTR[intch].GPIO_INTR_CTRL_b.FALL_EDGE_ENABLE = SET; + } + if ((int_flag & SL_GPIO_INTERRUPT_LEVEL_HIGH) == SL_GPIO_INTERRUPT_LEVEL_HIGH) { + GPIO->INTR[intch].GPIO_INTR_CTRL_b.LEVEL_HIGH_ENABLE = SET; + } + if ((int_flag & SL_GPIO_INTERRUPT_LEVEL_LOW) == SL_GPIO_INTERRUPT_LEVEL_LOW) { + GPIO->INTR[intch].GPIO_INTR_CTRL_b.LEVEL_LOW_ENABLE = SET; + } +} + +/***************************************************************************/ /** + * @brief Disable MCU HP Instance GPIO pin interrupts. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * @pre \ref sl_gpio_set_pin_mode() \n + * @pre \ref sl_si91x_gpio_set_pin_direction() \n + * @param[in] flags - GPIO interrupt sources to disable. + * @return None + ******************************************************************************/ +static __INLINE void sl_gpio_disable_interrupts(uint32_t flags) +{ + uint16_t intch, int_flag; + intch = (uint16_t)((flags >> WORD_SHIFT) & LSB_WORD_MASK); + int_flag = (uint16_t)(flags & LSB_NIBBLE_MASK); + if ((int_flag & SL_GPIO_INTERRUPT_RISE_EDGE) == SL_GPIO_INTERRUPT_RISE_EDGE) { + GPIO->INTR[intch].GPIO_INTR_CTRL_b.RISE_EDGE_ENABLE = CLR; + } + if ((int_flag & SL_GPIO_INTERRUPT_FALL_EDGE) == SL_GPIO_INTERRUPT_FALL_EDGE) { + GPIO->INTR[intch].GPIO_INTR_CTRL_b.FALL_EDGE_ENABLE = CLR; + } + if ((int_flag & SL_GPIO_INTERRUPT_LEVEL_HIGH) == SL_GPIO_INTERRUPT_LEVEL_HIGH) { + GPIO->INTR[intch].GPIO_INTR_CTRL_b.LEVEL_HIGH_ENABLE = CLR; + } + if ((int_flag & SL_GPIO_INTERRUPT_LEVEL_LOW) == SL_GPIO_INTERRUPT_LEVEL_LOW) { + GPIO->INTR[intch].GPIO_INTR_CTRL_b.LEVEL_LOW_ENABLE = CLR; + } +} + +/***************************************************************************/ /** + * @brief Clear MCU HP Instance GPIO pin interrupts. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * @pre \ref sl_gpio_set_pin_mode() \n + * @pre \ref sl_si91x_gpio_set_pin_direction() \n + * @param[in] flags - Bitwise logic OR of GPIO interrupt sources to clear. + * @return None + ******************************************************************************/ +static __INLINE void sl_gpio_clear_interrupts(uint32_t flags) +{ + uint32_t reg_data = GPIO->INTR[flags].GPIO_INTR_STATUS; + if (reg_data != 0) + GPIO->INTR[flags].GPIO_INTR_STATUS = INTR_CLR; +} + +/**************************************************************************/ /** + * @brief Set MCU HP Instance GPIO pin interrupts. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * @pre \ref sl_gpio_set_pin_mode() \n + * @pre \ref sl_si91x_gpio_set_pin_direction() \n + * @param[in] flags - GPIO interrupt sources to set to pending. + * @return None + *****************************************************************************/ +static __INLINE void sl_gpio_set_interrupts(uint32_t flags) +{ + uint16_t intch, int_flag; + intch = (uint16_t)((flags >> WORD_SHIFT) & LSB_WORD_MASK); + int_flag = (uint16_t)(flags & INTERRUPT_MASK); + GPIO->INTR[intch].GPIO_INTR_CTRL = (GPIO->INTR[intch].GPIO_INTR_CTRL | int_flag); +} + +/***************************************************************************/ /** + * @brief Get pending MCU HP Instance GPIO pin interrupts. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * @pre \ref sl_gpio_set_pin_mode() \n + * @pre \ref sl_si91x_gpio_set_pin_direction() \n + * @param[in] None + * @return GPIO interrupt sources pending. + ******************************************************************************/ +static __INLINE uint32_t sl_gpio_get_pending_interrupts(void) +{ + uint32_t intflags = 0, tmp = 0; + for (uint8_t intch = 0; intch < MAX_GPIO_PIN_INT; intch++) { + tmp = (GPIO->INTR[intch].GPIO_INTR_STATUS & LSB_NIBBLE_MASK); + intflags |= (tmp << (NIBBLE_SHIFT * intch)); + } + return intflags; +} + +/***************************************************************************/ /** + * @brief Get enabled MCU HP Instance GPIO pin interrupts. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * @pre \ref sl_gpio_set_pin_mode() \n + * @pre \ref sl_si91x_gpio_set_pin_direction() \n + * @param[in] None + * @return Returns enabled GPIO interrupt sources. + ******************************************************************************/ +static __INLINE uint32_t sl_gpio_get_enabled_interrupts(void) +{ + uint32_t intflags = 0, tmp = 0; + for (uint8_t intch = 0; intch < MAX_GPIO_PIN_INT; intch++) { + tmp = (GPIO->INTR[intch].GPIO_INTR_CTRL & LSB_NIBBLE_MASK); + intflags |= (tmp << (NIBBLE_SHIFT * intch)); + } + return intflags; +} + +/***************************************************************************/ /** + * @brief Get enabled and pending GPIO pin interrupt of MCU HP Instance. + * Useful for handling more interrupt sources in the same interrupt handler. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * @pre \ref sl_gpio_set_pin_mode() \n + * @pre \ref sl_si91x_gpio_set_pin_direction() \n + * @param[in] None + * @return Returns pending GPIO interrupt sources + ******************************************************************************/ +static __INLINE uint32_t sl_gpio_get_enabled_pending_interrupts(void) +{ + uint32_t intflags = 0, tmp_ctrl = 0, tmp_sts = 0; + uint8_t intch = 0; + for (intch = 0; intch < MAX_GPIO_PIN_INT; intch++) { + tmp_ctrl = (GPIO->INTR[intch].GPIO_INTR_CTRL & INTERRUPT_MASK); + if (tmp_ctrl & MASK_CTRL) { + tmp_ctrl = (tmp_ctrl >> 1) | MASK_INTR; + } + tmp_sts = ((GPIO->INTR[intch].GPIO_INTR_STATUS) & (tmp_ctrl)); + tmp_sts = (tmp_sts & LSB_NIBBLE_MASK); + intflags |= (tmp_sts << (NIBBLE_SHIFT * intch)); + } + return intflags; +} + +/**************************************************************************/ /** + * @brief This API is used set ulp soc gpio mode + * \n(Gpio pin mode,ranges 000 -> Mode 0 to 111 -> Mode 7 Used for GPIO Pin Muxing ) + * @param[in] ulp_gpio : ulp gpio number + * @param[in] mode : GPIO mode + * \n possible values for this parameter are the following + * - \ref EGPIO_PIN_MUX_MODE0 : Select pin mode 0 + * - \ref EGPIO_PIN_MUX_MODE1 : Select pin mode 1 + * - \ref EGPIO_PIN_MUX_MODE2 : Select pin mode 2 + * - \ref EGPIO_PIN_MUX_MODE3 : Select pin mode 3 + * - \ref EGPIO_PIN_MUX_MODE4 : Select pin mode 4 + * - \ref EGPIO_PIN_MUX_MODE5 : Select pin mode 5 + * - \ref EGPIO_PIN_MUX_MODE6 : Select pin mode 6 + * - \ref EGPIO_PIN_MUX_MODE7 : Select pin mode 7 + * @return None + ******************************************************************************/ +static __INLINE void sl_si91x_gpio_ulp_soc_mode(uint8_t ulp_gpio, uint8_t mode) + +{ + ULPCLK->ULP_SOC_GPIO_MODE_REG[ulp_gpio].ULP_SOC_GPIO_MODE_REG_b.ULP_SOC_GPIO_MODE_REG = (unsigned int)(mode & 0x07); +} + +/** @} (end addtogroup GPIO) */ + +#ifdef __cplusplus +} +#endif + +#endif ///< GPIO_PRESENT +#endif ///< SL_PERIPHERAL_GPIO_H diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/src/sl_si91x_peripheral_gpio.c b/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/src/sl_si91x_peripheral_gpio.c new file mode 100644 index 000000000..32a0d5584 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/src/sl_si91x_peripheral_gpio.c @@ -0,0 +1,1320 @@ +/******************************************************************************* + * @file sl_si91x_peripheral_gpio.c + * @brief General Purpose IO (GPIO) peripheral API. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licenser of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be miss represented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * miss represented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_si91x_peripheral_gpio.h" +#ifdef DEBUG_UART +#include "rsi_debug.h" +#endif + +/******************************************************************************* + *************************** DEFINES / MACROS ******************************** + ******************************************************************************/ +#define GPIO_RELEASE_VERSION 0 // gpio Release version +#define GPIO_MAJOR_VERSION 0 // gpio SQA version +#define GPIO_MINOR_VERSION 2 // gpio Developer version + +/******************************************************************************* + ************************ GLOBAL FUNCTIONS ************************** + ******************************************************************************/ +extern __INLINE void sl_gpio_set_pin_output(sl_gpio_port_t port, uint8_t pin); +extern __INLINE void sl_gpio_clear_pin_output(sl_gpio_port_t port, uint8_t pin); +/******************************************************************************* + * This API is used to configure the pin interrupt in GPIO HP instance. + * There are total 8 pin interrupts in this instance. + * To configure the interrupt, first GPIO initialization must be done. + * The actions to be performed in GPIO initialization are: + * - Enable the M4 clock of GPIO HP instance. + * - Select PAD selection of the GPIO HP instance. + * - Enable PAD receiver for GPIO pin number, whether GPIO pin is selected as + * output/input. + * - Set pin mode and direction of the GPIO pin. + * Configuring the pin interrupt requires port number, pin number, interrupt number, + * and interrupt flag to be generated. + * Enable the IRQ handler. + ******************************************************************************/ +void sl_gpio_configure_interrupt(sl_gpio_port_t port, uint8_t pin, uint32_t int_no, sl_gpio_interrupt_flag_t flags) +{ + // Pin interrupt configuration in HP GPIO instance + SL_GPIO_ASSERT(SL_GPIO_NDEBUG_PORT_PIN(port, pin)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_FLAG(flags)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_INTR(int_no)); + GPIO->INTR[int_no].GPIO_INTR_CTRL_b.PORT_NUMBER = port; + GPIO->INTR[int_no].GPIO_INTR_CTRL_b.PIN_NUMBER = (sl_si91x_gpio_pin_t)pin; + // Enable GPIO interrupt rising and falling edge + if ((flags & SL_GPIO_INTERRUPT_RISE_FALL_EDGE) == SL_GPIO_INTERRUPT_RISE_FALL_EDGE) { + GPIO->INTR[int_no].GPIO_INTR_CTRL_b.RISE_EDGE_ENABLE = SL_GPIO_INTERRUPT_ENABLE; + GPIO->INTR[int_no].GPIO_INTR_CTRL_b.FALL_EDGE_ENABLE = SL_GPIO_INTERRUPT_ENABLE; + } else { + GPIO->INTR[int_no].GPIO_INTR_CTRL_b.RISE_EDGE_ENABLE = SL_GPIO_INTERRUPT_DISABLE; + GPIO->INTR[int_no].GPIO_INTR_CTRL_b.FALL_EDGE_ENABLE = SL_GPIO_INTERRUPT_DISABLE; + } + // Enable GPIO interrupt falling edge + if ((flags & SL_GPIO_INTERRUPT_FALL_EDGE) == SL_GPIO_INTERRUPT_FALL_EDGE) { + GPIO->INTR[int_no].GPIO_INTR_CTRL_b.FALL_EDGE_ENABLE = SL_GPIO_INTERRUPT_ENABLE; + } + // Disable GPIO interrupt falling edge + else { + GPIO->INTR[int_no].GPIO_INTR_CTRL_b.FALL_EDGE_ENABLE = SL_GPIO_INTERRUPT_DISABLE; + } + // Enable GPIO interrupt rising edge + if ((flags & SL_GPIO_INTERRUPT_RISE_EDGE) == SL_GPIO_INTERRUPT_RISE_EDGE) { + GPIO->INTR[int_no].GPIO_INTR_CTRL_b.RISE_EDGE_ENABLE = SL_GPIO_INTERRUPT_ENABLE; + } + // Disable GPIO interrupt rising edge + else { + GPIO->INTR[int_no].GPIO_INTR_CTRL_b.RISE_EDGE_ENABLE = SL_GPIO_INTERRUPT_DISABLE; + } + // Enable GPIO interrupt level high + if ((flags & SL_GPIO_INTERRUPT_LEVEL_HIGH) == SL_GPIO_INTERRUPT_LEVEL_HIGH) { + GPIO->INTR[int_no].GPIO_INTR_CTRL_b.LEVEL_HIGH_ENABLE = SL_GPIO_INTERRUPT_ENABLE; + } + // Disable GPIO interrupt level high + else { + GPIO->INTR[int_no].GPIO_INTR_CTRL_b.LEVEL_HIGH_ENABLE = SL_GPIO_INTERRUPT_DISABLE; + } + // Enable GPIO interrupt level low + if ((flags & SL_GPIO_INTERRUPT_LEVEL_LOW) == SL_GPIO_INTERRUPT_LEVEL_LOW) { + GPIO->INTR[int_no].GPIO_INTR_CTRL_b.LEVEL_LOW_ENABLE = SL_GPIO_INTERRUPT_ENABLE; + } + // Disable GPIO interrupt level low + else { + GPIO->INTR[int_no].GPIO_INTR_CTRL_b.LEVEL_LOW_ENABLE = SL_GPIO_INTERRUPT_DISABLE; + } + // Un-mask the interrupt + GPIO->INTR[int_no].GPIO_INTR_CTRL_b.MASK = CLR; +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instances to set pin mode. + * - If GPIO HP instance is considered, the following actions are performed: + * - To set the pin mode in GPIO HP instance, GPIO initialization needs to be done first. + * - The actions to be performed in GPIO initialization are: + * - Enable the M4 clock of GPIO HP instance. + * - Select PAD selection of the GPIO HP instance. + * - Enable PAD receiver for GPIO pin number, whether GPIO pin is selected as + * output/input. + * @note: Select HP GPIO pins for HP instances(GPIO_6 to GPIO_57). Do not use + * GPIO pin number(0 to 5) in HP instance as these are used for other functionality. + * - If GPIO ULP instance is considered, the following actions are performed: + * - To set the pin mode in GPIO ULP instance, GPIO initialization needs to be done first. + * - The actions to be performed in GPIO initialization are: + * - Enable the ULP clock of GPIO ULP instance. + * - Enable ULP PAD receiver for GPIO pin number, whether GPIO pin is selected as + * output/input. + * @note: Select ULP GPIO pins for ULP instances(ULP_GPIO_0 to ULP_GPIO_11). + ******************************************************************************/ +void sl_gpio_set_pin_mode(sl_gpio_port_t port, uint8_t pin, sl_gpio_mode_t mode, uint32_t output_value) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PARAMETER(output_value)); + /* If disabling a pin, do not modify register to reduce the chance of */ + /* a glitch/spike(may not be sufficient precaution in all use cases). */ + if (mode != SL_GPIO_MODE_DISABLED) { + if (output_value) { + sl_gpio_set_pin_output(port, pin); // Set the GPIO pin + } else { + sl_gpio_clear_pin_output(port, pin); // Clear the GPIO pin + } + } + // if condition is satisfied when ULP GPIO instance occurs + if (port == SL_GPIO_ULP_PORT) { + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_MODE_PARAMETER(mode)); + ULP_GPIO->PIN_CONFIG[pin].GPIO_CONFIG_REG_b.MODE = mode; // Set mode in ULP GPIO instance + } + // else condition is satisfied when HP GPIO instance occurs + else { + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_MODE(mode)); + // Set mode in HP GPIO instance + GPIO->PIN_CONFIG[(port * MAX_GPIO_PORT_PIN) + pin].GPIO_CONFIG_REG_b.MODE = mode; + } + if (mode == SL_GPIO_MODE_DISABLED) { + if (output_value) { + sl_gpio_set_pin_output(port, pin); // Set the GPIO pin + } else { + sl_gpio_clear_pin_output(port, pin); // Clear the GPIO pin + } + } +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instances to get pin mode. + * - If GPIO HP instance is considered, the following actions are performed: + * - To get the pin status in GPIO HP instance, GPIO initialization needs to be done first. + * - The actions to be performed in GPIO initialization are: + * - Enable the M4 clock of GPIO HP instance. + * - Select PAD selection of the GPIO HP instance. + * - Enable PAD receiver for GPIO pin number, whether GPIO pin is selected as + * output/input. + * - Set pin mode and direction of the GPIO pin. + * - Get the pin mode of GPIO pin. + * @note: Select HP GPIO pins for HP instances(GPIO_6 to GPIO_57). Do not use + * GPIO pin number(0 to 5) in HP instance as these are used for other functionality. + * - If GPIO ULP instance is considered, the following actions are performed: + * - To get the pin mode in GPIO ULP instance, GPIO initialization needs to be done first. + * - The actions to be performed in GPIO initialization are: + * - Enable the ULP clock of GPIO ULP instance. + * - Enable ULP PAD receiver for GPIO pin number, whether GPIO pin is selected as + * output/input. + * - Set pin mode and direction of the GPIO pin. + * - Get the pin mode of GPIO pin. + * @note: Select ULP GPIO pins for ULP instances(ULP_GPIO_0 to ULP_GPIO_11). + ******************************************************************************/ +sl_gpio_mode_t sl_gpio_get_pin_mode(sl_gpio_port_t port, uint8_t pin) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port)); + if (port == SL_GPIO_ULP_PORT) { + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_ULP_PORT_PIN(port, pin)); + // Read status of the pin in ULP GPIO instance + return (sl_gpio_mode_t)(ULP_GPIO->PIN_CONFIG[pin].GPIO_CONFIG_REG_b.MODE); + } else { + SL_GPIO_ASSERT(SL_GPIO_NDEBUG_PORT_PIN(port, pin)); + // Read status of the pin in HP GPIO instance + return (sl_gpio_mode_t)(GPIO->PIN_CONFIG[(port * MAX_GPIO_PORT_PIN) + pin].GPIO_CONFIG_REG_b.MODE); + } +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instances to set pin direction. + * - If GPIO HP instance is considered, the following actions are performed: + * - To set the pin direction in GPIO HP instance, GPIO initialization needs to be done first. + * - The actions to be performed in GPIO initialization are: + * - Enable the M4 clock of GPIO HP instance. + * - Select PAD selection of the GPIO HP instance. + * - Enable PAD receiver for GPIO pin number, whether GPIO pin is selected as + * output/input. + * - Set pin mode and direction of the GPIO pin. + * @note: Select HP GPIO pins for HP instances(GPIO_6 to GPIO_57). Do not use + * GPIO pin number(0 to 5) in HP instance as these are used for other functionality. + * - If GPIO ULP instance is considered, the following actions are performed: + * - To set the pin direction in GPIO ULP instance, GPIO initialization needs to be done first. + * - The actions to be performed in GPIO initialization are: + * - Enable the ULP clock of GPIO ULP instance. + * - Enable ULP PAD receiver for GPIO pin number, whether GPIO pin is selected as + * output/input. + * - Set pin mode and direction of the GPIO pin. + * @note: Select ULP GPIO pins for ULP instances(ULP_GPIO_0 to ULP_GPIO_11). +*******************************************************************************/ +void sl_si91x_gpio_set_pin_direction(uint8_t port, uint8_t pin, sl_si91x_gpio_direction_t direction) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PARAMETER(direction)); + if ((port == SL_GPIO_PORT_A) || (port == SL_GPIO_PORT_B) || (port == SL_GPIO_PORT_C) || (port == SL_GPIO_PORT_D)) { + SL_GPIO_ASSERT(SL_GPIO_NDEBUG_PORT_PIN(port, pin)); + // Set the pin direction in HP GPIO instance + GPIO->PIN_CONFIG[(port * MAX_GPIO_PORT_PIN) + pin].GPIO_CONFIG_REG_b.DIRECTION = direction; + } else if (port == SL_GPIO_ULP_PORT) { + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_ULP_PORT_PIN(port, pin)); + // Set the pin direction in ULP GPIO instance + ULP_GPIO->PIN_CONFIG[pin].GPIO_CONFIG_REG_b.DIRECTION = direction; + } else { + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_UULP_PIN(pin)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PARAMETER(direction)); + // Set direction(input/output) in UULP GPIO instance + UULP_GPIO->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_OEN = direction; + } +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instances to get pin direction. + * - If GPIO HP instance is considered, the following actions are performed: + * - To get the pin direction in GPIO HP instance, GPIO initialization needs to be done first. + * - The actions to be performed in GPIO initialization are: + * - Enable the M4 clock of GPIO HP instance. + * - Select PAD selection of the GPIO HP instance. + * - Enable PAD receiver for GPIO pin number, whether GPIO pin is selected as + * output/input. + * - Set pin mode and direction of the GPIO pin. + * - Get the pin direction of the GPIO pin. + * @note: Select HP GPIO pins for HP instances(GPIO_6 to GPIO_57). Do not use + * GPIO pin number(0 to 5) in HP instance as these are used for other functionality. + * - If GPIO ULP instance is considered, the following actions are performed: + * - To get the pin direction in GPIO ULP instance, GPIO initialization needs to be done first. + * - The actions to be performed in GPIO initialization are: + * - Enable the ULP clock of GPIO ULP instance. + * - Enable ULP PAD receiver for GPIO pin number, whether GPIO pin is selected as + * output/input. + * - Set pin mode and direction of the GPIO pin. + * - Get the pin direction of the GPIO pin. + * @note: Select ULP GPIO pins for ULP instances(ULP_GPIO_0 to ULP_GPIO_11). + ******************************************************************************/ +uint8_t sl_si91x_gpio_get_pin_direction(uint8_t port, uint8_t pin) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port)); + if (port == SL_GPIO_ULP_PORT) { + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_ULP_PORT_PIN(port, pin)); + // Get the pin direction in ULP GPIO instance + return ULP_GPIO->PIN_CONFIG[pin].GPIO_CONFIG_REG_b.DIRECTION; + } else { + SL_GPIO_ASSERT(SL_GPIO_NDEBUG_PORT_PIN(port, pin)); + // Get the pin direction in HP GPIO instance + return GPIO->PIN_CONFIG[(port * MAX_GPIO_PORT_PIN) + pin].GPIO_CONFIG_REG_b.DIRECTION; + } +} + +/******************************************************************************* + * This API is used to enable PAD receiver in GPIO HP instance. + * The actions to be performed for enabling PAD are: + * - Enable the M4 clock of GPIO HP instance. + * - Select PAD selection of the GPIO HP instance. + * - Enable PAD receiver for GPIO pin number, whether GPIO pin is selected as + * output/input. + * @note: Select HP GPIO pins for HP instances(GPIO_6 to GPIO_57). Do not use + * GPIO pin number(0 to 5) in HP instance as these are used for other functionality. +*******************************************************************************/ +void sl_si91x_gpio_enable_pad_receiver(uint8_t gpio_num) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PIN(gpio_num)); + // Set the REN(receiver bit) in PAD configuration register + PAD_REG(gpio_num)->GPIO_PAD_CONFIG_REG_b.PADCONFIG_REN = SET; +} + +/******************************************************************************* + * This API is used to disable PAD receiver in GPIO HP instance. + * The actions to be performed for disabling PAD are: + * - Enable the M4 clock of GPIO HP instance. + * - Select PAD selection of the GPIO HP instance. + * - Disable PAD receiver for GPIO pin number, whether GPIO pin is selected as + * output/input. + * @note: Select HP GPIO pins for HP instances(GPIO_6 to GPIO_57). Do not use + * GPIO pin number(0 to 5) in HP instance as these are used for other functionality. +*******************************************************************************/ +void sl_si91x_gpio_disable_pad_receiver(uint8_t gpio_num) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PIN(gpio_num)); + // Clear the REN(receiver bit) in PAD configuration register + PAD_REG(gpio_num)->GPIO_PAD_CONFIG_REG_b.PADCONFIG_REN = CLR; +} + +/******************************************************************************* + * This API is used to enable PAD selection in GPIO HP instance. + * The actions to be performed for enable PAD selection are: + * - Enable the M4 clock of GPIO HP instance. + * - Select PAD selection of the GPIO HP instance. + * @note: PAD number(25 to 30) are used for HOST PAD selection. + * Do not use PAD number-9 as it is used for other functionality. + * @note: Select HP GPIO pins for HP instances(GPIO_6 to GPIO_57). Do not use + * GPIO pin number(0 to 5) in HP instance as these are used for other functionality. +*******************************************************************************/ +void sl_si91x_gpio_enable_pad_selection(uint8_t gpio_padnum) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PAD(gpio_padnum)); + if (gpio_padnum < PAD_SELECT) { + /*(tass_m4ss_gpio_sel)PAD selection (0 to 21) + A value of 1 on this gives control to M4SS(by default it is 0 means ta control) */ + PADSELECTION |= BIT(gpio_padnum); + } + if (gpio_padnum >= PAD_SELECT) { + /*(tass_m4ss_gpio_sel)PAD selection (22 to 33) + A value of 1 on this gives control to M4SS(by default it is 0 means ta control) */ + PADSELECTION_1 |= BIT(gpio_padnum - PAD_SELECT); + } +} + +/******************************************************************************* + * This API is used to enable PAD selection in GPIO HP instance. + * @note: GPIO pin number(25 to 30) are used for HOST PAD selection. +*******************************************************************************/ +void sl_si91x_gpio_enable_host_pad_selection(uint8_t gpio_num) +{ + if (gpio_num >= HOST_PAD_MIN && gpio_num <= HOST_PAD_MAX) { + // (tass_m4ss_gpio_sel)PAD selection (25 to 30) + // A value of 1 on this gives control to M4SS(by default it is 0) + HOST_PADS_GPIO_MODE |= BIT(gpio_num - HOST_PAD_SELECT); + } +} + +/******************************************************************************* + * To select the PAD driver strength in GPIO HP instance, GPIO initialization + * needs to be done first. + * - The actions to be performed in GPIO initialization are: + * - Enable the M4 clock of GPIO HP instance. + * - Select PAD selection of the GPIO HP instance. + * - Enable PAD receiver for GPIO pin number, whether GPIO pin is selected as + * output/input. + * - Set pin mode and direction of the GPIO pin. + * - Select the PAD driver strength of type @ref sl_si91x_gpio_driver_strength_select_t. + * @note: Select HP GPIO pins for HP instances(GPIO_6 to GPIO_57). Do not use + * GPIO pin number(0 to 5) in HP instance as these are used for other functionality. + ******************************************************************************/ +void sl_si91x_gpio_select_pad_driver_strength(uint8_t gpio_num, sl_si91x_gpio_driver_strength_select_t strength) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PIN(gpio_num)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_STRENGTH(strength)); + // Select the required drive strength in HP GPIO instance + PAD_REG(gpio_num)->GPIO_PAD_CONFIG_REG_b.PADCONFIG_E1_E2 = strength; +} + +/******************************************************************************* + * To select the PAD driver disable state in GPIO HP instance, GPIO initialization + * needs to be done first. + * - The actions to be performed in GPIO initialization are: + * - Enable the M4 clock of GPIO HP instance. + * - Select PAD selection of the GPIO HP instance. + * - Enable PAD receiver for GPIO pin number, whether GPIO pin is selected as + * output/input. + * - Set pin mode and direction of the GPIO pin. + * - Select the PAD driver disable state of type @ref sl_si91x_gpio_driver_disable_state_t. + * @note: Select HP GPIO pins for HP instances(GPIO_6 to GPIO_57). Do not use + * GPIO pin number(0 to 5) in HP instance as these are used for other functionality. + ******************************************************************************/ +void sl_si91x_gpio_select_pad_driver_disable_state(uint8_t gpio_num, sl_si91x_gpio_driver_disable_state_t disable_state) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PIN(gpio_num)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_DISABLE_STATE(disable_state)); + // Select the required driver disable state in HP GPIO instance + PAD_REG(gpio_num)->GPIO_PAD_CONFIG_REG_b.PADCONFIG_P1_P2 = disable_state; +} + +/******************************************************************************* + * The GPIO pins to work in different instances, requires this clock. + * For GPIO HP instance, enable M4 clock of type @ref sl_si91x_gpio_select_clock_t. + * For GPIO ULP/UULP instances, enable ULP clock of type + * @ref sl_si91x_gpio_select_clock_t + ******************************************************************************/ +void sl_si91x_gpio_enable_clock(sl_si91x_gpio_select_clock_t clock) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PARAMETER(clock)); + // Set M4 clock + if (clock == M4CLK_GPIO) { + SL_PERIPHERAL_CLK->CLK_ENABLE_SET_REG3_b.EGPIO_CLK_ENABLE_b = SET; + SL_PERIPHERAL_CLK->CLK_ENABLE_SET_REG2_b.EGPIO_PCLK_ENABLE_b = SET; + } + // Set ULP clock + else { + ULPCLK->ULP_MISC_SOFT_SET_REG_b.EGPIO_CLK_EN_b = SET; + ULPCLK->ULP_MISC_SOFT_SET_REG_b.EGPIO_PCLK_ENABLE_b = SET; + } +} + +/******************************************************************************* + * This API disables the M4/ ULP clock of GPIO instances. + * For GPIO HP instance, disable M4 clock of type @ref sl_si91x_gpio_select_clock_t. + * For GPIO ULP/UULP instances, disable ULP clock of type + * @ref sl_si91x_gpio_select_clock_t + ******************************************************************************/ +void sl_si91x_gpio_disable_clock(sl_si91x_gpio_select_clock_t clock) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PARAMETER(clock)); + // Clear M4 clock + if (clock == M4CLK_GPIO) { + SL_PERIPHERAL_CLK->CLK_ENABLE_SET_REG3_b.EGPIO_CLK_ENABLE_b = CLR; + SL_PERIPHERAL_CLK->CLK_ENABLE_SET_REG2_b.EGPIO_PCLK_ENABLE_b = CLR; + } + // Clear ULP clock + else { + ULPCLK->ULP_MISC_SOFT_SET_REG_b.EGPIO_CLK_EN_b = CLR; + ULPCLK->ULP_MISC_SOFT_SET_REG_b.EGPIO_PCLK_ENABLE_b = CLR; + } +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instances. + * It is used to enable the group interrupts. + * @note: We are calling this API, inside the group interrupt configuration API's + * @ref sl_si91x_gpio_configure_group_interrupt(), used for HP instance, + * @ref sl_si91x_gpio_configure_ulp_group_interrupt(), used for ULP instance. + * @note: Select HP GPIO pins for HP instances(GPIO_6 to GPIO_57). Do not use + * GPIO pin number(0 to 5) in HP instance as these are used for other functionality. + * @note: Select ULP GPIO pins for ULP instances(ULP_GPIO_0 to ULP_GPIO_11). +*******************************************************************************/ +void sl_si91x_gpio_enable_group_interrupt(sl_si91x_group_interrupt_t group_interrupt, uint8_t port, uint8_t pin) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PARAMETER(group_interrupt)); + // Enable group interrupt in ULP GPIO instance + if (port == SL_GPIO_ULP_PORT) { + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_ULP_PORT_PIN(port, pin)); + ULP_GPIO->GPIO_GRP_INTR[group_interrupt].GPIO_GRP_INTR_CTRL_REG_b.ENABLE_INTERRUPT = ENABLE; + // Enable group interrupt 1 in ULP GPIO instance + if (group_interrupt == GROUP_INT_1) { + ULP_GPIO->PIN_CONFIG[pin].GPIO_CONFIG_REG_b.GROUP_INTERRUPT1_ENABLE = ENABLE; + } else { + ULP_GPIO->PIN_CONFIG[pin].GPIO_CONFIG_REG_b.GROUP_INTERRUPT2_ENABLE = ENABLE; + } + } + // Enable group interrupt in HP GPIO instance + else { + SL_GPIO_ASSERT(SL_GPIO_NDEBUG_PORT_PIN(port, pin)); + GPIO->GPIO_GRP_INTR[group_interrupt].GPIO_GRP_INTR_CTRL_REG_b.ENABLE_INTERRUPT = ENABLE; + if (group_interrupt == GROUP_INT_1) { + // Enable group interrupt 1 in HP GPIO instance + GPIO->PIN_CONFIG[(port * MAX_GPIO_PORT_PIN) + pin].GPIO_CONFIG_REG_b.GROUP_INTERRUPT1_ENABLE = ENABLE; + } else { + // Enable group interrupt 2 in HP GPIO instance + GPIO->PIN_CONFIG[(port * MAX_GPIO_PORT_PIN) + pin].GPIO_CONFIG_REG_b.GROUP_INTERRUPT2_ENABLE = ENABLE; + } + } +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instances. + * It is used to disable the group interrupts. + * @note: Select HP GPIO pins for HP instances(GPIO_6 to GPIO_57). Do not use + * GPIO pin number(0 to 5) in HP instance as these are used for other functionality. + * @note: Select ULP GPIO pins for ULP instances(ULP_GPIO_0 to ULP_GPIO_11). +*******************************************************************************/ +void sl_si91x_gpio_disable_group_interrupt(sl_si91x_group_interrupt_t group_interrupt, uint8_t port, uint8_t pin) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PARAMETER(group_interrupt)); + // Disable group interrupt in ULP GPIO instance + if (port == SL_GPIO_ULP_PORT) { + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_ULP_PORT_PIN(port, pin)); + ULP_GPIO->GPIO_GRP_INTR[group_interrupt].GPIO_GRP_INTR_CTRL_REG_b.ENABLE_INTERRUPT = DISABLE; + // Disable group interrupt 1 in ULP GPIO instance + ULP_GPIO->PIN_CONFIG[pin].GPIO_CONFIG_REG_b.GROUP_INTERRUPT1_ENABLE = DISABLE; + } else { + SL_GPIO_ASSERT(SL_GPIO_NDEBUG_PORT_PIN(port, pin)); + // Disable group interrupt in HP GPIO instance + GPIO->GPIO_GRP_INTR[group_interrupt].GPIO_GRP_INTR_CTRL_REG_b.ENABLE_INTERRUPT = DISABLE; + if (group_interrupt == GROUP_INT_1) { + // Disable group interrupt 1 in HP GPIO instance + GPIO->PIN_CONFIG[(port * MAX_GPIO_PORT_PIN) + pin].GPIO_CONFIG_REG_b.GROUP_INTERRUPT1_ENABLE = DISABLE; + } else { + // Disable group interrupt 2 in HP GPIO instance + GPIO->PIN_CONFIG[(port * MAX_GPIO_PORT_PIN) + pin].GPIO_CONFIG_REG_b.GROUP_INTERRUPT2_ENABLE = DISABLE; + } + } +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instances. + * It is used to mask the group interrupts. + *******************************************************************************/ +void sl_si91x_gpio_mask_group_interrupt(uint8_t port, sl_si91x_group_interrupt_t group_interrupt) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PARAMETER(group_interrupt)); + if (port == SL_GPIO_ULP_PORT) { + // Enable group interrupt mask in ULP GPIO instance + ULP_GPIO->GPIO_GRP_INTR[group_interrupt].GPIO_GRP_INTR_CTRL_REG_b.MASK = ENABLE; + } else { + // Enable group interrupt mask in HP GPIO instance + GPIO->GPIO_GRP_INTR[group_interrupt].GPIO_GRP_INTR_CTRL_REG_b.MASK = ENABLE; + } +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instances. + * It is used to unmask the group interrupts. + * @note: We are calling this API, inside the group interrupt configuration API's + * @ref sl_si91x_gpio_configure_group_interrupt(), used for HP instance, + * @ref sl_si91x_gpio_configure_ulp_group_interrupt(), used for ULP instance. +*******************************************************************************/ +void sl_si91x_gpio_unmask_group_interrupt(uint8_t port, sl_si91x_group_interrupt_t group_interrupt) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PARAMETER(group_interrupt)); + if (port == SL_GPIO_ULP_PORT) { + // Disable group interrupt mask in ULP GPIO instance + ULP_GPIO->GPIO_GRP_INTR[group_interrupt].GPIO_GRP_INTR_CTRL_REG_b.MASK = DISABLE; + } else { + // Disable group interrupt mask in HP GPIO instance + GPIO->GPIO_GRP_INTR[group_interrupt].GPIO_GRP_INTR_CTRL_REG_b.MASK = DISABLE; + } +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instances. + * It is used to set level/edge event of group interrupt. + * @note: We are calling this API, inside the group interrupt configuration API's + * @ref sl_si91x_gpio_configure_group_interrupt(), used for HP instance, + * @ref sl_si91x_gpio_configure_ulp_group_interrupt(), used for ULP instance. + ******************************************************************************/ +void sl_si91x_gpio_set_group_interrupt_level_edge(uint8_t port, + sl_si91x_group_interrupt_t group_interrupt, + sl_si91x_gpio_level_edge_t level_edge) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PARAMETER(group_interrupt)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PARAMETER(level_edge)); + if (port == SL_GPIO_ULP_PORT) { + // Enable group level edge interrupt in ULP GPIO instance + ULP_GPIO->GPIO_GRP_INTR[group_interrupt].GPIO_GRP_INTR_CTRL_REG_b.LEVEL_EDGE = level_edge; + } else { + // Enable group level edge interrupt in HP GPIO instance + GPIO->GPIO_GRP_INTR[group_interrupt].GPIO_GRP_INTR_CTRL_REG_b.LEVEL_EDGE = level_edge; + } +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instances. + * It is used to get level/edge event of group interrupt. + ******************************************************************************/ +uint8_t sl_si91x_gpio_get_group_interrupt_level_edge(uint8_t port, sl_si91x_group_interrupt_t group_interrupt) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PARAMETER(group_interrupt)); + if (port == SL_GPIO_ULP_PORT) { + // Get group level edge interrupt in ULP GPIO instance + return ULP_GPIO->GPIO_GRP_INTR[group_interrupt].GPIO_GRP_INTR_CTRL_REG_b.LEVEL_EDGE; + } else { + // Get group level edge interrupt in HP GPIO instance + return GPIO->GPIO_GRP_INTR[group_interrupt].GPIO_GRP_INTR_CTRL_REG_b.LEVEL_EDGE; + } +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instances. + * It is used to set polarity of group interrupt. + * @note: We are calling this API, inside the group interrupt configuration API's + * @ref sl_si91x_gpio_configure_group_interrupt(), used for HP instance, + * @ref sl_si91x_gpio_configure_ulp_group_interrupt(), used for ULP instance. + * @note: Select HP GPIO pins for HP instances(GPIO_6 to GPIO_57). Do not use + * GPIO pin number(0 to 5) in HP instance as these are used for other functionality. + * @note: Select ULP GPIO pins for ULP instances(ULP_GPIO_0 to ULP_GPIO_11). + ******************************************************************************/ +void sl_si91x_gpio_set_group_interrupt_polarity(sl_si91x_group_interrupt_t group_interrupt, + uint8_t port, + uint8_t pin, + sl_si91x_gpio_polarity_t polarity) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PARAMETER(group_interrupt)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PARAMETER(polarity)); + if (port == SL_GPIO_ULP_PORT) { + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_ULP_PORT_PIN(port, pin)); + // Set group interrupt polarity in ULP GPIO instance + if (group_interrupt == GROUP_INT_1) { + ULP_GPIO->PIN_CONFIG[pin].GPIO_CONFIG_REG_b.GROUP_INTERRUPT1_POLARITY = polarity; + } else { + ULP_GPIO->PIN_CONFIG[pin].GPIO_CONFIG_REG_b.GROUP_INTERRUPT2_POLARITY = polarity; + } + } else { + SL_GPIO_ASSERT(SL_GPIO_NDEBUG_PORT_PIN(port, pin)); + // Set group interrupt polarity in HP GPIO instance + if (group_interrupt == GROUP_INT_1) { + GPIO->PIN_CONFIG[(port * MAX_GPIO_PORT_PIN) + pin].GPIO_CONFIG_REG_b.GROUP_INTERRUPT1_POLARITY = polarity; + } else { + GPIO->PIN_CONFIG[(port * MAX_GPIO_PORT_PIN) + pin].GPIO_CONFIG_REG_b.GROUP_INTERRUPT2_POLARITY = polarity; + } + } +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instances. + * It is used to get polarity of group interrupt . + * @note: Select HP GPIO pins for HP instances(GPIO_6 to GPIO_57). Do not use + * GPIO pin number(0 to 5) in HP instance as these are used for other functionality. + * @note: Select ULP GPIO pins for ULP instances(ULP_GPIO_0 to ULP_GPIO_11). + ******************************************************************************/ +uint8_t sl_si91x_gpio_get_group_interrupt_polarity(sl_si91x_group_interrupt_t group_interrupt, + uint8_t port, + uint8_t pin) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PARAMETER(group_interrupt)); + if (port == SL_GPIO_ULP_PORT) { + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_ULP_PORT_PIN(port, pin)); + // Get group interrupt polarity in ULP GPIO instance + return ULP_GPIO->PIN_CONFIG[pin].GPIO_CONFIG_REG_b.GROUP_INTERRUPT1_POLARITY; + } else { + SL_GPIO_ASSERT(SL_GPIO_NDEBUG_PORT_PIN(port, pin)); + // Get group interrupt polarity in HP GPIO instance + if (group_interrupt == GROUP_INT_1) { + return GPIO->PIN_CONFIG[(port * MAX_GPIO_PORT_PIN) + pin].GPIO_CONFIG_REG_b.GROUP_INTERRUPT1_POLARITY; + } else { + return GPIO->PIN_CONFIG[(port * MAX_GPIO_PORT_PIN) + pin].GPIO_CONFIG_REG_b.GROUP_INTERRUPT2_POLARITY; + } + } +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instances. + * It is used to select and/or event of group interrupt. + * @example: Consider two GPIO pins for group interrupts. + * - If AND event is selected then both GPIO pins, interrupt should be + * generated to do specific task. + * - If OR event is selected then any one GPIO pin, interrupt generation + * should be enough to do specific task. + * @note: We are calling this API, inside the group interrupt configuration API's + * @ref sl_si91x_gpio_configure_group_interrupt(), used for HP instance, + * @ref sl_si91x_gpio_configure_ulp_group_interrupt(), used for ULP instance. +*******************************************************************************/ +void sl_si91x_gpio_select_group_interrupt_and_or(uint8_t port, + sl_si91x_group_interrupt_t group_interrupt, + sl_si91x_gpio_and_or_t and_or) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PARAMETER(group_interrupt)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PARAMETER(and_or)); + if (port == SL_GPIO_ULP_PORT) { + // Set group interrupt OR in ULP GPIO instance + if ((and_or & SL_GPIO_GROUP_INTERRUPT_OR) == (SL_GPIO_GROUP_INTERRUPT_OR)) { + ULP_GPIO->GPIO_GRP_INTR[group_interrupt].GPIO_GRP_INTR_CTRL_REG_b.AND_OR = SET; + } + // Set group interrupt AND in ULP GPIO instance + else { + ULP_GPIO->GPIO_GRP_INTR[group_interrupt].GPIO_GRP_INTR_CTRL_REG_b.AND_OR = CLR; + } + } else { + // Set group interrupt OR in HP GPIO instance + if ((and_or & SL_GPIO_GROUP_INTERRUPT_OR) == (SL_GPIO_GROUP_INTERRUPT_OR)) { + GPIO->GPIO_GRP_INTR[group_interrupt].GPIO_GRP_INTR_CTRL_REG_b.AND_OR = SET; + } + // Set group interrupt AND in HP GPIO instance + else { + GPIO->GPIO_GRP_INTR[group_interrupt].GPIO_GRP_INTR_CTRL_REG_b.AND_OR = CLR; + } + } +} + +/******************************************************************************* + * This API is used in GPIO HP instance to configure group interrupts. + * It has configuration pointer of type @ref sl_si91x_gpio_group_interrupt_config_t + * structure. + * GPIO HP instance has total 4 ports. Port-0, 1, 2 has 16 pins each. Port-3 has 9 pins. + * While configuring group interrupts, one can select random ports and pins for + * group interrupt. + * @example 1: + * - If port 1 is selected, any group of pins(0 to 16) can be selected for group interrupt. + * - Same applied for other ports also. + * @example 2: + * - Once can select port 1, pin 7 and port 2, pin 3 as a group for interrupt generation. + * - One should assign group count of how many pins are passed. + * For more clarification look into group interrupt configuration structure + * @ref sl_si91x_gpio_group_interrupt_config_t. + * @note: Do not use Port 0, GPIO pin number(0 to 5) in HP instance + * as these are used for other functionality. +*******************************************************************************/ +void sl_si91x_gpio_configure_group_interrupt(sl_si91x_gpio_group_interrupt_config_t *configuration) +{ + uint8_t int_pin_count; + // Group interrupt pin configuration in HP GPIO instance + for (int_pin_count = 0; int_pin_count < configuration->grp_interrupt_cnt; int_pin_count++) { + sl_gpio_set_pin_mode(configuration->grp_interrupt_port[int_pin_count], + configuration->grp_interrupt_pin[int_pin_count], + SL_GPIO_MODE_0, + SET); + sl_si91x_gpio_set_pin_direction(configuration->grp_interrupt_port[int_pin_count], + configuration->grp_interrupt_pin[int_pin_count], + GPIO_INPUT); + sl_si91x_gpio_enable_pad_receiver(configuration->grp_interrupt_pin[int_pin_count]); + sl_si91x_gpio_set_group_interrupt_polarity(configuration->grp_interrupt, + configuration->grp_interrupt_port[int_pin_count], + configuration->grp_interrupt_pin[int_pin_count], + configuration->grp_interrupt_pol[int_pin_count]); + sl_si91x_gpio_set_group_interrupt_level_edge(configuration->grp_interrupt_port[int_pin_count], + configuration->grp_interrupt, + configuration->level_edge); + sl_si91x_gpio_select_group_interrupt_and_or(configuration->grp_interrupt_port[int_pin_count], + configuration->grp_interrupt, + configuration->and_or); + sl_si91x_gpio_enable_group_interrupt(configuration->grp_interrupt, + configuration->grp_interrupt_port[int_pin_count], + configuration->grp_interrupt_pin[int_pin_count]); + sl_si91x_gpio_unmask_group_interrupt(configuration->grp_interrupt_port[int_pin_count], + configuration->grp_interrupt); + } + // NVIC enable for group interrupt 1 + if (configuration->grp_interrupt == GROUP_INT_1) { + NVIC_EnableIRQ(GROUP_0_INTERRUPT_NAME); + NVIC_SetPriority(GROUP_0_INTERRUPT_NAME, PRIORITY_50); + } + // NVIC enable for group interrupt 2 + else if (configuration->grp_interrupt == GROUP_INT_2) { + NVIC_EnableIRQ(GROUP_1_INTERRUPT_NAME); + NVIC_SetPriority(GROUP_1_INTERRUPT_NAME, PRIORITY_51); + } +} + +/******************************************************************************* + * This API is used to configure the pin interrupt in GPIO ULP instance. + * There are total 12 pin interrupts in this instance. + * To configure the interrupt, first ULP GPIO initialization must be done. + * The actions to be performed in ULP GPIO initialization are: + * - Enable the ULP clock of GPIO ULP instance. + * - Enable ULP PAD receiver for GPIO pin number, whether GPIO pin is selected as + * output/input. + * - Set pin mode and direction of the GPIO pin. + * Configuring the pin interrupt requires pin number, interrupt number, + * and interrupt flag to be generated. + * Enable the IRQ handler. + * @note: Select ULP GPIO pins for ULP instances(ULP_GPIO_0 to ULP_GPIO_11). +*******************************************************************************/ +void sl_si91x_gpio_configure_ulp_pin_interrupt(uint8_t int_no, + sl_si91x_gpio_interrupt_config_flag_t flags, + sl_si91x_gpio_pin_ulp_t pin) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_ULP_PIN(pin)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_FLAG(flags)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_ULP_INTR(int_no)); + // Pin interrupt configuration in ULP GPIO instance + ULP_GPIO->INTR[int_no].GPIO_INTR_CTRL_b.PORT_NUMBER = ULP_PORT_NUM; + ULP_GPIO->INTR[int_no].GPIO_INTR_CTRL_b.PIN_NUMBER = pin; + // Enable GPIO interrupt rising and falling edge + if ((flags & SL_GPIO_INTERRUPT_RISE_FALL_EDGE) == SL_GPIO_INTERRUPT_RISE_FALL_EDGE) { + ULP_GPIO->INTR[int_no].GPIO_INTR_CTRL_b.RISE_EDGE_ENABLE = SL_GPIO_INTERRUPT_ENABLE; + ULP_GPIO->INTR[int_no].GPIO_INTR_CTRL_b.FALL_EDGE_ENABLE = SL_GPIO_INTERRUPT_ENABLE; + } else { + ULP_GPIO->INTR[int_no].GPIO_INTR_CTRL_b.RISE_EDGE_ENABLE = SL_GPIO_INTERRUPT_DISABLE; + ULP_GPIO->INTR[int_no].GPIO_INTR_CTRL_b.FALL_EDGE_ENABLE = SL_GPIO_INTERRUPT_DISABLE; + } + // Enable or disable GPIO interrupt falling edge + if ((flags & SL_GPIO_INTERRUPT_FALL_EDGE) == SL_GPIO_INTERRUPT_FALL_EDGE) { + ULP_GPIO->INTR[int_no].GPIO_INTR_CTRL_b.FALL_EDGE_ENABLE = SL_GPIO_INTERRUPT_ENABLE; + } else { + ULP_GPIO->INTR[int_no].GPIO_INTR_CTRL_b.FALL_EDGE_ENABLE = SL_GPIO_INTERRUPT_DISABLE; + } + // Enable or disable GPIO interrupt rising edge + if ((flags & SL_GPIO_INTERRUPT_RISE_EDGE) == SL_GPIO_INTERRUPT_RISE_EDGE) { + ULP_GPIO->INTR[int_no].GPIO_INTR_CTRL_b.RISE_EDGE_ENABLE = SL_GPIO_INTERRUPT_ENABLE; + } else { + ULP_GPIO->INTR[int_no].GPIO_INTR_CTRL_b.RISE_EDGE_ENABLE = SL_GPIO_INTERRUPT_DISABLE; + } + // Enable or disable GPIO interrupt level high + if ((flags & SL_GPIO_INTERRUPT_LEVEL_HIGH) == SL_GPIO_INTERRUPT_LEVEL_HIGH) { + ULP_GPIO->INTR[int_no].GPIO_INTR_CTRL_b.LEVEL_HIGH_ENABLE = SL_GPIO_INTERRUPT_ENABLE; + } else { + ULP_GPIO->INTR[int_no].GPIO_INTR_CTRL_b.LEVEL_HIGH_ENABLE = SL_GPIO_INTERRUPT_DISABLE; + } + // Enable or disable GPIO interrupt level low + if ((flags & SL_GPIO_INTERRUPT_LEVEL_LOW) == SL_GPIO_INTERRUPT_LEVEL_LOW) { + ULP_GPIO->INTR[int_no].GPIO_INTR_CTRL_b.LEVEL_LOW_ENABLE = SL_GPIO_INTERRUPT_ENABLE; + } else { + ULP_GPIO->INTR[int_no].GPIO_INTR_CTRL_b.LEVEL_LOW_ENABLE = SL_GPIO_INTERRUPT_DISABLE; + } + // Un-mask the interrupt + ULP_GPIO->INTR[int_no].GPIO_INTR_CTRL_b.MASK = CLR; +} + +/******************************************************************************* + * This API is used in GPIO ULP instance to configure group interrupts. + * It has configuration pointer of type @ref sl_si91x_gpio_group_interrupt_config_t + * structure. + * ULP GPIO domain has only one port and calling as Port 4 in program which has maximum of 12 pins. + * While configuring group interrupts, one can select random pins which are allocated for + * ULP port. + * - One should assign group count of how many pins are passed. + * For more clarification look into group interrupt configuration structure + * @ref sl_si91x_gpio_group_interrupt_config_t. +*******************************************************************************/ +void sl_si91x_gpio_configure_ulp_group_interrupt(sl_si91x_gpio_group_interrupt_config_t *configuration) +{ + uint8_t int_pin_count; + // Group interrupt pin configuration in ULP GPIO instance + for (int_pin_count = 0; int_pin_count < configuration->grp_interrupt_cnt; int_pin_count++) { + sl_gpio_set_pin_mode(SL_GPIO_ULP_PORT, configuration->grp_interrupt_pin[int_pin_count], SL_GPIO_MODE_0, SET); + sl_si91x_gpio_set_pin_direction(SL_GPIO_ULP_PORT, configuration->grp_interrupt_pin[int_pin_count], GPIO_INPUT); + sl_si91x_gpio_enable_ulp_pad_receiver(configuration->grp_interrupt_pin[int_pin_count]); + sl_si91x_gpio_set_group_interrupt_polarity(configuration->grp_interrupt, + SL_GPIO_ULP_PORT, + configuration->grp_interrupt_pin[int_pin_count], + configuration->grp_interrupt_pol[int_pin_count]); + sl_si91x_gpio_set_group_interrupt_level_edge(SL_GPIO_ULP_PORT, + configuration->grp_interrupt, + configuration->level_edge); + sl_si91x_gpio_select_group_interrupt_and_or(SL_GPIO_ULP_PORT, configuration->grp_interrupt, configuration->and_or); + sl_si91x_gpio_enable_group_interrupt(configuration->grp_interrupt, + SL_GPIO_ULP_PORT, + configuration->grp_interrupt_pin[int_pin_count]); + sl_si91x_gpio_unmask_group_interrupt(SL_GPIO_ULP_PORT, configuration->grp_interrupt); + } + // NVIC enable for ULP group interrupt + NVIC_EnableIRQ(ULP_GROUP_INTERRUPT_NAME); + NVIC_SetPriority(ULP_GROUP_INTERRUPT_NAME, PRIORITY_19); +} + +/******************************************************************************* + * This API is used for GPIO HP instance. + * It is used to clear group interrupt. +*******************************************************************************/ +void sl_si91x_gpio_clear_group_interrupt(sl_si91x_group_interrupt_t group_interrupt) +{ + // Clear group interrupt in HP GPIO instance + GPIO->GPIO_GRP_INTR[group_interrupt].GPIO_GRP_INTR_STS_b.INTERRUPT_STATUS = SET; +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instance. + * It is used to get status of group interrupt generated. + ******************************************************************************/ +uint32_t sl_si91x_gpio_get_group_interrupt_status(uint8_t port, sl_si91x_group_interrupt_t group_interrupt) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PARAMETER(group_interrupt)); + if (port == SL_GPIO_ULP_PORT) { + // Get group interrupt status in ULP GPIO instance + return ULP_GPIO->GPIO_GRP_INTR[group_interrupt].GPIO_GRP_INTR_STS; + } else { + // Get group interrupt status in HP GPIO instance + return GPIO->GPIO_GRP_INTR[group_interrupt].GPIO_GRP_INTR_STS; + } +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instance. + * It is used to select group interrupt wakeup. + ******************************************************************************/ +void sl_si91x_gpio_select_group_interrupt_wakeup(uint8_t port, + sl_si91x_group_interrupt_t group_interrupt, + uint8_t flags) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PARAMETER(group_interrupt)); + // Enables or Disables wakeup group interrupt in ULP GPIO instance + if (port == SL_GPIO_ULP_PORT) { + if ((flags & SL_GPIO_GROUP_INTERRUPT_WAKEUP) == (SL_GPIO_GROUP_INTERRUPT_WAKEUP)) { + ULP_GPIO->GPIO_GRP_INTR[group_interrupt].GPIO_GRP_INTR_CTRL_REG_b.ENABLE_WAKEUP = SET; + } else { + ULP_GPIO->GPIO_GRP_INTR[group_interrupt].GPIO_GRP_INTR_CTRL_REG_b.ENABLE_WAKEUP = CLR; + } + } else { + // Enables or Disables wakeup group interrupt in HP GPIO instance + if ((flags & SL_GPIO_GROUP_INTERRUPT_WAKEUP) == (SL_GPIO_GROUP_INTERRUPT_WAKEUP)) { + GPIO->GPIO_GRP_INTR[group_interrupt].GPIO_GRP_INTR_CTRL_REG_b.ENABLE_WAKEUP = SET; + } else { + GPIO->GPIO_GRP_INTR[group_interrupt].GPIO_GRP_INTR_CTRL_REG_b.ENABLE_WAKEUP = CLR; + } + } +} + +/******************************************************************************* + * To enable ULP PAD receiver in GPIO ULP instance, ULP GPIO initialization needs to be done first. + * - The actions to be performed in ULP GPIO initialization are: + * - Enable the ULP clock of GPIO ULP instance. + * - Enable ULP PAD receiver for GPIO pin number, whether GPIO pin is selected as + * output/input. + * @note: Select ULP GPIO pins for ULP instances(ULP_GPIO_0 to ULP_GPIO_11). +*******************************************************************************/ +void sl_si91x_gpio_enable_ulp_pad_receiver(uint8_t gpio_num) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_ULP_PIN(gpio_num)); + // Enable receiver bit in PAD configuration register in ULP instance + ULP_PAD_CONFIG_REG |= BIT(gpio_num); +} + +/******************************************************************************* + * This API is used to disable the ULP PAD receiver. + * @note: Select ULP GPIO pins for ULP instances(ULP_GPIO_0 to ULP_GPIO_11). +*******************************************************************************/ +void sl_si91x_gpio_disable_ulp_pad_receiver(uint32_t gpio_num) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_ULP_PIN(gpio_num)); + // Disable receiver bit in PAD configuration register in ULP instance + ULP_PAD_CONFIG_REG &= ~BIT(gpio_num); +} + +/******************************************************************************* + * To select the ULP PAD driver disable state in GPIO ULP instance, ULP GPIO initialization + * needs to be done first. + * - The actions to be performed in ULP GPIO initialization are: + * - Enable the ULP clock of GPIO ULP instance. + * - Enable ULP PAD receiver for GPIO pin number, whether GPIO pin is selected as + * output/input. + * - Set pin mode and direction of the GPIO pin. + * - Select the PAD driver disable state of type @ref sl_si91x_gpio_driver_disable_state_t. + * @note: Select ULP GPIO pins for ULP instances(ULP_GPIO_0 to ULP_GPIO_11). + ******************************************************************************/ +void sl_si91x_gpio_select_ulp_pad_driver_disable_state(uint8_t gpio_num, + sl_si91x_gpio_driver_disable_state_t disable_state) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_ULP_PIN(gpio_num)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_DISABLE_STATE(disable_state)); + // Select driver disable state in ULP PAD configuration registers + if (gpio_num <= GPIO_PAD_3) { + ULP_PAD_CONFIG0_REG->ULP_GPIO_PAD_CONFIG_REG_0.PADCONFIG_P1_P2_1 = disable_state; + } else if ((gpio_num >= GPIO_PAD_4) && (gpio_num <= GPIO_PAD_7)) { + ULP_PAD_CONFIG0_REG->ULP_GPIO_PAD_CONFIG_REG_0.PADCONFIG_P1_P2_2 = disable_state; + } else { + ULP_PAD_CONFIG1_REG->ULP_GPIO_PAD_CONFIG_REG_1.PADCONFIG_P1_P2_1 = disable_state; + } +} + +/******************************************************************************* + * To select the ULP PAD driver strength in GPIO ULP instance, ULP GPIO initialization + * needs to be done first. + * - The actions to be performed in ULP GPIO initialization are: + * - Enable the ULP clock of GPIO ULP instance. + * - Enable ULP PAD receiver for GPIO pin number, whether GPIO pin is selected as + * output/input. + * - Set pin mode and direction of the GPIO pin. + * - Select the PAD driver strength of type @ref sl_si91x_gpio_driver_strength_select_t. + * @note: Select ULP GPIO pins for ULP instances(ULP_GPIO_0 to ULP_GPIO_11). + ******************************************************************************/ +void sl_si91x_gpio_select_ulp_pad_driver_strength(uint8_t gpio_num, sl_si91x_gpio_driver_strength_select_t strength) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_ULP_PIN(gpio_num)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_STRENGTH(strength)); + // Select drive strength in ULP PAD configuration registers + if (gpio_num <= GPIO_PAD_3) { + ULP_PAD_CONFIG0_REG->ULP_GPIO_PAD_CONFIG_REG_0.PADCONFIG_E1_E2_1 = strength; + } else if ((gpio_num >= GPIO_PAD_4) && (gpio_num <= GPIO_PAD_7)) { + ULP_PAD_CONFIG0_REG->ULP_GPIO_PAD_CONFIG_REG_0.PADCONFIG_E1_E2_2 = strength; + } else { + ULP_PAD_CONFIG1_REG->ULP_GPIO_PAD_CONFIG_REG_1.PADCONFIG_E1_E2_1 = strength; + } +} + +/******************************************************************************* + * To select the ULP PAD slew rate in GPIO ULP instance, ULP GPIO initialization + * needs to be done first. + * - The actions to be performed in ULP GPIO initialization are: + * - Enable the ULP clock of GPIO ULP instance. + * - Enable ULP PAD receiver for GPIO pin number, whether GPIO pin is selected as + * output/input. + * - Set pin mode and direction of the GPIO pin. + * - Select the PAD slew rate of type @ref sl_si91x_gpio_slew_rate_t. + * @note: Select ULP GPIO pins for ULP instances(ULP_GPIO_0 to ULP_GPIO_11). + ******************************************************************************/ +void sl_si91x_gpio_select_ulp_pad_slew_rate(uint8_t gpio_num, sl_si91x_gpio_slew_rate_t slew_rate) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_ULP_PIN(gpio_num)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PARAMETER(slew_rate)); + // Select slew rate in ULP PAD configuration registers + if (gpio_num <= GPIO_PAD_3) { + ULP_PAD_CONFIG0_REG->ULP_GPIO_PAD_CONFIG_REG_0.PADCONFIG_SR_1 = slew_rate; + } else if ((gpio_num >= GPIO_PAD_4) && (gpio_num <= GPIO_PAD_7)) { + ULP_PAD_CONFIG0_REG->ULP_GPIO_PAD_CONFIG_REG_0.PADCONFIG_SR_2 = slew_rate; + } else { + ULP_PAD_CONFIG1_REG->ULP_GPIO_PAD_CONFIG_REG_1.PADCONFIG_SR_1 = slew_rate; + } +} + +/******************************************************************************* + * This API is used to select the UULP mode in NPSS GPIO control register. + * Few actions are required to be performed before setting the mode, + * - Enable the ULP clock using @ref sl_si91x_gpio_enable_clock() API. + * - Select UULP NPSS receiver for UULP GPIO pin. + * @note: Select UULP GPIO pins for UULP instances(UULP_GPIO_0 to UULP_GPIO_4). + ******************************************************************************/ +void sl_si91x_gpio_set_uulp_npss_pin_mux(uint8_t pin, sl_si91x_uulp_npss_mode_t mode) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_UULP_PIN(pin)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_MODE_PARAMETER(mode)); + // Select pin mode in UULP GPIO instance + UULP_GPIO->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_MODE = mode; +} + +/******************************************************************************* + * This API is used to enable receiver bit in NPSS GPIO control register. + * Enable the ULP clock using @ref sl_si91x_gpio_enable_clock() API, before + * using this API. + * @note: Select UULP GPIO pins for UULP instances(UULP_GPIO_0 to UULP_GPIO_4). + ******************************************************************************/ +void sl_si91x_gpio_select_uulp_npss_receiver(uint8_t pin, sl_si91x_gpio_receiver_t receiver) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_UULP_PIN(pin)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PARAMETER(receiver)); + // Select input buffer in UULP GPIO instance + UULP_GPIO->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_REN = receiver; +} + +/******************************************************************************* + * This API is used to select the UULP direction in NPSS GPIO control register. + * Few actions are required to be performed before setting the direction, + * - Enable the ULP clock using @ref sl_si91x_gpio_enable_clock() API. + * - Select UULP NPSS receiver for UULP GPIO pin. + * - Select UULP NPSS direction for UULP GPIO pin. + * - Set the mode of the GPIO pin. + * @note: Select UULP GPIO pins for UULP instances(UULP_GPIO_0 to UULP_GPIO_4). + ******************************************************************************/ +void sl_si91x_gpio_set_uulp_npss_direction(uint8_t pin, sl_si91x_gpio_direction_t direction) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_UULP_PIN(pin)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PARAMETER(direction)); + // Set direction(input/output) in UULP GPIO instance + UULP_GPIO->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_OEN = direction; +} + +/******************************************************************************* + * This API is used to get the UULP direction in NPSS GPIO control register. + * Few actions are required to be performed before setting the direction, + * - Enable the ULP clock using @ref sl_si91x_gpio_enable_clock() API. + * - Select UULP NPSS receiver for UULP GPIO pin. + * - Set the mode of the GPIO pin. + * - Set the direction of the GPIO pin. + * - Get the direction of the GPIO pin. + * @note: Select UULP GPIO pins for UULP instances(UULP_GPIO_0 to UULP_GPIO_4). +*******************************************************************************/ +uint8_t sl_si91x_gpio_get_uulp_npss_direction(uint8_t pin) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_UULP_PIN(pin)); + // Get direction(input/output) in UULP GPIO instance + return UULP_GPIO->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_OEN; +} + +/******************************************************************************* + * This API is used to select the UULP pin value in NPSS GPIO control register. + * Few actions are required to be performed before setting the direction, + * - Enable the ULP clock using @ref sl_si91x_gpio_enable_clock() API. + * - Select UULP NPSS receiver for UULP GPIO pin. + * - Set the mode of the GPIO pin. + * - Set the direction of the GPIO pin. + * - Select the GPIO pin value. + * @note: Select UULP GPIO pins for UULP instances(UULP_GPIO_0 to UULP_GPIO_4). + ******************************************************************************/ +void sl_si91x_gpio_set_uulp_npss_pin_value(uint8_t pin, sl_si91x_gpio_pin_value_t pin_value) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_UULP_PIN(pin)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PARAMETER(pin_value)); + // Set or Clear pin in UULP GPIO instance by controlling pin value + UULP_GPIO->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_OUT = pin_value; +} + +/******************************************************************************* + * This API is used to toggle the UULP pin. + * Few actions are required to be performed before setting the direction, + * - Enable the ULP clock using @ref sl_si91x_gpio_enable_clock() API. + * - Select UULP NPSS receiver for UULP GPIO pin. + * - Set the mode of the GPIO pin. + * - Set the direction of the GPIO pin. + * - Toggle the UULP GPIO pin. + * @note: Select UULP GPIO pins for UULP instances(UULP_GPIO_0 to UULP_GPIO_4). + ******************************************************************************/ +void sl_si91x_gpio_toggle_uulp_npss_pin(uint8_t pin) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_UULP_PIN(pin)); + // Set or Clear pin in UULP GPIO instance by controlling pin value + UULP_GPIO->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_OUT ^= SET; +} + +/******************************************************************************* + * This API is used to get the UULP pin value in NPSS GPIO control register. + * Few actions are required to be performed before setting the direction, + * - Enable the ULP clock using @ref sl_si91x_gpio_enable_clock() API. + * - Select UULP NPSS receiver for UULP GPIO pin. + * - Set the mode of the GPIO pin. + * - Set the direction of the GPIO pin. + * - Select the GPIO pin value. + * - Get the GPIO pin value. + * @note: Select UULP GPIO pins for UULP instances(UULP_GPIO_0 to UULP_GPIO_4). + ******************************************************************************/ +uint8_t sl_si91x_gpio_get_uulp_npss_pin(uint8_t pin) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_UULP_PIN(pin)); + // Read pin status in UULP GPIO instance + return (UULP_GPIO_STATUS >> pin) & MASK_INTR; +} + +/******************************************************************************* + * This API is used to select polarity of the UULP GPIO to be considered + when used as a wakeup source from any of the Sleep States. + ******************************************************************************/ +void sl_si91x_gpio_select_uulp_npss_polarity(uint8_t pin, sl_si91x_gpio_polarity_t polarity) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_UULP_PIN(pin)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PARAMETER(polarity)); + UULP_GPIO->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_POLARITY = polarity; +} + +/******************************************************************************* + * This API is used to set the UULP NPSS GPIO to wakeup interrupt +*******************************************************************************/ +void sl_si91x_gpio_set_uulp_npss_wakeup_interrupt(uint8_t npssgpio_interrupt) +{ + UULP_GPIO_FSM->GPIO_WAKEUP_REGISTER |= (BIT(npssgpio_interrupt)); +} + +/******************************************************************************* + * This API is used to clear the UULP NPSS GPIO to wakeup interrupt +*******************************************************************************/ +void sl_si91x_gpio_clear_uulp_npss_wakeup_interrupt(uint8_t npssgpio_interrupt) +{ + UULP_GPIO_FSM->GPIO_WAKEUP_REGISTER |= (BIT(npssgpio_interrupt)); +} + +/******************************************************************************* + * This API is used to mask the UULP NPSS GPIO interrupt. + * Few actions are required to be performed before interrupt mask is performed, + * - Enable the ULP clock using @ref sl_si91x_gpio_enable_clock() API. + * - Select the . + * @note: All the UULP interrupts are masked by default. +*******************************************************************************/ +void sl_si91x_gpio_mask_uulp_npss_interrupt(uint8_t npssgpio_interrupt) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_UULP_INTR(npssgpio_interrupt)); + GPIO_NPSS_INTERRUPT_MASK_SET_REG = (npssgpio_interrupt << 1); +} + +/******************************************************************************* + * This API is used to un-mask the UULP NPSS GPIO interrupt. + * Few actions are required to be performed before interrupt un-mask is performed, + * - Enable the ULP clock using @ref sl_si91x_gpio_enable_clock() API. + * - Set UULP PAD configuration register. + * - Select UULP NPSS receiver for UULP GPIO pin. + * - Set the mode of the GPIO pin. + * - Set the direction of the GPIO pin. + * - Un-mask interrupt by setting corresponding bit in register. + * @note: All the UULP interrupts are masked by default. +*******************************************************************************/ +void sl_si91x_gpio_unmask_uulp_npss_interrupt(uint8_t npssgpio_interrupt) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_UULP_INTR(npssgpio_interrupt)); + GPIO_NPSS_INTERRUPT_MASK_CLR_REG = (npssgpio_interrupt << 1); +} + +/******************************************************************************* + * This API is used to clear the UULP interrupt. +*******************************************************************************/ +void sl_si91x_gpio_clear_uulp_interrupt(uint8_t npssgpio_interrupt) +{ + GPIO_NPSS_INTERRUPT_CLEAR_REG = (npssgpio_interrupt << 1); +} + +/******************************************************************************* + * This API is used to get the UULP interrupt status. + ******************************************************************************/ +uint8_t sl_si91x_gpio_get_uulp_interrupt_status(void) +{ + return (GPIO_NPSS_INTERRUPT_STATUS_REG >> 1) & UULP_PIN_MASK; +} + +/******************************************************************************* + * This API is used to get the ULP interrupt status. + ******************************************************************************/ +uint32_t sl_si91x_gpio_get_ulp_interrupt_status(uint32_t flags) +{ + return ULP_GPIO->INTR[flags].GPIO_INTR_STATUS_b.INTERRUPT_STATUS; +} + +/******************************************************************************* + * This API is used to configure the pin interrupt in GPIO UULP instance. + * There are total 5 pin interrupts in this instance. + * To configure the interrupt, first UULP GPIO initialization must be done. + * The actions to be performed in UULP GPIO initialization are: + * - Enable the ULP clock using @ref sl_si91x_gpio_enable_clock() API. + * - Set UULP PAD configuration register. + * - Select UULP NPSS receiver for UULP GPIO pin. + * - Set the mode of the GPIO pin. + * - Set the direction of the GPIO pin. + * - Configure the UULP pin interrupt. + * Enable the IRQ handler. +*******************************************************************************/ +void sl_si91x_gpio_configure_uulp_interrupt(sl_si91x_gpio_interrupt_config_flag_t flags, uint8_t npssgpio_interrupt) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_FLAG(flags)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_INTR(npssgpio_interrupt)); + npssgpio_interrupt = BIT(npssgpio_interrupt); + // Unmask NPSS interrupt + sl_si91x_gpio_unmask_uulp_npss_interrupt(npssgpio_interrupt); + // Enable GPIO interrupt rising and falling edge + if ((flags & SL_GPIO_INTERRUPT_RISE_FALL_EDGE) == SL_GPIO_INTERRUPT_RISE_FALL_EDGE) { + GPIO_NPSS_GPIO_CONFIG_REG |= (npssgpio_interrupt << BIT_0); + GPIO_NPSS_GPIO_CONFIG_REG |= (npssgpio_interrupt << BIT_8); + } else { + GPIO_NPSS_GPIO_CONFIG_REG &= ~((uint32_t)npssgpio_interrupt << BIT_0); + GPIO_NPSS_GPIO_CONFIG_REG &= ~((uint32_t)npssgpio_interrupt << BIT_8); + } + // Enable or disable interrupt rising edge in UULP GPIO instance + if ((flags & SL_GPIO_INTERRUPT_RISE_EDGE) == SL_GPIO_INTERRUPT_RISE_EDGE) { + GPIO_NPSS_GPIO_CONFIG_REG |= (npssgpio_interrupt << BIT_0); + } else { + GPIO_NPSS_GPIO_CONFIG_REG &= ~((uint32_t)npssgpio_interrupt << BIT_0); + } + // Enable or disable GPIO interrupt falling edge in UULP GPIO instance + if ((flags & SL_GPIO_INTERRUPT_FALL_EDGE) == SL_GPIO_INTERRUPT_FALL_EDGE) { + GPIO_NPSS_GPIO_CONFIG_REG |= (npssgpio_interrupt << BIT_8); + } else { + GPIO_NPSS_GPIO_CONFIG_REG &= ~((uint32_t)npssgpio_interrupt << BIT_8); + } + // Enable or disable interrupt level low in UULP GPIO instance + if ((flags & SL_GPIO_INTERRUPT_LEVEL_LOW) == SL_GPIO_INTERRUPT_LEVEL_LOW) { + GPIO_NPSS_GPIO_CONFIG_REG |= (npssgpio_interrupt << BIT_16); + } else { + GPIO_NPSS_GPIO_CONFIG_REG &= ~((uint32_t)npssgpio_interrupt << BIT_16); + } + // Enable or disable interrupt level high in UULP GPIO instance + if ((flags & SL_GPIO_INTERRUPT_LEVEL_HIGH) == SL_GPIO_INTERRUPT_LEVEL_HIGH) { + GPIO_NPSS_GPIO_CONFIG_REG |= (npssgpio_interrupt << BIT_24); + } else { + GPIO_NPSS_GPIO_CONFIG_REG &= ~((uint32_t)npssgpio_interrupt << BIT_24); + } + NVIC_EnableIRQ(UULP_PININT_NVIC_NAME); +} + +/******************************************************************************* + * This API is used to clear one (or) more pending ULP GPIO interrupts. +*******************************************************************************/ +void sl_si91x_gpio_clear_ulp_interrupt(uint32_t flags) +{ + ULP_GPIO->INTR[flags].GPIO_INTR_STATUS_b.INTERRUPT_STATUS = SET; +} + +/******************************************************************************* + * This API is used to clear the ULP group interrupts. +*******************************************************************************/ +void sl_si91x_gpio_clear_ulp_group_interrupt(sl_si91x_group_interrupt_t group_interrupt) +{ + ULP_GPIO->GPIO_GRP_INTR[group_interrupt].GPIO_GRP_INTR_STS_b.INTERRUPT_STATUS = SET; +} + +/******************************************************************************* + * This API is used to verify assumptions and print message if the assumption is false. + ******************************************************************************/ +void sl_assert_failed(uint8_t *file, uint32_t line) +{ +#ifdef DEBUG_UART + DEBUGOUT("Assert failed: file %s on line %lu \r\n", file, line); +#else + (void)file; + (void)line; +#endif +} + +/******************************************************************************* + * This API is used to select the UULP PAD configuration register. + * It has pad_config pointer of type @ref uulp_pad_config_t. + * It selects the mode, direction, polarity, enables receiver etc in the register. + * To set the UULP PAD configuration, + * - Enable the ULP clock using @ref sl_si91x_gpio_enable_clock() API. + * - Select UULP NPSS input buffer for UULP GPIO pin. + * @note: Select UULP GPIO pins for UULP instances(UULP_GPIO_0 to UULP_GPIO_4). +*******************************************************************************/ +void sl_si91x_gpio_set_uulp_pad_configuration(uulp_pad_config_t *pad_config) +{ + UULP_PAD_CONFIG_REG(pad_config->gpio_padnum)->UULP_GPIO_PAD_CONFIG_REG_b.GPIO_MODE = + (sl_si91x_uulp_npss_mode_t)pad_config->mode; + UULP_PAD_CONFIG_REG(pad_config->gpio_padnum)->UULP_GPIO_PAD_CONFIG_REG_b.GPIO_REN = + (sl_si91x_gpio_receiver_t)pad_config->receiver; + UULP_PAD_CONFIG_REG(pad_config->gpio_padnum)->UULP_GPIO_PAD_CONFIG_REG_b.GPIO_OEN = + (sl_si91x_gpio_direction_t)pad_config->direction; + UULP_PAD_CONFIG_REG(pad_config->gpio_padnum)->UULP_GPIO_PAD_CONFIG_REG_b.GPIO_OUTPUT = + (sl_si91x_gpio_pin_value_t)pad_config->output; + UULP_PAD_CONFIG_REG(pad_config->gpio_padnum)->UULP_GPIO_PAD_CONFIG_REG_b.GPIO_PAD_SELECT = + (sl_si91x_gpio_uulp_pad_t)pad_config->pad_select; + UULP_PAD_CONFIG_REG(pad_config->gpio_padnum)->UULP_GPIO_PAD_CONFIG_REG_b.GPIO_POLARITY = + (sl_si91x_gpio_polarity_t)pad_config->polarity; +} + +/******************************************************************************* + * To get the release, sqa and dev version of gpio peripheral + * It returns the structure for gpio version. + * Structure includes three members: + * - Release version + * - Major version (SQA version) + * - Minor version (Dev version) + ******************************************************************************/ +sl_si91x_gpio_version_t sl_si91x_gpio_get_version(void) +{ + sl_si91x_gpio_version_t version; + version.release = GPIO_RELEASE_VERSION; + version.major = GPIO_MAJOR_VERSION; + version.minor = GPIO_MINOR_VERSION; + return version; +} From d098231015cdf127e48d1fb6ccbdcdd61a4b2d13 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C3=A9r=C3=B4me=20Pouiller?= Date: Fri, 9 Aug 2024 12:09:59 +0200 Subject: [PATCH 06/62] gecko: Import sl_bit.h and sl_string.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit WiseConnect and GeckoSDK share some APIs. The upcoming WiseConnect update will require sl_bit.h and sl_string.h. Note the original path of these files is platform/common/inc/ while this patch locate them in common/inc/. Origin: Silicon Labs Gecko SDK License: Zlib URL: https://github.com/SiliconLabs/gecko_sdk Commit: 124fa19de8c8b3961d21c20857f7df32239786da Version: 4.4 Purpose: Required by WiseConnect Signed-off-by: Jérôme Pouiller --- gecko/common/inc/sl_bit.h | 189 +++++++++++++++++++++++++++++++++++ gecko/common/inc/sl_string.h | 155 ++++++++++++++++++++++++++++ 2 files changed, 344 insertions(+) create mode 100644 gecko/common/inc/sl_bit.h create mode 100644 gecko/common/inc/sl_string.h diff --git a/gecko/common/inc/sl_bit.h b/gecko/common/inc/sl_bit.h new file mode 100644 index 000000000..ff15ae1b0 --- /dev/null +++ b/gecko/common/inc/sl_bit.h @@ -0,0 +1,189 @@ +/***************************************************************************//** + * @file + * @brief Implementation of bit operations. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_BIT_H +#define SL_BIT_H + +/***************************************************************************//** + * @addtogroup bit Bit Manipulation + * @brief Bitwise operations + * @{ + ******************************************************************************/ + +/****************************************************************************************************//** + * SL_DEF_BIT() + * + * @brief Create bit mask with single, specified bit set. + * + * @param bit Bit number of bit to set. + * + * @return Bit mask with single, specified bit set. + * + * @note (1) 'bit' SHOULD be a non-negative integer. + * + * @note (2) 'bit' values that overflow the target CPU &/or compiler environment (e.g. negative + * or greater-than-CPU-data-size values) MAY generate compiler warnings &/or errors. + *******************************************************************************************************/ + +#define SL_DEF_BIT(bit) (1u << (bit)) + +/****************************************************************************************************//** + * SL_SET_BIT() + * + * @brief Set specified bit(s) in a value. + * + * @param val Value to modify by setting specified bit(s). + * + * @param mask Mask of bits to set. + * + * @return Modified value with specified bit(s) set. + * + * @note 'val' & 'mask' SHOULD be unsigned integers. + *******************************************************************************************************/ + +#define SL_SET_BIT(val, mask) ((val) = ((val) | (mask))) + +/****************************************************************************************************//** + * SL_CLEAR_BIT() + * + * @brief Clear specified bit(s) in a value. + * + * @param val Value to modify by clearing specified bit(s). + * + * @param mask Mask of bits to clear. + * + * @return Modified value with specified bit(s) clear. + * + * @note 'val' & 'mask' SHOULD be unsigned integers. + * + * @note 'mask' SHOULD be cast with the same data type than 'val'. + *******************************************************************************************************/ + +#define SL_CLEAR_BIT(val, mask) ((val) = ((val) & (~(mask)))) + +/****************************************************************************************************//** + * SL_IS_BIT_SET() + * + * @brief Determine whether the specified bit(s) in a value are set. + * + * @param val Value to check for specified bit(s) set. + * + * @param mask Mask of bits to check if set. + * + * @return true, if ALL specified bit(s) are set in value. + * + * false, if ALL specified bit(s) are NOT set in value. + * + * @note 'val' & 'mask' SHOULD be unsigned integers. + * + * @note NULL 'mask' allowed; returns 'false' since NO mask bits specified. + *******************************************************************************************************/ + +#define SL_IS_BIT_SET(val, mask) (((((val) & (mask)) == (mask)) && ((mask) != 0u)) ? (true) : (false)) + +/****************************************************************************************************//** + * SL_IS_BIT_CLEAR() + * + * @brief Determine whether the specified bit(s) in a value are clear. + * + * @param val Value to check for specified bit(s) clear. + * + * @param mask Mask of bits to check if clear. + * + * @return true, if ALL specified bit(s) are clear in value. + * + * false, if ALL specified bit(s) are NOT clear in value. + * + * @note val' & 'mask' SHOULD be unsigned integers. + * + * @note NULL 'mask' allowed; returns 'false' since NO mask bits specified. + *******************************************************************************************************/ +#define SL_IS_BIT_CLEAR(val, mask) (((((val) & (mask)) == 0u) && ((mask) != 0u)) ? (true) : (false)) + +/****************************************************************************************************//** + * SL_IS_ANY_BIT_SET() + * + * @brief Determine whether any specified bit(s) in a value are set. + * + * @param val Value to check for specified bit(s) set. + * + * @param mask Mask of bits to check if set (see Note #2). + * + * @return true, if ANY specified bit(s) are set in value. + * + * false, if ALL specified bit(s) are NOT set in value. + * + * @note 'val' & 'mask' SHOULD be unsigned integers. + * + * @note NULL 'mask' allowed; returns 'false' since NO mask bits specified. + *******************************************************************************************************/ + +#define SL_IS_ANY_BIT_SET(val, mask) ((((val) & (mask)) == 0u) ? (false) : (true)) + +/****************************************************************************************************//** + * SL_IS_ANY_BIT_CLEAR() + * + * @brief Determine whether any specified bit(s) in a value are clear. + * + * @param val Value to check for specified bit(s) clear. + * + * @param mask Mask of bits to check if clear (see Note #2). + * + * @return true, if ANY specified bit(s) are clear in value. + * + * false, if ALL specified bit(s) are NOT clear in value. + * + * @note 'val' & 'mask' SHOULD be unsigned integers. + * + * @note NULL 'mask' allowed; returns 'false' since NO mask bits specified. + *******************************************************************************************************/ + +#define SL_IS_ANY_BIT_CLEAR(val, mask) ((((val) & (mask)) == (mask)) ? (false) : (true)) + +/****************************************************************************************************//** + * SL_MATH_IS_PWR2() + * + * @brief Determine if a value is a power of 2. + * + * @param val Value. + * + * @return true, 'val' is a power of 2. + * false, 'val' is not a power of 2. + *******************************************************************************************************/ + +#define SL_MATH_IS_PWR2(val) ((((val) != 0u) && (((val) & ((val) - 1u)) == 0u)) ? true : false) + +/******************************************************************************* + ****************************** DEFINES ************************************ + ******************************************************************************/ + +/** @} (end addtogroup bit) */ + +#endif /* SL_BIT_H */ diff --git a/gecko/common/inc/sl_string.h b/gecko/common/inc/sl_string.h new file mode 100644 index 000000000..89782a3dc --- /dev/null +++ b/gecko/common/inc/sl_string.h @@ -0,0 +1,155 @@ +/******************************************************************************* + * @file + * @brief Implementation of safe string functions. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_STRING_H +#define SL_STRING_H + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + * @addtogroup string String + * @brief String module provides APIs to handle string-related operations. + * @{ + ******************************************************************************/ + +// ----------------------------------------------------------------------------- +// Defines + +// ----------------------------------------------------------------------------- +// Prototypes + +/******************************************************************************* + * @brief + * Copy a string into a buffer. + * Normally, the complete source string including the '\0' termination will be + * copied to the destination. + * If the destination buffer doesn't have room to receive the + * complete source string, the source string will be truncated and the + * destination buffer will be '\0' terminated within the destination buffer. + * + * @param[in] dst Destination buffer. + * + * @param[in] dst_size The size of the destination buffer. + * + * @param[in] src Source string. + ******************************************************************************/ +void sl_strcpy_s(char *dst, size_t dst_size, const char *src); + +/******************************************************************************* + * @brief + * Append the source string to the end of destination string. + * Normally, the complete source string including the '\0' termination will be + * appended to the destination, starting at the source strings '\0' termination. + * If the destination buffer has no room to receive the + * complete source string, the source string will be truncated and the + * destination '\0' terminated within the destination buffer. + * + * @param[in] dst Destination string. + * + * @param[in] dst_size The size of the destination string buffer. + * + * @param[in] src Source string. + ******************************************************************************/ +void sl_strcat_s(char *dst, size_t dst_size, const char *src); + +/******************************************************************************* + * @brief + * Get the string length. + * + * @param[in] str The string to get the length for. + * + * @return String lenght. + ******************************************************************************/ +size_t sl_strlen(char *str); + +/******************************************************************************* + * @brief + * Get the string length, limited to given length. + * + * @param[in] str The string to get the length for. + * + * @param[in] max_len The input string is searched for at most max_lencharacters. + * + * @return String lenght. + ******************************************************************************/ +size_t sl_strnlen(char *str, size_t max_len); + +/******************************************************************************* + * @brief + * Check if the string is empty. + * + * @param[in] str The string to check. + * + * @return true if string is empty or null, else return false. + ******************************************************************************/ +bool sl_str_is_empty(const char *str); + +/******************************************************************************* + * @brief + * Compare two strings, ignoring case. + * + * @param[in] a String to compare. + * + * @param[in] b String to compare. + * + * @return An integer greater than, or less than 0 if the strings + * are not equal. 0 if the strings are equal. + ******************************************************************************/ +int sl_strcasecmp(char const *a, char const *b); + +/******************************************************************************* + * @brief + * Searches for the character in memory, in reverse order. + * + * @param[in] buff Address of the memory buffer. + * + * @param[in] c Character to look for. + * + * @param[in] buff_len Length of the memory buffer. + * + * @return The address of the character in the buffer if and only + * if it was found. + * NULL if no character was found. + ******************************************************************************/ +void* sl_memrchr(void const *buff, char c, size_t buff_len); + +/** @} (end addtogroup string) */ + +#ifdef __cplusplus +} +#endif + +#endif /* SL_STRING_H */ From c909f514d315fcf9052aabf8d00330cfb3bfb9fe Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C3=A9r=C3=B4me=20Pouiller?= Date: Thu, 11 Jul 2024 14:30:46 +0200 Subject: [PATCH 07/62] wiseconnect: Add WiFi components of WiSeConnect SDK MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Origin: Silicon Labs WiSeConnect SDK License: MSLA URL: https://github.com/siliconlabs/wiseconnect Commit: e97a0ed00ddda347a8a39e8276f470e1c5fea469 Version: 3.3 Purpose: Add WiFi support for SiWx917 Signed-off-by: Jérôme Pouiller --- .../common/inc/sl_additional_status.h | 702 +++++ .../components/common/inc/sl_constants.h | 184 ++ .../components/common/inc/sl_ieee802_types.h | 53 + .../components/common/inc/sl_ip_types.h | 89 + .../components/common/inc/sl_utility.h | 92 + .../components/common/src/sl_utility.c | 344 +++ .../core/chip/config/sl_board_configuration.h | 23 + .../rom_driver/inc/rsi_rom_power_save.h | 323 ++ .../si91x/wireless/ahb_interface/inc/rsi_m4.h | 223 ++ .../si91x/wireless/ahb_interface/inc/rsi_os.h | 130 + .../wireless/ahb_interface/inc/rsi_pkt_mgmt.h | 84 + .../inc/rsi_wisemcu_hardware_setup.h | 111 + .../wireless/ahb_interface/inc/sl_device.h | 21 + .../ahb_interface/inc/sli_siwx917_soc.h | 72 + .../ahb_interface/inc/sli_siwx917_timer.h | 45 + .../ahb_interface/src/rsi_hal_mcu_m4_ram.c | 63 + .../ahb_interface/src/rsi_hal_mcu_m4_rom.c | 226 ++ .../wireless/ahb_interface/src/sl_platform.c | 106 + .../ahb_interface/src/sl_platform_wireless.c | 423 +++ .../wireless/ahb_interface/src/sl_si91x_bus.c | 188 ++ .../ahb_interface/src/sli_siwx917_soc.c | 536 ++++ .../asynchronous_socket/inc/sl_si91x_socket.h | 357 +++ .../asynchronous_socket/src/sl_si91x_socket.c | 787 +++++ .../host_mcu/si91x/siwx917_soc_ncp_host.c | 132 + .../si91x/wireless/inc/sl_rsi_utility.h | 420 +++ .../si91x/wireless/inc/sl_si91x_constants.h | 717 +++++ .../wireless/inc/sl_si91x_core_utilities.h | 162 + .../si91x/wireless/inc/sl_si91x_driver.h | 868 ++++++ .../wireless/inc/sl_si91x_host_interface.h | 153 + .../wireless/inc/sl_si91x_protocol_types.h | 2161 ++++++++++++++ .../si91x/wireless/inc/sl_si91x_status.h | 89 + .../si91x/wireless/inc/sl_si91x_types.h | 248 ++ .../si91x/wireless/inc/sl_wifi_device.h | 1170 ++++++++ .../si91x/wireless/memory/malloc_buffers.c | 107 + .../wireless/sl_net/inc/sl_net_rsi_utility.h | 50 + .../si91x/wireless/sl_net/inc/sl_net_si91x.h | 72 + .../inc/sl_net_si91x_integration_handler.h | 35 + .../wireless/sl_net/src/sl_net_rsi_utility.c | 172 ++ .../src/sl_net_si91x_integration_handler.c | 191 ++ .../sl_net/src/sl_si91x_net_credentials.c | 210 ++ .../sl_net/src/sl_si91x_net_internal_stack.c | 234 ++ .../wireless/socket/inc/sl_bsd_utility.h | 49 + .../inc/sl_si91x_socket_callback_framework.h | 38 + .../socket/inc/sl_si91x_socket_constants.h | 165 ++ .../socket/inc/sl_si91x_socket_types.h | 166 ++ .../socket/inc/sl_si91x_socket_utility.h | 205 ++ .../socket/src/sl_si91x_socket_utility.c | 781 +++++ .../si91x/wireless/src/sl_rsi_utility.c | 1245 ++++++++ .../src/sl_si91x_callback_framework.c | 96 + .../si91x/wireless/src/sl_si91x_driver.c | 2620 +++++++++++++++++ .../threading/sli_si91x_multithreaded.c | 1414 +++++++++ .../components/protocol/wifi/inc/sl_wifi.h | 1512 ++++++++++ .../wifi/inc/sl_wifi_callback_framework.h | 325 ++ .../protocol/wifi/inc/sl_wifi_constants.h | 509 ++++ .../wifi/inc/sl_wifi_host_interface.h | 44 + .../protocol/wifi/inc/sl_wifi_types.h | 590 ++++ .../components/protocol/wifi/si91x/sl_wifi.c | 2566 ++++++++++++++++ .../wifi/src/sl_wifi_callback_framework.c | 138 + .../si91x_socket/sl_si91x_socket_support.h | 128 + .../service/network_manager/inc/sl_net.h | 346 +++ .../network_manager/inc/sl_net_constants.h | 189 ++ .../service/network_manager/inc/sl_net_dns.h | 48 + .../network_manager/inc/sl_net_ip_types.h | 45 + .../network_manager/inc/sl_net_types.h | 83 + .../network_manager/inc/sl_net_wifi_types.h | 54 + .../network_manager/si91x/sl_net_si91x.c | 254 ++ .../service/network_manager/src/sl_net.c | 199 ++ .../src/sl_net_basic_credentials.c | 194 ++ .../src/sl_net_basic_profiles.c | 108 + wiseconnect/license.md | 7 + .../defaults/sl_net_default_values.h | 148 + 71 files changed, 26639 insertions(+) create mode 100644 wiseconnect/components/common/inc/sl_additional_status.h create mode 100644 wiseconnect/components/common/inc/sl_constants.h create mode 100644 wiseconnect/components/common/inc/sl_ieee802_types.h create mode 100644 wiseconnect/components/common/inc/sl_ip_types.h create mode 100644 wiseconnect/components/common/inc/sl_utility.h create mode 100644 wiseconnect/components/common/src/sl_utility.c create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/core/chip/config/sl_board_configuration.h create mode 100644 wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_power_save.h create mode 100644 wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/inc/rsi_m4.h create mode 100644 wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/inc/rsi_os.h create mode 100644 wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/inc/rsi_pkt_mgmt.h create mode 100644 wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/inc/rsi_wisemcu_hardware_setup.h create mode 100644 wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/inc/sl_device.h create mode 100644 wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/inc/sli_siwx917_soc.h create mode 100644 wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/inc/sli_siwx917_timer.h create mode 100644 wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/src/rsi_hal_mcu_m4_ram.c create mode 100644 wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/src/rsi_hal_mcu_m4_rom.c create mode 100644 wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/src/sl_platform.c create mode 100644 wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/src/sl_platform_wireless.c create mode 100644 wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/src/sl_si91x_bus.c create mode 100644 wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/src/sli_siwx917_soc.c create mode 100644 wiseconnect/components/device/silabs/si91x/wireless/asynchronous_socket/inc/sl_si91x_socket.h create mode 100644 wiseconnect/components/device/silabs/si91x/wireless/asynchronous_socket/src/sl_si91x_socket.c create mode 100644 wiseconnect/components/device/silabs/si91x/wireless/host_mcu/si91x/siwx917_soc_ncp_host.c create mode 100644 wiseconnect/components/device/silabs/si91x/wireless/inc/sl_rsi_utility.h create mode 100644 wiseconnect/components/device/silabs/si91x/wireless/inc/sl_si91x_constants.h create mode 100644 wiseconnect/components/device/silabs/si91x/wireless/inc/sl_si91x_core_utilities.h create mode 100644 wiseconnect/components/device/silabs/si91x/wireless/inc/sl_si91x_driver.h create mode 100644 wiseconnect/components/device/silabs/si91x/wireless/inc/sl_si91x_host_interface.h create mode 100644 wiseconnect/components/device/silabs/si91x/wireless/inc/sl_si91x_protocol_types.h create mode 100644 wiseconnect/components/device/silabs/si91x/wireless/inc/sl_si91x_status.h create mode 100644 wiseconnect/components/device/silabs/si91x/wireless/inc/sl_si91x_types.h create mode 100644 wiseconnect/components/device/silabs/si91x/wireless/inc/sl_wifi_device.h create mode 100644 wiseconnect/components/device/silabs/si91x/wireless/memory/malloc_buffers.c create mode 100644 wiseconnect/components/device/silabs/si91x/wireless/sl_net/inc/sl_net_rsi_utility.h create mode 100644 wiseconnect/components/device/silabs/si91x/wireless/sl_net/inc/sl_net_si91x.h create mode 100644 wiseconnect/components/device/silabs/si91x/wireless/sl_net/inc/sl_net_si91x_integration_handler.h create mode 100644 wiseconnect/components/device/silabs/si91x/wireless/sl_net/src/sl_net_rsi_utility.c create mode 100644 wiseconnect/components/device/silabs/si91x/wireless/sl_net/src/sl_net_si91x_integration_handler.c create mode 100644 wiseconnect/components/device/silabs/si91x/wireless/sl_net/src/sl_si91x_net_credentials.c create mode 100644 wiseconnect/components/device/silabs/si91x/wireless/sl_net/src/sl_si91x_net_internal_stack.c create mode 100644 wiseconnect/components/device/silabs/si91x/wireless/socket/inc/sl_bsd_utility.h create mode 100644 wiseconnect/components/device/silabs/si91x/wireless/socket/inc/sl_si91x_socket_callback_framework.h create mode 100644 wiseconnect/components/device/silabs/si91x/wireless/socket/inc/sl_si91x_socket_constants.h create mode 100644 wiseconnect/components/device/silabs/si91x/wireless/socket/inc/sl_si91x_socket_types.h create mode 100644 wiseconnect/components/device/silabs/si91x/wireless/socket/inc/sl_si91x_socket_utility.h create mode 100644 wiseconnect/components/device/silabs/si91x/wireless/socket/src/sl_si91x_socket_utility.c create mode 100644 wiseconnect/components/device/silabs/si91x/wireless/src/sl_rsi_utility.c create mode 100644 wiseconnect/components/device/silabs/si91x/wireless/src/sl_si91x_callback_framework.c create mode 100644 wiseconnect/components/device/silabs/si91x/wireless/src/sl_si91x_driver.c create mode 100644 wiseconnect/components/device/silabs/si91x/wireless/threading/sli_si91x_multithreaded.c create mode 100644 wiseconnect/components/protocol/wifi/inc/sl_wifi.h create mode 100644 wiseconnect/components/protocol/wifi/inc/sl_wifi_callback_framework.h create mode 100644 wiseconnect/components/protocol/wifi/inc/sl_wifi_constants.h create mode 100644 wiseconnect/components/protocol/wifi/inc/sl_wifi_host_interface.h create mode 100644 wiseconnect/components/protocol/wifi/inc/sl_wifi_types.h create mode 100644 wiseconnect/components/protocol/wifi/si91x/sl_wifi.c create mode 100644 wiseconnect/components/protocol/wifi/src/sl_wifi_callback_framework.c create mode 100644 wiseconnect/components/service/bsd_socket/si91x_socket/sl_si91x_socket_support.h create mode 100644 wiseconnect/components/service/network_manager/inc/sl_net.h create mode 100644 wiseconnect/components/service/network_manager/inc/sl_net_constants.h create mode 100644 wiseconnect/components/service/network_manager/inc/sl_net_dns.h create mode 100644 wiseconnect/components/service/network_manager/inc/sl_net_ip_types.h create mode 100644 wiseconnect/components/service/network_manager/inc/sl_net_types.h create mode 100644 wiseconnect/components/service/network_manager/inc/sl_net_wifi_types.h create mode 100644 wiseconnect/components/service/network_manager/si91x/sl_net_si91x.c create mode 100644 wiseconnect/components/service/network_manager/src/sl_net.c create mode 100644 wiseconnect/components/service/network_manager/src/sl_net_basic_credentials.c create mode 100644 wiseconnect/components/service/network_manager/src/sl_net_basic_profiles.c create mode 100644 wiseconnect/license.md create mode 100644 wiseconnect/resources/defaults/sl_net_default_values.h diff --git a/wiseconnect/components/common/inc/sl_additional_status.h b/wiseconnect/components/common/inc/sl_additional_status.h new file mode 100644 index 000000000..3ce06d901 --- /dev/null +++ b/wiseconnect/components/common/inc/sl_additional_status.h @@ -0,0 +1,702 @@ +/******************************************************************************* +* @file sl_additional_status.h +* @brief +******************************************************************************* +* # License +* Copyright 2023 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ +#pragma once + +#define SL_STATUS_SI91X_SUBSPACE ((sl_status_t)0x00010000) + +/** + * @addtogroup SL_ADDITIONAL_STATUS_ERRORS + * @{ + */ + +// Additional generic errors +#define SL_STATUS_OS_OPERATION_FAILURE ((sl_status_t)0x0051) ///< OS operation failed. +#define SL_STATUS_BOOTUP_OPTIONS_NOT_SAVED ((sl_status_t)0x0052) ///< Bootup options not saved. +#define SL_STATUS_BOOTUP_OPTIONS_CHECKSUM_FAILURE ((sl_status_t)0x0053) ///< Bootup options checksum failed. +#define SL_STATUS_BOOTLOADER_VERSION_MISMATCH ((sl_status_t)0x0054) ///< Bootloader version mismatch. +#define SL_STATUS_WAITING_FOR_BOARD_READY ((sl_status_t)0x0055) ///< Waiting for board ready. +#define SL_STATUS_VALID_FIRMWARE_NOT_PRESENT ((sl_status_t)0x0056) ///< Invalid firmware. +#define SL_STATUS_INVALID_OPTION ((sl_status_t)0x0057) ///< Invalid option. +#define SL_STATUS_SPI_BUSY ((sl_status_t)0x0058) ///< SPI busy. +#define SL_STATUS_CARD_READY_TIMEOUT ((sl_status_t)0x0059) ///< Card ready not received. +#define SL_STATUS_FW_LOAD_OR_UPGRADE_TIMEOUT ((sl_status_t)0x005A) ///< Firmware upgrade timed out. + +// Additional Wi-Fi errors +#define SL_STATUS_WIFI_DOES_NOT_EXIST ((sl_status_t)0x0B21) ///< Does not exist. +#define SL_STATUS_WIFI_NOT_AUTHENTICATED ((sl_status_t)0x0B22) ///< Not authenticated. +#define SL_STATUS_WIFI_NOT_KEYED ((sl_status_t)0x0B23) ///< Not keyed. +#define SL_STATUS_WIFI_IOCTL_FAIL ((sl_status_t)0x0B24) ///< IOCTL fail. +#define SL_STATUS_WIFI_BUFFER_UNAVAILABLE_TEMPORARY ((sl_status_t)0x0B25) ///< Buffer unavailable temporarily. +#define SL_STATUS_WIFI_BUFFER_UNAVAILABLE_PERMANENT ((sl_status_t)0x0B26) ///< Buffer unavailable permanently. +#define SL_STATUS_WIFI_WPS_PBC_OVERLAP ((sl_status_t)0x0B27) ///< WPS PBC overlap. +#define SL_STATUS_WIFI_CONNECTION_LOST ((sl_status_t)0x0B28) ///< Connection lost. +#define SL_STATUS_WIFI_OUT_OF_EVENT_HANDLER_SPACE ((sl_status_t)0x0B29) ///< Cannot add extra event handler. +#define SL_STATUS_WIFI_SEMAPHORE_ERROR ((sl_status_t)0x0B2A) ///< Error manipulating a semaphore. +#define SL_STATUS_WIFI_FLOW_CONTROLLED ((sl_status_t)0x0B2B) ///< Packet retrieval cancelled due to flow control. +#define SL_STATUS_WIFI_NO_CREDITS ((sl_status_t)0x0B2C) ///< Packet retrieval cancelled due to lack of bus credits. +#define SL_STATUS_WIFI_NO_PACKET_TO_SEND \ + ((sl_status_t)0x0B2D) ///< Packet retrieval cancelled due to no pending packets. +#define SL_STATUS_WIFI_CORE_CLOCK_NOT_ENABLED ((sl_status_t)0x0B2E) ///< Core disabled due to no clock. +#define SL_STATUS_WIFI_CORE_IN_RESET ((sl_status_t)0x0B2F) ///< Core disabled - in reset. +#define SL_STATUS_WIFI_UNSUPPORTED ((sl_status_t)0x0B30) ///< Unsupported function. +#define SL_STATUS_WIFI_BUS_WRITE_REGISTER_ERROR ((sl_status_t)0x0B31) ///< Error writing to WLAN register. +#define SL_STATUS_WIFI_SDIO_BUS_UP_FAIL ((sl_status_t)0x0B32) ///< SDIO bus failed to come up. +#define SL_STATUS_WIFI_JOIN_IN_PROGRESS ((sl_status_t)0x0B33) ///< Join not finished yet. +#define SL_STATUS_WIFI_NETWORK_NOT_FOUND ((sl_status_t)0x0B34) ///< Specified network was not found. +#define SL_STATUS_WIFI_INVALID_JOIN_STATUS ((sl_status_t)0x0B35) ///< Join status error. +#define SL_STATUS_WIFI_UNKNOWN_INTERFACE ((sl_status_t)0x0B36) ///< Unknown interface specified. +#define SL_STATUS_WIFI_SDIO_RX_FAIL ((sl_status_t)0x0B37) ///< Error during SDIO receive. +#define SL_STATUS_WIFI_HWTAG_MISMATCH ((sl_status_t)0x0B38) ///< Hardware tag header corrupt. +#define SL_STATUS_WIFI_RX_BUFFER_ALLOC_FAIL ((sl_status_t)0x0B39) ///< Failed to allocate a buffer to receive into. +#define SL_STATUS_WIFI_BUS_READ_REGISTER_ERROR ((sl_status_t)0x0B3A) ///< Error reading a bus hardware register. +#define SL_STATUS_WIFI_THREAD_CREATE_FAILED ((sl_status_t)0x0B3B) ///< Failed to create a new thread. +#define SL_STATUS_WIFI_QUEUE_ERROR ((sl_status_t)0x0B3C) ///< Error manipulating a queue. +#define SL_STATUS_WIFI_BUFFER_POINTER_MOVE_ERROR \ + ((sl_status_t)0x0B3D) ///< Error moving the current pointer of a buffer. +#define SL_STATUS_WIFI_BUFFER_SIZE_SET_ERROR ((sl_status_t)0x0B3E) ///< Error setting size of packet buffer. +#define SL_STATUS_WIFI_THREAD_STACK_NULL \ + ((sl_status_t)0x0B3F) ///< Null stack pointer passed when non null was required. +#define SL_STATUS_WIFI_THREAD_DELETE_FAIL ((sl_status_t)0x0B40) ///< Error deleting a thread. +#define SL_STATUS_WIFI_SLEEP_ERROR ((sl_status_t)0x0B41) ///< Failed to put a thread to sleep. +#define SL_STATUS_WIFI_BUFFER_ALLOC_FAIL ((sl_status_t)0x0B42) ///< Failed to allocate a packet buffer. +#define SL_STATUS_WIFI_INTERFACE_NOT_UP ((sl_status_t)0x0B44) ///< Requested interface is not active. +#define SL_STATUS_WIFI_DELAY_TOO_LONG ((sl_status_t)0x0B45) ///< Requested delay is too long. +#define SL_STATUS_WIFI_INVALID_DUTY_CYCLE ((sl_status_t)0x0B46) ///< Duty cycle is outside limit 0 to 0. +#define SL_STATUS_WIFI_PMK_WRONG_LENGTH ((sl_status_t)0x0B47) ///< Returned pmk was the wrong length. +#define SL_STATUS_WIFI_UNKNOWN_SECURITY_TYPE ((sl_status_t)0x0B48) ///< AP security type was unknown. +#define SL_STATUS_WIFI_WEP_NOT_ALLOWED ((sl_status_t)0x0B49) ///< AP not allowed to use WEP - use Open instead. +#define SL_STATUS_WIFI_WPA_KEYLEN_BAD ((sl_status_t)0x0B4A) ///< WPA / WPA2 key length must be between 8 & 64 bytes. +#define SL_STATUS_WIFI_FILTER_NOT_FOUND ((sl_status_t)0x0B4B) ///< Specified filter id not found. +#define SL_STATUS_WIFI_SPI_ID_READ_FAIL ((sl_status_t)0x0B4C) ///< Failed to read 0xfeedbead SPI id from chip. +#define SL_STATUS_WIFI_SPI_SIZE_MISMATCH ((sl_status_t)0x0B4D) ///< Mismatch in sizes between SPI and SDPCM header. +#define SL_STATUS_WIFI_ADDRESS_ALREADY_REGISTERED \ + ((sl_status_t)0x0B4E) ///< Attempt to register a multicast address twice. +#define SL_STATUS_WIFI_SDIO_RETRIES_EXCEEDED ((sl_status_t)0x0B4F) ///< SDIO transfer failed too many times. +#define SL_STATUS_WIFI_NULL_PTR_ARG ((sl_status_t)0x0B50) ///< Null Pointer argument passed to function. +#define SL_STATUS_WIFI_THREAD_FINISH_FAIL ((sl_status_t)0x0B51) ///< Error deleting a thread. +#define SL_STATUS_WIFI_WAIT_ABORTED ((sl_status_t)0x0B52) ///< Semaphore/Mutex wait has been aborted. +#define SL_STATUS_WIFI_QUEUE_MESSAGE_UNALIGNED ((sl_status_t)0x0B53) ///< Unaligned message in the queue. +#define SL_STATUS_WIFI_MUTEX_ERROR ((sl_status_t)0x0B54) ///< Error while Mutex operation. +#define SL_STATUS_WIFI_SECURE_LINK_DECRYPT_ERROR ((sl_status_t)0x0B57) ///< Error while decryption over secure link. +#define SL_STATUS_WIFI_SECURE_LINK_KEY_RENEGOTIATION_ERROR \ + ((sl_status_t)0x0B59) ///< Error while renegotiation of key over secure link. +#define SL_STATUS_WIFI_INVALID_OPERMODE ((sl_status_t)0x0B60) ///< Invalid opermode provided. +#define SL_STATUS_WIFI_INVALID_ENCRYPTION_METHOD ((sl_status_t)0x0B61) ///< Invalid security encryption method provided. + +// Si91X Crypto errors +#define SL_STATUS_TRNG_DUPLICATE_ENTROPY ((sl_status_t)0x0B62) ///< TRNG duplicate elements error. + +// Si91X Wi-Fi transceiver error codes +#define SL_STATUS_TRANSCEIVER_INVALID_MAC_ADDRESS ((sl_status_t)0x0B63) ///< Invalid MAC address provided +#define SL_STATUS_TRANSCEIVER_INVALID_QOS_PRIORITY ((sl_status_t)0x0B64) ///< Invalid QOS priority provided +#define SL_STATUS_TRANSCEIVER_INVALID_CHANNEL ((sl_status_t)0x0B65) ///< Invalid channel provided +#define SL_STATUS_TRANSCEIVER_INVALID_DATA_RATE ((sl_status_t)0x0B66) ///< Invalid data rate provided +#define SL_STATUS_TRANSCEIVER_INVALID_CONFIG \ + ((sl_status_t)0x0B67) ///< Invalid transceiver configuration parameters provided + +// Si91X Crypto Firmware Errors +#define SL_STATUS_CRYPTO_INVALID_PARAMETER \ + ((sl_status_t)0x1CCFE) ///< Return when parameter passed to Crypto SAPI is invalid. +#define SL_STATUS_CRYPTO_INVALID_SIGNATURE \ + ((sl_status_t)0x1CC9A) ///< Return in AEAD (CCM, GCM, Chachapoly) decryption function, when MAC generated during decryption does not match the MAC passed. + +// Si91X Wi-Fi Firmware errors +#define SL_STATUS_SI91X_SCAN_ISSUED_IN_ASSOCIATED_STATE \ + ((sl_status_t)0x10002) ///< Scan command issued while device is already associated with an access point. +#define SL_STATUS_SI91X_NO_AP_FOUND ((sl_status_t)0x10003) ///< No AP found. +#define SL_STATUS_SI91X_INVALID_PSK_IN_WEP_SECURITY \ + ((sl_status_t)0x10004) ///< Wrong PSK is issued while the device client tries to join an access point with WEP security enabled. +#define SL_STATUS_SI91X_INVALID_BAND ((sl_status_t)0x10005) ///< Invalid band. +#define SL_STATUS_SI91X_UNASSOCIATED ((sl_status_t)0x10006) ///< Association not done or in unassociated state. +#define SL_STATUS_SI91X_DEAUTHENTICATION_RECEIVED_FROM_AP \ + ((sl_status_t)0x10008) ///< De-authentication received from AP. +#define SL_STATUS_SI91X_ASSOCIATION_FAILED \ + ((sl_status_t)0x10009) ///< Failed to associate to access point during "Join". +#define SL_STATUS_SI91X_INVALID_CHANNEL ((sl_status_t)0x1000A) ///< Invalid channel. +#define SL_STATUS_SI91X_JOIN_AUTHENTICATION_FAILED \ + ((sl_status_t)0x1000E) ///< Authentication failure during "Join". Unable to find AP during join which was found during scan. +#define SL_STATUS_SI91X_BEACON_MISSED_FROM_AP_DURING_JOIN ((sl_status_t)0x1000F) ///< Missed beacon from AP during join. +#define SL_STATUS_SI91X_INVALID_MAC_SUPPLIED \ + ((sl_status_t)0x10013) ///< Non-existent MAC address supplied in "Disassociate" command. +#define SL_STATUS_SI91X_EAP_CONFIG_NOT_DONE ((sl_status_t)0x10014) ///< EAP configuration is not done. +#define SL_STATUS_SI91X_MEMORY_FAILED_FROM_MODULE \ + ((sl_status_t)0x10015) ///< Memory allocation failed or Store configuration check sum failed. +#define SL_STATUS_SI91X_INSUFFICIENT_INFO \ + ((sl_status_t)0x10016) ///< Information is wrong or insufficient in join command. +#define SL_STATUS_SI91X_NOT_AP_INTERFACE ((sl_status_t)0x10017) ///< Not an AP interface. +#define SL_STATUS_SI91X_INVALID_PUSH_BUTTON_SEQUENCE \ + ((sl_status_t)0x10018) ///< Push button command given before the expiry of previous push button command. +#define SL_STATUS_SI91X_REJOIN_FAILURE ((sl_status_t)0x10019) ///< Access point not found. Rejoin failure. +#define SL_STATUS_SI91X_FREQUENCY_NOT_SUPPORTED ((sl_status_t)0x1001A) ///< Frequency not supported. +#define SL_STATUS_SI91X_INVALID_OPERMODE ((sl_status_t)0x1001B) ///< Invalid opermode. +#define SL_STATUS_SI91X_EAP_CONFIG_FAILED ((sl_status_t)0x1001C) ///< EAP configuration failed. +#define SL_STATUS_SI91X_P2P_CONFIG_FAILED ((sl_status_t)0x1001D) ///< P2P configuration failed. +#define SL_STATUS_SI91X_GROUP_OWNER_NEGOTIATION_FAILED \ + ((sl_status_t)0x1001E) ///< Unable to start Group Owner negotiation. +#define SL_STATUS_SI91X_JOIN_TIMEOUT ((sl_status_t)0x10020) ///< Join timeout. +#define SL_STATUS_SI91X_COMMAND_GIVEN_IN_INVALID_STATE ((sl_status_t)0x10021) ///< Command given in incorrect state. +#define SL_STATUS_SI91X_INVALID_QUERY_GO_PARAMS \ + ((sl_status_t)0x10022) ///< Query GO parameters issued in incorrect operating mode. +#define SL_STATUS_SI91X_ACCESS_POINT_FAILED ((sl_status_t)0x10023) ///< Unable to form access point. +#define SL_STATUS_SI91X_INVALID_SCAN_INFO \ + ((sl_status_t)0x10024) ///< Wrong scan input parameters supplied to "Scan" command. +#define SL_STATUS_SI91X_COMMAND_ISSUED_IN_REJOIN_STATE \ + ((sl_status_t)0x10025) ///< Command issued during re-join in progress. +#define SL_STATUS_SI91X_WRONG_PARAMETERS ((sl_status_t)0x10026) ///< Wrong parameters the command request. +#define SL_STATUS_SI91X_PROVISION_DISCOVERY_FAILED_IN_P2P ((sl_status_t)0x10027) ///< Provision discovery failed in P2P. +#define SL_STATUS_SI91X_INVALID_PSK_LENGTH \ + ((sl_status_t)0x10028) ///< PSK length less than 8 bytes or more than 63 bytes. +#define SL_STATUS_SI91X_FAILED_TO_CLEAR_OR_SET_EAP_CERTIFICATE \ + ((sl_status_t)0x10029) ///< Failed to clear or to set the Enterprise Certificate (Set Certificate). +#define SL_STATUS_SI91X_P2P_GO_NEGOTIATED_FAILED ((sl_status_t)0x1002A) ///< P2P Go negotiation failed. +#define SL_STATUS_SI91X_ASSOCIATION_TIMEOUT_IN_P2P_WPS_MODE \ + ((sl_status_t)0x1002B) ///< Association between nodes failed in P2P WPS mode due to timeout. +#define SL_STATUS_SI91X_COMMAND_ISSUED_WHILE_INTERNAL_OPERATION \ + ((sl_status_t)0x1002C) ///< If a command is issued by the Host when the device is internally executing auto-join or auto-create. +#define SL_STATUS_SI91X_INVALID_WEP_KEY_LEN ((sl_status_t)0x1002D) ///< WEP key is of wrong length. +#define SL_STATUS_SI91X_ICMP_REQUEST_TIMEOUT_ERROR ((sl_status_t)0x1002E) ///< ICMP request timeout error. +#define SL_STATUS_SI91X_ICMP_DATA_SIZE_EXCEED_MAX_LIMIT \ + ((sl_status_t)0x1002F) ///< ICMP data size exceeds maximum limit. +#define SL_STATUS_SI91X_SEND_DATA_PACKET_EXCEED_LIMIT \ + ((sl_status_t)0x10030) ///< Send data packet exceeded the limit or length that is mentioned (or) MQTT publish data and publish data length mismatched (or) MQTT Send data packet exceeded the limit. +#define SL_STATUS_SI91X_ARP_CACHE_NOT_FOUND ((sl_status_t)0x10031) ///< ARP cache entry not found. +#define SL_STATUS_SI91X_UART_COMMAND_TIMEOUT ((sl_status_t)0x10032) ///< UART command timeout happened. +#define SL_STATUS_SI91X_FIXED_DATA_RATE_NOT_SUPPORTED_BY_AP \ + ((sl_status_t)0x10033) ///< Fixed data rate is not supported by connecting AP. +#define SL_STATUS_SI91X_USERNAME_PASSWORD_CLIENTID_TOPIC_MAX_LEN \ + ((sl_status_t)0x10036) ///< Maximum length exceeded of username/password/client_id/topic in MQTT. +#define SL_STATUS_SI91X_INVALID_WPS_PIN ((sl_status_t)0x10037) ///< Wrong WPS PIN. +#define SL_STATUS_SI91X_INVALID_WPS_PIN_LEN ((sl_status_t)0x10038) ///< Wrong WPS PIN length. +#define SL_STATUS_SI91X_INVALID_PMK_LEN ((sl_status_t)0x10039) ///< Wrong PMK length. +#define SL_STATUS_SI91X_SSID_NOT_PRESENT_FOR_PMK_GENERATION \ + ((sl_status_t)0x1003A) ///< SSID not present for PMK generation. +#define SL_STATUS_SI91X_SSID_INCORRECT_PMK_GENERATION \ + ((sl_status_t)0x1003B) ///< SSID incorrect for PMK generation(more than 32 bytes). +#define SL_STATUS_SI91X_BAND_NOT_SUPPORTED ((sl_status_t)0x1003C) ///< Band not supported. +#define SL_STATUS_SI91X_INVALID_USR_STORE_CONFIGURATION_LEN \ + ((sl_status_t)0x1003D) ///< User store configuration invalid length. +#define SL_STATUS_SI91X_INVALID_COMMAND_LEN \ + ((sl_status_t)0x1003E) ///< Error in length of the command (Exceeds number of characters is mentioned in the PRM). +#define SL_STATUS_SI91X_DATA_PACKET_DROPPED ((sl_status_t)0x1003F) ///< Data packet dropped. +#define SL_STATUS_SI91X_WEP_KEY_NOT_GIVEN ((sl_status_t)0x10040) ///< WEP key not given. +#define SL_STATUS_SI91X_INVALID_STORE_CONFIG_PROFILE \ + ((sl_status_t)0x10041) ///< Error in length of store config profile. +#define SL_STATUS_SI91X_MISSING_PSK_OR_PMK ((sl_status_t)0x10042) ///< PSK or PMK not given. +#define SL_STATUS_SI91X_INVALID_SECURITY_MODE_IN_JOIN_COMMAND \ + ((sl_status_t)0x10043) ///< Security mode given in join command is invalid. +#define SL_STATUS_SI91X_MAX_BEACON_MISCOUNT \ + ((sl_status_t)0x10044) ///< Beacon miscount reaches max beacon miscount (De-authentication due to beacon miss). +#define SL_STATUS_SI91X_DEAUTH_REQUEST_FROM_SUPPLICANT \ + ((sl_status_t)0x10045) ///< De-authentication received from supplicant. +#define SL_STATUS_SI91X_DEAUTH_REQUEST_FROM_FROM_AP \ + ((sl_status_t)0x10046) ///< De-authentication received from AP after channel switching. +#define SL_STATUS_SI91X_MISSED_SYNCHRONIZATION ((sl_status_t)0x10047) ///< Synchronization missed. +#define SL_STATUS_SI91X_AUTHENTICATION_TIMEOUT ((sl_status_t)0x10048) ///< Authentication timeout occurred. +#define SL_STATUS_SI91X_ASSOCIATION_TIMEOUT ((sl_status_t)0x10049) ///< Association timeout. +#define SL_STATUS_SI91X_BG_SCAN_NOT_ALLOWED ((sl_status_t)0x1004A) ///< BG scan in given channels is not allowed. +#define SL_STATUS_SI91X_SSID_MISMATCH ((sl_status_t)0x1004B) ///< Scanned SSID and SSID given in join are not matching. +#define SL_STATUS_SI91X_CLIENT_MAX_SUPPORTED_EXCEEDED \ + ((sl_status_t)0x1004C) ///< Given number of clients exceeded max number of stations supported. +#define SL_STATUS_SI91X_HT_CAPABILITIES_NOT_SUPPORTED \ + ((sl_status_t)0x1004D) ///< Given HT capabilities are not supported. +#define SL_STATUS_SI91X_UART_FLOW_NOT_SUPPORTED ((sl_status_t)0x1004E) ///< UART Flow control not supported. +#define SL_STATUS_SI91X_ZB_BT_BLE_PKT_RECEIVED \ + ((sl_status_t)0x1004F) ///< ZB/BT/BLE packet received and protocol is not enabled. +#define SL_STATUS_SI91X_MGMT_PKT_DROPPED ((sl_status_t)0x10050) ///< MGMT pkt dropped. +#define SL_STATUS_SI91X_INVALID_RF_CURRENT_MODE ((sl_status_t)0x10051) ///< Invalid RF current mode. +#define SL_STATUS_SI91X_POWER_SAVE_NOT_SUPPORTED \ + ((sl_status_t)0x10052) ///< Power save support is not present for a given interface. +#define SL_STATUS_SI91X_CONCURRENT_AP_IN_CONNECTED_STATE ((sl_status_t)0x10053) ///< Concurrent AP in connected state. +#define SL_STATUS_SI91X_CONNECTED_AP_OR_STATION_CHANNEL_MISMATCH \ + ((sl_status_t)0x10054) ///< Connected AP or Station channel mismatch. +#define SL_STATUS_SI91X_IAP_COPROCESSOR_ERROR ((sl_status_t)0x10055) ///< IAP co processor error. +#define SL_STATUS_SI91X_WPS_NOT_SUPPORTED ((sl_status_t)0x10056) ///< WPS not supported in current operating mode. +#define SL_STATUS_SI91X_CONCURRENT_AP_CHANNEL_MISMATCH \ + ((sl_status_t)0x10057) ///< Concurrent AP doesn't have same channel as connected station channel. +#define SL_STATUS_SI91X_PBC_SESSION_OVERLAP ((sl_status_t)0x10058) ///< PBC session overlap error. +#define SL_STATUS_SI91X_BT_FEATURE_BITMAP_INVALID ((sl_status_t)0x10059) ///< BT feature bit map invalid. +#define SL_STATUS_SI91X_FOUR_WAY_HANDSHAKE_FAILED \ + ((sl_status_t)0x1005A) ///< 4/4 confirmation of 4 way handshake failed. +#define SL_STATUS_SI91X_MAC_ADDRESS_NOT_PRESENT_IN_MAC_JOIN \ + ((sl_status_t)0x1005B) ///< MAC address not present in MAC based join. +#define SL_STATUS_SI91X_CONCURRENT_MODE_DOWN \ + ((sl_status_t)0x1005C) ///< Concurrent mode, both AP and client should be up, to enable configuration. +#define SL_STATUS_SI91X_CERTIFICATE_LOAD_NOT_ALLOWED_IN_FLASH \ + ((sl_status_t)0x1005D) ///< Certificate load not allowed in flash. +#define SL_STATUS_SI91X_CERTIFICATE_LOAD_NOT_ALLOWED_IN_RAM \ + ((sl_status_t)0x1005E) ///< Certificate load not allowed in RAM. +#define SL_STATUS_SI91X_WRONG_CERTIFICATE_LOAD_INDEX \ + ((sl_status_t)0x1005F) ///< Certificate load failed due to wrong index. +#define SL_STATUS_SI91X_AP_HT_CAPS_NOT_ENABLED ((sl_status_t)0x10060) ///< AP HT caps not enabled. +#define SL_STATUS_SI91X_ADDRESS_FAMILY_NOT_SUPPORTED \ + ((sl_status_t)0x10061) ///< Address family not supported by protocol. +#define SL_STATUS_SI91X_INVALID_BEACON_INTERVAL_OR_DTM_PERIOD \ + ((sl_status_t)0x10062) ///< Invalid beacon interval or DTIM period provided. +#define SL_STATUS_SI91X_INVALID_CONFIG_RANGE_PROVIDED \ + ((sl_status_t)0x10063) ///< Invalid range of the configuration provided. +#define SL_STATUS_SI91X_INVALID_CONFIG_TYPE ((sl_status_t)0x10064) ///< RTS THRESHOLD Config type is invalid. +#define SL_STATUS_SI91X_ERROR_WITH_MQTT_COMMAND ((sl_status_t)0x10065) ///< Error with MQTT command. +#define SL_STATUS_SI91X_HIGHER_LISTEN_INTERVAL \ + ((sl_status_t)0x10066) ///< listen interval in power save is greater than that of join. +#define SL_STATUS_SI91X_WLAN_RADIO_DEREGISTERED ((sl_status_t)0x10067) ///< WLAN radio deregistered. +#define SL_STATUS_SI91X_SAE_FAILURE_DUE_TO_MULTIPLE_CONFIRM_FRAMES_FROM_AP \ + ((sl_status_t)0x10069) ///< SAE failure due to multiple confirm frames from AP. +#define SL_STATUS_SI91X_EC_GROUP_STATION_UNSUPPORTED_BY_AP \ + ((sl_status_t)0x1006A) ///< AP does not support the EC-group set by station. +#define SL_STATUS_SI91X_NO_11AX_SUPPORT_IN_AP ((sl_status_t)0x1006C) ///< 11AX is not supported in AP mode. +#define SL_STATUS_SI91X_NON_PREF_CHAN_CONFIG_FAILED \ + ((sl_status_t)0x1006D) ///< Non-preferred channel configuration failed. +#define SL_STATUS_TWT_SUPPORT_NOT_ENABLED_ERR \ + ((sl_status_t)0x10070) ///< Occurs when HE_PARAMS_SUPPORT and SLI_SI91X_ENABLE_TWT_FEATURE macros are not enabled. +#define SL_STATUS_TWT_SETUP_ERR_SESSION_ACTIVE \ + ((sl_status_t)0x10071) ///< Occurs when user tries to give TWT config command when there is an already active TWT session. +#define SL_STATUS_TWT_TEARDOWN_ERR_FLOWID_NOT_MATCHED \ + ((sl_status_t)0x10072) ///< Occurs when TWT teardown command is given with a flow ID that does not match existing session flow ID. +#define SL_STATUS_TWT_TEARDOWN_ERR_NOACTIVE_SESS \ + ((sl_status_t)0x10073) ///< Occurs when teardown command is given while there is no active session. +#define SL_STATUS_TWT_SESSION_NOT_FEASIBLE \ + ((sl_status_t)0x10074) ///< This error code indicates that TWT session is not feasible. It is thrown only when TWT Auto Selection API is used. +#define SL_STATUS_SI91X_RESCHEDULE_TWT_NOT_SUPPORTED \ + ((sl_status_t)0x10075) ///< AP does not support TWT information frame reception. +#define SL_STATUS_SI91X_RESCHEDULE_TWT_ERR_NOACTIVE_SESS \ + ((sl_status_t)0x10076) ///< No active TWT agreement corresponding to given flow id. +#define SL_STATUS_SI91X_TWT_RESCHEDULING_IN_PROGRESS \ + ((sl_status_t)0x10077) ///< Suspend or resume TWT action is in progress. +#define SL_STATUS_SI91X_RESCHEDULE_TWT_PACKET_CREATION_FAILED \ + ((sl_status_t)0x10078) ///< TWT information frame packet creation failed in firmware. +#define SL_STATUS_SI91X_INVALID_STATION_TSF \ + ((sl_status_t)0x10079) ///< Invalid station TSF error returned when station is not connected or atleast one beacon is not received +#define SL_STATUS_SI91X_MQTT_ERROR_UNACCEPTABLE_PROTOCOL \ + ((sl_status_t)0x10081) ///< The Server does not support the level of the MQTT protocol requested by the Client. +#define SL_STATUS_SI91X_MQTT_ERROR_IDENTIFIER_REJECTED \ + ((sl_status_t)0x10082) ///< The Client identifier is correct UTF-8 but not allowed by the Server. +#define SL_STATUS_SI91X_MQTT_ERROR_SERVER_UNAVAILABLE \ + ((sl_status_t)0x10083) ///< The Network Connection has been made but the MQTT service is unavailable. +#define SL_STATUS_SI91X_MQTT_ERROR_BAD_USERNAME_PASSWORD \ + ((sl_status_t)0x10084) ///< The data in the user name or password is malformed. +#define SL_STATUS_SI91X_MQTT_ERROR_NOT_AUTHORIZED ((sl_status_t)0x10085) ///< The Client is not authorized to connect. +#define SL_STATUS_SI91X_SA_QUERY_TIMEOUT ((sl_status_t)0x10086) ///< Disconnection due to SA Query Timeout. +#define SL_STATUS_SI91X_TRANSCEIVER_PEER_DS_FEAT_DISABLED \ + ((sl_status_t)0x10096) ///< Feature to add peers in MAC layer is disabled +#define SL_STATUS_SI91X_TRANSCEIVER_PEER_ALREADY_EXISTS ((sl_status_t)0x10097) ///< Peer already exists in MAC layer +#define SL_STATUS_SI91X_TRANSCEIVER_MAX_PEER_LIMIT_REACHED \ + ((sl_status_t)0x10098) ///< Max peer limit reached in MAC layer +#define SL_STATUS_SI91X_TRANSCEIVER_PEER_NOT_FOUND ((sl_status_t)0x10099) ///< Peer not found in MAC layer +#define SL_STATUS_SI91X_DUPLICATE_ENTRY_EXISTS_IN_DNS_SERVER_TABLE \ + ((sl_status_t)0x100AF) ///< Duplicate entry exists in DNS server table. +#define SL_STATUS_SI91X_NO_MEM_AVAILABLE ((sl_status_t)0x100B1) ///< Memory error: No memory available. +#define SL_STATUS_SI91X_INVALID_CHARACTERS_IN_JSON_OBJECT ((sl_status_t)0x100B2) ///< Invalid characters in JSON object. +#define SL_STATUS_SI91X_NO_KEY_FOUND ((sl_status_t)0x100B3) ///< Update commands: No such key found. +#define SL_STATUS_SI91X_NO_FILE_FOUND ((sl_status_t)0x100B4) ///< No such file found: Re-check filename. +#define SL_STATUS_SI91X_NO_WEB_PAGE_EXISTS_WITH_SAME_FILENAME \ + ((sl_status_t)0x100B5) ///< No corresponding web page exists with same filename. +#define SL_STATUS_SI91X_SPACE_UNAVAILABLE_FOR_NEW_FILE ((sl_status_t)0x100B6) ///< Space unavailable for new file. +#define SL_STATUS_SI91X_INVALID_INPUT_DATA \ + ((sl_status_t)0x100C1) ///< Invalid input data, Re-check filename, lengths, etc. +#define SL_STATUS_SI91X_NO_SPACE_AVAILABLE_FOR_NEW_FILE ((sl_status_t)0x100C2) ///< Space unavailable for new file. +#define SL_STATUS_SI91X_EXISTING_FILE_OVERWRITE \ + ((sl_status_t)0x100C3) ///< Existing file overwrite: Exceeds size of previous file. Use erase and try again. +#define SL_STATUS_SI91X_NO_SUCH_FILE_FOUND ((sl_status_t)0x100C4) ///< No such file found. Re-check filename. +#define SL_STATUS_SI91X_MEMORY_ERROR ((sl_status_t)0x100C5) ///< Memory Error: No memory available. +#define SL_STATUS_SI91X_RECEIVED_MORE_WEB_PAGE_DATA \ + ((sl_status_t)0x100C6) ///< Received more web page data than the total length initially specified. +#define SL_STATUS_SI91X_SET_REGION_ERROR ((sl_status_t)0x100C7) ///< Error in set region command. +#define SL_STATUS_SI91X_INVALID_WEBPAGE_CURRENT_CHUNK_LEN \ + ((sl_status_t)0x100C8) ///< Web page current chunk length is incorrect. +#define SL_STATUS_SI91X_AP_SET_REGION_COMMAND_ERROR ((sl_status_t)0x100CA) ///< Error in AP set region command. +#define SL_STATUS_SI91X_AP_SET_REGION_COMMAND_PARAMETERS_ERROR \ + ((sl_status_t)0x100CB) ///< Error in AP set region command parameters. +#define SL_STATUS_SI91X_REGION_CODE_NOT_SUPPORTED ((sl_status_t)0x100CC) ///< Region code not supported. +#define SL_STATUS_SI91X_EXTRACTING_COUNTRY_REGION_FROM_BEACON_FAILED \ + ((sl_status_t)0x100CD) ///< Error in extracting country region from beacon. +#define SL_STATUS_SI91X_SELECTED_REGION_NOT_SUPPORTED \ + ((sl_status_t)0x100CE) ///< Device does not have selected region support. +#define SL_STATUS_SI91X_SSL_TLS_CONTEXT_CREATION_FAILED ((sl_status_t)0x100D1) ///< SSL/TLS context create failed. +#define SL_STATUS_SI91X_SSL_TLS_HANDSHAKE_FAIL \ + ((sl_status_t)0x100D2) ///< SSL/TLS handshake failed. Socket will be closed. +#define SL_STATUS_SI91X_SSL_TLS_MAX_SOCKETS_REACHED ((sl_status_t)0x100D3) ///< SSL/TLS max sockets reached. +#define SL_STATUS_SI91X_FTP_CLIENT_NOT_CONNECTED ((sl_status_t)0x100D3) ///< FTP client is not connected. +#define SL_STATUS_SI91X_CIPHER_SET_FAILED ((sl_status_t)0x100D4) ///< Cipher set failure. +#define SL_STATUS_SI91X_HTTP_CREDENTIALS_MAX_LEN_EXCEEDED \ + ((sl_status_t)0x100F1) ///< HTTP credentials maximum length exceeded. +#define SL_STATUS_SI91X_FEATURE_NOT_SUPPORTED ((sl_status_t)0x100F7) ///< Feature not supported. +#define SL_STATUS_SI91X_FLASH_WRITE_OR_FLASH_DATA_VERIFICATION_FAILED \ + ((sl_status_t)0x100F8) ///< Unable to write to flash OR flash data verification failed. +#define SL_STATUS_SI91X_CALIBRATION_DATA_VERIFICATION_FAILED \ + ((sl_status_t)0x100F9) ///< Calibration data verification failed. +#define SL_STATUS_SI91X_SNMP_INTERNAL_ERROR ((sl_status_t)0x10100) ///< SNMP internal error. +#define SL_STATUS_SI91X_SNMP_INVALID_IP_PROTOCOL ((sl_status_t)0x10104) ///< SNMP invalid IP protocol error. +#define SL_STATUS_SI91X_NO_DATA_RECEIVED_OR_RECEIVE_TIMEOUT \ + ((sl_status_t)0x1BB01) ///< No data received or receive timeout. +#define SL_STATUS_SI91X_INSUFFICIENT_DATA_FOR_TIME_CONVERSION \ + ((sl_status_t)0x1BB08) ///< Insufficient data for converting NTP time to mm-dd-yy time format. +#define SL_STATUS_SI91X_INVALID_SNTP_SERVER_ADDRESS ((sl_status_t)0x1BB0A) ///< Invalid SNTP server address. +#define SL_STATUS_SI91X_SNTP_CLIENT_NOT_STARTED ((sl_status_t)0x1BB0B) ///< SNTP client not started. +#define SL_STATUS_SI91X_SNTP_SERVER_UNAVAILABLE \ + ((sl_status_t)0x1BB10) ///< SNTP server not available. Client will not get any time update service from current server. +#define SL_STATUS_SI91X_SNTP_SERVER_AUTHENTICATION_FAILED ((sl_status_t)0x1BB15) ///< SNTP server authentication failed. +#define SL_STATUS_SI91X_INTERNAL_ERROR ((sl_status_t)0x1BB0E) ///< Internal error. +#define SL_STATUS_SI91X_MULTICAST_IP_ADDRESS_ENTRY_NOT_FOUND \ + ((sl_status_t)0x1BB16) ///< Entry not found for multicast IP address. +#define SL_STATUS_SI91X_MULTICAST_NO_ENTRIES_FOUND ((sl_status_t)0x1BB17) ///< No more entries found for multicast. +#define SL_STATUS_SI91X_IP_ADDRESS_ERROR ((sl_status_t)0x1BB21) ///< IP address error. +#define SL_STATUS_SI91X_SOCKET_ALREADY_BOUND ((sl_status_t)0x1BB22) ///< Socket already bound. +#define SL_STATUS_SI91X_PORT_UNAVAILABLE ((sl_status_t)0x1BB23) ///< Port not available. +#define SL_STATUS_SI91X_SOCKET_NOT_CREATED ((sl_status_t)0x1BB27) ///< Socket is not created. +#define SL_STATUS_SI91X_ICMP_REQUEST_FAILED ((sl_status_t)0x1BB29) ///< ICMP request failed. +#define SL_STATUS_SI91X_MAX_LISTEN_SOCKETS_REACHED ((sl_status_t)0x1BB33) ///< Maximum listen sockets reached. +#define SL_STATUS_SI91X_DHCP_DUPLICATE_LISTEN ((sl_status_t)0x1BB34) ///< DHCP duplicate listen. +#define SL_STATUS_SI91X_PORT_NOT_IN_CLOSE_STATE ((sl_status_t)0x1BB35) ///< Port not in closed state. +#define SL_STATUS_SI91X_SOCKET_CLOSED ((sl_status_t)0x1BB36) ///< Socket is closed or in process of closing. +#define SL_STATUS_SI91X_PROCESS_IN_PROGRESS ((sl_status_t)0x1BB37) ///< Process in progress. +#define SL_STATUS_SI91X_CONNECT_TO_NON_EXISTING_TCP_SERVER_SOCKET \ + ((sl_status_t)0x1BB38) ///< Trying to connect non-existing TCP server socket. +#define SL_STATUS_SI91X_ERROR_IN_LEN_OF_THE_COMMAND \ + ((sl_status_t)0x1BB3E) ///< Error in length of the command ('Exceeds number of characters' is mentioned in the PRM). +#define SL_STATUS_SI91X_WRONG_PACKET_INFO ((sl_status_t)0x1BB40) ///< Wrong packet info. +#define SL_STATUS_SI91X_SOCKET_STILL_BOUND ((sl_status_t)0x1BB42) ///< Socket is still bound. +#define SL_STATUS_SI91X_NO_FREE_PORT ((sl_status_t)0x1BB45) ///< No free port. +#define SL_STATUS_SI91X_INVALID_PORT ((sl_status_t)0x1BB46) ///< Invalid port. +#define SL_STATUS_SI91X_CORRUPTED_RPS_HEADER \ + ((sl_status_t)0x1BB49) ///< Corrupted RPS header encountered during firmware update. +#define SL_STATUS_SI91X_FEATURE_UNSUPPORTED ((sl_status_t)0x1BB4B) ///< Feature not supported. +#define SL_STATUS_SI91X_SOCKET_IN_UNCONNECTED_STATE \ + ((sl_status_t)0x1BB50) ///< Socket is not in connected state. Disconnected from server. In case of FTP, user need to give destroy command after receiving this error. +#define SL_STATUS_SI91X_POP3_SESSION_CREATION_FAILED \ + ((sl_status_t)0x1BB87) ///< POP3 session creation failed / POP3 session got terminated. +#define SL_STATUS_SI91X_DHCPV6_HANDSHAKE_FAIL ((sl_status_t)0x1BB9C) ///< DHCPv6 handshake failure. +#define SL_STATUS_SI91X_DHCP_INVALID_IP_RESPONSE ((sl_status_t)0x1BB9D) ///< DHCP invalid IP response. +#define SL_STATUS_SI91X_SMTP_AUTHENTICATION_ERROR ((sl_status_t)0x1BBA0) ///< SMTP authentication error. +#define SL_STATUS_SI91X_SMTP_OVER_SIZE_MAIL_DATA \ + ((sl_status_t)0x1BBA1) ///< No DNS server was specified, SMTP over size mail data. +#define SL_STATUS_SI91X_SMTP_INVALID_SERVER_REPLY ((sl_status_t)0x1BBA2) ///< SMTP invalid server reply. +#define SL_STATUS_SI91X_SMTP_DNS_QUERY_FAILED ((sl_status_t)0x1BBA3) ///< DNS query failed, SMTP internal error. +#define SL_STATUS_SI91X_SMTP_BAD_DNS_ADDRESS \ + ((sl_status_t)0x1BBA4) ///< Bad DNS address, SMTP server error code received. +#define SL_STATUS_SI91X_SMTP_INVALID_PARAMETERS ((sl_status_t)0x1BBA5) ///< SMTP invalid parameters. +#define SL_STATUS_SI91X_SMTP_PACKET_ALLOCATION_FAILED ((sl_status_t)0x1BBA6) ///< SMTP packet allocation failed. +#define SL_STATUS_SI91X_SMTP_GREET_REPLY_FAILED ((sl_status_t)0x1BBA7) ///< SMTP Greet reply failed. +#define SL_STATUS_SI91X_SMTP_PARAMETER_ERROR ((sl_status_t)0x1BBA8) ///< Parameter error, SMTP hello reply error. +#define SL_STATUS_SI91X_SMTP_MAIL_REPLY_ERROR ((sl_status_t)0x1BBA9) ///< SMTP mail reply error. +#define SL_STATUS_SI91X_SMTP_RCPT_REPLY_ERROR ((sl_status_t)0x1BBAA) ///< SMTP RCPT reply error. +#define SL_STATUS_SI91X_SMTP_MESSAGE_REPLY_ERROR ((sl_status_t)0x1BBAB) ///< SMTP message reply error. +#define SL_STATUS_SI91X_SMTP_DATA_REPLY_ERROR ((sl_status_t)0x1BBAC) ///< SMTP data reply error. +#define SL_STATUS_SI91X_SMTP_AUTH_REPLY_ERROR ((sl_status_t)0x1BBAD) ///< SMTP authentication reply error. +#define SL_STATUS_SI91X_SMTP_SERVER_REPLY_ERROR ((sl_status_t)0x1BBAE) ///< SMTP server error reply. +#define SL_STATUS_SI91X_DNS_DUPLICATE_ENTRY ((sl_status_t)0x1BBAF) ///< DNS duplicate entry. +#define SL_STATUS_SI91X_SMTP_OVERSIZE_SERVER_REPLY ((sl_status_t)0x1BBB1) ///< SMTP oversize server reply. +#define SL_STATUS_SI91X_SMTP_CLIENT_NOT_INITIALIZED ((sl_status_t)0x1BBB2) ///< SMTP client not initialized. +#define SL_STATUS_SI91X_DNS_IPV6_NOT_SUPPORTED ((sl_status_t)0x1BBB3) ///< DNS IPv6 not supported. +#define SL_STATUS_SI91X_INVALID_MAIL_INDEX_FOR_POP3_MAIL_RETRIEVE_COMMAND \ + ((sl_status_t)0x1BBC5) ///< Invalid mail index for POP3 mail retrieve command. +#define SL_STATUS_SI91X_SSL_TLS_HANDSHAKE_FAILED ((sl_status_t)0x1BBD2) ///< SSL/TLS handshake failed. +#define SL_STATUS_SI91X_FTP_CLIENT_DISCONNECTED \ + ((sl_status_t)0x1BBD3) ///< FTP client is not connected or disconnected with the FTP server. +#define SL_STATUS_SI91X_FTP_CLIENT_NOT_DISCONNECTED ((sl_status_t)0x1BBD4) ///< FTP client is not disconnected. +#define SL_STATUS_SI91X_FTP_FILE_NOT_OPENED ((sl_status_t)0x1BBD5) ///< FTP file is not opened. +#define SL_STATUS_SI91X_SSL_TLS_HANDSHAKE_TIMEOUT_OR_FTP_FILE_NOT_CLOSED \ + ((sl_status_t)0x1BBD6) ///< SSL/TLS handshake timeout or FTP file is not closed. +#define SL_STATUS_SI91X_FTP_EXPECTED_1XX_RESPONSE_NOT_RECEIVED \ + ((sl_status_t)0x1BBD9) ///< Expected [1XX response from FTP server but not received]. +#define SL_STATUS_SI91X_FTP_EXPECTED_2XX_RESPONSE_NOT_RECEIVED \ + ((sl_status_t)0x1BBDA) ///< Expected [2XX response from FTP server but not received]. +#define SL_STATUS_SI91X_FTP_EXPECTED_22X_RESPONSE_NOT_RECEIVED \ + ((sl_status_t)0x1BBDB) ///< Expected [22X response from FTP server but not received]. +#define SL_STATUS_SI91X_FTP_EXPECTED_23X_RESPONSE_NOT_RECEIVED \ + ((sl_status_t)0x1BBDC) ///< Expected [23X response from FTP server but not received]. +#define SL_STATUS_SI91X_FTP_EXPECTED_3XX_RESPONSE_NOT_RECEIVED \ + ((sl_status_t)0x1BBDD) ///< Expected [3XX response from FTP server but not received]. +#define SL_STATUS_SI91X_FTP_EXPECTED_33X_RESPONSE_NOT_RECEIVED \ + ((sl_status_t)0x1BBDE) ///< Expected [33X response from FTP server but not received]. +#define SL_STATUS_SI91X_HTTP_TIMEOUT ((sl_status_t)0x1BBE1) ///< HTTP timeout. +#define SL_STATUS_SI91X_HTTP_FAILED ((sl_status_t)0x1BBE2) ///< HTTP failed. +#define SL_STATUS_SI91X_HTTP_PUT_CLIENT_TIMEOUT ((sl_status_t)0x1BBE7) ///< HTTP timeout for HTTP PUT client. +#define SL_STATUS_SI91X_AUTHENTICATION_ERROR ((sl_status_t)0x1BBEB) ///< Authentication error. +#define SL_STATUS_SI91X_INVALID_PACKET_LENGTH \ + ((sl_status_t)0x1BBED) ///< Invalid packet length. Content length and received data length is mismatching. +#define SL_STATUS_SI91X_SERVER_RESPONDS_BEFORE_REQUEST_COMPLETE \ + ((sl_status_t)0x1BBEF) ///< Server responds before HTTP client request is complete. +#define SL_STATUS_SI91X_HTTP_PASSWORD_TOO_LONG ((sl_status_t)0x1BBF0) ///< HTTP/HTTPS password is too long. +#define SL_STATUS_SI91X_MQTT_PING_TIMEOUT ((sl_status_t)0x1BBF1) ///< MQTT ping time out error. +#define SL_STATUS_SI91X_MQTT_COMMAND_SENT_IN_INCORRECT_STATE \ + ((sl_status_t)0x1BBF2) ///< MQTT command sent in incorrect state. +#define SL_STATUS_SI91X_MQTT_ACK_TIMEOUT ((sl_status_t)0x1BBF3) ///< MQTT ACK time out error. +#define SL_STATUS_SI91X_POP3_INVALID_MAIL_INDEX ((sl_status_t)0x1BBFF) ///< POP3 error for invalid mail index. +#define SL_STATUS_SI91X_SOCKET_NOT_CONNECTED \ + ((sl_status_t)0x1FFFF) ///< Listening TCP socket in device is not connected to the remote peer, or the LTCP socket is not yet opened in the device. +#define SL_STATUS_SI91X_SOCKET_LIMIT_EXCEEDED \ + ((sl_status_t)0x1FFFE) ///< Sockets not available. The error comes if the host tries to open more than 10 sockets. +#define SL_STATUS_SI91X_HTTP_OTAF_INVALID_PACKET ((sl_status_t)0x1FFFD) ///< HTTP OTAF invalid packet. +#define SL_STATUS_SI91X_TCP_IP_INIT_FAILED ((sl_status_t)0x1FFFC) ///< TCP_IP initialization failed. +#define SL_STATUS_SI91X_CONCURRENT_IP_CREATION_ERROR \ + ((sl_status_t)0x1FFFB) ///< Cannot create IP in same interface in concurrent mode. +#define SL_STATUS_SI91X_HTTP_OTAF_INCOMPLETE_PACKET ((sl_status_t)0x1FFF4) ///< HTTP OTAF incomplete packet. +#define SL_STATUS_SI91X_INVALID_STORE_CONFIGURATION_PROFILE \ + ((sl_status_t)0x1FFF5) ///< Store configuration profile type mismatch or invalid profile type. +#define SL_STATUS_SI91X_MQTT_REMOTE_TERMINATE_ERROR ((sl_status_t)0x1FFF6) ///< MQTT remote terminate error. +#define SL_STATUS_SI91X_MQTT_KEEP_ALIVE_TERMINATE_ERROR \ + ((sl_status_t)0x1BBF1) ///< MQTT remote terminate error due to keep alive response timeout. +#define SL_STATUS_SI91X_BYTE_STUFFING_ERROR_IN_AT_MODE ((sl_status_t)0x1FFF7) ///< Byte stuffing error in AT mode. +#define SL_STATUS_SI91X_INVALID_COMMAND_OR_OPERATION \ + ((sl_status_t)0x1FFF8) ///< Invalid command (e.g. parameters insufficient or invalid in the command). Invalid operation (e.g. power save command with the same mode given twice, accessing wrong socket, creating more than allowed sockets ). +#define SL_STATUS_SI91X_HTTP_OTAF_NO_PACKET ((sl_status_t)0x1FFF9) ///< HTTP OTAF no packet. +#define SL_STATUS_SI91X_TCP_SOCKET_NOT_CONNECTED ((sl_status_t)0x1FFFA) ///< TCP socket is not connected. +#define SL_STATUS_SI91X_MAX_STATION_COUNT_EXCEEDED \ + ((sl_status_t)0x1FFC5) ///< Station count exceeded max station supported. +#define SL_STATUS_SI91X_UNABLE_TO_SEND_TCP_DATA ((sl_status_t)0x1FFC4) ///< Unable to send TCP data. +#define SL_STATUS_SI91X_SOCKET_BUFFER_TOO_SMALL ((sl_status_t)0x1FFBC) ///< Socket buffer too small. +#define SL_STATUS_SI91X_INVALID_CONTENT_IN_DNS_RESPONSE \ + ((sl_status_t)0x1FFBB) ///< Invalid content in the DNS response to the DNS resolution query. +#define SL_STATUS_SI91X_DNS_CLASS_ERROR_IN_DNS_RESPONSE \ + ((sl_status_t)0x1FFBA) ///< DNS class error in response to the DNS resolution query. +#define SL_STATUS_SI91X_DNS_COUNT_ERROR_IN_DNS_RESPONSE \ + ((sl_status_t)0x1FFB8) ///< DNS count error in response to the DNS resolution query. +#define SL_STATUS_SI91X_DNS_RETURN_CODE_ERROR_IN_DNS_RESPONSE \ + ((sl_status_t)0x1FFB7) ///< DNS return code error in the response to the DNS resolution query. +#define SL_STATUS_SI91X_DNS_OPCODE_ERROR_IN_DNS_RESPONSE \ + ((sl_status_t)0x1FFB6) ///< DNS Opcode error in the response to the DNS resolution query. +#define SL_STATUS_SI91X_DNS_ID_MISMATCH \ + ((sl_status_t)0x1FFB5) ///< DNS id mismatch between DNS resolution request and response. +#define SL_STATUS_SI91X_INVALID_INPUT_IN_DNS_QUERY \ + ((sl_status_t)0x1FFAB) ///< An invalid input to the DNS resolution query. +#define SL_STATUS_SI91X_DNS_RESPONSE_TIMEOUT ((sl_status_t)0x1FF42) ///< DNS response was timed out. +#define SL_STATUS_SI91X_ARP_REQUEST_FAILURE ((sl_status_t)0x1FFA1) ///< ARP request failure. +#define SL_STATUS_SI91X_UNABLE_TO_UPDATE_TCP_WINDOW ((sl_status_t)0x1FF91) ///< Unable to update TCP window. +#define SL_STATUS_SI91X_DHCP_LEASE_EXPIRED ((sl_status_t)0x1FF9D) ///< DHCP lease time expired. +#define SL_STATUS_SI91X_DHCP_HANDSHAKE_FAILURE ((sl_status_t)0x1FF9C) ///< DHCP handshake failure. +#define SL_STATUS_SI91X_WEBSOCKET_CREATION_FAILED \ + ((sl_status_t)0x1FF88) ///< This error is issued when WebSocket creation failed. +#define SL_STATUS_SI91X_TRYING_TO_CONNECT_NON_EXISTENT_TCP_SERVER_SOCKET \ + ((sl_status_t)0x1FF87) ///< This error is issued when device tried to connect to a non-existent TCP server socket on the remote side. +#define SL_STATUS_SI91X_TRYING_TO_CLOSE_NON_EXISTENT_SOCKET \ + ((sl_status_t)0x1FF86) ///< This error is issued when tried to close non-existent socket. or invalid socket descriptor. +#define SL_STATUS_SI91X_INVALID_SOCKET_PARAMETERS ((sl_status_t)0x1FF85) ///< Invalid socket parameters. +#define SL_STATUS_SI91X_FEATURE_NOT_AVAILABLE ((sl_status_t)0x1FF82) ///< Feature not supported. +#define SL_STATUS_SI91X_SOCKET_ALREADY_OPEN ((sl_status_t)0x1FF81) ///< Socket already open. +#define SL_STATUS_SI91X_MAX_SOCKETS_EXCEEDED \ + ((sl_status_t)0x1FF80) ///< Attempt to open more than the maximum allowed number of sockets. +#define SL_STATUS_SI91X_DATA_LENGTH_EXCEEDS_MSS ((sl_status_t)0x1FF7E) ///< Data length exceeds mss. +#define SL_STATUS_SI91X_IP_CONFLICT_ERROR \ + ((sl_status_t)0x1FF75) ///< DUT unable to configure IP address due to IP conflict. +#define SL_STATUS_SI91X_FEATURE_NOT_ENABLED ((sl_status_t)0x1FF74) ///< Feature not enabled. +#define SL_STATUS_SI91X_DHCP_SERVER_NOT_SET ((sl_status_t)0x1FF73) ///< DHCP server not set in AP mode. +#define SL_STATUS_SI91X_AP_SET_REGION_PARAM_ERROR ((sl_status_t)0x1FF71) ///< Error in AP set region command parameters. +#define SL_STATUS_SI91X_SSL_TLS_NOT_SUPPORTED ((sl_status_t)0x1FF70) ///< SSL/TLS not supported. +#define SL_STATUS_SI91X_JSON_NOT_SUPPORTED ((sl_status_t)0x1FF6F) ///< JSON not supported. +#define SL_STATUS_SI91X_INVALID_OPERATING_MODE ((sl_status_t)0x1FF6E) ///< Invalid operating mode. +#define SL_STATUS_SI91X_INVALID_SOCKET_CONFIG_PARAMS \ + ((sl_status_t)0x1FF6D) ///< Invalid socket configuration parameters. +#define SL_STATUS_SI91X_WEBSOCKET_CREATION_TIMEOUT ((sl_status_t)0x1FF6C) ///< Web socket creation timeout. +#define SL_STATUS_SI91X_PARAM_MAX_VALUE_EXCEEDED \ + ((sl_status_t)0x1FF6B) ///< Parameter maximum allowed value is exceeded. +#define SL_STATUS_SI91X_SOCKET_READ_TIMEOUT ((sl_status_t)0x1FF6A) ///< Socket read timeout. +#define SL_STATUS_SI91X_INVALID_COMMAND_SEQUENCE ((sl_status_t)0x1FF69) ///< Invalid command in sequence. +#define SL_STATUS_SI91X_DNS_RESPONSE_TIMEOUT_ERROR ((sl_status_t)0x1FF42) ///< DNS response timed out. +#define SL_STATUS_SI91X_HTTP_SOCKET_CREATION_FAILED ((sl_status_t)0x1FF41) ///< HTTP socket creation failed. +#define SL_STATUS_SI91X_HTTP_GET_CMD_IN_PROGRESS ((sl_status_t)0x10005) ///< HTTP GET command is in progress +#define SL_STATUS_SI91X_TCP_CLOSE_BEFORE_RESPONSE_ERROR \ + ((sl_status_t)0x1FF40) ///< TCP socket close command is issued before getting the response of the previous close command. +#define SL_STATUS_SI91X_WAIT_ON_HOST_FEATURE_NOT_ENABLED ((sl_status_t)0x1FF36) ///< 'Wait On Host' feature not enabled. +#define SL_STATUS_SI91X_STORE_CONFIG_CHECKSUM_INVALID \ + ((sl_status_t)0x1FF35) ///< Store configuration checksum validation failed. +#define SL_STATUS_SI91X_TCP_KEEP_ALIVE_TIMEOUT ((sl_status_t)0x1FF33) ///< TCP keep alive timed out. +#define SL_STATUS_SI91X_TCP_ACK_FAILED_FOR_SYN_ACK ((sl_status_t)0x1FF2D) ///< TCP ACK failed for TCP SYN-ACK. +#define SL_STATUS_SI91X_MEMORY_LIMIT_EXCEEDED \ + ((sl_status_t)0x1FF2C) ///< Memory limit exceeded in a given operating mode. +#define SL_STATUS_SI91X_MEMORY_LIMIT_EXCEEDED_DURING_AUTO_JOIN \ + ((sl_status_t)0x1FF2A) ///< Memory limit exceeded in an operating mode during auto join/create. +#define SL_STATUS_SI91X_MDNS_COMMAND_NOT_SUPPORTED ((sl_status_t)0x1FF2B) ///< MDNS command type is invalid. +#define SL_STATUS_SI91X_PUF_OPERATION_BLOCKED ((sl_status_t)0x1CC2F) ///< PUF operation is blocked. +#define SL_STATUS_SI91X_PUF_ACTIVATION_CODE_INVALID ((sl_status_t)0x1CC31) ///< PUF activation code invalid. +#define SL_STATUS_SI91X_PUF_INPUT_PARAMETERS_INVALID ((sl_status_t)0x1CC32) ///< PUF input parameters invalid. +#define SL_STATUS_SI91X_PUF_IN_ERROR_STATE ((sl_status_t)0x1CC33) ///< PUF in error state. +#define SL_STATUS_SI91X_PUF_OPERATION_NOT_ALLOWED ((sl_status_t)0x1CC34) ///< PUF operation not allowed. +#define SL_STATUS_SI91X_PUF_OPERATION_FAILED ((sl_status_t)0x1CC35) ///< PUF operation failed. +#define SL_STATUS_SI91X_AUTO_JOIN_IN_PROGRESS \ + ((sl_status_t)0x15A5A) ///< Auto join or user store configuration going on. +#define SL_STATUS_SI91X_RSNIE_FROM_AP_INVALID ((sl_status_t)0x1FFE1) ///< Improper RSNIE from AP to station. +#define SL_STATUS_SI91X_SNTP_MAX_ATTEMPTS_REACHED ((sl_status_t)0x1FF5F) ///< Reached maximum SNTP invalid attempts. +#define SL_STATUS_SI91X_FREQUENCY_OFFSET_ZER0 ((sl_status_t)0x100FC) ///< Frequency offset sent is zero. +#define SL_STATUS_SI91X_FREQUENCY_OFFSET_OUT_OF_LIMITS \ + ((sl_status_t)0x100FB) ///< Frequency offset specified goes beyond upper or lower limits and indicates that frequency offset cannot be changed further. + +//Bluetooth Generic Error Codes +#define SL_STATUS_SI91X_UNKNOWN_HCI_COMMAND (0x4E01) ///< Unknown HCI command . +#define SL_STATUS_SI91X_UNKNOWN_CONNECTION_IDENTIFIER (0x4E02) ///< Unknown Connection Identifier . +#define SL_STATUS_SI91X_HARDWARE_FAILURE (0x4E03) ///< Hardware failure . +#define SL_STATUS_SI91X_PAGE_TIMEOUT (0x4E04) ///< Page timeout . +#define SL_STATUS_SI91X_AUTHENTICATION_FAILURE (0x4E05) ///< Authentication failure . +#define SL_STATUS_SI91X_PIN_MISSING (0x4E06) ///< Pin missing . +#define SL_STATUS_SI91X_MEMORY_CAPACITY_EXCEED (0x4E07) ///< Memory capacity exceeded . +#define SL_STATUS_SI91X_CONNECTION_TIMEOUT (0x4E08) ///< Connection timeout . +#define SL_STATUS_SI91X_CONNECTION_LIMIT_EXCEED (0x4E09) ///< Connection limit exceeded . +#define SL_STATUS_SI91X_SCO_LIMIT_EXCEED (0x4E0A) ///< SCO limit exceeded . +#define SL_STATUS_SI91X_ACL_CONNECTION_ALREADY_EXIST (0x4E0B) ///< ACL Connection already exists . +#define SL_STATUS_SI91X_COMMAND_DISALLOWED (0x4E0C) ///< Command disallowed . +#define SL_STATUS_SI91X_CONNECTION_REJECTED_LIMITED_RESOURCES \ + (0x4E0D) ///< Connection rejected due to limited resources . +#define SL_STATUS_SI91X_CONNECTION_REJECTED_SECURITY_REASONS (0x4E0E) ///< Connection rejected due to security reasons . +#define SL_STATUS_SI91X_CONNECTION_REJECTED_FOR_BD_ADDR (0x4E0F) ///< Connection rejected for BD address . +#define SL_STATUS_SI91X_CONNECTION_ACCEPT_TIMEOUT (0x4E10) ///< Connection accept timeout . +#define SL_STATUS_SI91X_UNSUPPORTED_FEATURE_OR_PARAMETER (0x4E11) ///< Unsupported feature or parameter . +#define SL_STATUS_SI91X_INVALID_HCI_COMMAND_PARAMETER (0x4E12) ///< Invalid HCI command parameter . +#define SL_STATUS_SI91X_REMOTE_USER_TERMINATED_CONNECTION (0x4E13) ///< Remote user terminated connection . +#define SL_STATUS_SI91X_REMOTE_DEVICE_TERMINATED_CONNECTION_LOW_RESOURCES \ + (0x4E14) ///< Remote device terminated connection due to low resources . +#define SL_STATUS_SI91X_REMOTE_DEVICE_TERMINATED_CONNECTION_POWER_OFF \ + (0x4E15) ///< Remote device terminated connection due to power off . +#define SL_STATUS_SI91X_LOCAL_DEVICE_TERMINATED_CONNECTION (0x4E16) ///< Local device terminated connection . +#define SL_STATUS_SI91X_REPEATED_ATTEMPTS (0x4E17) ///< Repeated attempts . +#define SL_STATUS_SI91X_PAIRING_NOT_ALLOWED (0x4E18) ///< Pairing not allowed . +#define SL_STATUS_SI91X_UNKNOWN_LMP_PDU (0x4E19) ///< Unknown LMP PDU . +#define SL_STATUS_SI91X_UNSUPPORTED_REMOTE_FEATURE (0x4E1A) ///< Unsupported remote feature . +#define SL_STATUS_SI91X_SCO_OFFSET_REJECTED (0x4E1B) ///< SCO offset rejected . +#define SL_STATUS_SI91X_SCO_INTERVAL_REJECTED (0x4E1C) ///< SCO interval rejected . +#define SL_STATUS_SI91X_SCO_AIR_MODE_REJECTED (0x4E1D) ///< SCO Air mode rejected . +#define SL_STATUS_SI91X_INVALID_LMP_PARAMETERS (0x4E1E) ///< Invalid LMP parameters . +#define SL_STATUS_SI91X_UNSPECIFIED (0x4E1F) ///< Unspecified . +#define SL_STATUS_SI91X_UNSUPPORTED_LMP_PARAMETER (0x4E20) ///< Unsupported LMP Parameter . +#define SL_STATUS_SI91X_ROLE_CHANGE_NOT_ALLOWED (0x4E21) ///< Role change not allowed . +#define SL_STATUS_SI91X_LMP_RESPONSE_TIMEOUT (0x4E22) ///< LMP response timeout . +#define SL_STATUS_SI91X_LMP_TRANSACTION_COLLISION (0x4E23) ///< LMP transaction collision . +#define SL_STATUS_SI91X_LMP_PDU_NOT_ALLOWED (0x4E24) ///< LMP PDU not allowed . +#define SL_STATUS_SI91X_ENCRYPTION_MODE_NOT_ACCEPTABLE (0x4E25) ///< Encryption mode not acceptable . +#define SL_STATUS_SI91X_LINK_KEY_CANNOT_CHANGE (0x4E26) ///< Link key cannot change . +#define SL_STATUS_SI91X_REQUESTED_QOS_NOT_SUPPORTED (0x4E27) ///< Requested QOS not supported . +#define SL_STATUS_SI91X_INSTANT_PASSED (0x4E28) ///< Instant passed . +#define SL_STATUS_SI91X_PAIRING_WITH_UNIT_KEY_NOT_SUPPORTED (0x4E29) ///< Pairing with unit key not supported . +#define SL_STATUS_SI91X_DIFFERENT_TRANSACTION_COLLISION (0x4E2A) ///< Different transaction collision . +#define SL_STATUS_SI91X_RESERVED_1 (0x4E2B) ///< Reserved 1 . +#define SL_STATUS_SI91X_QOS_PARAMETER_NOT_ACCEPTABLE (0x4E2C) ///< QOS parameter not acceptable . +#define SL_STATUS_SI91X_QOS_REJECTED (0x4E2D) ///< QOS rejected . +#define SL_STATUS_SI91X_CHANNEL_CLASSIFICATION_NOT_SUPPORTED (0x4E2E) ///< Channel classification not supported . +#define SL_STATUS_SI91X_INSUFFICIENT_SECURITY (0x4E2F) ///< Insufficient security . +#define SL_STATUS_SI91X_PARAMETER_OUT_OF_MANDATORY_RANGE (0x4E30) ///< Parameter out of mandatory range . +#define SL_STATUS_SI91X_RESERVED_2 (0x4E31) ///< Reserved 2 . +#define SL_STATUS_SI91X_ROLE_SWITCH_PENDING (0x4E32) ///< Role switch pending . +#define SL_STATUS_SI91X_RESERVED_3 (0x4E33) ///< Reserved 3 . +#define SL_STATUS_SI91X_RESERVED_SLOT_VIOLATION (0x4E34) ///< Reserved slot violation . +#define SL_STATUS_SI91X_ROLE_SWITCH_FAILED (0x4E35) ///< Role switch failed . +#define SL_STATUS_SI91X_EXTENDED_INQUIRY_RESPONSE_TOO_LARGE (0x4E36) ///< Extended Inquiry Response too large . +#define SL_STATUS_SI91X_EXTENDED_SECURE_SIMPLE_PAIRING_NOT_SUPPORTED (0x4E37) ///< Extended SSP not supported . +#define SL_STATUS_SI91X_HOST_BUSY_PAIRING (0X4E38) ///< Host busy pairing . +#define SL_STATUS_SI91X_PINCODE_REPLY_FOR_WRONG_BD_ADDRESS (0x4E39) ///< Wrong BD Address . +#define SL_STATUS_SI91X_CONNECTION_FAILED_ESTABLISHED (0x4E3E) ///< Connection Failed to be Established . +#define SL_STATUS_SI91X_INVALID_GAIN_TABLE_PAYLOAD_LENGTH (0x4F01) ///< Invalid Gain table payload length . +#define SL_STATUS_SI91X_INVALID_REGION (0x4F02) ///< Invalid Region . +#define SL_STATUS_SI91X_INVALID_GAIN_TABLE_OFFSET_REQUEST_TYPE (0x4F03) ///< Invalid Gain Table offset request type . +#define SL_STATUS_SI91X_INVALID_NODE_ID (0x4F04) ///< Invalid Node ID . +#define SL_STATUS_SI91X_BT_INVALID_COMMAND (0x4FF8) ///< BT Invalid Command . +#define SL_STATUS_SI91X_INVALID_ARGS (0x0101) ///< Invalid Args . +#define SL_STATUS_SI91X_UNKNOWN (0x0102) ///< Unknown . +#define SL_STATUS_SI91X_FIRMWARE_TIMEOUT (0x0103) ///< Firmware Timeout . +#define SL_STATUS_SI91X_MEMORY_ALLOC_FAIL (0x0104) ///< Memory alloc fail . +#define SL_STATUS_SI91X_IO_FAIL (0x0106) ///< I/O fail . +#define SL_STATUS_SI91X_UNSUPPORTED (0x0108) ///< Unsupported . +#define SL_STATUS_SI91X_SHORT_BUF (0x0109) ///< Short buf . +#define SL_STATUS_SI91X_BUF_OVERFLOW (0x010A) ///< Buf overflow . +#define SL_STATUS_SI91X_TOO_LARGE_BUF (0x010B) ///< Too large buf . +#define SL_STATUS_SI91X_I_O_ABORT (0x010C) ///< I/O abort . +#define SL_STATUS_SI91X_OPEN_FAIL (0x010D) ///< File open fail . +#define SL_STATUS_SI91X_OS_TASK_INVALID_PRIORITY (0x1010) ///< OS task invalid priority . +#define SL_STATUS_SI91X_OS_TASK_PRIO_EXISTS (0x1011) ///< OS task prio exists . +#define SL_STATUS_SI91X_OS_TASK_NOT_STOPPED (0x1012) ///< OS task not stopped . +#define SL_STATUS_SI91X_OS_SEM_MAX_VALUE (0x1020) ///< OS sem max value . +#define SL_STATUS_SI91X_OS_SEM_NOT_AVAILABLE (0x1021) ///< OS sem not available . +#define SL_STATUS_SI91X_OS_SEM_RESET (0x1022) ///< OS sem reset . +#define SL_STATUS_SI91X_OS_MUTEX_NOT_OWNER (0x1030) ///< OS mutex not owner . +#define SL_STATUS_SI91X_OS_MUTEX_NOT_LOCKED (0x1031) ///< OS mutex not locked . +#define SL_STATUS_SI91X_OS_MUTEX_LOCK_FAILED (0x1032) ///< OS mutex lock failed . +#define SL_STATUS_SI91X_OS_MUTEX_TRY_LOCK_FAILED (0x1033) ///< OS mutex try lock failed . +#define SL_STATUS_SI91X_OS_MSG_QUEUE_FULL (0x1040) ///< OS msg queue full . +#define SL_STATUS_SI91X_OS_MESSAGE_QUEUE_EMPTY (0x1041) ///< OS message queue empty . +#define SL_STATUS_SI91X_PIPE_EMPTY (0x1050) ///< Pipe empty . +#define SL_STATUS_SI91X_PIPE_FULL (0x1051) ///< Pipe full . +#define SL_STATUS_SI91X_INVALID_LEN (0x1052) ///< Invalid len . +#define SL_STATUS_SI91X_PIPE_READ_IN_USE (0x1053) ///< Pipe read in use . +#define SL_STATUS_SI91X_PIPE_WRITE_IN_USE (0x1054) ///< Pipe write in use . +#define SL_STATUS_SI91X_OS_TIMER_EXPIRED (0x1060) ///< OS timer expired . +#define SL_STATUS_SI91X_OS_TIMER_STATE_RUNNING (0x1061) ///< OS timer state running . +#define SL_STATUS_SI91X_OS_CANNOT_WAIT (0x1070) ///< OS cannot wait . +#define SL_STATUS_SI91X_OS_MEM_POOL_EMPTY (0x1080) ///< OS mem pool empty . +#define SL_STATUS_SI91X_OS_MEM_POOL_SIZE_SHORT (0x1081) ///< OS mem pool size short . + +//BLE Generic Error Codes +#define SL_STATUS_SI91X_DIRECTED_ADVERTISING_TIMEOUT (0x4E3C) ///< Directed Advertising Timeout . +#define SL_STATUS_SI91X_CONNECTION_TERMINATED_DUE_TO_MIC_FAILURE \ + (0x4E3D) ///< Connection terminated due to MIC failure . +#define SL_STATUS_SI91X_INVALID_HANDLE_RANGE (0x4E60) ///< Invalid Handle Range . +#define SL_STATUS_SI91X_MEMORY_IS_NOT_SUFFICIENT (0x4E61) ///< Memory is not sufficient . +#define SL_STATUS_SI91X_INVALID_PARAMETERS (0x4E62) ///< Invalid Parameters . +#define SL_STATUS_SI91X_BLE_BUFFER_COUNT_EXCEEDED (0x4E63) ///< BLE Buffer Count Exceeded . +#define SL_STATUS_SI91X_BLE_BUFFER_ALREADY_IN_USE (0x4E64) ///< BLE Buffer already in use . +#define SL_STATUS_SI91X_INVALID_ATTRIBUTE_LENGTH \ + (0x4E65) ///< Invalid Attribute Length When Small Buffer Mode is Configured . +#define SL_STATUS_SI91X_INVALID_NAME_LENGTH (0x4E66) ///< Invalid Name length when set to more than 16 bytes . + +//BLE Mode Error Codes +#define SL_STATUS_SI91X_INVALID_HANDLE (0x4A01) ///< Invalid Handle . +#define SL_STATUS_SI91X_READ_NOT_PERMITTED (0x4A02) ///< Read not permitted . +#define SL_STATUS_SI91X_WRITE_NOT_PERMITTED (0x4A03) ///< Write not permitted . +#define SL_STATUS_SI91X_INVALID_PDU (0x4A04) ///< Invalid PDU . +#define SL_STATUS_SI91X_INSUFFICIENT_AUTHENTICATION (0x4A05) ///< Insufficient authentication . +#define SL_STATUS_SI91X_REQUEST_NOT_SUPPORTED (0x4A06) ///< Request not supported . +#define SL_STATUS_SI91X_INVALID_OFFSET (0x4A07) ///< Invalid offset . +#define SL_STATUS_SI91X_INSUFFICIENTA_UTHORIZATION (0x4A08) ///< Insufficient authorization . +#define SL_STATUS_SI91X_PREPARE_QUEUE_FULL (0x4A09) ///< Prepare queue full . +#define SL_STATUS_SI91X_ATTRIBUTE_NOT_FOUND (0x4A0A) ///< Attribute not found . +#define SL_STATUS_SI91X_ATTRIBUTE_NOT_LONG (0x4A0B) ///< Attribute not Long . +#define SL_STATUS_SI91X_INSUFFICIENT_ENCRYPTION_KEY_SIZE (0x4A0C) ///< Insufficient encryption key size . +#define SL_STATUS_SI91X_INVALID_ATTRIBUTE_VALUE_LENGTH (0x4A0D) ///< Invalid attribute value length . +#define SL_STATUS_SI91X_UNLIKELY_ERROR (0x4A0E) ///< Unlikely error . +#define SL_STATUS_SI91X_INSUFFICIENT_ENCRYPTION (0x4A0F) ///< Insufficient encryption . +#define SL_STATUS_SI91X_UNSUPPORTED_GROUP_TYPE (0x4A10) ///< Unsupported group type . +#define SL_STATUS_SI91X_INSUFFICIENT_RESOURCES (0x4A11) ///< Insufficient resources . +#define SL_STATUS_SI91X_GATT_TIMEOUT (0x4A80) ///< GATT Timeout . +#define SL_STATUS_SI91X_DATA_MAINTAINED_IN_HOST (0x4AFF) ///< Data Maintained in Host . +#define SL_STATUS_SI91X_SMP_PASSKEY_ENTRY_FAILED (0x4B01) ///< SMP Passkey entry failed . +#define SL_STATUS_SI91X_SMP_OOB_NOT_AVAILABLE (0x4B02) ///< SMP OOB not available . +#define SL_STATUS_SI91X_SMP_AUTHENTICATION_REQUIREMENTS (0x4B03) ///< SMP Authentication Requirements . +#define SL_STATUS_SI91X_SMP_CONFIRM_VALUE_FAILED (0x4B04) ///< SMP confirm value failed . +#define SL_STATUS_SI91X_SMP_PAIRING_NOT_SUPPORTED (0x4B05) ///< SMP Pairing not supported . +#define SL_STATUS_SI91X_SMP_ENCRYPTION_KEY_SIZE_INSUFFICIENT (0x4B06) ///< SMP Encryption key size insufficient . +#define SL_STATUS_SI91X_SMP_COMMAND_NOT_SUPPORTED (0x4B07) ///< SMP command not supported . +#define SL_STATUS_SI91X_SMP_PAIRING_FAILED (0x4B08) ///< SMP pairing failed . +#define SL_STATUS_SI91X_SMP_REPEATED_ATTEMPTS (0x4B09) ///< SMP repeated attempts . +#define SL_STATUS_SI91X_SMP_INVALID_PARAMETERS (0x4B0A) ///< SMP Invalid parameters . +#define SL_STATUS_SI91X_SMP_DH_KEY_CHECK_FAILED (0x4B0B) ///< SMP DH Key check failed . +#define SL_STATUS_SI91X_SMP_NUMERIC_COMPARISON_FAILED (0x4B0C) ///< SMP Numeric Comparison Failed . +#define SL_STATUS_SI91X_SMP_INVALID_KEYS_GENERATED (0x4BFD) ///< SMP Invalid Keys Generated . +#define SL_STATUS_SI91X_SMP_IDENTICAL_PUBLIC_KEY (0x4BFE) ///< SMP Identical Public Key . +#define SL_STATUS_SI91X_PSM_CONN_FAILED (0x4C02) ///< PSM Conn Failed . +#define SL_STATUS_SI91X_BLE_REMOTE_DEVICE_FOUND (0x4D00) ///< BLE Remote device found . +#define SL_STATUS_SI91X_BLE_REMOTE_DEVICE_NOT_FOUND (0x4D01) ///< BLE Remote device not found . +#define SL_STATUS_SI91X_BLE_REMOTE_DEVICE_STRUCTURE_FULL (0x4D02) ///< BLE Remote device structure full . +#define SL_STATUS_SI91X_UNABLE_TO_CHANGE_STATE (0x4D03) ///< Unable to change state . +#define SL_STATUS_SI91X_BLE_NOT_CONNECTED (0x4D04) ///< BLE not Connected . +#define SL_STATUS_SI91X_BLE_SOCKET_NOT_AVAILABLE (0x4D05) ///< BLE socket not available. . +#define SL_STATUS_SI91X_ATTRIBUTE_RECORD_NOT_FOUND (0x4D06) ///< Attribute record not found . +#define SL_STATUS_SI91X_ATTRIBUTE_ENTRY_NOT_FOUND (0x4D07) ///< Attribute entry not found . +#define SL_STATUS_SI91X_PROFILE_RECORD_FULL (0x4D08) ///< Profile record full . +#define SL_STATUS_SI91X_ATTRIBUTE_RECORD_FULL (0x4D09) ///< Attribute record full . +#define SL_STATUS_SI91X_BLE_PROFILE_HANDLER_INVALID (0x4D0A) ///< BLE profile not found(profile handler invalid) . +#define SL_STATUS_SI91X_BLE_ATTRIBUTE_BUFFER_FULL (0x4D0B) ///< BLE Attribute Buffer Full . +#define SL_STATUS_SI91X_BLE_CONNECTION_SOCK_NOT_AVAILABLE (0x4D10) ///< BLE Connection Sock not Available . +#define SL_STATUS_SI91X_BLE_REMOTE_CREDITS_NOT_AVAILABLE (0x4D11) ///< BLE Remote Credits not Available . +#define SL_STATUS_SI91X_PARAMETER_OUTOFF_MANADATORY_RANGE (0x4D14) ///< Parameter is outoff the manadatory range . + +/** @} */ diff --git a/wiseconnect/components/common/inc/sl_constants.h b/wiseconnect/components/common/inc/sl_constants.h new file mode 100644 index 000000000..57e7716c2 --- /dev/null +++ b/wiseconnect/components/common/inc/sl_constants.h @@ -0,0 +1,184 @@ +/* + * EVALUATION AND USE OF THIS SOFTWARE IS SUBJECT TO THE TERMS AND + * CONDITIONS OF THE CONTROLLING LICENSE AGREEMENT FOUND AT LICENSE.md + * IN THIS SDK. IF YOU DO NOT AGREE TO THE LICENSE TERMS AND CONDITIONS, + * PLEASE RETURN ALL SOURCE FILES TO SILICON LABORATORIES. + * (c) Copyright 2018, Silicon Laboratories Inc. All rights reserved. + */ + +#pragma once + +#include "sl_additional_status.h" +#include +#include +#include +#include + +#define SL_STATUS_ENUM(prefix, name, value) prefix##_##name = (prefix##_ENUM_OFFSET + value) +#define SL_STATUS_SHARED_ENUM(prefix, name) prefix##_##name = (SL_##name) + +#ifdef __CC_ARM +#define BREAKPOINT() __asm__("bkpt #0"); +#else +#define BREAKPOINT() __asm__("bkpt"); +#endif + +#define SL_IPV4_ADDRESS_LENGTH 4 +#define SL_IPV6_ADDRESS_LENGTH 16 + +#ifndef UNUSED_VARIABLE +#define UNUSED_VARIABLE(x) (void)(x) +#endif // UNUSED_VARIABLE +#ifndef UNUSED_PARAMETER +#define UNUSED_PARAMETER(x) (void)(x) +#endif // UNUSED_PARAMETER + +#define ARRAY_COUNT(x) (sizeof(x) / sizeof *(x)) + +#ifndef FUZZING +#define SL_ASSERT(condition, ...) \ + if (!(condition)) { \ + BREAKPOINT(); \ + } +#else +#define SL_ASSERT(condition, ...) \ + if (!(condition)) { \ + } +#endif + +#ifndef ROUND_UP +#define ROUND_UP(x, y) ((x) % (y) ? (x) + (y) - ((x) % (y)) : (x)) +#endif /* ifndef ROUND_UP */ + +#define SL_WAIT_FOREVER 0xFFFFFFFF +#define SL_INVALID_POINTER ((void *)0xEFFFFFFF) // This can point to any location that will trigger an exception + +// Defines for log tags +#define ERROR_TAG "ERROR" +#define WARNING_TAG "WARNING" +#define DEBUG_TAG "DEBUG" +#define INFO_TAG "INFO" + +// Defines for error logging +#define PRINT_ERROR_LOGS 0 + +#define PRINT_STATUS(tag, status) printf("\r\n%s %s:%d: 0x%lu \r\n", tag, __FILE__, __LINE__, status); + +#define SL_CHECK_STATUS(x) \ + do { \ + if (x != SL_SUCCESS) { \ + goto status_check_fail; \ + } \ + } while (0) + +#define SL_CHECK_STATUS_AND_LOG(x, log) \ + do { \ + if (x != SL_SUCCESS) { \ + SL_LOG(log); \ + goto status_check_fail; \ + } \ + } while (0) + +// Macros to help work with pointers / allocations +#define SL_VERIFY_POINTER_OR_EXIT(pointer) \ + do { \ + if ((pointer) == NULL) { \ + goto exit; \ + } \ + } while (0) + +#define SL_VERIFY_POINTER_OR_GOTO(pointer, label) \ + do { \ + if ((pointer) == NULL) { \ + goto label; \ + } \ + } while (0) + +#define SL_VERIFY_POINTER_OR_RETURN(pointer, status) \ + do { \ + if ((pointer) == NULL) { \ + if (PRINT_ERROR_LOGS) { \ + PRINT_STATUS(ERROR_TAG, status) \ + } \ + return (status); \ + } \ + } while (0) + +#define SL_VERIFY_SUCCESS_OR_CONTINUE(x) \ + do { \ + if (x != SL_STATUS_OK) { \ + continue; \ + } \ + } while (0) + +#define SL_VERIFY_SUCCESS_OR_EXIT(x) \ + do { \ + if (x != SL_STATUS_OK) { \ + goto exit; \ + } \ + } while (0) + +#define SL_VERIFY_SUCCESS_OR_RETURN(x) \ + do { \ + if ((x) != SL_STATUS_OK) { \ + return (x); \ + } \ + } while (0) + +#define SL_CLEANUP_MALLOC(pointer) \ + do { \ + if ((pointer) != NULL) { \ + free(pointer); \ + pointer = NULL; \ + } \ + } while (0) + +#define SL_VERIFY_PARAMETER(condition) \ + do { \ + if (!(condition)) { \ + return SL_BAD_ARG; \ + } \ + } while (0) + +#define VERIFY_STATUS_AND_RETURN(status) \ + do { \ + if (status != SL_STATUS_OK) { \ + if (PRINT_ERROR_LOGS) { \ + PRINT_STATUS(ERROR_TAG, status) \ + } \ + return status; \ + } \ + } while (0) + +#define VERIFY_STATUS_AND_GOTO(status, goto_label) \ + do { \ + if (status != SL_STATUS_OK) { \ + if (PRINT_ERROR_LOGS) { \ + PRINT_STATUS(ERROR_TAG, status) \ + } \ + goto goto_label; \ + } \ + } while (0) + +#define PRINT_ERROR_STATUS(tag, status) \ + printf("\r\n%s %s:%d: 0x%x \r\n", tag, __FILE__, __LINE__, (unsigned int)status); + +#ifdef PRINT_DEBUG_LOG +extern void sl_debug_log(const char *format, ...); +#define SL_DEBUG_LOG(format, ...) \ + do { \ + sl_debug_log("%s:%s:%d:" format "\r\n", __FILE__, __func__, __LINE__, ##__VA_ARGS__); \ + } while (0) +#else +extern void sl_redirect_log(const char *format, ...); +#define SL_DEBUG_LOG(format, ...) \ + do { \ + sl_redirect_log("%s:%s:%d:" format "\r\n", __FILE__, __func__, __LINE__, ##__VA_ARGS__); \ + } while (0) +#endif + +#define SL_COMPILE_TIME_ASSERT(condition, comment) typedef char assertion_failed__##comment[2 * !!(condition)-1]; + +typedef uint32_t sl_duration_t; + +typedef void (*sl_event_handler_t)(void); diff --git a/wiseconnect/components/common/inc/sl_ieee802_types.h b/wiseconnect/components/common/inc/sl_ieee802_types.h new file mode 100644 index 000000000..a7467bf58 --- /dev/null +++ b/wiseconnect/components/common/inc/sl_ieee802_types.h @@ -0,0 +1,53 @@ +/***************************************************************************/ /** + * @file + * @brief Common IEEE 802 types + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#pragma once + +#include + +/** \addtogroup IEEE802 */ +/** @{ */ + +/// The IEEE defined 48-bit extended unique identifier (EUI-48) +typedef struct { + uint8_t octet[6]; ///< Value of EUI-48 address +} sl_eui48_address_t; + +/// The IEEE defined 64-bit extended unique identifier (EUI-64) +typedef struct { + uint8_t octet[8]; ///< Value of EUI-64 address +} sl_eui64_address_t; + +/// Generic SL MAC address type +typedef sl_eui48_address_t sl_mac_address_t; + +/// Ethernet MAC address +typedef sl_eui48_address_t sl_ethernet_address_t; + +/** @} */ diff --git a/wiseconnect/components/common/inc/sl_ip_types.h b/wiseconnect/components/common/inc/sl_ip_types.h new file mode 100644 index 000000000..493b53af2 --- /dev/null +++ b/wiseconnect/components/common/inc/sl_ip_types.h @@ -0,0 +1,89 @@ +/***************************************************************************/ /** + * @file + * @brief IP networking types + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#pragma once +#include "stdint.h" + +/** + * @addtogroup IP_ADDRESSES + * @{ + */ + +/// Enumeration of IP version +typedef enum { SL_IPV4_VERSION = 4, SL_IPV6_VERSION = 6 } sl_ip_version_t; + +/// Enumeration of IP address type +typedef enum { + SL_IPV4 = (1 << 2), ///< IPv4 + SL_IPV6 = (1 << 3), ///< IPv6. Unspecified sub-type + SL_IPV6_LINK_LOCAL = SL_IPV6 + 1, ///< IPv6. Link local address + SL_IPV6_SITE_LOCAL = SL_IPV6 + 2, ///< IPv6. Site local address + SL_IPV6_GLOBAL = SL_IPV6 + 3, ///< IPv6. Global address + SL_INVALID_IP = 0 ///< SL_INVALID_IP +} sl_ip_address_type_t; + +/// Enumeration of IP Management type +typedef enum { + SL_IP_MANAGEMENT_STATIC_IP = 1, ///< Assign STATIC IP address to an interface + SL_IP_MANAGEMENT_DHCP, ///< Assign IP address to an interface dynamically using DHCP + SL_IP_MANAGEMENT_LINK_LOCAL ///< Assign IP address using link-local addressing +} sl_ip_management_t; + +/// IPv4 address object +typedef union { + uint32_t value; ///< IPv4 address as a uint32_t + uint8_t bytes[4]; ///< IPv4 address as uint8_t[4] +} sl_ipv4_address_t; + +/// IPv6 address object +typedef union { + uint32_t value[4]; ///< IPv6 address as a uint32_t[4] + uint8_t bytes[16]; ///< IPv6 address as uint8_t[16] +} sl_ipv6_address_t; + +/// Generic IP Address Structure. Supports both IPv4 and IPv6 addresses +#pragma pack(1) +typedef struct { + /// IP address object + union { + sl_ipv4_address_t v4; ///< IPv4 address + sl_ipv6_address_t v6; ///< IPv6 address + } ip; + + sl_ip_address_type_t type; ///< IP address type +} sl_ip_address_t; +#pragma pack() + +/** @} */ + +/// Macro to assist initializing an IPv4 address +#define SL_IPV4_ADDRESS(a, b, c, d) \ + { \ + .ip.v4.bytes = { a, b, c, d }, .type = SL_IPV4 \ + } diff --git a/wiseconnect/components/common/inc/sl_utility.h b/wiseconnect/components/common/inc/sl_utility.h new file mode 100644 index 000000000..838f6ab1a --- /dev/null +++ b/wiseconnect/components/common/inc/sl_utility.h @@ -0,0 +1,92 @@ +/***************************************************************************/ /** + * @file + * @brief + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#pragma once + +#include "sl_status.h" +#include "sl_ip_types.h" +#include "sl_ieee802_types.h" +#include "sl_wifi_types.h" + +/***************************************************************************/ /** + * @brief + * Convert a character string into a sl_ipv4_address_t + * @param line + * Argument string that is expected to be like 192.168.0.1 + * @param ip + * Pointer to sl_ipv4_address_t. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + ******************************************************************************/ +sl_status_t convert_string_to_sl_ipv4_address(char *line, sl_ipv4_address_t *ip); + +/***************************************************************************/ /** +* @brief +* Convert IPv6 binary address into presentation (printable) format +* @param[in] input +* A pointer to the buffer containing the binary IPV6 address +* @param[in] dst +* A pointer to the buffer where the resulting string will be stored +* @param[in] size +* The size of the destination buffer in bytes +* @return +* A pointer to a resulting string containing human readable representation of IPV6 address. +******************************************************************************/ +char *sl_inet_ntop6(const unsigned char *input, char *dst, uint32_t size); + +/***************************************************************************/ /** + * @brief + * Convert a character string into a sl_mac_address_t + * @param line + * Argument string that is expected to be like 00:11:22:33:44:55 + * @param mac + * Pointer to sl_mac_address_t_address_t. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + ******************************************************************************/ +sl_status_t convert_string_to_mac_address(const char *line, sl_mac_address_t *mac); + +void print_sl_ip_address(const sl_ip_address_t *sl_ip_address); +void print_sl_ipv4_address(const sl_ipv4_address_t *ip_address); +void print_sl_ipv6_address(const sl_ipv6_address_t *ip_address); +void print_mac_address(sl_mac_address_t *mac_address); +void convert_uint32_to_bytestream(uint16_t data, uint8_t *buffer); +void little_to_big_endian(const unsigned int *source, unsigned char *result, unsigned int length); +int sl_inet_pton6(const char *src, const char *src_endp, unsigned char *dst, unsigned int *ptr_result); +void reverse_digits(unsigned char *xx, int no_digits); +void print_firmware_version(sl_wifi_firmware_version_t *firmware_version); + +/***************************************************************************/ /** + * @brief Print 802.11 packet + * + * @param[in] packet - pointer to start of MAC header + * @param[in] packet_length - total packet length (MAC header + payload) + * @param[in] max_payload_length - maximum number of payload bytes to print + ******************************************************************************/ +void print_80211_packet(uint8_t *packet, uint32_t packet_length, uint16_t max_payload_length); diff --git a/wiseconnect/components/common/src/sl_utility.c b/wiseconnect/components/common/src/sl_utility.c new file mode 100644 index 000000000..1f525c74b --- /dev/null +++ b/wiseconnect/components/common/src/sl_utility.c @@ -0,0 +1,344 @@ +/******************************************************************************* +* @file sl_utility.c +* @brief +******************************************************************************* +* # License +* Copyright 2023 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +#include +#include +#include "sl_utility.h" +#include "sl_constants.h" +#include "sl_string.h" +#include "cmsis_compiler.h" +#include +#include + +#ifdef SPRINTF_CHAR +#define SPRINTF(x) strlen(sprintf /**/ x) +#else +#define SPRINTF(x) ((size_t)sprintf x) +#endif + +#define DIGIT_VAL(c) \ + (((c >= '0') && (c <= '9')) ? (c - '0') \ + : ((c >= 'a') && (c <= 'z')) ? (c - 'a' + 10) \ + : ((c >= 'A') && (c <= 'Z')) ? (c - 'A' + 10) \ + : -1) + +extern char *strtok_r(char *, const char *, char **); + +void convert_uint32_to_bytestream(uint16_t data, uint8_t *buffer) +{ + buffer[0] = (uint8_t)(data & 0xFF); + buffer[1] = (uint8_t)((data >> 8) & 0xFF); + buffer[2] = (uint8_t)((data >> 16) & 0xFF); + buffer[3] = (uint8_t)((data >> 24) & 0xFF); + return; +} + +sl_status_t convert_string_to_sl_ipv4_address(char *line, sl_ipv4_address_t *ip) +{ + char *lasts = NULL; + const char *token = strtok_r(line, ".", &lasts); + + for (uint8_t i = 0; i < 4; i++, token = strtok_r(NULL, ".", &lasts)) { + if (token == NULL) { + return SL_STATUS_COMMAND_IS_INVALID; + } + ip->bytes[i] = (uint8_t)strtoul(token, 0, 0); + } + return SL_STATUS_OK; +} + +void print_sl_ip_address(const sl_ip_address_t *sl_ip_address) +{ + if (sl_ip_address == NULL) { + return; + } + + if (sl_ip_address->type == SL_IPV4) { + print_sl_ipv4_address(&sl_ip_address->ip.v4); + } else if (sl_ip_address->type == SL_IPV6) { + print_sl_ipv6_address(&sl_ip_address->ip.v6); + } +} + +void print_sl_ipv4_address(const sl_ipv4_address_t *ip_address) +{ + printf("%d.%d.%d.%d", ip_address->bytes[0], ip_address->bytes[1], ip_address->bytes[2], ip_address->bytes[3]); +} + +void print_sl_ipv6_address(const sl_ipv6_address_t *ip_address) +{ + char temp_buffer[46] = { 0 }; + sl_inet_ntop6((const unsigned char *)(ip_address), (char *)temp_buffer, sizeof(temp_buffer)); + printf("%s\r\n", temp_buffer); +} + +void print_mac_address(sl_mac_address_t *mac_address) +{ + if (mac_address == NULL) { + return; + } + printf("%2X:%2X:%2X:%2X:%2X:%2X", + mac_address->octet[0], + mac_address->octet[1], + mac_address->octet[2], + mac_address->octet[3], + mac_address->octet[4], + mac_address->octet[5]); +} + +char *sl_inet_ntop6(const unsigned char *input, char *dst, uint32_t size) +{ + char tmp[sizeof "ffff:ffff:ffff:ffff:ffff:ffff:255.255.255.255"]; + char *tp; + struct { + int base, len; + } best, cur; + unsigned int words[SL_IPV6_ADDRESS_LENGTH / 2]; + int i; + unsigned int ip_big_endian[4]; + const unsigned char *src; + src = (unsigned char *)&ip_big_endian; + + little_to_big_endian((const unsigned int *)input, (unsigned char *)ip_big_endian, SL_IPV6_ADDRESS_LENGTH); + + memset(words, '\0', sizeof words); + for (i = 0; i < SL_IPV6_ADDRESS_LENGTH; i += 2) { + int temp = src[i]; + words[i / 2] = (temp << 8) | src[i + 1]; + } + best.base = -1; + cur.base = -1; + best.len = 0; + cur.len = 0; + for (i = 0; i < (SL_IPV6_ADDRESS_LENGTH / 2); i++) { + if (words[i] == 0) { + if (cur.base == -1) { + cur.base = i; + cur.len = 1; + } else + cur.len++; + } else { + if (cur.base != -1) { + if (best.base == -1 || cur.len > best.len) + best = cur; + cur.base = -1; + } + } + } + if ((cur.base != -1) && (best.base == -1 || cur.len > best.len)) + best = cur; + if (best.base != -1 && best.len < 2) + best.base = -1; + /* + * Format the result. + */ + tp = tmp; + for (i = 0; i < (SL_IPV6_ADDRESS_LENGTH / 2); i++) { + /* Are we inside the best run of 0x00's? */ + if (best.base != -1 && i >= best.base && i < (best.base + best.len)) { + if (i == best.base) + *tp++ = ':'; + continue; + } + /* Are we following an initial run of 0x00s or any real hex? */ + if (i != 0) + *tp++ = ':'; + tp += SPRINTF((tp, "%x", words[i])); + } + /* Was it a trailing run of 0x00's? */ + if (best.base != -1 && (best.base + best.len) == (SL_IPV6_ADDRESS_LENGTH / 2)) + *tp++ = ':'; + *tp++ = '\0'; + /* + * Check for overflow, copy, and we're done. + */ + if ((uint32_t)(tp - tmp) > size) { + printf("\r\n Error \r\n"); + return NULL; + } + return memcpy(dst, tmp, size); +} + +static int hex_digit_value(char ch) +{ + if ('0' <= ch && ch <= '9') + return ch - '0'; + if ('a' <= ch && ch <= 'f') + return ch - 'a' + 10; + if ('A' <= ch && ch <= 'F') + return ch - 'A' + 10; + return -1; +} + +void little_to_big_endian(const unsigned int *source, unsigned char *result, unsigned int length) +{ + unsigned char *temp; + unsigned int curr = 0; + length /= 4; + + for (unsigned int i = 0; i < length; i++) { + curr = source[i]; + temp = &result[i * 4]; + temp[3] = (curr & 0xFF); + temp[2] = ((curr >> 8) & 0xFF); + temp[1] = ((curr >> 16) & 0xFF); + temp[0] = ((curr >> 24) & 0xFF); + } +} + +int sl_inet_pton6(const char *src, const char *src_endp, unsigned char *dst, unsigned int *ptr_result) +{ + unsigned char tmp[SL_IPV6_ADDRESS_LENGTH], *tp, *endp, *colonp; + const char *curtok __attribute__((__unused__)); + int ch; + size_t xdigits_seen; /* Number of hex digits since colon. */ + unsigned int val; + tp = memset(tmp, '\0', SL_IPV6_ADDRESS_LENGTH); + endp = tp + SL_IPV6_ADDRESS_LENGTH; + colonp = NULL; + + /* Leading :: requires some special handling. */ + if (src == src_endp) + return 0; + if (*src == ':') { + ++src; + if (src == src_endp || *src != ':') + return 0; + } + + curtok = src; + xdigits_seen = 0; + val = 0; + + while (src < src_endp) { + ch = *src++; + int digit = hex_digit_value((char)ch); + //printf(" digit :%d ",digit); + if (digit >= 0) { + if (xdigits_seen == 4) + return 0; + val <<= 4; + val |= digit; + if (val > 0xffff) + return 0; + ++xdigits_seen; + continue; + } + if (ch == ':') { + curtok = src; + + if (xdigits_seen == 0) { + if (colonp) + return 0; + colonp = tp; + continue; + } else if (src == src_endp) + return 0; + if (tp + 2 > endp) + return 0; + + *tp++ = (unsigned char)(val >> 8) & 0xff; + *tp++ = (unsigned char)val & 0xff; + + xdigits_seen = 0; + val = 0; + continue; + } + } + + if (xdigits_seen > 0) { + if (tp + 2 > endp) + return 0; + *tp++ = (unsigned char)(val >> 8) & 0xff; + *tp++ = (unsigned char)val & 0xff; + } + if (colonp != NULL) { + /* Replace :: with zeros. */ + if (tp == endp) + /* :: would expand to a zero-width field. */ + return 0; + size_t n = tp - colonp; + memmove(endp - n, colonp, n); + memset(colonp, 0, endp - n - colonp); + tp = endp; + } + if (tp != endp) + return 0; + + memcpy(dst, tmp, SL_IPV6_ADDRESS_LENGTH); + little_to_big_endian((const unsigned int *)dst, (unsigned char *)ptr_result, SL_IPV6_ADDRESS_LENGTH); + + return 1; +} + +sl_status_t convert_string_to_mac_address(const char *line, sl_mac_address_t *mac) +{ + // Verify we have the exact number of characters. Basic argument verification + if (sl_strnlen((char *)line, 18) != 17) { + return SL_STATUS_INVALID_PARAMETER; + } + + uint8_t index = 0; + while (index < 6) { + // Read all the data and verify validity + int char1 = DIGIT_VAL(line[0]); + int char2 = DIGIT_VAL(line[1]); + if (char1 == -1 || char2 == -1 || (line[2] != '\0' && line[2] != ':')) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Store value + mac->octet[index++] = (uint8_t)((uint8_t)char1 << 4) + (uint8_t)char2; + line += 3; + } + + return SL_STATUS_OK; +} + +void reverse_digits(unsigned char *xx, int no_digits) +{ + int count; + uint8_t temp; + for (count = 0; count < (no_digits / 2); count++) { + temp = xx[count]; + xx[count] = xx[no_digits - count - 1]; + xx[no_digits - count - 1] = temp; + } +} + +void print_firmware_version(sl_wifi_firmware_version_t *firmware_version) +{ + printf("\r\nFirmware version is: %x%x.%d.%d.%d.%d.%d.%d\r\n", + firmware_version->chip_id, + firmware_version->rom_id, + firmware_version->major, + firmware_version->minor, + firmware_version->security_version, + firmware_version->patch_num, + firmware_version->customer_id, + firmware_version->build_num); +} + +__WEAK void sl_debug_log(const char *format, ...) +{ + UNUSED_PARAMETER(format); +} + +void sl_redirect_log(const char *format, ...) +{ + UNUSED_PARAMETER(format); +} diff --git a/wiseconnect/components/device/silabs/si91x/mcu/core/chip/config/sl_board_configuration.h b/wiseconnect/components/device/silabs/si91x/mcu/core/chip/config/sl_board_configuration.h new file mode 100644 index 000000000..635fe5f8a --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/core/chip/config/sl_board_configuration.h @@ -0,0 +1,23 @@ +/******************************************************************************* +* @file sl_board_configuration.h +* @brief +******************************************************************************* +* # License +* Copyright 2023 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +#pragma once + +#include + +#define DEFAULT_UART NULL +#define DEFAULT_UART_PIN_CONFIG NULL diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_power_save.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_power_save.h new file mode 100644 index 000000000..db1b72ac5 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_power_save.h @@ -0,0 +1,323 @@ +/******************************************************************************* +* @file rsi_rom_power_save.h +* @brief +******************************************************************************* +* # License +* Copyright 2020 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ +/************************************************************************* + * + */ + +// Includes + +#ifndef __RSI_ROM_POWER_SAVE_H__ +#define __RSI_ROM_POWER_SAVE_H__ + +#include "rsi_ccp_user_config.h" +#include "rsi_packing.h" +#if defined(A11_ROM) +#include "rsi_rom_table_si91x.h" +#else +#include "rsi_rom_table_RS1xxxx.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef UNUSED_PARAMETER +#define UNUSED_PARAMETER(x) (void)(x) +#endif // UNUSED_PARAMETER + +/** + * \ingroup RSI_SPECIFIC_DRIVERS + * \defgroup POWER_SAVE + * @{ + * + */ +/** + * @fn STATIC INLINE rsi_error_t RSI_PS_PowerStateChangePs4toPs2(ULP_MODE_T enCtxSel , + * uint8_t PwrMuxSelUlpssRam , + * uint8_t pwrMuxSelM4UlpRam , + * uint8_t pwrMuxSelM4UlpRam16K , + * uint8_t pwrMuxSelM4Ulp , + * uint8_t pwrMuxSelUlpss , + * uint8_t bgSampleEnable , + * uint8_t dcDcEnable , + * uint8_t socLdoEnable , + * uint8_t standByDc + * ) + * @brief This API is used to used to change the power transition state from Power save state 4/3 to power save state 2 + * @param[in] enCtxSel : is Select enum for the context top ULP mode + * \n 00, 10 - \ref HP-MCU/LP-MCU Mode + * \n 01 - \ref ULP-MCU Mode + * \n 11 - \ref UULP-MCU Mode + * \n (1st 16K of M4 RAM is dedicated to IM, + * \n 2nd 16K of M4 RAM is dedicated to DM) + * @param[in] pwrMuxSelM4UlpRam : Select value for M4 ULP RAM Power MUX + * \n 3 \ref SOC LDO + * \n 1 \ref SCDCDC 0.9 + * \n 0 \ref SCDCDC 0.6 + * @param[in] PwrMuxSelUlpssRam :Select value for ULPSS RAM Power MUX + * \n 3 \ref SOC LDO + * \n 1 \ref SCDCDC 0.9 + * \n 0 \ref SCDCDC 0.6 + * @param[in] pwrMuxSelM4UlpRam16K : is Select value for M4 ULP RAM 16K Power MUX + * \n 3 \ref SOC LDO + * \n 1 \ref SCDCDC 0.9 + * \n 0 \ref SCDCDC 0.6 + * @param[in] pwrMuxSelM4Ulp : is Select value for M4 ULP (Peripherals + CORTEX Core )Power MUX + * \n 3 \ref SOC LDO + * \n 1 \ref SCDCDC 0.9 + * \n 0 \ref SCDCDC 0.6 + * @param[in] pwrMuxSelUlpss : is Select value for ULPSS(Peripherals) Power MUX + * \n 1 \ref SOC LDO + * \n 0 \ref SCDCDC 0.9 + * @param[in] bgSampleEnable : Value to enable or disable the bg Sample + * \n 0 :Disable + * \n 1 :Enale + * @param[in] dcDcEnable : Value to enable or disable the dcDcEnable + * \n 0 :Disable + * \n 1 :Enale + * @param[in] socLdoEnable : Value to enable or disable the socLdoEnable + * \n 0 :Disable + * \n 1 :Enale + * @param[in] standByDc : Value to enable or disable the standByDc + * \n 0 :Disable + * \n 1 :Enale + * @return returns 0 \ref RSI_OK on success,return error code on error + */ +STATIC INLINE rsi_error_t RSI_PS_PowerStateChangePs4toPs2(ULP_MODE_T enCtxSel, + uint8_t PwrMuxSelUlpssRam, + uint8_t pwrMuxSelM4UlpRam, + uint8_t pwrMuxSelM4UlpRam16K, + uint8_t pwrMuxSelM4Ulp, + uint8_t pwrMuxSelUlpss, + uint8_t bgSampleEnable, + uint8_t dcDcEnable, + uint8_t socLdoEnable, + uint8_t standByDc, + uint8_t taRamRetEnable, + uint8_t M4RamRetEnable) +{ + uint8_t x = 0; + // TODO: Check silicon rev from flash/efuse offset; for 1.4V do this programming + if (SiliconRev >= 0x14) { + if (taRamRetEnable) { + MCU_FSM->MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE |= HPSRAM_RET_ULP_MODE_EN; + MCU_FSM->MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE |= TA_RAM_RETENTION_MODE_EN; + } + if (M4RamRetEnable) { + MCU_FSM->MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE |= HPSRAM_RET_ULP_MODE_EN; + MCU_FSM->MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE |= M4SS_RAM_RETENTION_MODE_EN; +#ifndef SLI_SI917 + M4CLK->CLK_ENABLE_SET_REG1_b.M4SS_UM_CLK_STATIC_EN_b = 0x1; +#endif + for (x = 0; x < 10; x++) { + __ASM("NOP"); + } +#ifndef SLI_SI917 + M4CLK->CLK_ENABLE_CLR_REG1_b.M4SS_UM_CLK_STATIC_EN_b = 0x1; +#endif + } + } + // Moved this API from ROM to appication memmory + return ps_power_state_change_ps4tops2(enCtxSel, + PwrMuxSelUlpssRam, + pwrMuxSelM4UlpRam, + pwrMuxSelM4UlpRam16K, + pwrMuxSelM4Ulp, + pwrMuxSelUlpss, + bgSampleEnable, + dcDcEnable, + socLdoEnable, + standByDc); +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_PS_PowerStateChangePs2toPs4(uint32_t PmuBuckTurnOnWaitTime , uint32_t SocLdoTurnOnWaitTime) + * @brief This API is used to change the power state from PS2 to PS4 + * @param[in] PmuBuckTurnOnWaitTime : PMU buck time + * @param[in] SocLdoTurnOnWaitTime : soc ldo turn on time + * @return returns 0 \ref RSI_OK on success,return error code on error + */ +STATIC INLINE rsi_error_t RSI_PS_PowerStateChangePs2toPs4(uint32_t PmuBuckTurnOnWaitTime, uint32_t SocLdoTurnOnWaitTime) +{ + // Moved this API from ROM to appication memmory + return ps_power_state_change_ps2_to_Ps4(PmuBuckTurnOnWaitTime, SocLdoTurnOnWaitTime); +} + +/** + * @fn void RSI_PS_ClrWkpUpStatus(uint32_t wakeUpIntrClear) + * @brief This API is used clear the NPSS/wake up interrupts. + * @param wakeUpIntrClear : OR'ed value of register bits of NPSS interrupt register + * @return none + */ +STATIC INLINE void RSI_PS_ClrWkpUpStatus(uint32_t wakeUpIntrClear) +{ +#if defined(PS_ROMDRIVER_PRESENT) + ROMAPI_PWR_API->ps_clr_wkp_up_status(wakeUpIntrClear); +#else + ps_clr_wkp_up_status(wakeUpIntrClear); +#endif +} + +#ifdef SLI_SI917B0 + +STATIC INLINE void RSI_PS_RetentionSleepConfig_bypass(uint32_t stack_address, + uint32_t jump_cb_address, + uint32_t vector_offset, + uint32_t mode) +{ + UNUSED_PARAMETER(vector_offset); + qspi_reg_t *qspi_reg2 = (qspi_reg_t *)M4SS_PSRAM_QSPI_BASE_ADDRESS; + if (mode == RSI_WAKEUP_WITH_RETENTION) { + *(uint32 *)RSI_WAKE_FROM_FLASH_JUMP_ADDR = jump_cb_address; + } else { + if (MCURET_BOOTSTATUS_REG & BIT(13) || (M4_BBFF_STORAGE1 & PSRAM_SEC_EN)) { + if (((((qspi_reg_t *)QSPI)->QSPI_AES_CONFIG) & QSPI_KEY_SIZE_256) + || ((qspi_reg2->QSPI_AES_CONFIG) & QSPI_KEY_SIZE_256)) { + M4_BBFF_STORAGE1 |= KEY_LENGTH; + } + } + M4_BBFF_STORAGE1 &= ~(0xffUL << STACK_AND_CB_ADDR_BIT_NO); + //! Keeping stack address with 2k granularity. + M4_BBFF_STORAGE1 |= (((stack_address >> 11) & 0xFF) << STACK_AND_CB_ADDR_BIT_NO); + + M4_BBFF_STORAGE1 |= STACK_AND_CB_ADDR_PRESENT_IN_BBFF; + } +} +#endif + +/** + * @fn STATIC INLINE void RSI_PS_RetentionSleepConfig(uint32_t stack_address, uint32_t jump_cb_address, uint32_t vector_offset,uint32_t mode) + * @brief This API is used configure the wake up parameter for retention sleep + * @param stack_address : + * @param jump_cb_address : + * @param stack_address : + * @param vector_offset : + * @param mode : Following are the possible parameters for this parameter + * \n \ref RSI_WAKEUP_FROM_FLASH_MODE : Wakes from flash with retention. Upon wake up control jumps to wake up handler in flash. + * In this mode ULPSS RAMs are used to store the stack pointer and wake up handler address. + * \n \ref RSI_WAKEUP_WITH_OUT_RETENTION : Without retention sleep common for both FLASH/RAM based execution. + * In this mode ULPSS RAMs are used to store the stack pointer and control block address. + * if stack_addr and jump_cb_addr are not valid then 0x2404_0C00 and 0x2404_0000 are used + * for stack and control block address respectively. + * + * \n \ref RSI_WAKEUP_WITH_RETENTION : With retention branches to wake up handler in RAM. + * In this mode ULPSS RAMs are used to store the wake up handler address. + * \n \ref RSI_WAKEUP_WITH_RETENTION_WO_ULPSS_RAM : In this mode ULPSS RAMs are not used by boot-loader instead it uses the NPSS battery flip flops. + * \n \ref RSI_WAKEUP_WO_RETENTION_WO_ULPSS_RAM :In this mode ULPSS RAMs are not used by boot-loader. + * Instead it uses the NPSS battery flip flops to store the stack and derives the control block address by adding 0XC00 + * to the stack address stored in battery flops. + * @return none + */ +STATIC INLINE void RSI_PS_RetentionSleepConfig(uint32_t stack_address, + uint32_t jump_cb_address, + uint32_t vector_offset, + uint32_t mode) +{ + +#ifdef SLI_SI917B0 + //!write magic numbers in retention ram content ulp memory start ,end addresses (work around for jtag mode powersave) + RETEN_RAM_CONTENT_START_LOCATION = 0xBEAFBEAF; + RETEN_RAM_CONTENT_END_LOCATION = 0xBEADBEAD; + + //!remove wakeup flash bit in ulpss ram if flash is not required upon wakuep + if (mode == SL_SI91X_MCU_WAKEUP_PSRAM_MODE) { + RETEN_RAM_CONTENT_WAKEUP_FLASH_BIT_LOCATION = 0x0; + } + + if ((mode == RSI_WAKEUP_WITH_RETENTION) || (mode == RSI_WAKEUP_WO_RETENTION_WO_ULPSS_RAM)) { + RSI_PS_RetentionSleepConfig_bypass(stack_address, jump_cb_address, vector_offset, mode); + } else { + ROMAPI_PWR_API->RSI_GotoSleepWithRetention(stack_address, jump_cb_address, vector_offset, mode); + } +#else + ROMAPI_PWR_API->RSI_GotoSleepWithRetention(stack_address, jump_cb_address, vector_offset, mode); +#endif +} + +/** + * @fn STATIC INLINE void RSI_PS_BgLdoConfig(uint8_t ldo_0p6_ctrl, uint8_t ldo_0p6_lp_mode) + * @brief This API is used configure the LP low power mode and vref for DCDC1p1_lp_500uA + * @param ldo_0p6_ctrl : vref for DCDC1p1_lp_500uA + * - 0 - 0.8V + * - 1 - 0.75V + * - 2 - 0.7V + * - 3 - 0.65V + * - 4 - 0.6V + * - 5 - 0.55V + * @param ldo_0p6_lp_mode : 1:enable low power mode, 0:otherwise in high power mode + * @return none + */ +STATIC INLINE void RSI_PS_BgLdoConfig(uint8_t ldo_0p6_ctrl, uint8_t ldo_0p6_lp_mode) +{ +#if defined(CHIP_9118) && defined(A11_ROM) && defined(PS_ROMDRIVER_PRESENT) + ROMAPI_PWR_API->ps_bg_ldo_config(ldo_0p6_ctrl, ldo_0p6_lp_mode); +#else + ps_bg_ldo_config(ldo_0p6_ctrl, ldo_0p6_lp_mode); +#endif +} + +/** + * @fn STATIC INLINE void RSI_PS_ConfigurTrimValues(uint16_t lf_ro_trim ,uint16_t lf_rc_trim , uint16_t hf_ro_trim ,uint16_t hf_rc_trim ,uint16_t bg_ptat_trim , uint16_t bg_trim) + * @brief This API is used configure the clock and bg trim values + * @param[in] lf_ro_trim : trim value for low frequency RO clock + * @param[in] lf_rc_trim : trim value for low frequency RC clock + * @param[in] hf_ro_trim : trim value for high frequency RO clock + * @param[in] hf_rc_trim : trim value for high frequency RC clock + * @param[in] bg_ptat_trim : trim value for bg ptat + * @param[in] bg_trim : trim value for bg(Band Gap) + * @return none + */ +STATIC INLINE void RSI_PS_ConfigurTrimValues(uint16_t lf_ro_trim, + uint16_t lf_rc_trim, + uint16_t hf_ro_trim, + uint16_t hf_rc_trim, + uint16_t bg_ptat_trim, + uint16_t bg_trim) +{ +#if defined(CHIP_9118) && defined(A11_ROM) && defined(PS_ROMDRIVER_PRESENT) + ROMAPI_PWR_API->ps_configure_trim_values(lf_ro_trim, lf_rc_trim, hf_ro_trim, hf_rc_trim, bg_ptat_trim, bg_trim); +#else + ps_configure_trim_values(lf_ro_trim, lf_rc_trim, hf_ro_trim, hf_rc_trim, bg_ptat_trim, bg_trim); +#endif +} + +/** + * @fn STATIC INLINE void RSI_PS_WirelessShutdown(void) + * @brief This API is used shut-down the wireless + * @return none + */ +STATIC INLINE void RSI_PS_WirelessShutdown(void) +{ + // Wireless shutdown should be called only on First/Reset boot + if (MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b.FIRST_BOOTUP_MCU_N_b == 0) { +#if defined(CHIP_9118) && defined(A11_ROM) && defined(PS_ROMDRIVER_PRESENT) + ROMAPI_PWR_API->ps_wireless_shutdown(); +#else + ps_wireless_shutdown(); +#endif + } +} + +/*end of file*/ + +#ifdef __cplusplus +} +#endif + +#endif /*__RSI_ROM_POWER_SAVE_H__*/ + +/* @}end of RSI_POWER_SAVE */ diff --git a/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/inc/rsi_m4.h b/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/inc/rsi_m4.h new file mode 100644 index 000000000..1fe1f9061 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/inc/rsi_m4.h @@ -0,0 +1,223 @@ +/******************************************************************************* +* @file rsi_m4.h +* @brief +******************************************************************************* +* # License +* Copyright 2020 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +#ifndef _RSI_M4_HAL_H_ +#define _RSI_M4_HAL_H_ +#ifdef SLI_SI91X_MCU_INTERFACE + +#include "rsi_pkt_mgmt.h" +#include "sl_device.h" +#include "sl_status.h" + +/****************************************************** + * * Constants + * ******************************************************/ + +#define M4_ISR_IRQ 74 + +#define TA_MEMORY_OFFSET_ADDRESS 0x00400000 +#ifdef SLI_SI917 +#define M4_MEMORY_OFFSET_ADDRESS 0x00500000 +#else +#define M4_MEMORY_OFFSET_ADDRESS 0x00200000 +#endif + +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#ifndef NVIC +#define NVIC ((NVIC_Type *)NVIC_BASE) /*!< NVIC configuration struct */ +#endif + +#define M4SS_P2P_INT_BASE_ADDRESS 0x46008000 +#define MCU_PWR_CTRL_BASE_ADDR 0x24048400 +#define MISC_CFG_HOST_CTRL *(volatile uint32_t *)(M4SS_P2P_INT_BASE_ADDRESS + 0x0C) +#ifndef M4SS_P2P_INTR_SET_REG +#define M4SS_P2P_INTR_SET_REG *(volatile uint32_t *)(M4SS_P2P_INT_BASE_ADDRESS + 0x16C) +#endif +#ifndef M4SS_P2P_INTR_CLR_REG +#define M4SS_P2P_INTR_CLR_REG *(volatile uint32_t *)(M4SS_P2P_INT_BASE_ADDRESS + 0x170) +#endif +#define P2P_STATUS_REG *(volatile uint32_t *)(M4SS_P2P_INT_BASE_ADDRESS + 0x174) +#define TASS_P2P_INTR_MASK_SET *(volatile uint32_t *)(M4SS_P2P_INT_BASE_ADDRESS + 0x178) +#define TASS_P2P_INTR_MASK_CLR *(volatile uint32_t *)(M4SS_P2P_INT_BASE_ADDRESS + 0x17C) +#define TASS_P2P_INTR_CLEAR *(volatile uint32_t *)(M4SS_P2P_INT_BASE_ADDRESS + 0x180) + +#define TASS_P2P_INT_BASE_ADDRESS 0x41050000 + +#define TASS_P2P_INTR_SET_REG *(volatile uint32_t *)(TASS_P2P_INT_BASE_ADDRESS + 0x8C) +#define TASS_P2P_INTR_CLR_REG *(volatile uint32_t *)(TASS_P2P_INT_BASE_ADDRESS + 0x90) + +#define M4_TX_DMA_DESC_REG *(volatile uint32_t *)(TASS_P2P_INT_BASE_ADDRESS + 0x34) +#define M4_RX_DMA_DESC_REG *(volatile uint32_t *)(TASS_P2P_INT_BASE_ADDRESS + 0x5C) +#define HOST_INTR_STATUS_REG *(volatile uint32_t *)(TASS_P2P_INT_BASE_ADDRESS + 0x04) + +#define DMA_DESC_REG_VALID (0xA0 << 8) + +#define TA_wakeup_M4 BIT(2) +#define TA_is_active BIT(3) +#define M4_wakeup_TA BIT(0) +#define M4_is_active BIT(1) + +#define ARM_MASK_1 0xE000E100 +#define ARM_MASK_1 0xE000E100 +#define ARM_MASK_1 0xE000E100 + +#ifndef BIT +#define BIT(x) (1 << (x)) +#endif + +//! This interrupt is raised by M4 to TA when there is a TX packet from M4 to read +#define RX_BUFFER_VALID BIT(1) +#define TX_PKT_PENDING_INTERRUPT BIT(2) +#define UPGRADE_M4_IMAGE BIT(5) +#ifdef SLI_SI917 +#define M4_WAITING_FOR_TA_TO_WR_ON_FLASH BIT(6) +#endif +#ifdef SL_SI91X_SIDE_BAND_CRYPTO +#define SIDE_BAND_CRYPTO_INTR BIT(7) +#endif +#define M4_WAITING_FOR_TA_DEINIT BIT(8) + +#define TX_PKT_TRANSFER_DONE_INTERRUPT BIT(2) +//! This interrupt is received from TA when RX packet is pending from TA +#define RX_PKT_TRANSFER_DONE_INTERRUPT BIT(1) +//! This interrupt is received from TA when TX packet transfer from M4 to TA is done + +#define M4_IMAGE_UPGRADATION_PENDING_INTERRUPT BIT(4) +//! This interrupt is raised by TA to M4 when there is a TX packet from M4 to read + +#ifdef SLI_SI917 +//! This interrupt is raised by TA to M4 when there is a flash write request from M4 to TA in common flash mode +#define TA_WRITING_ON_COMM_FLASH BIT(5) +#endif + +#ifdef SL_SI91X_SIDE_BAND_CRYPTO +#define SIDE_BAND_CRYPTO_DONE BIT(6) +#endif +#define NWP_DEINIT_IN_COMM_FLASH BIT(7) + +#ifdef SLI_SI917 +//! Option value for m4 app from flash to ram API +#define UPGRADE_M4_IMAGE_OTA 1 +#define TA_WRITES_ON_COMM_FLASH 2 +#define M4_WAIT_FOR_NWP_DEINIT 3 +#endif + +#ifdef SLI_SI91X_ENABLE_OS +#define TASS_P2P_INTR_PRI 5 +#define SYSTICK_INTR_PRI 7 +#else +#define TASS_P2P_INTR_PRI 5 +#define SYSTICK_INTR_PRI (1 << __NVIC_PRIO_BITS) - 1 +#endif +/****************************************************** + * * Enumerations + * ******************************************************/ + +/****************************************************** + * * Type Definitions + * ******************************************************/ +typedef struct rsi_m4ta_desc_dword1_s { + //! Reserved + uint32_t reserved : 15; + + //! 1 bit : indicates the presence of more descriptors + //! 1 - last descriptor + //! 0 - more descriptors are present + uint32_t last_desc : 1; + + //! Buffer queue_no to be transfered for this descriptor + uint32_t queue_no : 4; + + //! Buffer length to be transfered for this descriptor + uint32_t length : 12; + +} rsi_m4ta_desc_dword1_t; + +typedef struct rsi_m4ta_desc_s { + //! source address + uint32_t addr; + + uint16_t length; + //! descriptor control fields + //rsi_m4ta_desc_dword1_t dword1; + +} rsi_m4ta_desc_t; + +//! host descriptor structure +typedef struct rsi_frame_desc_s { + //! Data frame body length. Bits 14:12=queue, 000 for data, Bits 11:0 are the length + uint8_t frame_len_queue_no[2]; + //! Frame type + uint8_t frame_type; + //! Unused , set to 0x00 + uint8_t reserved[9]; + //! Management frame descriptor response status, 0x00=success, else error + uint8_t status; + uint8_t reserved1[3]; +} rsi_frame_desc_t; + +//! P2P registers Backup structure +typedef struct rsi_p2p_intr_status_bkp_s { + uint32_t tass_p2p_intr_mask_clr_bkp; + uint32_t m4ss_p2p_intr_set_reg_bkp; +} rsi_p2p_intr_status_bkp_t; + +/****************************************************** + * * Structures + * ******************************************************/ + +/****************************************************** + * * Global Variables + * ******************************************************/ +/****************************************************** + * * Function Declarations + * ******************************************************/ +int16_t rsi_frame_write(rsi_frame_desc_t *uFrameDscFrame, uint8_t *payloadparam, uint16_t size_param); +rsi_pkt_t *rsi_frame_read(void); +int16_t rsi_device_interrupt_status(uint8_t *int_status); + +sl_status_t sli_m4_interrupt_isr(void); +void sli_m4_ta_interrupt_init(void); +void sli_si91x_raise_pkt_pending_interrupt_to_ta(void); +#ifdef SL_SI91X_SIDE_BAND_CRYPTO +void sli_si91x_raise_side_band_interrupt_to_ta(void); +#endif +int32_t rsi_send_pkt_to_ta(rsi_m4ta_desc_t *tx_desc); +void rsi_transfer_to_ta_done_isr(void); +void rsi_pkt_pending_from_ta_isr(void); +sl_status_t sli_receive_from_ta_done_isr(void); +int16_t rsi_device_buffer_full_status(void); +int rsi_submit_rx_pkt(void); +void unmask_ta_interrupt(uint32_t interrupt_no); +void mask_ta_interrupt(uint32_t interrupt_no); +void raise_m4_to_ta_interrupt(uint32_t interrupt_no); +void clear_m4_to_ta_interrupt(uint32_t interrupt_no); +void clear_ta_interrupt_mask(void); +void set_ta_interrupt_mask(void); +void clear_ta_to_m4_interrupt(uint32_t interrupt_no); +void sl_mv_m4_app_from_flash_to_ram(int option); +uint32_t NVIC_GetIRQEnable(IRQn_Type IRQn); +void sli_si91x_config_m4_dma_desc_on_reset(void); +void rsi_update_tx_dma_desc(uint8_t skip_dma_valid); +void rsi_update_rx_dma_desc(void); +sl_status_t si91x_req_wakeup(void); +void sl_si91x_ta_events_init(void); /*Function used to create and initialize event mechanism for TA related events */ + +#endif +#endif diff --git a/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/inc/rsi_os.h b/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/inc/rsi_os.h new file mode 100644 index 000000000..319af9f64 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/inc/rsi_os.h @@ -0,0 +1,130 @@ +/******************************************************************************* +* @file rsi_os.h +* @brief +******************************************************************************* +* # License +* Copyright 2020 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +#ifndef RSI_OS_H +#define RSI_OS_H + +#include "rsi_error.h" +#include +/****************************************************** + * * Macros + * ******************************************************/ +// Macro to increment a value +#define RSI_ATOMIC_INCREMENT(value) \ + { \ + (value)++; \ + } + +// Macro to decrement a value +#define RSI_ATOMIC_DECREMENT(value) \ + { \ + (value)--; \ + } +// Error none (success) +#define RSI_ERR_NONE (0) + +// Error returned when invalid arguments are given +#define RSI_ERR_INVALID_ARGS (1) + +// Error returned when timeout error occurs +#define RSI_ERR_TIMEOUT (3) + +// Mutex unlock value +#define RSI_NO_OS_MUTEX_UNLOCKED (0) + +// Mutex lock value +#define RSI_NO_OS_MUTEX_LOCKED (1) + +// Macro to set the mutex lock +#define RSI_NO_OS_ATOMIC_MUTEX_SET(mutex, value) (mutex) = value + +// Macro for checking whether mutex is locked or not +#define RSI_NO_OS_ATOMIC_MUTEX_CHECK(mutex, value) (((mutex) == value) ? 1 : 0) +/****************************************************** + * * Constants + * ******************************************************/ +/****************************************************** + * * Enumerations + * ******************************************************/ +/****************************************************** + * * Type Definitions + * ******************************************************/ +typedef uint32_t rsi_reg_flags_t; +// Handle to manage Semaphores. +typedef uint32_t rsi_semaphore_handle_t; +// Handle to manage Mutex. +typedef uint32_t rsi_mutex_handle_t; + +// Task handler +typedef void *rsi_task_handle_t; + +typedef long rsi_base_type_t; +// Task function +typedef void (*rsi_task_function_t)(void *function); +/****************************************************** + * * Structures + * ******************************************************/ +/****************************************************** + * * Global Variables + * ******************************************************/ +/****************************************************** + * * Function Declarations + * ******************************************************/ +/* --------- CRITICAL SECTION FUNCTIONS --------- */ +rsi_reg_flags_t rsi_critical_section_entry(void); +void rsi_critical_section_exit(rsi_reg_flags_t flags); +/* -------------- MUTEX FUNCTIONS -------------- */ +rsi_error_t rsi_mutex_create(rsi_mutex_handle_t *p_mutex); +rsi_error_t rsi_mutex_lock(volatile rsi_mutex_handle_t *p_mutex); +void rsi_mutex_lock_from_isr(volatile rsi_mutex_handle_t *mutex); +rsi_error_t rsi_mutex_unlock(volatile rsi_mutex_handle_t *p_mutex); +void rsi_mutex_unlock_from_isr(volatile rsi_mutex_handle_t *mutex); +rsi_error_t rsi_mutex_destroy(rsi_mutex_handle_t *p_mutex); + +/* ------------- SEMAPHORE FUNCTIONS ----------- */ +rsi_error_t rsi_semaphore_create(rsi_semaphore_handle_t *p_sem, uint32_t cnt); +rsi_error_t rsi_semaphore_destroy(rsi_semaphore_handle_t *p_sem); +rsi_error_t rsi_semaphore_check_and_destroy(rsi_semaphore_handle_t *p_sem); +rsi_error_t rsi_semaphore_wait(rsi_semaphore_handle_t *p_sem, uint32_t timeout); +rsi_error_t rsi_semaphore_post(rsi_semaphore_handle_t *p_sem); +rsi_error_t rsi_semaphore_post_from_isr(rsi_semaphore_handle_t *semaphore); +rsi_error_t rsi_semaphore_reset(rsi_semaphore_handle_t *p_sem); + +/* ------------- TASK FUNCTIONS ----------- */ +rsi_error_t rsi_task_create(rsi_task_function_t task_function, + uint8_t *task_name, + uint32_t stack_size, + void *parameters, + uint32_t task_priority, + rsi_task_handle_t *task_handle); + +void rsi_task_destroy(rsi_task_handle_t *task_handle); +void rsi_task_delete(rsi_task_handle_t *task_handle); +void rsi_os_task_delay(uint32_t timeout_ms); +void rsi_task_suspend(rsi_task_handle_t *task_handle); +void rsi_start_os_scheduler(void); +void rsi_wireless_driver_task_create(void); +/* ---------- OS MEMORY MAPPING FUNCTIONS -------- */ +void *rsi_virtual_to_physical_address(void *x); +void *rsi_physical_to_virtual_address(void *x); +void *rsi_malloc(uint32_t size); +void rsi_free(void *p); +void rsi_vport_enter_critical(void); +void rsi_vport_exit_critical(void); +int32_t rsi_get_error(int32_t sockID); +void rsi_set_os_errno(int32_t error); +#endif diff --git a/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/inc/rsi_pkt_mgmt.h b/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/inc/rsi_pkt_mgmt.h new file mode 100644 index 000000000..2dfbd37d7 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/inc/rsi_pkt_mgmt.h @@ -0,0 +1,84 @@ +/******************************************************************************* +* @file rsi_pkt_mgmt.h +* @brief +******************************************************************************* +* # License +* Copyright 2020 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +#ifndef RSI_PKT_MGMT_H +#define RSI_PKT_MGMT_H + +#include "rsi_os.h" +#include +#if ((defined RSI_SDIO_INTERFACE) && (defined SLI_SI917)) +#define SIZE_OF_HEADROOM 216 +#else +#define SIZE_OF_HEADROOM 0 +#endif +/****************************************************** + * * Macros + * ******************************************************/ +/****************************************************** + * * Constants + * ******************************************************/ +/****************************************************** + * * Enumerations + * ******************************************************/ +/****************************************************** + * * Type Definitions + * ******************************************************/ +// driver TX/RX packet structure +typedef struct rsi_pkt_s { + // next packet pointer + struct rsi_pkt_s *next; + +#if ((defined RSI_SDIO_INTERFACE) && (defined SLI_SI917)) + uint8_t headroom[SIZE_OF_HEADROOM]; +#endif + + // host descriptor + uint8_t desc[16]; + + // payload + uint8_t data[1]; +} rsi_pkt_t; + +// packet pool structure +typedef struct rsi_pkt_pool_s { + // Pool total packets count + uint16_t size; + + // Pool avaialble packets count + uint16_t avail; + + // Pool pointer + void **pool; + + rsi_semaphore_handle_t pkt_sem; + +} rsi_pkt_pool_t; + +/****************************************************** + * * Structures + * ******************************************************/ +/****************************************************** + * * Global Variables + * ******************************************************/ +/****************************************************** + * * Function Declarations + * ******************************************************/ +int32_t rsi_pkt_pool_init(rsi_pkt_pool_t *pool_cb, uint8_t *buffer, uint32_t total_size, uint32_t pkt_size); +rsi_pkt_t *rsi_pkt_alloc(rsi_pkt_pool_t *pool_cb); +int32_t rsi_pkt_free(rsi_pkt_pool_t *pool_cb, rsi_pkt_t *pkt); +uint32_t rsi_is_pkt_available(rsi_pkt_pool_t *pool_cb); +#endif diff --git a/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/inc/rsi_wisemcu_hardware_setup.h b/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/inc/rsi_wisemcu_hardware_setup.h new file mode 100644 index 000000000..1659afe34 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/inc/rsi_wisemcu_hardware_setup.h @@ -0,0 +1,111 @@ +/******************************************************************************* +* @file rsi_wisemcu_hardware_setup.h +* @brief +******************************************************************************* +* # License +* Copyright 2020 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +#ifndef __RSI_HW_SETUP_H__ +#define __RSI_HW_SETUP_H__ +/*Includes*/ + +// +#include "rsi_power_save.h" +#include "base_types.h" + +/*Configure the PMU and XTAL good times */ +#define PMU_GOOD_TIME 31 /*Duration in us*/ +#define XTAL_GOOD_TIME 31 /*Duration in us*/ + +#ifdef SLI_SI91X_MCU_COMMON_FLASH_MODE +#define NWPAON_MEM_HOST_ACCESS_CTRL_SET_1 (*(volatile uint32_t *)(0x41300000 + 0x0)) +#define NWPAON_MEM_HOST_ACCESS_CTRL_CLEAR_1 (*(volatile uint32_t *)(0x41300000 + 0x4)) +#define M4SS_TASS_CTRL_SET_REG (*(volatile uint32_t *)(0x24048400 + 0x34)) +#define M4SS_TASS_CTRL_CLR_REG (*(volatile uint32_t *)(0x24048400 + 0x38)) +#define M4SS_REF_CLK_MUX_CTRL BIT(24) +#define TASS_REF_CLK_MUX_CTRL BIT(25) +#define M4SS_CTRL_TASS_AON_PWR_DMN_RST_BYPASS BIT(2) +#endif + +#ifdef CHIP_9118 +/*Macro to be used for configuring the 'rams_in_use' parameter in 'sl_si91x_configure_ram_retention()' function*/ +#define WISEMCU_0KB_RAM_IN_USE \ + (RAM_BANK_0 | RAM_BANK_1 | RAM_BANK_2 | RAM_BANK_3 | RAM_BANK_4 | RAM_BANK_5 | RAM_BANK_6 | RAM_BANK_7 | RAM_BANK_8 \ + | RAM_BANK_9 | RAM_BANK_10 | RAM_BANK_11 | RAM_BANK_12 | RAM_BANK_13) +#define WISEMCU_16KB_RAM_IN_USE \ + (RAM_BANK_0 | RAM_BANK_1 | RAM_BANK_2 | RAM_BANK_7 | RAM_BANK_8 | RAM_BANK_9 | RAM_BANK_10 | RAM_BANK_11 \ + | RAM_BANK_12 | RAM_BANK_13) +#define WISEMCU_48KB_RAM_IN_USE \ + (RAM_BANK_0 | RAM_BANK_1 | RAM_BANK_2 | RAM_BANK_8 | RAM_BANK_9 | RAM_BANK_10 | RAM_BANK_11 | RAM_BANK_12 \ + | RAM_BANK_13) +#define WISEMCU_112KB_RAM_IN_USE \ + (RAM_BANK_0 | RAM_BANK_1 | RAM_BANK_2 | RAM_BANK_9 | RAM_BANK_10 | RAM_BANK_11 | RAM_BANK_12 | RAM_BANK_13) +#define WISEMCU_128KB_RAM_IN_USE \ + (RAM_BANK_0 | RAM_BANK_1 | RAM_BANK_2 | RAM_BANK_10 | RAM_BANK_11 | RAM_BANK_12 | RAM_BANK_13) +#define WISEMCU_144KB_RAM_IN_USE (RAM_BANK_1 | RAM_BANK_2 | RAM_BANK_10 | RAM_BANK_11 | RAM_BANK_12 | RAM_BANK_13) +#define WISEMCU_176KB_RAM_IN_USE (RAM_BANK_2 | RAM_BANK_10 | RAM_BANK_11 | RAM_BANK_12 | RAM_BANK_13) +#define WISEMCU_192KB_RAM_IN_USE (RAM_BANK_10 | RAM_BANK_11 | RAM_BANK_12 | RAM_BANK_13) +#define WISEMCU_208KB_RAM_IN_USE (RAM_BANK_11 | RAM_BANK_12 | RAM_BANK_13) +#define WISEMCU_240KB_RAM_IN_USE (RAM_BANK_12 | RAM_BANK_13) +#define WISEMCU_320KB_RAM_IN_USE (RAM_BANK_13) +#define WISEMCU_384KB_RAM_IN_USE (0) +#endif + +#ifdef SLI_SI917 +/*Macro to be used for configuring the 'rams_in_use' parameter in 'sl_si91x_configure_ram_retention()' function*/ +#define WISEMCU_0KB_RAM_IN_USE \ + (RAM_BANK_0 | RAM_BANK_1 | RAM_BANK_2 | RAM_BANK_3 | RAM_BANK_4 | RAM_BANK_5 | RAM_BANK_6 | RAM_BANK_7 | RAM_BANK_8 \ + | RAM_BANK_9) +#define WISEMCU_16KB_RAM_IN_USE (RAM_BANK_4 | RAM_BANK_5 | RAM_BANK_6 | RAM_BANK_7 | RAM_BANK_8 | RAM_BANK_9) +#define WISEMCU_64KB_RAM_IN_USE (RAM_BANK_6 | RAM_BANK_7 | RAM_BANK_8 | RAM_BANK_9) +#define WISEMCU_128KB_RAM_IN_USE (RAM_BANK_7 | RAM_BANK_8 | RAM_BANK_9) +#define WISEMCU_192KB_RAM_IN_USE (RAM_BANK_8 | RAM_BANK_9) +#define WISEMCU_256KB_RAM_IN_USE (RAM_BANK_9) +#define WISEMCU_320KB_RAM_IN_USE (0U) + +/*Macros are used for antenna front switch-end controls */ +#define FRONT_END_SWITCH_SEL0 0 +#define FRONT_END_SWITCH_SEL1 BIT(29) +#define FRONT_END_SWITCH_SEL2 BIT(30) +#define FRONT_END_SWITCH_SEL3 (BIT(29) | BIT(30)) +void RSI_Wireless_GPIO_Frontend_Switch_Controls(void); +#endif +/*Macro used to define the PTE CRC value of the Firmware 17 Boards*/ +#define FIRMWARE_17_PTE_CRC_VALUE 0 + +/*Macro to be used for configuring the 'rams_retention_during_sleep' parameter in 'sl_si91x_configure_ram_retention()' function*/ +#define WISEMCU_RETAIN_DEFAULT_RAM_DURING_SLEEP (1) +#define WISEMCU_RETAIN_16K_RAM_DURING_SLEEP (M4ULP_RAM16K_RETENTION_MODE_EN) +#define WISEMCU_RETAIN_128K_RAM_DURING_SLEEP (M4ULP_RAM16K_RETENTION_MODE_EN | M4ULP_RAM_RETENTION_MODE_EN) +#define WISEMCU_RETAIN_192K_RAM_DURING_SLEEP \ + (M4ULP_RAM16K_RETENTION_MODE_EN | M4ULP_RAM_RETENTION_MODE_EN | M4SS_RAM_RETENTION_MODE_EN) +#define WISEMCU_RETAIN_384K_RAM_DURING_SLEEP \ + (M4ULP_RAM16K_RETENTION_MODE_EN | M4ULP_RAM_RETENTION_MODE_EN | M4SS_RAM_RETENTION_MODE_EN | TA_RAM_RETENTION_MODE_EN) +#define WISEMCU_RETAIN_M4SS_RAM_DURING_SLEEP (M4SS_RAM_RETENTION_MODE_EN) +#define WISEMCU_RETAIN_ULPSS_RAM_DURING_SLEEP (ULPSS_RAM_RETENTION_MODE_EN) +#define WISEMCU_RETAIN_TASS_RAM_DURING_SLEEP (TA_RAM_RETENTION_MODE_EN) +#define WISEMCU_RETAIN_M4ULP_RAM_DURING_SLEEP (M4ULP_RAM_RETENTION_MODE_EN) + +/*Function proto-types*/ +void sli_si91x_configure_wireless_frontend_controls(uint32_t switch_sel); +void sl_si91x_hardware_setup(void); +void sl_si91x_trigger_sleep(SLEEP_TYPE_T sleepType, + uint8_t lf_clk_mode, + uint32_t stack_address, + uint32_t jump_cb_address, + uint32_t vector_offset, + uint32_t mode); +void sl_si91x_configure_ram_retention(uint32_t rams_in_use, uint32_t rams_retention_during_sleep); + +/*End of file not truncated*/ +#endif \ No newline at end of file diff --git a/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/inc/sl_device.h b/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/inc/sl_device.h new file mode 100644 index 000000000..680ae44f2 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/inc/sl_device.h @@ -0,0 +1,21 @@ +/******************************************************************************* +* @file sl_device.h +* @brief +******************************************************************************* +* # License +* Copyright 2023 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +#pragma once + +#include "si91x_device.h" +#include "rsi_m4.h" diff --git a/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/inc/sli_siwx917_soc.h b/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/inc/sli_siwx917_soc.h new file mode 100644 index 000000000..b695f99cb --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/inc/sli_siwx917_soc.h @@ -0,0 +1,72 @@ +/******************************************************************************* +* @file sli_siwx917_soc.h +* @brief +******************************************************************************* +* # License +* Copyright 2023 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +#pragma once + +#include + +// Upgrade images +#define RSI_JUMP_TO_PC 'J' + +//! Check CRC +#define CHECK_NWP_INTEGRITY 'K' +#define RSI_UPGRADE_BL '#' + +#define HOST_INTF_REG_OUT 0x4105003C +#define HOST_INTF_REG_IN 0x41050034 +#define BOARD_READY 0xABCD +#define REG_READ 0xD1 +#define REG_WRITE 0xD2 +#define PONG_WRITE 0xD4 +#define PING_WRITE 0xD5 +#define GPIO_RESET 0xD7 +#define LOAD_BOOTLOADER 0xD8 +#ifdef RS9116 +#define HOST_INTERACT_REG_VALID (0xA0 << 8) +#define HOST_INTERACT_REG_VALID_READ (0xAB << 8) +#else +#define HOST_INTERACT_REG_VALID (0xAB << 8) +#define HOST_INTERACT_REG_VALID_READ (0xAB << 8) +#endif + +#define RSI_RESET_LOOP_COUNTER(X) X = 0; +#define RSI_WHILE_LOOP(X, Y) while ((X++) < (uint32_t)Y) +#define RSI_LOOP_COUNT_UPGRADE_IMAGE 0xFFFF +#define RSI_LOOP_COUNT_WAKEUP_REQ 0xFFFFFFFF +#define RSI_LOOP_COUNT_WAKEUP_WAIT 0xFFFFFFFF +#define RSI_LOOP_COUNT_UPGRADE_REQ 0xFFFF +#define RSI_LOOP_COUNT_UPGRADE_CHUNK 0xFFFF +#define RSI_LOOP_COUNT_UPGRADE_STATUS 0xFFFF +#define RSI_LOOP_COUNT_SELECT_OPTION 0xFFFF +#define RSI_CHECK_LOOP_COUNTER(X, Y) \ + { \ + if (X >= Y) \ + return -1; \ + } + +void sli_siwx917_update_system_core_clock(void); +void RSI_Set_Cntrls_To_M4(void); +void RSI_Set_Cntrls_To_TA(void); + +void sli_si91x_platform_init(void); +int16_t sli_si91x_send_boot_instruction(uint8_t type, uint16_t *data); +int16_t rsi_waitfor_boardready(void); +int16_t rsi_select_option(uint8_t cmd); +int16_t rsi_bl_select_option(uint8_t cmd); +int16_t rsi_boot_insn(uint8_t type, uint16_t *data); +int16_t rsi_mem_rd(uint32_t addr, uint16_t len, uint8_t *dBuf); +void sl_si91x_ulp_wakeup_init(void); \ No newline at end of file diff --git a/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/inc/sli_siwx917_timer.h b/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/inc/sli_siwx917_timer.h new file mode 100644 index 000000000..d679a8e2d --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/inc/sli_siwx917_timer.h @@ -0,0 +1,45 @@ +/******************************************************************************* +* @file sli_siwx917_timer.h +* @brief +******************************************************************************* +* # License +* Copyright 2023 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +#pragma once + +#include + +/****************************************************** + * * Macros + * ******************************************************/ +#define sl_si91x_timer_NODE_0 0 + +/****************************************************** + * * Type Definitions + * ******************************************************/ + +typedef struct { + uint32_t start_time; + uint32_t timeout; +} sl_si91x_timer_t; + +/****************************************************** + * * Function Declarations + * ******************************************************/ +void sl_si91x_timer_expiry_interrupt_handler(void); +uint32_t sl_si91x_timer_read_counter(void); +void sl_si91x_timer_init(sl_si91x_timer_t *timer, uint32_t duration); +int32_t sl_si91x_timer_expired(sl_si91x_timer_t *timer); +uint32_t sl_si91x_timer_left(sl_si91x_timer_t *timer); + +uint32_t rsi_hal_gettickcount(void); diff --git a/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/src/rsi_hal_mcu_m4_ram.c b/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/src/rsi_hal_mcu_m4_ram.c new file mode 100644 index 000000000..0e3f705df --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/src/rsi_hal_mcu_m4_ram.c @@ -0,0 +1,63 @@ +/******************************************************************************* +* @file rsi_hal_mcu_m4_ram.c +* @brief +******************************************************************************* +* # License +* Copyright 2020 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +#ifdef SLI_SI917 +//! This file should be in RAM +#include "sl_device.h" + +/*==================================================*/ +/** + * @fn void sl_mv_m4_app_from_flash_to_ram(int option) + * @brief Raise interrupt to TA and poll for task done + * @param[in] option + * @param[out] none + */ + +void sl_mv_m4_app_from_flash_to_ram(int option) +{ + + //! Disable all interrupts + __disable_irq(); + + if (option == UPGRADE_M4_IMAGE_OTA) { + //! Raise interrupt to TA + raise_m4_to_ta_interrupt(UPGRADE_M4_IMAGE); + + //! Poll for bit to clear + while ((M4SS_P2P_INTR_CLR_REG & UPGRADE_M4_IMAGE)) + ; + } else if (option == TA_WRITES_ON_COMM_FLASH) { + //! Raise interrupt to TA + raise_m4_to_ta_interrupt(M4_WAITING_FOR_TA_TO_WR_ON_FLASH); + + //! Poll for bit to clear + while (M4SS_P2P_INTR_CLR_REG & M4_WAITING_FOR_TA_TO_WR_ON_FLASH) + ; + } else if (option == M4_WAIT_FOR_NWP_DEINIT) { + //! Raise interrupt to TA + raise_m4_to_ta_interrupt(M4_WAITING_FOR_TA_DEINIT); + + //! Poll for bit to clear + while (M4SS_P2P_INTR_CLR_REG & M4_WAITING_FOR_TA_DEINIT) + ; + } + + //! Enable all interrupts + __enable_irq(); +} + +#endif diff --git a/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/src/rsi_hal_mcu_m4_rom.c b/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/src/rsi_hal_mcu_m4_rom.c new file mode 100644 index 000000000..bce91947b --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/src/rsi_hal_mcu_m4_rom.c @@ -0,0 +1,226 @@ +/******************************************************************************* +* @file rsi_hal_mcu_m4_rom.c +* @brief +******************************************************************************* +* # License +* Copyright 2024 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +#include "sl_si91x_types.h" +#include "sl_constants.h" +#include "sl_status.h" +#include "sl_device.h" +#include "sl_rsi_utility.h" +#include "rsi_m4.h" + +#ifdef SL_WIFI_COMPONENT_INCLUDED +#include "sl_si91x_host_interface.h" +#endif + +#include "cmsis_os2.h" +osEventFlagsId_t ta_events = NULL; +#define TA_PKT_TX_DONE (1 << 1) +#ifdef SL_SI91X_SIDE_BAND_CRYPTO +#define SIDE_BAND_DONE (1 << 2) +#endif + +/** @addtogroup SOC4 +* @{ +*/ +/** + * @fn void sli_si91x_raise_pkt_pending_interrupt_to_ta(void) + * @brief Raise the packet pending interrupt to TA + * @param[in] void + * @return void + */ +void sli_si91x_raise_pkt_pending_interrupt_to_ta(void) +{ + // Write the packet pending interrupt to TA register + M4SS_P2P_INTR_SET_REG = TX_PKT_PENDING_INTERRUPT; + osEventFlagsWait(ta_events, TA_PKT_TX_DONE, (osFlagsWaitAny), osWaitForever); +} + +#ifdef SL_SI91X_SIDE_BAND_CRYPTO +/** + * @fn void sli_si91x_raise_side_band_interrupt_to_ta(void) + * @brief Raise the side band interrupt to TA + * @param[in] void + * @return void + */ +void sli_si91x_raise_side_band_interrupt_to_ta(void) +{ + // Write the packet pending interrupt to TA register + M4SS_P2P_INTR_SET_REG = SIDE_BAND_CRYPTO_INTR; +} +#endif + +/** + * @fn void raise_m4_to_ta_interrupt(uint32_t interrupt_no) + * @brief Set interrupt. + * @param[in] interrupt_no - Process of a interrupt number + * @return void + */ + +void raise_m4_to_ta_interrupt(uint32_t interrupt_no) +{ + M4SS_P2P_INTR_SET_REG = interrupt_no; +} + +/** + * @fn void mask_ta_interrupt(uint32_t interrupt_no) + * @brief Process a interrupt mask. + * @param[in] void + * @return void + */ +void mask_ta_interrupt(uint32_t interrupt_no) +{ + TASS_P2P_INTR_MASK_SET = interrupt_no; +} + +/** + * @fn void clear_ta_to_m4_interrupt(uint32_t interrupt_no) + * @brief Clear interrupt raised by TA. + * @param[in] interrupt_no - Process of a interrupt number + * @return void + */ +void clear_ta_to_m4_interrupt(uint32_t interrupt_no) +{ + TASS_P2P_INTR_CLEAR = interrupt_no; + TASS_P2P_INTR_CLR_REG = interrupt_no; +} + +/** + * @fn void sli_m4_interrupt_isr(void) + * @brief Raise the packet pending interrupt to TA + * @param[in] void + * @return void + */ + +sl_status_t sli_m4_interrupt_isr(void) +{ + if (TASS_P2P_INTR_CLEAR & TX_PKT_TRANSFER_DONE_INTERRUPT) { + + osEventFlagsSet(ta_events, TA_PKT_TX_DONE); + // Clear the interrupt + clear_ta_to_m4_interrupt(TX_PKT_TRANSFER_DONE_INTERRUPT); + + } else if (TASS_P2P_INTR_CLEAR & RX_PKT_TRANSFER_DONE_INTERRUPT) { + + // Call done interrupt isr + sl_status_t status = sli_receive_from_ta_done_isr(); + VERIFY_STATUS_AND_RETURN(status); + + // Clear the interrupt + clear_ta_to_m4_interrupt(RX_PKT_TRANSFER_DONE_INTERRUPT); + + } +#ifdef SLI_SI917 + else if (TASS_P2P_INTR_CLEAR & TA_WRITING_ON_COMM_FLASH) { + //! moves m4 app to RAM and polls for TA done + sl_mv_m4_app_from_flash_to_ram(TA_WRITES_ON_COMM_FLASH); + // Clear the interrupt + clear_ta_to_m4_interrupt(TA_WRITING_ON_COMM_FLASH); + } else if (TASS_P2P_INTR_CLEAR & NWP_DEINIT_IN_COMM_FLASH) { + //! moves m4 app to RAM and polls for TA done + sl_mv_m4_app_from_flash_to_ram(M4_WAIT_FOR_NWP_DEINIT); + // Clear the interrupt + clear_ta_to_m4_interrupt(NWP_DEINIT_IN_COMM_FLASH); + } + //! Below changes are requried for M4 Image upgration in dual flash config + else if (TASS_P2P_INTR_CLEAR & M4_IMAGE_UPGRADATION_PENDING_INTERRUPT) { + //! moves m4 app to RAM and polls for TA done + sl_mv_m4_app_from_flash_to_ram(UPGRADE_M4_IMAGE_OTA); + // Clear the interrupt + clear_ta_to_m4_interrupt(M4_IMAGE_UPGRADATION_PENDING_INTERRUPT); + } +#endif +#ifdef SL_SI91X_SIDE_BAND_CRYPTO + //! Below changes are requried for SIDE BAND CRYPTO + else if (TASS_P2P_INTR_CLEAR & SIDE_BAND_CRYPTO_DONE) { + osEventFlagsSet(ta_events, SIDE_BAND_DONE); + // Clear the interrupt + clear_ta_to_m4_interrupt(SIDE_BAND_CRYPTO_DONE); + } +#endif + else { + SL_DEBUG_LOG("\r\n INVALID INTERRUPT \r\n", 0); + BREAKPOINT(); + } + return SL_STATUS_OK; +} + +/** + * @fn sl_status_t sli_receive_from_ta_done_isr(void) + * @brief Called when DMA done for RX packet is received + * @param[in] global_cb_p - pointer to the global control block + * @return void + */ +sl_status_t sli_receive_from_ta_done_isr(void) +{ +#ifdef SL_WIFI_COMPONENT_INCLUDED + extern sl_wifi_buffer_t *rx_pkt_buffer; + // Add to rx packet to CCP queue + sl_status_t status = sl_si91x_host_add_to_queue(CCP_M4_TA_RX_QUEUE, rx_pkt_buffer); + VERIFY_STATUS_AND_RETURN(status); + + //! Set event RX pending event to host + sl_si91x_host_set_bus_event(SL_SI91X_NCP_HOST_BUS_RX_EVENT); +#endif + + return SL_STATUS_OK; +} + +/*==================================================*/ +/** + * @fn sl_status_t sl_si91x_bus_read_interrupt_status(uint8_t *int_status) + * @brief Returns the value of the Interrupt register + * @param[in] status + * @param[out] buffer full status reg value + * @return errorcode + * 0 = Success + * -2 = Reg read failure + */ +sl_status_t sl_si91x_bus_read_interrupt_status(uint16_t *int_status) +{ + *int_status = (uint8_t)HOST_INTR_STATUS_REG; + + return RSI_SUCCESS; +} + +sl_status_t si91x_req_wakeup(void) +{ + P2P_STATUS_REG |= M4_wakeup_TA; + if (!(P2P_STATUS_REG & TA_is_active)) { + //!TBD Need add timeout + while (!(P2P_STATUS_REG & TA_is_active)) + ; + } + return SL_STATUS_OK; +} + +void sl_si91x_host_clear_sleep_indicator(void) +{ + P2P_STATUS_REG &= ~M4_wakeup_TA; +} + +void IRQ074_Handler(void) +{ + sli_m4_interrupt_isr(); +} + +void sl_si91x_ta_events_init(void) +{ + if (ta_events == NULL) { + ta_events = osEventFlagsNew(NULL); + } +} +/** @} */ \ No newline at end of file diff --git a/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/src/sl_platform.c b/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/src/sl_platform.c new file mode 100644 index 000000000..de1f6990b --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/src/sl_platform.c @@ -0,0 +1,106 @@ +/******************************************************************************* +* @file sl_platform.c +* @brief +******************************************************************************* +* # License +* Copyright 2020 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ +#include "sli_siwx917_soc.h" +#include "sl_device.h" +#include "sl_si91x_constants.h" +#include "sl_si91x_status.h" +#include "sl_si91x_core_utilities.h" +#include "sl_status.h" +#include "sl_constants.h" +#include +#include "sl_board_configuration.h" + +#if defined(SL_CATALOG_KERNEL_PRESENT) +#include "cmsis_os2.h" +#include "FreeRTOSConfig.h" +#endif +sl_status_t sli_si91x_submit_rx_pkt(void); +void sl_board_enable_vcom(void); +sl_status_t si91x_bootup_firmware(const uint8_t select_option); + +void sli_si91x_platform_init(void) +{ +#ifdef SLI_SI91X_MCU_COMMON_FLASH_MODE + /* Before TA going to power save mode ,set m4ss_ref_clk_mux_ctrl ,tass_ref_clk_mux_ctrl, + AON domain power supply controls form TA to M4 */ + RSI_Set_Cntrls_To_M4(); +#endif + + // Enable DWT and cycle counting + CoreDebug->DEMCR |= 0x01000000; + DWT->CTRL |= 0x1; + +#if (configUSE_TICKLESS_IDLE == 0) + SysTick_Config(SystemCoreClock / configTICK_RATE_HZ); + // Set P2P Intr priority + NVIC_SetPriority(SysTick_IRQn, SYSTICK_INTR_PRI); +#endif +} + +void sl_board_enable_vcom(void) +{ +} + +sl_status_t si91x_bootup_firmware(const uint8_t select_option) +{ + uint8_t skip_bootload_sequence = 0; + si91x_status_t retval = RSI_ERROR_NONE; + + if (!(P2P_STATUS_REG & TA_is_active)) { + P2P_STATUS_REG |= M4_wakeup_TA; + skip_bootload_sequence = 1; + } + while (!(P2P_STATUS_REG & TA_is_active)) { + } + + if (!skip_bootload_sequence) { + do { + retval = rsi_waitfor_boardready(); + if (retval == RSI_ERROR_NONE) { + break; + } + if ((retval < 0) && (retval != RSI_ERROR_WAITING_FOR_BOARD_READY) && (retval != RSI_ERROR_IN_OS_OPERATION)) { + return convert_si91x_status_to_sl_status(retval); + } + } while ((retval == RSI_ERROR_WAITING_FOR_BOARD_READY) || (retval == RSI_ERROR_IN_OS_OPERATION)); + retval = rsi_select_option(select_option); + VERIFY_STATUS_AND_RETURN(convert_si91x_status_to_sl_status(retval)); + } + + // Update TX & RX DMA descriptor address + rsi_update_tx_dma_desc(skip_bootload_sequence); + rsi_update_rx_dma_desc(); + +#if SL_SI91X_FAST_FW_UP + status = rsi_set_fast_fw_up(); + if (status != RSI_SUCCESS) { + SL_PRINTF(SL_DEVICE_INIT_SET_FAST_FIRMWARE_UP_ERROR, COMMON, LOG_ERROR, "status: %4x", status); + return status; + } +#endif + + sli_m4_ta_interrupt_init(); + if (!(M4SS_P2P_INTR_SET_REG & RX_BUFFER_VALID)) { + sli_si91x_submit_rx_pkt(); + } + +#if defined(SL_CATALOG_KERNEL_PRESENT) + osKernelInitialize(); +#endif + + return SL_STATUS_OK; +} diff --git a/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/src/sl_platform_wireless.c b/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/src/sl_platform_wireless.c new file mode 100644 index 000000000..e2edd743c --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/src/sl_platform_wireless.c @@ -0,0 +1,423 @@ +/******************************************************************************* + * @file sl_platform_wireless.c +* @brief +******************************************************************************* +* # License +* Copyright 2024 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +#include "FreeRTOSConfig.h" +#include "rsi_wisemcu_hardware_setup.h" +#include "rsi_m4.h" +#include "rsi_rom_egpio.h" +#include "rsi_pll.h" +#include "rsi_rom_clks.h" +#include "rsi_rom_ulpss_clk.h" +#include "rsi_rom_power_save.h" +#include "sl_si91x_host_interface.h" +#include "sl_rsi_utility.h" +#include "system_si91x.h" +#include +#include "cmsis_os2.h" +#include "sl_rsi_utility.h" + +extern osEventFlagsId_t si91x_events; +extern osEventFlagsId_t si91x_bus_events; +extern osEventFlagsId_t si91x_async_events; +extern uint32_t frontend_switch_control; +extern osMutexId_t side_band_crypto_mutex; + +/** @addtogroup SOC2 +* @{ +*/ + +/** + * @brief Configure the default hardware configuration required for 'WiSeMCU' mode. + * @param[in] None + * @note Must be called in main before using any power save related configurations in applications. + * @return Void + */ +void sl_si91x_hardware_setup(void) +{ + /* Disable OTHER_CLK that was enabled at Start-up*/ + RSI_CLK_PeripheralClkDisable3(M4CLK, M4_SOC_CLK_FOR_OTHER_ENABLE); + +#ifndef SL_ULP_TIMER + /* Disable Timer clock that was enabled in Bootloader*/ + RSI_ULPSS_TimerClkDisable(ULPCLK); +#endif + +#if !(defined(SLI_SI917) || defined(SLI_SI917B0)) + /* Disable 40MHz Clocks*/ + RSI_ULPSS_DisableRefClks(MCU_ULP_40MHZ_CLK_EN); +#endif + + /* Power-Down Button Calibration*/ + RSI_PS_BodPwrGateButtonCalibDisable(); + + /* Disable PTAT for Analog Peripherals*/ + RSI_PS_AnalogPeriPtatDisable(); + + /* Disable PTAT for Brown-Out Detection Clocks*/ + RSI_PS_BodClksPtatDisable(); + + /* Power-Down unused Analog(IPMU) Domain peripherals*/ + RSI_IPMU_PowerGateClr(AUXDAC_PG_ENB | AUXADC_PG_ENB | WURX_CORR_PG_ENB | WURX_PG_ENB | ULP_ANG_CLKS_PG_ENB + | CMP_NPSS_PG_ENB); + + /* Power-Down unused NPSS Domain peripherals*/ + RSI_PS_NpssPeriPowerDown(SLPSS_PWRGATE_ULP_MCUWDT | SLPSS_PWRGATE_ULP_MCUPS | SLPSS_PWRGATE_ULP_MCUTS + | SLPSS_PWRGATE_ULP_MCUSTORE2 | SLPSS_PWRGATE_ULP_MCUSTORE3 +#ifndef SL_SLEEP_TIMER + | SLPSS_PWRGATE_ULP_MCURTC +#endif + ); + +#ifndef DS_BASED_WKP + RSI_PS_PowerSupplyDisable(POWER_ENABLE_DEEPSLEEP_TIMER); +#endif + /* Power-Down unused NPSS Domain peripherals*/ + RSI_PS_PowerSupplyDisable(POWER_ENABLE_TIMESTAMPING); + +#ifdef CHIP_9118 + /* Power-Down Unused M4SS Domain peripherals */ + RSI_PS_M4ssPeriPowerDown( + +#ifndef DEBUG_UART + M4SS_PWRGATE_ULP_M4_FPU | +#endif + M4SS_PWRGATE_ULP_ETHERNET | M4SS_PWRGATE_ULP_EFUSE | M4SS_PWRGATE_ULP_SDIO_SPI | M4SS_PWRGATE_ULP_USB + | M4SS_PWRGATE_ULP_RPDMA +#ifndef DEBUG_UART + | M4SS_PWRGATE_ULP_PERI1 +#endif + | M4SS_PWRGATE_ULP_PERI2 | M4SS_PWRGATE_ULP_PERI3 | M4SS_PWRGATE_ULP_CCI | M4SS_PWRGATE_ULP_SD_MEM); + /* Power-Down unused ULPSS Domain peripherals*/ + RSI_PS_UlpssPeriPowerDown( +#ifndef SL_ULP_TIMER + ULPSS_PWRGATE_ULP_MISC | +#endif + ULPSS_PWRGATE_ULP_AUX | ULPSS_PWRGATE_ULP_CAP | ULPSS_PWRGATE_ULP_VAD +#ifndef DEBUG_UART + | ULPSS_PWRGATE_ULP_UART +#endif + | ULPSS_PWRGATE_ULP_SSI | ULPSS_PWRGATE_ULP_I2S | ULPSS_PWRGATE_ULP_I2C | ULPSS_PWRGATE_ULP_IR + | ULPSS_PWRGATE_ULP_UDMA | ULPSS_PWRGATE_ULP_FIM); + + /* Turn off ULPSS SRAM domains*/ + RSI_PS_UlpssRamBanksPowerDown(ULPSS_2K_BANK_0 | ULPSS_2K_BANK_1 | ULPSS_2K_BANK_2 | ULPSS_2K_BANK_3 | ULPSS_2K_BANK_4 + | ULPSS_2K_BANK_5 | ULPSS_2K_BANK_6 | ULPSS_2K_BANK_7); + /* Turn off ULPSS SRAM Core/Periphery domains*/ + RSI_PS_UlpssRamBanksPeriPowerDown(ULPSS_2K_BANK_0 | ULPSS_2K_BANK_1 | ULPSS_2K_BANK_2 | ULPSS_2K_BANK_3 + | ULPSS_2K_BANK_4 | ULPSS_2K_BANK_5 | ULPSS_2K_BANK_6 | ULPSS_2K_BANK_7); +#endif + +#ifdef SLI_SI917 + /* Power-Down Unused M4SS Domains */ + RSI_PS_M4ssPeriPowerDown( +#ifndef SLI_SI91X_MCU_ENABLE_FLASH_BASED_EXECUTION + M4SS_PWRGATE_ULP_QSPI_ICACHE | +#endif +#ifndef DEBUG_UART + M4SS_PWRGATE_ULP_EFUSE_PERI | +#endif + M4SS_PWRGATE_ULP_SDIO_SPI | M4SS_PWRGATE_ULP_RPDMA); + + /* Power-Down Unused ULPSS Domain peripherals */ + RSI_PS_UlpssPeriPowerDown( +#ifndef SL_ULP_TIMER + ULPSS_PWRGATE_ULP_MISC | +#endif + ULPSS_PWRGATE_ULP_AUX | ULPSS_PWRGATE_ULP_CAP +#ifndef DEBUG_UART + | ULPSS_PWRGATE_ULP_UART +#endif + | ULPSS_PWRGATE_ULP_SSI | ULPSS_PWRGATE_ULP_I2S | ULPSS_PWRGATE_ULP_I2C | ULPSS_PWRGATE_ULP_IR + | ULPSS_PWRGATE_ULP_UDMA | ULPSS_PWRGATE_ULP_FIM); +#endif + /* Power-Down High-Frequency PLL Domain */ + RSI_PS_SocPllSpiDisable(); + /* Power-Down QSPI-DLL Domain */ + RSI_PS_QspiDllDomainDisable(); + /* Configure PMU Start-up Time to be used on Wake-up*/ + RSI_PS_PmuGoodTimeDurationConfig(PMU_GOOD_TIME); + /* Configure XTAL Start-up Time to be used on Wake-up*/ + RSI_PS_XtalGoodTimeDurationConfig(XTAL_GOOD_TIME); + /*Enable first boot up*/ + RSI_PS_EnableFirstBootUp(1); +} + +/** + * @brief This API is used to configure wireless GPIO front end controls from TA to M4 + * @return none + */ +void sli_si91x_configure_wireless_frontend_controls(uint32_t switch_sel) +{ +#if SLI_SI91X_MCU_INTERFACE + switch (switch_sel) { + case FRONT_END_SWITCH_SEL0: + //!GPIO 46,47,48 + break; + case FRONT_END_SWITCH_SEL1: +#ifdef SLI_SI917B0 + { + //!Program GPIO mode6 in ULP for ULP4,ULP5,ULP0 GPIOS + RSI_EGPIO_SetPinMux(EGPIO1, 0, GPIO4, 6); + RSI_EGPIO_SetPinMux(EGPIO1, 0, GPIO5, 6); + RSI_EGPIO_SetPinMux(EGPIO1, 0, GPIO0, 6); + } +#else + { + //!GPIO 46,47,48 + } +#endif + break; + case FRONT_END_SWITCH_SEL2: +#ifndef SLI_SI917B0 + //!Program GPIO mode6 in ULP for ULP4,ULP5,ULP0 GPIOS + RSI_EGPIO_SetPinMux(EGPIO1, 0, GPIO4, 6); + RSI_EGPIO_SetPinMux(EGPIO1, 0, GPIO5, 6); + RSI_EGPIO_SetPinMux(EGPIO1, 0, GPIO0, 6); +#endif + break; + case FRONT_END_SWITCH_SEL3: +#ifndef SLI_SI917B0 + //!Program GPIO mode6 in ULP for ULP4,ULP5,ULP7 GPIOS + RSI_EGPIO_SetPinMux(EGPIO1, 0, GPIO4, 6); + RSI_EGPIO_SetPinMux(EGPIO1, 0, GPIO5, 6); + RSI_EGPIO_SetPinMux(EGPIO1, 0, GPIO7, 6); +#endif + break; + } +#endif +} + +/** + * @brief Configure the default hardware configuration required for 'WiSeMCU' mode. + * @param[in] sleepType - Select the retention or non-retention mode of processor; refer to 'SLEEP_TYPE_T'. + * \n SLEEP_WITH_RETENTION : When used, user must configure the RAMs to be retained during sleep by using the 'RSI_PS_SetRamRetention()' function. + * @param[in] lf_clk_mode - This parameter is used to switch the processor clock from high frequency clock to low-frequency clock. This is used in some critical power save cases. + * \n '0' : ' \ref DISABLE_LF_MODE' Normal mode of operation , recommended in most applications. + * \n '1' : ' \ref LF_32_KHZ_RC' Processor clock is configured to low-frequency RC clock. + * \n '2' : ' \ref LF_32_KHZ_XTAL' Processor clock is configured to low-frequency XTAL clock. + * @param[in] stack_address - Stack pointer address to be used by bootloader. + * @param[in] jump_cb_address - Control block memory address or function address to be branched up on Wake-up + * @param[in] vector_offset - IVT offset to be programmed by boot-loader up on Wake-up. + * @param[in] mode - Possible parameters as follows: + * \n \ref RSI_WAKEUP_FROM_FLASH_MODE : Wakes from flash with retention. Upon wake up, control jumps to wake up handler in flash. + * In this mode, ULPSS RAMs are used to store the stack pointer and Wake-up handler address. + * \n \ref RSI_WAKEUP_WITH_OUT_RETENTION : Without retention sleep common for both FLASH/RAM based execution. + * In this mode, ULPSS RAMs are used to store the stack pointer and control block address. + * if stack_addr and jump_cb_addr are not valid, then 0x2404_0C00 and 0x2404_0000 are used + * for stack and control block address respectively. + * \n \ref RSI_WAKEUP_WITH_RETENTION : With retention branches to wake up handler in RAM. + * In this mode, ULPSS RAMs are used to store the wake up handler address. + * \n \ref RSI_WAKEUP_WITH_RETENTION_WO_ULPSS_RAM : In this mode, ULPSS RAMs are not used by boot-loader, instead it uses the NPSS battery flip flops. + * \n \ref RSI_WAKEUP_WO_RETENTION_WO_ULPSS_RAM : In this mode, ULPSS RAMs are not used by boot-loader, instead it uses the NPSS battery flip flops to store + * the stack and derives the control block address by adding 0XC00 + * to the stack address stored in battery flops. + * @return Void + */ + +void sl_si91x_trigger_sleep(SLEEP_TYPE_T sleepType, + uint8_t lf_clk_mode, + uint32_t stack_address, + uint32_t jump_cb_address, + uint32_t vector_offset, + uint32_t mode) +{ + // Turn on the ULPSS RAM domains and retain ULPSS RAMs + if ((mode != RSI_WAKEUP_WITH_RETENTION_WO_ULPSS_RAM) || (mode != RSI_WAKEUP_WO_RETENTION_WO_ULPSS_RAM)) { + /* Turn on ULPSS SRAM domains*/ + RSI_PS_UlpssRamBanksPowerUp(ULPSS_2K_BANK_0 | ULPSS_2K_BANK_1 | ULPSS_2K_BANK_2 | ULPSS_2K_BANK_3); + + /* Turn on ULPSS SRAM Core/Periphery domains*/ + RSI_PS_UlpssRamBanksPeriPowerUp(ULPSS_2K_BANK_0 | ULPSS_2K_BANK_1 | ULPSS_2K_BANK_2 | ULPSS_2K_BANK_3); + + if ((mode == RSI_WAKEUP_FROM_FLASH_MODE) || (mode == RSI_WAKEUP_WITH_RETENTION) +#if defined SLI_SI917B0 + || (mode == SL_SI91X_MCU_WAKEUP_PSRAM_MODE) +#endif // SLI_SI917B0 + ) { + /* Retain ULPSS RAM*/ + RSI_PS_SetRamRetention(ULPSS_RAM_RETENTION_MODE_EN); + } + } + + // Peripherals needed on Wake-up (without RAM retention) needs to be powered up before going to sleep + if ((mode == RSI_WAKEUP_WITH_OUT_RETENTION) || (mode == RSI_WAKEUP_WO_RETENTION_WO_ULPSS_RAM)) { + + RSI_PS_M4ssPeriPowerUp(M4SS_PWRGATE_ULP_M4_DEBUG_FPU); + } + +#if (configUSE_TICKLESS_IDLE == 0) + + volatile uint8_t delay; + if ((osEventFlagsGet(si91x_events) | osEventFlagsGet(si91x_bus_events) | osEventFlagsGet(si91x_async_events)) +#ifdef SL_SI91X_SIDE_BAND_CRYPTO + || (osMutexGetOwner(side_band_crypto_mutex) != NULL) +#endif + || ((sl_si91x_host_get_queue_packet_count((sl_si91x_queue_type_t)SI91X_COMMON_CMD) + | sl_si91x_host_get_queue_packet_count((sl_si91x_queue_type_t)SI91X_WLAN_CMD) + | sl_si91x_host_get_queue_packet_count((sl_si91x_queue_type_t)SI91X_NETWORK_CMD) + | sl_si91x_host_get_queue_packet_count((sl_si91x_queue_type_t)SI91X_SOCKET_CMD) + | sl_si91x_host_get_queue_packet_count((sl_si91x_queue_type_t)SI91X_BT_CMD) + | sl_si91x_host_get_queue_packet_count((sl_si91x_queue_type_t)SI91X_SOCKET_DATA)))) { + return; + } + // Disabling the interrupts & clearing m4_is_active as m4 is going to sleep + __disable_irq(); + + // Indicate M4 is Inactive + P2P_STATUS_REG &= ~M4_is_active; + P2P_STATUS_REG; + // Adding delay to sync m4 with TA + for (delay = 0; delay < 10; delay++) { + __ASM("NOP"); + } + + // Checking if already TA have triggered the packet to M4 + // RX_BUFFER_VALID will be cleared by TA if any packet is triggered + if ((P2P_STATUS_REG & TA_wakeup_M4) || (P2P_STATUS_REG & M4_wakeup_TA) + || (!(M4SS_P2P_INTR_SET_REG & RX_BUFFER_VALID))) { + P2P_STATUS_REG |= M4_is_active; + __enable_irq(); + return; + } + + //Disbling systick & clearing interrupt as systick is non-maskable interrupt + SysTick->CTRL = DISABLE; + NVIC_ClearPendingIRQ(SysTick_IRQn); + + //!Clear RX_BUFFER_VALID + M4SS_P2P_INTR_CLR_REG = RX_BUFFER_VALID; + M4SS_P2P_INTR_CLR_REG; +#endif // configUSE_TICKLESS_IDLE == 0 + +#ifndef ENABLE_DEBUG_MODULE + RSI_PS_M4ssPeriPowerDown(M4SS_PWRGATE_ULP_M4_DEBUG_FPU); +#endif // ENABLE_DEBUG_MODULE + + /* Define 'SLI_SI91X_MCU_ENABLE_FLASH_BASED_EXECUTION' macro if FLASH execution is needed*/ +#ifndef SLI_SI91X_MCU_ENABLE_FLASH_BASED_EXECUTION + RSI_PS_M4ssPeriPowerDown(M4SS_PWRGATE_ULP_QSPI_ICACHE); + // Remove this if MCU is executing from Flash +#endif //SLI_SI91X_MCU_ENABLE_FLASH_BASED_EXECUTION + + // Move M4 SOC clock to ULP reference clock before going to PowerSave + if (RSI_CLK_M4SocClkConfig(M4CLK, M4_ULPREFCLK, 0) != RSI_OK) { + printf("RSI_CLK_M4SocClkConfig failed\n"); + } + + // Configure sleep parameters required by bootloader upon Wake-up + RSI_PS_RetentionSleepConfig(stack_address, (uint32_t)jump_cb_address, vector_offset, mode); + + // Trigger M4 to sleep + RSI_PS_EnterDeepSleep(sleepType, lf_clk_mode); + +#ifdef SLI_SI917 + // Upon wake up program wireless GPIO frontend switch controls + if (frontend_switch_control != 0) { + sli_si91x_configure_wireless_frontend_controls(frontend_switch_control); + } +#endif + +#if (configUSE_TICKLESS_IDLE == 0) + //!Indicate M4 is active and rx buffer valid + P2P_STATUS_REG |= M4_is_active; + M4SS_P2P_INTR_SET_REG = RX_BUFFER_VALID; + __enable_irq(); + + // Systick configuration upon Wake-up + SysTick_Config(SystemCoreClock / configTICK_RATE_HZ); +#endif // configUSE_TICKLESS_IDLE == 0 +} + +/** + * @brief Configure the default hardware configuration required for 'WiSeMCU' mode. + * @param[in] rams_in_use - RAMs to be powered functionally (the rest of the RAM banks will be power gates) + * \n Macros used for this parameter: + * \n WISEMCU_0KB_RAM_IN_USE : None of the RAMs will be powered , i.e., all RAM banks will be power gates + * \n WISEMCU_16KB_RAM_IN_USE : Only 16KB RAM will be retained + * \n WISEMCU_48KB_RAM_IN_USE : Only 48KB RAM will be retained + * \n WISEMCU_112KB_RAM_IN_USE : Only 112KB RAM will be retained + * \n WISEMCU_128KB_RAM_IN_USE : Only 128KB RAM will be retained + * \n WISEMCU_144KB_RAM_IN_USE : Only 114KB RAM will be retained + * \n WISEMCU_176KB_RAM_IN_USE : Only 176KB RAM will be retained + * \n WISEMCU_192KB_RAM_IN_USE : Only 192KB RAM will be retained + * \n WISEMCU_208KB_RAM_IN_USE : Only 208KB RAM will be retained + * \n WISEMCU_240KB_RAM_IN_USE : Only 240KB RAM will be retained + * \n WISEMCU_320KB_RAM_IN_USE : Only 320KB RAM will be retained + * \n WISEMCU_384KB_RAM_IN_USE : Only 384KB RAM will be retained + * + * \n Macros used for 9117: + * \n WISEMCU_64KB_RAM_IN_USE : 320KB RAM will be retained + * \n WISEMCU_128KB_RAM_IN_USE : 320KB RAM will be retained + * \n WISEMCU_192KB_RAM_IN_USE : 320KB RAM will be retained + * \n WISEMCU_256KB_RAM_IN_USE : 320KB RAM will be retained + * + * @param[in] rams_retention_during_sleep - Configure RAM retentions to the hardware so that particular RAM banks are retained during sleep + * \n Macros used for this parameter: + * \n WISEMCU_RETAIN_DEFAULT_RAM_DURING_SLEEP : Select the RAM Retention controls automatically by API based on 'rams_power_gate' value passed by user + * \n WISEMCU_RETAIN_16K_RAM_DURING_SLEEP : Retain 16KB M4-ULP RAM + * \n WISEMCU_RETAIN_128K_RAM_DURING_SLEEP : Retain 16KB M4-ULP RAM and 112KB M4-ULP RAM + * \n WISEMCU_RETAIN_192K_RAM_DURING_SLEEP : Retain 16KB M4-ULP RAM and 112KB M4-ULP RAM and 64KB M4SS RAM + * \n WISEMCU_RETAIN_384K_RAM_DURING_SLEEP : Retain 16KB M4-ULP RAM and 112KB M4-ULP RAM and 64KB M4SS RAM and TASS 192KB RAM + * \n WISEMCU_RETAIN_M4SS_RAM_DURING_SLEEP : Retain Only 64KB M4SS RAM + * \n WISEMCU_RETAIN_ULPSS_RAM_DURING_SLEEP : Retain Only 16KB ULPSS RAM + * \n WISEMCU_RETAIN_TASS_RAM_DURING_SLEEP : Retain Only 192KB TASS RAM + * \n WISEMCU_RETAIN_M4ULP_RAM_DURING_SLEEP : Retain Only 112KB M4-ULP RAM + * @return void + * @note Must be called in main before using any power save related configurations in applications. + */ +void sl_si91x_configure_ram_retention(uint32_t rams_in_use, uint32_t rams_retention_during_sleep) +{ + + uint32_t rams_to_be_powered_down = rams_in_use; + +#if (SL_SI91X_SI917_RAM_MEM_CONFIG == 1) // SL_SI91X_RAM_LEVEL_NWP_ADV_MCU_BASIC + rams_to_be_powered_down &= ~(RAM_BANK_8 | RAM_BANK_9); +#elif (SL_SI91X_SI917_RAM_MEM_CONFIG == 2) // SL_SI91X_RAM_LEVEL_NWP_MEDIUM_MCU_MEDIUM + rams_to_be_powered_down &= ~(RAM_BANK_9); +#endif + + /* Turn off Unused SRAMs*/ + RSI_PS_M4ssRamBanksPowerDown(rams_to_be_powered_down); + + /* Turn off Unused SRAM Core/Periphery domains*/ + RSI_PS_M4ssRamBanksPeriPowerDown(rams_in_use); + + /* Clear all RAM retention control before configuring the user RAM retentions*/ + RSI_PS_ClrRamRetention(M4ULP_RAM16K_RETENTION_MODE_EN | TA_RAM_RETENTION_MODE_EN | M4ULP_RAM_RETENTION_MODE_EN); + + /* If user selects the default RAM retentions, then select the RAM retentions based on RAM power gates*/ + if (rams_retention_during_sleep & WISEMCU_RETAIN_DEFAULT_RAM_DURING_SLEEP) { + /* If none of the banks are powered on, clear all retention controls*/ + if (rams_in_use & WISEMCU_0KB_RAM_IN_USE) { + RSI_PS_ClrRamRetention(M4ULP_RAM16K_RETENTION_MODE_EN | TA_RAM_RETENTION_MODE_EN | M4ULP_RAM_RETENTION_MODE_EN); + } + /* Set the 16KB SRAM memory retention */ + if (rams_in_use == WISEMCU_16KB_RAM_IN_USE) { + RSI_PS_SetRamRetention(M4ULP_RAM16K_RETENTION_MODE_EN); + } + /* Set the full SRAM memory retention if the SRAM memory usage is greater than 16KB */ + /* For different SRAM retention modes, respective unused SRAM banks (both SRAM power and core/periphery domains) are powered down as part of the initial configuration above */ + else { + RSI_PS_SetRamRetention(M4ULP_RAM16K_RETENTION_MODE_EN | M4ULP_RAM_RETENTION_MODE_EN); + } + } else { + /* Program user configuration*/ + RSI_PS_SetRamRetention(rams_retention_during_sleep); + } +} + +/** @} */ \ No newline at end of file diff --git a/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/src/sl_si91x_bus.c b/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/src/sl_si91x_bus.c new file mode 100644 index 000000000..873a9165d --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/src/sl_si91x_bus.c @@ -0,0 +1,188 @@ +/******************************************************************************* +* @file +* @brief +******************************************************************************* +* # License +* Copyright 2020 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ +#include "sl_status.h" +#include "sl_si91x_types.h" +#include "system_si91x.h" +#include "rsi_m4.h" +#include "sl_constants.h" +#include "cmsis_os2.h" +#include "rsi_power_save.h" +#include "sl_si91x_host_interface.h" +#include +#include +#include "sl_rsi_utility.h" + +rsi_m4ta_desc_t tx_desc[2]; +rsi_m4ta_desc_t rx_desc[2]; + +/****************************************************** + * * Function Declarations + * ******************************************************/ +sl_status_t sli_si91x_submit_rx_pkt(void); +void sli_submit_rx_buffer(void); +void sli_si91x_raise_pkt_pending_interrupt_to_ta(void); + +/** + * @fn sl_status_t sli_si91x_submit_rx_pkt(void) + * @brief Submit receiver packets + * @param[in] None + * @return 0 - Success \n + * Non-Zero - Failure + */ +sl_wifi_buffer_t *rx_pkt_buffer; +sl_status_t sli_si91x_submit_rx_pkt(void) +{ + sl_status_t status; + uint16_t data_length = 0; + sl_si91x_packet_t *packet; + int8_t *pkt_buffer = NULL; + + if (M4SS_P2P_INTR_SET_REG & RX_BUFFER_VALID) { + return -2; + } + + // Allocate packet to receive packet from module + status = sl_si91x_host_allocate_buffer(&rx_pkt_buffer, SL_WIFI_RX_FRAME_BUFFER, 1616, 1000); + if (status != SL_STATUS_OK) { + SL_DEBUG_LOG("\r\n HEAP EXHAUSTED DURING ALLOCATION \r\n"); + BREAKPOINT(); + } + + packet = sl_si91x_host_get_buffer_data(rx_pkt_buffer, 0, &data_length); + pkt_buffer = (int8_t *)&packet->desc[0]; + + // Fill source address in the TX descriptors + rx_desc[0].addr = (M4_MEMORY_OFFSET_ADDRESS + (uint32_t)pkt_buffer); + + // Fill source address in the TX descriptors + rx_desc[0].length = (16); + + // Fill source address in the TX descriptors + rx_desc[1].addr = (M4_MEMORY_OFFSET_ADDRESS + (uint32_t)(pkt_buffer + 16)); + + // Fill source address in the TX descriptors + rx_desc[1].length = (1600); + + raise_m4_to_ta_interrupt(RX_BUFFER_VALID); + + return SL_STATUS_OK; +} + +sl_status_t sl_si91x_bus_read_frame(sl_wifi_buffer_t **buffer) +{ + sl_status_t status = sl_si91x_host_remove_from_queue(CCP_M4_TA_RX_QUEUE, buffer); + VERIFY_STATUS_AND_RETURN(status); + + return SL_STATUS_OK; +} + +/** + * @fn sl_status_t sl_si91x_bus_write_frame(sl_si91x_packet_t *packet, + * uint8_t *payloadparam, uint16_t size_param) + * @brief writing a command to the module. + * @param[in] payloadparam - pointer to the command payload parameter structure + * @param[in] size_param - size of the payload for the command + * @return 0 - Success \n + * Negative Value - Failure + */ + +sl_status_t sl_si91x_bus_write_frame(sl_si91x_packet_t *packet, const uint8_t *payloadparam, uint16_t size_param) +{ + + // Fill source address in the TX descriptors + tx_desc[0].addr = (M4_MEMORY_OFFSET_ADDRESS + (uint32_t)&packet->desc[0]); + + // Fill source address in the TX descriptors + tx_desc[0].length = (16); + + // Fill source address in the TX descriptors + tx_desc[1].addr = (M4_MEMORY_OFFSET_ADDRESS + (uint32_t)payloadparam); + + // Fill source address in the TX descriptors + tx_desc[1].length = (size_param); + + sli_si91x_raise_pkt_pending_interrupt_to_ta(); + + return SL_STATUS_OK; +} + +void sli_submit_rx_buffer(void) +{ + mask_ta_interrupt(RX_PKT_TRANSFER_DONE_INTERRUPT); + + //! submit to TA submit packet + sli_si91x_submit_rx_pkt(); + + unmask_ta_interrupt(RX_PKT_TRANSFER_DONE_INTERRUPT); +} + +/** + * @fn void rsi_update_tx_dma_desc(uint8 skip_dma_valid) + * @brief This function updates the TX DMA descriptor address + * @param[in] skip_dma_valid + * @param[out] none + * @return none + * @section description + * This function updates the TX DMA descriptor address + * + * + */ + +void rsi_update_tx_dma_desc(uint8_t skip_dma_valid) +{ + if (!skip_dma_valid) { +#ifdef SLI_SI91X_MCU_COMMON_FLASH_MODE + if (!(M4_ULP_SLP_STATUS_REG & MCU_ULP_WAKEUP)) +#endif + { + while (M4_TX_DMA_DESC_REG & DMA_DESC_REG_VALID) + ; + } + } + M4_TX_DMA_DESC_REG = (uint32_t)&tx_desc; +} + +/*==============================================*/ +/** + * @fn void rsi_update_rx_dma_desc() + * @brief This function updates the RX DMA descriptor address + * @param[in] none + * @param[out] none + * @return none + * @section description + * This function updates the RX DMA descriptor address + * + * + */ +void rsi_update_rx_dma_desc(void) +{ + M4_RX_DMA_DESC_REG = (uint32_t)&rx_desc; +} + +void sli_si91x_config_m4_dma_desc_on_reset(void) +{ + + //! Wait for TA to wakeup and should be in bootloader + while (!(P2P_STATUS_REG & TA_is_active)) + ; + SL_DEBUG_LOG("\r\nTA is in active state\r\n"); + //! TBD Need to address why soft reset expecting delay + osDelay(100); + //! Update M4 Tx and Rx DMA descriptors + M4_TX_DMA_DESC_REG = (uint32_t)&tx_desc; + M4_RX_DMA_DESC_REG = (uint32_t)&rx_desc; +} diff --git a/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/src/sli_siwx917_soc.c b/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/src/sli_siwx917_soc.c new file mode 100644 index 000000000..4832d9399 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/src/sli_siwx917_soc.c @@ -0,0 +1,536 @@ +/******************************************************************************* +* @file sli_siwx917_soc.c +* @brief +******************************************************************************* +* # License +* Copyright 2023 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +#include "sl_component_catalog.h" +#include "system_si91x.h" +#include "rsi_error.h" +#include "rsi_ccp_common.h" +#include "sl_si91x_constants.h" +#include "rsi_ipmu.h" +#include "rsi_rom_clks.h" +#include "rsi_rom_ulpss_clk.h" +#include "rsi_m4.h" +#include "sl_si91x_status.h" +#include "sli_siwx917_timer.h" +#include "sli_siwx917_soc.h" +#include "sl_constants.h" +#include "rsi_temp_sensor.h" +#include "sl_si91x_host_interface.h" +#if defined(SL_CATALOG_KERNEL_PRESENT) +#include "cmsis_os2.h" +#endif + +#define RSI_HAL_MAX_WR_BUFF_LEN 4096 + +#define SI91X_INTERFACE_OUT_REGISTER (*(uint32_t *)(RSI_HOST_INTF_REG_OUT)) +#define SI91X_INTERFACE_IN_REGISTER (*(uint32_t *)(RSI_HOST_INTF_REG_IN)) +#define SI91X_INTERFACE_STATUS_REGISTER (*(uint32_t *)(RSI_HOST_INTF_STATUS_REG)) +#define SI91X_PING_BUFFER_ADDRESS_REGISTER (*(uint32_t *)(RSI_PING_BUFFER_ADDR)) +#define SI91X_PONG_BUFFER_ADDRESS_REGISTER (*(uint32_t *)(RSI_PONG_BUFFER_ADDR)) + +typedef struct { + uint8_t _[2048]; +} sli_si91x_pingpong_buffer_t; + +#define SI91X_PING_BUFFER ((sli_si91x_pingpong_buffer_t *)(0x19000)) +#define SI91X_PONG_BUFFER ((sli_si91x_pingpong_buffer_t *)(0x1A000)) + +// #if defined(__GNUC__) +// #pragma GCC diagnostic push +// #pragma GCC diagnostic ignored "-Warray-bounds" +// #pragma GCC diagnostic ignored "-Wcast-align" +// #endif // __GNUC__ + +/** + *@} + */ +//static void rsi_mem_wr(uint32_t addr, uint16_t len, uint8_t *dBuf) +//{ +// UNUSED_PARAMETER(len); +// *(uint32_t *)addr = *(uint32_t *)dBuf; +//} + +//void rsi_mem_rd(uint32_t addr, uint16_t len, uint8_t *dBuf) +//{ +// UNUSED_PARAMETER(len); +// *(uint32_t *)dBuf = *(uint32_t *)addr; +//} +// #if defined(__GNUC__) +// #pragma GCC diagnostic pop +// #endif // __GNUC__ + +/** + * @fn int16_t rsi_bl_select_option(uint8_t cmd) + * @brief Send firmware load request to module or update default configurations. + * @param[in] cmd - type of configuration to be saved \n + * BURN_NWP_FW - 0x42 \n + * LOAD_NWP_FW - 0x31 \n + * LOAD_DEFAULT_NWP_FW_ACTIVE_LOW - 0x71 \n + * @return 0 - Success \n + * Non-Zero Value - Failure \n + * -28 - Firmware Load or Upgrade timeout error \n + * -14 - Valid Firmware not present \n + * -15 - Invalid Option + * + */ +/// @private +int16_t rsi_bl_select_option(uint8_t cmd) +{ + uint16_t boot_cmd = 0; + int16_t retval = 0; + uint16_t read_value = 0; + sl_si91x_timer_t timer_instance; + + SI91X_INTERFACE_OUT_REGISTER = boot_cmd; + + if (cmd == BURN_NWP_FW) { + boot_cmd = RSI_HOST_INTERACT_REG_VALID_FW | cmd; + } else { + boot_cmd = RSI_HOST_INTERACT_REG_VALID | cmd; + } + retval = sli_si91x_send_boot_instruction(RSI_REG_WRITE, &boot_cmd); + if (retval < 0) { + return retval; + } + + sl_si91x_timer_init(&timer_instance, 300); + + while ((cmd != LOAD_NWP_FW) && (cmd != LOAD_DEFAULT_NWP_FW_ACTIVE_LOW)) { + retval = sli_si91x_send_boot_instruction(RSI_REG_READ, &read_value); + if (retval < 0) { + return retval; + } + if (cmd == BURN_NWP_FW) { + if (read_value == (RSI_HOST_INTERACT_REG_VALID | RSI_SEND_RPS_FILE)) { + break; + } + } + + else if (read_value == (RSI_HOST_INTERACT_REG_VALID | cmd)) { + break; + } + if (sl_si91x_timer_expired(&timer_instance)) { + return RSI_ERROR_FW_LOAD_OR_UPGRADE_TIMEOUT; + } + } + if ((cmd == LOAD_NWP_FW) || (cmd == LOAD_DEFAULT_NWP_FW_ACTIVE_LOW)) { + sl_si91x_timer_init(&timer_instance, 3000); + do { + retval = sli_si91x_send_boot_instruction(RSI_REG_READ, &read_value); + if (retval < 0) { + return retval; + } + if ((read_value & 0xF000) == (RSI_HOST_INTERACT_REG_VALID_FW & 0xF000)) { + if ((read_value & 0xFF) == VALID_FIRMWARE_NOT_PRESENT) { +#ifdef RSI_DEBUG_PRINT + RSI_DPRINT(RSI_PL4, "VALID_FIRMWARE_NOT_PRESENT\n"); +#endif + return RSI_ERROR_VALID_FIRMWARE_NOT_PRESENT; + } + if ((read_value & 0xFF) == RSI_INVALID_OPTION) { +#ifdef RSI_DEBUG_PRINT + RSI_DPRINT(RSI_PL4, "INVALID CMD\n"); +#endif + + return RSI_ERROR_INVALID_OPTION; + } + if ((read_value & 0xFF) == RSI_CHECKSUM_SUCCESS) { +#ifdef RSI_DEBUG_PRINT + RSI_DPRINT(RSI_PL4, "LOAD SUCCESS\n"); +#endif + break; + } + } + if (sl_si91x_timer_expired(&timer_instance)) { + return RSI_ERROR_FW_LOAD_OR_UPGRADE_TIMEOUT; + } + + } while (1); + } + return retval; +} + +/** + * @fn int16_t sli_si91x_send_boot_instruction(uint8_t type, uint16_t *data) + * @brief Send boot instructions to module. + * @param[in] type - type of the insruction to perform \n + * 0xD1 - RSI_REG_READ \n + * 0xD2 - RSI_REG_WRITE \n + * 0xD5 - RSI_PING_WRITE \n + * 0xD4 - RSI_PONG_WRITE \n + * 0x42 - BURN_NWP_FW \n + * 0x31 - LOAD_NWP_FW \n + * 0x71 - LOAD_DEFAULT_NWP_FW_ACTIVE_LOW + * @param[in] data - pointer to data which is to be read/write \n + * @return 0 - Success \n + * Non-Zero Value - Failure \n + * -28 - Firmware Load or Upgrade timeout error \n + * -2 - Invalid Parameter \n + * -1 or -2 - SPI Failure + * @note This is a proprietry API and it is not recommended to be used by the user directly. + */ +/// @private +int16_t sli_si91x_send_boot_instruction(uint8_t type, uint16_t *data) +{ + int16_t retval = 0; + uint32_t cmd = 0; + uint16_t read_data = 0; + sl_si91x_timer_t timer_instance; + + switch (type) { + case RSI_REG_READ: + *data = SI91X_INTERFACE_OUT_REGISTER; + break; + + case RSI_REG_WRITE: + SI91X_INTERFACE_IN_REGISTER = *data; + break; + + // case RSI_PING_WRITE: + // + // for (j = 0; j <= RSI_PING_PONG_CHUNK_SIZE / RSI_HAL_MAX_WR_BUFF_LEN; j++) { + // if (j == RSI_PING_PONG_CHUNK_SIZE / RSI_HAL_MAX_WR_BUFF_LEN) { + // len = (RSI_PING_PONG_CHUNK_SIZE % RSI_HAL_MAX_WR_BUFF_LEN); + // if (len == 0) { + // break; + // } + // } else { + // len = RSI_HAL_MAX_WR_BUFF_LEN; + // } + // rsi_mem_wr(RSI_PING_BUFFER_ADDR + offset, len, (uint8_t *)((uint32_t)data + offset)); + // if (retval < 0) { + // return retval; + // } + // offset += len; + // } + // SI91X_INTERFACE_IN_REGISTER = RSI_PING_AVAIL | RSI_HOST_INTERACT_REG_VALID; + // break; + // case RSI_PONG_WRITE: + // + // for (j = 0; j <= RSI_PING_PONG_CHUNK_SIZE / RSI_HAL_MAX_WR_BUFF_LEN; j++) { + // if (j == RSI_PING_PONG_CHUNK_SIZE / RSI_HAL_MAX_WR_BUFF_LEN) { + // len = (RSI_PING_PONG_CHUNK_SIZE % RSI_HAL_MAX_WR_BUFF_LEN); + // if (len == 0) { + // break; + // } + // } else { + // len = RSI_HAL_MAX_WR_BUFF_LEN; + // } + // retval = rsi_mem_wr(RSI_PONG_BUFFER_ADDR + offset, len, (uint8_t *)((uint32_t)data + offset)); + // if (retval < 0) { + // return retval; + // } + // offset += len; + // } + // // Perform the write operation + // local = (RSI_PONG_AVAIL | RSI_HOST_INTERACT_REG_VALID); + // + // SI91X_INTERFACE_IN_REGISTER = local; + // break; + + case BURN_NWP_FW: + cmd = BURN_NWP_FW | RSI_HOST_INTERACT_REG_VALID; + + SI91X_INTERFACE_IN_REGISTER = cmd; + + sl_si91x_timer_init(&timer_instance, 300); + + do { + read_data = SI91X_INTERFACE_OUT_REGISTER; + if (sl_si91x_timer_expired(&timer_instance)) { + return RSI_ERROR_FW_LOAD_OR_UPGRADE_TIMEOUT; + } + } while (read_data != (RSI_SEND_RPS_FILE | RSI_HOST_INTERACT_REG_VALID)); + break; + + case LOAD_NWP_FW: + SI91X_INTERFACE_IN_REGISTER = LOAD_NWP_FW | RSI_HOST_INTERACT_REG_VALID; + break; + + case LOAD_DEFAULT_NWP_FW_ACTIVE_LOW: + SI91X_INTERFACE_IN_REGISTER = LOAD_DEFAULT_NWP_FW_ACTIVE_LOW | RSI_HOST_INTERACT_REG_VALID; + break; + + default: + retval = RSI_ERROR_INVALID_PARAM; + break; + } + return retval; +} + +/** + * @fn int16 rsi_waitfor_boardready(void) + * @brief Waits to receive board ready from WiFi module + * @param[in] none + * @param[out] none + * @return errCode + * 0 = SUCCESS + * < 0 = Failure + * -7 = Error in OS operation + * -9 = Bootup options last configuration not saved + * -10 = Bootup options checksum failed + * -11 = Bootloader version mismatch + * -12 = Board ready not received + * @section description + * This API is used to check board ready from WiFi module. + */ +int16_t rsi_waitfor_boardready(void) +{ + int16_t retval = 0; + uint16_t read_value = 0; + + retval = rsi_boot_insn(REG_READ, &read_value); + + if (retval < 0) { + return retval; + } + if (read_value == 0) { + return RSI_ERROR_IN_OS_OPERATION; + } + if ((read_value & 0xFF00) == (HOST_INTERACT_REG_VALID_READ & 0xFF00)) { + if ((read_value & 0xFF) == RSI_BOOTUP_OPTIONS_LAST_CONFIG_NOT_SAVED) { +#ifdef RSI_DEBUG_PRINT + RSI_DPRINT(RSI_PL3, "BOOTUP OPTIOINS LAST CONFIGURATION NOT SAVED\n"); +#endif + return RSI_ERROR_BOOTUP_OPTIONS_NOT_SAVED; + } else if ((read_value & 0xFF) == RSI_BOOTUP_OPTIONS_CHECKSUM_FAIL) { +#ifdef RSI_DEBUG_PRINT + RSI_DPRINT(RSI_PL3, "BOOTUP OPTIONS CHECKSUM FAIL\n"); +#endif + return RSI_ERROR_BOOTUP_OPTIONS_CHECKSUM_FAIL; + } +#if defined(BOOTLOADER_VERSION_CHECK) && (BOOTLOADER_VERSION_CHECK == 1) + else if ((read_value & 0xFF) == BOOTLOADER_VERSION) { +#ifdef RSI_DEBUG_PRINT + RSI_DPRINT(RSI_PL3, "BOOTLOADER VERSION CORRECT\n"); +#endif + } else { +#ifdef RSI_DEBUG_PRINT + RSI_DPRINT(RSI_PL3, "BOOTLOADER VERSION NOT MATCHING\n"); +#endif + + return RSI_ERROR_BOOTLOADER_VERSION_NOT_MATCHING; + } +#endif + +#ifdef RSI_DEBUG_PRINT + RSI_DPRINT(RSI_PL3, "RECIEVED BOARD READY\n"); +#endif + return RSI_ERROR_NONE; + } + +#ifdef RSI_DEBUG_PRINT + RSI_DPRINT(RSI_PL3, "WAITING FOR BOARD READY\n"); +#endif + return RSI_ERROR_WAITING_FOR_BOARD_READY; +} + +/** + * @fn int16 rsi_select_option(uint8 cmd) + * @brief Sends cmd to select option to load or update configuration + * @param[in] uint8 cmd, type of configuration to be saved + * @param[out] none + * @return errCode + < 0 = Command issue failed + * 0 = SUCCESS + * @section description + * This API is used to send firmware load request to WiFi module or update default configurations. + */ +int16_t rsi_select_option(uint8_t cmd) +{ + uint16_t boot_cmd = 0; + int16_t retval = 0; + uint16_t read_value = 0; + uint8_t image_number = 0; + volatile int32_t loop_counter = 0; + + boot_cmd = HOST_INTERACT_REG_VALID | cmd; + if (cmd == CHECK_NWP_INTEGRITY) { + boot_cmd &= 0xF0FF; + boot_cmd = boot_cmd | (uint16_t)(image_number << 8); + } + retval = rsi_boot_insn(REG_WRITE, &boot_cmd); + if (retval < 0) { + return retval; + } + + if ((cmd != LOAD_NWP_FW) && (cmd != LOAD_DEFAULT_NWP_FW_ACTIVE_LOW) && (cmd != RSI_JUMP_TO_PC)) { + RSI_RESET_LOOP_COUNTER(loop_counter); + RSI_WHILE_LOOP((uint32_t)loop_counter, RSI_LOOP_COUNT_SELECT_OPTION) + { + retval = rsi_boot_insn(REG_READ, &read_value); + if (retval < 0) { + return retval; + } + if (cmd == CHECK_NWP_INTEGRITY) { + if ((read_value & 0xFF) == RSI_CHECKSUM_SUCCESS) { +#ifdef RSI_DEBUG_PRINT + RSI_DPRINT(RSI_PL3, "CHECKSUM SUCCESS\n"); +#endif + } else if (read_value == RSI_CHECKSUM_FAILURE) { +#ifdef RSI_DEBUG_PRINT + RSI_DPRINT(RSI_PL3, "CHECKSUM FAIL\n"); +#endif + } else if (read_value == RSI_CHECKSUM_INVALID_ADDRESS) { +#ifdef RSI_DEBUG_PRINT + RSI_DPRINT(RSI_PL3, "Invalid Address \n"); +#endif + } + } + if (read_value == (HOST_INTERACT_REG_VALID | cmd)) { + break; + } + } + RSI_CHECK_LOOP_COUNTER(loop_counter, RSI_LOOP_COUNT_SELECT_OPTION); + } else if ((cmd == LOAD_NWP_FW) || (cmd == LOAD_DEFAULT_NWP_FW_ACTIVE_LOW) || (cmd == RSI_JUMP_TO_PC)) { + retval = rsi_boot_insn(REG_READ, &read_value); + if (retval < 0) { + return retval; + } + if ((read_value & 0xFF) == VALID_FIRMWARE_NOT_PRESENT) { +#ifdef RSI_DEBUG_PRINT + RSI_DPRINT(RSI_PL3, "VALID_FIRMWARE_NOT_PRESENT\n"); +#endif + return RSI_ERROR_VALID_FIRMWARE_NOT_PRESENT; + } + if ((read_value & 0xFF) == RSI_INVALID_OPTION) { +#ifdef RSI_DEBUG_PRINT + RSI_DPRINT(RSI_PL3, "INVALID CMD\n"); +#endif + return RSI_ERROR_COMMAND_NOT_SUPPORTED; + } + } + return retval; +} + +/** + * @fn int16 rsi_boot_insn(uint8 type, uint16 *data) + * @brief Sends boot instructions to WiFi module + * @param[in] uint8 type, type of the insruction to perform + * @param[in] uint32 *data, pointer to data which is to be read/write + * @param[out] none + * @return errCode + * < 0 = Command issued failure/Invalid command + * 0 = SUCCESS + * > 0 = Read value + * @section description + * This API is used to send boot instructions to WiFi module. + */ + +int16_t rsi_boot_insn(uint8_t type, uint16_t *data) +{ + int16_t retval = 0; + uint16_t read_data = 0; + volatile int32_t loop_counter = 0; +#ifdef RSI_DEBUG_PRINT + RSI_DPRINT(RSI_PL3, "\nBootInsn\n"); +#endif + + switch (type) { + case REG_READ: + *data = SI91X_INTERFACE_OUT_REGISTER; + break; + + case REG_WRITE: + SI91X_INTERFACE_IN_REGISTER = *data; + break; + + case PING_WRITE: + memcpy(SI91X_PING_BUFFER, data, sizeof(sli_si91x_pingpong_buffer_t)); + SI91X_INTERFACE_IN_REGISTER = 0xab49; + break; + + case PONG_WRITE: + memcpy(SI91X_PONG_BUFFER, data, sizeof(sli_si91x_pingpong_buffer_t)); + SI91X_INTERFACE_IN_REGISTER = 0xab4f; + break; + + case BURN_NWP_FW: + SI91X_INTERFACE_IN_REGISTER = BURN_NWP_FW | HOST_INTERACT_REG_VALID; + + RSI_RESET_LOOP_COUNTER(loop_counter); + RSI_WHILE_LOOP((uint32_t)loop_counter, RSI_LOOP_COUNT_UPGRADE_IMAGE) + { + read_data = SI91X_INTERFACE_OUT_REGISTER; + if (read_data == (RSI_SEND_RPS_FILE | HOST_INTERACT_REG_VALID)) { + break; + } + } + RSI_CHECK_LOOP_COUNTER(loop_counter, RSI_LOOP_COUNT_UPGRADE_IMAGE); + break; + + case LOAD_NWP_FW: + SI91X_INTERFACE_IN_REGISTER = LOAD_NWP_FW | HOST_INTERACT_REG_VALID; + break; + case LOAD_DEFAULT_NWP_FW_ACTIVE_LOW: + SI91X_INTERFACE_IN_REGISTER = LOAD_DEFAULT_NWP_FW_ACTIVE_LOW | HOST_INTERACT_REG_VALID; + break; + case RSI_UPGRADE_BL: + SI91X_INTERFACE_IN_REGISTER = RSI_UPGRADE_BL | HOST_INTERACT_REG_VALID; + RSI_RESET_LOOP_COUNTER(loop_counter); + RSI_WHILE_LOOP((uint32_t)loop_counter, RSI_LOOP_COUNT_UPGRADE_IMAGE) + { + read_data = SI91X_INTERFACE_OUT_REGISTER; + if (read_data == (RSI_SEND_RPS_FILE | HOST_INTERACT_REG_VALID)) { + break; + } + } + RSI_CHECK_LOOP_COUNTER(loop_counter, RSI_LOOP_COUNT_UPGRADE_IMAGE); + break; + default: + retval = -2; + break; + } + return retval; +} + +void unmask_ta_interrupt(uint32_t interrupt_no) +{ + TASS_P2P_INTR_MASK_CLR = interrupt_no; +} + +void sli_m4_ta_interrupt_init(void) +{ +#ifdef SLI_SI917 + //! Unmask the interrupt + unmask_ta_interrupt(TX_PKT_TRANSFER_DONE_INTERRUPT | RX_PKT_TRANSFER_DONE_INTERRUPT | TA_WRITING_ON_COMM_FLASH + | NWP_DEINIT_IN_COMM_FLASH +#ifdef SLI_SI91X_MCU_FW_UPGRADE_OTA_DUAL_FLASH + | M4_IMAGE_UPGRADATION_PENDING_INTERRUPT +#endif +#ifdef SL_SI91X_SIDE_BAND_CRYPTO + | SIDE_BAND_CRYPTO_DONE +#endif + ); +#else + //! Unmask the interrupt + unmask_ta_interrupt(TX_PKT_TRANSFER_DONE_INTERRUPT | RX_PKT_TRANSFER_DONE_INTERRUPT); +#endif + P2P_STATUS_REG |= M4_is_active; + + *(volatile uint32_t *)0xE000E108 = 0x00000400; + + //! Set P2P Intr priority + NVIC_SetPriority(TASS_P2P_IRQn, TASS_P2P_INTR_PRI); + + return; +} + +void sl_si91x_ulp_wakeup_init(void) +{ + // for compilation +} diff --git a/wiseconnect/components/device/silabs/si91x/wireless/asynchronous_socket/inc/sl_si91x_socket.h b/wiseconnect/components/device/silabs/si91x/wireless/asynchronous_socket/inc/sl_si91x_socket.h new file mode 100644 index 000000000..930698141 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/asynchronous_socket/inc/sl_si91x_socket.h @@ -0,0 +1,357 @@ +/******************************************************************************* +* @file sl_si91x_socket.h +* @brief +******************************************************************************* +* # License +* Copyright 2023 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +#pragma once +#include "sl_si91x_socket_types.h" + +/** + * @addtogroup SI91X_SOCKET_FUNCTIONS + * @{ + */ +/** + * @brief Creates a new socket. + * + * @param[in] family Specifies the communication domain for the socket. This selects the protocol family to be used. + * Accepts values from @ref BSD_SOCKET_FAMILIY. Currently, only @ref AF_INET and @ref AF_INET6 are supported. + * @param[in] type Specifies the type of the socket, which determines the semantics of communication. + * Accepts values from @ref BSD_SOCKET_TYPES. Currently, only @ref SOCK_STREAM and @ref SOCK_DGRAM are supported. + * @param[in] protocol Specifies a particular protocol to be used with the socket. + * Accepts values from @ref BSD_SOCKET_PROTOCOL. Currently, only @ref IPPROTO_TCP, @ref IPPROTO_UDP, and @ref IPPROTO_IP are supported. + * @return int + */ +int sl_si91x_socket(int family, int type, int protocol); + +/** + * @brief Creates an asynchronous socket and registers the provided callback. + * + * @param[in] family Specifies the communication domain for the socket. This selects the protocol family to be used. + * Accepts values from @ref BSD_SOCKET_FAMILIY. Currently, only @ref AF_INET and @ref AF_INET6 are supported. + * @param[in] type Specifies the type of the socket, which determines the semantics of communication. + * Accepts values from @ref BSD_SOCKET_TYPES. Currently, only @ref SOCK_STREAM and @ref SOCK_DGRAM are supported. + * @param[in] protocol Specifies a particular protocol to be used with the socket. + * Accepts values from @ref BSD_SOCKET_PROTOCOL. Currently, only @ref IPPROTO_TCP, @ref IPPROTO_UDP, and @ref IPPROTO_IP are supported. + * @param[in] callback A function pointer of type @ref receive_data_callback. This function is called when the socket receives data. + * @return int + */ +int sl_si91x_socket_async(int family, int type, int protocol, receive_data_callback callback); + +/** + * @brief Sets a specified socket option on the identified socket asynchronously. + * + * @param[in] socket The socket ID. + * @param[in] level The option level. Accepts values from @ref BSD_SOCKET_OPTION_LEVEL. + * @param[in] option_name The option to be configured. Accepts values from @ref SI91X_SOCKET_OPTION_NAME. + * Currently, only the following options are supported: + * - @ref SL_SI91X_SO_RCVTIME + * - @ref SL_SI91X_SO_MAXRETRY + * - @ref SL_SI91X_SO_MSS + * - @ref SL_SI91X_SO_TCP_KEEPALIVE + * - @ref SL_SI91X_SO_HIGH_PERFORMANCE_SOCKET + * - @ref SL_SI91X_SO_SSL_ENABLE + * - @ref SL_SI91X_SO_SSL_V_1_0_ENABLE + * - @ref SL_SI91X_SO_SSL_V_1_1_ENABLE + * - @ref SL_SI91X_SO_SSL_V_1_2_ENABLE + * - @ref SL_SI91X_SO_SOCK_VAP_ID + * - @ref SL_SI91X_SO_SSL_V_1_3_ENABLE + * - @ref SL_SI91X_SO_CERT_INDEX + * - @ref SL_SI91X_SO_TLS_SNI + * - @ref SL_SI91X_SO_MAX_RETRANSMISSION_TIMEOUT_VALUE + * @param[in] option_value The value of the parameter. + * @param[in] option_len The length of the parameter of type @ref socklen_t. + * @return int + */ +int sl_si91x_setsockopt_async(int32_t socket, + int level, + int option_name, + const void *option_value, + socklen_t option_len); + +/** + * @brief Assigns a local protocol address to a socket. + * + * @param[in] socket The socket ID. + * @param[in] addr The address of type @ref sockaddr to which datagrams are to be sent. + * @param[in] addr_len The length of the socket address of type @ref socklen_t in bytes. + * @return int + */ +int sl_si91x_bind(int socket, const struct sockaddr *addr, socklen_t addr_len); + +/** + * @brief Enables a socket to listen for remote connection requests in passive mode. + * + * @param[in] socket The socket ID. + * @param[in] max_number_of_clients The maximum number of clients that the socket can accept. + * @return int + */ +int sl_si91x_listen(int socket, int max_number_of_clients); + +/** + * @brief Accepts a connection request from a remote peer. + * + * This function blocks until a client attempts to connect to the server socket. After receiving a connection request, it proceeds. + * + * @param[in] socket The socket ID. + * @param[in] addr The address of type @ref sockaddr to which datagrams are to be sent. + * @param[in] addr_len The length of the socket address of type @ref socklen_t in bytes. + * @return int + */ +int sl_si91x_accept(int socket, const struct sockaddr *addr, socklen_t addr_len); + +/** + * @brief + * Accepts a connection request from the remote peer and registers a callback. + * + * This function sets up the server socket to listen for incoming connections + * and immediately returns without blocking the main program's execution. + * + * @param[in] socket + * Socket ID. + * @param[in] callback + * A function pointer of type @ref accept_callback that will be called when a new client is connected to the server. + * @return int + */ +int sl_si91x_accept_async(int socket, accept_callback callback); + +/** + * @brief + * Initiates a connection to a remote socket specified by the addr parameter. + * @param[in] socket + * Socket ID. + * @param[in] addr + * Address of type @ref sockaddr to which datagrams are to be sent. + * @param[in] addr_len + * Length of the socket address of type @ref socklen_t in bytes. + * @return int + */ +int sl_si91x_connect(int socket, const struct sockaddr *addr, socklen_t addr_len); + +/** + * @brief + * Sends the data to the remote peer on the given socket. + * + * This should be used only when the socket is in a connected state. + * + * @param[in] socket + * Socket ID. + * @param[in] buffer + * Pointer to the buffer containing data to send to the remote peer. + * @param[in] buffer_length + * Length of the buffer pointed to by the buffer parameter. + * @param[in] flags + * Controls the transmission of the data. + * @return int + * @note The flags parameter is not currently supported. + */ +int sl_si91x_send(int socket, const uint8_t *buffer, size_t buffer_length, int32_t flags); + +/** + * @brief + * Transmits one or more messages to a socket asynchronously. + * + * This should be used only when the socket is in a connected state. + * + * @param[in] socket + * Socket ID. + * @param[in] buffer + * Pointer to the buffer containing data to send to the remote peer + * @param[in] buffer_length + * Length of the buffer pointed to by the buffer parameter. + * @param[in] flags + * Controls the transmission of the data. + * @param[in] callback + * A function pointer of type @ref data_transfer_complete_handler that will be called after complete data transfer. + * @return int + * @note The flags parameter is not currently supported. + */ +int sl_si91x_send_async(int socket, + const uint8_t *buffer, + size_t buffer_length, + int32_t flags, + data_transfer_complete_handler callback); + +/** + * @brief + * Transmits one or more messages to another socket. + * + * The function can also be called from an unconnected socket, typically like a UDP socket. + * + * @param[in] socket + * Socket ID. + * @param[in] buffer + * Pointer to data buffer containing data to send to remote peer. + * @param[in] buffer_length + * Length of the buffer pointed to by the buffer parameter. + * @param[in] flags + * Controls the transmission of the data. + * @param[in] addr + * Address of type @ref sockaddr to which datagrams are to be sent. + * @param[in] addr_len + * Length of the socket address of type @ref socklen_t in bytes. + * @return int + * @note The flags parameter is not currently supported. + */ +int sl_si91x_sendto(int socket, + uint8_t *buffer, + size_t buffer_length, + int32_t flags, + const struct sockaddr *addr, + socklen_t addr_len); + +/** + * @brief + * Transmits one or more messages to another socket asynchronously and receives acknowledgement through the registered callback. + * + * The function can also be called from an unconnected socket, typically like a UDP socket. + * + * @param[in] socket + * Socket ID. + * @param[in] buffer + * Pointer to data buffer containing data to send to remote peer. + * @param[in] buffer_length + * Length of the buffer pointed to by the buffer parameter. + * @param[in] flags + * Controls the transmission of the data. + * @param[in] to_addr + * Address of type @ref sockaddr to which datagrams are to be sent. + * @param[in] to_addr_len + * Length of the socket address of type @ref socklen_t in bytes. + * @param[in] callback + * A function pointer of type @ref data_transfer_complete_handler that will be called after complete data transfer. + * @return int + * @note The flags parameter is not currently supported. + */ +int sl_si91x_sendto_async(int socket, + uint8_t *buffer, + size_t buffer_length, + int32_t flags, + const struct sockaddr *to_addr, + socklen_t to_addr_len, + data_transfer_complete_handler callback); + +/** + * @brief + * Sends the data that is greater than MSS size. + * @param[in] socket + * Socket ID. + * @param[in] buffer + * Pointer to data buffer containing data to send to remote peer. + * @param[in] buffer_length + * Length of the buffer pointed to by the buffer parameter. + * @param[in] flags + * Controls the transmission of the data. + * @return int + * @note The flags parameter is not currently supported. + */ +int sl_si91x_send_large_data(int socket, const uint8_t *buffer, size_t buffer_length, int32_t flags); + +/** + * @brief + * Receives data from a connected socket. + * @param[in] socket + * Socket ID. + * @param[in] buffer + * Pointer to the buffer to hold the data received from the remote peer. + * @param[in] bufferLength + * Length of the buffer pointed to by the buffer parameter. + * @param[in] flags + * Controls the reception of the data. + * @return int + * @note The flags parameter is not currently supported. + */ +int sl_si91x_recv(int socket, uint8_t *buffer, size_t bufferLength, int32_t flags); + +/** + * @brief + * Receives data from an unconnected socket typically like a UDP socket. + * @param[in] socket + * Socket Id. + * @param[in] buffer + * Pointer to the buffer to hold the data received from the remote peer. + * @param[in] buffersize + * Size of the buffer pointed to by the buffer parameter. + * @param[in] flags + * Controls the reception of the data. + * @param[in] fromAddr + * Address of remote peer of type @ref sockaddr, from where current packet was received. + * @param[in] fromAddrLen + * Pointer that contains remote peer address (fromAddr) length of type @ref socklen_t + * @return int + * @note The flags parameter is not currently supported. + */ +int sl_si91x_recvfrom(int socket, + uint8_t *buffer, + size_t buffersize, + int32_t flags, + struct sockaddr *fromAddr, + socklen_t *fromAddrLen); + +/** + * @brief + * Disables send or receive on a socket. + * @param[in] socket + * Socket ID that is to be closed. + * @param[in] how + * Determines whether the socket is closed based on given socket ID or port number. + * - 0: Close the specified socket. + * - 1: Close all the sockets open on a specified socket's source port number. + * @return int + * @note + * In case of socket being a server socket, the "how" parameter would be ignored and socket shall always be closed based on port number. + */ +int sl_si91x_shutdown(int socket, int how); + +/** + * @brief + * Monitors multiple file descriptors, including sockets, for various I/O events, such as readiness for reading or writing, and exceptional conditions. + * + * select() allows a program to monitor multiple file descriptors, + * waiting until one or more of the file descriptors become "ready" + * for some class of I/O operation (e.g., input possible). A file + * descriptor is considered ready if it is possible to perform a + * corresponding I/O operation without blocking. + * + * @param[in] nfds + * The first nfds descriptors are checked in each set; i.e., the descriptors from 0 through nfds-1. + * @param[in,out] readfds + * A pointer to a fd_set object that specifies the descriptors to check for files that are ready for reading. + * @param[in,out] writefds + * A pointer to a fd_set object that specifies the descriptors to check for files that are ready for writing. + * @param[in,out] exceptfds + * A pointer to a fd_set object that will be watched for exceptions. + * @param[in] timeout + * If timeout is not a null pointer, it specifies the maximum interval to wait for the selection to complete. + * @param[in] callback + * A function pointer of type @ref select_callback that will be called when asynchronous response reach the select request. + * @return int + * @note The readfds and writefds parameters are modified in the case of callback being NULL. + * The exceptfds parameter is not currently supported. + */ +int sl_si91x_select(int nfds, + fd_set *readfds, + fd_set *writefds, + fd_set *exceptfds, + struct timeval *timeout, + select_callback callback); + +/** + * @brief + * Register callback for remote socket termination event. + * @param[in] callback + * A valid function pointer of type @ref remote_socket_termination_callback that will be called when remote socket is terminated. + */ +void sl_si91x_set_remote_termination_callback(remote_socket_termination_callback callback); +/** @} */ diff --git a/wiseconnect/components/device/silabs/si91x/wireless/asynchronous_socket/src/sl_si91x_socket.c b/wiseconnect/components/device/silabs/si91x/wireless/asynchronous_socket/src/sl_si91x_socket.c new file mode 100644 index 000000000..22766d1de --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/asynchronous_socket/src/sl_si91x_socket.c @@ -0,0 +1,787 @@ +/******************************************************************************* +* @file sl_si91x_socket.c +* @brief +******************************************************************************* +* # License +* Copyright 2023 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +#include "sl_si91x_socket_utility.h" +#include "sl_status.h" +#include "sl_constants.h" +#include "sl_si91x_socket.h" +#include "sl_si91x_socket_callback_framework.h" +#include "sl_si91x_socket_types.h" +#include "sl_si91x_socket_constants.h" +#include "sl_si91x_protocol_types.h" +#include "sl_rsi_utility.h" +#include "sl_si91x_driver.h" +#include +#include + +/****************************************************** + * Macros + ******************************************************/ +#define TCP_HEADER_LENGTH 56 +#define UDP_HEADER_LENGTH 44 +#define TCP_V6_HEADER_LENGTH 76 +#define UDP_V6_HEADER_LENGTH 64 +#define SI91X_SSL_HEADER_SIZE_IPV4 90 +#define SI91X_SSL_HEADER_SIZE_IPV6 110 + +static int sli_si91x_accept_async(int socket, + const struct sockaddr *addr, + socklen_t addr_len, + accept_callback callback); +static int sli_si91x_socket(int family, int type, int protocol, receive_data_callback callback); + +void sl_si91x_set_remote_termination_callback(remote_socket_termination_callback callback) +{ + sli_si91x_set_remote_socket_termination_callback(callback); +} + +// Create a new socket +int sl_si91x_socket(int family, int type, int protocol) +{ + return sli_si91x_socket(family, type, protocol, NULL); +} + +int sl_si91x_socket_async(int family, int type, int protocol, receive_data_callback callback) +{ + SET_ERRNO_AND_RETURN_IF_TRUE(NULL == callback, 0); + + return sli_si91x_socket(family, type, protocol, callback); +} + +int sli_si91x_socket(int family, int type, int protocol, receive_data_callback callback) +{ + // Validate the socket parameters + SET_ERRNO_AND_RETURN_IF_TRUE(family != AF_INET && family != AF_INET6, EAFNOSUPPORT); + SET_ERRNO_AND_RETURN_IF_TRUE(type != SOCK_STREAM && type != SOCK_DGRAM, EINVAL); + SET_ERRNO_AND_RETURN_IF_TRUE(protocol != IPPROTO_TCP && protocol != IPPROTO_UDP && protocol != 0, EINVAL); + SET_ERRNO_AND_RETURN_IF_TRUE((type == SOCK_STREAM && (protocol != IPPROTO_TCP && protocol != 0)), EPROTOTYPE); + SET_ERRNO_AND_RETURN_IF_TRUE((type == SOCK_DGRAM && (protocol != IPPROTO_UDP && protocol != 0)), EPROTOTYPE); + + // Initialize a new socket structure + si91x_socket_t *si91x_socket; + int socket_index = -1; + + get_free_socket(&si91x_socket, &socket_index); + + // Check if there is enough memory to create the socket + if (socket_index < 0) { + SET_ERROR_AND_RETURN(ENOMEM); + } + + // Populate the socket structure with provided parameters and callbacks + si91x_socket->type = type; + si91x_socket->local_address.sin6_family = family; + si91x_socket->protocol = protocol; + si91x_socket->state = INITIALIZED; + si91x_socket->recv_data_callback = callback; + + // Return the socket index + return socket_index; +} + +int sl_si91x_bind(int socket, const struct sockaddr *addr, socklen_t addr_len) +{ + // Retrieve the socket using the socket index + si91x_socket_t *si91x_socket = get_si91x_socket(socket); + struct sockaddr_in *socket_address = (struct sockaddr_in *)addr; + + // Check if the socket is valid + SET_ERRNO_AND_RETURN_IF_TRUE(si91x_socket == NULL || si91x_socket->state != INITIALIZED, EBADF); + SET_ERRNO_AND_RETURN_IF_TRUE( + (si91x_socket->local_address.sin6_family == AF_INET && addr_len < sizeof(struct sockaddr_in)) + || (si91x_socket->local_address.sin6_family == AF_INET6 && addr_len < sizeof(struct sockaddr_in6)), + EINVAL); + + // Check if the provided address is valid and if the specified port is available + SET_ERRNO_AND_RETURN_IF_TRUE(addr == NULL, EFAULT); + + if (!is_port_available(socket_address->sin_port)) { + SET_ERROR_AND_RETURN(EADDRINUSE); + } + + // Copy the provided address and set the socket state to BOUND + memcpy(&si91x_socket->local_address, + addr, + (addr_len > sizeof(struct sockaddr_in6)) ? sizeof(struct sockaddr_in6) : addr_len); + + si91x_socket->state = BOUND; + + // For UDP sockets, create and send a socket request. + if (si91x_socket->type == SOCK_DGRAM) { + sl_status_t socket_create_request_status = create_and_send_socket_request(socket, SI91X_SOCKET_LUDP, NULL); + SOCKET_VERIFY_STATUS_AND_RETURN(socket_create_request_status, SI91X_NO_ERROR, SI91X_UNDEFINED_ERROR); + + si91x_socket->state = UDP_UNCONNECTED_READY; + } + + return SI91X_NO_ERROR; +} + +int sl_si91x_connect(int socket, const struct sockaddr *addr, socklen_t addr_len) +{ + return sli_si91x_connect(socket, addr, addr_len); +} + +int sl_si91x_listen(int socket, int max_number_of_clients) +{ + int32_t status; + si91x_socket_t *si91x_socket = get_si91x_socket(socket); + + // Check if the socket is valid + SET_ERRNO_AND_RETURN_IF_TRUE(si91x_socket == NULL, EBADF); + SET_ERRNO_AND_RETURN_IF_TRUE(si91x_socket->state != INITIALIZED && si91x_socket->state != BOUND, EBADF); + SET_ERRNO_AND_RETURN_IF_TRUE(si91x_socket->type != SOCK_STREAM, EOPNOTSUPP); + + // Create and send a socket request to make it a TCP server with the specified maximum number of clients + status = create_and_send_socket_request(socket, SI91X_SOCKET_TCP_SERVER, (int *)&max_number_of_clients); + SOCKET_VERIFY_STATUS_AND_RETURN(status, SI91X_NO_ERROR, SI91X_UNDEFINED_ERROR); + + si91x_socket->state = LISTEN; + + return SI91X_NO_ERROR; +} + +int sl_si91x_accept(int socket, const struct sockaddr *addr, socklen_t addr_len) +{ + return sli_si91x_accept_async(socket, addr, addr_len, NULL); +} + +int sl_si91x_shutdown(int socket, int how) +{ + return sli_si91x_shutdown(socket, how); +} + +int sl_si91x_accept_async(int socket, accept_callback callback) +{ + return sli_si91x_accept_async(socket, NULL, 0, callback); +} + +static int sli_si91x_accept_async(int socket, const struct sockaddr *addr, socklen_t addr_len, accept_callback callback) +{ + + // Get the server socket associated with the given socket ID + si91x_socket_t *si91x_server_socket = get_si91x_socket(socket); + si91x_socket_t *si91x_client_socket = NULL; + + // Create variables for context and client socket + sl_si91x_socket_context_t *context = NULL; + int *client_socket = NULL; + + // Create an accept request structure and LTCP response structure + sl_si91x_socket_accept_request_t accept_request = { 0 }; + sl_si91x_rsp_ltcp_est_t *ltcp = NULL; + + sl_wifi_buffer_t *buffer = NULL; + sl_si91x_packet_t *packet = NULL; + sl_si91x_wait_period_t wait_time = 0; + + sl_status_t status = SL_STATUS_OK; + int32_t client_socket_id = -1; + + // Check if the server socket is valid + SET_ERRNO_AND_RETURN_IF_TRUE(si91x_server_socket == NULL, EBADF); + SET_ERRNO_AND_RETURN_IF_TRUE(si91x_server_socket->type != SOCK_STREAM, EOPNOTSUPP); + SET_ERRNO_AND_RETURN_IF_TRUE(si91x_server_socket->state != LISTEN, EINVAL); + + // Create a new instance for socket + client_socket_id = sli_si91x_socket(si91x_server_socket->local_address.sin6_family, + si91x_server_socket->type, + si91x_server_socket->protocol, + si91x_server_socket->recv_data_callback); + + si91x_client_socket = get_si91x_socket(client_socket_id); + //Verifying socket existence + if (si91x_client_socket == NULL) + return -1; + memcpy(&si91x_client_socket->local_address, &si91x_server_socket->local_address, sizeof(struct sockaddr_in6)); + + // Create accept request + accept_request.socket_id = si91x_server_socket->id; + accept_request.source_port = si91x_server_socket->local_address.sin6_port; + + // Set the wait time based on whether a callback is provided + wait_time = + (callback == NULL ? (SL_SI91X_WAIT_FOR_EVER | SL_SI91X_WAIT_FOR_RESPONSE_BIT) : SL_SI91X_RETURN_IMMEDIATELY); + + if (callback != NULL) { + // Set the callback and client socket ID. + sli_si91x_set_accept_callback(callback, client_socket_id); + status = sl_si91x_driver_send_async_command(RSI_WLAN_REQ_SOCKET_ACCEPT, + SI91X_SOCKET_CMD_QUEUE, + &accept_request, + sizeof(accept_request)); + SOCKET_VERIFY_STATUS_AND_RETURN(status, SL_STATUS_OK, SI91X_UNDEFINED_ERROR); + return SI91X_NO_ERROR; + } else { + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_SOCKET_ACCEPT, + SI91X_SOCKET_CMD_QUEUE, + &accept_request, + sizeof(accept_request), + wait_time, + context, + &buffer); + } + + // If the accept request fails, clean up allocated memory and return an error + if (status != SL_STATUS_OK) { + SL_CLEANUP_MALLOC(client_socket); + SL_CLEANUP_MALLOC(context); + close(client_socket_id); + if (buffer != NULL) + sl_si91x_host_free_buffer(buffer); + SET_ERROR_AND_RETURN(SI91X_UNDEFINED_ERROR); + } + + // Extract LTCP response from the received buffer + packet = sl_si91x_host_get_buffer_data(buffer, 0, NULL); + ltcp = (sl_si91x_rsp_ltcp_est_t *)packet->data; + + // Handle the accept response and update the client socket's state + handle_accept_response(client_socket_id, ltcp); + sl_si91x_host_free_buffer(buffer); + + if (addr_len <= 0) { + return client_socket_id; + } + + memcpy((struct sockaddr *)&addr, + &si91x_client_socket->remote_address, + (addr_len > sizeof(struct sockaddr_in6)) ? sizeof(struct sockaddr_in6) : addr_len); + + return client_socket_id; +} + +int sl_si91x_setsockopt_async(int32_t sockID, + int level, + int option_name, + const void *option_value, + socklen_t option_len) +{ + UNUSED_PARAMETER(level); + + // Retrieve the socket using the socket index + si91x_socket_t *si91x_socket = get_si91x_socket(sockID); + sl_si91x_time_value *timeout = NULL; + uint16_t timeout_val; + + // Check if the socket is valid + SET_ERRNO_AND_RETURN_IF_TRUE(si91x_socket == NULL, EBADF); + + // Check if the option value is not NULL + SET_ERRNO_AND_RETURN_IF_TRUE(option_value == NULL, EFAULT) + + switch (option_name) { + case SL_SI91X_SO_RCVTIME: { + // Configure receive timeout + timeout = (sl_si91x_time_value *)option_value; + + // Ensure that the timeout value is at least 1 millisecond + if ((timeout->tv_sec == 0) && (timeout->tv_usec != 0) && (timeout->tv_usec < 1000)) { + timeout->tv_usec = 1000; + } + // Calculate the timeout value in milliseconds + timeout_val = (timeout->tv_usec / 1000) + (timeout->tv_sec * 1000); + + // Need to add check here if Synchronous bit map is set (after async socket_id implementation) + memcpy(&si91x_socket->read_timeout, + &timeout_val, + GET_SAFE_MEMCPY_LENGTH(sizeof(si91x_socket->read_timeout), option_len)); + break; + } + + case SL_SI91X_SO_MAXRETRY: { + // Set the maximum number of TCP retries + memcpy(&si91x_socket->max_tcp_retries, + (uint16_t *)option_value, + GET_SAFE_MEMCPY_LENGTH(sizeof(si91x_socket->max_tcp_retries), option_len)); + break; + } + + case SL_SI91X_SO_MSS: { + memcpy(&si91x_socket->mss, + (uint16_t *)option_value, + GET_SAFE_MEMCPY_LENGTH(sizeof(si91x_socket->mss), option_len)); + break; + } + + case SL_SI91X_SO_TCP_KEEPALIVE: { + // Set the TCP keep-alive initial time + memcpy(&si91x_socket->tcp_keepalive_initial_time, + (uint16_t *)option_value, + GET_SAFE_MEMCPY_LENGTH(sizeof(si91x_socket->tcp_keepalive_initial_time), option_len)); + break; + } + case SL_SI91X_SO_HIGH_PERFORMANCE_SOCKET: { + // Enable high-performance socket mode + SET_ERRNO_AND_RETURN_IF_TRUE(*(uint8_t *)option_value != SI91X_HIGH_PERFORMANCE_SOCKET, EINVAL); + si91x_socket->ssl_bitmap |= SI91X_HIGH_PERFORMANCE_SOCKET; + break; + } + + case SL_SI91X_SO_SSL_ENABLE: { + // Enable SSL for the socket + SET_ERRNO_AND_RETURN_IF_TRUE((*(uint8_t *)option_value) != SI91X_SOCKET_FEAT_SSL, EINVAL); + si91x_socket->ssl_bitmap |= SI91X_SOCKET_FEAT_SSL; + break; + } + case SL_SI91X_SO_SSL_V_1_0_ENABLE: { + // Enable SSL version 1.0 for the socket + SET_ERRNO_AND_RETURN_IF_TRUE(((*(uint8_t *)option_value) != (SI91X_SOCKET_FEAT_SSL | SL_SI91X_TLS_V_1_0)), + EINVAL); + si91x_socket->ssl_bitmap |= SI91X_SOCKET_FEAT_SSL | SL_SI91X_TLS_V_1_0; + break; + } + case SL_SI91X_SO_SSL_V_1_1_ENABLE: { + // Enable SSL version 1.1 for the socket + SET_ERRNO_AND_RETURN_IF_TRUE(((*(uint8_t *)option_value) != (SI91X_SOCKET_FEAT_SSL | SL_SI91X_TLS_V_1_1)), + EINVAL); + si91x_socket->ssl_bitmap |= SI91X_SOCKET_FEAT_SSL | SL_SI91X_TLS_V_1_1; + break; + } + case SL_SI91X_SO_SSL_V_1_2_ENABLE: { + // Enable SSL version 1.2 for the socket + SET_ERRNO_AND_RETURN_IF_TRUE(((*(uint8_t *)option_value) != (SI91X_SOCKET_FEAT_SSL | SL_SI91X_TLS_V_1_2)), + EINVAL); + si91x_socket->ssl_bitmap |= SI91X_SOCKET_FEAT_SSL | SL_SI91X_TLS_V_1_2; + break; + } + + case SL_SI91X_SO_SOCK_VAP_ID: { + // Set the VAP ID for the socket + si91x_socket->vap_id = *((uint8_t *)option_value); + break; + } + +#ifdef SLI_SI917 + case SL_SI91X_SO_SSL_V_1_3_ENABLE: { + // Enable SSL version 1.3 for the socket. + SET_ERRNO_AND_RETURN_IF_TRUE(((*(uint8_t *)option_value) != (SI91X_SOCKET_FEAT_SSL | SL_SI91X_TLS_V_1_3)), + EINVAL); + si91x_socket->ssl_bitmap |= SI91X_SOCKET_FEAT_SSL | SL_SI91X_TLS_V_1_3; + break; + } +#endif + + // case si91x_SO_TCP_ACK_INDICATION:{ + // SET_ERRNO_AND_RETURN_IF_TRUE(*(uint8_t *)option_value !=SI91X_SOCKET_FEAT_TCP_ACK_INDICATION,EINVAL ); + // si91x_socket->ssl_bitmap |= SI91X_SOCKET_FEAT_TCP_ACK_INDICATION; + // break; + // } + case SL_SI91X_SO_CERT_INDEX: { + SET_ERRNO_AND_RETURN_IF_TRUE( + ((*(uint8_t *)option_value < SI91X_CERT_INDEX_0) || (*(uint8_t *)option_value > SI91X_CERT_INDEX_2)), + EINVAL); + + si91x_socket->certificate_index = *(uint8_t *)option_value; + break; + } + + case SL_SI91X_SO_TLS_SNI: { + sl_status_t status = add_server_name_indication_extension(&si91x_socket->sni_extensions, + (si91x_socket_type_length_value_t *)option_value); + + if (status != SL_STATUS_OK) { + SET_ERROR_AND_RETURN(ENOMEM); + } + break; + } + +#ifdef SLI_SI917 + case SL_SI91X_SO_MAX_RETRANSMISSION_TIMEOUT_VALUE: { + if (IS_POWER_OF_TWO((*(uint8_t *)option_value)) && ((*(uint8_t *)option_value) < MAX_RETRANSMISSION_TIME_VALUE)) { + memcpy(&si91x_socket->max_retransmission_timeout_value, + (uint8_t *)option_value, + GET_SAFE_MEMCPY_LENGTH(sizeof(si91x_socket->max_retransmission_timeout_value), option_len)); + } else { + SL_DEBUG_LOG("\n Max retransmission timeout value in between 1 - 32 and " + "should be power of two. ex:1,2,4,8,16,32 \n"); + SET_ERROR_AND_RETURN(EINVAL); + } + break; + } +#endif + default: { + // Invalid socket option + SET_ERROR_AND_RETURN(ENOPROTOOPT); + } + } + return SI91X_NO_ERROR; +} + +int sl_si91x_send(int socket, const uint8_t *buffer, size_t buffer_length, int32_t flags) +{ + return sl_si91x_send_async(socket, buffer, buffer_length, flags, NULL); +} + +int sl_si91x_send_async(int socket, + const uint8_t *buffer, + size_t buffer_length, + int32_t flags, + data_transfer_complete_handler callback) +{ + return sl_si91x_sendto_async(socket, (uint8_t *)buffer, buffer_length, flags, NULL, 0, callback); +} + +int sl_si91x_sendto(int socket, + uint8_t *buffer, + size_t buffer_length, + int32_t flags, + const struct sockaddr *addr, + socklen_t addr_len) +{ + return sl_si91x_sendto_async(socket, buffer, buffer_length, flags, addr, addr_len, NULL); +} + +int sl_si91x_send_large_data(int socket, const uint8_t *buffer, size_t buffer_length, int32_t flags) +{ + si91x_socket_t *si91x_socket = get_si91x_socket(socket); + int bsd_ret_code = 0; + size_t offset = 0; + size_t chunk_size = 0; + size_t max_len = 0; + + SET_ERRNO_AND_RETURN_IF_TRUE(si91x_socket == NULL, EBADF); + SET_ERRNO_AND_RETURN_IF_TRUE(si91x_socket->state == RESET || si91x_socket->state == INITIALIZED, EBADF); + SET_ERRNO_AND_RETURN_IF_TRUE(buffer == NULL, EFAULT); + + // Find maximum limit based on the protocol + if (si91x_socket->type == SOCK_STREAM && si91x_socket->ssl_bitmap & SL_SI91X_ENABLE_TLS) { + max_len = (si91x_socket->local_address.sin6_family == AF_INET) ? si91x_socket->mss - SI91X_SSL_HEADER_SIZE_IPV4 + : si91x_socket->mss - SI91X_SSL_HEADER_SIZE_IPV6; + } else if (si91x_socket->type == SOCK_DGRAM) { + max_len = (si91x_socket->local_address.sin6_family == AF_INET) ? DEFAULT_DATAGRAM_MSS_SIZE_IPV4 + : DEFAULT_DATAGRAM_MSS_SIZE_IPV6; + } else { + max_len = (si91x_socket->local_address.sin6_family == AF_INET) ? DEFAULT_STREAM_MSS_SIZE_IPV4 + : DEFAULT_STREAM_MSS_SIZE_IPV6; + } + + while (offset < buffer_length) { + chunk_size = (max_len < (buffer_length - offset)) ? max_len : (buffer_length - offset); + // Send chunk of data and return the total data sent in successful case + bsd_ret_code = sl_si91x_send_async(socket, buffer + offset, chunk_size, flags, NULL); + if (bsd_ret_code < 0) { + SL_DEBUG_LOG("\n Send failed with error code 0x%X \n", errno); + break; + } else { + offset += bsd_ret_code; + } + } + return offset; +} + +int sl_si91x_sendto_async(int socket, + uint8_t *buffer, + size_t buffer_length, + int32_t flags, + const struct sockaddr *to_addr, + socklen_t to_addr_len, + data_transfer_complete_handler callback) +{ + + UNUSED_PARAMETER(flags); + sl_status_t status = SL_STATUS_OK; + si91x_socket_t *si91x_socket = get_si91x_socket(socket); + sl_si91x_socket_send_request_t request = { 0 }; + + // Check if the socket is valid + SET_ERRNO_AND_RETURN_IF_TRUE(si91x_socket == NULL, EBADF); + SET_ERRNO_AND_RETURN_IF_TRUE(si91x_socket->type == SOCK_STREAM && si91x_socket->state != CONNECTED, ENOTCONN); + SET_ERRNO_AND_RETURN_IF_TRUE(buffer == NULL, EFAULT); + SET_ERRNO_AND_RETURN_IF_TRUE(si91x_socket->state != CONNECTED && to_addr == NULL, EFAULT); + + // Set the data transfer callback for this socket + si91x_socket->data_transfer_callback = callback; + + // Check message size depending on socket type + if (si91x_socket->type == SOCK_STREAM) { + if (si91x_socket->ssl_bitmap & SL_SI91X_ENABLE_TLS) { + // For SOCK_STREAM (TCP), consider SSL overhead if TLS is enabled + size_t max_size = (si91x_socket->local_address.sin6_family == AF_INET) + ? si91x_socket->mss - SI91X_SSL_HEADER_SIZE_IPV4 + : si91x_socket->mss - SI91X_SSL_HEADER_SIZE_IPV6; + SET_ERRNO_AND_RETURN_IF_TRUE(buffer_length > max_size, EMSGSIZE); + } else { + size_t max_size = (si91x_socket->local_address.sin6_family == AF_INET) ? DEFAULT_STREAM_MSS_SIZE_IPV4 + : DEFAULT_STREAM_MSS_SIZE_IPV6; + SET_ERRNO_AND_RETURN_IF_TRUE(buffer_length > max_size, EMSGSIZE); + } + } else if (si91x_socket->type == SOCK_DGRAM) { + // For SOCK_DGRAM (UDP), check the message size against the default maximum size + size_t max_size = (si91x_socket->local_address.sin6_family == AF_INET) ? DEFAULT_DATAGRAM_MSS_SIZE_IPV4 + : DEFAULT_DATAGRAM_MSS_SIZE_IPV6; + SET_ERRNO_AND_RETURN_IF_TRUE(buffer_length > max_size, EMSGSIZE); + } + + if (si91x_socket->type == SOCK_DGRAM && (si91x_socket->state == BOUND || si91x_socket->state == INITIALIZED)) { + sl_status_t status = create_and_send_socket_request(socket, SI91X_SOCKET_LUDP, NULL); + + SET_ERRNO_AND_RETURN_IF_TRUE(status != SL_STATUS_OK, SI91X_UNDEFINED_ERROR); + si91x_socket->state = UDP_UNCONNECTED_READY; + } + + SET_ERRNO_AND_RETURN_IF_TRUE(si91x_socket->type == SOCK_DGRAM && si91x_socket->state != CONNECTED + && si91x_socket->state != UDP_UNCONNECTED_READY, + EBADF); + + SET_ERRNO_AND_RETURN_IF_TRUE( + si91x_socket->state == UDP_UNCONNECTED_READY + && ((si91x_socket->local_address.sin6_family == AF_INET && to_addr_len < sizeof(struct sockaddr_in)) + || (si91x_socket->local_address.sin6_family == AF_INET6 && to_addr_len < sizeof(struct sockaddr_in6))), + EINVAL) + + // create a socket send request + if (si91x_socket->local_address.sin6_family == AF_INET6) { + // If the socket uses IPv6, set the IP version and destination IPv6 address + struct sockaddr_in6 *socket_address = (struct sockaddr_in6 *)to_addr; + request.ip_version = SL_IPV6_ADDRESS_LENGTH; + request.data_offset = (si91x_socket->type == SOCK_STREAM) ? TCP_V6_HEADER_LENGTH : UDP_V6_HEADER_LENGTH; + uint8_t *destination_ip = + (si91x_socket->state == UDP_UNCONNECTED_READY || to_addr_len >= sizeof(struct sockaddr_in6)) + ? socket_address->sin6_addr.__u6_addr.__u6_addr8 + : si91x_socket->remote_address.sin6_addr.__u6_addr.__u6_addr8; + + memcpy(&request.dest_ip_addr.ipv6_address[0], destination_ip, SL_IPV6_ADDRESS_LENGTH); + } else { + // If the socket uses IPv4, set the IP version and destination IPv4 address + struct sockaddr_in *socket_address = (struct sockaddr_in *)to_addr; + request.ip_version = SL_IPV4_ADDRESS_LENGTH; + request.data_offset = (si91x_socket->type == SOCK_STREAM) ? TCP_HEADER_LENGTH : UDP_HEADER_LENGTH; + uint32_t *destination_ip = + (si91x_socket->state == UDP_UNCONNECTED_READY || to_addr_len >= sizeof(struct sockaddr_in)) + ? &socket_address->sin_addr.s_addr + : &((struct sockaddr_in *)&si91x_socket->remote_address)->sin_addr.s_addr; + + memcpy(&request.dest_ip_addr.ipv4_address[0], destination_ip, SL_IPV4_ADDRESS_LENGTH); + } + // Set other parameters in the send request + request.socket_id = si91x_socket->id; + request.dest_port = ((si91x_socket->state == UDP_UNCONNECTED_READY || to_addr_len > 0)) + ? ((struct sockaddr_in *)to_addr)->sin_port + : si91x_socket->remote_address.sin6_port; + request.length = buffer_length; + + // Send the socket data + status = sl_si91x_driver_send_socket_data(&request, buffer, 0); + SOCKET_VERIFY_STATUS_AND_RETURN(status, SL_STATUS_OK, ENOBUFS); + + return buffer_length; +} + +int sl_si91x_recv(int socket, uint8_t *buf, size_t buf_len, int32_t flags) +{ + return recvfrom(socket, buf, buf_len, flags, NULL, NULL); +} + +int sl_si91x_recvfrom(int socket, + uint8_t *buf, + size_t buf_len, + int32_t flags, + struct sockaddr *addr, + socklen_t *addr_len) +{ + UNUSED_PARAMETER(flags); + + // Initialize variables for socket communication + sl_si91x_wait_period_t wait_time = 0; + sl_si91x_req_socket_read_t request = { 0 }; + uint32_t event = NCP_HOST_SOCKET_RESPONSE_EVENT; + ssize_t bytes_read = 0; + si91x_rsp_socket_recv_t *response = NULL; + si91x_socket_t *si91x_socket = get_si91x_socket(socket); + sl_wifi_buffer_t *buffer = NULL; + void *sdk_context = NULL; + + // Check if the socket is valid + SET_ERRNO_AND_RETURN_IF_TRUE(si91x_socket == NULL, EBADF); + SET_ERRNO_AND_RETURN_IF_TRUE(si91x_socket->type == SOCK_STREAM && si91x_socket->state != CONNECTED, ENOTCONN); + + // Check if the buffer pointer is valid + SET_ERRNO_AND_RETURN_IF_TRUE(buf == NULL, EFAULT); + + // Check if the specified buffer length is valid + SET_ERRNO_AND_RETURN_IF_TRUE(buf_len <= 0, EINVAL) + + // create and send a socket request to configure it as UDP. + if (si91x_socket->type == SOCK_DGRAM && (si91x_socket->state == BOUND || si91x_socket->state == INITIALIZED)) { + int bsd_status = create_and_send_socket_request(socket, SI91X_SOCKET_LUDP, NULL); + SOCKET_VERIFY_STATUS_AND_RETURN(bsd_status, SI91X_NO_ERROR, SI91X_UNDEFINED_ERROR); + + si91x_socket->state = UDP_UNCONNECTED_READY; + } + + // Possible states are only reset and disconnected. + SET_ERRNO_AND_RETURN_IF_TRUE(si91x_socket->state != CONNECTED && si91x_socket->state != UDP_UNCONNECTED_READY, EBADF) + + // Limit the buffer length based on the socket type + if (si91x_socket->type == SOCK_STREAM) { + if (buf_len > DEFAULT_STREAM_MSS_SIZE_IPV4 || buf_len > DEFAULT_STREAM_MSS_SIZE_IPV6) + buf_len = (si91x_socket->local_address.sin6_family == AF_INET) ? DEFAULT_DATAGRAM_MSS_SIZE_IPV4 + : DEFAULT_DATAGRAM_MSS_SIZE_IPV6; + } else if (si91x_socket->type == SOCK_DGRAM) { + if (buf_len > DEFAULT_STREAM_MSS_SIZE_IPV4 || buf_len > DEFAULT_STREAM_MSS_SIZE_IPV6) + buf_len = (si91x_socket->local_address.sin6_family == AF_INET) ? DEFAULT_DATAGRAM_MSS_SIZE_IPV4 + : DEFAULT_DATAGRAM_MSS_SIZE_IPV6; + } + + // Initialize the socket read request with the socket ID and requested buffer length + request.socket_id = si91x_socket->id; + sdk_context = &(request.socket_id); + memcpy(request.requested_bytes, &buf_len, sizeof(buf_len)); + wait_time = (SL_SI91X_WAIT_FOR_EVER | SL_SI91X_WAIT_FOR_RESPONSE_BIT); + + sl_status_t status = sl_si91x_socket_driver_send_command(RSI_WLAN_REQ_SOCKET_READ_DATA, + &request, + sizeof(request), + SI91X_SOCKET_CMD_QUEUE, + SI91X_SOCKET_RESPONSE_QUEUE, + &buffer, + (void *)&response, + &event, + &wait_time, + sdk_context); + + // If the command failed and a buffer was allocated, free the buffer + if ((status != SL_STATUS_OK) && (buffer != NULL)) { + sl_si91x_host_free_buffer(buffer); + } + + SOCKET_VERIFY_STATUS_AND_RETURN(status, SL_STATUS_OK, SI91X_UNDEFINED_ERROR) + + // Determine the number of bytes read, considering the buffer length and response length + bytes_read = (response->length <= buf_len) ? response->length : buf_len; + memcpy(buf, ((uint8_t *)response + response->offset), bytes_read); + + // If address information is provided, populate it based on the IP version + if (addr != NULL) { + if (response->ip_version == SL_IPV4_ADDRESS_LENGTH && *addr_len >= sizeof(struct sockaddr_in)) { + struct sockaddr_in *socket_address = (struct sockaddr_in *)addr; + + socket_address->sin_port = response->dest_port; + socket_address->sin_family = AF_INET; + memcpy(&socket_address->sin_addr.s_addr, response->dest_ip_addr.ipv4_address, SL_IPV4_ADDRESS_LENGTH); + + *addr_len = sizeof(struct sockaddr_in); + } else if (response->ip_version == SL_IPV6_ADDRESS_LENGTH && *addr_len >= sizeof(struct sockaddr_in6)) { + struct sockaddr_in6 *ipv6_socket_address = ((struct sockaddr_in6 *)addr); + + ipv6_socket_address->sin6_port = response->dest_port; + ipv6_socket_address->sin6_family = AF_INET; + memcpy(&ipv6_socket_address->sin6_addr.__u6_addr.__u6_addr8, + response->dest_ip_addr.ipv6_address, + SL_IPV6_ADDRESS_LENGTH); + + *addr_len = sizeof(struct sockaddr_in6); + } else { + *addr_len = 0; + } + } + + sl_si91x_host_free_buffer(buffer); + + return bytes_read; +} + +int sl_si91x_select(int nfds, + fd_set *readfds, + fd_set *writefds, + fd_set *exceptfds, + struct timeval *timeout, + select_callback callback) +{ + UNUSED_PARAMETER(exceptfds); + + sl_status_t status = SL_STATUS_OK; + + // Define a structure to hold the select request parameters + sl_si91x_socket_select_req_t request = { 0 }; + + // Check if all file descriptor sets are NULL + // exceptfds are not being checked as firmware doesn't support it. + if ((readfds == NULL) && (writefds == NULL)) { + SET_ERROR_AND_RETURN(EINVAL); // Invalid argument, no sets specified + } + // Check if the number of file descriptors (nfds) is within a valid range + if (nfds < 0 || nfds > NUMBER_OF_BSD_SOCKETS) { + SET_ERROR_AND_RETURN(EINVAL); // Invalid argument, nfds out of range + } + + // Check if the provided timeout is valid + if ((timeout != NULL) && ((timeout->tv_sec < 0) || (timeout->tv_usec < 0))) { + SET_ERROR_AND_RETURN(EINVAL); // Invalid argument, negative timeout + } + + // Set the select callback function to be called upon completion + set_select_callback(callback); + + // Loop through file descriptor sets and populate the select request structure + for (uint8_t host_socket_index = 0; host_socket_index < nfds; host_socket_index++) { + + // Retrieve the si91x_socket associated with the host socket index + si91x_socket_t *socket = get_si91x_socket(host_socket_index); + + // Throw error if the socket file descriptor set by developer is not valid + if (socket == NULL + && ((readfds != NULL && FD_ISSET(host_socket_index, readfds)) + || (writefds != NULL && FD_ISSET(host_socket_index, writefds)))) { + SET_ERROR_AND_RETURN(EBADF); + } + + // If the socket is NULL, continue to iterate through other sockets. + // The code will reach this if clause in the case of a socket being NULL and the socket being neither set in readfds nor writefds. + if (socket == NULL) { + continue; + } + + if (readfds != NULL) { + // Check if the socket is set for read operations in the readfds set + if (FD_ISSET(host_socket_index, readfds)) { + // Set the corresponding bit in the read file descriptor set + request.read_fds.fd_array[0] |= (1U << socket->id); + } + } + + if (writefds != NULL) { + // Check if the socket is set for write operations in the writefds set + if (FD_ISSET(host_socket_index, writefds)) { + // Set the corresponding bit in the write file descriptor set + request.write_fds.fd_array[0] |= (1U << socket->id); + } + } + + // Update the maximum file descriptor number encountered + if (request.num_fd <= socket->id) { + request.num_fd = socket->id + 1; + } + } + + // Check if a timeout value is provided + if (timeout != NULL && ((timeout->tv_sec != 0) || (timeout->tv_usec != 0))) { + request.select_timeout.tv_sec = timeout->tv_sec; + request.select_timeout.tv_usec = timeout->tv_usec; + } else { + // Indicate that there is no timeout specified + request.no_timeout = 1; + } + + status = + sl_si91x_driver_send_async_command(RSI_WLAN_REQ_SELECT_REQUEST, SI91X_SOCKET_CMD_QUEUE, &request, sizeof(request)); + + SOCKET_VERIFY_STATUS_AND_RETURN(status, SL_STATUS_OK, SI91X_UNDEFINED_ERROR); + + return SI91X_NO_ERROR; +} diff --git a/wiseconnect/components/device/silabs/si91x/wireless/host_mcu/si91x/siwx917_soc_ncp_host.c b/wiseconnect/components/device/silabs/si91x/wireless/host_mcu/si91x/siwx917_soc_ncp_host.c new file mode 100644 index 000000000..0afa4f5f9 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/host_mcu/si91x/siwx917_soc_ncp_host.c @@ -0,0 +1,132 @@ +/******************************************************************************* +* @file siwx917_soc_ncp_host.c +* @brief +******************************************************************************* +* # License +* Copyright 2020 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +#include "sl_wifi_constants.h" +#include "sl_si91x_host_interface.h" +#include "sl_board_configuration.h" +#include "sl_status.h" +#include "sl_constants.h" +#include "os_tick.h" // CMSIS RTOS2 +#include "cmsis_os2.h" // CMSIS RTOS2 +#include "sl_si91x_types.h" +#include +#include +#include "rsi_m4.h" +#include "sl_common.h" +#include "si91x_device.h" +#include "core_cm4.h" + +extern int16_t rsi_mem_rd(uint32_t addr, uint16_t len, uint8_t *dBuf); +void sl_si91x_ta_events_init(void); +sl_status_t sl_si91x_bus_init(void); +sl_status_t sl_si91x_bus_set_interrupt_mask(uint32_t mask); +sl_status_t sl_si91x_bus_enable_high_speed(void); +sl_status_t sl_si91x_bus_write_memory(uint32_t addr, uint16_t length, const uint8_t *buffer); +sl_status_t sl_si91x_bus_read_memory(uint32_t addr, uint16_t length, uint8_t *buffer); + +void sl_si91x_host_enable_high_speed_bus() +{ + //! Sets specific control register bits + //! Sets the baud rate +} + +sl_status_t sl_si91x_bus_rx_irq_handler(void) +{ + return SL_STATUS_OK; +} + +void sl_si91x_bus_rx_done_handler(void) +{ + return; +} + +sl_status_t sl_si91x_bus_init(void) +{ + return RSI_SUCCESS; +} + +sl_status_t sl_si91x_bus_set_interrupt_mask(uint32_t mask) +{ + UNUSED_PARAMETER(mask); + return SL_STATUS_OK; +} + +sl_status_t sl_si91x_bus_enable_high_speed(void) +{ + return SL_STATUS_OK; +} + +void sl_si91x_host_set_sleep_indicator(void) +{ + // sets a sleep indicator by activating a specific GPIO pin +} + +uint32_t sl_si91x_host_get_wake_indicator(void) +{ + return 1; +} + +sl_status_t sl_si91x_host_init(sl_si91x_host_init_configuration *config) +{ + UNUSED_PARAMETER(config); + // Initialize SI91X TA events + sl_si91x_ta_events_init(); + return SL_STATUS_OK; +} + +sl_status_t sl_si91x_host_deinit(void) +{ + return SL_STATUS_OK; +} + +void sl_si91x_host_hold_in_reset(void) +{ + // initializes and activates a GPIO pin to forcefully reset or disable a connected device. +} + +void sl_si91x_host_release_from_reset(void) +{ + // Release the reset state of a connected device +} + +void sl_si91x_host_enable_bus_interrupt(void) +{ + // allowing the system to respond to specific events +} + +void sl_si91x_host_disable_bus_interrupt(void) +{ + // Preventing the system from responding to events +} + +sl_status_t sl_si91x_bus_write_memory(uint32_t addr, uint16_t length, const uint8_t *buffer) +{ + UNUSED_PARAMETER(length); + *(uint32_t *)addr = *(uint32_t *)buffer; + return 0; +} + +sl_status_t sl_si91x_bus_read_memory(uint32_t addr, uint16_t length, uint8_t *buffer) +{ + // Read memory + rsi_mem_rd(addr, length, buffer); + return 0; +} +bool sl_si91x_host_is_in_irq_context(void) +{ + return (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) != 0U; +} diff --git a/wiseconnect/components/device/silabs/si91x/wireless/inc/sl_rsi_utility.h b/wiseconnect/components/device/silabs/si91x/wireless/inc/sl_rsi_utility.h new file mode 100644 index 000000000..da09d0f9b --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/inc/sl_rsi_utility.h @@ -0,0 +1,420 @@ +/***************************************************************************/ /** + * @file + * @brief + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#pragma once + +#ifndef _SL_RSI_UTILITY_H_ +#define _SL_RSI_UTILITY_H_ + +#include +#include +#include +#include "sl_status.h" +#include "sl_constants.h" +#include "sl_wifi_constants.h" +#include "sl_si91x_host_interface.h" +#include "sl_si91x_protocol_types.h" +#include "sl_utility.h" +#include "sl_si91x_driver.h" +#include "sl_wifi_device.h" +#include "sl_si91x_types.h" + +#define NCP_HOST_COMMON_RESPONSE_EVENT (1 << 3) // Indicates RX response received for COMMON command type +#define NCP_HOST_WLAN_RESPONSE_EVENT (1 << 4) // Indicates synchronous RX response received for WLAN command type +#define NCP_HOST_WLAN_NOTIFICATION_EVENT (1 << 5) // Indicates asynchronous RX response received for WLAN command type +#define NCP_HOST_NETWORK_RESPONSE_EVENT (1 << 6) // Indicates synchronous RX response received for NETWORK command type +#define NCP_HOST_NETWORK_NOTIFICATION_EVENT \ + (1 << 7) // Indicates asynchronous RX response received for NETWORK command type +#define NCP_HOST_SOCKET_RESPONSE_EVENT (1 << 8) // Indicates RX response received for SOCKET command type +#define NCP_HOST_SOCKET_NOTIFICATION_EVENT \ + (1 << 9) // Indicates asynchronous RX response received for SOCKET command type +#define NCP_HOST_BT_RESPONSE_EVENT (1 << 10) // Indicates RX response received for BLE command type + +/// Low Transmit Power Threshold for Wi-Fi. +#define SI91X_LOW_TRANSMIT_POWER_THRESHOLD 6 + +/// Medium Transmit Power Threshold for Wi-Fi. +#define SI91X_MEDIUM_TRANSMIT_POWER_THRESHOLD 4 + +typedef struct { + sl_wifi_performance_profile_t wifi_performance_profile; + sl_bt_performance_profile_t bt_performance_profile; + sl_si91x_coex_mode_t coex_mode; +} sli_si91x_performance_profile_t; + +/// Efuse data information +typedef union { + uint8_t mfg_sw_version; ///< Manufacturing PTE software version + uint16_t pte_crc; ///< PTE CRC value +} sl_si91x_efuse_data_t; + +/// \details Mutex ID identifies the mutex. +typedef void *osMutexId_t; + +// Structure to represent a packet queue +typedef struct { + sl_wifi_buffer_t *head; + sl_wifi_buffer_t *tail; + osMutexId_t mutex; + uint32_t flag; + uint32_t queued_packet_count; +} si91x_packet_queue_t; + +typedef uint32_t sl_si91x_host_timestamp_t; + +typedef void (*sl_si91x_host_atomic_action_function_t)(void *user_data); +typedef uint8_t (*sl_si91x_compare_function_t)(sl_wifi_buffer_t *node, void *user_data); +typedef void (*sl_si91x_node_free_function_t)(sl_wifi_buffer_t *node); + +extern sl_si91x_performance_profile_t current_performance_profile; /*Indicates the current performance profile*/ + +sl_status_t convert_si91x_wifi_client_info( + sl_wifi_client_info_response_t *client_info_response, + sl_si91x_client_info_response *sl_si91x_client_info_response); /*Function converts TA client info to SDK client info*/ +sl_wifi_event_t convert_si91x_event_to_sl_wifi_event( + rsi_wlan_cmd_response_t command, + uint16_t frame_status); /*Function converts TA events to SDK events*/ + +sl_status_t save_sl_wifi_rate( + sl_wifi_rate_t transfer_rate); /*Function used to update the variable that stores the wifi rate*/ +sl_status_t get_saved_sl_wifi_rate(sl_wifi_rate_t *transfer_rate); /*Function used to retrieve the wifi rate*/ +void reset_sl_wifi_rate(); /*Function used to set wifi rate to default value of 1 Mbps*/ + +sl_status_t get_rate_protocol_and_data_rate( + const uint8_t data_rate, + sl_wifi_rate_protocol_t *rate_protocol, + sl_wifi_rate_t *transfer_rate); /*Function used to retrieve protocol and transfer rate*/ + +sl_status_t save_ap_configuration( + const sl_wifi_ap_configuration_t *wifi_ap_configuration); /*Function used to update the access point configuration*/ +sl_status_t get_saved_ap_configuration( + sl_wifi_ap_configuration_t *wifi_ap_confuguration); /*Function used to retrieve the access point configuration*/ +void reset_ap_configuration(); /*Function used to destroy the current access point configuration*/ + +void save_tcp_auto_close_choice( + bool is_tcp_auto_close_enabled); /*Function used to set whether tcp auto close is enabled or disabled*/ +bool is_tcp_auto_close_enabled(); /*Function used to check whether tcp auto close is enabled or disabled*/ +void set_card_ready_required(bool card_ready_required); /*Function used to set whether card ready is required or not*/ +bool get_card_ready_required(); /*Function used to check whether card ready is required or not*/ + +void save_max_tx_power(uint8_t max_scan_tx_power, + uint8_t max_join_tx_power); /*Function used to set the maximum transmission power*/ +sl_wifi_max_tx_power_t get_max_tx_power(); /*Function used to get maximum transmission power*/ +void reset_max_tx_power(); /*Function used to set maximum transmission power to default value(31dBm) */ + +void save_wifi_current_performance_profile( + const sl_wifi_performance_profile_t *profile); /*Function used to set the current performance profile*/ +void get_wifi_current_performance_profile( + sl_wifi_performance_profile_t *profile); /*Function used to get current wifi performance profile*/ + +void save_bt_current_performance_profile( + const sl_bt_performance_profile_t *profile); /*Function used to set the bluetooth performance profile*/ +void get_bt_current_performance_profile( + sl_bt_performance_profile_t *profile); /*Function used to retrieve bluetooth performance profile*/ + +void get_coex_performance_profile( + sl_si91x_performance_profile_t *profile); /*Function used to retrieve the coex performance profile*/ +void reset_coex_current_performance_profile(void); /*Function used to zero out the coex performance profile */ + +void save_boot_configuration( + const sl_si91x_boot_configuration_t *boot_configuration); /*Function used to update the boot configuration*/ +void get_saved_boot_configuration( + sl_si91x_boot_configuration_t *boot_configuration); /*Function used to retrieve the boot configuration*/ + +void save_coex_mode(sl_si91x_coex_mode_t coex_mode); /*Function used to update the coex mode*/ +sl_si91x_coex_mode_t get_coex_mode(void); /*Function used to retrieve the coex mode*/ + +sl_status_t convert_sl_wifi_to_sl_si91x_encryption( + sl_wifi_encryption_t encryption_mode, + uint8_t *encryption_request); /*Function converts SDK encryption mode to TA supported mode*/ + +/********************************************************************************************* + * @brief + * An utility function computes coex performance profile internally and converts into sl_si91x_power_save_request_t. + * @param profile + * performance profile which needs to be converted to its equivalent si91x_power_save_request structure. + * @param power_save_request + * si91x specific structure that holds required configuration for the given performance profile. + * This is optional parameter. + * @return coex_profile + * Coex power profile + * @return + * sl_status_t + *********************************************************************************************/ +sl_status_t sl_si91x_send_power_save_request(sl_si91x_performance_profile_t profile); + +/***************************************************************************/ /** + * @brief + * Get the Efuse Data content from flash. + * @pre Pre-conditions: + * - + * @ref sl_wifi_init should be called before this API. + * @param[out] efuse_data + * @ref sl_si91x_efuse_data_t object that contains the Manufacturing software version. + * efuse_data_type which holds the type of efuse data to be read. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + * @note + * This API is not supported in the current release. + ******************************************************************************/ +sl_status_t sl_si91x_get_flash_efuse_data(sl_si91x_efuse_data_t *efuse_data, uint8_t efuse_data_type); + +/***************************************************************************/ /** + * @brief + * Get the Efuse Data content from driver context. + * @pre Pre-conditions: + * - + * @ref sl_wifi_init should be called before this API. + * @param[out] efuse_data + * @ref sl_si91x_efuse_data_t object that contains the Manufacturing software version. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + ******************************************************************************/ +void sl_si91x_get_efuse_data(sl_si91x_efuse_data_t *efuse_data); + +/***************************************************************************/ /** + * @brief + * Set the Efuse Data content in driver context. + * @pre Pre-conditions: + * - + * @ref sl_wifi_init should be called before this API. + * @param[out] efuse_data + * @ref sl_si91x_efuse_data_t object that contains the Manufacturing software version. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + ******************************************************************************/ +void sl_si91x_set_efuse_data(const sl_si91x_efuse_data_t *efuse_data); + +/** + * An utility function to convert dBm value to si91x specific power value + * @param wifi_max_tx_power which holds the join power value with dBm as units. + * @return si91x power level + */ +static inline uint8_t convert_dbm_to_si91x_power_level(sl_wifi_max_tx_power_t wifi_max_tx_power) +{ + uint8_t power_value_in_dBm = wifi_max_tx_power.join_tx_power; + if (power_value_in_dBm >= SI91X_LOW_TRANSMIT_POWER_THRESHOLD) { + return SL_SI91X_LOW_POWER_LEVEL; + } else if (power_value_in_dBm >= SI91X_MEDIUM_TRANSMIT_POWER_THRESHOLD) { + return SL_SI91X_MEDIUM_POWER_LEVEL; + } else { + return SL_SI91X_HIGH_POWER_LEVEL; + } +} + +sl_status_t sl_si91x_platform_init(void); +sl_status_t sl_si91x_platform_deinit(void); + +/** +* @addtogroup EXTERNAL_HOST_INTERFACE_FUNCTIONS +* @{ +*/ + +/** + * @brief This API used to block MCU for specified time. + * + * @param[in] delay_milliseconds + * time delay in milliseconds + */ +void sl_si91x_host_delay_ms(uint32_t delay_milliseconds); + +/** + * @brief It retrieves a timestamp. + * + * @return sl_si91x_host_timestamp_t + */ +sl_si91x_host_timestamp_t sl_si91x_host_get_timestamp(void); + +/** + * @brief This API calculates the timestamp difference. + * + * @param[in] starting_timestamp + * This parameter is used to calculate the elapsed time. + * + * @return sl_si91x_host_timestamp_t + */ +sl_si91x_host_timestamp_t sl_si91x_host_elapsed_time(uint32_t starting_timestamp); + +/** @} */ + +// Event API +void sl_si91x_host_set_event(uint32_t event_mask); /*Function used to set specified flags for event*/ +void sl_si91x_host_set_bus_event(uint32_t event_mask); /*Function used to set specified flags for event*/ +void sl_si91x_host_set_async_event(uint32_t event_mask); /*Function used to set specified flags for event*/ +uint32_t si91x_host_wait_for_event(uint32_t event_mask, + uint32_t timeout); /*Function used to wait for specific event to occur*/ +uint32_t si91x_host_wait_for_bus_event(uint32_t event_mask, + uint32_t timeout); /*Function used to wait for specific event to occur*/ +uint32_t si91x_host_wait_for_async_event(uint32_t event_mask, + uint32_t timeout); /*Function used to wait for specific event to occur*/ +uint32_t si91x_host_clear_events(uint32_t event_mask); /*Function used to clear flags for specific event*/ +uint32_t si91x_host_clear_bus_events(uint32_t event_mask); /*Function used to clear flags for specific event*/ +uint32_t si91x_host_clear_async_events(uint32_t event_mask); /*Function used to clear flags for specific event*/ + +sl_status_t sl_si91x_host_init_buffer_manager(const sl_wifi_buffer_configuration_t *config); +sl_status_t sl_si91x_host_deinit_buffer_manager(void); +sl_status_t sl_si91x_host_allocate_buffer(sl_wifi_buffer_t **buffer, + sl_wifi_buffer_type_t type, + uint32_t buffer_size, + uint32_t wait_duration_ms); /*Function used to allocate memory*/ +void *sl_si91x_host_get_buffer_data( + sl_wifi_buffer_t *buffer, + uint16_t offset, + uint16_t *data_length); /*Function used to obtain pointer to a specified location in the buffer*/ +void sl_si91x_host_free_buffer( + sl_wifi_buffer_t *buffer); /*Function used to deallocate the memory associated with buffer*/ +// --------------- + +sl_status_t sl_si91x_host_add_to_queue( + sl_si91x_queue_type_t queue, + sl_wifi_buffer_t *buffer); /*Function enqueues response into corresponding response queue*/ +sl_status_t sl_si91x_host_add_to_queue_with_atomic_action( + sl_si91x_queue_type_t queue, + sl_wifi_buffer_t *buffer, + void *user_data, + sl_si91x_host_atomic_action_function_t handler); /*Function enqueues command into corresponding command queue*/ +sl_status_t sl_si91x_host_remove_from_queue( + sl_si91x_queue_type_t queue, + sl_wifi_buffer_t **buffer); /*Function dequeues responses from Asynch response queues*/ +sl_status_t sl_si91x_host_remove_node_from_queue( + sl_si91x_queue_type_t queue, + sl_wifi_buffer_t **buffer, + void *user_data, + sl_si91x_compare_function_t compare_function); /*Function dequeues response from Synch response queues*/ +/* Function used to flush the pending TX packets from the specified queue */ +sl_status_t sl_si91x_host_flush_nodes_from_queue(sl_si91x_queue_type_t queue, + void *user_data, + sl_si91x_compare_function_t compare_function, + sl_si91x_node_free_function_t node_free_function); + +/* Function used to flush all the pending TX packets from the specified queue */ +sl_status_t sl_si91x_flush_queue_based_on_type(sl_si91x_queue_type_t queue, + sl_si91x_node_free_function_t node_free_function); + +uint32_t sl_si91x_host_queue_status( + sl_si91x_queue_type_t queue); /*Function used to check whether queue is empty or not*/ + +uint32_t sl_si91x_host_get_queue_packet_count( + sl_si91x_queue_type_t queue); /*Function used to get the number of packets in the queue*/ + +// These aren't host APIs. These should go into a wifi bus API header +sl_status_t sl_si91x_bus_read_memory( + uint32_t addr, + uint16_t length, + uint8_t *buffer); /*Function used to set buffer pointer to point to specified memory address*/ +sl_status_t sl_si91x_bus_write_memory( + uint32_t addr, + uint16_t length, + const uint8_t *buffer); /*Function used to set specified memory address to point to buffer*/ +sl_status_t sl_si91x_bus_read_register(uint8_t address, + uint8_t register_size, + uint16_t *output); /*Function used to read contents of the register*/ +sl_status_t sl_si91x_bus_write_register(uint8_t address, + uint8_t register_size, + uint16_t data); /*Function used to write data into register*/ +sl_status_t sl_si91x_bus_read_frame(sl_wifi_buffer_t **buffer); /*Function used to read frame*/ +sl_status_t sl_si91x_bus_write_frame(sl_si91x_packet_t *packet, + const uint8_t *payloadparam, + uint16_t size_param); /*Function used to write frames*/ + +sl_status_t sl_si91x_bus_init(); /*Function used to check the bus availability */ +sl_status_t sl_si91x_bus_rx_irq_handler(void); /*Function used to check the bus availability */ +void sl_si91x_bus_rx_done_handler(void); /*Function used to check the bus availability */ + +/*==============================================*/ +/** + * @brief Calculate crc for a given byte and accumulate crc. + * @param[in] crc8_din - crc byte input + * @param[in] crc8_state - accumulated crc + * @param[in] end - last byte crc + * @return crc value + * + */ +uint8_t sli_lmac_crc8_c(uint8_t crc8_din, uint8_t crc8_state, uint8_t end); + +/*==============================================*/ +/** + * @brief Calculate 6-bit hash value for given mac address. + * @param[in] mac - pointer to mac address + * @return 6-bit Hash value + * + */ +uint8_t sli_multicast_mac_hash(uint8_t *mac); + +/*==============================================*/ +/** + * @brief Sends boot instructions to WiFi module + * @param[in] uint8 type, type of the insruction to perform + * @param[in] uint32 *data, pointer to data which is to be read/write + * @param[out] none + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + * @section description + * This API is used to send boot instructions to WiFi module. + **************************************************/ +sl_status_t sl_si91x_boot_instruction(uint8_t type, uint16_t *data); + +/***************************************************************************/ /** + * @brief + * The @ref sl_si91x_bus_enable_high_speed() should be called only if the SPI clock frequency is more than 25 MHz. + * @note + * SPI initialization has to be done in low-speed mode only. + * After device SPI is configured this API is been used for high-speed mode (>25 MHz). + * In addition to this API, the following API sl_si91x_host_enable_high_speed_bus has to be ported by the user to implement the host clock switch. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + ******************************************************************************/ +sl_status_t sl_si91x_bus_enable_high_speed(); /*Function used to start DMA channels for transmission and reception*/ + +sl_status_t sl_si91x_bus_read_interrupt_status( + uint16_t *interrupt_status); /*Function used to read the interrupt register*/ +sl_status_t sl_si91x_bus_set_interrupt_mask(uint32_t mask); /*Function used to block specified interrupts*/ + +void sl_si91x_ulp_wakeup_init(void); /*Function used to initialize SPI interface on ulp wakeup*/ + +/** + * @brief + * Function used to obtain wifi credential type like EsAP,PMK,etc.. + * @param id + * Credential ID as identified by [sl_wifi_credential_id_t](../wiseconnect-api-reference-guide-wi-fi/sl-wifi-types#sl-wifi-credential-id-t). + * @param type + * It specifies type of credential. + * @param cred + * Pointer to store the WiFi credential information of type [sl_wifi_credential_t](../wiseconnect-api-reference-guide-wi-fi/sl-wifi-credential-t) + * @return sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + */ +sl_status_t sl_si91x_host_get_credentials(sl_wifi_credential_id_t id, uint8_t type, sl_wifi_credential_t *cred); + +bool sli_si91x_get_flash_command_status(); + +void sli_si91x_update_flash_command_status(bool flag); + +bool sli_si91x_is_sdk_ok_to_sleep(); + +#endif // _SL_RSI_UTILITY_H_ diff --git a/wiseconnect/components/device/silabs/si91x/wireless/inc/sl_si91x_constants.h b/wiseconnect/components/device/silabs/si91x/wireless/inc/sl_si91x_constants.h new file mode 100644 index 000000000..33bc658ce --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/inc/sl_si91x_constants.h @@ -0,0 +1,717 @@ +/***************************************************************************/ /** + * @file + * @brief + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include +#pragma once + +/** \addtogroup SI91X_LOAD_IMAGE_TYPES + * @{ */ +// Load Image types +/// Load NWP firmware +#define LOAD_NWP_FW '1' + +/// Load default NWP firmware active low +#define LOAD_DEFAULT_NWP_FW_ACTIVE_LOW 0x71 +/** @} */ + +/** \addtogroup SI91X_TLS_DEFINE + * \ingroup SL_SI91X_CONSTANTS + * @{ */ +/*=========================================================================*/ +// TLS feature parameters description !// +/*=========================================================================*/ +/// Bit to enable SSL feature +#define SL_SI91X_ENABLE_TLS BIT(0) + +/// Bitmap to enable TLS version 1.0 +#define SL_SI91X_TLS_V_1_0 BIT(2) + +/// Bitmap to enable TLS version 1.2 +#define SL_SI91X_TLS_V_1_2 BIT(3) + +/// Bitmap to enable TLS version 1.1 +#define SL_SI91X_TLS_V_1_1 BIT(4) + +#ifdef SLI_SI917 +/// Bitmap to enable TLS version 1.3 +#define SL_SI91X_TLS_V_1_3 BIT(8) +#endif +/** @} */ + +/** \addtogroup SI91X_HTTP_CLIENT_DEFINE + * \ingroup SL_SI91X_CONSTANTS + * @{ */ +/*=========================================================================*/ +// HTTP Client feature parameters description !// +/*=========================================================================*/ +/// Bit to enable NULL delimiter for HTTP buffer instead of comma +#define SL_SI91X_ENABLE_NULL_DELIMETER BIT(1) + +/// HTTP client post big data support feature bitmap +#define SL_SI91X_SUPPORT_HTTP_POST_DATA BIT(5) + +/// HTTP version 1.1 support feature bitmap +#define SL_SI91X_HTTP_V_1_1 BIT(6) + +/// Bit to enable user given content type in extended header +#define SL_SI91X_HTTP_USER_DEFINED_CONTENT_TYPE BIT(7) + +/// To specify index of SSL cert to be used for HTTPS, for index 0 leave them unset +#define SL_SI91X_HTTPS_CERTIFICATE_INDEX_1 BIT(9) +/// To specify index of SSL cert to be used for HTTPS, for index 0 leave them unset +#define SL_SI91X_HTTPS_CERTIFICATE_INDEX_2 BIT(10) + +/// To enable SNI +#define SL_SI91X_HTTPS_USE_SNI BIT(11) +/** @} */ + +// Upgrade images +#define BURN_NWP_FW 'B' + +// Bootloader selects default NWP FW image number +#define SELECT_DEFAULT_NWP_FW_IMAGE_NUMBER '5' + +#define RSI_PING_PONG_CHUNK_SIZE 4096 +#define RSI_REG_READ 0xD1 +#define RSI_REG_WRITE 0xD2 +#define RSI_SEND_RPS_FILE '2' +#define RSI_FWUP_SUCCESSFUL 'S' +#define RSI_EOF_REACHED 'E' +#define RSI_PONG_VALID 'O' +#define RSI_PING_VALID 'I' +#define RSI_PONG_WRITE 0xD4 +#define RSI_PING_WRITE 0xD5 +#define RSI_PONG_AVAIL 'O' +#define RSI_PING_AVAIL 'I' + +#define RSI_PING_BUFFER_ADDR 0x418000 +#define RSI_PONG_BUFFER_ADDR 0x419000 + +#define RSI_ACTIVE_LOW_INTR 0x2 +#define RSI_ACTIVE_HIGH_INTR 0x0 + +#define RSI_OPERMODE_RESPONSE_WAIT_TIME (1000) // Milliseconds +#define RSI_SEND_RAW_DATA_RESPONSE_WAIT_TIME (1000) // Milliseconds + +#ifndef SL_WIFI_ALLOCATE_COMMAND_BUFFER_WAIT_TIME +#define SL_WIFI_ALLOCATE_COMMAND_BUFFER_WAIT_TIME 1000 // 1 second to wait for a command buffer +#endif + +//STM 32 Init Sequence +#define SL_SI91X_INIT_CMD 0x005c4a12 + +// SPI transfer type (8 BIT/32 BIT) +#define RSI_MODE_8BIT 0 +#define RSI_MODE_32BIT 1 + +// frame descriptor length +#define RSI_FRAME_DESC_LEN 16 + +// SPI interrupt register values +// Are these the same as other buses? +// buffer full indication register value from module +#ifndef RSI_BUFFER_FULL +#define RSI_BUFFER_FULL 0x01 +#endif +// buffer empty indication register value from module +#define RSI_BUFFER_EMPTY 0x02 +// RX packet pending register value from module +#define RSI_RX_PKT_PENDING 0x08 +// Assertion Interrupt indication from module +#define RSI_ASSERT_INTR 0x80 + +//Bootloader defines +#define SL_SI91X_SAFE_UPGRADE_ADDR 0x55408 +#define SL_SI91X_SAFE_UPGRADE BIT(12) +#define SL_SI91X_FW_START_OF_FILE BIT(0) +#define SL_SI91X_FW_END_OF_FILE BIT(1) +#define SL_SI91X_MIN_CHUNK_SIZE 4096 +#define SL_SI91X_LOOP_COUNT_UPGRADE_IMAGE 0xFFFF +#define SL_SI91X_RESET_LOOP_COUNTER(X) X = 0; +#define SL_SI91X_WHILE_LOOP(X, Y) while ((X++) < (int32_t)Y) +#define SL_SI91X_CHECK_LOOP_COUNTER(X, Y) \ + { \ + if (X >= Y) \ + return -1; \ + } + +//***************************** Macros for Crypto Start **********************************/ + +#define SL_SI91X_KEY_BUFFER_SIZE 32 +#define SL_SI91X_TAG_SIZE 16 +#define SL_SI91X_IV_SIZE 16 + +// ECDH defines +#define ECDH_BUFFER_SIZE 32 + +// TRNG defines +#define TRNG_INIT 1 +#define TRNG_ENTROPY 2 +#define TRNG_KEY 3 +#define TRNG_GENERATION 4 + +#define TRNG_INIT_MSG_LENGTH 16 +#define TRNG_KEY_SIZE 4 +#define TRNG_TEST_DATA_SIZE 64 + +// CCM defines +#define SL_SI91X_CCM_IV_MIN_SIZE 7 +#define SL_SI91X_CCM_IV_MAX_SIZE 13 +#define SL_SI91X_CCM_IV_BUFF_LEN 16 // SL_SI91X_CCM_IV_MAX_SIZE + 3 Bytes for Padding. +#define SL_SI91X_CCM_AD_MAX_SIZE 128 // Limiting header length to 128. +#define SL_SI91X_CCM_MSG_MAX_SIZE 1200 + +// GCM defines +#define SL_SI91X_GCM_IV_SIZE 12 +#define SL_SI91X_GCM_AD_MAX_SIZE 128 +#define SL_SI91X_GCM_MSG_MAX_SIZE 1400 + +// Chachapoly defines +#define SL_SI91X_KEYR_SIZE 16 +#define SL_SI91X_KEYS_SIZE 16 +#define SL_SI91X_CHACHAPOLY_IV_SIZE 12 +#define SL_SI91X_CHACHAPOLY_MSG_MAX_SIZE 1200 + +//ECDSA defines +#define SL_SI91X_PRIVATE_KEY_MAX_SIZE 64 +#define SL_SI91X_PUBLIC_KEY_MAX_SIZE 136 +#define SL_SI91X_SIGNATURE_MAX_SIZE 128 +#define SL_SI91X_ECDSA_MSG_MAX_SIZE 1000 + +//***************************** Macros for Crypto End **********************************/ + +typedef struct { + uint32_t buffer_full : 1; + uint32_t ready_to_transmit : 1; + uint32_t _reserved2 : 1; + uint32_t rx_packet_pending : 1; + uint32_t _reserved4 : 1; + uint32_t _reserved5 : 1; + uint32_t _reserved6 : 1; + uint32_t _reserved7 : 1; +} sl_si91x_interrupt_status_t; + +// Timeout used in get_channel API +#define SL_SI91X_GET_CHANNEL_TIMEOUT 30200 + +/** \addtogroup SL_SI91X_TYPES + * @{ */ +/// Si91x specific keepalive types. +typedef enum { + SL_SI91X_AP_KEEP_ALIVE_DISABLE = 0, ///< Disable keepalive + SL_SI91X_AP_DEAUTH_BASED_KEEP_ALIVE = + 1, ///< AP performs keep alive functionality based on the RX packets received from its stations. If no packet is received from the station with in time out, AP discards it. + SL_SI91X_AP_NULL_BASED_KEEP_ALIVE = + 3 ///< AP performs keep alive functionality by sending NULL DATA packet to the station. If no ACK is received from the station after specific no of retries, AP discards the station. +} sl_si91x_ap_keepalive_type_t; +/** @} */ + +typedef enum { + SL_SI91X_RETURN_IMMEDIATELY = 0, + SL_SI91X_WAIT_FOR_EVER = 1, + SL_SI91X_WAIT_FOR_RESPONSE_BIT = (1 << 30), + SL_SI91X_WAIT_FOR_SYNC_SCAN_RESULTS = (SL_SI91X_WAIT_FOR_RESPONSE_BIT | 12000), + SL_SI91X_WAIT_FOR_COMMAND_RESPONSE = (SL_SI91X_WAIT_FOR_RESPONSE_BIT | 1000), + SL_SI91X_WAIT_FOR_SOCKET_ACCEPT_RESPONSE = (SL_SI91X_WAIT_FOR_RESPONSE_BIT | 5000), +#ifdef SLI_SI91X_MCU_INTERFACE + SL_SI91X_WAIT_FOR_COMMAND_SUCCESS = (3000), +#else + SL_SI91X_WAIT_FOR_COMMAND_SUCCESS = (1000), +#endif + SL_SI91X_WAIT_FOR_DNS_RESOLUTION = (20000), +} sl_si91x_wait_period_t; + +#define SL_SI91X_WAIT_FOR(x) (sl_si91x_wait_period_t)(x) +#define SL_SI91X_WAIT_FOR_RESPONSE(x) (sl_si91x_wait_period_t)(SL_SI91X_WAIT_FOR_RESPONSE_BIT | (x)) + +typedef enum { + // (7+/-1)dBm in 2.4GHz band + // (5+/-1)dBm in 5GHz band + SL_SI91X_LOW_POWER_LEVEL, + + // (5+/-1)dBm in 2.4GHz band + // (7+/-1)dBm in 5GHz band + SL_SI91X_MEDIUM_POWER_LEVEL, + + SL_SI91X_HIGH_POWER_LEVEL +} sl_si91x_transmit_power_level; + +/*====================================================*/ +// Constant Defines +// SPI Status +#define RSI_SPI_SUCCESS 0x58 +#define RSI_SPI_BUSY 0x54 +#define RSI_SPI_FAIL 0x52 +#define RSI_SUCCESS 0 +//#define RSI_ERROR_SPI_BUSY (-1) +#define RSI_ERROR_BUFFER_FULL -3 // module buffer full error code +#define RSI_ERROR_IN_SLEEP -4 // module in sleep error code + +//SPI Internal Register Offset +#define RSI_SPI_INT_REG_ADDR 0x00 //@ register access method +#define RSI_SPI_MODE_REG_ADDR 0x08 //@ register access method +#define RSI_SPI_LENGTH_REG_ADDR 0x20 + +#define RSI_INT_MASK_REG_ADDR 0x41050000 // Interrupt mask register +#define RSI_INT_CLR_REG_ADDR 0x22000010 // Interrupt clear register + +// Packet queue identifiers +#define RSI_COMMON_Q 0 +#define RSI_ZB_Q 1 +#define RSI_BT_Q 2 +#define RSI_WLAN_MGMT_Q 4 +#define RSI_WLAN_DATA_Q 5 +#ifdef SAPIS_BT_STACK_ON_HOST +#define RSI_BT_INT_MGMT_Q 6 +#define RSI_BT_HCI_Q 7 +#endif + +// Event IDs +#define RSI_RX_EVENT 0 // RX event number used in the driver +#define RSI_TX_EVENT 1 // TX event number used in the driver +#define RSI_SOCKET_EVENT 2 // Socket event number used in the driver +#define RSI_MAX_NUM_EVENTS 3 // Max number events used in the driver + +#define RSI_HOST_INTF_REG_OUT 0x4105003C +#define RSI_HOST_INTF_REG_IN 0x41050034 +#define RSI_HOST_INTF_STATUS_REG 0x41050004 + +// si91x boot results +#define RSI_EOF_REACHED 'E' +#define RSI_BOOTUP_OPTIONS_LAST_CONFIG_NOT_SAVED 0xF1 +#define RSI_BOOTUP_OPTIONS_CHECKSUM_FAIL 0xF2 +#define RSI_INVALID_OPTION 0xF3 +#define RSI_CHECKSUM_SUCCESS 0xAA +#define RSI_CHECKSUM_FAILURE 0xCC +#define RSI_CHECKSUM_INVALID_ADDRESS 0x4C +#define VALID_FIRMWARE_NOT_PRESENT 0x23 +#define RSI_BOOTLOADER_VERSION_1P0 0x10 +#define RSI_BOOTLOADER_VERSION_1P1 0x11 +#define RSI_ROM_VERSION_1P0 1 +#define RSI_ROM_VERSION_1P1 2 + +#define SLI_WIFI_REGISTER_VALID (0xAB) + +#define RSI_HOST_INTERACT_REG_VALID (0xAB << 8) +#define RSI_HOST_INTERACT_REG_VALID_FW (0xA0 << 8) + +#define CONFIG_RTSTHRESHOLD 1 +#define RSI_RTS_THRESHOLD 2346 + +#define RSI_SEND_RAW_DATA 0x1 +#define RSI_RECEIVE_RAW_DATA 0x0 + +// enumeration for command request used in common control block +typedef enum { + // Common command requests + RSI_COMMON_REQ_OPERMODE = 0x10, + RSI_COMMON_REQ_ANTENNA_SELECT = 0x1B, + RSI_COMMON_REQ_FEATURE_FRAME = 0xC8, + RSI_COMMON_REQ_PWRMODE = 0x15, + // Reusing RSI_WLAN_REQ_FW_VERSION as RSI_COMMON_REQ_FW_VERSION + RSI_COMMON_REQ_FW_VERSION = 0x49, + RSI_COMMON_REQ_GET_EFUSE_DATA = 0xA0, + + // Unimplemented common command requests + RSI_COMMON_REQ_SOFT_RESET = 0x1C, + RSI_COMMON_REQ_ENCRYPT_CRYPTO = 0x76, + RSI_COMMON_REQ_UART_FLOW_CTRL_ENABLE = 0xA4, + RSI_COMMON_REQ_TA_M4_COMMANDS = 0xB0, + RSI_COMMON_REQ_DEBUG_LOG = 0x26 +#ifdef RSI_WAC_MFI_ENABLE + , + RSI_COMMON_REQ_IAP_GET_CERTIFICATE = 0xB6, + RSI_COMMON_REQ_IAP_INIT = 0xB7, + RSI_COMMON_REQ_IAP_GENERATE_SIGATURE = 0xB8 +#endif + +#ifdef RSI_PUF_ENABLE + , + RSI_COMMON_REQ_PUF_ENROLL = 0xD0, + RSI_COMMON_REQ_PUF_DIS_ENROLL = 0xD1, + RSI_COMMON_REQ_PUF_START = 0xD2, + RSI_COMMON_REQ_PUF_SET_KEY = 0xD3, + RSI_COMMON_REQ_PUF_DIS_SET_KEY = 0xD4, + RSI_COMMON_REQ_PUF_GET_KEY = 0xD5, + RSI_COMMON_REQ_PUF_DIS_GET_KEY = 0xD6, + RSI_COMMON_REQ_PUF_LOAD_KEY = 0xD7, + RSI_COMMON_REQ_AES_ENCRYPT = 0xD8, + RSI_COMMON_REQ_AES_DECRYPT = 0xD9, + RSI_COMMON_REQ_AES_MAC = 0xDA, + RSI_COMMON_REQ_PUF_INTR_KEY = 0xCE +#endif + , + RSI_COMMON_REQ_SWITCH_PROTO = 0x77, + RSI_COMMON_REQ_GET_RAM_DUMP = 0x92, + RSI_COMMON_REQ_ASSERT = 0xE1, + RSI_COMMON_REQ_SET_RTC_TIMER = 0xE9, + RSI_COMMON_REQ_GET_RTC_TIMER = 0xF2, + RSI_COMMON_REQ_SET_CONFIG = 0xBA +#ifdef CONFIGURE_GPIO_FROM_HOST + , + RSI_COMMON_REQ_GPIO_CONFIG = 0x28 +#endif +#ifdef FW_LOGGING_ENABLE + , + RSI_COMMON_REQ_DEVICE_LOGGING_INIT = 0x82 +#endif +} rsi_common_cmd_request_t; + +typedef enum { + // Common command responses + RSI_COMMON_RSP_OPERMODE = 0x10, + RSI_COMMON_RSP_ANTENNA_SELECT = 0x1B, + RSI_COMMON_RSP_FEATURE_FRAME = 0xC8, + RSI_COMMON_RSP_CARDREADY = 0x89, + RSI_COMMON_RSP_PWRMODE = 0x15, + + // Unimplemented common command responses + RSI_COMMON_RSP_CLEAR = 0x00, + RSI_COMMON_RSP_SOFT_RESET = 0x1C, + RSI_COMMON_RSP_ULP_NO_RAM_RETENTION = 0xCD, + RSI_COMMON_RSP_ASYNCHRONOUS = 0xFF, + RSI_COMMON_RSP_ENCRYPT_CRYPTO = 0x76, + RSI_COMMON_RSP_UART_FLOW_CTRL_ENABLE = 0xA4, + RSI_COMMON_RSP_TA_M4_COMMANDS = 0xB0, + RSI_COMMON_RSP_DEBUG_LOG = 0x26 +#ifdef RSI_PUF_ENABLE + , + RSI_COMMON_RSP_PUF_ENROLL = 0xD0, + RSI_COMMON_RSP_PUF_DIS_ENROLL = 0xD1, + RSI_COMMON_RSP_PUF_START = 0xD2, + RSI_COMMON_RSP_PUF_SET_KEY = 0xD3, + RSI_COMMON_RSP_PUF_DIS_SET_KEY = 0xD4, + RSI_COMMON_RSP_PUF_GET_KEY = 0xD5, + RSI_COMMON_RSP_PUF_DIS_GET_KEY = 0xD6, + RSI_COMMON_RSP_PUF_LOAD_KEY = 0xD7, + RSI_COMMON_RSP_AES_ENCRYPT = 0xD8, + RSI_COMMON_RSP_AES_DECRYPT = 0xD9, + RSI_COMMON_RSP_AES_MAC = 0xDA, + RSI_COMMON_RSP_PUF_INTR_KEY = 0xCE +#endif + +#ifdef RSI_WAC_MFI_ENABLE + , + RSI_COMMON_RSP_IAP_GET_CERTIFICATE = 0xB6, + RSI_COMMON_RSP_IAP_INIT = 0xB7, + RSI_COMMON_RSP_IAP_GENERATE_SIGATURE = 0xB8 +#endif + // Reusing RSI_WLAN_REQ_FW_VERSION as RSI_COMMON_REQ_FW_VERSION + , + RSI_COMMON_RSP_GET_EFUSE_DATA = 0xA0, + RSI_COMMON_RSP_FW_VERSION = 0x49, + RSI_COMMON_RSP_SWITCH_PROTO = 0x77, + RSI_COMMON_RSP_GET_RAM_DUMP = 0x92, + RSI_COMMON_RSP_ASSERT = 0xE1, + RSI_COMMON_RSP_SET_RTC_TIMER = 0xE9, + RSI_COMMON_RSP_GET_RTC_TIMER = 0xF2 +#ifdef CONFIGURE_GPIO_FROM_HOST + , + RSI_COMMON_RSP_GPIO_CONFIG = 0x28 +#endif +#ifdef FW_LOGGING_ENABLE + , + RSI_COMMON_RSP_DEVICE_LOGGING_INIT = 0x82 +#endif +} rsi_common_cmd_response_t; + +// enumeration for WLAN command request codes +typedef enum { + // Wi-Fi commands + RSI_WLAN_REQ_CONFIG = 0xBE, + RSI_WLAN_REQ_BAND = 0x11, + RSI_WLAN_REQ_INIT = 0x12, + RSI_WLAN_REQ_SCAN = 0x13, + RSI_WLAN_REQ_JOIN = 0x14, + RSI_WLAN_REQ_SET_MAC_ADDRESS = 0x17, + RSI_WLAN_REQ_DISCONNECT = 0x19, + RSI_WLAN_REQ_AP_STOP = 0xAE, + RSI_WLAN_REQ_SET_REGION = 0x1D, + RSI_WLAN_REQ_QUERY_NETWORK_PARAMS = 0x18, + RSI_WLAN_REQ_AP_CONFIGURATION = 0x24, + RSI_WLAN_REQ_EVM_OFFSET = 0x36, + RSI_WLAN_REQ_EVM_WRITE = 0x37, + RSI_WLAN_REQ_RSSI = 0x3A, + RSI_WLAN_REQ_EAP_CONFIG = 0x4C, + RSI_WLAN_REQ_FW_VERSION = 0x49, + RSI_WLAN_REQ_MAC_ADDRESS = 0x4A, + RSI_WLAN_REQ_QUERY_GO_PARAMS = 0x4E, + RSI_WLAN_REQ_SET_CERTIFICATE = 0x4D, + RSI_WLAN_REQ_BG_SCAN = 0x6A, + RSI_WLAN_REQ_BEACON_STOP = 0x63, + RSI_WLAN_REQ_WPS_METHOD = 0x72, + RSI_WLAN_REQ_EFUSE_READ = 0x73, + RSI_WLAN_REQ_ROAM_PARAMS = 0x7B, + RSI_WLAN_REQ_RX_STATS = 0xA2, + RSI_WLAN_REQ_RADIO = 0x81, + RSI_WLAN_REQ_EXT_STATS = 0x68, + RSI_WLAN_REQ_TWT_AUTO_CONFIG = 0x2E, + RSI_WLAN_REQ_TWT_PARAMS = 0x2F, + SL_WIFI_REQ_RESCHEDULE_TWT = 0x3F, + RSI_WLAN_REQ_GAIN_TABLE = 0x47, + RSI_WLAN_REQ_TX_TEST_MODE = 0x7C, + RSI_WLAN_REQ_HOST_PSK = 0xA5, + RSI_WLAN_REQ_SET_REGION_AP = 0xBD, + RSI_WLAN_REQ_CALIB_WRITE = 0xCA, + RSI_WLAN_REQ_FILTER_BCAST_PACKETS = 0xC9, + RSI_WLAN_REQ_CALIB_READ = 0xCF, + RSI_WLAN_REQ_FULL_FW_VERSION = 0xE0, + RSI_WLAN_REQ_HTTP_OTAF = 0xF4, + RSI_WLAN_REQ_11AX_PARAMS = 0xFF, + + // Network commands + RSI_WLAN_REQ_PING_PACKET = 0x29, + RSI_WLAN_REQ_IPCONFV4 = 0x41, + RSI_WLAN_REQ_DNS_QUERY = 0x44, + RSI_WLAN_REQ_HTTP_CLIENT_GET = 0x51, + RSI_WLAN_REQ_HTTP_CLIENT_POST = 0x52, + RSI_WLAN_REQ_HTTP_CLIENT_PUT = 0x53, + RSI_WLAN_REQ_IPCONFV6 = 0x90, + RSI_WLAN_REQ_MULTICAST = 0xB1, + RSI_WLAN_REQ_HTTP_ABORT = 0xB3, + RSI_WLAN_REQ_HTTP_CREDENTIALS = 0xB4, + RSI_WLAN_REQ_EMB_MQTT_CLIENT = 0xCB, + RSI_WLAN_REQ_SNTP_CLIENT = 0xE4, + RSI_WLAN_REQ_HTTP_CLIENT_POST_DATA = 0xEB, + + // Socket commands + RSI_WLAN_REQ_SOCKET_CREATE = 0x42, + RSI_WLAN_REQ_SOCKET_CLOSE = 0x43, + RSI_WLAN_REQ_SOCKET_READ_DATA = 0x6B, + RSI_WLAN_REQ_SOCKET_ACCEPT = 0x6C, + RSI_WLAN_REQ_SOCKET_CONFIG = 0xA7, + RSI_WLAN_REQ_SELECT_REQUEST = 0x74, + RSI_WLAN_REQ_SET_SNI_EMBEDDED = 0x6E, + + // Unimplemented commands + RSI_WLAN_REQ_SET_SLEEP_TIMER = 0x16, + RSI_WLAN_REQ_CFG_SAVE = 0x20, + RSI_WLAN_REQ_AUTO_CONFIG_ENABLE = 0x21, + RSI_WLAN_REQ_GET_CFG = 0x22, + RSI_WLAN_REQ_USER_STORE_CONFIG = 0x23, + RSI_WLAN_REQ_SET_WEP_KEYS = 0x25, + RSI_WLAN_REQ_SET_PROFILE = 0x31, + RSI_WLAN_REQ_GET_PROFILE = 0x32, + RSI_WLAN_REQ_DELETE_PROFILE = 0x33, + RSI_WLAN_REQ_SET_MULTICAST_FILTER = 0x40, + RSI_WLAN_REQ_CONNECTION_STATUS = 0x48, + RSI_WLAN_REQ_CONFIGURE_P2P = 0x4B, + RSI_WLAN_REQ_WIRELESS_FWUP = 0x59, + RSI_WLAN_REQ_HT_CAPABILITIES = 0x6D, + RSI_WLAN_REQ_REJOIN_PARAMS = 0x6F, + RSI_WLAN_REQ_WMM_PS = 0x97, + RSI_WLAN_REQ_FWUP = 0x99, +#ifdef RSI_WAC_MFI_ENABLE + RSI_WLAN_REQ_ADD_MFI_IE = 0xB5, +#endif +#ifndef SLI_SI91X_MCU_INTERFACE + RSI_WLAN_REQ_CERT_VALID = 0xBC, +#endif + RSI_WLAN_REQ_FREQ_OFFSET = 0xF3, + RSI_WLAN_REQ_DYNAMIC_POOL = 0xC7, + RSI_WLAN_REQ_MDNSD = 0xDB, + RSI_WLAN_REQ_GET_DPD_DATA = 0xDC, + RSI_WLAN_REQ_FTP = 0xE2, + RSI_WLAN_REQ_FTP_FILE_WRITE = 0xE3, + RSI_WLAN_REQ_SMTP_CLIENT = 0xE6, + RSI_WLAN_REQ_OTA_FWUP = 0xEF, + RSI_WLAN_REQ_WEBPAGE_LOAD = 0x50, + RSI_WLAN_REQ_JSON_LOAD = 0x9c, + RSI_WLAN_REQ_WEBPAGE_ERASE = 0x9A, + RSI_WLAN_REQ_JSON_OBJECT_ERASE = 0x9B, + RSI_WLAN_REQ_WEBPAGE_CLEAR_ALL = 0x7F, + RSI_WLAN_REQ_HOST_WEBPAGE_SEND = 0x56, + RSI_WLAN_REQ_GET_RANDOM = 0xF8, + RSI_WLAN_REQ_POP3_CLIENT = 0xE7, + RSI_WLAN_REQ_DHCP_USER_CLASS = 0xEC, + RSI_WLAN_REQ_TIMEOUT = 0xEA, + RSI_WLAN_REQ_GET_STATS = 0xF1, + RSI_WLAN_REQ_UPDATE_TCP_WINDOW = 0xF5, + RSI_WLAN_REQ_DNS_UPDATE = 0xED, + RSI_WLAN_REQ_DNS_SERVER_ADD = 0x55, + RSI_WLAN_REQ_TSF = 0x65, + RSI_WLAN_REQ_SET_TRANSCEIVER_CHANNEL = 0x7A, + RSI_WLAN_REQ_TRANSCEIVER_PEER_LIST_UPDATE = 0x8B, + RSI_WLAN_REQ_TRANSCEIVER_CONFIG_PARAMS = 0x8C, + RSI_WLAN_REQ_SET_TRANSCEIVER_MCAST_FILTER = 0x8D, + RSI_WLAN_REQ_TRANSCEIVER_FLUSH_DATA_Q = 0x8E, +} rsi_wlan_cmd_request_t; + +// enumeration for WLAN command response codes +typedef enum { + // Wi-Fi command response + RSI_WLAN_RSP_BAND = 0x11, + RSI_WLAN_RSP_INIT = 0x12, + RSI_WLAN_RSP_SCAN = 0x13, + RSI_WLAN_RSP_JOIN = 0x14, + RSI_WLAN_RSP_SET_MAC_ADDRESS = 0x17, + RSI_WLAN_RSP_QUERY_NETWORK_PARAMS = 0x18, + RSI_WLAN_RSP_DISCONNECT = 0x19, + RSI_WLAN_RSP_AP_STOP = 0xAE, + RSI_WLAN_RSP_SET_REGION = 0x1D, + RSI_WLAN_RSP_AP_CONFIGURATION = 0x24, + RSI_WLAN_RSP_TWT_AUTO_CONFIG = 0x2E, + RSI_WLAN_RSP_TWT_PARAMS = 0x2F, + SL_WIFI_RSP_RESCHEDULE_TWT = 0x3F, + RSI_WLAN_RSP_EVM_OFFSET = 0x36, + RSI_WLAN_RSP_EVM_WRITE = 0x37, + RSI_WLAN_RSP_RSSI = 0x3A, + RSI_WLAN_RSP_GAIN_TABLE = 0x47, + RSI_WLAN_RSP_FW_VERSION = 0x49, + RSI_WLAN_RSP_MAC_ADDRESS = 0x4A, + RSI_WLAN_RSP_EAP_CONFIG = 0x4C, + RSI_WLAN_RSP_SET_CERTIFICATE = 0x4D, + RSI_WLAN_RSP_QUERY_GO_PARAMS = 0x4E, + RSI_WLAN_RSP_BEACON_STOP = 0x63, + RSI_WLAN_RSP_BG_SCAN = 0x6A, + RSI_WLAN_RSP_EXT_STATS = 0x68, // Neither part 22q2 nor alpha 2 + RSI_WLAN_RSP_EFUSE_READ = 0x73, + RSI_WLAN_RSP_TX_TEST_MODE = 0x7C, + RSI_WLAN_RSP_ROAM_PARAMS = 0x7B, + RSI_WLAN_RSP_RADIO = 0x81, + RSI_WLAN_RSP_RX_STATS = 0xA2, + RSI_WLAN_RSP_HOST_PSK = 0xA5, + RSI_WLAN_RSP_SCAN_RESULTS = 0xAF, + RSI_WLAN_RSP_CONFIG = 0XBE, + RSI_WLAN_RSP_SET_REGION_AP = 0xBD, + RSI_WLAN_RSP_FILTER_BCAST_PACKETS = 0xC9, + RSI_WLAN_RSP_CALIB_READ = 0xCF, + RSI_WLAN_RSP_FULL_FW_VERSION = 0xE0, + RSI_WLAN_RSP_GET_STATS = 0xF1, + RSI_WLAN_RSP_HTTP_OTAF = 0xF4, + RSI_WLAN_RSP_11AX_PARAMS = 0xFF, + + // Network command response + RSI_WLAN_RSP_PING_PACKET = 0x29, + RSI_WLAN_RSP_IPCONFV4 = 0x41, + RSI_WLAN_RSP_DNS_QUERY = 0x44, + RSI_WLAN_RSP_HTTP_CLIENT_GET = 0x51, + RSI_WLAN_RSP_HTTP_CLIENT_POST = 0x52, + RSI_WLAN_RSP_HTTP_CLIENT_PUT = 0x53, + RSI_WLAN_RSP_IPCONFV6 = 0xA1, + RSI_WLAN_RSP_MULTICAST = 0xB1, + RSI_WLAN_RSP_HTTP_ABORT = 0xB3, + RSI_WLAN_RSP_HTTP_CREDENTIALS = 0xB4, + RSI_WLAN_RSP_EMB_MQTT_CLIENT = 0xCB, + RSI_WLAN_RSP_SNTP_CLIENT = 0xE4, + RSI_WLAN_RSP_HTTP_CLIENT_POST_DATA = 0xEB, + + // Socket command response + RSI_WLAN_RSP_SOCKET_CREATE = 0x42, + RSI_WLAN_RSP_SOCKET_CLOSE = 0x43, + RSI_WLAN_RSP_SOCKET_READ_DATA = 0x6B, + RSI_WLAN_RSP_SOCKET_ACCEPT = 0x6C, + RSI_WLAN_RSP_SOCKET_CONFIG = 0xA7, + RSI_WLAN_RSP_SELECT_REQUEST = 0x74, + RSI_WLAN_RSP_SET_SNI_EMBEDDED = 0x6E, + + // Unimplemented command for 22q2 + RSI_WLAN_RSP_CLEAR = 0x00, + RSI_WLAN_RSP_CFG_SAVE = 0x20, + RSI_WLAN_RSP_AUTO_CONFIG_ENABLE = 0x21, + RSI_WLAN_RSP_GET_CFG = 0x22, + RSI_WLAN_RSP_USER_STORE_CONFIG = 0x23, + RSI_WLAN_RSP_SET_WEP_KEYS = 0x25, + RSI_WLAN_RSP_P2P_CONNECTION_REQUEST = 0x30, + RSI_WLAN_RSP_SET_PROFILE = 0x31, + RSI_WLAN_RSP_GET_PROFILE = 0x32, + RSI_WLAN_RSP_DELETE_PROFILE = 0x33, + RSI_WLAN_RSP_CONN_ESTABLISH = 0x61, + RSI_WLAN_RSP_REMOTE_TERMINATE = 0x62, + RSI_WLAN_RSP_IPV4_CHANGE = 0xAA, + RSI_WLAN_RSP_TCP_ACK_INDICATION = 0xAB, + RSI_WLAN_RSP_UART_DATA_ACK = 0xAC, + RSI_WLAN_RSP_SET_MULTICAST_FILTER = 0x40, + RSI_WLAN_RSP_DNS_UPDATE = 0xED, + RSI_WLAN_RSP_CONNECTION_STATUS = 0x48, + RSI_WLAN_RSP_CONFIGURE_P2P = 0x4B, + RSI_WLAN_RSP_WFD_DEVICE = 0x54, + RSI_WLAN_RSP_DNS_SERVER_ADD = 0x55, + RSI_WLAN_RSP_WIRELESS_FWUP_OK = 0x59, + RSI_WLAN_RSP_WIRELESS_FWUP_DONE = 0x5A, + RSI_WLAN_RSP_HT_CAPABILITIES = 0x6D, + RSI_WLAN_RSP_REJOIN_PARAMS = 0x6F, + RSI_WLAN_RSP_WPS_METHOD = 0x72, + RSI_WLAN_RSP_WMM_PS = 0x97, + RSI_WLAN_RSP_FWUP = 0x99, +#ifdef RSI_WAC_MFI_ENABLE + RSI_WLAN_RSP_ADD_MFI_IE = 0xB5, +#endif +#ifndef SLI_SI91X_MCU_INTERFACE + RSI_WLAN_RSP_CERT_VALID = 0xBC, +#endif + RSI_WLAN_RSP_CLIENT_CONNECTED = 0xC2, + RSI_WLAN_RSP_CLIENT_DISCONNECTED = 0xC3, + RSI_WLAN_RSP_FREQ_OFFSET = 0xF3, + RSI_WLAN_RSP_CALIB_WRITE = 0xCA, + RSI_WLAN_RSP_DYNAMIC_POOL = 0xC7, + RSI_WLAN_RSP_EMB_MQTT_PUBLISH_PKT = 0xCC, + RSI_WLAN_RSP_MQTT_REMOTE_TERMINATE = 0xF0, + RSI_WLAN_RSP_MDNSD = 0xDB, + RSI_WLAN_RSP_GET_DPD_DATA = 0xDC, + RSI_WLAN_RSP_FTP = 0xE2, + RSI_WLAN_RSP_FTP_FILE_WRITE = 0xE3, + RSI_WLAN_RSP_SNTP_SERVER = 0xE5, + RSI_WLAN_RSP_SMTP_CLIENT = 0xE6, + RSI_WLAN_RSP_OTA_FWUP = 0xEF, + RSI_WLAN_RSP_WEBPAGE_LOAD = 0x50, + RSI_WLAN_RSP_JSON_LOAD = 0x9c, + RSI_WLAN_RSP_WEBPAGE_ERASE = 0x9A, + RSI_WLAN_RSP_JSON_OBJECT_ERASE = 0x9B, + RSI_WLAN_RSP_WEBPAGE_CLEAR_ALL = 0x7F, + RSI_WLAN_RSP_HOST_WEBPAGE_SEND = 0x56, + RSI_WLAN_RSP_JSON_UPDATE = 0x9D, + RSI_WLAN_RSP_GET_RANDOM = 0xF8, + RSI_WLAN_RSP_ASYNCHRONOUS = 0xFF, + RSI_WLAN_RSP_JSON_EVENT = 0xEE, + RSI_WLAN_RSP_POP3_CLIENT = 0xE7, + RSI_WLAN_RSP_POP3_CLIENT_TERMINATE = 0xE8, + RSI_WLAN_RSP_DHCP_USER_CLASS = 0xEC, + RSI_WLAN_RSP_TIMEOUT = 0xEA, + RSI_WLAN_RSP_URL_REQUEST = 0x64, + RSI_WLAN_RSP_MODULE_STATE = 0x70, + RSI_WLAN_RSP_TWT_ASYNC = 0x71, + RSI_WLAN_RSP_UPDATE_TCP_WINDOW = 0xF5, + RSI_WLAN_RSP_TSF = 0x65, + RSI_WLAN_RSP_TRANSCEIVER_SET_CHANNEL = 0x7A, + RSI_WLAN_RSP_TRANSCEIVER_PEER_LIST_UPDATE = 0x8B, + RSI_WLAN_RSP_TRANSCEIVER_CONFIG_PARAMS = 0x8C, + RSI_WLAN_RSP_TRANSCEIVER_SET_MCAST_FILTER = 0x8D, + RSI_WLAN_RSP_TRANSCEIVER_FLUSH_DATA_Q = 0x8E, + RSI_WLAN_RSP_TRANSCEIVER_TX_DATA_STATUS = 0x3D, + SL_SI91X_WIFI_RX_DOT11_DATA = 0x03, + // Unimplemented commands after 22Q2 + RSI_WLAN_RATE_RSP_STATS = 0x88 +} rsi_wlan_cmd_response_t; + +typedef enum { SET_REGION_CODE_FROM_BEACONS, SET_REGION_CODE_FROM_USER } si91x_set_region_code_command_t; + +typedef enum { SL_SI91X_SOCKET_REMOTE_TERMINATED_EVENT, SL_SI91X_SOCKET_EVENT_COUNT } sl_si91x_socket_event_t; + +typedef enum { SL_SI91X_NO_ENCRYPTION, SL_SI91X_TKIP_ENCRYPTION, SL_SI91X_CCMP_ENCRYPTION } sl_si91x_encryption_t; diff --git a/wiseconnect/components/device/silabs/si91x/wireless/inc/sl_si91x_core_utilities.h b/wiseconnect/components/device/silabs/si91x/wireless/inc/sl_si91x_core_utilities.h new file mode 100644 index 000000000..ae13c6ae3 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/inc/sl_si91x_core_utilities.h @@ -0,0 +1,162 @@ +/***************************************************************************/ /** + * @file + * @brief + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#pragma once +#include "sl_si91x_types.h" +#include "sl_wifi_device.h" +#include "sl_additional_status.h" +#include "sli_cmsis_os2_ext_task_register.h" + +#define CONVERTED_FIRMWARE_STATUS_INDEX 0 + +/****************************************************************************** + * A utility function to extract firmware status from RX packet. + * The extracted firmware status can be given to convert_and_save_firmware_status() to get sl_status equivalent. + * @param packet packet that contains the frame status which needs to be extracted. + * @return frame status + *****************************************************************************/ +static inline uint16_t get_si91x_frame_status(sl_si91x_packet_t *packet) +{ + return (uint16_t)(packet->desc[12] + (packet->desc[13] << 8)); +} + +/****************************************************************************** + * @brief + * A utility function that store the firmware status code in thread specific storage. + * @param[in] converted_firmware_status + * Firmware status code that needs to be saved. + *****************************************************************************/ +static inline void save_si91x_firmware_status(sl_status_t converted_firmware_status) +{ + sli_osTaskRegisterSetValue(NULL, CONVERTED_FIRMWARE_STATUS_INDEX, converted_firmware_status); +} + +/****************************************************************************** + * @brief + * A utility function that converts frame status sent by firmware to sl_status_t and stores in thread local storage of caller thread. + * @param[in] si91x_firmware_status + * si91x_firmware_status that needs to be converted to sl_status_t. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + *****************************************************************************/ +static inline sl_status_t convert_and_save_firmware_status(uint16_t si91x_firmware_status) +{ + sl_status_t converted_firmware_status = (si91x_firmware_status == SL_STATUS_OK) ? SL_STATUS_OK + : (si91x_firmware_status | BIT(16)); + save_si91x_firmware_status(converted_firmware_status); + return converted_firmware_status; +} + +/** \addtogroup SI91X_DRIVER_FUNCTIONS + * \ingroup SL_SI91X_API + * @{ */ +/***************************************************************************/ /** + * @brief + * Get the saved thread specific firmware status value. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + ******************************************************************************/ +static inline sl_status_t sl_si91x_get_saved_firmware_status(void) +{ + sl_status_t status = SL_STATUS_FAIL; + + sli_osTaskRegisterGetValue(NULL, CONVERTED_FIRMWARE_STATUS_INDEX, &status); + return status; +} +/** @} */ + +/****************************************************************************** + * @brief + * A utility function that converts si91x_status_t to sl_status_t + * @param[in] si91x_status + * si91x_status that needs to be converted to sl_status_t. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + *****************************************************************************/ +static inline sl_status_t convert_si91x_status_to_sl_status(si91x_status_t si91x_status) +{ + switch (si91x_status) { + case RSI_ERROR_NONE: + return SL_STATUS_OK; + case RSI_ERROR_TIMEOUT: + return SL_STATUS_TIMEOUT; + case RSI_ERROR_INVALID_PARAM: + return SL_STATUS_INVALID_PARAMETER; + case RSI_ERROR_COMMAND_GIVEN_IN_WRONG_STATE: + return SL_STATUS_INVALID_STATE; + case RSI_ERROR_PKT_ALLOCATION_FAILURE: + return SL_STATUS_ALLOCATION_FAILED; + case RSI_ERROR_COMMAND_NOT_SUPPORTED: + return SL_STATUS_NOT_SUPPORTED; + case RSI_ERROR_INSUFFICIENT_BUFFER: + return SL_STATUS_NO_MORE_RESOURCE; + case RSI_ERROR_IN_OS_OPERATION: + return SL_STATUS_OS_OPERATION_FAILURE; + case RSI_ERROR_BOOTUP_OPTIONS_NOT_SAVED: + return SL_STATUS_BOOTUP_OPTIONS_NOT_SAVED; + case RSI_ERROR_BOOTLOADER_VERSION_NOT_MATCHING: + return SL_STATUS_BOOTLOADER_VERSION_MISMATCH; + case RSI_ERROR_WAITING_FOR_BOARD_READY: + return SL_STATUS_WAITING_FOR_BOARD_READY; + case RSI_ERROR_VALID_FIRMWARE_NOT_PRESENT: + return SL_STATUS_VALID_FIRMWARE_NOT_PRESENT; + case RSI_ERROR_INVALID_OPTION: + return SL_STATUS_INVALID_OPTION; + case RSI_ERROR_SPI_BUSY: + return SL_STATUS_SPI_BUSY; + case RSI_ERROR_CARD_READY_TIMEOUT: + return SL_STATUS_CARD_READY_TIMEOUT; + case RSI_ERROR_FW_LOAD_OR_UPGRADE_TIMEOUT: + return SL_STATUS_FW_LOAD_OR_UPGRADE_TIMEOUT; + default: + return SL_STATUS_FAIL; + } +} + +/****************************************************************************** + * @brief + * Atomically append given buffer to the end of a buffer queue + * @param[in] queue + * Destination buffer queue + * @param[in] buffer + * Buffer + *****************************************************************************/ +void sli_si91x_append_to_buffer_queue(sl_si91x_buffer_queue_t *queue, sl_wifi_buffer_t *buffer); + +/****************************************************************************** + * @brief + * Atomically remove the head from a buffer queue + * @param[in] queue + * Source buffer queue + * @param[in] buffer + * Destination buffer + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + *****************************************************************************/ +sl_status_t sli_si91x_pop_from_buffer_queue(sl_si91x_buffer_queue_t *queue, sl_wifi_buffer_t **buffer); diff --git a/wiseconnect/components/device/silabs/si91x/wireless/inc/sl_si91x_driver.h b/wiseconnect/components/device/silabs/si91x/wireless/inc/sl_si91x_driver.h new file mode 100644 index 000000000..b341b1a07 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/inc/sl_si91x_driver.h @@ -0,0 +1,868 @@ +/***************************************************************************/ /** + * @file + * @brief + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#pragma once + +#include "sl_status.h" +#include "sl_wifi_device.h" +#include "sl_wifi_host_interface.h" +#include "sl_si91x_host_interface.h" +#include "sl_net_types.h" +#include "sl_rsi_utility.h" +#include "sl_si91x_constants.h" + +#define VERIFY_STATUS(s) \ + do { \ + if (s != SL_STATUS_OK) \ + return s; \ + } while (0) + +/** + * All flags used in bus event mask + * There are three main groups of flags, each with SL_SI91X_COMMAND_TYPE_COUNT number of unique flags + * + */ +#define SL_SI91X_TX_PENDING_FLAG(x) (1 << (x)) +#define SL_SI91X_RESPONSE_FLAG(x) (1 << (x)) + +//! Tx Flags +#define SL_SI91X_COMMON_TX_PENDING_EVENT SL_SI91X_TX_PENDING_FLAG(SI91X_COMMON_CMD) +#define SL_SI91X_WLAN_TX_PENDING_EVENT SL_SI91X_TX_PENDING_FLAG(SI91X_WLAN_CMD) +#define SL_SI91X_NETWORK_TX_PENDING_EVENT SL_SI91X_TX_PENDING_FLAG(SI91X_NETWORK_CMD) +#define SL_SI91X_BT_TX_PENDING_EVENT SL_SI91X_TX_PENDING_FLAG(SI91X_BT_CMD) +#define SL_SI91X_SOCKET_TX_PENDING_EVENT SL_SI91X_TX_PENDING_FLAG(SI91X_SOCKET_CMD) +#define SL_SI91X_SOCKET_DATA_TX_PENDING_EVENT SL_SI91X_TX_PENDING_FLAG(SI91X_SOCKET_DATA) + +//! Rx Flags +#define SL_SI91X_NCP_HOST_BUS_RX_EVENT \ + SL_SI91X_RESPONSE_FLAG(SI91X_CMD_MAX) //Triggered by IRQ to indicate something to read + +#define SL_SI91X_ALL_TX_PENDING_COMMAND_EVENTS \ + (SL_SI91X_COMMON_TX_PENDING_EVENT | SL_SI91X_WLAN_TX_PENDING_EVENT | SL_SI91X_NETWORK_TX_PENDING_EVENT \ + | SL_SI91X_BT_TX_PENDING_EVENT | SL_SI91X_SOCKET_TX_PENDING_EVENT) + +typedef enum { SL_NCP_NORMAL_POWER_MODE, SL_NCP_LOW_POWER_MODE, SL_NCP_ULTRA_LOW_POWER_MODE } sl_si91x_power_mode_t; + +typedef struct sl_si91x_power_configuration sl_si91x_power_configuration_t; + +/***************************************************************************/ /** + * @brief + * Initialize the driver. + * @param[in] config + * @ref sl_wifi_device_configuration_t Pointer to device configuration. + * @param[in] event_handler + * [sl_wifi_event_handler_t](../wiseconnect-api-reference-guide-wi-fi/sl-wifi-types#sl-wifi-event-handler-t) Function pointer to receive asynchronous events. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + ******************************************************************************/ +sl_status_t sl_si91x_driver_init(const sl_wifi_device_configuration_t *config, sl_wifi_event_handler_t event_handler); + +/***************************************************************************/ /** + * @brief + * De-initialize the driver. + * @pre Pre-conditions: + * - + * @ref sl_si91x_driver_init should be called before this API. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + ******************************************************************************/ +sl_status_t sl_si91x_driver_deinit(void); + +/***************************************************************************/ /** + * @brief + * Register a function and optional argument for scan results callback. + * @param[in] command + * Command type to be sent to TA firmware. + * @param[in] queue_type + * @ref sl_si91x_queue_type_t Queue type to be used to send the command on. + * @param[in] data + * Command packet to be sent to the TA firmware. + * @param[in] data_length + * Length of command packet. + * @param[in] wait_period + * @ref sl_si91x_wait_period_t Timeout for the command response. + * @param[in] sdk_context + * Pointer to the context. + * @param[in] data_buffer + * [sl_wifi_buffer_t](../wiseconnect-api-reference-guide-wi-fi/sl-wifi-buffer-t) Pointer to a data buffer pointer for the response data to be returned in. + * @pre Pre-conditions: + * - + * @ref sl_si91x_driver_init should be called before this API. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + ******************************************************************************/ +sl_status_t sl_si91x_driver_send_command(uint32_t command, + sl_si91x_queue_type_t queue_type, + const void *data, + uint32_t data_length, + sl_si91x_wait_period_t wait_period, + void *sdk_context, + sl_wifi_buffer_t **data_buffer); + +/***************************************************************************/ /** + * @brief + * Register a function and optional argument for scan results callback. + * @param[in] command + * Command type to be sent to TA firmware. + * @param[in] data + * Command packet to be sent to the TA firmware. + * @param[in] data_length + * Length of command packet. + * @param[in] wait_period + * @ref sl_si91x_wait_period_t Timeout for the command response. + * @pre + * @ref sl_si91x_driver_init should be called before this API. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + ******************************************************************************/ +sl_status_t sl_si91x_driver_send_side_band_crypto(uint32_t command, + const void *data, + uint32_t data_length, + sl_si91x_wait_period_t wait_period); + +/***************************************************************************/ /** + * @brief + * Send commands to the TA; whose response needs to be handled asynchronously. + * Note: This function doesn't acquire "command_in_flight" boolean + * @param[in] command + * Command type to be sent to TA firmware. + * @param[in] queue_type + * @ref sl_si91x_queue_type_t Queue type to be used to send the command on. + * @param[in] data + * Command packet to be sent to the TA firmware. + * @param[in] data_length + * Length of the command packet. + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + ******************************************************************************/ +sl_status_t sl_si91x_driver_send_async_command(uint32_t command, + sl_si91x_queue_type_t queue_type, + void *data, + uint32_t data_length); +/***************************************************************************/ /** + * @brief + * Wait for a command response. + * @param[in] command + * @ref rsi_wlan_cmd_request_t Command type to wait . + * @param[in] wait_period + * @ref sl_si91x_wait_period_t Wait time in milliseconds to wait for command response. + * @pre Pre-conditions: + * - + * @ref sl_si91x_driver_init should be called before this API. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + ******************************************************************************/ +sl_status_t sl_si91x_driver_wait_for_response(rsi_wlan_cmd_request_t command, sl_si91x_wait_period_t wait_period); + +/***************************************************************************/ /** + * @brief + * Send a socket command. + * @param[in] request + * @ref sl_si91x_socket_send_request_t Pointer to socket command packet. + * @param[in] data + * Pointer to socket data. + * @param[in] wait_time + * Timeout for the command response. + * @pre Pre-conditions: + * - + * @ref sl_si91x_driver_init should be called before this API. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + ******************************************************************************/ +sl_status_t sl_si91x_driver_send_socket_data(const sl_si91x_socket_send_request_t *request, + const void *data, + uint32_t wait_time); + +/***************************************************************************/ /** + * @brief + * Send a Bluetooth command. + * @param[in] command + * @ref rsi_wlan_cmd_request_t Command type to be sent. + * @param[in] queue_type + * @ref sl_si91x_queue_type_t Queue type to send command on. + * @param[in] data + * [sl_wifi_buffer_t](../wiseconnect-api-reference-guide-wi-fi/sl-wifi-buffer-t) Pointer to Bluetooth data. + * @param[in] sync_command + * Sync or Async command. + * @pre Pre-conditions: + * - + * @ref sl_si91x_driver_init should be called before this API. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + ******************************************************************************/ +sl_status_t sl_si91x_driver_send_bt_command(rsi_wlan_cmd_request_t command, + sl_si91x_queue_type_t queue_type, + sl_wifi_buffer_t *data, + uint8_t sync_command); + +/***************************************************************************/ /** + * @brief + * Load a certificate into a specified index. + * @param[in] certificate_type + * Type of certificate being loaded + * @param[in] certificate_index + * Index where the certificate is to be loaded. + * @param[in] buffer + * Pointer to the buffer containing the certificate to be loaded. + * @param[in] certificate_length + * Length of the certificate buffer. + * @pre Pre-conditions: + * - + * @ref sl_si91x_driver_init should be called before this API. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + ******************************************************************************/ +sl_status_t sl_si91x_wifi_set_certificate_index(uint8_t certificate_type, + uint8_t certificate_index, + const uint8_t *buffer, + uint32_t certificate_length); + +/***************************************************************************/ /** + * @brief + * Set the host rtc timer. This is a blocking API. + * @param[in] timer + * @ref sl_si91x_module_rtc_time_t Pointer to fill RTC time. + * second --> seconds [0-59] + * minute --> minutes [0-59] + * hour --> hours since midnight [0-23] + * day --> day of the month [1-31] + * month --> months since January [0-11] + * year --> year since 1990. + * Weekday--> Weekday from Sunday to Saturday [1-7]. + * @note Hour is 24-hour format only (valid values are 0 to 23). + * Valid values for Month are 0 to 11 (January to December). + * @pre Pre-conditions: + * - + * @ref sl_si91x_driver_init() API needs to be called before this API + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + ******************************************************************************/ +sl_status_t sl_si91x_set_rtc_timer(sl_si91x_module_rtc_time_t *timer); + +/***************************************************************************/ /** + * @brief + * Fetch current time from hardware Real Time Clock. This is a blocking API. + * @param[out] response + * @ref sl_si91x_module_rtc_time_t Response of the requested command. + - + * @note Response parameters: + - + * * Pointer to fill RTC time. + * second --> seconds [0-59] + * minute --> minutes [0-59] + * hour --> hours since midnight [0-23] + * day --> day of the month [1-31] + * month --> months since January [0-11] + * year --> year since 1990. + * Weekday--> Weekday from Sunday to Saturday [1-7]. + * @note Hour is 24-hour format only (valid values are 0 to 23). + * Valid values for Month are 0 to 11 (January to December). + * @pre Pre-conditions: + * - + * @ref sl_si91x_set_rtc_timer() API needs to be called before this API. + * @ref sl_si91x_driver_init() API needs to be called before this API also. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + ******************************************************************************/ +sl_status_t sl_si91x_get_rtc_timer(sl_si91x_module_rtc_time_t *response); + +/***************************************************************************/ /** + * @brief + * Writes calibration data to non-volatile device memory. + * @param[in] data + * @ref si91x_calibration_data_t Pointer to buffer containing calibration data. + * @pre Pre-conditions: + * - + * @ref sl_si91x_driver_init should be called before this API. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + ******************************************************************************/ +sl_status_t sl_si91x_write_calibration_data(const si91x_calibration_data_t *data); + +/** \addtogroup SI91X_RADIO_FUNCTIONS + * \ingroup SL_SI91X_API + * @{ */ + +/***************************************************************************/ /** + * @brief + * Start the transmit test. This is a blocking API. + * @pre Pre-conditions: + * - + * [sl_wifi_init](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) should be called before this API. + * @param[in] tx_test_info + * @ref sl_si91x_request_tx_test_info_t Configurable Tx test mode request structure + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + ******************************************************************************/ +sl_status_t sl_si91x_transmit_test_start(sl_si91x_request_tx_test_info_t *tx_test_info); +/***************************************************************************/ /** + * @brief + * Stop the transmit test. This is a blocking API. + * @pre Pre-conditions: + * - + * [sl_wifi_init](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) should be called before this API. + * @param[in] void + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + ******************************************************************************/ +sl_status_t sl_si91x_transmit_test_stop(void); + +/***************************************************************************/ /** + * @brief + * Used to provide feedback of Frequency error in KHz. This is a blocking API. + * @pre Pre-conditions: + * - + * [sl_wifi_init](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) should be called before this API. + * @param[in] frequency_calibration + * Frequency in KHz of type @ref sl_si91x_freq_offset_t. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + *******************************************************************************/ +sl_status_t sl_si91x_frequency_offset(const sl_si91x_freq_offset_t *frequency_calibration); + +/***************************************************************************/ /** + * @brief + * Set the device region. + * @param[in] operation_mode + * @ref sl_si91x_operation_mode_t Operation mode of the device. + * @param[in] band + * @ref sl_si91x_band_mode_t Operational band of the device. + * @param[in] region_code + * @ref sl_si91x_region_code_t Region code to be set in the device. + * @pre Pre-conditions: + * - + * @ref sl_si91x_driver_init should be called before this API. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + ******************************************************************************/ +sl_status_t sl_si91x_set_device_region(sl_si91x_operation_mode_t operation_mode, + sl_si91x_band_mode_t band, + sl_si91x_region_code_t region_code); + +/***************************************************************************/ /** + * @brief + * This API will command the firmware to update the existing Flash/EFuse calibration data. This is a blocking API. + * @pre Pre-conditions: + * - + * [sl_wifi_init](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init), sl_si91x_transmit_test_start and sl_si91x_frequency_offset should be called before this API. + * @param[in] calib_write + * Write calibration configuration of type @ref sl_si91x_calibration_write_t + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + ******************************************************************************/ +sl_status_t sl_si91x_calibration_write(sl_si91x_calibration_write_t calib_write); + +/***************************************************************************/ /** + * @brief + * This API reads the calibration data from the Flash/EFuse storage. This is a blocking API. + * @pre Pre-conditions: + * - + * [sl_wifi_init](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) should be called before this API. + * @param[in] target + * 0 - READ_FROM_EFUSE (read calibration data from the EFuse) + * 1 - READ_FROM_FLASH (read calibration data from the Flash) + * @param[out] calibration_read + * Read the calibration configuration of type @ref sl_si91x_calibration_read_t + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + *******************************************************************************/ +sl_status_t sl_si91x_calibration_read(sl_si91x_calibration_read_t target, + sl_si91x_calibration_read_t *calibration_read); + +/***************************************************************************/ /** + * @brief + * Application that offers feedback on the error caused by the EVM offset. This is a blocking API. + * @pre Pre-conditions: + * - + * [sl_wifi_init](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) should be called before this API. + * @param[in] evm_offset + * evm offset of type @ref sl_si91x_evm_offset_t + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + *******************************************************************************/ +sl_status_t sl_si91x_evm_offset(const sl_si91x_evm_offset_t *evm_offset); + +/***************************************************************************/ /** + * @brief + * This API will command the firmware to update the existing Flash/EFuse calibration data. This is a blocking API. + * @pre Pre-conditions: + * - + * [sl_wifi_init](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init), @ref sl_si91x_evm_offset and @ref sl_si91x_transmit_test_start should be called before this API. + * @param[in] evm_write + * Write the evm calibration configuration of type @ref sl_si91x_evm_write_t + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + *******************************************************************************/ +sl_status_t sl_si91x_evm_write(const sl_si91x_evm_write_t *evm_write); + +/***************************************************************************/ /** + * @brief + * This API updates Flash/Efuse DPD data. This is a synchronous API. + * @pre Pre-conditions: + * - + * [sl_wifi_init](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init), @ref sl_si91x_transmit_test_start should be called before this API. + * @param[in] dpd_calib_data + * Write DPD calibration data of type @ref sl_si91x_get_dpd_calib_data_t + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + ******************************************************************************/ +sl_status_t sl_si91x_dpd_calibration(const sl_si91x_get_dpd_calib_data_t *dpd_calib_data); + +/***************************************************************************/ /** + * @brief + * This API will command the firmware to get the data from the Efuse memory location. This is a blocking API. + * @pre Pre-conditions: + * - + * [sl_wifi_init](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) should be called before this API. + * @param[in] efuse_read + * efuse read structure, which contains efuse read address offset and read data length of type @ref sl_si91x_efuse_read_t + * @param[out] efuse_read_buf + * efuse read buffer + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + *******************************************************************************/ +sl_status_t sl_si91x_efuse_read(sl_si91x_efuse_read_t *efuse_read, uint8_t *efuse_read_buf); + +/** @} */ + +/***************************************************************************/ /** + * @brief + * Send a raw command frame. + * @param[in] command + * Command type to be sent. + * @param[in] data + * Pointer to the command data to be sent. + * @param[in] data_length + * Length of the data length + * @param[in] wait_time + * Wait time for the command response. + * @pre Pre-conditions: + * - + * @ref sl_si91x_driver_init should be called before this API. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + ******************************************************************************/ +sl_status_t sl_si91x_driver_raw_send_command(uint8_t command, + const void *data, + uint32_t data_length, + uint32_t wait_time); + +/***************************************************************************/ /** + * @brief + * Register a event handler for network events. + * @param[in] function + * Function pointer to callback. + * @pre Pre-conditions: + * - + * @ref sl_si91x_driver_init should be called before this API. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + ******************************************************************************/ +sl_status_t sl_si91x_register_event_handler(sl_net_event_handler_t function); + +/***************************************************************************/ /** + * @brief + * Default event handler for all events. + * @param[in] event + * [sl_net_event_t](../wiseconnect-api-reference-guide-nwk-mgmt/sl-net-constants#sl-net-event-t) Asynchronous event received. + * @param[in] buffer + * [sl_wifi_buffer_t](../wiseconnect-api-reference-guide-wi-fi/sl-wifi-buffer-t) Buffer containing data related to asynchronous event. + * @pre Pre-conditions: + * - + * @ref sl_si91x_driver_init should be called before this API. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + ******************************************************************************/ +sl_status_t sl_si91x_default_handler(sl_net_event_t event, sl_wifi_buffer_t *buffer); + +/***************************************************************************/ /** + * @brief + * Enable wireless radio. + * @pre Pre-conditions: + * - + * @ref sl_si91x_driver_init should be called before this API. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + ******************************************************************************/ +sl_status_t sl_si91x_enable_radio(void); + +/***************************************************************************/ /** + * @brief + * Disable wireless radio. + * @pre Pre-conditions: + * - + * @ref sl_si91x_driver_init should be called before this API. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + ******************************************************************************/ +sl_status_t sl_si91x_disable_radio(void); + +/***************************************************************************/ /** + * @brief + * Set device power configuration. + * @param[in] mode + * @ref sl_si91x_power_mode_t Power mode to be set to the device. + * @param[in] config + * @ref sl_si91x_power_configuration_t Pointer to structure containing power configuration. + * @pre Pre-conditions: + * - + * @ref sl_si91x_driver_init should be called before this API. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + ******************************************************************************/ +sl_status_t sl_si91x_set_power_mode(sl_si91x_power_mode_t mode, const sl_si91x_power_configuration_t *config); + +/** @} */ + +/** \addtogroup SI91X_FIRMWARE_UPDATE_FROM_HOST_FUNCTIONS Firmware Update From Host + * \ingroup SI91X_FIRMWARE_UPDATE_FUNCTIONS + * @{ */ + +/***************************************************************************/ /** + * @brief + * Send the RPS header content of firmware file.This is a blocking API. + * @param[in] rps_header + * Pointer to the RPS header content. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + ******************************************************************************/ +sl_status_t sl_si91x_fwup_start(uint8_t *rps_header); + +/***************************************************************************/ /** + * @brief + * Send the firmware file content.This is a blocking API. + * @param[in] content + * Pointer to the firmware file content. + * @param[in] length + * Length of the content + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + ******************************************************************************/ +sl_status_t sl_si91x_fwup_load(uint8_t *content, uint16_t length); + +/***************************************************************************/ /** + * @brief + * This API is used to abort the firmware update process on the SI91x device. This is a blocking API. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + ******************************************************************************/ +sl_status_t sl_si91x_fwup_abort(); +/** @} */ + +/** \addtogroup SI91X_DRIVER_FUNCTIONS + * \ingroup SL_SI91X_API + * @{ */ + +#if defined(SLI_SI91X_MCU_INTERFACE) || defined(DOXYGEN) +/*==============================================*//** + * @brief Secure handshake. This is a blocking API. + * + * @param[in] sub_cmd_type Specifies the Sub command type for the secure handshake. + * @param[in] input_data Input data is a pointer that contains the information used during a secure handshake. + * @param[in] input_len Specifies the length of input data. + * @param[in] output_len Specifies the length of output data. + * @param[in] output_data Pointer to store the response data after the secure handshake process. + * + * @return sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + * + */ +sl_status_t sl_si91x_m4_ta_secure_handshake(uint8_t sub_cmd_type, + uint8_t input_len, + uint8_t *input_data, + uint8_t output_len, + uint8_t *output_data); +#endif + +/***************************************************************************/ /** + * @brief + * Si91X specific set join feature bitmap configuration + * @param[in] interface + * [sl_wifi_interface_t](../wiseconnect-api-reference-guide-wi-fi/sl-wifi-constants#sl-wifi-interface-t) Selected interface. + * @param[in] join_feature_bitmap + * Join feature bitmap configuration. One of values from @ref SI91X_JOIN_FEATURE_BIT_MAP + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + * @note + * By default SL_SI91X_JOIN_FEAT_LISTEN_INTERVAL_VALID bitmap is enabled. User can call this API before calling [sl_wifi_connect](../wiseconnect-api-reference-guide-wi-fi/wifi-client-api#sl-wifi-connect), [sl_wifi_start_ap](../wiseconnect-api-reference-guide-wi-fi/wifi-ap-api#sl-wifi-start-ap), [sl_wifi_start_wps](../wiseconnect-api-reference-guide-wi-fi/wifi-wps-api#sl-wifi-start-wps) to overwrite the join feature bitmap + *******************************************************************************/ + +sl_status_t sl_si91x_set_join_configuration(sl_wifi_interface_t interface, uint8_t join_feature_bitmap); + +/***************************************************************************/ /** + * @brief + * Si91X specific get join feature bitmap configuration + * @param[in] interface + * [sl_wifi_interface_t](../wiseconnect-api-reference-guide-wi-fi/sl-wifi-constants#sl-wifi-interface-t) Selected interface. + * @param[out] join_feature_bitmap + * join feature bitmap configuration. One of values from @ref SI91X_JOIN_FEATURE_BIT_MAP + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + * @note + * By default SL_SI91X_JOIN_FEAT_LISTEN_INTERVAL_VALID bitmap is enabled. + *******************************************************************************/ +sl_status_t sl_si91x_get_join_configuration(sl_wifi_interface_t interface, uint8_t *join_feature_bitmap); + +/***************************************************************************/ /** + * @brief + * This API is used to set different module timeouts. + * @pre Pre-conditions: + * - + * @ref This API should be called after [sl_wifi_init](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) + * @param[in] timeout_type + * It is used to identify which timeout type to be set. The possible values can be @ref sl_si91x_timeout_type_t + - + * @param[in] timeout_value + * timeout value to be set. The time resolution depends on timeout_type. + * @note + * After a successful IP configuration, Gratuitous ARP is used as the periodic WLAN Keep-Alive packet with the configured keep_alive_timeout interval. + - + * If there is no IP configuration, the NULL Data Packets is used as the WLAN Keep-Alive packet. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + * + */ +sl_status_t sl_si91x_configure_timeout(sl_si91x_timeout_type_t timeout_type, uint16_t timeout_value); + +/***************************************************************************/ /** + * @brief + * Si91x specific set timeout. This function is used to set active channel scan timeout, authentication association timeout and keep alive timeout of module. + * @param[in] timeout_config + * Timeout configuration of type @ref sl_si91x_timeout_t. + * @return None + * @note + * This API should ONLY be called before [sl_wifi_init](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) and repeated call to this API will overwrite timeout values stored in SDK, will be applied on next call to [sl_wifi_init](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init). + *******************************************************************************/ +void sl_si91x_set_timeout(sl_si91x_timeout_t *timeout_config); + +/** @} */ + +/** \addtogroup SI91X_FIRMWARE_UPDATE_FROM_MODULE_FUNCTIONS Firmware Update From Module + * \ingroup SI91X_FIRMWARE_UPDATE_FUNCTIONS + * @{ */ +/***************************************************************************/ /** + * @brief + * Create an OTAF client. Initialize the client with a given configuration. + * @pre Pre-conditions: + * - + * [sl_net_up](../wiseconnect-api-reference-guide-nwk-mgmt/net-interface-functions#sl-net-up) API needs to be called before this API. + * @param[in] server_ip + * OTAF server IP address @ref sl_ip_address_t + * @param[in] server_port + * OTAF server port number. + * @param[in] chunk_number + * Firmware content request chunk number. + * @param[in] timeout + * TCP receive packet timeout. + * @param[in] tcp_retry_count + * TCP retransmissions count. + * @param[in] asynchronous + * OTAF upgrade done aynchronously when this is set, else synchronous upgrade. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + * @note For safe firmware upgrade via TCP server, + - + * it will take approx. 65 sec duration for upgrading the firmware of 1.5 MB file. + * @note + * This is an asynchronous API. The response is recieved via [sl_net_event_handler_t](../wiseconnect-api-reference-guide-nwk-mgmt/sl-net-types#sl-net-event-handler-t) with [SL_NET_OTA_FW_UPDATE_EVENT](../wiseconnect-api-reference-guide-nwk-mgmt/sl-net-constants#sl-net-event-t) as event + ******************************************************************************/ +sl_status_t sl_si91x_ota_firmware_upgradation(sl_ip_address_t server_ip, + uint16_t server_port, + uint16_t chunk_number, + uint16_t timeout, + uint16_t tcp_retry_count, + bool asynchronous); + +/** @} */ + +/** \addtogroup SI91X_DRIVER_FUNCTIONS + * \ingroup SL_SI91X_API + * @{ */ +/***************************************************************************/ /** + * @brief This function allows the Network Processor (NWP) to write content to the common flash from M4. + * It's a blocking API. + * @param[in] write_address + * The address in the common flash memory where the write operation should begin. + * For the M4 region, the write address should start from 0x8000000. Possible values range from the M4 image end address to the M4 region end address. + * For the NWP region, the write address should range from 0 to (20K-1). + * @param[in] write_data + * The data to be written. For sector erase it should be multiples of 4K. + * @param[in] write_data_length + * The total length of the data, which should be multiples of 4K for sector erase. + * @param[in] flash_sector_erase_enable + * Enable or disable sector erase. + * 1 - Erases multiples of 4 KB of data. + * 0 - Disable, allows to write data onto flash. + * @return sl_status_t. Refer to https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + ******************************************************************************/ +sl_status_t sl_si91x_command_to_write_common_flash(uint32_t write_address, + uint8_t *write_data, + uint16_t write_data_length, + uint8_t flash_sector_erase_enable); + +/***************************************************************************/ /** + * @brief Sends a command to read data from the NWP flash memory of the SI91x wireless device. This is a blocking API. + * This function is a command to the SI91x wireless device to read data from the NWP flash memory + * at the specified address. The read data is stored in the provider's output_data buffer. + * @param[in] read_address + * The address in the NWP flash memory to read from. The address should range from 0 to (20K-1). + * @param[in] length + * The number of bytes to read from the NWP flash memory. + * @param[out] output_buffer + * Pointer to the buffer where the data will be. + * @return sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + ******************************************************************************/ +sl_status_t sl_si91x_command_to_read_common_flash(uint32_t read_address, size_t length, uint8_t *output_buffer); +/** @} */ + +/***************************************************************************/ /** + * @brief + * Get the current Opermode of the module. + * @param[in] void + * @return + * sl_si91x_operation_mode_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + ******************************************************************************/ +sl_si91x_operation_mode_t get_opermode(void); + +/***************************************************************************/ /** + * @brief + * Si91X specific set listen interval + * @param[in] listen_interval + * Wi-Fi Listen interval. + * @return none + *******************************************************************************/ +void sl_si91x_set_listen_interval(uint32_t listen_interval); + +/***************************************************************************/ /** + * @brief + * Si91X specific get listen interval + * @return uint32_t + * Wi-Fi Listen interval + *******************************************************************************/ +uint32_t sl_si91x_get_listen_interval(void); + +/** \addtogroup SI91X_DRIVER_FUNCTIONS + * \ingroup SL_SI91X_API + * @{ */ + +/** + * @brief Signals the occurrence of an assertion in the firmware. + * @return sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. +*/ +sl_status_t sl_si91x_assert(void); + +/***************************************************************************/ /** + * @brief + * Retrieves TA RAM log/dump via Si91x UART/UART2. + * @param[in] address + * Address in Si91x module. + * @param[in] length + * Chunk length to read from Si91x module. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + ******************************************************************************/ +sl_status_t sl_si91x_get_ram_log(uint32_t address, uint32_t length); + +/** @} */ + +/***************************************************************************/ /** + * @brief Si91X specific Wi-Fi transceiver mode driver function to send Tx data + * @param[in] control - Meta data for the payload. + * @param[in] payload - Pointer to payload to be sent to LMAC. + * @param[in] payload_len - Length of the payload. + * @param[in] wait_time - Wait time for the command response. + * @return sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + *******************************************************************************/ +sl_status_t sl_si91x_driver_send_transceiver_data(sl_wifi_transceiver_tx_data_control_t *control, + uint8_t *payload, + uint16_t payload_len, + uint32_t wait_time); + +/***************************************************************************/ /** + * @brief + * Register a function and optional argument for scan results callback. + * @param[in] command + * Command type to be sent to TA firmware. + * @param[in] queue_type + * @ref sl_si91x_queue_type_t Queue type to be used to send the command on. + * @param[in] data + * Command packet to be sent to the TA firmware. + * @param[in] data_length + * Length of command packet. + * @param[in] wait_period + * @ref sl_si91x_wait_period_t Timeout for the command response. + * @param[in] sdk_context + * Pointer to the context. + * @param[in] data_buffer + * [sl_wifi_buffer_t](../wiseconnect-api-reference-guide-wi-fi/sl-wifi-buffer-t) Pointer to a data buffer pointer for the response data to be returned in. + * @param[in] custom_host_desc + * Custom Variable to send additional data to the firmware through the host descriptor. + * @pre Pre-conditions: + * - + * @ref sl_si91x_driver_init should be called before this API. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + ******************************************************************************/ +sl_status_t sl_si91x_custom_driver_send_command(uint32_t command, + sl_si91x_queue_type_t queue_type, + const void *data, + uint32_t data_length, + sl_si91x_wait_period_t wait_period, + void *sdk_context, + sl_wifi_buffer_t **data_buffer, + uint8_t custom_host_desc); + +/** \addtogroup SI91X_FIRMWARE_UPDATE_FROM_HOST_FUNCTIONS + * @{ */ + +/***************************************************************************/ /** + * @brief + * Flashes firmware to Wi-Fi module via bootloader. + * @param[in] firmware_image + * Pointer to firmware. + * @param[in] fw_image_size + * Size of firmware image.. + * @param[in] flags + * Flags indicating chuck position in file + * 0 = Middle of file + * 1 = Start of file + * 2 = End of file + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + ******************************************************************************/ +sl_status_t sl_si91x_bl_upgrade_firmware(uint8_t *firmware_image, uint32_t fw_image_size, uint8_t flags); + +/***************************************************************************/ /** + * @brief + * Set fast firmware upgrade. + * @param[in] void + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + ******************************************************************************/ +sl_status_t sl_si91x_set_fast_fw_up(void); + +/** @} */ diff --git a/wiseconnect/components/device/silabs/si91x/wireless/inc/sl_si91x_host_interface.h b/wiseconnect/components/device/silabs/si91x/wireless/inc/sl_si91x_host_interface.h new file mode 100644 index 000000000..d0fa4d0e2 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/inc/sl_si91x_host_interface.h @@ -0,0 +1,153 @@ +/***************************************************************************/ /** + * @file + * @brief + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#pragma once + +#include "sl_status.h" +#include "sl_wifi_types.h" +#include "sl_wifi_host_interface.h" +#include "sl_si91x_types.h" +#include "sl_wifi_device.h" +#include +#include + +typedef sl_status_t (*sl_si91x_host_rx_irq_handler)(void); +typedef void (*sl_si91x_host_rx_done_handler)(void); + +typedef struct { + sl_si91x_host_rx_irq_handler rx_irq; + sl_si91x_host_rx_done_handler rx_done; +} sl_si91x_host_init_configuration; + +/** + * @brief + * This API will make RST GPIO to low. + */ +void sl_si91x_host_hold_in_reset(void); + +/** + * @brief + * This API used to release the device from reset state. + */ +void sl_si91x_host_release_from_reset(void); + +/** + * @brief + * This API used to allocate all threads, mutexes and event handlers + * @return sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + */ +sl_status_t sl_si91x_host_init(sl_si91x_host_init_configuration *config); + +/** + * @brief + * This API used to deallocate all threads, mutexes and event handlers. + * @return sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + */ +sl_status_t sl_si91x_host_deinit(void); + +// --------------- +/** + * @brief + * This API is responsible for configuring a high speed communication bus. + */ +void sl_si91x_host_enable_high_speed_bus(); + +/** + * @brief + * This API is used for processing the data frames. + * @param interface + * [sl_wifi_interface_t](../wiseconnect-api-reference-guide-wi-fi/sl-wifi-constants#sl-wifi-interface-t) Wi-Fi interface on which the data frame needs to be processed. + * @param buffer + * pointer to a structure of type [sl_wifi_buffer_t](../wiseconnect-api-reference-guide-wi-fi/sl-wifi-buffer-t) containing the data frame to be processed. + * @return sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + */ +sl_status_t sl_si91x_host_process_data_frame(sl_wifi_interface_t interface, sl_wifi_buffer_t *buffer); + +/** + * @brief + * Enable interrupts + * + */ +void sl_si91x_host_enable_bus_interrupt(void); + +/** + * @brief + * Disable interrupts + */ +void sl_si91x_host_disable_bus_interrupt(void); + +/** + * @brief + * Sets sleep Indication GPIO to HIGH. + * + */ +void sl_si91x_host_set_sleep_indicator(void); + +/** +* @addtogroup EXTERNAL_HOST_INTERFACE_FUNCTIONS +* @{ +*/ + +/** + * @brief + * Sets sleep Indication GPIO to LOW + */ +void sl_si91x_host_clear_sleep_indicator(void); + +/** @} */ + +/** + * @brief + * Reads Wakeup Indication GPIO value + * + * @return uint32_t + */ +uint32_t sl_si91x_host_get_wake_indicator(void); + +sl_status_t sl_si91x_host_spi_transfer( + const void *tx_buffer, + void *rx_buffer, + uint16_t buffer_length); /*Function used for data transfer between TA and MCU over SPI*/ + +sl_status_t sl_si91x_host_uart_transfer( + const void *tx_buffer, + void *rx_buffer, + uint16_t buffer_length); /*Function used for data transfer between TA and MCU over UART/USART*/ + +void sl_si91x_host_flush_uart_rx(void); /*Function used to flush all the old data in the uart/usart rx stream*/ + +void sl_si91x_host_uart_enable_hardware_flow_control(void); /*Function to enable Hardware Flow Control on host*/ + +/** + * @brief Check whether the current CPU operation mode is handler mode + * + * @return true + * @return false + */ +bool sl_si91x_host_is_in_irq_context(void); \ No newline at end of file diff --git a/wiseconnect/components/device/silabs/si91x/wireless/inc/sl_si91x_protocol_types.h b/wiseconnect/components/device/silabs/si91x/wireless/inc/sl_si91x_protocol_types.h new file mode 100644 index 000000000..55dd2ca56 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/inc/sl_si91x_protocol_types.h @@ -0,0 +1,2161 @@ +/***************************************************************************/ /** + * @file + * @brief + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#pragma once + +#include +#include "sl_ieee802_types.h" +#include "sl_ip_types.h" +#include "sl_wifi_constants.h" +#include "sl_si91x_constants.h" +#include "sl_common.h" + +// below defines and structure for CFG_GET: Getting user store configuration. +#define IP_ADDRESS_SZ 4 +#define RSI_SSID_LEN 34 +#define WISE_PMK_LEN 32 +#define MAX_HTTP_SERVER_USERNAME 31 +#define MAX_HTTP_SERVER_PASSWORD 31 +#define RSI_PSK_LEN 64 +#define RSI_MAC_ADDR_LEN 6 + +// A macro to define the size of array in sl_si91x_socket_info_response_t to hold socket data. +#define SL_SI91X_SOCKET_INFO_RESPONSE_SOCKETS_COUNT 10 + +// Maximum Access points that can be scanned +#define RSI_AP_SCANNED_MAX 11 + +// Maximum number of stations associated when running as an AP +#define SI91X_MAX_STATIONS 16 + +// Quick reference: Bit 3 -> DHCPv6 client, Bit 5 -> DHCPv6 server, Bit 17 -> TCP_IP_FEAT_IPV6 +// Details: https://docs.silabs.com/rs9116-wiseconnect/latest/wifibt-wc-sapi-reference/opermode#rsi-tcp-ip-feature-bit-map +#define SI91X_IPV6_MODE (1 << 3) | (1 << 5) | (1 << 17) +#define RSI_IP_ADDRESS_LEN 4 +// Maximum payload size +#define RSI_MAX_PAYLOAD_SIZE 1500 + +#define SL_MAX_FWUP_CHUNK_SIZE 1024 +#define SL_RPS_HEADER_SIZE 64 + +// Firmware upgrade packet types +#define SL_FWUP_ABORT 2 +#define SL_FWUP_RPS_HEADER 1 +#define SL_FWUP_RPS_CONTENT 0 + +// Websocket max url length +#define RSI_WEBS_MAX_URL_LENGTH 51 + +// Websocket max host length +#define RSI_WEBS_MAX_HOST_LENGTH 51 + +#ifdef SLI_SI917 +#define SI91X_MAX_SIZE_OF_EXTENSION_DATA 256 +#else +#define SI91X_MAX_SIZE_OF_EXTENSION_DATA 64 +#endif + +#define SI91X_DNS_REQUEST_MAX_URL_LEN 90 + +#define SI91X_DNS_RESPONSE_MAX_ENTRIES 10 + +#define SI91X_MAX_CERT_SEND_SIZE 1400 + +/** NOTE: For power save related info + * https://confluence.silabs.com/pages/viewpage.action?spaceKey=RPD&title=Master+++Power+Save+modes + * https://confluence.silabs.com/display/RPD/Master+WLAN+APIs#MasterWLANAPIs-rsi_wlan_power_save_profile + * https://docs.silabs.com/rs9116/wiseconnect/rs9116w-wifi-at-command-prm/latest/wlan-commands#rsi-pwmode----power-mode + * NOTE: Wake up procedure provided in Confluence is outdated, Please refer AT PRM for it. + * ****************************** POWER RELATED DEFINES START *******************************/ +#define SL_POWER_MODE_DISABLE 0 +#define SL_CONNECTED_SLEEP_PS 1 +#define SL_CONNECTED_GPIO_BASED_PS 2 +#define SL_CONNECTED_MSG_BASED_PS 3 + +#ifdef SLI_SI91X_MCU_INTERFACE +#define SL_CONNECTED_M4_BASED_PS 4 +#endif + +#define SL_GPIO_BASED_DEEP_SLEEP 8 +#define SL_MSG_BASED_DEEP_SLEEP 9 + +#ifdef SLI_SI91X_MCU_INTERFACE +#define SL_M4_BASED_DEEP_SLEEP 10 +#endif + +#define DEFAULT_MONITOR_INTERVAL 50 +#define DEFAULT_DTIM_SKIP 0 +#define DEFAULT_DTIM_ALIGNMENT 0 + +#define SL_LP_MODE 0 +#define SL_ULP_WITH_RAM_RETENTION 1 +#define SL_ULP_WITHOUT_RAM_RET_RETENTION 2 + +#define SL_MAX_PSP 0 +#define SL_FAST_PSP 1 + +/****************************** POWER RELATED DEFINES END ***********************************/ + +// **************************** Macros for BG scan **************************************/ +#define SI91X_BG_SCAN_DISABLE 0 +#define SI91X_BG_SCAN_ENABLE 1 +#define SI91X_INSTANT_SCAN_DISABLE 0 +#define SI91X_INSTANT_SCAN_ENABLE 1 + +//**************************** Macros for BG end *********************************/ +#define NUMBER_OF_BSD_SOCKETS 10 + +//**************************** Macros for WPS Method request START *********************************/ + +#define SI91X_SET_WPS_METHOD_PUSH_BUTTON 0 +#define SI91X_SET_WPS_METHOD_PIN 1 +#define Si91X_SET_WPS_VALIDATE_PIN 0 +#define SI91X_SET_WPS_GENERATE_PIN 1 +#define SI91X_WPS_PIN_LEN 8 + +//**************************** Macros for WPS Method request END ***********************************/ + +/** \addtogroup SI91X_JOIN_FEATURE_BIT_MAP + * @{ */ +/*=========================================================================*/ +// Join feature bit map parameters description !// +/*=========================================================================*/ +/// To enable b/g only mode in station mode +#define SL_SI91X_JOIN_FEAT_STA_BG_ONLY_MODE_ENABLE (1 << 0) + +/// To take listen interval from join command. +#define SL_SI91X_JOIN_FEAT_LISTEN_INTERVAL_VALID (1 << 1) + +/// To enable quick join feature +#define SL_SI91X_JOIN_FEAT_QUICK_JOIN (1 << 2) + +/// To enable CCXV2 feature +#define SL_SI91X_JOIN_FEAT_CCXV2_FEATURE (1 << 3) + +/// To connect to AP based on BSSID together with configured SSID +#define SL_SI91X_JOIN_FEAT_BSSID_BASED (1 << 4) + +/// MFP Capable only +#define SL_SI91X_JOIN_FEAT_MFP_CAPABLE_ONLY (1 << 5) + +/// MFP Capable required +#define SL_SI91X_JOIN_FEAT_MFP_CAPABLE_REQUIRED ((1 << 5) | (1 << 6)) + +/// listen interval from power save command +#define SL_SI91X_JOIN_FEAT_PS_CMD_LISTEN_INTERVAL_VALID (1 << 7) +/** @} */ + +//**************************** Macros for FEATURE frame Method request START *********************************/ +#define SI91X_FEAT_FRAME_PREAMBLE_DUTY_CYCLE (1 << 0) +#define SI91X_FEAT_FRAME_PERMIT_UNDESTINED_PACKETS (1 << 1) +#define SI91X_FEAT_FRAME_LP_CHAIN (1 << 4) +#define SI91X_FEAT_FRAME_IN_PACKET_DUTY_CYCLE (1 << 5) + +#define PLL_MODE 0 +#define RF_TYPE 1 // 0 - External RF 1- Internal RF +#define WIRELESS_MODE 0 +#define ENABLE_PPP 0 +#define AFE_TYPE 1 +#ifndef FEATURE_ENABLES +#define FEATURE_ENABLES \ + (SI91X_FEAT_FRAME_PREAMBLE_DUTY_CYCLE | SI91X_FEAT_FRAME_LP_CHAIN | SI91X_FEAT_FRAME_IN_PACKET_DUTY_CYCLE) +#endif + +//**************************** Macros for FEATURE frame Method request END *********************************/ + +//**************************** Macros for HTTP Client START *********************************/ + +#define SI91X_HTTP_BUFFER_LEN 2400 +#define SI91X_MAX_HTTP_URL_SIZE 2048 +#define SI91X_MAX_HTTP_CHUNK_SIZE 900 +#define HTTP_GET_FIRST_PKT BIT(0) +#define HTTP_GET_MIDDLE_PKT BIT(1) +#define HTTP_GET_LAST_PKT BIT(2) + +#define SI91X_HTTP_CLIENT_MAX_WRITE_BUFFER_LENGTH 900 +#define SI91X_HTTP_CLIENT_PUT_MAX_BUFFER_LENGTH 900 +#define SI91X_HTTP_CLIENT_POST_MAX_BUFFER_LENGTH 900 + +// HTTP client PUT create command +#define SI91X_HTTP_CLIENT_PUT_CREATE 1 + +// HTTP client PUT START command +#define SI91X_HTTP_CLIENT_PUT_START 2 + +// HTTP client PUT PKT command +#define SI91X_HTTP_CLIENT_PUT_PKT 3 + +// HTTP client PUT DELETE command +#define SI91X_HTTP_CLIENT_PUT_DELETE 4 + +// HTTP client PUT PKT OFFSET command +#define SI91X_HTTP_CLIENT_PUT_OFFSET_PKT 5 + +//***************************** Macros for HTTP Client End **********************************/ + +#define SI91X_COUNTRY_CODE_LENGTH 3 +#define SI91X_MAX_POSSIBLE_CHANNEL 24 + +#define ATTESTATION 30 + +#define NONCE_DATA_SIZE 32 + +typedef enum { RSI_NONE, RSI_TKIP, RSI_CCMP } sl_si91x_encryption_mode_t; + +// Set region command request structure +typedef struct { + // Enable or disable set region from user: 1-take from user configuration,0-Take from Beacons + uint8_t set_region_code_from_user_cmd; + + // region code(1-US,2-EU,3-JP,4-World Domain,5-KR)*/ + uint8_t region_code; + + // module type (0- Without on board antenna, 1- With on board antenna) + uint16_t module_type; +} sl_si91x_set_region_request_t; + +// Set region in AP mode command request structure +typedef struct { + // Enable or disable set region from user: 1-take from user configuration, 0-Take US or EU or JP + uint8_t set_region_code_from_user_cmd; + + // region code(1-US,2-EU,3-JP) + uint8_t country_code[SI91X_COUNTRY_CODE_LENGTH]; + + uint32_t no_of_rules; + + struct { + uint8_t first_channel; + uint8_t no_of_channels; + uint8_t max_tx_power; + } channel_info[SI91X_MAX_POSSIBLE_CHANNEL]; +} sl_si91x_set_region_ap_request_t; + +// Scan command request structure +// channel: RF channel to scan, 0=All, 1-14 for 2.5GHz channels 1-14 +typedef struct { + uint8_t channel[4]; + uint8_t ssid[RSI_SSID_LEN]; + uint8_t pscan_bitmap[4]; + uint8_t _reserved; + uint8_t scan_feature_bitmap; + uint8_t channel_bit_map_2_4[2]; + uint8_t channel_bit_map_5[4]; +} sl_si91x_req_scan_t; + +// bg scan command request structure +typedef struct { + // enable or disable BG scan + uint16_t bgscan_enable; + + // Is it instant bgscan or normal bgscan + uint16_t enable_instant_bgscan; + + // bg scan threshold value + uint16_t bgscan_threshold; + + // tolerance threshold + uint16_t rssi_tolerance_threshold; + + // periodicity + uint16_t bgscan_periodicity; + + // active scan duration + uint16_t active_scan_duration; + + // passive scan duration + uint16_t passive_scan_duration; + + // multi probe + uint8_t multi_probe; +} sl_si91x_req_bg_scan_t; + +// Scan information response structure +// rf_channel: channel number of the scanned AP +// security_mode: security mode of the scanned AP +// rssi_val: rssi value of the scanned AP +// network_type: network type of the scanned AP +// ssid: SSID of the scanned AP +// bssid: BSSID of the scanned AP +typedef struct { + uint8_t rf_channel; + uint8_t security_mode; + uint8_t rssi_val; + uint8_t network_type; + uint8_t ssid[RSI_SSID_LEN]; + uint8_t bssid[RSI_MAC_ADDR_LEN]; + uint8_t reserved[2]; +} sl_si91x_scan_info_t; + +// Scan command response structure +// scan_count: number of access points scanned +// scan_info: scanned access points information +typedef struct { + uint8_t scan_count[4]; + uint8_t reserved[4]; + sl_si91x_scan_info_t scan_info[RSI_AP_SCANNED_MAX]; +} sl_si91x_rsp_scan_t; + +// Antenna select command request structure +typedef struct { + // Antenna value to set + uint8_t antenna_value; + // Antenna 2G gain value + uint8_t gain_2g; + // Antenna 5G gain value + uint8_t gain_5g; +} sl_si91x_antenna_select_t; + +// PSK command request structure +typedef struct { + // psk type , 1-psk alone, 2-pmk, 3-generate pmk from psk + uint8_t type; + + // psk or pmk + uint8_t psk_or_pmk[RSI_PSK_LEN]; + + // access point ssid: used for generation pmk + uint8_t ap_ssid[RSI_SSID_LEN]; +} sl_si91x_req_psk_t; + +// Enterprise configuration command request structure +typedef struct { + // EAP method + uint8_t eap_method[32]; + + // Inner method + uint8_t inner_method[32]; + + // Username + uint8_t user_identity[64]; + + // Password + uint8_t password[128]; + + // Opportunistic key caching enable + int8_t okc_enable[4]; + + // Private key password for encrypted private keys + uint8_t private_key_password[82]; +} sl_si91x_req_eap_config_t; + +// Set certificate information structure +typedef struct { + uint16_t total_len; // total length of the certificate + uint8_t certificate_type; // type of certificate + uint8_t more_chunks; // more chunks flag + uint16_t certificate_length; // length of the current segment + uint8_t certificate_inx; // index of certificate + uint8_t key_password[127]; // reserved +} sl_si91x_cert_info_t; + +typedef struct { + uint16_t socket_id; // Socket ID + volatile uint16_t status; // certificate valid status +} sl_si91x_req_cert_valid_t; + +// Set certificate command request structure +typedef struct { + sl_si91x_cert_info_t cert_info; // certificate information structure + uint8_t certificate[SI91X_MAX_CERT_SEND_SIZE]; // certificate +} sl_si91x_req_set_certificate_t; + +// join command request structure +#pragma pack(1) +typedef struct { + // reserved bytes:Can be used for security Type + uint8_t reserved1; + + // 0- Open, 1-WPA, 2-WPA2,6-MIXED_MODE, 7-WPA3, 8-WP3_Transition + uint8_t security_type; + + // data rate, 0=auto, 1=1Mbps, 2=2Mbps, 3=5.5Mbps, 4=11Mbps, 12=54Mbps + uint8_t data_rate; + + // transmit power level, 0=low (6-9dBm), 1=medium (10-14dBm, 2=high (15-17dBm) + uint8_t power_level; + + // pre-shared key, 63-byte string , last character is NULL + uint8_t psk[RSI_PSK_LEN]; + + // ssid of access point to join to, 34-byte string + uint8_t ssid[RSI_SSID_LEN]; + + // feature bitmap for join + uint8_t join_feature_bitmap; + + // reserved bytes + uint8_t reserved2[2]; + + // length of ssid given + uint8_t ssid_len; + + // listen interval + uint32_t listen_interval; + + // vap id, 0 - station mode, 1 - AP mode + uint8_t vap_id; + + // join bssid for mac based join + uint8_t join_bssid[6]; +} sl_si91x_join_request_t; +#pragma pack() + +// IPV4 ipconfig command request structure +typedef struct { + // 0=Manual, 1=Use DHCP + uint8_t dhcp_mode; + + // IP address of this module if in manual mode + uint8_t ipaddress[4]; + + // Netmask used if in manual mode + uint8_t netmask[4]; + + // IP address of default gateway if in manual mode + uint8_t gateway[4]; + + // DHCP client host name + uint8_t hostname[31]; + + // vap id, 0 - station and 1 - AP + uint8_t vap_id; +} sl_si91x_req_ipv4_params_t; + +// IPV4 ipconfig command response structure +typedef struct { + // MAC address of this module + uint8_t macAddr[6]; + + // Configured IP address + uint8_t ipaddr[4]; + + // Configured netmask + uint8_t netmask[4]; + + // Configured default gateway + uint8_t gateway[4]; +} sl_si91x_rsp_ipv4_params_t; + +// IPV6 ipconfig command request structure +typedef struct { + // 0=Manual, 1=Use DHCP + uint8_t mode[2]; + + // prefix length + uint8_t prefixLength[2]; + + // IPV6 address of the module + uint8_t ipaddr6[16]; + + // address of gateway + uint8_t gateway6[16]; + + // vap id, 0 - station and 1 - AP + uint8_t vap_id; +} sl_si91x_req_ipv6_params_t; + +// IPV6 ipconfig command response structure +typedef struct { + // prefix length + uint16_t prefixLength; + + // reserved bytes + uint16_t reserved; + + // Link local address + uint32_t link_local_address[4]; + + // Global address + uint32_t global_address[4]; + + // Gateway address + uint32_t gateway_address[4]; + + // Mac address + uint8_t mac_address[6]; + +} sl_si91x_rsp_ipv6_params_t; + +// Structure for firmware upgradation +typedef struct { + // Type of the packet + uint16_t type; + + // Length of the packet + uint16_t length; + + // RPS content + uint8_t content[SL_MAX_FWUP_CHUNK_SIZE]; +} sl_si91x_req_fwup_t; + +// RTC time from host +typedef struct { + // seconds [0-59] + uint32_t tm_sec; + // minutes [0-59] + uint32_t tm_min; + // hours since midnight [0-23] + uint32_t tm_hour; + // day of the month [1-31] + uint32_t tm_mday; + // months since January [0-11] + uint32_t tm_mon; + // year since 1990 + uint32_t tm_year; + // Weekday from Sunday to Saturday [1-7] + uint32_t tm_wday; +} sl_si91x_module_rtc_time_t; + +// wireless information +typedef struct { + // wlan state: connected or disconnected in station mode + // wlan state: no of stations connected in AP mode + uint16_t wlan_state; + + // channel number of connected AP + uint16_t channel_number; + + // uint8[32], SSID of connected access point + uint8_t ssid[RSI_SSID_LEN]; + + // Mac address + uint8_t mac_address[6]; + + // security type + uint8_t sec_type; + + // PSK + uint8_t psk[64]; + + // uint8[4], Module IP Address + uint8_t ipv4_address[4]; + + // uint8[16], Module IPv6 Address + uint8_t ipv6_address[16]; + + // reserved1 + uint8_t reserved1[2]; + + // reserved2 + uint8_t reserved2[2]; +} sl_si91x_rsp_wireless_info_t; + +// socket create command request structure +#pragma pack(1) +typedef struct { + // ip version4 or 6 + uint16_t ip_version; + + // 0=TCP Client, 1=UDP Client, 2=TCP Server (Listening TCP) + uint16_t socket_type; + + // Our local module port number + uint16_t local_port; + + // Port number of what we are connecting to + uint16_t remote_port; + + union { + // remote IPv4 Address + uint8_t ipv4_address[4]; + + // remote IPv6 Address + uint8_t ipv6_address[16]; + } dest_ip_addr; + + // maximum no of LTCP sockets on same port + uint16_t max_count; + +// type of service +#ifdef SLI_SI917 + uint16_t tos; +#else + uint32_t tos; +#endif + +// ssl version select bit map +#ifdef SLI_SI917 + uint32_t ssl_bitmap; +#else + uint8_t ssl_bitmap; + + // ssl ciphers bitmap + uint8_t ssl_ciphers; +#endif + // web socket resource name + uint8_t webs_resource_name[RSI_WEBS_MAX_URL_LENGTH]; + + // web socket host name + uint8_t webs_host_name[RSI_WEBS_MAX_HOST_LENGTH]; + + // TCP retries + uint8_t max_tcp_retries_count; + + // Socket bitmap + uint8_t socket_bitmap; + + // RX window size + uint8_t rx_window_size; + + // TCP keepalive initial timeout + uint16_t tcp_keepalive_initial_time; + + // VAPID + uint8_t vap_id; + + //socket cert inx + uint8_t socket_cert_inx; + + //ssl ciphers bitmap + uint32_t ssl_ciphers_bitmap; + +#ifdef SLI_SI917 + // ssl extended ciphers bitmap + uint32_t ssl_ext_ciphers_bitmap; + + // max retransmission timeout value + uint8_t max_retransmission_timeout_value; +#endif + + // tcp retry transmission timer + uint8_t tcp_retry_transmit_timer; + + // TCP MSS + uint16_t tcp_mss; + + uint16_t no_of_tls_extensions; + uint16_t total_extension_length; + uint8_t tls_extension_data[SI91X_MAX_SIZE_OF_EXTENSION_DATA]; + +#ifdef SLI_SI917 + uint16_t recv_buff_len; +#endif + +} sl_si91x_socket_create_request_t; +#pragma pack() + +// socket create command response structure +typedef struct { + // ip version 4 or 6 + uint8_t ip_version[2]; + + // 2 bytes, type of socket created + uint8_t socket_type[2]; + + // 2 bytes socket descriptor, like a file handle, usually 0x00 + uint8_t socket_id[2]; + + // 2 bytes, Port number of our local socket + uint8_t module_port[2]; + + uint8_t dst_port[2]; + union { + + // 4 bytes, Our (module) IPv4 Address + uint8_t ipv4_addr[4]; + + // 4 bytes, Our (module) IPv6 Address + uint8_t ipv6_addr[16]; + } module_ip_addr; + + union { + // 4 bytes, Our (module) IPv4 Address + uint8_t ipv4_addr[4]; + // 4 bytes, Our (module) IPv6 Address + uint8_t ipv6_addr[16]; + } dest_ip_addr; + + // 2 bytes, Remote peer MSS size + uint8_t mss[2]; + + // 4 bytes, Remote peer Window size + uint8_t window_size[4]; +} sl_si91x_socket_create_response_t; + +// Socket close command request structure +#pragma pack(1) +typedef struct { + // 2 bytes, socket that was closed + uint16_t socket_id; + + // 4 bytes, port number + uint16_t port_number; +} sl_si91x_socket_close_request_t; +#pragma pack() + +// Socket close command response structure +#pragma pack(1) +typedef struct { + // 2 bytes, socket that was closed + uint16_t socket_id; + + // 4 bytes, sent bytes count + uint32_t sent_bytes_count; + + // 2 bytes, port number + uint16_t port_number; +} sl_si91x_socket_close_response_t; +#pragma pack() + +#pragma pack(1) +// send data on socket request structure +typedef struct { + // ip version 4 or 6 + uint16_t ip_version; + + // socket descriptor of the already opened socket connection + uint16_t socket_id; + + // length of the data to be sent + uint32_t length; + + // Data Offset + uint16_t data_offset; + + // destination port + uint16_t dest_port; + + union { + // 4 bytes, IPv4 Address of the remote device + uint8_t ipv4_address[RSI_IP_ADDRESS_LEN]; + + // 4 bytes, IPv6 Address of the remote device + uint8_t ipv6_address[RSI_IP_ADDRESS_LEN * 4]; + } dest_ip_addr; + + // data buffer to send + uint8_t send_buffer[]; +} sl_si91x_socket_send_request_t; +#pragma pack() + +// socket accept request structure +#pragma pack(1) +typedef struct { + // Socket ID + uint8_t socket_id; + + // Local port number + uint16_t source_port; +} sl_si91x_socket_accept_request_t; +#pragma pack() + +// LTCP socket establish request structure +#pragma pack(1) +typedef struct { + uint16_t ip_version; + + // 2 bytes, socket handle + uint16_t socket_id; + + // 2 bytes, remote port number + uint16_t dest_port; + + union { + + // remote IPv4 Address + uint8_t ipv4_address[4]; + + // remote IPv6 Address + uint8_t ipv6_address[16]; + } dest_ip_addr; + + // 2 bytes, remote peer MSS size + uint16_t mss; + + // 4 bytes, remote peer Window size + uint32_t window_size; + + // source port number + uint16_t src_port_num; +} sl_si91x_rsp_ltcp_est_t; +#pragma pack() + +// disassociate command request structure +#pragma pack(1) +typedef struct { + // FIXME: Enumerate + // 0- Module in Client mode, 1- AP mode + uint16_t mode_flag; + + // client MAC address, Ignored/Reserved in case of client mode + sl_mac_address_t client_mac_address; +} sl_si91x_disassociation_request_t; +#pragma pack() + +// Access point configuration parameters +#pragma pack(1) +typedef struct { + // channel number of the access point + uint16_t channel; + + // ssid of the AP to be created + uint8_t ssid[RSI_SSID_LEN]; + + // security type of the Access point + uint8_t security_type; + + // encryption mode + uint8_t encryption_mode; + + // password in case of security mode + uint8_t psk[SL_WIFI_MAX_PMK_LENGTH]; + + // Beacon interval of the access point in milliseconds. Allowed values are integers in the range of 100 to 1000 in multiples of 100. + uint16_t beacon_interval; + + // DTIM period of the access point + uint16_t dtim_period; + + // This is the bitmap to enable AP keep alive functionality and to select the keep alive type. + uint8_t ap_keepalive_type; + + // Keep alive time after which AP will disconnect the station if there are no wireless exchanges from station to AP. + uint8_t ap_keepalive_period; + + // Number of clients supported + uint16_t max_sta_support; +} sl_si91x_ap_config_request; +#pragma pack() + +// wireless information +typedef struct { + // wlan state: connected or disconnected in station mode + // wlan state: no of stations connected in AP mode + uint16_t wlan_state; + + // channel number of connected AP + uint16_t channel_number; + + // uint8[32], SSID of connected access point + uint8_t ssid[RSI_SSID_LEN]; + + // MAC address + uint8_t mac_address[6]; + + // security type + uint8_t sec_type; + + // PSK + uint8_t psk[64]; + + // uint8[4], Module IP Address + uint8_t ipv4_address[4]; + + // uint8[16], Module IPv6 Address + uint8_t ipv6_address[16]; + + // reserved1 + uint8_t reserved1[2]; + + // reserved2 + uint8_t reserved2[2]; +} sl_si91x_wireless_info_t; + +/// Internal SiWx91x Socket information query +/// @note: This is internal structure and should not be used by the applicatiom. This is identical to sl_si91x_sock_info_query_t, will be cleaned to have single structure in future. +typedef struct { + uint8_t sock_id[2]; ///< Identifier for the socket + + uint8_t sock_type[2]; ///< Type of the socket (TCP, UDP, etc.) + + uint8_t source_port[2]; ///< Port number used by the source + + uint8_t dest_port[2]; ///< Port number used by the destination + + union { + uint8_t ipv4_address[4]; ///< IPv4 address of the remote host + + uint8_t ipv6_address[16]; ///< IPv6 address of the remote host + + } dest_ip_address; ///< IP address of the destination host +} sli_sock_info_query_t; + +// Network params command response structure +#pragma pack(1) +typedef struct { + // uint8, 0=NOT Connected, 1=Connected + uint8_t wlan_state; + + // channel number of connected AP + uint8_t channel_number; + + // PSK + uint8_t psk[64]; + + // Mac address + uint8_t mac_address[6]; + + // uint8[32], SSID of connected access point + uint8_t ssid[RSI_SSID_LEN]; + + // 2 bytes, 0=AdHoc, 1=Infrastructure + uint8_t connType[2]; + + // security type + uint8_t sec_type; + + // uint8, 0=Manual IP Configuration,1=DHCP + uint8_t dhcpMode; + + // uint8[4], Module IP Address + uint8_t ipv4_address[4]; + + // uint8[4], Module Subnet Mask + uint8_t subnetMask[4]; + + // uint8[4], Gateway address for the Module + uint8_t gateway[4]; + + // number of sockets opened + uint8_t num_open_socks[2]; + + // prefix length for ipv6 address + uint8_t prefix_length[2]; + + // modules ipv6 address + uint8_t ipv6_address[16]; + + // router ipv6 address + uint8_t defaultgw6[16]; + + // BIT(0) =1 - ipv4, BIT(1)=2 - ipv6, BIT(0) & BIT(1)=3 - BOTH + uint8_t tcp_stack_used; + + //sockets information array + sli_sock_info_query_t socket_info[10]; +} sl_si91x_network_params_response_t; +#pragma pack() + +typedef struct { + // IP version if the connected client + uint8_t ip_version[2]; + + // Mac Address of the connected client + uint8_t mac[6]; + union { + // IPv4 Address of the Connected client + uint8_t ipv4_address[4]; + + // IPv6 Address of the Connected client + uint8_t ipv6_address[16]; + } ip_address; +} sl_si91x_station_info_t; + +// go paramas response structure +#pragma pack(1) +typedef struct { + // SSID of the P2p GO + uint8_t ssid[RSI_SSID_LEN]; + + // BSSID of the P2p GO + uint8_t mac_address[6]; + + // Operating channel of the GO + uint8_t channel_number[2]; + + // PSK of the GO + uint8_t psk[64]; + + // IPv4 Address of the GO + uint8_t ipv4_address[4]; + + // IPv6 Address of the GO + uint8_t ipv6_address[16]; + + // Number of stations Connected to GO + uint8_t sta_count[2]; + + sl_si91x_station_info_t sta_info[SI91X_MAX_STATIONS]; +} sl_si91x_client_info_response; +#pragma pack() + +typedef enum { + START_STATISTICS_REPORT, + STOP_STATISTICS_REPORT, +} sl_wifi_statistics_report_t; + +// per stats command request structure +typedef struct { + // 0 - start , 1 -stop + uint8_t start[2]; + + // channel number + uint8_t channel[2]; +} sl_si91x_req_rx_stats_t; + +//! wlan per stats structure +typedef struct { + uint8_t tx_pkts[2]; + uint8_t reserved_1[2]; + uint8_t tx_retries[2]; + uint16_t crc_pass; + uint16_t crc_fail; + uint8_t cca_stk[2]; + uint8_t cca_not_stk[2]; + uint8_t pkt_abort[2]; + uint8_t fls_rx_start[2]; + uint8_t cca_idle[2]; + uint8_t reserved_2[26]; + uint8_t rx_retries[2]; + uint8_t reserved_3[2]; + uint16_t cal_rssi; + uint8_t reserved_4[4]; + uint8_t xretries[2]; + uint8_t max_cons_pkts_dropped[2]; + uint8_t reserved_5[2]; + uint8_t bss_broadcast_pkts[2]; + uint8_t bss_multicast_pkts[2]; + uint8_t bss_filter_matched_multicast_pkts[2]; +} sl_si91x_per_stats_rsp_t; + +// Sending data on specific socket structure +// sock_fd : Socket identifier +// length : Length of data +// data : Data +typedef struct { + uint8_t sock_fd; + uint32_t length; + // Need to discuss and increase data size + uint8_t data[50]; +} sl_si91x_socket_send_data_parameters_t; + +// Receiving data on specific socket structure +// sock_fd : Socket identifier +// length : Length of data +// data : Data +typedef struct { + uint8_t new_sock_fd; + uint32_t length; + uint8_t data[1460]; +} sl_si91x_socket_receive_data_parameters_t; + +// Socket creation and connection parameters +// domain : This parameter selects the address family (format of addresses within a domain) that is used. The families supported are 2(AF_INET), 0(AF_INET6) +// type : Socket protocol types (TCP/UDP/RAW) :: 1(SOCK_STREAM), 2(SOCK_DGRAM), 3(SOCK_RAW) +// protocol : protocol default : 0(IPPROTO_IP) +typedef struct { + uint8_t domain; + uint8_t type; + uint8_t protocol; +} sl_si91x_socket_create_parameters_t; + +// Socket connection parameters +// domain : This parameter selects the address family (format of addresses within a domain) that is used. The families supported are 2(AF_INET), 0(AF_INET6) +// sock_fd : socket descriptor +// port : Port number +// remote_ip_addr: Remote IP address +typedef struct { + uint8_t domain; + int8_t sock_fd; + uint32_t port; + uint32_t remote_ip_addr; +} sl_si91x_socket_connect_or_listen_parameters_t; + +typedef struct { + uint8_t + pll_mode; ///< PLL Mode. 0 - less than 120Mhz TA SoC clock; 1 - greater than 120Mhz TA SoC clock (Mode 1 is not currently supported for coex) + uint8_t rf_type; + uint8_t wireless_mode; + uint8_t enable_ppp; + uint8_t afe_type; + uint32_t feature_enables; +} sl_si91x_feature_frame_request; + +// structure for power save request +typedef struct { + // power mode to set + uint8_t power_mode; + + // set LP/ULP/ULP-without RAM retention + uint8_t ulp_mode_enable; + + // set DTIM aligment required + // 0 - module wakes up at beacon which is just before or equal to listen_interval + // 1 - module wakes up at DTIM beacon which is just before or equal to listen_interval + uint8_t dtim_aligned_type; + + // Set PSP type, 0-Max PSP, 1- FAST PSP, 2-APSD + uint8_t psp_type; + + // Monitor interval for the FAST PSP mode + // default is 50 ms, and this parameter is valid for FAST PSP only + uint16_t monitor_interval; + uint8_t num_of_dtim_skip; + uint16_t listen_interval; +} sl_si91x_power_save_request_t; + +typedef struct { + //! Ip version value + uint8_t ip_version[2]; + + //! URL name + uint8_t url_name[SI91X_DNS_REQUEST_MAX_URL_LEN]; + + //! DNS servers count + uint8_t dns_server_number[2]; +} sl_si91x_dns_query_request_t; + +typedef struct { + //! Ip version of the DNS server + uint8_t ip_version[2]; + + //! DNS response count + uint8_t ip_count[2]; + + //! DNS address responses + union { + uint8_t ipv4_address[4]; + uint8_t ipv6_address[16]; + } ip_address[SI91X_DNS_RESPONSE_MAX_ENTRIES]; +} sl_si91x_dns_response_t; +// Structure for TCP ACK indication +typedef struct { + // Socket ID + uint8_t socket_id; + + // Length + uint8_t length[2]; + +} sl_si91x_rsp_tcp_ack_t; + +// Config command request structure +typedef struct { + // config type + uint16_t config_type; + + // value to set + uint16_t value; +} sl_si91x_config_request_t; + +// read bytes coming on socket request structure +typedef struct { + // socket id + uint8_t socket_id; + + // requested bytes + uint8_t requested_bytes[4]; + + // Timeout for read + uint8_t read_timeout[2]; +} sl_si91x_req_socket_read_t; + +typedef struct { + // 2 bytes, the ip version of the ip address , 4 or 6 + uint16_t ip_version; + + // 2 bytes, the socket number associated with this read event + uint16_t socket_id; + + // 4 bytes, length of data received + uint32_t length; + + // 2 bytes, offset of data from start of buffer + uint16_t offset; + + // 2 bytes, port number of the device sending the data to us + uint16_t dest_port; + + union { + // 4 bytes, IPv4 Address of the device sending the data to us + uint8_t ipv4_address[4]; + + // 4 bytes, IPv6 Address of the device sending the data to us + uint8_t ipv6_address[16]; + } dest_ip_addr; +} si91x_rsp_socket_recv_t; + +typedef struct { + uint32_t tv_sec; /* Seconds */ + uint32_t tv_usec; /* Microseconds */ +} sl_si91x_time_value; + +/* The select socket array manager. */ +typedef struct { + uint32_t fd_array[(NUMBER_OF_BSD_SOCKETS + 31) / 32]; /* Bit map of SOCKET Descriptors.*/ + int32_t fd_count; /* How many are SET? */ +} sl_si91x_fd_set_t; + +typedef struct { + // Socket ID + uint8_t num_fd; + uint8_t select_id; + sl_si91x_fd_set_t read_fds; + sl_si91x_fd_set_t write_fds; + sl_si91x_time_value select_timeout; + uint8_t no_timeout; +} sl_si91x_socket_select_req_t; + +typedef struct { + // select id + uint8_t select_id; + + // readfd struct to store select info + sl_si91x_fd_set_t read_fds; + + // writefd struct to store select info + sl_si91x_fd_set_t write_fds; + + uint32_t socket_terminate_bitmap; +} sl_si91x_socket_select_rsp_t; + +// Structure for OTA firmware upgradation +typedef struct { + // Type of the packet + uint8_t ip_version; + + union { + // 4 bytes, IPv4 Address of the server + uint8_t ipv4_address[4]; + + // 16 bytes, IPv6 Address of the server + uint8_t ipv6_address[16]; + + } server_ip_address; + + // server port + uint8_t server_port[4]; + + // Chunk number + uint8_t chunk_number[2]; + + // Timeout + uint8_t timeout[2]; + + // TCP retry count + uint8_t retry_count[2]; + +} sl_si91x_ota_firmware_update_request_t; + +// Multicast request structure +typedef struct { + // IP version + uint8_t ip_version[2]; + + // command type + uint8_t type[2]; + + union { + uint8_t ipv4_address[4]; + uint8_t ipv6_address[16]; + } multicast_address; +} si91x_req_multicast_t; + +typedef struct { + // wps method: 0 - push button, 1 - pin method + uint16_t wps_method; + + // If 0 - validate given pin, 1 - generate new pin + uint16_t generate_pin; + + // wps pin for validation + uint8_t wps_pin[SI91X_WPS_PIN_LEN]; +} sl_si91x_wps_method_request_t; + +typedef struct { + uint32_t roam_enable; // Enable or disable roaming + uint32_t roam_threshold; // roaming threshold + uint32_t roam_hysteresis; // roaming hysteresis +} sl_si91x_req_roam_params_t; + +// Ping Request Frame +typedef struct { + // ip version + uint16_t ip_version; + + // ping size + uint16_t ping_size; + + union { + // ipv4 address + uint8_t ipv4_address[4]; + + // ipv6 address + uint8_t ipv6_address[16]; + + } ping_address; + + // ping request timeout + uint16_t timeout; +} sl_si91x_ping_request_t; + +//! HTTP Get/Post request structure +typedef struct { + //! ip version + uint16_t ip_version; + + //! https enable + uint16_t https_enable; + + //! port number + uint16_t port_number; + + //! buffer + uint8_t buffer[SI91X_HTTP_BUFFER_LEN]; +} sl_si91x_http_client_request_t; + +//! SNI for embedded sockets structure +#define SI91X_SNI_FOR_HTTPS 1 + +typedef struct si91x_sni_for_embedded_socket_request_s { + //! offset from which hostname starts + uint16_t offset; + + //! application protocol + uint16_t protocol; + + //! sni extension data + uint8_t tls_extension_data[SI91X_MAX_SIZE_OF_EXTENSION_DATA]; +} si91x_sni_for_embedded_socket_request_t; + +//! HTTP client PUT START create structure +typedef struct { + //! HTTP server ip version + uint8_t ip_version; + + //! HTTPS bit map + uint16_t https_enable; + + //! HTTP server port number + uint32_t port_number; + + //! HTTP Content Length + uint32_t content_length; +} SL_ATTRIBUTE_PACKED sl_si91x_http_client_put_start_t; + +typedef struct { + //! Current chunk length + uint16_t current_length; +} SL_ATTRIBUTE_PACKED sl_si91x_http_client_put_data_request_t; + +//! HTTP client PUT request structure +typedef struct { + //! Command type + uint8_t command_type; + + union http_client_put_s { + //! HTTP PUT START command structure + sl_si91x_http_client_put_start_t http_client_put_start; + + //! HTTP PUT PACKET command structure + sl_si91x_http_client_put_data_request_t http_client_put_data_req; + + } SL_ATTRIBUTE_PACKED http_client_put_struct; + + //! HTTP PUT buffer + uint8_t http_put_buffer[SI91X_HTTP_CLIENT_PUT_MAX_BUFFER_LENGTH]; +} SL_ATTRIBUTE_PACKED sl_si91x_http_client_put_request_t; + +//! HTTP Client POST DATA PKT request structure +typedef struct { + //! Current http data chunk length + uint16_t current_length; + + //! HTTP POST buffer + uint8_t http_post_data_buffer[SI91X_HTTP_CLIENT_POST_MAX_BUFFER_LENGTH]; +} sl_si91x_http_client_post_data_request_t; + +//! HTTP Client PUT PKT response structure +typedef struct { + //! Receive HTTP client PUT command type + uint8_t command_type; + + //! End of resource content file + uint8_t end_of_file; +} sl_si91x_http_client_put_pkt_rsp_t; + +//! HTTP Client PUT pkt server response structure +typedef struct { + uint32_t command_type; + uint32_t more; + uint32_t offset; + uint32_t data_len; +} sl_si91x_http_put_pkt_server_rsp_t; + +typedef struct { + uint8_t wake_duration; + uint8_t wake_duration_unit; + uint8_t wake_int_exp; + uint8_t negotiation_type; + uint16_t wake_int_mantissa; + uint8_t implicit_twt; + uint8_t un_announced_twt; + uint8_t triggered_twt; + uint8_t twt_channel; + uint8_t twt_protection; + uint8_t twt_flow_id; +} sl_si91x_twt_response_t; + +typedef struct { + uint8_t beacon_drop_threshold[2]; + uint8_t filter_bcast_in_tim; + uint8_t filter_bcast_tim_till_next_cmd; +} sl_si91x_request_wlan_filter_broadcast_t; + +//! user configurable gain table structure +typedef struct { + uint8_t band; ///< band value + uint8_t bandwidth; ///< bandwidth value + uint16_t size; ///< payload size + uint32_t reserved; + uint8_t gain_table[]; ///< payload +} sl_si91x_gain_table_info_t; + +typedef struct { + uint8_t guard_interval; ///< Period of time inserted between two packets in wireless transmission. Range : 0 - 3 + uint8_t nominal_pe; ///< Nominal Packet extension Range: 0 - 2 + uint8_t dcm_enable; ///< Enable or disable dual carrier modulation (DCM). 0 - Disable DCM, 1 - Enable DCM + uint8_t ldpc_enable; ///< Enable or disable low-density parity-check (LDPC). 0 - Disable LDPC, 1 - Enable LDPC + uint8_t + ng_cb_enable; ///< Enable or disable non-contiguous channel bonding (NG CB). 0 - Disable NG CB, 1 - Enable NG CB + uint8_t ng_cb_values; ///< Values of non-contiguous channel bonding (NG CB). Range: 0x00 - 0x11 + uint8_t + uora_enable; ///< Enable or disable uplink orthogonal frequency division multiple random access (UORA). 0 - Disable uora, 1 - Enable uora + uint8_t + trigger_rsp_ind; ///< Trigger_Response_Indication. BIT(0) ? Trigger Response For BE, BIT(1) ? Trigger Response For BK, BIT(2) ? Trigger Response For VI, BIT(3) ? Trigger Response For VO + uint8_t ipps_valid_value; + uint8_t tx_only_on_ap_trig; ///< Reserved for future use + uint8_t twt_support; ///< Enable or Disable TWT. 0 - Disable TWT, 1 - Enable TWT + uint8_t + config_er_su; ///< Extended Range Single User. 0 - NO ER_SU support, 1 - Use ER_SU rates along with Non_ER_SU rates, 2 - Use ER_SU rates only + uint8_t disable_su_beamformee_support; ///< Flag indicating whether Single User Beamformee support is disabled. + /// * 0: Enabled, 1: Disabled. +} sl_si91x_11ax_config_params_t; + +typedef struct { + uint32_t address; + uint32_t length; +} sl_si91x_ram_dump_t; + +#ifdef SLI_SI91X_MCU_INTERFACE +typedef enum { + SL_SI91X_TAKE_M4_64K = 1, + SL_SI91X_GET_IPMU_PROGRAMMING_VALUES = 2, + SL_SI91X_READ_TA_REGISTER = 3, + SL_SI91X_WRITE_TA_REGISTER = 4, + // This enum varibale added for M4 has to give indication to TA, for Configure the Clock switching between 1.3V to 3.3 .For more details check Jira Ticket RSC-3802. + SL_SI91X_ENABLE_XTAL = 5, + SL_SI91X_WRITE_TO_COMMON_FLASH = 6, +#ifdef SL_SI91X_SIDE_BAND_CRYPTO + SL_SI91X_ENABLE_SIDE_BAND = 7, +#endif + SL_SI91X_READ_FROM_COMMON_FLASH = 8, +} sl_si91x_ta_m4_commands_t; + +// M4 and TA secure handshake request structure. +typedef struct { + // sub_cmd form the enum ta_m4_commands_e(Main command type is RSI_COMMON_REQ_TA_M4_COMMANDS) + sl_si91x_ta_m4_commands_t sub_cmd; + // length of input_data + uint8_t input_data_size; + // Input data. In this input data first byte is reserved for enable(1) or Disable(0) sub_cmd of this structure. + uint8_t input_data[]; +} sl_si91x_ta_m4_handshake_parameters_t; + +#define MAX_CHUNK_SIZE 1400 +#define FLASH_SECTOR_SIZE 4096 +// TA2M4 handshake request structure. +typedef struct { + // sub_cmd + uint8_t sub_cmd; + + // TA flash location + uint32_t addr; + + // total length of input data + uint16_t input_buffer_length; + + // erases multiples of 4kbytes + uint8_t flash_sector_erase_enable; + + //data + uint8_t input_data[MAX_CHUNK_SIZE]; +} SL_ATTRIBUTE_PACKED sl_si91x_request_ta2m4_t; + +typedef struct { + // sub_cmd + uint8_t sub_cmd; + + // nwp flash location + uint32_t nwp_address; + + // total length of output data + uint16_t output_buffer_length; + +} SL_ATTRIBUTE_PACKED sl_si91x_read_flash_request_t; + +#endif // SLI_SI91X_MCU_INTERFACE + +/** \addtogroup SL_SI91X_TYPES + * @{ + * */ +/// Si91x specific TX test info +typedef struct { + uint16_t enable; ///< enable/disable tx test mode + uint16_t power; ///< tx test mode power. Range : 2 - 18 dBm. + uint32_t rate; ///< tx test mode rate + uint16_t + length; ///< tx test mode length. Range: [24 - 1500] bytes in Burst mode and [24 - 260] bytes in Continuous mode + uint16_t + mode; ///< tx test mode mode. 0 - Burst Mode; 1 - Continuous Mode; 2 - CW Mode; 3 - CW Mode center frequency - 2.5MHz; 4 - CW Mode center frequency + 5MHz + uint16_t channel; ///< tx test mode channel + uint16_t rate_flags; ///< tx test mode rate_flags + uint16_t channel_bw; ///< tx test mode tx test_ch_bw + uint16_t aggr_enable; ///< tx test mode aggr_enable + uint16_t reserved; ///< tx test mode reserved + uint16_t no_of_pkts; ///< tx test mode no_of_pkts + uint32_t delay; ///< tx test mode delay +#if defined(SLI_SI917) || defined(DOXYGEN) + uint8_t enable_11ax; ///< 11AX_ENABLE 0-disable, 1-enable + uint8_t coding_type; ///< Coding_type 0-BCC 1-LDPC + uint8_t nominal_pe; ///< Indicates Nominal T-PE value. 0-0Us 1-8Us 2-16Us + uint8_t + ul_dl; ///< Indicates whether the PPDU is UL/DL. Set it to 1 if PPDU is to be sent by station to AP; 0 if PPDU is to be sent by AP to station. + uint8_t he_ppdu_type; ///< he_ppdu_type 0-HE SU PPDU, 1-HE ER SU PPDU, 2-HE TB PPDU, 3-HE MU PPDU + uint8_t + beam_change; ///< Indicates the spatial mapping of pre-HE and HE fields. Enter 0 for pre-HE and HE fields are spatially mapped in the same way and 1 for pre-HE and HE fields are spatially mapped differently. + uint8_t bw; ///< Indicates the BW for the PPDU: 0 for 242-tone RU, 1 for upper 106-tone RU. + uint8_t + stbc; ///< Indicates whether STBC is used for PPDU transmission. Set to 0 for no STBC and 1 for STBC (only if DCM field is set to 0). + uint8_t + tx_bf; ///< Indicates whether beamforming matrix is applied to the transmission. 0 - no beamforming matrix, 1 - beamforming matrix. + uint8_t gi_ltf; ///< Indicates the GI and LTF size. GI_LTF shall be in the range 0-3 + uint8_t dcm; ///< Indicates whether DCM is applied to Data Symbols. 0 - No DCM, 1 - DCM. + uint8_t nsts_midamble; ///< Indicates the NSTS and Midamble Periodicity. NSTS_MIDAMBLE shall be in the range 0-7 + uint8_t + spatial_reuse; ///< spatial_reuse shall be in the range 0-15. 4 indicates that spatial reuse is allowed during the transmission of PPDU. + uint8_t bss_color; ///< Color value of BSS. Must be in the range 0 to 63 + uint16_t he_siga2_reserved; ///< HE_SIGA2_RESERVED shall be in the range 0-511 + uint8_t ru_allocation; ///< Indicates the RU Allocation Subfield for 20MHz BW. Must be in the range 0-255. + uint8_t n_heltf_tot; ///< Indicates the number of HE-LTF to be transmitted. Can be in the range 0-7. + uint8_t sigb_dcm; ///< Indicates whether DCM is applied to SIG-B Symbols. 0-disable, 1-enable + uint8_t sigb_mcs; ///< Indicates the MCS for SIG-B Symbols. Allowed range is 0-5. + uint16_t user_sta_id; ///< Indicates the Station ID of the intended user. Allowed range is 0-2047. + uint8_t user_idx; ///< USER_IDX shall be in the range 0-8 + uint8_t sigb_compression_field; ///< SIGB_COMPRESSION_FIELD shall be 0/1 +#endif +} sl_si91x_request_tx_test_info_t; +/** @} */ + +typedef struct { + /* Target + * 0 - BURN_INTO_EFUSE (Burns calibration data to EFuse) + - + * 1 - BURN_INTO_FLASH (Burns calibration data to Flash) + - + **/ + uint8_t target; + uint8_t reserved0[3]; + /* Flags - Validate information + * Bit | MACRO | Description + * :---|:---------------------:|:--------------------------------------------------- + * 0 | RESERVED_0 | Reserved + * 1 | BURN_FREQ_OFFSET | 1 - Update XO Ctune to calibration data + - 0 - Skip XO Ctune update + * 2 | SW_XO_CTUNE_VALID | 1 - Use XO Ctune provided as argument to update calibration data + - 0 - Use XO Ctune value as read from hardware register + * 3 | BURN_XO_FAST_DISABLE | Used to apply patch for cold temperature issue(host interface detection) observed on CC0/CC1 modules. \ref appendix + * 4 | BURN_GAIN_OFFSET_LOW | 1 - Update gain offset for low sub-band (2 GHz) + - 0 - Skip low sub-band gain-offset update + * 5 | BURN_GAIN_OFFSET_MID | 1 - Update gain offset for mid sub-band (2 GHz) + - 0 - Skip mid sub-band gain-offset update + * 6 | BURN_GAIN_OFFSET_HIGH | 1 - Update gain offset for high sub-band (2 GHz) + - 0 - Skip high sub-band gain-offset update + * 8 | ENABLE_DPD_CALIB | 1 - Collect dpd coefficients data + - 0 - Skip dpd coefficients calibration + * 9 | BURN_DPD_COEFFICIENTS | 1 - Burn dpd coefficients data + - 0 - Skip dpd coefficients calibration + * 10 | BURN_GAIN_OFFSET_CHANNEL-14 | 1 - Update gain offset for channel-14 sub-band (2 GHz) + - 0 - Skip channel-14 sub-band gain-offset update + * 31-4 | | Reserved + **/ + uint32_t flags; + /* +gain_offset_low - gain_offset as observed in dBm in channel-1 +gain_offset_mid - gain_offset as observed in dBm in channel-6 +gain_offset_high - gain_offset as observed in dBm in channel-11 +*/ + int8_t gain_offset[3]; + /*xo_ctune - Allow user to directly update xo_ctune value to calibration data bypassing the freq offset loop, + *valid only when BURN_FREQ_OFFSET & SW_XO_CTUNE_VALID of flags is set. The range of xo_ctune is [0, 255], and the typical value is 80 + */ + int8_t xo_ctune; + /*gain_offset_channel-14 - gain_offset as observed in dBm in channel-14 */ + int8_t gain_offset_ch14; +} sl_si91x_calibration_write_t; + +typedef struct { + + /* target +* 0 - READ_FROM_EFUSE (read calibration data from the EFuse) + - +* 1 - READ_FROM_FLASH (read calibration data from the Flash) +*/ + uint8_t target; + uint8_t reserved0[3]; + /* + gain_offset_low - gain_offset in dBm that will be applied for transmissions in channel-1. + gain_offset_mid - gain_offset in dBm that will be applied for transmissions in channel-6. + gain_offset_high -gain_offset in dBm that will be applied for transmissions in channel-11. + */ + int8_t gain_offset[3]; + + //xo_ctune - xo_ctune value as read from the target memory. + int8_t xo_ctune; + /*gain_offset_channel-14 - gain_offset in dBm that will be applied for transmissions in channel-14.*/ + int8_t gain_offset_ch14; +#ifndef SLI_SI917 + struct rsi_evm_data_t { + int8_t evm_offset[5]; + } rsi_evm_data_t; +#endif +} sl_si91x_calibration_read_t; + +typedef struct { + int32_t frequency_offset_in_khz; +} sl_si91x_freq_offset_t; + +/// Si91x specific get DPD calibration data +typedef struct { + int8_t dpd_power_index; // Dpd power index given by the user +} sl_si91x_get_dpd_calib_data_t; + +typedef struct { + int8_t evm_offset_val; //EVM_offset_val - emv_offset value observed. + /* index - index of EVM,range from[0 to 4]. + * index | description + * 0 | Update evm_offset_11B + * 1 | Update evm_offset_11G_6M_24M_11N_MCS0_MCS2 + * 2 | Update evm_offset_11G_36M_54M_11N_MCS3_MCS7 + * 3 | Update evm_offset_11N_MCS0 + * 4 | Update evm_offset_11N_MCS7 + * > 4 | Reserved + * */ + uint8_t evm_index; +} sl_si91x_evm_offset_t; + +typedef struct { + /* + *Target + * 0 - BURN_INTO_EFUSE (Burns calibration data to EFuse)(Not supported) + * 1 - BURN_INTO_FLASH (Burns calibration data to Flash) + **/ + uint8_t target; + /* + * Flags - Validate information + - + * Bit | MACRO | Description + * :---|:---------------------:|:--------------------------------------------------- + * 0 | EVM_OFFSET_CUST_0 | 1 - Update evm_offset_11B rate calibration data + - 0 - Skip evm_offset update + * 1 | EVM_OFFSET_CUST_1 | 1 - Update evm_offset_11G_6M_24M_11N_MCS0_MCS2 rate calibration data + - 0 - Skip evm_offset update + * 2 | EVM_OFFSET_CUST_2 | 1 - Update evm_offset_11G_36M_54M_11N_MCS3_MCS7 rate calibration data + - 0 - Skip evm_offset update + * 3 | EVM_OFFSET_CUST_3 | 1 - Update evm_offset_11N_MCS0 rate calibration data + - 0 - Skip evm_offset update + * 4 | EVM_OFFSET_CUST_4 | 1 - Update evm_offset_11N_MCS7 rate calibration data + - 0 - Skip evm_offset update + * 31-5| Reserved + */ + uint32_t flags; + uint8_t evm_offset_11B; //evm_offset for 11B rate + uint8_t evm_offset_11G_6M_24M_11N_MCS0_MCS2; //evm_offset for 11G_6M_24M_11N_MCS0_MCS2 rate + uint8_t evm_offset_11G_36M_54M_11N_MCS3_MCS7; //evm_offset for 11G_36M_54M_11N_MCS3_MCS7 rate + uint8_t evm_offset_11N_MCS0; //evm_offset for 11N_MCS0 rate + uint8_t evm_offset_11N_MCS7; //evm_offset for 11N_MCS7 rate +} sl_si91x_evm_write_t; + +typedef struct { + uint32_t efuse_read_addr_offset; + uint16_t efuse_read_data_len; +} sl_si91x_efuse_read_t; + +typedef struct { + uint32_t max_retry_attempts; ///< Maximum number of retries before indicating join failure + uint32_t scan_interval; ///< Scan interval between each retry + uint32_t beacon_missed_count; ///< Number of missed beacons that will trigger rejoin + uint32_t first_time_retry_enable; ///< Retry enable or disable for first time joining +} sl_si91x_rejoin_params_t; + +/** \addtogroup SL_SI91X_TYPES + * @{ + * */ +/// Si917 specific Wi-Fi asynchronous statistics +typedef struct { + uint16_t tx_pkts; ///< Number of tx pkts + uint8_t reserved_1[2]; ///< Number of rx pkts + uint16_t tx_retries; ///< Number of tx retries + uint16_t crc_pass; ///< Number ofpkts that pass crc + uint16_t crc_fail; ///< Number of pkts failing crc chk + uint16_t cca_stk; ///< Number of times cca got stuck + uint16_t cca_not_stk; ///< Number of times cca didn't get stuck + uint16_t pkt_abort; ///< Number of pkt aborts + uint16_t fls_rx_start; ///< Number of false rx starts + uint16_t cca_idle; ///< cca idle time + uint8_t reserved_2[26]; ///< Reserved fields + uint16_t rx_retries; ///< Number of rx retries + uint8_t reserved_3[2]; ///< rssi value + uint16_t cal_rssi; ///< cal_rssi + uint8_t reserved_4[4]; ///< lna_gain bb_gain + uint16_t xretries; ///< Number of tx packets dropped after maximum retries + uint16_t max_cons_pkts_dropped; ///< Consecutive pkts dropped + uint8_t reserved_5[2]; ///< Reserved fields + uint16_t bss_broadcast_pkts; ///< BSSID matched broadcast packets count + uint16_t bss_multicast_pkts; ///< BSSID matched multicast packets count + uint16_t bss_filter_matched_multicast_pkts; ///< BSSID & multicast filter matched packets count +} sl_si91x_async_stats_response_t; + +/// Si917 specific Wi-Fi advance statistics +typedef struct { + uint32_t beacon_lost_count; ///< Number of missed beacons + uint32_t beacon_rx_count; ///< Number of received beacons + uint32_t mcast_rx_count; ///< Multicast packets received + uint32_t mcast_tx_count; ///< Multicast packets transmitted + uint32_t ucast_rx_count; ///< Unicast packets received + uint32_t ucast_tx_count; ///< Unicast packets transmitted + uint32_t + overrun_count; ///< Number of packets dropped either at ingress or egress, due to lack of buffer memory to retain all packets. +} sl_si91x_advance_stats_response_t; +/** @} */ + +#ifdef SL_SI91X_SIDE_BAND_CRYPTO +typedef struct crypto_key_s { + uint32_t key_slot; ///< For built-in key + uint32_t wrap_iv_mode; ///< IV mode 0-> ECB; 1-> CBC + uint8_t wrap_iv[16]; ///< IV for CBC mode + uint8_t key_buffer[32]; ///< Key data wrapped/ Plain text +} sl_si91x_crypto_key_t; + +typedef struct { + uint32_t key_size; + sl_si91x_crypto_key_t key_spec; +} sl_si91x_key_info_t; + +typedef struct { + uint32_t key_type; + uint32_t reserved; + sl_si91x_key_info_t key_detail; +} sl_si91x_key_descriptor_t; + +typedef struct { + uint8_t algorithm_type; + uint8_t algorithm_sub_type; + uint16_t total_msg_length; + uint16_t encrypt_decryption; + uint16_t output_length; + sl_si91x_key_descriptor_t key_info; + uint8_t *IV; + uint8_t *msg; + uint8_t *output; +} sl_si91x_aes_request_t; + +typedef struct { + uint32_t key_type; + uint32_t reserved; + uint32_t key_size; + uint32_t wrap_iv_mode; + uint8_t *wrap_iv; + uint8_t *key_buffer; +} sl_si91x_wrap_key_descriptor_t; + +typedef struct { + uint16_t algorithm_type; + uint16_t output_length; + sl_si91x_wrap_key_descriptor_t key_info; + uint8_t *output; +} sl_si91x_wrap_request_t; + +typedef struct { + uint16_t algorithm_type; + uint16_t algorithm_sub_type; + uint16_t total_length; + uint16_t output_length; + sl_si91x_key_descriptor_t key_info; + uint8_t *hmac_data; + uint8_t *output; +} sl_si91x_hmac_sha_request_t; + +typedef struct { + uint16_t algorithm_type; + uint16_t algorithm_sub_type; + uint16_t total_msg_length; + uint16_t output_length; + uint8_t *msg; + uint8_t *output; +} sl_si91x_sha_request_t; + +typedef struct { + uint8_t algorithm_type; + uint8_t nonce_length; + uint16_t encrypt_decryption; + uint16_t total_msg_length; + uint16_t ad_length; + uint16_t tag_length; + uint16_t output_length; + sl_si91x_key_descriptor_t key_info; + uint8_t *nonce; + uint8_t *ad; + uint8_t *tag; // tag size = 16 + uint8_t *msg; + uint8_t *output; +} sl_si91x_ccm_request_t; + +typedef struct { + uint8_t algorithm_type; + uint8_t dma_use; + uint8_t gcm_mode; + uint8_t encrypt_decryption; + uint16_t total_msg_length; + uint16_t ad_length; + uint32_t output_length; + sl_si91x_key_descriptor_t key_info; + uint8_t *nonce; // iv length = 12 bytes + uint8_t *ad; + uint8_t *msg; + uint8_t *output; +} sl_si91x_gcm_request_t; + +typedef struct { + uint8_t algorithm_type; + uint8_t algorithm_sub_type; + uint8_t encrypt_decryption; + uint8_t dma_use; + uint16_t total_msg_length; + uint16_t header_length; + uint32_t output_length; + uint8_t *nonce; + sl_si91x_key_descriptor_t key_info; + uint8_t *header_input; + uint8_t *msg; + uint8_t *output; +} sl_si91x_chachapoly_request_t; + +typedef struct { + uint8_t algorithm_type; + uint8_t ecdh_mode; + uint8_t ecdh_sub_mode; + uint8_t *sx; + uint8_t *sy; + uint8_t *sz; + uint8_t *tx; + uint8_t *ty; + uint8_t *tz; + uint8_t *rx; + uint8_t *ry; + uint8_t *rz; +} sl_si91x_ecdh_add_sub_request_t; + +typedef struct { + uint8_t algorithm_type; + uint8_t ecdh_mode; + uint8_t ecdh_sub_mode; + uint8_t ecdh_curve_type; + uint32_t affinity; + uint8_t *d; + uint8_t *sx; + uint8_t *sy; + uint8_t *sz; + uint8_t *rx; + uint8_t *ry; + uint8_t *rz; +} sl_si91x_ecdh_mul_request_t; + +typedef struct { + uint8_t algorithm_type; + uint8_t ecdh_mode; + uint8_t ecdh_sub_mode; + uint8_t *sx; + uint8_t *sy; + uint8_t *sz; + uint8_t *rx; + uint8_t *ry; + uint8_t *rz; +} sl_si91x_ecdh_double_request_t; + +typedef struct { + uint8_t algorithm_type; + uint8_t ecdh_mode; + uint8_t ecdh_sub_mode; + uint8_t ecdh_curve_type; + uint8_t *sx; + uint8_t *sy; + uint8_t *sz; + uint8_t *rx; + uint8_t *ry; + uint8_t *rz; +} sl_si91x_ecdh_affine_request_t; + +typedef struct { + uint8_t algorithm_type; + uint8_t algorithm_sub_type; + uint16_t total_msg_length; + uint8_t *trng_key; + uint8_t *msg; + uint8_t *output; +} sl_si91x_trng_request_t; + +// Attestation token Request Frames Structures +typedef struct { + uint16_t algorithm_type; + uint16_t total_msg_length; + uint32_t *msg; + uint8_t *token_buf; +} sl_si91x_rsi_token_req_t; + +#else +typedef struct crypto_key_s { + uint32_t key_slot; ///< For built-in key + uint32_t wrap_iv_mode; ///< IV mode 0-> ECB; 1-> CBC + uint8_t wrap_iv[16]; ///< IV for CBC mode + uint8_t key_buffer[32]; ///< Key data wrapped/ Plain text +} sl_si91x_crypto_key_t; + +typedef struct { + uint32_t key_size; + sl_si91x_crypto_key_t key_spec; +} sl_si91x_key_info_t; + +typedef struct { + uint32_t key_type; + uint32_t reserved; + sl_si91x_key_info_t key_detail; +} sl_si91x_key_descriptor_t; + +typedef struct { + uint16_t algorithm_type; + uint8_t algorithm_sub_type; + uint8_t aes_flags; + uint16_t total_msg_length; + uint16_t current_chunk_length; + uint32_t encrypt_decryption; +#ifdef SLI_SI917B0 + sl_si91x_key_descriptor_t key_info; +#else + uint32_t key_length; + uint8_t key[32]; +#endif + uint8_t IV[16]; + uint8_t msg[1400]; +} sl_si91x_aes_request_t; + +typedef struct { + uint32_t key_type; + uint32_t reserved; + uint32_t key_size; + uint32_t wrap_iv_mode; + uint8_t wrap_iv[16]; + uint8_t key_buffer[1400]; +} sl_si91x_wrap_key_descriptor_t; + +typedef struct { + uint8_t algorithm_type; + uint8_t wrap_flags; + uint16_t current_chunk_length; + sl_si91x_wrap_key_descriptor_t key_info; +} sl_si91x_wrap_request_t; + +typedef struct { + uint16_t algorithm_type; + uint8_t algorithm_sub_type; + uint8_t hmac_sha_flags; + uint16_t total_length; + uint16_t current_chunk_length; +#ifdef SLI_SI917B0 + sl_si91x_key_descriptor_t key_info; +#else + uint32_t key_length; +#endif + uint8_t hmac_data[1400]; +} sl_si91x_hmac_sha_request_t; + +typedef struct { + uint16_t algorithm_type; + uint8_t algorithm_sub_type; + uint8_t sha_flags; + uint16_t total_msg_length; + uint16_t current_chunk_length; + uint8_t msg[1400]; +} sl_si91x_sha_request_t; + +typedef struct { + uint16_t algorithm_type; + uint8_t ccm_flags; + uint8_t nonce_length; + uint16_t encrypt_decryption; + uint16_t total_msg_length; + uint16_t current_chunk_length; + uint16_t ad_length; + uint32_t tag_length; +#ifdef SLI_SI917B0 + sl_si91x_key_descriptor_t key_info; +#else + uint32_t key_length; + uint8_t key[SL_SI91X_KEY_BUFFER_SIZE]; +#endif + uint8_t nonce[SL_SI91X_CCM_IV_BUFF_LEN]; + uint8_t ad[SL_SI91X_CCM_AD_MAX_SIZE]; + uint8_t tag[SL_SI91X_TAG_SIZE]; // tag size = 16 + uint8_t msg[SL_SI91X_CCM_MSG_MAX_SIZE]; // max msg size = 1200 bytes +} sl_si91x_ccm_request_t; + +typedef struct { + uint16_t algorithm_type; + uint8_t gcm_flags; + uint8_t encrypt_decryption; + uint16_t total_msg_length; + uint16_t current_chunk_length; + uint16_t ad_length; + uint16_t dma_use; +#ifdef SLI_SI917B0 + uint32_t gcm_mode; + sl_si91x_key_descriptor_t key_info; +#else + uint32_t key_length; + uint8_t key[SL_SI91X_KEY_BUFFER_SIZE]; +#endif + uint8_t nonce[SL_SI91X_GCM_IV_SIZE]; // iv length = 12 bytes + uint8_t ad[SL_SI91X_GCM_AD_MAX_SIZE]; + uint8_t msg[SL_SI91X_GCM_MSG_MAX_SIZE]; +} sl_si91x_gcm_request_t; + +typedef struct { + uint16_t algorithm_type; + uint8_t algorithm_sub_type; + uint8_t chachapoly_flags; + uint16_t total_msg_length; + uint16_t header_length; + uint16_t current_chunk_length; + uint16_t encrypt_decryption; + uint32_t dma_use; + uint8_t nonce[SL_SI91X_IV_SIZE]; +#ifdef SLI_SI917B0 + sl_si91x_key_descriptor_t key_info; +#else + uint8_t key_chacha[SL_SI91X_KEY_BUFFER_SIZE]; + uint8_t keyr_in[SL_SI91X_KEYR_SIZE]; + uint8_t keys_in[SL_SI91X_KEYS_SIZE]; +#endif + uint8_t header_input[SL_SI91X_GCM_AD_MAX_SIZE]; + uint8_t msg[SL_SI91X_CHACHAPOLY_MSG_MAX_SIZE]; +} sl_si91x_chachapoly_request_t; + +typedef struct { + uint8_t algorithm_type; + uint8_t algorithm_sub_type; + uint8_t ecdsa_flags; + uint8_t curve_id; + uint8_t sha_mode; + uint8_t private_key_length; + uint8_t public_key_length; + uint8_t signature_length; + uint16_t current_chunk_length; + uint16_t msg_len; +#ifdef SLI_SI917B0 + sl_si91x_key_descriptor_t key_info; +#else + uint32_t key_length; +#endif + uint8_t private_key[SL_SI91X_PRIVATE_KEY_MAX_SIZE]; + uint8_t public_key[SL_SI91X_PUBLIC_KEY_MAX_SIZE]; + uint8_t signature[SL_SI91X_SIGNATURE_MAX_SIZE]; + uint8_t msg[SL_SI91X_ECDSA_MSG_MAX_SIZE]; +} sl_si91x_ecdsa_request_t; + +typedef struct { + uint8_t algorithm_type; + uint8_t ecdh_mode; + uint8_t ecdh_sub_mode; + uint8_t sx[ECDH_BUFFER_SIZE]; + uint8_t sy[ECDH_BUFFER_SIZE]; + uint8_t sz[ECDH_BUFFER_SIZE]; + uint8_t tx[ECDH_BUFFER_SIZE]; + uint8_t ty[ECDH_BUFFER_SIZE]; + uint8_t tz[ECDH_BUFFER_SIZE]; +} sl_si91x_ecdh_add_sub_request_t; + +typedef struct { + uint8_t algorithm_type; + uint8_t ecdh_mode; + uint8_t ecdh_sub_mode; + uint8_t ecdh_curve_type; + uint32_t affinity; + uint8_t d[ECDH_BUFFER_SIZE]; + uint8_t sx[ECDH_BUFFER_SIZE]; + uint8_t sy[ECDH_BUFFER_SIZE]; + uint8_t sz[ECDH_BUFFER_SIZE]; +} sl_si91x_ecdh_mul_request_t; + +typedef struct { + uint8_t algorithm_type; + uint8_t ecdh_mode; + uint8_t ecdh_sub_mode; + uint8_t sx[ECDH_BUFFER_SIZE]; + uint8_t sy[ECDH_BUFFER_SIZE]; + uint8_t sz[ECDH_BUFFER_SIZE]; +} sl_si91x_ecdh_double_request_t; + +typedef struct { + uint8_t algorithm_type; + uint8_t ecdh_mode; + uint8_t ecdh_sub_mode; + uint8_t ecdh_curve_type; + uint8_t sx[ECDH_BUFFER_SIZE]; + uint8_t sy[ECDH_BUFFER_SIZE]; + uint8_t sz[ECDH_BUFFER_SIZE]; +} sl_si91x_ecdh_affine_request_t; + +typedef struct { + uint8_t algorithm_type; + uint8_t algorithm_sub_type; + uint16_t total_msg_length; + uint32_t trng_key[TRNG_KEY_SIZE]; + uint32_t msg[TRNG_TEST_DATA_SIZE]; +} sl_si91x_trng_request_t; + +// Attestation token Request Frames Structures +typedef struct { + uint8_t algorithm_type; + uint16_t total_msg_length; + uint32_t msg[NONCE_DATA_SIZE]; +} sl_si91x_rsi_token_req_t; + +#endif + +// Request timeout Structure +typedef struct { + uint32_t timeout_bitmap; + uint16_t timeout_value; +} sl_si91x_request_timeout_t; + +// High throughputs enable command +typedef struct { + uint16_t mode_11n_enable; + uint16_t ht_caps_bitmap; +} sl_si91x_request_ap_high_throughput_capability_t; diff --git a/wiseconnect/components/device/silabs/si91x/wireless/inc/sl_si91x_status.h b/wiseconnect/components/device/silabs/si91x/wireless/inc/sl_si91x_status.h new file mode 100644 index 000000000..19804bacf --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/inc/sl_si91x_status.h @@ -0,0 +1,89 @@ +/***************************************************************************/ /** + * @file + * @brief + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#pragma once +typedef enum { + RSI_ERROR_NONE = 0, + RSI_ERROR_TIMEOUT = -1, + RSI_ERROR_INVALID_PARAM = -2, + RSI_ERROR_COMMAND_GIVEN_IN_WRONG_STATE = -3, + RSI_ERROR_PKT_ALLOCATION_FAILURE = -4, + RSI_ERROR_COMMAND_NOT_SUPPORTED = -5, + RSI_ERROR_INSUFFICIENT_BUFFER = -6, + RSI_ERROR_IN_OS_OPERATION = -7, + RSI_ERROR_INVALID_MEMORY = -8, + RSI_ERROR_BOOTUP_OPTIONS_NOT_SAVED = -9, + RSI_ERROR_BOOTUP_OPTIONS_CHECKSUM_FAIL = -10, + RSI_ERROR_BOOTLOADER_VERSION_NOT_MATCHING = -11, + RSI_ERROR_WAITING_FOR_BOARD_READY = -12, + RSI_ERROR_INVALID_ADDRESS = -13, + RSI_ERROR_VALID_FIRMWARE_NOT_PRESENT = -14, + RSI_ERROR_INVALID_OPTION = -15, + RSI_ERROR_EXCEEDS_MAX_CALLBACKS = -16, + RSI_ERROR_SET_ITIMER = -17, + RSI_ERROR_SIG_ACTION = -18, + RSI_ERROR_NOT_IN_CONNECTED_STATE = -19, + RSI_ERROR_NOT_IN_IPCONFIG_STATE = -20, + RSI_ERROR_SPI_BUSY = -21, + RSI_ERROR_SPI_FAIL = -22, + RSI_ERROR_SPI_TIMEOUT = -23, + RSI_ERROR_CARD_READY_TIMEOUT = -24, + RSI_ERROR_BOARD_READY_TIMEOUT = -25, + RSI_ERROR_INVALID_PACKET = -26, + RSI_ERROR_FW_UPGRADE_TIMEOUT = -27, + RSI_ERROR_FW_LOAD_OR_UPGRADE_TIMEOUT = -28, + RSI_ERROR_GPIO_WAKEUP_TIMEOUT = -29, + RSI_ERROR_RESPONSE_TIMEOUT = -30, + RSI_ERROR_BLE_DEV_BUF_FULL = -31, + RSI_ERROR_NWK_CMD_IN_PROGRESS = -32, + RSI_ERROR_SOCKET_CMD_IN_PROGRESS = -33, + RSI_ERROR_WLAN_CMD_IN_PROGRESS = -34, + RSI_ERROR_COMMON_CMD_IN_PROGRESS = -35, + RSI_ERROR_ANT_DEV_BUF_FULL = -36, + RSI_ERROR_BT_BLE_CMD_IN_PROGRESS = -37, + RSI_ERROR_ANT_CMD_IN_PROGRESS = -38, + RSI_ERROR_BLE_ATT_CMD_IN_PROGRESS = -39, + RSI_ERROR_MEMORY_NOT_ALIGNED = -40, + RSI_ERROR_SEMAPHORE_CREATE_FAILED = -41, + RSI_ERROR_SEMAPHORE_DESTROY_FAILED = -42, + RSI_ERROR_IN_WLAN_CMD = -43, + RSI_ERROR_RX_BUFFER_CHECK = -44, + RSI_ERROR_PARAMETER_LENGTH_EXCEEDS_MAX_VAL = -45, + RSI_ERROR_IN_COMMON_CMD = -46, + RSI_ERROR_TX_BUFFER_FULL = -47, + RSI_ERROR_SDIO_TIMEOUT = -48, + RSI_ERROR_SDIO_WRITE_FAIL = -49, + RSI_ERROR_INVALID_SET_CONFIG_FLAG = -50, + RSI_ERROR_BLE_DEV_BUF_IS_IN_PROGRESS = -51, + RSI_ERROR_SET_REGION_NOT_ENABLED = -52, + RSI_ERROR_BLE_INVALID_CALLBACK_CNT = -53, + RSI_ERROR_BLE_ADV_EXT_COMMAND_NOT_ALLOWED = -54, + RSI_ERROR_BLE_LEGACY_COMMAND_NOT_ALLOWED = -55, + RSI_ERROR_TRNG_DUPLICATE_ENTROPY = -56 +} si91x_status_t; diff --git a/wiseconnect/components/device/silabs/si91x/wireless/inc/sl_si91x_types.h b/wiseconnect/components/device/silabs/si91x/wireless/inc/sl_si91x_types.h new file mode 100644 index 000000000..979b902f2 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/inc/sl_si91x_types.h @@ -0,0 +1,248 @@ +/***************************************************************************/ /** + * @file + * @brief + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#pragma once + +#include "sl_si91x_constants.h" +#include "sl_wifi_host_interface.h" +#include + +/// Flag to indicate that the response status of the command is expected +#define SI91X_PACKET_RESPONSE_STATUS (1 << 0) + +/// Flag to indicate that the response packet of the command is expected +#define SI91X_PACKET_RESPONSE_PACKET (1 << 1) + +/// Flag to indicate that all the packet tx has to be suspended until the corresponding command response is received +#define SI91X_PACKET_GLOBAL_QUEUE_BLOCK (1 << 3) + +/// Flag to indicate that host would receive the response from firmware in asynchronous manner. +#define SI91X_PACKET_WITH_ASYNC_RESPONSE (1 << 4) + +typedef enum { + SI91X_COMMON_CMD = 0, ///< SI91X Common Command + SI91X_WLAN_CMD = 1, ///< SI91X Wireless LAN Command + SI91X_NETWORK_CMD = 2, ///< SI91X Network Command + SI91X_SOCKET_CMD = 3, ///< SI91X Socket Command + SI91X_BT_CMD = 4, ///< SI91X Bluetooth Command + SI91X_SOCKET_DATA = 5, ///< SI91X Socket Data Command + SI91X_CMD_MAX ///< SI91X Maximum Command value +} sl_si91x_command_type_t; + +/// Si91x queue types +typedef enum { + // SI91X command queue types + // Note: The values of the command queue type should be + // in sync with that of sl_si91x_command_type_t + SI91X_COMMON_CMD_QUEUE = 0, ///< SI91X common Command queue + SI91X_WLAN_CMD_QUEUE = 1, ///< SI91X Wireless LAN Command queue + SI91X_NETWORK_CMD_QUEUE = 2, ///< SI91X Network Command queue + SI91X_SOCKET_CMD_QUEUE = 3, ///< SI91X Socket Command queue + SI91X_BT_CMD_QUEUE = 4, ///< SI91X Bluetooth Command queue + SI91X_SOCKET_DATA_QUEUE = 5, ///< SI91X Socket Command queue + + // SI91X response queue types + SI91X_COMMON_RESPONSE_QUEUE = 6, ///< SI91X common Command response queue + SI91X_WLAN_RESPONSE_QUEUE = 7, ///< SI91X Wireless LAN Command response queue + SI91X_NETWORK_RESPONSE_QUEUE = 8, ///< SI91X Network Command response queue + SI91X_SOCKET_RESPONSE_QUEUE = 9, ///< SI91X Socket Command response queue + SI91X_BT_RESPONSE_QUEUE = 10, ///< SI91X Bluetooth Command response queue + + // All SI91X WLAN Async Events use this queue + SI91X_WLAN_EVENT_QUEUE = 11, ///< SI91X Wireless LAN Asynchronous response queue + // All SI91X Network Async Events use this queue + SI91X_NETWORK_EVENT_QUEUE = 12, ///< SI91X Network Asynchronous response queue + + SI91X_SOCKET_EVENT_QUEUE = 13, ///< SI91X Asynchronous Sockets events queue + + // ALL SOC rx packets use this queue + CCP_M4_TA_RX_QUEUE = 14, ///< SI91X M4 Receive queue + + SI91X_QUEUE_MAX ///< SI91X Maximum queue type +} sl_si91x_queue_type_t; + +/** \addtogroup SL_SI91X_TYPES + * @{ + * */ +/// Si91x command types +/// Si91x band mode. +/// @note Only 2.4 GHz currently supported. +typedef enum { + SL_SI91X_WIFI_BAND_2_4GHZ = 0, ///< 2.4GHz WiFi band + SL_SI91X_WIFI_BAND_5GHZ = 1, ///< 5GHz WiFi band (not currently supported) + SL_SI91X_WIFI_DUAL_BAND = 2 ///< both 2.4GHz and 5GHZ WiFi band (not currently supported) +} sl_si91x_band_mode_t; + +/// Si91x region code. +/// @note Singapore region not currently supported. +typedef enum { + DEFAULT_REGION, ///< Factory default region + US, ///< United States + EU, ///< European Union + JP, ///< Japan + WORLD_DOMAIN, ///< World wide domain + KR, ///< Korea + SG ///< Singapore (not currently supported) +} sl_si91x_region_code_t; + +/// Si91x Timeout types +typedef enum { + SL_SI91X_AUTHENTICATION_ASSOCIATION_TIMEOUT = + 0, ///< Used for setting association and authentication timeout request in millisecs + SL_SI91X_CHANNEL_ACTIVE_SCAN_TIMEOUT, ///< Used for setting dwell time per channel in milli seconds during active scan + SL_SI91X_KEEP_ALIVE_TIMEOUT, ///< Used for setting WLAN keep alive time in seconds + SL_SI91X_CHANNEL_PASSIVE_SCAN_TIMEOUT ///< Used for setting dwell time per channel in milli seconds during passive scan +} sl_si91x_timeout_type_t; + +/// Si91x Wi-Fi VAP ID +typedef enum { + SL_SI91X_WIFI_CLIENT_VAP_ID, ///< Wi-Fi Client VAP ID + SL_SI91X_WIFI_AP_VAP_ID, ///< Wi-Fi Access point VAP ID +} sl_si91x_wifi_vap_id_t; + +// TA RSI_COMMON_REQ_OPERMODE command request structure +// Note: refer sl_wifi_device.h for complete bit map details +/// Si91x boot configuration structure +typedef struct { + uint16_t oper_mode; ///< operation mode, one of the values from @ref sl_si91x_operation_mode_t. + uint16_t coex_mode; ///< coex mode, one of the values from @ref sl_si91x_coex_mode_t. + uint32_t feature_bit_map; ///< Feature bit map, @ref SI91X_FEATURE_BITMAP + uint32_t tcp_ip_feature_bit_map; ///< TCP/IP feature bit map, @ref SI91X_TCP_IP_FEATURE_BITMAP + uint32_t custom_feature_bit_map; ///< Custom feature bit map, @ref SI91X_CUSTOM_FEATURE_BITMAP + uint32_t ext_custom_feature_bit_map; ///< Extended custom feature bit map, @ref SI91X_EXTENDED_CUSTOM_FEATURE_BITMAP + uint32_t bt_feature_bit_map; ///< BT featured bit map, @ref SI91X_BT_FEATURE_BITMAP + uint32_t ext_tcp_ip_feature_bit_map; ///< Extended tcp/ip feature bit map, @ref SI91X_EXTENDED_TCP_IP_FEATURE_BITMAP + uint32_t ble_feature_bit_map; ///< BLE feature bitmap, @ref SI91X_BLE_FEATURE_BITMAP + uint32_t ble_ext_feature_bit_map; ///< BLE extended feature bit map, @ref SI91X_EXTENDED_BLE_CUSTOM_FEATURE_BITMAP + uint32_t config_feature_bit_map; ///< Config feature bit map, @ref SI91X_CONFIG_FEATURE_BITMAP +} sl_si91x_boot_configuration_t; + +/// Timeout Configuration Structure +typedef struct { + uint16_t + active_chan_scan_timeout_value; ///< Time spent on each channel when performing active scan (milliseconds). Default value of 100 millisecs is used when SL_WIFI_DEFAULT_ACTIVE_CHANNEL_SCAN_TIME is passed. + uint16_t + auth_assoc_timeout_value; ///< Authentication and association timeout value. Default value of 300 millisecs is used when SL_WIFI_DEFAULT_AUTH_ASSOCIATION_TIMEOUT is passed. + uint16_t + keep_alive_timeout_value; ///< Keep Alive Timeout value. Default value of 30 secs is used when SL_WIFI_DEFAULT_KEEP_ALIVE_TIMEOUT is passed + uint16_t + passive_scan_timeout_value; ///