From d9ce65c45a550d1b86f4efe149655c5fafa0cda4 Mon Sep 17 00:00:00 2001 From: Gustavo Martin Date: Sun, 21 Dec 2025 21:13:42 +0100 Subject: [PATCH 1/3] created osvvm tests for fifo_cc_got --- tb/RunAllTests.pro | 2 +- tb/fifo/RunAllTests.pro | 35 ++ .../fifo_cc_got/FifoCcGotComponentPkg.vhdl | 95 ++++ tb/fifo/fifo_cc_got/FifoCcGotReceiver.vhdl | 406 +++++++++++++++++ tb/fifo/fifo_cc_got/FifoCcGotTransmitter.vhdl | 277 ++++++++++++ tb/fifo/fifo_cc_got/RunAllTests.pro | 63 +++ tb/fifo/fifo_cc_got/fifo_cc_got_Burst.vhdl | 332 ++++++++++++++ .../fifo_cc_got_FullEmpty_Flags.vhdl | 284 ++++++++++++ tb/fifo/fifo_cc_got/fifo_cc_got_Random.vhdl | 422 ++++++++++++++++++ tb/fifo/fifo_cc_got/fifo_cc_got_Simple.vhdl | 201 +++++++++ .../fifo_cc_got_TestController.vhdl | 68 +++ .../fifo_cc_got_TestController_pkg.vhdl | 85 ++++ .../fifo_cc_got/fifo_cc_got_TestHarness.vhdl | 182 ++++++++ tb/fifo/fifo_cc_got_tb.vhdl | 163 ------- 14 files changed, 2451 insertions(+), 164 deletions(-) create mode 100644 tb/fifo/RunAllTests.pro create mode 100644 tb/fifo/fifo_cc_got/FifoCcGotComponentPkg.vhdl create mode 100644 tb/fifo/fifo_cc_got/FifoCcGotReceiver.vhdl create mode 100644 tb/fifo/fifo_cc_got/FifoCcGotTransmitter.vhdl create mode 100644 tb/fifo/fifo_cc_got/RunAllTests.pro create mode 100644 tb/fifo/fifo_cc_got/fifo_cc_got_Burst.vhdl create mode 100644 tb/fifo/fifo_cc_got/fifo_cc_got_FullEmpty_Flags.vhdl create mode 100644 tb/fifo/fifo_cc_got/fifo_cc_got_Random.vhdl create mode 100644 tb/fifo/fifo_cc_got/fifo_cc_got_Simple.vhdl create mode 100644 tb/fifo/fifo_cc_got/fifo_cc_got_TestController.vhdl create mode 100644 tb/fifo/fifo_cc_got/fifo_cc_got_TestController_pkg.vhdl create mode 100644 tb/fifo/fifo_cc_got/fifo_cc_got_TestHarness.vhdl delete mode 100644 tb/fifo/fifo_cc_got_tb.vhdl diff --git a/tb/RunAllTests.pro b/tb/RunAllTests.pro index b7614f379..06533fd1d 100644 --- a/tb/RunAllTests.pro +++ b/tb/RunAllTests.pro @@ -25,7 +25,7 @@ include ./sync/RunAllTests.pro #include ./cache/RunAllTests.pro #include ./common/RunAllTests.pro #include ./dstruct/RunAllTests.pro -#include ./fifo/RunAllTests.pro +include ./fifo/RunAllTests.pro #include ./io/RunAllTests.pro #include ./mem/RunAllTests.pro #include ./misc/RunAllTests.pro diff --git a/tb/fifo/RunAllTests.pro b/tb/fifo/RunAllTests.pro new file mode 100644 index 000000000..cd8a6e58b --- /dev/null +++ b/tb/fifo/RunAllTests.pro @@ -0,0 +1,35 @@ +# ============================================================================= +# Authors: +# Gustavo Martin +# +# Description: +# RunAllTests.pro for PoC.fifo OSVVM testbench suite +# +# License: +# ============================================================================= +# Copyright 2025-2025 The PoC-Library Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================= + +# FIFO with Common Clock (cc), pipelined interface +include ./fifo_cc_got/RunAllTests.pro + +# FIFO with Common Clock (cc), temporary put with commit/rollback +# include ./fifo_cc_got_tempput/RunAllTests.pro + +# # FIFO with Independent Clocks (ic), address-based stream assembly +# include ./fifo_ic_assembly/RunAllTests.pro + +# # FIFO with Independent Clocks (ic), first-word-fall-through +# include ./fifo_ic_got/RunAllTests.pro diff --git a/tb/fifo/fifo_cc_got/FifoCcGotComponentPkg.vhdl b/tb/fifo/fifo_cc_got/FifoCcGotComponentPkg.vhdl new file mode 100644 index 000000000..39750aaf2 --- /dev/null +++ b/tb/fifo/fifo_cc_got/FifoCcGotComponentPkg.vhdl @@ -0,0 +1,95 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- ============================================================================= +-- Authors: Gustavo Martin +-- +-- Package: FifoCcGotComponentPkg +-- +-- Description: +-- ------------------------------------- +-- Component declarations for FIFO CC Got Verification Components +-- Uses OSVVM's standard StreamRecType for transaction interfaces +-- +-- License: +-- ============================================================================= +-- Copyright 2025-2025 The PoC-Library Authors +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library IEEE; +use IEEE.std_logic_1164.all; + +library osvvm; +context osvvm.OsvvmContext; + +library osvvm_common; +context osvvm_common.OsvvmCommonContext; + +package FifoCcGotComponentPkg is + + ------------------------------------------------------------ + -- FifoCcGotTransmitter - Write side VC + ------------------------------------------------------------ + component FifoCcGotTransmitter is + generic ( + MODEL_ID_NAME : string := ""; + DATA_WIDTH : integer := 8; + ESTATE_WIDTH : integer := 2; + tpd_Clk_put : time := 2 ns; + tpd_Clk_din : time := 2 ns + ); + port ( + -- Global Signals + Clk : in std_logic; + nReset : in std_logic; + + -- FIFO Write Interface + put : out std_logic; + din : out std_logic_vector(DATA_WIDTH-1 downto 0); + full : in std_logic; + estate_wr : in std_logic_vector(ESTATE_WIDTH-1 downto 0); + + -- Transaction Interface (OSVVM Standard) + TransRec : inOut StreamRecType + ); + end component FifoCcGotTransmitter; + + ------------------------------------------------------------ + -- FifoCcGotReceiver - Read side VC + ------------------------------------------------------------ + component FifoCcGotReceiver is + generic ( + MODEL_ID_NAME : string := ""; + DATA_WIDTH : integer := 8; + FSTATE_WIDTH : integer := 2; + tpd_Clk_got : time := 2 ns + ); + port ( + -- Global Signals + Clk : in std_logic; + nReset : in std_logic; + + -- FIFO Read Interface + got : out std_logic; + dout : in std_logic_vector(DATA_WIDTH-1 downto 0); + valid : in std_logic; + fstate_rd : in std_logic_vector(FSTATE_WIDTH-1 downto 0); + + -- Transaction Interface (OSVVM Standard) + TransRec : inOut StreamRecType + ); + end component FifoCcGotReceiver; + +end package FifoCcGotComponentPkg; diff --git a/tb/fifo/fifo_cc_got/FifoCcGotReceiver.vhdl b/tb/fifo/fifo_cc_got/FifoCcGotReceiver.vhdl new file mode 100644 index 000000000..f30a2ad77 --- /dev/null +++ b/tb/fifo/fifo_cc_got/FifoCcGotReceiver.vhdl @@ -0,0 +1,406 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- ============================================================================= +-- Authors: Gustavo Martin +-- +-- Entity: FifoCcGotReceiver +-- +-- Description: +-- ------------------------------------- +-- OSVVM-based Verification Component - FIFO Receiver (Read side) +-- Implements the read interface (got/dout/valid) for fifo_cc_got +-- Uses OSVVM's standard StreamRecType for transaction interface +-- +-- License: +-- ============================================================================= +-- Copyright 2025-2025 The PoC-Library Authors +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +library osvvm; +context osvvm.OsvvmContext; +use osvvm.ScoreboardPkg_slv.all; + +library osvvm_common; +context osvvm_common.OsvvmCommonContext; +use osvvm_common.FifoFillPkg_slv.all; + +entity FifoCcGotReceiver is + generic ( + MODEL_ID_NAME : string := ""; + DATA_WIDTH : integer := 8; + FSTATE_WIDTH : integer := 2; + tpd_Clk_got : time := 2 ns + ); + port ( + -- Global Signals + Clk : in std_logic; + nReset : in std_logic; + + -- FIFO Read Interface + got : out std_logic; + dout : in std_logic_vector(DATA_WIDTH-1 downto 0); + valid : in std_logic; + fstate_rd : in std_logic_vector(FSTATE_WIDTH-1 downto 0); + + -- Transaction Interface (OSVVM Standard) + TransRec : inout StreamRecType + ); +end entity FifoCcGotReceiver; + + +architecture VC of FifoCcGotReceiver is + + constant MODEL_INSTANCE_NAME : string := + IfElse(MODEL_ID_NAME'length > 0, MODEL_ID_NAME, + to_lower(PathTail(FifoCcGotReceiver'path_name))); + + signal ModelID : AlertLogIDType; + signal TransactionCount : integer := 0; + +begin + + ------------------------------------------------------------ + -- Initialize + ------------------------------------------------------------ + Initialize : process + variable ID : AlertLogIDType; + begin + ID := NewID(MODEL_INSTANCE_NAME); + ModelID <= ID; + wait; + end process; + + ------------------------------------------------------------ + -- Transaction Handler + ------------------------------------------------------------ + TransactionHandler : process + variable LocalData : std_logic_vector(DATA_WIDTH-1 downto 0); + variable ExpectedData : std_logic_vector(DATA_WIDTH-1 downto 0); + variable NumWords : integer; + variable IntOption : integer; + variable Available : boolean; + begin + -- Initialize outputs + got <= '0'; + + -- Wait for model ID initialization + wait for 0 ns; + + -- Wait for reset release + wait until nReset = '1'; + WaitForClock(Clk, 2); + + -- Main transaction loop + TransactionLoop: loop + -- Wait for transaction request + WaitForTransaction( + Rdy => TransRec.Rdy, + Ack => TransRec.Ack + ); + + case TransRec.Operation is + + --------------------------------------------------------- + -- GET - Blocking read + --------------------------------------------------------- + when GET => + -- Acknowledge read (handshake) - hold until valid confirmed + got <= '1'; + loop + WaitForClock(Clk, 1); + exit when valid = '1'; + end loop; + + -- Capture data when both valid and got are high + LocalData := dout; + + -- Deassert got + got <= '0'; + + TransRec.DataFromModel <= SafeResize(LocalData, TransRec.DataFromModel'length); + TransactionCount <= TransactionCount + 1; + Log(ModelID, "GET: 0x" & to_hstring(LocalData), DEBUG); + + --------------------------------------------------------- + -- TRY_GET - Non-blocking read + --------------------------------------------------------- + when TRY_GET => + if valid = '1' then + -- Acknowledge read (handshake) + got <= '1'; + WaitForClock(Clk, 1); + + -- Capture data if handshake confirmed + if valid = '1' then + LocalData := dout; + end if; + + got <= '0'; + + TransRec.DataFromModel <= SafeResize(LocalData, TransRec.DataFromModel'length); + TransRec.BoolFromModel <= true; + TransactionCount <= TransactionCount + 1; + Log(ModelID, "TRY_GET success: 0x" & to_hstring(LocalData), DEBUG); + else + TransRec.BoolFromModel <= false; + Log(ModelID, "TRY_GET failed: FIFO empty", DEBUG); + end if; + + --------------------------------------------------------- + -- CHECK - Blocking read with verification + --------------------------------------------------------- + when CHECK => + ExpectedData := SafeResize(TransRec.DataToModel, DATA_WIDTH); + + -- Acknowledge read (handshake) - hold until valid confirmed + got <= '1'; + loop + WaitForClock(Clk, 1); + exit when valid = '1'; + end loop; + + -- Capture data when both valid and got are high + LocalData := dout; + + got <= '0'; + + TransRec.DataFromModel <= SafeResize(LocalData, TransRec.DataFromModel'length); + TransactionCount <= TransactionCount + 1; + + -- Verify data + AffirmIf(ModelID, + LocalData = ExpectedData, + "CHECK: Got 0x" & to_hstring(LocalData) & + ", Expected 0x" & to_hstring(ExpectedData)); + + --------------------------------------------------------- + -- TRY_CHECK - Non-blocking check + --------------------------------------------------------- + when TRY_CHECK => + ExpectedData := SafeResize(TransRec.DataToModel, DATA_WIDTH); + + if valid = '1' then + -- Acknowledge read (handshake) + got <= '1'; + WaitForClock(Clk, 1); + + -- Capture data if handshake confirmed + if valid = '1' then + LocalData := dout; + end if; + + got <= '0'; + + TransRec.DataFromModel <= SafeResize(LocalData, TransRec.DataFromModel'length); + TransRec.BoolFromModel <= true; + TransactionCount <= TransactionCount + 1; + + AffirmIf(ModelID, + LocalData = ExpectedData, + "TRY_CHECK: Got 0x" & to_hstring(LocalData) & + ", Expected 0x" & to_hstring(ExpectedData)); + else + TransRec.BoolFromModel <= false; + end if; + + --------------------------------------------------------- + -- GET_BURST - Read burst into BurstFifo + --------------------------------------------------------- + when GET_BURST => + NumWords := TransRec.IntToModel; + Log(ModelID, "GET_BURST: " & integer'image(NumWords) & " words", INFO); + + for i in 1 to NumWords loop + -- Acknowledge read (handshake) - hold until valid confirmed + got <= '1'; + loop + WaitForClock(Clk, 1); + exit when valid = '1'; + end loop; + + -- Capture data when both valid and got are high + LocalData := dout; + + got <= '0'; + + -- Push to burst FIFO + Push(TransRec.BurstFifo, SafeResize(LocalData, TransRec.DataFromModel'length)); + + TransactionCount <= TransactionCount + 1; + end loop; + + --------------------------------------------------------- + -- TRY_GET_BURST - Non-blocking burst read + --------------------------------------------------------- + when TRY_GET_BURST => + NumWords := TransRec.IntToModel; + TransRec.IntFromModel <= 0; + Log(ModelID, "TRY_GET_BURST: " & integer'image(NumWords) & " words requested", INFO); + + for i in 1 to NumWords loop + if valid = '0' then + exit; + end if; + + -- Acknowledge read (handshake) + got <= '1'; + WaitForClock(Clk, 1); + + -- Capture data if handshake confirmed + if valid = '0' then + got <= '0'; + exit; + end if; + LocalData := dout; + + got <= '0'; + + Push(TransRec.BurstFifo, SafeResize(LocalData, TransRec.DataFromModel'length)); + TransactionCount <= TransactionCount + 1; + TransRec.IntFromModel <= i; + end loop; + + --------------------------------------------------------- + -- CHECK_BURST - Read and verify against BurstFifo + --------------------------------------------------------- + when CHECK_BURST => + NumWords := TransRec.IntToModel; + Log(ModelID, "CHECK_BURST: " & integer'image(NumWords) & " words", INFO); + + for i in 1 to NumWords loop + -- Acknowledge read (handshake) - hold until valid confirmed + got <= '1'; + loop + WaitForClock(Clk, 1); + exit when valid = '1'; + end loop; + + -- Capture data when both valid and got are high + LocalData := dout; + + got <= '0'; + + -- Use OSVVM Check with BurstFifo scoreboard + Check(TransRec.BurstFifo, SafeResize(LocalData, TransRec.DataFromModel'length)); + + TransactionCount <= TransactionCount + 1; + end loop; + + --------------------------------------------------------- + -- TRY_CHECK_BURST - Non-blocking check burst + --------------------------------------------------------- + when TRY_CHECK_BURST => + NumWords := TransRec.IntToModel; + TransRec.IntFromModel <= 0; + Log(ModelID, "TRY_CHECK_BURST: " & integer'image(NumWords) & " words", INFO); + + for i in 1 to NumWords loop + if valid = '0' then + exit; + end if; + + -- Acknowledge read (handshake) + got <= '1'; + WaitForClock(Clk, 1); + + -- Capture data if handshake confirmed + if valid = '0' then + got <= '0'; + exit; + end if; + LocalData := dout; + + got <= '0'; + + -- Use OSVVM Check with BurstFifo scoreboard + Check(TransRec.BurstFifo, SafeResize(LocalData, TransRec.DataFromModel'length)); + + TransactionCount <= TransactionCount + 1; + TransRec.IntFromModel <= i; + end loop; + + --------------------------------------------------------- + -- GOT_BURST - Check if burst data is available + --------------------------------------------------------- + when GOT_BURST => + NumWords := TransRec.IntToModel; + Available := (valid = '1'); -- Check if at least one word available + TransRec.BoolFromModel <= Available; + + --------------------------------------------------------- + -- WAIT_FOR_CLOCK + --------------------------------------------------------- + when WAIT_FOR_CLOCK => + NumWords := TransRec.IntToModel; + WaitForClock(Clk, NumWords); + + --------------------------------------------------------- + -- GET_TRANSACTION_COUNT + --------------------------------------------------------- + when GET_TRANSACTION_COUNT => + TransRec.IntFromModel <= TransactionCount; + + --------------------------------------------------------- + -- WAIT_FOR_TRANSACTION + --------------------------------------------------------- + when WAIT_FOR_TRANSACTION => + -- Wait for data to become available + if valid = '0' then + wait until valid = '1'; + end if; + + --------------------------------------------------------- + -- GET_ALERTLOG_ID + --------------------------------------------------------- + when GET_ALERTLOG_ID => + TransRec.IntFromModel <= integer(ModelID); + + --------------------------------------------------------- + -- SET_MODEL_OPTIONS + --------------------------------------------------------- + when SET_MODEL_OPTIONS => + IntOption := TransRec.Options; + case IntOption is + when others => + Alert(ModelID, "SetModelOptions: Unknown option: " & integer'image(IntOption), FAILURE); + end case; + + --------------------------------------------------------- + -- GET_MODEL_OPTIONS + --------------------------------------------------------- + when GET_MODEL_OPTIONS => + IntOption := TransRec.Options; + case IntOption is + when others => + Alert(ModelID, "GetModelOptions: Unknown option: " & integer'image(IntOption), FAILURE); + end case; + + --------------------------------------------------------- + -- Others + --------------------------------------------------------- + when others => + Alert(ModelID, "Unsupported operation: " & StreamOperationType'image(TransRec.Operation), ERROR); + + end case; + + end loop TransactionLoop; + end process; + +end architecture VC; diff --git a/tb/fifo/fifo_cc_got/FifoCcGotTransmitter.vhdl b/tb/fifo/fifo_cc_got/FifoCcGotTransmitter.vhdl new file mode 100644 index 000000000..74d03c472 --- /dev/null +++ b/tb/fifo/fifo_cc_got/FifoCcGotTransmitter.vhdl @@ -0,0 +1,277 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- ============================================================================= +-- Authors: Gustavo Martin +-- +-- Entity: FifoCcGotTransmitter +-- +-- Description: +-- ------------------------------------- +-- OSVVM-based Verification Component - FIFO Transmitter (Write side) +-- Implements the write interface (put/din/full) for fifo_cc_got +-- Uses OSVVM's standard StreamRecType for transaction interface +-- +-- License: +-- ============================================================================= +-- Copyright 2025-2025 The PoC-Library Authors +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +library osvvm; +context osvvm.OsvvmContext; +use osvvm.ScoreboardPkg_slv.all; + +library osvvm_common; +context osvvm_common.OsvvmCommonContext; +use osvvm_common.FifoFillPkg_slv.all; + +entity FifoCcGotTransmitter is + generic ( + MODEL_ID_NAME : string := ""; + DATA_WIDTH : integer := 8; + ESTATE_WIDTH : integer := 2; + tpd_Clk_put : time := 2 ns; + tpd_Clk_din : time := 2 ns + ); + port ( + -- Global Signals + Clk : in std_logic; + nReset : in std_logic; + + -- FIFO Write Interface + put : out std_logic; + din : out std_logic_vector(DATA_WIDTH-1 downto 0); + full : in std_logic; + estate_wr : in std_logic_vector(ESTATE_WIDTH-1 downto 0); + + -- Transaction Interface (OSVVM Standard) + TransRec : inout StreamRecType + ); +end entity FifoCcGotTransmitter; + + +architecture VC of FifoCcGotTransmitter is + + constant MODEL_INSTANCE_NAME : string := + IfElse(MODEL_ID_NAME'length > 0, MODEL_ID_NAME, + to_lower(PathTail(FifoCcGotTransmitter'path_name))); + + signal ModelID : AlertLogIDType; + signal TransactionCount : integer := 0; + +begin + + ------------------------------------------------------------ + -- Initialize + ------------------------------------------------------------ + Initialize : process + variable ID : AlertLogIDType; + begin + ID := NewID(MODEL_INSTANCE_NAME); + ModelID <= ID; + wait; + end process; + + ------------------------------------------------------------ + -- Transaction Handler + ------------------------------------------------------------ + TransactionHandler : process + variable LocalData : std_logic_vector(DATA_WIDTH-1 downto 0); + variable NumWords : integer; + variable IntOption : integer; + begin + -- Initialize outputs + put <= '0'; + din <= (others => '0'); + + -- Wait for model ID initialization + wait for 0 ns; + + -- Wait for reset release + wait until nReset = '1'; + WaitForClock(Clk, 2); + + -- Main transaction loop + TransactionLoop: loop + -- Wait for transaction request + WaitForTransaction( + Rdy => TransRec.Rdy, + Ack => TransRec.Ack + ); + + case TransRec.Operation is + + --------------------------------------------------------- + -- SEND - Blocking write + --------------------------------------------------------- + when SEND => + LocalData := SafeResize(TransRec.DataToModel, DATA_WIDTH); + + -- Assert write request with data + din <= LocalData; + put <= '1'; + + -- Hold put='1' until clock edge with full='0' (handshake confirmed) + loop + WaitForClock(Clk); + exit when full = '0'; + end loop; + + -- Deassert after handshake completes + put <= '0'; + + TransactionCount <= TransactionCount + 1; + Log(ModelID, "SEND: 0x" & to_hstring(LocalData), DEBUG); + + --------------------------------------------------------- + -- SEND_ASYNC - Non-blocking write (immediate return) + --------------------------------------------------------- + when SEND_ASYNC => + LocalData := SafeResize(TransRec.DataToModel, DATA_WIDTH); + + -- Assert write request + din <= LocalData; + put <= '1'; + WaitForClock(Clk); + + -- Check if write was accepted on this clock edge + if full = '0' then + TransactionCount <= TransactionCount + 1; + Log(ModelID, "SEND_ASYNC: 0x" & to_hstring(LocalData), DEBUG); + else + Alert(ModelID, "SEND_ASYNC failed: FIFO full", WARNING); + end if; + + put <= '0'; + + --------------------------------------------------------- + -- SEND_BURST - Write burst from BurstFifo + --------------------------------------------------------- + when SEND_BURST => + NumWords := TransRec.IntToModel; + Log(ModelID, "SEND_BURST: " & integer'image(NumWords) & " words", INFO); + + for i in 1 to NumWords loop + LocalData := SafeResize(Pop(TransRec.BurstFifo), DATA_WIDTH); + + -- Assert write request with data + din <= LocalData; + put <= '1'; + + -- Hold put='1' until clock edge with full='0' (handshake confirmed) + loop + WaitForClock(Clk); + exit when full = '0'; + end loop; + + TransactionCount <= TransactionCount + 1; + end loop; + + -- Deassert put after burst completes + put <= '0'; + + --------------------------------------------------------- + -- SEND_BURST_ASYNC - Non-blocking burst + --------------------------------------------------------- + when SEND_BURST_ASYNC => + NumWords := TransRec.IntToModel; + Log(ModelID, "SEND_BURST_ASYNC: " & integer'image(NumWords) & " words", INFO); + + for i in 1 to NumWords loop + LocalData := SafeResize(Pop(TransRec.BurstFifo), DATA_WIDTH); + + -- Assert write request + din <= LocalData; + put <= '1'; + WaitForClock(Clk); + + -- Check if write was accepted on this clock edge + if full = '0' then + TransactionCount <= TransactionCount + 1; + else + -- FIFO full - exit burst early + put <= '0'; + Alert(ModelID, "SEND_BURST_ASYNC: FIFO full at word " & integer'image(i), WARNING); + exit; + end if; + end loop; + + -- Deassert put after burst completes + put <= '0'; + + --------------------------------------------------------- + -- WAIT_FOR_CLOCK + --------------------------------------------------------- + when WAIT_FOR_CLOCK => + NumWords := TransRec.IntToModel; + WaitForClock(Clk, NumWords); + + --------------------------------------------------------- + -- GET_TRANSACTION_COUNT + --------------------------------------------------------- + when GET_TRANSACTION_COUNT => + TransRec.IntFromModel <= TransactionCount; + + --------------------------------------------------------- + -- WAIT_FOR_TRANSACTION + --------------------------------------------------------- + when WAIT_FOR_TRANSACTION => + -- Wait for any pending transactions to complete + if full = '1' then + wait until full = '0'; + end if; + + --------------------------------------------------------- + -- GET_ALERTLOG_ID + --------------------------------------------------------- + when GET_ALERTLOG_ID => + TransRec.IntFromModel <= integer(ModelID); + + --------------------------------------------------------- + -- SET_MODEL_OPTIONS + --------------------------------------------------------- + when SET_MODEL_OPTIONS => + IntOption := TransRec.Options; + case IntOption is + when others => + Alert(ModelID, "SetModelOptions: Unknown option: " & integer'image(IntOption), FAILURE); + end case; + + --------------------------------------------------------- + -- GET_MODEL_OPTIONS + --------------------------------------------------------- + when GET_MODEL_OPTIONS => + IntOption := TransRec.Options; + case IntOption is + when others => + Alert(ModelID, "GetModelOptions: Unknown option: " & integer'image(IntOption), FAILURE); + end case; + + --------------------------------------------------------- + -- Others + --------------------------------------------------------- + when others => + Alert(ModelID, "Unsupported operation: " & StreamOperationType'image(TransRec.Operation), ERROR); + + end case; + + end loop TransactionLoop; + end process; + +end architecture VC; diff --git a/tb/fifo/fifo_cc_got/RunAllTests.pro b/tb/fifo/fifo_cc_got/RunAllTests.pro new file mode 100644 index 000000000..5033dc4df --- /dev/null +++ b/tb/fifo/fifo_cc_got/RunAllTests.pro @@ -0,0 +1,63 @@ +# ============================================================================= +# Authors: +# Gustavo Martin +# +# Description: +# RunAllTests.pro for fifo_cc_got OSVVM testbench +# Uses Verification Components with Transaction interfaces +# Uses FifoFillPkg for sophisticated burst patterns +# +# License: +# ============================================================================= +# Copyright 2025-2025 The PoC-Library Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================= + +TestSuite PoC.fifo.cc.got +library tb_fifo_cc_got + +# Analyze Verification Component packages and entities +# Note: FifoCcGotTransactionPkg is no longer needed - using OSVVM's StreamRecType +analyze FifoCcGotComponentPkg.vhdl +analyze FifoCcGotTransmitter.vhdl +analyze FifoCcGotReceiver.vhdl + +# Analyze Test Controller package and entity +analyze fifo_cc_got_TestController_pkg.vhdl +analyze fifo_cc_got_TestController.vhdl + +# Analyze Test Harness (instantiates DUT and VCs) +analyze fifo_cc_got_TestHarness.vhdl + +# Run all tests for each configuration (CONFIG_INDEX 0 to 7) +# CONFIG_INDEX bits: [2]=OUTPUT_REG, [1]=STATE_REG, [0]=DATA_REG +for {set config 0} {$config < 8} {incr config} { + + # Run Simple test + TestCase fifo_cc_got_Simple_Config_$config + RunTest fifo_cc_got_Simple.vhdl [generic CONFIG_INDEX $config] + + # Run Flags test + TestCase fifo_cc_got_Flags_Config_$config + RunTest fifo_cc_got_FullEmpty_Flags.vhdl [generic CONFIG_INDEX $config] + + # Run Burst test + TestCase fifo_cc_got_Burst_Config_$config + RunTest fifo_cc_got_Burst.vhdl [generic CONFIG_INDEX $config] + + # Run Random test + TestCase fifo_cc_got_Random_Config_$config + RunTest fifo_cc_got_Random.vhdl [generic CONFIG_INDEX $config] + +} diff --git a/tb/fifo/fifo_cc_got/fifo_cc_got_Burst.vhdl b/tb/fifo/fifo_cc_got/fifo_cc_got_Burst.vhdl new file mode 100644 index 000000000..f356d7163 --- /dev/null +++ b/tb/fifo/fifo_cc_got/fifo_cc_got_Burst.vhdl @@ -0,0 +1,332 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- ============================================================================= +-- Authors: Thomas B. Preusser +-- Gustavo Martin +-- +-- Architecture: fifo_cc_got_Burst +-- +-- Description: +-- ------------------------------------- +-- Burst OSVVM test for fifo_cc_got using Verification Components +-- Uses Transaction interface to communicate with VCs for: +-- - Full/Empty transitions +-- - Back-to-back operations +-- - Burst operations with PushBurstIncrement/PushBurstRandom +-- - State indicator verification via GetFifoStatus +-- - Simultaneous read/write stress testing +-- +-- Uses OSVVM FifoFillPkg for sophisticated burst patterns +-- Uses cross-coverage for state combinations +-- +-- License: +-- ============================================================================= +-- Copyright 2025-2025 The PoC-Library Authors +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +library osvvm; +context osvvm.OsvvmContext; +use osvvm.ScoreboardPkg_slv.all; + +library osvvm_common; +context osvvm_common.OsvvmCommonContext; +use osvvm_common.FifoFillPkg_slv.all; + +use work.fifo_cc_got_TestController_pkg.all; + +architecture Burst of fifo_cc_got_TestController is + -- Phase synchronization barriers + signal TestDone : integer_barrier := 1; + signal Phase1Fill : integer_barrier := 1; -- Writer fills FIFO + signal Phase1Done : integer_barrier := 1; -- Reader drains FIFO + signal Phase2Start : integer_barrier := 1; -- Both ready for Phase 2 + signal Phase2Done : integer_barrier := 1; + signal Phase3Start : integer_barrier := 1; -- Both ready for Phase 3 + signal Phase3Done : integer_barrier := 1; + signal Phase4Start : integer_barrier := 1; -- Both ready for Phase 4 + signal Phase4Done : integer_barrier := 1; + + -- Alert/Log IDs + constant TCID : AlertLogIDType := NewID("FifoCcGotBurst_" & ConfigToString(CONFIG_INDEX)); + +begin + ---------------------------------------------------------------------------- + -- Control Process - manages test lifecycle + ---------------------------------------------------------------------------- + ControlProc : process + constant ProcID : AlertLogIDType := NewID("ControlProc", TCID); + constant TIMEOUT : time := 500 ms; + begin + SetTestName("fifo_cc_got_Burst"); + + SetLogEnable(PASSED, FALSE); + SetLogEnable(INFO, TRUE); + SetLogEnable(DEBUG, FALSE); + wait for 0 ns; wait for 0 ns; + + TranscriptOpen; + SetTranscriptMirror(TRUE); + + -- Initialize Burst FIFOs + TxBurstFifo <= NewID("TxBurstFifo", TCID); + RxBurstFifo <= NewID("RxBurstFifo", TCID); + + wait until nReset = '1'; + ClearAlerts; + + WaitForBarrier(TestDone, TIMEOUT); + AlertIf(ProcID, now >= TIMEOUT, "Test finished due to timeout"); + AlertIf(ProcID, GetAffirmCount < 1, "Test is not Self-Checking"); + + EndOfTestReports(ReportAll => TRUE); + std.env.stop; + end process; + + ---------------------------------------------------------------------------- + -- Writer Process - uses Transaction interface to send data + ---------------------------------------------------------------------------- + WriterProc : process + constant ProcID : AlertLogIDType := NewID("WriterProc", TCID); + variable WriteCount : integer := 0; + variable SendOk : boolean; + begin + wait until nReset = '1'; + WaitForClock(TxRec, 2); + + -- Assign BurstFifo to transaction record + TxRec.BurstFifo <= TxBurstFifo; + + --------------------------------------------------------------------------- + -- Phase 1: Fill FIFO to capacity using Send() + --------------------------------------------------------------------------- + Log(ProcID, "Phase 1: Fill FIFO to capacity via Send()", INFO); + + -- Fill with sequential data using individual Send transactions + loop + -- Use blocking Send with std_logic_vector + Send(TxRec, std_logic_vector(to_unsigned(WriteCount, D_BITS))); + WriteCount := WriteCount + 1; + + -- Wait for full signal to update after the write + WaitForClock(TxRec, 1); + + -- Check if FIFO is now full + exit when full = '1'; + end loop; + + -- Verify FIFO reached full state + AffirmIf(ProcID, full = '1', "Phase 1: FIFO should be full after filling"); + + Log(ProcID, "Phase 1: Filled " & integer'image(WriteCount) & " words", INFO); + -- WaitForClock(TxRec); + -- Signal that FIFO is full, reader can now drain + WaitForBarrier(Phase1Fill); + + -- Wait for reader to drain Phase 1 + WaitForBarrier(Phase1Done); + + --------------------------------------------------------------------------- + -- Phase 2: Burst writes using SendBurst (128 words) + --------------------------------------------------------------------------- + -- Synchronize start of Phase 2 + WaitForBarrier(Phase2Start); + + Log(ProcID, "Phase 2: Burst writes via SendBurst()", INFO); + + -- Fill TxBurstFifo with incremental data + PushBurstIncrement(TxBurstFifo, WriteCount, 128, D_BITS); + + -- Send burst + SendBurst(TxRec, 128); + WriteCount := WriteCount + 128; + + Log(ProcID, "Phase 2: Wrote 128 burst words", INFO); + + -- Wait for reader to complete Phase 2 + WaitForBarrier(Phase2Done); + + --------------------------------------------------------------------------- + -- Phase 3: Random burst writes with multiple small bursts + --------------------------------------------------------------------------- + -- Synchronize start of Phase 3 + WaitForBarrier(Phase3Start); + + Log(ProcID, "Phase 3: Multiple random bursts via SendBurst()", INFO); + + for burst in 0 to 9 loop + -- Fill with random data + PushBurstRandom(TxBurstFifo, WriteCount + burst*16, 16, D_BITS); + + -- Send burst of 16 words + SendBurst(TxRec, 16); + WriteCount := WriteCount + 16; + + -- Small gap between bursts + WaitForClock(TxRec, 5); + end loop; + + Log(ProcID, "Phase 3: Wrote random burst words", INFO); + + -- Wait for reader to complete Phase 3 + WaitForBarrier(Phase3Done); + + --------------------------------------------------------------------------- + -- Phase 4: Mixed operations stress test + --------------------------------------------------------------------------- + -- Synchronize start of Phase 4 + WaitForBarrier(Phase4Start); + + Log(ProcID, "Phase 4: Mixed operations stress test", INFO); + + -- Mix of single sends and small bursts + for i in 0 to 24 loop + if (i mod 3) = 0 then + -- Single send + Send(TxRec, std_logic_vector(to_unsigned(WriteCount, D_BITS))); + WriteCount := WriteCount + 1; + else + -- Small burst of 4 words + PushBurstIncrement(TxBurstFifo, WriteCount, 4, D_BITS); + SendBurst(TxRec, 4); + WriteCount := WriteCount + 4; + end if; + end loop; + + Log(ProcID, "Total writes: " & integer'image(WriteCount), INFO); + + WaitForBarrier(Phase4Done); + WaitForBarrier(TestDone); + wait; + end process; + + ---------------------------------------------------------------------------- + -- Reader Process - uses Transaction interface to verify data + ---------------------------------------------------------------------------- + ReaderProc : process + constant ProcID : AlertLogIDType := NewID("ReaderProc", TCID); + variable ReadCount : integer := 0; + variable ReadData : std_logic_vector(D_BITS-1 downto 0); + begin + wait until nReset = '1'; + WaitForClock(RxRec, 2); + + -- Assign BurstFifo to transaction record + RxRec.BurstFifo <= RxBurstFifo; + + --------------------------------------------------------------------------- + -- Phase 1: Drain FIFO using Check() + --------------------------------------------------------------------------- + -- Wait for writer to fill FIFO completely + Log(ProcID, "Phase 1: Wait for writer to fill FIFO completely", INFO); + WaitForBarrier(Phase1Fill); + + Log(ProcID, "Phase 1: Drain FIFO via Check()", INFO); + + -- Drain sequential data using individual Check transactions until FIFO is empty + while valid = '1' loop + Check(RxRec, std_logic_vector(to_unsigned(ReadCount, D_BITS))); + ReadCount := ReadCount + 1; + WaitForClock(RxRec, 1); + end loop; + + -- Verify FIFO is empty + AffirmIf(ProcID, valid = '0', "Phase 1: FIFO should be empty after draining"); + + Log(ProcID, "Phase 1: Read " & integer'image(ReadCount) & " words", INFO); + + WaitForBarrier(Phase1Done); + + --------------------------------------------------------------------------- + -- Phase 2: Verify burst data using CheckBurst + --------------------------------------------------------------------------- + -- Synchronize start of Phase 2 + WaitForBarrier(Phase2Start); + + Log(ProcID, "Phase 2: Verify burst data via CheckBurst()", INFO); + + -- Prepare expected values + PushBurstIncrement(RxBurstFifo, ReadCount, 128, D_BITS); + + -- Check burst + CheckBurst(RxRec, 128); + ReadCount := ReadCount + 128; + Log(ProcID, "Phase 2: Verified 128 words", INFO); + + WaitForBarrier(Phase2Done); + + --------------------------------------------------------------------------- + -- Phase 3: Verify random burst data + --------------------------------------------------------------------------- + -- Synchronize start of Phase 3 + WaitForBarrier(Phase3Start); + + Log(ProcID, "Phase 3: Verify random bursts via CheckBurst()", INFO); + + for burst in 0 to 9 loop + -- Same seed pattern as writer + PushBurstRandom(RxBurstFifo, ReadCount + burst*16, 16, D_BITS); + + -- Check burst + CheckBurst(RxRec, 16); + ReadCount := ReadCount + 16; + end loop; + + Log(ProcID, "Phase 3: Verified 64 words", INFO); + + WaitForBarrier(Phase3Done); + + --------------------------------------------------------------------------- + -- Phase 4: Verify mixed operations + --------------------------------------------------------------------------- + -- Synchronize start of Phase 4 + WaitForBarrier(Phase4Start); + + Log(ProcID, "Phase 4: Verify mixed operations", INFO); + + for i in 0 to 24 loop + if (i mod 3) = 0 then + -- Single check + Check(RxRec, std_logic_vector(to_unsigned(ReadCount, D_BITS))); + ReadCount := ReadCount + 1; + else + -- Small burst of 4 words + PushBurstIncrement(RxBurstFifo, ReadCount, 4, D_BITS); + CheckBurst(RxRec, 4); + ReadCount := ReadCount + 4; + end if; + end loop; + + Log(ProcID, "Total reads verified: " & integer'image(ReadCount), INFO); + + WaitForBarrier(Phase4Done); + WaitForBarrier(TestDone); + wait; + end process; + +end architecture; + +-- Configuration for Burst test +configuration fifo_cc_got_Burst of fifo_cc_got_TestHarness is + for TestHarness + for TestCtrl : fifo_cc_got_TestController + use entity work.fifo_cc_got_TestController(Burst); + end for; + end for; +end configuration; diff --git a/tb/fifo/fifo_cc_got/fifo_cc_got_FullEmpty_Flags.vhdl b/tb/fifo/fifo_cc_got/fifo_cc_got_FullEmpty_Flags.vhdl new file mode 100644 index 000000000..224b627d0 --- /dev/null +++ b/tb/fifo/fifo_cc_got/fifo_cc_got_FullEmpty_Flags.vhdl @@ -0,0 +1,284 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- ============================================================================= +-- Authors: Thomas B. Preusser +-- Gustavo Martin +-- +-- Architecture: fifo_cc_got_FullEmpty_Flags +-- +-- Description: +-- ------------------------------------- +-- Full/Empty Flags OSVVM test for fifo_cc_got using Verification Components +-- Uses Transaction interface to test: +-- - Reaching Full state (full = '1') with single writes and bursts +-- - Reaching Empty state (valid = '0') with single reads and bursts +-- - Verifying flag transitions during fill/drain operations +-- +-- Test Phases: +-- Phase 1: Fill to full using single Send() operations +-- Phase 2: Drain to empty using single Check() operations +-- Phase 3: Fill to full using SendBurst() operation +-- Phase 4: Drain to empty using CheckBurst() operation +-- +-- License: +-- ============================================================================= +-- Copyright 2025-2025 The PoC-Library Authors +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +library osvvm; +context osvvm.OsvvmContext; +use osvvm.ScoreboardPkg_slv.all; + +library osvvm_common; +context osvvm_common.OsvvmCommonContext; +use osvvm_common.FifoFillPkg_slv.all; + +use work.fifo_cc_got_TestController_pkg.all; + +architecture FullEmpty_Flags of fifo_cc_got_TestController is + -- Phase synchronization barriers + signal TestDone : integer_barrier := 1; + signal Phase1Done : integer_barrier := 1; -- Phase 1: Single fill to full + signal Phase2Done : integer_barrier := 1; -- Phase 2: Single drain to empty + signal Phase3Done : integer_barrier := 1; -- Phase 3: Burst fill to full + signal Phase4Done : integer_barrier := 1; -- Phase 4: Burst drain to empty + + -- Alert/Log IDs + constant TCID : AlertLogIDType := NewID("FifoCcGotFullEmpty_" & ConfigToString(CONFIG_INDEX)); + +begin + ---------------------------------------------------------------------------- + -- Control Process - manages test lifecycle + ---------------------------------------------------------------------------- + ControlProc : process + constant ProcID : AlertLogIDType := NewID("ControlProc", TCID); + constant TIMEOUT : time := 500 ms; + begin + SetTestName("fifo_cc_got_FullEmpty_Flags"); + + SetLogEnable(PASSED, FALSE); + SetLogEnable(INFO, TRUE); + SetLogEnable(DEBUG, FALSE); + wait for 0 ns; wait for 0 ns; + + TranscriptOpen; + SetTranscriptMirror(TRUE); + + -- Initialize Burst FIFOs + TxBurstFifo <= NewID("TxBurstFifo", TCID); + RxBurstFifo <= NewID("RxBurstFifo", TCID); + + wait until nReset = '1'; + ClearAlerts; + + WaitForBarrier(TestDone, TIMEOUT); + AlertIf(ProcID, now >= TIMEOUT, "Test finished due to timeout"); + AlertIf(ProcID, GetAffirmCount < 1, "Test is not Self-Checking"); + + EndOfTestReports(ReportAll => TRUE); + std.env.stop; + end process; + + ---------------------------------------------------------------------------- + -- Writer Process - uses Transaction interface to send data + ---------------------------------------------------------------------------- + WriterProc : process + constant ProcID : AlertLogIDType := NewID("WriterProc", TCID); + variable WriteCount : integer := 0; + begin + wait until nReset = '1'; + WaitForClock(TxRec, 2); + + -- Assign BurstFifo to transaction record + TxRec.BurstFifo <= TxBurstFifo; + + -- Verify initial state: FIFO should not be full + AffirmIf(ProcID, full = '0', "Initial: FIFO should not be full"); + AffirmIf(ProcID, estate_wr = "1111", "Initial: estate_wr should be max (1111), got: " & to_string(estate_wr)); + AffirmIf(ProcID, fstate_rd = "0000", "Initial: fstate_rd should be min (0000), got: " & to_string(fstate_rd)); + Log(ProcID, "Initial: full = '" & std_logic'image(full) & "', estate_wr=" & to_string(estate_wr), INFO); + + --------------------------------------------------------------------------- + -- Phase 1: Fill FIFO to full using single Send() operations + --------------------------------------------------------------------------- + Log(ProcID, "Phase 1: Fill to FULL using single Send()", INFO); + + -- Fill with sequential data using individual Send transactions + loop + Send(TxRec, std_logic_vector(to_unsigned(WriteCount, D_BITS))); + WriteCount := WriteCount + 1; + + -- Wait for full signal to update + WaitForClock(TxRec, 1); + + -- Check if FIFO is now full + exit when full = '1'; + end loop; + + -- Verify FIFO reached full state + AffirmIf(ProcID, full = '1', "Phase 1: FIFO should be FULL after single writes"); + -- Verify estate_wr indicates full state (should be at maximum) + AffirmIf(ProcID, estate_wr = "0000", "Phase 3: estate_wr should be max (0000) when full, got: " & to_string(estate_wr)); + AffirmIf(ProcID, fstate_rd = "1111", "Phase 3: fstate_rd should be max (1111) when full, got: " & to_string(fstate_rd)); + Log(ProcID, "Phase 1: Reached FULL after " & integer'image(WriteCount) & " single writes, estate_wr=" & to_string(estate_wr), INFO); + + WaitForBarrier(Phase1Done); + + --------------------------------------------------------------------------- + -- Phase 2: Wait for reader to drain to empty (no writes) + --------------------------------------------------------------------------- + Log(ProcID, "Phase 2: Waiting for reader to drain to empty", INFO); + WaitForBarrier(Phase2Done); + + --------------------------------------------------------------------------- + -- Phase 3: Fill FIFO to full using single Send() operations + --------------------------------------------------------------------------- + Log(ProcID, "Phase 3: Fill to FULL using single Send()", INFO); + + -- Calculate how many words to send to fill (assuming empty after Phase 2) + WriteCount := 0; + + -- Fill with sequential data using individual Send transactions + loop + Send(TxRec, std_logic_vector(to_unsigned(WriteCount, D_BITS))); + WriteCount := WriteCount + 1; + + -- Wait for full signal to update + WaitForClock(TxRec, 1); + + -- Check if FIFO is now full + exit when full = '1'; + end loop; + + -- Verify FIFO reached full state + AffirmIf(ProcID, full = '1', "Phase 3: FIFO should be FULL after single writes"); + -- Verify estate_wr indicates full state (should be at maximum) + AffirmIf(ProcID, estate_wr = "0000", "Phase 3: estate_wr should be max (0000) when full, got: " & to_string(estate_wr)); + AffirmIf(ProcID, fstate_rd = "1111", "Phase 3: fstate_rd should be max (1111) when full, got: " & to_string(fstate_rd)); + + Log(ProcID, "Phase 3: Reached FULL after " & integer'image(WriteCount) & " single writes, estate_wr=" & to_string(estate_wr), INFO); + + WaitForBarrier(Phase3Done); + + --------------------------------------------------------------------------- + -- Phase 4: Wait for reader to drain to empty (no writes) + --------------------------------------------------------------------------- + Log(ProcID, "Phase 4: Waiting for reader to drain to empty", INFO); + WaitForBarrier(Phase4Done); + + Log(ProcID, "Writer complete", INFO); + WaitForBarrier(TestDone); + wait; + end process; + + ---------------------------------------------------------------------------- + -- Reader Process - uses Transaction interface to verify data + ---------------------------------------------------------------------------- + ReaderProc : process + constant ProcID : AlertLogIDType := NewID("ReaderProc", TCID); + variable ReadCount : integer := 0; + begin + wait until nReset = '1'; + WaitForClock(RxRec, 2); + + -- Assign BurstFifo to transaction record + RxRec.BurstFifo <= RxBurstFifo; + + -- Verify initial state: FIFO should be empty (valid = '0') + AffirmIf(ProcID, valid = '0', "Initial: FIFO should be EMPTY (valid = '0')"); + AffirmIf(ProcID, fstate_rd = "0000", "Initial: fstate_rd should be min (0000), got: " & to_string(fstate_rd)); + Log(ProcID, "Initial: valid = '" & std_logic'image(valid) & "', fstate_rd=" & to_string(fstate_rd), INFO); + + --------------------------------------------------------------------------- + -- Phase 1: Wait for writer to fill, verify not empty + --------------------------------------------------------------------------- + Log(ProcID, "Phase 1: Wait for writer to fill FIFO to full", INFO); + WaitForBarrier(Phase1Done); + + -- Verify FIFO is not empty now + AffirmIf(ProcID, valid = '1', "Phase 1: FIFO should not be EMPTY after fill"); + Log(ProcID, "Phase 1: FIFO is not empty, valid = '" & std_logic'image(valid) & "'", INFO); + + --------------------------------------------------------------------------- + -- Phase 2: Drain FIFO to empty using single Check() operations + --------------------------------------------------------------------------- + Log(ProcID, "Phase 2: Drain to EMPTY using single Check()", INFO); + + -- Drain using individual Check transactions until FIFO is empty + ReadCount := 0; + while valid = '1' loop + Check(RxRec, std_logic_vector(to_unsigned(ReadCount, D_BITS))); + ReadCount := ReadCount + 1; + WaitForClock(RxRec, 1); + end loop; + + -- Verify FIFO reached empty state + AffirmIf(ProcID, valid = '0', "Phase 2: FIFO should be EMPTY (valid = '0') after single reads"); + -- Verify fstate_rd indicates empty state (should be at minimum) + AffirmIf(ProcID, fstate_rd = "0000", "Phase 2: fstate_rd should be min (0000) when empty, got: " & to_string(fstate_rd)); + Log(ProcID, "Phase 2: Reached EMPTY after " & integer'image(ReadCount) & " single reads, fstate_rd=" & to_string(fstate_rd), INFO); + + WaitForBarrier(Phase2Done); + + --------------------------------------------------------------------------- + -- Phase 3: Wait for writer to fill with bursts + --------------------------------------------------------------------------- + Log(ProcID, "Phase 3: Wait for writer to fill FIFO with bursts", INFO); + WaitForBarrier(Phase3Done); + + -- Verify FIFO is not empty now + AffirmIf(ProcID, valid = '1', "Phase 3: FIFO should not be EMPTY after burst fill"); + Log(ProcID, "Phase 3: FIFO is not empty, valid = '" & std_logic'image(valid) & "'", INFO); + + --------------------------------------------------------------------------- + -- Phase 4: Drain FIFO to empty using single Check() operations + --------------------------------------------------------------------------- + Log(ProcID, "Phase 4: Drain to EMPTY using single Check()", INFO); + + ReadCount := 0; + while valid = '1' loop + Check(RxRec, std_logic_vector(to_unsigned(ReadCount, D_BITS))); + ReadCount := ReadCount + 1; + WaitForClock(RxRec, 1); + end loop; + + -- Verify FIFO reached empty state + AffirmIf(ProcID, valid = '0', "Phase 4: FIFO should be EMPTY (valid = '0') after single reads"); + -- Verify fstate_rd indicates empty state (should be at minimum) + AffirmIf(ProcID, fstate_rd = "0000", "Phase 4: fstate_rd should be min (0000) when empty, got: " & to_string(fstate_rd)); + Log(ProcID, "Phase 4: Reached EMPTY after " & integer'image(ReadCount) & " single reads, fstate_rd=" & to_string(fstate_rd), INFO); + + WaitForBarrier(Phase4Done); + + Log(ProcID, "Reader complete", INFO); + WaitForBarrier(TestDone); + wait; + end process; + +end architecture; + +-- Configuration for Full/Empty Flags test +configuration fifo_cc_got_FullEmpty_Flags of fifo_cc_got_TestHarness is + for TestHarness + for TestCtrl : fifo_cc_got_TestController + use entity work.fifo_cc_got_TestController(FullEmpty_Flags); + end for; + end for; +end configuration; diff --git a/tb/fifo/fifo_cc_got/fifo_cc_got_Random.vhdl b/tb/fifo/fifo_cc_got/fifo_cc_got_Random.vhdl new file mode 100644 index 000000000..77e0b894d --- /dev/null +++ b/tb/fifo/fifo_cc_got/fifo_cc_got_Random.vhdl @@ -0,0 +1,422 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- ============================================================================= +-- Authors: Gustavo Martin +-- +-- Architecture: fifo_cc_got_Random +-- +-- Description: +-- ------------------------------------- +-- Random stress test for fifo_cc_got using OSVVM Verification Components +-- Uses Transaction interface with randomized operations: +-- - Random single Send/Check vs SendBurst/CheckBurst selection +-- - Random burst sizes (1 to 32 words) +-- - Random delays between operations +-- - TrySend/TryCheck for non-blocking operations when FIFO full/empty +-- - Asynchronous writer/reader processes (no barriers) +-- +-- Coverage Requirements: +-- - Each fill level (0-15) covered multiple times (at least 3x) +-- - All operation types covered +-- - Full and Empty states reached multiple times +-- +-- License: +-- ============================================================================= +-- Copyright 2025-2025 The PoC-Library Authors +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +library osvvm; +context osvvm.OsvvmContext; +use osvvm.ScoreboardPkg_slv.all; + +library osvvm_common; +context osvvm_common.OsvvmCommonContext; +use osvvm_common.FifoFillPkg_slv.all; + +use work.fifo_cc_got_TestController_pkg.all; + +architecture Random of fifo_cc_got_TestController is + -- Test synchronization + signal TestDone : integer_barrier := 1; + signal WriterDone : integer := 0; + signal ReaderDone : integer := 0; + + -- Alert/Log IDs + constant TCID : AlertLogIDType := NewID("FifoCcGotRandom_" & ConfigToString(CONFIG_INDEX)); + + -- Shared Scoreboard for data checking + constant Scoreboard : ScoreboardIdType := NewID("DataScoreboard", TCID); + + -- Functional Coverage + constant FillCov : CoverageIDType := NewID("FillLevelCoverage", TCID); + constant OpCov : CoverageIDType := NewID("OperationCoverage", TCID); + constant FlagCov : CoverageIDType := NewID("FlagCoverage", TCID); + + -- Test parameters + constant MAX_BURST : integer := 32; -- Maximum burst size + constant MAX_OPS : integer := 1000000; -- Safety limit on operations + + constant COV_SEND_ID : integer := 1; + constant COV_CHECK_ID : integer := 2; + constant COV_BURSTOFSINGLES_ID : integer := 3; + constant COV_ACTUALBURST_ID : integer := 4; + + constant COV_EMPTY_ID : integer := 0; + constant COV_NOT_EMPTY_ID : integer := 1; + constant COV_FULL_ID : integer := 2; + constant COV_NOT_FULL_ID : integer := 3; + +begin + ---------------------------------------------------------------------------- + -- Control Process - manages test lifecycle + ---------------------------------------------------------------------------- + ControlProc : process + constant ProcID : AlertLogIDType := NewID("ControlProc", TCID); + constant TIMEOUT : time := 1 sec; + begin + SetTestName("fifo_cc_got_Random"); + + SetLogEnable(PASSED, FALSE); + SetLogEnable(INFO, TRUE); + SetLogEnable(DEBUG, FALSE); + wait for 0 ns; wait for 0 ns; + + TranscriptOpen; + SetTranscriptMirror(TRUE); + + -- Initialize Burst FIFOs + TxBurstFifo <= NewID("TxBurstFifo", TCID); + RxBurstFifo <= NewID("RxBurstFifo", TCID); + + -- Initialize Fill Level Coverage (4-bit state = 0-15) + -- Require at least 20 hits per bin + for i in 0 to 15 loop + AddBins(FillCov, "Fill_" & integer'image(i), 20, GenBin(i)); + end loop; + + -- Initialize Operation Coverage + AddBins(OpCov, "Send", 20, GenBin(COV_SEND_ID)); + AddBins(OpCov, "Check", 20, GenBin(COV_CHECK_ID)); + AddBins(OpCov, "BurstOfSingles", 20, GenBin(COV_BURSTOFSINGLES_ID)); + AddBins(OpCov, "ActualBurst", 20, GenBin(COV_ACTUALBURST_ID)); + + -- Initialize Flag Coverage (require 20+ hits for Full/Empty states) + AddBins(FlagCov, "Empty", 20, GenBin(COV_EMPTY_ID)); + AddBins(FlagCov, "Not_Empty", 20, GenBin(COV_NOT_EMPTY_ID)); + AddBins(FlagCov, "Full", 20, GenBin(COV_FULL_ID)); + AddBins(FlagCov, "Not_Full", 20, GenBin(COV_NOT_FULL_ID)); + + wait until nReset = '1'; + ClearAlerts; + + -- Wait until all coverage goals are met + loop + wait for 1 us; + exit when (IsCovered(FillCov) and IsCovered(OpCov) and IsCovered(FlagCov)) or now >= TIMEOUT; + if now >= TIMEOUT then + Alert(ProcID, "Coverage timeout - not all bins covered", WARNING); + exit; + end if; + exit when WriterDone > 0 and ReaderDone > 0; + end loop; + + WaitForBarrier(TestDone, 10 ms); + AlertIf(ProcID, GetAffirmCount < 1, "Test is not Self-Checking"); + + -- Check coverage goals before reporting + AlertIfNot(ProcID, IsCovered(FillCov), "FillCov: Coverage goals not met"); + AlertIfNot(ProcID, IsCovered(OpCov), "OpCov: Coverage goals not met"); + AlertIfNot(ProcID, IsCovered(FlagCov), "FlagCov: Coverage goals not met"); + + -- Report Coverage results + Log(ProcID, "=== Coverage Reports ===", ALWAYS); + WriteBin(FillCov); + WriteBin(OpCov); + WriteBin(FlagCov); + + EndOfTestReports(ReportAll => TRUE); + std.env.stop; + end process; + + ---------------------------------------------------------------------------- + -- Writer Process - randomized writes using Transaction interface + ---------------------------------------------------------------------------- + WriterProc : process + constant ProcID : AlertLogIDType := NewID("WriterProc", TCID); + variable RV : RandomPType; + variable WriteCount : integer := 0; + variable BurstSize : integer; + variable WaitCycles : integer; + variable UseBurst : boolean; + variable CurrFill : integer; + variable TargetFill : integer; + begin + wait until nReset = '1'; + WaitForClock(TxRec, 2); + + -- Assign local BurstFifo to transaction record + TxRec.BurstFifo <= TxBurstFifo; + + -- Initialize random generator with unique seed + RV.InitSeed(RV'instance_name); + + Log(ProcID, "Starting coverage-driven write operations", INFO); + + while WriteCount < MAX_OPS loop + -- Get current fill level (must match Monitor's coverage tracking) + CurrFill := to_integer(unsigned(fstate_rd)); + + -- Intelligent coverage: get a fill level that needs more hits + TargetFill := GetRandPoint(FillCov); + + -- Adjust delay based on coverage needs: + -- If need lower fill levels, wait longer to let FIFO drain + -- If need higher fill levels, write quickly + if TargetFill < CurrFill then + -- Need to drain - wait longer + WaitCycles := RV.RandInt(50, 100); + elsif TargetFill > CurrFill then + -- Need to fill - write fast + WaitCycles := RV.RandInt(1, 5); + else + -- At target - moderate pace + WaitCycles := RV.RandInt(10, 30); + end if; + + if WaitCycles > 0 then + WaitForClock(TxRec, WaitCycles); + end if; + + -- Stop if all coverage met + exit when IsCovered(FillCov) and IsCovered(OpCov) and IsCovered(FlagCov); + + -- Randomly choose between single, burst of singles, and actual burst + UseBurst := RV.RandInt(0, 99) < 70; -- 70% burst, 30% single + + if UseBurst then + -- Random burst size (2 to MAX_BURST words) + BurstSize := RV.RandInt(2, MAX_BURST); + + -- 50/50 choice between burst of singles vs actual burst + if RV.RandInt(0, 99) < 50 then + -- Burst of singles: loop of individual Send() calls + for i in 0 to BurstSize-1 loop + Push(Scoreboard, std_logic_vector(to_unsigned(WriteCount + i, D_BITS))); + Send(TxRec, std_logic_vector(to_unsigned(WriteCount + i, D_BITS))); + end loop; + WriteCount := WriteCount + BurstSize; + ICover(OpCov, COV_BURSTOFSINGLES_ID); + else + -- Actual burst: use SendBurst() with TxBurstFifo + for i in 0 to BurstSize-1 loop + Push(Scoreboard, std_logic_vector(to_unsigned(WriteCount + i, D_BITS))); + Push(TxBurstFifo, std_logic_vector(to_unsigned(WriteCount + i, D_BITS))); + end loop; + SendBurst(TxRec, BurstSize); + WriteCount := WriteCount + BurstSize; + ICover(OpCov, COV_ACTUALBURST_ID); + end if; + else + -- Single word operation: Push before Send + Push(Scoreboard, std_logic_vector(to_unsigned(WriteCount, D_BITS))); + Send(TxRec, std_logic_vector(to_unsigned(WriteCount, D_BITS))); + WriteCount := WriteCount + 1; + ICover(OpCov, COV_SEND_ID); + end if; + end loop; + + Log(ProcID, "Writer complete - " & integer'image(WriteCount) & " words sent, coverage met", INFO); + WriterDone <= 1; + WaitForBarrier(TestDone); + wait; + end process; + + ---------------------------------------------------------------------------- + -- Reader Process - randomized reads using Transaction interface + ---------------------------------------------------------------------------- + ReaderProc : process + constant ProcID : AlertLogIDType := NewID("ReaderProc", TCID); + variable RV : RandomPType; + variable ReadCount : integer := 0; + variable BurstSize : integer; + variable WaitCycles : integer; + variable UseBurst : boolean; + variable ReadData : std_logic_vector(D_BITS-1 downto 0); + variable CurrFill : integer; + variable TargetFill : integer; + variable ActualBurstSize : integer := 0; + begin + wait until nReset = '1'; + WaitForClock(RxRec, 2); + + -- Assign local BurstFifo to transaction record + RxRec.BurstFifo <= RxBurstFifo; + + -- Initialize random generator with unique seed + RV.InitSeed(RV'instance_name); + + Log(ProcID, "Starting coverage-driven read operations", INFO); + + while ReadCount < MAX_OPS loop + -- Exit only when Writer is done AND Scoreboard is empty + exit when WriterDone > 0 and IsEmpty(Scoreboard); + + -- Skip iteration if Scoreboard is empty (Writer still active, waiting for data) + if IsEmpty(Scoreboard) then + WaitForClock(RxRec, 10); + next; + end if; + + -- Get current fill level (must match Monitor's coverage tracking) + CurrFill := to_integer(unsigned(fstate_rd)); + + -- Intelligent coverage: get a fill level that needs more hits + TargetFill := GetRandPoint(FillCov); + + -- Adjust delay based on coverage needs: + -- If need lower fill levels, read quickly to drain + -- If need higher fill levels, wait to let FIFO fill + if TargetFill < CurrFill then + -- Need to drain - read fast + WaitCycles := RV.RandInt(1, 5); + elsif TargetFill > CurrFill then + -- Need to fill - wait longer + WaitCycles := RV.RandInt(40, 80); + else + -- At target - moderate pace + WaitCycles := RV.RandInt(10, 30); + end if; + + if WaitCycles > 0 then + WaitForClock(RxRec, WaitCycles); + end if; + + -- Randomly choose between single, burst of singles, and actual burst + -- Only do burst if Scoreboard has enough data + UseBurst := RV.RandInt(0, 99) < 70 and not IsEmpty(Scoreboard); -- 70% burst, 30% single + + if UseBurst then + -- Random burst size limited by available data + BurstSize := RV.RandInt(2, minimum(MAX_BURST, 10)); + + -- 50/50 choice between burst of singles vs actual burst + if RV.RandInt(0, 99) < 50 then + -- Burst of singles: loop of individual Get/Check calls + for i in 0 to BurstSize-1 loop + exit when IsEmpty(Scoreboard); + Get(RxRec, ReadData); + Check(Scoreboard, ReadData); + ReadCount := ReadCount + 1; + end loop; + ICover(OpCov, COV_BURSTOFSINGLES_ID); + else + -- Actual burst: use CheckBurst() with RxBurstFifo + -- Transfer expected data from Scoreboard to RxBurstFifo + for i in 0 to BurstSize-1 loop + exit when IsEmpty(Scoreboard); + Push(RxBurstFifo, Pop(Scoreboard)); + ActualBurstSize := ActualBurstSize + 1; + end loop; + -- Now check the burst from FIFO (only if we pushed data) + if ActualBurstSize > 0 then + CheckBurst(RxRec, ActualBurstSize); + ReadCount := ReadCount + ActualBurstSize; + end if; + ICover(OpCov, COV_ACTUALBURST_ID); + ActualBurstSize := 0; + end if; + else + -- Single word operation + Get(RxRec, ReadData); + Check(Scoreboard, ReadData); + ReadCount := ReadCount + 1; + ICover(OpCov, COV_CHECK_ID); + end if; + end loop; + + Log(ProcID, "Reader complete - " & integer'image(ReadCount) & " words verified, Scoreboard empty", INFO); + ReaderDone <= 1; + WaitForBarrier(TestDone); + wait; + end process; + + ---------------------------------------------------------------------------- + -- Monitor Process - samples FIFO state for coverage + ---------------------------------------------------------------------------- + MonitorProc : process + constant ProcID : AlertLogIDType := NewID("MonitorProc", TCID); + variable PrevFull : std_logic := '0'; + variable PrevValid : std_logic := '0'; + variable PrevState : integer := -1; + variable CurrState : integer := 0; + begin + wait until nReset = '1'; + + loop + WaitForClock(Clock); + + -- Sample write-side fill state + CurrState := to_integer(unsigned(fstate_rd)); + + -- Record coverage on state change + if CurrState /= PrevState then + ICover(FillCov, CurrState); + PrevState := CurrState; + end if; + + -- Sample Full flag + if full /= PrevFull then + if full = '1' then + ICover(FlagCov, COV_FULL_ID); + Log(ProcID, "FULL detected", DEBUG); + else + ICover(FlagCov, COV_NOT_FULL_ID); + end if; + PrevFull := full; + end if; + + -- Sample Empty flag (via valid) + if valid /= PrevValid then + if valid = '0' then + ICover(FlagCov, COV_EMPTY_ID); + Log(ProcID, "EMPTY detected", DEBUG); + else + ICover(FlagCov, COV_NOT_EMPTY_ID); + end if; + PrevValid := valid; + end if; + + -- Exit when both writer and reader are done + exit when WriterDone > 0 and ReaderDone > 0; + end loop; + + wait; + end process; + +end architecture; + +-- Configuration for Random test +configuration fifo_cc_got_Random of fifo_cc_got_TestHarness is + for TestHarness + for TestCtrl : fifo_cc_got_TestController + use entity work.fifo_cc_got_TestController(Random); + end for; + end for; +end configuration; diff --git a/tb/fifo/fifo_cc_got/fifo_cc_got_Simple.vhdl b/tb/fifo/fifo_cc_got/fifo_cc_got_Simple.vhdl new file mode 100644 index 000000000..e732e1c22 --- /dev/null +++ b/tb/fifo/fifo_cc_got/fifo_cc_got_Simple.vhdl @@ -0,0 +1,201 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- ============================================================================= +-- Authors: Thomas B. Preusser +-- Gustavo Martin +-- +-- Architecture: fifo_cc_got_Simple +-- +-- Description: +-- ------------------------------------- +-- Simple OSVVM test for fifo_cc_got using Verification Components +-- Uses Transaction interface to communicate with VCs: +-- - Send for writes via TxRec +-- - Check for reads/verification via RxRec +-- +-- Tests only single-word operations (no bursts): +-- - Sequential writes/reads (0 to 63) +-- - More sequential writes/reads (64 to 191) +-- - Random pattern writes/reads (192 to 255) +-- +-- License: +-- ============================================================================= +-- Copyright 2025-2025 The PoC-Library Authors +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +library osvvm; +context osvvm.OsvvmContext; +use osvvm.ScoreboardPkg_slv.all; + +library osvvm_common; +context osvvm_common.OsvvmCommonContext; +use osvvm_common.FifoFillPkg_slv.all; + +use work.fifo_cc_got_TestController_pkg.all; + +architecture Simple of fifo_cc_got_TestController is + -- Test synchronization + signal TestDone : integer_barrier := 1; + signal Phase1Done : integer_barrier := 1; + signal Phase2Done : integer_barrier := 1; + + -- Alert/Log IDs + constant TCID : AlertLogIDType := NewID("FifoCcGotSimple_" & ConfigToString(CONFIG_INDEX)); + +begin + ---------------------------------------------------------------------------- + -- Control Process - manages test lifecycle + ---------------------------------------------------------------------------- + ControlProc : process + constant ProcID : AlertLogIDType := NewID("ControlProc", TCID); + constant TIMEOUT : time := 100 ms; + begin + SetTestName("fifo_cc_got_Simple"); + + SetLogEnable(PASSED, FALSE); + SetLogEnable(INFO, TRUE); + SetLogEnable(DEBUG, FALSE); + wait for 0 ns; wait for 0 ns; + + TranscriptOpen; + SetTranscriptMirror(TRUE); + + wait until nReset = '1'; + ClearAlerts; + + WaitForBarrier(TestDone, TIMEOUT); + AlertIf(ProcID, now >= TIMEOUT, "Test finished due to timeout"); + AlertIf(ProcID, GetAffirmCount < 1, "Test is not Self-Checking"); + + EndOfTestReports(ReportAll => TRUE); + std.env.stop; + end process; + + ---------------------------------------------------------------------------- + -- Writer Process - uses Transaction interface to send data via TxRec + ---------------------------------------------------------------------------- + WriterProc : process + constant ProcID : AlertLogIDType := NewID("WriterProc", TCID); + begin + wait until nReset = '1'; + WaitForClock(TxRec, 2); + + --------------------------------------------------------------------------- + -- Phase 1: Sequential single-word sends (0 to 63) + -- Uses Send() transaction for each word + --------------------------------------------------------------------------- + Log(ProcID, "Phase 1: Sequential single-word writes via Send()", INFO); + for i in 0 to 63 loop + Send(TxRec, std_logic_vector(to_unsigned(i, D_BITS))); + end loop; + + -- Wait for reader to complete Phase 1 + WaitForBarrier(Phase1Done); + + --------------------------------------------------------------------------- + -- Phase 2: Sequential single-word sends (64 to 191) + -- Uses Send() transaction for each word + --------------------------------------------------------------------------- + Log(ProcID, "Phase 2: Sequential single-word writes via Send()", INFO); + for i in 64 to 191 loop + Send(TxRec, std_logic_vector(to_unsigned(i, D_BITS))); + end loop; + + -- Wait for reader to complete Phase 2 + WaitForBarrier(Phase2Done); + + --------------------------------------------------------------------------- + -- Phase 3: Random pattern writes using single Send (192 to 255) + -- Uses RandomParm for random data generation + --------------------------------------------------------------------------- + Log(ProcID, "Phase 3: Random pattern writes via Send()", INFO); + + for i in 192 to 255 loop + -- Generate pseudo-random value based on index for reproducibility + Send(TxRec, std_logic_vector(to_unsigned((i * 37 + 17) mod (2**D_BITS), D_BITS))); + end loop; + + Log(ProcID, "Writer complete - 256 words sent", INFO); + WaitForBarrier(TestDone); + wait; + end process; + + ---------------------------------------------------------------------------- + -- Reader Process - uses Transaction interface to check data via RxRec + ---------------------------------------------------------------------------- + ReaderProc : process + constant ProcID : AlertLogIDType := NewID("ReaderProc", TCID); + variable ReadData : std_logic_vector(D_BITS-1 downto 0); + begin + wait until nReset = '1'; + WaitForClock(RxRec, 2); + + --------------------------------------------------------------------------- + -- Phase 1: Check sequential data (0 to 63) + -- Uses Check() transaction which reads and verifies expected value + --------------------------------------------------------------------------- + Log(ProcID, "Phase 1: Verifying sequential data via Check()", INFO); + for i in 0 to 63 loop + Check(RxRec, std_logic_vector(to_unsigned(i, D_BITS))); + end loop; + + -- Signal writer that Phase 1 read is complete + WaitForBarrier(Phase1Done); + + --------------------------------------------------------------------------- + -- Phase 2: Check sequential data using single Check (64 to 191) + -- Uses Check() transaction which reads and verifies expected value + --------------------------------------------------------------------------- + Log(ProcID, "Phase 2: Verifying sequential data via Check()", INFO); + for i in 64 to 191 loop + Check(RxRec, std_logic_vector(to_unsigned(i, D_BITS))); + end loop; + + -- Signal writer that Phase 2 read is complete + WaitForBarrier(Phase2Done); + + --------------------------------------------------------------------------- + -- Phase 3: Check random data using single Check (192 to 255) + -- Uses same formula as writer for matching sequence + --------------------------------------------------------------------------- + Log(ProcID, "Phase 3: Verifying random data via Check()", INFO); + + for i in 192 to 255 loop + -- Same pseudo-random formula as writer + Check(RxRec, std_logic_vector(to_unsigned((i * 37 + 17) mod (2**D_BITS), D_BITS))); + end loop; + + Log(ProcID, "Reader complete - 256 words verified", INFO); + + -- Signal completion + WaitForBarrier(TestDone); + wait; + end process; + +end architecture; + +-- Configuration for Simple test +configuration fifo_cc_got_Simple of fifo_cc_got_TestHarness is + for TestHarness + for TestCtrl : fifo_cc_got_TestController + use entity work.fifo_cc_got_TestController(Simple); + end for; + end for; +end configuration; diff --git a/tb/fifo/fifo_cc_got/fifo_cc_got_TestController.vhdl b/tb/fifo/fifo_cc_got/fifo_cc_got_TestController.vhdl new file mode 100644 index 000000000..4895846a5 --- /dev/null +++ b/tb/fifo/fifo_cc_got/fifo_cc_got_TestController.vhdl @@ -0,0 +1,68 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- ============================================================================= +-- Authors: Gustavo Martin +-- +-- Entity: fifo_cc_got_TestController +-- +-- Description: +-- ------------------------------------- +-- Test controller entity for fifo_cc_got OSVVM testbench +-- Uses Transaction interfaces to communicate with VCs +-- +-- License: +-- ============================================================================= +-- Copyright 2025-2025 The PoC-Library Authors +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +library osvvm; +context osvvm.OsvvmContext; +use osvvm.ScoreboardPkg_slv.all; + +library osvvm_common; +context osvvm_common.OsvvmCommonContext; + +use work.fifo_cc_got_TestController_pkg.all; + +entity fifo_cc_got_TestController is + generic ( + CONFIG_INDEX : tConfigIndex := 0 + ); + port ( + -- Clock and Reset + Clock : in std_logic; + nReset : in std_logic; + + -- FIFO Status Signals (for direct monitoring) + full : in std_logic; -- Write side status + valid : in std_logic; -- Read side status + estate_wr : in std_logic_vector(3 downto 0); -- Write side fill state + fstate_rd : in std_logic_vector(3 downto 0); -- Read side fill state + + -- Transaction interfaces to VCs (OSVVM Standard) + TxRec : inOut StreamRecType; -- To Transmitter VC + RxRec : inOut StreamRecType -- To Receiver VC + ); + + -- Simplifying access to Burst FIFOs using aliases (OSVVM pattern) + alias TxBurstFifo : ScoreboardIdType is TxRec.BurstFifo; + alias RxBurstFifo : ScoreboardIdType is RxRec.BurstFifo; + +end entity; diff --git a/tb/fifo/fifo_cc_got/fifo_cc_got_TestController_pkg.vhdl b/tb/fifo/fifo_cc_got/fifo_cc_got_TestController_pkg.vhdl new file mode 100644 index 000000000..761eddd00 --- /dev/null +++ b/tb/fifo/fifo_cc_got/fifo_cc_got_TestController_pkg.vhdl @@ -0,0 +1,85 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- ============================================================================= +-- Authors: Gustavo Martin +-- +-- Package: fifo_cc_got_TestController_pkg +-- +-- Description: +-- ------------------------------------- +-- Test controller package for fifo_cc_got OSVVM testbench +-- Defines types and constants for testing FIFO with Common Clock +-- +-- License: +-- ============================================================================= +-- Copyright 2025-2025 The PoC-Library Authors +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +library osvvm; +context osvvm.OsvvmContext; + +package fifo_cc_got_TestController_pkg is + + -- FIFO Configuration Constants + constant D_BITS : positive := 8; + constant MIN_DEPTH : positive := 64; + constant ESTATE_WR_BITS : natural := 4; + constant FSTATE_RD_BITS : natural := 4; + + -- Test Configuration Types + -- Boolean array for DATA_REG, STATE_REG, OUTPUT_REG combinations + type tConfigIndex is range 0 to 7; + + -- Helper functions to decode configuration + function GetDataReg(idx : tConfigIndex) return boolean; + function GetStateReg(idx : tConfigIndex) return boolean; + function GetOutputReg(idx : tConfigIndex) return boolean; + function ConfigToString(idx : tConfigIndex) return string; + + -- Data word type (only used in TestHarness for signal declarations) + subtype tDataWord is std_logic_vector(D_BITS-1 downto 0); + +end package; + +package body fifo_cc_got_TestController_pkg is + + function GetDataReg(idx : tConfigIndex) return boolean is + begin + return (idx mod 2) > 0; + end function; + + function GetStateReg(idx : tConfigIndex) return boolean is + begin + return (idx mod 4) > 1; + end function; + + function GetOutputReg(idx : tConfigIndex) return boolean is + begin + return (idx mod 8) > 3; + end function; + + function ConfigToString(idx : tConfigIndex) return string is + begin + return "DATA_REG=" & boolean'image(GetDataReg(idx)) & + " STATE_REG=" & boolean'image(GetStateReg(idx)) & + " OUTPUT_REG=" & boolean'image(GetOutputReg(idx)); + end function; + +end package body; diff --git a/tb/fifo/fifo_cc_got/fifo_cc_got_TestHarness.vhdl b/tb/fifo/fifo_cc_got/fifo_cc_got_TestHarness.vhdl new file mode 100644 index 000000000..17b96da7c --- /dev/null +++ b/tb/fifo/fifo_cc_got/fifo_cc_got_TestHarness.vhdl @@ -0,0 +1,182 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- ============================================================================= +-- Authors: Gustavo Martin +-- +-- Entity: fifo_cc_got_TestHarness +-- +-- Description: +-- ------------------------------------- +-- Test harness for fifo_cc_got OSVVM testbench +-- Instantiates DUT and Verification Components (Transmitter/Receiver) +-- Connects VCs to TestController via Transaction interfaces +-- +-- License: +-- ============================================================================= +-- Copyright 2025-2025 The PoC-Library Authors +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +library osvvm; +context osvvm.OsvvmContext; + +library osvvm_common; +context osvvm_common.OsvvmCommonContext; + +library PoC; + +use work.fifo_cc_got_TestController_pkg.all; +use work.FifoCcGotComponentPkg.all; + +entity fifo_cc_got_TestHarness is + generic ( + CONFIG_INDEX : tConfigIndex := 0 + ); +end entity; + +architecture TestHarness of fifo_cc_got_TestHarness is + constant TPERIOD_CLOCK : time := 10 ns; + + signal Clock : std_logic := '1'; + signal nReset : std_logic := '0'; -- Active low for VCs + + -- Write interface signals (between VC and DUT) + signal put : std_logic; + signal din : tDataWord; + signal full : std_logic; + signal estate_wr : std_logic_vector(ESTATE_WR_BITS-1 downto 0); + + -- Read interface signals (between VC and DUT) + signal got : std_logic; + signal dout : tDataWord; + signal valid : std_logic; + signal fstate_rd : std_logic_vector(FSTATE_RD_BITS-1 downto 0); + + -- Transaction interfaces (between VCs and TestController) + signal TxRec : StreamRecType(DataToModel(D_BITS-1 downto 0), DataFromModel(D_BITS-1 downto 0), ParamToModel(0 downto 0), ParamFromModel(0 downto 0)); + signal RxRec : StreamRecType(DataToModel(D_BITS-1 downto 0), DataFromModel(D_BITS-1 downto 0), ParamToModel(0 downto 0), ParamFromModel(0 downto 0)); + + -- Test Controller component declaration + component fifo_cc_got_TestController is + generic ( + CONFIG_INDEX : tConfigIndex := 0 + ); + port ( + Clock : in std_logic; + nReset : in std_logic; + full : in std_logic; + valid : in std_logic; + estate_wr : in std_logic_vector(3 downto 0); + fstate_rd : in std_logic_vector(3 downto 0); + TxRec : inOut StreamRecType; + RxRec : inOut StreamRecType + ); + end component; + +begin + -- Clock generation + Osvvm.ClockResetPkg.CreateClock( + Clk => Clock, + Period => TPERIOD_CLOCK + ); + + -- Reset generation (active low for VCs) + Osvvm.ClockResetPkg.CreateReset( + Reset => nReset, + ResetActive => '0', + Clk => Clock, + Period => 5 * TPERIOD_CLOCK, + tpd => 0 ns + ); + + -- DUT instantiation + DUT : entity PoC.fifo_cc_got + generic map ( + D_BITS => D_BITS, + MIN_DEPTH => MIN_DEPTH, + DATA_REG => GetDataReg(CONFIG_INDEX), + STATE_REG => GetStateReg(CONFIG_INDEX), + OUTPUT_REG => GetOutputReg(CONFIG_INDEX), + ESTATE_WR_BITS => ESTATE_WR_BITS, + FSTATE_RD_BITS => FSTATE_RD_BITS + ) + port map ( + rst => not nReset, -- DUT uses active-high reset + clk => Clock, + put => put, + din => din, + full => full, + estate_wr => estate_wr, + got => got, + dout => dout, + valid => valid, + fstate_rd => fstate_rd + ); + + -- Transmitter VC instantiation (Write side) + Transmitter_VC : FifoCcGotTransmitter + generic map ( + MODEL_ID_NAME => "FifoTx", + DATA_WIDTH => D_BITS, + ESTATE_WIDTH => ESTATE_WR_BITS + ) + port map ( + Clk => Clock, + nReset => nReset, + put => put, + din => din, + full => full, + estate_wr => estate_wr, + TransRec => TxRec + ); + + -- Receiver VC instantiation (Read side) + Receiver_VC : FifoCcGotReceiver + generic map ( + MODEL_ID_NAME => "FifoRx", + DATA_WIDTH => D_BITS, + FSTATE_WIDTH => FSTATE_RD_BITS + ) + port map ( + Clk => Clock, + nReset => nReset, + got => got, + dout => dout, + valid => valid, + fstate_rd => fstate_rd, + TransRec => RxRec + ); + + -- Test Controller instantiation + TestCtrl : component fifo_cc_got_TestController + generic map ( + CONFIG_INDEX => CONFIG_INDEX + ) + port map ( + Clock => Clock, + nReset => nReset, + full => full, + valid => valid, + estate_wr => estate_wr, + fstate_rd => fstate_rd, + TxRec => TxRec, + RxRec => RxRec + ); + +end architecture; diff --git a/tb/fifo/fifo_cc_got_tb.vhdl b/tb/fifo/fifo_cc_got_tb.vhdl deleted file mode 100644 index f14c7da2e..000000000 --- a/tb/fifo/fifo_cc_got_tb.vhdl +++ /dev/null @@ -1,163 +0,0 @@ --- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- --- vim: tabstop=2:shiftwidth=2:noexpandtab --- kate: tab-width 2; replace-tabs off; indent-width 2; --- --- ============================================================================ --- Authors: Thomas B. Preusser --- --- Testbench: Testbench for a FIFO with Common Clock (cc) and Pipelined Interface --- --- Description: --- ------------------------------------ --- TODO --- --- --- License: --- ============================================================================ --- Copyright 2007-2016 Technische Universitaet Dresden - Germany, --- Chair of VLSI-Design, Diagnostics and Architecture --- --- Licensed under the Apache License, Version 2.0 (the "License"); --- you may not use this file except in compliance with the License. --- You may obtain a copy of the License at --- --- http://www.apache.org/licenses/LICENSE-2.0 --- --- Unless required by applicable law or agreed to in writing, software --- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --- See the License for the specific language governing permissions and --- limitations under the License. --- ============================================================================ - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -library PoC; -use PoC.utils.all; -use PoC.physical.all; --- simulation only packages -use PoC.sim_types.all; -use PoC.simulation.all; -use PoC.waveform.all; - - -entity fifo_cc_got_tb is -end entity; - - -architecture tb of fifo_cc_got_tb is - constant CLOCK_FREQ : FREQ := 100 MHz; - - -- component generics - constant D_BITS : positive := 8; - constant MIN_DEPTH : positive := 30; - constant ESTATE_WR_BITS : natural := 2; - constant FSTATE_RD_BITS : natural := 2; - - -- Clock Control - signal rst : std_logic; - signal clk : std_logic; - -begin - -- initialize global simulation status - simInitialize; - -- generate global testbench clock - simGenerateClock(clk, CLOCK_FREQ); - simGenerateWaveform(rst, simGenerateWaveform_Reset(Pause => 10 ns, ResetPulse => 10 ns)); - - genDUTs: for c in 0 to 7 generate - constant DATA_REG : boolean := c mod 2 > 0; - constant STATE_REG : boolean := c mod 4 > 1; - constant OUTPUT_REG : boolean := c mod 8 > 3; - - constant simTestID : T_SIM_TEST_ID := simCreateTest("Test setup for DATA_REG=" & boolean'image(DATA_REG) & " STATE_REG=" & BOOLEAN'image(STATE_REG) & " OUTPUT_REG=" & boolean'image(OUTPUT_REG)); - - -- Local Component Ports - signal put : std_logic; - signal din : std_logic_vector(D_BITS-1 downto 0); - signal full : std_logic; - signal estate_wr : std_logic_vector(ESTATE_WR_BITS - 1 downto 0); - signal got : std_logic; - signal dout : std_logic_vector(D_BITS-1 downto 0); - signal valid : std_logic; - signal fstate_rd : std_logic_vector(FSTATE_RD_BITS - 1 downto 0); - - begin - - DUT : entity PoC.fifo_cc_got - generic map ( - D_BITS => D_BITS, - MIN_DEPTH => MIN_DEPTH, - STATE_REG => STATE_REG, - DATA_REG => DATA_REG, - OUTPUT_REG => OUTPUT_REG, - ESTATE_WR_BITS => ESTATE_WR_BITS, - FSTATE_RD_BITS => FSTATE_RD_BITS - ) - port map ( - rst => rst, - clk => clk, - put => put, - din => din, - full => full, - estate_wr => estate_wr, - got => got, - dout => dout, - valid => valid, - fstate_rd => fstate_rd - ); - - -- Writer - procWriter : process - constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "Writer for DATA_REG=" & boolean'image(DATA_REG) & " STATE_REG=" & BOOLEAN'image(STATE_REG) & " OUTPUT_REG=" & boolean'image(OUTPUT_REG)); - begin - din <= (others => '-'); - put <= '0'; - wait until rising_edge(clk) and rst = '0'; - - for i in 0 to 2**(D_BITS-1)-1 loop - din <= std_logic_vector(to_unsigned(i, D_BITS)); - put <= '1'; - wait until rising_edge(clk) and full = '0'; - end loop; - - for i in 2**(D_BITS-1) to 2**D_BITS-1 loop - din <= (others => '-'); - put <= '0'; - wait until rising_edge(clk) and valid = '0'; - din <= std_logic_vector(to_unsigned(i, D_BITS)); - put <= '1'; - wait until rising_edge(clk); - end loop; - - din <= (others => '-'); - put <= '0'; - - -- This process is finished - simDeactivateProcess(simProcessID); - wait; -- forever - end process; - - -- Reader - procReader : process - constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess(simTestID, "Reader for DATA_REG=" & boolean'image(DATA_REG) & " STATE_REG=" & BOOLEAN'image(STATE_REG) & " OUTPUT_REG=" & boolean'image(OUTPUT_REG)); - begin - got <= '0'; - for i in 0 to 2**D_BITS-1 loop - wait until rising_edge(clk) and valid = '1'; - simAssertion((dout = std_logic_vector(to_unsigned(i, D_BITS))), "Output failure in configuration " & integer'image(c) & " @ Pos " & INTEGER'image(i)); - got <= '1'; - wait until rising_edge(clk); - got <= '0'; - wait until rising_edge(clk); - end loop; - - -- This process is finished - simDeactivateProcess(simProcessID); - simFinalizeTest(simTestID); - wait; -- forever - end process; - end generate genDUTs; -end architecture; From 124465b0670ff453e449000e33b41c8e62f61590 Mon Sep 17 00:00:00 2001 From: Gustavo Martin Date: Mon, 22 Dec 2025 19:35:29 +0100 Subject: [PATCH 2/3] PR fixes --- tb/arith/div/arith_div_Simple.vhdl | 8 ++++---- tb/fifo/fifo_cc_got/fifo_cc_got_Burst.vhdl | 2 ++ tb/fifo/fifo_cc_got/fifo_cc_got_FullEmpty_Flags.vhdl | 2 ++ tb/fifo/fifo_cc_got/fifo_cc_got_Simple.vhdl | 2 ++ 4 files changed, 10 insertions(+), 4 deletions(-) diff --git a/tb/arith/div/arith_div_Simple.vhdl b/tb/arith/div/arith_div_Simple.vhdl index 9badc6fe7..13a8ff1a1 100644 --- a/tb/arith/div/arith_div_Simple.vhdl +++ b/tb/arith/div/arith_div_Simple.vhdl @@ -100,8 +100,8 @@ begin WaitForClock(Clock); wait for 1 ns; Start <= '0'; - A <= (others => '-'); - D <= (others => '-'); + A <= (A'range => 'U'); + D <= (D'range => 'U'); done := (others => false); loop @@ -136,8 +136,8 @@ begin begin Start <= '0'; - A <= (others => '-'); - D <= (others => '-'); + A <= (A'range => 'U'); + D <= (D'range => 'U'); -- Initialize Random Random.InitSeed(Random'instance_name); diff --git a/tb/fifo/fifo_cc_got/fifo_cc_got_Burst.vhdl b/tb/fifo/fifo_cc_got/fifo_cc_got_Burst.vhdl index f356d7163..ba528b8a7 100644 --- a/tb/fifo/fifo_cc_got/fifo_cc_got_Burst.vhdl +++ b/tb/fifo/fifo_cc_got/fifo_cc_got_Burst.vhdl @@ -23,6 +23,8 @@ -- License: -- ============================================================================= -- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2007-2016 Technische Universitaet Dresden - Germany +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/fifo/fifo_cc_got/fifo_cc_got_FullEmpty_Flags.vhdl b/tb/fifo/fifo_cc_got/fifo_cc_got_FullEmpty_Flags.vhdl index 224b627d0..a373dc1b1 100644 --- a/tb/fifo/fifo_cc_got/fifo_cc_got_FullEmpty_Flags.vhdl +++ b/tb/fifo/fifo_cc_got/fifo_cc_got_FullEmpty_Flags.vhdl @@ -24,6 +24,8 @@ -- License: -- ============================================================================= -- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2007-2016 Technische Universitaet Dresden - Germany +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. diff --git a/tb/fifo/fifo_cc_got/fifo_cc_got_Simple.vhdl b/tb/fifo/fifo_cc_got/fifo_cc_got_Simple.vhdl index e732e1c22..e87b3612b 100644 --- a/tb/fifo/fifo_cc_got/fifo_cc_got_Simple.vhdl +++ b/tb/fifo/fifo_cc_got/fifo_cc_got_Simple.vhdl @@ -22,6 +22,8 @@ -- License: -- ============================================================================= -- Copyright 2025-2025 The PoC-Library Authors +-- Copyright 2007-2016 Technische Universitaet Dresden - Germany +-- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. From 14e56bfb291ec8e9abcf084720834b3b467fd91f Mon Sep 17 00:00:00 2001 From: Gustavo Martin Date: Mon, 22 Dec 2025 20:17:33 +0100 Subject: [PATCH 3/3] Fix NVC simulation --- tb/fifo/fifo_cc_got/fifo_cc_got_TestController_pkg.vhdl | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tb/fifo/fifo_cc_got/fifo_cc_got_TestController_pkg.vhdl b/tb/fifo/fifo_cc_got/fifo_cc_got_TestController_pkg.vhdl index 761eddd00..13daeac08 100644 --- a/tb/fifo/fifo_cc_got/fifo_cc_got_TestController_pkg.vhdl +++ b/tb/fifo/fifo_cc_got/fifo_cc_got_TestController_pkg.vhdl @@ -62,17 +62,17 @@ package body fifo_cc_got_TestController_pkg is function GetDataReg(idx : tConfigIndex) return boolean is begin - return (idx mod 2) > 0; + return (integer(idx) mod 2) > 0; end function; function GetStateReg(idx : tConfigIndex) return boolean is begin - return (idx mod 4) > 1; + return (integer(idx) mod 4) > 1; end function; function GetOutputReg(idx : tConfigIndex) return boolean is begin - return (idx mod 8) > 3; + return (integer(idx) mod 8) > 3; end function; function ConfigToString(idx : tConfigIndex) return string is