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2 changes: 1 addition & 1 deletion tb/RunAllTests.pro
Original file line number Diff line number Diff line change
Expand Up @@ -25,7 +25,7 @@ include ./sync/RunAllTests.pro
#include ./cache/RunAllTests.pro
#include ./common/RunAllTests.pro
#include ./dstruct/RunAllTests.pro
#include ./fifo/RunAllTests.pro
include ./fifo/RunAllTests.pro
#include ./io/RunAllTests.pro
#include ./mem/RunAllTests.pro
#include ./misc/RunAllTests.pro
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8 changes: 4 additions & 4 deletions tb/arith/div/arith_div_Simple.vhdl
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This file is not related to this PR topic. But I was getting an error when doing a regression test with GHDL. I dont understand why this didnt show up in previous PRs.

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Do you have an older GHDL and/or NVC?

This was a bug in older revisions in both tools. It should be fixed. Any you need to compile using -frelaxed.

Original file line number Diff line number Diff line change
Expand Up @@ -100,8 +100,8 @@ begin
WaitForClock(Clock);
wait for 1 ns;
Start <= '0';
A <= (others => '-');
D <= (others => '-');
A <= (A'range => 'U');
D <= (D'range => 'U');
done := (others => false);

loop
Expand Down Expand Up @@ -136,8 +136,8 @@ begin

begin
Start <= '0';
A <= (others => '-');
D <= (others => '-');
A <= (A'range => 'U');
D <= (D'range => 'U');

-- Initialize Random
Random.InitSeed(Random'instance_name);
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35 changes: 35 additions & 0 deletions tb/fifo/RunAllTests.pro
Original file line number Diff line number Diff line change
@@ -0,0 +1,35 @@
# =============================================================================
# Authors:
# Gustavo Martin
#
# Description:
# RunAllTests.pro for PoC.fifo OSVVM testbench suite
#
# License:
# =============================================================================
# Copyright 2025-2025 The PoC-Library Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
# =============================================================================

# FIFO with Common Clock (cc), pipelined interface
include ./fifo_cc_got/RunAllTests.pro

# FIFO with Common Clock (cc), temporary put with commit/rollback
# include ./fifo_cc_got_tempput/RunAllTests.pro

# # FIFO with Independent Clocks (ic), address-based stream assembly
# include ./fifo_ic_assembly/RunAllTests.pro

# # FIFO with Independent Clocks (ic), first-word-fall-through
# include ./fifo_ic_got/RunAllTests.pro
95 changes: 95 additions & 0 deletions tb/fifo/fifo_cc_got/FifoCcGotComponentPkg.vhdl
Original file line number Diff line number Diff line change
@@ -0,0 +1,95 @@
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- Authors: Gustavo Martin
--
-- Package: FifoCcGotComponentPkg
--
-- Description:
-- -------------------------------------
-- Component declarations for FIFO CC Got Verification Components
-- Uses OSVVM's standard StreamRecType for transaction interfaces
--
-- License:
-- =============================================================================
-- Copyright 2025-2025 The PoC-Library Authors
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================

library IEEE;
use IEEE.std_logic_1164.all;

library osvvm;
context osvvm.OsvvmContext;

library osvvm_common;
context osvvm_common.OsvvmCommonContext;

package FifoCcGotComponentPkg is

------------------------------------------------------------
-- FifoCcGotTransmitter - Write side VC
------------------------------------------------------------
component FifoCcGotTransmitter is
generic (
MODEL_ID_NAME : string := "";
DATA_WIDTH : integer := 8;
ESTATE_WIDTH : integer := 2;
tpd_Clk_put : time := 2 ns;
tpd_Clk_din : time := 2 ns
);
port (
-- Global Signals
Clk : in std_logic;
nReset : in std_logic;

-- FIFO Write Interface
put : out std_logic;
din : out std_logic_vector(DATA_WIDTH-1 downto 0);
full : in std_logic;
estate_wr : in std_logic_vector(ESTATE_WIDTH-1 downto 0);

-- Transaction Interface (OSVVM Standard)
TransRec : inOut StreamRecType
);
end component FifoCcGotTransmitter;

------------------------------------------------------------
-- FifoCcGotReceiver - Read side VC
------------------------------------------------------------
component FifoCcGotReceiver is
generic (
MODEL_ID_NAME : string := "";
DATA_WIDTH : integer := 8;
FSTATE_WIDTH : integer := 2;
tpd_Clk_got : time := 2 ns
);
port (
-- Global Signals
Clk : in std_logic;
nReset : in std_logic;

-- FIFO Read Interface
got : out std_logic;
dout : in std_logic_vector(DATA_WIDTH-1 downto 0);
valid : in std_logic;
fstate_rd : in std_logic_vector(FSTATE_WIDTH-1 downto 0);

-- Transaction Interface (OSVVM Standard)
TransRec : inOut StreamRecType
);
end component FifoCcGotReceiver;

end package FifoCcGotComponentPkg;
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