From 4adfc4e6ed661d8d105a4ade5aa211dc3e99ae1b Mon Sep 17 00:00:00 2001 From: Datawallet Investment <53367049+DatawalletInvestment@users.noreply.github.com> Date: Fri, 20 May 2022 10:06:25 +0800 Subject: [PATCH] Update and rename catalog_2017.1.json to catalog_2018.3.json updata catalog for 2018.3 --- ...atalog_2017.1.json => catalog_2018.3.json} | 848 +++++++++--------- 1 file changed, 445 insertions(+), 403 deletions(-) rename catalog/{catalog_2017.1.json => catalog_2018.3.json} (71%) diff --git a/catalog/catalog_2017.1.json b/catalog/catalog_2018.3.json similarity index 71% rename from catalog/catalog_2017.1.json rename to catalog/catalog_2018.3.json index 3924eee8b..92748e85f 100644 --- a/catalog/catalog_2017.1.json +++ b/catalog/catalog_2018.3.json @@ -1,5 +1,5 @@ { - "name": "apps", + "name": "sdaccel_examples", "displayName": "", "description": "", "categories": [ @@ -11,7 +11,7 @@ "examples": [ { "name": "kmeans", - "commit_id": "76f75048dd359ef028b528a7c4b405bd77831e4e", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This is OpenCL Based K-Means clustering Implementation for Xilinx FPGA ", "Devices. K-means clustering is a method of vector quantization, that ", @@ -43,34 +43,20 @@ "\t -o : output cluster center coordinates [default=off]" ], "displayName": "K-Means", - "version": "1.0", "author": "Xilinx" }, { "name": "nearest_neighbor_linear_search", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This is an optimized implementation of a nearest neighbor linear search algorithm targeting execution on a SDAccel supported FPGA acceleration card." ], "displayName": "Nearest Neighbor Linear Search", - "version": "3.0", - "author": "Xilinx" - }, - { - "name": "prng", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", - "description": [ - "This is an optimized implementation of the pseudo random number generator algorithm", - "The method used to generate a random number sequence is called complementary multiply with carry (CMWC)", - "targeting exection on an SDAccel support FPGA acceleration card" - ], - "displayName": "pseudo random number generator", - "version": "1.0", "author": "Xilinx" }, { "name": "smithwaterman", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This is an optimized implementation of the smithwaterman algorithm targeting exection on an SDAccel support FPGA acceleration card.", "", @@ -80,7 +66,6 @@ "2. Systolic array implementation" ], "displayName": "Smithwaterman Genetic Sequencing Demo", - "version": "3.0", "author": "Xilinx" } ] @@ -110,22 +95,21 @@ "categories": [], "examples": [ { - "name": "critical_path_ocl", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "name": "critical_path_c", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This example shows a normal coding style which could lead to critical path issue and design will give degraded timing. Example also contains better coding style which can improve design timing." ], - "displayName": "Critical Path(CL)", + "displayName": "Critical Path (C)", "key_concepts": [ "Critical Path handling", "Improve Timing" ], - "version": "1.0", "author": "Xilinx" }, { "name": "large_loop_c", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This is a CNN (Convolutional Neural Network) based example which mainly focuses on Convolution operation of a CNN network. The goal of this example is to demonstrate a method to overcome kernel design timing failure issue. It also presents the effectiveness of using multiple compute units to improve performance." ], @@ -140,12 +124,11 @@ "Multiple Compute Units", "Convolutional Neural Networks" ], - "version": "1.0", "author": "Xilinx" }, { "name": "large_loop_ocl", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This is a CNN (Convolutional Neural Network) based example which mainly focuses on Convolution operation of a CNN network. The goal of this example is to demonstrate a method to overcome kernel design timing failure issue. It also presents the effectiveness of using multiple compute units to improve performance." ], @@ -160,12 +143,11 @@ "Multiple Compute Units", "Convolutional Neural Networks" ], - "version": "1.0", "author": "Xilinx" }, { "name": "split_kernel_c", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This is a multi-filter image processing application to showcase effectiveness of Dataflow/Streams usage. This examples is intended to help developers to break down the complex kernels into multiple sub-functions using HLS Dataflow/Streams. It presents a way to concurrently execute multiple functions with better area utilization compared to a complex single kernel implementation. The main objective of this example is to showcase a way to build a optimal FPGA design which achieves maximum frequency with optimal resource utilization and achieves better performance compared to single complex kernel implementations." ], @@ -181,12 +163,11 @@ "Dataflow", "Stream" ], - "version": "1.0", "author": "Xilinx" }, { "name": "split_kernel_ocl", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This is a multi-filter image processing application to showcase effectiveness of Dataflow/Streams usage. This examples is intended to help developers to break down the complex kernel into multiple sub-functions using OpenCL Dataflow. It presents a way to concurrently execute multiple functions with better area utilization compared to a complex single kernel implementation. The main objective of this example is to showcase a way to build a optimal FPGA design which achieves maximum frequency with optimal resource utilization and achieves better performance compared to single kernel implementations." ], @@ -200,12 +181,11 @@ "Dataflow", "Stream" ], - "version": "1.0", "author": "Xilinx" }, { "name": "too_many_cu_c", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This is simple example of vector addition to demonstrate effectiveness of using single compute unit with heavy work load to achieve better performance. Bad example uses multiple compute units to achieve good performance but it results in heavy usage of FPGA resources and area due to which design fails timing. Good example uses single compute unit to compute with heavier work load, it helps in less resource utilization and also helps in kernel scalability. To switch between Good/Bad cases use the flag provided in makefile." ], @@ -219,12 +199,11 @@ "Data Level Parallelism", "Multiple Compute Units" ], - "version": "1.0", "author": "Xilinx" }, { "name": "too_many_cu_ocl", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This is simple example of vector addition to demonstrate effectiveness of using single compute unit with heavy work load to achieve better performance. Bad example uses multiple compute units to achieve good performance but it results in heavy usage of FPGA resources and area due to which design fails timing. Good example uses single compute unit to compute with heavier work load, it helps in less resource utilization and also helps in kernel scalability. To switch between Good/Bad cases use the flag provided in makefile." ], @@ -238,7 +217,6 @@ "Data Level Parallelism", "Multiple Compute Units" ], - "version": "1.0", "author": "Xilinx" } ] @@ -246,7 +224,7 @@ { "name": "cpu_to_fpga", "displayName": [ - "CPU_to_FPGA Examples" + "CPU to FPGA Examples" ], "description": [ "Labs to showcase the cpu to fpga conversion with kernel optimizations." @@ -255,72 +233,67 @@ "examples": [ { "name": "00_cpu", - "commit_id": "76f75048dd359ef028b528a7c4b405bd77831e4e", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This is a simple example of matrix multiplication (Row x Col)." ], - "displayName": "Matrix Multiplication", - "version": "1.0", + "displayName": "00 Matrix Multiplication", "author": "Xilinx" }, { - "name": "01_ocl", - "commit_id": "76f75048dd359ef028b528a7c4b405bd77831e4e", + "name": "01_kernel_c", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ - "This is a simple example of OpenCL matrix multiplication (Row x Col)." + "This is a simple example of HLS matrix multiplication (Row x Col)." ], - "displayName": "Matrix Multiplication with OpenCL Kernel", + "displayName": "01 Matrix Multiplication with OpenCL Kernel", "key_concepts": [ "OpenCL APIs" ], - "version": "1.0", "author": "Xilinx" }, { - "name": "02_lmem_ocl", - "commit_id": "76f75048dd359ef028b528a7c4b405bd77831e4e", + "name": "02_local_mem_c", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This is a simple example of matrix multiplication (Row x Col) to demonstrate how to reduce number of memory accesses using local memory." ], - "displayName": "Matrix Multiplication with Local Memory", + "displayName": "02 Matrix Multiplication with Local Memory", "key_concepts": [ "Kernel Optimization", "Local Memory" ], - "version": "1.0", "author": "Xilinx" }, { - "name": "03_burst_rw_ocl", - "commit_id": "76f75048dd359ef028b528a7c4b405bd77831e4e", + "name": "03_burst_rw_c", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This is a simple example of matrix multiplication (Row x Col) to demonstrate how to achieve better pipeline with burst read and write to/from local memory from/to DDR." ], - "displayName": "Matrix Multiplication Burst Read Write", + "displayName": "03 Matrix Multiplication Burst Read Write", "key_concepts": [ "Kernel Optimization", "Burst Read/Write" ], - "version": "1.0", "author": "Xilinx" }, { - "name": "04_partition_ocl", - "commit_id": "76f75048dd359ef028b528a7c4b405bd77831e4e", + "name": "04_partition_c", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This is a simple example of matrix multiplication (Row x Col) to demonstrate how to achieve better performance by array partitioning and loop unrolling." ], - "displayName": "Matrix Multiplication Array Partition and Loop Unroll", + "displayName": "04 Matrix Multiplication Array Partition and Loop Unroll", "keywords": [ - "xcl_pipeline_loop", - "xcl_array_partition(complete, dim)", - "opencl_unroll_hint" + "pragma HLS PIPELINE", + "pragma HLS ARRAY_PARTITION complete", + "pragma HLS UNROLL" ], "key_concepts": [ "Array Partition", "Loop Unroll" ], - "version": "1.0", "author": "Xilinx" } ] @@ -337,7 +310,7 @@ "examples": [ { "name": "dataflow_func_ocl", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This is simple example of vector addition to demonstrate Dataflow functionality in OpenCL Kernel. OpenCL Dataflow allows user to run multiple functions together to achieve higher throughput." ], @@ -349,29 +322,11 @@ "key_concepts": [ "Function/Task Level Parallelism" ], - "version": "1.0", - "author": "Xilinx" - }, - { - "name": "dataflow_loop_c", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", - "description": [ - "This is simple example of vector addition to demonstrate Loops Dataflow functionality of HLS. HLS Dataflow allows user to schedule multiple sequential loops concurrently to achieve higher throughput." - ], - "displayName": "Loops Dataflow Using HLS Stream(C)", - "keywords": [ - "dataflow", - "hls::stream<>" - ], - "key_concepts": [ - "Loop Dataflow" - ], - "version": "1.0", "author": "Xilinx" }, { "name": "dataflow_pipes_ocl", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This is simple example of vector addition to demonstrate OpenCL Pipe Memory usage. OpenCL PIPE memory functionality allows user to achieve kernel-to-kernel data transfer without using global memory." ], @@ -386,12 +341,11 @@ "Dataflow", "kernel to kernel pipes" ], - "version": "1.0", "author": "Xilinx" }, { "name": "dataflow_stream_array_c", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This is simple example of Multiple Stages Vector Addition to demonstrate Array of Stream usage in HLS C Kernel Code." ], @@ -403,12 +357,11 @@ "key_concepts": [ "Array of Stream" ], - "version": "1.0", "author": "Xilinx" }, { "name": "dataflow_stream_c", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This is simple example of vector addition to demonstrate Dataflow functionality of HLS. HLS Dataflow allows user to schedule multiple task together to achieve higher throughput." ], @@ -420,7 +373,22 @@ "key_concepts": [ "Task Level Parallelism" ], - "version": "1.0", + "author": "Xilinx" + }, + { + "name": "dataflow_subfunc_ocl", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", + "description": [ + "This is simple example of vector addition to demonstrate how OpenCL Dataflow allows user to run multiple sub functions together to achieve higher throughput." + ], + "displayName": "Dataflow SubFunction OpenCL(CL)", + "keywords": [ + "xcl_dataflow", + "xclDataflowFifoDepth" + ], + "key_concepts": [ + "SubFunction Level Parallelism" + ], "author": "Xilinx" } ] @@ -437,7 +405,7 @@ "examples": [ { "name": "debug_printf_ocl", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This is simple example of vector addition and printing of data that is computational result (addition). It is based on vectored addition that demonstrates printing of work item data (integer product in this case)" ], @@ -449,21 +417,63 @@ "key_concepts": [ "Use of print statements for debugging" ], - "version": "1.0", "author": "Xilinx" }, { - "name": "debug_profile_ocl", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "name": "debug_profile_c", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This is simple example of vector addition and printing profile data (wall clock time taken between start and stop). It also dump a waveform file which can be reloaded to vivado to see the waveform. Run command 'vivado -source ./scripts/open_waveform.tcl -tclargs -...wdb' to launch waveform viewer. User can also update batch to gui in sdaccel.ini file to see the live waveform while running application." ], - "displayName": " Printing Profile Data and Dumping Waveform file (CL)", + "displayName": " Printing Profile Data and Dumping Waveform file (C)", "key_concepts": [ "Use of Profile API", "Waveform Dumping and loading" ], - "version": "1.0", + "author": "Xilinx" + } + ] + }, + { + "name": "hello_world", + "displayName": [ + "Hello World Examples" + ], + "description": [ + "Hello World examples for new users" + ], + "categories": [], + "examples": [ + { + "name": "helloworld_c", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", + "description": [ + "This is simple example of vector addition to describe how to use HLS kernels in Sdx Environment. This example highlights the concepts like PIPELINE which increases the kernel performance " + ], + "displayName": "Hello World (HLS C/C++ Kernel)", + "keywords": [ + "gmem", + "bundle", + "#pragma HLS INTERFACE", + "m_axi", + "s_axi4lite" + ], + "key_concepts": [ + "HLS C Kernel", + "OpenCL Host APIs" + ], + "author": "Xilinx" + }, + { + "name": "helloworld_ocl", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", + "description": [ + "This example is a simple OpenCL application. It will highlight the basic flow of an OpenCL application." + ], + "displayName": "Hello World (CL)", + "key_concepts": [ + "OpenCL API" + ], "author": "Xilinx" } ] @@ -479,12 +489,12 @@ "categories": [], "examples": [ { - "name": "concurrent_kernel_execution_ocl", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "name": "concurrent_kernel_execution_c", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This example will demonstrate how to use multiple and out of order command queues to simultaneously execute multiple kernels on an FPGA." ], - "displayName": "Concurrent Kernel Execution (CL)", + "displayName": "Concurrent Kernel Execution (C)", "keywords": [ "CL_QUEUE_OUT_OF_ORDER_EXEC_MODE_ENABLE", "clSetEventCallback()" @@ -494,37 +504,36 @@ "Out of Order Command Queues", "Multiple Command Queues" ], - "version": "1.0", "author": "Xilinx" }, { - "name": "copy_buffer_ocl", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "name": "copy_buffer_c", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This Copy Buffer example demonstrate how one buffer can be copied from another buffer." ], - "displayName": "Copy Buffer (CL)", + "displayName": "Copy Buffer (C)", "keywords": [ "cl::CommandQueue::enqueueCopyBuffer()" ], "key_concepts": [ "Copy Buffer" ], - "version": "1.0", "author": "Xilinx" }, { - "name": "data_transfer_ocl", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "name": "data_transfer_c", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This example illustrates several ways to use the OpenCL API to transfer data to and from the FPGA" ], - "displayName": "Data Transfer (CL)", + "displayName": "Data Transfer (C)", "keywords": [ - "clEnqueueWriteBuffer()", - "clEnqueueReadBuffer()", - "clEnqueueMapBuffer()", - "clEnqueueUnmapMemObject()" + "enqueueWriteBuffer()", + "enqueueReadBuffer()", + "enqueueMapBuffer()", + "enqueueUnmapMemObject()", + "enqueueMigrateMemObjects()" ], "key_concepts": [ "OpenCL API", @@ -534,16 +543,15 @@ "Map Buffers", "Async Memcpy" ], - "version": "1.0", "author": "Xilinx" }, { - "name": "device_query_ocl", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "name": "device_query_c", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This example prints the OpenCL properties of the platform and its devices. It also displays the limits and capabilities of the hardware." ], - "displayName": "Device Query (CL)", + "displayName": "Device Query (C)", "keywords": [ "clGetPlatformIDs()", "clGetPlatformInfo()", @@ -554,16 +562,28 @@ "OpenCL API", "Querying device properties" ], - "version": "1.0", "author": "Xilinx" }, { - "name": "errors_ocl", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "name": "device_query_cpp", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", + "description": [ + "This Example prints the OpenCL properties of the platform and its devices using OpenCL CPP APIs. It also displays the limits and capabilities of the hardware." + ], + "displayName": "Device Query (CPP)", + "key_concepts": [ + "OpenCL API", + "Querying device properties" + ], + "author": "Xilinx" + }, + { + "name": "errors_c", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This example discuss the different reasons for errors in OpenCL and how to handle them at runtime." ], - "displayName": "Error Handling (CL)", + "displayName": "Error Handling (C)", "keywords": [ "CL_SUCCESS", "CL_DEVICE_NOT_FOUND", @@ -573,48 +593,98 @@ "OpenCL API", "Error handling" ], - "version": "1.0", "author": "Xilinx" }, { - "name": "helloworld_ocl", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "name": "errors_cpp", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ - "This example is a simple OpenCL application. It will highlight the basic flow of an OpenCL application." + "This example discuss the different reasons for errors in OpenCL C++ and how to handle them at runtime." + ], + "displayName": "Error Handling (CPP)", + "keywords": [ + "CL_SUCCESS", + "CL_DEVICE_NOT_FOUND", + "CL_DEVICE_NOT_AVAILABLE", + "CL_INVALID_VALUE", + "CL_INVALID_KERNEL_NAME", + "CL_INVALID_BUFFER_SIZE" ], - "displayName": "Hello World (CL)", "key_concepts": [ - "OpenCL API" + "OpenCL C++ API", + "Error handling" + ], + "author": "Xilinx" + }, + { + "name": "hbm_bandwidth", + "commit_id": "2ea0641ef1c5ff6a2d1ddc44c021f22b8a081f13", + "description": [ + "This is a HBM bandwidth check design. Design contains 8 compute units of a kernel which has access to all HBM banks (0:31). Host application allocate buffer into all HBM banks and run these 8 compute units concurrently and measure the overall bandwidth between Kernel and HBM Memory." ], - "version": "1.0", + "displayName": "HBM Bandwidth", "author": "Xilinx" }, { - "name": "kernel_swap_ocl", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "name": "hbm_simple", + "commit_id": "2ea0641ef1c5ff6a2d1ddc44c021f22b8a081f13", "description": [ - "This example shows how host can swap the kernels and share same buffer between two kernels exist in separate binary containers. For Non-XPR(Extended Partial Reconfiguration) Specific Devices, device memory can persist buffer data so both kernels can share data directly. Whereas in XPR devices, device memory does not persist the buffer data so host has to migrate data from device to host memory before swapping the next kernel. After kernel swap, host has to migrate the buffer back to device." + "This is a simple example of vector addition to describe how to use HLS kernels with HBM (High Bandwidth Memory) for achieving high throughput." ], - "displayName": "Vector Add - Vector Multiplication for XPR-NON_XPR Devices", + "displayName": "HBM Simple Vector Addition", + "keywords": [ + "HBM", + "XCL_MEM_TOPOLOGY", + "cl_mem_ext_ptr_t" + ], + "key_concepts": [ + "High Bandwidth Memory", + "Multiple HBM Banks" + ], + "author": "Xilinx" + }, + { + "name": "host_global_bandwidth", + "commit_id": "2ea0641ef1c5ff6a2d1ddc44c021f22b8a081f13", + "description": [ + "Host to global memory bandwidth test" + ], + "displayName": "host_global", + "author": "Xilinx" + }, + { + "name": "host_global_bandwidth_5.0_shell", + "commit_id": "2ea0641ef1c5ff6a2d1ddc44c021f22b8a081f13", + "description": [ + "Host to global memory bandwidth test for 5.0 shell" + ], + "displayName": "host_global_5.0_shell", + "author": "Xilinx" + }, + { + "name": "kernel_swap_c", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", + "description": [ + "This example shows how host can swap the kernels and share same buffer between two kernels which are exist in separate binary containers. Dynamic platforms does not persist the buffer data so host has to migrate data from device to host memory before swapping the next kernel. After kernel swap, host has to migrate the buffer back to device." + ], + "displayName": "Vector Add - Vector Multiplication for XPR Devices", "keywords": [ "clEnqueueMigrateMemObjects()", "CL_MIGRATE_MEM_OBJECT_HOST" ], "key_concepts": [ - "Handling Buffer sharing across multiple binaries for XPR-NON_XPR Platform", - "Multiple Kernel Binaries", - "Buffer sharing across Multiple binaries" + "Handling Buffer sharing across multiple binaries", + "Multiple Kernel Binaries" ], - "version": "1.0", "author": "Xilinx" }, { - "name": "multiple_devices_ocl", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "name": "multiple_devices_c", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This example show how to take advantage of multiple FPGAs on a system. It will show how to initialized an OpenCL context, allocate memory on the two devices and execute a kernel on each FPGA." ], - "displayName": "Multiple FPGA Devices Execution Concurrently (CL)", + "displayName": "Multiple FPGA Devices Execution Concurrently (C)", "keywords": [ "cl_device_id", "clGetDeviceIDs()" @@ -624,16 +694,35 @@ "Multi-FPGA Execution", "Event Handling" ], - "version": "1.0", "author": "Xilinx" }, { - "name": "overlap_ocl", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "name": "multiple_process_c", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", + "description": [ + "This example will demonstrate how to run multiple processes to utilize multiple kernels simultaneously on an FPGA device. Multiple processes can share access to the same device provided each process uses the same xclbin. Processes share access to all device resources but there is no support for exclusive access to resources by any process." + ], + "displayName": "Multiple Process (C)", + "keywords": [ + "PID", + "fork", + "XCL_MULTIPROCESS_MODE", + "multiprocess" + ], + "key_concepts": [ + "Concurrent execution", + "Multiple HLS kernels", + "Multiple Process Support" + ], + "author": "Xilinx" + }, + { + "name": "overlap_c", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This examples demonstrates techniques that allow user to overlap Host(CPU) and FPGA computation in an application. It will cover asynchronous operations and event object." ], - "displayName": "Overlap Host and OpenCL kernels (CL)", + "displayName": "Overlap Host and HLS kernels (C)", "keywords": [ "cl_event", "clCreateCommandQueue", @@ -647,18 +736,17 @@ "Events", "Asynchronous memcpy" ], - "version": "1.0", "author": "Xilinx" }, { - "name": "stream_access_ocl", - "commit_id": "a921ac7e938cdf68692ea4622332a2db0e2620aa", + "name": "stream_access_c", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This is a simple example that demonstrates on how to process an input stream of data for computation in an application. It shows how to perform asynchronous operations and event handling." ], - "displayName": "Stream Access (CL)", + "displayName": "Stream Access (C)", "keywords": [ - "cl_event", + "cl::event", "CL_QUEUE_OUT_OF_ORDER_EXEC_MODE_ENABLE" ], "key_concepts": [ @@ -668,7 +756,23 @@ "Events", "Asynchronous Data Transfer" ], - "version": "1.0", + "author": "Xilinx" + }, + { + "name": "sub_devices_c", + "commit_id": "2ea0641ef1c5ff6a2d1ddc44c021f22b8a081f13", + "description": [ + "This example demonstrates how to create OpenCL subdevices which uses a single kernel multiple times in order to show how to handle each instance independently including independent buffers, command queues and sequencing." + ], + "displayName": "Sub Devices (C)", + "keywords": [ + "cl_device_partition_property", + "createSubDevices", + "CL_DEVICE_PARTITION_EQUALLY" + ], + "key_concepts": [ + "Sub Devices" + ], "author": "Xilinx" } ] @@ -684,22 +788,39 @@ "categories": [], "examples": [ { - "name": "aos_vs_soa_ocl", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "name": "aos_vs_soa_c", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This example demonstrates how data layout can impact the performance of certain kernels. The example we will demonstrate how using the Structure of Array data layout can impact certain data parallel problems." ], - "displayName": "Array of Structure(AoS) vs Structure of Arrays(SoA) (CL)", + "displayName": "Array of Structure(AoS) vs Structure of Arrays(SoA) (C)", "key_concepts": [ "Kernel Optimization", "Data Layout" ], - "version": "1.0", + "author": "Xilinx" + }, + { + "name": "array_partition_c", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", + "description": [ + "This is a simple example of matrix multiplication (Row x Col) to demonstrate how to achieve better performance by array partitioning, using HLS kernel in SDx Environment." + ], + "displayName": "Array Partition (HLS C/C++ Kernel)", + "keywords": [ + "#pragma HLS ARRAY_PARTITION", + "complete" + ], + "key_concepts": [ + "Kernel Optimization", + "HLS C Kernel", + "Array Partition" + ], "author": "Xilinx" }, { "name": "array_partition_ocl", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This example shows how to use array partitioning to improve performance of a kernel" ], @@ -712,29 +833,28 @@ "Kernel Optimization", "Array Partitioning" ], - "version": "1.0", "author": "Xilinx" }, { "name": "dependence_inter_c", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ - "This Example to demonstrate HLS pragma 'DEPENDENCE'. Using 'DEPENDENCE' pragma, user can provide additional dependency details to compiler which allow compiler to perform unrolling/pipelining to get better performance." + "This Example demonstrates the HLS pragma 'DEPENDENCE'.Using 'DEPENDENCE' pragma, user can provide additional dependency details to the compiler by specifying if the dependency in consecutive loop iterations on buffer is true/false, which allows the compiler to perform unrolling/pipelining to get better performance." ], "displayName": "Loop Iteration Dependency (C)", "keywords": [ "DEPENDENCE", - "inter" + "inter", + "WAR" ], "key_concepts": [ "Inter Dependence" ], - "version": "1.0", "author": "Xilinx" }, { "name": "lmem_2rw_c", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This is simple example of vector addition to demonstrate how to utilized both ports of Local Memory memory." ], @@ -747,12 +867,11 @@ "2port BRAM Utilization", "two read/write Local Memory" ], - "version": "1.0", "author": "Xilinx" }, { "name": "lmem_2rw_ocl", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This is simple example of vector addition to demonstrate how to utilized both ports of Local Memory." ], @@ -765,12 +884,11 @@ "2port BRAM Utilization", "two read/write Local Memory" ], - "version": "1.0", "author": "Xilinx" }, { "name": "loop_fusion_c", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This example will demonstrate how to fuse two loops into one to improve the performance of an OpenCL C/C++ Kernel." ], @@ -783,12 +901,11 @@ "Loop Fusion", "Loop Pipelining" ], - "version": "1.0", "author": "Xilinx" }, { "name": "loop_fusion_ocl", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This example will demonstrate how to fuse two loops into one to improve the performance of an OpenCL kernel." ], @@ -801,49 +918,27 @@ "Loop Fusion", "Loop Pipelining" ], - "version": "1.0", - "author": "Xilinx" - }, - { - "name": "loop_perfect_c", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", - "description": [ - "This nearest neighbor example is to demonstrate how to achieve better performance using perfect loop." - ], - "displayName": "Improve performance using loop perfect (C)", - "version": "1.0", - "author": "Xilinx" - }, - { - "name": "loop_perfect_ocl", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", - "description": [ - "This nearest neighbor example is to demonstrate how to achieve better performance using loop perfect." - ], - "displayName": "Improve performance using loop perfect (CL)", - "version": "1.0", "author": "Xilinx" }, { - "name": "loop_pipeline_ocl", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "name": "loop_pipeline_c", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This example demonstrates how loop pipelining can be used to improve the performance of a kernel." ], - "displayName": "Loop Pipelining (CL)", + "displayName": "Loop Pipelining (C)", "keywords": [ - "xcl_pipeline_loop" + "pragma HLS PIPELINE" ], "key_concepts": [ "Kernel Optimization", "Loop Pipelining" ], - "version": "1.0", "author": "Xilinx" }, { "name": "loop_reorder_c", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This is a simple example of matrix multiplication (Row x Col) to demonstrate how to achieve better pipeline II factor by loop reordering." ], @@ -856,12 +951,11 @@ "Kernel Optimization", "Loop reorder to improve II" ], - "version": "1.0", "author": "Xilinx" }, { "name": "loop_reorder_ocl", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This is a simple example of matrix multiplication (Row x Col) to demonstrate how to achieve better pipeline II factor by loop reordering." ], @@ -874,12 +968,11 @@ "Kernel Optimization", "Loop reorder to improve II" ], - "version": "1.0", "author": "Xilinx" }, { "name": "partition_cyclicblock_c", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This example shows how to use array block and cyclic partitioning to improve performance of a kernel" ], @@ -897,12 +990,11 @@ "Block Partition", "Cyclic Partition" ], - "version": "1.0", "author": "Xilinx" }, { "name": "partition_cyclicblock_ocl", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This example shows how to use array block and cyclic partitioning to improve performance of a kernel" ], @@ -918,12 +1010,11 @@ "Block Partition", "Cyclic Partition" ], - "version": "1.0", "author": "Xilinx" }, { "name": "shift_register_c", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This example demonstrates how to shift values in registers in each clock cycle" ], @@ -936,45 +1027,76 @@ "Shift Register", "FIR" ], - "version": "1.0", "author": "Xilinx" }, { "name": "shift_register_ocl", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This example demonstrates how to shift values in registers in each clock cycle" ], "displayName": "Shift Register (CL)", "keywords": [ - "xcl_array_partition" + "xcl_array_partition", + "getprofilingInfo()" ], "key_concepts": [ "Kernel Optimization", "Shift Register", "FIR" ], - "version": "1.0", + "author": "Xilinx" + }, + { + "name": "sum_scan_ocl", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", + "description": [ + "This is a simple example to explain the usage of pipeline and array partitioning for designing parallel prefix sum " + ], + "displayName": "Parallel Prefix Sum (CL)", + "keywords": [ + "xcl_array_partition", + "xcl_pipeline_loop" + ], + "key_concepts": [ + "Kernel Optimization", + "Array Partitioning", + "Pipeline" + ], "author": "Xilinx" }, { "name": "systolic_array_c", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This is a simple example of matrix multiplication (Row x Col) to help developers learn systolic array based algorithm design. Note : Systolic array based algorithm design is well suited for FPGA." ], "displayName": "Systolic Array Implementation (C)", - "version": "1.0", "author": "Xilinx" }, { "name": "systolic_array_ocl", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This is a simple example of matrix multiplication (Row x Col) to help developers learn systolic array based algorithm design. Note: Systolic array based algorithm design is well suited for FPGA." ], "displayName": "Systolic Array Implementation (CL)", - "version": "1.0", + "author": "Xilinx" + }, + { + "name": "vectorization_memorycoalescing_ocl", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", + "description": [ + "This example is a simple OpenCL application which highlights the vectorization concept. It provides a basis for calculating the bandwidth utilization when the compiler looking to vectorize." + ], + "displayName": "Vectorization (CL)", + "keywords": [ + "vec_type_hint" + ], + "key_concepts": [ + "Vectorization", + "Memory Coalescing" + ], "author": "Xilinx" } ] @@ -991,36 +1113,40 @@ "examples": [ { "name": "burst_rw_c", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This is simple example of using AXI4-master interface for burst read and write" ], "displayName": "Burst Read/Write (C)", "keywords": [ - "memcpy" + "memcpy", + "max_read_burst_length", + "max_write_burst_length" ], "key_concepts": [ "burst access" ], - "version": "1.0", "author": "Xilinx" }, { "name": "burst_rw_ocl", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This is simple example of using AXI4-master interface for burst read and write" ], "displayName": "Burst Read/Write (CL)", + "keywords": [ + "param:compiler.interfaceWrBurstLen", + "param:compiler.interfaceRdBurstLen" + ], "key_concepts": [ "burst access" ], - "version": "1.0", "author": "Xilinx" }, { "name": "custom_datatype_c", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This is simple example of RGB to HSV conversion to demonstrate Custom DATA Type usages in C Based Kernel. Xilinx HLS Compiler Supports Custom Data Type to use for operation as well as Memory Interface between Kernel and Global Memory." ], @@ -1033,29 +1159,11 @@ "key_concepts": [ "Custom Datatype" ], - "version": "1.0", - "author": "Xilinx" - }, - { - "name": "custom_datatype_ocl", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", - "description": [ - "This is simple example of RGB to HSV conversion to demonstrate Custom DATA Type usages in OpenCL Based Kernel. Xilinx HLS Compiler Supports Custom Data Type to use for operation as well as Memory Interface between Kernel and Global Memory." - ], - "displayName": "Custom Data Type (CL)", - "keywords": [ - "struct" - ], - "key_concepts": [ - "Dataflow", - "Custom Datatype" - ], - "version": "1.0", "author": "Xilinx" }, { "name": "full_array_2d_c", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This is a simple example of accessing full data from 2d array" ], @@ -1063,12 +1171,11 @@ "key_concepts": [ "2D data full array Access" ], - "version": "1.0", "author": "Xilinx" }, { "name": "full_array_2d_ocl", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This is a simple example of accessing full data from 2d array" ], @@ -1076,12 +1183,11 @@ "key_concepts": [ "2D data full array Access" ], - "version": "1.0", "author": "Xilinx" }, { "name": "gmem_2banks_c", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "commit_id": "2ea0641ef1c5ff6a2d1ddc44c021f22b8a081f13", "description": [ "This example of 2ddr to demonstrate on how to use 2ddr DSA. How to create buffers in each DDR." ], @@ -1089,44 +1195,74 @@ "keywords": [ "max_memory_ports", "misc:map_connect", - "cl_mem_ext_ptr_t", - "XCL_MEM_DDR_BANK0", - "XCL_MEM_DDR_BANK1", - "XCL_MEM_DDR_BANKx", - "CL_MEM_EXT_PTR_XILINX", "HLS Interface m_axi bundle" ], "key_concepts": [ "Multiple Banks" ], - "version": "1.0", + "author": "Xilinx" + }, + { + "name": "gmem_2banks_c_5.0_shell", + "commit_id": "2ea0641ef1c5ff6a2d1ddc44c021f22b8a081f13", + "description": [ + "This example of 2ddr to demonstrate on how to use 2ddr DSA. How to create buffers in each DDR." + ], + "displayName": "Global Memory Two Banks (C) for 5.0 shell", + "keywords": [ + "max_memory_ports", + "misc:map_connect", + "HLS Interface m_axi bundle" + ], + "key_concepts": [ + "Multiple Banks" + ], "author": "Xilinx" }, { "name": "gmem_2banks_ocl", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "commit_id": "2ea0641ef1c5ff6a2d1ddc44c021f22b8a081f13", "description": [ "This example of 2ddr to demonstrate on how to use 2ddr DSA. How to create buffers in each DDR." ], "displayName": "Global Memory Two Banks (CL)", "keywords": [ "max_memory_ports", - "misc:map_connect", - "cl_mem_ext_ptr_t", - "XCL_MEM_DDR_BANK0", - "XCL_MEM_DDR_BANK1", - "XCL_MEM_DDR_BANKx", - "CL_MEM_EXT_PTR_XILINX" + "misc:map_connect" ], "key_concepts": [ "Multiple Banks" ], - "version": "1.0", + "author": "Xilinx" + }, + { + "name": "gmem_2banks_ocl_5.0_shell", + "commit_id": "2ea0641ef1c5ff6a2d1ddc44c021f22b8a081f13", + "description": [ + "This example of 2ddr to demonstrate on how to use 2ddr DSA. How to create buffers in each DDR." + ], + "displayName": "Global Memory Two Banks (CL) for 5.0 shell", + "keywords": [ + "max_memory_ports", + "misc:map_connect" + ], + "key_concepts": [ + "Multiple Banks" + ], + "author": "Xilinx" + }, + { + "name": "kernel_global_bandwidth", + "commit_id": "2ea0641ef1c5ff6a2d1ddc44c021f22b8a081f13", + "description": [ + "Bandwidth test of global to local memory." + ], + "displayName": "kernel_global", "author": "Xilinx" }, { "name": "memcoalesce_hang_c", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This example shows Memory Coalesce Deadlock/Hand situation and how to handle it. User can switch between BAD and GOOD case using makefile variable KFLOW." ], @@ -1141,12 +1277,27 @@ "Memory Deadlock/Hang", "Multiple Interfaces" ], - "version": "1.0", + "author": "Xilinx" + }, + { + "name": "plram_access_c", + "commit_id": "2ea0641ef1c5ff6a2d1ddc44c021f22b8a081f13", + "description": [ + "This example shows the usage of PLRAM and how to use it with simple matrix multiplication (Row x Col)." + ], + "displayName": "PLRAM access (C)", + "keywords": [ + "PLRAM" + ], + "key_concepts": [ + "SDx Memory Hierarchy", + "PLRAMs" + ], "author": "Xilinx" }, { "name": "row_array_2d_c", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This is a simple example of accessing each row of data from 2d array" ], @@ -1157,12 +1308,11 @@ "key_concepts": [ "Row of 2D data array access" ], - "version": "1.0", "author": "Xilinx" }, { "name": "row_array_2d_ocl", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This is a simple example of accessing each row of data from 2d array" ], @@ -1174,12 +1324,26 @@ "key_concepts": [ "Row of 2D data array access" ], - "version": "1.0", + "author": "Xilinx" + }, + { + "name": "slr_assign", + "commit_id": "2ea0641ef1c5ff6a2d1ddc44c021f22b8a081f13", + "description": [ + "This is simple example to describe SLR assignment information for a platform design. This example highlights how to provide extra input to assign the logic of the kernel into a nominated SLR. In this example we are assigning first kernel(Vector Multiplication) to SLR0 and assigning the second kernel(Vector Addition) to SLR1" + ], + "displayName": "SLR Assign (CL)", + "keywords": [ + "slr" + ], + "key_concepts": [ + "SLR Assignments" + ], "author": "Xilinx" }, { "name": "wide_mem_rw_c", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This is simple example of vector addition to demonstrate Wide Memory Access using ap_uint<512> data type. Based on input argument type, xocc compiler will figure our the memory datawidth between Global Memory and Kernel. For this example, ap_uint<512> datatype is used, so Memory datawidth will be 16 x (integer bit size) = 16 x 32 = 512 bit." ], @@ -1193,12 +1357,11 @@ "wide memory access", "burst read and write" ], - "version": "1.0", "author": "Xilinx" }, { "name": "wide_mem_rw_ocl", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This is simple example of vector addition to demonstrate Wide Memory Access using uint16 data type. Based on input argument type, xocc compiler will figure our the memory datawidth between Global Memory and Kernel. For this example, uint16 datatype is used, so Memory datawidth will be 16 x (integer bit size) = 16 x 32 = 512 bit." ], @@ -1212,12 +1375,11 @@ "wide memory access", "burst read and write" ], - "version": "1.0", "author": "Xilinx" }, { "name": "window_array_2d_c", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This is a simple example of accessing each window of data from 2d array" ], @@ -1230,87 +1392,6 @@ "key_concepts": [ "window of 2D data array access" ], - "version": "1.0", - "author": "Xilinx" - }, - { - "name": "window_array_2d_ocl", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", - "description": [ - "This is a simple example of accessing each window of data from 2d array" - ], - "displayName": "Read/Write Window of 2D Array (CL)", - "keywords": [ - "pipe", - "xcl_pipeline_loop", - "xcl_reqd_pipe_depth" - ], - "key_concepts": [ - "window/tile of 2D data array access" - ], - "version": "1.0", - "author": "Xilinx" - } - ] - }, - { - "name": "misc", - "displayName": [ - "Miscellaneous Examples" - ], - "description": [ - "OpenCL miscellaneous Examples" - ], - "categories": [], - "examples": [ - { - "name": "host_global_bandwidth", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", - "description": [ - "Host to global memory bandwidth test" - ], - "displayName": "host_global", - "version": "3.0", - "author": "Xilinx" - }, - { - "name": "kernel_global_bandwidth", - "commit_id": "e502a7e079b456f91effca52141fca89b62c619e", - "description": [ - "Bandwidth test of global to local memory." - ], - "displayName": "kernel_global", - "version": "3.0", - "author": "Xilinx" - }, - { - "name": "sum_scan", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", - "description": [ - "Example of parallel prefix sum" - ], - "displayName": "Parallel Prefix Sum", - "version": "2.0", - "author": "Xilinx" - }, - { - "name": "vadd", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", - "description": [ - "Simple example of vector addition." - ], - "displayName": "Vector Addition", - "version": "3.0", - "author": "Xilinx" - }, - { - "name": "vdotprod", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", - "description": [ - "Simple example of vector dot-product." - ], - "displayName": "Vector Dot-Product", - "version": "3.0", "author": "Xilinx" } ] @@ -1318,54 +1399,6 @@ ], "examples": [] }, - { - "name": "security", - "displayName": "", - "description": "", - "categories": [], - "examples": [ - { - "name": "aes_decrypt", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", - "description": [ - "Implementation of an AES-128 ECB Encrypt in software, followed by decryption written in OpenCL and targeting execution on an SDAccel supported FPGA acceleration card." - ], - "displayName": "AES Decryption", - "version": "3.0", - "author": "Xilinx" - }, - { - "name": "rsa", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", - "description": [ - "This is an implementation of a RSA Decryption algorithm targeting execution on an SDAccel supported FPGA acceleration card." - ], - "displayName": "RSA Decryption Example", - "version": "2.0", - "author": "Xilinx" - }, - { - "name": "sha1", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", - "description": [ - "This is an optimized implementation of SHA1 secure hash algorithm targeting execution on an SDAccel supported FPGA acceleration card." - ], - "displayName": "SHA1", - "version": "3.0", - "author": "Xilinx" - }, - { - "name": "tiny_encryption", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", - "description": [ - "implementation of the tiny encryption algorithm." - ], - "displayName": "Tiny Encryption", - "version": "3.0", - "author": "Xilinx" - } - ] - }, { "name": "vision", "displayName": "", @@ -1374,87 +1407,96 @@ "examples": [ { "name": "affine", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "Affine transformation is a linear mapping method that preserves points, straight lines, and planes. Sets of parallel lines remain parallel after an affine transformation. The affine transformation technique is typically used to correct for geometric distortions or deformations that occur with non-ideal camera angles. The demo performs a 30 degree X rotation and a 50% X and Y scaling on a 512 by 512, 16 bits per pixels grayscale, raw MRI image." ], "displayName": "Affine", - "version": "2.0", "author": "Wakahara Project" }, { "name": "convolve", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "The convolve example is a performant design which showcases convolutional image filtering. The example processes the image 8 pixels at a time." ], "displayName": "Convolve", - "version": "3.0", "author": "Xilinx" }, { "name": "edge_detection", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "Implementation of a Sobel Filter for edge detection." ], "displayName": "Edge Detection", - "version": "3.0", "author": "Xilinx" }, { "name": "histogram_eq", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This is an optimized implementation of a 12-bit histogram equalizer targeting execution on an SDAccel supported FPGA acceleration card." ], "displayName": "Histogram Equalization", - "version": "3.0", "author": "Xilinx" }, { "name": "huffman_codec", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This is an implementation of a huffman encoding/decoding algorithm targeting execution on an SDAccel supported FPGA acceleration card." ], "displayName": "Huffman Encoding/Decoding", - "version": "3.0", "author": "Xilinx" }, { "name": "idct", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "commit_id": "2ea0641ef1c5ff6a2d1ddc44c021f22b8a081f13", "description": [ - "Example of processing Inverse Discrete Cosine Transfom on multiple blocks of data." + "Example shows an optimized Inverse Discrete Cosine Transfom. Optimizations are applied to the kernel as well as the host code." ], "displayName": "Inverse Discrete Cosine Transform", - "version": "1.0", + "author": "Xilinx" + }, + { + "name": "idct_5.0_shell", + "commit_id": "2ea0641ef1c5ff6a2d1ddc44c021f22b8a081f13", + "description": [ + "Example shows an optimized Inverse Discrete Cosine Transfom. Optimizations are applied to the kernel as well as the host code." + ], + "displayName": "Inverse Discrete Cosine Transform for 5.0 shell", "author": "Xilinx" }, { "name": "median_filter", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "commit_id": "4679ad762c22f4acd541efca41562bdc3b9e4035", "description": [ "This is an optimized implementation of a median filter being used to remove noise in images targeting execution on an SDAccel supported FPGA acceleration card." ], "displayName": "Median Filter", - "version": "3.0", "author": "Xilinx" }, { "name": "watermarking", - "commit_id": "5d6b726d4a1735660e8bdef776dc7ab63f429174", + "commit_id": "2ea0641ef1c5ff6a2d1ddc44c021f22b8a081f13", "description": [ "This is an optimized implementation of a watermarking application to add watermarking to images targeting execution on an SDAccel supported FPGA acceleration card." ], "displayName": "Watermarking", - "version": "4.0", + "author": "Xilinx" + }, + { + "name": "watermarking_5.0_shell", + "commit_id": "2ea0641ef1c5ff6a2d1ddc44c021f22b8a081f13", + "description": [ + "This is an optimized implementation of a watermarking application to add watermarking to images targeting execution on an SDAccel supported FPGA acceleration card." + ], + "displayName": "Watermarking for 5.0 shell", "author": "Xilinx" } ] } ], "examples": [], - "branch": "2017.1" -} + "branch": "2018.3"