From ec5a52f5c3bb2b14a092646285bcc3669599abf9 Mon Sep 17 00:00:00 2001 From: AndrDragomir Date: Thu, 13 Nov 2025 16:00:30 +0200 Subject: [PATCH 1/2] projects/adrv9026: Upgrade design - Improved configurability by changing the lane mapping to work with any number of lanes and adding TPL_DATA_WIDTH build parameter for cases where F needs to be changed. - Improved timing on DMA - Changed the JESD204B NLS use case to enable all RX channels Signed-off-by: AndrDragomir --- projects/adrv9026/common/adrv9026_bd.tcl | 55 +++++++++++++-------- projects/adrv9026/common/adrv9026_fmc.txt | 24 ++++----- projects/adrv9026/vcu118/system_constr.xdc | 16 +++--- projects/adrv9026/vcu118/system_project.tcl | 6 ++- projects/adrv9026/vcu118/system_top.v | 24 ++++----- projects/adrv9026/zcu102/system_constr.xdc | 16 +++--- projects/adrv9026/zcu102/system_project.tcl | 6 ++- projects/adrv9026/zcu102/system_top.v | 24 ++++----- 8 files changed, 97 insertions(+), 74 deletions(-) diff --git a/projects/adrv9026/common/adrv9026_bd.tcl b/projects/adrv9026/common/adrv9026_bd.tcl index 8e664b18ede..5c178951342 100644 --- a/projects/adrv9026/common/adrv9026_bd.tcl +++ b/projects/adrv9026/common/adrv9026_bd.tcl @@ -38,13 +38,20 @@ if {$JESD_MODE == "8B10B"} { set ENCODER_SEL 2 } +set TX_TPL_WIDTH [ expr { [info exists ad_project_params(TX_TPL_WIDTH)] \ + ? $ad_project_params(TX_TPL_WIDTH) : {} } ] +set RX_TPL_WIDTH [ expr { [info exists ad_project_params(RX_TPL_WIDTH)] \ + ? $ad_project_params(RX_TPL_WIDTH) : {} } ] +set RX_OS_TPL_WIDTH [ expr { [info exists ad_project_params(RX_OS_TPL_WIDTH)] \ + ? $ad_project_params(RX_OS_TPL_WIDTH) : {} } ] + # TX parameters set TX_NUM_OF_LANES [expr $TX_JESD_L * $TX_NUM_LINKS] ; # L set TX_NUM_OF_CONVERTERS [expr $TX_JESD_M * $TX_NUM_LINKS] ; # M set TX_SAMPLES_PER_FRAME $ad_project_params(TX_JESD_S) ; # S set TX_SAMPLE_WIDTH $TX_JESD_NP ; # N/NP -set TX_DATAPATH_WIDTH [adi_jesd204_calc_tpl_width $DATAPATH_WIDTH $TX_NUM_OF_LANES $TX_NUM_OF_CONVERTERS $TX_SAMPLES_PER_FRAME $TX_SAMPLE_WIDTH] +set TX_DATAPATH_WIDTH [adi_jesd204_calc_tpl_width $DATAPATH_WIDTH $TX_NUM_OF_LANES $TX_NUM_OF_CONVERTERS $TX_SAMPLES_PER_FRAME $TX_SAMPLE_WIDTH $TX_TPL_WIDTH] set TX_SAMPLES_PER_CHANNEL [expr $TX_NUM_OF_LANES * 8 * $TX_DATAPATH_WIDTH / ($TX_NUM_OF_CONVERTERS * $TX_SAMPLE_WIDTH)] # RX parameters @@ -53,9 +60,8 @@ set RX_NUM_OF_CONVERTERS [expr $RX_JESD_M * $RX_NUM_LINKS] ; # M set RX_SAMPLES_PER_FRAME $ad_project_params(RX_JESD_S) ; # S set RX_SAMPLE_WIDTH $RX_JESD_NP ; # N/NP -set RX_OCTETS_PER_FRAME [expr $RX_NUM_OF_CONVERTERS * $RX_SAMPLES_PER_FRAME * $RX_SAMPLE_WIDTH / (8 * $RX_NUM_OF_LANES)] ; # F -set RX_DATAPATH_WIDTH [expr max(4, $RX_OCTETS_PER_FRAME)] ; #max(4, F) -set RX_SAMPLES_PER_CHANNEL [expr $RX_NUM_OF_LANES * 8 * $RX_DATAPATH_WIDTH / ($RX_NUM_OF_CONVERTERS * $RX_SAMPLE_WIDTH)] ; # L * 8 * RX_DATAPATH_WIDTH / (M* N) +set RX_DATAPATH_WIDTH [adi_jesd204_calc_tpl_width $DATAPATH_WIDTH $RX_NUM_OF_LANES $RX_NUM_OF_CONVERTERS $RX_SAMPLES_PER_FRAME $RX_SAMPLE_WIDTH $RX_TPL_WIDTH] +set RX_SAMPLES_PER_CHANNEL [expr $RX_NUM_OF_LANES * 8 * $RX_DATAPATH_WIDTH / ($RX_NUM_OF_CONVERTERS * $RX_SAMPLE_WIDTH)] ; set adc_dma_data_width [expr $RX_NUM_OF_LANES * 8 * $RX_DATAPATH_WIDTH] @@ -66,14 +72,16 @@ set RX_OS_SAMPLES_PER_FRAME $ad_project_params(RX_OS_JESD_S) ; # S set RX_OS_SAMPLE_WIDTH $RX_OS_JESD_NP ; # N/NP if {$ORX_ENABLE} { - set RX_OS_DATAPATH_WIDTH [adi_jesd204_calc_tpl_width $DATAPATH_WIDTH $RX_OS_NUM_OF_LANES $RX_OS_NUM_OF_CONVERTERS $RX_OS_SAMPLES_PER_FRAME $RX_OS_SAMPLE_WIDTH] + set RX_OS_DATAPATH_WIDTH [adi_jesd204_calc_tpl_width $DATAPATH_WIDTH $RX_OS_NUM_OF_LANES $RX_OS_NUM_OF_CONVERTERS $RX_OS_SAMPLES_PER_FRAME $RX_OS_SAMPLE_WIDTH $RX_OS_TPL_WIDTH] set RX_OS_SAMPLES_PER_CHANNEL [expr $RX_OS_NUM_OF_LANES * 8 * $RX_OS_DATAPATH_WIDTH / ($RX_OS_NUM_OF_CONVERTERS * $RX_OS_SAMPLE_WIDTH)] } set dac_offload_name adrv9026_data_offload set dac_data_width [expr $TX_SAMPLE_WIDTH * $TX_NUM_OF_CONVERTERS * $TX_SAMPLES_PER_CHANNEL] -set MAX_RX_NUM_OF_LANES [expr $ORX_ENABLE ? [expr $RX_NUM_OF_LANES + $RX_OS_NUM_OF_LANES] : $RX_NUM_OF_LANES] +set MAX_RX_NUM_OF_LANES [expr $ORX_ENABLE ? 2 : 4] +set MAX_TX_NUM_OF_LANES 4 +set MAX_RX_OS_NUM_OF_LANES [expr $ORX_ENABLE ? 2 : 0] source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl source $ad_hdl_dir/projects/common/xilinx/data_offload_bd.tcl @@ -94,7 +102,7 @@ ad_ip_parameter axi_adrv9026_tx_clkgen CONFIG.CLK0_DIV 4 ad_ip_instance axi_adxcvr axi_adrv9026_tx_xcvr ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.LINK_MODE $ENCODER_SEL -ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.NUM_OF_LANES $TX_NUM_OF_LANES +ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.NUM_OF_LANES $MAX_TX_NUM_OF_LANES ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.QPLL_ENABLE 1 ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.TX_OR_RX_N 1 ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.SYS_CLK_SEL 3 @@ -148,7 +156,7 @@ ad_ip_parameter axi_adrv9026_rx_clkgen CONFIG.CLK0_DIV 4 ad_ip_instance axi_adxcvr axi_adrv9026_rx_xcvr ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.LINK_MODE $ENCODER_SEL -ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.NUM_OF_LANES $RX_NUM_OF_LANES +ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.NUM_OF_LANES $MAX_RX_NUM_OF_LANES ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.QPLL_ENABLE 0 ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.TX_OR_RX_N 0 ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.SYS_CLK_SEL 0 @@ -174,6 +182,8 @@ ad_ip_instance axi_dmac axi_adrv9026_rx_dma ad_ip_parameter axi_adrv9026_rx_dma CONFIG.DMA_TYPE_SRC 2 ad_ip_parameter axi_adrv9026_rx_dma CONFIG.DMA_TYPE_DEST 0 ad_ip_parameter axi_adrv9026_rx_dma CONFIG.CYCLIC 0 +ad_ip_parameter axi_adrv9026_rx_dma CONFIG.AXI_SLICE_DEST {true} +ad_ip_parameter axi_adrv9026_rx_dma CONFIG.AXI_SLICE_SRC {true} ad_ip_parameter axi_adrv9026_rx_dma CONFIG.SYNC_TRANSFER_START 1 ad_ip_parameter axi_adrv9026_rx_dma CONFIG.DMA_DATA_WIDTH_SRC $adc_dma_data_width ad_ip_parameter axi_adrv9026_rx_dma CONFIG.MAX_BYTES_PER_BURST 4096 @@ -192,7 +202,7 @@ if {$ORX_ENABLE} { ad_ip_instance axi_adxcvr axi_adrv9026_rx_os_xcvr ad_ip_parameter axi_adrv9026_rx_os_xcvr CONFIG.LINK_MODE $ENCODER_SEL - ad_ip_parameter axi_adrv9026_rx_os_xcvr CONFIG.NUM_OF_LANES $RX_OS_NUM_OF_LANES + ad_ip_parameter axi_adrv9026_rx_os_xcvr CONFIG.NUM_OF_LANES $MAX_RX_OS_NUM_OF_LANES ad_ip_parameter axi_adrv9026_rx_os_xcvr CONFIG.QPLL_ENABLE 0 ad_ip_parameter axi_adrv9026_rx_os_xcvr CONFIG.TX_OR_RX_N 0 ad_ip_parameter axi_adrv9026_rx_os_xcvr CONFIG.SYS_CLK_SEL 0 @@ -218,6 +228,8 @@ if {$ORX_ENABLE} { ad_ip_parameter axi_adrv9026_rx_os_dma CONFIG.DMA_TYPE_SRC 2 ad_ip_parameter axi_adrv9026_rx_os_dma CONFIG.DMA_TYPE_DEST 0 ad_ip_parameter axi_adrv9026_rx_os_dma CONFIG.CYCLIC 0 + ad_ip_parameter axi_adrv9026_rx_os_dma CONFIG.AXI_SLICE_DEST {true} + ad_ip_parameter axi_adrv9026_rx_os_dma CONFIG.AXI_SLICE_SRC {true} ad_ip_parameter axi_adrv9026_rx_os_dma CONFIG.SYNC_TRANSFER_START 1 ad_ip_parameter axi_adrv9026_rx_os_dma CONFIG.DMA_DATA_WIDTH_SRC [expr $RX_OS_SAMPLE_WIDTH * $RX_OS_NUM_OF_CONVERTERS * $RX_OS_SAMPLES_PER_CHANNEL]; ad_ip_parameter axi_adrv9026_rx_os_dma CONFIG.MAX_BYTES_PER_BURST 4096 @@ -228,8 +240,8 @@ if {$ORX_ENABLE} { # common cores ad_ip_instance util_adxcvr util_adrv9026_xcvr -ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_NUM_OF_LANES $MAX_RX_NUM_OF_LANES -ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_NUM_OF_LANES $TX_NUM_OF_LANES +ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_NUM_OF_LANES [expr $MAX_RX_NUM_OF_LANES + $MAX_RX_OS_NUM_OF_LANES] +ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_NUM_OF_LANES $MAX_TX_NUM_OF_LANES ad_ip_parameter util_adrv9026_xcvr CONFIG.LINK_MODE $ENCODER_SEL ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_LANE_RATE $RX_LANE_RATE ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_LANE_RATE $TX_LANE_RATE @@ -237,7 +249,7 @@ ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_OUT_DIV 1 ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_OUT_DIV 1 ad_ip_parameter util_adrv9026_xcvr CONFIG.CPLL_FBDIV_4_5 5 ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_CDR_CFG 0x0b000023ff10400020 -ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_LANE_INVERT 6 +ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_LANE_INVERT 5 ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_LANE_INVERT 15 if {$JESD_MODE == "8B10B"} { @@ -302,7 +314,8 @@ ad_connect $sys_cpu_clk util_adrv9026_xcvr/up_clk ad_connect adrv9026_tx_device_clk axi_adrv9026_tx_clkgen/clk_0 ad_connect core_clk axi_adrv9026_tx_clkgen/clk -ad_xcvrcon util_adrv9026_xcvr axi_adrv9026_tx_xcvr axi_adrv9026_tx_jesd {3 2 0 1} {} adrv9026_tx_device_clk $TX_NUM_OF_LANES +ad_xcvrcon util_adrv9026_xcvr axi_adrv9026_tx_xcvr axi_adrv9026_tx_jesd {} {} adrv9026_tx_device_clk $MAX_TX_NUM_OF_LANES {3 2 1 0} + ad_xcvrpll $tx_ref_clk util_adrv9026_xcvr/qpll_ref_clk_0 ad_xcvrpll axi_adrv9026_tx_xcvr/up_pll_rst util_adrv9026_xcvr/up_qpll_rst_0 @@ -310,9 +323,9 @@ ad_xcvrpll axi_adrv9026_tx_xcvr/up_pll_rst util_adrv9026_xcvr/up_qpll_rst_0 ad_connect adrv9026_rx_device_clk axi_adrv9026_rx_clkgen/clk_0 ad_connect core_clk axi_adrv9026_rx_clkgen/clk -ad_xcvrcon util_adrv9026_xcvr axi_adrv9026_rx_xcvr axi_adrv9026_rx_jesd {} {} adrv9026_rx_device_clk $RX_NUM_OF_LANES +ad_xcvrcon util_adrv9026_xcvr axi_adrv9026_rx_xcvr axi_adrv9026_rx_jesd {} {} adrv9026_rx_device_clk $MAX_RX_NUM_OF_LANES {1 0 2 3} -for {set i 0} {$i < $RX_NUM_OF_LANES} {incr i} { +for {set i 0} {$i < $MAX_RX_NUM_OF_LANES} {incr i} { set ch [expr $i] ad_xcvrpll $rx_ref_clk util_adrv9026_xcvr/cpll_ref_clk_$ch ad_xcvrpll axi_adrv9026_rx_xcvr/up_pll_rst util_adrv9026_xcvr/up_cpll_rst_$ch @@ -322,15 +335,17 @@ if {$ORX_ENABLE} { # Rx - OBS ad_connect adrv9026_rx_os_device_clk axi_adrv9026_rx_os_clkgen/clk_0 ad_connect core_clk axi_adrv9026_rx_os_clkgen/clk - ad_xcvrcon util_adrv9026_xcvr axi_adrv9026_rx_os_xcvr axi_adrv9026_rx_os_jesd {} {} adrv9026_rx_os_device_clk $RX_OS_NUM_OF_LANES - for {set i 0} {$i < $RX_OS_NUM_OF_LANES} {incr i} { - set ch [expr $RX_NUM_OF_LANES + $i] + + ad_xcvrcon util_adrv9026_xcvr axi_adrv9026_rx_os_xcvr axi_adrv9026_rx_os_jesd {2 3} {} adrv9026_rx_os_device_clk $MAX_RX_OS_NUM_OF_LANES {} + + for {set i 0} {$i < $MAX_RX_OS_NUM_OF_LANES} {incr i} { + set ch [expr $MAX_RX_NUM_OF_LANES + $i] ad_xcvrpll $rx_obs_ref_clk util_adrv9026_xcvr/cpll_ref_clk_$ch ad_xcvrpll axi_adrv9026_rx_os_xcvr/up_pll_rst util_adrv9026_xcvr/up_cpll_rst_$ch } - delete_bd_objs [get_bd_ports rx_sync_$RX_NUM_OF_LANES] - delete_bd_objs [get_bd_ports rx_sysref_$RX_NUM_OF_LANES] + delete_bd_objs [get_bd_ports rx_sync_$MAX_RX_NUM_OF_LANES] + delete_bd_objs [get_bd_ports rx_sysref_$MAX_RX_NUM_OF_LANES] ad_connect rx_os_sync axi_adrv9026_rx_os_jesd_sync ad_connect rx_os_sysref sysref_3 } diff --git a/projects/adrv9026/common/adrv9026_fmc.txt b/projects/adrv9026/common/adrv9026_fmc.txt index 77db74da2ae..c8ebdf73c7a 100644 --- a/projects/adrv9026/common/adrv9026_fmc.txt +++ b/projects/adrv9026/common/adrv9026_fmc.txt @@ -7,23 +7,23 @@ D5 GBTCLK0_M2C_N FPGA_REF_CLK- ref_clk_n #N/A #N/A H4 CLK0_M2C_P FPGA_MMCM_CLK+ core_clk_p LVDS #N/A H5 CLK0_M2C_N FPGA_MMCM_CLK- core_clk_n LVDS #N/A -C6 DP0_M2C_P SERDOUTB- rx_data_p[0] #N/A #N/A -C7 DP0_M2C_N SERDOUTB+ rx_data_n[0] #N/A #N/A -A2 DP1_M2C_P SERDOUTA- rx_data_p[1] #N/A #N/A -A3 DP1_M2C_N SERDOUTA+ rx_data_n[1] #N/A #N/A +A2 DP1_M2C_P SERDOUTA- rx_data_p[0] #N/A #N/A +A3 DP1_M2C_N SERDOUTA+ rx_data_n[0] #N/A #N/A +C6 DP0_M2C_P SERDOUTB- rx_data_p[1] #N/A #N/A +C7 DP0_M2C_N SERDOUTB+ rx_data_n[1] #N/A #N/A A6 DP2_M2C_P SERDOUTC- rx_data_p[2] #N/A #N/A A7 DP2_M2C_N SERDOUTC+ rx_data_n[2] #N/A #N/A A10 DP3_M2C_P SERDOUTD- rx_data_p[3] #N/A #N/A A11 DP3_M2C_N SERDOUTD+ rx_data_n[3] #N/A #N/A -C2 DP0_C2M_P SERDIND- tx_data_p[0] #N/A #N/A -C3 DP0_C2M_N SERDIND+ tx_data_n[0] #N/A #N/A -A22 DP1_C2M_P SERDINC+ tx_data_p[1] #N/A #N/A -A23 DP1_C2M_N SERDINC- tx_data_n[1] #N/A #N/A -A26 DP2_C2M_P SERDINB- tx_data_p[2] #N/A #N/A -A27 DP2_C2M_N SERDINB+ tx_data_n[2] #N/A #N/A -A30 DP3_C2M_P SERDINA+ tx_data_p[3] #N/A #N/A -A31 DP3_C2M_N SERDINA- tx_data_n[3] #N/A #N/A +A30 DP3_C2M_P SERDINA+ tx_data_p[0] #N/A #N/A +A31 DP3_C2M_N SERDINA- tx_data_n[0] #N/A #N/A +A26 DP2_C2M_P SERDINB- tx_data_p[1] #N/A #N/A +A27 DP2_C2M_N SERDINB+ tx_data_n[1] #N/A #N/A +A22 DP1_C2M_P SERDINC+ tx_data_p[2] #N/A #N/A +A23 DP1_C2M_N SERDINC- tx_data_n[2] #N/A #N/A +C2 DP0_C2M_P SERDIND- tx_data_p[3] #N/A #N/A +C3 DP0_C2M_N SERDIND+ tx_data_n[3] #N/A #N/A G9 LA03_P SYNCIN1- rx_sync_p LVDS #N/A G10 LA03_N SYNCIN1+ rx_sync_n LVDS #N/A diff --git a/projects/adrv9026/vcu118/system_constr.xdc b/projects/adrv9026/vcu118/system_constr.xdc index 142ae4ea8c3..511f0077f4e 100644 --- a/projects/adrv9026/vcu118/system_constr.xdc +++ b/projects/adrv9026/vcu118/system_constr.xdc @@ -19,14 +19,14 @@ set_property -dict {PACKAGE_PIN AL46} [get_ports rx_data_n[2]] set_property -dict {PACKAGE_PIN AJ45} [get_ports rx_data_p[3]] ; ## A10 FMC_DP3_M2C_P MGTYRXP3_121 set_property -dict {PACKAGE_PIN AJ46} [get_ports rx_data_n[3]] ; ## A11 FMC_DP3_M2C_N MGTYRXN3_121 -set_property -dict {PACKAGE_PIN AP42} [get_ports tx_data_p[0]] ; ## A22 FMC_DP1_C2M_P MGTYTXP1_121 -set_property -dict {PACKAGE_PIN AP43} [get_ports tx_data_n[0]] ; ## A23 FMC_DP1_C2M_N MGTYTXN1_121 -set_property -dict {PACKAGE_PIN AT42} [get_ports tx_data_p[1]] ; ## C2 FMC_DP0_C2M_P MGTYTXP0_121 -set_property -dict {PACKAGE_PIN AT43} [get_ports tx_data_n[1]] ; ## C3 FMC_DP0_C2M_N MGTYTXN0_121 -set_property -dict {PACKAGE_PIN AM42} [get_ports tx_data_p[2]] ; ## A26 FMC_DP2_C2M_P MGTYTXP2_121 -set_property -dict {PACKAGE_PIN AM43} [get_ports tx_data_n[2]] ; ## A27 FMC_DP2_C2M_N MGTYTXN2_121 -set_property -dict {PACKAGE_PIN AL40} [get_ports tx_data_p[3]] ; ## A30 FMC_DP3_C2M_P MGTYTXP3_121 -set_property -dict {PACKAGE_PIN AL41} [get_ports tx_data_n[3]] ; ## A31 FMC_DP3_C2M_N MGTYTXN3_121 +set_property -dict {PACKAGE_PIN AL40} [get_ports tx_data_p[0]] ; ## A30 FMC_DP3_C2M_P MGTYTXP3_121 +set_property -dict {PACKAGE_PIN AL41} [get_ports tx_data_n[0]] ; ## A31 FMC_DP3_C2M_N MGTYTXN3_121 +set_property -dict {PACKAGE_PIN AM42} [get_ports tx_data_p[1]] ; ## A26 FMC_DP2_C2M_P MGTYTXP2_121 +set_property -dict {PACKAGE_PIN AM43} [get_ports tx_data_n[1]] ; ## A27 FMC_DP2_C2M_N MGTYTXN2_121 +set_property -dict {PACKAGE_PIN AP42} [get_ports tx_data_p[2]] ; ## A22 FMC_DP1_C2M_P MGTYTXP1_121 +set_property -dict {PACKAGE_PIN AP43} [get_ports tx_data_n[2]] ; ## A23 FMC_DP1_C2M_N MGTYTXN1_121 +set_property -dict {PACKAGE_PIN AT42} [get_ports tx_data_p[3]] ; ## C2 FMC_DP0_C2M_P MGTYTXP0_121 +set_property -dict {PACKAGE_PIN AT43} [get_ports tx_data_n[3]] ; ## C3 FMC_DP0_C2M_N MGTYTXN0_121 set_property -dict {PACKAGE_PIN AT39 IOSTANDARD LVDS} [get_ports rx_sync_p] ; ## G9 FMC_LA03_P IO_L4P_T0U_N6_DBC_AD7P_43 set_property -dict {PACKAGE_PIN AT40 IOSTANDARD LVDS} [get_ports rx_sync_n] ; ## G10 FMC_LA03_N IO_L4N_T0U_N7_DBC_AD7N_43 diff --git a/projects/adrv9026/vcu118/system_project.tcl b/projects/adrv9026/vcu118/system_project.tcl index 0c2c89bf193..c90235e29d6 100644 --- a/projects/adrv9026/vcu118/system_project.tcl +++ b/projects/adrv9026/vcu118/system_project.tcl @@ -15,7 +15,7 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl # e.g. # RX-OS disabled: make # RX-OS Non-LinkSharing: -# - JESD204B: make ORX_ENABLE=1 RX_OS_JESD_M=4 RX_OS_JESD_L=2 RX_OS_JESD_S=1 RX_OS_JESD_NP=16 RX_JESD_M=4 RX_JESD_L=2 +# - JESD204B: make ORX_ENABLE=1 RX_OS_JESD_M=4 RX_OS_JESD_L=2 RX_OS_JESD_S=1 RX_OS_JESD_NP=16 RX_JESD_L=2 RX_TPL_WIDTH=8 # - JESD204C: make JESD_MODE=64B66B ORX_ENABLE=1 TX_LANE_RATE=16.22 RX_LANE_RATE=16.22 \ RX_OS_JESD_M=4 RX_OS_JESD_L=2 RX_OS_JESD_S=1 RX_OS_JESD_NP=16 RX_JESD_L=2 # @@ -33,6 +33,7 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl # [TX/RX/RX_OS]_JESD_L : Number of lanes per link # [TX/RX/RX_OS]_JESD_S : Number of samples per frame # [TX/RX/RX_OS]_JESD_NP : Number of bits per sample +# [TX/RX/RX_OS]_TPL_WIDTH : TPL data path width in bits adi_project adrv9026_vcu118 0 [list \ JESD_MODE [get_env_param JESD_MODE 8B10B ] \ @@ -46,14 +47,17 @@ adi_project adrv9026_vcu118 0 [list \ TX_JESD_L [get_env_param TX_JESD_L 4 ] \ TX_JESD_S [get_env_param TX_JESD_S 1 ] \ TX_JESD_NP [get_env_param TX_JESD_NP 16 ] \ + TX_TPL_WIDTH [get_env_param TX_TPL_WIDTH {} ] \ RX_JESD_M [get_env_param RX_JESD_M 8 ] \ RX_JESD_L [get_env_param RX_JESD_L 4 ] \ RX_JESD_S [get_env_param RX_JESD_S 1 ] \ RX_JESD_NP [get_env_param RX_JESD_NP 16 ] \ + RX_TPL_WIDTH [get_env_param TX_TPL_WIDTH {} ] \ RX_OS_JESD_M [get_env_param RX_OS_JESD_M 0 ] \ RX_OS_JESD_L [get_env_param RX_OS_JESD_L 0 ] \ RX_OS_JESD_S [get_env_param RX_OS_JESD_S 0 ] \ RX_OS_JESD_NP [get_env_param RX_OS_JESD_NP 0 ] \ + RX_OS_TPL_WIDTH [get_env_param TX_TPL_WIDTH {} ] \ ] adi_project_files adrv9026_vcu118 [list \ diff --git a/projects/adrv9026/vcu118/system_top.v b/projects/adrv9026/vcu118/system_top.v index fba0a0ebfb4..b4cc0f1942a 100644 --- a/projects/adrv9026/vcu118/system_top.v +++ b/projects/adrv9026/vcu118/system_top.v @@ -308,10 +308,10 @@ module system_top ( .gpio1_o (gpio_o[62:32]), .gpio1_t (gpio_t[62:32]), .core_clk (core_clk), - .rx_data_0_n (rx_data_n[0]), - .rx_data_0_p (rx_data_p[0]), - .rx_data_1_n (rx_data_n[1]), - .rx_data_1_p (rx_data_p[1]), + .rx_data_0_n (rx_data_n[1]), + .rx_data_0_p (rx_data_p[1]), + .rx_data_1_n (rx_data_n[0]), + .rx_data_1_p (rx_data_p[0]), .rx_data_2_n (rx_data_n[2]), .rx_data_2_p (rx_data_p[2]), .rx_data_3_n (rx_data_n[3]), @@ -322,14 +322,14 @@ module system_top ( .rx_os_sync (rx_os_sync), .rx_sysref_0 (sysref), .rx_os_sysref (sysref), - .tx_data_0_n (tx_data_n[0]), - .tx_data_0_p (tx_data_p[0]), - .tx_data_1_n (tx_data_n[1]), - .tx_data_1_p (tx_data_p[1]), - .tx_data_2_n (tx_data_n[2]), - .tx_data_2_p (tx_data_p[2]), - .tx_data_3_n (tx_data_n[3]), - .tx_data_3_p (tx_data_p[3]), + .tx_data_0_n (tx_data_n[3]), + .tx_data_0_p (tx_data_p[3]), + .tx_data_1_n (tx_data_n[2]), + .tx_data_1_p (tx_data_p[2]), + .tx_data_2_n (tx_data_n[1]), + .tx_data_2_p (tx_data_p[1]), + .tx_data_3_n (tx_data_n[0]), + .tx_data_3_p (tx_data_p[0]), .tx_ref_clk_0 (ref_clk), .tx_sync_0 (tx_sync), .tx_sysref_0 (sysref)); diff --git a/projects/adrv9026/zcu102/system_constr.xdc b/projects/adrv9026/zcu102/system_constr.xdc index 3b0e6bc581d..89ee8582a04 100644 --- a/projects/adrv9026/zcu102/system_constr.xdc +++ b/projects/adrv9026/zcu102/system_constr.xdc @@ -19,14 +19,14 @@ set_property -dict {PACKAGE_PIN C32} [get_ports rx_data_n[2]] set_property -dict {PACKAGE_PIN B33} [get_ports rx_data_p[3]] ; ## A10 FMC1_DP3_M2C_P MGTHRXP3_130 set_property -dict {PACKAGE_PIN B34} [get_ports rx_data_n[3]] ; ## A11 FMC1_DP3_M2C_N MGTHRXN3_130 -set_property -dict {PACKAGE_PIN D29} [get_ports tx_data_p[0]] ; ## A22 FMC1_DP1_C2M_P MGTHTXP1_130 (tx_data_p[2]) -set_property -dict {PACKAGE_PIN D30} [get_ports tx_data_n[0]] ; ## A23 FMC1_DP1_C2M_N MGTHTXN1_130 (tx_data_n[2]) -set_property -dict {PACKAGE_PIN F29} [get_ports tx_data_p[1]] ; ## C2 FMC1_DP0_C2M_P MGTHTXP0_130 (tx_data_p[3]) -set_property -dict {PACKAGE_PIN F30} [get_ports tx_data_n[1]] ; ## C3 FMC1_DP0_C2M_N MGTHTXN0_130 (tx_data_n[3]) -set_property -dict {PACKAGE_PIN B29} [get_ports tx_data_p[2]] ; ## A26 FMC1_DP2_C2M_P MGTHTXP2_130 (tx_data_p[1]) -set_property -dict {PACKAGE_PIN B30} [get_ports tx_data_n[2]] ; ## A27 FMC1_DP2_C2M_N MGTHTXN2_130 (tx_data_n[1]) -set_property -dict {PACKAGE_PIN A31} [get_ports tx_data_p[3]] ; ## A30 FMC1_DP3_C2M_P MGTHTXP3_130 (tx_data_p[0]) -set_property -dict {PACKAGE_PIN A32} [get_ports tx_data_n[3]] ; ## A31 FMC1_DP3_C2M_N MGTHTXN3_130 (tx_data_n[0]) +set_property -dict {PACKAGE_PIN A31} [get_ports tx_data_p[0]] ; ## A30 FMC1_DP3_C2M_P MGTHTXP3_130 (tx_data_p[0]) +set_property -dict {PACKAGE_PIN A32} [get_ports tx_data_n[0]] ; ## A31 FMC1_DP3_C2M_N MGTHTXN3_130 (tx_data_n[0]) +set_property -dict {PACKAGE_PIN B29} [get_ports tx_data_p[1]] ; ## A26 FMC1_DP2_C2M_P MGTHTXP2_130 (tx_data_p[1]) +set_property -dict {PACKAGE_PIN B30} [get_ports tx_data_n[1]] ; ## A27 FMC1_DP2_C2M_N MGTHTXN2_130 (tx_data_n[1]) +set_property -dict {PACKAGE_PIN D29} [get_ports tx_data_p[2]] ; ## A22 FMC1_DP1_C2M_P MGTHTXP1_130 (tx_data_p[2]) +set_property -dict {PACKAGE_PIN D30} [get_ports tx_data_n[2]] ; ## A23 FMC1_DP1_C2M_N MGTHTXN1_130 (tx_data_n[2]) +set_property -dict {PACKAGE_PIN F29} [get_ports tx_data_p[3]] ; ## C2 FMC1_DP0_C2M_P MGTHTXP0_130 (tx_data_p[3]) +set_property -dict {PACKAGE_PIN F30} [get_ports tx_data_n[3]] ; ## C3 FMC1_DP0_C2M_N MGTHTXN0_130 (tx_data_n[3]) set_property -dict {PACKAGE_PIN AH1 IOSTANDARD LVDS} [get_ports rx_sync_p] ; ## G9 FMC1_LA03_P IO_L22P_T3U_N6_DBC_AD0P_65 set_property -dict {PACKAGE_PIN AJ1 IOSTANDARD LVDS} [get_ports rx_sync_n] ; ## G10 FMC1_LA03_N IO_L22N_T3U_N7_DBC_AD0N_65 diff --git a/projects/adrv9026/zcu102/system_project.tcl b/projects/adrv9026/zcu102/system_project.tcl index 44684a910eb..e5e04e0fb99 100644 --- a/projects/adrv9026/zcu102/system_project.tcl +++ b/projects/adrv9026/zcu102/system_project.tcl @@ -15,7 +15,7 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl # e.g. # RX-OS disabled: make # RX-OS Non-LinkSharing: -# - JESD204B: make ORX_ENABLE=1 RX_OS_JESD_M=4 RX_OS_JESD_L=2 RX_OS_JESD_S=1 RX_OS_JESD_NP=16 RX_JESD_M=4 RX_JESD_L=2 +# - JESD204B: make ORX_ENABLE=1 RX_OS_JESD_M=4 RX_OS_JESD_L=2 RX_OS_JESD_S=1 RX_OS_JESD_NP=16 RX_JESD_L=2 RX_TPL_WIDTH=8 # - JESD204C: make JESD_MODE=64B66B ORX_ENABLE=1 TX_LANE_RATE=16.22 RX_LANE_RATE=16.22 \ RX_OS_JESD_M=4 RX_OS_JESD_L=2 RX_OS_JESD_S=1 RX_OS_JESD_NP=16 RX_JESD_L=2 # @@ -33,6 +33,7 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl # [TX/RX/RX_OS]_JESD_L : Number of lanes per link # [TX/RX/RX_OS]_JESD_S : Number of samples per frame # [TX/RX/RX_OS]_JESD_NP : Number of bits per sample +# [TX/RX/RX_OS]_TPL_WIDTH : TPL data path width in bits adi_project adrv9026_zcu102 0 [list \ JESD_MODE [get_env_param JESD_MODE 8B10B ] \ @@ -46,14 +47,17 @@ adi_project adrv9026_zcu102 0 [list \ TX_JESD_L [get_env_param TX_JESD_L 4 ] \ TX_JESD_S [get_env_param TX_JESD_S 1 ] \ TX_JESD_NP [get_env_param TX_JESD_NP 16 ] \ + TX_TPL_WIDTH [get_env_param TX_TPL_WIDTH {} ] \ RX_JESD_M [get_env_param RX_JESD_M 8 ] \ RX_JESD_L [get_env_param RX_JESD_L 4 ] \ RX_JESD_S [get_env_param RX_JESD_S 1 ] \ RX_JESD_NP [get_env_param RX_JESD_NP 16 ] \ + RX_TPL_WIDTH [get_env_param RX_TPL_WIDTH {} ] \ RX_OS_JESD_M [get_env_param RX_OS_JESD_M 0 ] \ RX_OS_JESD_L [get_env_param RX_OS_JESD_L 0 ] \ RX_OS_JESD_S [get_env_param RX_OS_JESD_S 0 ] \ RX_OS_JESD_NP [get_env_param RX_OS_JESD_NP 0 ] \ + RX_OS_TPL_WIDTH [get_env_param RX_OS_TPL_WIDTH {} ] \ ] adi_project_files adrv9026_zcu102 [list \ "system_top.v" \ diff --git a/projects/adrv9026/zcu102/system_top.v b/projects/adrv9026/zcu102/system_top.v index a9328255d6c..485f6a67b8f 100644 --- a/projects/adrv9026/zcu102/system_top.v +++ b/projects/adrv9026/zcu102/system_top.v @@ -224,10 +224,10 @@ module system_top ( .gpio_o (gpio_o), .gpio_t (gpio_t), .core_clk (core_clk), - .rx_data_0_n (rx_data_n[0]), - .rx_data_0_p (rx_data_p[0]), - .rx_data_1_n (rx_data_n[1]), - .rx_data_1_p (rx_data_p[1]), + .rx_data_0_n (rx_data_n[1]), + .rx_data_0_p (rx_data_p[1]), + .rx_data_1_n (rx_data_n[0]), + .rx_data_1_p (rx_data_p[0]), .rx_data_2_n (rx_data_n[2]), .rx_data_2_p (rx_data_p[2]), .rx_data_3_n (rx_data_n[3]), @@ -246,14 +246,14 @@ module system_top ( .spi1_csn (), .spi1_miso (1'b0), .spi1_mosi (), - .tx_data_0_n (tx_data_n[0]), - .tx_data_0_p (tx_data_p[0]), - .tx_data_1_n (tx_data_n[1]), - .tx_data_1_p (tx_data_p[1]), - .tx_data_2_n (tx_data_n[2]), - .tx_data_2_p (tx_data_p[2]), - .tx_data_3_n (tx_data_n[3]), - .tx_data_3_p (tx_data_p[3]), + .tx_data_0_n (tx_data_n[3]), + .tx_data_0_p (tx_data_p[3]), + .tx_data_1_n (tx_data_n[2]), + .tx_data_1_p (tx_data_p[2]), + .tx_data_2_n (tx_data_n[1]), + .tx_data_2_p (tx_data_p[1]), + .tx_data_3_n (tx_data_n[0]), + .tx_data_3_p (tx_data_p[0]), .tx_ref_clk_0 (ref_clk), .tx_sync_0 (tx_sync), .tx_sysref_0 (sysref)); From 434381cafc39cd62a8b35245e474dc4f12f79fe0 Mon Sep 17 00:00:00 2001 From: AndrDragomir Date: Mon, 17 Nov 2025 16:07:15 +0200 Subject: [PATCH 2/2] docs/adrv9026: Update documentation Updated lane mapping, new build parameter and ORX NLS profile Signed-off-by: AndrDragomir --- .../adrv9026/adrv9026_nls_block_diagram.svg | 48 ++++---- docs/projects/adrv9026/index.rst | 108 ++++++++++-------- 2 files changed, 85 insertions(+), 71 deletions(-) diff --git a/docs/projects/adrv9026/adrv9026_nls_block_diagram.svg b/docs/projects/adrv9026/adrv9026_nls_block_diagram.svg index eb6e6b2d668..4c953bb856c 100644 --- a/docs/projects/adrv9026/adrv9026_nls_block_diagram.svg +++ b/docs/projects/adrv9026/adrv9026_nls_block_diagram.svg @@ -3887,17 +3887,17 @@ borderopacity="1.0" inkscape:pageopacity="0.0" inkscape:pageshadow="2" - inkscape:zoom="1" - inkscape:cx="217.5" - inkscape:cy="874" + inkscape:zoom="1.4142136" + inkscape:cx="350.01786" + inkscape:cy="406.93995" inkscape:document-units="px" inkscape:current-layer="layer1" showgrid="false" units="px" - inkscape:window-width="2400" - inkscape:window-height="1262" - inkscape:window-x="2392" - inkscape:window-y="-8" + inkscape:window-width="1920" + inkscape:window-height="991" + inkscape:window-x="-9" + inkscape:window-y="-9" inkscape:window-maximized="1" inkscape:pagecheckerboard="0" inkscape:showpageshadow="2" @@ -3973,12 +3973,12 @@ id="tspan15208" style="font-size:9.99999px;line-height:1.25;text-align:center;text-anchor:middle;fill:#000000;fill-opacity:1;stroke-width:0.708661" x="-1577.7908" - y="549.37189">64bits128bits@245.76MHz + y="564.96576">@122.88MHz + 64b + style="fill:#ffffff;fill-opacity:1;stroke-width:0.3607">128b 64b128b@250MHz + id="tspan102401">@122.88MHz 64b + style="fill:#ffffff;fill-opacity:1;stroke-width:0.3607">128b 4 samples + y="353.01727">8 samples @250MHz + id="tspan26">@245.76MHz 4x1 8x1