From 19ab08c9fe781104eb19fce6c6b92838e91004f1 Mon Sep 17 00:00:00 2001 From: AndrDragomir Date: Mon, 25 Aug 2025 14:19:22 +0300 Subject: [PATCH 1/2] projects/adrv903x: Add ADRV903x initial design Initial design for ADRV903x + ZCU102 ORX support available in Non-LinkSharing mode Signed-off-by: AndrDragomir --- projects/adrv903x/Makefile | 7 + projects/adrv903x/README.md | 16 + projects/adrv903x/common/adrv903x_bd.tcl | 551 ++++++++++++++++++++ projects/adrv903x/zcu102/Makefile | 41 ++ projects/adrv903x/zcu102/README.md | 69 +++ projects/adrv903x/zcu102/system_bd.tcl | 49 ++ projects/adrv903x/zcu102/system_constr.xdc | 118 +++++ projects/adrv903x/zcu102/system_project.tcl | 63 +++ projects/adrv903x/zcu102/system_top.v | 256 +++++++++ 9 files changed, 1170 insertions(+) create mode 100644 projects/adrv903x/Makefile create mode 100644 projects/adrv903x/README.md create mode 100644 projects/adrv903x/common/adrv903x_bd.tcl create mode 100644 projects/adrv903x/zcu102/Makefile create mode 100644 projects/adrv903x/zcu102/README.md create mode 100644 projects/adrv903x/zcu102/system_bd.tcl create mode 100644 projects/adrv903x/zcu102/system_constr.xdc create mode 100644 projects/adrv903x/zcu102/system_project.tcl create mode 100644 projects/adrv903x/zcu102/system_top.v diff --git a/projects/adrv903x/Makefile b/projects/adrv903x/Makefile new file mode 100644 index 00000000000..68a7ed005cb --- /dev/null +++ b/projects/adrv903x/Makefile @@ -0,0 +1,7 @@ +#################################################################################### +## Copyright (c) 2018 - 2025 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +include ../scripts/project-toplevel.mk diff --git a/projects/adrv903x/README.md b/projects/adrv903x/README.md new file mode 100644 index 00000000000..bf9db373d5c --- /dev/null +++ b/projects/adrv903x/README.md @@ -0,0 +1,16 @@ +# ADRV903X HDL Project + +- Evaluation board product page: [EVAL-ADRV903x](https://www.analog.com/eval-adrv903x) +- System documentation: https://wiki.analog.com/resources/eval/user-guides/adrv903x/quickstart/zynqmp +- HDL project documentation: https://analogdevicesinc.github.io/hdl/projects/adrv903x/index.html +- Evaluation board VADJ: 1.8V + +## Supported parts + +| Part name | Description | +|----------------------------------------------|-----------------------------------------| +| [ADRV903x](https://www.analog.com/adrv9030) | 8T8R2OR SoC, 400 MHz iBW RF Transceiver | + +## Building the project + +Please enter the folder for the FPGA carrier you want to use and read the README.md. diff --git a/projects/adrv903x/common/adrv903x_bd.tcl b/projects/adrv903x/common/adrv903x_bd.tcl new file mode 100644 index 00000000000..79ca3c171d0 --- /dev/null +++ b/projects/adrv903x/common/adrv903x_bd.tcl @@ -0,0 +1,551 @@ +############################################################################### +## Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set ORX_ENABLE $ad_project_params(ORX_ENABLE) ; # 0 = Disabled ; 1 = Enabled + +set JESD_MODE $ad_project_params(JESD_MODE) +set TX_LANE_RATE $ad_project_params(TX_LANE_RATE) +set RX_LANE_RATE $ad_project_params(RX_LANE_RATE) + +set TX_NUM_LINKS $ad_project_params(TX_NUM_LINKS) +set RX_NUM_LINKS $ad_project_params(RX_NUM_LINKS) +set RX_OS_NUM_LINKS $ad_project_params(RX_OS_NUM_LINKS) + +set TX_JESD_L $ad_project_params(TX_JESD_L) +set TX_JESD_M $ad_project_params(TX_JESD_M) +set TX_JESD_S $ad_project_params(TX_JESD_S) +set TX_JESD_NP $ad_project_params(TX_JESD_NP) + +set RX_JESD_L $ad_project_params(RX_JESD_L) +set RX_JESD_M $ad_project_params(RX_JESD_M) +set RX_JESD_S $ad_project_params(RX_JESD_S) +set RX_JESD_NP $ad_project_params(RX_JESD_NP) + +set RX_OS_JESD_L $ad_project_params(RX_OS_JESD_L) +set RX_OS_JESD_M $ad_project_params(RX_OS_JESD_M) +set RX_OS_JESD_S $ad_project_params(RX_OS_JESD_S) +set RX_OS_JESD_NP $ad_project_params(RX_OS_JESD_NP) + +if {$JESD_MODE == "8B10B"} { + set DATAPATH_WIDTH 4 + set NP12_DATAPATH_WIDTH 6 + set ENCODER_SEL 1 +} else { + set DATAPATH_WIDTH 8 + set NP12_DATAPATH_WIDTH 12 + set ENCODER_SEL 2 +} + +set TX_TPL_WIDTH [ expr { [info exists ad_project_params(TX_TPL_WIDTH)] \ + ? $ad_project_params(TX_TPL_WIDTH) : {} } ] +set RX_TPL_WIDTH [ expr { [info exists ad_project_params(RX_TPL_WIDTH)] \ + ? $ad_project_params(RX_TPL_WIDTH) : {} } ] +set RX_OS_TPL_WIDTH [ expr { [info exists ad_project_params(RX_OS_TPL_WIDTH)] \ + ? $ad_project_params(RX_OS_TPL_WIDTH) : {} } ] + +source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl +source $ad_hdl_dir/projects/common/xilinx/data_offload_bd.tcl + +# TX parameters +set TX_NUM_OF_LANES [expr $TX_JESD_L * $TX_NUM_LINKS] ; # L +set TX_NUM_OF_CONVERTERS [expr $TX_JESD_M * $TX_NUM_LINKS] ; # M +set TX_SAMPLES_PER_FRAME $TX_JESD_S ; # S +set TX_SAMPLE_WIDTH $TX_JESD_NP ; # N/NP + +set TX_DMA_SAMPLE_WIDTH $TX_JESD_NP +if {$TX_DMA_SAMPLE_WIDTH == 12} { + set TX_DMA_SAMPLE_WIDTH 16 +} + +set TX_DATAPATH_WIDTH [adi_jesd204_calc_tpl_width $DATAPATH_WIDTH $TX_JESD_L $TX_JESD_M $TX_JESD_S $TX_JESD_NP $TX_TPL_WIDTH] + +set TX_SAMPLES_PER_CHANNEL [expr $TX_NUM_OF_LANES * 8* $TX_DATAPATH_WIDTH / ($TX_NUM_OF_CONVERTERS * $TX_SAMPLE_WIDTH)] + +# RX parameters +set RX_NUM_OF_LANES [expr $RX_JESD_L * $RX_NUM_LINKS] ; # L +set RX_NUM_OF_CONVERTERS [expr $RX_JESD_M * $RX_NUM_LINKS] ; # M +set RX_SAMPLES_PER_FRAME $RX_JESD_S ; # S +set RX_SAMPLE_WIDTH $RX_JESD_NP ; # N/NP + +set RX_DMA_SAMPLE_WIDTH $RX_JESD_NP +if {$RX_DMA_SAMPLE_WIDTH == 12} { + set RX_DMA_SAMPLE_WIDTH 16 +} + +set RX_DATAPATH_WIDTH [adi_jesd204_calc_tpl_width $DATAPATH_WIDTH $RX_JESD_L $RX_JESD_M $RX_JESD_S $RX_JESD_NP $RX_TPL_WIDTH] +set RX_SAMPLES_PER_CHANNEL [expr $RX_NUM_OF_LANES * 8* $RX_DATAPATH_WIDTH / ($RX_NUM_OF_CONVERTERS * $RX_SAMPLE_WIDTH)] + +# RX OBS parameters +set RX_OS_NUM_OF_LANES [expr $RX_OS_JESD_L * $RX_OS_NUM_LINKS] ; # L +set RX_OS_NUM_OF_CONVERTERS [expr $RX_OS_JESD_M * $RX_OS_NUM_LINKS] ; # M +set RX_OS_SAMPLES_PER_FRAME $RX_OS_JESD_S ; # S +set RX_OS_SAMPLE_WIDTH $RX_OS_JESD_NP ; # N/NP + +set RX_OS_DMA_SAMPLE_WIDTH $RX_OS_JESD_NP +if {$RX_OS_DMA_SAMPLE_WIDTH == 12} { + set RX_OS_DMA_SAMPLE_WIDTH 16 +} + +if {$ORX_ENABLE} { + set RX_OS_DATAPATH_WIDTH [adi_jesd204_calc_tpl_width $DATAPATH_WIDTH $RX_OS_JESD_L $RX_OS_JESD_M $RX_OS_JESD_S $RX_OS_JESD_NP $RX_OS_TPL_WIDTH] + set RX_OS_SAMPLES_PER_CHANNEL [expr $RX_OS_NUM_OF_LANES * 8* $RX_OS_DATAPATH_WIDTH / ($RX_OS_NUM_OF_CONVERTERS * $RX_OS_SAMPLE_WIDTH)] +} + +set adc_data_offload_name adrv903x_rx_data_offload +set adc_data_width [expr $RX_DMA_SAMPLE_WIDTH*$RX_NUM_OF_CONVERTERS*$RX_SAMPLES_PER_CHANNEL] +set adc_dma_data_width $adc_data_width +set adc_fifo_address_width [expr int(ceil(log(($adc_fifo_samples_per_converter*$RX_NUM_OF_CONVERTERS) / ($adc_data_width/$RX_DMA_SAMPLE_WIDTH))/log(2)))] + +set dac_data_offload_name adrv903x_tx_data_offload +set dac_data_width [expr $TX_DMA_SAMPLE_WIDTH*$TX_NUM_OF_CONVERTERS*$TX_SAMPLES_PER_CHANNEL] +set dac_dma_data_width $dac_data_width +set dac_fifo_address_width [expr int(ceil(log(($dac_fifo_samples_per_converter*$TX_NUM_OF_CONVERTERS) / ($dac_data_width/$TX_DMA_SAMPLE_WIDTH))/log(2)))] + +set do_axi_data_width 512 + +set MAX_RX_NUM_OF_LANES [expr $ORX_ENABLE ? 4 : 8] +set MAX_TX_NUM_OF_LANES 8 +set MAX_RX_OS_NUM_OF_LANES [expr $ORX_ENABLE ? 4 : 0] + +# adrv903x + +create_bd_port -dir I core_clk +create_bd_port -dir O rx_os_sync +create_bd_port -dir I rx_os_sysref + +# dac peripherals + +ad_ip_instance axi_clkgen axi_adrv903x_tx_clkgen +ad_ip_parameter axi_adrv903x_tx_clkgen CONFIG.ID 2 +ad_ip_parameter axi_adrv903x_tx_clkgen CONFIG.CLKIN_PERIOD 4 +ad_ip_parameter axi_adrv903x_tx_clkgen CONFIG.VCO_DIV 1 +ad_ip_parameter axi_adrv903x_tx_clkgen CONFIG.VCO_MUL 4 +ad_ip_parameter axi_adrv903x_tx_clkgen CONFIG.CLK0_DIV 4 + +ad_ip_instance axi_adxcvr axi_adrv903x_tx_xcvr +ad_ip_parameter axi_adrv903x_tx_xcvr CONFIG.LINK_MODE $ENCODER_SEL +ad_ip_parameter axi_adrv903x_tx_xcvr CONFIG.NUM_OF_LANES $MAX_TX_NUM_OF_LANES +ad_ip_parameter axi_adrv903x_tx_xcvr CONFIG.QPLL_ENABLE 1 +ad_ip_parameter axi_adrv903x_tx_xcvr CONFIG.TX_OR_RX_N 1 +ad_ip_parameter axi_adrv903x_tx_xcvr CONFIG.SYS_CLK_SEL 3 +ad_ip_parameter axi_adrv903x_tx_xcvr CONFIG.OUT_CLK_SEL 3 + +adi_axi_jesd204_tx_create axi_adrv903x_tx_jesd $TX_NUM_OF_LANES $TX_NUM_LINKS $ENCODER_SEL +ad_ip_parameter axi_adrv903x_tx_jesd/tx CONFIG.TPL_DATA_PATH_WIDTH $TX_DATAPATH_WIDTH + +ad_ip_instance util_upack2 util_adrv903x_tx_upack [list \ + NUM_OF_CHANNELS $TX_NUM_OF_CONVERTERS \ + SAMPLES_PER_CHANNEL $TX_SAMPLES_PER_CHANNEL \ + SAMPLE_DATA_WIDTH $TX_DMA_SAMPLE_WIDTH \ +] + + set dac_data_offload_size [expr $dac_data_width / 8 * 2**$dac_fifo_address_width] + ad_data_offload_create $dac_data_offload_name \ + 1 \ + 0 \ + $dac_data_offload_size \ + $dac_data_width \ + $dac_data_width \ + $do_axi_data_width \ + {} + 1 + +adi_tpl_jesd204_tx_create tx_adrv903x_tpl_core $TX_NUM_OF_LANES \ + $TX_NUM_OF_CONVERTERS \ + $TX_SAMPLES_PER_FRAME \ + $TX_SAMPLE_WIDTH \ + $TX_DATAPATH_WIDTH \ + $TX_DMA_SAMPLE_WIDTH + +ad_ip_parameter tx_adrv903x_tpl_core/dac_tpl_core CONFIG.IQCORRECTION_DISABLE 0 + +ad_ip_instance axi_dmac axi_adrv903x_tx_dma +ad_ip_parameter axi_adrv903x_tx_dma CONFIG.DMA_TYPE_SRC 0 +ad_ip_parameter axi_adrv903x_tx_dma CONFIG.DMA_TYPE_DEST 1 +ad_ip_parameter axi_adrv903x_tx_dma CONFIG.ID 0 +ad_ip_parameter axi_adrv903x_tx_dma CONFIG.SYNC_TRANSFER_START 0 +ad_ip_parameter axi_adrv903x_tx_dma CONFIG.DMA_LENGTH_WIDTH 24 +ad_ip_parameter axi_adrv903x_tx_dma CONFIG.DMA_2D_TRANSFER 0 +ad_ip_parameter axi_adrv903x_tx_dma CONFIG.CYCLIC 1 +ad_ip_parameter axi_adrv903x_tx_dma CONFIG.MAX_BYTES_PER_BURST 4096 +ad_ip_parameter axi_adrv903x_tx_dma CONFIG.DMA_DATA_WIDTH_SRC [expr min(512, $dac_dma_data_width)] +ad_ip_parameter axi_adrv903x_tx_dma CONFIG.DMA_DATA_WIDTH_DEST $dac_dma_data_width +ad_ip_parameter axi_adrv903x_tx_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY + +# adc peripherals + +ad_ip_instance axi_clkgen axi_adrv903x_rx_clkgen +ad_ip_parameter axi_adrv903x_rx_clkgen CONFIG.ID 2 +ad_ip_parameter axi_adrv903x_rx_clkgen CONFIG.CLKIN_PERIOD 4 +ad_ip_parameter axi_adrv903x_rx_clkgen CONFIG.VCO_DIV 1 +ad_ip_parameter axi_adrv903x_rx_clkgen CONFIG.VCO_MUL 4 +ad_ip_parameter axi_adrv903x_rx_clkgen CONFIG.CLK0_DIV 4 + +ad_ip_instance axi_adxcvr axi_adrv903x_rx_xcvr +ad_ip_parameter axi_adrv903x_rx_xcvr CONFIG.LINK_MODE $ENCODER_SEL +ad_ip_parameter axi_adrv903x_rx_xcvr CONFIG.NUM_OF_LANES $MAX_RX_NUM_OF_LANES +ad_ip_parameter axi_adrv903x_rx_xcvr CONFIG.QPLL_ENABLE 0 +ad_ip_parameter axi_adrv903x_rx_xcvr CONFIG.TX_OR_RX_N 0 +ad_ip_parameter axi_adrv903x_rx_xcvr CONFIG.SYS_CLK_SEL 3 +ad_ip_parameter axi_adrv903x_rx_xcvr CONFIG.OUT_CLK_SEL 3 + +adi_axi_jesd204_rx_create axi_adrv903x_rx_jesd $RX_NUM_OF_LANES $RX_NUM_LINKS $ENCODER_SEL +ad_ip_parameter axi_adrv903x_rx_jesd/rx CONFIG.TPL_DATA_PATH_WIDTH $RX_DATAPATH_WIDTH + +ad_ip_instance util_cpack2 util_adrv903x_rx_cpack [list \ + NUM_OF_CHANNELS $RX_NUM_OF_CONVERTERS \ + SAMPLES_PER_CHANNEL $RX_SAMPLES_PER_CHANNEL \ + SAMPLE_DATA_WIDTH $RX_DMA_SAMPLE_WIDTH \ + ] + +set adc_data_offload_size [expr $adc_data_width / 8 * 2**$adc_fifo_address_width] + ad_data_offload_create $adc_data_offload_name \ + 0 \ + 0 \ + $adc_data_offload_size \ + $adc_data_width \ + $adc_data_width \ + $do_axi_data_width \ + {} + 1 + +adi_tpl_jesd204_rx_create rx_adrv903x_tpl_core $RX_NUM_OF_LANES \ + $RX_NUM_OF_CONVERTERS \ + $RX_SAMPLES_PER_FRAME \ + $RX_SAMPLE_WIDTH \ + $RX_DATAPATH_WIDTH \ + $RX_DMA_SAMPLE_WIDTH + +ad_ip_instance axi_dmac axi_adrv903x_rx_dma +ad_ip_parameter axi_adrv903x_rx_dma CONFIG.DMA_TYPE_SRC 1 +ad_ip_parameter axi_adrv903x_rx_dma CONFIG.DMA_TYPE_DEST 0 +ad_ip_parameter axi_adrv903x_rx_dma CONFIG.ID 0 +ad_ip_parameter axi_adrv903x_rx_dma CONFIG.SYNC_TRANSFER_START 0 +ad_ip_parameter axi_adrv903x_rx_dma CONFIG.DMA_LENGTH_WIDTH 24 +ad_ip_parameter axi_adrv903x_rx_dma CONFIG.DMA_2D_TRANSFER 0 +ad_ip_parameter axi_adrv903x_rx_dma CONFIG.MAX_BYTES_PER_BURST 4096 +ad_ip_parameter axi_adrv903x_rx_dma CONFIG.CYCLIC 0 +ad_ip_parameter axi_adrv903x_rx_dma CONFIG.DMA_DATA_WIDTH_SRC $adc_dma_data_width +ad_ip_parameter axi_adrv903x_rx_dma CONFIG.DMA_DATA_WIDTH_DEST [expr min(512, $adc_dma_data_width)] +ad_ip_parameter axi_adrv903x_rx_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY + +set tx_ref_clk tx_ref_clk_0 +set tx_ref_clk_1 tx_ref_clk_1 +set rx_ref_clk rx_ref_clk_0 +set rx_os_ref_clk rx_os_ref_clk_0 + +create_bd_port -dir I $tx_ref_clk +create_bd_port -dir I $tx_ref_clk_1 +create_bd_port -dir I $rx_ref_clk +create_bd_port -dir I $rx_os_ref_clk + +if {$ORX_ENABLE} { + # adc-obs peripherals + + ad_ip_instance axi_clkgen axi_adrv903x_rx_os_clkgen + ad_ip_parameter axi_adrv903x_rx_os_clkgen CONFIG.ID 2 + ad_ip_parameter axi_adrv903x_rx_os_clkgen CONFIG.CLKIN_PERIOD 4 + ad_ip_parameter axi_adrv903x_rx_os_clkgen CONFIG.VCO_DIV 1 + ad_ip_parameter axi_adrv903x_rx_os_clkgen CONFIG.VCO_MUL 4 + ad_ip_parameter axi_adrv903x_rx_os_clkgen CONFIG.CLK0_DIV 4 + + ad_ip_instance axi_adxcvr axi_adrv903x_rx_os_xcvr + ad_ip_parameter axi_adrv903x_rx_os_xcvr CONFIG.LINK_MODE $ENCODER_SEL + ad_ip_parameter axi_adrv903x_rx_os_xcvr CONFIG.NUM_OF_LANES $MAX_RX_OS_NUM_OF_LANES + ad_ip_parameter axi_adrv903x_rx_os_xcvr CONFIG.QPLL_ENABLE 0 + ad_ip_parameter axi_adrv903x_rx_os_xcvr CONFIG.TX_OR_RX_N 0 + ad_ip_parameter axi_adrv903x_rx_os_xcvr CONFIG.SYS_CLK_SEL 3 + ad_ip_parameter axi_adrv903x_rx_os_xcvr CONFIG.OUT_CLK_SEL 3 + + adi_axi_jesd204_rx_create axi_adrv903x_rx_os_jesd $RX_OS_NUM_OF_LANES $RX_OS_NUM_LINKS $ENCODER_SEL + ad_ip_parameter axi_adrv903x_rx_os_jesd/rx CONFIG.TPL_DATA_PATH_WIDTH $RX_OS_DATAPATH_WIDTH + + ad_ip_instance util_cpack2 util_adrv903x_rx_os_cpack [list \ + NUM_OF_CHANNELS $RX_OS_NUM_OF_CONVERTERS \ + SAMPLES_PER_CHANNEL $RX_OS_SAMPLES_PER_CHANNEL \ + SAMPLE_DATA_WIDTH $RX_OS_SAMPLE_WIDTH \ + ] + + adi_tpl_jesd204_rx_create rx_os_adrv903x_tpl_core $RX_OS_NUM_OF_LANES \ + $RX_OS_NUM_OF_CONVERTERS \ + $RX_OS_SAMPLES_PER_FRAME \ + $RX_OS_SAMPLE_WIDTH \ + $RX_OS_DATAPATH_WIDTH \ + $RX_OS_DMA_SAMPLE_WIDTH + + ad_ip_instance axi_dmac axi_adrv903x_rx_os_dma + ad_ip_parameter axi_adrv903x_rx_os_dma CONFIG.DMA_TYPE_SRC 2 + ad_ip_parameter axi_adrv903x_rx_os_dma CONFIG.DMA_TYPE_DEST 0 + ad_ip_parameter axi_adrv903x_rx_os_dma CONFIG.CYCLIC 0 + ad_ip_parameter axi_adrv903x_rx_os_dma CONFIG.SYNC_TRANSFER_START 1 + ad_ip_parameter axi_adrv903x_rx_os_dma CONFIG.DMA_DATA_WIDTH_SRC [expr $RX_OS_SAMPLE_WIDTH * $RX_OS_NUM_OF_CONVERTERS * $RX_OS_SAMPLES_PER_CHANNEL]; + ad_ip_parameter axi_adrv903x_rx_os_dma CONFIG.MAX_BYTES_PER_BURST 4096 + ad_ip_parameter axi_adrv903x_rx_os_dma CONFIG.DMA_DATA_WIDTH_DEST 128 + ad_ip_parameter axi_adrv903x_rx_os_dma CONFIG.FIFO_SIZE 32 + ad_ip_parameter axi_adrv903x_rx_os_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY +} +# common cores + +ad_ip_instance util_adxcvr util_adrv903x_xcvr +ad_ip_parameter util_adrv903x_xcvr CONFIG.RX_NUM_OF_LANES [expr $MAX_RX_NUM_OF_LANES + $MAX_RX_OS_NUM_OF_LANES] +ad_ip_parameter util_adrv903x_xcvr CONFIG.TX_NUM_OF_LANES $MAX_TX_NUM_OF_LANES +ad_ip_parameter util_adrv903x_xcvr CONFIG.LINK_MODE $ENCODER_SEL +ad_ip_parameter util_adrv903x_xcvr CONFIG.RX_LANE_RATE $RX_LANE_RATE +ad_ip_parameter util_adrv903x_xcvr CONFIG.TX_LANE_RATE $TX_LANE_RATE +ad_ip_parameter util_adrv903x_xcvr CONFIG.RX_OUT_DIV 1 +ad_ip_parameter util_adrv903x_xcvr CONFIG.TX_OUT_DIV 1 +ad_ip_parameter util_adrv903x_xcvr CONFIG.CPLL_FBDIV 2 +ad_ip_parameter util_adrv903x_xcvr CONFIG.CPLL_FBDIV_4_5 5 +ad_ip_parameter util_adrv903x_xcvr CONFIG.RX_CLK25_DIV 20 +ad_ip_parameter util_adrv903x_xcvr CONFIG.TX_CLK25_DIV 20 +ad_ip_parameter util_adrv903x_xcvr CONFIG.RX_PMA_CFG 0x280A +ad_ip_parameter util_adrv903x_xcvr CONFIG.RX_CDR_CFG 0x0b000023ff10400020 +ad_ip_parameter util_adrv903x_xcvr CONFIG.QPLL_FBDIV 33 +ad_ip_parameter util_adrv903x_xcvr CONFIG.QPLL_REFCLK_DIV 1 +ad_ip_parameter util_adrv903x_xcvr CONFIG.TX_LANE_INVERT 240 +ad_ip_parameter util_adrv903x_xcvr CONFIG.RX_LANE_INVERT 255 +ad_ip_parameter util_adrv903x_xcvr CONFIG.CPLL_CFG0 0x1fa +ad_ip_parameter util_adrv903x_xcvr CONFIG.CPLL_CFG1 0x23 +ad_ip_parameter util_adrv903x_xcvr CONFIG.CPLL_CFG2 0x2 +ad_ip_parameter util_adrv903x_xcvr CONFIG.A_TXDIFFCTRL 0xC +ad_ip_parameter util_adrv903x_xcvr CONFIG.RXCDR_CFG0 0x3 +ad_ip_parameter util_adrv903x_xcvr CONFIG.RXCDR_CFG2_GEN2 0x269 +ad_ip_parameter util_adrv903x_xcvr CONFIG.RXCDR_CFG2_GEN4 0x164 +ad_ip_parameter util_adrv903x_xcvr CONFIG.RXCDR_CFG3 0x12 +ad_ip_parameter util_adrv903x_xcvr CONFIG.RXCDR_CFG3_GEN2 0x12 +ad_ip_parameter util_adrv903x_xcvr CONFIG.RXCDR_CFG3_GEN3 0x12 +ad_ip_parameter util_adrv903x_xcvr CONFIG.RXCDR_CFG3_GEN4 0x12 +ad_ip_parameter util_adrv903x_xcvr CONFIG.CH_HSPMUX 0x6868 +ad_ip_parameter util_adrv903x_xcvr CONFIG.PREIQ_FREQ_BST 1 +ad_ip_parameter util_adrv903x_xcvr CONFIG.RXPI_CFG0 0x4 +ad_ip_parameter util_adrv903x_xcvr CONFIG.RXPI_CFG1 0x0 +ad_ip_parameter util_adrv903x_xcvr CONFIG.TXPI_CFG 0x0 +ad_ip_parameter util_adrv903x_xcvr CONFIG.TX_PI_BIASSET 3 +ad_ip_parameter util_adrv903x_xcvr CONFIG.POR_CFG 0x0 +ad_ip_parameter util_adrv903x_xcvr CONFIG.QPLL_CFG0 0x333c +ad_ip_parameter util_adrv903x_xcvr CONFIG.QPLL_CFG4 0x45 +ad_ip_parameter util_adrv903x_xcvr CONFIG.PPF0_CFG 0xF00 +ad_ip_parameter util_adrv903x_xcvr CONFIG.QPLL_CP 0xFF +ad_ip_parameter util_adrv903x_xcvr CONFIG.QPLL_CP_G3 0xF +ad_ip_parameter util_adrv903x_xcvr CONFIG.QPLL_LPF 0x31D +ad_ip_parameter util_adrv903x_xcvr CONFIG.RXDFE_KH_CFG2 {0x2631} +ad_ip_parameter util_adrv903x_xcvr CONFIG.RXDFE_KH_CFG3 {0x411C} +ad_ip_parameter util_adrv903x_xcvr CONFIG.RX_WIDEMODE_CDR {"01"} +ad_ip_parameter util_adrv903x_xcvr CONFIG.RX_XMODE_SEL {"0"} +ad_ip_parameter util_adrv903x_xcvr CONFIG.TXPI_CFG0 {0x0000} +ad_ip_parameter util_adrv903x_xcvr CONFIG.TXPI_CFG1 {0x0000} + +# xcvr interfaces + +ad_connect $sys_cpu_resetn util_adrv903x_xcvr/up_rstn +ad_connect $sys_cpu_clk util_adrv903x_xcvr/up_clk + +# Tx +ad_connect adrv903x_tx_device_clk axi_adrv903x_tx_clkgen/clk_0 +ad_connect core_clk axi_adrv903x_tx_clkgen/clk + +ad_xcvrcon util_adrv903x_xcvr axi_adrv903x_tx_xcvr axi_adrv903x_tx_jesd {} {} adrv903x_tx_device_clk $MAX_TX_NUM_OF_LANES {6 7 5 4 2 0 1 3} + +ad_xcvrpll $tx_ref_clk util_adrv903x_xcvr/qpll_ref_clk_0 +ad_xcvrpll axi_adrv903x_tx_xcvr/up_pll_rst util_adrv903x_xcvr/up_qpll_rst_0 +ad_xcvrpll $tx_ref_clk_1 util_adrv903x_xcvr/qpll_ref_clk_4 +ad_xcvrpll axi_adrv903x_tx_xcvr/up_pll_rst util_adrv903x_xcvr/up_qpll_rst_4 + +# Rx +ad_connect adrv903x_rx_device_clk axi_adrv903x_rx_clkgen/clk_0 +ad_connect core_clk axi_adrv903x_rx_clkgen/clk + +ad_xcvrcon util_adrv903x_xcvr axi_adrv903x_rx_xcvr axi_adrv903x_rx_jesd {} {} adrv903x_rx_device_clk $MAX_RX_NUM_OF_LANES {1 3 0 2 7 4 5 6} + +for {set i 0} {$i < 4} {incr i} { + ad_xcvrpll $rx_ref_clk util_adrv903x_xcvr/cpll_ref_clk_$i + ad_xcvrpll axi_adrv903x_rx_xcvr/up_pll_rst util_adrv903x_xcvr/up_cpll_rst_$i + if {$RX_NUM_OF_LANES > 4} { + ad_xcvrpll $rx_ref_clk util_adrv903x_xcvr/cpll_ref_clk_p[expr $i+4] + ad_xcvrpll axi_adrv903x_rx_xcvr/up_pll_rst util_adrv903x_xcvr/up_cpll_rst_$[expr $i+4] + } +} + +if {$ORX_ENABLE} { +# Rx - OBS + ad_connect adrv903x_rx_os_device_clk axi_adrv903x_rx_os_clkgen/clk_0 + ad_connect core_clk axi_adrv903x_rx_os_clkgen/clk + + ad_xcvrcon util_adrv903x_xcvr axi_adrv903x_rx_os_xcvr axi_adrv903x_rx_os_jesd {4 5 6 7} {} adrv903x_rx_os_device_clk $MAX_RX_OS_NUM_OF_LANES {7 4 5 6} + + for {set i 0} {$i < 4} {incr i} { + set ch [expr $i + 4] + ad_xcvrpll $rx_os_ref_clk util_adrv903x_xcvr/cpll_ref_clk_$ch + ad_xcvrpll axi_adrv903x_rx_os_xcvr/up_pll_rst util_adrv903x_xcvr/up_cpll_rst_$ch + } + + delete_bd_objs [get_bd_ports rx_sync_$MAX_RX_NUM_OF_LANES] + delete_bd_objs [get_bd_ports rx_sysref_$MAX_RX_NUM_OF_LANES] + ad_connect rx_os_sync axi_adrv903x_rx_os_jesd_sync + ad_connect rx_os_sysref sysref_3 +} + +# connections (dac) + +ad_connect adrv903x_tx_device_clk tx_adrv903x_tpl_core/link_clk +ad_connect axi_adrv903x_tx_jesd/tx_data tx_adrv903x_tpl_core/link + +ad_connect adrv903x_tx_device_clk util_adrv903x_tx_upack/clk +ad_connect adrv903x_tx_device_clk_rstgen/peripheral_reset util_adrv903x_tx_upack/reset + +for {set i 0} {$i < $TX_NUM_OF_CONVERTERS} {incr i} { + ad_connect tx_adrv903x_tpl_core/dac_enable_$i util_adrv903x_tx_upack/enable_$i + ad_connect util_adrv903x_tx_upack/fifo_rd_data_$i tx_adrv903x_tpl_core/dac_data_$i +} +ad_connect tx_adrv903x_tpl_core/dac_dunf GND +ad_connect tx_adrv903x_tpl_core/dac_valid_0 util_adrv903x_tx_upack/fifo_rd_en +ad_connect util_adrv903x_tx_upack/s_axis_valid VCC +ad_connect $sys_dma_clk axi_adrv903x_tx_dma/m_axis_aclk +ad_connect $sys_dma_resetn axi_adrv903x_tx_dma/m_src_axi_aresetn + +ad_connect adrv903x_tx_device_clk $dac_data_offload_name/m_axis_aclk +ad_connect $sys_dma_clk $dac_data_offload_name/s_axis_aclk +ad_connect adrv903x_tx_device_clk_rstgen/peripheral_aresetn $dac_data_offload_name/m_axis_aresetn +ad_connect $sys_dma_resetn $dac_data_offload_name/s_axis_aresetn +ad_connect $sys_cpu_resetn $dac_data_offload_name/s_axi_aresetn +ad_connect $dac_data_offload_name/s_axis axi_adrv903x_tx_dma/m_axis +ad_connect util_adrv903x_tx_upack/s_axis $dac_data_offload_name/m_axis +ad_connect $dac_data_offload_name/init_req axi_adrv903x_tx_dma/m_axis_xfer_req +ad_connect $dac_data_offload_name/sync_ext GND + +# connections (adc) + +ad_connect adrv903x_rx_device_clk rx_adrv903x_tpl_core/link_clk +ad_connect axi_adrv903x_rx_jesd/rx_sof rx_adrv903x_tpl_core/link_sof +ad_connect axi_adrv903x_rx_jesd/rx_data_tdata rx_adrv903x_tpl_core/link_data +ad_connect axi_adrv903x_rx_jesd/rx_data_tvalid rx_adrv903x_tpl_core/link_valid +ad_connect adrv903x_rx_device_clk util_adrv903x_rx_cpack/clk +ad_connect adrv903x_rx_device_clk_rstgen/peripheral_reset util_adrv903x_rx_cpack/reset + +for {set i 0} {$i < $RX_NUM_OF_CONVERTERS} {incr i} { + ad_connect rx_adrv903x_tpl_core/adc_enable_$i util_adrv903x_rx_cpack/enable_$i + ad_connect rx_adrv903x_tpl_core/adc_data_$i util_adrv903x_rx_cpack/fifo_wr_data_$i +} +ad_connect $sys_dma_resetn axi_adrv903x_rx_dma/m_dest_axi_aresetn +ad_connect $sys_dma_clk axi_adrv903x_rx_dma/s_axis_aclk + +ad_connect rx_adrv903x_tpl_core/adc_valid_0 util_adrv903x_rx_cpack/fifo_wr_en +ad_connect rx_adrv903x_tpl_core/adc_dovf util_adrv903x_rx_cpack/fifo_wr_overflow + +ad_connect adrv903x_rx_device_clk $adc_data_offload_name/s_axis_aclk +ad_connect $sys_dma_clk $adc_data_offload_name/m_axis_aclk +ad_connect adrv903x_rx_device_clk_rstgen/peripheral_aresetn $adc_data_offload_name/s_axis_aresetn +ad_connect $sys_dma_resetn $adc_data_offload_name/m_axis_aresetn +ad_connect $sys_cpu_resetn $adc_data_offload_name/s_axi_aresetn +ad_connect util_adrv903x_rx_cpack/packed_fifo_wr_data $adc_data_offload_name/s_axis_tdata +ad_connect util_adrv903x_rx_cpack/packed_fifo_wr_en $adc_data_offload_name/s_axis_tvalid +ad_connect $adc_data_offload_name/s_axis_tlast GND +ad_connect $adc_data_offload_name/s_axis_tkeep VCC +ad_connect $adc_data_offload_name/m_axis axi_adrv903x_rx_dma/s_axis +ad_connect $adc_data_offload_name/init_req axi_adrv903x_rx_dma/s_axis_xfer_req +ad_connect $adc_data_offload_name/sync_ext GND + +if {$ORX_ENABLE} { + # connections (adc-obs) + ad_connect adrv903x_rx_os_device_clk rx_os_adrv903x_tpl_core/link_clk + ad_connect axi_adrv903x_rx_os_jesd/rx_sof rx_os_adrv903x_tpl_core/link_sof + ad_connect axi_adrv903x_rx_os_jesd/rx_data_tdata rx_os_adrv903x_tpl_core/link_data + ad_connect axi_adrv903x_rx_os_jesd/rx_data_tvalid rx_os_adrv903x_tpl_core/link_valid + + ad_connect adrv903x_rx_os_device_clk util_adrv903x_rx_os_cpack/clk + ad_connect adrv903x_rx_os_device_clk_rstgen/peripheral_reset util_adrv903x_rx_os_cpack/reset + ad_connect adrv903x_rx_os_device_clk axi_adrv903x_rx_os_dma/fifo_wr_clk + + for {set i 0} {$i < $RX_OS_NUM_OF_CONVERTERS} {incr i} { + ad_connect rx_os_adrv903x_tpl_core/adc_enable_$i util_adrv903x_rx_os_cpack/enable_$i + ad_connect rx_os_adrv903x_tpl_core/adc_data_$i util_adrv903x_rx_os_cpack/fifo_wr_data_$i + } + ad_connect $sys_dma_resetn axi_adrv903x_rx_os_dma/m_dest_axi_aresetn + + ad_connect rx_os_adrv903x_tpl_core/adc_valid_0 util_adrv903x_rx_os_cpack/fifo_wr_en + ad_connect rx_os_adrv903x_tpl_core/adc_dovf util_adrv903x_rx_os_cpack/fifo_wr_overflow + + ad_connect util_adrv903x_rx_os_cpack/packed_fifo_wr axi_adrv903x_rx_os_dma/fifo_wr + ad_connect util_adrv903x_rx_os_cpack/packed_sync axi_adrv903x_rx_os_dma/sync +} + +# Sync at TPL level +create_bd_port -dir I ext_sync_in + +# ADC (Rx) external sync +ad_ip_parameter rx_adrv903x_tpl_core/adc_tpl_core CONFIG.EXT_SYNC 1 +ad_connect ext_sync_in rx_adrv903x_tpl_core/adc_tpl_core/adc_sync_in + +ad_ip_instance util_vector_logic manual_sync_or [list \ + C_SIZE 1 \ + C_OPERATION {or} \ +] +ad_connect rx_adrv903x_tpl_core/adc_tpl_core/adc_sync_manual_req_out manual_sync_or/Op1 +ad_connect manual_sync_or/Res rx_adrv903x_tpl_core/adc_tpl_core/adc_sync_manual_req_in + +# DAC (Tx) external sync +ad_ip_parameter tx_adrv903x_tpl_core/dac_tpl_core CONFIG.EXT_SYNC 1 +ad_connect ext_sync_in tx_adrv903x_tpl_core/dac_tpl_core/dac_sync_in + +ad_connect tx_adrv903x_tpl_core/dac_tpl_core/dac_sync_manual_req_out manual_sync_or/Op2 +ad_connect manual_sync_or/Res tx_adrv903x_tpl_core/dac_tpl_core/dac_sync_manual_req_in + +# interconnect (cpu) + +ad_cpu_interconnect 0x44A00000 rx_adrv903x_tpl_core +ad_cpu_interconnect 0x44A04000 tx_adrv903x_tpl_core +ad_cpu_interconnect 0x44A80000 axi_adrv903x_tx_xcvr +ad_cpu_interconnect 0x44A60000 axi_adrv903x_rx_xcvr +ad_cpu_interconnect 0x44A90000 axi_adrv903x_tx_jesd +ad_cpu_interconnect 0x7c420000 axi_adrv903x_tx_dma +ad_cpu_interconnect 0x44AA0000 axi_adrv903x_rx_jesd +ad_cpu_interconnect 0x7c400000 axi_adrv903x_rx_dma +ad_cpu_interconnect 0x7c440000 $dac_data_offload_name +ad_cpu_interconnect 0x7c450000 $adc_data_offload_name +ad_cpu_interconnect 0x43C10000 axi_adrv903x_rx_clkgen +ad_cpu_interconnect 0x43C00000 axi_adrv903x_tx_clkgen +if {$ORX_ENABLE} { + ad_cpu_interconnect 0x44A08000 rx_os_adrv903x_tpl_core + ad_cpu_interconnect 0x7C800000 axi_adrv903x_rx_os_dma + ad_cpu_interconnect 0x43C20000 axi_adrv903x_rx_os_clkgen + ad_cpu_interconnect 0x45A60000 axi_adrv903x_rx_os_xcvr + ad_cpu_interconnect 0x45AA0000 axi_adrv903x_rx_os_jesd +} +ad_mem_hp0_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP0 +ad_mem_hp0_interconnect $sys_cpu_clk axi_adrv903x_rx_xcvr/m_axi +if {$ORX_ENABLE} { + ad_mem_hp0_interconnect $sys_cpu_clk axi_adrv903x_rx_os_xcvr/m_axi +} +# interconnect (mem/dac) + +if {$CACHE_COHERENCY} { + ad_mem_hpc0_interconnect $sys_dma_clk sys_ps8/S_AXI_HPC0 + ad_mem_hpc0_interconnect $sys_dma_clk axi_adrv903x_rx_dma/m_dest_axi + ad_mem_hpc1_interconnect $sys_dma_clk sys_ps8/S_AXI_HPC1 + ad_mem_hpc1_interconnect $sys_dma_clk axi_adrv903x_tx_dma/m_src_axi + if {$ORX_ENABLE} { + ad_mem_hpc1_interconnect $sys_dma_clk axi_adrv903x_rx_os_dma/m_dest_axi + } +} else { + ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2 + ad_mem_hp2_interconnect $sys_dma_clk axi_adrv903x_rx_dma/m_dest_axi + ad_mem_hp3_interconnect $sys_dma_clk sys_ps7/S_AXI_HP3 + ad_mem_hp3_interconnect $sys_dma_clk axi_adrv903x_tx_dma/m_src_axi + if {$ORX_ENABLE} { + ad_mem_hp1_interconnect $sys_dma_clk sys_ps7/S_AXI_HP1 + ad_mem_hp1_interconnect $sys_dma_clk axi_adrv903x_rx_os_dma/m_dest_axi + } +} + +# interrupts + +ad_cpu_interrupt ps-10 mb-7 axi_adrv903x_tx_jesd/irq +ad_cpu_interrupt ps-11 mb-8 axi_adrv903x_rx_jesd/irq +ad_cpu_interrupt ps-13 mb-12 axi_adrv903x_tx_dma/irq +ad_cpu_interrupt ps-14 mb-13 axi_adrv903x_rx_dma/irq +if {$ORX_ENABLE} { + ad_cpu_interrupt ps-12 mb-15 axi_adrv903x_rx_os_jesd/irq + ad_cpu_interrupt ps-15 mb-14 axi_adrv903x_rx_os_dma/irq +} diff --git a/projects/adrv903x/zcu102/Makefile b/projects/adrv903x/zcu102/Makefile new file mode 100644 index 00000000000..f86623cfef1 --- /dev/null +++ b/projects/adrv903x/zcu102/Makefile @@ -0,0 +1,41 @@ +#################################################################################### +## Copyright (c) 2018 - 2025 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := adrv903x_zcu102 + +M_DEPS += ../common/adrv903x_bd.tcl +M_DEPS += ../../scripts/adi_pd.tcl +M_DEPS += ../../common/zcu102/zcu102_system_constr.xdc +M_DEPS += ../../common/zcu102/zcu102_system_bd.tcl +M_DEPS += ../../common/xilinx/data_offload_bd.tcl +M_DEPS += ../../common/xilinx/adi_fir_filter_constr.xdc +M_DEPS += ../../common/xilinx/adi_fir_filter_bd.tcl +M_DEPS += ../../../library/util_hbm/scripts/adi_util_hbm.tcl +M_DEPS += ../../../library/util_cdc/sync_bits.v +M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl +M_DEPS += ../../../library/common/util_pulse_gen.v +M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/common/ad_bus_mux.v + +LIB_DEPS += axi_clkgen +LIB_DEPS += axi_dmac +LIB_DEPS += axi_sysid +LIB_DEPS += data_offload +LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc +LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac +LIB_DEPS += jesd204/axi_jesd204_rx +LIB_DEPS += jesd204/axi_jesd204_tx +LIB_DEPS += jesd204/jesd204_rx +LIB_DEPS += jesd204/jesd204_tx +LIB_DEPS += sysid_rom +LIB_DEPS += util_do_ram +LIB_DEPS += util_hbm +LIB_DEPS += util_pack/util_cpack2 +LIB_DEPS += util_pack/util_upack2 +LIB_DEPS += xilinx/axi_adxcvr +LIB_DEPS += xilinx/util_adxcvr + +include ../../scripts/project-xilinx.mk diff --git a/projects/adrv903x/zcu102/README.md b/projects/adrv903x/zcu102/README.md new file mode 100644 index 00000000000..dd5673614ad --- /dev/null +++ b/projects/adrv903x/zcu102/README.md @@ -0,0 +1,69 @@ + + +# ADRV903X/ZCU102 HDL Project + +- VADJ with which it was tested in hardware: 1.8V + +## Building the project + +The parameters configurable through the `make` command, can be found below, as well as in the **system_project.tcl** file; it contains the default configuration. + +``` +cd projects/adrv903x/zcu102 +make +``` + +All of the RX/TX link modes can be found in the [ADRV9030 data sheet](https://www.analog.com/media/en/technical-documentation/data-sheets/adrv9030.pdf). We offer support for only a few of them. + +If other configurations are desired, then the parameters from the HDL project (see below) need to be changed, as well as the Linux/no-OS project configurations. + +**Warning**: The JESD link mode is configured using the ADRV903x plugin from [ACE](https://wiki.analog.com/resources/tools-software/ace) application. The device tree is the same, regardless of the configuration: [zynqmp-zcu102-rev10-adrv903x.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-adrv903x.dts) + +The overwritable parameters from the environment: + +- JESD_MODE - link layer encoder mode used; + - 8B10B - 8b10b link layer defined in JESD204B + - 64B66B - 64b66b link layer defined in JESD204C +- ORX_ENABLE : Additional data path for RX-OS + - 0 - Disabled (used for profiles with RX-OS disabled) + - 1 - Enabled (used for profiles with RX-OS enabled) +- [RX/TX]_LANE_RATE - lane rate of the [RX/TX] link +- [RX/TX/RX_OS]_JESD_M - [RX/TX/RX_OS] number of converters per link +- [RX/TX/RX_OS]_JESD_L - [RX/TX/RX_OS] number of lanes per link +- [RX/TX/RX_OS]_JESD_S - [RX/TX/RX_OS] number of samples per converter per frame +- [RX/TX/RX_OS]_JESD_NP - [RX/TX/RX_OS] number of bits per sample +- [TX/RX/RX_OS]_TPL_WIDTH - [RX/TX/RX_OS] TPL data path width in bits +- [RX/TX/RX_OS]_NUM_LINKS - [RX/TX/RX_OS] number of links + +### Example configurations + +#### Default configuration + +This specific command is equivalent to running `make` only: + +``` +make JESD_MODE=64B66B \ +RX_LANE_RATE=16.22 \ +TX_LANE_RATE=16.22 \ +ORX_ENABLE=1 \ +RX_NUM_LINKS=1 \ +TX_NUM_LINK=1 \ +RX_OS_NUM_LINKS=1 \ +RX_JESD_M=16 \ +RX_JESD_L=4 \ +RX_JESD_S=1 \ +RX_JESD_NP=16 \ +RX_TPL_WIDTH={} \ +RX_OS_JESD_M=8 \ +RX_OS_JESD_L=4 \ +RX_OS_JESD_S=1 \ +RX_OS_JESD_NP=16 \ +RX_OS_TPL_WIDTH={} \ +TX_JESD_M=16 \ +TX_JESD_L=8 \ +TX_JESD_S=1 \ +TX_JESD_NP=16 \ +TX_TPL_WIDTH={} +``` + +Corresponding device tree: [zynqmp-zcu102-rev10-adrv903x.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-adrv903x.dts) diff --git a/projects/adrv903x/zcu102/system_bd.tcl b/projects/adrv903x/zcu102/system_bd.tcl new file mode 100644 index 00000000000..ed5f2cf0f31 --- /dev/null +++ b/projects/adrv903x/zcu102/system_bd.tcl @@ -0,0 +1,49 @@ +############################################################################### +## Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +## ADC FIFO depth in samples per converter +set adc_fifo_samples_per_converter [expr 32*1024] +## DAC FIFO depth in samples per converter +set dac_fifo_samples_per_converter [expr 32*1024] + +source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl +source $ad_hdl_dir/projects/scripts/adi_pd.tcl + +set mem_init_sys_path [get_env_param ADI_PROJECT_DIR ""]mem_init_sys.txt; + +#system ID +ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 10 +ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/$mem_init_sys_path" +ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 10 + +set sys_cstring "JESD_MODE=$ad_project_params(JESD_MODE)\ +ORX_ENABLE=$ad_project_params(ORX_ENABLE)\ +RX:RATE=$ad_project_params(RX_LANE_RATE)\ +M=$ad_project_params(RX_JESD_M)\ +L=$ad_project_params(RX_JESD_L)\ +S=$ad_project_params(RX_JESD_S)\ +NP=$ad_project_params(RX_JESD_NP)\ +TPL_WIDTH=$ad_project_params(RX_TPL_WIDTH)\ +LINKS=$ad_project_params(RX_NUM_LINKS)\ +TX:RATE=$ad_project_params(TX_LANE_RATE)\ +M=$ad_project_params(TX_JESD_M)\ +L=$ad_project_params(TX_JESD_L)\ +S=$ad_project_params(TX_JESD_S)\ +NP=$ad_project_params(TX_JESD_NP)\ +TPL_WIDTH=$ad_project_params(TX_TPL_WIDTH)\ +LINKS=$ad_project_params(TX_NUM_LINKS)\ +ORX:RATE=$ad_project_params(RX_LANE_RATE)\ +M=$ad_project_params(RX_OS_JESD_M)\ +L=$ad_project_params(RX_OS_JESD_L)\ +S=$ad_project_params(RX_OS_JESD_S)\ +NP=$ad_project_params(RX_OS_JESD_NP)\ +TPL_WIDTH=$ad_project_params(RX_OS_TPL_WIDTH)\ +LINKS=$ad_project_params(RX_OS_NUM_LINKS)" + +sysid_gen_sys_init_file $sys_cstring 10 + +source ../common/adrv903x_bd.tcl + +ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {300} diff --git a/projects/adrv903x/zcu102/system_constr.xdc b/projects/adrv903x/zcu102/system_constr.xdc new file mode 100644 index 00000000000..ebfe1c5adb3 --- /dev/null +++ b/projects/adrv903x/zcu102/system_constr.xdc @@ -0,0 +1,118 @@ +############################################################################### +## Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +#adrv903x + +set_property -dict {PACKAGE_PIN G8} [get_ports ref_clk0_p] ; ## D4 FMC0_GBTCLK0_M2C_C_P MGTREFCLK0P_229 +set_property -dict {PACKAGE_PIN G7} [get_ports ref_clk0_n] ; ## D5 FMC0_GBTCLK0_M2C_C_N MGTREFCLK0N_229 +set_property -dict {PACKAGE_PIN L8} [get_ports ref_clk1_p] ; ## B20 FMC0_GBTCLK1_M2C_C_P MGTREFCLK0P_228 +set_property -dict {PACKAGE_PIN L7} [get_ports ref_clk1_n] ; ## B21 FMC0_GBTCLK1_M2C_C_N MGTREFCLK0N_228 + +set_property -dict {PACKAGE_PIN AA7 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports core_clk_p] ; ## H4 FMC0_CLK0_M2C_P IO_L12P_T1U_N10_GC_66 +set_property -dict {PACKAGE_PIN AA6 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports core_clk_n] ; ## H5 FMC0_CLK0_M2C_N IO_L12N_T1U_N11_GC_66 + +set_property -dict {PACKAGE_PIN P2} [get_ports rx_data_p[0]] ; ## A18 FMC0_DP5_M2C_P MGTHRXP1_228 (rx_data_n[0]) +set_property -dict {PACKAGE_PIN P1} [get_ports rx_data_n[0]] ; ## A19 FMC0_DP5_M2C_N MGTHRXN1_228 (rx_data_p[0]) +set_property -dict {PACKAGE_PIN L4} [get_ports rx_data_p[1]] ; ## A14 FMC0_DP4_M2C_P MGTHRXP3_228 (rx_data_n[1]) +set_property -dict {PACKAGE_PIN L3} [get_ports rx_data_n[1]] ; ## A15 FMC0_DP4_M2C_N MGTHRXN3_228 (rx_data_p[1]) +set_property -dict {PACKAGE_PIN T2} [get_ports rx_data_p[2]] ; ## B16 FMC0_DP6_M2C_P MGTHRXP0_228 (rx_data_n[2]) +set_property -dict {PACKAGE_PIN T1} [get_ports rx_data_n[2]] ; ## B17 FMC0_DP6_M2C_N MGTHRXN0_228 (rx_data_p[2]) +set_property -dict {PACKAGE_PIN M2} [get_ports rx_data_p[3]] ; ## B12 FMC0_DP7_M2C_P MGTHRXP2_228 (rx_data_n[3]) +set_property -dict {PACKAGE_PIN M1} [get_ports rx_data_n[3]] ; ## B13 FMC0_DP7_M2C_N MGTHRXN2_228 (rx_data_p[3]) +set_property -dict {PACKAGE_PIN F2} [get_ports rx_data_p[4]] ; ## A6 FMC0_DP2_M2C_P MGTHRXP3_229 (rx_data_n[4]) +set_property -dict {PACKAGE_PIN F1} [get_ports rx_data_n[4]] ; ## A7 FMC0_DP2_M2C_N MGTHRXN3_229 (rx_data_p[4]) +set_property -dict {PACKAGE_PIN K2} [get_ports rx_data_p[5]] ; ## A10 FMC0_DP3_M2C_P MGTHRXP0_229 (rx_data_n[5]) +set_property -dict {PACKAGE_PIN K1} [get_ports rx_data_n[5]] ; ## A11 FMC0_DP3_M2C_N MGTHRXN0_229 (rx_data_p[5]) +set_property -dict {PACKAGE_PIN J4} [get_ports rx_data_p[6]] ; ## A2 FMC0_DP1_M2C_P MGTHRXP1_229 (rx_data_n[6]) +set_property -dict {PACKAGE_PIN J3} [get_ports rx_data_n[6]] ; ## A3 FMC0_DP1_M2C_N MGTHRXN1_229 (rx_data_p[6]) +set_property -dict {PACKAGE_PIN H2} [get_ports rx_data_p[7]] ; ## C6 FMC0_DP0_M2C_P MGTHRXP2_229 (rx_data_n[7]) +set_property -dict {PACKAGE_PIN H1} [get_ports rx_data_n[7]] ; ## C7 FMC0_DP0_M2C_N MGTHRXN2_229 (rx_data_p[7]) + +set_property -dict {PACKAGE_PIN G4} [get_ports tx_data_p[0]] ; ## C2 FMC0_DP0_C2M_P MGTHTXP2_229 (tx_data_n[0]) +set_property -dict {PACKAGE_PIN G3} [get_ports tx_data_n[0]] ; ## C3 FMC0_DP0_C2M_N MGTHTXN2_229 (tx_data_p[0]) +set_property -dict {PACKAGE_PIN F6} [get_ports tx_data_p[1]] ; ## A26 FMC0_DP2_C2M_P MGTHTXP3_229 (tx_data_n[1]) +set_property -dict {PACKAGE_PIN F5} [get_ports tx_data_n[1]] ; ## A27 FMC0_DP2_C2M_N MGTHTXN3_229 (tx_data_p[1]) +set_property -dict {PACKAGE_PIN H6} [get_ports tx_data_p[2]] ; ## A22 FMC0_DP1_C2M_P MGTHTXP1_229 (tx_data_n[2]) +set_property -dict {PACKAGE_PIN H5} [get_ports tx_data_n[2]] ; ## A23 FMC0_DP1_C2M_N MGTHTXN1_229 (tx_data_p[2]) +set_property -dict {PACKAGE_PIN K6} [get_ports tx_data_p[3]] ; ## A30 FMC0_DP3_C2M_P MGTHTXP0_229 (tx_data_n[3]) +set_property -dict {PACKAGE_PIN K5} [get_ports tx_data_n[3]] ; ## A31 FMC0_DP3_C2M_N MGTHTXN0_229 (tx_data_p[3]) +set_property -dict {PACKAGE_PIN N4} [get_ports tx_data_p[4]] ; ## B32 FMC0_DP7_C2M_P MGTHTXP2_228 (tx_data_p[4]) +set_property -dict {PACKAGE_PIN N3} [get_ports tx_data_n[4]] ; ## B33 FMC0_DP7_C2M_N MGTHTXN2_228 (tx_data_n[4]) +set_property -dict {PACKAGE_PIN R4} [get_ports tx_data_p[5]] ; ## B36 FMC0_DP6_C2M_P MGTHTXP0_228 (tx_data_p[5]) +set_property -dict {PACKAGE_PIN R3} [get_ports tx_data_n[5]] ; ## B37 FMC0_DP6_C2M_N MGTHTXN0_228 (tx_data_n[5]) +set_property -dict {PACKAGE_PIN P6} [get_ports tx_data_p[6]] ; ## A38 FMC0_DP5_C2M_P MGTHTXP1_228 (tx_data_p[6]) +set_property -dict {PACKAGE_PIN P5} [get_ports tx_data_n[6]] ; ## A39 FMC0_DP5_C2M_N MGTHTXN1_228 (tx_data_n[6]) +set_property -dict {PACKAGE_PIN M6} [get_ports tx_data_p[7]] ; ## A34 FMC0_DP4_C2M_P MGTHTXP3_228 (tx_data_p[7]) +set_property -dict {PACKAGE_PIN M5} [get_ports tx_data_n[7]] ; ## A35 FMC0_DP4_C2M_N MGTHTXN3_228 (tx_data_n[7]) + +set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVDS} [get_ports rx_sync_p] ; ## H7 FMC0_LA02_P IO_L23P_T3U_N8_66 +set_property -dict {PACKAGE_PIN V1 IOSTANDARD LVDS} [get_ports rx_sync_n] ; ## H8 FMC0_LA02_N IO_L23N_T3U_N9_66 +set_property -dict {PACKAGE_PIN U11 IOSTANDARD LVDS} [get_ports rx_os_sync_p] ; ## H37 FMC0_LA32_P IO_L6P_T0U_N10_AD6P_67 +set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVDS} [get_ports rx_os_sync_n] ; ## H38 FMC0_LA32_N IO_L6N_T0U_N11_AD6N_67 +set_property -dict {PACKAGE_PIN V8 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_p] ; ## G33 FMC0_LA31_P IO_L7P_T1L_N0_QBC_AD13P_67 +set_property -dict {PACKAGE_PIN V7 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_n] ; ## G34 FMC0_LA31_N IO_L7N_T1L_N1_QBC_AD13N_67 +set_property -dict {PACKAGE_PIN M11 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_1_p] ; ## G27 FMC0_LA25_P IO_L17P_T2U_N8_AD10P_67 +set_property -dict {PACKAGE_PIN L11 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_1_n] ; ## G28 FMC0_LA25_N IO_L17N_T2U_N9_AD10N_67 +set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_2_p] ; ## G36 FMC0_LA33_P IO_L5P_T0U_N8_AD14P_67 +set_property -dict {PACKAGE_PIN V11 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_2_n] ; ## G37 FMC0_LA33_N IO_L5N_T0U_N9_AD14N_67 + +set_property -dict {PACKAGE_PIN AB4 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports sysref_in_p] ; ## D8 FMC0_LA01_CC_P IO_L16P_T2U_N6_QBC_AD3P_66 +set_property -dict {PACKAGE_PIN AC4 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports sysref_in_n] ; ## D9 FMC0_LA01_CC_N IO_L16N_T2U_N7_QBC_AD3N_66 +set_property -dict {PACKAGE_PIN Y2 IOSTANDARD LVDS} [get_ports sysref_out_p] ; ## G9 FMC0_LA03_P IO_L22P_T3U_N6_DBC_AD0P_66 +set_property -dict {PACKAGE_PIN Y1 IOSTANDARD LVDS} [get_ports sysref_out_n] ; ## G10 FMC0_LA03_N IO_L22N_T3U_N7_DBC_AD0N_66 + +set_property -dict {PACKAGE_PIN L10 IOSTANDARD LVCMOS18} [get_ports ad9528_sysref_req] ; ## C27 FMC0_LA27_N IO_L15N_T2L_N5_AD11N_67 +set_property -dict {PACKAGE_PIN AB3 IOSTANDARD LVCMOS18} [get_ports adrv903x_test] ; ## D11 FMC0_LA05_P IO_L20P_T3L_N2_AD1P_66 + +set_property -dict {PACKAGE_PIN AC2 IOSTANDARD LVCMOS18} [get_ports adrv903x_orx0_enable] ; ## C10 FMC0_LA06_P IO_L19P_T3L_N0_DBC_AD9P_66 +set_property -dict {PACKAGE_PIN AC1 IOSTANDARD LVCMOS18} [get_ports adrv903x_orx1_enable] ; ## C11 FMC0_LA06_N IO_L19N_T3L_N1_DBC_AD9N_66 +set_property -dict {PACKAGE_PIN AB8 IOSTANDARD LVCMOS18} [get_ports adrv903x_trx0_enable] ; ## D17 FMC0_LA13_P IO_L8P_T1L_N2_AD5P_66 +set_property -dict {PACKAGE_PIN AC8 IOSTANDARD LVCMOS18} [get_ports adrv903x_trx1_enable] ; ## D18 FMC0_LA13_N IO_L8N_T1L_N3_AD5N_66 +set_property -dict {PACKAGE_PIN W5 IOSTANDARD LVCMOS18} [get_ports adrv903x_trx2_enable] ; ## C14 FMC0_LA10_P IO_L15P_T2L_N4_AD11P_66 +set_property -dict {PACKAGE_PIN W4 IOSTANDARD LVCMOS18} [get_ports adrv903x_trx3_enable] ; ## C15 FMC0_LA10_N IO_L15N_T2L_N5_AD11N_66 +set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS18} [get_ports adrv903x_trx4_enable] ; ## D23 FMC0_LA23_P IO_L19P_T3L_N0_DBC_AD9P_67 +set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS18} [get_ports adrv903x_trx5_enable] ; ## D24 FMC0_LA23_N IO_L19N_T3L_N1_DBC_AD9N_67 +set_property -dict {PACKAGE_PIN AC7 IOSTANDARD LVCMOS18} [get_ports adrv903x_trx6_enable] ; ## C18 FMC0_LA14_P IO_L7P_T1L_N0_QBC_AD13P_66 +set_property -dict {PACKAGE_PIN AC6 IOSTANDARD LVCMOS18} [get_ports adrv903x_trx7_enable] ; ## C19 FMC0_LA14_N IO_L7N_T1L_N1_QBC_AD13N_66 + +set_property -dict {PACKAGE_PIN Y10 IOSTANDARD LVCMOS18} [get_ports adrv903x_gpio[0]] ; ## H19 FMC0_LA15_P IO_L6P_T0U_N10_AD6P_66 +set_property -dict {PACKAGE_PIN Y9 IOSTANDARD LVCMOS18} [get_ports adrv903x_gpio[1]] ; ## H20 FMC0_LA15_N IO_L6N_T0U_N11_AD6N_66 +set_property -dict {PACKAGE_PIN Y12 IOSTANDARD LVCMOS18} [get_ports adrv903x_gpio[2]] ; ## G18 FMC0_LA16_P IO_L5P_T0U_N8_AD14P_66 +set_property -dict {PACKAGE_PIN AA12 IOSTANDARD LVCMOS18} [get_ports adrv903x_gpio[3]] ; ## G19 FMC0_LA16_N IO_L5N_T0U_N9_AD14N_66 +set_property -dict {PACKAGE_PIN P12 IOSTANDARD LVCMOS18} [get_ports adrv903x_gpio[4]] ; ## H25 FMC0_LA21_P IO_L21P_T3L_N4_AD8P_67 +set_property -dict {PACKAGE_PIN N12 IOSTANDARD LVCMOS18} [get_ports adrv903x_gpio[5]] ; ## H26 FMC0_LA21_N IO_L21N_T3L_N5_AD8N_67 +set_property -dict {PACKAGE_PIN N9 IOSTANDARD LVCMOS18} [get_ports adrv903x_gpio[6]] ; ## C22 FMC0_LA18_CC_P IO_L16P_T2U_N6_QBC_AD3P_67 +set_property -dict {PACKAGE_PIN N8 IOSTANDARD LVCMOS18} [get_ports adrv903x_gpio[7]] ; ## C23 FMC0_LA18_CC_N IO_L16N_T2U_N7_QBC_AD3N_67 +set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS18} [get_ports adrv903x_gpio[8]] ; ## H22 FMC0_LA19_P IO_L23P_T3U_N8_67 +set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS18} [get_ports adrv903x_gpio[9]] ; ## H23 FMC0_LA19_N IO_L23N_T3U_N9_67 +set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS18} [get_ports adrv903x_gpio[10]] ; ## G24 FMC0_LA22_P IO_L20P_T3L_N2_AD1P_67 +set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS18} [get_ports adrv903x_gpio[11]] ; ## G25 FMC0_LA22_N IO_L20N_T3L_N3_AD1N_67 +set_property -dict {PACKAGE_PIN AA2 IOSTANDARD LVCMOS18} [get_ports adrv903x_gpio[12]] ; ## H10 FMC0_LA04_P IO_L21P_T3L_N4_AD8P_66 +set_property -dict {PACKAGE_PIN AA1 IOSTANDARD LVCMOS18} [get_ports adrv903x_gpio[13]] ; ## H11 FMC0_LA04_N IO_L21N_T3L_N5_AD8N_66 +set_property -dict {PACKAGE_PIN U9 IOSTANDARD LVCMOS18} [get_ports adrv903x_gpio[14]] ; ## G30 FMC0_LA29_P IO_L9P_T1L_N4_AD12P_67 +set_property -dict {PACKAGE_PIN U8 IOSTANDARD LVCMOS18} [get_ports adrv903x_gpio[15]] ; ## G31 FMC0_LA29_N IO_L9N_T1L_N5_AD12N_67 +set_property -dict {PACKAGE_PIN W7 IOSTANDARD LVCMOS18} [get_ports adrv903x_gpio[16]] ; ## G15 FMC0_LA12_P IO_L9P_T1L_N4_AD12P_66 +set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVCMOS18} [get_ports adrv903x_gpio[17]] ; ## G16 FMC0_LA12_N IO_L9N_T1L_N5_AD12N_66 +set_property -dict {PACKAGE_PIN AC3 IOSTANDARD LVCMOS18} [get_ports adrv903x_gpio[18]] ; ## D12 FMC0_LA05_N IO_L20N_T3L_N3_AD1N_66 +set_property -dict {PACKAGE_PIN N13 IOSTANDARD LVCMOS18} [get_ports adrv903x_gpio[19]] ; ## G21 FMC0_LA20_P IO_L22P_T3U_N6_DBC_AD0P_67 +set_property -dict {PACKAGE_PIN V6 IOSTANDARD LVCMOS18} [get_ports adrv903x_gpio[20]] ; ## H34 FMC0_LA30_P IO_L8P_T1L_N2_AD5P_67 +set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS18} [get_ports adrv903x_gpio[21]] ; ## H35 FMC0_LA30_N IO_L8N_T1L_N3_AD5N_67 +set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVCMOS18} [get_ports adrv903x_gpio[22]] ; ## H28 FMC0_LA24_P IO_L18P_T2U_N10_AD2P_67 +set_property -dict {PACKAGE_PIN K12 IOSTANDARD LVCMOS18} [get_ports adrv903x_gpio[23]] ; ## H29 FMC0_LA24_N IO_L18N_T2U_N11_AD2N_67 + +set_property -dict {PACKAGE_PIN M10 IOSTANDARD LVCMOS18} [get_ports ad9528_reset_b] ; ## C26 FMC0_LA27_P IO_L15P_T2L_N4_AD11P_67 +set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVCMOS18} [get_ports adrv903x_reset_b] ; ## G22 FMC0_LA20_N IO_L22N_T3U_N7_DBC_AD0N_67 + +set_property -dict {PACKAGE_PIN W2 IOSTANDARD LVCMOS18} [get_ports spi_csn_adrv903x] ; ## D14 FMC0_LA09_P IO_L24P_T3U_N10_66 +set_property -dict {PACKAGE_PIN W1 IOSTANDARD LVCMOS18} [get_ports spi_csn_ad9528] ; ## D15 FMC0_LA09_N IO_L24N_T3U_N11_66 +set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS18} [get_ports spi_clk] ; ## H13 FMC0_LA07_P IO_L18P_T2U_N10_AD2P_66 +set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVCMOS18} [get_ports spi_miso] ; ## G12 FMC0_LA08_P IO_L17P_T2U_N8_AD10P_66 +set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVCMOS18} [get_ports spi_mosi] ; ## H14 FMC0_LA07_N IO_L18N_T2U_N11_AD2N_66 + +# clocks + +create_clock -period 4.069 -name device_clk [get_ports core_clk_p] +create_clock -period 2.035 -name tx_ref_clk [get_ports ref_clk0_p] +create_clock -period 2.035 -name rx_ref_clk [get_ports ref_clk1_p] diff --git a/projects/adrv903x/zcu102/system_project.tcl b/projects/adrv903x/zcu102/system_project.tcl new file mode 100644 index 00000000000..f517ba733d1 --- /dev/null +++ b/projects/adrv903x/zcu102/system_project.tcl @@ -0,0 +1,63 @@ +############################################################################### +## Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +# get_env_param retrieves parameter value from the environment if exists, +# other case use the default value +# +# Use over-writable parameters from the environment. +# +# Parameter description: +# Parameter description: +# JESD_MODE : Used link layer encoder mode +# 64B66B - 64b66b link layer defined in JESD 204C +# 8B10B - 8b10b link layer defined in JESD 204B +# ORX_ENABLE : Additional data path for RX-OS +# 0 - Disabled (used for profiles with RX-OS disabled) +# 1 - Enabled (used for profiles with RX-OS enabled) +# TX_LANE_RATE : Transceiver line rate of the TX link +# RX_LANE_RATE : Transceiver line rate of the RX link +# [TX/RX/RX_OS]_NUM_LINKS : Number of links +# [TX/RX/RX_OS]_JESD_M : Number of converters per link +# [TX/RX/RX_OS]_JESD_L : Number of lanes per link +# [TX/RX/RX_OS]_JESD_S : Number of samples per frame +# [TX/RX/RX_OS]_JESD_NP : Number of bits per sample +# [TX/RX/RX_OS]_TPL_WIDTH : TPL data path width in bits + +adi_project adrv903x_zcu102 0 [list \ + JESD_MODE [get_env_param JESD_MODE 64B66B] \ + ORX_ENABLE [get_env_param ORX_ENABLE 1] \ + TX_LANE_RATE [get_env_param TX_LANE_RATE 16.22] \ + RX_LANE_RATE [get_env_param RX_LANE_RATE 16.22] \ + TX_NUM_LINKS [get_env_param TX_NUM_LINKS 1] \ + RX_NUM_LINKS [get_env_param RX_NUM_LINKS 1] \ + RX_OS_NUM_LINKS [get_env_param RX_OS_NUM_LINKS 1] \ + TX_JESD_M [get_env_param TX_JESD_M 16] \ + TX_JESD_L [get_env_param TX_JESD_L 8] \ + TX_JESD_S [get_env_param TX_JESD_S 1] \ + TX_JESD_NP [get_env_param TX_JESD_NP 16] \ + TX_TPL_WIDTH [get_env_param TX_TPL_WIDTH {}] \ + RX_JESD_M [get_env_param RX_JESD_M 16] \ + RX_JESD_L [get_env_param RX_JESD_L 4] \ + RX_JESD_S [get_env_param RX_JESD_S 1] \ + RX_JESD_NP [get_env_param RX_JESD_NP 16] \ + RX_TPL_WIDTH [get_env_param RX_TPL_WIDTH {}] \ + RX_OS_JESD_M [get_env_param RX_OS_JESD_M 8] \ + RX_OS_JESD_L [get_env_param RX_OS_JESD_L 4] \ + RX_OS_JESD_S [get_env_param RX_OS_JESD_S 1] \ + RX_OS_JESD_NP [get_env_param RX_OS_JESD_NP 16] \ + RX_OS_TPL_WIDTH [get_env_param RX_OS_TPL_WIDTH {}] \ +] + +adi_project_files adrv903x_zcu102 [list \ + "system_top.v" \ + "system_constr.xdc"\ + "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/projects/common/zcu102/zcu102_system_constr.xdc" ] + +adi_project_run adrv903x_zcu102 diff --git a/projects/adrv903x/zcu102/system_top.v b/projects/adrv903x/zcu102/system_top.v new file mode 100644 index 00000000000..099991c8a34 --- /dev/null +++ b/projects/adrv903x/zcu102/system_top.v @@ -0,0 +1,256 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + input core_clk_p, + input core_clk_n, + input ref_clk0_p, + input ref_clk0_n, + input ref_clk1_p, + input ref_clk1_n, + input [ 7:0] rx_data_p, + input [ 7:0] rx_data_n, + output [ 7:0] tx_data_p, + output [ 7:0] tx_data_n, + output rx_sync_p, + output rx_sync_n, + output rx_os_sync_p, + output rx_os_sync_n, + input tx_sync_p, + input tx_sync_n, + input tx_sync_1_p, + input tx_sync_1_n, + input tx_sync_2_p, + input tx_sync_2_n, + + input sysref_in_p, + input sysref_in_n, + output sysref_out_p, + output sysref_out_n, + + input [12:0] gpio_bd_i, + output [ 7:0] gpio_bd_o, + + output spi_csn_ad9528, + output spi_csn_adrv903x, + output spi_clk, + output spi_mosi, + input spi_miso, + + inout ad9528_reset_b, + inout ad9528_sysref_req, + inout adrv903x_trx0_enable, + inout adrv903x_trx1_enable, + inout adrv903x_trx2_enable, + inout adrv903x_trx3_enable, + inout adrv903x_trx4_enable, + inout adrv903x_trx5_enable, + inout adrv903x_trx6_enable, + inout adrv903x_trx7_enable, + inout adrv903x_orx0_enable, + inout adrv903x_orx1_enable, + inout adrv903x_test, + inout adrv903x_reset_b, + + inout [23:0] adrv903x_gpio +); + + // internal signals + + wire [94:0] gpio_i; + wire [94:0] gpio_o; + wire [94:0] gpio_t; + wire [ 2:0] spi_csn; + wire rx_sync; + wire rx_os_sync; + wire tx_sync; + wire sysref; + wire ref_clk0; + wire ref_clk1; + + assign gpio_i[94:70] = gpio_o[94:70]; + assign gpio_i[31:21] = gpio_o[31:21]; + + assign sysref_out = 0; + + // instantiations + + IBUFDS i_ibufds_core_clk ( + .I (core_clk_p), + .IB (core_clk_n), + .O (core_clk)); + + BUFG i_ibufg_core_clk ( + .I (core_clk), + .O (core_clk_buf)); + + IBUFDS_GTE4 i_ibufds_ref_clk0 ( + .CEB (1'd0), + .I (ref_clk0_p), + .IB (ref_clk0_n), + .O (ref_clk0), + .ODIV2 (ref_clk0_odiv2)); + + IBUFDS_GTE4 i_ibufds_ref_clk1 ( + .CEB (1'd0), + .I (ref_clk1_p), + .IB (ref_clk1_n), + .O (ref_clk1), + .ODIV2 (ref_clk1_odiv2)); + + OBUFDS i_obufds_rx_sync ( + .I (rx_sync), + .O (rx_sync_p), + .OB (rx_sync_n)); + + OBUFDS i_obufds_rx_os_sync ( + .I (rx_os_sync), + .O (rx_os_sync_p), + .OB (rx_os_sync_n)); + + OBUFDS i_obufds_sysref_out ( + .I (sysref_out), + .O (sysref_out_p), + .OB (sysref_out_n)); + + IBUFDS i_ibufds_tx_sync ( + .I (tx_sync_p), + .IB (tx_sync_n), + .O (tx_sync)); + + IBUFDS i_ibufds_tx_sync_1 ( + .I (tx_sync_1_p), + .IB (tx_sync_1_n), + .O (tx_sync_1)); + + IBUFDS i_ibufds_tx_sync_2 ( + .I (tx_sync_2_p), + .IB (tx_sync_2_n), + .O (tx_sync_2)); + + IBUFDS i_ibufds_sysref ( + .I (sysref_in_p), + .IB (sysref_in_n), + .O (sysref)); + + ad_iobuf #( + .DATA_WIDTH(38) + ) i_iobuf ( + .dio_t ({gpio_t[69:32]}), + .dio_i ({gpio_o[69:32]}), + .dio_o ({gpio_i[69:32]}), + .dio_p ({ ad9528_reset_b, // 69 + ad9528_sysref_req, // 68 + adrv903x_trx0_enable, // 67 + adrv903x_trx1_enable, // 66 + adrv903x_trx2_enable, // 65 + adrv903x_trx3_enable, // 64 + adrv903x_trx4_enable, // 63 + adrv903x_trx5_enable, // 62 + adrv903x_trx6_enable, // 61 + adrv903x_trx7_enable, // 60 + adrv903x_orx0_enable, // 59 + adrv903x_orx1_enable, // 58 + adrv903x_test, // 57 + adrv903x_reset_b, // 56 + adrv903x_gpio})); // 55-32 + + assign gpio_i[ 7: 0] = gpio_o[ 7: 0]; + assign gpio_i[20: 8] = gpio_bd_i; + assign gpio_bd_o = gpio_o[ 7: 0]; + + assign spi_csn_ad9528 = spi_csn[1]; + assign spi_csn_adrv903x = spi_csn[0]; + + system_wrapper i_system_wrapper ( + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .core_clk(core_clk_buf), + .rx_data_0_n (rx_data_n[2]), + .rx_data_0_p (rx_data_p[2]), + .rx_data_1_n (rx_data_n[0]), + .rx_data_1_p (rx_data_p[0]), + .rx_data_2_n (rx_data_n[3]), + .rx_data_2_p (rx_data_p[3]), + .rx_data_3_n (rx_data_n[1]), + .rx_data_3_p (rx_data_p[1]), + .rx_data_4_n (rx_data_n[5]), + .rx_data_4_p (rx_data_p[5]), + .rx_data_5_n (rx_data_n[6]), + .rx_data_5_p (rx_data_p[6]), + .rx_data_6_n (rx_data_n[7]), + .rx_data_6_p (rx_data_p[7]), + .rx_data_7_n (rx_data_n[4]), + .rx_data_7_p (rx_data_p[4]), + .rx_ref_clk_0 (ref_clk0), + .rx_sync_0 (rx_sync), + .rx_sysref_0 (sysref), + .rx_os_ref_clk_0 (ref_clk0), + .rx_os_sync (rx_os_sync), + .rx_os_sysref (sysref), + .spi0_sclk (spi_clk), + .spi0_csn (spi_csn), + .spi0_miso (spi_miso), + .spi0_mosi (spi_mosi), + .spi1_sclk (), + .spi1_csn (), + .spi1_miso (1'b0), + .spi1_mosi (), + .tx_data_0_n (tx_data_n[5]), + .tx_data_0_p (tx_data_p[5]), + .tx_data_1_n (tx_data_n[6]), + .tx_data_1_p (tx_data_p[6]), + .tx_data_2_n (tx_data_n[4]), + .tx_data_2_p (tx_data_p[4]), + .tx_data_3_n (tx_data_n[7]), + .tx_data_3_p (tx_data_p[7]), + .tx_data_4_n (tx_data_n[3]), + .tx_data_4_p (tx_data_p[3]), + .tx_data_5_n (tx_data_n[2]), + .tx_data_5_p (tx_data_p[2]), + .tx_data_6_n (tx_data_n[0]), + .tx_data_6_p (tx_data_p[0]), + .tx_data_7_n (tx_data_n[1]), + .tx_data_7_p (tx_data_p[1]), + .tx_ref_clk_0 (ref_clk0), + .tx_ref_clk_1 (ref_clk0), + .tx_sync_0 (tx_sync), + .tx_sysref_0 (sysref), + .ext_sync_in (sysref)); + +endmodule From fee6bcfd4c8ba934dbe4b1817d3bff269727df1a Mon Sep 17 00:00:00 2001 From: AndrDragomir Date: Mon, 25 Aug 2025 14:22:49 +0300 Subject: [PATCH 2/2] docs: Add ADRV903x documentation Signed-off-by: AndrDragomir --- .../adrv903x/adrv903x_zcu102_clocking.svg | 4 + .../adrv903x/adrv903x_zcu102_jesd204c.svg | 6839 +++++++++++++++++ docs/projects/adrv903x/index.rst | 460 ++ docs/projects/index.rst | 1 + 4 files changed, 7304 insertions(+) create mode 100644 docs/projects/adrv903x/adrv903x_zcu102_clocking.svg create mode 100644 docs/projects/adrv903x/adrv903x_zcu102_jesd204c.svg create mode 100644 docs/projects/adrv903x/index.rst diff --git a/docs/projects/adrv903x/adrv903x_zcu102_clocking.svg b/docs/projects/adrv903x/adrv903x_zcu102_clocking.svg new file mode 100644 index 00000000000..c842b58870c --- /dev/null +++ b/docs/projects/adrv903x/adrv903x_zcu102_clocking.svg @@ -0,0 +1,4 @@ + + + +
AD9528
FPGA
REFCLK0
SYSREF
CORE_CLK
OUT3
OUT12
OUT13
OUT1 - DEVCLK
OUT0 - SYSREF
REFCLK1
OUT11
 \ No newline at end of file diff --git a/docs/projects/adrv903x/adrv903x_zcu102_jesd204c.svg b/docs/projects/adrv903x/adrv903x_zcu102_jesd204c.svg new file mode 100644 index 00000000000..653797007d5 --- /dev/null +++ b/docs/projects/adrv903x/adrv903x_zcu102_jesd204c.svg @@ -0,0 +1,6839 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + TX Device Clock = TX Lane Rate/66 = 245.76MHz + + 4x64bits@245.76MHz + 256bits@245.76MHz + 8x64bits@245.76MHz + 512bits@245.76MHz + 1 x32 samples + 16x2 samples + 512bits@245.76MHz + RX Device Clock = RX Lane Rate/66 = 245.76MHz + + + + tx_data_7_p, n + RX Lane Rate 16.22Gbps  + + + tx_data_0_p, n + + + + AXI_ADXCVR + + TX Lane Rate16.22Gbps + + + +   + + RX JESD LINK + + + + + 128b + + + UTIL_UPACK + + clk + + + DATA_OFFLOAD + AXI_DMAC + JESD PHY + 1MB + m_axis_clk + + + RX JESD TPL + + link_clk + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Ethernet + UART + GPIO + DDRx + SPI + I2C + Interrupts + Timer + + + + ZynqMP + + + + + Receive path + + + + Transmit path + + + + Clock domain + + + + + AXI_ADXCVR + + + + + + AXI_DMAC + + + + + + + + DATA_OFFLOAD + + + + + 128b + + device_clk + link_clk + rx_0 + + + UTIL_ADXCVR + + QPLL,CPLL* + 256b@250MHz + + + + FMC CONNECTOR + + MEMORY INTERCONNECT + + + + rx_data_3_p, n + + + rx_data_0_p, n + + ZCU102 + + rx_3 + + ADRV903x + SYS_CPU_CLKFCLK_CLK0 = 100MHz + + + + + 512b + + + + + + + + + + 512b + + + + + + + link_clk + TX JESD TPL + + TX JESD LINK + + + + + + + 32b + 32b + + + + + + + 32b + 32b + + + + + + + 512b + + + + 256b + + 256b + + 256b + + JESD204C in subclass 1 + tx_0 + + tx_7 + + + + device_clk + + + + + + + + link_clk + + + + 1 x16 samples + 512b@250MHz + REF_CLK = 491.52MHz + 1 x32 samples + 256bits@245.76MHz + + RX OS JESD LINK + + + RX OS JESD TPL + + link_clk + + + AXI_DMAC + + + + + UTIL_CPACK + + + device_clk + link_clk + 256b@250MHz + + + 128b + + + + 256b + + + + 1 x16 samples + RX_OS Lane Rate 16.22Gbps  +   + + + + AXI_ADXCVR + + + + + + + + ref_clk0_p, n + + rx_data_7_p, n + + + rx_data_4_p, n + + + core_clk_p, n + core_clk + + + RX_OS Device Clock = RX_OS Lane Rate/66 = 245.76MHz + + 4x64bits@245.76MHz + + + rx_4 + rx_7 + + + 256b + + + + + + AXICLKGEN + + + + BUF + + + + + AXICLKGEN + + + + + + + AXICLKGEN + + + + AXICLKGEN + + + + + SYS_DMA_CLKFCLK_CLK1 = 300MHz + + + 32b + + 32b + + 32b + + 32b + + 32b + + + + UTIL_CPACK + + 16x1 samples + 256bits@245.76MHz + s_axis_clk + 1MB + clk + clk + + + 32b + + 32b + + 32b + + 32b + + 32b + + 8x2 samples + tx_out_clk_div2_0 + + + rx_out_clk_div2_0 + + rx_out_clk_div2_4 + + + + + + + + + + diff --git a/docs/projects/adrv903x/index.rst b/docs/projects/adrv903x/index.rst new file mode 100644 index 00000000000..c8f8f7b59f5 --- /dev/null +++ b/docs/projects/adrv903x/index.rst @@ -0,0 +1,460 @@ +.. _adrv903x: + +ADRV903x HDL reference design +=============================================================================== + +The ADRV903x is a highly integrated, system on chip (SoC) radio frequency (RF) +agile transceiver with integrated digital front end (DFE). The SoC contains +eight transmitters, two observation receivers for monitoring transmitter +channels, eight receivers, integrated LO and clock synthesizers, and digital +signal processing functions. The SoC meets the high radio performance and low +power consumption demanded by cellular infrastructure applications, such as +software-definded radios, portable instrumentation and military communications. + +Supported devices +------------------------------------------------------------------------------- + +- :adi:`ADRV9032R` + +Supported boards +------------------------------------------------------------------------------- + +- :adi:`EVAL-ADRV903x` + +Supported carriers +------------------------------------------------------------------------------- + +.. list-table:: + :widths: 35 35 30 + :header-rows: 1 + + * - Evaluation board + - Carrier + - FMC slot + * - EVAL-ADRV903x + - :xilinx:`ZCU102` + - FMC HPC0 + +Block design +------------------------------------------------------------------------------- + +Block diagram +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The data path and clock domains are depicted in the below diagrams: + +Example block design for Single link +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +.. image:: adrv903x_zcu102_jesd204c.svg + :width: 800 + :align: center + :alt: ADRV903x JESD204C M=16 L=8 block diagram + +The Rx links (ADC Path) operate with the following parameters: + +- Rx Deframer parameters: L=4, M=16, F=8, S=1, NP=16, N=16 +- Sample Rate: 245.76 MSPS +- Dual link: No +- RX_DEVICE_CLK: 245.76 MHz (Lane Rate/66) +- REF_CLK: 491.52 MHz +- JESD204C Lane Rate: 16.22 Gbps +- QPLL0 + +The Tx links (DAC Path) operate with the following parameters: + +- Tx Deframer parameters: L=8, M=16, F=4, S=1, NP=16, N=16 +- Sample Rate: 491.52 MSPS +- Dual link: No +- TX_DEVICE_CLK: 245.76 MHz (Lane Rate/66) +- REF_CLK: 491.52 MHz +- JESD204C Lane Rate: 16.22 Gbps +- QPLL0 + +The ORx links (ADC Obs Path) operate with the following parameters: + +- ORx Deframer parameters: L=4, M=8, F=4, S=1, NP=16, N=16 +- Sample Rate: 491.52 MSPS +- Dual link: No +- ORX_DEVICE_CLK: 245.76 MHz (Lane Rate/66) +- REF_CLK: 491.52 MHz +- JESD204C Lane Rate: 16.22 Gbps +- QPLL0 + +Configuration modes +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The block design supports configuration of parameters and scales. + +We have listed a couple of examples at section +`Building the HDL project`_ and the default modes +for each project. + +.. note:: + + The parameters for Rx or Tx links can be changed from the + **system_project.tcl** file, located in + hdl/projects/adrv903x/$CARRIER/system_project.tcl + +.. math:: + Lane Rate = Sample Rate*\frac{M}{L}*N'* \frac{66}{64} + +The following are the parameters of this project that can be configured: + +- JESD_MODE: used link layer encoder mode + + - 64B66B - 64b66b link layer defined in JESD204C + - 8B10B - 8b10b link layer defined in JESD204B + +- ORX_ENABLE : Additional data path for RX-OS + + - 0 - Disabled (used for profiles with RX-OS disabled) + - 1 - Enabled (used for profiles with RX-OS enabled) + +- RX_LANE_RATE: Transceiver lane rate of the Rx link +- TX_LANE_RATE: Transceiver lane rate of the Tx link +- [RX/TX/RX_OS]_JESD_M: number of converters per link +- [RX/TX/RX_OS]_JESD_L: number of lanes per link +- [RX/TX/RX_OS]_JESD_S: number of samples per frame +- [RX/TX/RX_OS]_JESD_NP: number of bits per sample +- [RX/TX/RX_OS]_TPL_WIDTH : TPL data path width in bits +- [RX/TX/RX_OS]_NUM_LINKS: number of links + +Clock scheme +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. image:: adrv903x_zcu102_clocking.svg + :width: 500 + :align: center + :alt: ADRV903x ZCU102 clock scheme + +CPU/Memory interconnects addresses +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The addresses are dependent on the architecture of the FPGA, having an offset +added to the base address from HDL (see more at :ref:`architecture cpu-intercon-addr`). + +========================= =========== +Instance ZynqMP +========================= =========== +axi_adrv903x_tx_jesd 0x84A9_0000 +axi_adrv903x_rx_jesd 0x84AA_0000 +axi_adrv903x_rx_os_jesd 0x85AA_0000 +axi_adrv903x_tx_dma 0x9C42_0000 +axi_adrv903x_rx_dma 0x9C40_0000 +axi_adrv903x_rx_os_dma 0x9C80_0000 +tx_adrv903x_tpl_core 0x84A0_4000 +rx_adrv903x_tpl_core 0x84A0_0000 +rx_os_adrv903x_tpl_core 0x84A0_8000 +axi_adrv903x_tx_xcvr 0x84A8_0000 +axi_adrv903x_rx_xcvr 0x84A6_0000 +axi_adrv903x_rx_os_xcvr 0x85A6_0000 +axi_adrv903x_tx_clkgen 0x83C0_0000 +axi_adrv903x_rx_clkgen 0x83C1_0000 +axi_adrv903x_rx_os_clkgen 0x83C2_0000 +adrv903x_tx_data_offload 0x9c44_0000 +adrv903x_rx_data_offload 0x9c45_0000 +========================= =========== + +SPI connections +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. list-table:: + :widths: 25 25 25 25 + :header-rows: 1 + + * - SPI type + - SPI manager instance + - SPI subordinate + - CS + * - PS + - spi0 + - ADRV903x + - 0 + * - + - + - AD9528 + - 1 + +GPIOs +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. list-table:: + :widths: 25 20 20 15 + :header-rows: 2 + + * - GPIO signal + - Direction + - HDL GPIO EMIO + - Software GPIO + * - + - (from FPGA view) + - + - Zynq MP + * - ad9528_reset_b + - INOUT + - 69 + - 147 + * - ad9528_sysref_req + - INOUT + - 68 + - 146 + * - adrv903x_trx0_enable + - INOUT + - 67 + - 145 + * - adrv903x_trx1_enable + - INOUT + - 66 + - 144 + * - adrv903x_trx2_enable + - INOUT + - 65 + - 143 + * - adrv903x_trx3_enable + - INOUT + - 64 + - 142 + * - adrv903x_trx4_enable + - INOUT + - 63 + - 141 + * - adrv903x_trx5_enable + - INOUT + - 62 + - 140 + * - adrv903x_trx6_enable + - INOUT + - 61 + - 139 + * - adrv903x_trx7_enable + - INOUT + - 60 + - 138 + * - adrv903x_orx0_enable + - INOUT + - 59 + - 137 + * - adrv903x_orx1_enable + - INOUT + - 58 + - 136 + * - adrv903x_test + - INOUT + - 57 + - 135 + * - adrv903x_reset_b + - INOUT + - 56 + - 134 + * - adrv903x_gpio[0:23] + - INOUT + - 55:32 + - 133:110 + +Interrupts +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Below are the Programmable Logic interrupts used in this project. + +======================= === ============ ============= +Instance name HDL Linux ZynqMP Actual ZynqMP +======================= === ============ ============= +axi_adrv903x_tx_jesd 10 106 138 +axi_adrv903x_rx_jesd 11 107 139 +axi_adrv903x_rx_os_jesd 12 108 140 +axi_adrv903x_tx_dma 13 109 141 +axi_adrv903x_rx_dma 14 110 142 +axi_adrv903x_rx_os_dma 15 111 143 +======================= === ============ ============= + +Building the HDL project +------------------------------------------------------------------------------- + +The design is built upon ADI's generic HDL reference design framework. +ADI distributes the bit/elf files of these projects as part of the +:dokuwiki:`ADI Kuiper Linux `. +If you want to build the sources, ADI makes them available on the +:git-hdl:`HDL repository `. To get the source you must +`clone `__ +the HDL repository. + +Then go to the :git-hdl:`projects/adrv903x ` +location and run the make command by typing in your command prompt: + +**Linux/Cygwin/WSL** + +.. shell:: + + $cd hdl/projects/adrv903x/zcu102 + $make + +The following dropdowns contain tables with the parameters that can be used to +configure this project, depending on the carrier used. +Where a cell contains a --- (dash) it means that the parameter doesn't exist +for that project (adrv903x/carrier or adrv903x/carrier). + +.. collapsible:: Default values of the ``make`` parameters for ADRV903x + + +----------------------+------------------------------------------------------+ + | Parameter | Default value of the parameters depending on carrier | + +----------------------+------------------------------------------------------+ + | | ZCU102 | + +======================+======================================================+ + | JESD_MODE | 64B66B | + +----------------------+------------------------------------------------------+ + | ORX_ENABLE | 1 | + +----------------------+------------------------------------------------------+ + | RX_LANE_RATE | 16.22 | + +----------------------+------------------------------------------------------+ + | TX_LANE_RATE | 16.22 | + +----------------------+------------------------------------------------------+ + | TX_NUM_LINKS | 1 | + +----------------------+------------------------------------------------------+ + | RX_NUM_LINKS | 1 | + +----------------------+------------------------------------------------------+ + | RX_OS_NUM_LINKS | 1 | + +----------------------+------------------------------------------------------+ + | RX_JESD_M | 16 | + +----------------------+------------------------------------------------------+ + | RX_JESD_L | 4 | + +----------------------+------------------------------------------------------+ + | RX_JESD_S | 1 | + +----------------------+------------------------------------------------------+ + | RX_JESD_NP | 16 | + +----------------------+------------------------------------------------------+ + | RX_JESD_TPL_WIDTH | {} | + +----------------------+------------------------------------------------------+ + | TX_JESD_M | 16 | + +----------------------+------------------------------------------------------+ + | TX_JESD_L | 8 | + +----------------------+------------------------------------------------------+ + | TX_JESD_S | 1 | + +----------------------+------------------------------------------------------+ + | TX_JESD_NP | 16 | + +----------------------+------------------------------------------------------+ + | TX_JESD_TPL_WIDTH | {} | + +----------------------+------------------------------------------------------+ + | RX_OS_JESD_M | 8 | + +----------------------+------------------------------------------------------+ + | RX_OS_JESD_L | 4 | + +----------------------+------------------------------------------------------+ + | RX_OS_JESD_S | 1 | + +----------------------+------------------------------------------------------+ + | RX_OS_JESD_NP | 16 | + +----------------------+------------------------------------------------------+ + | RX_OS_JESD_TPL_WIDTH | {} | + +----------------------+------------------------------------------------------+ + +A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. + +Other considerations +------------------------------------------------------------------------------- + +ADC - lane mapping +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Due to physical constraints, Rx lanes are reordered as described in the +following table. + +============ =========================== +ADC phy Lane FPGA Rx lane / Logical Lane +============ =========================== +0 0 +1 1 +2 2 +3 3 +4 4 +5 5 +6 6 +7 7 +============ =========================== + +DAC - lane mapping +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Due to physical constraints, Tx lanes are reordered as described in the +following table. + +============ =========================== +DAC phy lane FPGA Tx lane / Logical lane +============ =========================== +0 0 +1 1 +2 2 +3 3 +4 4 +5 5 +6 6 +7 7 +============ =========================== + +Resources +------------------------------------------------------------------------------- + +Hardware related +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- Product datasheets: :adi:`ADRV9032R` + +HDL related +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- :git-hdl:`ADRV903x HDL project source code ` + +.. list-table:: + :widths: 30 40 35 + :header-rows: 1 + + * - IP name + - Source code link + - Documentation link + * - AXI_CLKGEN + - :git-hdl:`library/axi_clkgen` + - :ref:`axi_clkgen` + * - AXI_DMAC + - :git-hdl:`library/axi_dmac` + - :ref:`axi_dmac` + * - AXI_SYSID + - :git-hdl:`library/axi_sysid` + - :ref:`axi_sysid` + * - SYSID_ROM + - :git-hdl:`library/sysid_rom` + - :ref:`axi_sysid` + * - UTIL_CPACK2 + - :git-hdl:`library/util_pack/util_cpack2` + - :ref:`util_cpack2` + * - UTIL_UPACK2 + - :git-hdl:`library/util_pack/util_upack2` + - :ref:`util_upack2` + * - DATA_OFFLOAD + - :git-hdl:`library/data_offload` + - :ref:`data_offload` + * - UTIL_DO_RAM + - :git-hdl:`library/util_do_ram` + - :ref:`data_offload` + * - UTIL_ADXCVR for AMD + - :git-hdl:`library/xilinx/util_adxcvr` + - :ref:`util_adxcvr` + * - AXI_ADXCVR for AMD + - :git-hdl:`library/xilinx/axi_adxcvr` + - :ref:`axi_adxcvr amd` + * - AXI_JESD204_RX + - :git-hdl:`library/jesd204/axi_jesd204_rx` + - :ref:`axi_jesd204_rx` + * - AXI_JESD204_TX + - :git-hdl:`library/jesd204/axi_jesd204_tx` + - :ref:`axi_jesd204_tx` + * - JESD204_TPL_ADC + - :git-hdl:`library/jesd204/ad_ip_jesd204_tpl_adc` + - :ref:`ad_ip_jesd204_tpl_dac` + * - JESD204_TPL_DAC + - :git-hdl:`library/jesd204/ad_ip_jesd204_tpl_dac` + - :ref:`ad_ip_jesd204_tpl_dac` + +- :ref:`jesd204` + +.. include:: ../common/more_information.rst + +.. include:: ../common/support.rst + diff --git a/docs/projects/index.rst b/docs/projects/index.rst index 3fb512706d5..2a5b1b4f3e4 100644 --- a/docs/projects/index.rst +++ b/docs/projects/index.rst @@ -72,6 +72,7 @@ Contents ADRV9009 ADRV9009-ZU11EG ADRV9026 + ADRV903x ADRV904x ADRV9361Z7035 ADRV9364Z7020