diff --git a/docs/library/axi_ad9740/axi_ad9740_block_diagram.svg b/docs/library/axi_ad9740/axi_ad9740_block_diagram.svg new file mode 100644 index 00000000000..58670dcbfd5 --- /dev/null +++ b/docs/library/axi_ad9740/axi_ad9740_block_diagram.svg @@ -0,0 +1,1272 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + +   +   +   +   + + Register Map + + AD974X INTERFACE + + CLK + + + + + RAMP + DMA + + + TX CHANNEL + + TX CORE + + + + + + 16b + DMA +   + + + + S_AXI_MM + + AXI_AD974X + + + + 14 12 10 8b + DATA + + diff --git a/docs/library/axi_ad9740/index.rst b/docs/library/axi_ad9740/index.rst new file mode 100644 index 00000000000..9c3befebddd --- /dev/null +++ b/docs/library/axi_ad9740/index.rst @@ -0,0 +1,220 @@ +.. _axi_ad9740: + +AXI AD9740 +================================================================================ + +.. hdl-component-diagram:: + +The :git-hdl:`AXI AD9740 ` IP core +can be used to interface the :adi:`AD9740`, :adi:`AD9742`, :adi:`AD9744` or +:adi:`AD9748` devices. +It is a DAC with 8, 10, 12 or 14 bits resolution and with sample rates up to 210 +MSPS. This documentation only covers the IP core and requires +that one must be familiar with the device for a complete and better understanding. + +More about the generic framework interfacing DACs can be read in :ref:`axi_dac`. + +Features +-------------------------------------------------------------------------------- + +* AXI Lite control/status interface +* AXI-Stream interface for DMA data +* Configurable DAC resolution (8/10/12/14-bit via DAC_RESOLUTION parameter) +* Multiple data source modes: + + * DDS - Direct Digital Synthesis with dual-tone support + * DMA - Data streaming from memory + * Ramp - Internal test pattern generator + * Sedation - Zero output (mute) + +* Data format conversion (two's complement to offset binary) +* MSB-aligned data path for all resolutions + +Files +-------------------------------------------------------------------------------- + +.. list-table:: + :header-rows: 1 + + * - Name + - Description + * - :git-hdl:`library/axi_ad9740/axi_ad9740.v` + - Verilog source for the AXI AD9740 top module. + * - :git-hdl:`library/axi_ad9740/axi_ad9740_core.v` + - Verilog source for the AXI AD9740 core. + * - :git-hdl:`library/axi_ad9740/axi_ad9740_channel.v` + - Verilog source for the AXI AD9740 channel processing. + * - :git-hdl:`library/axi_ad9740/axi_ad9740_if.v` + - Verilog source for the AXI AD9740 data format interface. + * - :git-hdl:`library/common/up_dac_common.v` + - Verilog source for the DAC Common regmap. + * - :git-hdl:`library/common/up_dac_channel.v` + - Verilog source for the DAC Channel regmap. + +Functional Description +-------------------------------------------------------------------------------- + +The axi_ad9740 cores architecture contains: + +* :git-hdl:`Interface ` + module for Xilinx devices +* :git-hdl:`Transmit ` + module, which contains: + + * :git-hdl:`DAC channel processing ` + + * :git-hdl:`DAC Common register map ` + +* :git-hdl:`AXI control and status ` modules. + +Block Diagram +-------------------------------------------------------------------------------- + +.. image:: axi_ad9740_block_diagram.svg + :width: 600 + :alt: AXI AD9740 block diagram + +Configuration Parameters +-------------------------------------------------------------------------------- + +.. hdl-parameters:: + + * - ID + - Core ID should be unique for each IP in the system + * - FPGA_TECHNOLOGY + - Encoded value describing the technology/generation of the FPGA device + (e.g., 1=7series, 2=ultrascale, 3=ultrascale+, 4=versal). Auto-set in + project. + * - FPGA_FAMILY + - Encoded value describing the family variant of the FPGA device (e.g., + 1=artix, 2=kintex, 3=virtex, 4=zynq). Auto-set in project. + * - SPEED_GRADE + - Encoded value describing the FPGA's speed-grade. Auto-set in project. + * - DEV_PACKAGE + - Encoded value describing the device package. The package might affect + high-speed interfaces. Auto-set in project. + * - DAC_RESOLUTION + - Sets the DAC resolution in bits. Valid values are 8, 10, 12, or 14 + corresponding to the target device: AD9748 (8-bit), AD9740 (10-bit), + AD9742 (12-bit), or AD9744 (14-bit). This parameter controls the DDS + output width and the DMA data alignment. Default value is 14. + * - DDS_DISABLE + - Disable the DDS logic to save FPGA resources when not needed. Set to 1 + to disable. Default value is 0. + * - DDS_TYPE + - Selects the DDS phase-to-amplitude converter implementation. Set to 1 + for CORDIC (better precision) or 2 for Polynomial (uses more DSPs but + fewer LUTs). Default value is 1. + * - DDS_CORDIC_DW + - CORDIC DDS data width, range 8-24. Default value is 14. + * - DDS_CORDIC_PHASE_DW + - Number of CORDIC rotation stages, range 8-32. Higher values provide + better precision at the cost of more resources. Default value is 14. + +Interface +-------------------------------------------------------------------------------- + +.. hdl-interfaces:: + + * - dac_clk + - Input clock for the DAC interface + * - s_axis + - AXI-Stream slave interface for DMA data (16-bit TDATA, TVALID, TREADY) + * - dac_data + - Output data to DAC, MSB-aligned for all resolutions + * - s_axi + - Standard AXI Slave Memory Map interface + +Register Map +-------------------------------------------------------------------------------- + +The register map of the core contains instances of several generic register maps +like DAC common and DAC channel. The following table presents the base addresses +of each instance, after that can be found the detailed description of each +generic register map. The absolute address of a register should be calculated +by adding the instance base address to the registers relative address. + +.. list-table:: Register Map base addresses for axi_ad9740 + :header-rows: 1 + + * - DWORD + - BYTE + - Name + - Description + * - 0x0000 + - 0x0000 + - TX COMMON + - See the `DAC Common <#hdl-regmap-DAC_COMMON>`__ table for more details. + * - 0x0100 + - 0x0400 + - TX CHANNEL + - See the `DAC Channel <#hdl-regmap-DAC_CHANNEL>`__ table for more details. + +.. hdl-regmap:: + :name: COMMON + :no-type-info: + +.. hdl-regmap:: + :name: DAC_COMMON + :no-type-info: + +.. hdl-regmap:: + :name: DAC_CHANNEL + :no-type-info: + +Design Guidelines +-------------------------------------------------------------------------------- + +The control of the AD9740/AD9742/AD9744/AD9748 DAC is done through the AXI AD9740 +IP core registers. These devices use a parallel data interface and do not require +a separate SPI interface for configuration. + +The *DAC interface signals* must be directly connected to the top-level FPGA I/O +pins. + +The example design uses a DMA to stream data from memory to the DAC. The IP +supports multiple data sources selectable via the DAC_DDS_SEL register: + +* DDS mode (0x0) - Internal dual-tone DDS generator +* DMA mode (0x2) - Data streaming from memory +* Ramp mode (0xB) - Internal ramp pattern for testing + +The data format (signed/unsigned) can be configured via the DAC_DATAFMT register +in DAC Common. When set to 1, the IP converts two's complement data to offset +binary format expected by these devices. + +Software Guidelines +-------------------------------------------------------------------------------- + +The software for this IP can be found as part of the ZedBoard Reference Design. + +Software Support +-------------------------------------------------------------------------------- + +.. warning:: + + The software support for this IP is not yet merged into the main ADI Linux + kernel branch. The links below refer to development branches. + +.. collapsible:: Linux driver and device tree sources + + * Linux device driver at :git-linux:`drivers/iio/dac/ad9740.c` + * Linux device tree at :git-linux:`arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad9740.dts` + * Linux device tree at :git-linux:`arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad9742.dts` + * Linux device tree at :git-linux:`arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad9744.dts` + * Linux device tree at :git-linux:`arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad9748.dts` + +References +------------------------------------------------------------------------------- + +* HDL IP core at :git-hdl:`library/axi_ad9740` +* HDL project at :git-hdl:`projects/ad9740_fmc` +* HDL project documentation at :ref:`ad9740_fmc` +* :adi:`AD9740` +* :adi:`AD9742` +* :adi:`AD9744` +* :adi:`AD9748` +* :adi:`EVAL-AD9740` +* :adi:`EVAL-AD9742` +* :adi:`EVAL-AD9744` +* :adi:`EVAL-AD9748` diff --git a/docs/library/index.rst b/docs/library/index.rst index 8e409aeeb01..fbf925e57a0 100644 --- a/docs/library/index.rst +++ b/docs/library/index.rst @@ -34,6 +34,7 @@ ADC/DAC axi_ad9265/index axi_ad9361/index axi_ad9467/index + axi_ad9740/index axi_ad9783/index axi_ad9963/index axi_ada4355/index diff --git a/docs/projects/ad9740_fmc/ad9740_zed_block_diagram.svg b/docs/projects/ad9740_fmc/ad9740_zed_block_diagram.svg new file mode 100644 index 00000000000..ff52d8c4587 --- /dev/null +++ b/docs/projects/ad9740_fmc/ad9740_zed_block_diagram.svg @@ -0,0 +1,1466 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + MEMORY INTERCONNECT + + + Zedboard + + FMC CONNECTOR +   + +   +   +   + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Transmit path + + + + + + + + ARM (Zynq) + Zynq SoC + + + + + + + + Ethernet + UART + DDRx + SPI + I2C + Interrupts + Timer + + + DAC core frame + + + + + + DAC CHANNEL + + AD974X CORE + + + + + DMA_Clk =100MHz + DAC_Clk =210MHz + + + + + AD9740_DMA + + + + IQ Correction + + + + + + + + + PRBS + PATTERN + DDS + DMA + + + + + + DATA[13:0] + + CLK + + 16 + 32 + 16 + + + ADF4351 + + diff --git a/docs/projects/ad9740_fmc/index.rst b/docs/projects/ad9740_fmc/index.rst new file mode 100644 index 00000000000..e7b2649f590 --- /dev/null +++ b/docs/projects/ad9740_fmc/index.rst @@ -0,0 +1,196 @@ +.. _ad9740_fmc: + +AD9740-FMC HDL project +================================================================================ + +Overview +------------------------------------------------------------------------------- + +The :adi:`AD9740`, :adi:`AD9742`, :adi:`AD9744` and :adi:`AD9748` are wideband, +3G members of the TxDAC® series of high performance, low power CMOS, +digital-to-analog converters (DACs). The TxDAC family, consisting of +pin-compatible 14-, 12-, 10-, and 8-bit DACs, is specifically optimized for the +transmit signal path of communication systems. All the devices share the same +interface options, small outline package, and pinout. The :adi:`AD9740`, +:adi:`AD9742`, :adi:`AD9744` and :adi:`AD9748` also provide an upward or +downward component selection path based on performance, resolution and +financial cost, offering exceptional AC and DC performance while supporting +update rates up to 210 MSPS. + +The :adi:`EVAL-AD9740`, :adi:`EVAL-AD9742`, :adi:`EVAL-AD9744` and +:adi:`EVAL-AD9748` evaluation boards are FMC form-factor boards with FMC +connector that is compatible to the Vita 57.1 standard. This board provides the +user with the flexibility to operate the :adi:`AD9740`, :adi:`AD9742`, +:adi:`AD9744` and :adi:`AD9748` in various configurations. + +Output configurations include transformer-coupled, resistor terminated, and +single and differential outputs. The digital inputs are designed to be driven +from various word generators with the onboard option to add a resistor network +for proper load termination. Provisions are also made to operate the +:adi:`AD9740`, :adi:`AD9742`, :adi:`AD9744` and :adi:`AD9748` with either the +onboard clock source (:adi:`ADF4351`) or with external clock configuration. + +Supported boards +------------------------------------------------------------------------------- + +- :adi:`EVAL-AD9740` +- :adi:`EVAL-AD9742` +- :adi:`EVAL-AD9744` +- :adi:`EVAL-AD9748` + +Supported devices +------------------------------------------------------------------------------- + +- :adi:`AD9740` +- :adi:`AD9742` +- :adi:`AD9744` +- :adi:`AD9748` + +Supported carriers +------------------------------------------------------------------------------- + +.. list-table:: + :widths: 35 35 30 + :header-rows: 1 + + * - Evaluation board + - Carrier + - FMC slot + * - :adi:`EVAL-AD9740` + - `ZedBoard `__ + - FMC-LPC + * - :adi:`EVAL-AD9742` + - `ZedBoard `__ + - FMC-LPC + * - :adi:`EVAL-AD9744` + - `ZedBoard `__ + - FMC-LPC + * - :adi:`EVAL-AD9748` + - `ZedBoard `__ + - FMC-LPC + +Block design +------------------------------------------------------------------------------- + +.. warning:: + + The VADJ for Zedboard must be set to 3.3V. + +Block diagram +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The data path and clock domains are depicted in the below diagram: + +.. image:: ad9740_zed_block_diagram.svg + :width: 800 + :align: center + :alt: EVAL-AD9740/ZedBoard block diagram + +CPU/Memory interconnects addresses +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The addresses are dependent on the architecture of the FPGA, having an offset +added to the base address from HDL (see more at :ref:`architecture cpu-intercon-addr`). + +==================== =============== +Instance Zynq +==================== =============== +ad9740_dac 0x44A7_0000 +ad9740_dma 0x44A4_0000 +==================== =============== + +Interrupts +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Below are the Programmable Logic interrupts used in this project. + +================ === ========== =========== +Instance name HDL Linux Zynq Actual Zynq +================ === ========== =========== +ad9740_dma 13 57 89 +================ === ========== =========== + +Building the HDL project +------------------------------------------------------------------------------- + +The design is built upon ADI's generic HDL reference design framework. +ADI distributes the bit/elf files of these projects as part of the +:dokuwiki:`ADI Kuiper Linux `. +If you want to build the sources, ADI makes them available on the +:git-hdl:`HDL repository `. To get the source you must +`clone `__ +the HDL repository, and then build the project as follows: + +**Linux/Cygwin/WSL** + +.. shell:: bash + :user: user + :group: analog + + $cd hdl/projects/ad9740_fmc/zed + $make + +A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. + +Resources +------------------------------------------------------------------------------- + +Systems related +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- :dokuwiki:`[Wiki] Evaluating the AD9740/AD9742/AD9744/AD9748 Digital-to-Analog Converters ` + +Hardware related +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- Product datasheets: + + - :adi:`AD9740` + - :adi:`AD9742` + - :adi:`AD9744` + - :adi:`AD9748` + +HDL related +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- :git-hdl:`EVAL-AD9740-FMC HDL project source code ` + +.. list-table:: + :widths: 30 35 35 + :header-rows: 1 + + * - IP name + - Source code link + - Documentation link + + * - AXI_AD9740 + - :git-hdl:`library/axi_ad9740` + - :ref:`axi_ad9740` + * - AXI_DMAC + - :git-hdl:`library/axi_dmac` + - :ref:`axi_dmac` + * - AXI_HDMI_TX + - :git-hdl:`library/axi_hdmi_tx` + - :ref:`axi_hdmi_tx` + * - AXI_I2S_ADI + - :git-hdl:`library/axi_i2s_adi` + - — + * - AXI_SPDIF_TX + - :git-hdl:`library/axi_spdif_tx` + - — + * - AXI_SYSID + - :git-hdl:`library/axi_sysid` + - :ref:`axi_sysid` + * - SYSID_ROM + - :git-hdl:`library/sysid_rom` + - :ref:`axi_sysid` + * - UTIL_I2C_MIXER + - :git-hdl:`library/util_i2c_mixer` + - — + +Software related +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. include:: ../common/more_information.rst + +.. include:: ../common/support.rst diff --git a/docs/projects/index.rst b/docs/projects/index.rst index 86caa2d8b57..1fe9ed5cfed 100644 --- a/docs/projects/index.rst +++ b/docs/projects/index.rst @@ -62,6 +62,7 @@ Contents AD9656-FMC AD9694-FMC AD9695-FMC + AD9740-FMC AD9783-EBZ ADA4355-FMC ADAQ7980-SDZ diff --git a/library/axi_ad9740/Makefile b/library/axi_ad9740/Makefile new file mode 100644 index 00000000000..4dcbe6293ce --- /dev/null +++ b/library/axi_ad9740/Makefile @@ -0,0 +1,35 @@ +#################################################################################### +## Copyright (c) 2018 - 2025 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_ad9740 + +GENERIC_DEPS += ../common/ad_addsub.v +GENERIC_DEPS += ../common/ad_dds.v +GENERIC_DEPS += ../common/ad_dds_1.v +GENERIC_DEPS += ../common/ad_dds_2.v +GENERIC_DEPS += ../common/ad_dds_cordic_pipe.v +GENERIC_DEPS += ../common/ad_dds_sine.v +GENERIC_DEPS += ../common/ad_dds_sine_cordic.v +GENERIC_DEPS += ../common/ad_rst.v +GENERIC_DEPS += ../common/up_axi.v +GENERIC_DEPS += ../common/up_clock_mon.v +GENERIC_DEPS += ../common/up_dac_channel.v +GENERIC_DEPS += ../common/up_dac_common.v +GENERIC_DEPS += ../common/up_xfer_cntrl.v +GENERIC_DEPS += ../common/up_xfer_status.v +GENERIC_DEPS += axi_ad9740.v +GENERIC_DEPS += axi_ad9740_channel.v +GENERIC_DEPS += axi_ad9740_core.v +GENERIC_DEPS += axi_ad9740_if.v + +XILINX_DEPS += ../xilinx/common/ad_mul.v +XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc +XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc +XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc +XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc +XILINX_DEPS += axi_ad9740_ip.tcl + +include ../scripts/library.mk diff --git a/library/axi_ad9740/axi_ad9740.v b/library/axi_ad9740/axi_ad9740.v new file mode 100644 index 00000000000..bec2f88278f --- /dev/null +++ b/library/axi_ad9740/axi_ad9740.v @@ -0,0 +1,191 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9740 #( + + parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, + parameter DAC_RESOLUTION = 14, + parameter DDS_DISABLE = 0, + parameter DDS_TYPE = 1, + parameter DDS_CORDIC_DW = 14, + parameter DDS_CORDIC_PHASE_DW = 14 +) ( + + // dac interface + + input dac_clk, + input [15:0] dma_data, + input dma_valid, + output dma_ready, + output reg [13:0] dac_data, + + // axi interface + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [15:0] s_axi_awaddr, + input [ 2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [15:0] s_axi_araddr, + input [ 2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + input s_axi_rready +); + + // internal clocks and resets + + wire dac_rst_s; + wire up_clk; + wire up_rstn; + + // internal data signals + + wire [15:0] dac_data_s; + wire [ 3:0] dac_data_sel_s; + wire dac_dfmt_type_s; + + // internal signals + + wire up_wreq_s; + wire [13:0] up_waddr_s; + wire [31:0] up_wdata_s; + wire up_wack_s; + wire up_rreq_s; + wire [13:0] up_raddr_s; + wire [31:0] up_rdata_s; + wire up_rack_s; + wire [13:0] dac_data_int; + + // signal name changes + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + + always @(posedge dac_clk) begin + dac_data <= dac_data_int; + end + + // device interface + + axi_ad9740_if #( + .DAC_RESOLUTION(DAC_RESOLUTION) + ) axi_ad9740_interface ( + .dac_data_in(dac_data_s), + .dac_data_sel(dac_data_sel_s), + .dac_dfmt_type(dac_dfmt_type_s), + .dac_data_out(dac_data_int)); + + // core + + axi_ad9740_core #( + .ID(ID), + .FPGA_TECHNOLOGY(FPGA_TECHNOLOGY), + .FPGA_FAMILY(FPGA_FAMILY), + .SPEED_GRADE(SPEED_GRADE), + .DEV_PACKAGE(DEV_PACKAGE), + .DAC_RESOLUTION(DAC_RESOLUTION), + .DDS_DISABLE(DDS_DISABLE), + .DDS_TYPE(DDS_TYPE), + .DDS_CORDIC_DW(DDS_CORDIC_DW), + .DDS_CORDIC_PHASE_DW(DDS_CORDIC_PHASE_DW) + ) axi_ad9740_up_core ( + .dac_clk(dac_clk), + .dac_rst(dac_rst_s), + .dac_data(dac_data_s), + .dac_data_sel(dac_data_sel_s), + .dac_dfmt_type(dac_dfmt_type_s), + .dma_data(dma_data), + .dma_ready(dma_ready), + .dma_valid(dma_valid), + .up_rstn(up_rstn), + .up_clk(up_clk), + .up_wreq(up_wreq_s), + .up_waddr(up_waddr_s), + .up_wdata(up_wdata_s), + .up_wack(up_wack_s), + .up_rreq(up_rreq_s), + .up_raddr(up_raddr_s), + .up_rdata(up_rdata_s), + .up_rack(up_rack_s)); + + // up bus interface + + up_axi i_up_axi( + .up_rstn(up_rstn), + .up_clk(up_clk), + .up_axi_awvalid(s_axi_awvalid), + .up_axi_awaddr(s_axi_awaddr), + .up_axi_awready(s_axi_awready), + .up_axi_wvalid(s_axi_wvalid), + .up_axi_wdata(s_axi_wdata), + .up_axi_wstrb(s_axi_wstrb), + .up_axi_wready(s_axi_wready), + .up_axi_bvalid(s_axi_bvalid), + .up_axi_bresp(s_axi_bresp), + .up_axi_bready(s_axi_bready), + .up_axi_arvalid(s_axi_arvalid), + .up_axi_araddr(s_axi_araddr), + .up_axi_arready(s_axi_arready), + .up_axi_rvalid(s_axi_rvalid), + .up_axi_rresp(s_axi_rresp), + .up_axi_rdata(s_axi_rdata), + .up_axi_rready(s_axi_rready), + .up_wreq(up_wreq_s), + .up_waddr(up_waddr_s), + .up_wdata(up_wdata_s), + .up_wack(up_wack_s), + .up_rreq(up_rreq_s), + .up_raddr(up_raddr_s), + .up_rdata(up_rdata_s), + .up_rack(up_rack_s)); +endmodule diff --git a/library/axi_ad9740/axi_ad9740_channel.v b/library/axi_ad9740/axi_ad9740_channel.v new file mode 100644 index 00000000000..5466d76b987 --- /dev/null +++ b/library/axi_ad9740/axi_ad9740_channel.v @@ -0,0 +1,233 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modificat +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9740_channel #( + + parameter CHANNEL_ID = 32'h0, + parameter DAC_RESOLUTION = 14, + parameter DDS_DISABLE = 0, + parameter DDS_TYPE = 1, + parameter DDS_CORDIC_DW = 14, + parameter DDS_CORDIC_PHASE_DW = 14 +) ( + + // dac interface + + input dac_clk, + input dac_rst, + output reg [13:0] dac_data, + output [ 3:0] dac_data_sel, + + // input sources + + input [15:0] dma_data, + input dma_valid, + output reg dma_ready, + + // processor interface + + input dac_data_sync, + input dac_dfmt_type, + + // bus interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack +); + + // internal signals + + wire [ 3:0] dac_data_sel_s; + wire [DAC_RESOLUTION-1:0] dac_dds_data_s; + wire [15:0] dac_dds_scale_1_s; + wire [15:0] dac_dds_init_1_s; + wire [15:0] dac_dds_incr_1_s; + wire [15:0] dac_dds_scale_2_s; + wire [15:0] dac_dds_init_2_s; + wire [15:0] dac_dds_incr_2_s; + wire [15:0] dac_pat_data_1_s; + wire [15:0] dac_pat_data_2_s; + + reg [15:0] dma_pattern; + reg [DAC_RESOLUTION-1:0] ramp_pattern; + + always @(posedge dac_clk) begin + dma_ready <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0; + + case(dac_data_sel_s) + 4'h0 : + begin + if (DAC_RESOLUTION == 14) begin + dac_data = dac_dds_data_s; + end else begin + // Scale up to 14 bits for output interface - MSB aligned + dac_data = {dac_dds_data_s, {(14-DAC_RESOLUTION){1'b0}}}; + end + end + 4'h2 : + begin + // DMA data - truncate or pad as needed + if (DAC_RESOLUTION >= 14) begin + dac_data = dma_pattern[13:0]; + end else begin + // Take MSBs from DMA and scale up to 14 bits - MSB aligned + // For 10-bit: takes DMA[15:6] and puts in Internal[13:4] + // For 12-bit: takes DMA[15:4] and puts in Internal[13:2] + // For 8-bit: takes DMA[15:8] and puts in Internal[13:6] + dac_data = {dma_pattern[15:16-DAC_RESOLUTION], {(14-DAC_RESOLUTION){1'b0}}}; + end + end + 4'h3 : + begin + dac_data = 'b0; + end + 4'hb : + begin + // Ramp data - scale up to 14 bits - MSB aligned + if (DAC_RESOLUTION == 14) begin + dac_data = ramp_pattern; + end else begin + // Ramp pattern is DAC_RESOLUTION bits, put in upper bits of 14-bit bus + dac_data = {ramp_pattern, {(14-DAC_RESOLUTION){1'b0}}}; + end + end + default : + begin + dac_data = 'b0; + end + endcase + end + + // dma data + + always @(posedge dac_clk) begin + if (dma_valid == 1'b0 || dac_rst == 1'b1) begin + dma_pattern <= 'h0; + end else begin + dma_pattern <= dma_data; + end + end + + // ramp data generator + + always @(posedge dac_clk) begin + if(ramp_pattern == {DAC_RESOLUTION{1'b1}} || dac_rst == 1'b1) begin + ramp_pattern <= {DAC_RESOLUTION{1'b0}}; + end else begin + ramp_pattern <= ramp_pattern + 1'b1; + end + end + + // DDS generator + + ad_dds #( + .DISABLE (DDS_DISABLE), + .DDS_DW (DAC_RESOLUTION), + .PHASE_DW (16), + .DDS_TYPE (DDS_TYPE), + .CORDIC_DW (DDS_CORDIC_DW), + .CORDIC_PHASE_DW (DDS_CORDIC_PHASE_DW), + .CLK_RATIO (1) + ) i_dds ( + .clk (dac_clk), + .dac_dds_format (1'b0), // DDS outputs signed (CORDIC native), conversion handled by axi_ad9740_if + .dac_data_sync (dac_data_sync), + .dac_valid (~|dac_data_sel_s), + .tone_1_scale (dac_dds_scale_1_s), + .tone_2_scale (dac_dds_scale_2_s), + .tone_1_init_offset (dac_dds_init_1_s), + .tone_2_init_offset (dac_dds_init_2_s), + .tone_1_freq_word (dac_dds_incr_1_s), + .tone_2_freq_word (dac_dds_incr_2_s), + .dac_dds_data (dac_dds_data_s)); + + // single channel processor + + up_dac_channel #( + .CHANNEL_ID(CHANNEL_ID), + .COMMON_ID(6'h01) + ) dac_channel ( + .dac_clk(dac_clk), + .dac_rst(dac_rst), + .dac_dds_scale_1(dac_dds_scale_1_s), + .dac_dds_init_1(dac_dds_init_1_s), + .dac_dds_incr_1(dac_dds_incr_1_s), + .dac_dds_scale_2(dac_dds_scale_2_s), + .dac_dds_init_2(dac_dds_init_2_s), + .dac_dds_incr_2(dac_dds_incr_2_s), + .dac_pat_data_1(dac_pat_data_1_s), + .dac_pat_data_2(dac_pat_data_2_s), + .dac_data_sel(dac_data_sel_s), + .dac_mask_enable(), + .dac_iq_mode(), + .dac_iqcor_enb(), + .dac_iqcor_coeff_1(), + .dac_iqcor_coeff_2(), + .dac_src_chan_sel(), + .up_usr_datatype_be(), + .up_usr_datatype_signed(), + .up_usr_datatype_shift(), + .up_usr_datatype_total_bits(), + .up_usr_datatype_bits(), + .up_usr_interpolation_m(), + .up_usr_interpolation_n(), + .dac_usr_datatype_be(1'd0), + .dac_usr_datatype_signed(1'd1), + .dac_usr_datatype_shift(8'd0), + .dac_usr_datatype_total_bits(8'd16), + .dac_usr_datatype_bits(8'd16), + .dac_usr_interpolation_m(16'd1), + .dac_usr_interpolation_n(16'd1), + .up_rstn(up_rstn), + .up_clk(up_clk), + .up_wreq(up_wreq), + .up_waddr(up_waddr), + .up_wdata(up_wdata), + .up_wack(up_wack), + .up_rreq(up_rreq), + .up_raddr(up_raddr), + .up_rdata(up_rdata), + .up_rack(up_rack)); +endmodule diff --git a/library/axi_ad9740/axi_ad9740_core.v b/library/axi_ad9740/axi_ad9740_core.v new file mode 100644 index 00000000000..113c1c67bc7 --- /dev/null +++ b/library/axi_ad9740/axi_ad9740_core.v @@ -0,0 +1,205 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9740_core #( + parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, + parameter DAC_RESOLUTION = 14, + parameter DDS_DISABLE = 0, + parameter DDS_TYPE = 1, + parameter DDS_CORDIC_DW = 14, + parameter DDS_CORDIC_PHASE_DW = 14 +) ( + + // dac interface + + input dac_clk, + output dac_rst, + input [15:0] dma_data, + input dma_valid, + output dma_ready, + output [13:0] dac_data, + output [ 3:0] dac_data_sel, + output dac_dfmt_type, + + // processor interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [13:0] up_raddr, + output reg [31:0] up_rdata, + output reg up_rack +); + + wire [31:0] up_rdata_0_s; + wire up_rack_0_s; + wire up_wack_0_s; + wire [31:0] up_rdata_1_s; + wire up_rack_1_s; + wire up_wack_1_s; + wire [31:0] up_rdata_s; + wire up_rack_s; + wire up_wack_s; + + wire [13:0] dac_data_channel_0; + wire [ 3:0] dac_data_sel_channel_0; + wire dac_rst_s; + wire dac_data_sync; + wire dac_dfmt_type_s; + + // defaults + + assign dac_rst = dac_rst_s; + assign dac_data = dac_data_channel_0; + assign dac_data_sel = dac_data_sel_channel_0; + assign dac_dfmt_type = dac_dfmt_type_s; + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if(up_rstn == 0) begin + up_rdata <= 'd0; + up_rack <= 'd0; + up_wack <= 'd0; + end else begin + up_rdata <= up_rdata_s | up_rdata_0_s | up_rdata_1_s; + up_rack <= up_rack_s | up_rack_0_s | up_rack_1_s; + up_wack <= up_wack_s | up_wack_0_s | up_wack_1_s; + end + end + + // dac channel 0 + + axi_ad9740_channel #( + .CHANNEL_ID(0), + .DAC_RESOLUTION(DAC_RESOLUTION), + .DDS_DISABLE(DDS_DISABLE), + .DDS_TYPE(DDS_TYPE), + .DDS_CORDIC_DW(DDS_CORDIC_DW), + .DDS_CORDIC_PHASE_DW(DDS_CORDIC_PHASE_DW) + ) axi_ad9740_channel_0 ( + .dac_clk(dac_clk), + .dac_rst(dac_rst_s), + .dac_data(dac_data_channel_0), + .dac_data_sel(dac_data_sel_channel_0), + .dma_data(dma_data[15:0]), + .dma_ready(dma_ready), + .dma_valid(dma_valid), + .dac_data_sync(dac_data_sync), + .dac_dfmt_type(dac_dfmt_type_s), + .up_rstn(up_rstn), + .up_clk(up_clk), + .up_wreq(up_wreq), + .up_waddr(up_waddr), + .up_wdata(up_wdata), + .up_wack(up_wack_0_s), + .up_rreq(up_rreq), + .up_raddr(up_raddr), + .up_rdata(up_rdata_0_s), + .up_rack(up_rack_0_s)); + + // dac common processor interface + + up_dac_common #( + .ID(ID), + .FPGA_TECHNOLOGY(FPGA_TECHNOLOGY), + .FPGA_FAMILY(FPGA_FAMILY), + .SPEED_GRADE(SPEED_GRADE), + .DEV_PACKAGE(DEV_PACKAGE), + .COMMON_ID(6'h00) + ) axi_ad9740_common_core ( + .mmcm_rst(), + .dac_clk(dac_clk), + .dac_rst(dac_rst_s), + .dac_num_lanes(), + .dac_sdr_ddr_n(), + .dac_symb_op(), + .dac_symb_8_16b(), + .dac_sync(dac_data_sync), + .dac_ext_sync_arm(), + .dac_ext_sync_disarm(), + .dac_ext_sync_manual_req(), + .dac_frame(), + .dac_clksel(), + .dac_custom_wr(), + .dac_custom_rd(32'b0), + .dac_custom_control(), + .dac_status_if_busy(if_busy), + .dac_par_type(), + .dac_par_enb(), + .dac_r1_mode(), + .dac_datafmt(dac_dfmt_type_s), + .dac_datarate(), + .dac_status(), + .dac_sync_in_status(), + .dac_status_unf(), + .dac_clk_ratio(32'd1), + .up_dac_ce(), + .up_pps_rcounter(32'd0), + .up_pps_status(1'd0), + .up_pps_irq_mask(), + .up_dac_r1_mode(), + .up_drp_sel(), + .up_drp_wr(), + .up_drp_addr(), + .up_drp_wdata() , + .up_drp_rdata(32'd0), + .up_drp_ready(1'd1), + .up_drp_locked(1'd1), + .up_usr_chanmax(), + .dac_usr_chanmax(8'd1), + .up_dac_gpio_in(32'd0), + .up_dac_gpio_out(), + .up_rstn(up_rstn), + .up_clk(up_clk), + .up_wreq(up_wreq), + .up_waddr(up_waddr), + .up_wdata(up_wdata), + .up_wack(up_wack_s), + .up_rreq(up_rreq), + .up_raddr(up_raddr), + .up_rdata(up_rdata_s), + .up_rack (up_rack_s)); +endmodule diff --git a/library/axi_ad9740/axi_ad9740_if.v b/library/axi_ad9740/axi_ad9740_if.v new file mode 100644 index 00000000000..16d5e28796a --- /dev/null +++ b/library/axi_ad9740/axi_ad9740_if.v @@ -0,0 +1,70 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9740_if #( + parameter DAC_RESOLUTION = 14 +) ( + + // dac interface + + output [13:0] dac_data_out, + + // data interface + + input [13:0] dac_data_in, + input [ 3:0] dac_data_sel, + input dac_dfmt_type +); + + // The AD974x DACs expect offset binary format + // Data format conversion based on dac_dfmt_type register: + // - dac_dfmt_type = 0: Data is offset binary (unsigned) - pass through + // - dac_dfmt_type = 1: Data is two's complement (signed) - invert MSB + // + // This applies to ALL data sources (DDS, DMA, Ramp): + // - DDS can be configured for signed or unsigned output + // - DMA data format depends on what software sends + // - Ramp is always unsigned (offset binary) + // + // For all DAC resolutions, data is MSB-aligned in the 14-bit bus + + // MSB inversion for two's complement to offset binary conversion + // Note: dac_dfmt_type=1 means signed (two's complement) data + assign dac_data_out[13] = dac_dfmt_type ? ~dac_data_in[13] : dac_data_in[13]; + assign dac_data_out[12:0] = dac_data_in[12:0]; + +endmodule diff --git a/library/axi_ad9740/axi_ad9740_ip.tcl b/library/axi_ad9740/axi_ad9740_ip.tcl new file mode 100644 index 00000000000..f65259ce351 --- /dev/null +++ b/library/axi_ad9740/axi_ad9740_ip.tcl @@ -0,0 +1,59 @@ +############################################################################### +## Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create axi_ad9740 +adi_ip_files axi_ad9740 [list \ + "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "$ad_hdl_dir/library/common/up_clock_mon.v" \ + "$ad_hdl_dir/library/common/up_dac_common.v" \ + "$ad_hdl_dir/library/common/up_dac_channel.v" \ + "$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v" \ + "$ad_hdl_dir/library/common/ad_dds_sine_cordic.v" \ + "$ad_hdl_dir/library/common/ad_dds_sine.v" \ + "$ad_hdl_dir/library/common/ad_dds_2.v" \ + "$ad_hdl_dir/library/common/ad_dds_1.v" \ + "$ad_hdl_dir/library/common/ad_dds.v" \ + "$ad_hdl_dir/library/common/ad_addsub.v" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ + "axi_ad9740_channel.v" \ + "axi_ad9740_core.v" \ + "axi_ad9740_if.v" \ + "axi_ad9740.v" ] + +adi_ip_properties axi_ad9740 +adi_init_bd_tcl +adi_ip_bd axi_ad9740 "bd/bd.tcl" + +set cc [ipx::current_core] + +set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_ad9740} $cc + +set_property driver_value 0 [ipx::get_ports *dac* -of_objects $cc] +set_property driver_value 0 [ipx::get_ports *data* -of_objects $cc] +set_property driver_value 0 [ipx::get_ports *valid* -of_objects $cc] +ipx::infer_bus_interface dac_clk xilinx.com:signal:clock_rtl:1.0 $cc + +adi_add_bus "s_axis" "slave" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + [list {"dma_ready" "TREADY"} \ + {"dma_valid" "TVALID"} \ + {"dma_data" "TDATA"}] +adi_add_bus_clock "dac_clk" "s_axis" + +adi_add_auto_fpga_spec_params + +ipx::create_xgui_files $cc +ipx::save_core $cc diff --git a/library/common/ad_dds.v b/library/common/ad_dds.v index 5a44ed27187..e846c834868 100644 --- a/library/common/ad_dds.v +++ b/library/common/ad_dds.v @@ -86,6 +86,8 @@ module ad_dds #( // enable dds + // Phase registers - initialize to 0 to avoid X in simulation + // Note: These are arrays indexed [1:CLK_RATIO], initialized via initial block reg [PHASE_DW-1:0] dac_dds_phase_0[1:CLK_RATIO]; reg [PHASE_DW-1:0] dac_dds_phase_1[1:CLK_RATIO]; reg [PHASE_DW-1:0] dac_dds_phase_0_m[1:CLK_RATIO]; @@ -94,6 +96,17 @@ module ad_dds #( reg [PHASE_DW-1:0] dac_dds_incr_1 = 'd0; reg [CLK_RATIO :1] sync_min_pulse_m = 'd0; + // Initialize phase array registers to avoid X in simulation + integer init_idx; + initial begin + for (init_idx = 1; init_idx <= CLK_RATIO; init_idx = init_idx + 1) begin + dac_dds_phase_0[init_idx] = 'd0; + dac_dds_phase_1[init_idx] = 'd0; + dac_dds_phase_0_m[init_idx] = 'd0; + dac_dds_phase_1_m[init_idx] = 'd0; + end + end + // For scenarios where the synchronization signal comes from an external // source and it is high for a longer period of time, the phase // accumulator stages must be reset, in order to avoid a noise like diff --git a/projects/ad9740_fmc/Makefile b/projects/ad9740_fmc/Makefile new file mode 100644 index 00000000000..172ebbbe4bd --- /dev/null +++ b/projects/ad9740_fmc/Makefile @@ -0,0 +1,7 @@ +#################################################################################### +## Copyright (c) 2025 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +include ../scripts/project-toplevel.mk diff --git a/projects/ad9740_fmc/README.md b/projects/ad9740_fmc/README.md new file mode 100644 index 00000000000..be5a889c200 --- /dev/null +++ b/projects/ad9740_fmc/README.md @@ -0,0 +1,23 @@ +# AD9740-FMC HDL Project + +- Evaluation boards product pages: + - [EVAL-AD9740](https://www.analog.com/eval-ad9740) + - [EVAL-AD9742](https://www.analog.com/eval-ad9742) + - [EVAL-AD9744](https://www.analog.com/eval-ad9744) + - [EVAL-AD9748](https://www.analog.com/eval-ad9748) +- System documentation: TO BE ADDED +- HDL project documentation: https://analogdevicesinc.github.io/hdl/projects/ad9740_fmc/index.html +- Evaluation board VADJ range: 1.2V - 3.3V + +## Supported parts + +| Part name | Description | +|-----------------------------------------|------------------------------------------------------------| +| [AD9740](https://www.analog.com/ad9740) | 10-Bit, 210 MSPS TxDAC® D/A Converter | +| [AD9742](https://www.analog.com/ad9742) | 12-Bit, 210 MSPS TxDAC® D/A Converter | +| [AD9744](https://www.analog.com/ad9744) | 14-Bit, 210 MSPS TxDAC® D/A Converter | +| [AD9748](https://www.analog.com/ad9748) | 8-Bit, 210 MSPS TxDAC® D/A Converter | + +## Building the project + +Please enter the folder for the FPGA carrier you want to use and read the README.md. diff --git a/projects/ad9740_fmc/common/ad9740_fmc_bd.tcl b/projects/ad9740_fmc/common/ad9740_fmc_bd.tcl new file mode 100644 index 00000000000..5c469c04226 --- /dev/null +++ b/projects/ad9740_fmc/common/ad9740_fmc_bd.tcl @@ -0,0 +1,87 @@ +############################################################################### +## Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# bd ports + +create_bd_port -dir I ad9740_clk +create_bd_port -dir O -from 13 -to 0 ad9740_data + +# dma + +ad_ip_instance axi_dmac ad9740_dma +ad_ip_parameter ad9740_dma CONFIG.DMA_TYPE_SRC 0 +ad_ip_parameter ad9740_dma CONFIG.DMA_TYPE_DEST 2 +ad_ip_parameter ad9740_dma CONFIG.CYCLIC 1 +ad_ip_parameter ad9740_dma CONFIG.SYNC_TRANSFER_START 0 +ad_ip_parameter ad9740_dma CONFIG.DMA_2D_TRANSFER 0 +ad_ip_parameter ad9740_dma CONFIG.DMA_DATA_WIDTH_SRC 64 +ad_ip_parameter ad9740_dma CONFIG.DMA_DATA_WIDTH_DEST 16 + +# ad9740 + +ad_ip_instance axi_ad9740 ad9740_dac + +set DEVICE $ad_project_params(DEVICE) + +# Set DAC resolution based on DEVICE parameter +# DEVICE must be set by the calling script (system_bd.tcl or system_project.tcl) +switch $DEVICE { + "AD9748" { + ad_ip_parameter ad9740_dac CONFIG.DAC_RESOLUTION 8 + puts "common bd tcl: detected AD9748" + } + "AD9740" { + ad_ip_parameter ad9740_dac CONFIG.DAC_RESOLUTION 10 + puts "common bd tcl: detected AD9740" + } + "AD9742" { + ad_ip_parameter ad9740_dac CONFIG.DAC_RESOLUTION 12 + puts "common bd tcl: detected AD9742" + } + "AD9744" { + ad_ip_parameter ad9740_dac CONFIG.DAC_RESOLUTION 14 + puts "common bd tcl: detected AD9744" + } + default { + ad_ip_parameter ad9740_dac CONFIG.DAC_RESOLUTION 14 + puts "common bd tcl: detected default AD9744" + } +} + +# clocks + +#ad_connect ad9740_clk ad9740_dma/m_axis_aclk +ad_connect ad9740_clk ad9740_dac/dac_clk + +# resets + +ad_connect sys_rstgen/peripheral_aresetn ad9740_dma/m_src_axi_aresetn + +# data path + +connect_bd_net [get_bd_pins ad9740_dma/fifo_rd_dout] [get_bd_pins ad9740_dac/dma_data] +connect_bd_net [get_bd_pins ad9740_dma/fifo_rd_valid] [get_bd_pins ad9740_dac/dma_valid] + +connect_bd_net [get_bd_ports ad9740_clk] [get_bd_pins ad9740_dma/fifo_rd_clk] + +connect_bd_net [get_bd_pins ad9740_dma/fifo_rd_en] [get_bd_pins ad9740_dac/dma_ready] + + +#ad_connect ad9740_dma/m_axis ad9740_dac/s_axis +ad_connect ad9740_dac/dac_data ad9740_data + +# AXI address definitions + +ad_cpu_interconnect 0x44a40000 ad9740_dma +ad_cpu_interconnect 0x44a70000 ad9740_dac + +# interrupts + +ad_cpu_interrupt "ps-13" "mb-13" ad9740_dma/irq + +# memory interconnects + +ad_mem_hp1_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP1 +ad_mem_hp1_interconnect $sys_cpu_clk ad9740_dma/m_src_axi diff --git a/projects/ad9740_fmc/common/ad9744_fmc.txt b/projects/ad9740_fmc/common/ad9744_fmc.txt new file mode 100644 index 00000000000..9e51130960d --- /dev/null +++ b/projects/ad9740_fmc/common/ad9744_fmc.txt @@ -0,0 +1,28 @@ +FMC_pin FMC_port Schematic_name System_top_name IOSTANDARD Termination + +# ad9744 + +H4 FMC-CLK0_P REFCLK_P ad9740_clk_p TMDS_33 #N/A +H5 FMC-CLK0_N REFCLK_N ad9740_clk_n TMDS_33 #N/A + +G9 FMC-LA03_P DB13 ad9740_data[13] LVCMOS33 #N/A +G10 FMC-LA03_N DB12 ad9740_data[12] LVCMOS33 #N/A +H10 FMC-LA04_P DB11 ad9740_data[11] LVCMOS33 #N/A +C10 FMC-LA06_P DB10 ad9740_data[10] LVCMOS33 #N/A +H11 FMC-LA04_N DB09 ad9740_data[9] LVCMOS33 #N/A +D11 FMC-LA05_P DB08 ad9740_data[8] LVCMOS33 #N/A +G12 FMC-LA08_P DB07 ad9740_data[7] LVCMOS33 #N/A +H13 FMC-LA07_P DB06 ad9740_data[6] LVCMOS33 #N/A +G13 FMC-LA08_N DB05 ad9740_data[5] LVCMOS33 #N/A +H14 FMC-LA07_N DB04 ad9740_data[4] LVCMOS33 #N/A +C11 FMC-LA06_N DB03 ad9740_data[3] LVCMOS33 #N/A +D12 FMC-LA05_N DB02 ad9740_data[2] LVCMOS33 #N/A +D14 FMC-LA09_P DB01 ad9740_data[1] LVCMOS33 #N/A +D15 FMC-LA09_N DB00 ad9740_data[0] LVCMOS33 #N/A + +# adf4351 + +H7 FMC-LA02_P ADF4351_CLK adf4351_clk LVCMOS33 #N/A +H8 FMC-LA02_N ADF4351_CS adf4351_ce LVCMOS33 #N/A +G16 FMC-LA12_N ADF4351_LE adf4351_csn LVCMOS33 #N/A +H16 FMC-LA11_P ADF4351_D adf4351_mosi LVCMOS33 #N/A diff --git a/projects/ad9740_fmc/zed/Makefile b/projects/ad9740_fmc/zed/Makefile new file mode 100644 index 00000000000..98bebbf3af0 --- /dev/null +++ b/projects/ad9740_fmc/zed/Makefile @@ -0,0 +1,28 @@ +#################################################################################### +## Copyright (c) 2025 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := ad9740_fmc_zed + +M_DEPS += ../../scripts/adi_pd.tcl +M_DEPS += ../common/ad9740_fmc_bd.tcl +M_DEPS += ../../common/zed/zed_system_constr.xdc +M_DEPS += ../../common/zed/zed_system_bd.tcl +M_DEPS += ../../../library/xilinx/common/ad_data_clk.v +M_DEPS += ../../../library/util_cdc/sync_bits.v +M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/common/ad_edge_detect.v + +LIB_DEPS += axi_ad9740 +LIB_DEPS += axi_clkgen +LIB_DEPS += axi_dmac +LIB_DEPS += axi_hdmi_tx +LIB_DEPS += axi_i2s_adi +LIB_DEPS += axi_spdif_tx +LIB_DEPS += axi_sysid +LIB_DEPS += sysid_rom +LIB_DEPS += util_i2c_mixer + +include ../../scripts/project-xilinx.mk diff --git a/projects/ad9740_fmc/zed/README.md b/projects/ad9740_fmc/zed/README.md new file mode 100644 index 00000000000..922e76f505f --- /dev/null +++ b/projects/ad9740_fmc/zed/README.md @@ -0,0 +1,12 @@ + + +# AD9740-FMC/ZED HDL Project + +- VADJ with which it was tested in hardware: 2.5V + +## Building the project + +``` +cd projects/ad9740_fmc/zed +make +``` diff --git a/projects/ad9740_fmc/zed/system_bd.tcl b/projects/ad9740_fmc/zed/system_bd.tcl new file mode 100644 index 00000000000..296ccff1f10 --- /dev/null +++ b/projects/ad9740_fmc/zed/system_bd.tcl @@ -0,0 +1,22 @@ +############################################################################### +## Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source $ad_hdl_dir/projects/scripts/adi_pd.tcl +source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl + +# Pass DEVICE parameter to block design +if {![info exists DEVICE]} { + set DEVICE "AD9744" +} + +# block design +source ../common/ad9740_fmc_bd.tcl + +# system ID +ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 +ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "$mem_init_sys_file_path/mem_init_sys.txt" +ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 + +sysid_gen_sys_init_file diff --git a/projects/ad9740_fmc/zed/system_constr.xdc b/projects/ad9740_fmc/zed/system_constr.xdc new file mode 100644 index 00000000000..b296f30e790 --- /dev/null +++ b/projects/ad9740_fmc/zed/system_constr.xdc @@ -0,0 +1,144 @@ +############################################################################### +## Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ad9740 clk interface + +set_property -dict {PACKAGE_PIN L18 IOSTANDARD TMDS_33} [get_ports ad9740_clk_p] +set_property -dict {PACKAGE_PIN L19 IOSTANDARD TMDS_33} [get_ports ad9740_clk_n] + +# adf4351 interface + +set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS33} [get_ports adf4351_ce] +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS33} [get_ports adf4351_clk] +set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS33} [get_ports adf4351_csn] +set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports adf4351_mosi] + +# ad9740 data interface + +set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVCMOS33 IOB TRUE SLEW FAST DRIVE 12} [get_ports ad9740_data[0]] +set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVCMOS33 IOB TRUE SLEW FAST DRIVE 12} [get_ports ad9740_data[1]] +set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS33 IOB TRUE SLEW FAST DRIVE 12} [get_ports ad9740_data[2]] +set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS33 IOB TRUE SLEW FAST DRIVE 12} [get_ports ad9740_data[3]] +set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS33 IOB TRUE SLEW FAST DRIVE 12} [get_ports ad9740_data[4]] +set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS33 IOB TRUE SLEW FAST DRIVE 12} [get_ports ad9740_data[5]] +set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS33 IOB TRUE SLEW FAST DRIVE 12} [get_ports ad9740_data[6]] +set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS33 IOB TRUE SLEW FAST DRIVE 12} [get_ports ad9740_data[7]] +set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS33 IOB TRUE SLEW FAST DRIVE 12} [get_ports ad9740_data[8]] +set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS33 IOB TRUE SLEW FAST DRIVE 12} [get_ports ad9740_data[9]] +set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS33 IOB TRUE SLEW FAST DRIVE 12} [get_ports ad9740_data[10]] +set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS33 IOB TRUE SLEW FAST DRIVE 12} [get_ports ad9740_data[11]] +set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS33 IOB TRUE SLEW FAST DRIVE 12} [get_ports ad9740_data[12]] +set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS33 IOB TRUE SLEW FAST DRIVE 12} [get_ports ad9740_data[13]] + +# clocks + +create_clock -period 4.761 -name ad9740_clk [get_ports ad9740_clk_p] + +# Output delay constraints for data pins +# AD9744 datasheet specs (Table 3, Page 5): tS (setup) = 2.0ns, tH (hold) = 1.5ns + +set_output_delay -clock ad9740_clk -max 2.000 [get_ports ad9740_data[*]] +set_output_delay -clock ad9740_clk -min -1.500 [get_ports ad9740_data[*]] + +# Multicycle path constraint +# Due to the clock architecture where AD9744 receives clock directly from ADF4351 while +# FPGA sees the same clock after IBUFDS+BUFG delays (~5.1ns), the data path takes longer +# than one clock period. Data arrives at ~8.6ns but needs to be sampled at edge 2 (~9.5ns). +# Allow 3 cycles for setup to ensure positive slack + +set_multicycle_path -setup -to [get_ports ad9740_data[*]] 3 +set_multicycle_path -hold -to [get_ports ad9740_data[*]] 2 + +# hdmi + +set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports hdmi_out_clk] +set_property -dict {PACKAGE_PIN W17 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports hdmi_vsync] +set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports hdmi_hsync] +set_property -dict {PACKAGE_PIN U16 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports hdmi_data_e] +set_property -dict {PACKAGE_PIN Y13 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports hdmi_data[0]] +set_property -dict {PACKAGE_PIN AA13 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports hdmi_data[1]] +set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports hdmi_data[2]] +set_property -dict {PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports hdmi_data[3]] +set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports hdmi_data[4]] +set_property -dict {PACKAGE_PIN AB16 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports hdmi_data[5]] +set_property -dict {PACKAGE_PIN AA16 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports hdmi_data[6]] +set_property -dict {PACKAGE_PIN AB17 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports hdmi_data[7]] +set_property -dict {PACKAGE_PIN AA17 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports hdmi_data[8]] +set_property -dict {PACKAGE_PIN Y15 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports hdmi_data[9]] +set_property -dict {PACKAGE_PIN W13 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports hdmi_data[10]] +set_property -dict {PACKAGE_PIN W15 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports hdmi_data[11]] +set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports hdmi_data[12]] +set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports hdmi_data[13]] +set_property -dict {PACKAGE_PIN V14 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports hdmi_data[14]] +set_property -dict {PACKAGE_PIN V13 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports hdmi_data[15]] + +# spdif + +set_property -dict {PACKAGE_PIN U15 IOSTANDARD LVCMOS33} [get_ports spdif] + +# i2s + +set_property -dict {PACKAGE_PIN AB2 IOSTANDARD LVCMOS33} [get_ports i2s_mclk] +set_property -dict {PACKAGE_PIN AA6 IOSTANDARD LVCMOS33} [get_ports i2s_bclk] +set_property -dict {PACKAGE_PIN Y6 IOSTANDARD LVCMOS33} [get_ports i2s_lrclk] +set_property -dict {PACKAGE_PIN Y8 IOSTANDARD LVCMOS33} [get_ports i2s_sdata_out] +set_property -dict {PACKAGE_PIN AA7 IOSTANDARD LVCMOS33} [get_ports i2s_sdata_in] + +# iic + +set_property -dict {PACKAGE_PIN R7 IOSTANDARD LVCMOS33} [get_ports iic_scl] +set_property -dict {PACKAGE_PIN U7 IOSTANDARD LVCMOS33} [get_ports iic_sda] +set_property -dict {PACKAGE_PIN AA18 IOSTANDARD LVCMOS33 PULLTYPE PULLUP} [get_ports iic_mux_scl[1]] +set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 PULLTYPE PULLUP} [get_ports iic_mux_sda[1]] +set_property -dict {PACKAGE_PIN AB4 IOSTANDARD LVCMOS33 PULLTYPE PULLUP} [get_ports iic_mux_scl[0]] +set_property -dict {PACKAGE_PIN AB5 IOSTANDARD LVCMOS33 PULLTYPE PULLUP} [get_ports iic_mux_sda[0]] + +# otg + +set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS33} [get_ports otg_vbusoc] + +# gpio (switches, leds and such) + +set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS33} [get_ports gpio_bd[0]] ; ## BTNC +set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS33} [get_ports gpio_bd[1]] ; ## BTND +set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS33} [get_ports gpio_bd[2]] ; ## BTNL +set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS33} [get_ports gpio_bd[3]] ; ## BTNR +set_property -dict {PACKAGE_PIN T18 IOSTANDARD LVCMOS33} [get_ports gpio_bd[4]] ; ## BTNU +set_property -dict {PACKAGE_PIN U10 IOSTANDARD LVCMOS33} [get_ports gpio_bd[5]] ; ## OLED-DC +set_property -dict {PACKAGE_PIN U9 IOSTANDARD LVCMOS33} [get_ports gpio_bd[6]] ; ## OLED-RES +set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVCMOS33} [get_ports gpio_bd[7]] ; ## OLED-SCLK +set_property -dict {PACKAGE_PIN AA12 IOSTANDARD LVCMOS33} [get_ports gpio_bd[8]] ; ## OLED-SDIN +set_property -dict {PACKAGE_PIN U11 IOSTANDARD LVCMOS33} [get_ports gpio_bd[9]] ; ## OLED-VBAT +set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS33} [get_ports gpio_bd[10]] ; ## OLED-VDD + +set_property -dict {PACKAGE_PIN F22 IOSTANDARD LVCMOS33} [get_ports gpio_bd[11]] ; ## SW0 +set_property -dict {PACKAGE_PIN G22 IOSTANDARD LVCMOS33} [get_ports gpio_bd[12]] ; ## SW1 +set_property -dict {PACKAGE_PIN H22 IOSTANDARD LVCMOS33} [get_ports gpio_bd[13]] ; ## SW2 +set_property -dict {PACKAGE_PIN F21 IOSTANDARD LVCMOS33} [get_ports gpio_bd[14]] ; ## SW3 +set_property -dict {PACKAGE_PIN H19 IOSTANDARD LVCMOS33} [get_ports gpio_bd[15]] ; ## SW4 +set_property -dict {PACKAGE_PIN H18 IOSTANDARD LVCMOS33} [get_ports gpio_bd[16]] ; ## SW5 +set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS33} [get_ports gpio_bd[17]] ; ## SW6 +set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS33} [get_ports gpio_bd[18]] ; ## SW7 + +set_property -dict {PACKAGE_PIN T22 IOSTANDARD LVCMOS33} [get_ports gpio_bd[19]] ; ## LD0 +set_property -dict {PACKAGE_PIN T21 IOSTANDARD LVCMOS33} [get_ports gpio_bd[20]] ; ## LD1 +set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVCMOS33} [get_ports gpio_bd[21]] ; ## LD2 +set_property -dict {PACKAGE_PIN U21 IOSTANDARD LVCMOS33} [get_ports gpio_bd[22]] ; ## LD3 +set_property -dict {PACKAGE_PIN V22 IOSTANDARD LVCMOS33} [get_ports gpio_bd[23]] ; ## LD4 +set_property -dict {PACKAGE_PIN W22 IOSTANDARD LVCMOS33} [get_ports gpio_bd[24]] ; ## LD5 +set_property -dict {PACKAGE_PIN U19 IOSTANDARD LVCMOS33} [get_ports gpio_bd[25]] ; ## LD6 +set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS33} [get_ports gpio_bd[26]] ; ## LD7 + +set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports gpio_bd[27]] ; ## XADC-GIO0 +set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS33} [get_ports gpio_bd[28]] ; ## XADC-GIO1 +set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS33} [get_ports gpio_bd[29]] ; ## XADC-GIO2 +set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS33} [get_ports gpio_bd[30]] ; ## XADC-GIO3 + +set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS33} [get_ports gpio_bd[31]] ; ## OTG-RESETN + +# Define SPI clock + +create_clock -name spi0_clk -period 40 [get_pins -hier */EMIOSPI0SCLKO] +create_clock -name spi1_clk -period 40 [get_pins -hier */EMIOSPI1SCLKO] diff --git a/projects/ad9740_fmc/zed/system_project.tcl b/projects/ad9740_fmc/zed/system_project.tcl new file mode 100644 index 00000000000..2dde4d12f65 --- /dev/null +++ b/projects/ad9740_fmc/zed/system_project.tcl @@ -0,0 +1,24 @@ +############################################################################### +## Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + + +puts "system_project.tcl: param: [get_env_param DEVICE "AD9744"]" + +adi_project ad9740_fmc_zed 0 [list \ + DEVICE [get_env_param DEVICE "AD9744"] \ + ] + +adi_project_files ad9740_fmc_zed [list \ + "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_data_clk.v" \ + "system_top.v" \ + "system_constr.xdc" \ + ] + +adi_project_run ad9740_fmc_zed diff --git a/projects/ad9740_fmc/zed/system_top.v b/projects/ad9740_fmc/zed/system_top.v new file mode 100644 index 00000000000..e25ec5953fb --- /dev/null +++ b/projects/ad9740_fmc/zed/system_top.v @@ -0,0 +1,246 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top #( + parameter DEVICE = "AD9744" +) ( + + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, + + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, + + inout [31:0] gpio_bd, + + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [15:0] hdmi_data, + + output spdif, + + output i2s_mclk, + output i2s_bclk, + output i2s_lrclk, + output i2s_sdata_out, + input i2s_sdata_in, + + inout iic_scl, + inout iic_sda, + inout [ 1:0] iic_mux_scl, + inout [ 1:0] iic_mux_sda, + + input otg_vbusoc, + + // adf4351 interface + + output adf4351_ce, + output adf4351_clk, + output adf4351_csn, + output adf4351_mosi, + + // ad9740 interface + + input ad9740_clk_p, + input ad9740_clk_n, + output [13:0] ad9740_data +); + + // internal signals + + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + wire [ 1:0] iic_mux_scl_i_s; + wire [ 1:0] iic_mux_scl_o_s; + wire iic_mux_scl_t_s; + wire [ 1:0] iic_mux_sda_i_s; + wire [ 1:0] iic_mux_sda_o_s; + wire iic_mux_sda_t_s; + wire ad9740_clk_ds; + wire ad9740_clk; + wire [13:0] ad9740_data_int; + + // instantiations + + assign gpio_i[63:32] = gpio_o[63:32]; + assign adf4351_ce = 1'b1; + + generate + if (DEVICE == "AD9744") begin + // AD9744: 14-bit DAC - use all bits + assign ad9740_data = ad9740_data_int [13:0]; + end else if (DEVICE == "AD9742") begin + // AD9742: 12-bit DAC - MSB aligned, use upper 12 bits, tie lower 2 bits to 0 + // FIX: Take upper 12 bits from internal 14-bit bus (was taking lower 12 bits) + assign ad9740_data[13:2] = ad9740_data_int[13:2]; + assign ad9740_data[1:0] = 2'b00; + end else if (DEVICE == "AD9740") begin + // AD9740: 10-bit DAC - MSB aligned, use upper 10 bits, tie lower 4 bits to 0 + // FIX: Take upper 10 bits from internal 14-bit bus (was taking lower 10 bits) + assign ad9740_data[13:4] = ad9740_data_int[13:4]; + assign ad9740_data[3:0] = 4'b0000; + end else if (DEVICE == "AD9748") begin + // AD9748: 8-bit DAC - MSB aligned, use upper 8 bits, tie lower 6 bits to 0 + // FIX: Take upper 8 bits from internal 14-bit bus (was taking lower 8 bits) + assign ad9740_data[13:6] = ad9740_data_int[13:6]; + assign ad9740_data[5:0] = 6'b000000; + end else begin + // Default case: assume full 14-bit width + assign ad9740_data = ad9740_data_int; + end + endgenerate + + IBUFDS i_ad9740_clk_ibuf_ds ( + .I (ad9740_clk_p), + .IB (ad9740_clk_n), + .O (ad9740_clk_ds)); + + BUFG i_ad9740_clk_ibuf ( + .I (ad9740_clk_ds), + .O (ad9740_clk)); + + ad_iobuf #( + .DATA_WIDTH(32) + ) i_iobuf ( + .dio_t(gpio_t[31:0]), + .dio_i(gpio_o[31:0]), + .dio_o(gpio_i[31:0]), + .dio_p(gpio_bd)); + + ad_iobuf #( + .DATA_WIDTH(2) + ) i_iic_mux_scl ( + .dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}), + .dio_i(iic_mux_scl_o_s), + .dio_o(iic_mux_scl_i_s), + .dio_p(iic_mux_scl)); + + ad_iobuf #( + .DATA_WIDTH(2) + ) i_iic_mux_sda ( + .dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}), + .dio_i(iic_mux_sda_o_s), + .dio_o(iic_mux_sda_i_s), + .dio_p(iic_mux_sda)); + + system_wrapper i_system_wrapper ( + .ad9740_clk (ad9740_clk), + .ad9740_data (ad9740_data_int), + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + .i2s_bclk (i2s_bclk), + .i2s_lrclk (i2s_lrclk), + .i2s_mclk (i2s_mclk), + .i2s_sdata_in (i2s_sdata_in), + .i2s_sdata_out (i2s_sdata_out), + .iic_fmc_scl_io (iic_scl), + .iic_fmc_sda_io (iic_sda), + .iic_mux_scl_i (iic_mux_scl_i_s), + .iic_mux_scl_o (iic_mux_scl_o_s), + .iic_mux_scl_t (iic_mux_scl_t_s), + .iic_mux_sda_i (iic_mux_sda_i_s), + .iic_mux_sda_o (iic_mux_sda_o_s), + .iic_mux_sda_t (iic_mux_sda_t_s), + .otg_vbusoc (otg_vbusoc), + .spdif (spdif), + .spi0_clk_i (1'b0), + .spi0_clk_o (adf4351_clk), + .spi0_csn_0_o (adf4351_csn), + .spi0_csn_1_o (), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (1'b0), + .spi0_sdo_i (1'b0), + .spi0_sdo_o (adf4351_mosi), + .spi1_clk_i (1'b0), + .spi1_clk_o (), + .spi1_csn_0_o (), + .spi1_csn_1_o (), + .spi1_csn_2_o (), + .spi1_csn_i (1'b1), + .spi1_sdi_i (1'b0), + .spi1_sdo_i (1'b0), + .spi1_sdo_o ()); + +endmodule