diff --git a/Documentation/devicetree/bindings/iio/frequency/adi,adf4030.yaml b/Documentation/devicetree/bindings/iio/frequency/adi,adf4030.yaml
index f0a62590b76550..e728b93e3cb210 100644
--- a/Documentation/devicetree/bindings/iio/frequency/adi,adf4030.yaml
+++ b/Documentation/devicetree/bindings/iio/frequency/adi,adf4030.yaml
@@ -69,6 +69,12 @@ properties:
     minimum: 0
     maximum: 88200
 
+  adi,cmos-3v3-enable:
+    description:
+      When set the CMOS output level is 3.3V. This applies to SPI
+      MUXOUT, and IRQB.(Default is 1.8V)
+    $ref: /schemas/types.yaml#/definitions/flag
+
   clock-output-names:
     description: Names of the clock outputs.
     minItems: 1
diff --git a/drivers/iio/frequency/adf4030.c b/drivers/iio/frequency/adf4030.c
index 1645264a543932..a8d46320a5e69e 100644
--- a/drivers/iio/frequency/adf4030.c
+++ b/drivers/iio/frequency/adf4030.c
@@ -88,6 +88,13 @@
 /* REG 0x5A */
 #define ADF4030_PLL_CAL_EN_MSK		BIT(6)
 
+/* REG 0x5C */
+#define ADF4030_TEMP_INT_MSK		BIT(1)
+#define ADF4030_ALIGN_INT_MSK		BIT(2)
+#define ADF4030_LD_INT_MSK		BIT(3)
+#define ADF4030_TDC_ERR_INT_MSK		BIT(4)
+#define ADF4030_CMOS_OV_MSK		BIT(7)
+
 /* REG 0x61 */
 #define ADF4030_EN_ADC_MSK		BIT(0)
 #define ADF4030_EN_ADC_CLK_MSK		BIT(1)
@@ -202,6 +209,7 @@ struct adf4030_state {
 	unsigned int num_channels;
 	bool adc_enabled;
 	bool spi_3wire_en;
+	bool cmos_3v3_en;
 
 	u8 vals[3] __aligned(IIO_DMA_MINALIGN);
 };
@@ -217,13 +225,13 @@ static const struct regmap_config adf4030_regmap_config = {
 static const struct reg_sequence adf4030_reg_default[] = {
 	{0x6A, 0x0A}, {0x69, 0x0A}, {0x66, 0x80}, {0x64, 0x1E}, {0x63, 0x1E},
 	{0x62, 0x4C}, {0x61, 0x05}, {0x60, 0x2B}, {0x5F, 0x5D}, {0x5E, 0x32},
-	{0x5D, 0x10}, {0x5C, 0x1E}, {0x5B, 0xC9}, {0x5A, 0x17}, {0x59, 0x49},
-	{0x58, 0x53}, {0x57, 0x45}, {0x56, 0x7D}, {0x55, 0x01}, {0x54, 0x90},
-	{0x53, 0x19}, {0x52, 0xE9}, {0x50, 0xE9}, {0x4E, 0xE9}, {0x4C, 0xE9},
-	{0x4A, 0xE9}, {0x48, 0xE9}, {0x46, 0xE9}, {0x44, 0xE9}, {0x42, 0xE9},
-	{0x40, 0xE9}, {0x3C, 0xFF}, {0x3B, 0xFC}, {0x37, 0x02}, {0x35, 0x05},
-	{0x34, 0x24}, {0x33, 0x1D}, {0x32, 0x1D}, {0x31, 0x45}, {0x16, 0x06},
-	{0x11, 0x1F}, {0x10, 0x1F}
+	{0x5D, 0x10}, {0x5B, 0xC9}, {0x5A, 0x17}, {0x59, 0x49}, {0x58, 0x53},
+	{0x57, 0x45}, {0x56, 0x7D}, {0x55, 0x01}, {0x54, 0x90}, {0x53, 0x19},
+	{0x52, 0xE9}, {0x50, 0xE9}, {0x4E, 0xE9}, {0x4C, 0xE9}, {0x4A, 0xE9},
+	{0x48, 0xE9}, {0x46, 0xE9}, {0x44, 0xE9}, {0x42, 0xE9}, {0x40, 0xE9},
+	{0x3C, 0xFF}, {0x3B, 0xFC}, {0x37, 0x02}, {0x35, 0x05}, {0x34, 0x24},
+	{0x33, 0x1D}, {0x32, 0x1D}, {0x31, 0x45}, {0x16, 0x06}, {0x11, 0x1F},
+	{0x10, 0x1F}
 };
 
 static int adf4030_compute_r_n(u32 ref_freq, u32 vco_freq, u32 *rdiv, u32 *ndiv)
@@ -1139,6 +1147,16 @@ static int adf4030_startup(struct adf4030_state *st, u32 ref_input_freq_hz,
 	if (ret)
 		return ret;
 
+	/* Setup the CMOS Level and IRQ Masks */
+	ret = regmap_write(st->regmap, ADF4030_REG(0x5C),
+			   FIELD_PREP(ADF4030_TEMP_INT_MSK, 1) |
+			   FIELD_PREP(ADF4030_ALIGN_INT_MSK, 1) |
+			   FIELD_PREP(ADF4030_LD_INT_MSK, 1) |
+			   FIELD_PREP(ADF4030_TDC_ERR_INT_MSK, 1) |
+			   FIELD_PREP(ADF4030_CMOS_OV_MSK, st->cmos_3v3_en));
+	if (ret)
+		return ret;
+
 	ret = regmap_write(st->regmap, ADF4030_REG(0x01), 0);
 	if (ret)
 		return ret;
@@ -1276,6 +1294,8 @@ static int adf4030_parse_fw(struct adf4030_state *st)
 	st->spi_3wire_en = device_property_read_bool(dev,
 						     "adi,spi-3wire-enable");
 
+	st->cmos_3v3_en = device_property_read_bool(dev, "adi,cmos-3v3-enable");
+
 	ret = device_property_read_u32(dev, "adi,vco-frequency-hz",
 				       &st->vco_freq);
 	if (ret)