change description

pawel-kojma · pawel-kojma · commit e71dadfede50 · 2026-01-09T09:45:42.000+01:00
Signed-off-by: Pawel Kojma &lt;pkojma@internships.antmicro.com&gt;
diff --git a/test_regress/t/t_init_array_bad.v b/test_regress/t/t_init_array_bad.v
@@ -1,4 +1,4 @@
-// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias'
+// DESCRIPTION: Verilator: Verilog Test module
 //
 // This file ONLY is placed under the Creative Commons Public Domain, for
 // any use, without warranty, 2026 by Antmicro.

Original file line number	Diff line number	Diff line change
`@@ -1,4 +1,4 @@`
`1`		`-// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias'`
	`1`	`+// DESCRIPTION: Verilator: Verilog Test module`
`2`	`2`	`//`
`3`	`3`	`// This file ONLY is placed under the Creative Commons Public Domain, for`
`4`	`4`	`// any use, without warranty, 2026 by Antmicro.`