From fa6207d0a23256a9d87f8f191c91b814bfd64e32 Mon Sep 17 00:00:00 2001 From: byby9527 <99935115+byby9527@users.noreply.github.com> Date: Thu, 3 Nov 2022 11:02:05 +0800 Subject: [PATCH] Update CPU.hdl --- 05/CPU.hdl | 29 ++++++++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/05/CPU.hdl b/05/CPU.hdl index 86558934..10574030 100644 --- a/05/CPU.hdl +++ b/05/CPU.hdl @@ -40,4 +40,31 @@ CHIP CPU { PARTS: // Put your code here: -} \ No newline at end of file + Mux16(a = instruction, b = ALUout, sel = instruction[15], out = inA); + Not(in = instruction[15], out = isA); + And(a = instruction[15], b = instruction[5], out = CloadA); + Or(a = isA, b = CloadA, out = loadA); + ARegister(in = inA, load = loadA, out = outA, out[0..14] = addressM, out = pcin); + And(a = instruction[15], b = instruction[4], out = loadD); + DRegister(in = ALUout, load = loadD, out = outD); + And(a = instruction[15], b = instruction[3], out = writeM); + And(a = instruction[12], b = instruction[15], out = sel1); + Mux16(a = outA, b = inM, sel = sel1, out = ALUin); + And(a = instruction[15], b = instruction[11], out = zx); + And(a = instruction[15], b = instruction[10], out = nx); + And(a = instruction[15], b = instruction[9], out = zy); + And(a = instruction[15], b = instruction[8], out = ny); + And(a = instruction[15], b = instruction[7], out = f); + And(a = instruction[15], b = instruction[6], out = no); + ALU(x = outD, y = ALUin, zx = zx, nx = nx, zy = zy, ny = ny, f = f, no = no, out = ALUout, out = outM, zr = zr, ng = ng); + And(a = ng, b = instruction[2], out = t1); // < 0 + And(a = zr, b = instruction[1], out = t2); // = 0 + Or(a = ng, b = zr, out = ngz); + Not(in = ngz, out = pos); + And(a = pos, b = instruction[0], out = t3); // > 0 + Or(a = t1, b = t2, out = tt1); + Or(a = tt1, b = t3, out = tt); + And(a = instruction[15], b = tt, out = PCload); + PC(in = pcin, load = PCload, inc = true, reset = reset, out[0..14] = pc); + +}