Merge pull request #1512 from diffblue/implicit_declaration1

KNOWNBUG test for type of implicit net

Author: tautschnig

regression/verilog/assignments/implicit_declaration1.desc

@@ -0,0 +1,9 @@
+KNOWNBUG
+implicit_declaration1.sv
+
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+This gives the wrong answer.

regression/verilog/assignments/implicit_declaration1.sv

@@ -0,0 +1,11 @@
+module main;
+
+  // 1800-2017 6.10: continuous assignment statements can trigger an
+  // implicit declaration of a "scalar net of default net type".
+  assign some_net0 = 'b10;
+  assign some_net1 = 'b11;
+
+  initial assert($bits(some_net0) == 1 && some_net0 == 0);
+  initial assert($bits(some_net1) == 1 && some_net1 == 1);
+
+endmodule