From 0dbde23a14a1534283e7a6414aa00e5bd98ad162 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Fri, 2 Sep 2022 15:51:48 -0700 Subject: [PATCH 001/244] ARM: dts: imx6: ts7970: Initial commit Cleaned up to match current dts syntax and specifications. There is no longer a need to have seperate dts files for TI vs Silex Wi-Fi chips. Both are able to be supported in the same dts. Signed-off-by: Kris Bahnsen --- arch/arm/boot/dts/nxp/imx/imx6dl-ts7970.dts | 42 +-- arch/arm/boot/dts/nxp/imx/imx6q-ts7970.dts | 42 +-- arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi | 262 ++++++++++++------ 3 files changed, 178 insertions(+), 168 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-ts7970.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-ts7970.dts index 5da6feba2e66a..7eb46c6512289 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-ts7970.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-ts7970.dts @@ -1,43 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 /* - * Copyright 2015 Technologic Systems - * Copyright 2017 Savoir-faire Linux - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * Copyright 2015 Technologic Systems Inc., dba embeddedTS + * Copyright 2017 Savoir-Faire Linux */ /dts-v1/; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-ts7970.dts b/arch/arm/boot/dts/nxp/imx/imx6q-ts7970.dts index 570bd3c309a6e..fb26b15185a08 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-ts7970.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-ts7970.dts @@ -1,43 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 /* - * Copyright 2015 Technologic Systems - * Copyright 2017 Savoir-faire Linux - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * Copyright 2015 Technologic Systems, Inc. dba embeddedTS + * Copyright 2017 Savoir-Faire Linux */ /dts-v1/; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi index 17f6a568f0e8c..949c1f6724b41 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi @@ -1,130 +1,104 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 /* - * Copyright 2015 Technologic Systems + * Copyright 2015-2022 Technologic Systems, Inc. dba embeddedTS * Copyright 2017 Savoir-Faire Linux - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include +#include #include / { - leds { + chosen { + stdout-path = &uart1; + }; + + aliases { + ethernet0 = &fec; + }; + + led-controller { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds1>; + pinctrl-0 = <&pinctrl_gpio_leds>; compatible = "gpio-leds"; - green-led { - label = "green-led"; + led-0 { + color = ; + function = LED_FUNCTION_POWER; gpios = <&gpio3 27 GPIO_ACTIVE_LOW>; default-state = "on"; }; - red-led { - label = "red-led"; + led-1 { + color = ; + function = LED_FUNCTION_STATUS; gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; default-state = "off"; }; - yel-led { - label = "yellow-led"; + led-2 { + color = ; + function = LED_FUNCTION_INDICATOR; gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; default-state = "off"; }; - blue-led { - label = "blue-led"; - gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - en-usb-5v-led { - label = "en-usb-5v"; - gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - sel-dc-usb-led { - label = "sel_dc_usb"; - gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; + led-3 { + color = ; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>; default-state = "off"; }; + }; + reg_1v5: regulator-1v5 { + compatible = "regulator-fixed"; + regulator-name = "AUDIO_1V5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; }; - reg_3p3v: regulator-3p3v { + reg_3v3: regulator-3v3 { compatible = "regulator-fixed"; - regulator-name = "3p3v"; + regulator-name = "3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; - reg_can1_3v3: reg_can1_3v3 { + reg_can1_3v3: regulator-can1-en { compatible = "regulator-fixed"; - regulator-name = "reg_can1_3v3"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1_en>; + regulator-name = "CAN1_EN"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; - enable-active-high; + gpio = <&gpio4 21 GPIO_ACTIVE_LOW>; }; - reg_can2_3v3: en-reg_can2_3v3 { + reg_can2_3v3: regulator-can2-en { compatible = "regulator-fixed"; - regulator-name = "reg_can2_3v3"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2_en>; + regulator-name = "CAN2_EN"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&gpio6 31 GPIO_ACTIVE_HIGH>; - enable-active-high; + gpio = <&gpio6 31 GPIO_ACTIVE_LOW>; }; reg_usb_otg_vbus: regulator-usb-otg-vbus { compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; + regulator-name = "USB_OTG_VBUS"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; enable-active-high; }; - reg_wlan_vmmc: regulator_wlan_vmmc { + reg_wlan_vqmmc: regulator-wlan-vqmmc { compatible = "regulator-fixed"; - regulator-name = "wlan_vmmc"; + regulator-name = "WLAN_1V8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; gpio = <&gpio8 14 GPIO_ACTIVE_HIGH>; @@ -132,7 +106,7 @@ enable-active-high; }; - sound-sgtl5000 { + sound { audio-codec = <&sgtl5000>; audio-routing = "MIC_IN", "Mic Jack", @@ -165,6 +139,7 @@ }; &ecspi1 { + num-cs = <1>; cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; @@ -178,6 +153,7 @@ }; &ecspi2 { + num-cs = <3>; cs-gpios = < &gpio5 31 GPIO_ACTIVE_LOW &gpio7 12 GPIO_ACTIVE_LOW @@ -186,6 +162,19 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi2>; status = "okay"; + + /* CS0# is FPGA emulated MAX3100 UARTs, not compatible with the + * standard kernel drive since multiple UARTs are implemented in the + * single FPGA IP instance. + */ + + /* CS1# is generic FPGA SPI access, normally unused */ + + spidevhd1: spi@2 { + compatible = "spidev"; + reg = <2>; + spi-max-frequency = <1000000>; + }; }; &fec { @@ -199,7 +188,42 @@ status = "okay"; }; +&gpio2 { + gpio-line-names = "", "", "", "", "", "", "", "", "", "", "", + "USB_HUB_RESET#", "", "", "", "", "", "", "", + "EN_MODBUS_24V", "", "I210_RESET#", "EN_USB_5V", "BUS_CS", + "", "MODBUS_FAULT", "BUS_DIR", "BUS_ALE#", "", "BUS_BHE#", "", ""; +}; + +&gpio3 { + gpio-line-names = "MUX_AD_00", "MUX_AD_01", "MUX_AD_02", "MUX_AD_03", + "MUX_AD_04", "MUX_AD_05", "MUX_AD_06", "MUX_AD_07", "MUX_AD_08", + "MUX_AD_09", "MUX_AD_10", "MUX_AD_11", "MUX_AD_12", "MUX_AD_13", + "MUX_AD_14", "MUX_AD_15", "", "", "", "", "", "", "", + "EN_RTC_PWR#", "", "", "", "", "", "", "", ""; + + en-rtc-hog { + gpio-hog; + gpios = <23 GPIO_ACTIVE_HIGH>; + output-low; + }; +}; + +&gpio4 { + gpio-line-names = "", "", "", "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", "", "", "", + "EN_MODBUS_3V#", "", "LCD_D09", "", "HD1_IRQ", "LCD_D10"; +}; + +&gpio5 { + gpio-line-names = "BUS_WAIT#", "", "", "", "DIO_20", "LCD_D11", "", "", + "", "JTAG_FPGA_TMS", "", "", "JTAG_FPGA_TCK", "JTAG_FPGA_TDO", + "", "GYRO_INT", "", "", "SEL_DC_USB#", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + &hdmi { + ddc-i2c-bus = <&i2c2>; status = "okay"; }; @@ -208,8 +232,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; m41t00s: rtc@68 { @@ -228,17 +252,23 @@ #gpio-cells = <2>; gpio-controller; ngpios = <62>; + base = <224>; + gpio-line-names = "", "", "", "", "", "", "", "", "", "", "", + "", "", "BT_EN", "WL_EN", "", "", "", "", "HD1_DIO_1", + "HD1_DIO_2", "HD1_DIO_3", "HD1_DIO_4", "HD1_DIO_5", + "HD1_DIO_6", "EN_OUT_1", "EN_OUT_2"; }; - sgtl5000: codec@a { + sgtl5000: audio-codec@a { compatible = "fsl,sgtl5000"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sgtl5000>; reg = <0x0a>; #sound-dai-cells = <0>; clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; + VDDA-supply = <®_3v3>; + VDDIO-supply = <®_3v3>; + VDDD-supply = <®_1v5>; }; }; @@ -247,8 +277,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; pinctrl-1 = <&pinctrl_i2c2_gpio>; - scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; }; @@ -307,6 +337,11 @@ fsl,pins = < MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b088 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b088 + >; + }; + + pinctrl_flexcan1_en: flexcan1engrp { + fsl,pins = < MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x1b088 /* EN_CAN_1 */ >; }; @@ -315,10 +350,21 @@ fsl,pins = < MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b088 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b088 + >; + }; + + pinctrl_flexcan2_en: flexcan2engrp { + fsl,pins = < MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b088 /* EN_CAN_2 */ >; }; + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b088 /* I210_RESET */ + >; + }; + pinctrl_hog: hoggrp { fsl,pins = < /* Onboard */ @@ -334,9 +380,7 @@ MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b088 /* BUS_DIR/JP_SD_BOOT */ MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b088 /* EN_MODBUS_24V */ MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b088 /* EN_MODBUS_3V */ - MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b088 /* I210_RESET */ MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b088 /* EN_RTC_PWR */ - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b088 /* REVSTRAP1 */ /* Offboard */ MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b088 /* LCD_D09 */ @@ -368,6 +412,9 @@ /* Strapping only */ MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b088 MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x1b088 + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b088 /* REV STRAP B */ + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b088 /* REV STRAP C */ + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b088 /* Rev STRAP H */ >; }; @@ -399,7 +446,7 @@ >; }; - pinctrl_leds1: leds1grp { + pinctrl_gpio_leds: leds1grp { fsl,pins = < MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b088 /* GREEN_LED */ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b088 /* RED_LED */ @@ -475,6 +522,28 @@ >; }; + pinctrl_usdhc1_100mhz: usdhc1grp-100mhz { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170B9 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100B9 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170B9 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170B9 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170B9 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170B9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp-200mhz { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170F9 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100F9 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170F9 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170F9 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170F9 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170F9 + >; + }; + pinctrl_usdhc2: usdhc2grp { fsl,pins = < MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 @@ -500,6 +569,9 @@ }; &pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio2 21 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -556,16 +628,22 @@ /* WIFI */ &usdhc1 { - pinctrl-names = "default"; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; - vmmc-supply = <®_wlan_vmmc>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + vmmc-supply = <®_3v3>; + vqmmc-supply = <®_wlan_vqmmc>; bus-width = <4>; + fsl,tuning-step = <2>; + cap-sdio-irq; non-removable; + keep-power-in-suspend; #address-cells = <1>; #size-cells = <0>; status = "okay"; - wlcore: wlcore@2 { + wlcore: wifi@2 { compatible = "ti,wl1271"; reg = <2>; interrupt-parent = <&gpio1>; @@ -578,9 +656,11 @@ &usdhc2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc2>; - vmmc-supply = <®_3p3v>; + vmmc-supply = <®_3v3>; + vqmmc-supply = <®_3v3>; bus-width = <4>; fsl,wp-controller; + no-1-8-v; status = "okay"; }; @@ -588,8 +668,10 @@ &usdhc3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc3>; - vmmc-supply = <®_3p3v>; + vmmc-supply = <®_3v3>; + vqmmc-supply = <®_3v3>; bus-width = <4>; non-removable; + no-1-8-v; status = "okay"; }; From 81deb8a054822d0f00e279a15e90d72d625c2e20 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Thu, 16 Dec 2021 13:34:08 -0800 Subject: [PATCH 002/244] wlcore: Enable PM operations on card during probe Needed since there was some change in the PM system that would cause an error if PM runtime was not specifically enabled before the call. Signed-off-by: Kris Bahnsen --- drivers/net/wireless/ti/wlcore/sdio.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/net/wireless/ti/wlcore/sdio.c b/drivers/net/wireless/ti/wlcore/sdio.c index a73207bbe5d7a..982d5b6440c92 100644 --- a/drivers/net/wireless/ti/wlcore/sdio.c +++ b/drivers/net/wireless/ti/wlcore/sdio.c @@ -289,6 +289,14 @@ static int wl1271_probe(struct sdio_func *func, if (ret) goto out; + /* Enable PM runtime for the card. This is needed for the call to + * pm_runtime_get_sync in power control. Without enabling PM runtime, + * those calls will fail. There is a proposed patch that might address + * this, see https://lore.kernel.org/linux-arm-kernel/641a41bc-68ea-c0e9-9430-faf3803e12d5@ti.com/T/ However this has not been upstreamed at all and this is a tested + * workaround that doesn't change core PM functionality. + */ + pm_runtime_enable(&func->card->dev); + /* if sdio can keep power while host is suspended, enable wow */ mmcflags = sdio_get_host_pm_caps(func); dev_dbg(glue->dev, "sdio PM caps = 0x%x\n", mmcflags); From 97ba04bbf6c3b7b2041c0a379c05fcfdd337f73f Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Fri, 31 Aug 2018 08:42:44 -0700 Subject: [PATCH 003/244] gpio: gpio-ts4900: Added device tree base property This allows consistent numbering between products. While not required, this makes the gpio numbers in our manuals match linux. commit 1cdddde5f71acd177532794e52730f255e1e35ea in https://github.com/embeddedarm/linux-tsimx/ Signed-off-by: Kris Bahnsen --- drivers/gpio/gpio-ts4900.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpio/gpio-ts4900.c b/drivers/gpio/gpio-ts4900.c index d9ee8fc77ccdf..7f6ce22b9d039 100644 --- a/drivers/gpio/gpio-ts4900.c +++ b/drivers/gpio/gpio-ts4900.c @@ -140,11 +140,16 @@ static int ts4900_gpio_probe(struct i2c_client *client) { struct ts4900_gpio_priv *priv; u32 ngpio; + u32 base; int ret; if (device_property_read_u32(&client->dev, "ngpios", &ngpio)) ngpio = DEFAULT_PIN_NUMBER; + if (of_property_read_u32(client->dev.of_node, "base", &base)) + base = -1; + + priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL); if (!priv) return -ENOMEM; @@ -152,6 +157,7 @@ static int ts4900_gpio_probe(struct i2c_client *client) priv->gpio_chip = template_chip; priv->gpio_chip.label = "ts4900-gpio"; priv->gpio_chip.ngpio = ngpio; + priv->gpio_chip.base = base; priv->gpio_chip.parent = &client->dev; priv->input_bit = (uintptr_t)device_get_match_data(&client->dev); From 0b98d653be1368a9ebe65abad2bac972e2000fd9 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Wed, 26 Oct 2022 11:56:26 -0700 Subject: [PATCH 004/244] firmware: sdma-imx6q: Initial commit of SDMA FW Version 3.5 from linux-firmware Signed-off-by: Kris Bahnsen --- firmware/imx/sdma/sdma-imx6q.bin | Bin 0 -> 2746 bytes 1 file changed, 0 insertions(+), 0 deletions(-) create mode 100644 firmware/imx/sdma/sdma-imx6q.bin diff --git a/firmware/imx/sdma/sdma-imx6q.bin b/firmware/imx/sdma/sdma-imx6q.bin new file mode 100644 index 0000000000000000000000000000000000000000..4d0593cec7dfdae1a8bf28a2d83bdd1e95839b82 GIT binary patch literal 2746 zcmb7GU2GiH6+UzK&dkoNo%I@)4XKUY5Y|qp6H?SdX@sGwDnGCZjDK;wW|_n#o;bE& zq8NJbjM^t?(zufIuzykg&=-WLR0&>C1o2uTBaui!%TI_CA+b;aP8y`3(qtvJ=g#bS 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z584?yV4}z4V4L?0RN_lk8GNiD@)sH)7)WC4^&-O8(bqj+cp7?|rD2|`1F$j-DcQ^8 z+q{pnn)el6wyHzN$qBp}Tyv5n`H6d$r_0l>DPgr;>qIh(zH4Ta%hMSW<-RvXLR>_S z6b_{#2dOdn+ccHLgjBP~+u!Oa zuY3n(xAnE7mtHA6bV=OuvUO&%QS;z7kK>NN2XAxN?6xyXP~pv9Z9BYYn|G66W67eZ zEuLjFV%>+fuynMFa{8`zz1rYI)=+RL6HM#p@a$ zLyi9`9Vk4cDBoQSt77C)ST^24-M)gl-CLBVBhT)zBW8~s*>}I))GY481U*T^?Pq0) zH8sC$LG)LuJ9Bxa%{dMyK{^n5E@8iakcJWEOsg7Wk>{dz;OXr0OxSsMQi_T z-CtCphW|8x>@U7o=dEg-S$D7gaORfRF;`k+uJk{dTPUt)?#iV<7k>zItG8k9Qt>~J Ckg?GK literal 0 HcmV?d00001 From 8f3b1f20b9237c554ae1be946fafb50c0cdb3a3e Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Fri, 2 Sep 2022 16:15:25 -0700 Subject: [PATCH 005/244] ARM: configs: tsimx6_defconfig: Initial commit Based on previous 5.10 builds Adds GPU workaround by setting CMA area to 128 M instead of 320 M that we've used in the past: https://www.spinics.net/lists/dri-devel/msg296244.html Signed-off-by: Kris Bahnsen --- arch/arm/configs/tsimx6_defconfig | 1625 +++++++++++++++++++++++++++++ 1 file changed, 1625 insertions(+) create mode 100644 arch/arm/configs/tsimx6_defconfig diff --git a/arch/arm/configs/tsimx6_defconfig b/arch/arm/configs/tsimx6_defconfig new file mode 100644 index 0000000000000..29daca9da6903 --- /dev/null +++ b/arch/arm/configs/tsimx6_defconfig @@ -0,0 +1,1625 @@ +CONFIG_KERNEL_XZ=y +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_USELIB=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_PREEMPT=y +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_CGROUPS=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CPUSETS=y +# CONFIG_PROC_PID_CPUSET is not set +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_BPF=y +CONFIG_CGROUP_DEBUG=y +CONFIG_NAMESPACES=y +CONFIG_USER_NS=y +CONFIG_CHECKPOINT_RESTORE=y +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_BPF_SYSCALL=y +CONFIG_EMBEDDED=y +# CONFIG_COMPAT_BRK is not set +CONFIG_ARCH_MXC=y +CONFIG_SOC_IMX6Q=y +CONFIG_SOC_IMX6SL=y +CONFIG_SOC_IMX6SLL=y +CONFIG_SOC_IMX6SX=y +CONFIG_ARM_ERRATA_814220=y +CONFIG_SMP=y +CONFIG_HAVE_ARM_ARCH_TIMER=y +CONFIG_ARM_PSCI=y +CONFIG_HZ_1000=y +CONFIG_HIGHMEM=y +CONFIG_FORCE_MAX_ZONEORDER=14 +CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" +CONFIG_KEXEC=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y +CONFIG_ARM_IMX6Q_CPUFREQ=y +CONFIG_CPU_IDLE=y +CONFIG_ARM_CPUIDLE=y +CONFIG_ARM_PSCI_CPUIDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_PM_DEBUG=y +CONFIG_PM_TEST_SUSPEND=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_BLK_DEV_INTEGRITY=y +CONFIG_BLK_CMDLINE_PARSER=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_BINFMT_MISC=y +# CONFIG_COREDUMP is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_PACKET_DIAG=m +CONFIG_UNIX=y +CONFIG_UNIX_DIAG=m +CONFIG_XFRM_USER=m +CONFIG_XFRM_SUB_POLICY=y +CONFIG_XFRM_STATISTICS=y +CONFIG_NET_KEY=m +CONFIG_NET_KEY_MIGRATE=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_FIB_TRIE_STATS=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE_DEMUX=m +CONFIG_NET_IPGRE=m +CONFIG_NET_IPGRE_BROADCAST=y +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_NET_IPVTI=m +CONFIG_NET_FOU_IP_TUNNELS=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_UDP_DIAG=m +CONFIG_INET_DIAG_DESTROY=y +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_TCP_CONG_HSTCP=m +CONFIG_TCP_CONG_HYBLA=m +CONFIG_TCP_CONG_NV=m +CONFIG_TCP_CONG_SCALABLE=m +CONFIG_TCP_CONG_LP=m +CONFIG_TCP_CONG_VENO=m +CONFIG_TCP_CONG_YEAH=m +CONFIG_TCP_CONG_ILLINOIS=m +CONFIG_TCP_CONG_DCTCP=m +CONFIG_TCP_CONG_CDG=m +CONFIG_TCP_CONG_BBR=m +CONFIG_TCP_MD5SIG=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_MIP6=m +CONFIG_IPV6_ILA=m +CONFIG_IPV6_VTI=m +CONFIG_IPV6_SIT=m +CONFIG_IPV6_SIT_6RD=y +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y +CONFIG_IPV6_PIMSM_V2=y +CONFIG_NETWORK_SECMARK=y +CONFIG_NETWORK_PHY_TIMESTAMPING=y +CONFIG_NETFILTER=y +CONFIG_NF_CONNTRACK=m +CONFIG_NF_CONNTRACK_ZONES=y +CONFIG_NF_CONNTRACK_PROCFS=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_TIMEOUT=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y +CONFIG_NF_CONNTRACK_AMANDA=m +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_SNMP=m +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_CT_NETLINK=m +CONFIG_NF_CT_NETLINK_TIMEOUT=m +CONFIG_NETFILTER_NETLINK_GLUE_CT=y +CONFIG_NF_TABLES=m +CONFIG_NFT_NUMGEN=m +CONFIG_NFT_CT=m +CONFIG_NFT_COUNTER=m +CONFIG_NFT_LOG=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_REDIR=m +CONFIG_NFT_QUEUE=m +CONFIG_NFT_QUOTA=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_HASH=m +CONFIG_NETFILTER_XT_SET=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LED=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_TEE=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m +CONFIG_NETFILTER_XT_MATCH_CGROUP=m +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_CPU=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_IPCOMP=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_IPVS=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +CONFIG_IP_SET=m +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPMARK=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_MAC=m +CONFIG_IP_SET_HASH_NETPORTNET=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETNET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m +CONFIG_IP_VS=m +CONFIG_IP_VS_IPV6=y +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_AH=y +CONFIG_IP_VS_PROTO_SCTP=y +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_WRR=m +CONFIG_IP_VS_LC=m +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_FO=m +CONFIG_IP_VS_OVF=m +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_NQ=m +CONFIG_IP_VS_FTP=m +CONFIG_IP_VS_PE_SIP=m +CONFIG_NF_LOG_ARP=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_SYNPROXY=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m +CONFIG_DECNET_NF_GRABULATOR=m +CONFIG_NF_TABLES_BRIDGE=m +CONFIG_NFT_BRIDGE_META=m +CONFIG_NF_LOG_BRIDGE=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_IP6=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_NFLOG=m +CONFIG_IP_DCCP=m +CONFIG_IP_SCTP=m +CONFIG_RDS=m +CONFIG_RDS_TCP=m +CONFIG_TIPC=m +CONFIG_ATM=m +CONFIG_ATM_CLIP=m +CONFIG_ATM_LANE=m +CONFIG_ATM_MPOA=m +CONFIG_ATM_BR2684=m +CONFIG_L2TP=m +CONFIG_L2TP_V3=y +CONFIG_L2TP_IP=m +CONFIG_L2TP_ETH=m +CONFIG_BRIDGE=m +CONFIG_NET_DSA=m +CONFIG_VLAN_8021Q=m +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_VLAN_8021Q_MVRP=y +CONFIG_DECNET=m +CONFIG_DECNET_ROUTER=y +CONFIG_LLC2=m +CONFIG_ATALK=m +CONFIG_DEV_APPLETALK=m +CONFIG_IPDDP=m +CONFIG_IPDDP_ENCAP=y +CONFIG_X25=m +CONFIG_LAPB=m +CONFIG_PHONET=m +CONFIG_6LOWPAN=m +CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m +CONFIG_6LOWPAN_GHC_UDP=m +CONFIG_6LOWPAN_GHC_ICMPV6=m +CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m +CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m +CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m +CONFIG_IEEE802154=m +CONFIG_IEEE802154_6LOWPAN=m +CONFIG_MAC802154=m +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_ATM=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_MULTIQ=m +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFB=m +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_DSMARK=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_DRR=m +CONFIG_NET_SCH_MQPRIO=m +CONFIG_NET_SCH_CHOKE=m +CONFIG_NET_SCH_QFQ=m +CONFIG_NET_SCH_CODEL=m +CONFIG_NET_SCH_FQ_CODEL=m +CONFIG_NET_SCH_FQ=m +CONFIG_NET_SCH_HHF=m +CONFIG_NET_SCH_PIE=m +CONFIG_NET_SCH_INGRESS=m +CONFIG_NET_SCH_PLUG=m +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_TCINDEX=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +CONFIG_CLS_U32_PERF=y +CONFIG_CLS_U32_MARK=y +CONFIG_NET_CLS_RSVP=m +CONFIG_NET_CLS_RSVP6=m +CONFIG_NET_CLS_FLOW=m +CONFIG_NET_CLS_CGROUP=m +CONFIG_NET_CLS_BPF=m +CONFIG_NET_CLS_FLOWER=m +CONFIG_NET_CLS_MATCHALL=m +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_CMP=m +CONFIG_NET_EMATCH_NBYTE=m +CONFIG_NET_EMATCH_U32=m +CONFIG_NET_EMATCH_META=m +CONFIG_NET_EMATCH_TEXT=m +CONFIG_NET_EMATCH_CANID=m +CONFIG_NET_EMATCH_IPSET=m +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=m +CONFIG_NET_ACT_GACT=m +CONFIG_GACT_PROB=y +CONFIG_NET_ACT_MIRRED=m +CONFIG_NET_ACT_IPT=m +CONFIG_NET_ACT_NAT=m +CONFIG_NET_ACT_PEDIT=m +CONFIG_NET_ACT_SIMP=m +CONFIG_NET_ACT_SKBEDIT=m +CONFIG_NET_ACT_CSUM=m +CONFIG_NET_ACT_VLAN=m +CONFIG_NET_ACT_BPF=m +CONFIG_NET_ACT_CONNMARK=m +CONFIG_NET_ACT_SKBMOD=m +CONFIG_NET_ACT_IFE=m +CONFIG_NET_ACT_TUNNEL_KEY=m +CONFIG_DCB=y +CONFIG_BATMAN_ADV=m +CONFIG_BATMAN_ADV_NC=y +CONFIG_BATMAN_ADV_DEBUG=y +CONFIG_OPENVSWITCH=m +CONFIG_VSOCKETS=m +CONFIG_NETLINK_DIAG=m +CONFIG_MPLS_ROUTING=m +CONFIG_MPLS_IPTUNNEL=m +CONFIG_HSR=m +CONFIG_NET_NCSI=y +CONFIG_CGROUP_NET_PRIO=y +CONFIG_BPF_JIT=y +CONFIG_CAN=y +CONFIG_CAN_VCAN=m +CONFIG_CAN_SLCAN=m +CONFIG_CAN_FLEXCAN=y +CONFIG_CAN_8DEV_USB=m +CONFIG_CAN_EMS_USB=m +CONFIG_CAN_ESD_USB2=m +CONFIG_CAN_GS_USB=m +CONFIG_CAN_KVASER_USB=m +CONFIG_CAN_PEAK_USB=m +CONFIG_BT=m +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=y +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_CMTP=m +CONFIG_BT_HIDP=y +CONFIG_BT_6LOWPAN=m +CONFIG_BT_LEDS=y +CONFIG_BT_HCIBTUSB=m +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_BCSP=y +CONFIG_BT_HCIUART_ATH3K=y +CONFIG_BT_HCIUART_LL=y +CONFIG_BT_HCIUART_3WIRE=y +CONFIG_BT_HCIUART_INTEL=y +CONFIG_BT_HCIUART_BCM=y +CONFIG_BT_HCIUART_QCA=y +CONFIG_BT_HCIUART_AG6XX=y +CONFIG_BT_HCIUART_MRVL=y +CONFIG_BT_HCIBCM203X=m +CONFIG_BT_HCIBPA10X=m +CONFIG_BT_HCIBFUSB=m +CONFIG_BT_HCIVHCI=m +CONFIG_BT_MRVL=m +CONFIG_BT_ATH3K=m +CONFIG_CFG80211=m +CONFIG_NL80211_TESTMODE=y +CONFIG_CFG80211_CERTIFICATION_ONUS=y +CONFIG_CFG80211_REG_CELLULAR_HINTS=y +CONFIG_CFG80211_REG_RELAX_NO_IR=y +CONFIG_MAC80211=m +CONFIG_MAC80211_MESH=y +CONFIG_MAC80211_MESSAGE_TRACING=y +CONFIG_RFKILL=m +CONFIG_RFKILL_INPUT=y +CONFIG_RFKILL_GPIO=m +CONFIG_CAIF=m +CONFIG_CAIF_USB=m +CONFIG_NFC=m +CONFIG_NFC_DIGITAL=m +CONFIG_NFC_NCI=m +CONFIG_NFC_NCI_SPI=m +CONFIG_NFC_NCI_UART=m +CONFIG_NFC_HCI=m +CONFIG_NFC_SHDLC=y +CONFIG_NFC_PORT100=m +CONFIG_NFC_PN533_USB=m +CONFIG_NFC_MRVL_USB=m +CONFIG_PCI=y +CONFIG_PCI_MSI=y +CONFIG_PCI_IMX6=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +CONFIG_EXTRA_FIRMWARE="imx/sdma/sdma-imx6q.bin" +CONFIG_EXTRA_FIRMWARE_DIR="firmware" +CONFIG_FW_LOADER_USER_HELPER=y +CONFIG_IMX_WEIM=y +CONFIG_CONNECTOR=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_OF_PARTS=m +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_DATAFLASH=y +CONFIG_MTD_SST25L=y +CONFIG_MTD_SPI_NOR=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_NBD=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=65536 +CONFIG_CDROM_PKTCDVD=m +CONFIG_ATA_OVER_ETH=m +CONFIG_BLK_DEV_NVME=m +CONFIG_NVME_TARGET=m +CONFIG_NVME_TARGET_LOOP=m +CONFIG_C2PORT=m +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_AT25=y +CONFIG_TI_ST=m +CONFIG_RAID_ATTRS=m +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_ST=m +CONFIG_BLK_DEV_SR=m +CONFIG_CHR_DEV_SG=m +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_SCSI_FC_ATTRS=m +CONFIG_SCSI_ISCSI_ATTRS=m +CONFIG_SCSI_SAS_LIBSAS=m +CONFIG_SCSI_SRP_ATTRS=m +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_ATA=y +CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_AHCI_IMX=y +CONFIG_PATA_IMX=y +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_LINEAR=y +CONFIG_MD_RAID0=y +CONFIG_MD_RAID1=y +CONFIG_MD_RAID10=y +CONFIG_MD_RAID456=y +CONFIG_MD_MULTIPATH=y +CONFIG_BCACHE=m +CONFIG_BLK_DEV_DM=y +CONFIG_DM_CRYPT=y +CONFIG_DM_SNAPSHOT=y +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_DM_CACHE=m +CONFIG_DM_ERA=m +CONFIG_DM_MIRROR=m +CONFIG_DM_LOG_USERSPACE=m +CONFIG_DM_RAID=m +CONFIG_DM_ZERO=m +CONFIG_DM_MULTIPATH=m +CONFIG_DM_MULTIPATH_QL=m +CONFIG_DM_MULTIPATH_ST=m +CONFIG_DM_DELAY=m +CONFIG_DM_FLAKEY=m +CONFIG_DM_VERITY=m +CONFIG_DM_SWITCH=m +CONFIG_DM_LOG_WRITES=m +CONFIG_NETDEVICES=y +CONFIG_BONDING=m +CONFIG_EQUALIZER=m +CONFIG_IFB=m +CONFIG_NET_TEAM=m +CONFIG_MACVLAN=m +CONFIG_MACVTAP=m +CONFIG_IPVLAN=m +CONFIG_VXLAN=m +CONFIG_GENEVE=m +CONFIG_GTP=m +CONFIG_MACSEC=m +CONFIG_NETCONSOLE=m +CONFIG_NETCONSOLE_DYNAMIC=y +CONFIG_TUN=m +CONFIG_VETH=m +CONFIG_NLMON=m +CONFIG_NET_VRF=m +CONFIG_ARCNET=m +CONFIG_ARCNET_1201=m +CONFIG_ARCNET_1051=m +CONFIG_ARCNET_RAW=m +CONFIG_ARCNET_CAP=m +CONFIG_ARCNET_COM90xx=m +CONFIG_ARCNET_COM90xxIO=m +CONFIG_ARCNET_RIM_I=m +CONFIG_ARCNET_COM20020=m +CONFIG_ATM_TCP=m +CONFIG_NET_DSA_MV88E6060=m +CONFIG_NET_DSA_MV88E6XXX=m +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_ADAPTEC is not set +# CONFIG_NET_VENDOR_AGERE is not set +# CONFIG_NET_VENDOR_ALTEON is not set +# CONFIG_NET_VENDOR_AMD is not set +# CONFIG_NET_VENDOR_ARC is not set +CONFIG_ATL2=m +CONFIG_ATL1=m +CONFIG_ATL1E=m +CONFIG_ATL1C=m +CONFIG_ALX=m +# CONFIG_NET_VENDOR_BROADCOM is not set +CONFIG_CS89x0=y +CONFIG_CS89x0_PLATFORM=y +# CONFIG_NET_VENDOR_FARADAY is not set +CONFIG_IGB=y +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +CONFIG_8139CP=m +CONFIG_8139TOO=m +CONFIG_R8169=m +# CONFIG_NET_VENDOR_SEEQ is not set +CONFIG_SMC91X=m +CONFIG_EPIC100=m +CONFIG_SMC911X=m +CONFIG_SMSC911X=m +CONFIG_SMSC9420=m +# CONFIG_NET_VENDOR_STMICRO is not set +CONFIG_TLAN=m +CONFIG_FDDI=m +CONFIG_DEFXX=m +CONFIG_SKFP=m +CONFIG_MICREL_PHY=y +CONFIG_PPP=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_MPPE=m +CONFIG_PPPOATM=m +CONFIG_PPPOE=m +CONFIG_PPTP=m +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_SLIP=m +CONFIG_SLIP_COMPRESSED=y +CONFIG_SLIP_SMART=y +CONFIG_SLIP_MODE_SLIP6=y +CONFIG_USB_CATC=m +CONFIG_USB_KAWETH=m +CONFIG_USB_PEGASUS=m +CONFIG_USB_RTL8150=m +CONFIG_USB_RTL8152=m +CONFIG_USB_LAN78XX=m +CONFIG_USB_NET_CDC_EEM=m +CONFIG_USB_NET_HUAWEI_CDC_NCM=m +CONFIG_USB_NET_CDC_MBIM=m +CONFIG_USB_NET_DM9601=m +CONFIG_USB_NET_SR9700=m +CONFIG_USB_NET_SR9800=m +CONFIG_USB_NET_SMSC75XX=m +CONFIG_USB_NET_SMSC95XX=m +CONFIG_USB_NET_GL620A=m +CONFIG_USB_NET_PLUSB=m +CONFIG_USB_NET_MCS7830=m +CONFIG_USB_ALI_M5632=y +CONFIG_USB_NET_CX82310_ETH=m +CONFIG_USB_NET_KALMIA=m +CONFIG_USB_NET_QMI_WWAN=m +CONFIG_USB_HSO=m +CONFIG_USB_NET_INT51X1=m +CONFIG_USB_CDC_PHONET=m +CONFIG_USB_IPHETH=m +CONFIG_USB_SIERRA_NET=m +CONFIG_USB_VL600=m +CONFIG_USB_NET_CH9200=m +CONFIG_ATH5K=m +CONFIG_ATH9K=m +CONFIG_ATH9K_HTC=m +CONFIG_CARL9170=m +CONFIG_ATH6KL=m +CONFIG_ATH6KL_USB=m +CONFIG_AR5523=m +CONFIG_WIL6210=m +CONFIG_ATH10K=m +CONFIG_ATH10K_SDIO=m +CONFIG_WCN36XX=m +CONFIG_ATMEL=m +CONFIG_PCI_ATMEL=m +CONFIG_AT76C50X_USB=m +CONFIG_B43=m +CONFIG_B43LEGACY=m +CONFIG_BRCMSMAC=m +CONFIG_BRCMFMAC=m +CONFIG_BRCMFMAC_USB=y +CONFIG_BRCMFMAC_PCIE=y +CONFIG_IPW2100=m +CONFIG_IPW2100_MONITOR=y +CONFIG_IPW2200=m +CONFIG_IPW2200_MONITOR=y +CONFIG_IPW2200_PROMISCUOUS=y +CONFIG_IPW2200_QOS=y +CONFIG_IWL4965=m +CONFIG_IWL3945=m +CONFIG_IWLWIFI=m +CONFIG_IWLDVM=m +CONFIG_IWLMVM=m +CONFIG_IWLWIFI_BCAST_FILTERING=y +CONFIG_HOSTAP=m +CONFIG_HOSTAP_FIRMWARE=y +CONFIG_HOSTAP_PLX=m +CONFIG_HOSTAP_PCI=m +CONFIG_HERMES=m +CONFIG_PLX_HERMES=m +CONFIG_TMD_HERMES=m +CONFIG_NORTEL_HERMES=m +CONFIG_ORINOCO_USB=m +CONFIG_P54_COMMON=m +CONFIG_P54_USB=m +CONFIG_P54_PCI=m +CONFIG_PRISM54=m +CONFIG_LIBERTAS=m +CONFIG_LIBERTAS_USB=m +CONFIG_LIBERTAS_SDIO=m +CONFIG_LIBERTAS_SPI=m +CONFIG_LIBERTAS_THINFIRM=m +CONFIG_LIBERTAS_THINFIRM_USB=m +CONFIG_MWIFIEX=m +CONFIG_MWIFIEX_SDIO=m +CONFIG_MWIFIEX_PCIE=m +CONFIG_MWIFIEX_USB=m +CONFIG_MWL8K=m +CONFIG_MT7601U=m +CONFIG_RT2X00=m +CONFIG_RT2400PCI=m +CONFIG_RT2500PCI=m +CONFIG_RT61PCI=m +CONFIG_RT2800PCI=m +CONFIG_RT2500USB=m +CONFIG_RT73USB=m +CONFIG_RT2800USB=m +CONFIG_RT2800USB_RT3573=y +CONFIG_RT2800USB_RT53XX=y +CONFIG_RT2800USB_RT55XX=y +CONFIG_RT2800USB_UNKNOWN=y +CONFIG_RTL8180=m +CONFIG_RTL8187=m +CONFIG_RTL8XXXU=m +CONFIG_RTL8XXXU_UNTESTED=y +CONFIG_WL12XX=m +CONFIG_WLCORE_SDIO=m +# CONFIG_WILINK_PLATFORM_DATA is not set +CONFIG_USB_ZD1201=m +CONFIG_ZD1211RW=m +CONFIG_MAC80211_HWSIM=m +CONFIG_USB_NET_RNDIS_WLAN=m +CONFIG_WAN=y +CONFIG_HDLC=m +CONFIG_HDLC_RAW=m +CONFIG_HDLC_RAW_ETH=m +CONFIG_HDLC_CISCO=m +CONFIG_HDLC_FR=m +CONFIG_HDLC_PPP=m +CONFIG_HDLC_X25=m +CONFIG_PCI200SYN=m +CONFIG_WANXL=m +CONFIG_PC300TOO=m +CONFIG_FARSYNC=m +CONFIG_SLIC_DS26522=m +CONFIG_DLCI=m +CONFIG_LAPBETHER=m +CONFIG_X25_ASY=m +CONFIG_IEEE802154_FAKELB=m +CONFIG_IEEE802154_AT86RF230=m +CONFIG_IEEE802154_MRF24J40=m +CONFIG_IEEE802154_CC2520=m +CONFIG_IEEE802154_ATUSB=m +CONFIG_IEEE802154_ADF7242=m +CONFIG_ISDN=y +CONFIG_MISDN=m +CONFIG_MISDN_DSP=m +CONFIG_MISDN_L1OIP=m +CONFIG_MISDN_HFCPCI=m +CONFIG_MISDN_HFCMULTI=m +CONFIG_MISDN_HFCUSB=m +CONFIG_MISDN_AVMFRITZ=m +CONFIG_MISDN_SPEEDFAX=m +CONFIG_MISDN_INFINEON=m +CONFIG_MISDN_W6692=m +CONFIG_MISDN_NETJET=m +CONFIG_INPUT_SPARSEKMAP=m +CONFIG_INPUT_MATRIXKMAP=y +CONFIG_INPUT_MOUSEDEV=m +CONFIG_INPUT_JOYDEV=m +CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_GPIO_POLLED=m +# CONFIG_MOUSE_PS2 is not set +CONFIG_MOUSE_SERIAL=m +CONFIG_MOUSE_APPLETOUCH=m +CONFIG_MOUSE_BCM5974=m +CONFIG_MOUSE_GPIO=m +CONFIG_MOUSE_SYNAPTICS_USB=m +CONFIG_INPUT_JOYSTICK=y +CONFIG_JOYSTICK_ANALOG=m +CONFIG_JOYSTICK_A3D=m +CONFIG_JOYSTICK_ADI=m +CONFIG_JOYSTICK_COBRA=m +CONFIG_JOYSTICK_GF2K=m +CONFIG_JOYSTICK_GRIP=m +CONFIG_JOYSTICK_GRIP_MP=m +CONFIG_JOYSTICK_GUILLEMOT=m +CONFIG_JOYSTICK_INTERACT=m +CONFIG_JOYSTICK_SIDEWINDER=m +CONFIG_JOYSTICK_TMDC=m +CONFIG_JOYSTICK_IFORCE=m +CONFIG_JOYSTICK_IFORCE_USB=m +CONFIG_JOYSTICK_IFORCE_232=m +CONFIG_JOYSTICK_WARRIOR=m +CONFIG_JOYSTICK_MAGELLAN=m +CONFIG_JOYSTICK_SPACEORB=m +CONFIG_JOYSTICK_SPACEBALL=m +CONFIG_JOYSTICK_STINGER=m +CONFIG_JOYSTICK_TWIDJOY=m +CONFIG_JOYSTICK_ZHENHUA=m +CONFIG_JOYSTICK_AS5011=m +CONFIG_JOYSTICK_JOYDUMP=m +CONFIG_JOYSTICK_XPAD=m +CONFIG_JOYSTICK_XPAD_FF=y +CONFIG_JOYSTICK_XPAD_LEDS=y +CONFIG_INPUT_TABLET=y +CONFIG_TABLET_USB_ACECAD=m +CONFIG_TABLET_USB_AIPTEK=m +CONFIG_TABLET_USB_GTCO=m +CONFIG_TABLET_USB_HANWANG=m +CONFIG_TABLET_USB_KBTAB=m +CONFIG_TABLET_USB_PEGASUS=m +CONFIG_TABLET_SERIAL_WACOM4=m +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ADS7846=y +CONFIG_TOUCHSCREEN_TSC2004=y +CONFIG_TOUCHSCREEN_TSC2005=y +CONFIG_TOUCHSCREEN_TSC2007=y +CONFIG_INPUT_MISC=y +CONFIG_SERIO_SERPORT=m +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_IMX=y +CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_SERIAL_FSL_LPUART=y +CONFIG_SERIAL_FSL_LPUART_CONSOLE=y +CONFIG_SERIAL_DEV_BUS=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_GPIO=y +CONFIG_I2C_MUX_PINCTRL=y +CONFIG_I2C_MUX_REG=y +CONFIG_I2C_DEMUX_PINCTRL=y +# CONFIG_I2C_HELPER_AUTO is not set +CONFIG_I2C_ALGOPCF=m +CONFIG_I2C_ALGOPCA=m +CONFIG_I2C_GPIO=y +CONFIG_I2C_IMX=y +CONFIG_SPI=y +CONFIG_SPI_FSL_QUADSPI=y +CONFIG_SPI_GPIO=y +CONFIG_SPI_IMX=y +CONFIG_SPI_SPIDEV=y +CONFIG_PPS_CLIENT_LDISC=m +CONFIG_PPS_CLIENT_GPIO=m +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_MXC=y +CONFIG_GPIO_ADP5588=m +CONFIG_GPIO_MAX7300=m +CONFIG_GPIO_MAX732X=m +CONFIG_GPIO_PCA953X=m +CONFIG_GPIO_PCF857X=m +CONFIG_GPIO_TS4900=y +CONFIG_GPIO_PISOSR=m +CONFIG_W1=m +CONFIG_W1_MASTER_DS2490=m +CONFIG_W1_MASTER_GPIO=m +CONFIG_W1_SLAVE_THERM=m +CONFIG_W1_SLAVE_SMEM=m +CONFIG_W1_SLAVE_DS2408=m +CONFIG_W1_SLAVE_DS2413=m +CONFIG_W1_SLAVE_DS2406=m +CONFIG_W1_SLAVE_DS2423=m +CONFIG_W1_SLAVE_DS2431=m +CONFIG_W1_SLAVE_DS2433=m +CONFIG_W1_SLAVE_DS2780=m +CONFIG_W1_SLAVE_DS2781=m +CONFIG_W1_SLAVE_DS28E04=m +# CONFIG_HWMON is not set +CONFIG_THERMAL_STATISTICS=y +CONFIG_THERMAL_WRITABLE_TRIPS=y +CONFIG_CPU_THERMAL=y +CONFIG_IMX_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_RN5T618_WATCHDOG=y +CONFIG_IMX2_WDT=y +CONFIG_MFD_DA9052_I2C=y +CONFIG_MFD_DA9062=y +CONFIG_MFD_DA9063=y +CONFIG_MFD_MC13XXX_SPI=y +CONFIG_MFD_MC13XXX_I2C=y +CONFIG_MFD_RN5T618=y +CONFIG_MFD_STMPE=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_ANATOP=y +CONFIG_REGULATOR_DA9052=y +CONFIG_REGULATOR_DA9062=y +CONFIG_REGULATOR_DA9063=y +CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_MC13783=y +CONFIG_REGULATOR_MC13892=y +CONFIG_REGULATOR_PFUZE100=y +CONFIG_REGULATOR_RN5T618=y +CONFIG_RC_CORE=y +CONFIG_RC_MAP=m +CONFIG_RC_DEVICES=y +CONFIG_RC_ATI_REMOTE=m +CONFIG_IR_HIX5HD2=m +CONFIG_IR_IMON=m +CONFIG_IR_MCEUSB=m +CONFIG_IR_REDRAT3=m +CONFIG_IR_STREAMZAP=m +CONFIG_IR_IGORPLUGUSB=m +CONFIG_IR_IGUANA=m +CONFIG_IR_TTUSBIR=m +CONFIG_RC_LOOPBACK=m +CONFIG_IR_GPIO_CIR=m +CONFIG_MEDIA_SUPPORT=y +CONFIG_VIDEO_ADV_DEBUG=y +CONFIG_VIDEO_FIXED_MINOR_RANGES=y +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_VIDEO_CLASS=m +CONFIG_USB_M5602=m +CONFIG_USB_STV06XX=m +CONFIG_USB_GL860=m +CONFIG_USB_GSPCA_BENQ=m +CONFIG_USB_GSPCA_CONEX=m +CONFIG_USB_GSPCA_CPIA1=m +CONFIG_USB_GSPCA_DTCS033=m +CONFIG_USB_GSPCA_ETOMS=m +CONFIG_USB_GSPCA_FINEPIX=m +CONFIG_USB_GSPCA_JEILINJ=m +CONFIG_USB_GSPCA_JL2005BCD=m +CONFIG_USB_GSPCA_KINECT=m +CONFIG_USB_GSPCA_KONICA=m +CONFIG_USB_GSPCA_MARS=m +CONFIG_USB_GSPCA_MR97310A=m +CONFIG_USB_GSPCA_NW80X=m +CONFIG_USB_GSPCA_OV519=m +CONFIG_USB_GSPCA_OV534=m +CONFIG_USB_GSPCA_OV534_9=m +CONFIG_USB_GSPCA_PAC207=m +CONFIG_USB_GSPCA_PAC7302=m +CONFIG_USB_GSPCA_PAC7311=m +CONFIG_USB_GSPCA_SE401=m +CONFIG_USB_GSPCA_SN9C2028=m +CONFIG_USB_GSPCA_SN9C20X=m +CONFIG_USB_GSPCA_SONIXB=m +CONFIG_USB_GSPCA_SONIXJ=m +CONFIG_USB_GSPCA_SPCA500=m +CONFIG_USB_GSPCA_SPCA501=m +CONFIG_USB_GSPCA_SPCA505=m +CONFIG_USB_GSPCA_SPCA506=m +CONFIG_USB_GSPCA_SPCA508=m +CONFIG_USB_GSPCA_SPCA561=m +CONFIG_USB_GSPCA_SPCA1528=m +CONFIG_USB_GSPCA_SQ905=m +CONFIG_USB_GSPCA_SQ905C=m +CONFIG_USB_GSPCA_SQ930X=m +CONFIG_USB_GSPCA_STK014=m +CONFIG_USB_GSPCA_STK1135=m +CONFIG_USB_GSPCA_STV0680=m +CONFIG_USB_GSPCA_SUNPLUS=m +CONFIG_USB_GSPCA_T613=m +CONFIG_USB_GSPCA_TOPRO=m +CONFIG_USB_GSPCA_TOUPTEK=m +CONFIG_USB_GSPCA_TV8532=m +CONFIG_USB_GSPCA_VC032X=m +CONFIG_USB_GSPCA_VICAM=m +CONFIG_USB_GSPCA_XIRLINK_CIT=m +CONFIG_USB_GSPCA_ZC3XX=m +CONFIG_USB_PWC=m +CONFIG_VIDEO_CPIA2=m +CONFIG_USB_ZR364XX=m +CONFIG_USB_STKWEBCAM=m +CONFIG_USB_S2255=m +CONFIG_VIDEO_USBTV=m +CONFIG_VIDEO_PVRUSB2=m +CONFIG_VIDEO_HDPVR=m +CONFIG_VIDEO_STK1160_COMMON=m +CONFIG_VIDEO_GO7007=m +CONFIG_VIDEO_GO7007_USB=m +CONFIG_VIDEO_AU0828=m +CONFIG_VIDEO_CX231XX=m +CONFIG_VIDEO_CX231XX_ALSA=m +CONFIG_VIDEO_CX231XX_DVB=m +CONFIG_VIDEO_TM6000=m +CONFIG_VIDEO_TM6000_ALSA=m +CONFIG_VIDEO_TM6000_DVB=m +CONFIG_DVB_USB=m +CONFIG_DVB_USB_A800=m +CONFIG_DVB_USB_DIBUSB_MB=m +CONFIG_DVB_USB_DIBUSB_MC=m +CONFIG_DVB_USB_DIB0700=m +CONFIG_DVB_USB_UMT_010=m +CONFIG_DVB_USB_CXUSB=m +CONFIG_DVB_USB_M920X=m +CONFIG_DVB_USB_DIGITV=m +CONFIG_DVB_USB_VP7045=m +CONFIG_DVB_USB_VP702X=m +CONFIG_DVB_USB_GP8PSK=m +CONFIG_DVB_USB_NOVA_T_USB2=m +CONFIG_DVB_USB_TTUSB2=m +CONFIG_DVB_USB_DTT200U=m +CONFIG_DVB_USB_OPERA1=m +CONFIG_DVB_USB_AF9005=m +CONFIG_DVB_USB_AF9005_REMOTE=m +CONFIG_DVB_USB_PCTV452E=m +CONFIG_DVB_USB_DW2102=m +CONFIG_DVB_USB_CINERGY_T2=m +CONFIG_DVB_USB_DTV5100=m +CONFIG_DVB_USB_AZ6027=m +CONFIG_DVB_USB_TECHNISAT_USB2=m +CONFIG_DVB_USB_V2=m +CONFIG_DVB_USB_AF9015=m +CONFIG_DVB_USB_AF9035=m +CONFIG_DVB_USB_ANYSEE=m +CONFIG_DVB_USB_AU6610=m +CONFIG_DVB_USB_AZ6007=m +CONFIG_DVB_USB_CE6230=m +CONFIG_DVB_USB_EC168=m +CONFIG_DVB_USB_GL861=m +CONFIG_DVB_USB_MXL111SF=m +CONFIG_DVB_USB_RTL28XXU=m +CONFIG_DVB_USB_DVBSKY=m +CONFIG_DVB_TTUSB_BUDGET=m +CONFIG_DVB_TTUSB_DEC=m +CONFIG_SMS_USB_DRV=m +CONFIG_DVB_B2C2_FLEXCOP_USB=m +CONFIG_DVB_AS102=m +CONFIG_VIDEO_EM28XX=m +CONFIG_VIDEO_EM28XX_V4L2=m +CONFIG_VIDEO_EM28XX_ALSA=m +CONFIG_VIDEO_EM28XX_DVB=m +CONFIG_USB_AIRSPY=m +CONFIG_USB_HACKRF=m +CONFIG_USB_MSI2500=m +CONFIG_MEDIA_PCI_SUPPORT=y +CONFIG_VIDEO_SOLO6X10=m +CONFIG_VIDEO_TW5864=m +CONFIG_VIDEO_TW68=m +CONFIG_VIDEO_TW686X=m +CONFIG_VIDEO_HEXIUM_GEMINI=m +CONFIG_VIDEO_HEXIUM_ORION=m +CONFIG_VIDEO_MXB=m +CONFIG_VIDEO_DT3155=m +CONFIG_VIDEO_CX25821=m +CONFIG_VIDEO_CX25821_ALSA=m +CONFIG_VIDEO_SAA7134=m +CONFIG_VIDEO_SAA7134_ALSA=m +CONFIG_VIDEO_SAA7134_DVB=m +CONFIG_VIDEO_SAA7134_GO7007=m +CONFIG_VIDEO_SAA7164=m +CONFIG_DVB_AV7110=m +CONFIG_DVB_BUDGET_CORE=m +CONFIG_DVB_BUDGET=m +CONFIG_DVB_BUDGET_AV=m +CONFIG_DVB_BUDGET_PATCH=m +CONFIG_DVB_B2C2_FLEXCOP_PCI=m +CONFIG_DVB_PLUTO2=m +CONFIG_DVB_PT1=m +CONFIG_DVB_PT3=m +CONFIG_DVB_NGENE=m +CONFIG_DVB_DDBRIDGE=m +CONFIG_DVB_NETUP_UNIDVB=m +CONFIG_RADIO_SI4713=m +CONFIG_USB_SI4713=m +CONFIG_PLATFORM_SI4713=m +CONFIG_USB_MR800=m +CONFIG_USB_DSBR=m +CONFIG_RADIO_MAXIRADIO=m +CONFIG_RADIO_SHARK=m +CONFIG_RADIO_SHARK2=m +CONFIG_USB_KEENE=m +CONFIG_USB_RAREMONO=m +CONFIG_USB_MA901=m +CONFIG_RADIO_TEA5764=m +CONFIG_RADIO_SAA7706H=m +CONFIG_RADIO_TEF6862=m +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_VIDEO_MUX=y +CONFIG_V4L_MEM2MEM_DRIVERS=y +CONFIG_VIDEO_CODA=m +CONFIG_VIDEO_ADV7180=m +CONFIG_VIDEO_OV2680=m +CONFIG_VIDEO_OV5640=m +CONFIG_VIDEO_OV5645=m +CONFIG_IMX_IPUV3_CORE=y +CONFIG_DRM=y +CONFIG_DRM_PANEL_LVDS=y +CONFIG_DRM_PANEL_SIMPLE=y +CONFIG_DRM_PANEL_SEIKO_43WVF1G=y +CONFIG_DRM_TI_TFP410=y +CONFIG_DRM_DW_HDMI_AHB_AUDIO=m +CONFIG_DRM_DW_HDMI_CEC=y +CONFIG_DRM_IMX=y +CONFIG_DRM_IMX_PARALLEL_DISPLAY=y +CONFIG_DRM_IMX_TVE=y +CONFIG_DRM_IMX_LDB=y +CONFIG_DRM_IMX_HDMI=y +CONFIG_DRM_ETNAVIV=y +CONFIG_DRM_MXSFB=y +CONFIG_FB_MODE_HELPERS=y +# CONFIG_FB_MX3 is not set +CONFIG_LCD_CLASS_DEVICE=y +CONFIG_LCD_L4F00242T03=y +CONFIG_LCD_PLATFORM=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_BACKLIGHT_GPIO=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_LOGO=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_HRTIMER=y +CONFIG_SND_USB_AUDIO=m +CONFIG_SND_USB_UA101=m +CONFIG_SND_USB_CAIAQ=m +CONFIG_SND_USB_6FIRE=m +CONFIG_SND_USB_HIFACE=m +CONFIG_SND_BCD2000=m +CONFIG_SND_USB_POD=m +CONFIG_SND_USB_PODHD=m +CONFIG_SND_USB_TONEPORT=m +CONFIG_SND_USB_VARIAX=m +CONFIG_SND_SOC=y +CONFIG_SND_IMX_SOC=y +CONFIG_SND_SOC_IMX_SGTL5000=y +CONFIG_SND_SOC_FSL_ASOC_CARD=y +CONFIG_SND_SOC_AC97_CODEC=y +CONFIG_SND_SOC_CS42XX8_I2C=y +CONFIG_SND_SOC_ES8328_I2C=y +CONFIG_SND_SOC_ES8328_SPI=y +CONFIG_SND_SOC_TLV320AIC23_I2C=y +CONFIG_SND_SOC_TLV320AIC3X=y +CONFIG_SND_SOC_WM8960=y +CONFIG_SND_SOC_WM8962=y +CONFIG_SND_SIMPLE_CARD=y +CONFIG_UHID=m +CONFIG_HID_A4TECH=m +CONFIG_HID_ACRUX=m +CONFIG_HID_APPLE=m +CONFIG_HID_APPLEIR=m +CONFIG_HID_AUREAL=m +CONFIG_HID_BELKIN=m +CONFIG_HID_BETOP_FF=m +CONFIG_HID_CHERRY=m +CONFIG_HID_CHICONY=m +CONFIG_HID_CORSAIR=m +CONFIG_HID_PRODIKEYS=m +CONFIG_HID_CMEDIA=m +CONFIG_HID_CYPRESS=m +CONFIG_HID_DRAGONRISE=m +CONFIG_HID_EMS_FF=m +CONFIG_HID_ELECOM=m +CONFIG_HID_ELO=m +CONFIG_HID_EZKEY=m +CONFIG_HID_GEMBIRD=m +CONFIG_HID_GFRM=m +CONFIG_HID_HOLTEK=m +CONFIG_HID_GT683R=m +CONFIG_HID_KEYTOUCH=m +CONFIG_HID_KYE=m +CONFIG_HID_UCLOGIC=m +CONFIG_HID_WALTOP=m +CONFIG_HID_GYRATION=m +CONFIG_HID_ICADE=m +CONFIG_HID_TWINHAN=m +CONFIG_HID_KENSINGTON=m +CONFIG_HID_LCPOWER=m +CONFIG_HID_LENOVO=m +CONFIG_HID_LOGITECH=m +CONFIG_HID_LOGITECH_HIDPP=m +CONFIG_HID_MAGICMOUSE=m +CONFIG_HID_MICROSOFT=m +CONFIG_HID_MONTEREY=m +CONFIG_HID_MULTITOUCH=m +CONFIG_HID_NTRIG=m +CONFIG_HID_ORTEK=m +CONFIG_HID_PANTHERLORD=m +CONFIG_HID_PENMOUNT=m +CONFIG_HID_PETALYNX=m +CONFIG_HID_PICOLCD=m +CONFIG_HID_PLANTRONICS=m +CONFIG_HID_PRIMAX=m +CONFIG_HID_ROCCAT=m +CONFIG_HID_SAITEK=m +CONFIG_HID_SAMSUNG=m +CONFIG_HID_SONY=m +CONFIG_HID_SPEEDLINK=m +CONFIG_HID_STEELSERIES=m +CONFIG_HID_SUNPLUS=m +CONFIG_HID_RMI=m +CONFIG_HID_GREENASIA=m +CONFIG_HID_SMARTJOYPLUS=m +CONFIG_HID_TIVO=m +CONFIG_HID_TOPSEED=m +CONFIG_HID_THINGM=m +CONFIG_HID_THRUSTMASTER=m +CONFIG_HID_WACOM=m +CONFIG_HID_WIIMOTE=m +CONFIG_HID_XINMO=m +CONFIG_HID_ZEROPLUS=m +CONFIG_HID_ZYDACRON=m +CONFIG_HID_ALPS=m +CONFIG_USB_LED_TRIG=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_OTG=y +CONFIG_USB_OTG_FSM=y +CONFIG_USB_LEDS_TRIGGER_USBPORT=y +CONFIG_USB_MON=m +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_MXC=y +CONFIG_USB_HCD_TEST_MODE=y +CONFIG_USB_PRINTER=m +CONFIG_USB_STORAGE=y +CONFIG_USB_STORAGE_REALTEK=m +CONFIG_USB_STORAGE_DATAFAB=m +CONFIG_USB_STORAGE_FREECOM=m +CONFIG_USB_STORAGE_ISD200=m +CONFIG_USB_STORAGE_USBAT=m +CONFIG_USB_STORAGE_SDDR09=m +CONFIG_USB_STORAGE_SDDR55=m +CONFIG_USB_STORAGE_JUMPSHOT=m +CONFIG_USB_STORAGE_ALAUDA=m +CONFIG_USB_STORAGE_ONETOUCH=m +CONFIG_USB_STORAGE_KARMA=m +CONFIG_USB_STORAGE_CYPRESS_ATACB=m +CONFIG_USB_STORAGE_ENE_UB6250=m +CONFIG_USB_UAS=m +CONFIG_USB_MDC800=m +CONFIG_USB_MICROTEK=m +CONFIG_USBIP_CORE=m +CONFIG_USBIP_VHCI_HCD=m +CONFIG_USBIP_HOST=m +CONFIG_USB_MUSB_HDRC=m +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_SIMPLE=m +CONFIG_USB_SERIAL_AIRCABLE=m +CONFIG_USB_SERIAL_ARK3116=m +CONFIG_USB_SERIAL_BELKIN=m +CONFIG_USB_SERIAL_CH341=m +CONFIG_USB_SERIAL_WHITEHEAT=m +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m +CONFIG_USB_SERIAL_CP210X=m +CONFIG_USB_SERIAL_CYPRESS_M8=m +CONFIG_USB_SERIAL_EMPEG=m +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_VISOR=m +CONFIG_USB_SERIAL_IPAQ=m +CONFIG_USB_SERIAL_IR=m +CONFIG_USB_SERIAL_EDGEPORT=m +CONFIG_USB_SERIAL_EDGEPORT_TI=m +CONFIG_USB_SERIAL_F81232=m +CONFIG_USB_SERIAL_GARMIN=m +CONFIG_USB_SERIAL_IPW=m +CONFIG_USB_SERIAL_IUU=m +CONFIG_USB_SERIAL_KEYSPAN_PDA=m +CONFIG_USB_SERIAL_KEYSPAN=m +CONFIG_USB_SERIAL_KLSI=m +CONFIG_USB_SERIAL_KOBIL_SCT=m +CONFIG_USB_SERIAL_MCT_U232=m +CONFIG_USB_SERIAL_METRO=m +CONFIG_USB_SERIAL_MOS7720=m +CONFIG_USB_SERIAL_MOS7840=m +CONFIG_USB_SERIAL_MXUPORT=m +CONFIG_USB_SERIAL_NAVMAN=m +CONFIG_USB_SERIAL_PL2303=m +CONFIG_USB_SERIAL_OTI6858=m +CONFIG_USB_SERIAL_QCAUX=m +CONFIG_USB_SERIAL_QUALCOMM=m +CONFIG_USB_SERIAL_SPCP8X5=m +CONFIG_USB_SERIAL_SAFE=m +CONFIG_USB_SERIAL_SAFE_PADDED=y +CONFIG_USB_SERIAL_SIERRAWIRELESS=m +CONFIG_USB_SERIAL_SYMBOL=m +CONFIG_USB_SERIAL_TI=m +CONFIG_USB_SERIAL_CYBERJACK=m +CONFIG_USB_SERIAL_XIRCOM=m +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_SERIAL_OMNINET=m +CONFIG_USB_SERIAL_OPTICON=m +CONFIG_USB_SERIAL_XSENS_MT=m +CONFIG_USB_SERIAL_WISHBONE=m +CONFIG_USB_SERIAL_SSU100=m +CONFIG_USB_SERIAL_QT2=m +CONFIG_USB_SERIAL_DEBUG=m +CONFIG_USB_EMI62=m +CONFIG_USB_EMI26=m +CONFIG_USB_ADUTUX=m +CONFIG_USB_SEVSEG=m +CONFIG_USB_LEGOTOWER=m +CONFIG_USB_LCD=m +CONFIG_USB_CYPRESS_CY7C63=m +CONFIG_USB_CYTHERM=m +CONFIG_USB_IDMOUSE=m +CONFIG_USB_FTDI_ELAN=m +CONFIG_USB_APPLEDISPLAY=m +CONFIG_USB_SISUSBVGA=m +CONFIG_USB_LD=m +CONFIG_USB_TRANCEVIBRATOR=m +CONFIG_USB_IOWARRIOR=m +CONFIG_USB_TEST=m +CONFIG_USB_EHSET_TEST_FIXTURE=m +CONFIG_USB_ISIGHTFW=m +CONFIG_USB_YUREX=m +CONFIG_USB_HSIC_USB3503=m +CONFIG_USB_HSIC_USB4604=m +CONFIG_USB_LINK_LAYER_TEST=m +CONFIG_USB_CHAOSKEY=m +CONFIG_USB_ATM=m +CONFIG_USB_SPEEDTOUCH=m +CONFIG_USB_CXACRU=m +CONFIG_USB_UEAGLEATM=m +CONFIG_USB_XUSBATM=m +CONFIG_NOP_USB_XCEIV=y +CONFIG_USB_MXS_PHY=y +CONFIG_USB_GADGET=y +CONFIG_USB_FSL_USB2=y +CONFIG_USB_CONFIGFS=y +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONFIGFS_ACM=y +CONFIG_USB_CONFIGFS_OBEX=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_ECM=y +CONFIG_USB_CONFIGFS_ECM_SUBSET=y +CONFIG_USB_CONFIGFS_RNDIS=y +CONFIG_USB_CONFIGFS_EEM=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_LB_SS=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_CONFIGFS_F_UAC1=y +CONFIG_USB_CONFIGFS_F_UAC2=y +CONFIG_USB_CONFIGFS_F_MIDI=y +CONFIG_USB_CONFIGFS_F_HID=y +CONFIG_USB_CONFIGFS_F_UVC=y +CONFIG_USB_CONFIGFS_F_PRINTER=y +CONFIG_USB_ZERO=m +CONFIG_USB_AUDIO=m +CONFIG_USB_ETH=m +CONFIG_USB_G_NCM=m +CONFIG_USB_GADGETFS=m +CONFIG_USB_FUNCTIONFS=m +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m +CONFIG_USB_MIDI_GADGET=m +CONFIG_USB_G_PRINTER=m +CONFIG_USB_CDC_COMPOSITE=m +CONFIG_USB_G_NOKIA=m +CONFIG_USB_G_ACM_MS=m +CONFIG_USB_G_MULTI=m +CONFIG_USB_G_MULTI_CDC=y +CONFIG_USB_G_HID=m +CONFIG_USB_G_DBGP=m +CONFIG_USB_G_WEBCAM=m +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_ESDHC_IMX=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_PWM=y +CONFIG_LEDS_SYSCON=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_ONESHOT=y +CONFIG_LEDS_TRIGGER_DISK=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_LEDS_TRIGGER_TRANSIENT=y +CONFIG_LEDS_TRIGGER_CAMERA=y +CONFIG_LEDS_TRIGGER_PANIC=y +CONFIG_INFINIBAND=m +CONFIG_RTC_CLASS=y +CONFIG_RTC_INTF_DEV_UIE_EMUL=y +CONFIG_RTC_DRV_DS1307=y +CONFIG_RTC_DRV_ISL1208=y +CONFIG_RTC_DRV_ISL12022=y +CONFIG_RTC_DRV_PCF8523=y +CONFIG_RTC_DRV_PCF8563=y +CONFIG_RTC_DRV_M41T80=y +CONFIG_RTC_DRV_RC5T619=y +CONFIG_RTC_DRV_DA9063=y +CONFIG_RTC_DRV_MC13XXX=y +CONFIG_RTC_DRV_MXC=y +CONFIG_RTC_DRV_MXC_V2=y +CONFIG_RTC_DRV_SNVS=y +CONFIG_DMADEVICES=y +CONFIG_FSL_EDMA=y +CONFIG_IMX_SDMA=y +CONFIG_MXS_DMA=y +CONFIG_DMATEST=m +CONFIG_UIO=m +CONFIG_UIO_PDRV_GENIRQ=m +CONFIG_UIO_DMEM_GENIRQ=m +CONFIG_UIO_PCI_GENERIC=m +CONFIG_STAGING=y +CONFIG_PRISM2_USB=m +CONFIG_RTL8192U=m +CONFIG_RTLLIB=m +CONFIG_RTL8192E=m +CONFIG_R8712U=m +CONFIG_R8188EU=m +CONFIG_RTS5208=m +CONFIG_VT6655=m +CONFIG_STAGING_MEDIA=y +CONFIG_VIDEO_IMX_MEDIA=y +CONFIG_COMMON_CLK_PWM=y +CONFIG_CLK_IMX8MM=y +CONFIG_CLK_IMX8MN=y +CONFIG_CLK_IMX8MP=y +CONFIG_CLK_IMX8MQ=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_IMX_GPCV2_PM_DOMAINS=y +CONFIG_SOC_IMX8M=y +CONFIG_EXTCON_ADC_JACK=m +CONFIG_EXTCON_GPIO=m +CONFIG_EXTCON_USB_GPIO=m +CONFIG_IIO=y +CONFIG_IIO_BUFFER_CB=m +CONFIG_IIO_SW_DEVICE=m +CONFIG_IIO_SW_TRIGGER=m +CONFIG_MMA8452=y +CONFIG_IMX7D_ADC=y +CONFIG_RN5T618_ADC=y +CONFIG_VF610_ADC=y +CONFIG_SENSORS_ISL29018=y +CONFIG_MAG3110=y +CONFIG_MPL3115=y +CONFIG_PWM=y +CONFIG_PWM_FSL_FTM=y +CONFIG_PWM_IMX27=y +CONFIG_PWM_IMX_TPM=y +CONFIG_NVMEM_IMX_OCOTP=y +CONFIG_NVMEM_SNVS_LPGPR=y +CONFIG_TEE=y +CONFIG_OPTEE=y +CONFIG_MUX_MMIO=y +CONFIG_SIOX=m +CONFIG_SIOX_BUS_GPIO=m +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_REISERFS_FS=y +CONFIG_REISERFS_FS_XATTR=y +CONFIG_REISERFS_FS_POSIX_ACL=y +CONFIG_REISERFS_FS_SECURITY=y +CONFIG_JFS_FS=y +CONFIG_JFS_POSIX_ACL=y +CONFIG_JFS_SECURITY=y +CONFIG_XFS_FS=y +CONFIG_XFS_QUOTA=y +CONFIG_XFS_POSIX_ACL=y +CONFIG_XFS_RT=y +CONFIG_GFS2_FS=m +CONFIG_OCFS2_FS=m +CONFIG_BTRFS_FS=y +CONFIG_BTRFS_FS_POSIX_ACL=y +CONFIG_NILFS2_FS=y +CONFIG_F2FS_FS=y +CONFIG_F2FS_FS_SECURITY=y +CONFIG_F2FS_CHECK_FS=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +CONFIG_QFMT_V2=m +CONFIG_AUTOFS4_FS=m +CONFIG_FUSE_FS=m +CONFIG_CUSE=m +CONFIG_OVERLAY_FS=m +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=y +CONFIG_NTFS_FS=m +CONFIG_NTFS_RW=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_ORANGEFS_FS=m +CONFIG_ADFS_FS=m +CONFIG_AFFS_FS=m +CONFIG_ECRYPT_FS=m +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +CONFIG_BEFS_FS=m +CONFIG_BFS_FS=m +CONFIG_EFS_FS=m +CONFIG_JFFS2_FS=m +CONFIG_CRAMFS=m +CONFIG_SQUASHFS=m +CONFIG_SQUASHFS_LZ4=y +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_XZ=y +CONFIG_VXFS_FS=m +CONFIG_MINIX_FS=m +CONFIG_OMFS_FS=m +CONFIG_HPFS_FS=m +CONFIG_QNX4FS_FS=m +CONFIG_QNX6FS_FS=m +CONFIG_ROMFS_FS=m +CONFIG_PSTORE=m +CONFIG_SYSV_FS=m +CONFIG_UFS_FS=m +CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_2=y +CONFIG_NFS_V4_1_MIGRATION=y +CONFIG_ROOT_NFS=y +CONFIG_NFSD=m +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y +CONFIG_NFSD_BLOCKLAYOUT=y +CONFIG_NFSD_SCSILAYOUT=y +CONFIG_NFSD_FLEXFILELAYOUT=y +CONFIG_CEPH_FS=m +CONFIG_CIFS=m +CONFIG_CODA_FS=m +CONFIG_AFS_FS=m +CONFIG_NLS_DEFAULT="cp437" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_MAC_ROMAN=m +CONFIG_NLS_MAC_CELTIC=m +CONFIG_NLS_MAC_CENTEURO=m +CONFIG_NLS_MAC_CROATIAN=m +CONFIG_NLS_MAC_CYRILLIC=m +CONFIG_NLS_MAC_GAELIC=m +CONFIG_NLS_MAC_GREEK=m +CONFIG_NLS_MAC_ICELAND=m +CONFIG_NLS_MAC_INUIT=m +CONFIG_NLS_MAC_ROMANIAN=m +CONFIG_NLS_MAC_TURKISH=m +CONFIG_NLS_UTF8=y +CONFIG_CRYPTO_USER=y +# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set +CONFIG_CRYPTO_TEST=m +CONFIG_CRYPTO_CCM=y +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_ECHAINIV=y +CONFIG_CRYPTO_LRW=y +CONFIG_CRYPTO_CMAC=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MICHAEL_MIC=y +CONFIG_CRYPTO_RMD128=y +CONFIG_CRYPTO_RMD160=y +CONFIG_CRYPTO_RMD256=y +CONFIG_CRYPTO_RMD320=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_SHA3=y +CONFIG_CRYPTO_TGR192=y +CONFIG_CRYPTO_WP512=y +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_CAMELLIA=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_DEV_FSL_CAAM=y +CONFIG_CRYPTO_DEV_SAHARA=y +CONFIG_CRYPTO_DEV_MXS_DCP=y +CONFIG_CRC7=m +CONFIG_CMA_SIZE_MBYTES=128 +CONFIG_PRINTK_TIME=y +CONFIG_DYNAMIC_DEBUG=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_FS=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_PREEMPT is not set +CONFIG_PROVE_LOCKING=y +# CONFIG_FTRACE is not set From 494091165f17162a47d48968b92c7fbd4c89cc22 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Wed, 12 Oct 2022 09:46:56 -0700 Subject: [PATCH 006/244] ARM: dts: imx6: ts7970: Add max3100-ts support Signed-off-by: Kris Bahnsen --- arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi index 949c1f6724b41..fba4ae93c8e00 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi @@ -163,10 +163,17 @@ pinctrl-0 = <&pinctrl_ecspi2>; status = "okay"; - /* CS0# is FPGA emulated MAX3100 UARTs, not compatible with the - * standard kernel drive since multiple UARTs are implemented in the - * single FPGA IP instance. - */ + max3100ts: serial@0 { + compatible = "technologic,max3100-ts"; + reg = <0>; + interrupt-parent = <&gpio1>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + spi-max-frequency = <1000000>; + loopback = <0>; + crystal = <1>; + poll-time = <100>; + fifo-size = <16>; + }; /* CS1# is generic FPGA SPI access, normally unused */ From 0214bb538ba2691d46b79c4a499b9e951289349b Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Fri, 21 Oct 2022 10:49:15 -0700 Subject: [PATCH 007/244] ARM: tsimx6: Add max3100-ts support Signed-off-by: Kris Bahnsen --- arch/arm/configs/tsimx6_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/tsimx6_defconfig b/arch/arm/configs/tsimx6_defconfig index 29daca9da6903..581a5cdec578f 100644 --- a/arch/arm/configs/tsimx6_defconfig +++ b/arch/arm/configs/tsimx6_defconfig @@ -836,6 +836,7 @@ CONFIG_TOUCHSCREEN_TSC2007=y CONFIG_INPUT_MISC=y CONFIG_SERIO_SERPORT=m # CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_MAX3100_TS=y CONFIG_SERIAL_IMX=y CONFIG_SERIAL_IMX_CONSOLE=y CONFIG_SERIAL_FSL_LPUART=y From 639fe55705545937201e7cd220071cfb14dfc39d Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Wed, 22 May 2024 20:04:21 +0000 Subject: [PATCH 008/244] rtc: isl12022: option to enable temp. comp. in battery mode The driver turns on temperature compensation while operating with main input power, however there are environments where having the temperature compentation enabled while the main power is off and the RTC is on battery power that would be beneficial. Signed-off-by: Kris Bahnsen --- drivers/rtc/rtc-isl12022.c | 48 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/drivers/rtc/rtc-isl12022.c b/drivers/rtc/rtc-isl12022.c index 5fc52dc642130..5acef689b136b 100644 --- a/drivers/rtc/rtc-isl12022.c +++ b/drivers/rtc/rtc-isl12022.c @@ -70,6 +70,8 @@ #define ISL12022_ALARM_ENABLE (1 << 7) /* for all ALARM registers */ #define ISL12022_BETA_TSE (1 << 7) +#define ISL12022_BETA_BTSE (1 << 6) +#define ISL12022_BETA_BTSR (1 << 5) static struct i2c_driver isl12022_driver; @@ -547,6 +549,51 @@ static void isl12022_set_trip_levels(struct device *dev) ISL12022_BETA_TSE, ISL12022_BETA_TSE); } +static void isl12022_set_battery_mode_compensation(struct device *dev) +{ + struct regmap *regmap = dev_get_drvdata(dev); + u32 minutes; + unsigned int beta_reg; + u8 val; + int ret; + + /* + * As a shortcut, we assume the value will be not present, 1, or 10. + * Later it is assumed that if the value is not 1, then it must be 10. + * + * When battery mode compensation is enabled, expect an overall average + * increase in battery draw of 25 nA at 10 minutes, and 250 nA at 1 minute. + */ + ret = device_property_read_u32(dev, "isil,compensation-in-battery-mode-mins", + &minutes); + if (ret) + return; + + dev_dbg(dev, "Enable temp. compensation in battery mode every %d minutes\n", + minutes == 1 ? 1 : 10); + + /* + * Disable TSE, modifications to the BETA register need to happen with + * TSE disabled. Save the TSE value in case it was not enabled. The datasheet + * is not clear on if TSE needs to be enabled for BTSE to be effective. + */ + regmap_read(regmap, ISL12022_REG_BETA, &beta_reg); + regmap_write_bits(regmap, ISL12022_REG_BETA, ISL12022_BETA_TSE, 0); + + val = ISL12022_BETA_BTSE; + if (minutes == 1) + val |= ISL12022_BETA_BTSR; + + regmap_write_bits(regmap, ISL12022_REG_BETA, + (ISL12022_BETA_BTSE | ISL12022_BETA_BTSR), val); + + if (beta_reg & ISL12022_BETA_TSE) + regmap_write_bits(regmap, ISL12022_REG_BETA, + ISL12022_BETA_TSE, ISL12022_BETA_TSE); +} + + + static int isl12022_probe(struct i2c_client *client) { struct isl12022 *isl12022; @@ -574,6 +621,7 @@ static int isl12022_probe(struct i2c_client *client) return ret; isl12022_set_trip_levels(&client->dev); + isl12022_set_battery_mode_compensation(&client->dev); isl12022_hwmon_register(&client->dev); rtc = devm_rtc_allocate_device(&client->dev); From 497d2041ae4f15b5368557809090f3c91f01049d Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Wed, 22 May 2024 20:20:00 +0000 Subject: [PATCH 009/244] rtc: isl12022: check RTCF and OSCF at probe Give a warning if the RTC has detected either the oscillator has failed, or the RTC has a complete power failure. RTCF is cleared on a write of the RTC registers, while the datasheet gives no clear indication of how an OSCF condition can be cleared. Signed-off-by: Kris Bahnsen --- drivers/rtc/rtc-isl12022.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/rtc/rtc-isl12022.c b/drivers/rtc/rtc-isl12022.c index 5acef689b136b..75b325a3b1c6e 100644 --- a/drivers/rtc/rtc-isl12022.c +++ b/drivers/rtc/rtc-isl12022.c @@ -52,9 +52,11 @@ /* ISL register bits */ #define ISL12022_HR_MIL (1 << 7) /* military or 24 hour time */ +#define ISL12022_SR_OSCF (1 << 7) #define ISL12022_SR_ALM (1 << 4) #define ISL12022_SR_LBAT85 (1 << 2) #define ISL12022_SR_LBAT75 (1 << 1) +#define ISL12022_SR_RTCF (1 << 0) #define ISL12022_INT_ARST (1 << 7) #define ISL12022_INT_WRTC (1 << 6) @@ -599,6 +601,7 @@ static int isl12022_probe(struct i2c_client *client) struct isl12022 *isl12022; struct rtc_device *rtc; struct regmap *regmap; + unsigned int sr; int ret; if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) @@ -616,6 +619,13 @@ static int isl12022_probe(struct i2c_client *client) dev_set_drvdata(&client->dev, isl12022); + regmap_read(regmap, ISL12022_REG_SR, &sr); + if (sr & ISL12022_SR_RTCF) + dev_warn(&client->dev, "rtc power failure detected, " + "please set clock.\n"); + if (sr & ISL12022_SR_OSCF) + dev_warn(&client->dev, "rtc oscillator failure detected\n"); + ret = isl12022_register_clock(&client->dev); if (ret) return ret; From ee6c0de01c8eda16791a0964647de478ee0c3035 Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Thu, 17 Nov 2022 12:35:12 -0700 Subject: [PATCH 010/244] rtc: isl12022: Support for RTC offset in emulated ISL12022 The embeddedTS microcontroller implementation of the ISL12022 RTC includes oscillator trim support that is able to tie in to RTC offsets in Linux. Enable these operations when the driver detects it is talking to an emulated ISL12022, no effect on a real part. Signed-off-by: Mark Featherston Signed-off-by: Kris Bahnsen --- drivers/rtc/rtc-isl12022.c | 82 +++++++++++++++++++++++++++++++++++++- 1 file changed, 81 insertions(+), 1 deletion(-) diff --git a/drivers/rtc/rtc-isl12022.c b/drivers/rtc/rtc-isl12022.c index 75b325a3b1c6e..17bdf70c534ff 100644 --- a/drivers/rtc/rtc-isl12022.c +++ b/drivers/rtc/rtc-isl12022.c @@ -49,6 +49,23 @@ /* TEMP - Temperature sensor registers */ #define ISL12022_REG_TEMP_L 0x28 +#define ISL12022_REG_FATR 0x0e + +#define ISL12022_REG_FDTR 0x0f +/* Detect embeddedTS emulated ISL12022. This is always 0 on the real RTC. */ +#define ISL12022_FDTR_EMULATED (1 << 7) + +/* + * These registers only exist in the emulated device, they are unused dst + * registers on the real RTC. + */ +#define ISL12022_REG_OFF_VAL 0x21 + +#define ISL12022_REG_OFF_CTL 0x25 +#define ISL12022_OFF_CTL_APPLY (1 << 0) /* Make value take affect now */ +#define ISL12022_OFF_CTL_ADD (1 << 1) /* 1 if the value is add, 0 if subtract */ +#define ISL12022_OFF_CTL_FLASH (1 << 2) /* 1 to commit to flash, 0 to just ram */ + /* ISL register bits */ #define ISL12022_HR_MIL (1 << 7) /* military or 24 hour time */ @@ -430,6 +447,51 @@ static int isl12022_setup_irq(struct device *dev, int irq) return 0; } +static int emulated_isl12022_set_offset(struct device *dev, long offset) +{ + struct regmap *regmap = dev_get_drvdata(dev); + uint32_t ppb = abs(offset); + uint8_t data; + int ret; + + ret = regmap_bulk_write(regmap, ISL12022_REG_OFF_VAL, &ppb, sizeof(ppb)); + if (ret) + return ret; + + data = ISL12022_OFF_CTL_APPLY | + ((offset > 0) ? ISL12022_OFF_CTL_ADD : 0) | + ISL12022_OFF_CTL_FLASH; + + ret = regmap_bulk_write(regmap, ISL12022_REG_OFF_CTL, &data, 1); + if (ret) + return ret; + + return ret; +} + +static int emulated_isl12022_read_offset(struct device *dev, long *offset) +{ + struct regmap *regmap = dev_get_drvdata(dev); + int ret; + uint32_t ppb; + uint8_t data; + + ret = regmap_bulk_read(regmap, ISL12022_REG_OFF_VAL, &ppb, sizeof(ppb)); + if (ret) + return ret; + + ret = regmap_bulk_read(regmap, ISL12022_REG_OFF_CTL, &data, 1); + if (ret) + return -EIO; + + *offset = ppb; + + if ((data & ISL12022_OFF_CTL_ADD) == 0) + *offset *= -1; + + return ret; +} + static int isl12022_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg) { struct isl12022 *isl12022 = dev_get_drvdata(dev); @@ -466,6 +528,13 @@ static const struct rtc_class_ops isl12022_rtc_ops = { .alarm_irq_enable = isl12022_rtc_alarm_irq_enable, }; +static const struct rtc_class_ops emulated_isl12022_rtc_ops = { + .read_time = isl12022_rtc_read_time, + .set_time = isl12022_rtc_set_time, + .set_offset = emulated_isl12022_set_offset, + .read_offset = emulated_isl12022_read_offset, +}; + static const struct regmap_config regmap_config = { .reg_bits = 8, .val_bits = 8, @@ -602,6 +671,7 @@ static int isl12022_probe(struct i2c_client *client) struct rtc_device *rtc; struct regmap *regmap; unsigned int sr; + uint32_t data; int ret; if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) @@ -639,7 +709,17 @@ static int isl12022_probe(struct i2c_client *client) return PTR_ERR(rtc); isl12022->rtc = rtc; - rtc->ops = &isl12022_rtc_ops; + /* Detect emulated isl12022 */ + ret = regmap_bulk_read(regmap, ISL12022_REG_FDTR, &data, 1); + if (ret) + return ret; + + if (data & ISL12022_FDTR_EMULATED) { + dev_info(&client->dev, "Emulated isl12022 detected"); + rtc->ops = &emulated_isl12022_rtc_ops; + } else { + rtc->ops = &isl12022_rtc_ops; + } rtc->range_min = RTC_TIMESTAMP_BEGIN_2000; rtc->range_max = RTC_TIMESTAMP_END_2099; From 94f9d3342bb0aa609877ba9d7c627eb36481f484 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Thu, 17 Nov 2022 18:37:24 -0700 Subject: [PATCH 011/244] ARM: dts: ts7970: Add ISL12022 properties --- arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi index fba4ae93c8e00..869f3669b0b07 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi @@ -251,6 +251,8 @@ isl12022: rtc@6f { compatible = "isil,isl12022"; reg = <0x6f>; + btse-minutes = <1>; + isil,battery-trip-levels-microvolt = <2550000>, <2250000>; }; gpio8: gpio@28 { From 78d2a2b8098b8bdb02c9a3f570b2c7f02b80985b Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Fri, 18 Nov 2022 11:34:20 -0800 Subject: [PATCH 012/244] ARM: tsimx6: Add HWMON and remove unused RTC driver --- arch/arm/configs/tsimx6_defconfig | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/configs/tsimx6_defconfig b/arch/arm/configs/tsimx6_defconfig index 581a5cdec578f..f23857f233cbe 100644 --- a/arch/arm/configs/tsimx6_defconfig +++ b/arch/arm/configs/tsimx6_defconfig @@ -884,7 +884,6 @@ CONFIG_W1_SLAVE_DS2433=m CONFIG_W1_SLAVE_DS2780=m CONFIG_W1_SLAVE_DS2781=m CONFIG_W1_SLAVE_DS28E04=m -# CONFIG_HWMON is not set CONFIG_THERMAL_STATISTICS=y CONFIG_THERMAL_WRITABLE_TRIPS=y CONFIG_CPU_THERMAL=y @@ -1390,7 +1389,6 @@ CONFIG_INFINIBAND=m CONFIG_RTC_CLASS=y CONFIG_RTC_INTF_DEV_UIE_EMUL=y CONFIG_RTC_DRV_DS1307=y -CONFIG_RTC_DRV_ISL1208=y CONFIG_RTC_DRV_ISL12022=y CONFIG_RTC_DRV_PCF8523=y CONFIG_RTC_DRV_PCF8563=y From 0f16809e7e41a71ff1ee73a23ca992c31a92e7a6 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Wed, 30 Nov 2022 15:44:09 -0700 Subject: [PATCH 013/244] ARM: dts: ts7970: Add isl SRAM as EEPROM Signed-off-by: Kris Bahnsen --- arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi index 869f3669b0b07..75f75992ccd69 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi @@ -255,6 +255,15 @@ isil,battery-trip-levels-microvolt = <2550000>, <2250000>; }; + isl12022_sram: eeprom@57 { + compatible = "atmel,24c01"; + reg = <0x57>; + label = "isl12022-SRAM"; + pagesize = <128>; + size = <128>; + address-width = <8>; + }; + gpio8: gpio@28 { compatible = "technologic,ts7970-gpio"; reg = <0x28>; From 3b8111a4a7637c83251abf3113dc598f7beb0a8b Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Thu, 27 Oct 2022 15:43:33 -0700 Subject: [PATCH 014/244] ARM: dts: imx6: Update TS-4900 support Brought in more features that were not upstream Support all Wi-Fi flavors in a single FDT Add GPIO names Set up iomux framework for SoM modules Clean up copyrights Normalize GPIO and regulator names Signed-off-by: Kris Bahnsen --- arch/arm/boot/dts/nxp/imx/imx6dl-ts4900.dts | 47 +- arch/arm/boot/dts/nxp/imx/imx6q-ts4900.dts | 47 +- arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900.dtsi | 625 ++++++++++++------ 3 files changed, 432 insertions(+), 287 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-ts4900.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-ts4900.dts index 3d60cc725d9e4..d122d7633c3de 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-ts4900.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-ts4900.dts @@ -1,42 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 /* - * Copyright 2015 Technologic Systems - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * Copyright 2015-2022 Technologic Systems, Inc. dba embeddedTS */ /dts-v1/; @@ -44,7 +8,7 @@ #include "imx6qdl-ts4900.dtsi" / { - model = "Technologic Systems i.MX6 Solo/DualLite TS-4900 (Default Device Tree)"; + model = "embeddedTS i.MX6 Solo/DualLite TS-4900 (Default Device Tree)"; compatible = "technologic,imx6dl-ts4900", "fsl,imx6dl"; /* Will be filled by the bootloader */ @@ -53,3 +17,8 @@ reg = <0x10000000 0>; }; }; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_muxbus_gpio &pinctrl_lcd_gpio &pinctrl_i2s_gpio &pinctrl_hog>; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-ts4900.dts b/arch/arm/boot/dts/nxp/imx/imx6q-ts4900.dts index dce1e8671ebea..a301bca4dd27a 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-ts4900.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-ts4900.dts @@ -1,42 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 /* - * Copyright 2015 Technologic Systems - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * Copyright 2015 Technologic Systems, Inc. dba embeddedTS */ /dts-v1/; @@ -44,7 +8,7 @@ #include "imx6qdl-ts4900.dtsi" / { - model = "Technologic Systems i.MX6 Quad TS-4900 (Default Device Tree)"; + model = "embeddedTS i.MX6 Quad TS-4900 (Default Device Tree)"; compatible = "technologic,imx6q-ts4900", "fsl,imx6q"; /* Will be filled by the bootloader */ @@ -57,3 +21,8 @@ &sata { status = "okay"; }; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_muxbus_gpio &pinctrl_lcd_gpio &pinctrl_i2s_gpio &pinctrl_hog>; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900.dtsi index f88da757edda5..b7c1ed1b5f85f 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900.dtsi @@ -1,44 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 /* - * Copyright 2015 Technologic Systems - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * Copyright 2015-2022 Technologic Systems, Inc. dba embeddedTS */ +#include #include #include @@ -47,39 +12,60 @@ ethernet0 = &fec; }; - leds { + led-controller { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds1>; + pinctrl-0 = <&pinctrl_gpio_leds>; compatible = "gpio-leds"; - green-led { - label = "green-led"; + led-0 { + color = ; + function = LED_FUNCTION_POWER; gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; default-state = "on"; }; - red-led { - label = "red-led"; + red-1 { + color = ; + functino = LED_FUNCTION_STATUS; gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; default-state = "off"; }; }; - reg_3p3v: regulator-3p3v { + reg_3v3: regulator-3v3 { compatible = "regulator-fixed"; - regulator-name = "3p3v"; + regulator-name = "3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; }; reg_usb_otg_vbus: regulator-usb-otg-vbus { compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; + regulator-name = "USB_OTG_VBUS"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; enable-active-high; }; + + reg_wlan_vmmc: regulator-wlan-vmmc { + compatible = "regulator-fixed"; + regulator-name = "WLAN_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio8 14 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; + }; }; &can1 { @@ -95,44 +81,122 @@ }; &ecspi1 { + num-cs = <1>; cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; - n25q064: flash@0 { - compatible = "micron,n25q064", "jedec,spi-nor"; + spiboot: flash@0 { + compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <20000000>; }; }; &ecspi2 { + num-cs = <1>; cs-gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi2>; status = "okay"; + + max3100ts: serial@0 { + compatible = "technologic,max3100-ts"; + reg = <0>; + interrupt-parent = <&gpio1>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + spi-max-frequency = <10000000>; + loopback = <0>; + crystal = <1>; + poll-time = <100>; + }; }; &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; + interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, + <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; + fsl,err006687-workaround-present; phy-mode = "rgmii"; status = "okay"; }; +&gpio1 { + gpio-line-names = "AUD_MCLK", "", "", "", "", "REVA_DIO_1", "", "", "", + "REVA_DIO_3", "", "", "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = "", "", "", "", "", "", "", "", "", "", "", "", "", + "", "", "DIO_2", "DIO_18", "DIO_12", "DIO_16", "EN_LCD_3.3V", + "DIO_14", "OFF_BD_RESET#", "EN_USB_5V#", "BUS_CS#", "", "DIO_15", "BUS_DIR", + "BUS_ALE", "EN_SD_POWER#", "DIO_10", "", ""; +}; + +&gpio3 { + gpio-line-names = "MUX_AD_00", "MUX_AD_01", "MUX_AD_02", "MUX_AD_03", + "MUX_AD_04", "MUX_AD_05", "MUX_AD_06", "MUX_AD_07", "MUX_AD_08", + "MUX_AD_09", "MUX_AD_10", "MUX_AD_11", "MUX_AD_12", "MUX_AD_13", + "MUX_AD_14", "MUX_AD_15", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "BUS_BHE#"; +}; + +&gpio4 { + gpio-line-names = "", "", "", "", "", "DIO_7", "", "", "", "", "", "", + "", "", "", "", "LCD_CLK", "LCD_DE", "LCD_HSYNC", "LCD_VSYNC", + "", "LCD_D00", "LCD_D01", "LCD_D02", "LCD_D03", "LCD_D04", + "LCD_D05", "LCD_D06", "LCD_D07", "LCD_D08", "LCD_D08", + "LCD_D10"; +}; + +&gpio5 { + gpio-line-names = "EIM_WAIT#", "", "", "", "DIO_20", "LCD_D11", + "LCD_D12", "LCD_D13", "LCD_D14", "LCD_D15", "LCD_D16", + "LCD_D17","LCD_D18", "LCD_D19", "LCD_D20", "LCD_D21", + "LCD_D22", "LCD_D23", "DIO_9", "DIO_8", "FPGA_DONE", + "FPGA_RESET#", "AUD_CLK", "AUD_TXD", "AUD_FRM", "AUD_RXD", + "", "", "", "", "DIO_0", "DIO_6"; +}; + +&gpio6 { + gpio-line-names = "", "", "", "CPU_DIO_A", "", "", "DIO_19", "", "", + "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "DIO_13"; +}; + +&gpio7 { + gpio-line-names = "", "", "", "", "", "", "", "", "CPU_DIO_B", "", "", + "DIO_4", "DIO_5", "", "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + &i2c1 { clock-frequency = <100000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; isl12022: rtc@6f { compatible = "isil,isl12022"; reg = <0x6f>; + btse-minutes = <1>; + isil,battery-trip-levels-microvolt = <2550000>, <2250000>; + #clock-cells = <0>; + }; + + isl12022_sram: eeprom@57 { + compatible = "atmel,24c01"; + reg = <0x57>; + label = "isl12022-SRAM"; + pagesize = <128>; + size = <128>; + address-width = <8>; }; gpio8: gpio@28 { @@ -140,7 +204,14 @@ reg = <0x28>; #gpio-cells = <2>; gpio-controller; - ngpio = <32>; + base = <224>; + ngpios = <32>; + + gpio-line-names = "CN1_63", "CN1_67", "CN1_87", "REVA_MUX_AD_15", + "REVA_CN2_54", "CN2_78", "CN2_80", "CN2_86", "CN2_88", + "CN2_94", "CN2_96", "CN2_98", "CN2_100", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", "", "", "", "", + "PUSH_SW#"; }; }; @@ -149,8 +220,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; pinctrl-1 = <&pinctrl_i2c2_gpio>; - scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; }; @@ -160,261 +231,371 @@ pinctrl_ecspi1: ecspi1grp { fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x100b1 /* Onboard flash CS1# */ + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x100b1 /* Onboard flash CS1# */ >; }; pinctrl_ecspi2: ecspi2grp { fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1 - MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 - MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1 - MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x100b1 /* Offboard CS0# */ - MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x100b1 /* FPGA CS1# */ - MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b1 /* FPGA_RESET# */ - MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b1 /* FPGA_DONE */ - MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x10 /* FPGA 24MHZ */ - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b1 /* FPGA_IRQ */ + MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1 + MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x100b1 /* Offboard CS0# */ + MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x100b1 /* FPGA CS1# */ + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b1 /* FPGA_IRQ */ >; }; pinctrl_enet: enetgrp { fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x4001b0a8 - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1 - MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b1 /* ETH_PHY_RESET */ + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x4001b0a8 + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1 + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b1 /* ETH_PHY_RESET */ + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 >; }; pinctrl_flexcan1: flexcan1grp { fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 >; }; pinctrl_flexcan2: flexcan2grp { fsl,pins = < - MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b1 - MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b1 + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b1 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b1 >; }; + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b088 /* OFF_BD_RESET#/PE_RST# */ + >; + }; + + /* Pins common to ALL baseboards that are always GPIO */ pinctrl_hog: hoggrp { fsl,pins = < - MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b1 /* OFF_BD_RESET# */ - MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b1 /* EN_USB_5V# */ - MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b1 /* EN_LCD_3.3V */ - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* Audio CLK */ - MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1 /* DIO_1 */ - MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b1 /* DIO_2 */ - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b1 /* DIO_3 */ - MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1b0b1 /* DIO_4 */ - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b1 /* DIO_5 */ - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b1 /* DIO_7 */ - MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b1 /* DIO_8 */ - MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b1 /* DIO_9 */ - MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x1b0b1 /* DIO_0 */ - MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x1b0b1 /* DIO_6 */ - MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x1b0b1 /* CPU_DIO_A */ - MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b1 /* DIO_2 */ - MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b1 /* CPU_DIO_B */ - MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b1 /* BUS_ALE# */ - MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x1b0b1 /* DIO_15 */ - MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b0b1 /* BUS_DIR */ - MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b1 /* BUS_CS# */ - MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b1 /* DIO_14 */ - MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x1b0b1 /* DIO_16 */ - MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x1b0b1 /* DIO_12 */ - MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x1b0b1 /* DIO_18 */ - MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b1 /* DIO_19 */ - MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b1 /* DIO_20 */ - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b1 /* BUS_BHE# */ - MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b1 /* DIO_13 */ - MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b1 /* EIM_WAIT# */ - MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b1 /* DIO_10 */ - MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b0b1 /* MUX_AD_00 */ - MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x1b0b1 /* MUX_AD_01 */ - MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b1 /* MUX_AD_02 */ - MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1b0b1 /* MUX_AD_03 */ - MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b0b1 /* MUX_AD_04 */ - MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b1 /* MUX_AD_05 */ - MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b0b1 /* MUX_AD_06 */ - MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b0b1 /* MUX_AD_07 */ - MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1b0b1 /* MUX_AD_08 */ - MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1b0b1 /* MUX_AD_09 */ - MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x1b0b1 /* MUX_AD_10 */ - MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x1b0b1 /* MUX_AD_11 */ - MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x1b0b1 /* MUX_AD_12 */ - MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b1 /* MUX_AD_13 */ - MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x1b0b1 /* MUX_AD_14 */ - MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x1b0b1 /* MUX_AD_15 */ - MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b1 /* LCD_CLK */ - MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x1b0b1 /* DE */ - MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b1 /* Hsync */ - MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x1b0b1 /* Vsync */ - MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x1b0b1 - MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0x1b0b1 - MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23 0x1b0b1 - MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x1b0b1 - MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b1 - MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b1 - MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x1b0b1 - MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b1 - MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29 0x1b0b1 - MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b1 - MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b0b1 - MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x1b0b1 - MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x1b0b1 - MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1b0b1 - MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b0b1 - MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b1 - MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0b1 - MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b0b1 - MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b1 - MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b1 - MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b1 - MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b1 - MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b1 - MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b1 + MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b1 /* DIO_2 */ + MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x1b0b1 /* DIO_18 */ + MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x1b0b1 /* DIO_12 */ + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x1b0b1 /* DIO_16 */ + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b1 /* DIO_14 */ + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b1 /* EN_USB_5V# */ + MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x1b0b1 /* DIO_15 */ + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b1 /* DIO_7 */ + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b1 /* DIO_20 */ + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b1 /* DIO_9 */ + MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b1 /* DIO_8 */ + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b1 /* FPGA_DONE */ + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b1 /* FPGA_RESET# */ + MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x1b0b1 /* DIO_0 */ + MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x1b0b1 /* DIO_6 */ + MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x1b0b1 /* CPU_DIO_A */ + MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b1 /* DIO_19 */ + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1b0b1 /* DIO_4 */ + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b1 /* DIO_5 */ + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b1 /* CPU_DIO_B */ + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b1 /* DIO_13 */ + MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x10 /* FPGA 24MHZ */ + /* Only on rev A PCBs */ + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1 /* DIO_1 */ + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b1 /* DIO_3 */ + >; + }; + + pinctrl_muxbus_gpio: mbgpiogrp { + fsl,pins = < + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b1 /* DIO_10 */ + MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b1 /* BUS_BHE# */ + + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b1 /* EIM_WAIT# */ + MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b1 /* BUS_CS# */ + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b0b1 /* BUS_DIR */ + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b1 /* BUS_ALE# */ + MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b0b1 /* MUX_AD_00 */ + MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x1b0b1 /* MUX_AD_01 */ + MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b1 /* MUX_AD_02 */ + MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1b0b1 /* MUX_AD_03 */ + MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b0b1 /* MUX_AD_04 */ + MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b1 /* MUX_AD_05 */ + MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b0b1 /* MUX_AD_06 */ + MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b0b1 /* MUX_AD_07 */ + MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1b0b1 /* MUX_AD_08 */ + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1b0b1 /* MUX_AD_09 */ + MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x1b0b1 /* MUX_AD_10 */ + MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x1b0b1 /* MUX_AD_11 */ + MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x1b0b1 /* MUX_AD_12 */ + MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b1 /* MUX_AD_13 */ + MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x1b0b1 /* MUX_AD_14 */ + MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x1b0b1 /* MUX_AD_15 */ + >; + }; + + pinctrl_bb_spi: bbspigrp { + fsl,pins = < + MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x1b088 /* IRQn (usually) */ + MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x1b088 /* CS# */ + MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b088 /* MISO */ + MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x1b088 /* MOSI */ + MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x1b088 /* CLK */ + >; + }; + + pinctrl_i2s: i2sgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* Audio CLK */ + >; + }; + + pinctrl_i2s_gpio: i2sgpiogrp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x130b0 /* AUD_MCLK */ + MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x1b0b1 /* AUD_CLK */ + MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x1b0b1 /* AUD_TXD */ + MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24 0x1b0b1 /* AUD_FRM */ + MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x1b0b1 /* AUD_RXD */ + >; + }; + + pinctrl_lcd: lcdgrp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x38 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xe0 /* DE */ + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0xe0 /* Hsync */ + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0xe0 /* Vsync */ + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xe0 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xe0 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xe0 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xe0 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xe0 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xe0 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xe0 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xe0 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xe0 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xe0 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xe0 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xe0 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xe0 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xe0 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xe0 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xe0 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xe0 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xe0 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0xe0 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0xe0 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0xe0 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0xe0 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0xe0 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0xe0 + >; + }; + + pinctrl_lcd_gpio: lcdgpiogrp { + fsl,pins = < + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b1 /* EN_LCD_3.3V */ + MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b1 /* LCD_CLK */ + MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x1b0b1 /* DE */ + MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b1 /* Hsync */ + MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x1b0b1 /* Vsync */ + MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x1b0b1 + MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0x1b0b1 + MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23 0x1b0b1 + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x1b0b1 + MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b1 + MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b1 + MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x1b0b1 + MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b1 + MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29 0x1b0b1 + MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b1 + MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b0b1 + MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x1b0b1 + MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x1b0b1 + MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1b0b1 + MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b0b1 + MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b1 + MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0b1 + MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b0b1 + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b1 + MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b1 + MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b1 + MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b1 + MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b1 + MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b1 >; }; pinctrl_i2c1: i2c1grp { fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 >; }; pinctrl_i2c1_gpio: i2c1gpiogrp { fsl,pins = < - MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 - MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 >; }; pinctrl_i2c2: i2c2grp { fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 >; }; pinctrl_i2c2_gpio: i2c2gpiogrp { fsl,pins = < - MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 >; }; - pinctrl_leds1: leds1grp { + pinctrl_gpio_leds: leds1grp { fsl,pins = < - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1 /* RED_LED# */ - MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b1 /* GREEN_LED# */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1 /* RED_LED# */ + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b1 /* GREEN_LED# */ >; }; pinctrl_uart1: uart1grp { fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 >; }; pinctrl_uart2: uart2grp { fsl,pins = < - MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 - MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 + MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 >; }; pinctrl_uart3: uart3grp { fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 >; }; pinctrl_uart4: uart4grp { fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 >; }; pinctrl_uart5: uart5grp { fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 >; }; pinctrl_usbotg: usbotggrp { fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 >; }; pinctrl_usdhc1: usdhc1grp { fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x17059 /* WIFI IRQ */ + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x17059 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x17059 /* BT_EN */ + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x17059 /* WIFI IRQ / WIFI_EN */ + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp-100mhz { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170B9 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100B9 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170B9 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170B9 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170B9 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170B9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp-200mhz { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170F9 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100F9 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170F9 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170F9 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170F9 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170F9 >; }; pinctrl_usdhc2: usdhc2grp { fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b1 /* EN_SD_POWER# */ + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b1 /* EN_SD_POWER# */ >; }; pinctrl_usdhc3: usdhc3grp { fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 >; }; }; &pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio2 21 GPIO_ACTIVE_HIGH>; status = "okay"; }; +&snvs_rtc { + status = "disabled"; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; @@ -447,6 +628,7 @@ }; &usbh1 { + disable-over-current; status = "okay"; }; @@ -458,11 +640,36 @@ status = "okay"; }; +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + vmmc-supply = <®_wlan_vmmc>; + vqmmc-supply = <®_1v8>; + bus-width = <4>; + non-removable; + keep-power-in-suspend; + cap-sdio-irq; + fsl,tuning-step = <2>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + reg = <2>; + interrupt-parent = <&gpio1>; + interrupts = <26 IRQ_TYPE_LEVEL_HIGH>; + ref-clock-frequency = <38400000>; + }; +}; + /* SD */ &usdhc2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc2>; - vmmc-supply = <®_3p3v>; + vmmc-supply = <®_3v3>; bus-width = <4>; fsl,wp-controller; status = "okay"; @@ -472,7 +679,7 @@ &usdhc3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc3>; - vmmc-supply = <®_3p3v>; + vmmc-supply = <®_3v3>; bus-width = <4>; non-removable; status = "okay"; From d8b0849c30de5783226bd055d0e9609848d0ddde Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Tue, 13 Dec 2022 17:12:04 -0700 Subject: [PATCH 015/244] ARM: dts: imx6: TS-7970: Remove specific spi-nor part This part can be one of a few different part numbers. All of which support JEDEC ID and specifying the specific part number is not necessary Signed-off-by: Kris Bahnsen --- arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi index 75f75992ccd69..5de0c8cf786c9 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi @@ -145,8 +145,8 @@ pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; - n25q064: flash@0 { - compatible = "micron,n25q064", "jedec,spi-nor"; + spiboot: flash@0 { + compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <20000000>; }; From 94c7e747ac10c01df1f653e7d95674c6cde7f793 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Mon, 6 May 2024 21:15:31 +0000 Subject: [PATCH 016/244] ARM: dts: imx6: Initial TS-8950-4900 support Signed-off-by: Kris Bahnsen Signed-off-by: Mark Featherston --- arch/arm/boot/dts/nxp/imx/Makefile | 2 + .../arm/boot/dts/nxp/imx/imx6dl-ts4900-14.dts | 14 + arch/arm/boot/dts/nxp/imx/imx6q-ts4900-14.dts | 18 + .../dts/nxp/imx/imx6qdl-ts4900-ts8950.dtsi | 333 ++++++++++++++++++ 4 files changed, 367 insertions(+) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6dl-ts4900-14.dts create mode 100644 arch/arm/boot/dts/nxp/imx/imx6q-ts4900-14.dts create mode 100644 arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900-ts8950.dtsi diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx/Makefile index de4142e8f3ce8..919250e319ca2 100644 --- a/arch/arm/boot/dts/nxp/imx/Makefile +++ b/arch/arm/boot/dts/nxp/imx/Makefile @@ -133,6 +133,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-skov-revc-lt6.dtb \ imx6dl-solidsense.dtb \ imx6dl-ts4900.dtb \ + imx6dl-ts4900-14.dtb \ imx6dl-ts7970.dtb \ imx6dl-tx6dl-comtft.dtb \ imx6dl-tx6s-8034.dtb \ @@ -252,6 +253,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-solidsense.dtb \ imx6q-tbs2910.dtb \ imx6q-ts4900.dtb \ + imx6q-ts4900-14.dtb \ imx6q-ts7970.dtb \ imx6q-tx6q-1010.dtb \ imx6q-tx6q-1010-comtft.dtb \ diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-ts4900-14.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-ts4900-14.dts new file mode 100644 index 0000000000000..74fc1ddbb104c --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-ts4900-14.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright 2017-2022 Technologic Systems, Inc. dba embeddedTS + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-ts4900.dtsi" +#include "imx6qdl-ts4900-ts8950.dtsi" + +/ { + model = "embeddedTS i.MX6 Solo/DualLite TS-4900 (TS-TPC-8950)"; + compatible = "fsl,imx6dl-ts4900", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-ts4900-14.dts b/arch/arm/boot/dts/nxp/imx/imx6q-ts4900-14.dts new file mode 100644 index 0000000000000..2b330baf2aab8 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-ts4900-14.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright 2017-2022 Technologic Systems, Inc. dba embeddedTS + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-ts4900.dtsi" +#include "imx6qdl-ts4900-ts8950.dtsi" + +/ { + model = "embeddedTS i.MX6 Quad TS-4900 (TS-TPC-8950)"; + compatible = "fsl,imx6q-ts4900", "fsl,imx6q"; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900-ts8950.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900-ts8950.dtsi new file mode 100644 index 0000000000000..8e69b272aaf6e --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900-ts8950.dtsi @@ -0,0 +1,333 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright 2018-2022 Technologic Systems, Inc. dba embeddedTS + */ + +#include + +/ { + chosen { + stdout-path = &uart1; + }; + + aliases { + ethernet0 = &fec; + }; + + backlight_lvds: backlight-lvds { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 500000 0>; + /* + * Backlight doesn't register anything until about half of max + * brightness. So start the first real step at something that + * makes the display visible. From there, make each step + * meaningful along the scale. + */ + brightness-levels = < 0 48 49 50 51 52 53 54 55 56 + 57 58 59 60 61 62 63 64 65 66 + 67 68 69 70 71 72 73 74 75 76 + 77 78 78 80 81 82 83 84 85 86 + 87 88 89 90 91 92 93 94 95 96 + 97 98 99 100>; + default-brightness-level = <53>; + + power-supply = <®_5v>; + }; + + lcd_lvds0: disp0 { + compatible = "panel-lvds"; + backlight = <&backlight_lvds>; + power-supply = <®_lcd_3v3>; + width-mm = <21>; + height-mm = <16>; + data-mapping = "vesa-24"; + + panel-timing { + clock-frequency = <40000000>; + hactive = <800>; + vactive = <600>; + hback-porch = <46>; + hfront-porch = <210>; + vback-porch = <23>; + vfront-porch = <12>; + hsync-len = <20>; + vsync-len = <10>; + de-active = <1>; + hsync-active = <1>; + vsync-active = <1>; + pixelclk-active = <0>; + }; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; + + pps { + /* Part of Telit GPS radio */ + compatible = "pps-gpio"; + gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_can_3v3: regulator-can-en { + compatible = "regulator-fixed"; + regulator-name = "CAN_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 16 GPIO_ACTIVE_HIGH>; + }; + + reg_lcd_3v3: regulator-lcd { + /* pinctrl_lcd_gpio hog already sets up the GPIO for this reg */ + compatible = "regulator-fixed"; + regulator-name = "LCD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + startup-delay-us = <60000>; + }; + + sound { + compatible = "fsl,imx-audio-sgtl5000"; + audio-codec = <&sgtl5000>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + model = "On-board Codec"; + /* These describe the connection of SSI source (int) to audio out (ext) */ + mux-int-port = <1>; + mux-ext-port = <3>; + ssi-controller = <&ssi1>; + }; +}; + +&audmux { + status = "okay"; +}; + +&can1 { + xceiver-supply = <®_can_3v3>; +}; + +&can2 { + xceiver-supply = <®_can_3v3>; +}; + +&ecspi2 { + num-cs = <3>; + cs-gpios = < + &gpio6 2 GPIO_ACTIVE_LOW + &gpio5 29 GPIO_ACTIVE_LOW + &gpio4 27 GPIO_ACTIVE_LOW + >; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + status = "okay"; + + tsc2046: touchscreen@1 { + reg = <1>; + compatible = "ti,tsc2046"; + interrupt-parent = <&gpio4>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + spi-max-frequency = <2000000>; + pendown-gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; + vcc-supply = <®_3v3>; + ti,swap-xy; + ti,keep-vref-on; + ti,vref-mv = <3300>; + ti,settle-delay-usec = /bits/ 16 <500>; + ti,x-plate-ohms = /bits/ 16 <715>; + ti,pressure-max = /bits/ 16 <65535>; + ti,debounce-rep = /bits/ 16 <1>; + ti,debounce-tol = /bits/ 16 <30>; + ti,debounce-max = /bits/ 16 <255>; + ti,pendown-gpio-debounce = <5000>; + wakeup-source; + }; + + spidev: spi@2 { + compatible = "spidev"; + reg = <2>; + spi-max-frequency = <18000000>; + }; +}; + +/* + * This platform uses a different pin for USB 5 V control than other + * combinations and what the TS-4900 dts expects. Because of that, + * need to adjust pin names for sanity. + */ + +&gpio2 { + gpio-line-names = "", "", "", "", "", "", "", "", "", "", "", "", "", + "", "", "", "IRQ7", "", "XBEE_CTS", "", "", "OFF_BD_RESET", + "", "", "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = "", "", "", "", "", "", "", "", "", "", "", "", "", + "", "", "", "PUSH_SW_1#", "", "PCIE_SEL#", "", "ETH_PHY_RESET", + "", "EN_USB_5V", "", "EN_GPS_3.3V#", "TOUCH_WAKE#", "", "", + "PWR_FAIL#", "", "DIO_7", "DIO_8"; +}; + +&gpio5 { + gpio-line-names = "", "", "", "", "IRQ5", "DIO_9", "DIO_10", "DIO_11", + "DIO_12", "IRQ9", "PUSH_SW_2#", "GPS_PPS", "", "USER_JMP_1#", + "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", + "", ""; + + en-line-amp-hog { + gpio-hog; + gpios = <15 GPIO_ACTIVE_HIGH>; + line-name = "LINE_AMP_EN"; + output-high; + }; +}; + +&gpio6 { + gpio-line-names = "", "", "", "", "", "", "IRQ6", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", + "", "", "", ""; +}; + +&i2c2 { + status = "okay"; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + + sgtl5000: audio-codec@a { + compatible = "fsl,sgtl5000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sgtl5000>; + reg = <0x0a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <®_3v3>; + VDDIO-supply = <®_3v3>; + }; + + mma8451: accelerometer@1c { + compatible = "fsl,mma8451"; + reg = <0x1c>; + vdd-supply = <®_3v3>; + vddio-supply = <®_3v3>; + interrupt-parent = <&gpio5>; + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "INT1"; + /* INT2 connected to spare pins, otherwise unused */ + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog &pinctrl_lcd_gpio>; + + pinctrl_ecspi2_touch: ecspi2 { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1 + MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x100b1 // Offboard CS0# + MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x100b1 // FPGA CS1# + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b088 // FPGA_RESET# + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b088 // FPGA_DONE + MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x10 // FPGA 24MHZ + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b088 // FPGA_IRQ + MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b088 // TOUCH_WAKE# + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b088 + >; + }; + + pinctrl_lcd3v3: lcdreggrp { + fsl,pins = < + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b088 // EN_LCD_3.3V + >; + }; + + pinctrl_sgtl5000: sgtl5000grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 // Audio CLK + >; + }; + + pinctrl_eim: eim { + fsl,pins = < + MX6QDL_PAD_EIM_DA0__EIM_AD00 0x1b088 // MUX_AD_00 + MX6QDL_PAD_EIM_DA1__EIM_AD01 0x1b088 // MUX_AD_01 + MX6QDL_PAD_EIM_DA2__EIM_AD02 0x1b088 // MUX_AD_02 + MX6QDL_PAD_EIM_DA3__EIM_AD03 0x1b088 // MUX_AD_03 + MX6QDL_PAD_EIM_DA4__EIM_AD04 0x1b088 // MUX_AD_04 + MX6QDL_PAD_EIM_DA5__EIM_AD05 0x1b088 // MUX_AD_05 + MX6QDL_PAD_EIM_DA6__EIM_AD06 0x1b088 // MUX_AD_06 + MX6QDL_PAD_EIM_DA7__EIM_AD07 0x1b088 // MUX_AD_07 + MX6QDL_PAD_EIM_DA8__EIM_AD08 0x1b088 // MUX_AD_08 + MX6QDL_PAD_EIM_DA9__EIM_AD09 0x1b088 // MUX_AD_09 + MX6QDL_PAD_EIM_DA10__EIM_AD10 0x1b088 // MUX_AD_10 + MX6QDL_PAD_EIM_DA11__EIM_AD11 0x1b088 // MUX_AD_11 + MX6QDL_PAD_EIM_DA12__EIM_AD12 0x1b088 // MUX_AD_12 + MX6QDL_PAD_EIM_DA13__EIM_AD13 0x1b088 // MUX_AD_13 + MX6QDL_PAD_EIM_DA14__EIM_AD14 0x1b088 // MUX_AD_14 + MX6QDL_PAD_EIM_DA15__EIM_AD15 0x1b088 // MUX_AD_15 + MX6QDL_PAD_EIM_A16__EIM_ADDR16 0x1b088 // MX6_A16 + MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0x1b088 // BUS_ALE# + MX6QDL_PAD_EIM_RW__EIM_RW 0x1b088 // BUS_DIR + MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0x1b088 // BUS_CS# + MX6QDL_PAD_EIM_WAIT__EIM_DTACK_B 0x1b088 // BUS_WAIT# + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b088 // D31/GPIO + MX6QDL_PAD_EIM_EB1__EIM_EB1_B 0x1b088 // BUS_BHE# + >; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + + status = "okay"; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; From 9d00ae8e2f9c3ab5ca8dfb5af38bf970689c6e09 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Tue, 15 Nov 2022 17:26:29 -0800 Subject: [PATCH 017/244] ARM: dts: imx6: Initial TS-8390-4900 support Signed-off-by: Kris Bahnsen Signed-off-by: Mark Featherston --- arch/arm/boot/dts/nxp/imx/Makefile | 2 + arch/arm/boot/dts/nxp/imx/imx6dl-ts4900-2.dts | 18 + arch/arm/boot/dts/nxp/imx/imx6q-ts4900-2.dts | 14 + .../dts/nxp/imx/imx6qdl-ts4900-ts8390.dtsi | 309 ++++++++++++++++++ 4 files changed, 343 insertions(+) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6dl-ts4900-2.dts create mode 100644 arch/arm/boot/dts/nxp/imx/imx6q-ts4900-2.dts create mode 100644 arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900-ts8390.dtsi diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx/Makefile index 919250e319ca2..488ecb2a723c5 100644 --- a/arch/arm/boot/dts/nxp/imx/Makefile +++ b/arch/arm/boot/dts/nxp/imx/Makefile @@ -133,6 +133,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-skov-revc-lt6.dtb \ imx6dl-solidsense.dtb \ imx6dl-ts4900.dtb \ + imx6dl-ts4900-2.dtb \ imx6dl-ts4900-14.dtb \ imx6dl-ts7970.dtb \ imx6dl-tx6dl-comtft.dtb \ @@ -253,6 +254,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-solidsense.dtb \ imx6q-tbs2910.dtb \ imx6q-ts4900.dtb \ + imx6q-ts4900-2.dtb \ imx6q-ts4900-14.dtb \ imx6q-ts7970.dtb \ imx6q-tx6q-1010.dtb \ diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-ts4900-2.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-ts4900-2.dts new file mode 100644 index 0000000000000..ccc32058e4d8e --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-ts4900-2.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright 2017-2022 Technologic Systems, Inc. dba embeddedTS + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-ts4900.dtsi" +#include "imx6qdl-ts4900-ts8390.dtsi" + +/ { + model = "embeddedTS i.MX6 Solo/DualLite TS-4900 (TS-TPC-8390)"; + compatible = "fsl,imx6dl-ts4900", "fsl,imx6dl"; +}; + +&epdc { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-ts4900-2.dts b/arch/arm/boot/dts/nxp/imx/imx6q-ts4900-2.dts new file mode 100644 index 0000000000000..b49b9ce54a8ea --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-ts4900-2.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright 2017-2022 Technologic Systems, Inc. dba embeddedTS + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-ts4900.dtsi" +#include "imx6qdl-ts4900-ts8390.dtsi" + +/ { + model = "embeddedTS i.MX6 Quad TS-4900 (TS-TPC-8390)"; + compatible = "fsl,imx6q-ts4900", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900-ts8390.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900-ts8390.dtsi new file mode 100644 index 0000000000000..6c5d37ff5eeb2 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900-ts8390.dtsi @@ -0,0 +1,309 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright 2017-2022 Technologic Systems, Inc. dba embeddedTS + */ + +#include +#include + +/ { + chosen { + stdout-path = &uart1; + }; + + aliases { + ethernet0 = &fec; + i2c3 = &i2c3_gpio; + }; + + adc_ansel_mux: mux-controller { + compatible = "gpio-mux"; + #mux-control-cells = <0>; + mux-gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>; + }; + + adc_chan23: chan23-mux { + compatible = "io-channel-mux"; + io-channels = <&muxed_adc 2>; + io-channel-names = "parent"; + #io-channel-cells = <1>; + mux-controls = <&adc_ansel_mux>; + settle-time-us = <10000>; + + channels = "channel2", "channel3"; + }; + + adc_chan45: chan45-mux { + compatible = "io-channel-mux"; + io-channels = <&muxed_adc 3>; + io-channel-names = "parent"; + #io-channel-cells = <1>; + mux-controls = <&adc_ansel_mux>; + settle-time-us = <10000>; + + channels = "channel4", "channel5"; + }; + + backlight_lcd: backlight-lcd { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 500000 0>; + /* + * Backlight doesn't register anything until about half of max + * brightness. So start the first real step at something that + * makes the display visible. From there, make each step + * meaningful along the scale. + */ + brightness-levels = < 0 48 49 50 51 52 53 54 55 56 + 57 58 59 60 61 62 63 64 65 66 + 67 68 69 70 71 72 73 74 75 76 + 77 78 78 80 81 82 83 84 85 86 + 87 88 89 90 91 92 93 94 95 96 + 97 98 99 100>; + default-brightness-level = <53>; + power-supply = <®_5v>; + }; + + /* The TS-4900 pinctrl hog provides these as GPIO */ + i2c3_gpio: i2c { + compatible = "i2c-gpio"; + scl-gpios = <&gpio6 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + #address-cells = <1>; + #size-cells = <0>; + + muxed_adc: adc@68 { + compatible = "mcp3428", "mcp3422"; + #io-channel-cells = <1>; + reg = <0x68>; + }; + }; + + lcd_display: disp0 { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd>; + + display-timings { + OKAYA-WVGA { + clock-frequency = <30066000>; + hactive = <800>; + vactive = <480>; + hfront-porch = <50>; + hback-porch = <70>; + hsync-len = <50>; + vback-porch = <2>; + vfront-porch = <2>; + vsync-len = <50>; + + de-active = <1>; + pixelclk-active = <1>; + }; + }; + + port@0 { + lcd_display_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_lcd3v3: regulator-lcd { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd3v3>; + regulator-name = "LCD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + startup-delay-us = <60000>; + }; + + sound { + compatible = "fsl,imx-audio-sgtl5000"; + audio-codec = <&sgtl5000>; + audio-routing = + "Ext Spk", "LINE_OUT", + "Headphone Jack", "HP_OUT"; + model = "On-board Codec"; + /* These describe the connection of SSI source (int) to audio out (ext) */ + mux-int-port = <1>; + mux-ext-port = <3>; + ssi-controller = <&ssi1>; + }; + + /* The TS-4900 pinctrl hog provides these as GPIO */ + spi_gpio: spi { + compatible = "spi-gpio"; + num-chipselects = <1>; + #address-cells = <1>; + #size-cells = <0>; + + sck-gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; + miso-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; + + ads7843: touchscreen@0 { + compatible = "ti,ads7843"; + reg = <0>; + interrupt-parent = <&gpio3>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + vcc-supply = <®_3v3>; + spi-max-frequency = <100000>; + pendown-gpio = <&gpio3 11 GPIO_ACTIVE_HIGH>; + touchscreen-swapped-x-y; + ti,vref-mv = /bits/ 16 <3300>; + ti,keep-vref-on; + ti,settle-delay-usec = /bits/ 16 <500>; + ti,debounce-rep = /bits/ 16 <1>; + ti,debounce-tol = /bits/ 16 <30>; + ti,debounce-max = /bits/ 16 <255>; + ti,penirq-recheck-delay-usecs = /bits/ 16 <500>; + ti,pressure-max = /bits/ 16 <255>; + wakeup-source; + }; + }; +}; + +&audmux { + status = "okay"; +}; + +&ecspi2 { + num-cs = <2>; + cs-gpios = < + &gpio6 2 GPIO_ACTIVE_LOW + &gpio5 29 GPIO_ACTIVE_LOW + >; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + status = "okay"; + + offbdspi: spi@1 { + compatible = "spidev"; + reg = <1>; + spi-max-frequency = <1000000>; + }; +}; + +&gpio2 { + gpio-line-names = "", "", "", "", "", "", "", "", "", "", "", "", "", + "", "", "IN_11", "OUT_2", "IN_0", "IN_4", "", "", "", "", + "OUT_4", "", "", "", "OUT_5", "", "OUT_3", ""; +}; +&gpio3 { + gpio-line-names = "", "", "", "", "", "", "", "", "OUT_6", "OUT_7", "", + "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", + "", "", "", ""; +}; +&gpio4 { + gpio-line-names = "", "", "", "", "", "IN_5", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", + "", "", ""; +}; + +&gpio5 { + gpio-line-names = "IN_2", "", "", "", "OUT_0", "", "", "", "", "", "", + "", "", "", "", "", "", "", "IN_7", "OUT_8", "", "", "", "", "", + "", "", "", "", "", ""; + + en-line-amp-hog { + gpio-hog; + gpios = <30 GPIO_ACTIVE_HIGH>; + line-name = "LINE_AMP_EN"; + output-high; + }; +}; + +&gpio6 { + gpio-line-names = "", "", "", "IN_6", "", "", "OUT_1", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", + "", "", "", ""; +}; + +&gpio7 { + gpio-line-names = "", "", "", "", "", "", "", "", "IN_9", "", "", + "IN_10", "IN_8", "", "", "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", ""; +}; + +&gpio8 { + gpio-line-names = "", "", "IN_3", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", + "", "", "", "IN_1"; +}; + +&i2c2 { + sgtl5000: sgtl5000@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2s>; + #sound-dai-cells = <0>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <®_3v3>; + VDDIO-supply = <®_3v3>; + VDDD-supply = <®_1v8>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog &pinctrl_muxbus_gpio>; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b088 + >; + }; + + pinctrl_lcd3v3: lcdreggrp { + fsl,pins = < + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b088 /* EN_LCD_3.3V */ + >; + }; + + /* + * These are normally GPIO per hog and muxbus_gpio, but kept separate + * in case either of those need to be broken up. + */ + pinctrl_i2c3adc: i2c3adcgrp { + fsl,pins = < + MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x1b088 /* AN_SEL */ + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b088 /* ADC_CLK */ + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b088 /* ADC_DAT */ + >; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&lcd_display_in>; +}; + +&pcie { + status = "disabled"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; From 7bc0b35614f3b82336d961297f6bdec6795dcaf9 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Tue, 13 Dec 2022 17:14:00 -0700 Subject: [PATCH 018/244] ARM: imx6: Move accelerometer to module Signed-off-by: Kris Bahnsen --- arch/arm/configs/tsimx6_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/configs/tsimx6_defconfig b/arch/arm/configs/tsimx6_defconfig index f23857f233cbe..e0ee7e4b4de65 100644 --- a/arch/arm/configs/tsimx6_defconfig +++ b/arch/arm/configs/tsimx6_defconfig @@ -1434,7 +1434,7 @@ CONFIG_IIO=y CONFIG_IIO_BUFFER_CB=m CONFIG_IIO_SW_DEVICE=m CONFIG_IIO_SW_TRIGGER=m -CONFIG_MMA8452=y +CONFIG_MMA8452=m CONFIG_IMX7D_ADC=y CONFIG_RN5T618_ADC=y CONFIG_VF610_ADC=y From 9c5665d5f8c788ef889dafab7625cc86dba2fa49 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Fri, 6 Jan 2023 17:22:53 -0700 Subject: [PATCH 019/244] ARM: dts: imx6: Fix model string for TS-7970 Signed-off-by: Kris Bahnsen --- arch/arm/boot/dts/nxp/imx/imx6dl-ts7970.dts | 2 +- arch/arm/boot/dts/nxp/imx/imx6q-ts7970.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-ts7970.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-ts7970.dts index 7eb46c6512289..52096ae47ed8d 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-ts7970.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-ts7970.dts @@ -9,7 +9,7 @@ #include "imx6qdl-ts7970.dtsi" / { - model = "Technologic Systems i.MX6 Solo/DualLite TS-7970 (Default Device Tree)"; + model = "embeddedTS i.MX6 Solo/DualLite TS-7970 (Default Device Tree)"; compatible = "technologic,imx6dl-ts7970", "fsl,imx6dl"; /* Will be filled by the bootloader */ diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-ts7970.dts b/arch/arm/boot/dts/nxp/imx/imx6q-ts7970.dts index fb26b15185a08..ecbec7d8bbe11 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-ts7970.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-ts7970.dts @@ -9,7 +9,7 @@ #include "imx6qdl-ts7970.dtsi" / { - model = "Technologic Systems i.MX6 Quad TS-7970 (Default Device Tree)"; + model = "embeddedTS i.MX6 Quad TS-7970 (Default Device Tree)"; compatible = "technologic,imx6q-ts7970", "fsl,imx6q"; /* Will be filled by the bootloader */ From 57df112e8c81df81beeb253b2b0892ae06062929 Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Wed, 18 Jan 2023 16:41:54 -0700 Subject: [PATCH 020/244] ARM: tsimx6_defconfig: Renamed to ts_defconfig Preparing to move to a common config file for most of embeddedTS devices. --- arch/arm/configs/{tsimx6_defconfig => ts_defconfig} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename arch/arm/configs/{tsimx6_defconfig => ts_defconfig} (100%) diff --git a/arch/arm/configs/tsimx6_defconfig b/arch/arm/configs/ts_defconfig similarity index 100% rename from arch/arm/configs/tsimx6_defconfig rename to arch/arm/configs/ts_defconfig From cea76281374521f0fa2b5fa5c7d27d80d901406b Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Wed, 18 Jan 2023 16:43:25 -0700 Subject: [PATCH 021/244] ARM: ts_defconfig: Add i.MX6UL, add features, reduce size Remove i.MX SL/SX support, not needed Added configuration options needed by Docker Larger features (e.g. nfsv4) moved to modules to reduce kernel size Added compressed module support --- arch/arm/configs/ts_defconfig | 65 ++++++++++++++++++++++------------- 1 file changed, 41 insertions(+), 24 deletions(-) diff --git a/arch/arm/configs/ts_defconfig b/arch/arm/configs/ts_defconfig index e0ee7e4b4de65..0401c2d9950d0 100644 --- a/arch/arm/configs/ts_defconfig +++ b/arch/arm/configs/ts_defconfig @@ -7,11 +7,19 @@ CONFIG_HIGH_RES_TIMERS=y CONFIG_PREEMPT=y CONFIG_LOG_BUF_SHIFT=18 CONFIG_CGROUPS=y +CONFIG_MEMCG=y +CONFIG_BLK_CGROUP=y +CONFIG_CGROUP_SCHED=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_RT_GROUP_SCHED=y CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_RDMA=y CONFIG_CGROUP_FREEZER=y CONFIG_CPUSETS=y # CONFIG_PROC_PID_CPUSET is not set CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_PERF=y CONFIG_CGROUP_BPF=y CONFIG_CGROUP_DEBUG=y CONFIG_NAMESPACES=y @@ -19,16 +27,18 @@ CONFIG_USER_NS=y CONFIG_CHECKPOINT_RESTORE=y CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y +# CONFIG_RD_LZMA is not set +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +# CONFIG_RD_ZSTD is not set CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_BPF_SYSCALL=y CONFIG_EMBEDDED=y +CONFIG_PERF_EVENTS=y # CONFIG_COMPAT_BRK is not set CONFIG_ARCH_MXC=y CONFIG_SOC_IMX6Q=y -CONFIG_SOC_IMX6SL=y -CONFIG_SOC_IMX6SLL=y -CONFIG_SOC_IMX6SX=y -CONFIG_ARM_ERRATA_814220=y +CONFIG_SOC_IMX6UL=y CONFIG_SMP=y CONFIG_HAVE_ARM_ARCH_TIMER=y CONFIG_ARM_PSCI=y @@ -56,7 +66,10 @@ CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODVERSIONS=y CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_MODULE_COMPRESS=y +CONFIG_MODULE_COMPRESS_XZ=y CONFIG_BLK_DEV_INTEGRITY=y +CONFIG_BLK_DEV_THROTTLING=y CONFIG_BLK_CMDLINE_PARSER=y CONFIG_PARTITION_ADVANCED=y CONFIG_BINFMT_MISC=y @@ -129,6 +142,7 @@ CONFIG_IPV6_PIMSM_V2=y CONFIG_NETWORK_SECMARK=y CONFIG_NETWORK_PHY_TIMESTAMPING=y CONFIG_NETFILTER=y +CONFIG_BRIDGE_NETFILTER=m CONFIG_NF_CONNTRACK=m CONFIG_NF_CONNTRACK_ZONES=y CONFIG_NF_CONNTRACK_PROCFS=y @@ -316,6 +330,7 @@ CONFIG_L2TP_V3=y CONFIG_L2TP_IP=m CONFIG_L2TP_ETH=m CONFIG_BRIDGE=m +CONFIG_BRIDGE_VLAN_FILTERING=y CONFIG_NET_DSA=m CONFIG_VLAN_8021Q=m CONFIG_VLAN_8021Q_GVRP=y @@ -406,6 +421,7 @@ CONFIG_NET_ACT_SKBMOD=m CONFIG_NET_ACT_IFE=m CONFIG_NET_ACT_TUNNEL_KEY=m CONFIG_DCB=y +CONFIG_DNS_RESOLVER=y CONFIG_BATMAN_ADV=m CONFIG_BATMAN_ADV_NC=y CONFIG_BATMAN_ADV_DEBUG=y @@ -533,13 +549,8 @@ CONFIG_SATA_AHCI_PLATFORM=y CONFIG_AHCI_IMX=y CONFIG_PATA_IMX=y CONFIG_MD=y -CONFIG_BLK_DEV_MD=y -CONFIG_MD_LINEAR=y -CONFIG_MD_RAID0=y -CONFIG_MD_RAID1=y -CONFIG_MD_RAID10=y -CONFIG_MD_RAID456=y -CONFIG_MD_MULTIPATH=y +CONFIG_MD_LINEAR=m +CONFIG_MD_MULTIPATH=m CONFIG_BCACHE=m CONFIG_BLK_DEV_DM=y CONFIG_DM_CRYPT=y @@ -561,6 +572,7 @@ CONFIG_DM_SWITCH=m CONFIG_DM_LOG_WRITES=m CONFIG_NETDEVICES=y CONFIG_BONDING=m +CONFIG_DUMMY=m CONFIG_EQUALIZER=m CONFIG_IFB=m CONFIG_NET_TEAM=m @@ -1459,23 +1471,23 @@ CONFIG_EXT2_FS_SECURITY=y CONFIG_EXT3_FS=y CONFIG_EXT3_FS_POSIX_ACL=y CONFIG_EXT3_FS_SECURITY=y -CONFIG_REISERFS_FS=y +CONFIG_REISERFS_FS=m CONFIG_REISERFS_FS_XATTR=y CONFIG_REISERFS_FS_POSIX_ACL=y CONFIG_REISERFS_FS_SECURITY=y -CONFIG_JFS_FS=y +CONFIG_JFS_FS=m CONFIG_JFS_POSIX_ACL=y CONFIG_JFS_SECURITY=y -CONFIG_XFS_FS=y +CONFIG_XFS_FS=m CONFIG_XFS_QUOTA=y CONFIG_XFS_POSIX_ACL=y CONFIG_XFS_RT=y CONFIG_GFS2_FS=m CONFIG_OCFS2_FS=m -CONFIG_BTRFS_FS=y +CONFIG_BTRFS_FS=m CONFIG_BTRFS_FS_POSIX_ACL=y -CONFIG_NILFS2_FS=y -CONFIG_F2FS_FS=y +CONFIG_NILFS2_FS=m +CONFIG_F2FS_FS=m CONFIG_F2FS_FS_SECURITY=y CONFIG_F2FS_CHECK_FS=y CONFIG_QUOTA_NETLINK_INTERFACE=y @@ -1490,7 +1502,7 @@ CONFIG_JOLIET=y CONFIG_ZISOFS=y CONFIG_UDF_FS=m CONFIG_MSDOS_FS=m -CONFIG_VFAT_FS=y +CONFIG_VFAT_FS=m CONFIG_NTFS_FS=m CONFIG_NTFS_RW=y CONFIG_TMPFS_POSIX_ACL=y @@ -1521,7 +1533,7 @@ CONFIG_SYSV_FS=m CONFIG_UFS_FS=m CONFIG_NFS_FS=y CONFIG_NFS_V3_ACL=y -CONFIG_NFS_V4=y +CONFIG_NFS_V4=m CONFIG_NFS_V4_1=y CONFIG_NFS_V4_2=y CONFIG_NFS_V4_1_MIGRATION=y @@ -1588,12 +1600,16 @@ CONFIG_NLS_MAC_TURKISH=m CONFIG_NLS_UTF8=y CONFIG_CRYPTO_USER=y # CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set -CONFIG_CRYPTO_TEST=m +CONFIG_CRYPTO_ECDH=y CONFIG_CRYPTO_CCM=y CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_SEQIV=y CONFIG_CRYPTO_ECHAINIV=y CONFIG_CRYPTO_LRW=y CONFIG_CRYPTO_CMAC=y +CONFIG_CRYPTO_CRC32=y +CONFIG_CRYPTO_XXHASH=y +CONFIG_CRYPTO_BLAKE2B=y CONFIG_CRYPTO_MD4=y CONFIG_CRYPTO_MICHAEL_MIC=y CONFIG_CRYPTO_RMD128=y @@ -1604,15 +1620,16 @@ CONFIG_CRYPTO_SHA512=y CONFIG_CRYPTO_SHA3=y CONFIG_CRYPTO_TGR192=y CONFIG_CRYPTO_WP512=y -CONFIG_CRYPTO_BLOWFISH=y -CONFIG_CRYPTO_CAMELLIA=y -CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_TWOFISH=m CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_LZO=m CONFIG_CRYPTO_DEV_FSL_CAAM=y CONFIG_CRYPTO_DEV_SAHARA=y CONFIG_CRYPTO_DEV_MXS_DCP=y CONFIG_CRC7=m +CONFIG_LIBCRC32C=y CONFIG_CMA_SIZE_MBYTES=128 CONFIG_PRINTK_TIME=y CONFIG_DYNAMIC_DEBUG=y From 82e4bf609dc7aefb5b80746bcbbfb99f9efd1d20 Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Tue, 28 Aug 2018 10:23:34 -0700 Subject: [PATCH 022/244] pixcir: Support inverted IRQ polarity The TS-TPC-7990 has an inverted interrupt system in order to allow the touchscreen to wake the device. The CPU pin is expecting a falling IRQ, but the INT pin on the touchscreen controller must be set to active high output. This adds invert-int-output property to the devicetree parsing. If set, it inverts the INT output from the controller, but the driver remains configured for active low IRQ. Base on commit 461fc502098ea5296e0cb3de6afd567a4ce17874 from https://github.com/embeddedTS/linux-tsimx Signed-off-by: Kris Bahnsen --- drivers/input/touchscreen/pixcir_i2c_ts.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/input/touchscreen/pixcir_i2c_ts.c b/drivers/input/touchscreen/pixcir_i2c_ts.c index dad5786e82a46..20a8d64c028b4 100644 --- a/drivers/input/touchscreen/pixcir_i2c_ts.c +++ b/drivers/input/touchscreen/pixcir_i2c_ts.c @@ -81,6 +81,7 @@ struct pixcir_i2c_ts_data { struct gpio_desc *gpio_wake; const struct pixcir_i2c_chip_data *chip; struct touchscreen_properties prop; + int irq_polarity; bool running; }; @@ -345,7 +346,8 @@ static int pixcir_start(struct pixcir_i2c_ts_data *ts) } /* LEVEL_TOUCH interrupt with active low polarity */ - error = pixcir_set_int_mode(ts, PIXCIR_INT_LEVEL_TOUCH, 0); + error = pixcir_set_int_mode(ts, PIXCIR_INT_LEVEL_TOUCH, + ts->irq_polarity); if (error) { dev_err(dev, "Failed to set interrupt mode: %d\n", error); return error; @@ -514,6 +516,8 @@ static int pixcir_i2c_ts_probe(struct i2c_client *client) input_set_drvdata(input, tsdata); + tsdata->irq_polarity = device_property_read_bool(dev, "invert-int-output"); + tsdata->gpio_attb = devm_gpiod_get(dev, "attb", GPIOD_IN); if (IS_ERR(tsdata->gpio_attb)) return dev_err_probe(dev, PTR_ERR(tsdata->gpio_attb), From 0b91fdcd494c358a231eeef76ab230877b95a2f8 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Wed, 14 Dec 2022 11:32:49 -0800 Subject: [PATCH 023/244] ARM: dts: imx6: Initial TS-TPC-7990 support Similar support to what is available in our linux-tsimx repo. Supports all TS-7990 variants including LXD, Okaya, and Microtips LCDs and touch screens. Signed-off-by: Kris Bahnsen Signed-off-by: Mark Featherston --- arch/arm/boot/dts/nxp/imx/Makefile | 12 + .../dts/nxp/imx/imx6dl-ts7990-lxd-revb.dts | 106 +++ .../boot/dts/nxp/imx/imx6dl-ts7990-lxd.dts | 74 ++ .../nxp/imx/imx6dl-ts7990-microtips-revb.dts | 93 +++ .../dts/nxp/imx/imx6dl-ts7990-microtips.dts | 61 ++ .../dts/nxp/imx/imx6dl-ts7990-okaya-revb.dts | 93 +++ .../boot/dts/nxp/imx/imx6dl-ts7990-okaya.dts | 61 ++ .../dts/nxp/imx/imx6q-ts7990-lxd-revb.dts | 103 +++ .../arm/boot/dts/nxp/imx/imx6q-ts7990-lxd.dts | 78 ++ .../nxp/imx/imx6q-ts7990-microtips-revb.dts | 90 +++ .../dts/nxp/imx/imx6q-ts7990-microtips.dts | 65 ++ .../dts/nxp/imx/imx6q-ts7990-okaya-revb.dts | 90 +++ .../boot/dts/nxp/imx/imx6q-ts7990-okaya.dts | 65 ++ arch/arm/boot/dts/nxp/imx/imx6qdl-ts7990.dtsi | 724 ++++++++++++++++++ 14 files changed, 1715 insertions(+) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6dl-ts7990-lxd-revb.dts create mode 100644 arch/arm/boot/dts/nxp/imx/imx6dl-ts7990-lxd.dts create mode 100644 arch/arm/boot/dts/nxp/imx/imx6dl-ts7990-microtips-revb.dts create mode 100644 arch/arm/boot/dts/nxp/imx/imx6dl-ts7990-microtips.dts create mode 100644 arch/arm/boot/dts/nxp/imx/imx6dl-ts7990-okaya-revb.dts create mode 100644 arch/arm/boot/dts/nxp/imx/imx6dl-ts7990-okaya.dts create mode 100644 arch/arm/boot/dts/nxp/imx/imx6q-ts7990-lxd-revb.dts create mode 100644 arch/arm/boot/dts/nxp/imx/imx6q-ts7990-lxd.dts create mode 100644 arch/arm/boot/dts/nxp/imx/imx6q-ts7990-microtips-revb.dts create mode 100644 arch/arm/boot/dts/nxp/imx/imx6q-ts7990-microtips.dts create mode 100644 arch/arm/boot/dts/nxp/imx/imx6q-ts7990-okaya-revb.dts create mode 100644 arch/arm/boot/dts/nxp/imx/imx6q-ts7990-okaya.dts create mode 100644 arch/arm/boot/dts/nxp/imx/imx6qdl-ts7990.dtsi diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx/Makefile index 488ecb2a723c5..1262dbd3ba95c 100644 --- a/arch/arm/boot/dts/nxp/imx/Makefile +++ b/arch/arm/boot/dts/nxp/imx/Makefile @@ -136,6 +136,12 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-ts4900-2.dtb \ imx6dl-ts4900-14.dtb \ imx6dl-ts7970.dtb \ + imx6dl-ts7990-lxd-revb.dtb \ + imx6dl-ts7990-lxd.dtb \ + imx6dl-ts7990-microtips-revb.dtb \ + imx6dl-ts7990-microtips.dtb \ + imx6dl-ts7990-okaya-revb.dtb \ + imx6dl-ts7990-okaya.dtb \ imx6dl-tx6dl-comtft.dtb \ imx6dl-tx6s-8034.dtb \ imx6dl-tx6s-8034-mb7.dtb \ @@ -257,6 +263,12 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-ts4900-2.dtb \ imx6q-ts4900-14.dtb \ imx6q-ts7970.dtb \ + imx6q-ts7990-lxd-revb.dtb \ + imx6q-ts7990-lxd.dtb \ + imx6q-ts7990-microtips-revb.dtb \ + imx6q-ts7990-microtips.dtb \ + imx6q-ts7990-okaya-revb.dtb \ + imx6q-ts7990-okaya.dtb \ imx6q-tx6q-1010.dtb \ imx6q-tx6q-1010-comtft.dtb \ imx6q-tx6q-1020.dtb \ diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-ts7990-lxd-revb.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-ts7990-lxd-revb.dts new file mode 100644 index 0000000000000..d99a2ea29ff05 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-ts7990-lxd-revb.dts @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright 2017-2022 Technologic Systems, Inc. dba embeddedTS + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-ts7990.dtsi" + +/ { + model = "embeddedTS i.MX6 Solo/DualLite TS-7990 (LXD) REV B"; + compatible = "fsl,imx6dl-ts7990", "fsl,imx6dl"; + + lcd_lvds0: disp0 { + compatible = "panel-lvds"; + backlight = <&backlight0>; + width-mm = <15>; + height-mm = <9>; + data-mapping = "vesa-24"; + + panel-timing { + clock-frequency = <51200000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <46>; + hfront-porch = <210>; + vback-porch = <23>; + vfront-porch = <12>; + hsync-len = <20>; + vsync-len = <10>; + de-active = <1>; + hsync-active = <1>; + vsync-active = <1>; + pixelclk-active = <0>; + }; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; + + wifi_spi: spi-gpio { + compatible = "spi-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi5gpio>; + status = "okay"; + num-chipselects = <1>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-sck = <&gpio1 20 GPIO_ACTIVE_HIGH>; + gpio-mosi = <&gpio1 18 GPIO_ACTIVE_HIGH>; + gpio-miso = <&gpio1 16 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; + + wilc3000: wifi@0 { + compatible = "microchip,wilc3000"; + reg = <0>; + spi-max-frequency = <18000000>; + reset-gpios = <&gpio8 13 GPIO_ACTIVE_HIGH>; + chip_en-gpios = <&gpio8 14 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio1>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + }; + }; +}; + +&pixcir_tangoc { + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + imx6-ts7990 { + pinctrl_ecspi5gpio: ecspi5gpio { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x100b1 /* mosi */ + MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x100b1 /* sclk */ + MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x100b1 /* miso */ + MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b088 /* SPI_1_CS# */ + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b088 /* WIFI_IRQ# */ + >; + }; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + + status = "okay"; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-ts7990-lxd.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-ts7990-lxd.dts new file mode 100644 index 0000000000000..12442900d913e --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-ts7990-lxd.dts @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright 2017-2022 Technologic Systems, Inc. dba embeddedTS + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-ts7990.dtsi" + +/ { + model = "embeddedTS i.MX6 Solo/DualLite TS-7990 (LXD)"; + compatible = "fsl,imx6dl-ts7990", "fsl,imx6dl"; + + lcd_lvds0: disp0 { + compatible = "panel-lvds"; + backlight = <&backlight0>; + width-mm = <15>; + height-mm = <9>; + data-mapping = "vesa-24"; + + panel-timing { + clock-frequency = <51200000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <46>; + hfront-porch = <210>; + vback-porch = <23>; + vfront-porch = <12>; + hsync-len = <20>; + vsync-len = <10>; + de-active = <1>; + hsync-active = <1>; + vsync-active = <1>; + pixelclk-active = <0>; + }; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&pixcir_tangoc { + status = "okay"; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + + status = "okay"; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&usdhc1 { + status = "okay"; +}; + +®_wlan_vqmmc { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-ts7990-microtips-revb.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-ts7990-microtips-revb.dts new file mode 100644 index 0000000000000..cfa248ab5f3ad --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-ts7990-microtips-revb.dts @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright 2017-2022 Technologic Systems, Inc. dba embeddedTS + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-ts7990.dtsi" + +/ { + model = "embeddedTS i.MX6 Solo/DualLite TS-7990 (Microtips)"; + compatible = "fsl,imx6dl-ts7990", "fsl,imx6dl"; + + lcd_display: disp0 { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu>; + + display-timings { + MICROTIPS-WVGA { + clock-frequency = <30030000>; + hactive = <800>; + vactive = <480>; + hfront-porch = <46>; + hback-porch = <210>; + hsync-len = <1>; + vback-porch = <22>; + vfront-porch = <23>; + vsync-len = <1>; + + de-active = <1>; + pixelclk-active = <1>; + }; + }; + + port@0 { + lcd_display_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + }; + + wifi_spi: spi-gpio { + compatible = "spi-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi5gpio>; + status = "okay"; + num-chipselects = <1>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-sck = <&gpio1 20 GPIO_ACTIVE_HIGH>; + gpio-mosi = <&gpio1 18 GPIO_ACTIVE_HIGH>; + gpio-miso = <&gpio1 16 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; + + wilc3000: wifi@0 { + compatible = "microchip,wilc3000"; + reg = <0>; + spi-max-frequency = <18000000>; + reset-gpios = <&gpio8 13 GPIO_ACTIVE_HIGH>; + chip_en-gpios = <&gpio8 14 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio1>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + imx6-ts7990 { + pinctrl_ecspi5gpio: ecspi5gpio { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x100b1 /* mosi */ + MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x100b1 /* sclk */ + MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x100b1 /* miso */ + MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b088 /* SPI_1_CS# */ + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b088 /* WIFI_IRQ# */ + >; + }; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&lcd_display_in>; +}; + +&touch_spi { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-ts7990-microtips.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-ts7990-microtips.dts new file mode 100644 index 0000000000000..7ebcea1bd6868 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-ts7990-microtips.dts @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright 2017-2022 Technologic Systems, Inc. dba embeddedTS + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-ts7990.dtsi" + +/ { + model = "embeddedTS i.MX6 Solo/DualLite TS-7990 (Microtips)"; + compatible = "fsl,imx6dl-ts7990", "fsl,imx6dl"; + + lcd_display: disp0 { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu>; + + display-timings { + MICROTIPS-WVGA { + clock-frequency = <30030000>; + hactive = <800>; + vactive = <480>; + hfront-porch = <46>; + hback-porch = <210>; + hsync-len = <1>; + vback-porch = <22>; + vfront-porch = <23>; + vsync-len = <1>; + + de-active = <1>; + pixelclk-active = <1>; + }; + }; + + port@0 { + lcd_display_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&lcd_display_in>; +}; + +&touch_spi { + status = "okay"; +}; + +&usdhc1 { + status = "okay"; +}; + +®_wlan_vqmmc { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-ts7990-okaya-revb.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-ts7990-okaya-revb.dts new file mode 100644 index 0000000000000..557edfd5a724b --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-ts7990-okaya-revb.dts @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright 2017-2022 Technologic Systems, Inc. dba embeddedTS + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-ts7990.dtsi" + +/ { + model = "embeddedTS i.MX6 Solo/DualLite TS-7990 (Okaya)"; + compatible = "fsl,imx6dl-ts7990", "fsl,imx6dl"; + + lcd_display: disp0 { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu>; + + display-timings { + OKAYA-WVGA { + clock-frequency = <30066000>; + hactive = <800>; + vactive = <480>; + hfront-porch = <50>; + hback-porch = <70>; + hsync-len = <50>; + vback-porch = <2>; + vfront-porch = <2>; + vsync-len = <50>; + + de-active = <1>; + pixelclk-active = <1>; + }; + }; + + port@0 { + lcd_display_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + }; + + wifi_spi: spi-gpio { + compatible = "spi-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi5gpio>; + status = "okay"; + num-chipselects = <1>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-sck = <&gpio1 20 GPIO_ACTIVE_HIGH>; + gpio-mosi = <&gpio1 18 GPIO_ACTIVE_HIGH>; + gpio-miso = <&gpio1 16 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; + + wilc3000: wifi@0 { + compatible = "microchip,wilc3000"; + reg = <0>; + spi-max-frequency = <18000000>; + reset-gpios = <&gpio8 13 GPIO_ACTIVE_HIGH>; + chip_en-gpios = <&gpio8 14 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio1>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + imx6-ts7990 { + pinctrl_ecspi5gpio: ecspi5gpio { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x100b1 /* mosi */ + MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x100b1 /* sclk */ + MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x100b1 /* miso */ + MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b088 /* SPI_1_CS# */ + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b088 /* WIFI_IRQ# */ + >; + }; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&lcd_display_in>; +}; + +&touch_spi { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-ts7990-okaya.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-ts7990-okaya.dts new file mode 100644 index 0000000000000..730b1029b8c0e --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-ts7990-okaya.dts @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright 2017-2022 Technologic Systems, Inc. dba embeddedTS + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-ts7990.dtsi" + +/ { + model = "embeddedTS i.MX6 Solo/DualLite TS-7990 (Okaya)"; + compatible = "fsl,imx6dl-ts7990", "fsl,imx6dl"; + + lcd_display: disp0 { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu>; + + display-timings { + OKAYA-WVGA { + clock-frequency = <30066000>; + hactive = <800>; + vactive = <480>; + hfront-porch = <50>; + hback-porch = <70>; + hsync-len = <50>; + vback-porch = <2>; + vfront-porch = <2>; + vsync-len = <50>; + + de-active = <1>; + pixelclk-active = <1>; + }; + }; + + port@0 { + lcd_display_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&lcd_display_in>; +}; + +&touch_spi { + status = "okay"; +}; + +&usdhc1 { + status = "okay"; +}; + +®_wlan_vqmmc { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-ts7990-lxd-revb.dts b/arch/arm/boot/dts/nxp/imx/imx6q-ts7990-lxd-revb.dts new file mode 100644 index 0000000000000..85cd3b25bcc33 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-ts7990-lxd-revb.dts @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright 2017-2022 Technologic Systems, Inc. dba embeddedTS + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-ts7990.dtsi" + +/ { + model = "embeddedTS i.MX6 Quad TS-7990 (LXD) REV B"; + compatible = "fsl,imx6q-ts7990", "fsl,imx6q"; + + lcd_lvds0: disp0 { + compatible = "panel-lvds"; + backlight = <&backlight0>; + width-mm = <15>; + height-mm = <9>; + data-mapping = "vesa-24"; + + panel-timing { + clock-frequency = <51200000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <46>; + hfront-porch = <210>; + vback-porch = <23>; + vfront-porch = <12>; + hsync-len = <20>; + vsync-len = <10>; + de-active = <1>; + hsync-active = <1>; + vsync-active = <1>; + pixelclk-active = <0>; + }; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&pixcir_tangoc { + status = "okay"; +}; + +&ecspi5 { + num-cs = <1>; + cs-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi5>; + status = "okay"; + + wilc3000: wifi@0 { + compatible = "microchip,wilc3000"; + reg = <0>; + spi-max-frequency = <18000000>; + reset-gpios = <&gpio8 13 GPIO_ACTIVE_HIGH>; + chip_en-gpios = <&gpio8 14 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio1>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + imx6-ts7990 { + pinctrl_ecspi5: ecspi5 { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x1b0b0 + MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x1b0b0 + MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x1b0b0 + MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b088 /* SPI_1_CS# */ + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b088 /* WIFI_IRQ# */ + >; + }; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + + status = "okay"; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-ts7990-lxd.dts b/arch/arm/boot/dts/nxp/imx/imx6q-ts7990-lxd.dts new file mode 100644 index 0000000000000..d0887232d77f2 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-ts7990-lxd.dts @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright 2017-2022 Technologic Systems, Inc. dba embeddedTS + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-ts7990.dtsi" + +/ { + model = "embeddedTS i.MX6 Quad TS-7990 (LXD)"; + compatible = "fsl,imx6q-ts7990", "fsl,imx6q"; + + lcd_lvds0: disp0 { + compatible = "panel-lvds"; + backlight = <&backlight0>; + width-mm = <15>; + height-mm = <9>; + data-mapping = "vesa-24"; + + panel-timing { + clock-frequency = <51200000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <46>; + hfront-porch = <210>; + vback-porch = <23>; + vfront-porch = <12>; + hsync-len = <20>; + vsync-len = <10>; + de-active = <1>; + hsync-active = <1>; + vsync-active = <1>; + pixelclk-active = <0>; + }; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&pixcir_tangoc { + status = "okay"; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + + status = "okay"; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&sata { + status = "okay"; +}; + +&usdhc1 { + status = "okay"; +}; + +®_wlan_vqmmc { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-ts7990-microtips-revb.dts b/arch/arm/boot/dts/nxp/imx/imx6q-ts7990-microtips-revb.dts new file mode 100644 index 0000000000000..cbbc32da86732 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-ts7990-microtips-revb.dts @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright 2017-2022 Technologic Systems, Inc. dba embeddedTS + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-ts7990.dtsi" + +/ { + model = "embeddedTS i.MX6 Quad TS-7990 (Microtips)"; + compatible = "fsl,imx6q-ts7990", "fsl,imx6q"; + + lcd_display: disp0 { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu>; + + display-timings { + MICROTIPS-WVGA { + clock-frequency = <30030000>; + hactive = <800>; + vactive = <480>; + hfront-porch = <46>; + hback-porch = <210>; + hsync-len = <1>; + vback-porch = <22>; + vfront-porch = <23>; + vsync-len = <1>; + + de-active = <1>; + pixelclk-active = <1>; + }; + }; + + port@0 { + lcd_display_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + }; +}; + +&ecspi5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi5>; + num-cs = <1>; + cs-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; + status = "okay"; + + wilc3000: wifi@0 { + compatible = "microchip,wilc3000"; + reg = <0>; + spi-max-frequency = <18000000>; + reset-gpios = <&gpio8 13 GPIO_ACTIVE_HIGH>; + chip_en-gpios = <&gpio8 14 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio1>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&iomuxc { + imx6-ts7990 { + pinctrl_ecspi5: ecspi5grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x100b1 + MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x100b1 + MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x100b1 + MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b088 /* SPI_1_CS# */ + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b088 /* WIFI_IRQ# */ + /* XXX: Add chip-en and reset GPIOS */ + >; + }; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&lcd_display_in>; +}; + +&sata { + status = "okay"; +}; + +&touch_spi { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-ts7990-microtips.dts b/arch/arm/boot/dts/nxp/imx/imx6q-ts7990-microtips.dts new file mode 100644 index 0000000000000..28c40cbd4681a --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-ts7990-microtips.dts @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright 2017-2022 Technologic Systems, Inc. dba embeddedTS + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-ts7990.dtsi" + +/ { + model = "embeddedTS i.MX6 Quad TS-7990 (Microtips)"; + compatible = "fsl,imx6q-ts7990", "fsl,imx6q"; + + lcd_display: disp0 { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu>; + + display-timings { + MICROTIPS-WVGA { + clock-frequency = <30030000>; + hactive = <800>; + vactive = <480>; + hfront-porch = <46>; + hback-porch = <210>; + hsync-len = <1>; + vback-porch = <22>; + vfront-porch = <23>; + vsync-len = <1>; + + de-active = <1>; + pixelclk-active = <1>; + }; + }; + + port@0 { + lcd_display_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&lcd_display_in>; +}; + +&sata { + status = "okay"; +}; + +&touch_spi { + status = "okay"; +}; + +&usdhc1 { + status = "okay"; +}; + +®_wlan_vqmmc { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-ts7990-okaya-revb.dts b/arch/arm/boot/dts/nxp/imx/imx6q-ts7990-okaya-revb.dts new file mode 100644 index 0000000000000..05263d9335541 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-ts7990-okaya-revb.dts @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright 2017-2022 Technologic Systems, Inc. dba embeddedTS + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-ts7990.dtsi" + +/ { + model = "embeddedTS i.MX6 Quad TS-7990 (Okaya)"; + compatible = "fsl,imx6q-ts7990", "fsl,imx6q"; + + lcd_display: disp0 { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu>; + + display-timings { + OKAYA-WVGA { + clock-frequency = <30066000>; + hactive = <800>; + vactive = <480>; + hfront-porch = <50>; + hback-porch = <70>; + hsync-len = <50>; + vback-porch = <2>; + vfront-porch = <2>; + vsync-len = <50>; + + de-active = <1>; + pixelclk-active = <1>; + }; + }; + + port@0 { + lcd_display_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + }; +}; + +&ecspi5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi5>; + num-cs = <1>; + cs-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; + status = "okay"; + + wilc3000: wifi@0 { + compatible = "microchip,wilc3000"; + reg = <0>; + spi-max-frequency = <18000000>; + reset-gpios = <&gpio8 13 GPIO_ACTIVE_HIGH>; + chip_en-gpios = <&gpio8 14 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio1>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&iomuxc { + imx6-ts7990 { + pinctrl_ecspi5: ecspi5grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x100b1 + MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x100b1 + MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x100b1 + MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b088 /* SPI_1_CS# */ + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b088 /* WIFI_IRQ# */ + /* XXX: Add chip-en and reset GPIOS */ + >; + }; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&lcd_display_in>; +}; + +&sata { + status = "okay"; +}; + +&touch_spi { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-ts7990-okaya.dts b/arch/arm/boot/dts/nxp/imx/imx6q-ts7990-okaya.dts new file mode 100644 index 0000000000000..95eda930adac3 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-ts7990-okaya.dts @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright 2017-2022 Technologic Systems, Inc. dba embeddedTS + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-ts7990.dtsi" + +/ { + model = "embeddedTS i.MX6 Quad TS-7990 (Okaya)"; + compatible = "fsl,imx6q-ts7990", "fsl,imx6q"; + + lcd_display: disp0 { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu>; + + display-timings { + OKAYA-WVGA { + clock-frequency = <30066000>; + hactive = <800>; + vactive = <480>; + hfront-porch = <50>; + hback-porch = <70>; + hsync-len = <50>; + vback-porch = <2>; + vfront-porch = <2>; + vsync-len = <50>; + + de-active = <1>; + pixelclk-active = <1>; + }; + }; + + port@0 { + lcd_display_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&lcd_display_in>; +}; + +&sata { + status = "okay"; +}; + +&touch_spi { + status = "okay"; +}; + +&usdhc1 { + status = "okay"; +}; + +®_wlan_vqmmc { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7990.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7990.dtsi new file mode 100644 index 0000000000000..e6dbd0698e7e6 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7990.dtsi @@ -0,0 +1,724 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright 2017-2022 Technologic Systems, Inc. dba embeddedTS + */ + +#include +#include +#include + +/ { + chosen { + stdout-path = &uart1; + }; + + aliases { + ethernet0 = &fec; + }; + + backlight0: backlight { + compatible = "pwm-backlight"; + power-supply = <®_backlight>; + pwms = <&pwm3 0 5000000 0>; + brightness-levels = <0 100>; + num-interpolated-steps = <100>; + default-brightness-level = <100>; + }; + + led-controller { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds1>; + compatible = "gpio-leds"; + + led-0 { + color = ; + function = LED_FUNCTION_POWER; + gpios = <&gpio5 21 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + led-1 { + color = ; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + + reg_backlight: regulator-backlight { + compatible = "regulator-fixed"; + regulator-name = "BACKLIGHT_LCD"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bkl>; + regulator-min-microvolt = <28000000>; + regulator-max-microvolt = <28000000>; + startup-delay-us = <2000>; + gpio = <&gpio3 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_1v2: regulator-1v2 { + compatible = "regulator-fixed"; + regulator-name = "1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_can_3v3: regulator-can-en { + compatible = "regulator-fixed"; + regulator-name = "CAN_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio6 31 GPIO_ACTIVE_HIGH>; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "USB_OTG_VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_wlan_vqmmc: regulator-wlan-vqmmc { + compatible = "regulator-fixed"; + regulator-name = "WLAN_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio8 14 GPIO_ACTIVE_HIGH>; + startup-delay-us = <100000>; + enable-active-high; + status = "disabled"; + }; + + sound { + audio-codec = <&sgtl5000>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + compatible = "fsl,imx-audio-sgtl5000"; + model = "On-board Codec"; + mux-ext-port = <3>; + mux-int-port = <1>; + ssi-controller = <&ssi1>; + }; + + touch_spi: spi { + compatible = "spi-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch_spi>; + gpio-sck = <&gpio2 20 GPIO_ACTIVE_HIGH>; + gpio-mosi = <&gpio2 18 GPIO_ACTIVE_HIGH>; + gpio-miso = <&gpio2 17 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio2 19 GPIO_ACTIVE_LOW>; + num-chipselects = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + tsc2046: touchscreen@0 { + compatible = "ti,tsc2046"; + reg = <0>; + /* Interrupt configured by GPIO hog, shared with cap touch */ + interrupt-parent = <&gpio3>; + interrupts = <12 IRQ_TYPE_EDGE_FALLING>; + vcc-supply = <®_3v3>; + spi-max-frequency = <100000>; + pendown-gpio = <&gpio3 12 0>; + ti,penirq-recheck-delay-usecs = /bits/ 16 <5000>; + ti,vref-mv = <3300>; + ti,swap-xy; + ti,keep-vref-on; + ti,settle-delay-usec = /bits/ 16 <5000>; + ti,vref-delay-usecs = /bits/ 16 <0>; + ti,x-plate-ohms = /bits/ 16 <400>; + ti,y-plate-ohms = /bits/ 16 <400>; + ti,debounce-rep = /bits/ 16 <2>; + ti,debounce-tol = /bits/ 16 <65535>; + ti,debounce-max = /bits/ 16 <0>; + ti,pressure-max = /bits/ 16 <15000>; + ti,pendown-gpio-debounce = <10000>; + linux,wakeup; + }; + }; +}; + +&audmux { + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_3v3>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_3v3>; + status = "okay"; +}; + + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + spiboot: flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&ecspi2 { + num-cs = <3>; + cs-gpios = < + &gpio5 31 GPIO_ACTIVE_LOW + &gpio1 6 GPIO_ACTIVE_LOW + &gpio8 7 GPIO_ACTIVE_LOW + >; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + status = "okay"; + + max3100ts: serial@0 { + compatible = "technologic,max3100-ts"; + reg = <0>; + interrupt-parent = <&gpio5>; + interrupts = <20 IRQ_TYPE_LEVEL_LOW>; + spi-max-frequency = <10000000>; + loopback = <0>; + crystal = <1>; + poll-time = <100>; + }; + + spidevfpga: spidev@1 { + compatible = "spidev"; + reg = <1>; + spi-max-frequency = <1000000>; + }; + + spidevdc1: spidev@2 { + compatible = "spidev"; + reg = <2>; + spi-max-frequency = <1000000>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + status = "okay"; +}; + +&gpio1 { + gpio-line-names = "", "", "", "", "", "", "", "", "", "TOUCH_RESET", + "", "", "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = "", "", "", "", "PCIE_RESET#", "", "", "", "", "", "", + "USB_HUB_RESET#", "", "", "", "", "", "", "", "", "", "", + "EN_USB_5V", "", "", "JP_OPTION#", "JP_SD_BOOT#", "", "", + "EN_800_NIT"; +}; + +&gpio3 { + gpio-line-names = "", "", "", "", "5V_REG_PWM_MODE", "EN_HUB_3.3V", "", + "", "", "PUSH_SW_1#", "PUSH_SW_2#", "POE_DETECT#", "", "", "", + "", "", "", "", "", "", "", "", "EN_EMMC_3.3V#"; +}; + +&gpio4 { + gpio-line-names = "", "", "", "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "EN_232_TRANS"; +}; + +&gpio5 { + gpio-line-names = "", "", "", "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "EN_NIM_USB#", "", "", "", "", "", "", "", + "", "", "", "", "NIM_PWR_ON"; +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + + pixcir_tangoc: touchscreen@5c { + compatible = "pixcir,pixcir_tangoc"; + reg = <0x5c>; + /* Interrupt configured by GPIO hog, shared with res touch */ + interrupt-parent = <&gpio3>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + attb-gpio = <&gpio3 12 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + touchscreen-size-x = <1024>; + touchscreen-size-y = <600>; + /* + * The actual interrupt pin logic is inverted from touchscreen + * INT output pin on the TS-TPC-7990. Indicate that we want the + * touchscreen to drive active high, but the CPU interrupt will + * actually be active low. + */ + invert-int-output; + wakeup-source; + status = "disabled"; + }; + + m41t00s: rtc@68 { + compatible = "m41t00"; + reg = <0x68>; + }; + + sgtl5000: audio-codec@a { + compatible = "fsl,sgtl5000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sgtl5000>; + reg = <0x0a>; + clocks = <&clks 201>; + VDDA-supply = <®_3v3>; + VDDIO-supply = <®_3v3>; + VDDD-supply = <®_1v2>; + }; + + mma8451: accelerometer@1c { + compatible = "fsl,mma8451"; + reg = <0x1c>; + vdd-supply = <®_3v3>; + vddio-supply = <®_3v3>; + interrupt-parent = <&gpio2>; + interrupts = <23 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "INT1"; + /* INT2 is connected to CPU but is unused */ + }; + + gpio8: gpio@28 { + compatible = "technologic,ts7970-gpio"; + reg = <0x28>; + #gpio-cells = <2>; + gpio-controller; + ngpios = <64>; + base = <224>; + + gpio-line-names = "", "", "", "", "", "", "DIO_8", "DIO_9", "", + "", "", "", "", "BT_EN", "WL_EN", "", "", "", "", "", + "DIO_1_SEL0", "DIO_2_SEL1", "DIO_3_SEL2", "DIO_4_PWM", + "DIO_5_SILAB_DATA", "DIO_6_POWER_FAIL", "DIO_7", "IRQ1", + "", "", "REBOOT", "", "", "", "", "", "", "", "", "", + "", "", "", "", "TTYMAX0_RXD", "TTYMAX1_RXD", + "TTYMAX2_RXD", "TXEN3_485", "COM1_TXD", "COM2_TXD", + "COM3_TXD", "", "COM1_RTS", "TTYMAX0_CTS", + "TTYMAX1_CTS", "TTYMAX2_CTS", "", "", "", "", + "MT_LCD_PRESENT", "EN_SPKR"; + + en-spkr-hog { + gpio-hog; + gpios = <61 GPIO_ACTIVE_HIGH>; + line-name = "EN_SPKR"; + output-high; + }; + }; +}; + +&i2c2 { + status = "okay"; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx6-ts7990 { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x100b1 /* Onboard flash CS1# */ + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1 /* FPGA_SPI_CLK */ + MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 /* FPGA_SPI_MOSI */ + MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1 /* FPGA_SPI_MISO */ + MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x1b088 /* FPGA_SPI_CS0# */ + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b088 /* FPGA_IRQ_0 */ + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b088 /* FPGA_IRQ_1 */ + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b088 /* FPGA_IRQ_2 */ + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b088 /* FPGA_SPI_CS1# */ + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b088 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b088 + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b088 /* ETH_PHY_RESET */ + >; + }; + + pinctrl_bkl: bklreggrp { + fsl,pins = < + MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b088 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b088 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b088 + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b088 /* EN_CAN# */ + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b088 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b088 + >; + }; + + pinctrl_ipu: tsipugrp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x38 /* LCD_PIX_CLK */ + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xf0 /* LCD_DE */ + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xe0 /* LCD_D02 */ + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xe0 /* LCD_D03 */ + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xe0 /* LCD_D04 */ + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xe0 /* LCD_D05 */ + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xe0 /* LCD_D06 */ + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xe0 /* LCD_D07 */ + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xe0 /* LCD_D10 */ + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xe0 /* LCD_D11 */ + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xe0 /* LCD_D12 */ + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xe0 /* LCD_D13 */ + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xe0 /* LCD_D14 */ + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xe0 /* LCD_D15 */ + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0xe0 /* LCD_D18 */ + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0xe0 /* LCD_D19 */ + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0xe0 /* LCD_D20 */ + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0xe0 /* LCD_D21 */ + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0xe0 /* LCD_D22 */ + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0xe0 /* LCD_D23 */ + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x17059 /* ACCEL_INT */ + MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x17059 /* ACCEL_2_INT */ + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x88 /* TOUCH_RESET */ + >; + }; + + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b088 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b088 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x1b088 + MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x1b088 + MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b088 + MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b088 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b088 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b088 + MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x1b088 + MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x1b088 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b088 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b088 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b088 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b088 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1f0d9 /* WIFI IRQ */ + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x88 /* EN_EMMC_3.3V# */ + >; + }; + + pinctrl_leds1: leds1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b088 /* RED_LED# */ + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b088 /* GREEN_LED# */ + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b088 /* PCIE_RESET# */ + >; + }; + + pinctrl_sgtl5000: sgtl5000grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* Audio CLK */ + >; + }; + + pinctrl_touch_spi: touchspigrp { + fsl,pins = < + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x100b1 /* TOUCH_SPI_CLK */ + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x180b1 /* TOUCH_SPI_CS# */ + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x100b1 /* TOUCH_SPI_MOSI */ + MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x100b1 /* TOUCH_SPI_MISO */ + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x10 /* FPGA_24MHZ */ + MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x1b088 /* TOUCH_IRQ */ + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b088 /* USB_HUB_RESET# */ + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1b088 /* JTAG_FPGA_TCK */ + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b088 /* JTAG_FPGA_TDI */ + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b088 /* JTAG_FPGA_TMS */ + MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b088 /* JTAG_FPGA_TDO */ + MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b088 /* EN_232_TRANS */ + MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x1b088 /* JP_OPTION# */ + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b088 /* JP_SD_BOOT# */ + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b088 /* EN_USB_5V */ + MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b088 /* EN_800_NIT */ + MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b088 /* 5V_REG_PWM_MODE */ + MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b088 /* EN_HUB_3.3V */ + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1b088 /* PUSH_SW_1# */ + MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x1b088 /* PUSH_SW_2# */ + MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b088 /* REVB_STRAP */ + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b088 /* EN_NIM_USB# */ + MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x1b088 /* NIM_PWR_ON */ + >; + }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + status = "okay"; + reset-gpio = <&gpio2 4 GPIO_ACTIVE_LOW>; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&snvs_rtc { + status = "disabled"; +}; + +&ssi1 { + status = "okay"; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; +}; + +&uart2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; +}; + +&uart4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; +}; + +&uart5 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { /* Wifi */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + vqmmc-supply = <®_wlan_vqmmc>; + bus-width = <4>; + non-removable; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + wl1271: wifi@2 { + compatible = "ti,wl1271"; + reg = <2>; + status = "disabled"; + interrupt-parent = <&gpio1>; + interrupts = <26 IRQ_TYPE_LEVEL_HIGH>; + ref-clock-frequency = <38400000>; + }; +}; + +&usdhc2 { /* SD */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + vmmc-supply = <®_3v3>; + vqmmc-supply = <®_3v3>; + bus-width = <4>; + fsl,wp-controller; + status = "okay"; +}; + +&usdhc3 { /* eMMC */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + vmmc-supply = <®_3v3>; + vqmmc-supply = <®_3v3>; + bus-width = <4>; + non-removable; + no-1-8-v; + status = "okay"; +}; From 4f12db569fb5af884aa05a8e492acdc58eb3484c Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Tue, 12 Mar 2019 17:03:28 -0700 Subject: [PATCH 024/244] video: fbdev: st7565p: Add kernel driver half for SPI LCD [ commit 2121d7fae0f621109d24febd52841abe324fe874 in 4.9.y ] Bring in support for st7565p LCD using the driver shim and userspace companion tool. Signed-off-by: Kris Bahnsen --- drivers/video/fbdev/Kconfig | 16 + drivers/video/fbdev/Makefile | 1 + drivers/video/fbdev/ts-st7565p-fb.c | 561 ++++++++++++++++++++++++++++ 3 files changed, 578 insertions(+) create mode 100644 drivers/video/fbdev/ts-st7565p-fb.c diff --git a/drivers/video/fbdev/Kconfig b/drivers/video/fbdev/Kconfig index a257b739188d6..148896a75c877 100644 --- a/drivers/video/fbdev/Kconfig +++ b/drivers/video/fbdev/Kconfig @@ -1797,6 +1797,22 @@ config FB_SIMPLE Configuration re: surface address, size, and format must be provided through device tree, or plain old platform data. +config FB_ST7565P + tristate "ST7565P Virtual Frame Buffer support" + depends on FB + select FB_SYS_FILLRECT + select FB_SYS_COPYAREA + select FB_SYS_IMAGEBLIT + select FB_SYS_FOPS + help + This is a `virtual' frame buffer device specifically for the + ST7565P LCD display device when attached to a + Technologic Systems TS-7553-V2 + board. + + This driver also requires a userspace program ("lcd-helper") to communicate + with the ST7565P via SPI. + config FB_SSD1307 tristate "Solomon SSD1307 framebuffer support" depends on FB && I2C diff --git a/drivers/video/fbdev/Makefile b/drivers/video/fbdev/Makefile index b3d12f977c06b..485b881aca391 100644 --- a/drivers/video/fbdev/Makefile +++ b/drivers/video/fbdev/Makefile @@ -123,6 +123,7 @@ obj-$(CONFIG_FB_VGA16) += vga16fb.o obj-$(CONFIG_FB_OF) += offb.o obj-$(CONFIG_FB_SSD1307) += ssd1307fb.o obj-$(CONFIG_FB_SIMPLE) += simplefb.o +obj-$(CONFIG_FB_ST7565P) += ts-st7565p-fb.o # the test framebuffer is last obj-$(CONFIG_FB_VIRTUAL) += vfb.o diff --git a/drivers/video/fbdev/ts-st7565p-fb.c b/drivers/video/fbdev/ts-st7565p-fb.c new file mode 100644 index 0000000000000..f6a391f297a89 --- /dev/null +++ b/drivers/video/fbdev/ts-st7565p-fb.c @@ -0,0 +1,561 @@ +/* + * linux/drivers/video/ts-st7565p-.c -- Virtual frame buffer device for + * the Technologic Systems 4600 with attached ST7565P LCD display + * + * This driver is based on the vfb.c file. + * + * Copyright (C) 2002 James Simmons + * + * Copyright (C) 1997 Geert Uytterhoeven + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive for + * more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + + /* + * RAM we reserve for the frame buffer. This defines the maximum screen + * size + * + * The default can be overridden if the driver is compiled as a module + */ +#define VIDEOMEMSIZE 4096 +static void *videomemory; +static u_long videomemorysize = VIDEOMEMSIZE; +module_param(videomemorysize, ulong, 0); + +/********************************************************************** + * + * Memory management + * + **********************************************************************/ +static void *rvmalloc(unsigned long size) +{ + void *mem; + unsigned long adr; + + size = PAGE_ALIGN(size); + mem = vmalloc_32(size); + if (!mem) + return NULL; + + memset(mem, 0, size); /* Clear the ram out, no junk to the user */ + adr = (unsigned long) mem; + while (size > 0) { + SetPageReserved(vmalloc_to_page((void *)adr)); + adr += PAGE_SIZE; + size -= PAGE_SIZE; + } + + return mem; +} + +static void rvfree(void *mem, unsigned long size) +{ + unsigned long adr; + + if (!mem) + return; + + adr = (unsigned long) mem; + while ((long) size > 0) { + ClearPageReserved(vmalloc_to_page((void *)adr)); + adr += PAGE_SIZE; + size -= PAGE_SIZE; + } + vfree(mem); +} + + +static struct fb_var_screeninfo st7565p_default __initdata = { + .xres = 128, + .yres = 64, + .xres_virtual = 128, + .yres_virtual = 64, + .bits_per_pixel = 1, + .red = { 0, 1, 0 }, + .green = { 0, 1, 0 }, + .blue = { 0, 1, 0 }, + .activate = FB_ACTIVATE_TEST, + .height = -1, + .width = -1, + .pixclock = 3800000, + .left_margin = 0, + .right_margin = 0, + .upper_margin = 0, + .lower_margin = 0, + .hsync_len = 1, + .vsync_len = 1, + .vmode = FB_VMODE_NONINTERLACED, +}; + +static struct fb_fix_screeninfo st7565p_fix __initdata = { + .id = "ST7565P FB", + .type = FB_TYPE_PACKED_PIXELS, + .visual = FB_VISUAL_PSEUDOCOLOR, + .xpanstep = 1, + .ypanstep = 1, + .ywrapstep = 1, + .accel = FB_ACCEL_NONE, + .line_length = 16 +}; + +static int st7565p_check_var(struct fb_var_screeninfo *var, + struct fb_info *info); +static int st7565p_set_par(struct fb_info *info); +static int st7565p_setcolreg(u_int regno, u_int red, u_int green, u_int blue, + u_int transp, struct fb_info *info); +static int st7565p_mmap(struct fb_info *info, + struct vm_area_struct *vma); + +static struct fb_ops st7565p_ops = { + .fb_read = fb_sys_read, + .fb_write = fb_sys_write, + .fb_check_var = st7565p_check_var, + .fb_set_par = st7565p_set_par, + .fb_setcolreg = st7565p_setcolreg, + .fb_fillrect = sys_fillrect, + .fb_copyarea = sys_copyarea, + .fb_imageblit = sys_imageblit, + .fb_mmap = st7565p_mmap, +}; + + /* + * Internal routines + */ + +static u_long get_line_length(int xres_virtual, int bpp) +{ + u_long length; + + length = xres_virtual * bpp; + length = (length + 31) & ~31; + length >>= 3; + + return (length); +} + + /* + * Setting the video mode has been split into two parts. + * First part, xxxfb_check_var, must not write anything + * to hardware, it should only verify and adjust var. + * This means it doesn't alter par but it does use hardware + * data from it to check this var. + */ + +static int st7565p_check_var(struct fb_var_screeninfo *var, + struct fb_info *info) +{ + u_long line_length; + + /* + * FB_VMODE_CONUPDATE and FB_VMODE_SMOOTH_XPAN are equal! + * as FB_VMODE_SMOOTH_XPAN is only used internally + */ + + if (var->vmode & FB_VMODE_CONUPDATE) { + var->vmode |= FB_VMODE_YWRAP; + var->xoffset = info->var.xoffset; + var->yoffset = info->var.yoffset; + } + + /* + * Some very basic checks + */ + if (!var->xres) + var->xres = 1; + if (!var->yres) + var->yres = 1; + if (var->xres > var->xres_virtual) + var->xres_virtual = var->xres; + if (var->yres > var->yres_virtual) + var->yres_virtual = var->yres; + if (var->bits_per_pixel <= 1) + var->bits_per_pixel = 1; + else if (var->bits_per_pixel <= 8) + var->bits_per_pixel = 8; + else if (var->bits_per_pixel <= 16) + var->bits_per_pixel = 16; + else if (var->bits_per_pixel <= 24) + var->bits_per_pixel = 24; + else if (var->bits_per_pixel <= 32) + var->bits_per_pixel = 32; + else + return -EINVAL; + + if (var->xres_virtual < var->xoffset + var->xres) + var->xres_virtual = var->xoffset + var->xres; + if (var->yres_virtual < var->yoffset + var->yres) + var->yres_virtual = var->yoffset + var->yres; + + /* + * Memory limit + */ + line_length = + get_line_length(var->xres_virtual, var->bits_per_pixel); + if (line_length * var->yres_virtual > videomemorysize) + return -ENOMEM; + + /* + * Now that we checked it we alter var. The reason being is that the video + * mode passed in might not work but slight changes to it might make it + * work. This way we let the user know what is acceptable. + */ + switch (var->bits_per_pixel) { + case 1: + case 8: + var->red.offset = 0; + var->red.length = 8; + var->green.offset = 0; + var->green.length = 8; + var->blue.offset = 0; + var->blue.length = 8; + var->transp.offset = 0; + var->transp.length = 0; + break; + case 16: /* RGBA 5551 */ + if (var->transp.length) { + var->red.offset = 0; + var->red.length = 5; + var->green.offset = 5; + var->green.length = 5; + var->blue.offset = 10; + var->blue.length = 5; + var->transp.offset = 15; + var->transp.length = 1; + } else { /* RGB 565 */ + var->red.offset = 0; + var->red.length = 5; + var->green.offset = 5; + var->green.length = 6; + var->blue.offset = 11; + var->blue.length = 5; + var->transp.offset = 0; + var->transp.length = 0; + } + break; + case 24: /* RGB 888 */ + var->red.offset = 0; + var->red.length = 8; + var->green.offset = 8; + var->green.length = 8; + var->blue.offset = 16; + var->blue.length = 8; + var->transp.offset = 0; + var->transp.length = 0; + break; + case 32: /* RGBA 8888 */ + var->red.offset = 0; + var->red.length = 8; + var->green.offset = 8; + var->green.length = 8; + var->blue.offset = 16; + var->blue.length = 8; + var->transp.offset = 24; + var->transp.length = 8; + break; + } + var->red.msb_right = 0; + var->green.msb_right = 0; + var->blue.msb_right = 0; + var->transp.msb_right = 0; + + return 0; +} + +/* This routine actually sets the video mode. It's in here where we + * the hardware state info->par and fix which can be affected by the + * change in par. For this driver it doesn't do much. + */ +static int st7565p_set_par(struct fb_info *info) +{ + info->fix.line_length = get_line_length(info->var.xres_virtual, + info->var.bits_per_pixel); + + return 0; +} + + /* + * Set a single color register. The values supplied are already + * rounded down to the hardware's capabilities (according to the + * entries in the var structure). Return != 0 for invalid regno. + */ + +static int st7565p_setcolreg(u_int regno, u_int red, u_int green, u_int blue, + u_int transp, struct fb_info *info) +{ + if (regno >= 256) /* no. of hw registers */ + return 1; + /* + * Program hardware... do anything you want with transp + */ + + /* grayscale works only partially under directcolor */ + if (info->var.grayscale) { + /* grayscale = 0.30*R + 0.59*G + 0.11*B */ + red = green = blue = + (red * 77 + green * 151 + blue * 28) >> 8; + } + + /* Directcolor: + * var->{color}.offset contains start of bitfield + * var->{color}.length contains length of bitfield + * {hardwarespecific} contains width of RAMDAC + * cmap[X] is programmed to (X << red.offset) | (X << green.offset) | (X << blue.offset) + * RAMDAC[X] is programmed to (red, green, blue) + * + * Pseudocolor: + * uses offset = 0 && length = RAMDAC register width. + * var->{color}.offset is 0 + * var->{color}.length contains widht of DAC + * cmap is not used + * RAMDAC[X] is programmed to (red, green, blue) + * Truecolor: + * does not use DAC. Usually 3 are present. + * var->{color}.offset contains start of bitfield + * var->{color}.length contains length of bitfield + * cmap is programmed to (red << red.offset) | (green << green.offset) | + * (blue << blue.offset) | (transp << transp.offset) + * RAMDAC does not exist + */ +#define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16) + switch (info->fix.visual) { + case FB_VISUAL_TRUECOLOR: + case FB_VISUAL_PSEUDOCOLOR: + red = CNVT_TOHW(red, info->var.red.length); + green = CNVT_TOHW(green, info->var.green.length); + blue = CNVT_TOHW(blue, info->var.blue.length); + transp = CNVT_TOHW(transp, info->var.transp.length); + break; + case FB_VISUAL_DIRECTCOLOR: + red = CNVT_TOHW(red, 8); /* expect 8 bit DAC */ + green = CNVT_TOHW(green, 8); + blue = CNVT_TOHW(blue, 8); + /* hey, there is bug in transp handling... */ + transp = CNVT_TOHW(transp, 8); + break; + } +#undef CNVT_TOHW + /* Truecolor has hardware independent palette */ + if (info->fix.visual == FB_VISUAL_TRUECOLOR) { + u32 v; + + if (regno >= 16) + return 1; + + v = (red << info->var.red.offset) | + (green << info->var.green.offset) | + (blue << info->var.blue.offset) | + (transp << info->var.transp.offset); + switch (info->var.bits_per_pixel) { + case 8: + break; + case 16: + ((u32 *) (info->pseudo_palette))[regno] = v; + break; + case 24: + case 32: + ((u32 *) (info->pseudo_palette))[regno] = v; + break; + } + return 0; + } + return 0; +} + + /* + * Most drivers don't need their own mmap function + */ + +static int st7565p_mmap(struct fb_info *info, + struct vm_area_struct *vma) +{ + unsigned long start = vma->vm_start; + unsigned long size = vma->vm_end - vma->vm_start; + unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; + unsigned long page, pos; + + if (offset + size > info->fix.smem_len) { + return -EINVAL; + } + + pos = (unsigned long)info->fix.smem_start + offset; + + while (size > 0) { + page = vmalloc_to_pfn((void *)pos); + if (remap_pfn_range(vma, start, page, PAGE_SIZE, PAGE_SHARED)) { + return -EAGAIN; + } + start += PAGE_SIZE; + pos += PAGE_SIZE; + if (size > PAGE_SIZE) + size -= PAGE_SIZE; + else + size = 0; + } + + vma->vm_flags |= (VM_DONTEXPAND | VM_DONTDUMP); /* avoid to swap out this VMA */ + return 0; + +} + +#ifndef MODULE +static int __init st7565p_setup(char *options) +{ + char *this_opt; + + if (!options || !*options) + return 1; + + while ((this_opt = strsep(&options, ",")) != NULL) { + if (!*this_opt) + continue; + } + return 1; +} +#endif /* MODULE */ + + /* + * Initialisation + */ + +static int __init st7565p_probe(struct platform_device *dev) +{ + struct fb_info *info; + int retval = -ENOMEM; + + /* + * For real video cards we use ioremap. + */ + if (!(videomemory = rvmalloc(videomemorysize))) + return retval; + + /* + * ST7565P must clear memory to prevent kernel info + * leakage into userspace + * VGA-based drivers MUST NOT clear memory if + * they want to be able to take over vgacon + */ + memset(videomemory, 0, videomemorysize); + + info = framebuffer_alloc(sizeof(u32) * 256, &dev->dev); + if (!info) + goto err; + + info->screen_base = (char __iomem *)videomemory; + info->fbops = &st7565p_ops; + + retval = fb_find_mode(&info->var, info, NULL, + NULL, 0, NULL, 8); + + if (!retval || (retval == 4)) + info->var = st7565p_default; + st7565p_fix.smem_start = (unsigned long) videomemory; + st7565p_fix.smem_len = videomemorysize; + info->fix = st7565p_fix; + info->pseudo_palette = info->par; + info->par = NULL; + info->flags = FBINFO_FLAG_DEFAULT; + + retval = fb_alloc_cmap(&info->cmap, 256, 0); + if (retval < 0) + goto err1; + + retval = register_framebuffer(info); + if (retval < 0) + goto err2; + platform_set_drvdata(dev, info); + + printk(KERN_INFO + "fb%d: Virtual frame buffer device, using %ldK of video memory\n", + info->node, videomemorysize >> 10); + return 0; +err2: + fb_dealloc_cmap(&info->cmap); +err1: + framebuffer_release(info); +err: + rvfree(videomemory, videomemorysize); + return retval; +} + +static int st7565p_remove(struct platform_device *dev) +{ + struct fb_info *info = platform_get_drvdata(dev); + + if (info) { + unregister_framebuffer(info); + rvfree(videomemory, videomemorysize); + framebuffer_release(info); + } + return 0; +} + +static struct platform_driver st7565p_driver = { + .probe = st7565p_probe, + .remove = st7565p_remove, + .driver = { + .name = "st7565p", + }, +}; + +static struct platform_device *st7565p_device; + +static int __init st7565p_init(void) +{ + int ret = 0; + +#ifndef MODULE + char *option = NULL; + + if (fb_get_options("st7565p", &option)) + return -ENODEV; + st7565p_setup(option); +#endif + + ret = platform_driver_register(&st7565p_driver); + + if (!ret) { + st7565p_device = platform_device_alloc("st7565p", 0); + + if (st7565p_device) + ret = platform_device_add(st7565p_device); + else + ret = -ENOMEM; + + if (ret) { + platform_device_put(st7565p_device); + platform_driver_unregister(&st7565p_driver); + } + } + + return ret; +} + +module_init(st7565p_init); + +#ifdef MODULE +static void __exit st7565p_exit(void) +{ + platform_device_unregister(st7565p_device); + platform_driver_unregister(&st7565p_driver); +} + +module_exit(st7565p_exit); + +MODULE_LICENSE("GPL"); +#endif /* MODULE */ From 3f2fb45f37f91895fdfb4a5f1d31e6bd9d075f28 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Tue, 8 Mar 2022 13:42:55 -0800 Subject: [PATCH 025/244] ARM: dts: imx6ul: Add TS-7553-V2 support Add initial support of the i.MX6UL based TS-7553-V2 platform. Signed-off-by: Kris Bahnsen --- arch/arm/boot/dts/nxp/imx/Makefile | 1 + arch/arm/boot/dts/nxp/imx/imx6ul-ts7553v2.dts | 692 ++++++++++++++++++ 2 files changed, 693 insertions(+) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-ts7553v2.dts diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx/Makefile index 1262dbd3ba95c..7602bb65d7c5d 100644 --- a/arch/arm/boot/dts/nxp/imx/Makefile +++ b/arch/arm/boot/dts/nxp/imx/Makefile @@ -351,6 +351,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ul-phytec-segin-ff-rdk-emmc.dtb \ imx6ul-phytec-segin-ff-rdk-nand.dtb \ imx6ul-prti6g.dtb \ + imx6ul-ts7553v2.dtb \ imx6ul-tx6ul-0010.dtb \ imx6ul-tx6ul-0011.dtb \ imx6ul-tx6ul-mainboard.dtb \ diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7553v2.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7553v2.dts new file mode 100644 index 0000000000000..f49ce18e39921 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7553v2.dts @@ -0,0 +1,692 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (C) 2023 Technologic Systems, Inc. dba embeddedTS + */ + +/dts-v1/; +#include +#include +#include "imx6ul.dtsi" + +/ { + model = "embeddedTS i.MX6UL TS-7553-V2"; + compatible = "technologic,ts7553v2", "fsl,imx6ul"; + + chosen { + stdout-path = &uart1; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0>; /* will be filled by U-Boot */ + }; + + led-controller { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led-0 { + color = ; + function = LED_FUNCTION_POWER; + gpios = <&gpio4 20 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + led-1 { + color = ; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + /* + * The keypad may be oriented in one of two ways (depending on + * how the HMI enclosure is rotated when mounted) resulting + * in the swapping of left/right and up/down. The following + * keycodes assume the unit is mounted with the keypad above + * the LCD. With a wall mount of the HMI enclosure, this would + * put the TS-7553-V2 I/O connectors pointing toward the ground. + */ + key-0 { + label = "GPIO Key RIGHT"; + gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <20>; + wakeup-source; + }; + + key-1 { + label = "GPIO Key DOWN"; + gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <20>; + wakeup-source; + }; + + key-2 { + label = "GPIO Key UP"; + gpios = <&gpio4 23 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <20>; + wakeup-source; + }; + + key-3 { + label = "GPIO Key LEFT"; + gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <20>; + wakeup-source; + }; + }; + + reg_sd1_vmmc: regulator-sd1-vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_enet_phy_3v3: regulator-phy { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet_3v3>; + regulator-name = "ENET_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_flexcan_3v3: regulator-can-3v3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan_3v3>; + regulator-name = "CAN_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 9 GPIO_ACTIVE_LOW>; + }; + + i2c_gpio: i2c { + compatible = "i2c-gpio"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2cgpio>; + sda-gpios = <&gpio5 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio5 4 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + + mpu9250a: imu@68 { + compatible = "invensense,mpu9250"; + reg = <0x68>; + interrupt-parent = <&gpio3>; + interrupts = <1 IRQ_TYPE_EDGE_RISING>; + i2c-gate { + #address-cells = <1>; + #size-cells = <0>; + magnetometer@c { + compatible = "asahi-kasei,ak8975"; + reg = <0xc>; + }; + }; + }; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_flexcan_3v3>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_flexcan_3v3>; + status = "okay"; +}; + +&ecspi3 { + num-cs = <3>; + cs-gpios = <&gpio4 12 GPIO_ACTIVE_LOW + &gpio2 15 GPIO_ACTIVE_LOW + &gpio5 6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + status = "okay"; + + /* CS# 0 is SPI LCD interface */ + spidevlcd: spi@0 { + compatible = "spidev"; + reg = <0>; + spi-max-frequency = <5000000>; + }; + + /* CS# 1 is HD1 pin header SPI interface */ + hd1_spidev: spidev@1 { + compatible = "spidev"; + reg = <1>; + }; + + fm25l16b: eeprom@2 { + compatible = "atmel,at25"; + reg = <2>; + spi-max-frequency = <20000000>; + size = <0x800>; + address-width = <16>; + pagesize = <64>; + }; +}; + +&ecspi4 { + num-cs = <1>; + cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4>; + status = "okay"; + + wilc: wifi@0 { + compatible = "microchip,wilc3000"; + reg = <0>; + spi-max-frequency = <18000000>; + reset-gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; + chip_en-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio5>; + interrupts = <1 GPIO_ACTIVE_HIGH>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + phy-supply = <®_enet_phy_3v3>; + /* These are needed in 5.10 and should probably go away upstream */ + phy-reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + status = "okay"; + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + micrel,led-mode = <1>; + clocks = <&clks IMX6UL_CLK_ENET_REF>; + clock-names = "rmii-ref"; + /* The above reset stuff should be replaced with these + * reset-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + * reset-assert-us = <10000>; + * reset-deassert-us = <100>; + */ + }; + }; +}; + +&gpio1 { + gpio-line-names = "", "USB_5V_EN", "", "", "", "", "", "", + "MODEM_5V_EN", "XBEE_3V3_EN", "", "", "", "", "", "", "", "", + "", "", "", "", "", "RS232_XCEIVER_EN"; +}; + +&gpio2 { + gpio-line-names = "", "", "", "", "", "", "", "", + "XBEE_PIN_9", "XBEE_PIN_16", "", "", "", "", + "XBEE_PIN_12"; + + /* + * Let the main 5 V reg automatically switch between PWM and PFM modes. + * This saves ~60 mW of power across various states at 12 V input. + * Note that PFM mode could cause issues with fast transients, PWM mode + * doesn't kick in until ~700 mA consumption on the regulator. Setting + * this to output-high; will force PWM mode + */ + vreg-mode-hog { + gpio-hog; + gpios = <13 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "VREG_MODE"; + }; +}; + +&gpio3 { + gpio-line-names = "USB_HUB_RESET#", "", "", "", "", "", "", + "USB_MUX_CPU_OTG", "", "", "", "NO_CHRG_JMP#", "", "", "", "", + "", "SD_BOOT_JMP#", "PUSH_SW_CPU#", "U_BOOT_JMP#", "XBEE_RESET#", + "", "", "RES_STRAP_0", "RES_STRAP_1", "", "", + "RES_STRAP_2", "RES-STRAP_3"; +}; + +&gpio5 { + gpio-line-names = "POWER_FAIL#", "", "EMMC_PWR_EN", "", "", "", "", + "XBEE_USB_EN#", "RELAY_EN"; + + vdd-soc-in-v-hog { + gpio-hog; + gpios = <3 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "VDD_SOC_IN_V"; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clock-frequency = <400000>; + status = "okay"; + + m41t00s: rtc@68 { + compatible = "st,m41t00"; + reg = <0x68>; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + /* Reserved signals */ + MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x1b020 + MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x1a020 + MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0x1a020 + MX6UL_PAD_LCD_DATA04__GPIO3_IO09 0x1a020 + MX6UL_PAD_LCD_DATA05__GPIO3_IO10 0x1a020 + MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x13020 + MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x1b020 + MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x1b020 + MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x1b020 + MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x1b020 + MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x1a020 + MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x1b020 + + + /* Has hardware pull resistor */ + MX6UL_PAD_LCD_DATA14__GPIO3_IO19 0x1a020 /* U_BOOT_JMP#_ */ + MX6UL_PAD_LCD_DATA06__GPIO3_IO11 0x1a020 /* NO_CHRG_JMP# */ + MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x1a020 /* SD_BOOT_JMP# */ + MX6UL_PAD_LCD_DATA02__GPIO3_IO07 0x1a020 /* 6UL_TO_USB_DEV */ + MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x1a020 /* MODEM 5 v */ + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x1a020 /* XBee 3.3 v */ + MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1a020 /* eMMC En. */ + MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0a0 + + /* Needs internal pull resistor */ + MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x1b020 /* RES_STRAP_0 */ + MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x1b020 /* RES_STRAP_1 */ + MX6UL_PAD_LCD_DATA22__GPIO3_IO27 0x1b020 /* RES_STRAP_2 */ + MX6UL_PAD_LCD_DATA23__GPIO3_IO28 0x1b020 /* RES_STRAP_3 */ + MX6UL_PAD_LCD_DATA15__GPIO3_IO20 0x1b020 /* XBEE_RESET# */ + MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b020 /* XBEE_USB_EN# */ + MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14 0x1b020 /* XBEE_DIO_8 */ + MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x1b020 /* XBEE_DIO_7 */ + MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x1b020 /* XBEE_DIO_6 */ + MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x1a020 /* RELAY_EN */ + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x1b020 /* USB 5v EN */ + MX6UL_PAD_LCD_CLK__GPIO3_IO00 0x1b020 /* USB_HUB_RESET# */ + MX6UL_PAD_ENET2_TX_DATA0__REF_CLK_24M 0x1b020 /* USB hub */ + MX6UL_PAD_LCD_DATA13__GPIO3_IO18 0x1a020 /* PUSH_SW_CPU# */ + MX6UL_PAD_UART2_RTS_B__GPIO1_IO23 0x1b020 /* 232_TRANS_EN */ + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b020 /* POWER_FAIL */ + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x1b020 /* LCD_BKLT */ + MX6UL_PAD_NAND_WP_B__GPIO4_IO11 0x1b020 /* LCD_RESET# */ + MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x1b020 /* LCD_CMD# */ + MX6UL_PAD_NAND_CE0_B__ECSPI3_SCLK 0x1b020 /* SPI_3_CLK */ + MX6UL_PAD_NAND_CE1_B__ECSPI3_MOSI 0x1b020 /* SPI_3_MOSI */ + MX6UL_PAD_NAND_CLE__ECSPI3_MISO 0x1b820 /* SPI_3_MISO */ + MX6UL_PAD_NAND_READY_B__GPIO4_IO12 0x1b020 /* LCD CS0# */ + MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x1b020 /* HD1 CS1# */ + MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b020 /* FRAM CS2# */ + >; + }; + + pinctrl_ecspi4: ecspi4grp { + fsl,pins = < + MX6UL_PAD_NAND_DATA04__ECSPI4_SCLK 0x1b020 + MX6UL_PAD_NAND_DATA05__ECSPI4_MOSI 0x1b020 + MX6UL_PAD_NAND_DATA06__ECSPI4_MISO 0x1b020 + MX6UL_PAD_NAND_DATA07__GPIO4_IO09 0x1b020 /* WIFI CS# */ + MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x1b020 /* WIFI IRQ# */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x1b020 /* WIFI RST# */ + MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x1b020 /* WIFI EN */ + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + /* Should be 0x4001b010 or 0x4001b000 for noise */ + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b010 + >; + }; + + pinctrl_enet_3v3: enet3v3grp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x1b0b0 + >; + }; + + pinctrl_flexcan1: flexcan1grp{ + fsl,pins = < + MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX 0x1b020 + MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX 0x1b020 + >; + }; + + pinctrl_flexcan2: flexcan2grp{ + fsl,pins = < + MX6UL_PAD_LCD_DATA10__FLEXCAN2_TX 0x1b020 + MX6UL_PAD_LCD_DATA11__FLEXCAN2_RX 0x1b020 + >; + }; + + pinctrl_flexcan_3v3: flexcan3v3grp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b020 /* CAN En. */ + >; + }; + + pinctrl_gpio_keys: gpiokeysgrp { + fsl,pins = < + MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x1a020 /* Right */ + MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x1a020 /* Down */ + MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x1a020 /* Up */ + MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x1a020 /* Left */ + >; + }; + + pinctrl_gpio_leds: gpioledgrp { + fsl,pins = < + MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x1b020 /* Red LED */ + MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x1b020 /* Grn LED */ + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x4001a8b0 + MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x4001a8b0 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA01__I2C3_SCL 0x4001a8b0 + MX6UL_PAD_LCD_DATA00__I2C3_SDA 0x4001a8b0 + >; + }; + + pinctrl_i2cgpio: i2cgpiogrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x4001a8b0 + MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x4001a8b0 + MX6UL_PAD_LCD_ENABLE__GPIO3_IO01 0x13020 /* IMU IRQ */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_UART2_CTS_B__GPIO1_IO22 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 + MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 + MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1 + MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1 + MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1 + MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1 + >; + }; + + pinctrl_uart6: uart6grp { + fsl,pins = < + MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x1b0b1 + MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x1b0b1 + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x1b0b1 + >; + }; + + pinctrl_uart7: uart7grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA17__UART7_DCE_RX 0x1b0b1 + MX6UL_PAD_LCD_DATA16__UART7_DCE_TX 0x1b0b1 + >; + }; + + pinctrl_uart8: uart8grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA21__UART8_DCE_RX 0x1b0b1 + MX6UL_PAD_LCD_DATA20__UART8_DCE_TX 0x1b0b1 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + /* Wired always high for device mode on TS-7553-V2 */ + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x16059 + >; + }; + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + /* hysteresis, en 47k PU */ + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_LCD_DATA07__GPIO3_IO12 0x17059 /* EN_SD_POWER */ + MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + >; + }; + + pinctrl_wdog1: wdog1grp { + fsl,pins = < + MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0xb8b0 + >; + }; +}; + +/* Unused, enabled for backward compatibility with ts7553v2-utils */ +&snvs_pwrkey { + status = "okay"; +}; + +&snvs_rtc { + status = "disabled"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + /* + * Need to use GPIO for TXEN even though CTS is available on this port. + * All instances of the UART2 RTS signal have other uses therefore leaving + * the UART module RTS_B input unconnected which generates spurious IRQs. + * If the imx.c driver is ever adjusted to allow configuration of RTSDEN + * then it may be possible to use real CTS here if RTS IRQs are disabled. + */ + rts-gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; + linux,rs485-enabled-at-boot-time; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + cts-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; + rts-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart7>; + status = "okay"; +}; + +&uart8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart8>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "peripheral"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + srp-disable; + hnp-disable; + adp-disable; + disable-over-current; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + disable-wp; + broken-cd; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + no-1-8-v; + disable-wp; + broken-cd; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog1>; + fsl,ext-reset-output; +}; From b274720d69abf7f2fbf1b097a6348817ac9c5d67 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Mon, 23 Jan 2023 18:04:20 -0700 Subject: [PATCH 026/244] ARM: ts_defconfig: Changes for TS-7553-V2 support Specifically adds IIO drivers, mono LCD driver, adds SNVS power key as a builtin for compatibility with `keypad-test` demo in ts7553v2-utils.git. The framebuffer console is needed for TPC platforms, it causes some issues in the TS-7553-V2 that will be resolved later. Also removes drivers that would never be used, moves a few from builtin to module, adds some other features/drivers in as a module for potential future support. Signed-off-by: Kris Bahnsen --- arch/arm/configs/ts_defconfig | 454 +++++++++++++++++++--------------- 1 file changed, 255 insertions(+), 199 deletions(-) diff --git a/arch/arm/configs/ts_defconfig b/arch/arm/configs/ts_defconfig index 0401c2d9950d0..1206ff503de1f 100644 --- a/arch/arm/configs/ts_defconfig +++ b/arch/arm/configs/ts_defconfig @@ -5,6 +5,8 @@ CONFIG_USELIB=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y CONFIG_PREEMPT=y +CONFIG_IKCONFIG=m +CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=18 CONFIG_CGROUPS=y CONFIG_MEMCG=y @@ -56,6 +58,8 @@ CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y CONFIG_ARM_IMX6Q_CPUFREQ=y CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_IDLE_GOV_TEO=y CONFIG_ARM_CPUIDLE=y CONFIG_ARM_PSCI_CPUIDLE=y CONFIG_VFP=y @@ -79,6 +83,8 @@ CONFIG_PACKET=y CONFIG_PACKET_DIAG=m CONFIG_UNIX=y CONFIG_UNIX_DIAG=m +CONFIG_TLS=m +CONFIG_TLS_DEVICE=y CONFIG_XFRM_USER=m CONFIG_XFRM_SUB_POLICY=y CONFIG_XFRM_STATISTICS=y @@ -134,6 +140,7 @@ CONFIG_IPV6_ILA=m CONFIG_IPV6_VTI=m CONFIG_IPV6_SIT=m CONFIG_IPV6_SIT_6RD=y +CONFIG_IPV6_GRE=m CONFIG_IPV6_MULTIPLE_TABLES=y CONFIG_IPV6_SUBTREES=y CONFIG_IPV6_MROUTE=y @@ -290,6 +297,26 @@ CONFIG_IP_NF_RAW=m CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RPFILTER=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_MATCH_SRH=m +CONFIG_IP6_NF_TARGET_HL=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_TARGET_SYNPROXY=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_RAW=m +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_IP6_NF_TARGET_NPT=m CONFIG_DECNET_NF_GRABULATOR=m CONFIG_NF_TABLES_BRIDGE=m CONFIG_NFT_BRIDGE_META=m @@ -435,7 +462,10 @@ CONFIG_NET_NCSI=y CONFIG_CGROUP_NET_PRIO=y CONFIG_BPF_JIT=y CONFIG_CAN=y +CONFIG_CAN_J1939=m +CONFIG_CAN_ISOTP=m CONFIG_CAN_VCAN=m +CONFIG_CAN_VXCAN=m CONFIG_CAN_SLCAN=m CONFIG_CAN_FLEXCAN=y CONFIG_CAN_8DEV_USB=m @@ -444,24 +474,27 @@ CONFIG_CAN_ESD_USB2=m CONFIG_CAN_GS_USB=m CONFIG_CAN_KVASER_USB=m CONFIG_CAN_PEAK_USB=m +CONFIG_CAN_UCAN=m CONFIG_BT=m CONFIG_BT_RFCOMM=y CONFIG_BT_RFCOMM_TTY=y CONFIG_BT_BNEP=y CONFIG_BT_BNEP_MC_FILTER=y CONFIG_BT_BNEP_PROTO_FILTER=y -CONFIG_BT_CMTP=m CONFIG_BT_HIDP=y +CONFIG_BT_HS=y CONFIG_BT_6LOWPAN=m CONFIG_BT_LEDS=y CONFIG_BT_HCIBTUSB=m +CONFIG_BT_HCIBTUSB_MTK=y CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_NOKIA=m CONFIG_BT_HCIUART_BCSP=y CONFIG_BT_HCIUART_ATH3K=y CONFIG_BT_HCIUART_LL=y -CONFIG_BT_HCIUART_3WIRE=y CONFIG_BT_HCIUART_INTEL=y CONFIG_BT_HCIUART_BCM=y +CONFIG_BT_HCIUART_RTL=y CONFIG_BT_HCIUART_QCA=y CONFIG_BT_HCIUART_AG6XX=y CONFIG_BT_HCIUART_MRVL=y @@ -472,10 +505,7 @@ CONFIG_BT_HCIVHCI=m CONFIG_BT_MRVL=m CONFIG_BT_ATH3K=m CONFIG_CFG80211=m -CONFIG_NL80211_TESTMODE=y -CONFIG_CFG80211_CERTIFICATION_ONUS=y -CONFIG_CFG80211_REG_CELLULAR_HINTS=y -CONFIG_CFG80211_REG_RELAX_NO_IR=y +# CONFIG_CFG80211_DEFAULT_PS is not set CONFIG_MAC80211=m CONFIG_MAC80211_MESH=y CONFIG_MAC80211_MESSAGE_TRACING=y @@ -491,9 +521,27 @@ CONFIG_NFC_NCI_SPI=m CONFIG_NFC_NCI_UART=m CONFIG_NFC_HCI=m CONFIG_NFC_SHDLC=y +CONFIG_NFC_TRF7970A=m +CONFIG_NFC_SIM=m CONFIG_NFC_PORT100=m +CONFIG_NFC_FDP=m +CONFIG_NFC_FDP_I2C=m +CONFIG_NFC_PN544_I2C=m CONFIG_NFC_PN533_USB=m +CONFIG_NFC_PN533_I2C=m +CONFIG_NFC_PN532_UART=m +CONFIG_NFC_MICROREAD_I2C=m CONFIG_NFC_MRVL_USB=m +CONFIG_NFC_MRVL_UART=m +CONFIG_NFC_MRVL_I2C=m +CONFIG_NFC_MRVL_SPI=m +CONFIG_NFC_ST21NFCA_I2C=m +CONFIG_NFC_ST_NCI_I2C=m +CONFIG_NFC_ST_NCI_SPI=m +CONFIG_NFC_NXP_NCI=m +CONFIG_NFC_NXP_NCI_I2C=m +CONFIG_NFC_S3FWRN5_I2C=m +CONFIG_NFC_ST95HF=m CONFIG_PCI=y CONFIG_PCI_MSI=y CONFIG_PCI_IMX6=y @@ -505,23 +553,27 @@ CONFIG_EXTRA_FIRMWARE_DIR="firmware" CONFIG_FW_LOADER_USER_HELPER=y CONFIG_IMX_WEIM=y CONFIG_CONNECTOR=y -CONFIG_MTD=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_OF_PARTS=m -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_JEDECPROBE=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_CFI_STAA=y -CONFIG_MTD_DATAFLASH=y -CONFIG_MTD_SST25L=y -CONFIG_MTD_SPI_NOR=y +CONFIG_GNSS=m +CONFIG_GNSS_MTK_SERIAL=m +CONFIG_GNSS_SIRF_SERIAL=m +CONFIG_GNSS_UBX_SERIAL=m +CONFIG_MTD=m +CONFIG_MTD_CMDLINE_PARTS=m +CONFIG_MTD_BLOCK=m +CONFIG_MTD_CFI=m +CONFIG_MTD_JEDECPROBE=m +CONFIG_MTD_CFI_INTELEXT=m +CONFIG_MTD_CFI_AMDSTD=m +CONFIG_MTD_CFI_STAA=m +CONFIG_MTD_DATAFLASH=m +CONFIG_MTD_MCHP23K256=m +CONFIG_MTD_SST25L=m +CONFIG_MTD_SPI_NOR=m +CONFIG_OF_OVERLAY=y CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_NBD=y +CONFIG_BLK_DEV_NBD=m CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=65536 -CONFIG_CDROM_PKTCDVD=m CONFIG_ATA_OVER_ETH=m CONFIG_BLK_DEV_NVME=m CONFIG_NVME_TARGET=m @@ -536,7 +588,6 @@ CONFIG_BLK_DEV_SD=y CONFIG_CHR_DEV_ST=m CONFIG_BLK_DEV_SR=m CONFIG_CHR_DEV_SG=m -CONFIG_SCSI_CONSTANTS=y CONFIG_SCSI_LOGGING=y CONFIG_SCSI_SCAN_ASYNC=y CONFIG_SCSI_FC_ATTRS=m @@ -573,9 +624,15 @@ CONFIG_DM_LOG_WRITES=m CONFIG_NETDEVICES=y CONFIG_BONDING=m CONFIG_DUMMY=m +CONFIG_WIREGUARD=m CONFIG_EQUALIZER=m CONFIG_IFB=m CONFIG_NET_TEAM=m +CONFIG_NET_TEAM_MODE_BROADCAST=m +CONFIG_NET_TEAM_MODE_ROUNDROBIN=m +CONFIG_NET_TEAM_MODE_RANDOM=m +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m +CONFIG_NET_TEAM_MODE_LOADBALANCE=m CONFIG_MACVLAN=m CONFIG_MACVTAP=m CONFIG_IPVLAN=m @@ -589,56 +646,99 @@ CONFIG_TUN=m CONFIG_VETH=m CONFIG_NLMON=m CONFIG_NET_VRF=m -CONFIG_ARCNET=m -CONFIG_ARCNET_1201=m -CONFIG_ARCNET_1051=m -CONFIG_ARCNET_RAW=m -CONFIG_ARCNET_CAP=m -CONFIG_ARCNET_COM90xx=m -CONFIG_ARCNET_COM90xxIO=m -CONFIG_ARCNET_RIM_I=m -CONFIG_ARCNET_COM20020=m -CONFIG_ATM_TCP=m +# CONFIG_ATM_DRIVERS is not set CONFIG_NET_DSA_MV88E6060=m CONFIG_NET_DSA_MV88E6XXX=m # CONFIG_NET_VENDOR_3COM is not set # CONFIG_NET_VENDOR_ADAPTEC is not set # CONFIG_NET_VENDOR_AGERE is not set +# CONFIG_NET_VENDOR_ALACRITECH is not set # CONFIG_NET_VENDOR_ALTEON is not set +# CONFIG_NET_VENDOR_AMAZON is not set # CONFIG_NET_VENDOR_AMD is not set +# CONFIG_NET_VENDOR_AQUANTIA is not set # CONFIG_NET_VENDOR_ARC is not set CONFIG_ATL2=m CONFIG_ATL1=m CONFIG_ATL1E=m CONFIG_ATL1C=m CONFIG_ALX=m +# CONFIG_NET_VENDOR_AURORA is not set # CONFIG_NET_VENDOR_BROADCOM is not set -CONFIG_CS89x0=y -CONFIG_CS89x0_PLATFORM=y +# CONFIG_NET_VENDOR_BROCADE is not set +# CONFIG_NET_VENDOR_CADENCE is not set +# CONFIG_NET_VENDOR_CAVIUM is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_CISCO is not set +# CONFIG_NET_VENDOR_CORTINA is not set +# CONFIG_NET_VENDOR_DEC is not set +# CONFIG_NET_VENDOR_DLINK is not set +# CONFIG_NET_VENDOR_EMULEX is not set +# CONFIG_NET_VENDOR_EZCHIP is not set # CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_GOOGLE is not set +# CONFIG_NET_VENDOR_HISILICON is not set +# CONFIG_NET_VENDOR_HUAWEI is not set +# CONFIG_NET_VENDOR_I825XX is not set CONFIG_IGB=y # CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MELLANOX is not set # CONFIG_NET_VENDOR_MICREL is not set -# CONFIG_NET_VENDOR_MICROCHIP is not set +CONFIG_LAN743X=m +# CONFIG_NET_VENDOR_MICROSEMI is not set +# CONFIG_NET_VENDOR_MYRI is not set # CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NETERION is not set +# CONFIG_NET_VENDOR_NETRONOME is not set +# CONFIG_NET_VENDOR_NI is not set +# CONFIG_NET_VENDOR_NVIDIA is not set +# CONFIG_NET_VENDOR_OKI is not set +CONFIG_ETHOC=m +# CONFIG_NET_VENDOR_PACKET_ENGINES is not set +# CONFIG_NET_VENDOR_PENSANDO is not set +# CONFIG_NET_VENDOR_QLOGIC is not set +CONFIG_QCA7000_SPI=m +CONFIG_QCA7000_UART=m +# CONFIG_NET_VENDOR_RDC is not set CONFIG_8139CP=m CONFIG_8139TOO=m CONFIG_R8169=m +# CONFIG_NET_VENDOR_RENESAS is not set +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set # CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SOLARFLARE is not set +# CONFIG_NET_VENDOR_SILAN is not set +# CONFIG_NET_VENDOR_SIS is not set CONFIG_SMC91X=m CONFIG_EPIC100=m CONFIG_SMC911X=m CONFIG_SMSC911X=m CONFIG_SMSC9420=m +# CONFIG_NET_VENDOR_SOCIONEXT is not set # CONFIG_NET_VENDOR_STMICRO is not set -CONFIG_TLAN=m +# CONFIG_NET_VENDOR_SUN is not set +# CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_TEHUTI is not set +# CONFIG_NET_VENDOR_TI is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_XILINX_AXI_EMAC=m +CONFIG_XILINX_LL_TEMAC=m CONFIG_FDDI=m CONFIG_DEFXX=m CONFIG_SKFP=m CONFIG_MICREL_PHY=y +CONFIG_MICROCHIP_PHY=y +CONFIG_REALTEK_PHY=y +CONFIG_SMSC_PHY=y +CONFIG_MDIO_BITBANG=y +CONFIG_MDIO_GPIO=y CONFIG_PPP=m CONFIG_PPP_BSDCOMP=m CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y CONFIG_PPP_MPPE=m CONFIG_PPPOATM=m CONFIG_PPPOE=m @@ -678,8 +778,11 @@ CONFIG_USB_IPHETH=m CONFIG_USB_SIERRA_NET=m CONFIG_USB_VL600=m CONFIG_USB_NET_CH9200=m +# CONFIG_WLAN_VENDOR_ADMTEK is not set CONFIG_ATH5K=m CONFIG_ATH9K=m +# CONFIG_ATH9K_PCOEM is not set +CONFIG_ATH9K_PCI_NO_EEPROM=m CONFIG_ATH9K_HTC=m CONFIG_CARL9170=m CONFIG_ATH6KL=m @@ -698,6 +801,7 @@ CONFIG_BRCMSMAC=m CONFIG_BRCMFMAC=m CONFIG_BRCMFMAC_USB=y CONFIG_BRCMFMAC_PCIE=y +# CONFIG_WLAN_VENDOR_CISCO is not set CONFIG_IPW2100=m CONFIG_IPW2100_MONITOR=y CONFIG_IPW2200=m @@ -735,6 +839,7 @@ CONFIG_MWIFIEX_PCIE=m CONFIG_MWIFIEX_USB=m CONFIG_MWL8K=m CONFIG_MT7601U=m +# CONFIG_WLAN_VENDOR_MICROCHIP is not set CONFIG_RT2X00=m CONFIG_RT2400PCI=m CONFIG_RT2500PCI=m @@ -756,58 +861,32 @@ CONFIG_WLCORE_SDIO=m # CONFIG_WILINK_PLATFORM_DATA is not set CONFIG_USB_ZD1201=m CONFIG_ZD1211RW=m -CONFIG_MAC80211_HWSIM=m CONFIG_USB_NET_RNDIS_WLAN=m -CONFIG_WAN=y -CONFIG_HDLC=m -CONFIG_HDLC_RAW=m -CONFIG_HDLC_RAW_ETH=m -CONFIG_HDLC_CISCO=m -CONFIG_HDLC_FR=m -CONFIG_HDLC_PPP=m -CONFIG_HDLC_X25=m -CONFIG_PCI200SYN=m -CONFIG_WANXL=m -CONFIG_PC300TOO=m -CONFIG_FARSYNC=m -CONFIG_SLIC_DS26522=m -CONFIG_DLCI=m -CONFIG_LAPBETHER=m -CONFIG_X25_ASY=m CONFIG_IEEE802154_FAKELB=m CONFIG_IEEE802154_AT86RF230=m CONFIG_IEEE802154_MRF24J40=m CONFIG_IEEE802154_CC2520=m CONFIG_IEEE802154_ATUSB=m CONFIG_IEEE802154_ADF7242=m -CONFIG_ISDN=y -CONFIG_MISDN=m -CONFIG_MISDN_DSP=m -CONFIG_MISDN_L1OIP=m -CONFIG_MISDN_HFCPCI=m -CONFIG_MISDN_HFCMULTI=m -CONFIG_MISDN_HFCUSB=m -CONFIG_MISDN_AVMFRITZ=m -CONFIG_MISDN_SPEEDFAX=m -CONFIG_MISDN_INFINEON=m -CONFIG_MISDN_W6692=m -CONFIG_MISDN_NETJET=m -CONFIG_INPUT_SPARSEKMAP=m -CONFIG_INPUT_MATRIXKMAP=y -CONFIG_INPUT_MOUSEDEV=m CONFIG_INPUT_JOYDEV=m CONFIG_INPUT_EVDEV=y -CONFIG_KEYBOARD_GPIO=y +# CONFIG_KEYBOARD_ATKBD is not set +CONFIG_KEYBOARD_GPIO=m CONFIG_KEYBOARD_GPIO_POLLED=m +CONFIG_KEYBOARD_MATRIX=m +CONFIG_KEYBOARD_SNVS_PWRKEY=y +CONFIG_KEYBOARD_IMX=m # CONFIG_MOUSE_PS2 is not set CONFIG_MOUSE_SERIAL=m CONFIG_MOUSE_APPLETOUCH=m CONFIG_MOUSE_BCM5974=m CONFIG_MOUSE_GPIO=m +CONFIG_MOUSE_SYNAPTICS_I2C=m CONFIG_MOUSE_SYNAPTICS_USB=m CONFIG_INPUT_JOYSTICK=y CONFIG_JOYSTICK_ANALOG=m CONFIG_JOYSTICK_A3D=m +CONFIG_JOYSTICK_ADC=m CONFIG_JOYSTICK_ADI=m CONFIG_JOYSTICK_COBRA=m CONFIG_JOYSTICK_GF2K=m @@ -832,6 +911,10 @@ CONFIG_JOYSTICK_JOYDUMP=m CONFIG_JOYSTICK_XPAD=m CONFIG_JOYSTICK_XPAD_FF=y CONFIG_JOYSTICK_XPAD_LEDS=y +CONFIG_JOYSTICK_PSXPAD_SPI=m +CONFIG_JOYSTICK_PSXPAD_SPI_FF=y +CONFIG_JOYSTICK_PXRC=m +CONFIG_JOYSTICK_FSIA6B=m CONFIG_INPUT_TABLET=y CONFIG_TABLET_USB_ACECAD=m CONFIG_TABLET_USB_AIPTEK=m @@ -841,14 +924,24 @@ CONFIG_TABLET_USB_KBTAB=m CONFIG_TABLET_USB_PEGASUS=m CONFIG_TABLET_SERIAL_WACOM4=m CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_ADS7846=y -CONFIG_TOUCHSCREEN_TSC2004=y -CONFIG_TOUCHSCREEN_TSC2005=y -CONFIG_TOUCHSCREEN_TSC2007=y +CONFIG_TOUCHSCREEN_ADS7846=m +CONFIG_TOUCHSCREEN_ADC=m +CONFIG_TOUCHSCREEN_PIXCIR=m +CONFIG_TOUCHSCREEN_TSC2004=m +CONFIG_TOUCHSCREEN_TSC2005=m +CONFIG_TOUCHSCREEN_TSC2007=m +CONFIG_TOUCHSCREEN_TSC2007_IIO=y CONFIG_INPUT_MISC=y +CONFIG_INPUT_MMA8450=m CONFIG_SERIO_SERPORT=m # CONFIG_LEGACY_PTYS is not set -CONFIG_SERIAL_MAX3100_TS=y +CONFIG_SERIAL_8250=m +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +# CONFIG_SERIAL_8250_16550A_VARIANTS is not set +CONFIG_SERIAL_8250_NR_UARTS=24 +CONFIG_SERIAL_8250_RUNTIME_UARTS=24 +CONFIG_SERIAL_OF_PLATFORM=m +CONFIG_SERIAL_MAX3100_TS=m CONFIG_SERIAL_IMX=y CONFIG_SERIAL_IMX_CONSOLE=y CONFIG_SERIAL_FSL_LPUART=y @@ -856,7 +949,6 @@ CONFIG_SERIAL_FSL_LPUART_CONSOLE=y CONFIG_SERIAL_DEV_BUS=y # CONFIG_I2C_COMPAT is not set CONFIG_I2C_CHARDEV=y -CONFIG_I2C_MUX=y CONFIG_I2C_MUX_GPIO=y CONFIG_I2C_MUX_PINCTRL=y CONFIG_I2C_MUX_REG=y @@ -866,6 +958,7 @@ CONFIG_I2C_ALGOPCF=m CONFIG_I2C_ALGOPCA=m CONFIG_I2C_GPIO=y CONFIG_I2C_IMX=y +CONFIG_I2C_OCORES=m CONFIG_SPI=y CONFIG_SPI_FSL_QUADSPI=y CONFIG_SPI_GPIO=y @@ -881,9 +974,11 @@ CONFIG_GPIO_MAX732X=m CONFIG_GPIO_PCA953X=m CONFIG_GPIO_PCF857X=m CONFIG_GPIO_TS4900=y +CONFIG_GPIO_74X164=m CONFIG_GPIO_PISOSR=m CONFIG_W1=m CONFIG_W1_MASTER_DS2490=m +CONFIG_W1_MASTER_MXC=m CONFIG_W1_MASTER_GPIO=m CONFIG_W1_SLAVE_THERM=m CONFIG_W1_SLAVE_SMEM=m @@ -896,37 +991,24 @@ CONFIG_W1_SLAVE_DS2433=m CONFIG_W1_SLAVE_DS2780=m CONFIG_W1_SLAVE_DS2781=m CONFIG_W1_SLAVE_DS28E04=m +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_SYSCON_POWEROFF=y CONFIG_THERMAL_STATISTICS=y CONFIG_THERMAL_WRITABLE_TRIPS=y CONFIG_CPU_THERMAL=y CONFIG_IMX_THERMAL=y CONFIG_WATCHDOG=y -CONFIG_RN5T618_WATCHDOG=y CONFIG_IMX2_WDT=y -CONFIG_MFD_DA9052_I2C=y -CONFIG_MFD_DA9062=y -CONFIG_MFD_DA9063=y -CONFIG_MFD_MC13XXX_SPI=y -CONFIG_MFD_MC13XXX_I2C=y -CONFIG_MFD_RN5T618=y -CONFIG_MFD_STMPE=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_ANATOP=y -CONFIG_REGULATOR_DA9052=y -CONFIG_REGULATOR_DA9062=y -CONFIG_REGULATOR_DA9063=y CONFIG_REGULATOR_GPIO=y -CONFIG_REGULATOR_MC13783=y -CONFIG_REGULATOR_MC13892=y -CONFIG_REGULATOR_PFUZE100=y -CONFIG_REGULATOR_RN5T618=y -CONFIG_RC_CORE=y -CONFIG_RC_MAP=m +CONFIG_RC_CORE=m CONFIG_RC_DEVICES=y CONFIG_RC_ATI_REMOTE=m CONFIG_IR_HIX5HD2=m CONFIG_IR_IMON=m +CONFIG_IR_IMON_RAW=m CONFIG_IR_MCEUSB=m CONFIG_IR_REDRAT3=m CONFIG_IR_STREAMZAP=m @@ -935,9 +1017,16 @@ CONFIG_IR_IGUANA=m CONFIG_IR_TTUSBIR=m CONFIG_RC_LOOPBACK=m CONFIG_IR_GPIO_CIR=m +CONFIG_IR_SERIAL=m +CONFIG_IR_SERIAL_TRANSMITTER=y +CONFIG_IR_SIR=m +CONFIG_RC_XBOX_DVD=m +CONFIG_IR_TOY=m CONFIG_MEDIA_SUPPORT=y -CONFIG_VIDEO_ADV_DEBUG=y -CONFIG_VIDEO_FIXED_MINOR_RANGES=y +CONFIG_MEDIA_SUBDRV_AUTOSELECT=y +CONFIG_VIDEO_DEV=m +# CONFIG_DVB_NET is not set +# CONFIG_DVB_DYNAMIC_MINORS is not set CONFIG_MEDIA_USB_SUPPORT=y CONFIG_USB_VIDEO_CLASS=m CONFIG_USB_M5602=m @@ -1040,9 +1129,11 @@ CONFIG_DVB_USB_AZ6007=m CONFIG_DVB_USB_CE6230=m CONFIG_DVB_USB_EC168=m CONFIG_DVB_USB_GL861=m +CONFIG_DVB_USB_LME2510=m CONFIG_DVB_USB_MXL111SF=m CONFIG_DVB_USB_RTL28XXU=m CONFIG_DVB_USB_DVBSKY=m +CONFIG_DVB_USB_ZD1301=m CONFIG_DVB_TTUSB_BUDGET=m CONFIG_DVB_TTUSB_DEC=m CONFIG_SMS_USB_DRV=m @@ -1055,75 +1146,69 @@ CONFIG_VIDEO_EM28XX_DVB=m CONFIG_USB_AIRSPY=m CONFIG_USB_HACKRF=m CONFIG_USB_MSI2500=m -CONFIG_MEDIA_PCI_SUPPORT=y -CONFIG_VIDEO_SOLO6X10=m -CONFIG_VIDEO_TW5864=m -CONFIG_VIDEO_TW68=m -CONFIG_VIDEO_TW686X=m -CONFIG_VIDEO_HEXIUM_GEMINI=m -CONFIG_VIDEO_HEXIUM_ORION=m -CONFIG_VIDEO_MXB=m -CONFIG_VIDEO_DT3155=m -CONFIG_VIDEO_CX25821=m -CONFIG_VIDEO_CX25821_ALSA=m -CONFIG_VIDEO_SAA7134=m -CONFIG_VIDEO_SAA7134_ALSA=m -CONFIG_VIDEO_SAA7134_DVB=m -CONFIG_VIDEO_SAA7134_GO7007=m -CONFIG_VIDEO_SAA7164=m -CONFIG_DVB_AV7110=m -CONFIG_DVB_BUDGET_CORE=m -CONFIG_DVB_BUDGET=m -CONFIG_DVB_BUDGET_AV=m -CONFIG_DVB_BUDGET_PATCH=m -CONFIG_DVB_B2C2_FLEXCOP_PCI=m -CONFIG_DVB_PLUTO2=m -CONFIG_DVB_PT1=m -CONFIG_DVB_PT3=m -CONFIG_DVB_NGENE=m -CONFIG_DVB_DDBRIDGE=m -CONFIG_DVB_NETUP_UNIDVB=m -CONFIG_RADIO_SI4713=m -CONFIG_USB_SI4713=m -CONFIG_PLATFORM_SI4713=m -CONFIG_USB_MR800=m -CONFIG_USB_DSBR=m -CONFIG_RADIO_MAXIRADIO=m -CONFIG_RADIO_SHARK=m -CONFIG_RADIO_SHARK2=m -CONFIG_USB_KEENE=m -CONFIG_USB_RAREMONO=m -CONFIG_USB_MA901=m -CONFIG_RADIO_TEA5764=m -CONFIG_RADIO_SAA7706H=m -CONFIG_RADIO_TEF6862=m +# CONFIG_RADIO_ADAPTERS is not set CONFIG_V4L_PLATFORM_DRIVERS=y -CONFIG_VIDEO_MUX=y +CONFIG_VIDEO_MUX=m CONFIG_V4L_MEM2MEM_DRIVERS=y CONFIG_VIDEO_CODA=m +CONFIG_VIDEO_IMX_PXP=m CONFIG_VIDEO_ADV7180=m CONFIG_VIDEO_OV2680=m CONFIG_VIDEO_OV5640=m CONFIG_VIDEO_OV5645=m +CONFIG_CXD2880_SPI_DRV=m +CONFIG_MEDIA_TUNER_MT2131=m +CONFIG_MEDIA_TUNER_M88RS6000T=m +CONFIG_MEDIA_TUNER_MXL301RF=m +CONFIG_MEDIA_TUNER_QM1D1B0004=m +CONFIG_DVB_STV0910=m +CONFIG_DVB_STV6111=m +CONFIG_DVB_MXL5XX=m +CONFIG_DVB_CX24110=m +CONFIG_DVB_ZL10036=m +CONFIG_DVB_TDA8261=m +CONFIG_DVB_VES1X93=m +CONFIG_DVB_TUA6100=m +CONFIG_DVB_CX24117=m +CONFIG_DVB_MB86A16=m +CONFIG_DVB_SP8870=m +CONFIG_DVB_SP887X=m +CONFIG_DVB_S5H1432=m +CONFIG_DVB_L64781=m +CONFIG_DVB_DIB9000=m +CONFIG_DVB_STV0367=m +CONFIG_DVB_CXD2880=m +CONFIG_DVB_TDA10021=m +CONFIG_DVB_OR51211=m +CONFIG_DVB_OR51132=m +CONFIG_DVB_MN88443X=m +CONFIG_DVB_LNBH25=m +CONFIG_DVB_LNBH29=m +CONFIG_DVB_ISL6405=m +CONFIG_DVB_LGS8GL5=m +CONFIG_DVB_TDA665x=m +CONFIG_DVB_HORUS3A=m +CONFIG_DVB_ASCOT2E=m +CONFIG_DVB_HELENE=m +CONFIG_DVB_CXD2099=m +# CONFIG_VGA_ARB is not set CONFIG_IMX_IPUV3_CORE=y CONFIG_DRM=y CONFIG_DRM_PANEL_LVDS=y CONFIG_DRM_PANEL_SIMPLE=y -CONFIG_DRM_PANEL_SEIKO_43WVF1G=y CONFIG_DRM_TI_TFP410=y CONFIG_DRM_DW_HDMI_AHB_AUDIO=m CONFIG_DRM_DW_HDMI_CEC=y CONFIG_DRM_IMX=y CONFIG_DRM_IMX_PARALLEL_DISPLAY=y -CONFIG_DRM_IMX_TVE=y CONFIG_DRM_IMX_LDB=y CONFIG_DRM_IMX_HDMI=y CONFIG_DRM_ETNAVIV=y CONFIG_DRM_MXSFB=y CONFIG_FB_MODE_HELPERS=y # CONFIG_FB_MX3 is not set +CONFIG_FB_ST7565P=m CONFIG_LCD_CLASS_DEVICE=y -CONFIG_LCD_L4F00242T03=y CONFIG_LCD_PLATFORM=y CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BACKLIGHT_PWM=y @@ -1131,8 +1216,9 @@ CONFIG_BACKLIGHT_GPIO=y CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_LOGO=y CONFIG_SOUND=y -CONFIG_SND=y -CONFIG_SND_HRTIMER=y +CONFIG_SND=m +CONFIG_SND_HRTIMER=m +# CONFIG_SND_PCI is not set CONFIG_SND_USB_AUDIO=m CONFIG_SND_USB_UA101=m CONFIG_SND_USB_CAIAQ=m @@ -1143,19 +1229,15 @@ CONFIG_SND_USB_POD=m CONFIG_SND_USB_PODHD=m CONFIG_SND_USB_TONEPORT=m CONFIG_SND_USB_VARIAX=m -CONFIG_SND_SOC=y -CONFIG_SND_IMX_SOC=y -CONFIG_SND_SOC_IMX_SGTL5000=y -CONFIG_SND_SOC_FSL_ASOC_CARD=y -CONFIG_SND_SOC_AC97_CODEC=y -CONFIG_SND_SOC_CS42XX8_I2C=y -CONFIG_SND_SOC_ES8328_I2C=y -CONFIG_SND_SOC_ES8328_SPI=y -CONFIG_SND_SOC_TLV320AIC23_I2C=y -CONFIG_SND_SOC_TLV320AIC3X=y -CONFIG_SND_SOC_WM8960=y -CONFIG_SND_SOC_WM8962=y -CONFIG_SND_SIMPLE_CARD=y +CONFIG_SND_SOC=m +CONFIG_SND_IMX_SOC=m +CONFIG_SND_SOC_IMX_SGTL5000=m +CONFIG_SND_SOC_FSL_ASOC_CARD=m +CONFIG_SND_SOC_AC97_CODEC=m +CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m +CONFIG_SND_SOC_TLV320AIC23_I2C=m +CONFIG_SND_SOC_TLV320AIC3X=m +CONFIG_SND_SIMPLE_CARD=m CONFIG_UHID=m CONFIG_HID_A4TECH=m CONFIG_HID_ACRUX=m @@ -1231,8 +1313,9 @@ CONFIG_USB_OTG_FSM=y CONFIG_USB_LEDS_TRIGGER_USBPORT=y CONFIG_USB_MON=m CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_FSL=y CONFIG_USB_EHCI_MXC=y -CONFIG_USB_HCD_TEST_MODE=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_PRINTER=m CONFIG_USB_STORAGE=y CONFIG_USB_STORAGE_REALTEK=m @@ -1251,9 +1334,6 @@ CONFIG_USB_STORAGE_ENE_UB6250=m CONFIG_USB_UAS=m CONFIG_USB_MDC800=m CONFIG_USB_MICROTEK=m -CONFIG_USBIP_CORE=m -CONFIG_USBIP_VHCI_HCD=m -CONFIG_USBIP_HOST=m CONFIG_USB_MUSB_HDRC=m CONFIG_USB_CHIPIDEA=y CONFIG_USB_CHIPIDEA_UDC=y @@ -1338,6 +1418,7 @@ CONFIG_USB_SPEEDTOUCH=m CONFIG_USB_CXACRU=m CONFIG_USB_UEAGLEATM=m CONFIG_USB_XUSBATM=m +CONFIG_FSL_USB2_OTG=y CONFIG_NOP_USB_XCEIV=y CONFIG_USB_MXS_PHY=y CONFIG_USB_GADGET=y @@ -1381,6 +1462,7 @@ CONFIG_USB_G_WEBCAM=m CONFIG_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_OF_ESDHC=y CONFIG_MMC_SDHCI_ESDHC_IMX=y CONFIG_LEDS_CLASS=y CONFIG_LEDS_GPIO=y @@ -1397,19 +1479,15 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=y CONFIG_LEDS_TRIGGER_TRANSIENT=y CONFIG_LEDS_TRIGGER_CAMERA=y CONFIG_LEDS_TRIGGER_PANIC=y -CONFIG_INFINIBAND=m +CONFIG_LEDS_TRIGGER_NETDEV=y +CONFIG_LEDS_TRIGGER_PATTERN=y +CONFIG_LEDS_TRIGGER_AUDIO=y CONFIG_RTC_CLASS=y CONFIG_RTC_INTF_DEV_UIE_EMUL=y CONFIG_RTC_DRV_DS1307=y CONFIG_RTC_DRV_ISL12022=y -CONFIG_RTC_DRV_PCF8523=y -CONFIG_RTC_DRV_PCF8563=y CONFIG_RTC_DRV_M41T80=y -CONFIG_RTC_DRV_RC5T619=y -CONFIG_RTC_DRV_DA9063=y -CONFIG_RTC_DRV_MC13XXX=y CONFIG_RTC_DRV_MXC=y -CONFIG_RTC_DRV_MXC_V2=y CONFIG_RTC_DRV_SNVS=y CONFIG_DMADEVICES=y CONFIG_FSL_EDMA=y @@ -1430,29 +1508,25 @@ CONFIG_R8188EU=m CONFIG_RTS5208=m CONFIG_VT6655=m CONFIG_STAGING_MEDIA=y -CONFIG_VIDEO_IMX_MEDIA=y +CONFIG_VIDEO_IMX_MEDIA=m CONFIG_COMMON_CLK_PWM=y -CONFIG_CLK_IMX8MM=y -CONFIG_CLK_IMX8MN=y -CONFIG_CLK_IMX8MP=y -CONFIG_CLK_IMX8MQ=y # CONFIG_IOMMU_SUPPORT is not set CONFIG_IMX_GPCV2_PM_DOMAINS=y -CONFIG_SOC_IMX8M=y CONFIG_EXTCON_ADC_JACK=m CONFIG_EXTCON_GPIO=m CONFIG_EXTCON_USB_GPIO=m CONFIG_IIO=y -CONFIG_IIO_BUFFER_CB=m +CONFIG_IIO_TRIGGERED_BUFFER=y CONFIG_IIO_SW_DEVICE=m CONFIG_IIO_SW_TRIGGER=m CONFIG_MMA8452=m -CONFIG_IMX7D_ADC=y -CONFIG_RN5T618_ADC=y -CONFIG_VF610_ADC=y -CONFIG_SENSORS_ISL29018=y -CONFIG_MAG3110=y -CONFIG_MPL3115=y +CONFIG_VF610_ADC=m +CONFIG_INV_MPU6050_I2C=m +CONFIG_AK8975=m +CONFIG_IIO_HRTIMER_TRIGGER=m +CONFIG_IIO_INTERRUPT_TRIGGER=m +CONFIG_IIO_TIGHTLOOP_TRIGGER=m +CONFIG_IIO_SYSFS_TRIGGER=m CONFIG_PWM=y CONFIG_PWM_FSL_FTM=y CONFIG_PWM_IMX27=y @@ -1461,9 +1535,7 @@ CONFIG_NVMEM_IMX_OCOTP=y CONFIG_NVMEM_SNVS_LPGPR=y CONFIG_TEE=y CONFIG_OPTEE=y -CONFIG_MUX_MMIO=y -CONFIG_SIOX=m -CONFIG_SIOX_BUS_GPIO=m +CONFIG_MUX_MMIO=m CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y @@ -1490,6 +1562,7 @@ CONFIG_NILFS2_FS=m CONFIG_F2FS_FS=m CONFIG_F2FS_FS_SECURITY=y CONFIG_F2FS_CHECK_FS=y +CONFIG_FANOTIFY=y CONFIG_QUOTA_NETLINK_INTERFACE=y # CONFIG_PRINT_QUOTA_WARNING is not set CONFIG_QFMT_V2=m @@ -1506,31 +1579,13 @@ CONFIG_VFAT_FS=m CONFIG_NTFS_FS=m CONFIG_NTFS_RW=y CONFIG_TMPFS_POSIX_ACL=y -CONFIG_ORANGEFS_FS=m -CONFIG_ADFS_FS=m -CONFIG_AFFS_FS=m -CONFIG_ECRYPT_FS=m CONFIG_HFS_FS=m CONFIG_HFSPLUS_FS=m -CONFIG_BEFS_FS=m -CONFIG_BFS_FS=m -CONFIG_EFS_FS=m -CONFIG_JFFS2_FS=m CONFIG_CRAMFS=m CONFIG_SQUASHFS=m CONFIG_SQUASHFS_LZ4=y CONFIG_SQUASHFS_LZO=y CONFIG_SQUASHFS_XZ=y -CONFIG_VXFS_FS=m -CONFIG_MINIX_FS=m -CONFIG_OMFS_FS=m -CONFIG_HPFS_FS=m -CONFIG_QNX4FS_FS=m -CONFIG_QNX6FS_FS=m -CONFIG_ROMFS_FS=m -CONFIG_PSTORE=m -CONFIG_SYSV_FS=m -CONFIG_UFS_FS=m CONFIG_NFS_FS=y CONFIG_NFS_V3_ACL=y CONFIG_NFS_V4=m @@ -1631,6 +1686,7 @@ CONFIG_CRYPTO_DEV_MXS_DCP=y CONFIG_CRC7=m CONFIG_LIBCRC32C=y CONFIG_CMA_SIZE_MBYTES=128 +CONFIG_IRQ_POLL=y CONFIG_PRINTK_TIME=y CONFIG_DYNAMIC_DEBUG=y CONFIG_MAGIC_SYSRQ=y From a5685dd6e215c178ca290df9c9220eb54f4be5a6 Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Fri, 31 Aug 2018 11:53:25 -0700 Subject: [PATCH 027/244] drivers: watchdog: ts_wdt: Initial commit of I2C based WDT Based on 564d5d813ea02aa24af7d9e684cdeed1f535cd4c from https://github.com/embeddedts/linux-4.9.y with modifications to be more in-line with modern kernel WDT paradigms. Signed-off-by: Kris Bahnsen --- drivers/watchdog/Kconfig | 19 +++ drivers/watchdog/Makefile | 1 + drivers/watchdog/ts_wdt.c | 274 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 294 insertions(+) create mode 100644 drivers/watchdog/ts_wdt.c diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 05008d937e405..431ca364d9eb9 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -720,6 +720,25 @@ config STMP3XXX_RTC_WATCHDOG To compile this driver as a module, choose M here: the module will be called stmp3xxx_rtc_wdt. +config TS_WDT_MICRO + tristate "embeddedTS Microcontroller Watchdog" + depends on ARM + select WATCHDOG_CORE + help + embeddedTS supervisory microcontroller watchdog implemented + over I2C. Say Y here if you want support for the watchdog + timer on compatible platforms. + + If WATCHDOG_HANDLE_BOOT_ENABLED is set, then this driver will + start the WDT as soon as possible (if not already started by + the bootloader) and do an automatic feed until userspace takes + over and starts feeding the WDT. Note that a quirk of this + is if userspace does not start feeding, a system halt will + not stop the WDT and the WDT will reset after its timeout. + + To compile this driver as a module, choose M here: the module + will be called ts_wdt. + config TS4800_WATCHDOG tristate "TS-4800 Watchdog" depends on HAS_IOMEM && OF diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index b680e4d3c1bc2..7affedf4c43c4 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -64,6 +64,7 @@ obj-$(CONFIG_SUNXI_WATCHDOG) += sunxi_wdt.o obj-$(CONFIG_RN5T618_WATCHDOG) += rn5t618_wdt.o obj-$(CONFIG_NPCM7XX_WATCHDOG) += npcm_wdt.o obj-$(CONFIG_STMP3XXX_RTC_WATCHDOG) += stmp3xxx_rtc_wdt.o +obj-$(CONFIG_TS_WDT_MICRO) += ts_wdt.o obj-$(CONFIG_TS4800_WATCHDOG) += ts4800_wdt.o obj-$(CONFIG_TS72XX_WATCHDOG) += ts72xx_wdt.o obj-$(CONFIG_IMX2_WDT) += imx2_wdt.o diff --git a/drivers/watchdog/ts_wdt.c b/drivers/watchdog/ts_wdt.c new file mode 100644 index 0000000000000..8a923e4f48d50 --- /dev/null +++ b/drivers/watchdog/ts_wdt.c @@ -0,0 +1,274 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * embeddedTS uC i2c watchdog driver + * + * Copyright (C) 2017, 2023 Technologic Systems, Inc. dba embeddedTS + * + * Originally written for kernel 4.1, this has been updated with more + * modern paradigms and does not behave quite the same as the original. + */ + +#include +#include +#include + +#define TS_DEFAULT_TIMEOUT 30 + +static int wdt_timeout; +module_param(wdt_timeout, int, 0); +MODULE_PARM_DESC(wdt_timeout, "Watchdog timeout in seconds"); + +static bool nowayout = WATCHDOG_NOWAYOUT; +module_param(nowayout, bool, 0); +MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started default=" + __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); + +/* Global for ts_wdt_poweroff to access needed data */ +static struct i2c_client *ts_wdt_poweroff_dev; + +/* The WDT expects 3 values: + * 0 (command to feed) + * and two bytes for the feed length in deciseconds + * + * + * there are also 4 special values if they are specified + * in the LSB with a 0 MSB: + * 0 - 400 ms + * 1 - 2.7 s + * 2 - 10 s + * 3 - disable watchdog + * + * Additionally, some platforms support a special poweroff/halt command + * 0x40 (command to poweroff) + * 0xAA + * 0xAA + */ + +static int ts_wdt_write(struct i2c_client *client, u16 deciseconds) +{ + u8 out[3]; + int ret; + struct i2c_msg msg; + + out[0] = 0; + out[1] = (deciseconds & 0xff00) >> 8; + out[2] = deciseconds & 0xff; + dev_dbg(&client->dev, "Writing 0x00, 0x%02x, 0x%02x\n", + out[1], + out[2]); + + msg.addr = client->addr; + msg.flags = 0; + msg.len = 3; + msg.buf = out; + + ret = i2c_transfer(client->adapter, &msg, 1); + if (ret != 1) { + dev_err(&client->dev, "%s: write error, ret=%d\n", + __func__, ret); + return ret; + } + return 0; +} + +static int ts_wdt_start(struct watchdog_device *wdd) +{ + struct i2c_client *client = to_i2c_client(wdd->parent); + + dev_dbg(&client->dev, "%s\n", __func__); + + return ts_wdt_write(client, wdd->timeout * 10); +} + +static int ts_wdt_stop(struct watchdog_device *wdd) +{ + struct i2c_client *client = to_i2c_client(wdd->parent); + + dev_dbg(&client->dev, "%s\n", __func__); + return ts_wdt_write(client, 3); +} + +static int ts_wdt_restart(struct watchdog_device *wdd, + unsigned long a, void *b) +{ + struct i2c_client *client = to_i2c_client(wdd->parent); + + dev_dbg(&client->dev, "%s\n", __func__); + + ts_wdt_write(client, 0); + while (1) + ; + + return 0; +} + +void ts_wdt_poweroff(void) +{ + struct i2c_client *client = ts_wdt_poweroff_dev; + + u8 out[3]; + int ret; + struct i2c_msg msg; + + dev_dbg(&client->dev, "%s\n", __func__); + + ts_wdt_write(client, 3); + + out[0] = 0x40; + out[1] = 0xAA; + out[2] = 0xAA; + + msg.addr = client->addr; + msg.flags = 0; + msg.len = 3; + msg.buf = out; + + ret = i2c_transfer(client->adapter, &msg, 1); + if (ret != 1) { + dev_err(&client->dev, "%s: write error, ret=%d\n", + __func__, ret); + } + + + while (1) + ; +} + +static int ts_set_timeout(struct watchdog_device *wdd, + unsigned int timeout) +{ + struct i2c_client *client = to_i2c_client(wdd->parent); + + dev_dbg(&client->dev, "%s\n", __func__); + wdd->timeout = timeout; + return 0; +} + +static struct watchdog_info ts_wdt_info = { + .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | + WDIOF_MAGICCLOSE, + .identity = "embeddedTS Micro Watchdog", +}; + +static struct watchdog_ops ts_wdt_ops = { + .owner = THIS_MODULE, + .start = ts_wdt_start, + .stop = ts_wdt_stop, + .set_timeout = ts_set_timeout, + .restart = ts_wdt_restart, +}; + +static int ts_wdt_probe(struct i2c_client *client) +{ + int err; + bool enable_early = false; + struct watchdog_device *wdd; + + dev_dbg(&client->dev, "%s\n", __func__); + + wdd = devm_kzalloc(&client->dev, sizeof(*wdd), GFP_KERNEL); + if (!wdd) + return -ENOMEM; + + wdd->info = &ts_wdt_info; + wdd->ops = &ts_wdt_ops; + wdd->min_timeout = 1; + wdd->max_timeout = 6553; + wdd->timeout = TS_DEFAULT_TIMEOUT; + wdd->parent = &client->dev; + + watchdog_init_timeout(wdd, wdt_timeout, &client->dev); + if (of_property_read_bool(client->dev.of_node, "enable-early")) + enable_early = true; + + watchdog_set_nowayout(wdd, nowayout); + + i2c_set_clientdata(client, wdd); + + err = watchdog_register_device(wdd); + if (err) + return err; + + /* We want this handler to be the first priority handler for reboots */ + watchdog_set_restart_priority(wdd, 255); + + /* + * On supported platforms either: + * The bootloader has already armed the WDT. + * -or- + * This platform's bootloader doesn't support starting the WDT and we + * want it started as quickly as possible at boot. + * + * In either case, there is no mechanism to query the WDT running status + * in hardware so we want to ensure the WDT is started and let the WDT + * core know that it is. If CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED is set, + * then the WDT core will know to automatically feed this until + * userspace can take over. If not set, a single feed takes place at + * this point in time. + */ + if (enable_early) { + err = ts_wdt_start(wdd); + if (err) + return err; + + set_bit(WDOG_HW_RUNNING, &wdd->status); + } + + /* + * On supported platforms, this will generally be the only way to + * correctly power_off the system. So, clobber any other handlers that + * may have already been set but generate some noise if this happens. + */ + if (pm_power_off != NULL) { + dev_err(&client->dev, + "%s: pm_power_off function already registered, overwriting", + __func__); + } + pm_power_off = ts_wdt_poweroff; + ts_wdt_poweroff_dev = client; + + dev_info(&client->dev, "Registered embeddedTS microcontroller watchdog\n"); + + return 0; +} + +static const struct i2c_device_id ts_wdt_id[] = { + { "ts-wdt", 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, ts_wdt_id); + +static const struct of_device_id ts_wdt_of_match[] = { + { .compatible = "technologic,ts-wdt", }, + { .compatible = "ts_wdt", }, + { }, +}; +MODULE_DEVICE_TABLE(of, ts_wdt_of_match); + +MODULE_ALIAS("platform:ts-wdt"); + +static struct i2c_driver ts_wdt_driver = { + .driver = { + .name = "ts-wdt", + .owner = THIS_MODULE, + }, + .probe = ts_wdt_probe, + .id_table = ts_wdt_id, +}; + +static int __init ts_wdt_init(void) +{ + return i2c_add_driver(&ts_wdt_driver); +} +subsys_initcall(ts_wdt_init); + +static void __exit ts_wdt_exit(void) +{ + i2c_del_driver(&ts_wdt_driver); +} +module_exit(ts_wdt_exit); + +MODULE_AUTHOR("Mark Featherston "); +MODULE_AUTHOR("Kris Bahnsen "); +MODULE_DESCRIPTION("embeddedTS watchdog driver"); +MODULE_LICENSE("GPL"); From 5f6b716b38066f6a67be77a3100f898602a0910e Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Wed, 15 Feb 2023 10:52:31 -0700 Subject: [PATCH 028/244] ARM: ts_defconfig: Add ts_wdt driver Signed-off-by: Kris Bahnsen --- arch/arm/configs/ts_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/ts_defconfig b/arch/arm/configs/ts_defconfig index 1206ff503de1f..7fcc1341601f8 100644 --- a/arch/arm/configs/ts_defconfig +++ b/arch/arm/configs/ts_defconfig @@ -998,6 +998,7 @@ CONFIG_THERMAL_WRITABLE_TRIPS=y CONFIG_CPU_THERMAL=y CONFIG_IMX_THERMAL=y CONFIG_WATCHDOG=y +CONFIG_TS_WDT_MICRO=y CONFIG_IMX2_WDT=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y From a0f3fec0f21368732ba111e391cd7d36b4eb3413 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Tue, 24 Jan 2023 15:22:21 -0700 Subject: [PATCH 029/244] ARM: dts: imx6ul: Initial commit of TS-4100 files Copied from 4.9.y branch and updated/modified for 5.10 Signed-off-by: Kris Bahnsen --- arch/arm/boot/dts/nxp/imx/Makefile | 4 + .../arm/boot/dts/nxp/imx/imx6ul-ts4100-16.dts | 13 + arch/arm/boot/dts/nxp/imx/imx6ul-ts4100-7.dts | 13 + arch/arm/boot/dts/nxp/imx/imx6ul-ts4100-8.dts | 13 + .../dts/nxp/imx/imx6ul-ts4100-ts8100.dtsi | 52 ++ .../dts/nxp/imx/imx6ul-ts4100-ts8551.dtsi | 57 ++ .../dts/nxp/imx/imx6ul-ts4100-ts8820.dtsi | 33 + arch/arm/boot/dts/nxp/imx/imx6ul-ts4100.dts | 30 + arch/arm/boot/dts/nxp/imx/imx6ul-ts4100.dtsi | 725 ++++++++++++++++++ 9 files changed, 940 insertions(+) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-ts4100-16.dts create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-ts4100-7.dts create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-ts4100-8.dts create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-ts4100-ts8100.dtsi create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-ts4100-ts8551.dtsi create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-ts4100-ts8820.dtsi create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-ts4100.dts create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-ts4100.dtsi diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx/Makefile index 7602bb65d7c5d..ee947080a9211 100644 --- a/arch/arm/boot/dts/nxp/imx/Makefile +++ b/arch/arm/boot/dts/nxp/imx/Makefile @@ -351,6 +351,10 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ul-phytec-segin-ff-rdk-emmc.dtb \ imx6ul-phytec-segin-ff-rdk-nand.dtb \ imx6ul-prti6g.dtb \ + imx6ul-ts4100.dtb \ + imx6ul-ts4100-7.dtb \ + imx6ul-ts4100-8.dtb \ + imx6ul-ts4100-16.dtb \ imx6ul-ts7553v2.dtb \ imx6ul-tx6ul-0010.dtb \ imx6ul-tx6ul-0011.dtb \ diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts4100-16.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-ts4100-16.dts new file mode 100644 index 0000000000000..cec032ba65dcc --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts4100-16.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (C) 2023 Technologic Systems, Inc. dba embeddedTS + */ + +/dts-v1/; +#include "imx6ul-ts4100.dtsi" +#include "imx6ul-ts4100-ts8551.dtsi" + +/ { + model = "embeddedTS i.MX6UL TS-4100 (TS-8551)"; + compatible = "fsl,imx6ul-ts4100", "fsl,imx6ul"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts4100-7.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-ts4100-7.dts new file mode 100644 index 0000000000000..bd5c6221a478e --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts4100-7.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (C) 2023 Technologic Systems, Inc. dba embeddedTS + */ + +/dts-v1/; +#include "imx6ul-ts4100.dtsi" +#include "imx6ul-ts4100-ts8100.dtsi" + +/ { + model = "embeddedTS i.MX6UL TS-4100 (TS-8100)"; + compatible = "fsl,imx6ul-ts4100", "fsl,imx6ul"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts4100-8.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-ts4100-8.dts new file mode 100644 index 0000000000000..94acca47bbf12 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts4100-8.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (C) 2023 Technologic Systems, Inc. dba embeddedTS + */ + +/dts-v1/; +#include "imx6ul-ts4100.dtsi" +#include "imx6ul-ts4100-ts8820.dtsi" + +/ { + model = "embeddedTS i.MX6UL TS-4100 (TS-8820)"; + compatible = "fsl,imx6ul-ts4100", "fsl,imx6ul"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts4100-ts8100.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-ts4100-ts8100.dtsi new file mode 100644 index 0000000000000..3aa5aa824f099 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts4100-ts8100.dtsi @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (C) 2023 Technologic Systems, Inc. dba embeddedTS + */ + +#include +/ { + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ppsgpio>; + gpios = <&gpio4 15 GPIO_ACTIVE_HIGH>; + + status = "okay"; + }; +}; + +/* TODO: Due to the shared MDIO bus, its tricky to disable one eth MAC without + * taking both of them out. Need to come back to this in the future. +&fec1 { + status = "disabled"; +}; +*/ + +&uart4 { + uart-has-rtscts; + /* gpio 1_18 is initialized by the hog group in 4100.dtsi + * It is the SPARE_1 pin, needs to be set up in FPGA to pass to TXEN + * with the command 'tshwctl --out 0x33 --in 0x1' + */ + rts-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; + dma-names = "", ""; + linux,rs485-enabled-at-boot-time; +}; + +&ecspi3 { + status = "disabled"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&ts4100_pinctrl_hog &pinctrl_cam_gpio &pinctrl_lcd_gpio>; + + imx6ul-ts4100-ts8100 { + pinctrl_ppsgpio: ppsgpio { + fsl,pins = < + /* Normally ECSPI3 MISO */ + MX6UL_PAD_NAND_CLE__GPIO4_IO15 0x1a020 + >; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts4100-ts8551.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-ts4100-ts8551.dtsi new file mode 100644 index 0000000000000..bd385ebf41806 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts4100-ts8551.dtsi @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (C) 2023 Technologic Systems, Inc. dba embeddedTS + */ + +#include + +/* Requires more CS GPIO and updated pinctrl? */ +&ecspi3 { + num-cs = <2>; + cs-gpios = <&gpio4 12 GPIO_ACTIVE_LOW + &gpio4 10 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + status = "okay"; + + spifram: eeprom@1 { + compatible = "atmel,at25", "cypress,fm25l16b"; + reg = <1>; + spi-max-frequency = <20000000>; + size = <0x800>; + address-width = <16>; + pagesize = <64>; + }; + +}; + +&can2 { + status = "disabled"; +}; + +&i2c3 { + m41t00s: rtc@68 { + compatible = "st,m41t00"; + reg = <0x68>; + }; +}; + +&snvs_rtc { + status = "disabled"; +}; + +&uart4 { + uart-has-rtscts; + /* gpio 1_18 is initialized by the hog group in 4100.dtsi + * It is the SPARE_1 pin, needs to be set up in FPGA to pass to TXEN + * with the command 'tshwctl --out 0x31 --in 0x1' + */ + rts-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; + dma-names = "", ""; + linux,rs485-enabled-at-boot-time; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&ts4100_pinctrl_hog &pinctrl_cam_gpio &pinctrl_lcd_gpio>; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts4100-ts8820.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-ts4100-ts8820.dtsi new file mode 100644 index 0000000000000..046a5bef438b3 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts4100-ts8820.dtsi @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (C) 2023 Technologic Systems, Inc. dba embeddedTS + */ + +#include + +&can2 { + status = "disabled"; +}; + +/* TODO: Due to the shared MDIO bus, its tricky to disable one eth MAC without + * taking both of them out. Need to come back to this in the future. +&fec1 { + status = "disabled"; +}; +*/ + +&uart4 { + uart-has-rtscts; + /* gpio 1_18 is initialized by the hog group in 4100.dtsi + * It is the SPARE_1 pin, needs to be set up in FPGA to pass to TXEN + * with the command 'tshwctl --out 0x31 --in 0x1' + */ + rts-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; + dma-names = "", ""; + linux,rs485-enabled-at-boot-time; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&ts4100_pinctrl_hog &pinctrl_cam_gpio &pinctrl_lcd_gpio>; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts4100.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-ts4100.dts new file mode 100644 index 0000000000000..b6ea2fccbc09a --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts4100.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (C) 2023 Technologic Systems, Inc. dba embeddedTS + */ + +/dts-v1/; + +#include "imx6ul-ts4100.dtsi" + +/ { + model = "embeddedTS i.MX6UL TS-4100 (Default Device Tree)"; + compatible = "fsl,imx6ul-ts4100", "fsl,imx6ul"; +}; + +&ecspi3 { + num-cs = <2>; + cs-gpios = <&gpio4 12 GPIO_ACTIVE_LOW + &gpio4 10 GPIO_ACTIVE_LOW>; + + spioffbd: spi@1 { + compatible = "spidev"; + reg = <1>; + spi-max-frequency = <1000000>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cam_gpio &pinctrl_lcd_gpio &ts4100_pinctrl_hog>; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts4100.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-ts4100.dtsi new file mode 100644 index 0000000000000..63c50b39bbc12 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts4100.dtsi @@ -0,0 +1,725 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (C) 2023 Technologic Systems, Inc. dba embeddedTS + */ + +#include +#include +#include "imx6ul.dtsi" + +/ { + aliases { + ethernet0 = &fec2; + ethernet1 = &fec1; + gpio5 = &gpio6; /* Map FPGA gpio expander to gpiochip5 */ + }; + + chosen { + stdout-path = &uart1; + }; + + led-controller { + compatible = "gpio-leds"; + + led-0 { + color = ; + function = LED_FUNCTION_POWER; + gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + led-1 { + color = ; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpio6 28 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + memory { + /* Memory size to be filled in by U-Boot */ + reg = <0x80000000 0>; + }; + + reg_sd1_vmmc: regulator-sd1-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd1_vmmc>; + regulator-name = "SD1_VMMC"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg1_vbus: regulator-otg1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; + regulator-name = "USB_OTG1_VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vref_vdd_adc_3v3: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-name = "ADC_VREF"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&adc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc1>; + vref-supply = <&vref_vdd_adc_3v3>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&ecspi3 { + num-cs = <1>; + cs-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + status = "okay"; + + spidevfpga: spi@0 { + compatible = "spidev"; + reg = <0>; + spi-max-frequency = <1000000>; + }; +}; + +&ecspi4 { + num-cs = <1>; + cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4>; + status = "okay"; + + wilc: wifi@0 { + compatible = "microchip,wilc3000"; + reg = <0>; + /* XXX: Lower this */ + spi-max-frequency = <18000000>; + reset-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; + chip_en-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio5>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@2 { + clocks = <&clks IMX6UL_CLK_ENET_REF>; + clock-names = "rmii-ref"; + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + }; + + ethphy1: ethernet-phy@1 { + clocks = <&clks IMX6UL_CLK_ENET2_REF>; + clock-names = "rmii-ref"; + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&gpio1 { + gpio-line-names = "USB_OTG_ID", "GPIO_1_ADC", "I2C_1_CLK", "I2C_1_DAT", + "EN_OTG1_5V", "", "", "", "GPIO_8_PWM", "GPIO_9_ADC", "", "", + "", "", "", "", "", "", "SPARE_1", "SPARE_2"; +}; + +&gpio3 { + gpio-line-names = "LCD_PIX_CLK", "EN_LCD_3.3V", "LCD_HSYNC", "LCD_VSYNC", + "", "I2C_3_DAT", "I2C_3_CLK", "LCD_D02", "LCD_D03", "LCD_D04", + "LCD_D05", "LCD_D06", "LCD_D07", "", "", "LCD_D10", "LCD_D11", + "LCD_D12", "LCD_D13", "LCD_D14", "LCD_D15", "", "", "LCD_D18_PWM5", + "LCD_D19_PWM6", "LCD_D20", "LCD_D21", "LCD_D22", "LCD_D23"; +}; + +&gpio4 { + gpio-line-names = "", "", "", "", "", "", "", "", "", "", "", "FPGA_RESET#", + "", "", "", "", "", "CAM_MCLK", "CAM_PIX_CLK", "CAM_VSYNC", + "CAM_HSYNC", "CAM_D_0", "CAM_D_1", "CAM_D_2", "CAM_D_3", "CAM_D_4", + "CAM_D_5", "CAM_D_6", "CAM_D_7"; +}; + +&gpio5 { + gpio-line-names = "POWER_FAIL", "FPGA_IRQ", "EN_EMMC_PWR", "", + "JTAG_FPGA_TDO", "JTAG_FPGA_TDI", "JTAG_FPGA_TMS", "JTAG_JTAG_TCK"; + + vdd-soc-in-v-hog { + gpio-hog; + gpios = <3 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "VDD_SOC_IN_V"; + }; +}; + +/* These must be GPIO mode for uC WDT */ +&i2c1 { + compatible = "i2c-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_gpio>; + sda-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + silabs: wdt@4a { + compatible = "technologic,ts-wdt"; + timeout-sec = <500>; + enable-early; + reg = <0x4a>; + /* + * Not using uC WDT by default any longer. If you need features + * provided by this, such as a real poweroff state, an external + * WDT, or proper feedback from the uC on the platform's reboot + * source (via tsmicroctl), then enable this driver (and disable + * the CPU driver, wdog1, unless you want both active). + */ + status = "disabled"; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + status = "okay"; + sda-gpios = <&gpio3 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio3 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + + /* FPGA emulates register access like an eeprom */ + fpgareg: eeprom@29 { + compatible = "atmel,24c512"; + reg = <0x29>; + }; + + /* This may need to be reworked here */ + gpio6: gpio-controller@28 { + compatible = "technologic,ts4900-gpio"; + reg = <0x28>; + #gpio-cells = <2>; + gpio-controller; + base = <160>; + ngpios = <128>; + + gpio-line-names = "", "SPARE_1", "SPARE_2", "WIFI_RESET#", "WIFI_IRQ", + "UART2_TXD", "UART2_CTS#", "UART3_TXD", "UART6_TXD", + "UART2_RXD", "UART2_RTS#", "UART3_RXD", "UART6_RXD", + "WIFI_RXD", "WIFI_RTS", "WIFI_IRQ#", "WIFI_TXD", + "WIFI_CTS", "ZPU_BREAK", "ZPU_RESET", "EN_WIFI_PWR", + "WIFI_RESET#", "EN_USB_HOST_5V", "EN_LCD_3V3", + "ETH_PHY_RESET#", "OFF_BD_RESET#", "", "GREEN_LED#", + "RED_LED#", "UARTA_RXD", "UARTB_RXD", "UARTC_RXD", + "UARTD_RXD", "UARTA_TXD", "UARTB_TXD", "UARTC_TXD", + "UARTD_TXD", "DIO_0", "DIO_1", "DIO_2", "DIO_3", "DIO_4", + "DIO_5", "DIO_6", "DIO_7", "DIO_8", "DIO_9", "", "", + "DIO_12", "DIO_13", "DIO_14", "DIO_15", "DIO_16", "DIO_17", + "DIO_18", "DIO_19", "DIO_20", "DIO_21", "DIO_22", + "DIO_23", "DIO_24", "DIO_25", "DIO_26", "DIO_27", + "DIO_28", "DIO_29", "DIO_30", "DIO_31", "DIO_32", + "DIO_33", "DIO_34", "DIO_35", "DIO_36", "DIO_37", + "DIO_38", "DIO_39", "", "DIO_41", "DIO_42", "DIO_43", + "DIO_44", "DIO_45", "DIO_46"; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&ts4100_pinctrl_hog>; + imx6ul-ts4100 { + /* NOTE: All of the hogged pins below are the common rule. + * Exceptions for them are listed in their respective baseboard + * DTS. + * + * Most IO pins default to GPIO, however they are set up with + * keepers rather than a sane pull. Because of that, we have to + * list them all here so they are set up in a known state. + * It is then up to individual DTS files to call out the pinctrl + * needed for pins that could have different states. + */ + /* All GPIO should be 0x1b020 unless special + * 0x1b020 == Hyst., 100k PU, 50 mA drive + * 0x1a020 == no pull resistor + * 0x13020 == 100k PD + */ + ts4100_pinctrl_hog: hoggrp { + fsl,pins = < + /* SD1 VSELECT, special setting */ + MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 + /* POWER_FAIL */ + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x13020 + /* FPGA_IRQ */ + MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x13020 + /* FPGA_RESET# */ + MX6UL_PAD_NAND_WP_B__GPIO4_IO11 0x1b020 + /* JTAG_FPGA_TDO */ + MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b020 + /* JTAG_FPGA_TDI */ + MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b020 + /* JTAG_FPGA_TMS */ + MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b020 + /* JTAG_FPGA_TCK */ + MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b020 + /* SPARE_1 */ + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x1b020 + /* SPARE_2 */ + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x1b020 + /* eMMC En. */ + MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b020 + /* VDD_SOC_IN_V control */ + MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79 + >; + }; + + pinctrl_adc1: adc1grp{ + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x1a020 + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x1a020 + >; + }; + + pinctrl_cam_gpio: cameragpio { + fsl,pins = < + /* Camera interface pins */ + MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x1b020 + MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x1b020 + MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x1b020 + MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x1b020 + MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x1b020 + MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x1b020 + MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x1b020 + MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x1b020 + MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x1b020 + MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x1b020 + MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x1b020 + MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x1b020 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + /* SPI_3_FPGA_CS# */ + MX6UL_PAD_NAND_READY_B__GPIO4_IO12 0x10b0 + MX6UL_PAD_NAND_CE0_B__ECSPI3_SCLK 0x10b0 + MX6UL_PAD_NAND_CE1_B__ECSPI3_MOSI 0x10b0 + MX6UL_PAD_NAND_CLE__ECSPI3_MISO 0x10b0 + /* SPI_3_OFF_BD_CS# */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x10b0 + >; + }; + + pinctrl_ecspi4: ecspi4grp { + fsl,pins = < + MX6UL_PAD_NAND_DATA04__ECSPI4_SCLK 0x10b0 + MX6UL_PAD_NAND_DATA05__ECSPI4_MOSI 0x10b0 + MX6UL_PAD_NAND_DATA06__ECSPI4_MISO 0x10b0 + /* WIFI chip select */ + MX6UL_PAD_NAND_DATA07__GPIO4_IO09 0x10b0 + /* SPARE_4/WIFI_IRQ */ + MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x1b020 + /* SPARE_3/WIFI_RESET# */ + MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x1b020 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x1f0b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + >; + }; + + pinctrl_flexcan1: flexcan1grp{ + fsl,pins = < + MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX 0x1b020 + MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX 0x1b020 + >; + }; + + pinctrl_flexcan2: flexcan2grp{ + fsl,pins = < + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 + >; + }; + + pinctrl_i2c1_gpio: i2c1grpgpio { + fsl,pins = < + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x4001b8b0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x4001b8b0 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA01__I2C3_SCL 0x4001b8b0 + MX6UL_PAD_LCD_DATA00__I2C3_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c3_gpio: i2c3grpgpio { + fsl,pins = < + MX6UL_PAD_LCD_DATA01__GPIO3_IO06 0x4001b8b0 + MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x4001b8b0 + >; + }; + + pinctrl_lcd_gpio: lcdgpio { + fsl,pins = < + /* LCD Interface pins */ + MX6UL_PAD_LCD_DATA02__GPIO3_IO07 0x1b020 + MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0x1b020 + MX6UL_PAD_LCD_DATA04__GPIO3_IO09 0x1b020 + MX6UL_PAD_LCD_DATA05__GPIO3_IO10 0x1b020 + MX6UL_PAD_LCD_DATA06__GPIO3_IO11 0x1b020 + MX6UL_PAD_LCD_DATA07__GPIO3_IO12 0x1b020 + MX6UL_PAD_LCD_DATA10__GPIO3_IO15 0x1b020 + MX6UL_PAD_LCD_DATA11__GPIO3_IO16 0x1b020 + MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x1b020 + MX6UL_PAD_LCD_DATA13__GPIO3_IO18 0x1b020 + MX6UL_PAD_LCD_DATA14__GPIO3_IO19 0x1b020 + MX6UL_PAD_LCD_DATA15__GPIO3_IO20 0x1b020 + MX6UL_PAD_LCD_DATA20__GPIO3_IO25 0x1b020 + MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x1b020 + MX6UL_PAD_LCD_DATA22__GPIO3_IO27 0x1b020 + MX6UL_PAD_LCD_DATA23__GPIO3_IO28 0x1b020 + MX6UL_PAD_LCD_CLK__GPIO3_IO00 0x1b020 + MX6UL_PAD_LCD_ENABLE__GPIO3_IO01 0x1b020 + MX6UL_PAD_LCD_HSYNC__GPIO3_IO02 0x1b020 + MX6UL_PAD_LCD_VSYNC__GPIO3_IO03 0x1b020 + >; + }; + + pinctrl_pwm1: ts4100pwm1 { + fsl,pins = < + MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x13020 + >; + }; + + /* adc1 is currently using IO09,to use pwm2 remove IO09 from the ADC + * definition and set pwm2 peripheral to "okay" + */ + pinctrl_pwm2: ts4100pwm2 { + fsl,pins = < + MX6UL_PAD_GPIO1_IO09__PWM2_OUT 0x13020 + >; + }; + + pinctrl_pwm5: ts4100pwm5 { + fsl,pins = < + MX6UL_PAD_LCD_DATA18__PWM5_OUT 0x13020 + >; + }; + + pinctrl_pwm6: ts4100pwm6 { + fsl,pins = < + MX6UL_PAD_LCD_DATA19__PWM6_OUT 0x13020 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 + MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 + >; + }; + + pinctrl_sd1_vmmc: sd1vmmcgrp { + fsl,pins = < + /* EN_SD_POWER, special setting*/ + MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x17059 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 + MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 + MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1 + MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1 + MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1 + MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1 + >; + }; + + pinctrl_uart7: uart7grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA17__UART7_DCE_RX 0x1b0b1 + MX6UL_PAD_LCD_DATA16__UART7_DCE_TX 0x1b0b1 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + >; + }; + + /* OTG1 PWR: XXX: should this hook up to not GPIO? */ + pinctrl_usb_otg1: usbotg1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x10b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 + >; + }; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "disabled"; +}; + +&pwm5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm5>; + status = "okay"; +}; + +&pwm6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm6>; + status = "okay"; +}; + +&snvs_rtc { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + /* BT, requires CTS/RTS */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; + uart-has-rtscts; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart7>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + /* keep-power-in-suspend has been found to not have any significant + * reduction in power + */ + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + max-frequency = <208000000>; + keep-power-in-suspend; + enable-sdio-wakeup; + disable-wp; + cap-sd-highspeed; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + sd-uhs-ddr50; + broken-cd = <1>; + bus-width = <4>; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + no-1-8-v; + disable-wp; + broken-cd = <1>; + enable-sdio-wakeup; + bus-width = <4>; + status = "okay"; +}; From f7ed6c53ffccba80cfc04f147f9af606a4552153 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Fri, 17 Feb 2023 18:31:58 -0700 Subject: [PATCH 030/244] drivers: gnss: Initial commit of nmea-serial Generic NMEA-0183 over serial device Signed-off-by: Kris Bahnsen --- drivers/gnss/Kconfig | 13 ++++ drivers/gnss/Makefile | 3 + drivers/gnss/nmea-serial.c | 145 +++++++++++++++++++++++++++++++++++++ 3 files changed, 161 insertions(+) create mode 100644 drivers/gnss/nmea-serial.c diff --git a/drivers/gnss/Kconfig b/drivers/gnss/Kconfig index d7fe265c28696..bd7ea7a2b69ab 100644 --- a/drivers/gnss/Kconfig +++ b/drivers/gnss/Kconfig @@ -29,6 +29,19 @@ config GNSS_MTK_SERIAL If unsure, say N. +config GNSS_NMEA_SERIAL + tristate "Generic NMEA-0183 serial receiver support" + depends on SERIAL_DEV_BUS + select GNSS_SERIAL + help + Say Y here to support a serially connected NMEA-0183 compatible GNSS + receiver. + + To compiler this driver as a module, choose M here: the module will + be called gnss-nmea-serial. + + If unsure, say N. + config GNSS_SIRF_SERIAL tristate "SiRFstar GNSS receiver support" depends on SERIAL_DEV_BUS diff --git a/drivers/gnss/Makefile b/drivers/gnss/Makefile index bb2cbada34359..7839353d5f9a6 100644 --- a/drivers/gnss/Makefile +++ b/drivers/gnss/Makefile @@ -12,6 +12,9 @@ gnss-serial-y := serial.o obj-$(CONFIG_GNSS_MTK_SERIAL) += gnss-mtk.o gnss-mtk-y := mtk.o +obj-$(CONFIG_GNSS_NMEA_SERIAL) += gnss-nmea-serial.o +gnss-nmea-serial-y := nmea-serial.o + obj-$(CONFIG_GNSS_SIRF_SERIAL) += gnss-sirf.o gnss-sirf-y := sirf.o diff --git a/drivers/gnss/nmea-serial.c b/drivers/gnss/nmea-serial.c new file mode 100644 index 0000000000000..3114678424249 --- /dev/null +++ b/drivers/gnss/nmea-serial.c @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * GNSS receiver driver for NMEA-0183 over serial + * + * Copyright (C) 2023 Technologic Systems, Inc. dba embeddedTS + * + * Based on mtk driver + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "serial.h" + +struct nmea_ser_data { + struct regulator *vbackup; + struct regulator *vcc; +}; + +static int nmea_ser_set_active(struct gnss_serial *gserial) +{ + struct nmea_ser_data *data = gnss_serial_get_drvdata(gserial); + int ret; + + ret = regulator_enable(data->vcc); + if (ret) + return ret; + + return 0; +} + +static int nmea_ser_set_standby(struct gnss_serial *gserial) +{ + struct nmea_ser_data *data = gnss_serial_get_drvdata(gserial); + int ret; + + ret = regulator_disable(data->vcc); + if (ret) + return ret; + + return 0; +} + +static int nmea_ser_set_power(struct gnss_serial *gserial, + enum gnss_serial_pm_state state) +{ + switch (state) { + case GNSS_SERIAL_ACTIVE: + return nmea_ser_set_active(gserial); + case GNSS_SERIAL_OFF: + case GNSS_SERIAL_STANDBY: + return nmea_ser_set_standby(gserial); + } + + return -EINVAL; +} + +static const struct gnss_serial_ops nmea_ser_gserial_ops = { + .set_power = nmea_ser_set_power, +}; + +static int nmea_ser_probe(struct serdev_device *serdev) +{ + struct gnss_serial *gserial; + struct nmea_ser_data *data; + int ret; + + gserial = gnss_serial_allocate(serdev, sizeof(*data)); + if (IS_ERR(gserial)) { + ret = PTR_ERR(gserial); + return ret; + } + + gserial->ops = &nmea_ser_gserial_ops; + + gserial->gdev->type = GNSS_TYPE_NMEA; + + data = gnss_serial_get_drvdata(gserial); + + data->vcc = devm_regulator_get(&serdev->dev, "vcc"); + if (IS_ERR(data->vcc)) { + ret = PTR_ERR(data->vcc); + goto err_free_gserial; + } + + if (data->vbackup) { + ret = regulator_enable(data->vbackup); + if (ret) + goto err_free_gserial; + } + + ret = gnss_serial_register(gserial); + if (ret) + goto err_disable_vbackup; + + return 0; + +err_disable_vbackup: + if (data->vbackup) + regulator_disable(data->vbackup); +err_free_gserial: + gnss_serial_free(gserial); + + return ret; +} + +static void nmea_ser_remove(struct serdev_device *serdev) +{ + struct gnss_serial *gserial = serdev_device_get_drvdata(serdev); + struct nmea_ser_data *data = gnss_serial_get_drvdata(gserial); + + gnss_serial_deregister(gserial); + if (data->vbackup) + regulator_disable(data->vbackup); + gnss_serial_free(gserial); +}; + +#ifdef CONFIG_OF +static const struct of_device_id nmea_ser_of_match[] = { + { .compatible = "gnss,nmea-serial" }, + {}, +}; +MODULE_DEVICE_TABLE(of, nmea_ser_of_match); +#endif + +static struct serdev_device_driver nmea_ser_driver = { + .driver = { + .name = "gnss-nmea-serial", + .of_match_table = of_match_ptr(nmea_ser_of_match), + .pm = &gnss_serial_pm_ops, + }, + .probe = nmea_ser_probe, + .remove = nmea_ser_remove, +}; +module_serdev_device_driver(nmea_ser_driver); + +MODULE_AUTHOR("Kris Bahnsen "); +MODULE_DESCRIPTION("Generic GNSS NMEA-0183 serial receiver driver"); +MODULE_LICENSE("GPL v2"); From 0d941bae704ff7e5560224ab26d306fd8afe0404 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Thu, 23 Feb 2023 16:27:57 -0700 Subject: [PATCH 031/244] ARM: dts: imx28: TS-7400-V2 initial commit Signed-off-by: Kris Bahnsen --- arch/arm/boot/dts/nxp/mxs/Makefile | 1 + arch/arm/boot/dts/nxp/mxs/imx28-ts7400v2.dts | 413 +++++++++++++++++++ 2 files changed, 414 insertions(+) create mode 100644 arch/arm/boot/dts/nxp/mxs/imx28-ts7400v2.dts diff --git a/arch/arm/boot/dts/nxp/mxs/Makefile b/arch/arm/boot/dts/nxp/mxs/Makefile index d72ba702b6fa6..6dedec72b1348 100644 --- a/arch/arm/boot/dts/nxp/mxs/Makefile +++ b/arch/arm/boot/dts/nxp/mxs/Makefile @@ -31,5 +31,6 @@ dtb-$(CONFIG_ARCH_MXS) += \ imx28-m28evk.dtb \ imx28-sps1.dtb \ imx28-ts4600.dtb \ + imx28-ts7400v2.dtb \ imx28-tx28.dtb \ imx28-xea.dtb diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-ts7400v2.dts b/arch/arm/boot/dts/nxp/mxs/imx28-ts7400v2.dts new file mode 100644 index 0000000000000..dd62764d1340a --- /dev/null +++ b/arch/arm/boot/dts/nxp/mxs/imx28-ts7400v2.dts @@ -0,0 +1,413 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (C) 2018-2023 Technologic Systems, Inc. dba embeddedTS + */ + +/dts-v1/; +#include +#include +#include "imx28.dtsi" + +/ { + + model = "embeddedTS i.MX28 TS-7400-V2 (Default Device Tree)"; + compatible = "fsl,imx28-ts7400v2", "fsl,imx28"; + + aliases { + mmc0 = &ssp0; + mmc2 = &ssp1; + spi0 = &ssp2; + i2c0 = &i2c0; + }; + + memory { + reg = <0x40000000 0x08000000>; /* 128MB */ + }; + + led-controller { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + compatible = "gpio-leds"; + + led-0 { + color = ; + function = LED_FUNCTION_POWER; + gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + led-1 { + color = ; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_sd_vmmc: regulator-sd-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&en_sd_pwr>; + regulator-name = "SD_VMMC"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + gpio = <&gpio3 28 GPIO_ACTIVE_LOW>; + }; + + reg_enet_3v3: regulator-enet-3v3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&mac0_pwr_ctrl>; + regulator-name = "ENET_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio0 6 GPIO_ACTIVE_LOW>; + }; + + reg_can_3v3: regulator-can-en { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan_3v3>; + regulator-name = "CAN_EN"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio3 30 GPIO_ACTIVE_LOW>; + }; +}; + +&auart0 { + pinctrl-names = "default"; + pinctrl-0 = <&auart0_2pins_a>; + status = "okay"; +}; + +&auart1 { + pinctrl-names = "default"; + pinctrl-0 = <&auart1_2pins_a>; + status = "okay"; +}; + +&auart2 { + pinctrl-names = "default"; + pinctrl-0 = <&auart2_2pins_a>; + status = "okay"; +}; + +&auart3 { + pinctrl-names = "default"; + pinctrl-0 = <&auart3_2pins_a>; + status = "okay"; +}; + +&auart4 { + pinctrl-names = "default"; + pinctrl-0 = <&auart4_2pins>; + status = "okay"; +}; + +&can0 { + pinctrl-names = "default"; + pinctrl-0 = <&can0_pins_a>; + xceiver-supply = <®_can_3v3>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&can1_pins_a>; + status = "okay"; +}; + +&duart { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_a>; + status = "okay"; +}; + +&gpio0 { + gpio-line-names = "", "", "", "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "CAN_TX1", "CAN_RX1", "", "", "CAN_TX0", + "CAN_RX0"; +}; + +&gpio1 { + gpio-line-names = "", "", "", "", "", "", "", "LCD_D07", "LCD_D08", + "LCD_D09", "LCD_D10", "LCD_D11", "LCD_D12", "", "DIO_09", + "DIO_08", "DIO_00", "DIO_01", "DIO_02", "DIO_03", "DIO_04", + "DIO_05", "DIO_06", "DIO_07", "DIO_19", "DIO_25", "", + "EN_USB_5V"; +}; + +&gpio2 { + gpio-line-names = "", "", "", "", "SPI_MISO", "SPI_CS#", "SPI_MOSI", + "SPI_CLK", "", "", "", "", "", "", "", "", "", "UART2_RXD", + "UART2_TXD", "UART3_RXD", "UART3_TXD", "CAN_TX0", "CAN_RX0"; +}; + +&gpio3 { + gpio-line-names = "UART0_RXD", "UART0_TXD", "CAN_RX1", "CAN_TX1", + "UART1_RXD", "UART1_TXD", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "I2S_MCLK", "I2S_FRAME", "I2S_BIT_CLK", + "I2S_TXD", "I2C_CLK", "I2C_DAT", "I2S_RXD", "", "", "DIO_15"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + clock-frequency = <100000>; + status = "okay"; + + isl12022: rtc@6f { + compatible = "isil,isl12022"; + btse-minutes = <1>; + isil,battery-trip-levels-microvolt = <2550000>, <2250000>; + reg = <0x6f>; + }; + + isl12022_sram: eeprom@57 { + compatible = "atmel,24c01"; + reg = <0x57>; + label = "isl12022-SRAM"; + pagesize = <128>; + size = <128>; + address-width = <8>; + }; + + silabs: watchdog@78 { + compatible = "ts-wdt"; + timeout-sec = <500>; + enable-early; + reg = <0x78>; + }; +}; + +&lradc { + status = "okay"; +}; + +&mac0 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac0_pins>; + phy-supply = <®_enet_3v3>; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; + reset-assert-us = <26000>; + reset-deassert-us = <100>; + reg = <0>; + }; + }; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + reg = <0>; + fsl,pinmux-ids = < + //USB 5V EN + MX28_PAD_LCD_CS__GPIO_1_27 + >; + fsl,drive-strength = ; + fsl,voltage = ; + /* This pin uses PULL_DISABLE == 0 == Enable Keeper */ + fsl,pull-up = ; + }; + + en_sd_pwr: en_sd_pwr { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_PWM3__GPIO_3_28 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + mmc0_4bit_pins: mmc0-4bit@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP0_DATA0__SSP0_D0 + MX28_PAD_SSP0_DATA1__SSP0_D1 + MX28_PAD_SSP0_DATA2__SSP0_D2 + MX28_PAD_SSP0_DATA3__SSP0_D3 + MX28_PAD_SSP0_CMD__SSP0_CMD + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + mmc1_4bit_pins: mmc1-4bit@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_RDY1__SSP1_CMD + MX28_PAD_GPMI_D00__SSP1_D0 + MX28_PAD_GPMI_D01__SSP1_D1 + MX28_PAD_GPMI_D02__SSP1_D2 + MX28_PAD_GPMI_D03__SSP1_D3 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + mac0_pins: mac0@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_ENET0_MDC__ENET0_MDC + MX28_PAD_ENET0_MDIO__ENET0_MDIO + MX28_PAD_ENET0_RX_EN__ENET0_RX_EN + MX28_PAD_ENET0_RXD0__ENET0_RXD0 + MX28_PAD_ENET0_RXD1__ENET0_RXD1 + MX28_PAD_ENET0_TX_EN__ENET0_TX_EN + MX28_PAD_ENET0_TXD0__ENET0_TXD0 + MX28_PAD_ENET0_TXD1__ENET0_TXD1 + MX28_PAD_ENET_CLK__CLKCTRL_ENET + /* PHY reset */ + MX28_PAD_SSP0_DETECT__GPIO_2_9 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + mac0_pwr_ctrl: mac-pwr-ctrl@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_D06__GPIO_0_6 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + auart4_2pins: auart4@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SAIF0_BITCLK__AUART4_RX + MX28_PAD_SAIF0_SDATA0__AUART4_TX + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + pinctrl_spi0: spi@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP0_DATA4__SSP2_D0 + MX28_PAD_SSP0_DATA5__SSP2_D3 + MX28_PAD_SSP0_DATA6__SSP2_CMD + MX28_PAD_SSP0_DATA7__SSP2_SCK + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + pinctrl_flexcan_3v3: en-can@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_RESET__GPIO_3_30 + >; + fsl,drive-strength = ; + fsl,voltage = ; + /* This pin uses PULL_DISABLE == 0 == Enable Keeper */ + fsl,pull-up = ; + }; + + pinctrl_gpio_leds: gpio-led@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_CE1N__GPIO_0_17 + MX28_PAD_GPMI_RESETN__GPIO_0_28 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_pins_a>; + status = "okay"; +}; + +&ssp0 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_4bit_pins + &mmc0_sck_cfg>; + broken-cd = <1>; + bus-width = <4>; + vmmc-supply = <®_sd_vmmc>; + status = "okay"; +}; + +&ssp1 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_4bit_pins + &mmc1_sck_cfg>; + broken-cd = <1>; + bus-width = <4>; + vmmc-supply = <®_sd_vmmc>; + status = "okay"; +}; + +&ssp2 { + compatible = "fsl,imx28-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + status = "okay"; + + spidevdc: spi@0 { + compatible = "spidev"; + reg = <0>; + spi-max-frequency = <1000000>; + }; +}; + +&usb0 { + disable-over-current; + dr_mode = "host"; + status = "okay"; +}; + +&usb1 { + disable-over-current; + dr_mode = "host"; + status = "okay"; +}; + +&usbphy0 { + status = "okay"; + +}; + +&usbphy1 { + status = "okay"; +}; + + + From b920c061cd764d3bec8e7d7cb98232ca82d03eaa Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Thu, 16 Feb 2023 12:15:28 -0700 Subject: [PATCH 032/244] ARM: dts: imx28: TS-7670 initial commit Based on the dts file from our linux-4.9.y repo, updated to work with more modern 5.10 paradigms and drivers. Signed-off-by: Kris Bahnsen --- arch/arm/boot/dts/nxp/mxs/Makefile | 1 + arch/arm/boot/dts/nxp/mxs/imx28-ts7670.dts | 548 +++++++++++++++++++++ 2 files changed, 549 insertions(+) create mode 100644 arch/arm/boot/dts/nxp/mxs/imx28-ts7670.dts diff --git a/arch/arm/boot/dts/nxp/mxs/Makefile b/arch/arm/boot/dts/nxp/mxs/Makefile index 6dedec72b1348..63c307c12e3e9 100644 --- a/arch/arm/boot/dts/nxp/mxs/Makefile +++ b/arch/arm/boot/dts/nxp/mxs/Makefile @@ -32,5 +32,6 @@ dtb-$(CONFIG_ARCH_MXS) += \ imx28-sps1.dtb \ imx28-ts4600.dtb \ imx28-ts7400v2.dtb \ + imx28-ts7670.dtb \ imx28-tx28.dtb \ imx28-xea.dtb diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-ts7670.dts b/arch/arm/boot/dts/nxp/mxs/imx28-ts7670.dts new file mode 100644 index 0000000000000..27f7ede337eff --- /dev/null +++ b/arch/arm/boot/dts/nxp/mxs/imx28-ts7670.dts @@ -0,0 +1,548 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (C) 2019-2023 Technologic Systems, Inc. dba embeddedTS + */ + +/dts-v1/; +#include +#include +#include "imx28.dtsi" + +/ { + + model = "embeddedTS i.MX28 TS-7670 (Default Device Tree)"; + compatible = "fsl,imx28-ts7670", "fsl,imx28"; + + aliases { + i2c0 = &i2c0_gpio; + }; + + i2c0_gpio: i2c { + compatible = "i2c-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_gpio>; + #address-cells = <1>; + #size-cells = <0>; + scl-gpios = <&gpio3 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio3 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + clock-frequency = <100000>; + + isl12022: rtc@6f { + compatible = "isil,isl12022"; + btse-minutes = <1>; + isil,battery-trip-levels-microvolt = <2550000>, <2250000>; + reg = <0x6f>; + }; + + isl12022_sram: eeprom@57 { + compatible = "atmel,24c01"; + reg = <0x57>; + label = "isl12022-SRAM"; + pagesize = <128>; + size = <128>; + address-width = <8>; + }; + + silabs: watchdog@78 { + compatible = "technologic,ts-wdt"; + timeout-sec = <500>; + enable-early; + reg = <0x78>; + }; + }; + + memory { + reg = <0x40000000 0x08000000>; /* 128MB */ + }; + + led-controller { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + compatible = "gpio-leds"; + + led-0 { + color = ; + function = LED_FUNCTION_POWER; + gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + led-1 { + color = ; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-2 { + color = ; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpio1 26 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-3 { + color = ; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gps_pps>; + gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_can_3v3: regulator-can-en { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan_3v3>; + compatible = "regulator-fixed"; + regulator-name = "CAN_EN"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio3 30 GPIO_ACTIVE_LOW>; + }; + + reg_enet_3v3: regulator-enet-3v3 { + pinctrl-names = "default"; + pinctrl-0 = <&mac0_pwr_ctrl>; + compatible = "regulator-fixed"; + regulator-name = "ENET_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 10 GPIO_ACTIVE_LOW>; + }; + + reg_gps_3v3: regulator-gps-3v3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gps_3v3>; + compatible = "regulator-fixed"; + regulator-name = "GPS_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 1 GPIO_ACTIVE_LOW>; + }; + + reg_sd_vmmc: regulator-sd-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&sd_pwr_ctrl>; + regulator-name = "SD_VMMC"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + gpio = <&gpio3 28 GPIO_ACTIVE_LOW>; + }; +}; + +&auart0 { + pinctrl-names = "default"; + pinctrl-0 = <&auart0_pins_a>; + status = "okay"; +}; + +&auart1 { + pinctrl-names = "default"; + pinctrl-0 = <&auart1_2pins_gpio_rtscts>; + rts-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; + cts-gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&auart2 { + pinctrl-names = "default"; + pinctrl-0 = <&auart2_2pins_a>; + status = "okay"; +}; + +&auart3 { + pinctrl-names = "default"; + pinctrl-0 = <&auart3_2pins_a>; + status = "okay"; +}; + +&auart4 { + pinctrl-names = "default"; + pinctrl-0 = <&auart4_2pins>; + status = "okay"; + + gnss { + compatible = "gnss,nmea-serial"; + current-speed = <9600>; + vcc-supply = <®_gps_3v3>; + timepulse-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; + }; +}; + +&can0 { + pinctrl-names = "default"; + pinctrl-0 = <&can0_pins_a>; + xceiver-supply = <®_can_3v3>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&can1_pins_a>; + xceiver-supply = <®_can_3v3>; + status = "okay"; +}; + +&duart { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_a>; + status = "okay"; +}; + +&gpio0 { + gpio-line-names = "", "", "", "", "", "HD2_8", "HD2_6", "STRAP_1"; +}; + +&gpio1 { + gpio-line-names = "", "", "", "", "", "", "", "DC_DIO_4", "DC_DIO_5", + "DC_DIO_6", "", "STRAP_4", "", "EN_MODBUS_24V", "MODBUS_FAULT", + "EN_MODBUS_3V#", "", "", "HD2_7", "STRAP_3", "PUSH_SW#", + "STRAP_2", "", "", "", "EN_232_TRANS", "", "EN_HOST_USB_5V"; +}; + +&lradc { + status = "okay"; +}; + +&mac0 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac0_pins>; + phy-supply = <®_enet_3v3>; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; + reset-assert-us = <26000>; + reset-deassert-us = <100>; + reg = <0>; + }; + }; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog &pinctrl_hog_keeperonly>; + + pinctrl_hog: hog-pins@0 { + reg = <0>; + fsl,pinmux-ids = < + /* Option strap 1 */ + MX28_PAD_GPMI_D07__GPIO_0_7 + /* HD2 pin 4,6,8 */ + MX28_PAD_GPMI_CE0N__GPIO_0_16 + MX28_PAD_GPMI_D06__GPIO_0_6 + MX28_PAD_GPMI_D05__GPIO_0_5 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + /* + * Pins that should be hogged, but only have an internal keeper, no + * pullup internally. Setting PULL_ENABLE on these will disable the + * internal keeper and then the pin, if an input, will be left floating. + */ + pinctrl_hog_keeperonly: hog-pins@1 { + reg = <0>; + fsl,pinmux-ids = < + /* Push switch */ + MX28_PAD_LCD_D20__GPIO_1_20 + /* Boot strapping */ + MX28_PAD_LCD_D00__GPIO_1_0 + MX28_PAD_LCD_D02__GPIO_1_2 + MX28_PAD_LCD_D03__GPIO_1_3 + MX28_PAD_LCD_D04__GPIO_1_4 + MX28_PAD_LCD_D05__GPIO_1_5 + MX28_PAD_LCD_D06__GPIO_1_6 + /* DC DIO 4-6 */ + MX28_PAD_LCD_D07__GPIO_1_7 + MX28_PAD_LCD_D08__GPIO_1_8 + MX28_PAD_LCD_D09__GPIO_1_9 + /* Option strap 2-4 */ + MX28_PAD_LCD_D21__GPIO_1_21 + MX28_PAD_LCD_D19__GPIO_1_19 + MX28_PAD_LCD_D11__GPIO_1_11 + /* EN MODBUS 24 V */ + MX28_PAD_LCD_D13__GPIO_1_13 + /* MODBUS FAULT */ + MX28_PAD_LCD_D14__GPIO_1_14 + /* EN MODBUS 3V# */ + MX28_PAD_LCD_D15__GPIO_1_15 + /* HD2 pin 7 */ + MX28_PAD_LCD_D18__GPIO_1_18 + /* EN 232 transceiver */ + MX28_PAD_LCD_WR_RWN__GPIO_1_25 + /* USB 5V EN */ + MX28_PAD_LCD_CS__GPIO_1_27 + >; + fsl,drive-strength = ; + fsl,voltage = ; + /* This pin uses PULL_DISABLE == 0 == Enable Keeper */ + fsl,pull-up = ; + }; + + i2c0_pins_gpio: i2c-gpio-pins@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_I2C0_SCL__GPIO_3_24 + MX28_PAD_I2C0_SDA__GPIO_3_25 + >; + fsl,drive-strength = ; + fsl,voltage = ; + /* This pin uses PULL_DISABLE == 0 == Enable Keeper */ + fsl,pull-up = ; + }; + + mmc0_4bit_pins: mmc0-4bit-pins@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP0_DATA0__SSP0_D0 + MX28_PAD_SSP0_DATA1__SSP0_D1 + MX28_PAD_SSP0_DATA2__SSP0_D2 + MX28_PAD_SSP0_DATA3__SSP0_D3 + MX28_PAD_SSP0_CMD__SSP0_CMD + MX28_PAD_SSP0_SCK__SSP0_SCK + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + sd_pwr_ctrl: sd-pwr-ctrl@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_PWM3__GPIO_3_28 + >; + fsl,drive-strength = ; + fsl,voltage = ; + /* This pin uses PULL_DISABLE == 0 == Enable Keeper */ + fsl,pull-up = ; + }; + + mmc1_4bit_pins: mmc1-4bit-pins@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_D00__SSP1_D0 + MX28_PAD_GPMI_D01__SSP1_D1 + MX28_PAD_GPMI_D02__SSP1_D2 + MX28_PAD_GPMI_D03__SSP1_D3 + MX28_PAD_GPMI_RDY1__SSP1_CMD + MX28_PAD_GPMI_WRN__SSP1_SCK + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + mmc2_4bit_pins: mmc2-4bit-pins@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP0_DATA4__SSP2_D0 + MX28_PAD_SSP2_SS1__SSP2_D1 + MX28_PAD_SSP2_SS2__SSP2_D2 + MX28_PAD_SSP0_DATA5__SSP2_D3 + MX28_PAD_SSP0_DATA6__SSP2_CMD + MX28_PAD_SSP0_DATA7__SSP2_SCK + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + mac0_pins: mac0-pins@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_ENET0_MDC__ENET0_MDC + MX28_PAD_ENET0_MDIO__ENET0_MDIO + MX28_PAD_ENET0_RX_EN__ENET0_RX_EN + MX28_PAD_ENET0_RXD0__ENET0_RXD0 + MX28_PAD_ENET0_RXD1__ENET0_RXD1 + MX28_PAD_ENET0_TX_EN__ENET0_TX_EN + MX28_PAD_ENET0_TXD0__ENET0_TXD0 + MX28_PAD_ENET0_TXD1__ENET0_TXD1 + MX28_PAD_ENET_CLK__CLKCTRL_ENET + /* PHY reset */ + MX28_PAD_SSP0_DETECT__GPIO_2_9 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + mac0_pwr_ctrl: mac0-pwr-ctrl@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_D10__GPIO_1_10 + >; + fsl,drive-strength = ; + fsl,voltage = ; + /* This pin uses PULL_DISABLE == 0 == Enable Keeper */ + fsl,pull-up = ; + }; + + auart4_2pins: auart4-2pins@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SAIF0_BITCLK__AUART4_RX + MX28_PAD_SAIF0_SDATA0__AUART4_TX + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + auart1_2pins_gpio_rtscts: auart1-pins@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_AUART1_RX__AUART1_RX + MX28_PAD_AUART1_TX__AUART1_TX + /* AUART1 RTS GPIO */ + MX28_PAD_LCD_D23__GPIO_1_23 + /* AUART1 CTS GPIO */ + MX28_PAD_LCD_D22__GPIO_1_22 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + pinctrl_flexcan_3v3: can-en-pins@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_RESET__GPIO_3_30 + >; + fsl,drive-strength = ; + fsl,voltage = ; + /* This pin uses PULL_DISABLE == 0 == Enable Keeper */ + fsl,pull-up = ; + }; + + pinctrl_gpio_leds: led-pins@0 { + reg = <0>; + fsl,pinmux-ids = < + /* Red LED */ + MX28_PAD_GPMI_CE1N__GPIO_0_17 + /* Green LED */ + MX28_PAD_GPMI_RESETN__GPIO_0_28 + /* Yellow LED */ + MX28_PAD_LCD_RS__GPIO_1_26 + /* Blue LED */ + MX28_PAD_LCD_RD_E__GPIO_1_24 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + pinctrl_gps_3v3: gps-pwr-ctrl@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_D01__GPIO_1_1 + >; + fsl,drive-strength = ; + fsl,voltage = ; + /* This pin uses PULL_DISABLE == 0 == Enable Keeper */ + fsl,pull-up = ; + }; + + pinctrl_gps_pps: gps-pps-pins@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_D16__GPIO_1_16 + >; + fsl,drive-strength = ; + fsl,voltage = ; + /* This pin uses PULL_DISABLE == 0 == Enable Keeper */ + fsl,pull-up = ; + }; + +}; + + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_pins_a>; + status = "okay"; +}; + +/* SD 0 */ +&ssp0 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_4bit_pins>; + vmmc-supply = <®_sd_vmmc>; + bus-width = <4>; + broken-cd; + disable-wp; + status = "okay"; +}; + +/* eMMC */ +&ssp1 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_4bit_pins>; + vmmc-supply = <®_sd_vmmc>; + bus-width = <4>; + broken-cd; + disable-wp; + non-removable; + status = "okay"; +}; + +/* SD 1 */ +&ssp2 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_4bit_pins>; + vmmc-supply = <®_sd_vmmc>; + bus-width = <4>; + broken-cd; + disable-wp; + status = "okay"; +}; + +&usb0 { + disable-over-current; + dr_mode = "host"; + status = "okay"; +}; + +&usb1 { + disable-over-current; + dr_mode = "host"; + status = "okay"; +}; + +&usbphy0 { + status = "okay"; + +}; + +&usbphy1 { + status = "okay"; +}; From d8e96743322efbf6440749f39fc127171b06b52c Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Thu, 16 Feb 2023 12:26:32 -0700 Subject: [PATCH 033/244] ARM: configs: ts_imx28: Initial commit Based on ts_imx28_defconfig from our linux-4.9.y repo, updated options for 5.10 Signed-off-by: Kris Bahnsen --- arch/arm/configs/ts_imx28_defconfig | 311 ++++++++++++++++++++++++++++ 1 file changed, 311 insertions(+) create mode 100644 arch/arm/configs/ts_imx28_defconfig diff --git a/arch/arm/configs/ts_imx28_defconfig b/arch/arm/configs/ts_imx28_defconfig new file mode 100644 index 0000000000000..646c8b70bb182 --- /dev/null +++ b/arch/arm/configs/ts_imx28_defconfig @@ -0,0 +1,311 @@ +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +# CONFIG_CROSS_MEMORY_ATTACH is not set +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_PREEMPT_VOLUNTARY=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_CGROUPS=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_PID_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_PERF_EVENTS=y +# CONFIG_COMPAT_BRK is not set +# CONFIG_ARCH_MULTI_V7 is not set +CONFIG_ARCH_MXS=y +CONFIG_AEABI=y +CONFIG_MODULES=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_UNUSED_SYMBOLS=y +CONFIG_BLK_DEV_INTEGRITY=y +CONFIG_CLEANCACHE=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_NET_IPIP=m +CONFIG_SYN_COOKIES=y +# CONFIG_INET_DIAG is not set +CONFIG_IPV6=m +CONFIG_IPV6_VTI=m +CONFIG_BRIDGE=m +CONFIG_BRIDGE_VLAN_FILTERING=y +CONFIG_NET_DSA=m +CONFIG_VLAN_8021Q=m +CONFIG_CAN=m +CONFIG_CAN_FLEXCAN=m +CONFIG_BT=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=m +CONFIG_BT_HCIBTUSB=m +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_BCSP=y +CONFIG_BT_HCIUART_ATH3K=y +CONFIG_BT_HCIBCM203X=m +CONFIG_BT_HCIBPA10X=m +CONFIG_BT_HCIBFUSB=m +CONFIG_BT_HCIVHCI=m +CONFIG_CFG80211=m +CONFIG_CFG80211_WEXT=y +CONFIG_MAC80211=m +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_GNSS=y +CONFIG_GNSS_NMEA_SERIAL=y +CONFIG_BLK_DEV_LOOP=m +CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_RAM=m +CONFIG_EEPROM_AT24=m +CONFIG_EEPROM_AT25=m +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_DEV_SR=m +CONFIG_CHR_DEV_SG=m +CONFIG_NETDEVICES=y +CONFIG_MACVLAN=m +CONFIG_TUN=m +CONFIG_NET_DSA_MV88E6XXX=m +# CONFIG_NET_VENDOR_AMAZON is not set +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_EZCHIP is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_HISILICON is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NETRONOME is not set +# CONFIG_NET_VENDOR_QUALCOMM is not set +# CONFIG_NET_VENDOR_RENESAS is not set +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_PPP=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_MPPE=m +CONFIG_PPPOE=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_USB_RTL8152=m +CONFIG_USB_LAN78XX=m +CONFIG_USB_USBNET=y +CONFIG_USB_NET_HUAWEI_CDC_NCM=m +CONFIG_USB_NET_CDC_MBIM=m +CONFIG_USB_NET_SMSC75XX=m +CONFIG_USB_NET_SMSC95XX=y +CONFIG_USB_NET_PLUSB=m +# CONFIG_WLAN_VENDOR_ADMTEK is not set +CONFIG_ATH9K=m +CONFIG_ATH9K_HTC=m +CONFIG_CARL9170=m +CONFIG_ATH6KL=m +CONFIG_ATH6KL_USB=m +CONFIG_AR5523=m +CONFIG_ATH10K=m +CONFIG_WCN36XX=m +CONFIG_AT76C50X_USB=m +# CONFIG_WLAN_VENDOR_BROADCOM is not set +# CONFIG_WLAN_VENDOR_CISCO is not set +# CONFIG_WLAN_VENDOR_INTEL is not set +# CONFIG_WLAN_VENDOR_INTERSIL is not set +# CONFIG_WLAN_VENDOR_MARVELL is not set +# CONFIG_WLAN_VENDOR_MEDIATEK is not set +CONFIG_RT2X00=m +CONFIG_RT2500USB=m +CONFIG_RT73USB=m +CONFIG_RT2800USB=m +# CONFIG_RT2800USB_RT35XX is not set +CONFIG_RTL8192CU=m +CONFIG_RTL8XXXU=m +# CONFIG_WLAN_VENDOR_RSI is not set +# CONFIG_WLAN_VENDOR_ST is not set +CONFIG_WL12XX=m +CONFIG_WLCORE_SDIO=m +CONFIG_USB_ZD1201=m +CONFIG_ZD1211RW=m +CONFIG_INPUT_MOUSEDEV=m +CONFIG_INPUT_JOYDEV=m +CONFIG_INPUT_EVDEV=m +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +CONFIG_VT_HW_CONSOLE_BINDING=y +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_MXS_AUART=y +CONFIG_SERIAL_DEV_BUS=y +# CONFIG_HW_RANDOM is not set +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_GPIO=y +CONFIG_I2C_MXS=y +CONFIG_SPI=y +CONFIG_SPI_GPIO=m +CONFIG_SPI_MXS=y +CONFIG_SPI_SPIDEV=m +CONFIG_PPS_CLIENT_GPIO=m +CONFIG_GPIO_SYSFS=y +CONFIG_HWMON=m +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED is not set +CONFIG_TS_WDT_MICRO=y +CONFIG_MFD_MXS_LRADC=m +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_SOUND=y +CONFIG_SND=y +# CONFIG_SND_ARM is not set +# CONFIG_SND_SPI is not set +CONFIG_SND_USB_AUDIO=m +CONFIG_SND_USB_UA101=m +CONFIG_SND_USB_CAIAQ=m +CONFIG_SND_USB_6FIRE=m +CONFIG_SND_USB_HIFACE=m +CONFIG_SND_BCD2000=m +CONFIG_SND_USB_POD=m +CONFIG_SND_USB_PODHD=m +CONFIG_SND_USB_TONEPORT=m +CONFIG_SND_USB_VARIAX=m +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MONTEREY is not set +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_OTG=y +CONFIG_USB_OTG_FSM=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_ACM=m +CONFIG_USB_STORAGE=y +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_SIMPLE=m +CONFIG_USB_SERIAL_CP210X=m +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_GARMIN=m +CONFIG_USB_SERIAL_PL2303=m +CONFIG_USB_SERIAL_SIERRAWIRELESS=m +CONFIG_USB_SERIAL_SYMBOL=m +CONFIG_USB_MXS_PHY=y +CONFIG_USB_GADGET=y +CONFIG_USB_CONFIGFS=m +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONFIGFS_ACM=y +CONFIG_USB_CONFIGFS_OBEX=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_ECM=y +CONFIG_USB_CONFIGFS_ECM_SUBSET=y +CONFIG_USB_CONFIGFS_RNDIS=y +CONFIG_USB_CONFIGFS_EEM=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_LB_SS=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_CONFIGFS_F_UAC1=y +CONFIG_USB_CONFIGFS_F_UAC2=y +CONFIG_USB_CONFIGFS_F_MIDI=y +CONFIG_USB_CONFIGFS_F_HID=y +CONFIG_USB_CONFIGFS_F_PRINTER=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_GADGETFS=m +CONFIG_USB_FUNCTIONFS=m +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m +CONFIG_USB_CDC_COMPOSITE=m +CONFIG_USB_G_ACM_MS=m +CONFIG_USB_G_HID=m +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_MXS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_ONESHOT=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_LEDS_TRIGGER_PANIC=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_DS1307=y +CONFIG_RTC_DRV_ISL12022=m +CONFIG_DMADEVICES=y +CONFIG_MXS_DMA=y +CONFIG_COMMON_CLK_PWM=y +CONFIG_IIO=m +CONFIG_MMA8452=m +CONFIG_MXS_LRADC_ADC=m +CONFIG_PWM=y +CONFIG_PWM_MXS=y +CONFIG_NVMEM_MXS_OCOTP=m +CONFIG_EXT4_FS=y +# CONFIG_DNOTIFY is not set +CONFIG_FANOTIFY=y +CONFIG_AUTOFS4_FS=y +CONFIG_FSCACHE=m +CONFIG_FSCACHE_STATS=y +CONFIG_CACHEFILES=m +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_ROOT_NFS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_15=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_DEV_MXS_DCP=y +CONFIG_CRC7=m +CONFIG_PRINTK_TIME=y +CONFIG_DEBUG_INFO=y +CONFIG_FRAME_WARN=2048 +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_KERNEL=y +CONFIG_PROVE_LOCKING=y +CONFIG_BLK_DEV_IO_TRACE=y +CONFIG_STRICT_DEVMEM=y +CONFIG_DEBUG_USER=y From 7bf02d9aecc4ce2a5b06b27a21900fc47da90de2 Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Thu, 2 Mar 2023 14:15:30 -0700 Subject: [PATCH 034/244] drivers: bus: ts-pc104: Initial commit of Technologic Systems PC/104 memory window --- drivers/bus/Kconfig | 7 + drivers/bus/Makefile | 1 + drivers/bus/ts-pc104.c | 464 ++++++++++++++++++++++++++++++++++++ include/linux/tspc104_bus.h | 91 +++++++ 4 files changed, 563 insertions(+) create mode 100644 drivers/bus/ts-pc104.c create mode 100644 include/linux/tspc104_bus.h diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig index fe7600283e709..08c924dff5e7c 100644 --- a/drivers/bus/Kconfig +++ b/drivers/bus/Kconfig @@ -241,6 +241,13 @@ config TS_NBUS Driver for the Technologic Systems NBUS which is used to interface with the peripherals in the FPGA of the TS-4600 SoM. +config TSPC104 + tristate "embeddedTS PC104 memory window bus" + depends on HAS_IOMEM + depends on OF + help + Driver for embeddedTS PC104 implementation inside of a memory window + config UNIPHIER_SYSTEM_BUS tristate "UniPhier System Bus driver" depends on ARCH_UNIPHIER && OF diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile index 8e693fe8a03a5..12c76654df2a4 100644 --- a/drivers/bus/Makefile +++ b/drivers/bus/Makefile @@ -36,6 +36,7 @@ obj-$(CONFIG_TEGRA_GMI) += tegra-gmi.o obj-$(CONFIG_TI_PWMSS) += ti-pwmss.o obj-$(CONFIG_TI_SYSC) += ti-sysc.o obj-$(CONFIG_TS_NBUS) += ts-nbus.o +obj-$(CONFIG_TSPC104) += ts-pc104.o obj-$(CONFIG_UNIPHIER_SYSTEM_BUS) += uniphier-system-bus.o obj-$(CONFIG_VEXPRESS_CONFIG) += vexpress-config.o diff --git a/drivers/bus/ts-pc104.c b/drivers/bus/ts-pc104.c new file mode 100644 index 0000000000000..3bee38f75a644 --- /dev/null +++ b/drivers/bus/ts-pc104.c @@ -0,0 +1,464 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * + * PC104 bus driver for TS systems. This uses a memory window to provide + * io / mem cycles at 8/16 bit sizes. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * 0x4050: 32-bit register for kernel space + * bit 31: busy, means do not write. (RO) - On write 0 = address, 1 = start cycle + * bit 30: IO (1) memory (0) + * bit 29: 8-bit (1) 16-bit (0) + * bit 28: read (1), write (0) + * bit 27: funky-TS mode enable + * bit 26-0: address/data + */ + +#define PC104_ADDR_SPACE ((1<<20) - 1) + +struct tspc104_bus { + struct gpio_desc *gpio_reset; + /* + * This the standard pinout, but supports a pinout that allows 16-bit + * cycles without the 40 pin header just using 64 pins. + */ + int use_ts_mode; + void __iomem *reg; + spinlock_t lock; +}; + +static int tspc104_block_while_busy(struct tspc104_bus *bus) +{ + while (readl(bus->reg) & TSISA_GOBSY) + ; + + return 0; +} + +int tspc104_reg_write(struct tspc104_bus *bus, unsigned int reg, + unsigned int *val, uint32_t busflags) +{ + unsigned long flags; + int ret; + + spin_lock_irqsave(&bus->lock, flags); + writel(reg & 0x7FFFFFF, bus->reg); + writel((*val & 0xffff) | busflags | TSISA_GOBSY, bus->reg); + ret = tspc104_block_while_busy(bus); + spin_unlock_irqrestore(&bus->lock, flags); + + return ret; +} +EXPORT_SYMBOL_GPL(tspc104_reg_write); + +int tspc104_reg_read(struct tspc104_bus *bus, unsigned int reg, + unsigned int *val, uint32_t busflags) +{ + unsigned long flags; + int ret; + + spin_lock_irqsave(&bus->lock, flags); + writel(reg & 0x7FFFFFF, bus->reg); + writel(busflags | TSISA_RDEN | TSISA_GOBSY, bus->reg); + ret = tspc104_block_while_busy(bus); + *val = readl(bus->reg); + spin_unlock_irqrestore(&bus->lock, flags); + + if (busflags & TSISA_8BIT) + *val &= 0xff; + else + *val &= 0xffff; + + return ret; +} +EXPORT_SYMBOL_GPL(tspc104_reg_read); + +static int ts_pc104bus_init_pdata(struct platform_device *pdev, + struct tspc104_bus *bus) +{ + bus->gpio_reset = devm_gpiod_get(&pdev->dev, "reset", + GPIOD_OUT_HIGH); + if (IS_ERR(bus->gpio_reset)) { + dev_err(&pdev->dev, "Failed to get ISA_RESET\n"); + return PTR_ERR(bus->gpio_reset); + } + + return 0; +} + +static ssize_t isa_io8_read(struct file *filp, struct kobject *kobj, + struct bin_attribute *bin_attr, + char *buf, loff_t off, size_t count) +{ + struct device *dev = container_of(kobj, struct device, kobj); + struct tspc104_bus *bus = dev_get_drvdata(dev); + unsigned int val; + int i; + + for (i = 0; i < count; i++) { + tspc104_io_read8(bus, off + i, &val); + buf[i] = (char)val; + } + + return i; +} + +static ssize_t isa_io8_write(struct file *filp, struct kobject *kobj, + struct bin_attribute *bin_attr, + char *buf, loff_t off, size_t count) +{ + struct device *dev = container_of(kobj, struct device, kobj); + struct tspc104_bus *bus = dev_get_drvdata(dev); + unsigned int val; + int i; + + for (i = 0; i < count; i++) { + val = (unsigned int)buf[i]; + tspc104_io_write8(bus, off + i, &val); + } + + return i; +} + +static ssize_t isa_mem8_read(struct file *filp, struct kobject *kobj, + struct bin_attribute *bin_attr, + char *buf, loff_t off, size_t count) +{ + struct device *dev = container_of(kobj, struct device, kobj); + struct tspc104_bus *bus = dev_get_drvdata(dev); + unsigned int val; + int i; + + for (i = 0; i < count; i++) { + tspc104_mem_read8(bus, off + i, &val); + buf[i] = (char)val; + } + + return i; +} + +static ssize_t isa_mem8_write(struct file *filp, struct kobject *kobj, + struct bin_attribute *bin_attr, + char *buf, loff_t off, size_t count) +{ + struct device *dev = container_of(kobj, struct device, kobj); + struct tspc104_bus *bus = dev_get_drvdata(dev); + unsigned int val; + int i; + + for (i = 0; i < count; i++) { + val = (unsigned int)buf[i]; + tspc104_mem_write8(bus, off + i, &val); + } + + return i; +} + +static ssize_t isa_io16_read(struct file *filp, struct kobject *kobj, + struct bin_attribute *bin_attr, + char *buf, loff_t off, size_t count) +{ + struct device *dev = container_of(kobj, struct device, kobj); + struct tspc104_bus *bus = dev_get_drvdata(dev); + unsigned int val; + int i; + + for (i = 0; i < count; i += 2) { + tspc104_io_read16(bus, off + i, &val); + buf[i] = (char)val; + if (i <= count) + buf[i+1] = (char)(val >> 8); + } + + return i; +} + +static ssize_t isa_io16_write(struct file *filp, struct kobject *kobj, + struct bin_attribute *bin_attr, + char *buf, loff_t off, size_t count) +{ + struct device *dev = container_of(kobj, struct device, kobj); + struct tspc104_bus *bus = dev_get_drvdata(dev); + unsigned int val; + int i; + + BUG_ON(count % 2 != 0); + + for (i = 0; i < count; i += 2) { + val = (unsigned int)(buf[i]); + val |= (unsigned int)(buf[i+1] << 8); + tspc104_io_write16(bus, off + i, &val); + } + + return i; +} + +static ssize_t isa_mem16_read(struct file *filp, struct kobject *kobj, + struct bin_attribute *bin_attr, + char *buf, loff_t off, size_t count) +{ + struct device *dev = container_of(kobj, struct device, kobj); + struct tspc104_bus *bus = dev_get_drvdata(dev); + unsigned int val; + int i; + + for (i = 0; i < count; i += 2) { + tspc104_mem_read16(bus, off + i, &val); + buf[i] = (char)val; + if (i <= count) + buf[i+1] = (char)(val >> 8); + } + + return i; +} + +static ssize_t isa_mem16_write(struct file *filp, struct kobject *kobj, + struct bin_attribute *bin_attr, + char *buf, loff_t off, size_t count) +{ + struct device *dev = container_of(kobj, struct device, kobj); + struct tspc104_bus *bus = dev_get_drvdata(dev); + unsigned int val; + int i; + + BUG_ON(count % 2 != 0); + + for (i = 0; i < count; i += 2) { + val = (unsigned int)(buf[i]); + val |= (unsigned int)(buf[i+1] << 8); + tspc104_mem_write16(bus, off + i, &val); + } + + return i; +} + +static ssize_t isa_io16alt_read(struct file *filp, struct kobject *kobj, + struct bin_attribute *bin_attr, + char *buf, loff_t off, size_t count) +{ + struct device *dev = container_of(kobj, struct device, kobj); + struct tspc104_bus *bus = dev_get_drvdata(dev); + unsigned int val; + int i; + + for (i = 0; i < count; i += 2) { + tspc104_io_read16_altpinout(bus, off + i, &val); + buf[i] = (char)val; + if (i <= count) + buf[i+1] = (char)(val >> 8); + } + + return i; +} + +static ssize_t isa_io16alt_write(struct file *filp, struct kobject *kobj, + struct bin_attribute *bin_attr, + char *buf, loff_t off, size_t count) +{ + struct device *dev = container_of(kobj, struct device, kobj); + struct tspc104_bus *bus = dev_get_drvdata(dev); + unsigned int val; + int i; + + BUG_ON(count % 2 != 0); + + for (i = 0; i < count; i += 2) { + val = (unsigned int)(buf[i]); + val |= (unsigned int)(buf[i+1] << 8); + tspc104_io_write16_altpinout(bus, off + i, &val); + } + + return i; +} + +static ssize_t isa_mem16alt_read(struct file *filp, struct kobject *kobj, + struct bin_attribute *bin_attr, + char *buf, loff_t off, size_t count) +{ + struct device *dev = container_of(kobj, struct device, kobj); + struct tspc104_bus *bus = dev_get_drvdata(dev); + unsigned int val; + int i; + + for (i = 0; i < count; i += 2) { + tspc104_mem_read16_altpinout(bus, off + i, &val); + buf[i] = (char)val; + if (i <= count) + buf[i+1] = (char)(val >> 8); + } + + return i; +} + +static ssize_t isa_mem16alt_write(struct file *filp, struct kobject *kobj, + struct bin_attribute *bin_attr, + char *buf, loff_t off, size_t count) +{ + struct device *dev = container_of(kobj, struct device, kobj); + struct tspc104_bus *bus = dev_get_drvdata(dev); + unsigned int val; + int i; + + BUG_ON(count % 2 != 0); + + for (i = 0; i < count; i += 2) { + val = (unsigned int)(buf[i]); + val |= (unsigned int)(buf[i+1] << 8); + tspc104_mem_write16_altpinout(bus, off + i, &val); + } + + return i; +} + +struct bin_attribute isa_io8_attr = { + .attr = { + .name = "io8", + .mode = 0644, + }, + .size = PC104_ADDR_SPACE, + .read = isa_io8_read, + .write = isa_io8_write, +}; + +struct bin_attribute isa_mem8_attr = { + .attr = { + .name = "mem8", + .mode = 0644, + }, + .size = PC104_ADDR_SPACE, + .read = isa_mem8_read, + .write = isa_mem8_write, +}; + +struct bin_attribute isa_io16_attr = { + .attr = { + .name = "io16", + .mode = 0644, + }, + .size = PC104_ADDR_SPACE, + .read = isa_io16_read, + .write = isa_io16_write, +}; + +struct bin_attribute isa_mem16_attr = { + .attr = { + .name = "mem16", + .mode = 0644, + }, + .size = PC104_ADDR_SPACE, + .read = isa_mem16_read, + .write = isa_mem16_write, +}; + +struct bin_attribute isa_io16alt_attr = { + .attr = { + .name = "ioalt16", + .mode = 0644, + }, + .size = PC104_ADDR_SPACE, + .read = isa_io16alt_read, + .write = isa_io16alt_write, +}; + +struct bin_attribute isa_mem16alt_attr = { + .attr = { + .name = "memalt16", + .mode = 0644, + }, + .size = PC104_ADDR_SPACE, + .read = isa_mem16alt_read, + .write = isa_mem16alt_write, +}; + +static struct bin_attribute *tsisa_sysfs_bin_attrs[] = { + &isa_io8_attr, + &isa_mem8_attr, + &isa_io16_attr, + &isa_mem16_attr, + &isa_io16alt_attr, + &isa_mem16alt_attr, + NULL, +}; + +static const struct attribute_group tsisa_sysfs_group = { + .bin_attrs = tsisa_sysfs_bin_attrs, +}; + +static int technologic_isa_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct resource *mem; + struct tspc104_bus *bus; + int ret; + + bus = devm_kzalloc(dev, sizeof(*bus), GFP_KERNEL); + if (!bus) + return -ENOMEM; + + spin_lock_init(&bus->lock); + + ret = ts_pc104bus_init_pdata(pdev, bus); + if (ret < 0) + return ret; + + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!mem) { + dev_err(dev, "missing IOMEM\n"); + return -EINVAL; + } + + bus->reg = devm_ioremap(dev, mem->start, resource_size(mem)); + if (!bus->reg) { + dev_err(dev, "failed to remap I/O memory\n"); + return -ENXIO; + } + + gpiod_direction_output(bus->gpio_reset, 1); + msleep(20); + gpiod_set_value(bus->gpio_reset, 0); + + dev_set_drvdata(dev, bus); + ret = of_platform_populate(dev->of_node, NULL, NULL, dev); + if (ret < 0) + return ret; + + ret = sysfs_create_group(&dev->kobj, &tsisa_sysfs_group); + if (ret < 0) + return ret; + + dev_info(dev, "ready\n"); + + return 0; +} + +static const struct of_device_id tsisa_of_match[] = { + { .compatible = "technologic,pc104-bus", }, + {}, +}; + +static struct platform_driver tsisa_driver = { + .probe = technologic_isa_probe, + .driver = { + .name = "ts-pc104-bus", + .of_match_table = tsisa_of_match, + }, +}; +module_platform_driver(tsisa_driver); + +MODULE_ALIAS("platform:ts_pc104"); +MODULE_AUTHOR("Mark Featherston "); +MODULE_DESCRIPTION("embeddedTS ISA driver"); +MODULE_LICENSE("GPL v2"); diff --git a/include/linux/tspc104_bus.h b/include/linux/tspc104_bus.h new file mode 100644 index 0000000000000..d45ec5ad8ad77 --- /dev/null +++ b/include/linux/tspc104_bus.h @@ -0,0 +1,91 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef _TS_PC104_H +#define _TS_PC104_H + +#define TSISA_GOBSY (1 << 31) /* Addr if 0, go if 1 */ +#define TSISA_IO (1 << 30) /* io=1, mem=0 */ +#define TSISA_8BIT (1 << 29) /* 8bit=1, 16-bit=0 */ +#define TSISA_RDEN (1 << 28) /* read=1, write=0 */ +#define TSISA_TS (1 << 27) /* 1=TS PC104 pinout, 0=standard pinout */ + +struct tspc104_bus; + +extern int tspc104_reg_read(struct tspc104_bus *bus, unsigned int reg, + unsigned int *val, uint32_t flags); +extern int tspc104_reg_write(struct tspc104_bus *bus, unsigned int reg, + unsigned int *val, uint32_t flags); + +static inline int tspc104_io_read8(struct tspc104_bus *bus, unsigned int reg, + unsigned int *val) +{ + return tspc104_reg_read(bus, reg, val, TSISA_8BIT | TSISA_IO); +} + +static inline int tspc104_io_read16(struct tspc104_bus *bus, unsigned int reg, + unsigned int *val) +{ + return tspc104_reg_read(bus, reg, val, TSISA_IO); +} + +static inline int tspc104_mem_read8(struct tspc104_bus *bus, unsigned int reg, + unsigned int *val) +{ + return tspc104_reg_read(bus, reg, val, TSISA_8BIT); +} + +static inline int tspc104_mem_read16(struct tspc104_bus *bus, unsigned int reg, + unsigned int *val) +{ + return tspc104_reg_read(bus, reg, val, 0); +} + +static inline int tspc104_io_write8(struct tspc104_bus *bus, unsigned int reg, + unsigned int *val) +{ + return tspc104_reg_write(bus, reg, val, TSISA_8BIT | TSISA_IO); +} + +static inline int tspc104_io_write16(struct tspc104_bus *bus, unsigned int reg, + unsigned int *val) +{ + return tspc104_reg_write(bus, reg, val, TSISA_IO); +} + +static inline int tspc104_mem_write8(struct tspc104_bus *bus, unsigned int reg, + unsigned int *val) +{ + return tspc104_reg_write(bus, reg, val, TSISA_8BIT); +} + +static inline int tspc104_mem_write16(struct tspc104_bus *bus, unsigned int reg, + unsigned int *val) +{ + return tspc104_reg_write(bus, reg, val, 0); +} + +/* TS special pinout modes */ +static inline int tspc104_mem_write16_altpinout(struct tspc104_bus *bus, unsigned int reg, + unsigned int *val) +{ + return tspc104_reg_write(bus, reg, val, TSISA_TS); +} + +static inline int tspc104_mem_read16_altpinout(struct tspc104_bus *bus, unsigned int reg, + unsigned int *val) +{ + return tspc104_reg_read(bus, reg, val, TSISA_TS); +} + +static inline int tspc104_io_write16_altpinout(struct tspc104_bus *bus, unsigned int reg, + unsigned int *val) +{ + return tspc104_reg_write(bus, reg, val, TSISA_IO | TSISA_TS); +} + +static inline int tspc104_io_read16_altpinout(struct tspc104_bus *bus, unsigned int reg, + unsigned int *val) +{ + return tspc104_reg_read(bus, reg, val, TSISA_IO | TSISA_TS); +} + +#endif /* _TS_PC104_H */ From 03d901edb27efbb3264924df8bc47bc401fa3de4 Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Thu, 2 Mar 2023 14:16:31 -0700 Subject: [PATCH 035/244] irqchip: irq-ts71xxweim: Initial commit of FPGA IRQ expander for embeddedTS TS-7100/TS-7120/TS-7250-V3 --- drivers/irqchip/Kconfig | 8 ++ drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-ts71xxweim.c | 164 +++++++++++++++++++++++++++++++ 3 files changed, 173 insertions(+) create mode 100644 drivers/irqchip/irq-ts71xxweim.c diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index a61c6dc63c29c..7a93d99fb02b2 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -345,6 +345,14 @@ config TS4800_IRQ help Support for the TS-4800 FPGA IRQ controller +config TSWEIM_FPGA_INTC + tristate "TS-71XX WEIM FPGA IRQ Support" + default n + help + Select this option if you have a embeddedTS TS-71XX SBC. + This driver is necessary to support the in FPGA IRQ controller + that is present on the WEIM bus. + config VERSATILE_FPGA_IRQ bool select IRQ_DOMAIN diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 3de083f5484cc..077d2d8af7f30 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -62,6 +62,7 @@ obj-$(CONFIG_ARCH_VT8500) += irq-vt8500.o obj-$(CONFIG_ST_IRQCHIP) += irq-st.o obj-$(CONFIG_TB10X_IRQC) += irq-tb10x.o obj-$(CONFIG_TS4800_IRQ) += irq-ts4800.o +obj-$(CONFIG_TSWEIM_FPGA_INTC) += irq-ts71xxweim.o obj-$(CONFIG_XTENSA) += irq-xtensa-pic.o obj-$(CONFIG_XTENSA_MX) += irq-xtensa-mx.o obj-$(CONFIG_XILINX_INTC) += irq-xilinx-intc.o diff --git a/drivers/irqchip/irq-ts71xxweim.c b/drivers/irqchip/irq-ts71xxweim.c new file mode 100644 index 0000000000000..de96ddc219636 --- /dev/null +++ b/drivers/irqchip/irq-ts71xxweim.c @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include +#include +#include +#include +#include + +#define TSWEIM_IRQ_STATUS 0x24 +#define TSWEIM_IRQ_MASK 0x48 +#define TSWEIM_NUM_FPGA_IRQ 32 + +static struct tsweim_intc_priv { + void __iomem *syscon; + struct irq_domain *irqdomain; + int irq; + u32 mask; +} priv; + +static const struct of_device_id tsweim_intc_of_match_table[] = { + {.compatible = "technologic,ts71xxweim-intc", }, + {}, +}; +MODULE_DEVICE_TABLE(of, tsweim_intc_of_match_table); + +static void tsweim_intc_mask(struct irq_data *d) +{ + priv.mask = readl(priv.syscon + TSWEIM_IRQ_MASK) & ~BIT(d->hwirq); + writel(priv.mask, priv.syscon + TSWEIM_IRQ_MASK); +} + +static void tsweim_intc_unmask(struct irq_data *d) +{ + priv.mask = readl(priv.syscon + TSWEIM_IRQ_MASK) | BIT(d->hwirq); + writel(priv.mask, priv.syscon + TSWEIM_IRQ_MASK); +} + +static void tsweim_irq_handler(struct irq_desc *desc) +{ + struct irq_chip *chip = irq_desc_get_chip(desc); + unsigned int irq; + unsigned int status; + + chained_irq_enter(chip, desc); + + while ((status = + (priv.mask & readl(priv.syscon + TSWEIM_IRQ_STATUS)))) { + irq = 0; + do { + if (status & 1) { + generic_handle_irq(irq_linear_revmap( + priv.irqdomain, irq)); + } + status >>= 1; + irq++; + } while (status); + } + + chained_irq_exit(chip, desc); +} + +static struct irq_chip tsweim_irq_chip = { + .name = "tsweim_intc", + .irq_mask = tsweim_intc_mask, + .irq_unmask = tsweim_intc_unmask, +}; + +static int tsweim_intc_irqdomain_map(struct irq_domain *d, + unsigned int irq, irq_hw_number_t hwirq) +{ + irq_set_chip_and_handler(irq, &tsweim_irq_chip, + handle_level_irq); + + irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE); + irq_set_status_flags(irq, IRQ_LEVEL); + + return 0; +} + +static const struct irq_domain_ops tsweim_intc_irqdomain_ops = { + .map = tsweim_intc_irqdomain_map, +}; + +static int tsweim_intc_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + const struct of_device_id *match; + struct device_node *np = pdev->dev.of_node; + void __iomem *membase; + struct resource *res = 0; + + match = of_match_device(tsweim_intc_of_match_table, dev); + if (!match) + return -EINVAL; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + if (res == NULL) { + pr_err("Can't get device address\n"); + return -EFAULT; + } + + membase = devm_ioremap(&pdev->dev, res->start, resource_size(res)); + if (IS_ERR(membase)) { + pr_err("Could not map resource\n"); + return -ENOMEM; + } + + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (res == NULL) { + pr_err("Can't get interrupt\n"); + return -EFAULT; + } + + priv.irq = res->start; + priv.syscon = membase; + + priv.irqdomain = irq_domain_add_linear( + np, TSWEIM_NUM_FPGA_IRQ, &tsweim_intc_irqdomain_ops, &priv); + + if (!priv.irqdomain) { + pr_err("%s: unable to add irq domain\n", np->name); + return -ENOMEM; + } + + irq_set_handler_data(priv.irq, &priv); + irq_set_chained_handler(priv.irq, tsweim_irq_handler); + + platform_set_drvdata(pdev, &priv); + + return 0; +} + +static int tsweim_intc_remove(struct platform_device *pdev) +{ + if (priv.irqdomain) { + int i, irq; + + for (i = 0; i < TSWEIM_NUM_FPGA_IRQ; i++) { + irq = irq_find_mapping(priv.irqdomain, i); + if (irq > 0) + irq_dispose_mapping(irq); + } + irq_domain_remove(priv.irqdomain); + priv.irqdomain = NULL; + } + + return 0; +} + +static struct platform_driver tsweim_intc_driver = { + .driver = { + .name = "tsweim-intc", + .of_match_table = of_match_ptr(tsweim_intc_of_match_table), + }, + .probe = tsweim_intc_probe, + .remove = tsweim_intc_remove, +}; +module_platform_driver(tsweim_intc_driver); + +MODULE_AUTHOR("embeddedTS"); +MODULE_DESCRIPTION("Interrupt Controller for embeddedTS FPGA platforms connected with WEIM"); +MODULE_LICENSE("GPL"); From f36b334b408586cecf23aa427ab52e6cdb56157f Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Thu, 2 Mar 2023 14:18:07 -0700 Subject: [PATCH 036/244] gpio: ts71xxweim: Initial commit of WEIM 16-bit GPIO driver for embeddedTS TS-7100/TS-7120/TS-7250-V3 --- drivers/gpio/Kconfig | 9 ++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-ts71xxweim.c | 171 +++++++++++++++++++++++++++++++++ 3 files changed, 181 insertions(+) create mode 100644 drivers/gpio/gpio-ts71xxweim.c diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index e053524c5e35f..9b4995e1d743f 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -888,6 +888,15 @@ config GPIO_LOONGSON1 help Say Y or M here to support GPIO on Loongson1 SoCs. +config GPIO_TS71XXWEIM + bool "embeddedTS WEIM FPGA GPIO" + depends on IMX_WEIM + help + Say yes here to enable the GPIO driver for embeddedTS's FPGA core + connected to the i.MX6UL WEIM bus. + + Compatible with TS-7120, TS-7250-V3, TS-7100, and similar + config GPIO_AMD_FCH tristate "GPIO support for AMD Fusion Controller Hub (G-series SOCs)" help diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index ec296fa14bfdb..e94ac4ea68059 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -191,6 +191,7 @@ obj-$(CONFIG_GPIO_TQMX86) += gpio-tqmx86.o obj-$(CONFIG_GPIO_TS4800) += gpio-ts4800.o obj-$(CONFIG_GPIO_TS4900) += gpio-ts4900.o obj-$(CONFIG_GPIO_TS5500) += gpio-ts5500.o +obj-$(CONFIG_GPIO_TS71XXWEIM) += gpio-ts71xxweim.o obj-$(CONFIG_GPIO_TWL4030) += gpio-twl4030.o obj-$(CONFIG_GPIO_TWL6040) += gpio-twl6040.o obj-$(CONFIG_GPIO_UNIPHIER) += gpio-uniphier.o diff --git a/drivers/gpio/gpio-ts71xxweim.c b/drivers/gpio/gpio-ts71xxweim.c new file mode 100644 index 0000000000000..72827a418d93b --- /dev/null +++ b/drivers/gpio/gpio-ts71xxweim.c @@ -0,0 +1,171 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Digital I/O driver for embeddedTS TS-7120, TS-7100, et al. + * Copyright (C) 2022 Technologic Systems, Inc. dba embeddedTS + */ + +#include +#include +#include +#include + +/* Most that this driver can currently support in a single bank is 16. This is + * due simply to how the FPGA used for these devices is structured. + */ +#define TSWEIM_NR_DIO 16 + +/* Register offsets from the 'reg' value passed in device tree source */ +#define TSWEIM_SET_REG 0x00 +#define TSWEIM_GET_REG 0x00 +#define TSWEIM_EN_SET_REG 0x02 +#define TSWEIM_CLR_REG 0x04 +#define TSWEIM_EN_CLR_REG 0x06 + +struct tsweim_gpio_priv { + void __iomem *syscon; + struct gpio_chip gpio_chip; +}; + +static inline struct tsweim_gpio_priv *to_gpio_tsweim(struct gpio_chip *chip) +{ + return container_of(chip, struct tsweim_gpio_priv, gpio_chip); +} + +static int tsweim_gpio_direction_input(struct gpio_chip *chip, + unsigned int offset) +{ + struct tsweim_gpio_priv *priv = to_gpio_tsweim(chip); + + if (!(offset < priv->gpio_chip.ngpio)) + return -EINVAL; + + writew((1 << offset), priv->syscon + TSWEIM_EN_CLR_REG); + + return 0; +} + +static int tsweim_gpio_direction_output(struct gpio_chip *chip, + unsigned int offset, int value) +{ + struct tsweim_gpio_priv *priv = to_gpio_tsweim(chip); + + if (!(offset < priv->gpio_chip.ngpio)) + return -EINVAL; + + if (value) + writew((1 << offset), priv->syscon + TSWEIM_SET_REG); + else + writew((1 << offset), priv->syscon + TSWEIM_CLR_REG); + + writew((1 << offset), priv->syscon + TSWEIM_EN_SET_REG); + + return 0; +} + +static int tsweim_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + struct tsweim_gpio_priv *priv = to_gpio_tsweim(chip); + uint16_t reg; + + if (!(offset < priv->gpio_chip.ngpio)) + return -EINVAL; + + reg = readw(priv->syscon + TSWEIM_GET_REG); + return !!(reg & (1 << offset)); +} + +static void tsweim_gpio_set(struct gpio_chip *chip, unsigned int offset, + int value) +{ + struct tsweim_gpio_priv *priv = to_gpio_tsweim(chip); + + if (!(offset < priv->gpio_chip.ngpio)) + return; + + if (value) + writew((1 << offset), priv->syscon + TSWEIM_SET_REG); + else + writew((1 << offset), priv->syscon + TSWEIM_CLR_REG); +} + +static const struct gpio_chip template_chip = { + .label = "tsweim-gpio", + .owner = THIS_MODULE, + .direction_input = tsweim_gpio_direction_input, + .direction_output = tsweim_gpio_direction_output, + .get = tsweim_gpio_get, + .set = tsweim_gpio_set, + .base = -1, + .can_sleep = false, +}; + +static const struct of_device_id tsweim_gpio_of_match_table[] = { + { .compatible = "technologic,ts71xxweim-gpio", }, + {}, +}; +MODULE_DEVICE_TABLE(of, tsweim_gpio_of_match_table); + +static int tsweim_gpio_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + const struct of_device_id *match; + struct tsweim_gpio_priv *priv; + u32 ngpio; + int base; + void __iomem *membase; + struct resource *res; + + match = of_match_device(tsweim_gpio_of_match_table, dev); + if (!match) + return -EINVAL; + + if (of_property_read_u32(dev->of_node, "ngpios", &ngpio)) + ngpio = TSWEIM_NR_DIO; + + if (of_property_read_u32(dev->of_node, "base", &base)) + base = -1; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) { + pr_err("Can't get device address\n"); + return -EFAULT; + } + + membase = devm_ioremap(&pdev->dev, res->start, + resource_size(res)); + if (IS_ERR(membase)) { + pr_err("Could not map resource\n"); + return -ENOMEM; + } + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->syscon = membase; + + pr_info("FPGA syscon mapped to 0x%08X, %d bytes\n", + (unsigned int)priv->syscon, resource_size(res)); + + priv->gpio_chip = template_chip; + priv->gpio_chip.label = "tsweim-gpio"; + priv->gpio_chip.ngpio = ngpio; + priv->gpio_chip.base = base; + pdev->dev.platform_data = &priv; + priv->gpio_chip.of_node = pdev->dev.of_node; + + return devm_gpiochip_add_data(&pdev->dev, &priv->gpio_chip, &priv); +} + +static struct platform_driver tsweim_gpio_driver = { + .driver = { + .name = "tsweim-gpio", + .of_match_table = of_match_ptr(tsweim_gpio_of_match_table), + }, + .probe = tsweim_gpio_probe, +}; +module_platform_driver(tsweim_gpio_driver); + +MODULE_AUTHOR("embeddedTS"); +MODULE_DESCRIPTION("GPIO interface for embeddedTS WEIM FPGA"); +MODULE_LICENSE("GPL"); From cb62dbca58f7d418ea7143d8ca315280afaa55c5 Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Thu, 2 Mar 2023 14:27:26 -0700 Subject: [PATCH 037/244] serial: 8250: 8250_ts: initial commit Signed-off-by: Mark Featherston Signed-off-by: Kris Bahnsen --- drivers/tty/serial/8250/8250_ts.c | 75 +++++++++++++++++++++++++++++++ drivers/tty/serial/8250/Kconfig | 6 +++ drivers/tty/serial/8250/Makefile | 1 + include/uapi/linux/serial.h | 1 + 4 files changed, 83 insertions(+) create mode 100644 drivers/tty/serial/8250/8250_ts.c diff --git a/drivers/tty/serial/8250/8250_ts.c b/drivers/tty/serial/8250/8250_ts.c new file mode 100644 index 0000000000000..ce17e3469f2d8 --- /dev/null +++ b/drivers/tty/serial/8250/8250_ts.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include +#include +#include +#include +#include +#include + +static unsigned int tsisa_serial_in(struct uart_port *p, int offset) +{ + struct tspc104_bus *bus = (struct tspc104_bus *)p->private_data; + unsigned int value; + + tspc104_io_read8(bus, p->mapbase + offset, &value); + return value; +} + +static void tsisa_serial_out(struct uart_port *p, int offset, int value) +{ + struct tspc104_bus *bus = (struct tspc104_bus *)p->private_data; + tspc104_io_write8(bus, p->mapbase + offset, &value); +} + +static int technologic_ts16550_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct uart_8250_port uport; + struct uart_port *port; + const __be32 *addr_be; + + memset(&uport, 0, sizeof(uport)); + + addr_be = of_get_property(dev->of_node, "reg", NULL); + if (!addr_be) + return -ENODEV; + + port = &uport.port; + port->irq = platform_get_irq(pdev, 0); + if (port->irq < 0) + return port->irq; + + port->mapbase = be32_to_cpup(addr_be); + port->flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | + UPF_FIXED_PORT | UPF_FIXED_TYPE; + port->iotype = UPIO_MEM; + port->irqflags = IRQF_TRIGGER_HIGH; + port->private_data = platform_get_drvdata(to_platform_device(pdev->dev.parent)); + port->uartclk = 1843200; + port->type = PORT_16550A; + port->serial_in = tsisa_serial_in; + port->serial_out = tsisa_serial_out; + + return serial8250_register_8250_port(&uport); +} + +static const struct of_device_id ts16550_of_match[] = { + { .compatible = "technologic,ts16550", }, + {}, +}; + +static struct platform_driver ts16550_driver = { + .probe = technologic_ts16550_probe, + .driver = { + .name = "ts16550", + .of_match_table = ts16550_of_match, + }, +}; +module_platform_driver(ts16550_driver); + +MODULE_ALIAS("platform:ts16550"); +MODULE_AUTHOR("Mark Featherston "); +MODULE_DESCRIPTION("embeddedTS 16550 PC104 driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/tty/serial/8250/Kconfig b/drivers/tty/serial/8250/Kconfig index f64ef0819cd4e..a20308e8d826c 100644 --- a/drivers/tty/serial/8250/Kconfig +++ b/drivers/tty/serial/8250/Kconfig @@ -582,6 +582,12 @@ config SERIAL_8250_NI To compile this driver as a module, choose M here: the module will be called 8250_ni. +config SERIAL_8250_TS + tristate "TS-16550 Driver" + help + Enables support for a generic ISA 16550. Used with the + TS-SER4, TS-SER2, TS-IS0485, TS-MULTI104, and others. + config SERIAL_OF_PLATFORM tristate "Devicetree based probing for 8250 ports" depends on SERIAL_8250 && OF diff --git a/drivers/tty/serial/8250/Makefile b/drivers/tty/serial/8250/Makefile index 9ec4d5fe64de5..8e4128ff728e7 100644 --- a/drivers/tty/serial/8250/Makefile +++ b/drivers/tty/serial/8250/Makefile @@ -55,5 +55,6 @@ obj-$(CONFIG_SERIAL_8250_RT288X) += 8250_rt288x.o obj-$(CONFIG_SERIAL_8250_CS) += serial_cs.o obj-$(CONFIG_SERIAL_8250_UNIPHIER) += 8250_uniphier.o obj-$(CONFIG_SERIAL_8250_TEGRA) += 8250_tegra.o +obj-$(CONFIG_SERIAL_8250_TS) += 8250_ts.o CFLAGS_8250_ingenic.o += -I$(srctree)/scripts/dtc/libfdt diff --git a/include/uapi/linux/serial.h b/include/uapi/linux/serial.h index de9b4733607e6..23c1a9fde5567 100644 --- a/include/uapi/linux/serial.h +++ b/include/uapi/linux/serial.h @@ -72,6 +72,7 @@ struct serial_struct { #define SERIAL_IO_TSI 5 #define SERIAL_IO_MEM32BE 6 #define SERIAL_IO_MEM16 7 +#define SERIAL_IO_TSISABUS 8 #define UART_CLEAR_FIFO 0x01 #define UART_USE_FIFO 0x02 From 0a633ab4f854681a01eecdddeaa8403c1589b6e1 Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Thu, 2 Mar 2023 14:28:48 -0700 Subject: [PATCH 038/244] spi: oc: Initial commit of SPI OpenCores driver --- drivers/spi/Kconfig | 5 + drivers/spi/Makefile | 1 + drivers/spi/spi-oc.c | 548 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 554 insertions(+) create mode 100644 drivers/spi/spi-oc.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 1872f9d54a5cc..126d474a10928 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -800,6 +800,11 @@ config SPI_OCTEON SPI host driver for the hardware found on some Cavium OCTEON SOCs. +config SPI_OCORES + tristate "OpenCores SPI Controller" + help + This enables using the OpenCores SPI controller. + config SPI_OMAP_UWIRE tristate "OMAP1 MicroWire" depends on ARCH_OMAP1 || (ARM && COMPILE_TEST) diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 1f7c06a3091d9..b96ca5ca342a8 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -102,6 +102,7 @@ obj-$(CONFIG_SPI_NPCM_FIU) += spi-npcm-fiu.o obj-$(CONFIG_SPI_NPCM_PSPI) += spi-npcm-pspi.o obj-$(CONFIG_SPI_NXP_FLEXSPI) += spi-nxp-fspi.o obj-$(CONFIG_SPI_OC_TINY) += spi-oc-tiny.o +obj-$(CONFIG_SPI_OCORES) += spi-oc.o spi-octeon-objs := spi-cavium.o spi-cavium-octeon.o obj-$(CONFIG_SPI_OCTEON) += spi-octeon.o obj-$(CONFIG_SPI_OMAP_UWIRE) += spi-omap-uwire.o diff --git a/drivers/spi/spi-oc.c b/drivers/spi/spi-oc.c new file mode 100644 index 0000000000000..7d37028d9b915 --- /dev/null +++ b/drivers/spi/spi-oc.c @@ -0,0 +1,548 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2007-2008 Avionic Design Development GmbH + * Copyright (C) 2008-2009 Avionic Design GmbH + * Written by Thierry Reding + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* register definitions */ +#define SPIOC_RX(i) (i * 4) +#define SPIOC_TX(i) (i * 4) +#define SPIOC_CTRL 0x10 +#define SPIOC_DIV 0x14 +#define SPIOC_SS 0x18 + +/* SPIOC_CTRL register */ +#define CTRL_LEN(x) ((x < 128) ? x : 0) +#define CTRL_BUSY (1 << 8) +#define CTRL_RXNEG (1 << 9) +#define CTRL_TXNEG (1 << 10) +#define CTRL_LSB (1 << 11) +#define CTRL_IE (1 << 12) +#define CTRL_ASS (1 << 13) +#define CTRL_CPOL (1 << 14) +#define CTRL_CPHA (1 << 15) + +/** + * struct spioc - driver-specific context information + * @controller: SPI controller device + * @info: pointer to platform data + * @clk: SPI controller clock + * @irq: SPI controller interrupt + * @mmio: physical I/O memory resource + * @base: base of memory-mapped I/O + * @message: current SPI message + * @transfer: current transfer of current SPI message + * @nx: number of bytes sent/received for current transfer + * @queue: SPI message queue + */ +struct spioc { + struct spi_controller *controller; + struct clk *clk; + int irq; + u32 idx; + struct platform_device *pdev; + s16 bus_num; + u16 num_chipselect; + struct resource *mmio; + void __iomem *base; + struct spi_message *message; + struct spi_transfer *transfer; + unsigned long nx; + struct list_head queue; + struct workqueue_struct *workqueue; + struct work_struct process_messages; + struct tasklet_struct process_transfers; + + spinlock_t lock; +}; + +static inline u32 spioc_read(struct spioc *spioc, unsigned long offset) +{ + return readl(spioc->base + offset); +} + +static inline void spioc_write(struct spioc *spioc, unsigned int offset, + u32 value) +{ + writel(value, spioc->base + offset); +} + +static void spioc_chipselect(struct spioc *controller, struct spi_device *spi) +{ + if (spi) + spioc_write(controller, SPIOC_SS, 1 << spi->chip_select); + else + spioc_write(controller, SPIOC_SS, 0); +} + +/* + * count is assumed to be less than or equal to the maximum number of bytes + * that can be transferred in one go + */ +static void spioc_copy_tx(struct spioc *spioc, const void *src, size_t count) +{ + u32 val = 0; + int i; + + for (i = 0; i < count; i++) { + int rem = count - i; + int reg = (rem - 1) / 4; + int ofs = (rem - 1) % 4; + + val |= (((u8 *)src)[i] & 0xff) << (ofs * 8); + if (!ofs) { + spioc_write(spioc, SPIOC_TX(reg), val); + val = 0; + } + } +} + +static void spioc_copy_rx(struct spioc *spioc, void *dest, size_t count) +{ + u32 val = 0; + int i; + + for (i = 0; i < count; i++) { + int rem = count - i; + int reg = (rem - 1) / 4; + int ofs = (rem - 1) % 4; + + if ((i == 0) || (rem % 4 == 0)) + val = spioc_read(spioc, SPIOC_RX(reg)); + + ((u8 *)dest)[i] = (val >> (ofs * 8)) & 0xff; + } +} + +static void process_messages(struct work_struct *work) +{ + struct spioc *spioc = + container_of(work, struct spioc, process_messages); + unsigned long flags; + + spin_lock_irqsave(&spioc->lock, flags); + + /* obtain next message */ + if (list_empty(&spioc->queue)) { + spin_unlock_irqrestore(&spioc->lock, flags); + return; + } + + spioc->message = list_entry(spioc->queue.next, struct spi_message, + queue); + list_del_init(&spioc->message->queue); + + /* process transfers */ + tasklet_schedule(&spioc->process_transfers); + spin_unlock_irqrestore(&spioc->lock, flags); +} + +static void process_transfers(unsigned long data) +{ + struct spioc *spioc = (struct spioc *)data; + struct spi_transfer *transfer = spioc->transfer; + size_t rem; + u32 ctrl; + + /* + * if this is the start of a message, get a pointer to the first + * transfer + */ + if (!transfer || (spioc->nx >= transfer->len)) { + if (!transfer) { + transfer = list_entry(spioc->message->transfers.next, + struct spi_transfer, transfer_list); + spioc_chipselect(spioc, spioc->message->spi); + } else { + struct list_head *next = transfer->transfer_list.next; + + if (next != &spioc->message->transfers) { + transfer = list_entry(next, + struct spi_transfer, + transfer_list); + } else { + complete(spioc->message->context); + spioc->transfer = NULL; + spioc->message->status = 0; + spioc_chipselect(spioc, NULL); + return; + } + } + + spioc->transfer = transfer; + spioc->nx = 0; + spioc->message->actual_length += transfer->len; + } + + /* write data to registers */ + rem = min_t(size_t, transfer->len - spioc->nx, 16); + if (transfer->tx_buf) + spioc_copy_tx(spioc, transfer->tx_buf + spioc->nx, rem); + + /* read control register */ + ctrl = spioc_read(spioc, SPIOC_CTRL); + ctrl &= ~CTRL_LEN(127); /* clear length bits */ + ctrl &= ~CTRL_ASS; /* Disable automatic CS control */ + ctrl |= CTRL_IE /* assert interrupt on completion */ + | CTRL_LEN(rem * 8); /* set word length */ + spioc_write(spioc, SPIOC_CTRL, ctrl); + + /* start transfer */ + ctrl |= CTRL_BUSY; + spioc_write(spioc, SPIOC_CTRL, ctrl); +} + +static int spioc_setup(struct spi_device *spi) +{ + struct spioc *spioc = spi_controller_get_devdata(spi->controller); + unsigned long clkdiv = 0x0000ffff; + u32 ctrl = spioc_read(spioc, SPIOC_CTRL); + + /* make sure we're not busy */ + BUG_ON(ctrl & CTRL_BUSY); + + if (!spi->bits_per_word) + spi->bits_per_word = 8; + + if (spi->mode & SPI_LSB_FIRST) + ctrl |= CTRL_LSB; + else + ctrl &= ~CTRL_LSB; + + ctrl &= ~(CTRL_RXNEG | CTRL_TXNEG | CTRL_CPOL | CTRL_CPHA); + if (spi->mode & SPI_CPOL) + ctrl |= CTRL_CPOL; + if (spi->mode & SPI_CPHA) + ctrl |= CTRL_CPHA; + + /* + * used on older versions of the controller without cpol/cpha, ignored + * on newer controllers + */ + if (spi->mode & SPI_CPHA) + ctrl |= CTRL_RXNEG; + else + ctrl |= CTRL_TXNEG; + + /* set the clock divider */ + if (spi->max_speed_hz) + clkdiv = DIV_ROUND_UP(clk_get_rate(spioc->clk), + 2 * spi->max_speed_hz) - 1; + + if (clkdiv > 0x0000ffff) + clkdiv = 0x0000ffff; + + spioc_write(spioc, SPIOC_DIV, clkdiv); + spioc_write(spioc, SPIOC_CTRL, ctrl); + + /* deassert chip-select */ + spioc_chipselect(spioc, NULL); + + return 0; +} + +static int spioc_transfer(struct spi_device *spi, struct spi_message *message) +{ + struct spioc *spioc = spi_controller_get_devdata(spi->controller); + unsigned long flags; + + spin_lock_irqsave(&spioc->lock, flags); + + message->actual_length = 0; + message->status = -EINPROGRESS; + + list_add_tail(&message->queue, &spioc->queue); + queue_work(spioc->workqueue, &spioc->process_messages); + + spin_unlock_irqrestore(&spioc->lock, flags); + return 0; +} + +static void spioc_cleanup(struct spi_device *spi) +{ +} + +static irqreturn_t spioc_interrupt(int irq, void *dev_id) +{ + struct spioc *spioc = (struct spioc *)dev_id; + struct spi_transfer *transfer; + size_t rem; + u32 ctrl; + + if (!spioc) + return IRQ_NONE; + + transfer = spioc->transfer; + ctrl = spioc_read(spioc, SPIOC_CTRL); + BUG_ON(ctrl & CTRL_BUSY); + + /* read data from registers */ + rem = min_t(size_t, transfer->len - spioc->nx, 16); + if (transfer->rx_buf) + spioc_copy_rx(spioc, transfer->rx_buf + spioc->nx, rem); + spioc->nx += rem; + + tasklet_schedule(&spioc->process_transfers); + + return IRQ_HANDLED; +} + +static int init_queue(struct spi_controller *controller, const char *buf) +{ + struct spioc *spioc = spi_controller_get_devdata(controller); + + if (spioc == NULL) { + pr_err("%s %d error\n", __func__, __LINE__); + return -EBUSY; + } + + /* initialize message workqueue */ + INIT_LIST_HEAD(&spioc->queue); + spin_lock_init(&spioc->lock); + INIT_WORK(&spioc->process_messages, process_messages); + + /* initialize transfer processing tasklet */ + tasklet_init(&spioc->process_transfers, process_transfers, + (unsigned long)spioc); + + spioc->workqueue = create_singlethread_workqueue( + dev_name(controller->dev.parent)); + + if (!spioc->workqueue) + return -EBUSY; + + return 0; +} + +static int start_queue(struct spi_controller *controller) +{ + struct spioc *spioc = spi_controller_get_devdata(controller); + + WARN_ON(spioc->message != NULL); + WARN_ON(spioc->transfer != NULL); + + spioc->message = NULL; + spioc->transfer = NULL; + + queue_work(spioc->workqueue, &spioc->process_messages); + return 0; +} + +static int stop_queue(struct spi_controller *controller) +{ + return 0; +} + +static int destroy_queue(struct spi_controller *controller) +{ + struct spioc *spioc = spi_controller_get_devdata(controller); + int retval = 0; + + retval = stop_queue(controller); + if (retval) + return retval; + + destroy_workqueue(spioc->workqueue); + return 0; +} + + +static const struct of_device_id opencores_spi_match[] = { + { .compatible = "opencores,spi-oc" }, + {}, +}; +MODULE_DEVICE_TABLE(of, opencores_spi_match); + + +static int spioc_probe(struct platform_device *pdev) +{ + struct resource *res = NULL; + void __iomem *mmio = NULL; + int retval = 0, irq; + struct spi_controller *controller = NULL; + struct spioc *spioc = NULL; + struct device_node *node = pdev->dev.of_node; + char buf[16]; + u32 idx, num_chipselect; + + if (of_property_read_u32(node, "opencores-spi,idx", &idx) < 0) { + dev_warn(&pdev->dev, "Node idx not defined, assuming 0\n"); + idx = 0; + } + + if (of_property_read_u32(node, "opencores-spi,num-chipselects", + &num_chipselect) < 0) { + dev_warn(&pdev->dev, "Node num_chipselect not defined, assuming 1\n"); + num_chipselect = 1; + } + + controller = spi_alloc_host(&pdev->dev, sizeof(struct spioc)); + if (controller == NULL) { + dev_err(&pdev->dev, "unable to allocate SPI controller\n"); + return -ENOMEM; + } + spioc = spi_controller_get_devdata(controller); + platform_set_drvdata(pdev, controller); + + snprintf(buf, sizeof(buf), "spi_oc_%d", idx); + + irq = irq_of_parse_and_map(pdev->dev.of_node, 0); + if (irq < 0) { + dev_err(&pdev->dev, "IRQ not defined\n"); + return -ENXIO; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "MMIO resource not defined\n"); + return -ENXIO; + } + + mmio = devm_ioremap(&pdev->dev, res->start, + resource_size(res)); + if (IS_ERR(mmio)) { + dev_err(&pdev->dev, "can't remap I/O region\n"); + retval = PTR_ERR(mmio); + goto err1; + } + + controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; + controller->setup = spioc_setup; + controller->transfer = spioc_transfer; + controller->cleanup = spioc_cleanup; + controller->dev.of_node = pdev->dev.of_node; + controller->bus_num = pdev->id; + controller->num_chipselect = num_chipselect; + + spioc->controller = controller; + spioc->pdev = pdev; + + spioc->idx = idx; + spioc->irq = irq; + spioc->mmio = res; + spioc->base = mmio; + spioc->message = NULL; + spioc->transfer = NULL; + spioc->bus_num = pdev->id; + spioc->num_chipselect = num_chipselect; + spioc->nx = 0; + + spioc->clk = devm_clk_get(&pdev->dev, "spi-oc-clk"); + if (IS_ERR(spioc->clk)) { + dev_err(&pdev->dev, "unable to get SPI controller clock\n"); + retval = PTR_ERR(spioc->clk); + spioc->clk = NULL; + goto err1; + } + + retval = init_queue(controller, buf); + if (retval) { + dev_err(&pdev->dev, "unable to initialize workqueue\n"); + goto free; + } + + retval = start_queue(controller); + if (retval) { + dev_err(&pdev->dev, "unable to start workqueue\n"); + goto free; + } + + retval = devm_request_irq(&pdev->dev, irq, spioc_interrupt, 0, + "spioc", spioc); + if (retval) { + dev_err(&pdev->dev, "unable to install handler for IRQ #%d\n", irq); + retval = -EPROBE_DEFER; + goto free; + } + + dev_info(&pdev->dev, "IRQ: %d, CLK: %ldHz\n", + irq, clk_get_rate(spioc->clk)); + + retval = devm_spi_register_controller(&pdev->dev, controller); + if (retval) { + dev_err(&pdev->dev, "unable to register SPI controller\n"); + retval = -ENOMEM; + goto free; + } + + dev_info(&pdev->dev, "SPI controller %d registered\n", idx); + +out: + return retval; + +free: + destroy_queue(controller); + +err1: + spi_controller_put(controller); + goto out; +} + +static void spioc_remove(struct platform_device *pdev) +{ + struct spi_controller *controller = platform_get_drvdata(pdev); + + if (controller) { + spi_controller_get(controller); + platform_set_drvdata(pdev, NULL); + destroy_queue(controller); + spi_controller_put(controller); + } +} + +#ifdef CONFIG_PM +static int spioc_suspend(struct platform_device *pdev, pm_message_t state) +{ + return 0; +} + +static int spioc_resume(struct platform_device *pdev) +{ + return 0; +} +#else +#define spioc_suspend NULL +#define spioc_resume NULL +#endif /* CONFIG_PM */ + +static struct platform_driver spioc_driver = { + .probe = spioc_probe, + .remove = spioc_remove, + .suspend = spioc_suspend, + .resume = spioc_resume, + .driver = { + .name = "spioc", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(opencores_spi_match), + }, +}; + +static int __init spioc_init(void) +{ + return platform_driver_register(&spioc_driver); +} + +static void __exit spioc_exit(void) +{ + platform_driver_unregister(&spioc_driver); +} + +module_init(spioc_init); +module_exit(spioc_exit); + +MODULE_AUTHOR("Thierry Reding "); +MODULE_DESCRIPTION("OpenCores SPI controller driver"); +MODULE_LICENSE("GPL v2"); + From cbae5278ce772deae826be2b91bbd81cef87763a Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Thu, 2 Mar 2023 14:32:13 -0700 Subject: [PATCH 039/244] iio: adc: ts_simple_adc: Initial commit of simple FPGA ADC controller --- drivers/iio/adc/Kconfig | 9 ++ drivers/iio/adc/Makefile | 1 + drivers/iio/adc/ts_simple_adc.c | 217 ++++++++++++++++++++++++++++++++ 3 files changed, 227 insertions(+) create mode 100644 drivers/iio/adc/ts_simple_adc.c diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 58a14e6833f60..2768033addaa1 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -1796,6 +1796,15 @@ config TI_TSC2046 This driver can also be built as a module. If so, the module will be called ti-tsc2046. +config TS_SIMPLEADC + tristate "embeddedTS simple FPGA ADC" + depends on OF + depends on HAS_IOMEM + select IIO_BUFFER + select IIO_KFIFO_BUF + help + Say yes here to build support for embeddedTS FPGA based ADC. + config TWL4030_MADC tristate "TWL4030 MADC (Monitoring A/D Converter)" depends on TWL4030_CORE diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index d008f78dc010a..7c0d4fce2ba9e 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -156,6 +156,7 @@ obj-$(CONFIG_TI_AM335X_ADC) += ti_am335x_adc.o obj-$(CONFIG_TI_LMP92064) += ti-lmp92064.o obj-$(CONFIG_TI_TLC4541) += ti-tlc4541.o obj-$(CONFIG_TI_TSC2046) += ti-tsc2046.o +obj-$(CONFIG_TS_SIMPLEADC) += ts_simple_adc.o obj-$(CONFIG_TWL4030_MADC) += twl4030-madc.o obj-$(CONFIG_TWL6030_GPADC) += twl6030-gpadc.o obj-$(CONFIG_VF610_ADC) += vf610_adc.o diff --git a/drivers/iio/adc/ts_simple_adc.c b/drivers/iio/adc/ts_simple_adc.c new file mode 100644 index 0000000000000..70fd1fe60287a --- /dev/null +++ b/drivers/iio/adc/ts_simple_adc.c @@ -0,0 +1,217 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ADC driver for simple 8-bit ADC on TS-7250-V3 + * Copyright (C) 2021-2022 Technologic Systems, Inc. dba embeddedTS + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Core is 4 bytes wide in total. + * Base + 0x00: ADCFLAGS + * bits 15-3: Reserved + * bit 2: sample_missed (RW) + * Data in 0x02 was overwritten without being read + * (cleared on write or sample read) + * bit 1: sample_ready (RO) + * Data in 0x02 is new and has not been read + * (cleared on write or sample read) + * bit 0: standby (RW, default 1) - Stop sampling ADC + * Base + 0x02: 8-bit sample (RO) (upper 8 bits are 0) + */ + +#define TS_ADC_FLAGS 0x0 +#define TS_ADC_FLAGS_SAMPLE_MISSED (1<<2) +#define TS_ADC_FLAGS_SAMPLE_READY (1<<1) +#define TS_ADC_FLAGS_STANDBY (1<<0) +#define TS_ADC_RESULT 0x2 +#define ADC_TIMEOUT_US 50000 + +struct ts_simple_adc { + struct resource *mem; + void __iomem *base; + u16 value; + u8 buffer[16] ____cacheline_aligned; + struct completion completion; +}; + +static const struct iio_chan_spec ts_simple_adc_iio_channels[] = { + { + .type = IIO_VOLTAGE, + .indexed = 1, + .channel = 0, + .info_mask_separate = + BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), + .scan_index = 0, + .scan_type = { + .sign = 'u', + .realbits = 8, + .storagebits = 16, + }, + }, + IIO_CHAN_SOFT_TIMESTAMP(1), +}; + +static void ts_simple_adc_set_standby(struct ts_simple_adc *adc, int en_standby) +{ + if (en_standby) + writew(TS_ADC_FLAGS_STANDBY, adc->base + TS_ADC_FLAGS); + else + writew(0x0, adc->base + TS_ADC_FLAGS); +} + +static int ts_simple_adc_iio_read_raw(struct iio_dev *iio_dev, + struct iio_chan_spec const *chan, int *val, + int *val2, long mask) +{ + struct ts_simple_adc *adc = iio_priv(iio_dev); + int ret; + + switch (mask) { + case IIO_CHAN_INFO_RAW: + if (iio_buffer_enabled(iio_dev)) + return -EBUSY; + ts_simple_adc_set_standby(adc, 0); + reinit_completion(&adc->completion); + ret = wait_for_completion_interruptible_timeout(&adc->completion, + ADC_TIMEOUT_US); + if (ret == 0) + return -ETIMEDOUT; + + *val = adc->value; + ts_simple_adc_set_standby(adc, 1); + return IIO_VAL_INT; + case IIO_CHAN_INFO_SCALE: + *val = 6600; + *val2 = 8; + return IIO_VAL_FRACTIONAL_LOG2; + default: + break; + } + return -EINVAL; +} + +static irqreturn_t ts_simple_adc_isr(int irq, void *dev_id) +{ + struct iio_dev *indio_dev = (struct iio_dev *)dev_id; + struct ts_simple_adc *adc = iio_priv(indio_dev); + + adc->value = readw(adc->base + TS_ADC_RESULT) & 0xFF; + + if (iio_buffer_enabled(indio_dev)) { + iio_push_to_buffers_with_timestamp(indio_dev, + &adc->value, + iio_get_time_ns(indio_dev)); + } else { + complete(&adc->completion); + } + + return IRQ_HANDLED; +} + +static const struct iio_info ts_simple_adc_info = { + .read_raw = &ts_simple_adc_iio_read_raw, +}; + +static int ts_simple_adc_buffer_enable(struct iio_dev *indio_dev) +{ + struct ts_simple_adc *adc = iio_priv(indio_dev); + + ts_simple_adc_set_standby(adc, 0); + return 0; +} + +static int ts_simple_adc_buffer_disable(struct iio_dev *indio_dev) +{ + struct ts_simple_adc *adc = iio_priv(indio_dev); + + ts_simple_adc_set_standby(adc, 1); + return 0; +} + +static const struct iio_buffer_setup_ops ts_simple_setup_ops = { + .postenable = &ts_simple_adc_buffer_enable, + .predisable = &ts_simple_adc_buffer_disable, +}; + +static int ts_simple_adc_probe(struct platform_device *pdev) +{ + struct ts_simple_adc *adc_dev; + struct iio_dev *indio_dev; + struct resource *mem; + int irq; + int ret; + + indio_dev = devm_iio_device_alloc(&pdev->dev, + sizeof(struct ts_simple_adc)); + if (!indio_dev) + return -ENOMEM; + + adc_dev = iio_priv(indio_dev); + indio_dev->name = dev_name(&pdev->dev); + indio_dev->dev.parent = &pdev->dev; + indio_dev->dev.of_node = pdev->dev.of_node; + indio_dev->info = &ts_simple_adc_info; + indio_dev->channels = ts_simple_adc_iio_channels; + indio_dev->num_channels = ARRAY_SIZE(ts_simple_adc_iio_channels); + + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + dev_err(&pdev->dev, "no irq resource?\n"); + return irq; + } + + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + init_completion(&adc_dev->completion); + adc_dev->base = devm_ioremap_resource(&pdev->dev, mem); + if (IS_ERR(adc_dev->base)) { + dev_err(&pdev->dev, "failed to get ts adc base address\n"); + return PTR_ERR(adc_dev->base); + } + + ret = devm_iio_kfifo_buffer_setup(&pdev->dev, indio_dev, + &ts_simple_setup_ops); + if (ret) + return ret; + + ret = devm_request_irq(&pdev->dev, irq, + ts_simple_adc_isr, 0, + dev_name(&pdev->dev), indio_dev); + if (ret) { + dev_err(&pdev->dev, "failed requesting irq, irq = %d\n", irq); + return ret; + } + + return devm_iio_device_register(&pdev->dev, indio_dev); +} + +static const struct of_device_id tsadc_of_match[] = { + { .compatible = "technologic,ts-simple-adc", }, + { } +}; +MODULE_DEVICE_TABLE(of, tsadc_of_match); + +static struct platform_driver tsadc_driver = { + .driver = { + .name = "ts_adc", + .of_match_table = tsadc_of_match, + }, + .probe = ts_simple_adc_probe, +}; +module_platform_driver(tsadc_driver); + +MODULE_AUTHOR("Mark Featherston "); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("IIO ADC driver embeddedTS Simple FPGA ADC"); From 7a5fcf53afa98932eea2361a6bb5c5933a33c5d7 Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Thu, 2 Mar 2023 14:33:50 -0700 Subject: [PATCH 040/244] pwm: pwm-ts: Initial commit of PWM driver for TS-7250-V3 --- drivers/pwm/Kconfig | 8 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-ts.c | 210 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 219 insertions(+) create mode 100644 drivers/pwm/pwm-ts.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index c2fd3f4b62d9e..ebb3a5bf72fee 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -768,6 +768,14 @@ config PWM_TIEHRPWM To compile this driver as a module, choose M here: the module will be called pwm-tiehrpwm. +config PWM_TS + tristate "embeddedTS FPGA PWM support" + help + PWM driver support for embeddedTS FPGA based PWM controller + + To compile this driver as a module, choose M here: the module + will be called pwm-ts. + config PWM_TWL tristate "TWL4030/6030 PWM support" depends on TWL4030_CORE diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index dfa8b4966ee19..7ee19b98eaf2d 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -70,6 +70,7 @@ obj-$(CONFIG_PWM_SUNPLUS) += pwm-sunplus.o obj-$(CONFIG_PWM_TEGRA) += pwm-tegra.o obj-$(CONFIG_PWM_TIECAP) += pwm-tiecap.o obj-$(CONFIG_PWM_TIEHRPWM) += pwm-tiehrpwm.o +obj-$(CONFIG_PWM_TS) += pwm-ts.o obj-$(CONFIG_PWM_TWL) += pwm-twl.o obj-$(CONFIG_PWM_TWL_LED) += pwm-twl-led.o obj-$(CONFIG_PWM_VISCONTI) += pwm-visconti.o diff --git a/drivers/pwm/pwm-ts.c b/drivers/pwm/pwm-ts.c new file mode 100644 index 0000000000000..48e8af3295693 --- /dev/null +++ b/drivers/pwm/pwm-ts.c @@ -0,0 +1,210 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PWM for embeddedTS TS-7250-V3, TS-7120, et al. + * Copyright (C) 2021-2022 Technologic Systems, Inc. dba embeddedTS + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Enabled bit is the only one that applies immediately. All other registers + * take effect when apply is set + */ +#define REG_CONFIG 0x0 +/* Enable PWM Output */ +#define ENABLED (1 << 0) +/* 0 = idle high, active low. 1 = idle low, active high */ +#define INVERSED (1 << 1) + +#define REG_PERIOD 0x2 +#define REG_DUTY 0x4 +#define PWM_DUTY_WIDTH 10 +#define CYCLE_MASK 0x3ff +#define REG_SHIFT 0x6 +#define SHIFT_MAX 12 + +struct ts_pwm { + struct pwm_chip chip; + void __iomem *base; + spinlock_t lock; + u16 duty; + u16 period; + u8 shift; + struct pwm_state state; + struct clk *clk; +}; + +static inline struct ts_pwm *to_ts_pwm(struct pwm_chip *chip) +{ + return container_of(chip, struct ts_pwm, chip); +} + +static int ts_pwm_calc(struct ts_pwm *ts, + unsigned int duty, + unsigned int period) +{ + unsigned long clk_rate = clk_get_rate(ts->clk); + unsigned long long cycle; + unsigned int shift, cnt, duty_cnt; + + /* Calc shift & period reg */ + for (shift = 0; shift < SHIFT_MAX; shift++) { + cycle = DIV_ROUND_CLOSEST_ULL(NSEC_PER_SEC, + (clk_rate / 100) >> shift); + cnt = DIV_ROUND_CLOSEST(period * 100, (unsigned int)cycle); + if (cnt <= CYCLE_MASK) + break; + } + + if (cnt > CYCLE_MASK) + return -EINVAL; + + dev_dbg(ts->chip.dev, "cycle=%llu shift=%u cnt=%u\n", + cycle, shift, cnt); + + if (duty == period) { + ts->shift = shift; + ts->period = cnt; + ts->duty = cnt; + } else if (duty == 0) { + ts->shift = shift; + ts->period = cnt; + ts->duty = 0; + } else { + duty_cnt = DIV_ROUND_CLOSEST(duty * 100, (unsigned int)cycle); + if (duty_cnt > CYCLE_MASK) { + dev_err(ts->chip.dev, "unable to get duty cycle\n"); + return -EINVAL; + } + + dev_dbg(ts->chip.dev, "shift=%u cnt=%u duty_cnt=%u\n", + shift, cnt, duty_cnt); + + ts->shift = shift; + ts->period = cnt; + ts->duty = cnt - duty_cnt; + } + + return 0; +} + +static int ts_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) +{ + struct ts_pwm *ts = to_ts_pwm(chip); + u16 value = 0; + int err; + + BUG_ON(!state); + + if (!state->enabled) { + writel(0x0, ts->base + REG_CONFIG); + ts->state.enabled = false; + return 0; + } + + if (state->polarity == PWM_POLARITY_NORMAL) + value &= ~(INVERSED); + else + value |= INVERSED; + + + err = ts_pwm_calc(ts, state->duty_cycle, state->period); + if (err < 0) + return err; + + ts->state.polarity = state->polarity; + ts->state.period = state->period; + ts->state.duty_cycle = state->duty_cycle; + ts->state.enabled = true; + + writew(ts->period, ts->base + REG_PERIOD); + writew(ts->duty, ts->base + REG_DUTY); + writew(ts->shift, ts->base + REG_SHIFT); + writew(value | ENABLED, ts->base + REG_CONFIG); + + return 0; +} + +static const struct pwm_ops ts_pwm_ops = { + .apply = ts_pwm_apply, + .owner = THIS_MODULE, +}; + +static const struct of_device_id ts_pwm_matches[] = { + { .compatible = "technologic,pwm", }, + {}, +}; +MODULE_DEVICE_TABLE(of, ts_pwm_matches); + +static int ts_pwm_probe(struct platform_device *pdev) +{ + struct ts_pwm *ts; + struct resource *regs; + int err; + + ts = devm_kzalloc(&pdev->dev, sizeof(*ts), GFP_KERNEL); + if (!ts) + return -ENOMEM; + + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); + ts->base = devm_ioremap_resource(&pdev->dev, regs); + if (IS_ERR(ts->base)) + return PTR_ERR(ts->base); + + ts->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(ts->clk)) { + dev_err(&pdev->dev, "cannot get clock\n"); + return PTR_ERR(ts->clk); + } + + platform_set_drvdata(pdev, ts); + + spin_lock_init(&ts->lock); + ts->chip.dev = &pdev->dev; + ts->chip.ops = &ts_pwm_ops; + ts->chip.base = -1; + ts->chip.npwm = 1; + + pm_runtime_enable(&pdev->dev); + + err = pwmchip_add(&ts->chip); + if (err < 0) { + dev_err(&pdev->dev, "failed to register PWM chip: %d\n", err); + return err; + } + + return 0; +} + +static void ts_pwm_remove(struct platform_device *pdev) +{ + struct ts_pwm *ts = platform_get_drvdata(pdev); + pwmchip_remove(&ts->chip); +} + +static struct platform_driver ts_pwm_driver = { + .driver = { + .name = "ts-pwm", + .of_match_table = ts_pwm_matches, + }, + .probe = ts_pwm_probe, + .remove_new = ts_pwm_remove, +}; +module_platform_driver(ts_pwm_driver); + +MODULE_ALIAS("platform:ts-pwm"); +MODULE_DESCRIPTION("embeddedTS PS"); +MODULE_AUTHOR("Mark Featherston "); +MODULE_LICENSE("GPL"); From a51562eb49666fb278ba19c26b3d2cc0ed18f4c6 Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Wed, 8 Mar 2023 08:49:14 -0700 Subject: [PATCH 041/244] mfd: tssupervisor-core: Initial commit of embeddedTS supervisory microcontroller core --- drivers/mfd/Kconfig | 10 ++ drivers/mfd/Makefile | 1 + drivers/mfd/tssupervisor-core.c | 246 ++++++++++++++++++++++++++++++ include/linux/mfd/ts_supervisor.h | 60 ++++++++ 4 files changed, 317 insertions(+) create mode 100644 drivers/mfd/tssupervisor-core.c create mode 100644 include/linux/mfd/ts_supervisor.h diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 6cec1858947bf..122cb85631125 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -2032,6 +2032,16 @@ config MFD_TC3589X additional drivers must be enabled in order to use the functionality of the device. +config MFD_TS_SUPERVISOR + tristate "embeddedTS Supervisor" + select MFD_CORE + select REGMAP_I2C + depends on I2C && OF + help + Support for embeddedTS supervisory controller. This includes an adc + driver for system rails, supercap backup management, and some misc + controls. + config MFD_TQMX86 tristate "TQ-Systems IO controller TQMX86" select MFD_CORE diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 865e9f12faff0..285cd1a13f4d6 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -33,6 +33,7 @@ obj-$(CONFIG_STMPE_I2C) += stmpe-i2c.o obj-$(CONFIG_STMPE_SPI) += stmpe-spi.o obj-$(CONFIG_MFD_SUN6I_PRCM) += sun6i-prcm.o obj-$(CONFIG_MFD_TC3589X) += tc3589x.o +obj-$(CONFIG_MFD_TS_SUPERVISOR) += tssupervisor-core.o obj-$(CONFIG_MFD_TQMX86) += tqmx86.o obj-$(CONFIG_MFD_LOCHNAGAR) += lochnagar-i2c.o diff --git a/drivers/mfd/tssupervisor-core.c b/drivers/mfd/tssupervisor-core.c new file mode 100644 index 0000000000000..7f02362763bce --- /dev/null +++ b/drivers/mfd/tssupervisor-core.c @@ -0,0 +1,246 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include +#include +#include +#include +#include + +#define MODEL_TS_7250_V3 0x7250 + +static struct mfd_cell tssupervisor_devs[] = { + { + .name = "tssupervisor-reset", + .id = -1, + }, + { + .name = "tssupervisor-temp", + .of_compatible = "technologic,supervisor-temp", + .id = -1, + }, + { + .name = "tssupervisor-adc", + .of_compatible = "technologic,supervisor-adc", + .id = -1, + } +}; + +static const struct regmap_range ts_supervisor_read_regs[] = { + regmap_reg_range(0, 3), /* model/version/advertisements */ + regmap_reg_range(16, 16), /* flags */ + regmap_reg_range(24, 24), /* inputs */ + regmap_reg_range(32, 32), /* reboot_reason */ + regmap_reg_range(128, 160), /* ADCs+temp */ +}; + +static const struct regmap_range ts_supervisor_write_regs[] = { + regmap_reg_range(8, 8), /* cmds */ + regmap_reg_range(16, 16), /* flags */ +}; + +const struct regmap_access_table ts_supervisor_read_register_set = { + .yes_ranges = ts_supervisor_read_regs, + .n_yes_ranges = ARRAY_SIZE(ts_supervisor_read_regs), +}; + +const struct regmap_access_table ts_supervisor_write_register_set = { + .yes_ranges = ts_supervisor_write_regs, + .n_yes_ranges = ARRAY_SIZE(ts_supervisor_write_regs), +}; + +const struct regmap_config ts_supervisor_i2c_regmap = { + .reg_bits = 16, + .val_bits = 16, + .can_multi_write = true, + .reg_format_endian = REGMAP_ENDIAN_LITTLE, + .val_format_endian = REGMAP_ENDIAN_LITTLE, + + .wr_table = &ts_supervisor_write_register_set, + .rd_table = &ts_supervisor_read_register_set, + .volatile_table = &ts_supervisor_read_register_set, + + .disable_locking = true, + .cache_type = REGCACHE_NONE, +}; +EXPORT_SYMBOL_GPL(ts_supervisor_i2c_regmap); + +static ssize_t vbus_present_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct ts_supervisor *super = dev_get_drvdata(dev); + unsigned int reg; + int ret; + + ret = regmap_read(super->regmap, SUPER_INPUTS, ®); + if (ret) + return ret; + ret = sprintf(buf, "%d\n", !!(reg & INPUTS_USB_VBUS)); + return ret; +} +static DEVICE_ATTR_RO(vbus_present); + +static ssize_t wake_en_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + struct ts_supervisor *super = dev_get_drvdata(dev); + unsigned int ctrl_reg = 0; + bool en; + int ret; + + ret = kstrtobool(buf, &en); + if (ret) + return ret; + + if (en) + ctrl_reg |= FLG_WAKE_EN; + + ret = regmap_update_bits(super->regmap, SUPER_FLAGS, + FLG_WAKE_EN, + ctrl_reg); + + return ret ? ret : count; +} + +static ssize_t wake_en_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct ts_supervisor *super = dev_get_drvdata(dev); + unsigned int reg; + int ret; + + ret = regmap_read(super->regmap, SUPER_FLAGS, ®); + if (ret) + return ret; + ret = sprintf(buf, "%d\n", !!(reg & FLG_WAKE_EN)); + return ret; +} +static DEVICE_ATTR_RW(wake_en); + +static ssize_t console_cfg_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + struct ts_supervisor *super = dev_get_drvdata(dev); + unsigned int ctrl_reg; + int ret; + + if (sysfs_streq(buf, "auto")) + ctrl_reg = 0; + else if (sysfs_streq(buf, "always-usb")) + ctrl_reg = FLG_FORCE_USB_CON; + else + return -EINVAL; + + ret = regmap_update_bits(super->regmap, SUPER_FLAGS, FLG_FORCE_USB_CON, + ctrl_reg); + + return ret ? ret : count; +} + +static ssize_t console_cfg_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct ts_supervisor *super = dev_get_drvdata(dev); + unsigned int reg; + int ret; + + ret = regmap_read(super->regmap, SUPER_FLAGS, ®); + if (ret) + return ret; + + if (reg & FLG_FORCE_USB_CON) + ret = sprintf(buf, "auto [always-usb]\n"); + else + ret = sprintf(buf, "[auto] always-usb\n"); + + return ret; +} +static DEVICE_ATTR_RW(console_cfg); + +static struct attribute *ts7250v3_sysfs_entries[] = { + &dev_attr_vbus_present.attr, + &dev_attr_wake_en.attr, + &dev_attr_console_cfg.attr, + NULL, +}; + +static struct attribute_group ts7250v3_attr_group = { + .attrs = ts7250v3_sysfs_entries, +}; + +static int ts_supervisor_i2c_probe(struct i2c_client *client) +{ + struct ts_supervisor *super; + struct device *dev = &client->dev; + int err = 0, i; + uint32_t model, revision; + + super = devm_kzalloc(dev, sizeof(struct ts_supervisor), + GFP_KERNEL); + if (!super) + return -ENOMEM; + + dev_set_drvdata(dev, super); + + super->client = client; + super->regmap = devm_regmap_init_i2c(client, &ts_supervisor_i2c_regmap); + if (IS_ERR(super->regmap)) { + err = PTR_ERR(super->regmap); + dev_err(dev, "Failed to allocate register map: %d\n", err); + return err; + } + + err = regmap_read(super->regmap, SUPER_MODEL, &model); + if (err < 0) + dev_err(dev, "error reading reg %u", SUPER_MODEL); + err = regmap_read(super->regmap, SUPER_REV_INFO, &revision); + if (err < 0) + dev_err(dev, "error reading reg %u", SUPER_REV_INFO); + dev_info(&client->dev, "Model %04X rev %d%s\n", + model, + revision & 0x7fff, + revision & 0x8000 ? " (DIRTY)" : ""); + + if (model == MODEL_TS_7250_V3) { + err = sysfs_create_group(&dev->kobj, &ts7250v3_attr_group); + if (err) + dev_warn(dev, "error creating sysfs entries\n"); + } + + /* Set up and register the platform devices. */ + for (i = 0; i < ARRAY_SIZE(tssupervisor_devs); i++) { + tssupervisor_devs[i].platform_data = super; + tssupervisor_devs[i].pdata_size = sizeof(struct ts_supervisor); + } + + return mfd_add_devices(dev, 0, tssupervisor_devs, + ARRAY_SIZE(tssupervisor_devs), NULL, 0, NULL); +} + +static const struct i2c_device_id ts_supervisor_i2c_id[] = { + { "tssupervisor", 0 }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(i2c, ts_supervisor_i2c_id); + +static const struct of_device_id ts_supervisor_i2c_of_match[] = { + { .compatible = "technologic,supervisor", }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, ts_supervisor_i2c_of_match); + +static struct i2c_driver ts_supervisor_i2c_driver = { + .driver = { + .name = "tssupervisor-core", + .of_match_table = of_match_ptr(ts_supervisor_i2c_of_match), + }, + .probe = ts_supervisor_i2c_probe, + .id_table = ts_supervisor_i2c_id, +}; +module_i2c_driver(ts_supervisor_i2c_driver); + +MODULE_AUTHOR("Mark Featherston "); +MODULE_DESCRIPTION("Core driver for embeddedTS Supervisory microcontroller"); +MODULE_LICENSE("GPL v2"); diff --git a/include/linux/mfd/ts_supervisor.h b/include/linux/mfd/ts_supervisor.h new file mode 100644 index 0000000000000..0f01d0d03857c --- /dev/null +++ b/include/linux/mfd/ts_supervisor.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __LINUX_MFD_TS_SUPERVISOR_H +#define __LINUX_MFD_TS_SUPERVISOR_H + +struct ts_supervisor { + struct i2c_client *client; + struct regmap *regmap; + struct platform_device *rstc_pdev; + struct platform_device *adc_pdev; + struct platform_device *temp_pdev; +}; + +/* I2C Register addresses */ +#define SUPER_MODEL 0 +#define SUPER_REV_INFO 1 +#define SUPER_ADC_CHAN_ADV 2 +#define SUPER_FEATURES0 3 +#define SUPER_CMDS 8 +#define SUPER_FLAGS 16 +#define SUPER_INPUTS 24 +#define SUPER_REBOOT_REASON 32 +#define SUPER_ADC_BASE 128 +#define SUPER_ADC_LAST 159 +#define SUPER_TEMPERATURE 160 + +enum gen_flags_t { + FLG_FORCE_USB_CON = (1 << 4), + FLG_LED_DAT = (1 << 3), + FLG_OVERRIDE_LED = (1 << 2), + FLG_WAKE_EN = (1 << 1), +}; + +enum gen_inputs_t { + INPUTS_USB_VBUS = (1 << 0), +}; + +enum super_features_t { + SUPER_FEAT_SN = (1 << 2), + SUPER_FEAT_FWUPD = (1 << 1), + SUPER_FEAT_RSTC = (1 << 0), +}; + +enum reboot_reasons_t { + REBOOT_REASON_POR = 0, + REBOOT_REASON_CPU_WDT = 1, + REBOOT_REASON_SOFTWARE_REBOOT = 2, + REBOOT_REASON_BROWNOUT = 3, + REBOOT_REASON_RTC_ALARM_REBOOT = 4, + REBOOT_REASON_WAKE_FROM_PWR_CYCLE = 5, + REBOOT_REASON_WAKE_FROM_WAKE_SIGNAL = 6, + REBOOT_REASON_WAKE_FROM_RTC_ALARM = 7, + REBOOT_REASON_WAKE_FROM_USB_VBUS = 8, +}; + +enum super_cmds_t { + I2C_REBOOT = (1 << 0), + I2C_HALT = (1 << 1), +}; + +#endif \ No newline at end of file From e5bd3a070e9c86e9e28561e2172648376861ca5b Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Wed, 8 Mar 2023 08:49:28 -0700 Subject: [PATCH 042/244] rtc: tssupervisor-rtc: Initial commit of embeddedTS counter based RTC --- drivers/rtc/Kconfig | 6 + drivers/rtc/Makefile | 1 + drivers/rtc/rtc-tssupervisor.c | 341 +++++++++++++++++++++++++++++++++ 3 files changed, 348 insertions(+) create mode 100644 drivers/rtc/rtc-tssupervisor.c diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 2933c41c77c88..1be6242ff727e 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -575,6 +575,12 @@ config RTC_DRV_BQ32K This driver can also be built as a module. If so, the module will be called rtc-bq32k. +config RTC_DRV_TSSUPERVISOR + tristate "embeddedTS Supervisory Microcontroller RTC" + select REGMAP_I2C + help + Supports the RTC on embeddedTS Supervisory microcontroller + config RTC_DRV_TWL92330 bool "TI TWL92330/Menelaus" depends on MENELAUS diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 8221bda6e6dca..f5f06a9d520ae 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -189,6 +189,7 @@ obj-$(CONFIG_RTC_DRV_TI_K3) += rtc-ti-k3.o obj-$(CONFIG_RTC_DRV_TPS6586X) += rtc-tps6586x.o obj-$(CONFIG_RTC_DRV_TPS6594) += rtc-tps6594.o obj-$(CONFIG_RTC_DRV_TPS65910) += rtc-tps65910.o +obj-$(CONFIG_RTC_DRV_TSSUPERVISOR) += rtc-tssupervisor.o obj-$(CONFIG_RTC_DRV_TWL4030) += rtc-twl.o obj-$(CONFIG_RTC_DRV_VT8500) += rtc-vt8500.o obj-$(CONFIG_RTC_DRV_WILCO_EC) += rtc-wilco-ec.o diff --git a/drivers/rtc/rtc-tssupervisor.c b/drivers/rtc/rtc-tssupervisor.c new file mode 100644 index 0000000000000..ae114e2c59cef --- /dev/null +++ b/drivers/rtc/rtc-tssupervisor.c @@ -0,0 +1,341 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * RTC for embeddedts's supervisory microcontroller + * Alarm does not have an IRQ, controls wakeup or reset from the external + * supervisory microcontroller. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define RTC_MAGIC 0x0 +#define RTC_MAGIC_VALUE 0xAA +#define RTC_RESERVED0 0x1 +#define RTC_FLAGS 0x2 +#define RTC_FLAGS_OF (1 << 7) /* Cleared writing any new epoch value */ +#define RTC_FLAGS_ALARM_EN (1 << 6) +#define RTC_FLAGS_ALARM_TRIPPED (1 << 5) /* Clear by writing RTC Alarm regs */ +#define RTC_FLAGS_ALARM_REBOOT (1 << 4) +#define RTC_FLAGS_BATT_PRESENT (1 << 3) +#define RTC_RESERVED1 0x3 +#define RTC_EPOCH_0 0x4 +#define RTC_EPOCH_1 0x5 +#define RTC_EPOCH_2 0x6 +#define RTC_EPOCH_3 0x7 +#define RTC_ALARM_0 0x12 +#define RTC_ALARM_1 0x13 +#define RTC_ALARM_2 0x14 +#define RTC_ALARM_3 0x15 +#define RTC_PPB_0 0x1A +#define RTC_PPB_1 0x1B +#define RTC_PPB_2 0x1C +#define RTC_PPB_3 0x1D +#define RTC_PPB_CTL 0x1E +#define RTC_PPB_CTL_SIGN (1 << 1) /* 1 = positive, 0 = negative */ +#define RTC_PPB_CTL_EN (1 << 0) /* Calibration is applied anytime this is 1*/ + +struct supervisor_rtc { + struct device *dev; + struct regmap *regmap; + const char *name; + struct rtc_device *rtc; +}; + +static int supervisor_rtc_get_time(struct device *dev, struct rtc_time *tm) +{ + struct supervisor_rtc *super = dev_get_drvdata(dev); + time64_t timestamp = 0; + unsigned int reg; + int ret; + + ret = regmap_read(super->regmap, RTC_FLAGS, ®); + if (ret) + return ret; + + /* RTC has invalid time */ + if (reg & RTC_FLAGS_OF) + return -EINVAL; + + ret = regmap_bulk_read(super->regmap, RTC_EPOCH_0, ×tamp, 4); + if (ret) + return ret; + + rtc_time64_to_tm(timestamp, tm); + + return 0; +} + +static int supervisor_rtc_set_time(struct device *dev, struct rtc_time *tm) +{ + struct supervisor_rtc *super = dev_get_drvdata(dev); + time64_t timestamp = rtc_tm_to_time64(tm); + + return regmap_bulk_write(super->regmap, RTC_EPOCH_0, ×tamp, 4); +} + +static int supervisor_rtc_read_offset(struct device *dev, long *offset) +{ + struct supervisor_rtc *super = dev_get_drvdata(dev); + unsigned int ctrl_reg; + uint32_t ppb; + int ret; + + ret = regmap_bulk_read(super->regmap, RTC_PPB_0, &ppb, sizeof(ppb)); + if (ret) + return ret; + + ret = regmap_read(super->regmap, RTC_PPB_CTL, &ctrl_reg); + if (ret) + return ret; + + /* check if positive */ + if (ctrl_reg & RTC_PPB_CTL_SIGN) + *offset = (ppb); + else + *offset = -(ppb); + + return 0; +} + +static int supervisor_rtc_set_offset(struct device *dev, long offset) +{ + struct supervisor_rtc *super = dev_get_drvdata(dev); + unsigned int ctrl_reg = RTC_PPB_CTL_EN; + u32 ppb = (uint32_t)offset; + int ret; + + ret = regmap_bulk_write(super->regmap, RTC_PPB_0, &ppb, sizeof(ppb)); + if (ret) + return ret; + + if (offset >= 0) + ctrl_reg |= RTC_PPB_CTL_SIGN; + + return regmap_update_bits(super->regmap, RTC_FLAGS, + RTC_PPB_CTL_SIGN | RTC_PPB_CTL_EN, + ctrl_reg); +} + +static const struct rtc_class_ops supervisor_rtc_ops = { + .read_time = supervisor_rtc_get_time, + .set_time = supervisor_rtc_set_time, + .read_offset = supervisor_rtc_read_offset, + .set_offset = supervisor_rtc_set_offset, +}; + +static const struct regmap_config regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .max_register = 32, +}; + +static ssize_t alarm_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + struct supervisor_rtc *super = dev_get_drvdata(dev); + unsigned long timestamp; + int ret; + + ret = kstrtoul(buf, 0, ×tamp); + if (ret) + return ret; + + ret = regmap_bulk_write(super->regmap, RTC_ALARM_0, ×tamp, 4); + if (ret) + return ret; + + return count; +} + +static ssize_t alarm_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct supervisor_rtc *super = dev_get_drvdata(dev); + u32 timestamp; + int len; + int ret; + + ret = regmap_bulk_read(super->regmap, RTC_ALARM_0, ×tamp, 4); + if (ret) + return ret; + + len = sprintf(buf, "%d\n", timestamp); + + return len; +} +static DEVICE_ATTR_RW(alarm); + +static ssize_t alarm_en_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + struct supervisor_rtc *super = dev_get_drvdata(dev); + unsigned int ctrl_reg = 0; + bool en; + int ret; + + ret = kstrtobool(buf, &en); + if (ret) + return ret; + + if (en) + ctrl_reg |= RTC_FLAGS_ALARM_EN; + + ret = regmap_update_bits(super->regmap, RTC_FLAGS, + RTC_FLAGS_ALARM_EN, + ctrl_reg); + + return ret ? ret : count; +} + +static ssize_t alarm_en_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct supervisor_rtc *super = dev_get_drvdata(dev); + unsigned int reg; + int ret; + + ret = regmap_read(super->regmap, RTC_FLAGS, ®); + if (ret) + return ret; + ret = sprintf(buf, "%d\n", !!(reg & RTC_FLAGS_ALARM_EN)); + return ret; +} +static DEVICE_ATTR_RW(alarm_en); + +static ssize_t alarm_cause_reboot_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + struct supervisor_rtc *super = dev_get_drvdata(dev); + unsigned int ctrl_reg = 0; + bool en; + int ret; + + ret = kstrtobool(buf, &en); + if (ret) + return ret; + + if (en) + ctrl_reg |= RTC_FLAGS_ALARM_REBOOT; + + ret = regmap_update_bits(super->regmap, RTC_FLAGS, + RTC_FLAGS_ALARM_REBOOT, + ctrl_reg); + + return ret ? ret : count; +} + +static ssize_t alarm_cause_reboot_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct supervisor_rtc *super = dev_get_drvdata(dev); + unsigned int reg; + int ret; + + ret = regmap_read(super->regmap, RTC_FLAGS, ®); + if (ret) + return ret; + ret = sprintf(buf, "%d\n", !!(reg & RTC_FLAGS_ALARM_REBOOT)); + return ret; +} +static DEVICE_ATTR_RW(alarm_cause_reboot); + +static ssize_t batt_present_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct supervisor_rtc *super = dev_get_drvdata(dev); + unsigned int reg; + int ret; + + ret = regmap_read(super->regmap, RTC_FLAGS, ®); + if (ret) + return ret; + ret = sprintf(buf, "%d\n", !!(reg & RTC_FLAGS_BATT_PRESENT)); + return ret; +} +static DEVICE_ATTR_RO(batt_present); + +static struct attribute *supervisor_rtc_sysfs_entries[] = { + &dev_attr_alarm_en.attr, + &dev_attr_alarm.attr, + &dev_attr_alarm_cause_reboot.attr, + &dev_attr_batt_present.attr, + NULL, +}; + +static struct attribute_group supervisor_rtc_attr_group = { + .attrs = supervisor_rtc_sysfs_entries, +}; + +static int supervisor_rtc_probe(struct i2c_client *client) +{ + struct supervisor_rtc *super; + struct device *dev = &client->dev; + int err = -ENODEV; + + super = devm_kzalloc(dev, sizeof(struct supervisor_rtc), GFP_KERNEL); + if (!super) + return -ENOMEM; + + dev_set_drvdata(dev, super); + super->dev = dev; + super->name = client->name; + super->regmap = devm_regmap_init_i2c(client, ®map_config); + if (IS_ERR(super->regmap)) { + dev_err(dev, "regmap allocation failed\n"); + return PTR_ERR(super->regmap); + } + + i2c_set_clientdata(client, super); + + super->rtc = devm_rtc_allocate_device(dev); + if (IS_ERR(super->rtc)) + return PTR_ERR(super->rtc); + + err = sysfs_create_group(&dev->kobj, &supervisor_rtc_attr_group); + if (err) + dev_warn(dev, "error creating sysfs entries\n"); + + super->rtc->ops = &supervisor_rtc_ops; + err = devm_rtc_register_device(super->rtc); + if (err) + return err; + + return 0; +} + +static const struct i2c_device_id tssupervisor_rtc_id[] = { + { "tssupervisor_rtc", 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, tssupervisor_rtc_id); + +static const struct of_device_id tssupervisor_rtc_of_match[] = { + { .compatible = "technologic,supervisor-rtc", }, + { } +}; +MODULE_DEVICE_TABLE(of, tssupervisor_rtc_of_match); + +static struct i2c_driver supervisor_rtc_driver = { + .driver = { + .name = "rtc-tssupervisor", + .of_match_table = of_match_ptr(tssupervisor_rtc_of_match), + }, + .probe = supervisor_rtc_probe, + .id_table = tssupervisor_rtc_id, +}; + +module_i2c_driver(supervisor_rtc_driver); + +MODULE_DESCRIPTION("RTC driver for embeddedTS supervisory microcontroller"); +MODULE_LICENSE("GPL"); From ac2b0806325bf35207d92f3d1d96e1e78e5a705c Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Wed, 8 Mar 2023 08:54:19 -0700 Subject: [PATCH 043/244] iio: tssupervisor-adc: Initial commit of embeddedTS supervisory microcontroller ADC --- drivers/iio/adc/Kconfig | 8 ++ drivers/iio/adc/Makefile | 1 + drivers/iio/adc/tssupervisor_adc.c | 169 +++++++++++++++++++++++++++++ 3 files changed, 178 insertions(+) create mode 100644 drivers/iio/adc/tssupervisor_adc.c diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 2768033addaa1..2cf0fa10ad773 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -1805,6 +1805,14 @@ config TS_SIMPLEADC help Say yes here to build support for embeddedTS FPGA based ADC. +config TS_SUPERVISOR_ADC + tristate "embeddedTS Supervisory Microcontroller ADC" + depends on OF + depends on MFD_TS_SUPERVISOR + help + Say yes here to build support for embeddedTS supervisory + microcontroller ADC. + config TWL4030_MADC tristate "TWL4030 MADC (Monitoring A/D Converter)" depends on TWL4030_CORE diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index 7c0d4fce2ba9e..4dc1c19e0d8e8 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -157,6 +157,7 @@ obj-$(CONFIG_TI_LMP92064) += ti-lmp92064.o obj-$(CONFIG_TI_TLC4541) += ti-tlc4541.o obj-$(CONFIG_TI_TSC2046) += ti-tsc2046.o obj-$(CONFIG_TS_SIMPLEADC) += ts_simple_adc.o +obj-$(CONFIG_TS_SUPERVISOR_ADC) += tssupervisor_adc.o obj-$(CONFIG_TWL4030_MADC) += twl4030-madc.o obj-$(CONFIG_TWL6030_GPADC) += twl6030-gpadc.o obj-$(CONFIG_VF610_ADC) += vf610_adc.o diff --git a/drivers/iio/adc/tssupervisor_adc.c b/drivers/iio/adc/tssupervisor_adc.c new file mode 100644 index 0000000000000..dd65e35ac6643 --- /dev/null +++ b/drivers/iio/adc/tssupervisor_adc.c @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ADC driver for simple 8-bit ADC on TS-7250-V3 + * Copyright (C) 2021-2022 Technologic Systems, Inc. dba embeddedTS + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define TS_SUPERVISOR_MAX_ADC 32 + +struct ts_adc { + struct ts_supervisor *super; + uint16_t channel_count; +}; + +#define SUPERVISOR_CHAN(index) \ +{ \ + .type = IIO_VOLTAGE, \ + .indexed = 1, \ + .channel = index, \ + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \ + | BIT(IIO_CHAN_INFO_SCALE), \ + .scan_index = index, \ + .scan_type = { \ + .sign = 'u', \ + .realbits = 12, \ + .storagebits = 16, \ + .endianness = IIO_LE, \ + }, \ +} + +static const struct iio_chan_spec tssupervisor_channels[] = { + SUPERVISOR_CHAN(0), + SUPERVISOR_CHAN(1), + SUPERVISOR_CHAN(2), + SUPERVISOR_CHAN(3), + SUPERVISOR_CHAN(4), + SUPERVISOR_CHAN(5), + SUPERVISOR_CHAN(6), + SUPERVISOR_CHAN(7), + SUPERVISOR_CHAN(8), + SUPERVISOR_CHAN(9), + SUPERVISOR_CHAN(10), + SUPERVISOR_CHAN(11), + SUPERVISOR_CHAN(12), + SUPERVISOR_CHAN(13), + SUPERVISOR_CHAN(14), + SUPERVISOR_CHAN(15), + SUPERVISOR_CHAN(16), + SUPERVISOR_CHAN(17), + SUPERVISOR_CHAN(18), + SUPERVISOR_CHAN(19), + SUPERVISOR_CHAN(20), + SUPERVISOR_CHAN(21), + SUPERVISOR_CHAN(22), + SUPERVISOR_CHAN(23), + SUPERVISOR_CHAN(24), + SUPERVISOR_CHAN(25), + SUPERVISOR_CHAN(26), + SUPERVISOR_CHAN(27), + SUPERVISOR_CHAN(28), + SUPERVISOR_CHAN(29), + SUPERVISOR_CHAN(30), + SUPERVISOR_CHAN(31), +}; + +static int ts_adc_iio_read_raw(struct iio_dev *iio_dev, + struct iio_chan_spec const *chan, int *val, + int *val2, long mask) +{ + struct ts_adc *adc = iio_priv(iio_dev); + int addr; + uint32_t data; + int ret; + + switch (mask) { + case IIO_CHAN_INFO_RAW: + addr = SUPER_ADC_BASE + chan->channel; + ret = regmap_read(adc->super->regmap, addr, &data); + if (ret < 0) + return ret; + *val = data; + return IIO_VAL_INT; + case IIO_CHAN_INFO_SCALE: + *val = 3300; + *val2 = 12; + return IIO_VAL_FRACTIONAL_LOG2; + default: + break; + } + return -EINVAL; +} + +static const struct iio_info ts_adc_info = { + .read_raw = &ts_adc_iio_read_raw, +}; + +static int ts_supervisor_adc_probe(struct platform_device *pdev) +{ + struct ts_supervisor *super = dev_get_drvdata(pdev->dev.parent); + struct ts_adc *adc; + struct device *dev = &pdev->dev; + struct iio_dev *indio_dev; + uint32_t chan_count; + int ret; + + ret = regmap_read(super->regmap, SUPER_ADC_CHAN_ADV, &chan_count); + if (ret < 0) { + dev_err(dev, "error reading reg %u", SUPER_ADC_CHAN_ADV); + return ret; + } + + /* This supervisor does not support ADC channels */ + if (chan_count == 0) + return 0; + + indio_dev = devm_iio_device_alloc(dev, sizeof(*adc)); + if (indio_dev == NULL) + return -ENOMEM; + adc = iio_priv(indio_dev); + adc->super = super; + adc->channel_count = chan_count; + + /* + * The microcontroller advertises how many ADC are present. This can + * be up to 32 channels depending on muxes onboard and channels that + * need to be sampled, but most will be < 7 channels. + */ + if (adc->channel_count > TS_SUPERVISOR_MAX_ADC) { + dev_warn(dev, "The ADC device is advertising more ADC than supported!"); + adc->channel_count = TS_SUPERVISOR_MAX_ADC; + } + indio_dev->num_channels = adc->channel_count; + indio_dev->channels = tssupervisor_channels; + + indio_dev->name = dev_name(&pdev->dev); + indio_dev->dev.of_node = pdev->dev.of_node; + indio_dev->info = &ts_adc_info; + + return devm_iio_device_register(&pdev->dev, indio_dev); +} + +static const struct of_device_id tssupervisor_of_match[] = { + { .compatible = "technologic,tssupervisor-adc", }, + { } +}; +MODULE_DEVICE_TABLE(of, tsadc_of_match); + +static struct platform_driver tsadc_driver = { + .driver = { + .name = "tssupervisor-adc", + .of_match_table = tssupervisor_of_match, + }, + .probe = ts_supervisor_adc_probe, +}; +module_platform_driver(tsadc_driver); + +MODULE_DESCRIPTION("embeddedTS supervisor adc controller driver"); +MODULE_AUTHOR("Mark Featherston "); +MODULE_LICENSE("GPL"); From dbe37dc8f31ebbf4ae1d3adde1fade030ea2d6de Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Wed, 8 Mar 2023 08:55:39 -0700 Subject: [PATCH 044/244] iio: tssupervisor-temp: Initial commit of embeddedTS supervisory temperature sensor --- drivers/iio/temperature/Kconfig | 8 ++ drivers/iio/temperature/Makefile | 1 + drivers/iio/temperature/tssupervisor_temp.c | 88 +++++++++++++++++++++ 3 files changed, 97 insertions(+) create mode 100644 drivers/iio/temperature/tssupervisor_temp.c diff --git a/drivers/iio/temperature/Kconfig b/drivers/iio/temperature/Kconfig index 9328b2250aced..8dc396e0ef5b1 100644 --- a/drivers/iio/temperature/Kconfig +++ b/drivers/iio/temperature/Kconfig @@ -152,6 +152,14 @@ config MAX30208 This driver can also be built as a module. If so, the module will be called max30208. +config TS_SUPERVISOR_TEMP + tristate "embeddedTS Supervisory Microcontroller TEMP" + depends on OF + depends on MFD_TS_SUPERVISOR + help + Say yes here to build support for embeddedTS supervisory + microcontroller temperature sensor. + config MAX31856 tristate "MAX31856 thermocouple sensor" depends on SPI diff --git a/drivers/iio/temperature/Makefile b/drivers/iio/temperature/Makefile index 07d6e65709f7f..023d5306d8c47 100644 --- a/drivers/iio/temperature/Makefile +++ b/drivers/iio/temperature/Makefile @@ -17,5 +17,6 @@ obj-$(CONFIG_MLX90632) += mlx90635.o obj-$(CONFIG_TMP006) += tmp006.o obj-$(CONFIG_TMP007) += tmp007.o obj-$(CONFIG_TMP117) += tmp117.o +obj-$(CONFIG_TS_SUPERVISOR_TEMP) += tssupervisor_temp.o obj-$(CONFIG_TSYS01) += tsys01.o obj-$(CONFIG_TSYS02D) += tsys02d.o diff --git a/drivers/iio/temperature/tssupervisor_temp.c b/drivers/iio/temperature/tssupervisor_temp.c new file mode 100644 index 0000000000000..5f2e754b1d4e7 --- /dev/null +++ b/drivers/iio/temperature/tssupervisor_temp.c @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ADC driver for simple 8-bit ADC on TS-7250-V3 + * Copyright (C) 2021-2022 Technologic Systems, Inc. dba embeddedTS + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct ts_temp_adc { + struct ts_supervisor *super; +}; + +static const struct iio_chan_spec ts_temp_channel = +{ + .type = IIO_TEMP, + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_PROCESSED), +}; + +static int ts_temp_iio_read_raw(struct iio_dev *iio_dev, + struct iio_chan_spec const *chan, int *val, + int *val2, long mask) +{ + struct ts_temp_adc *adc = iio_priv(iio_dev); + int32_t data; + int ret; + + ret = regmap_read(adc->super->regmap, SUPER_TEMPERATURE, &data); + if (ret < 0) + return ret; + + switch (mask) { + case IIO_CHAN_INFO_PROCESSED: + *val = (int32_t)data*196551/1000-277439; + return IIO_VAL_INT; + default: + return -EINVAL; + } +} + +static const struct iio_info ts_adc_info = { + .read_raw = &ts_temp_iio_read_raw, +}; + +static int ts_supervisor_temp_probe(struct platform_device *pdev) +{ + struct ts_supervisor *super = dev_get_drvdata(pdev->dev.parent); + struct ts_temp_adc *adc; + struct device *dev = &pdev->dev; + struct iio_dev *indio_dev; + + indio_dev = devm_iio_device_alloc(dev, sizeof(*adc)); + if (indio_dev == NULL) + return -ENOMEM; + adc = iio_priv(indio_dev); + adc->super = super; + + /* ADC Channels + 1 temperature sensor */ + indio_dev->num_channels = 1; + indio_dev->channels = &ts_temp_channel; + + indio_dev->name = dev_name(&pdev->dev); + indio_dev->dev.parent = &pdev->dev; + indio_dev->dev.of_node = pdev->dev.of_node; + indio_dev->info = &ts_adc_info; + + return devm_iio_device_register(&pdev->dev, indio_dev); +} + +static struct platform_driver tsadc_driver = { + .driver = { + .name = "tssupervisor-temp", + }, + .probe = ts_supervisor_temp_probe, +}; +module_platform_driver(tsadc_driver); + +MODULE_DESCRIPTION("embeddedTS supervisor temperature sensor"); +MODULE_AUTHOR("Mark Featherston "); +MODULE_LICENSE("GPL"); From b30b0c237af7e0d6f56ff71e1e80da4b0ef5f38a Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Wed, 8 Mar 2023 08:55:55 -0700 Subject: [PATCH 045/244] reset: tssupervisor-reset: Initial commit of embeddedTS supervisory reset controller --- drivers/power/reset/Kconfig | 6 + drivers/power/reset/Makefile | 1 + drivers/power/reset/tssupervisor-reset.c | 161 +++++++++++++++++++++++ 3 files changed, 168 insertions(+) create mode 100644 drivers/power/reset/tssupervisor-reset.c diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig index 8248895ca9038..a45187d44a51f 100644 --- a/drivers/power/reset/Kconfig +++ b/drivers/power/reset/Kconfig @@ -252,6 +252,12 @@ config POWER_RESET_TPS65086 help This driver adds support for resetting the TPS65086 PMIC on restart. +config POWER_RESET_TS_SUPERVISOR + bool "embeddedTS Supervisory reset driver" + depends on MFD_TS_SUPERVISOR + help + Reset support for embeddedTS boards + config POWER_RESET_VERSATILE bool "ARM Versatile family reboot driver" depends on ARM diff --git a/drivers/power/reset/Makefile b/drivers/power/reset/Makefile index 51da87e05ce76..50c82f9f63417 100644 --- a/drivers/power/reset/Makefile +++ b/drivers/power/reset/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_POWER_RESET_ST) += st-poweroff.o obj-$(CONFIG_POWER_RESET_TH1520_AON) += th1520-aon-reboot.o obj-$(CONFIG_POWER_RESET_TORADEX_EC) += tdx-ec-poweroff.o obj-$(CONFIG_POWER_RESET_TPS65086) += tps65086-restart.o +obj-$(CONFIG_POWER_RESET_TS_SUPERVISOR) += tssupervisor-reset.o obj-$(CONFIG_POWER_RESET_VERSATILE) += arm-versatile-reboot.o obj-$(CONFIG_POWER_RESET_VEXPRESS) += vexpress-poweroff.o obj-$(CONFIG_POWER_RESET_XGENE) += xgene-reboot.o diff --git a/drivers/power/reset/tssupervisor-reset.c b/drivers/power/reset/tssupervisor-reset.c new file mode 100644 index 0000000000000..284f67f73147c --- /dev/null +++ b/drivers/power/reset/tssupervisor-reset.c @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include +#include +#include +#include +#include +#include +#include +#include + +/* We need a static device to support this for shutdown/reboot hooks */ +static struct device *ts_rstc_device; +static atomic_t ts_restart_nb_refcnt = ATOMIC_INIT(0); + +static ssize_t reboot_reason_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct ts_supervisor *super = dev_get_drvdata(dev); + uint32_t reason; + int len, err; + + err = regmap_read(super->regmap, SUPER_REBOOT_REASON, &reason); + if (err < 0) + dev_err(dev, "error reading reg %u", SUPER_REBOOT_REASON); + + switch (reason) { + case REBOOT_REASON_POR: + len = sprintf(buf, "POR\n"); + break; + case REBOOT_REASON_CPU_WDT: + len = sprintf(buf, "CPU WDT\n"); + break; + case REBOOT_REASON_SOFTWARE_REBOOT: + len = sprintf(buf, "Software Reboot\n"); + break; + case REBOOT_REASON_BROWNOUT: + len = sprintf(buf, "Brownout\n"); + break; + case REBOOT_REASON_RTC_ALARM_REBOOT: + len = sprintf(buf, "RTC Alarm Reboot\n"); + break; + case REBOOT_REASON_WAKE_FROM_PWR_CYCLE: + len = sprintf(buf, "Wake from PWR Cycle\n"); + break; + case REBOOT_REASON_WAKE_FROM_WAKE_SIGNAL: + len = sprintf(buf, "Wake from WAKE_EN\n"); + break; + case REBOOT_REASON_WAKE_FROM_RTC_ALARM: + len = sprintf(buf, "Wake from RTC Alarm\n"); + break; + case REBOOT_REASON_WAKE_FROM_USB_VBUS: + len = sprintf(buf, "Wake from USB VBUS\n"); + break; + default: + len = sprintf(buf, "Unknown\n"); + break; + } + + return len; +} +static DEVICE_ATTR_RO(reboot_reason); + +static struct attribute *ts_supervisor_sysfs_entries[] = { + &dev_attr_reboot_reason.attr, + NULL, +}; + +static struct attribute_group ts_supervisor_attr_group = { + .attrs = ts_supervisor_sysfs_entries, +}; + +static int ts_supervisor_restart(struct notifier_block *this, + unsigned long mode, + void *cmd) +{ + int err = -ENOENT; + struct ts_supervisor *super = dev_get_drvdata(ts_rstc_device); + + if (super) { + err = regmap_write(super->regmap, SUPER_CMDS, I2C_REBOOT); + if (!err) + mdelay(1000); + } + + dev_emerg(ts_rstc_device, "reset controller could not cause a reset!"); + + return NOTIFY_DONE; +} + +static struct notifier_block ts_supervisor_restart_nb = { + .notifier_call = ts_supervisor_restart, + .priority = 128, +}; + +static void ts_supervisor_poweroff(void) +{ + int err = -ENOENT; + struct ts_supervisor *super = dev_get_drvdata(ts_rstc_device); + + if (super) { + err = regmap_write(super->regmap, SUPER_CMDS, I2C_HALT); + if (!err) + mdelay(1000); + } + + dev_emerg(ts_rstc_device, "Unable to call halt (%d)", err); +} + +static int ts_supervisor_rstc_probe(struct platform_device *pdev) +{ + struct ts_supervisor *super = dev_get_drvdata(pdev->dev.parent); + struct device *dev = &pdev->dev; + uint32_t features; + int err = 0; + + err = regmap_read(super->regmap, SUPER_FEATURES0, &features); + if (err < 0) + dev_err(dev, "error reading reg %u", SUPER_FEATURES0); + + if ((features & SUPER_FEAT_RSTC) == 0) { + /* Reset controller not supported on this supervisor */ + return 0; + } + + dev_set_drvdata(dev, super); + if (atomic_inc_return(&ts_restart_nb_refcnt) == 1) { + ts_rstc_device = dev; + pm_power_off = ts_supervisor_poweroff; + + err = register_restart_handler(&ts_supervisor_restart_nb); + if (err) { + dev_err(dev, "cannot register restart handler (err=%d)\n", err); + atomic_dec(&ts_restart_nb_refcnt); + return err; + } + } else { + err = EEXIST; + dev_err(dev, "rstc already registered"); + } + + err = sysfs_create_group(&dev->kobj, &ts_supervisor_attr_group); + if (err) + dev_warn(dev, "error creating sysfs entries\n"); + + dev_info(dev, "Using supervisor for reset controller"); + + return 0; +} + +static struct platform_driver tssupervisor_rstc_driver = { + .driver = { + .name = "tssupervisor-reset", + }, + .probe = ts_supervisor_rstc_probe, +}; + +module_platform_driver(tssupervisor_rstc_driver); + +MODULE_DESCRIPTION("embeddedTS supervisor reset controller driver"); +MODULE_AUTHOR("Mark Featherston "); +MODULE_LICENSE("GPL"); From 9768890d51561ed81092080c6e0f9223b6439e7f Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Wed, 8 Mar 2023 08:58:22 -0700 Subject: [PATCH 046/244] ARM: dts: imx6ul: Initial commit of TS-7250-V3 device tree --- arch/arm/boot/dts/nxp/imx/Makefile | 2 + .../boot/dts/nxp/imx/imx6ul-ts7250v3-reva.dts | 26 + arch/arm/boot/dts/nxp/imx/imx6ul-ts7250v3.dts | 17 + .../arm/boot/dts/nxp/imx/imx6ul-ts7250v3.dtsi | 1012 +++++++++++++++++ 4 files changed, 1057 insertions(+) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-ts7250v3-reva.dts create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-ts7250v3.dts create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-ts7250v3.dtsi diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx/Makefile index ee947080a9211..0f6277c62d288 100644 --- a/arch/arm/boot/dts/nxp/imx/Makefile +++ b/arch/arm/boot/dts/nxp/imx/Makefile @@ -355,6 +355,8 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ul-ts4100-7.dtb \ imx6ul-ts4100-8.dtb \ imx6ul-ts4100-16.dtb \ + imx6ul-ts7250v3-reva.dtb \ + imx6ul-ts7250v3.dtb \ imx6ul-ts7553v2.dtb \ imx6ul-tx6ul-0010.dtb \ imx6ul-tx6ul-0011.dtb \ diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7250v3-reva.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7250v3-reva.dts new file mode 100644 index 0000000000000..8fc9e9d07671d --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7250v3-reva.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (C) 2019-2022 Technologic Systems, Inc. dba embeddedTS + */ + +/dts-v1/; +#include +#include +#include "imx6ul-ts7250v3.dtsi" + +/ { + model = "embeddedTS i.MX6UL TS-7250-V3 (REV A)"; +}; + +&wdt { + status = "okay"; +}; + +&m41t00s { + status = "okay"; +}; + +&pc104bus { + reset-gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; +}; + diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7250v3.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7250v3.dts new file mode 100644 index 0000000000000..9b9afc4cd7180 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7250v3.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (C) 2019-2022 Technologic Systems, Inc. dba embeddedTS + */ + +/dts-v1/; +#include +#include +#include "imx6ul-ts7250v3.dtsi" + +&supervisor { + status = "okay"; +}; + +&supervisor_rtc { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7250v3.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7250v3.dtsi new file mode 100644 index 0000000000000..bb63f0d0796fe --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7250v3.dtsi @@ -0,0 +1,1012 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (C) 2019-2022 Technologic Systems, Inc. dba embeddedTS + */ + +/dts-v1/; +#include +#include +#include "imx6ul.dtsi" + +/ { + model = "embeddedTS i.MX6UL TS-7250-V3"; + compatible = "technologic,ts7250v3", "fsl,imx6ul"; + + aliases { + ethernet0 = &fec1; + ethernet1 = &fec2; + pc104bus = &pc104bus; + serial8 = &fpga_uart0; + serial9 = &fpga_uart1; + serial10 = &fpga_uart2; + serial11 = &fpga_uart3; + serial12 = &fpga_uart4; + serial13 = &fpga_uart5; + serial14 = &fpga_uart6; + serial15 = &fpga_uart7; + serial16 = &fpga_uart8; + spi4 = &opencores_spi0; + spi5 = &opencores_spi1; + gpio5 = &fpga_bank0; + gpio6 = &fpga_bank1; + gpio7 = &fpga_bank2; + gpio8 = &fpga_bank3; + gpio9 = &fpga_bank4; + gpio10 = &fpga_bank5; + gpio11 = &pc104gpio; + }; + + chosen { + stdout-path = &uart1; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + led-controller { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cpu_leds>; + compatible = "gpio-leds"; + + led-0 { + color = ; + function = LED_FUNCTION_POWER; + gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + led-1 { + color = ; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + reg_3v3: rev_3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vref_adc_2v5: adc { + compatible = "regulator-fixed"; + regulator-name = "ADC_VREF"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + }; + + an_3p3v: an_3p3v { + compatible = "voltage-divider"; + io-channels = <&supervisor_adc 0>; + label = "3.3V"; + output-ohms = <100000>; /* R2 (100k) */ + full-ohms = <110700>; /* R1 (10.7k) + R2 (100k) */ + #io-channel-cells = <0>; + }; + + an_5v: an_5v { + compatible = "voltage-divider"; + io-channels = <&supervisor_adc 3>; + label = "5V_A"; + output-ohms = <42200>; /* R2 (42.2k) */ + full-ohms = <84400>; /* R1 (42.2k) + R2 (42.2k) */ + #io-channel-cells = <0>; + }; + + an_8v_48v: an_8v_48v { + compatible = "voltage-divider"; + io-channels = <&supervisor_adc 4>; + label = "8V_48V"; + output-ohms = <10700>; /* R2 (10.7k) */ + full-ohms = <247700>; /* R1 (237K) + R2 (10.7k) */ + #io-channel-cells = <0>; + }; + + /* + * At the time of writing, there is a locking bug when using AFE channels + * that can be consumed within the kernel. The hwmon device is disabled + * until this is resolved + */ + supervisor-adcs { + compatible = "iio-hwmon"; + io-channels = <&an_3p3v>, <&supervisor_adc 1>, <&supervisor_adc 2>, + <&supervisor_adc 3>, <&an_5v>, <&an_8v_48v>; + io-channel-names = "3.3V", "VDD_ARM_CAP", "VDD_SOC_CAP", "5V_A", "8V_48V"; + status = "disabled"; + }; + + supervisor-temp { + compatible = "iio-hwmon"; + io-channels = <&supervisor_temp>; + io-channel-names = "Supervisor Temp"; + status = "okay"; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + magnet: magnetometer@1e { + compatible = "st,lis2mdl"; + reg = <0x1e>; + st,drdy-int-pin = <1>; + interrupt-parent = <&gpio1>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; + }; + + wdt: watchdog@54 { + compatible = "technologic,ts7100-wdt"; + /* 5min timeout default, in case of slow userspace. + * Set to 0 to disable WDT at startup. Userspace procs + * can still start feeding later. + */ + timeout-sec = <300>; + reg = <0x54>; + status = "disabled"; + }; + + supervisor: supervisor@10 { + compatible = "technologic,supervisor"; + reg = <0x10>; + status = "disabled"; + + supervisor_adc: supervisor_adc { + compatible = "technologic,supervisor-adc"; + #io-channel-cells = <1>; + }; + + supervisor_temp: supervisor_temp { + compatible = "technologic,supervisor-temp"; + #io-channel-cells = <0>; + }; + }; + + m41t00s: rtc@68 { + compatible = "m41t00"; + reg = <0x68>; + status = "disabled"; + }; + + supervisor_rtc: rtc@68 { + compatible = "technologic,supervisor-rtc"; + reg = <0x68>; + wakeup-source; + status = "disabled"; + }; + + ism330: gyro@6a { + compatible = "st,ism330dlc"; + reg = <0x6a>; + interrupt-parent = <&gpio5>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +&adc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc1>; + vref-supply = <&vref_adc_2v5>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&ecspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + num-cs = <1>; + cs-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; + status = "okay"; + + wilc3000: wifi@0 { + compatible = "microchip,wilc3000"; + reg = <0>; + spi-max-frequency = <20000000>; + reset-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; + chip_en-gpios = <&gpio5 6 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio3>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + phy-supply = <®_3v3>; + + status = "okay"; + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + clocks = <&clks IMX6UL_CLK_ENET_REF>; + clock-names = "rmii-ref"; + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + }; + + ethphy1: ethernet-phy@1 { + clocks = <&clks IMX6UL_CLK_ENET_REF>; + clock-names = "rmii-ref"; + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + phy-supply = <®_3v3>; + status = "okay"; +}; + +&gpio1 { + gpio-line-names = + "AN_CH1", "AN_CH2", "", "", "", "AN_CH3", "", "", "AN_CH4", + "AN_CH5", "", "SEL_XBEE_USB", "", "FPGA_RESET", "MAGNET_IRQ", + "", "CONSOLE_TXD", "CONSOLE_RXD", "EN_RED_LED#", "EN_GRN_LED#", + "", "EN_XBEE_USB", "", "", "", "", "", "", "", "", "EN_DIO_FET", + "NIM_PWR_ON"; +}; + +&gpio3 { + gpio-line-names = + "EN_USB_5V", "", "", "UART4_CTS#", "", "I2C_3_DAT", + "I2C_3_CLK", "ISA_RESET", "ISA_IOCHK", "LCD_PIN7", "LCD_PIN8", + "LCD_PIN9", "LCD_PIN10", "", "", "LCD_PIN11", "LCD_PIN12", + "LCD_PIN13", "LCD_PIN14", "LCD_WR#", "LCD_EN", "LCD_RS", "", + "", "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + "FPGA_FLASH_SELECT", "DETECT_94-120", "", "", "", "", "", "", + "", "", "EIM_IRQ", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", "", ""; +}; + +&gpio5 { + gpio-line-names = + "", "", "", "", "", "", "EN_WIFI_PWR", "EN_CL_1", "EN_CL_2", + "EN_CL_3", "", "", "", "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", ""; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio3 06 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio3 05 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pc104gpio: pca9555@20 { + compatible = "nxp,pca9555"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = "ISA_CN_D03", "ISA_CN_D04", "ISA_CN_D05", + "ISA_CN_D06", "ISA_CN_D07", "ISA_CN_D08", "ISA_CN_D09", + "ISA_CN_D10", "ISA_CN_D11", "ISA_CN_D12", "ISA_CN_D13", + "ISA_CN_D14", "ISA_CN_D15", "", "", ""; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + uart-has-rtscts; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + no-1-8-v; + disable-wp; + non-removable; + bus-width = <4>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + no-1-8-v; + disable-wp; + broken-cd; + bus-width = <4>; + status = "okay"; +}; + +&snvs_rtc { + status = "disabled"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + status = "okay"; + fsl,ext-reset-output; +}; + +&weim { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_weim_fpga &pinctrl_weim_cs0>; + #address-cells = <2>; + #size-cells = <1>; + clocks = <&clks IMX6UL_CLK_EIM>, <&clks IMX6UL_CLK_EIM_SLOW_SEL>; + ranges = <0 0 0x50000000 0x08000000>; + status = "okay"; + + fpga: fpga@50000000 { + compatible = "simple-bus"; + reg = <0 0x50000000 0x00010000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0x10000>; + + fsl,weim-cs-timing = < + 0x0161030F // EIM_CSnGCR1 @ 0x021b8000 + 0x00000000 // EIM_CSnGCR2 @ 0x021b8004 + 0x03000000 // EIM_CSnRCR1 @ 0x021b8008 + 0x00000000 // EIM_CSnRCR2 @ 0x021b800c + 0x01000000 // EIM_CSnWCR1 @ 0x021b8010 + 0 // EIM_CSnWCR2 @ 0x021b8014 + >; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + fpga_clk_weim_bclk: fpga_clk_weim_bclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <79200000>; + }; + }; + + syscon: syscon@4000 { + compatible = "simple-bus"; + #address-cells = <0x1>; + #size-cells = <0x1>; + reg = <0x4000 0x100>; + ranges = <0 0x4000 0x100>; + + fpga_intc: fpga_intc@0 { + compatible = "technologic,ts71xxweim-intc"; + reg = <0x0 0x50>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&gpio5>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; + }; + + fpga_bank0: fpga_gpio@10 { + compatible = "technologic,ts71xxweim-gpio"; + reg = <0x10 0x08>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + + gpio-line-names = "", "DIO_PIN1", "DIO_PIN3", + "DIO_PIN5", "DIO_PIN7", "DIO_PIN8", + "DIO_PIN9", "DIO_PIN11", "DIO_PIN13", + "DIO_PIN15", "DIO_SPI_MISO", + "DIO_SPI_CS#", "", "", "DIO_SPI_CLK", + "DIO_SPI_MOSI"; + }; + + fpga_bank1: fpga_gpio@40 { + compatible = "technologic,ts71xxweim-gpio"; + reg = <0x40 0x08>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + + gpio-line-names = "ISA_AEN", "ISA_BALE", + "ISA_TC", "ISA_ENDX", "EN_NIMBEL_3V3", + "ISA_IORDY", "ISA_REFRESH", "ISA_DRQ1", + "ISA_DACK1", "ISA_DRQ2", "ISA_DACK2", + "EN_NIMBEL_4V", "ISA_DRQ3", "ISA_DACK3", + "", "EN_RS422"; + }; + + fpga_bank2: fpga_gpio@54 { + compatible = "technologic,ts71xxweim-gpio"; + reg = <0x54 0x08>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + + gpio-line-names = + "MIKRO_RESET#", "MIKRO_AN", "MIKRO_INT", + "MIKRO_180", "MIKRO_PWM", + "MIKRO_SPI_CS#", "MIKRO_SPI_CLK", + "MIKRO_SPI_MISO", "MIKRO_SPI_MOSI", + "MIKRO_TXD", "MIKRO_RXD", + "MIKRO_I2C_DAT", "MIKRO_I2C_CLK", "", + "", ""; + }; + + fpga_bank3: fpga_gpio@5c { + compatible = "technologic,ts71xxweim-gpio"; + reg = <0x5c 0x08>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + + gpio-line-names = "ISA_DAT00", "ISA_DAT01", + "ISA_DAT02", "ISA_DAT03", "ISA_DAT04", + "ISA_DAT05", "ISA_DAT06", "ISA_DAT07", + "ISA_DAT08", "ISA_DAT09", "ISA_DAT10", + "ISA_DAT11", "ISA_DAT12", "ISA_DAT13", + "ISA_DAT14", "ISA_DAT15"; + }; + + fpga_bank4: fpga_gpio@64 { + compatible = "technologic,ts71xxweim-gpio"; + reg = <0x64 0x08>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + + gpio-line-names = "ISA_ADD_00", "ISA_ADD_01", + "ISA_ADD_02", "ISA_ADD_03", + "ISA_ADD_04", "ISA_ADD_05", + "ISA_ADD_06", "ISA_ADD_07", + "ISA_ADD_08", "ISA_ADD_09", + "ISA_ADD_10", "ISA_ADD_11", + "ISA_ADD_12", "ISA_ADD_13", + "ISA_ADD_14", "ISA_ADD_15"; + }; + + fpga_bank5: fpga_gpio@6c { + compatible = "technologic,ts71xxweim-gpio"; + reg = <0x6c 0x08>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + + gpio-line-names = "ISA_ADD_16", "ISA_ADD_17", + "ISA_ADD_18", "ISA_ADD_19", "ISA_IOR", + "ISA_IOW", "ISA_MEMR", "ISA_MEMW", + "ISA_CN_D01", "ISA_CN_D02", "", "", "", + "", "", ""; + }; + + pc104bus: fpgaisa@50 { + compatible = "technologic,pc104-bus"; + reg = <0x50 0x4>; + + ranges = <0 0 0x1000>; + reset-gpio = <&gpio3 7 GPIO_ACTIVE_LOW>; + + #address-cells = <0x1>; + #size-cells = <0x1>; + }; + }; + + /* DB9 */ + fpga_uart0: serial@0 { + compatible = "ns16550a"; + device_type = "serial"; + reg = <0x0 16>; + + current-speed = <115200>; + reg-shift = <1>; + reg-io-width = <1>; + fifo-size = <64>; + clock-frequency = <1843200>; + interrupt-parent = <&fpga_intc>; + interrupts = <0>; + }; + + /* COM2 RS-232 */ + fpga_uart1: serial@10 { + compatible = "ns16550a"; + device_type = "serial"; + reg = <0x10 16>; + + current-speed = <115200>; + reg-shift = <1>; + reg-io-width = <1>; + fifo-size = <64>; + clock-frequency = <1843200>; + interrupt-parent = <&fpga_intc>; + interrupts = <1>; + }; + + /* COM3 RS-232 */ + fpga_uart2: serial@20 { + compatible = "ns16550a"; + device_type = "serial"; + reg = <0x20 16>; + + current-speed = <115200>; + reg-shift = <1>; + reg-io-width = <1>; + fifo-size = <64>; + clock-frequency = <1843200>; + interrupt-parent = <&fpga_intc>; + interrupts = <2>; + }; + + /* COM2 RS-485 */ + fpga_uart3: serial@30 { + compatible = "ns16550a"; + device_type = "serial"; + reg = <0x30 16>; + + current-speed = <115200>; + reg-shift = <1>; + reg-io-width = <1>; + fifo-size = <64>; + clock-frequency = <1843200>; + interrupt-parent = <&fpga_intc>; + interrupts = <3>; + }; + + /* COM2 RS-422 */ + fpga_uart4: serial@40 { + compatible = "ns16550a"; + device_type = "serial"; + reg = <0x40 16>; + + current-speed = <115200>; + reg-shift = <1>; + reg-io-width = <1>; + fifo-size = <64>; + clock-frequency = <1843200>; + interrupt-parent = <&fpga_intc>; + interrupts = <4>; + }; + + /* Mikrobus UART */ + fpga_uart5: serial@50 { + compatible = "ns16550a"; + device_type = "serial"; + reg = <0x50 16>; + + current-speed = <115200>; + reg-shift = <1>; + reg-io-width = <1>; + fifo-size = <64>; + clock-frequency = <1843200>; + interrupt-parent = <&fpga_intc>; + interrupts = <5>; + }; + + fpga_uart6: serial@60 { + compatible = "ns16550a"; + device_type = "serial"; + reg = <0x60 16>; + + current-speed = <115200>; + reg-shift = <1>; + reg-io-width = <1>; + fifo-size = <64>; + clock-frequency = <1843200>; + interrupt-parent = <&fpga_intc>; + interrupts = <6>; + }; + + fpga_uart7: serial@70 { + compatible = "ns16550a"; + device_type = "serial"; + reg = <0x70 16>; + + current-speed = <115200>; + reg-shift = <1>; + reg-io-width = <1>; + fifo-size = <64>; + clock-frequency = <1843200>; + interrupt-parent = <&fpga_intc>; + interrupts = <7>; + }; + + fpga_uart8: serial@80 { + compatible = "ns16550a"; + device_type = "serial"; + reg = <0x80 16>; + + current-speed = <115200>; + reg-shift = <1>; + reg-io-width = <1>; + fifo-size = <64>; + clock-frequency = <1843200>; + interrupt-parent = <&fpga_intc>; + interrupts = <8>; + }; + + opencores_spi0: spi@100 { + compatible = "opencores,spi-oc"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x100 32>; + interrupt-parent = <&fpga_intc>; + interrupts = <9>; + clocks = <&fpga_clk_weim_bclk>; + clock-names = "spi-oc-clk"; + opencores-spi,idx = <0>; + opencores-spi,num-chipselects = <3>; + + dioheader: spi@0 { + compatible = "spidev"; + spi-max-frequency = <19800000>; + reg = <0>; + }; + + spifram: spi@1 { + compatible = "cypress,fm25l16b", "atmel,at25"; + reg = <1>; + spi-max-frequency = <19800000>; + size = <0x800>; + address-width = <16>; + pagesize = <64>; + }; + + /* Onboard FPGA Flash */ + spifpga: flash@2 { + compatible = "jedec,spi-nor"; + reg = <2>; + spi-max-frequency = <19800000>; + }; + }; + + opencores_spi1: spi@120 { + compatible = "opencores,spi-oc"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x120 32>; + interrupt-parent = <&fpga_intc>; + interrupts = <10>; + clocks = <&fpga_clk_weim_bclk>; + clock-names = "spi-oc-clk"; + opencores-spi,idx = <0>; + opencores-spi,num-chipselects = <1>; + + mikrobus: spi@0 { + compatible = "spidev"; + spi-max-frequency = <19800000>; + reg = <0>; + }; + }; + + mikro_adc0: mikro_adc@180 { + compatible = "technologic,ts-simple-adc"; + reg = <0x180 4>; + interrupt-parent = <&fpga_intc>; + interrupts = <19>; + }; + + mikro_i2c: mikro_i2c@188 { + compatible = "opencores,i2c-ocores"; + reg = <0x188 16>; + interrupt-parent = <&fpga_intc>; + interrupts = <20>; + clocks = <&fpga_clk_weim_bclk>; + clock-names = "i2c-oc-clk"; + reg-io-width = <1>; + reg-shift = <1>; + }; + + mikro_pwm: mikro_pwm@1a8 { + compatible = "technologic,pwm"; + reg = <0x1a8 8>; + clocks = <&fpga_clk_weim_bclk>; + clock-names = "PWM-INPUT-CLK"; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&ts7250v3_pinctrl_hog>; + + imx6ul-ts7250v3 { + ts7250v3_pinctrl_hog: hoggrp { + fsl,pins = < + /* + * 0x1b020 == Hyst., 100k PU, 50 mA drive + * 0x1a020 == no pull resistor + * 0x13020 == 100k PD + */ + + MX6UL_PAD_LCD_DATA02__GPIO3_IO07 0x13020 /* ISA_RESET */ + MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0x13020 /* ISA_IOCHK */ + + MX6UL_PAD_LCD_DATA04__GPIO3_IO09 0x1a020 /* LCD_PIN7 */ + MX6UL_PAD_LCD_DATA05__GPIO3_IO10 0x1a020 /* LCD_PIN8 */ + MX6UL_PAD_LCD_DATA06__GPIO3_IO11 0x1a020 /* LCD_PIN9 */ + MX6UL_PAD_LCD_DATA07__GPIO3_IO12 0x1a020 /* LCD_PIN10 */ + MX6UL_PAD_LCD_DATA10__GPIO3_IO15 0x1a020 /* LCD_PIN11 */ + MX6UL_PAD_LCD_DATA11__GPIO3_IO16 0x1a020 /* LCD_PIN12 */ + MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x1a020 /* LCD_PIN13 */ + MX6UL_PAD_LCD_DATA13__GPIO3_IO18 0x1a020 /* LCD_PIN14 */ + MX6UL_PAD_LCD_DATA14__GPIO3_IO19 0x1a020 /* LCD_WR# */ + MX6UL_PAD_LCD_DATA15__GPIO3_IO20 0x1a020 /* LCD_EN */ + MX6UL_PAD_LCD_DATA16__GPIO3_IO21 0x1a020 /* LCD_RS */ + + MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21 0x13020 /* EN_XBEE_USB */ + MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x13020 /* NIM_PWR_ON */ + MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x13020 /* EN_DIO_FET */ + MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x1b029 /* FPGA_RESET */ + MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x13020 /* SEL_XBEE_USB */ + MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x1b029 /* FPGA IRQ */ + + MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1a020 /* EN_CL_1 */ + MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x1a020 /* EN_CL_2 */ + MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1a020 /* EN_CL_3 */ + MX6UL_PAD_LCD_CLK__GPIO3_IO00 0x1b020 /* EN_USB_5V */ + MX6UL_PAD_NAND_RE_B__GPIO4_IO00 0x1b029 /* FPGA_FLASH_SELECT */ + MX6UL_PAD_NAND_WE_B__GPIO4_IO01 0x1b029 /* DETECT_94-120 */ + >; + }; + + pinctrl_cpu_leds: cpuledgrp { + fsl,pins = < + /* Red LED */ + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x1b020 + /* Green LED */ + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x1b020 + >; + }; + + pinctrl_adc1: adc1grp{ + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x20 + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x20 + MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x20 + MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x20 + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x20 + >; + }; + + pinctrl_flexcan1: flexcan1grp{ + fsl,pins = < + MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX 0x1b020 + MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX 0x1b020 + >; + }; + + pinctrl_flexcan2: flexcan2grp{ + fsl,pins = < + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 + MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 + MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1 + MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1 + MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1 + MX6UL_PAD_LCD_VSYNC__UART4_DCE_RTS 0x1b0b1 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x4001a8b0 + MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x4001a8b0 + >; + }; + + pinctrl_i2c1_gpio: i2c1grpgpio { + fsl,pins = < + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x108B0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x108B0 + MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x1b020 /* MAGNET_IRQ */ + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b020 /* GYRO_INT */ + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6UL_PAD_NAND_READY_B__GPIO4_IO12 0x10b0 /* SPI_3_CS# */ + MX6UL_PAD_NAND_CE0_B__ECSPI3_SCLK 0x10b0 + MX6UL_PAD_NAND_CE1_B__ECSPI3_MOSI 0x10b0 + MX6UL_PAD_NAND_CLE__ECSPI3_MISO 0x10b0 + MX6UL_PAD_LCD_ENABLE__GPIO3_IO01 0x1b020 /* WIFI_IRQ# */ + MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x100b1 /* WIFI_RESET# */ + MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x100b1 /* EN_WIFI_PWR */ + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__I2C3_SDA 0x4001a8b0 + MX6UL_PAD_LCD_DATA01__I2C3_SCL 0x4001a8b0 + >; + }; + + pinctrl_i2c3_gpio: i2c3grpgpio { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x4001a8b0 + MX6UL_PAD_LCD_DATA01__GPIO3_IO06 0x4001a8b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b020 /* EN_EMMC_3.3V */ + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA18__USDHC2_CMD 0x17059 + MX6UL_PAD_LCD_DATA19__USDHC2_CLK 0x10071 + MX6UL_PAD_LCD_DATA20__USDHC2_DATA0 0x17059 + MX6UL_PAD_LCD_DATA21__USDHC2_DATA1 0x17059 + MX6UL_PAD_LCD_DATA22__USDHC2_DATA2 0x17059 + MX6UL_PAD_LCD_DATA23__USDHC2_DATA3 0x17059 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x1b020 /* EN_SD_CARD_3.3V */ + >; + }; + + pinctrl_dvfs: dvfsgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0a0 + >; + }; + pinctrl_weim_cs0: weimcs0grp { + fsl,pins = < + MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0xb029 /* EIM_CS0# */ + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0xb029 + >; + }; + + pinctrl_weim_fpga: weimfpgagrp { + fsl,pins = < + /* EIM_OE# */ + MX6UL_PAD_CSI_PIXCLK__EIM_OE 0x1b069 + /* EIM_WE# */ + MX6UL_PAD_CSI_VSYNC__EIM_RW 0x1b069 + /* EIM_LBA# */ + MX6UL_PAD_CSI_HSYNC__EIM_LBA_B 0x1b069 + /* EIM_IRQ */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x1b069 + /* EIM_WAIT */ + MX6UL_PAD_NAND_DQS__EIM_WAIT 0x1b069 + /* EIM_BCLK */ + MX6UL_PAD_NAND_WP_B__EIM_BCLK 0x1b069 + + /* EIM Address */ + MX6UL_PAD_NAND_DATA07__EIM_AD15 0x1b069 + MX6UL_PAD_NAND_DATA06__EIM_AD14 0x1b069 + MX6UL_PAD_NAND_DATA05__EIM_AD13 0x1b069 + MX6UL_PAD_NAND_DATA04__EIM_AD12 0x1b069 + MX6UL_PAD_NAND_DATA03__EIM_AD11 0x1b069 + MX6UL_PAD_NAND_DATA02__EIM_AD10 0x1b069 + MX6UL_PAD_NAND_DATA01__EIM_AD09 0x1b069 + MX6UL_PAD_NAND_DATA00__EIM_AD08 0x1b069 + MX6UL_PAD_CSI_DATA07__EIM_AD07 0x1b069 + MX6UL_PAD_CSI_DATA06__EIM_AD06 0x1b069 + MX6UL_PAD_CSI_DATA05__EIM_AD05 0x1b069 + MX6UL_PAD_CSI_DATA04__EIM_AD04 0x1b069 + MX6UL_PAD_CSI_DATA03__EIM_AD03 0x1b069 + MX6UL_PAD_CSI_DATA02__EIM_AD02 0x1b069 + MX6UL_PAD_CSI_DATA01__EIM_AD01 0x1b069 + MX6UL_PAD_CSI_DATA00__EIM_AD00 0x1b069 + >; + }; + }; +}; + +&usbotg1 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; From 75374f51d500c56fb31dcf68f135dfcc12f82407 Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Wed, 8 Mar 2023 16:15:53 -0700 Subject: [PATCH 047/244] arm: configs: Initial commit of defconfig for embeddedTS i.MX6ul systems --- arch/arm/configs/tsimx6ul_defconfig | 839 ++++++++++++++++++++++++++++ 1 file changed, 839 insertions(+) create mode 100644 arch/arm/configs/tsimx6ul_defconfig diff --git a/arch/arm/configs/tsimx6ul_defconfig b/arch/arm/configs/tsimx6ul_defconfig new file mode 100644 index 0000000000000..cc36cb4f2a71e --- /dev/null +++ b/arch/arm/configs/tsimx6ul_defconfig @@ -0,0 +1,839 @@ +CONFIG_KERNEL_LZO=y +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_PREEMPT=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_CGROUPS=y +CONFIG_MEMCG=y +CONFIG_BLK_CGROUP=y +CONFIG_CGROUP_SCHED=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_RDMA=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CPUSETS=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_PERF=y +CONFIG_NAMESPACES=y +CONFIG_USER_NS=y +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_EXPERT=y +CONFIG_BPF_SYSCALL=y +CONFIG_KCMP=y +CONFIG_PC104=y +CONFIG_PERF_EVENTS=y +# CONFIG_SLUB_DEBUG is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_ARCH_MXC=y +CONFIG_SOC_IMX6UL=y +CONFIG_ARM_ERRATA_754322=y +CONFIG_ARM_ERRATA_764369=y +CONFIG_ARM_ERRATA_775420=y +CONFIG_SMP=y +CONFIG_HAVE_ARM_ARCH_TIMER=y +CONFIG_ARM_PSCI=y +CONFIG_HIGHMEM=y +CONFIG_FORCE_MAX_ZONEORDER=14 +CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" +CONFIG_KEXEC=y +CONFIG_EFI=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPUFREQ_DT=y +CONFIG_ARM_IMX6Q_CPUFREQ=y +CONFIG_CPU_IDLE=y +CONFIG_ARM_CPUIDLE=y +CONFIG_ARM_PSCI_CPUIDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_PM_DEBUG=y +CONFIG_PM_TEST_SUSPEND=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_BLK_DEV_BSGLIB=y +CONFIG_BLK_DEV_THROTTLING=y +CONFIG_BINFMT_MISC=m +CONFIG_CMA=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_NETFILTER=y +CONFIG_DNS_RESOLVER=y +CONFIG_CAN=y +CONFIG_CAN_FLEXCAN=y +CONFIG_BT=y +CONFIG_BT_BNEP=m +CONFIG_BT_HCIUART=y +CONFIG_BT_HCIUART_LL=y +CONFIG_CFG80211=y +CONFIG_CFG80211_WEXT=y +CONFIG_MAC80211=y +CONFIG_RFKILL=y +CONFIG_RFKILL_INPUT=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +CONFIG_EXTRA_FIRMWARE="imx/sdma/sdma-imx6q.bin" +CONFIG_EXTRA_FIRMWARE_DIR="firmware" +CONFIG_FW_LOADER_USER_HELPER=y +CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y +CONFIG_IMX_WEIM=y +CONFIG_TSPC104=y +CONFIG_CONNECTOR=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_DATAFLASH=y +CONFIG_MTD_SST25L=y +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD_NAND_MXC=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_FASTMAP=y +CONFIG_MTD_UBI_BLOCK=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=65536 +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_AT25=y +CONFIG_SCSI=y +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_NETDEVICES=y +CONFIG_WIREGUARD=m +CONFIG_MACVLAN=m +CONFIG_IPVLAN=m +CONFIG_VXLAN=m +CONFIG_GENEVE=m +CONFIG_TUN=m +CONFIG_VETH=m +# CONFIG_NET_VENDOR_ALACRITECH is not set +# CONFIG_NET_VENDOR_AMAZON is not set +# CONFIG_NET_VENDOR_AQUANTIA is not set +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_AURORA is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CADENCE is not set +# CONFIG_NET_VENDOR_CAVIUM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_CORTINA is not set +# CONFIG_NET_VENDOR_EZCHIP is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_GOOGLE is not set +# CONFIG_NET_VENDOR_HISILICON is not set +# CONFIG_NET_VENDOR_HUAWEI is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MELLANOX is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_MICROSEMI is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NETRONOME is not set +# CONFIG_NET_VENDOR_NI is not set +# CONFIG_NET_VENDOR_PENSANDO is not set +# CONFIG_NET_VENDOR_QUALCOMM is not set +# CONFIG_NET_VENDOR_RENESAS is not set +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SOLARFLARE is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_SOCIONEXT is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +# CONFIG_NET_VENDOR_XILINX is not set +CONFIG_MICREL_PHY=y +CONFIG_SMSC_PHY=y +CONFIG_PPP=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPPOE=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_USB_CATC=m +CONFIG_USB_KAWETH=m +CONFIG_USB_PEGASUS=m +CONFIG_USB_RTL8150=m +CONFIG_USB_RTL8152=y +CONFIG_USB_LAN78XX=y +CONFIG_USB_USBNET=y +CONFIG_USB_NET_CDC_EEM=m +CONFIG_USB_NET_HUAWEI_CDC_NCM=m +CONFIG_USB_NET_CDC_MBIM=m +CONFIG_USB_NET_DM9601=m +CONFIG_USB_NET_SR9700=m +CONFIG_USB_NET_SR9800=m +CONFIG_USB_NET_SMSC75XX=m +CONFIG_USB_NET_SMSC95XX=m +CONFIG_USB_NET_GL620A=m +CONFIG_USB_NET_NET1080=m +CONFIG_USB_NET_PLUSB=m +CONFIG_USB_NET_MCS7830=m +CONFIG_USB_NET_CDC_SUBSET=m +CONFIG_USB_NET_ZAURUS=m +CONFIG_USB_NET_CX82310_ETH=m +CONFIG_USB_NET_KALMIA=m +CONFIG_USB_NET_QMI_WWAN=m +CONFIG_USB_HSO=m +CONFIG_USB_NET_INT51X1=m +CONFIG_USB_IPHETH=m +CONFIG_USB_SIERRA_NET=m +CONFIG_USB_VL600=m +CONFIG_USB_NET_CH9200=m +CONFIG_USB_NET_AQC111=m +# CONFIG_WLAN_VENDOR_ADMTEK is not set +CONFIG_ATH9K=m +CONFIG_ATH9K_HTC=m +CONFIG_CARL9170=m +CONFIG_AR5523=m +CONFIG_ATH10K=m +CONFIG_ATH10K_USB=m +CONFIG_WCN36XX=m +# CONFIG_WLAN_VENDOR_ATMEL is not set +CONFIG_BRCMFMAC=m +CONFIG_BRCMFMAC_USB=y +# CONFIG_WLAN_VENDOR_CISCO is not set +# CONFIG_WLAN_VENDOR_INTEL is not set +# CONFIG_WLAN_VENDOR_INTERSIL is not set +# CONFIG_WLAN_VENDOR_MARVELL is not set +CONFIG_MT7601U=m +CONFIG_MT76x0U=m +CONFIG_MT76x2U=m +CONFIG_MT7663U=m +# CONFIG_WLAN_VENDOR_MICROCHIP is not set +CONFIG_RT2X00=m +CONFIG_RTL8187=m +CONFIG_RTL_CARDS=m +CONFIG_RTL8192CU=m +# CONFIG_RTLWIFI_DEBUG is not set +CONFIG_RTL8XXXU=m +CONFIG_RTL8XXXU_UNTESTED=y +CONFIG_RTW88=m +# CONFIG_WLAN_VENDOR_RSI is not set +# CONFIG_WLAN_VENDOR_ST is not set +CONFIG_WL12XX=m +CONFIG_WLCORE_SDIO=m +# CONFIG_WILINK_PLATFORM_DATA is not set +CONFIG_USB_ZD1201=m +CONFIG_USB_NET_RNDIS_WLAN=m +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_EVBUG=m +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_MATRIX=m +CONFIG_KEYBOARD_SNVS_PWRKEY=y +CONFIG_KEYBOARD_IMX=y +CONFIG_MOUSE_PS2=m +CONFIG_MOUSE_PS2_ELANTECH=y +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ADS7846=y +CONFIG_TOUCHSCREEN_AD7879=y +CONFIG_TOUCHSCREEN_AD7879_I2C=y +CONFIG_TOUCHSCREEN_ATMEL_MXT=y +CONFIG_TOUCHSCREEN_EGALAX=y +CONFIG_TOUCHSCREEN_GOODIX=y +CONFIG_TOUCHSCREEN_ILI210X=y +CONFIG_TOUCHSCREEN_MAX11801=y +CONFIG_TOUCHSCREEN_IMX6UL_TSC=y +CONFIG_TOUCHSCREEN_EDT_FT5X06=y +CONFIG_TOUCHSCREEN_TSC2004=y +CONFIG_TOUCHSCREEN_TSC2007=y +CONFIG_TOUCHSCREEN_SX8654=y +CONFIG_TOUCHSCREEN_COLIBRI_VF50=y +CONFIG_INPUT_MISC=y +CONFIG_INPUT_MMA8450=y +CONFIG_SERIO_SERPORT=m +CONFIG_VT_HW_CONSOLE_BINDING=y +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_NR_UARTS=24 +CONFIG_SERIAL_8250_RUNTIME_UARTS=24 +CONFIG_SERIAL_8250_TS=m +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_IMX=y +CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_SERIAL_DEV_BUS=y +CONFIG_I2C=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX=y +# CONFIG_I2C_HELPER_AUTO is not set +CONFIG_I2C_ALGOPCF=m +CONFIG_I2C_ALGOPCA=m +CONFIG_I2C_GPIO=y +CONFIG_I2C_IMX=y +CONFIG_SPI=y +CONFIG_SPI_FSL_QUADSPI=y +CONFIG_SPI_GPIO=y +CONFIG_SPI_IMX=y +CONFIG_SPI_OCORES=m +CONFIG_SPI_SPIDEV=y +CONFIG_PPS_CLIENT_LDISC=m +CONFIG_PPS_CLIENT_GPIO=m +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_MXC=y +CONFIG_GPIO_SIOX=m +CONFIG_GPIO_TS71XXWEIM=y +CONFIG_GPIO_PCA953X=y +CONFIG_GPIO_PCF857X=y +CONFIG_GPIO_TS4900=y +CONFIG_GPIO_74X164=m +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_TS_SUPERVISOR=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_POWER_RESET_SYSCON_POWEROFF=y +CONFIG_POWER_SUPPLY=y +CONFIG_SENSORS_GPIO_FAN=y +CONFIG_SENSORS_IIO_HWMON=y +CONFIG_THERMAL=y +CONFIG_THERMAL_STATISTICS=y +CONFIG_THERMAL_WRITABLE_TRIPS=y +CONFIG_CPU_THERMAL=y +CONFIG_IMX_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_TS_WDT_MICRO=y +CONFIG_IMX2_WDT=y +CONFIG_IMX7ULP_WDT=y +CONFIG_MFD_TS_SUPERVISOR=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_ANATOP=y +CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_PFUZE100=y +CONFIG_RC_CORE=y +CONFIG_RC_DEVICES=y +CONFIG_IR_GPIO_CIR=y +# CONFIG_MEDIA_CEC_SUPPORT is not set +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_VIDEO_CLASS=m +CONFIG_USB_M5602=m +CONFIG_USB_STV06XX=m +CONFIG_USB_GL860=m +CONFIG_USB_GSPCA_BENQ=m +CONFIG_USB_GSPCA_CONEX=m +CONFIG_USB_GSPCA_CPIA1=m +CONFIG_USB_GSPCA_DTCS033=m +CONFIG_USB_GSPCA_ETOMS=m +CONFIG_USB_GSPCA_FINEPIX=m +CONFIG_USB_GSPCA_JEILINJ=m +CONFIG_USB_GSPCA_JL2005BCD=m +CONFIG_USB_GSPCA_KINECT=m +CONFIG_USB_GSPCA_KONICA=m +CONFIG_USB_GSPCA_MARS=m +CONFIG_USB_GSPCA_MR97310A=m +CONFIG_USB_GSPCA_NW80X=m +CONFIG_USB_GSPCA_OV519=m +CONFIG_USB_GSPCA_OV534=m +CONFIG_USB_GSPCA_OV534_9=m +CONFIG_USB_GSPCA_PAC207=m +CONFIG_USB_GSPCA_PAC7302=m +CONFIG_USB_GSPCA_PAC7311=m +CONFIG_USB_GSPCA_SE401=m +CONFIG_USB_GSPCA_SN9C2028=m +CONFIG_USB_GSPCA_SN9C20X=m +CONFIG_USB_GSPCA_SONIXB=m +CONFIG_USB_GSPCA_SONIXJ=m +CONFIG_USB_GSPCA_SPCA500=m +CONFIG_USB_GSPCA_SPCA501=m +CONFIG_USB_GSPCA_SPCA505=m +CONFIG_USB_GSPCA_SPCA506=m +CONFIG_USB_GSPCA_SPCA508=m +CONFIG_USB_GSPCA_SPCA561=m +CONFIG_USB_GSPCA_SPCA1528=m +CONFIG_USB_GSPCA_SQ905=m +CONFIG_USB_GSPCA_SQ905C=m +CONFIG_USB_GSPCA_SQ930X=m +CONFIG_USB_GSPCA_STK014=m +CONFIG_USB_GSPCA_STK1135=m +CONFIG_USB_GSPCA_STV0680=m +CONFIG_USB_GSPCA_SUNPLUS=m +CONFIG_USB_GSPCA_T613=m +CONFIG_USB_GSPCA_TOPRO=m +CONFIG_USB_GSPCA_TOUPTEK=m +CONFIG_USB_GSPCA_TV8532=m +CONFIG_USB_GSPCA_VC032X=m +CONFIG_USB_GSPCA_VICAM=m +CONFIG_USB_GSPCA_XIRLINK_CIT=m +CONFIG_USB_GSPCA_ZC3XX=m +CONFIG_USB_PWC=m +CONFIG_VIDEO_CPIA2=m +CONFIG_USB_ZR364XX=m +CONFIG_USB_STKWEBCAM=m +CONFIG_USB_S2255=m +CONFIG_VIDEO_USBTV=m +CONFIG_VIDEO_PVRUSB2=m +CONFIG_VIDEO_HDPVR=m +CONFIG_VIDEO_STK1160_COMMON=m +CONFIG_VIDEO_GO7007=m +CONFIG_VIDEO_AU0828=m +CONFIG_VIDEO_CX231XX=m +CONFIG_VIDEO_TM6000=m +CONFIG_DVB_USB=m +CONFIG_DVB_USB_A800=m +CONFIG_DVB_USB_DIBUSB_MB=m +CONFIG_DVB_USB_DIBUSB_MC=m +CONFIG_DVB_USB_DIB0700=m +CONFIG_DVB_USB_UMT_010=m +CONFIG_DVB_USB_CXUSB=m +CONFIG_DVB_USB_M920X=m +CONFIG_DVB_USB_DIGITV=m +CONFIG_DVB_USB_VP7045=m +CONFIG_DVB_USB_VP702X=m +CONFIG_DVB_USB_GP8PSK=m +CONFIG_DVB_USB_NOVA_T_USB2=m +CONFIG_DVB_USB_TTUSB2=m +CONFIG_DVB_USB_DTT200U=m +CONFIG_DVB_USB_OPERA1=m +CONFIG_DVB_USB_AF9005=m +CONFIG_DVB_USB_AF9005_REMOTE=m +CONFIG_DVB_USB_PCTV452E=m +CONFIG_DVB_USB_DW2102=m +CONFIG_DVB_USB_CINERGY_T2=m +CONFIG_DVB_USB_DTV5100=m +CONFIG_DVB_USB_AZ6027=m +CONFIG_DVB_USB_TECHNISAT_USB2=m +CONFIG_DVB_USB_V2=m +CONFIG_DVB_USB_AF9015=m +CONFIG_DVB_USB_AF9035=m +CONFIG_DVB_USB_ANYSEE=m +CONFIG_DVB_USB_AU6610=m +CONFIG_DVB_USB_AZ6007=m +CONFIG_DVB_USB_CE6230=m +CONFIG_DVB_USB_EC168=m +CONFIG_DVB_USB_GL861=m +CONFIG_DVB_USB_LME2510=m +CONFIG_DVB_USB_MXL111SF=m +CONFIG_DVB_USB_RTL28XXU=m +CONFIG_DVB_USB_DVBSKY=m +CONFIG_DVB_USB_ZD1301=m +CONFIG_SMS_USB_DRV=m +CONFIG_DVB_B2C2_FLEXCOP_USB=m +CONFIG_DVB_AS102=m +CONFIG_VIDEO_EM28XX=m +CONFIG_VIDEO_EM28XX_V4L2=m +CONFIG_VIDEO_EM28XX_ALSA=m +CONFIG_VIDEO_EM28XX_DVB=m +CONFIG_USB_AIRSPY=m +CONFIG_USB_HACKRF=m +CONFIG_USB_MSI2500=m +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_VIDEO_MUX=y +CONFIG_V4L_MEM2MEM_DRIVERS=y +CONFIG_VIDEO_CODA=m +CONFIG_VIDEO_IMX_PXP=y +# CONFIG_VIDEO_IR_I2C is not set +# CONFIG_CXD2880_SPI_DRV is not set +# CONFIG_MEDIA_TUNER_SIMPLE is not set +# CONFIG_MEDIA_TUNER_TDA18250 is not set +# CONFIG_MEDIA_TUNER_TDA8290 is not set +# CONFIG_MEDIA_TUNER_TDA827X is not set +# CONFIG_MEDIA_TUNER_TDA18271 is not set +# CONFIG_MEDIA_TUNER_TDA9887 is not set +# CONFIG_MEDIA_TUNER_TEA5761 is not set +# CONFIG_MEDIA_TUNER_TEA5767 is not set +# CONFIG_MEDIA_TUNER_MT20XX is not set +# CONFIG_MEDIA_TUNER_MT2060 is not set +# CONFIG_MEDIA_TUNER_MT2063 is not set +# CONFIG_MEDIA_TUNER_MT2266 is not set +# CONFIG_MEDIA_TUNER_MT2131 is not set +# CONFIG_MEDIA_TUNER_QT1010 is not set +# CONFIG_MEDIA_TUNER_XC4000 is not set +# CONFIG_MEDIA_TUNER_MXL5005S is not set +# CONFIG_MEDIA_TUNER_MXL5007T is not set +# CONFIG_MEDIA_TUNER_MC44S803 is not set +# CONFIG_MEDIA_TUNER_MAX2165 is not set +# CONFIG_MEDIA_TUNER_TDA18218 is not set +# CONFIG_MEDIA_TUNER_FC0011 is not set +# CONFIG_MEDIA_TUNER_FC0012 is not set +# CONFIG_MEDIA_TUNER_FC0013 is not set +# CONFIG_MEDIA_TUNER_TDA18212 is not set +# CONFIG_MEDIA_TUNER_E4000 is not set +# CONFIG_MEDIA_TUNER_FC2580 is not set +# CONFIG_MEDIA_TUNER_M88RS6000T is not set +# CONFIG_MEDIA_TUNER_TUA9001 is not set +# CONFIG_MEDIA_TUNER_SI2157 is not set +# CONFIG_MEDIA_TUNER_IT913X is not set +# CONFIG_MEDIA_TUNER_R820T is not set +# CONFIG_MEDIA_TUNER_MXL301RF is not set +# CONFIG_MEDIA_TUNER_QM1D1C0042 is not set +# CONFIG_MEDIA_TUNER_QM1D1B0004 is not set +# CONFIG_DVB_STB0899 is not set +# CONFIG_DVB_STB6100 is not set +# CONFIG_DVB_STV090x is not set +# CONFIG_DVB_STV0910 is not set +# CONFIG_DVB_STV6110x is not set +# CONFIG_DVB_STV6111 is not set +# CONFIG_DVB_MXL5XX is not set +# CONFIG_DVB_M88DS3103 is not set +# CONFIG_DVB_DRXK is not set +# CONFIG_DVB_TDA18271C2DD is not set +# CONFIG_DVB_SI2165 is not set +# CONFIG_DVB_MN88472 is not set +# CONFIG_DVB_MN88473 is not set +# CONFIG_DVB_CX24110 is not set +# CONFIG_DVB_CX24123 is not set +# CONFIG_DVB_MT312 is not set +# CONFIG_DVB_ZL10036 is not set +# CONFIG_DVB_ZL10039 is not set +# CONFIG_DVB_S5H1420 is not set +# CONFIG_DVB_STV0288 is not set +# CONFIG_DVB_STB6000 is not set +# CONFIG_DVB_STV0299 is not set +# CONFIG_DVB_STV6110 is not set +# CONFIG_DVB_STV0900 is not set +# CONFIG_DVB_TDA8083 is not set +# CONFIG_DVB_TDA10086 is not set +# CONFIG_DVB_TDA8261 is not set +# CONFIG_DVB_VES1X93 is not set +# CONFIG_DVB_TUNER_ITD1000 is not set +# CONFIG_DVB_TUNER_CX24113 is not set +# CONFIG_DVB_TDA826X is not set +# CONFIG_DVB_TUA6100 is not set +# CONFIG_DVB_CX24116 is not set +# CONFIG_DVB_CX24117 is not set +# CONFIG_DVB_CX24120 is not set +# CONFIG_DVB_SI21XX is not set +# CONFIG_DVB_TS2020 is not set +# CONFIG_DVB_DS3000 is not set +# CONFIG_DVB_MB86A16 is not set +# CONFIG_DVB_TDA10071 is not set +# CONFIG_DVB_SP8870 is not set +# CONFIG_DVB_SP887X is not set +# CONFIG_DVB_CX22700 is not set +# CONFIG_DVB_CX22702 is not set +# CONFIG_DVB_S5H1432 is not set +# CONFIG_DVB_DRXD is not set +# CONFIG_DVB_L64781 is not set +# CONFIG_DVB_TDA1004X is not set +# CONFIG_DVB_NXT6000 is not set +# CONFIG_DVB_MT352 is not set +# CONFIG_DVB_DIB7000M is not set +# CONFIG_DVB_DIB7000P is not set +# CONFIG_DVB_DIB9000 is not set +# CONFIG_DVB_TDA10048 is not set +# CONFIG_DVB_STV0367 is not set +# CONFIG_DVB_CXD2820R is not set +# CONFIG_DVB_CXD2841ER is not set +# CONFIG_DVB_RTL2832_SDR is not set +# CONFIG_DVB_SI2168 is not set +# CONFIG_DVB_ZD1301_DEMOD is not set +# CONFIG_DVB_CXD2880 is not set +# CONFIG_DVB_VES1820 is not set +# CONFIG_DVB_TDA10021 is not set +# CONFIG_DVB_TDA10023 is not set +# CONFIG_DVB_STV0297 is not set +# CONFIG_DVB_NXT200X is not set +# CONFIG_DVB_OR51211 is not set +# CONFIG_DVB_OR51132 is not set +# CONFIG_DVB_BCM3510 is not set +# CONFIG_DVB_LGDT330X is not set +# CONFIG_DVB_LGDT3305 is not set +# CONFIG_DVB_LGDT3306A is not set +# CONFIG_DVB_LG2160 is not set +# CONFIG_DVB_S5H1409 is not set +# CONFIG_DVB_AU8522_DTV is not set +# CONFIG_DVB_AU8522_V4L is not set +# CONFIG_DVB_S5H1411 is not set +# CONFIG_DVB_S921 is not set +# CONFIG_DVB_DIB8000 is not set +# CONFIG_DVB_MB86A20S is not set +# CONFIG_DVB_TC90522 is not set +# CONFIG_DVB_MN88443X is not set +# CONFIG_DVB_PLL is not set +# CONFIG_DVB_TUNER_DIB0070 is not set +# CONFIG_DVB_TUNER_DIB0090 is not set +# CONFIG_DVB_DRX39XYJ is not set +# CONFIG_DVB_LNBH25 is not set +# CONFIG_DVB_LNBH29 is not set +# CONFIG_DVB_LNBP21 is not set +# CONFIG_DVB_LNBP22 is not set +# CONFIG_DVB_ISL6405 is not set +# CONFIG_DVB_ISL6421 is not set +# CONFIG_DVB_ISL6423 is not set +# CONFIG_DVB_A8293 is not set +# CONFIG_DVB_LGS8GL5 is not set +# CONFIG_DVB_LGS8GXX is not set +# CONFIG_DVB_ATBM8830 is not set +# CONFIG_DVB_TDA665x is not set +# CONFIG_DVB_IX2505V is not set +# CONFIG_DVB_M88RS2000 is not set +# CONFIG_DVB_HORUS3A is not set +# CONFIG_DVB_ASCOT2E is not set +# CONFIG_DVB_HELENE is not set +# CONFIG_DVB_CXD2099 is not set +# CONFIG_DVB_SP2 is not set +CONFIG_FB=m +CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_ST7565P=m +CONFIG_SOUND=y +CONFIG_SND=y +# CONFIG_SND_ARM is not set +# CONFIG_SND_SPI is not set +CONFIG_SND_USB_AUDIO=m +CONFIG_HID_MULTITOUCH=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_OTG=y +CONFIG_USB_OTG_FSM=m +CONFIG_USB_LEDS_TRIGGER_USBPORT=m +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_MXC=y +CONFIG_USB_PRINTER=m +CONFIG_USB_STORAGE=y +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_SIMPLE=m +CONFIG_USB_SERIAL_AIRCABLE=m +CONFIG_USB_SERIAL_ARK3116=m +CONFIG_USB_SERIAL_BELKIN=m +CONFIG_USB_SERIAL_CH341=m +CONFIG_USB_SERIAL_WHITEHEAT=m +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m +CONFIG_USB_SERIAL_CP210X=m +CONFIG_USB_SERIAL_CYPRESS_M8=m +CONFIG_USB_SERIAL_EMPEG=m +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_VISOR=m +CONFIG_USB_SERIAL_IPAQ=m +CONFIG_USB_SERIAL_IR=m +CONFIG_USB_SERIAL_EDGEPORT=m +CONFIG_USB_SERIAL_EDGEPORT_TI=m +CONFIG_USB_SERIAL_F81232=m +CONFIG_USB_SERIAL_F8153X=m +CONFIG_USB_SERIAL_GARMIN=m +CONFIG_USB_SERIAL_IPW=m +CONFIG_USB_SERIAL_IUU=m +CONFIG_USB_SERIAL_KEYSPAN_PDA=m +CONFIG_USB_SERIAL_KEYSPAN=m +CONFIG_USB_SERIAL_KLSI=m +CONFIG_USB_SERIAL_KOBIL_SCT=m +CONFIG_USB_SERIAL_MCT_U232=m +CONFIG_USB_SERIAL_METRO=m +CONFIG_USB_SERIAL_MOS7720=m +CONFIG_USB_SERIAL_MOS7840=m +CONFIG_USB_SERIAL_MXUPORT=m +CONFIG_USB_SERIAL_NAVMAN=m +CONFIG_USB_SERIAL_PL2303=m +CONFIG_USB_SERIAL_OTI6858=m +CONFIG_USB_SERIAL_QCAUX=m +CONFIG_USB_SERIAL_QUALCOMM=m +CONFIG_USB_SERIAL_SPCP8X5=m +CONFIG_USB_SERIAL_SAFE=m +CONFIG_USB_SERIAL_SIERRAWIRELESS=m +CONFIG_USB_SERIAL_SYMBOL=m +CONFIG_USB_SERIAL_TI=m +CONFIG_USB_SERIAL_CYBERJACK=m +CONFIG_USB_SERIAL_XIRCOM=m +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_SERIAL_OMNINET=m +CONFIG_USB_SERIAL_OPTICON=m +CONFIG_USB_SERIAL_XSENS_MT=m +CONFIG_USB_SERIAL_WISHBONE=m +CONFIG_USB_SERIAL_SSU100=m +CONFIG_USB_SERIAL_QT2=m +CONFIG_USB_SERIAL_UPD78F0730=m +CONFIG_USB_SERIAL_DEBUG=m +CONFIG_USB_TEST=m +CONFIG_USB_EHSET_TEST_FIXTURE=m +CONFIG_NOP_USB_XCEIV=y +CONFIG_USB_MXS_PHY=y +CONFIG_USB_GADGET=y +CONFIG_USB_FSL_USB2=y +CONFIG_USB_CONFIGFS=y +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONFIGFS_ACM=y +CONFIG_USB_CONFIGFS_OBEX=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_ECM=y +CONFIG_USB_CONFIGFS_ECM_SUBSET=y +CONFIG_USB_CONFIGFS_RNDIS=y +CONFIG_USB_CONFIGFS_EEM=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_LB_SS=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_CONFIGFS_F_UAC1=y +CONFIG_USB_CONFIGFS_F_UAC2=y +CONFIG_USB_CONFIGFS_F_MIDI=y +CONFIG_USB_CONFIGFS_F_HID=y +CONFIG_USB_CONFIGFS_F_UVC=y +CONFIG_USB_CONFIGFS_F_PRINTER=y +CONFIG_USB_ZERO=m +CONFIG_USB_AUDIO=m +CONFIG_USB_ETH=m +CONFIG_USB_G_NCM=m +CONFIG_USB_GADGETFS=m +CONFIG_USB_FUNCTIONFS=m +CONFIG_USB_FUNCTIONFS_ETH=y +CONFIG_USB_FUNCTIONFS_RNDIS=y +CONFIG_USB_FUNCTIONFS_GENERIC=y +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m +CONFIG_USB_MIDI_GADGET=m +CONFIG_USB_G_PRINTER=m +CONFIG_USB_CDC_COMPOSITE=m +CONFIG_USB_G_ACM_MS=m +CONFIG_USB_G_MULTI=m +CONFIG_USB_G_HID=m +CONFIG_USB_G_DBGP=m +CONFIG_USB_G_WEBCAM=m +CONFIG_USB_RAW_GADGET=m +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_ESDHC_IMX=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_PWM=y +CONFIG_LEDS_USER=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_ONESHOT=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_ACTIVITY=m +CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_LEDS_TRIGGER_TRANSIENT=m +CONFIG_LEDS_TRIGGER_CAMERA=m +CONFIG_LEDS_TRIGGER_PANIC=y +CONFIG_LEDS_TRIGGER_NETDEV=m +CONFIG_LEDS_TRIGGER_PATTERN=m +CONFIG_LEDS_TRIGGER_AUDIO=m +CONFIG_RTC_CLASS=y +CONFIG_RTC_INTF_DEV_UIE_EMUL=y +CONFIG_RTC_DRV_DS1307=y +CONFIG_RTC_DRV_TSSUPERVISOR=y +CONFIG_RTC_DRV_MXC=y +CONFIG_RTC_DRV_SNVS=y +CONFIG_DMADEVICES=y +CONFIG_IMX_SDMA=y +# CONFIG_MX3_IPU is not set +CONFIG_DMATEST=m +CONFIG_SYNC_FILE=y +# CONFIG_VIRTIO_MENU is not set +# CONFIG_VHOST_MENU is not set +CONFIG_STAGING=y +CONFIG_STAGING_MEDIA=y +CONFIG_COMMON_CLK_PWM=y +CONFIG_IMX_GPCV2_PM_DOMAINS=y +CONFIG_IIO=y +CONFIG_IIO_BUFFER_CB=m +CONFIG_IIO_BUFFER_DMAENGINE=m +CONFIG_IIO_BUFFER_HW_CONSUMER=m +CONFIG_IIO_SW_DEVICE=m +CONFIG_IIO_SW_TRIGGER=m +CONFIG_IIO_TRIGGERED_EVENT=m +CONFIG_MMA8452=y +CONFIG_IMX7D_ADC=y +CONFIG_TS_SIMPLEADC=y +CONFIG_TS_SUPERVISOR_ADC=y +CONFIG_VF610_ADC=y +CONFIG_IIO_RESCALE=m +CONFIG_IIO_ST_LSM6DSX=m +CONFIG_SENSORS_ISL29018=y +CONFIG_MAG3110=y +CONFIG_IIO_ST_MAGN_3AXIS=m +CONFIG_IIO_MUX=m +CONFIG_IIO_INTERRUPT_TRIGGER=m +CONFIG_IIO_SYSFS_TRIGGER=m +CONFIG_MPL3115=y +CONFIG_TS_SUPERVISOR_TEMP=y +CONFIG_PWM=y +CONFIG_PWM_FSL_FTM=y +CONFIG_PWM_IMX27=y +CONFIG_PWM_IMX_TPM=y +CONFIG_PWM_TS=y +CONFIG_TSWEIM_FPGA_INTC=y +CONFIG_NVMEM_IMX_OCOTP=y +CONFIG_NVMEM_SNVS_LPGPR=y +CONFIG_TEE=y +CONFIG_OPTEE=y +CONFIG_MUX_MMIO=y +CONFIG_SIOX=m +CONFIG_SIOX_BUS_GPIO=m +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=y +CONFIG_OVERLAY_FS=m +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=y +CONFIG_EXFAT_FS=m +CONFIG_NTFS_FS=m +CONFIG_NTFS_RW=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y +CONFIG_ROOT_NFS=y +CONFIG_NLS_DEFAULT="cp437" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_UTF8=y +CONFIG_SECURITYFS=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_ZSTD=y +CONFIG_CRYPTO_DEV_FSL_CAAM=y +CONFIG_CRYPTO_DEV_SAHARA=y +CONFIG_CRYPTO_DEV_MXS_DCP=y +CONFIG_CRC_T10DIF=y +CONFIG_CRC7=m +CONFIG_LIBCRC32C=m +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=64 +CONFIG_PRINTK_TIME=y +# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_FS=y +# CONFIG_SCHED_DEBUG is not set +CONFIG_PROVE_LOCKING=y +# CONFIG_FTRACE is not set From ab8d80db744b6a6e3ea112e3a1a6efa62c83fcde Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Wed, 8 Mar 2023 16:15:53 -0700 Subject: [PATCH 048/244] arm: configs: Initial commit of minimal defconfig for embeddedTS i.MX6ul systems with bare minimum hardware support --- arch/arm/configs/tsimx6ul_minimal_defconfig | 345 ++++++++++++++++++++ 1 file changed, 345 insertions(+) create mode 100644 arch/arm/configs/tsimx6ul_minimal_defconfig diff --git a/arch/arm/configs/tsimx6ul_minimal_defconfig b/arch/arm/configs/tsimx6ul_minimal_defconfig new file mode 100644 index 0000000000000..874f2f9f2a0aa --- /dev/null +++ b/arch/arm/configs/tsimx6ul_minimal_defconfig @@ -0,0 +1,345 @@ +CONFIG_KERNEL_LZO=y +# CONFIG_SWAP is not set +# CONFIG_CROSS_MEMORY_ATTACH is not set +CONFIG_NO_HZ_IDLE=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_PREEMPT=y +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_CGROUPS=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +# CONFIG_KALLSYMS is not set +# CONFIG_RSEQ is not set +CONFIG_EMBEDDED=y +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_SLOB=y +# CONFIG_SLAB_MERGE_DEFAULT is not set +CONFIG_ARCH_MXC=y +CONFIG_SOC_IMX6UL=y +CONFIG_ARM_ERRATA_754322=y +CONFIG_ARM_ERRATA_775420=y +CONFIG_HAVE_ARM_ARCH_TIMER=y +CONFIG_ARM_PSCI=y +CONFIG_HIGHMEM=y +CONFIG_FORCE_MAX_ZONEORDER=14 +CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPUFREQ_DT=y +CONFIG_ARM_IMX6Q_CPUFREQ=y +CONFIG_CPU_IDLE=y +CONFIG_ARM_CPUIDLE=y +CONFIG_ARM_PSCI_CPUIDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +# CONFIG_SUSPEND is not set +CONFIG_PM=y +CONFIG_PM_DEBUG=y +# CONFIG_SECCOMP is not set +# CONFIG_STACKPROTECTOR is not set +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_MQ_IOSCHED_KYBER is not set +# CONFIG_COREDUMP is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IPV6 is not set +CONFIG_CAN=m +CONFIG_CAN_FLEXCAN=m +CONFIG_BT=m +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_LL=y +CONFIG_CFG80211=m +# CONFIG_CFG80211_DEFAULT_PS is not set +CONFIG_CFG80211_WEXT=y +CONFIG_MAC80211=m +CONFIG_RFKILL=m +CONFIG_RFKILL_INPUT=y +# CONFIG_ETHTOOL_NETLINK is not set +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +CONFIG_EXTRA_FIRMWARE="imx/sdma/sdma-imx6q.bin" +CONFIG_EXTRA_FIRMWARE_DIR="firmware" +CONFIG_FW_LOADER_USER_HELPER=y +CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y +# CONFIG_ALLOW_DEV_COREDUMP is not set +CONFIG_IMX_WEIM=y +CONFIG_TSPC104=y +CONFIG_CONNECTOR=y +CONFIG_MTD=m +# CONFIG_MTD_OF_PARTS is not set +CONFIG_MTD_BLOCK=m +CONFIG_MTD_CFI=m +CONFIG_MTD_JEDECPROBE=m +CONFIG_MTD_CFI_INTELEXT=m +CONFIG_MTD_CFI_AMDSTD=m +CONFIG_MTD_CFI_STAA=m +CONFIG_MTD_SST25L=m +CONFIG_MTD_SPI_NOR=m +CONFIG_BLK_DEV_LOOP=y +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_AT25=y +CONFIG_SCSI=y +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_NETDEVICES=y +# CONFIG_NET_VENDOR_ALACRITECH is not set +# CONFIG_NET_VENDOR_AMAZON is not set +# CONFIG_NET_VENDOR_AQUANTIA is not set +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_AURORA is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CADENCE is not set +# CONFIG_NET_VENDOR_CAVIUM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_CORTINA is not set +# CONFIG_NET_VENDOR_EZCHIP is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_GOOGLE is not set +# CONFIG_NET_VENDOR_HISILICON is not set +# CONFIG_NET_VENDOR_HUAWEI is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MELLANOX is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_MICROSEMI is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NETRONOME is not set +# CONFIG_NET_VENDOR_NI is not set +# CONFIG_NET_VENDOR_PENSANDO is not set +# CONFIG_NET_VENDOR_QUALCOMM is not set +# CONFIG_NET_VENDOR_RENESAS is not set +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SOLARFLARE is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_SOCIONEXT is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +# CONFIG_NET_VENDOR_XILINX is not set +CONFIG_MICREL_PHY=y +CONFIG_MICROCHIP_PHY=y +CONFIG_SMSC_PHY=y +CONFIG_USB_NET_DRIVERS=m +CONFIG_USB_USBNET=m +# CONFIG_USB_NET_AX8817X is not set +# CONFIG_USB_NET_AX88179_178A is not set +# CONFIG_USB_NET_CDCETHER is not set +# CONFIG_USB_NET_CDC_NCM is not set +CONFIG_USB_NET_SMSC95XX=m +# CONFIG_USB_NET_NET1080 is not set +# CONFIG_USB_NET_CDC_SUBSET is not set +# CONFIG_USB_NET_ZAURUS is not set +# CONFIG_WLAN_VENDOR_ADMTEK is not set +# CONFIG_WLAN_VENDOR_ATH is not set +# CONFIG_WLAN_VENDOR_ATMEL is not set +# CONFIG_WLAN_VENDOR_BROADCOM is not set +# CONFIG_WLAN_VENDOR_CISCO is not set +# CONFIG_WLAN_VENDOR_INTEL is not set +# CONFIG_WLAN_VENDOR_INTERSIL is not set +# CONFIG_WLAN_VENDOR_MARVELL is not set +# CONFIG_WLAN_VENDOR_MEDIATEK is not set +# CONFIG_WLAN_VENDOR_MICROCHIP is not set +# CONFIG_WLAN_VENDOR_RALINK is not set +# CONFIG_WLAN_VENDOR_REALTEK is not set +# CONFIG_WLAN_VENDOR_RSI is not set +# CONFIG_WLAN_VENDOR_ST is not set +CONFIG_WL12XX=m +CONFIG_WLCORE_SDIO=m +# CONFIG_WILINK_PLATFORM_DATA is not set +# CONFIG_WLAN_VENDOR_ZYDAS is not set +# CONFIG_WLAN_VENDOR_QUANTENNA is not set +# CONFIG_INPUT_LEDS is not set +CONFIG_INPUT_EVDEV=m +# CONFIG_KEYBOARD_ATKBD is not set +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_MATRIX=m +CONFIG_KEYBOARD_SNVS_PWRKEY=y +CONFIG_KEYBOARD_IMX=y +# CONFIG_MOUSE_PS2 is not set +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ADS7846=m +# CONFIG_SERIO is not set +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_8250=m +CONFIG_SERIAL_8250_NR_UARTS=24 +CONFIG_SERIAL_8250_RUNTIME_UARTS=24 +CONFIG_SERIAL_OF_PLATFORM=m +CONFIG_SERIAL_IMX=y +CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_SERIAL_FSL_LPUART=y +CONFIG_SERIAL_FSL_LPUART_CONSOLE=y +CONFIG_SERIAL_DEV_BUS=y +# CONFIG_RANDOM_TRUST_BOOTLOADER is not set +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX=y +# CONFIG_I2C_HELPER_AUTO is not set +CONFIG_I2C_ALGOPCF=m +CONFIG_I2C_ALGOPCA=m +CONFIG_I2C_GPIO=y +CONFIG_I2C_IMX=y +CONFIG_SPI=y +CONFIG_SPI_GPIO=y +CONFIG_SPI_IMX=y +# CONFIG_PTP_1588_CLOCK is not set +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_MXC=y +CONFIG_GPIO_TS4900=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_TS_SUPERVISOR=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_POWER_RESET_SYSCON_POWEROFF=y +# CONFIG_HWMON is not set +CONFIG_THERMAL_STATISTICS=y +CONFIG_THERMAL_WRITABLE_TRIPS=y +CONFIG_CPU_THERMAL=y +CONFIG_IMX_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_TS_WDT_MICRO=y +CONFIG_IMX2_WDT=y +CONFIG_MFD_TS_SUPERVISOR=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_ANATOP=y +CONFIG_REGULATOR_GPIO=y +CONFIG_IMX_IPUV3_CORE=y +CONFIG_DRM=y +CONFIG_DRM_PANEL_LVDS=y +CONFIG_DRM_PANEL_SIMPLE=y +CONFIG_DRM_PANEL_SEIKO_43WVF1G=y +CONFIG_DRM_TI_TFP410=y +CONFIG_DRM_DW_HDMI_CEC=y +CONFIG_DRM_IMX=y +CONFIG_DRM_IMX_PARALLEL_DISPLAY=y +CONFIG_DRM_IMX_TVE=y +CONFIG_DRM_IMX_LDB=y +CONFIG_DRM_IMX_HDMI=y +CONFIG_DRM_ETNAVIV=y +CONFIG_DRM_MXSFB=y +CONFIG_FB_MODE_HELPERS=y +CONFIG_LCD_CLASS_DEVICE=y +CONFIG_LCD_L4F00242T03=y +CONFIG_LCD_PLATFORM=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_BACKLIGHT_GPIO=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_USB_HID is not set +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_MXC=y +CONFIG_USB_STORAGE=y +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_NOP_USB_XCEIV=y +CONFIG_USB_MXS_PHY=y +CONFIG_USB_GADGET=y +CONFIG_USB_FSL_USB2=y +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_ESDHC_IMX=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_PWM=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_RTC_CLASS=y +# CONFIG_RTC_NVMEM is not set +CONFIG_RTC_INTF_DEV_UIE_EMUL=y +CONFIG_RTC_DRV_DS1307=y +CONFIG_RTC_DRV_TSSUPERVISOR=y +CONFIG_DMADEVICES=y +CONFIG_IMX_SDMA=y +# CONFIG_VIRTIO_MENU is not set +# CONFIG_VHOST_MENU is not set +CONFIG_COMMON_CLK_PWM=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_IMX_GPCV2_PM_DOMAINS=y +CONFIG_IIO=y +CONFIG_MMA8452=y +CONFIG_TS_SIMPLEADC=y +CONFIG_TS_SUPERVISOR_ADC=y +CONFIG_VF610_ADC=y +CONFIG_IIO_RESCALE=m +CONFIG_IIO_ST_LSM6DSX=m +CONFIG_SENSORS_ISL29018=y +CONFIG_MAG3110=y +CONFIG_IIO_ST_MAGN_3AXIS=m +CONFIG_MPL3115=y +CONFIG_TS_SUPERVISOR_TEMP=m +CONFIG_PWM=y +CONFIG_PWM_IMX27=y +CONFIG_TSWEIM_FPGA_INTC=y +CONFIG_NVMEM_IMX_OCOTP=y +CONFIG_NVMEM_SNVS_LPGPR=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +CONFIG_AUTOFS4_FS=m +CONFIG_FUSE_FS=m +CONFIG_VFAT_FS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_CONFIGFS_FS=y +CONFIG_NFS_FS=y +CONFIG_ROOT_NFS=y +CONFIG_NLS_DEFAULT="cp437" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_UTF8=y +CONFIG_CRYPTO_ECDH=y +CONFIG_CRYPTO_CCM=y +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_CMAC=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_DEV_FSL_CAAM=y +CONFIG_CRYPTO_DEV_SAHARA=y +CONFIG_CRYPTO_DEV_MXS_DCP=y +CONFIG_CRC_CCITT=m +CONFIG_CRC_T10DIF=y +CONFIG_CRC_ITU_T=m +CONFIG_CRC7=m +CONFIG_LIBCRC32C=m +CONFIG_XZ_DEC=y +CONFIG_CMA_SIZE_MBYTES=64 +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +# CONFIG_SYMBOLIC_ERRNAME is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_ENABLE_MUST_CHECK is not set +# CONFIG_DEBUG_MISC is not set +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_PREEMPT is not set +# CONFIG_RCU_TRACE is not set +# CONFIG_FTRACE is not set +# CONFIG_RUNTIME_TESTING_MENU is not set From 8a0b560c20da1dd1289702a90b96c1ae2deb9011 Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Wed, 22 Mar 2023 09:39:44 -0700 Subject: [PATCH 049/244] gpio: ts71xxweim: Fix static gpio label This uses the device name instead of our own static label so we can safely use the device name instead of a dynamic chip id to address different banks. Eg: gpioset 5004010.fpga_gpio 0=1 --- drivers/gpio/gpio-ts71xxweim.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpio/gpio-ts71xxweim.c b/drivers/gpio/gpio-ts71xxweim.c index 72827a418d93b..6cdfd02eabef4 100644 --- a/drivers/gpio/gpio-ts71xxweim.c +++ b/drivers/gpio/gpio-ts71xxweim.c @@ -89,7 +89,6 @@ static void tsweim_gpio_set(struct gpio_chip *chip, unsigned int offset, } static const struct gpio_chip template_chip = { - .label = "tsweim-gpio", .owner = THIS_MODULE, .direction_input = tsweim_gpio_direction_input, .direction_output = tsweim_gpio_direction_output, @@ -148,7 +147,7 @@ static int tsweim_gpio_probe(struct platform_device *pdev) (unsigned int)priv->syscon, resource_size(res)); priv->gpio_chip = template_chip; - priv->gpio_chip.label = "tsweim-gpio"; + priv->gpio_chip.label = dev_name(dev); priv->gpio_chip.ngpio = ngpio; priv->gpio_chip.base = base; pdev->dev.platform_data = &priv; From 04d0fe1d4d1b30b04120f3de3775e603c3b1930f Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Wed, 22 Mar 2023 09:51:13 -0700 Subject: [PATCH 050/244] gpio: ts71xxweim: Remove unused code No new uses of this driver set a base, this was only to help with the transition to gpiochips when users were still using sysfs GPIO numbers on past controllers. "ngpios" does not need to be lowered from 16 since the controller usage will always reserve 16-bits. --- drivers/gpio/gpio-ts71xxweim.c | 20 +------------------- 1 file changed, 1 insertion(+), 19 deletions(-) diff --git a/drivers/gpio/gpio-ts71xxweim.c b/drivers/gpio/gpio-ts71xxweim.c index 6cdfd02eabef4..6f11d6013c77a 100644 --- a/drivers/gpio/gpio-ts71xxweim.c +++ b/drivers/gpio/gpio-ts71xxweim.c @@ -107,23 +107,10 @@ MODULE_DEVICE_TABLE(of, tsweim_gpio_of_match_table); static int tsweim_gpio_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; - const struct of_device_id *match; struct tsweim_gpio_priv *priv; - u32 ngpio; - int base; void __iomem *membase; struct resource *res; - match = of_match_device(tsweim_gpio_of_match_table, dev); - if (!match) - return -EINVAL; - - if (of_property_read_u32(dev->of_node, "ngpios", &ngpio)) - ngpio = TSWEIM_NR_DIO; - - if (of_property_read_u32(dev->of_node, "base", &base)) - base = -1; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (res == NULL) { pr_err("Can't get device address\n"); @@ -143,15 +130,10 @@ static int tsweim_gpio_probe(struct platform_device *pdev) priv->syscon = membase; - pr_info("FPGA syscon mapped to 0x%08X, %d bytes\n", - (unsigned int)priv->syscon, resource_size(res)); - priv->gpio_chip = template_chip; priv->gpio_chip.label = dev_name(dev); - priv->gpio_chip.ngpio = ngpio; - priv->gpio_chip.base = base; + priv->gpio_chip.ngpio = TSWEIM_NR_DIO; pdev->dev.platform_data = &priv; - priv->gpio_chip.of_node = pdev->dev.of_node; return devm_gpiochip_add_data(&pdev->dev, &priv->gpio_chip, &priv); } From 90b2f3d66b22a628e181803e1d87c44bb26982ca Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Tue, 21 Mar 2023 11:24:54 -0700 Subject: [PATCH 051/244] mfd: tssupervisor-core: Add serial support Added support for a "serial" sysfs entry that can be written once in the product's lifetime --- drivers/mfd/tssupervisor-core.c | 90 ++++++++++++++++++++++++++++++- include/linux/mfd/ts_supervisor.h | 8 +++ 2 files changed, 97 insertions(+), 1 deletion(-) diff --git a/drivers/mfd/tssupervisor-core.c b/drivers/mfd/tssupervisor-core.c index 7f02362763bce..423375dd88dbc 100644 --- a/drivers/mfd/tssupervisor-core.c +++ b/drivers/mfd/tssupervisor-core.c @@ -33,12 +33,14 @@ static const struct regmap_range ts_supervisor_read_regs[] = { regmap_reg_range(16, 16), /* flags */ regmap_reg_range(24, 24), /* inputs */ regmap_reg_range(32, 32), /* reboot_reason */ + regmap_reg_range(34, 37), /* serial */ regmap_reg_range(128, 160), /* ADCs+temp */ }; static const struct regmap_range ts_supervisor_write_regs[] = { regmap_reg_range(8, 8), /* cmds */ regmap_reg_range(16, 16), /* flags */ + regmap_reg_range(34, 37), /* serial */ }; const struct regmap_access_table ts_supervisor_read_register_set = { @@ -119,6 +121,74 @@ static ssize_t wake_en_show(struct device *dev, } static DEVICE_ATTR_RW(wake_en); +static ssize_t serial_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + struct ts_supervisor *super = dev_get_drvdata(dev); + unsigned int ctrl = 0; + u8 sn[6], verify[6]; + int ret; + + ret = regmap_read(super->regmap, SUPER_SERIAL_CTRL, &ctrl); + if (ret) + return ret; + + /* Dont write the SN if its already written */ + if (ctrl & SUPER_SN_LOCKED) + return -EEXIST; + + if (count < 17) + return -EIO; + + if (sscanf(buf, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx", + &sn[0], &sn[1], &sn[2], &sn[3], &sn[4], &sn[5]) != 6) + return -EINVAL; + + ret = regmap_bulk_write(super->regmap, SUPER_SERIAL0, sn, 3); + if (ret) + return ret; + + /* Verify data before commiting OTP SN */ + ret = regmap_bulk_read(super->regmap, SUPER_SERIAL0, verify, 3); + if (ret) + return ret; + + if (memcmp(verify, sn, 6) != 0) + return -EIO; + + ret = regmap_update_bits(super->regmap, SUPER_SERIAL_CTRL, + SUPER_SN_LOCKED, + SUPER_SN_LOCKED); + + return ret ? ret : count; +} + +static ssize_t serial_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct ts_supervisor *super = dev_get_drvdata(dev); + unsigned int ctrl; + u8 sn[6]; + int ret; + + ret = regmap_read(super->regmap, SUPER_SERIAL_CTRL, &ctrl); + if (ret) + return ret; + + /* Dont show the serial number if its not written yet */ + if (!(ctrl & SUPER_SN_LOCKED)) + return -EINVAL; + + ret = regmap_bulk_read(super->regmap, SUPER_SERIAL0, sn, 3); + if (ret) + return ret; + ret = sprintf(buf, "%02x:%02x:%02x:%02x:%02x:%02x\n", + sn[0], sn[1], sn[2], sn[3], sn[4], sn[5]); + + return ret; +} +static DEVICE_ATTR_RW(serial); + static ssize_t console_cfg_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { @@ -170,12 +240,21 @@ static struct attribute_group ts7250v3_attr_group = { .attrs = ts7250v3_sysfs_entries, }; +static struct attribute *serial_sysfs_entries[] = { + &dev_attr_serial.attr, + NULL, +}; + +static struct attribute_group serial_attr_group = { + .attrs = serial_sysfs_entries, +}; + static int ts_supervisor_i2c_probe(struct i2c_client *client) { struct ts_supervisor *super; struct device *dev = &client->dev; int err = 0, i; - uint32_t model, revision; + uint32_t model, revision, features; super = devm_kzalloc(dev, sizeof(struct ts_supervisor), GFP_KERNEL); @@ -198,6 +277,9 @@ static int ts_supervisor_i2c_probe(struct i2c_client *client) err = regmap_read(super->regmap, SUPER_REV_INFO, &revision); if (err < 0) dev_err(dev, "error reading reg %u", SUPER_REV_INFO); + err = regmap_read(super->regmap, SUPER_FEATURES0, &features); + if (err < 0) + dev_err(dev, "error reading reg %u", SUPER_FEATURES0); dev_info(&client->dev, "Model %04X rev %d%s\n", model, revision & 0x7fff, @@ -209,6 +291,12 @@ static int ts_supervisor_i2c_probe(struct i2c_client *client) dev_warn(dev, "error creating sysfs entries\n"); } + if (features & SUPER_FEAT_SN) { + err = sysfs_create_group(&dev->kobj, &serial_attr_group); + if (err) + dev_warn(dev, "error creating sysfs entries\n"); + } + /* Set up and register the platform devices. */ for (i = 0; i < ARRAY_SIZE(tssupervisor_devs); i++) { tssupervisor_devs[i].platform_data = super; diff --git a/include/linux/mfd/ts_supervisor.h b/include/linux/mfd/ts_supervisor.h index 0f01d0d03857c..d29feaa3bc47e 100644 --- a/include/linux/mfd/ts_supervisor.h +++ b/include/linux/mfd/ts_supervisor.h @@ -19,6 +19,10 @@ struct ts_supervisor { #define SUPER_FLAGS 16 #define SUPER_INPUTS 24 #define SUPER_REBOOT_REASON 32 +#define SUPER_SERIAL0 34 +#define SUPER_SERIAL1 35 +#define SUPER_SERIAL2 36 +#define SUPER_SERIAL_CTRL 37 #define SUPER_ADC_BASE 128 #define SUPER_ADC_LAST 159 #define SUPER_TEMPERATURE 160 @@ -57,4 +61,8 @@ enum super_cmds_t { I2C_HALT = (1 << 1), }; +enum super_serial_ctrl_t { + SUPER_SN_LOCKED = (1 << 0), +}; + #endif \ No newline at end of file From 77cd47e5f8acb3a1b6c74bde5edc5eb32a7e407f Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Thu, 9 Mar 2023 13:57:57 -0700 Subject: [PATCH 052/244] ARM: configs: tsimx6: Initial commit Config files targetting embeddedTS i.MX6 based platforms. Includes a minimal config as well as a full config intended to support many other device drivers that could be connected to these platforms. Signed-off-by: Mark Featherston Signed-off-by: Kris Bahnsen --- arch/arm/configs/tsimx6_defconfig | 1092 +++++++++++++++++++++ arch/arm/configs/tsimx6_minimal_defconfig | 380 +++++++ 2 files changed, 1472 insertions(+) create mode 100644 arch/arm/configs/tsimx6_defconfig create mode 100644 arch/arm/configs/tsimx6_minimal_defconfig diff --git a/arch/arm/configs/tsimx6_defconfig b/arch/arm/configs/tsimx6_defconfig new file mode 100644 index 0000000000000..1d4b80d14d2f8 --- /dev/null +++ b/arch/arm/configs/tsimx6_defconfig @@ -0,0 +1,1092 @@ +CONFIG_KERNEL_LZO=y +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_PREEMPT=y +CONFIG_IRQ_TIME_ACCOUNTING=y +CONFIG_PSI=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_CGROUPS=y +CONFIG_MEMCG=y +CONFIG_BLK_CGROUP=y +CONFIG_CGROUP_SCHED=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_RDMA=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CPUSETS=y +# CONFIG_PROC_PID_CPUSET is not set +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_PERF=y +CONFIG_CGROUP_BPF=y +CONFIG_CGROUP_DEBUG=y +CONFIG_NAMESPACES=y +CONFIG_USER_NS=y +CONFIG_CHECKPOINT_RESTORE=y +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +# CONFIG_RD_ZSTD is not set +CONFIG_EXPERT=y +CONFIG_KALLSYMS_ALL=y +CONFIG_BPF_SYSCALL=y +# CONFIG_SLUB_DEBUG is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_PROFILING=y +CONFIG_ARCH_MXC=y +CONFIG_SOC_IMX6Q=y +CONFIG_ARM_ERRATA_814220=y +CONFIG_SMP=y +CONFIG_HAVE_ARM_ARCH_TIMER=y +CONFIG_ARM_PSCI=y +CONFIG_HIGHMEM=y +CONFIG_FORCE_MAX_ZONEORDER=14 +CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" +CONFIG_KEXEC=y +CONFIG_EFI=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPUFREQ_DT=y +CONFIG_ARM_IMX6Q_CPUFREQ=y +CONFIG_ARM_IMX_CPUFREQ_DT=y +CONFIG_CPU_IDLE=y +CONFIG_ARM_CPUIDLE=y +CONFIG_ARM_PSCI_CPUIDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_PM_DEBUG=y +CONFIG_PM_TEST_SUSPEND=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_BINFMT_MISC=m +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_PACKET_DIAG=m +CONFIG_UNIX=y +CONFIG_UNIX_DIAG=m +CONFIG_TLS=m +CONFIG_TLS_DEVICE=y +CONFIG_TLS_TOE=y +CONFIG_XFRM_USER=m +CONFIG_XFRM_INTERFACE=m +CONFIG_XFRM_SUB_POLICY=y +CONFIG_XFRM_STATISTICS=y +CONFIG_NET_KEY=m +CONFIG_NET_KEY_MIGRATE=y +CONFIG_XDP_SOCKETS=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE_DEMUX=m +CONFIG_NET_IPGRE=m +CONFIG_NET_IPGRE_BROADCAST=y +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_NET_IPVTI=m +CONFIG_NET_FOU=y +CONFIG_NET_FOU_IP_TUNNELS=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_ESP_OFFLOAD=m +CONFIG_INET_ESPINTCP=y +CONFIG_INET_IPCOMP=m +CONFIG_INET_UDP_DIAG=m +CONFIG_INET_RAW_DIAG=m +CONFIG_INET_DIAG_DESTROY=y +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_TCP_CONG_HSTCP=m +CONFIG_TCP_CONG_HYBLA=m +CONFIG_TCP_CONG_NV=m +CONFIG_TCP_CONG_SCALABLE=m +CONFIG_TCP_CONG_LP=m +CONFIG_TCP_CONG_VENO=m +CONFIG_TCP_CONG_YEAH=m +CONFIG_TCP_CONG_ILLINOIS=m +CONFIG_TCP_CONG_DCTCP=m +CONFIG_TCP_CONG_CDG=m +CONFIG_TCP_CONG_BBR=m +CONFIG_TCP_MD5SIG=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_ESP_OFFLOAD=m +CONFIG_INET6_ESPINTCP=y +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_MIP6=m +CONFIG_IPV6_ILA=m +CONFIG_IPV6_VTI=m +CONFIG_IPV6_SIT=m +CONFIG_IPV6_SIT_6RD=y +CONFIG_IPV6_GRE=m +CONFIG_IPV6_SUBTREES=y +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y +CONFIG_IPV6_PIMSM_V2=y +CONFIG_IPV6_SEG6_LWTUNNEL=y +CONFIG_IPV6_SEG6_HMAC=y +CONFIG_IPV6_RPL_LWTUNNEL=y +CONFIG_MPTCP=y +CONFIG_NETWORK_SECMARK=y +CONFIG_NETWORK_PHY_TIMESTAMPING=y +CONFIG_NETFILTER=y +CONFIG_BRIDGE_NETFILTER=m +CONFIG_NF_CONNTRACK=m +CONFIG_NF_LOG_NETDEV=m +CONFIG_NF_CONNTRACK_ZONES=y +CONFIG_NF_CONNTRACK_PROCFS=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_TIMEOUT=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y +CONFIG_NF_CONNTRACK_AMANDA=m +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_SNMP=m +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_CT_NETLINK=m +CONFIG_NF_CT_NETLINK_TIMEOUT=m +CONFIG_NF_CT_NETLINK_HELPER=m +CONFIG_NETFILTER_NETLINK_GLUE_CT=y +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_INET=y +CONFIG_NF_TABLES_NETDEV=y +CONFIG_NFT_NUMGEN=m +CONFIG_NFT_CT=m +CONFIG_NFT_FLOW_OFFLOAD=m +CONFIG_NFT_COUNTER=m +CONFIG_NFT_CONNLIMIT=m +CONFIG_NFT_LOG=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_REDIR=m +CONFIG_NFT_NAT=m +CONFIG_NFT_TUNNEL=m +CONFIG_NFT_OBJREF=m +CONFIG_NFT_QUEUE=m +CONFIG_NFT_QUOTA=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_HASH=m +CONFIG_NFT_FIB_INET=m +CONFIG_NFT_XFRM=m +CONFIG_NFT_SOCKET=m +CONFIG_NFT_OSF=m +CONFIG_NFT_TPROXY=m +CONFIG_NFT_SYNPROXY=m +CONFIG_NFT_DUP_NETDEV=m +CONFIG_NFT_FWD_NETDEV=m +CONFIG_NF_FLOW_TABLE_INET=m +CONFIG_NF_FLOW_TABLE=m +CONFIG_NETFILTER_XT_SET=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LED=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_TEE=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFILTER_XT_TARGET_SECMARK=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m +CONFIG_NETFILTER_XT_MATCH_CGROUP=m +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_CPU=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_IPCOMP=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_IPVS=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +CONFIG_IP_SET=m +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPMARK=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_IPMAC=m +CONFIG_IP_SET_HASH_MAC=m +CONFIG_IP_SET_HASH_NETPORTNET=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETNET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m +CONFIG_IP_VS=m +CONFIG_IP_VS_IPV6=y +CONFIG_IP_VS_DEBUG=y +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_AH=y +CONFIG_IP_VS_PROTO_SCTP=y +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_WRR=m +CONFIG_IP_VS_LC=m +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_FO=m +CONFIG_IP_VS_OVF=m +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_MH=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_NQ=m +CONFIG_IP_VS_FTP=m +CONFIG_IP_VS_PE_SIP=m +CONFIG_NFT_DUP_IPV4=m +CONFIG_NFT_FIB_IPV4=m +CONFIG_NF_TABLES_ARP=y +CONFIG_NF_FLOW_TABLE_IPV4=m +CONFIG_NF_LOG_ARP=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_SYNPROXY=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NFT_FIB_IPV6=m +CONFIG_NF_FLOW_TABLE_IPV6=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RPFILTER=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_MATCH_SRH=m +CONFIG_IP6_NF_TARGET_HL=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_TARGET_SYNPROXY=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_RAW=m +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_IP6_NF_TARGET_NPT=m +CONFIG_DECNET_NF_GRABULATOR=m +CONFIG_NF_TABLES_BRIDGE=m +CONFIG_NFT_BRIDGE_META=m +CONFIG_NFT_BRIDGE_REJECT=m +CONFIG_NF_LOG_BRIDGE=m +CONFIG_NF_CONNTRACK_BRIDGE=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_IP6=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_NFLOG=m +CONFIG_BPFILTER=y +CONFIG_IP_DCCP=m +CONFIG_IP_SCTP=m +CONFIG_RDS=m +CONFIG_RDS_TCP=m +CONFIG_TIPC=m +CONFIG_ATM=m +CONFIG_ATM_CLIP=m +CONFIG_ATM_LANE=m +CONFIG_ATM_BR2684=m +CONFIG_L2TP=m +CONFIG_L2TP_V3=y +CONFIG_L2TP_IP=m +CONFIG_L2TP_ETH=m +CONFIG_BRIDGE=m +CONFIG_BRIDGE_VLAN_FILTERING=y +CONFIG_BRIDGE_MRP=y +CONFIG_NET_DSA=m +CONFIG_VLAN_8021Q=m +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_VLAN_8021Q_MVRP=y +CONFIG_DECNET=m +CONFIG_LLC2=m +CONFIG_ATALK=m +CONFIG_X25=m +CONFIG_LAPB=m +CONFIG_PHONET=m +CONFIG_6LOWPAN=m +CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m +CONFIG_6LOWPAN_GHC_UDP=m +CONFIG_6LOWPAN_GHC_ICMPV6=m +CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m +CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m +CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m +CONFIG_IEEE802154=m +CONFIG_IEEE802154_6LOWPAN=m +CONFIG_MAC802154=m +CONFIG_NET_SCHED=y +CONFIG_DCB=y +CONFIG_DNS_RESOLVER=y +CONFIG_BATMAN_ADV=m +CONFIG_BATMAN_ADV_NC=y +CONFIG_OPENVSWITCH=m +CONFIG_VSOCKETS=m +CONFIG_NETLINK_DIAG=m +CONFIG_MPLS_ROUTING=m +CONFIG_MPLS_IPTUNNEL=m +CONFIG_HSR=m +CONFIG_QRTR=m +CONFIG_QRTR_TUN=m +CONFIG_NET_NCSI=y +CONFIG_NCSI_OEM_CMD_GET_MAC=y +CONFIG_CGROUP_NET_PRIO=y +CONFIG_BPF_JIT=y +CONFIG_CAN=m +CONFIG_CAN_J1939=m +CONFIG_CAN_ISOTP=m +CONFIG_CAN_VCAN=m +CONFIG_CAN_VXCAN=m +CONFIG_CAN_SLCAN=m +CONFIG_CAN_FLEXCAN=m +CONFIG_CAN_8DEV_USB=m +CONFIG_CAN_EMS_USB=m +CONFIG_CAN_ESD_USB2=m +CONFIG_CAN_GS_USB=m +CONFIG_CAN_KVASER_USB=m +CONFIG_CAN_MCBA_USB=m +CONFIG_CAN_PEAK_USB=m +CONFIG_CAN_UCAN=m +CONFIG_BT=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HS=y +CONFIG_BT_LEDS=y +CONFIG_BT_MSFTEXT=y +CONFIG_BT_HCIBTUSB=m +CONFIG_BT_HCIBTUSB_MTK=y +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_NOKIA=m +CONFIG_BT_HCIUART_BCSP=y +CONFIG_BT_HCIUART_ATH3K=y +CONFIG_BT_HCIUART_LL=y +CONFIG_CFG80211=m +# CONFIG_CFG80211_DEFAULT_PS is not set +CONFIG_MAC80211=m +CONFIG_RFKILL=m +CONFIG_RFKILL_INPUT=y +CONFIG_NFC=m +CONFIG_NFC_DIGITAL=m +CONFIG_NFC_NCI=m +CONFIG_NFC_NCI_SPI=m +CONFIG_NFC_NCI_UART=m +CONFIG_NFC_HCI=m +CONFIG_NFC_PN533_USB=m +CONFIG_NFC_NXP_NCI=m +CONFIG_NFC_ST95HF=m +CONFIG_PCI=y +CONFIG_PCI_MSI=y +CONFIG_PCI_IMX6=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +CONFIG_EXTRA_FIRMWARE="imx/sdma/sdma-imx6q.bin" +CONFIG_EXTRA_FIRMWARE_DIR="firmware" +CONFIG_IMX_WEIM=y +CONFIG_CONNECTOR=y +CONFIG_MTD=m +CONFIG_MTD_CMDLINE_PARTS=m +CONFIG_MTD_BLOCK=m +CONFIG_MTD_CFI=m +CONFIG_MTD_JEDECPROBE=m +CONFIG_MTD_CFI_INTELEXT=m +CONFIG_MTD_CFI_AMDSTD=m +CONFIG_MTD_CFI_STAA=m +CONFIG_MTD_DATAFLASH=m +CONFIG_MTD_SST25L=m +CONFIG_MTD_RAW_NAND=m +CONFIG_MTD_NAND_MXC=m +CONFIG_MTD_SPI_NOR=m +CONFIG_MTD_UBI=m +CONFIG_MTD_UBI_FASTMAP=y +CONFIG_MTD_UBI_BLOCK=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=65536 +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_AT25=y +CONFIG_MISC_RTSX_USB=m +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_ATA=y +CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_AHCI_IMX=y +CONFIG_PATA_IMX=y +CONFIG_MD=y +CONFIG_BLK_DEV_DM=m +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_NETDEVICES=y +CONFIG_DUMMY=m +CONFIG_WIREGUARD=m +CONFIG_MACVLAN=m +CONFIG_MACVTAP=m +CONFIG_IPVLAN=m +CONFIG_IPVTAP=m +CONFIG_VXLAN=m +CONFIG_VETH=m +# CONFIG_NET_VENDOR_BROADCOM is not set +CONFIG_CS89x0=y +CONFIG_CS89x0_PLATFORM=y +# CONFIG_NET_VENDOR_FARADAY is not set +CONFIG_IGB=m +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set +CONFIG_SMC91X=y +CONFIG_SMC911X=y +CONFIG_SMSC911X=y +# CONFIG_NET_VENDOR_STMICRO is not set +CONFIG_MICREL_PHY=y +CONFIG_MICROCHIP_PHY=y +CONFIG_AT803X_PHY=y +CONFIG_SMSC_PHY=y +CONFIG_PPP=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPPOATM=m +CONFIG_PPPOE=m +CONFIG_PPTP=m +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_USB_CATC=m +CONFIG_USB_KAWETH=m +CONFIG_USB_PEGASUS=m +CONFIG_USB_RTL8150=m +CONFIG_USB_RTL8152=m +CONFIG_USB_LAN78XX=m +CONFIG_USB_NET_CDC_EEM=m +CONFIG_USB_NET_HUAWEI_CDC_NCM=m +CONFIG_USB_NET_CDC_MBIM=m +CONFIG_USB_NET_DM9601=m +CONFIG_USB_NET_SR9700=m +CONFIG_USB_NET_SR9800=m +CONFIG_USB_NET_SMSC75XX=m +CONFIG_USB_NET_SMSC95XX=m +CONFIG_USB_NET_GL620A=m +CONFIG_USB_NET_PLUSB=m +CONFIG_USB_NET_MCS7830=m +CONFIG_USB_NET_CX82310_ETH=m +CONFIG_USB_NET_KALMIA=m +CONFIG_USB_NET_QMI_WWAN=m +CONFIG_USB_HSO=m +CONFIG_USB_NET_INT51X1=m +CONFIG_USB_IPHETH=m +CONFIG_USB_SIERRA_NET=m +CONFIG_USB_VL600=m +CONFIG_USB_NET_CH9200=m +CONFIG_USB_NET_AQC111=m +CONFIG_ATH5K_PCI=y +CONFIG_ATH9K=m +CONFIG_ATH10K=m +CONFIG_ATH10K_SDIO=m +CONFIG_AT76C50X_USB=m +CONFIG_BRCMFMAC=m +# CONFIG_BRCMFMAC_SDIO is not set +CONFIG_BRCMFMAC_USB=y +CONFIG_IPW2100=m +CONFIG_IPW2100_MONITOR=y +CONFIG_IPW2200=m +CONFIG_IPW2200_MONITOR=y +CONFIG_IPW2200_PROMISCUOUS=y +CONFIG_IWL4965=m +CONFIG_IWL3945=m +CONFIG_IWLWIFI=m +CONFIG_IWLDVM=m +CONFIG_IWLMVM=m +# CONFIG_WLAN_VENDOR_INTERSIL is not set +CONFIG_MWIFIEX=m +CONFIG_MWIFIEX_SDIO=m +CONFIG_MWIFIEX_PCIE=m +CONFIG_MWIFIEX_USB=m +CONFIG_MWL8K=m +CONFIG_MT7601U=m +CONFIG_MT76x0U=m +CONFIG_MT76x0E=m +CONFIG_MT76x2E=m +CONFIG_MT76x2U=m +CONFIG_MT7603E=m +CONFIG_MT7615E=m +CONFIG_MT7663U=m +CONFIG_MT7663S=m +CONFIG_MT7915E=m +# CONFIG_WLAN_VENDOR_MICROCHIP is not set +CONFIG_RT2X00=m +CONFIG_RT2500USB=m +CONFIG_RT73USB=m +CONFIG_RT2800USB=m +CONFIG_RT2800USB_RT3573=y +CONFIG_RT2800USB_RT53XX=y +CONFIG_RT2800USB_RT55XX=y +CONFIG_RT2800USB_UNKNOWN=y +CONFIG_RTL8180=m +CONFIG_RTL8187=m +CONFIG_RTL8XXXU=m +CONFIG_RTL8XXXU_UNTESTED=y +CONFIG_RTW88=m +CONFIG_RTW88_8822BE=m +CONFIG_RTW88_8822CE=m +CONFIG_RTW88_8723DE=m +CONFIG_RTW88_8821CE=m +CONFIG_RSI_91X=m +# CONFIG_RSI_SDIO is not set +# CONFIG_WLAN_VENDOR_ST is not set +CONFIG_WL12XX=m +CONFIG_WLCORE_SDIO=m +# CONFIG_WILINK_PLATFORM_DATA is not set +CONFIG_ZD1211RW=m +CONFIG_QTNFMAC_PCIE=m +CONFIG_USB_NET_RNDIS_WLAN=m +CONFIG_VIRT_WIFI=m +CONFIG_INPUT_MOUSEDEV=m +CONFIG_INPUT_JOYDEV=m +CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_SNVS_PWRKEY=y +CONFIG_KEYBOARD_IMX=y +CONFIG_MOUSE_PS2=m +CONFIG_MOUSE_PS2_ELANTECH=y +CONFIG_INPUT_JOYSTICK=y +CONFIG_JOYSTICK_ANALOG=m +CONFIG_JOYSTICK_A3D=m +CONFIG_JOYSTICK_ADC=m +CONFIG_JOYSTICK_ADI=m +CONFIG_JOYSTICK_COBRA=m +CONFIG_JOYSTICK_GF2K=m +CONFIG_JOYSTICK_GRIP=m +CONFIG_JOYSTICK_GRIP_MP=m +CONFIG_JOYSTICK_GUILLEMOT=m +CONFIG_JOYSTICK_INTERACT=m +CONFIG_JOYSTICK_SIDEWINDER=m +CONFIG_JOYSTICK_TMDC=m +CONFIG_JOYSTICK_IFORCE=m +CONFIG_JOYSTICK_WARRIOR=m +CONFIG_JOYSTICK_MAGELLAN=m +CONFIG_JOYSTICK_SPACEORB=m +CONFIG_JOYSTICK_SPACEBALL=m +CONFIG_JOYSTICK_STINGER=m +CONFIG_JOYSTICK_TWIDJOY=m +CONFIG_JOYSTICK_ZHENHUA=m +CONFIG_JOYSTICK_AS5011=m +CONFIG_JOYSTICK_JOYDUMP=m +CONFIG_JOYSTICK_XPAD=m +CONFIG_JOYSTICK_PSXPAD_SPI=m +CONFIG_JOYSTICK_PXRC=m +CONFIG_JOYSTICK_FSIA6B=m +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ADS7846=y +CONFIG_TOUCHSCREEN_AD7879=y +CONFIG_TOUCHSCREEN_AD7879_I2C=y +CONFIG_TOUCHSCREEN_IMX6UL_TSC=m +CONFIG_TOUCHSCREEN_PIXCIR=y +CONFIG_TOUCHSCREEN_TSC2004=y +CONFIG_INPUT_MISC=y +CONFIG_INPUT_MMA8450=y +CONFIG_SERIO_SERPORT=m +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_IMX=y +CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_SERIAL_FSL_LPUART=y +CONFIG_SERIAL_FSL_LPUART_CONSOLE=y +CONFIG_SERIAL_DEV_BUS=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_GPIO=y +# CONFIG_I2C_HELPER_AUTO is not set +CONFIG_I2C_ALGOPCF=m +CONFIG_I2C_ALGOPCA=m +CONFIG_I2C_GPIO=y +CONFIG_I2C_IMX=y +CONFIG_SPI=y +CONFIG_SPI_FSL_QUADSPI=y +CONFIG_SPI_GPIO=y +CONFIG_SPI_IMX=y +CONFIG_SPI_SPIDEV=m +CONFIG_PINCTRL_IMX8MM=y +CONFIG_PINCTRL_IMX8MN=y +CONFIG_PINCTRL_IMX8MP=y +CONFIG_PINCTRL_IMX8MQ=y +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_MXC=y +CONFIG_GPIO_MAX732X=y +CONFIG_GPIO_PCA953X=y +CONFIG_GPIO_PCF857X=y +CONFIG_GPIO_TS4900=y +CONFIG_GPIO_74X164=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_POWER_RESET_SYSCON_POWEROFF=y +CONFIG_POWER_SUPPLY=y +CONFIG_SENSORS_GPIO_FAN=y +CONFIG_SENSORS_IIO_HWMON=m +CONFIG_THERMAL_STATISTICS=y +CONFIG_THERMAL_WRITABLE_TRIPS=y +CONFIG_CPU_THERMAL=y +CONFIG_IMX_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_IMX2_WDT=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_USERSPACE_CONSUMER=m +CONFIG_REGULATOR_ANATOP=y +CONFIG_REGULATOR_GPIO=y +CONFIG_RC_CORE=m +CONFIG_RC_DEVICES=y +CONFIG_IR_GPIO_CIR=m +CONFIG_MEDIA_SUPPORT=m +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_VIDEO_CLASS=m +CONFIG_USB_M5602=m +CONFIG_USB_STV06XX=m +CONFIG_USB_GL860=m +CONFIG_USB_GSPCA_BENQ=m +CONFIG_USB_GSPCA_CONEX=m +CONFIG_USB_GSPCA_CPIA1=m +CONFIG_USB_GSPCA_DTCS033=m +CONFIG_USB_GSPCA_ETOMS=m +CONFIG_USB_GSPCA_FINEPIX=m +CONFIG_USB_GSPCA_JEILINJ=m +CONFIG_USB_GSPCA_JL2005BCD=m +CONFIG_USB_GSPCA_KINECT=m +CONFIG_USB_GSPCA_KONICA=m +CONFIG_USB_GSPCA_MARS=m +CONFIG_USB_GSPCA_MR97310A=m +CONFIG_USB_GSPCA_NW80X=m +CONFIG_USB_GSPCA_OV519=m +CONFIG_USB_GSPCA_OV534=m +CONFIG_USB_GSPCA_OV534_9=m +CONFIG_USB_GSPCA_PAC207=m +CONFIG_USB_GSPCA_PAC7302=m +CONFIG_USB_GSPCA_PAC7311=m +CONFIG_USB_GSPCA_SE401=m +CONFIG_USB_GSPCA_SN9C2028=m +CONFIG_USB_GSPCA_SN9C20X=m +CONFIG_USB_GSPCA_SONIXB=m +CONFIG_USB_GSPCA_SONIXJ=m +CONFIG_USB_GSPCA_SPCA500=m +CONFIG_USB_GSPCA_SPCA501=m +CONFIG_USB_GSPCA_SPCA505=m +CONFIG_USB_GSPCA_SPCA506=m +CONFIG_USB_GSPCA_SPCA508=m +CONFIG_USB_GSPCA_SPCA561=m +CONFIG_USB_GSPCA_SPCA1528=m +CONFIG_USB_GSPCA_SQ905=m +CONFIG_USB_GSPCA_SQ905C=m +CONFIG_USB_GSPCA_SQ930X=m +CONFIG_USB_GSPCA_STK014=m +CONFIG_USB_GSPCA_STK1135=m +CONFIG_USB_GSPCA_STV0680=m +CONFIG_USB_GSPCA_SUNPLUS=m +CONFIG_USB_GSPCA_T613=m +CONFIG_USB_GSPCA_TOPRO=m +CONFIG_USB_GSPCA_TOUPTEK=m +CONFIG_USB_GSPCA_TV8532=m +CONFIG_USB_GSPCA_VC032X=m +CONFIG_USB_GSPCA_VICAM=m +CONFIG_USB_GSPCA_XIRLINK_CIT=m +CONFIG_USB_GSPCA_ZC3XX=m +CONFIG_USB_PWC=m +CONFIG_VIDEO_CPIA2=m +CONFIG_USB_ZR364XX=m +CONFIG_USB_STKWEBCAM=m +CONFIG_USB_S2255=m +CONFIG_VIDEO_USBTV=m +CONFIG_VIDEO_PVRUSB2=m +CONFIG_VIDEO_HDPVR=m +CONFIG_VIDEO_STK1160_COMMON=m +CONFIG_VIDEO_GO7007=m +CONFIG_VIDEO_AU0828=m +CONFIG_VIDEO_CX231XX=m +CONFIG_VIDEO_TM6000=m +CONFIG_VIDEO_TM6000_ALSA=m +CONFIG_VIDEO_TM6000_DVB=m +CONFIG_DVB_USB=m +CONFIG_DVB_USB_A800=m +CONFIG_DVB_USB_DIBUSB_MB=m +CONFIG_DVB_USB_DIBUSB_MC=m +CONFIG_DVB_USB_DIB0700=m +CONFIG_DVB_USB_UMT_010=m +CONFIG_DVB_USB_CXUSB=m +CONFIG_DVB_USB_M920X=m +CONFIG_DVB_USB_DIGITV=m +CONFIG_DVB_USB_VP7045=m +CONFIG_DVB_USB_VP702X=m +CONFIG_DVB_USB_GP8PSK=m +CONFIG_DVB_USB_NOVA_T_USB2=m +CONFIG_DVB_USB_TTUSB2=m +CONFIG_DVB_USB_DTT200U=m +CONFIG_DVB_USB_OPERA1=m +CONFIG_DVB_USB_AF9005=m +CONFIG_DVB_USB_AF9005_REMOTE=m +CONFIG_DVB_USB_PCTV452E=m +CONFIG_DVB_USB_DW2102=m +CONFIG_DVB_USB_CINERGY_T2=m +CONFIG_DVB_USB_DTV5100=m +CONFIG_DVB_USB_AZ6027=m +CONFIG_DVB_USB_TECHNISAT_USB2=m +CONFIG_DVB_USB_V2=m +CONFIG_DVB_USB_AF9015=m +CONFIG_DVB_USB_AF9035=m +CONFIG_DVB_USB_ANYSEE=m +CONFIG_DVB_USB_AU6610=m +CONFIG_DVB_USB_AZ6007=m +CONFIG_DVB_USB_CE6230=m +CONFIG_DVB_USB_EC168=m +CONFIG_DVB_USB_GL861=m +CONFIG_DVB_USB_LME2510=m +CONFIG_DVB_USB_MXL111SF=m +CONFIG_DVB_USB_RTL28XXU=m +CONFIG_DVB_USB_DVBSKY=m +CONFIG_DVB_USB_ZD1301=m +CONFIG_DVB_TTUSB_BUDGET=m +CONFIG_DVB_TTUSB_DEC=m +CONFIG_SMS_USB_DRV=m +CONFIG_DVB_B2C2_FLEXCOP_USB=m +CONFIG_DVB_AS102=m +CONFIG_VIDEO_EM28XX=m +CONFIG_VIDEO_EM28XX_V4L2=m +CONFIG_VIDEO_EM28XX_ALSA=m +CONFIG_VIDEO_EM28XX_DVB=m +CONFIG_USB_AIRSPY=m +CONFIG_USB_HACKRF=m +CONFIG_USB_MSI2500=m +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_VIDEO_MUX=m +CONFIG_V4L_MEM2MEM_DRIVERS=y +CONFIG_VIDEO_CODA=m +CONFIG_VIDEO_IMX_PXP=m +CONFIG_VIDEO_ADV7180=m +CONFIG_VIDEO_OV2680=m +CONFIG_VIDEO_OV5640=m +CONFIG_VIDEO_OV5645=m +CONFIG_IMX_IPUV3_CORE=y +CONFIG_DRM=y +CONFIG_DRM_PANEL_LVDS=y +CONFIG_DRM_PANEL_SIMPLE=y +CONFIG_DRM_TI_TFP410=y +CONFIG_DRM_DW_HDMI_AHB_AUDIO=m +CONFIG_DRM_DW_HDMI_CEC=y +CONFIG_DRM_IMX=y +CONFIG_DRM_IMX_PARALLEL_DISPLAY=y +CONFIG_DRM_IMX_LDB=y +CONFIG_DRM_IMX_HDMI=y +CONFIG_DRM_ETNAVIV=y +CONFIG_DRM_MXSFB=y +CONFIG_FB_MODE_HELPERS=y +CONFIG_LCD_CLASS_DEVICE=y +CONFIG_LCD_PLATFORM=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_BACKLIGHT_GPIO=m +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_LOGO=y +CONFIG_SOUND=m +CONFIG_SND=m +# CONFIG_SND_PCI is not set +CONFIG_SND_USB_AUDIO=m +CONFIG_SND_SOC=m +CONFIG_SND_SOC_FSL_ASRC=m +CONFIG_SND_IMX_SOC=m +CONFIG_SND_SOC_EUKREA_TLV320=m +CONFIG_SND_SOC_IMX_ES8328=m +CONFIG_SND_SOC_IMX_SGTL5000=m +CONFIG_SND_SOC_IMX_SPDIF=m +CONFIG_SND_SOC_FSL_ASOC_CARD=m +CONFIG_SND_SOC_AC97_CODEC=m +CONFIG_SND_SOC_CS42XX8_I2C=m +CONFIG_SND_SOC_TLV320AIC3X=m +CONFIG_SND_SOC_WM8960=m +CONFIG_SND_SOC_WM8962=m +CONFIG_SND_SIMPLE_CARD=m +CONFIG_HID_MULTITOUCH=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_MXC=y +CONFIG_USB_STORAGE=y +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_TEST=m +CONFIG_USB_EHSET_TEST_FIXTURE=m +CONFIG_NOP_USB_XCEIV=y +CONFIG_USB_MXS_PHY=y +CONFIG_USB_GADGET=y +CONFIG_USB_FSL_USB2=y +CONFIG_USB_CONFIGFS=y +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONFIGFS_ACM=y +CONFIG_USB_CONFIGFS_OBEX=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_ECM=y +CONFIG_USB_CONFIGFS_ECM_SUBSET=y +CONFIG_USB_CONFIGFS_RNDIS=y +CONFIG_USB_CONFIGFS_EEM=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_LB_SS=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_CONFIGFS_F_UAC1=y +CONFIG_USB_CONFIGFS_F_UAC2=y +CONFIG_USB_CONFIGFS_F_MIDI=y +CONFIG_USB_CONFIGFS_F_HID=y +CONFIG_USB_CONFIGFS_F_UVC=y +CONFIG_USB_CONFIGFS_F_PRINTER=y +CONFIG_USB_ZERO=m +CONFIG_USB_AUDIO=m +CONFIG_USB_ETH=m +CONFIG_USB_G_NCM=m +CONFIG_USB_GADGETFS=m +CONFIG_USB_FUNCTIONFS=m +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_ESDHC_IMX=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_PWM=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_ONESHOT=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_INTF_DEV_UIE_EMUL=y +CONFIG_RTC_DRV_DS1307=y +CONFIG_RTC_DRV_ISL12022=y +CONFIG_RTC_DRV_PCF8563=y +CONFIG_RTC_DRV_M41T80=y +CONFIG_DMADEVICES=y +CONFIG_IMX_SDMA=y +# CONFIG_MX3_IPU is not set +CONFIG_DMATEST=m +CONFIG_UIO=m +CONFIG_UIO_PDRV_GENIRQ=m +CONFIG_UIO_DMEM_GENIRQ=m +CONFIG_UIO_PCI_GENERIC=m +CONFIG_STAGING=y +CONFIG_COMMON_CLK_PWM=y +CONFIG_CLK_IMX8MM=y +CONFIG_CLK_IMX8MN=y +CONFIG_CLK_IMX8MP=y +CONFIG_CLK_IMX8MQ=y +CONFIG_IMX_GPCV2_PM_DOMAINS=y +CONFIG_SOC_IMX8M=y +CONFIG_PM_DEVFREQ=y +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=m +CONFIG_DEVFREQ_GOV_PERFORMANCE=m +CONFIG_DEVFREQ_GOV_POWERSAVE=m +CONFIG_DEVFREQ_GOV_PASSIVE=m +CONFIG_ARM_IMX_BUS_DEVFREQ=m +CONFIG_PM_DEVFREQ_EVENT=y +CONFIG_IIO=m +CONFIG_IIO_BUFFER_DMAENGINE=m +CONFIG_IIO_BUFFER_HW_CONSUMER=m +CONFIG_IIO_SW_DEVICE=m +CONFIG_IIO_SW_TRIGGER=m +CONFIG_IIO_TRIGGERED_EVENT=m +CONFIG_IIO_ST_ACCEL_3AXIS=m +CONFIG_MMA8452=m +CONFIG_IMX7D_ADC=m +CONFIG_MCP320X=m +CONFIG_VF610_ADC=m +CONFIG_IIO_RESCALE=m +CONFIG_IIO_ST_LSM6DSX=m +CONFIG_SENSORS_ISL29018=m +CONFIG_MAG3110=m +CONFIG_IIO_ST_MAGN_3AXIS=m +CONFIG_MPL3115=m +CONFIG_PWM=y +CONFIG_PWM_FSL_FTM=y +CONFIG_PWM_IMX27=y +CONFIG_PWM_IMX_TPM=y +CONFIG_NVMEM_IMX_OCOTP=y +CONFIG_NVMEM_SNVS_LPGPR=y +CONFIG_MUX_GPIO=m +CONFIG_MUX_MMIO=m +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_JFS_FS=m +CONFIG_XFS_FS=m +CONFIG_BTRFS_FS=m +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +CONFIG_AUTOFS4_FS=m +CONFIG_FUSE_FS=m +CONFIG_CUSE=m +CONFIG_VIRTIO_FS=m +CONFIG_OVERLAY_FS=m +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=y +CONFIG_EXFAT_FS=m +CONFIG_NTFS_FS=m +CONFIG_NTFS_RW=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_CRAMFS=m +CONFIG_SQUASHFS=m +CONFIG_SQUASHFS_LZ4=y +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_XZ=y +CONFIG_ROMFS_FS=m +CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y +CONFIG_ROOT_NFS=y +CONFIG_CIFS=m +CONFIG_NLS_DEFAULT="cp437" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_UTF8=y +CONFIG_SECURITYFS=y +CONFIG_CRYPTO_ECDH=y +CONFIG_CRYPTO_CCM=y +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CMAC=y +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_LZO=m +CONFIG_CRYPTO_DEV_FSL_CAAM=y +CONFIG_CRC_T10DIF=y +CONFIG_CRC7=m +CONFIG_CMA_SIZE_MBYTES=64 +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_PRINTK_TIME=y +# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_FS=y +# CONFIG_DEBUG_MISC is not set +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_PREEMPT is not set +CONFIG_STACKTRACE=y +# CONFIG_FTRACE is not set +# CONFIG_RUNTIME_TESTING_MENU is not set diff --git a/arch/arm/configs/tsimx6_minimal_defconfig b/arch/arm/configs/tsimx6_minimal_defconfig new file mode 100644 index 0000000000000..805dfcd59ebd3 --- /dev/null +++ b/arch/arm/configs/tsimx6_minimal_defconfig @@ -0,0 +1,380 @@ +CONFIG_KERNEL_LZO=y +# CONFIG_SWAP is not set +# CONFIG_CROSS_MEMORY_ATTACH is not set +CONFIG_NO_HZ_IDLE=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_PREEMPT=y +# CONFIG_CPU_ISOLATION is not set +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_CGROUPS=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +# CONFIG_KALLSYMS is not set +# CONFIG_RSEQ is not set +CONFIG_EMBEDDED=y +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_SLOB=y +# CONFIG_SLAB_MERGE_DEFAULT is not set +CONFIG_ARCH_MULTI_V6=y +CONFIG_ARCH_MXC=y +CONFIG_SOC_IMX6Q=y +CONFIG_ARM_ERRATA_814220=y +CONFIG_SMP=y +CONFIG_HAVE_ARM_ARCH_TIMER=y +CONFIG_HOTPLUG_CPU=y +CONFIG_ARM_PSCI=y +CONFIG_FORCE_MAX_ZONEORDER=14 +CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPUFREQ_DT=y +CONFIG_ARM_IMX6Q_CPUFREQ=y +CONFIG_CPU_IDLE=y +CONFIG_ARM_CPUIDLE=y +CONFIG_ARM_PSCI_CPUIDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +# CONFIG_SUSPEND is not set +CONFIG_PM=y +CONFIG_PM_DEBUG=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_MQ_IOSCHED_KYBER is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IPV6 is not set +CONFIG_CAN=m +CONFIG_CAN_FLEXCAN=m +CONFIG_BT=m +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_LL=y +CONFIG_CFG80211=m +# CONFIG_CFG80211_DEFAULT_PS is not set +CONFIG_CFG80211_WEXT=y +CONFIG_MAC80211=m +CONFIG_RFKILL=m +CONFIG_RFKILL_INPUT=y +# CONFIG_ETHTOOL_NETLINK is not set +CONFIG_PCI=y +CONFIG_PCI_MSI=y +CONFIG_PCI_IMX6=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +CONFIG_EXTRA_FIRMWARE="imx/sdma/sdma-imx6q.bin" +CONFIG_EXTRA_FIRMWARE_DIR="firmware" +CONFIG_FW_LOADER_USER_HELPER=y +CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y +CONFIG_CONNECTOR=y +CONFIG_MTD=m +# CONFIG_MTD_OF_PARTS is not set +CONFIG_MTD_BLOCK=m +CONFIG_MTD_CFI=m +CONFIG_MTD_JEDECPROBE=m +CONFIG_MTD_CFI_INTELEXT=m +CONFIG_MTD_CFI_AMDSTD=m +CONFIG_MTD_CFI_STAA=m +CONFIG_MTD_SST25L=m +CONFIG_MTD_SPI_NOR=m +CONFIG_BLK_DEV_LOOP=y +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_AT25=y +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_ATA=y +CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_AHCI_IMX=y +CONFIG_PATA_IMX=y +CONFIG_NETDEVICES=y +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_ADAPTEC is not set +# CONFIG_NET_VENDOR_AGERE is not set +# CONFIG_NET_VENDOR_ALACRITECH is not set +# CONFIG_NET_VENDOR_ALTEON is not set +# CONFIG_NET_VENDOR_AMAZON is not set +# CONFIG_NET_VENDOR_AMD is not set +# CONFIG_NET_VENDOR_AQUANTIA is not set +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_ATHEROS is not set +# CONFIG_NET_VENDOR_AURORA is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_BROCADE is not set +# CONFIG_NET_VENDOR_CADENCE is not set +# CONFIG_NET_VENDOR_CAVIUM is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_CISCO is not set +# CONFIG_NET_VENDOR_CORTINA is not set +# CONFIG_NET_VENDOR_DEC is not set +# CONFIG_NET_VENDOR_DLINK is not set +# CONFIG_NET_VENDOR_EMULEX is not set +# CONFIG_NET_VENDOR_EZCHIP is not set +# CONFIG_NET_VENDOR_FARADAY is not set +CONFIG_IGB=m +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MELLANOX is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_MICROSEMI is not set +# CONFIG_NET_VENDOR_MYRI is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NETERION is not set +# CONFIG_NET_VENDOR_NETRONOME is not set +# CONFIG_NET_VENDOR_NI is not set +# CONFIG_NET_VENDOR_NVIDIA is not set +# CONFIG_NET_VENDOR_OKI is not set +# CONFIG_NET_VENDOR_PACKET_ENGINES is not set +# CONFIG_NET_VENDOR_PENSANDO is not set +# CONFIG_NET_VENDOR_QLOGIC is not set +# CONFIG_NET_VENDOR_QUALCOMM is not set +# CONFIG_NET_VENDOR_RDC is not set +# CONFIG_NET_VENDOR_REALTEK is not set +# CONFIG_NET_VENDOR_RENESAS is not set +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SOLARFLARE is not set +# CONFIG_NET_VENDOR_SILAN is not set +# CONFIG_NET_VENDOR_SIS is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_SOCIONEXT is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SUN is not set +# CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_TEHUTI is not set +# CONFIG_NET_VENDOR_TI is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +# CONFIG_NET_VENDOR_XILINX is not set +CONFIG_MICREL_PHY=y +CONFIG_MICROCHIP_PHY=y +CONFIG_SMSC_PHY=y +CONFIG_USB_USBNET=m +# CONFIG_USB_NET_AX8817X is not set +# CONFIG_USB_NET_AX88179_178A is not set +# CONFIG_USB_NET_CDCETHER is not set +# CONFIG_USB_NET_CDC_NCM is not set +CONFIG_USB_NET_SMSC95XX=m +# CONFIG_USB_NET_NET1080 is not set +# CONFIG_USB_NET_CDC_SUBSET is not set +# CONFIG_USB_NET_ZAURUS is not set +# CONFIG_WLAN_VENDOR_ADMTEK is not set +CONFIG_ATH10K=m +CONFIG_ATH10K_SDIO=m +# CONFIG_WLAN_VENDOR_ATMEL is not set +# CONFIG_WLAN_VENDOR_BROADCOM is not set +# CONFIG_WLAN_VENDOR_CISCO is not set +# CONFIG_WLAN_VENDOR_INTEL is not set +# CONFIG_WLAN_VENDOR_INTERSIL is not set +# CONFIG_WLAN_VENDOR_MARVELL is not set +# CONFIG_WLAN_VENDOR_MEDIATEK is not set +# CONFIG_WLAN_VENDOR_MICROCHIP is not set +# CONFIG_WLAN_VENDOR_RALINK is not set +# CONFIG_WLAN_VENDOR_REALTEK is not set +# CONFIG_WLAN_VENDOR_RSI is not set +# CONFIG_WLAN_VENDOR_ST is not set +CONFIG_WL12XX=m +CONFIG_WLCORE_SDIO=m +# CONFIG_WILINK_PLATFORM_DATA is not set +# CONFIG_WLAN_VENDOR_ZYDAS is not set +# CONFIG_WLAN_VENDOR_QUANTENNA is not set +# CONFIG_INPUT_LEDS is not set +CONFIG_INPUT_MOUSEDEV=m +CONFIG_INPUT_EVDEV=y +# CONFIG_KEYBOARD_ATKBD is not set +CONFIG_KEYBOARD_GPIO=y +# CONFIG_MOUSE_PS2 is not set +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ADS7846=y +CONFIG_TOUCHSCREEN_PIXCIR=y +# CONFIG_SERIO is not set +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_MAX3100_TS=y +CONFIG_SERIAL_IMX=y +CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_SERIAL_FSL_LPUART=y +CONFIG_SERIAL_FSL_LPUART_CONSOLE=y +CONFIG_SERIAL_DEV_BUS=y +# CONFIG_RANDOM_TRUST_BOOTLOADER is not set +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_GPIO=y +# CONFIG_I2C_HELPER_AUTO is not set +CONFIG_I2C_ALGOPCF=m +CONFIG_I2C_ALGOPCA=m +CONFIG_I2C_GPIO=y +CONFIG_I2C_IMX=y +CONFIG_SPI=y +CONFIG_SPI_GPIO=y +CONFIG_SPI_IMX=y +CONFIG_SPI_SPIDEV=m +# CONFIG_PTP_1588_CLOCK is not set +CONFIG_PINCTRL_IMX8MM=y +CONFIG_PINCTRL_IMX8MN=y +CONFIG_PINCTRL_IMX8MP=y +CONFIG_PINCTRL_IMX8MQ=y +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_MXC=y +CONFIG_GPIO_TS4900=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_POWER_RESET_SYSCON_POWEROFF=y +# CONFIG_HWMON is not set +CONFIG_THERMAL_STATISTICS=y +CONFIG_THERMAL_WRITABLE_TRIPS=y +CONFIG_CPU_THERMAL=y +CONFIG_IMX_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_IMX2_WDT=y +CONFIG_MFD_DA9052_I2C=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_ANATOP=y +CONFIG_REGULATOR_GPIO=y +CONFIG_IMX_IPUV3_CORE=y +CONFIG_DRM=y +CONFIG_DRM_PANEL_LVDS=y +CONFIG_DRM_PANEL_SIMPLE=y +CONFIG_DRM_PANEL_SEIKO_43WVF1G=y +CONFIG_DRM_TI_TFP410=y +CONFIG_DRM_DW_HDMI_AHB_AUDIO=m +CONFIG_DRM_DW_HDMI_CEC=y +CONFIG_DRM_IMX=y +CONFIG_DRM_IMX_PARALLEL_DISPLAY=y +CONFIG_DRM_IMX_TVE=y +CONFIG_DRM_IMX_LDB=y +CONFIG_DRM_IMX_HDMI=y +CONFIG_DRM_ETNAVIV=y +CONFIG_DRM_MXSFB=y +CONFIG_FB_MODE_HELPERS=y +CONFIG_LCD_CLASS_DEVICE=y +CONFIG_LCD_L4F00242T03=y +CONFIG_LCD_PLATFORM=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_BACKLIGHT_GPIO=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_SOUND=m +CONFIG_SND=m +# CONFIG_SND_PCI is not set +# CONFIG_SND_SPI is not set +# CONFIG_SND_USB is not set +CONFIG_SND_SOC=m +CONFIG_SND_SOC_FSL_ASRC=m +CONFIG_SND_IMX_SOC=m +CONFIG_SND_SOC_EUKREA_TLV320=m +CONFIG_SND_SOC_IMX_ES8328=m +CONFIG_SND_SOC_IMX_SGTL5000=m +CONFIG_SND_SOC_IMX_SPDIF=m +CONFIG_SND_SOC_FSL_ASOC_CARD=m +CONFIG_SND_SIMPLE_CARD=m +CONFIG_HID_MULTITOUCH=m +CONFIG_USB=y +# CONFIG_USB_PCI is not set +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_MXC=y +CONFIG_USB_STORAGE=y +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_NOP_USB_XCEIV=y +CONFIG_USB_MXS_PHY=y +CONFIG_USB_GADGET=y +CONFIG_USB_FSL_USB2=y +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_ESDHC_IMX=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_PWM=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_INTF_DEV_UIE_EMUL=y +CONFIG_RTC_DRV_DS1307=y +CONFIG_RTC_DRV_ISL12022=y +CONFIG_DMADEVICES=y +CONFIG_IMX_SDMA=y +# CONFIG_VIRTIO_MENU is not set +# CONFIG_VHOST_MENU is not set +CONFIG_COMMON_CLK_PWM=y +CONFIG_CLK_IMX8MM=y +CONFIG_CLK_IMX8MN=y +CONFIG_CLK_IMX8MP=y +CONFIG_CLK_IMX8MQ=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_IMX_GPCV2_PM_DOMAINS=y +CONFIG_IIO=y +CONFIG_MMA8452=y +CONFIG_SENSORS_ISL29018=y +CONFIG_MAG3110=y +CONFIG_MPL3115=y +CONFIG_PWM=y +CONFIG_PWM_IMX27=y +CONFIG_NVMEM_IMX_OCOTP=y +CONFIG_NVMEM_SNVS_LPGPR=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +CONFIG_AUTOFS4_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_CONFIGFS_FS=y +# CONFIG_MISC_FILESYSTEMS is not set +CONFIG_NFS_FS=y +CONFIG_ROOT_NFS=y +CONFIG_NLS_DEFAULT="cp437" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_UTF8=y +CONFIG_CRYPTO_ECDH=y +CONFIG_CRYPTO_CCM=y +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_CMAC=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_DEV_FSL_CAAM=y +CONFIG_CRYPTO_DEV_SAHARA=y +CONFIG_CRYPTO_DEV_MXS_DCP=y +CONFIG_CRC_CCITT=m +CONFIG_CRC_T10DIF=y +CONFIG_CRC_ITU_T=m +CONFIG_CRC7=m +CONFIG_LIBCRC32C=m +CONFIG_XZ_DEC=y +CONFIG_CMA_SIZE_MBYTES=64 +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +# CONFIG_SYMBOLIC_ERRNAME is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_ENABLE_MUST_CHECK is not set +# CONFIG_DEBUG_MISC is not set +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_PREEMPT is not set +# CONFIG_RCU_TRACE is not set +# CONFIG_FTRACE is not set +# CONFIG_RUNTIME_TESTING_MENU is not set From 04cf47dd50ed18ab6cd7d75e16fed4e5059305e4 Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Thu, 9 Mar 2023 16:54:56 -0700 Subject: [PATCH 053/244] ARM: configs: tsimx28: Split in to two defconfigs Config files targetting embeddedTS i.MX28 based platforms. Includes a minimal config as well as a full config intended to support many other device drivers that could be connected to these platforms. Standardizes the defconfig names to match other configs. Signed-off-by: Mark Featherston Signed-off-by: Kris Bahnsen --- arch/arm/configs/tsimx28_defconfig | 708 ++++++++++++++++++ ...28_defconfig => tsimx28_minimal_defconfig} | 114 ++- 2 files changed, 757 insertions(+), 65 deletions(-) create mode 100644 arch/arm/configs/tsimx28_defconfig rename arch/arm/configs/{ts_imx28_defconfig => tsimx28_minimal_defconfig} (78%) diff --git a/arch/arm/configs/tsimx28_defconfig b/arch/arm/configs/tsimx28_defconfig new file mode 100644 index 0000000000000..4cff9f55b08bc --- /dev/null +++ b/arch/arm/configs/tsimx28_defconfig @@ -0,0 +1,708 @@ +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_PREEMPT=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_PSI=y +CONFIG_IKCONFIG=m +CONFIG_IKCONFIG_PROC=y +CONFIG_CGROUPS=y +CONFIG_MEMCG=y +CONFIG_BLK_CGROUP=y +CONFIG_CGROUP_SCHED=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_RDMA=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_PERF=y +CONFIG_CGROUP_BPF=y +CONFIG_USER_NS=y +CONFIG_CHECKPOINT_RESTORE=y +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +# CONFIG_RD_ZSTD is not set +CONFIG_BPF_SYSCALL=y +CONFIG_PERF_EVENTS=y +# CONFIG_COMPAT_BRK is not set +# CONFIG_ARCH_MULTI_V7 is not set +CONFIG_ARCH_MXS=y +CONFIG_AEABI=y +CONFIG_EFI=y +CONFIG_MODULES=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_UNUSED_SYMBOLS=y +CONFIG_BLK_DEV_INTEGRITY=y +CONFIG_CLEANCACHE=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_PACKET_DIAG=m +CONFIG_UNIX=y +CONFIG_UNIX_DIAG=m +CONFIG_TLS=m +CONFIG_XFRM_USER=m +CONFIG_XFRM_INTERFACE=m +CONFIG_XFRM_SUB_POLICY=y +CONFIG_XFRM_STATISTICS=y +CONFIG_NET_KEY=m +CONFIG_NET_KEY_MIGRATE=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_FIB_TRIE_STATS=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE_DEMUX=m +CONFIG_NET_IPGRE=m +CONFIG_NET_IPGRE_BROADCAST=y +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_NET_IPVTI=m +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_DIAG=m +CONFIG_INET_UDP_DIAG=m +CONFIG_INET_RAW_DIAG=m +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_ESP_OFFLOAD=m +CONFIG_INET6_ESPINTCP=y +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_MIP6=m +CONFIG_IPV6_ILA=m +CONFIG_IPV6_VTI=m +CONFIG_IPV6_SIT=m +CONFIG_IPV6_SIT_6RD=y +CONFIG_IPV6_GRE=m +CONFIG_IPV6_SUBTREES=y +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y +CONFIG_IPV6_PIMSM_V2=y +CONFIG_IPV6_SEG6_LWTUNNEL=y +CONFIG_IPV6_SEG6_HMAC=y +CONFIG_IPV6_RPL_LWTUNNEL=y +CONFIG_MPTCP=y +CONFIG_NETWORK_PHY_TIMESTAMPING=y +CONFIG_NETFILTER=y +CONFIG_BRIDGE_NETFILTER=m +CONFIG_NF_CONNTRACK=m +CONFIG_NF_LOG_NETDEV=m +CONFIG_NF_CONNTRACK_AMANDA=m +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_SNMP=m +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_CT_NETLINK=m +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_INET=y +CONFIG_NF_TABLES_NETDEV=y +CONFIG_NFT_NUMGEN=m +CONFIG_NFT_CT=m +CONFIG_NFT_FLOW_OFFLOAD=m +CONFIG_NFT_COUNTER=m +CONFIG_NFT_CONNLIMIT=m +CONFIG_NFT_LOG=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_REDIR=m +CONFIG_NFT_NAT=m +CONFIG_NFT_TUNNEL=m +CONFIG_NFT_OBJREF=m +CONFIG_NFT_QUEUE=m +CONFIG_NFT_QUOTA=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_HASH=m +CONFIG_NFT_XFRM=m +CONFIG_NFT_SOCKET=m +CONFIG_NFT_OSF=m +CONFIG_NFT_TPROXY=m +CONFIG_NFT_SYNPROXY=m +CONFIG_NFT_DUP_NETDEV=m +CONFIG_NFT_FWD_NETDEV=m +CONFIG_NF_FLOW_TABLE_INET=m +CONFIG_NF_FLOW_TABLE=m +CONFIG_NETFILTER_XT_SET=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LED=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_TEE=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m +CONFIG_NETFILTER_XT_MATCH_CGROUP=m +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_CPU=m +CONFIG_NETFILTER_XT_MATCH_DCCP=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_IPCOMP=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_IPVS=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SCTP=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +CONFIG_IP_SET=m +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPMARK=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_IPMAC=m +CONFIG_IP_SET_HASH_MAC=m +CONFIG_IP_SET_HASH_NETPORTNET=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETNET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m +CONFIG_IP_VS=m +CONFIG_IP_VS_IPV6=y +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_AH=y +CONFIG_IP_VS_PROTO_SCTP=y +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_WRR=m +CONFIG_IP_VS_LC=m +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_FO=m +CONFIG_IP_VS_OVF=m +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_MH=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_NQ=m +CONFIG_NFT_DUP_IPV4=m +CONFIG_NFT_FIB_IPV4=m +CONFIG_NF_TABLES_ARP=y +CONFIG_NF_FLOW_TABLE_IPV4=m +CONFIG_NF_LOG_ARP=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_SYNPROXY=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NFT_FIB_IPV6=m +CONFIG_NF_FLOW_TABLE_IPV6=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RPFILTER=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_MATCH_SRH=m +CONFIG_IP6_NF_TARGET_HL=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_TARGET_SYNPROXY=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_RAW=m +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_IP6_NF_TARGET_NPT=m +CONFIG_NF_TABLES_BRIDGE=m +CONFIG_NFT_BRIDGE_META=m +CONFIG_NFT_BRIDGE_REJECT=m +CONFIG_NF_LOG_BRIDGE=m +CONFIG_NF_CONNTRACK_BRIDGE=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_IP6=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_NFLOG=m +CONFIG_BPFILTER=y +CONFIG_L2TP=m +CONFIG_L2TP_V3=y +CONFIG_L2TP_IP=m +CONFIG_L2TP_ETH=m +CONFIG_BRIDGE=m +CONFIG_BRIDGE_VLAN_FILTERING=y +CONFIG_BRIDGE_MRP=y +CONFIG_NET_DSA=m +CONFIG_VLAN_8021Q=m +CONFIG_6LOWPAN=m +CONFIG_DNS_RESOLVER=y +CONFIG_BATMAN_ADV=m +CONFIG_NETLINK_DIAG=m +CONFIG_NET_NCSI=y +CONFIG_CGROUP_NET_PRIO=y +CONFIG_BPF_JIT=y +CONFIG_CAN=m +CONFIG_CAN_J1939=m +CONFIG_CAN_ISOTP=m +CONFIG_CAN_VCAN=m +CONFIG_CAN_FLEXCAN=m +CONFIG_BT=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=m +CONFIG_BT_6LOWPAN=m +CONFIG_BT_HCIBTUSB=m +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_BCSP=y +CONFIG_BT_HCIUART_ATH3K=y +CONFIG_BT_HCIBCM203X=m +CONFIG_BT_HCIBPA10X=m +CONFIG_BT_HCIBFUSB=m +CONFIG_BT_HCIVHCI=m +CONFIG_CFG80211=m +# CONFIG_CFG80211_DEFAULT_PS is not set +CONFIG_CFG80211_WEXT=y +CONFIG_MAC80211=m +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_GNSS=y +CONFIG_GNSS_NMEA_SERIAL=y +CONFIG_BLK_DEV_LOOP=m +CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_RAM=m +CONFIG_EEPROM_AT24=m +CONFIG_EEPROM_AT25=m +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_DEV_SR=m +CONFIG_CHR_DEV_SG=m +CONFIG_MD=y +CONFIG_BLK_DEV_DM=m +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_NETDEVICES=y +CONFIG_DUMMY=m +CONFIG_WIREGUARD=m +CONFIG_MACVLAN=m +CONFIG_IPVLAN=m +CONFIG_VXLAN=m +CONFIG_TUN=m +CONFIG_VETH=m +CONFIG_NET_DSA_MV88E6XXX=m +# CONFIG_NET_VENDOR_ALACRITECH is not set +# CONFIG_NET_VENDOR_AMAZON is not set +# CONFIG_NET_VENDOR_AQUANTIA is not set +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_AURORA is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CADENCE is not set +# CONFIG_NET_VENDOR_CAVIUM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_CORTINA is not set +# CONFIG_NET_VENDOR_EZCHIP is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_GOOGLE is not set +# CONFIG_NET_VENDOR_HISILICON is not set +# CONFIG_NET_VENDOR_HUAWEI is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MELLANOX is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_MICROSEMI is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NETRONOME is not set +# CONFIG_NET_VENDOR_NI is not set +# CONFIG_NET_VENDOR_PENSANDO is not set +# CONFIG_NET_VENDOR_QUALCOMM is not set +# CONFIG_NET_VENDOR_RENESAS is not set +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SOLARFLARE is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_SOCIONEXT is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +# CONFIG_NET_VENDOR_XILINX is not set +CONFIG_SMSC_PHY=y +CONFIG_PPP=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPPOE=m +CONFIG_PPTP=m +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_USB_CATC=m +CONFIG_USB_KAWETH=m +CONFIG_USB_PEGASUS=m +CONFIG_USB_RTL8150=m +CONFIG_USB_RTL8152=m +CONFIG_USB_LAN78XX=m +CONFIG_USB_USBNET=m +CONFIG_USB_NET_CDC_EEM=m +CONFIG_USB_NET_HUAWEI_CDC_NCM=m +CONFIG_USB_NET_CDC_MBIM=m +CONFIG_USB_NET_DM9601=m +CONFIG_USB_NET_SR9700=m +CONFIG_USB_NET_SR9800=m +CONFIG_USB_NET_SMSC75XX=m +CONFIG_USB_NET_SMSC95XX=m +CONFIG_USB_NET_GL620A=m +CONFIG_USB_NET_PLUSB=m +CONFIG_USB_NET_MCS7830=m +CONFIG_USB_NET_RNDIS_HOST=m +CONFIG_USB_NET_CX82310_ETH=m +CONFIG_USB_NET_KALMIA=m +CONFIG_USB_NET_QMI_WWAN=m +CONFIG_USB_NET_INT51X1=m +CONFIG_USB_IPHETH=m +CONFIG_USB_SIERRA_NET=m +CONFIG_USB_VL600=m +CONFIG_USB_NET_CH9200=m +CONFIG_USB_NET_AQC111=m +# CONFIG_WLAN_VENDOR_ADMTEK is not set +CONFIG_ATH9K=m +CONFIG_ATH9K_HTC=m +CONFIG_CARL9170=m +CONFIG_ATH6KL=m +CONFIG_ATH6KL_USB=m +CONFIG_AR5523=m +CONFIG_ATH10K=m +CONFIG_ATH10K_USB=m +CONFIG_WCN36XX=m +CONFIG_AT76C50X_USB=m +# CONFIG_WLAN_VENDOR_BROADCOM is not set +# CONFIG_WLAN_VENDOR_CISCO is not set +# CONFIG_WLAN_VENDOR_INTEL is not set +# CONFIG_WLAN_VENDOR_INTERSIL is not set +# CONFIG_WLAN_VENDOR_MARVELL is not set +# CONFIG_WLAN_VENDOR_MEDIATEK is not set +# CONFIG_WLAN_VENDOR_MICROCHIP is not set +CONFIG_RT2X00=m +CONFIG_RT2500USB=m +CONFIG_RT73USB=m +CONFIG_RT2800USB=m +CONFIG_RT2800USB_RT3573=y +CONFIG_RT2800USB_RT53XX=y +CONFIG_RT2800USB_RT55XX=y +CONFIG_RT2800USB_UNKNOWN=y +CONFIG_RTL8192CU=m +CONFIG_RTL8XXXU=m +CONFIG_RTL8XXXU_UNTESTED=y +# CONFIG_WLAN_VENDOR_RSI is not set +# CONFIG_WLAN_VENDOR_ST is not set +CONFIG_WL12XX=m +CONFIG_WLCORE_SDIO=m +CONFIG_USB_ZD1201=m +CONFIG_ZD1211RW=m +CONFIG_INPUT_MOUSEDEV=m +CONFIG_INPUT_JOYDEV=m +CONFIG_INPUT_EVDEV=m +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +CONFIG_VT_HW_CONSOLE_BINDING=y +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_MXS_AUART=y +CONFIG_SERIAL_DEV_BUS=y +# CONFIG_HW_RANDOM is not set +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_GPIO=y +CONFIG_I2C_MXS=y +CONFIG_SPI=y +CONFIG_SPI_GPIO=m +CONFIG_SPI_MXS=y +CONFIG_SPI_SPIDEV=m +CONFIG_PPS_CLIENT_GPIO=m +CONFIG_GPIO_SYSFS=y +CONFIG_HWMON=m +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED is not set +CONFIG_TS_WDT_MICRO=y +CONFIG_MFD_MXS_LRADC=m +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_SOUND=y +CONFIG_SND=y +# CONFIG_SND_ARM is not set +# CONFIG_SND_SPI is not set +CONFIG_SND_USB_AUDIO=m +CONFIG_SND_USB_UA101=m +CONFIG_SND_USB_CAIAQ=m +CONFIG_SND_USB_6FIRE=m +CONFIG_SND_USB_HIFACE=m +CONFIG_SND_BCD2000=m +CONFIG_SND_USB_POD=m +CONFIG_SND_USB_PODHD=m +CONFIG_SND_USB_TONEPORT=m +CONFIG_SND_USB_VARIAX=m +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MONTEREY is not set +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_OTG=y +CONFIG_USB_OTG_FSM=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_SIMPLE=m +CONFIG_USB_SERIAL_AIRCABLE=m +CONFIG_USB_SERIAL_ARK3116=m +CONFIG_USB_SERIAL_BELKIN=m +CONFIG_USB_SERIAL_CH341=m +CONFIG_USB_SERIAL_WHITEHEAT=m +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m +CONFIG_USB_SERIAL_CP210X=m +CONFIG_USB_SERIAL_CYPRESS_M8=m +CONFIG_USB_SERIAL_EMPEG=m +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_VISOR=m +CONFIG_USB_SERIAL_IPAQ=m +CONFIG_USB_SERIAL_IR=m +CONFIG_USB_SERIAL_EDGEPORT=m +CONFIG_USB_SERIAL_EDGEPORT_TI=m +CONFIG_USB_SERIAL_F81232=m +CONFIG_USB_SERIAL_F8153X=m +CONFIG_USB_SERIAL_GARMIN=m +CONFIG_USB_SERIAL_IPW=m +CONFIG_USB_SERIAL_IUU=m +CONFIG_USB_SERIAL_KEYSPAN_PDA=m +CONFIG_USB_SERIAL_KEYSPAN=m +CONFIG_USB_SERIAL_KLSI=m +CONFIG_USB_SERIAL_KOBIL_SCT=m +CONFIG_USB_SERIAL_MCT_U232=m +CONFIG_USB_SERIAL_METRO=m +CONFIG_USB_SERIAL_MOS7720=m +CONFIG_USB_SERIAL_MOS7840=m +CONFIG_USB_SERIAL_MXUPORT=m +CONFIG_USB_SERIAL_NAVMAN=m +CONFIG_USB_SERIAL_PL2303=m +CONFIG_USB_SERIAL_OTI6858=m +CONFIG_USB_SERIAL_QCAUX=m +CONFIG_USB_SERIAL_QUALCOMM=m +CONFIG_USB_SERIAL_SPCP8X5=m +CONFIG_USB_SERIAL_SAFE=m +CONFIG_USB_SERIAL_SIERRAWIRELESS=m +CONFIG_USB_SERIAL_SYMBOL=m +CONFIG_USB_SERIAL_TI=m +CONFIG_USB_SERIAL_CYBERJACK=m +CONFIG_USB_SERIAL_XIRCOM=m +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_SERIAL_OMNINET=m +CONFIG_USB_SERIAL_OPTICON=m +CONFIG_USB_SERIAL_XSENS_MT=m +CONFIG_USB_SERIAL_WISHBONE=m +CONFIG_USB_SERIAL_SSU100=m +CONFIG_USB_SERIAL_QT2=m +CONFIG_USB_SERIAL_UPD78F0730=m +CONFIG_USB_SERIAL_DEBUG=m +CONFIG_USB_MXS_PHY=y +CONFIG_USB_GADGET=y +CONFIG_USB_CONFIGFS=m +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONFIGFS_ACM=y +CONFIG_USB_CONFIGFS_OBEX=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_ECM=y +CONFIG_USB_CONFIGFS_ECM_SUBSET=y +CONFIG_USB_CONFIGFS_RNDIS=y +CONFIG_USB_CONFIGFS_EEM=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_LB_SS=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_CONFIGFS_F_UAC1=y +CONFIG_USB_CONFIGFS_F_UAC2=y +CONFIG_USB_CONFIGFS_F_MIDI=y +CONFIG_USB_CONFIGFS_F_HID=y +CONFIG_USB_CONFIGFS_F_PRINTER=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_GADGETFS=m +CONFIG_USB_FUNCTIONFS=m +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m +CONFIG_USB_CDC_COMPOSITE=m +CONFIG_USB_G_ACM_MS=m +CONFIG_USB_G_HID=m +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_MXS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_ONESHOT=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_LEDS_TRIGGER_PANIC=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_DS1307=y +CONFIG_RTC_DRV_ISL12022=m +CONFIG_DMADEVICES=y +CONFIG_MXS_DMA=y +CONFIG_COMMON_CLK_PWM=y +CONFIG_IIO=m +CONFIG_MMA8452=m +CONFIG_MXS_LRADC_ADC=m +CONFIG_PWM=y +CONFIG_PWM_MXS=y +CONFIG_NVMEM_MXS_OCOTP=m +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_FANOTIFY=y +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=m +CONFIG_CUSE=m +CONFIG_OVERLAY_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=y +CONFIG_EXFAT_FS=m +CONFIG_NTFS_FS=m +CONFIG_NTFS_RW=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y +CONFIG_ROOT_NFS=y +CONFIG_CIFS=m +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_15=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_DEV_MXS_DCP=y +CONFIG_CRC7=m +CONFIG_PRINTK_TIME=y +CONFIG_FRAME_WARN=2048 +CONFIG_DEBUG_FS=y +CONFIG_STACKTRACE=y +CONFIG_STRICT_DEVMEM=y +CONFIG_DEBUG_USER=y +# CONFIG_RUNTIME_TESTING_MENU is not set diff --git a/arch/arm/configs/ts_imx28_defconfig b/arch/arm/configs/tsimx28_minimal_defconfig similarity index 78% rename from arch/arm/configs/ts_imx28_defconfig rename to arch/arm/configs/tsimx28_minimal_defconfig index 646c8b70bb182..81351c73463f8 100644 --- a/arch/arm/configs/ts_imx28_defconfig +++ b/arch/arm/configs/tsimx28_minimal_defconfig @@ -1,6 +1,4 @@ # CONFIG_SWAP is not set -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y # CONFIG_CROSS_MEMORY_ATTACH is not set CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y @@ -11,11 +9,13 @@ CONFIG_TASK_XACCT=y CONFIG_TASK_IO_ACCOUNTING=y CONFIG_CGROUPS=y # CONFIG_UTS_NS is not set -# CONFIG_IPC_NS is not set # CONFIG_PID_NS is not set CONFIG_BLK_DEV_INITRD=y +# CONFIG_RD_ZSTD is not set +CONFIG_KALLSYMS_ALL=y CONFIG_PERF_EVENTS=y # CONFIG_COMPAT_BRK is not set +# CONFIG_SLAB_MERGE_DEFAULT is not set # CONFIG_ARCH_MULTI_V7 is not set CONFIG_ARCH_MXS=y CONFIG_AEABI=y @@ -40,10 +40,7 @@ CONFIG_SYN_COOKIES=y # CONFIG_INET_DIAG is not set CONFIG_IPV6=m CONFIG_IPV6_VTI=m -CONFIG_BRIDGE=m -CONFIG_BRIDGE_VLAN_FILTERING=y -CONFIG_NET_DSA=m -CONFIG_VLAN_8021Q=m +CONFIG_DNS_RESOLVER=y CONFIG_CAN=m CONFIG_CAN_FLEXCAN=m CONFIG_BT=m @@ -62,8 +59,10 @@ CONFIG_BT_HCIBPA10X=m CONFIG_BT_HCIBFUSB=m CONFIG_BT_HCIVHCI=m CONFIG_CFG80211=m +# CONFIG_CFG80211_DEFAULT_PS is not set CONFIG_CFG80211_WEXT=y CONFIG_MAC80211=m +CONFIG_MAC80211_LEDS=y CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_GNSS=y @@ -79,79 +78,73 @@ CONFIG_BLK_DEV_SD=y CONFIG_BLK_DEV_SR=m CONFIG_CHR_DEV_SG=m CONFIG_NETDEVICES=y -CONFIG_MACVLAN=m -CONFIG_TUN=m -CONFIG_NET_DSA_MV88E6XXX=m +# CONFIG_NET_VENDOR_ALACRITECH is not set # CONFIG_NET_VENDOR_AMAZON is not set +# CONFIG_NET_VENDOR_AQUANTIA is not set # CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_AURORA is not set # CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CADENCE is not set +# CONFIG_NET_VENDOR_CAVIUM is not set # CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_CORTINA is not set # CONFIG_NET_VENDOR_EZCHIP is not set # CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_GOOGLE is not set # CONFIG_NET_VENDOR_HISILICON is not set +# CONFIG_NET_VENDOR_HUAWEI is not set # CONFIG_NET_VENDOR_INTEL is not set # CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MELLANOX is not set # CONFIG_NET_VENDOR_MICREL is not set # CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_MICROSEMI is not set # CONFIG_NET_VENDOR_NATSEMI is not set # CONFIG_NET_VENDOR_NETRONOME is not set +# CONFIG_NET_VENDOR_NI is not set +# CONFIG_NET_VENDOR_PENSANDO is not set # CONFIG_NET_VENDOR_QUALCOMM is not set # CONFIG_NET_VENDOR_RENESAS is not set # CONFIG_NET_VENDOR_ROCKER is not set # CONFIG_NET_VENDOR_SAMSUNG is not set # CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SOLARFLARE is not set # CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_SOCIONEXT is not set # CONFIG_NET_VENDOR_STMICRO is not set # CONFIG_NET_VENDOR_SYNOPSYS is not set # CONFIG_NET_VENDOR_VIA is not set # CONFIG_NET_VENDOR_WIZNET is not set -CONFIG_PPP=m -CONFIG_PPP_BSDCOMP=m -CONFIG_PPP_DEFLATE=m -CONFIG_PPP_MPPE=m -CONFIG_PPPOE=m -CONFIG_PPP_ASYNC=m -CONFIG_PPP_SYNC_TTY=m -CONFIG_USB_RTL8152=m -CONFIG_USB_LAN78XX=m -CONFIG_USB_USBNET=y -CONFIG_USB_NET_HUAWEI_CDC_NCM=m -CONFIG_USB_NET_CDC_MBIM=m -CONFIG_USB_NET_SMSC75XX=m -CONFIG_USB_NET_SMSC95XX=y -CONFIG_USB_NET_PLUSB=m +# CONFIG_NET_VENDOR_XILINX is not set +CONFIG_MICROCHIP_PHY=m +CONFIG_SMSC_PHY=y +CONFIG_USB_USBNET=m +# CONFIG_USB_NET_AX8817X is not set +# CONFIG_USB_NET_AX88179_178A is not set +# CONFIG_USB_NET_CDCETHER is not set +# CONFIG_USB_NET_CDC_NCM is not set +CONFIG_USB_NET_SMSC95XX=m +# CONFIG_USB_NET_NET1080 is not set +# CONFIG_USB_NET_CDC_SUBSET is not set +# CONFIG_USB_NET_ZAURUS is not set # CONFIG_WLAN_VENDOR_ADMTEK is not set -CONFIG_ATH9K=m -CONFIG_ATH9K_HTC=m -CONFIG_CARL9170=m -CONFIG_ATH6KL=m -CONFIG_ATH6KL_USB=m -CONFIG_AR5523=m -CONFIG_ATH10K=m -CONFIG_WCN36XX=m -CONFIG_AT76C50X_USB=m +# CONFIG_WLAN_VENDOR_ATH is not set +# CONFIG_WLAN_VENDOR_ATMEL is not set # CONFIG_WLAN_VENDOR_BROADCOM is not set # CONFIG_WLAN_VENDOR_CISCO is not set # CONFIG_WLAN_VENDOR_INTEL is not set # CONFIG_WLAN_VENDOR_INTERSIL is not set # CONFIG_WLAN_VENDOR_MARVELL is not set # CONFIG_WLAN_VENDOR_MEDIATEK is not set -CONFIG_RT2X00=m -CONFIG_RT2500USB=m -CONFIG_RT73USB=m -CONFIG_RT2800USB=m -# CONFIG_RT2800USB_RT35XX is not set -CONFIG_RTL8192CU=m -CONFIG_RTL8XXXU=m +# CONFIG_WLAN_VENDOR_MICROCHIP is not set +# CONFIG_WLAN_VENDOR_RALINK is not set +# CONFIG_WLAN_VENDOR_REALTEK is not set # CONFIG_WLAN_VENDOR_RSI is not set # CONFIG_WLAN_VENDOR_ST is not set CONFIG_WL12XX=m CONFIG_WLCORE_SDIO=m -CONFIG_USB_ZD1201=m -CONFIG_ZD1211RW=m -CONFIG_INPUT_MOUSEDEV=m -CONFIG_INPUT_JOYDEV=m -CONFIG_INPUT_EVDEV=m +# CONFIG_WLAN_VENDOR_ZYDAS is not set +# CONFIG_WLAN_VENDOR_QUANTENNA is not set # CONFIG_INPUT_KEYBOARD is not set # CONFIG_INPUT_MOUSE is not set # CONFIG_SERIO is not set @@ -170,7 +163,8 @@ CONFIG_SPI=y CONFIG_SPI_GPIO=m CONFIG_SPI_MXS=y CONFIG_SPI_SPIDEV=m -CONFIG_PPS_CLIENT_GPIO=m +CONFIG_PPS=y +# CONFIG_PTP_1588_CLOCK is not set CONFIG_GPIO_SYSFS=y CONFIG_HWMON=m CONFIG_WATCHDOG=y @@ -210,20 +204,10 @@ CONFIG_USB_OTG=y CONFIG_USB_OTG_FSM=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_USB_ACM=m CONFIG_USB_STORAGE=y CONFIG_USB_CHIPIDEA=y CONFIG_USB_CHIPIDEA_UDC=y CONFIG_USB_CHIPIDEA_HOST=y -CONFIG_USB_SERIAL=m -CONFIG_USB_SERIAL_GENERIC=y -CONFIG_USB_SERIAL_SIMPLE=m -CONFIG_USB_SERIAL_CP210X=m -CONFIG_USB_SERIAL_FTDI_SIO=m -CONFIG_USB_SERIAL_GARMIN=m -CONFIG_USB_SERIAL_PL2303=m -CONFIG_USB_SERIAL_SIERRAWIRELESS=m -CONFIG_USB_SERIAL_SYMBOL=m CONFIG_USB_MXS_PHY=y CONFIG_USB_GADGET=y CONFIG_USB_CONFIGFS=m @@ -271,6 +255,8 @@ CONFIG_RTC_DRV_DS1307=y CONFIG_RTC_DRV_ISL12022=m CONFIG_DMADEVICES=y CONFIG_MXS_DMA=y +# CONFIG_VIRTIO_MENU is not set +# CONFIG_VHOST_MENU is not set CONFIG_COMMON_CLK_PWM=y CONFIG_IIO=m CONFIG_MMA8452=m @@ -282,30 +268,28 @@ CONFIG_EXT4_FS=y # CONFIG_DNOTIFY is not set CONFIG_FANOTIFY=y CONFIG_AUTOFS4_FS=y -CONFIG_FSCACHE=m -CONFIG_FSCACHE_STATS=y -CONFIG_CACHEFILES=m CONFIG_VFAT_FS=y CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y +# CONFIG_MISC_FILESYSTEMS is not set CONFIG_NFS_FS=y CONFIG_NFS_V3_ACL=y -CONFIG_NFS_V4=y CONFIG_ROOT_NFS=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_CODEPAGE_850=y CONFIG_NLS_ISO8859_1=y CONFIG_NLS_ISO8859_15=y +CONFIG_CRYPTO_SHA1=m CONFIG_CRYPTO_DEFLATE=y CONFIG_CRYPTO_LZO=y CONFIG_CRYPTO_DEV_MXS_DCP=y +CONFIG_CRC_CCITT=m +CONFIG_CRC_ITU_T=m CONFIG_CRC7=m CONFIG_PRINTK_TIME=y -CONFIG_DEBUG_INFO=y CONFIG_FRAME_WARN=2048 -CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_KERNEL=y -CONFIG_PROVE_LOCKING=y +# CONFIG_DEBUG_MISC is not set CONFIG_BLK_DEV_IO_TRACE=y -CONFIG_STRICT_DEVMEM=y CONFIG_DEBUG_USER=y +# CONFIG_RUNTIME_TESTING_MENU is not set From 85d9770421c0c4b60add7b7ab1107fd3bbddd3c6 Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Wed, 15 Mar 2023 09:07:24 -0700 Subject: [PATCH 054/244] ARM: configs: tsimx6ul: Align with other defconfigs Updated config to be consistent with our *_config_requirements Signed-off-by: Mark Featherston Signed-off-by: Kris Bahnsen --- arch/arm/configs/tsimx6ul_defconfig | 283 +++++++++++++++++++- arch/arm/configs/tsimx6ul_minimal_defconfig | 5 + 2 files changed, 275 insertions(+), 13 deletions(-) diff --git a/arch/arm/configs/tsimx6ul_defconfig b/arch/arm/configs/tsimx6ul_defconfig index cc36cb4f2a71e..e96905e13efc5 100644 --- a/arch/arm/configs/tsimx6ul_defconfig +++ b/arch/arm/configs/tsimx6ul_defconfig @@ -4,6 +4,7 @@ CONFIG_POSIX_MQUEUE=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y CONFIG_PREEMPT=y +CONFIG_PSI=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=18 @@ -19,13 +20,15 @@ CONFIG_CPUSETS=y CONFIG_CGROUP_DEVICE=y CONFIG_CGROUP_CPUACCT=y CONFIG_CGROUP_PERF=y +CONFIG_CGROUP_BPF=y CONFIG_NAMESPACES=y CONFIG_USER_NS=y +CONFIG_CHECKPOINT_RESTORE=y CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y CONFIG_EXPERT=y +CONFIG_KALLSYMS_ALL=y CONFIG_BPF_SYSCALL=y -CONFIG_KCMP=y CONFIG_PC104=y CONFIG_PERF_EVENTS=y # CONFIG_SLUB_DEBUG is not set @@ -69,18 +72,269 @@ CONFIG_CMA=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y +CONFIG_TLS=m +CONFIG_XFRM_USER=m CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE_DEMUX=m +CONFIG_NET_IPGRE=m +CONFIG_NET_IPVTI=m +CONFIG_NET_FOU=m +CONFIG_INET_ESP=m +CONFIG_INET_IPCOMP=m +CONFIG_MPTCP=y CONFIG_NETFILTER=y +CONFIG_BRIDGE_NETFILTER=m +CONFIG_NF_CONNTRACK=m +CONFIG_NF_LOG_NETDEV=m +CONFIG_NF_CONNTRACK_ZONES=y +CONFIG_NF_CONNTRACK_PROCFS=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_TIMEOUT=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y +CONFIG_NF_CONNTRACK_AMANDA=m +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_SNMP=m +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_CT_NETLINK=m +CONFIG_NF_CT_NETLINK_TIMEOUT=m +CONFIG_NF_CT_NETLINK_HELPER=m +CONFIG_NETFILTER_NETLINK_GLUE_CT=y +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_INET=y +CONFIG_NF_TABLES_NETDEV=y +CONFIG_NFT_NUMGEN=m +CONFIG_NFT_CT=m +CONFIG_NFT_FLOW_OFFLOAD=m +CONFIG_NFT_COUNTER=m +CONFIG_NFT_CONNLIMIT=m +CONFIG_NFT_LOG=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_REDIR=m +CONFIG_NFT_NAT=m +CONFIG_NFT_TUNNEL=m +CONFIG_NFT_OBJREF=m +CONFIG_NFT_QUEUE=m +CONFIG_NFT_QUOTA=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_HASH=m +CONFIG_NFT_FIB_INET=m +CONFIG_NFT_XFRM=m +CONFIG_NFT_SOCKET=m +CONFIG_NFT_OSF=m +CONFIG_NFT_TPROXY=m +CONFIG_NFT_SYNPROXY=m +CONFIG_NFT_DUP_NETDEV=m +CONFIG_NFT_FWD_NETDEV=m +CONFIG_NFT_FIB_NETDEV=m +CONFIG_NF_FLOW_TABLE_INET=m +CONFIG_NF_FLOW_TABLE=m +CONFIG_NETFILTER_XT_SET=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LED=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_TEE=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m +CONFIG_NETFILTER_XT_MATCH_CGROUP=m +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_CPU=m +CONFIG_NETFILTER_XT_MATCH_DCCP=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_IPCOMP=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_IPVS=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SCTP=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +CONFIG_IP_SET=m +CONFIG_IP_VS=m +CONFIG_IP_VS_IPV6=y +CONFIG_IP_VS_DEBUG=y +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_AH=y +CONFIG_IP_VS_PROTO_SCTP=y +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_WRR=m +CONFIG_IP_VS_LC=m +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_FO=m +CONFIG_IP_VS_OVF=m +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_MH=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_NQ=m +CONFIG_IP_VS_NFCT=y +CONFIG_NFT_DUP_IPV4=m +CONFIG_NFT_FIB_IPV4=m +CONFIG_NF_TABLES_ARP=y +CONFIG_NF_FLOW_TABLE_IPV4=m +CONFIG_NF_LOG_ARP=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_SYNPROXY=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NFT_FIB_IPV6=m +CONFIG_NF_FLOW_TABLE_IPV6=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RPFILTER=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_MATCH_SRH=m +CONFIG_IP6_NF_TARGET_HL=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_TARGET_SYNPROXY=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_RAW=m +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_IP6_NF_TARGET_NPT=m +CONFIG_NF_TABLES_BRIDGE=m +CONFIG_NFT_BRIDGE_META=m +CONFIG_NFT_BRIDGE_REJECT=m +CONFIG_NF_LOG_BRIDGE=m +CONFIG_NF_CONNTRACK_BRIDGE=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_IP6=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_NFLOG=m +CONFIG_BPFILTER=y +CONFIG_L2TP=m +CONFIG_L2TP_V3=y +CONFIG_L2TP_IP=m +CONFIG_L2TP_ETH=m +CONFIG_BRIDGE=m +CONFIG_BRIDGE_VLAN_FILTERING=y +CONFIG_VLAN_8021Q=m +CONFIG_6LOWPAN=m +CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m +CONFIG_6LOWPAN_GHC_UDP=m +CONFIG_6LOWPAN_GHC_ICMPV6=m +CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m +CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m +CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m CONFIG_DNS_RESOLVER=y +CONFIG_BPF_JIT=y CONFIG_CAN=y +CONFIG_CAN_J1939=m +CONFIG_CAN_ISOTP=m +CONFIG_CAN_VCAN=m CONFIG_CAN_FLEXCAN=y +CONFIG_CAN_8DEV_USB=m +CONFIG_CAN_EMS_USB=m +CONFIG_CAN_ESD_USB2=m +CONFIG_CAN_GS_USB=m +CONFIG_CAN_KVASER_USB=m +CONFIG_CAN_MCBA_USB=m +CONFIG_CAN_PEAK_USB=m +CONFIG_CAN_UCAN=m CONFIG_BT=y CONFIG_BT_BNEP=m CONFIG_BT_HCIUART=y CONFIG_BT_HCIUART_LL=y CONFIG_CFG80211=y +# CONFIG_CFG80211_DEFAULT_PS is not set CONFIG_CFG80211_WEXT=y CONFIG_MAC80211=y CONFIG_RFKILL=y @@ -90,8 +344,6 @@ CONFIG_DEVTMPFS_MOUNT=y # CONFIG_STANDALONE is not set CONFIG_EXTRA_FIRMWARE="imx/sdma/sdma-imx6q.bin" CONFIG_EXTRA_FIRMWARE_DIR="firmware" -CONFIG_FW_LOADER_USER_HELPER=y -CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y CONFIG_IMX_WEIM=y CONFIG_TSPC104=y CONFIG_CONNECTOR=y @@ -123,7 +375,12 @@ CONFIG_SCSI_CONSTANTS=y CONFIG_SCSI_LOGGING=y CONFIG_SCSI_SCAN_ASYNC=y # CONFIG_SCSI_LOWLEVEL is not set +CONFIG_MD=y +CONFIG_BLK_DEV_DM=m +CONFIG_DM_THIN_PROVISIONING=m CONFIG_NETDEVICES=y +CONFIG_BONDING=m +CONFIG_DUMMY=m CONFIG_WIREGUARD=m CONFIG_MACVLAN=m CONFIG_IPVLAN=m @@ -170,6 +427,7 @@ CONFIG_VETH=m # CONFIG_NET_VENDOR_WIZNET is not set # CONFIG_NET_VENDOR_XILINX is not set CONFIG_MICREL_PHY=y +CONFIG_MICROCHIP_PHY=y CONFIG_SMSC_PHY=y CONFIG_PPP=m CONFIG_PPP_BSDCOMP=m @@ -178,15 +436,17 @@ CONFIG_PPP_FILTER=y CONFIG_PPP_MPPE=m CONFIG_PPP_MULTILINK=y CONFIG_PPPOE=m +CONFIG_PPTP=m +CONFIG_PPPOL2TP=m CONFIG_PPP_ASYNC=m CONFIG_PPP_SYNC_TTY=m +CONFIG_USB_NET_DRIVERS=m CONFIG_USB_CATC=m CONFIG_USB_KAWETH=m CONFIG_USB_PEGASUS=m CONFIG_USB_RTL8150=m -CONFIG_USB_RTL8152=y -CONFIG_USB_LAN78XX=y -CONFIG_USB_USBNET=y +CONFIG_USB_RTL8152=m +CONFIG_USB_LAN78XX=m CONFIG_USB_NET_CDC_EEM=m CONFIG_USB_NET_HUAWEI_CDC_NCM=m CONFIG_USB_NET_CDC_MBIM=m @@ -196,11 +456,8 @@ CONFIG_USB_NET_SR9800=m CONFIG_USB_NET_SMSC75XX=m CONFIG_USB_NET_SMSC95XX=m CONFIG_USB_NET_GL620A=m -CONFIG_USB_NET_NET1080=m CONFIG_USB_NET_PLUSB=m CONFIG_USB_NET_MCS7830=m -CONFIG_USB_NET_CDC_SUBSET=m -CONFIG_USB_NET_ZAURUS=m CONFIG_USB_NET_CX82310_ETH=m CONFIG_USB_NET_KALMIA=m CONFIG_USB_NET_QMI_WWAN=m @@ -821,19 +1078,19 @@ CONFIG_NLS_UTF8=y CONFIG_SECURITYFS=y CONFIG_CRYPTO_DEFLATE=y CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_ZSTD=y CONFIG_CRYPTO_DEV_FSL_CAAM=y CONFIG_CRYPTO_DEV_SAHARA=y CONFIG_CRYPTO_DEV_MXS_DCP=y CONFIG_CRC_T10DIF=y CONFIG_CRC7=m -CONFIG_LIBCRC32C=m CONFIG_DMA_CMA=y CONFIG_CMA_SIZE_MBYTES=64 CONFIG_PRINTK_TIME=y # CONFIG_DEBUG_BUGVERBOSE is not set -CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_FS=y +# CONFIG_DEBUG_MISC is not set # CONFIG_SCHED_DEBUG is not set -CONFIG_PROVE_LOCKING=y +# CONFIG_DEBUG_PREEMPT is not set +CONFIG_STACKTRACE=y # CONFIG_FTRACE is not set +# CONFIG_RUNTIME_TESTING_MENU is not set diff --git a/arch/arm/configs/tsimx6ul_minimal_defconfig b/arch/arm/configs/tsimx6ul_minimal_defconfig index 874f2f9f2a0aa..8aadc17546c46 100644 --- a/arch/arm/configs/tsimx6ul_minimal_defconfig +++ b/arch/arm/configs/tsimx6ul_minimal_defconfig @@ -201,9 +201,13 @@ CONFIG_I2C_IMX=y CONFIG_SPI=y CONFIG_SPI_GPIO=y CONFIG_SPI_IMX=y +CONFIG_SPI_OCORES=m +CONFIG_SPI_SPIDEV=m # CONFIG_PTP_1588_CLOCK is not set CONFIG_GPIO_SYSFS=y CONFIG_GPIO_MXC=y +CONFIG_GPIO_TS71XXWEIM=y +CONFIG_GPIO_PCA953X=m CONFIG_GPIO_TS4900=y CONFIG_POWER_RESET=y CONFIG_POWER_RESET_TS_SUPERVISOR=y @@ -293,6 +297,7 @@ CONFIG_MPL3115=y CONFIG_TS_SUPERVISOR_TEMP=m CONFIG_PWM=y CONFIG_PWM_IMX27=y +CONFIG_PWM_TS=m CONFIG_TSWEIM_FPGA_INTC=y CONFIG_NVMEM_IMX_OCOTP=y CONFIG_NVMEM_SNVS_LPGPR=y From accaef2d7d226fba518134c32c65395e1d046769 Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Wed, 15 Mar 2023 09:06:01 -0700 Subject: [PATCH 055/244] tests: ts_check_configs: Initial commit Added tests to verify config file changes to be consistent between embeddedTS platforms. Signed-off-by: Mark Featherston Signed-off-by: Kris Bahnsen --- tests/ts_check_configs/config_check | 64 +++++++ .../full_graphics_config_requirements | 171 ++++++++++++++++++ .../full_headless_config_requirements | 162 +++++++++++++++++ .../min_graphics_config_requirements | 49 +++++ .../min_headless_config_requirements | 40 ++++ tests/ts_check_configs/run_test.sh | 51 ++++++ 6 files changed, 537 insertions(+) create mode 100755 tests/ts_check_configs/config_check create mode 100644 tests/ts_check_configs/full_graphics_config_requirements create mode 100644 tests/ts_check_configs/full_headless_config_requirements create mode 100644 tests/ts_check_configs/min_graphics_config_requirements create mode 100644 tests/ts_check_configs/min_headless_config_requirements create mode 100755 tests/ts_check_configs/run_test.sh diff --git a/tests/ts_check_configs/config_check b/tests/ts_check_configs/config_check new file mode 100755 index 0000000000000..1326b2c709bfa --- /dev/null +++ b/tests/ts_check_configs/config_check @@ -0,0 +1,64 @@ +#!/usr/bin/env python3 +import sys +import os + +def parse_config_file(file_path): + """ + Parses a Linux kernel .config file and returns a dictionary of options + that have a value of 'y' or 'm'. + + Args: + file_path (str): The path to the .config file to be parsed. + + Returns: + dict: A dictionary containing the names of options that have a value + of 'y' or 'm' as keys, and their values as values. + + Raises: + IOError: If the file at `file_path` cannot be opened. + ValueError: If the contents of the file at `file_path` are not + formatted correctly. + + Example: + >>> parse_config_file('/path/to/config_file.config') + {'CONFIG_THING1': 'y', 'CONFIG_THING2': 'm'} + options = {} + """ + + options = {} + with open(file_path, 'r', encoding='utf-8') as f: + for line in f: + line = line.strip() + if not line or line.startswith('#') or '=' not in line: + continue + option, value = map(str.strip, line.split('=', 1)) + if value in ('y', 'm', 'n'): + options[option] = value + else: + options[option] = 'x' + return options + +if len(sys.argv) != 3: + print("Usage: check_config requirements.config your.config") + sys.exit(1) + +expected_options = parse_config_file(sys.argv[1]) +config_options = parse_config_file(sys.argv[2]) +RESULT = 0 + +# Check if the config options match the expected options +for expected_option, expected_value in expected_options.items(): + if expected_option in config_options: + if expected_value == 'x': + continue + + if expected_value != config_options[expected_option]: + print(f'{expected_option} is set to {config_options[expected_option]} and should be {expected_value}') + RESULT = 1 + else: + if expected_value == 'n': + continue + print(f'{expected_option} is missing') + RESULT = 1 + +sys.exit(RESULT) diff --git a/tests/ts_check_configs/full_graphics_config_requirements b/tests/ts_check_configs/full_graphics_config_requirements new file mode 100644 index 0000000000000..d6c1e297cea95 --- /dev/null +++ b/tests/ts_check_configs/full_graphics_config_requirements @@ -0,0 +1,171 @@ +# =y required as compiled in +# =m required as a module +# =x either is fine +# =n Must not be included + +######## Driver frameworks required on all hardware: +CONFIG_SPI_SPIDEV=x + +######## Debug options: +CONFIG_LOCKDEP=n +CONFIG_DEBUG_INFO=n +CONFIG_RUNTIME_TESTING_MENU=n +CONFIG_DEBUG_MISC=n +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=n + +######## Systemd requirements: +CONFIG_DEVTMPFS=x +CONFIG_CGROUPS=x +CONFIG_INOTIFY_USER=x +CONFIG_SIGNALFD=x +CONFIG_TIMERFD=x +CONFIG_EPOLL=x +CONFIG_UNIX =x +CONFIG_SYSFS=x +CONFIG_PROC_FS=x +CONFIG_FHANDLE=x + +######## Systemd Optional: +#CONFIG_DMIID=x SMBIOS thing, we dont need thsi +CONFIG_BLK_DEV_BSG=x +CONFIG_NET_NS=x +CONFIG_USER_NS=x +CONFIG_IPV6=x +CONFIG_AUTOFS_FS=x +CONFIG_TMPFS_XATTR=x +CONFIG_TMPFS_POSIX_ACL=x +CONFIG_EXT4_FS_POSIX_ACL=x +CONFIG_SECCOMP=x +CONFIG_SECCOMP_FILTER=x +CONFIG_CHECKPOINT_RESTORE=x +CONFIG_CGROUP_SCHED=x +CONFIG_FAIR_GROUP_SCHED=x +CONFIG_CFS_BANDWIDTH=x +CONFIG_BPF=x +CONFIG_BPF_SYSCALL=x +CONFIG_BPF_JIT=x +CONFIG_HAVE_EBPF_JIT=x +CONFIG_CGROUP_BPF=x +CONFIG_BPF=x +CONFIG_BPF_SYSCALL=x +CONFIG_BPF_JIT=x +CONFIG_HAVE_EBPF_JIT=x +CONFIG_CGROUP_BPF=x +CONFIG_EFIVAR_FS=x +CONFIG_EFI_PARTITION=x +# Skipping verity thinsg +#CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=x +#CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING=x +#CONFIG_IMA_ARCH_POLICY=x +# Skipping these because they require expensive tracing to be enabled +#CONFIG_BPF=x +#CONFIG_BPF_SYSCALL=x +#CONFIG_BPF_LSM=x +#CONFIG_DEBUG_INFO_BTF=x +CONFIG_PSI=x +CONFIG_RT_GROUP_SCHED=n +CONFIG_AUDIT=n +CONFIG_SYSFS_DEPRECATED=n +CONFIG_FW_LOADER_USER_HELPER=n + +######## NFS root requirements: +CONFIG_ROOT_NFS=y +CONFIG_NFS_V3=y +CONFIG_NFS_V2=y +CONFIG_NFS_DISABLE_UDP_SUPPORT=y +CONFIG_IP_PNP_DHCP=y +# Skipped because its huge +CONFIG_NFS_V4=n + +######## Docker requirements: +CONFIG_NAMESPACES=x +CONFIG_NET_NS=x +CONFIG_PID_NS=x +CONFIG_IPC_NS=x +CONFIG_UTS_NS=x +CONFIG_CGROUPS=x +CONFIG_CGROUP_CPUACCT=x +CONFIG_CGROUP_DEVICE=x +CONFIG_CGROUP_FREEZER=x +CONFIG_CGROUP_SCHED=x +# We do want this, but it wont exist on our configs without smp +#CONFIG_CPUSETS=x +CONFIG_MEMCG=x +CONFIG_KEYS=x +CONFIG_VETH=x +CONFIG_BRIDGE=x +CONFIG_BRIDGE_NETFILTER=x +CONFIG_IP_NF_FILTER=x +CONFIG_IP_NF_TARGET_MASQUERADE=x +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=x +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=x +CONFIG_NETFILTER_XT_MATCH_IPVS=x +CONFIG_NETFILTER_XT_MARK=x +CONFIG_IP_NF_NAT=x +CONFIG_NF_NAT=x +CONFIG_POSIX_MQUEUE=x + +######## Docker Optional: +CONFIG_USER_NS=x +CONFIG_SECCOMP=x +CONFIG_SECCOMP_FILTER=x +CONFIG_CGROUP_PIDS=x +CONFIG_MEMCG_SWAP=x +CONFIG_EXT4_FS=x +CONFIG_EXT4_FS_POSIX_ACL=x +CONFIG_EXT4_FS_SECURITY=x +CONFIG_BRIDGE_VLAN_FILTERING=x +CONFIG_VXLAN=x +CONFIG_CRYPTO=x +CONFIG_CRYPTO_AEAD=x +CONFIG_CRYPTO_GCM=x +CONFIG_CRYPTO_SEQIV=x +CONFIG_CRYPTO_GHASH=x +CONFIG_XFRM=x +CONFIG_XFRM_USER=x +CONFIG_XFRM_ALGO=x +CONFIG_INET_ESP=x +CONFIG_IPVLAN=x +CONFIG_MACVLAN=x +CONFIG_DUMMY=x +CONFIG_NF_NAT_FTP=x +CONFIG_NF_CONNTRACK_FTP=x +CONFIG_NF_NAT_TFTP=x +CONFIG_NF_CONNTRACK_TFTP=x +CONFIG_BLK_DEV_DM=x +CONFIG_DM_THIN_PROVISIONING=x +CONFIG_OVERLAY_FS=x + +# Support very common input devices +CONFIG_HID_MULTITOUCH=x +CONFIG_INPUT_MOUSEDEV=x +CONFIG_HID_GENERIC=x + +# Support PWM backlight +CONFIG_BACKLIGHT_CLASS_DEVICE=x +CONFIG_BACKLIGHT_PWM=x + +######## Common customer requirements: +CONFIG_CAN_J1939=x +CONFIG_PTP_1588_CLOCK=x +CONFIG_NETFILTER=x +CONFIG_IPV6=y +#Cell modems: +CONFIG_PPP=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPPOE=m +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_USB_NET_CDCETHER=m +CONFIG_USB_NET_CDC_NCM=m +CONFIG_USB_NET_QMI_WWAN=m + +# Needed for WILC3000 correct operation! +# With powersaving enabled, BLE is completely broken, while Wi-Fi will show +# strange hiccups and subtle breakages sometimes. +CONFIG_CFG80211_DEFAULT_PS=n diff --git a/tests/ts_check_configs/full_headless_config_requirements b/tests/ts_check_configs/full_headless_config_requirements new file mode 100644 index 0000000000000..05126e60cb0c2 --- /dev/null +++ b/tests/ts_check_configs/full_headless_config_requirements @@ -0,0 +1,162 @@ +# =y required as compiled in +# =m required as a module +# =x either is fine +# =n Must not be included + +######## Driver frameworks required on all hardware: +CONFIG_SPI_SPIDEV=x + +######## Debug options: +CONFIG_LOCKDEP=n +CONFIG_DEBUG_INFO=n +CONFIG_RUNTIME_TESTING_MENU=n +CONFIG_DEBUG_MISC=n +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=n + +######## Systemd requirements: +CONFIG_DEVTMPFS=x +CONFIG_CGROUPS=x +CONFIG_INOTIFY_USER=x +CONFIG_SIGNALFD=x +CONFIG_TIMERFD=x +CONFIG_EPOLL=x +CONFIG_UNIX =x +CONFIG_SYSFS=x +CONFIG_PROC_FS=x +CONFIG_FHANDLE=x + +######## Systemd Optional: +#CONFIG_DMIID=x SMBIOS thing, we dont need thsi +CONFIG_BLK_DEV_BSG=x +CONFIG_NET_NS=x +CONFIG_USER_NS=x +CONFIG_IPV6=x +CONFIG_AUTOFS_FS=x +CONFIG_TMPFS_XATTR=x +CONFIG_TMPFS_POSIX_ACL=x +CONFIG_EXT4_FS_POSIX_ACL=x +CONFIG_SECCOMP=x +CONFIG_SECCOMP_FILTER=x +CONFIG_CHECKPOINT_RESTORE=x +CONFIG_CGROUP_SCHED=x +CONFIG_FAIR_GROUP_SCHED=x +CONFIG_CFS_BANDWIDTH=x +CONFIG_BPF=x +CONFIG_BPF_SYSCALL=x +CONFIG_BPF_JIT=x +CONFIG_HAVE_EBPF_JIT=x +CONFIG_CGROUP_BPF=x +CONFIG_BPF=x +CONFIG_BPF_SYSCALL=x +CONFIG_BPF_JIT=x +CONFIG_HAVE_EBPF_JIT=x +CONFIG_CGROUP_BPF=x +CONFIG_EFIVAR_FS=x +CONFIG_EFI_PARTITION=x +# Skipping verity thinsg +#CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=x +#CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING=x +#CONFIG_IMA_ARCH_POLICY=x +# Skipping these because they require expensive tracing to be enabled +#CONFIG_BPF=x +#CONFIG_BPF_SYSCALL=x +#CONFIG_BPF_LSM=x +#CONFIG_DEBUG_INFO_BTF=x +CONFIG_PSI=x +CONFIG_RT_GROUP_SCHED=n +CONFIG_AUDIT=n +CONFIG_SYSFS_DEPRECATED=n +CONFIG_FW_LOADER_USER_HELPER=n + +######## NFS root requirements: +CONFIG_ROOT_NFS=y +CONFIG_NFS_V3=y +CONFIG_NFS_V2=y +CONFIG_NFS_DISABLE_UDP_SUPPORT=y +CONFIG_IP_PNP_DHCP=y +# Skipped because its huge +CONFIG_NFS_V4=n + +######## Docker requirements: +CONFIG_NAMESPACES=x +CONFIG_NET_NS=x +CONFIG_PID_NS=x +CONFIG_IPC_NS=x +CONFIG_UTS_NS=x +CONFIG_CGROUPS=x +CONFIG_CGROUP_CPUACCT=x +CONFIG_CGROUP_DEVICE=x +CONFIG_CGROUP_FREEZER=x +CONFIG_CGROUP_SCHED=x +# We do want this, but it wont exist on our configs without smp +#CONFIG_CPUSETS=x +CONFIG_MEMCG=x +CONFIG_KEYS=x +CONFIG_VETH=x +CONFIG_BRIDGE=x +CONFIG_BRIDGE_NETFILTER=x +CONFIG_IP_NF_FILTER=x +CONFIG_IP_NF_TARGET_MASQUERADE=x +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=x +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=x +CONFIG_NETFILTER_XT_MATCH_IPVS=x +CONFIG_NETFILTER_XT_MARK=x +CONFIG_IP_NF_NAT=x +CONFIG_NF_NAT=x +CONFIG_POSIX_MQUEUE=x + +######## Docker Optional: +CONFIG_USER_NS=x +CONFIG_SECCOMP=x +CONFIG_SECCOMP_FILTER=x +CONFIG_CGROUP_PIDS=x +CONFIG_MEMCG_SWAP=x +CONFIG_EXT4_FS=x +CONFIG_EXT4_FS_POSIX_ACL=x +CONFIG_EXT4_FS_SECURITY=x +CONFIG_BRIDGE_VLAN_FILTERING=x +CONFIG_VXLAN=x +CONFIG_CRYPTO=x +CONFIG_CRYPTO_AEAD=x +CONFIG_CRYPTO_GCM=x +CONFIG_CRYPTO_SEQIV=x +CONFIG_CRYPTO_GHASH=x +CONFIG_XFRM=x +CONFIG_XFRM_USER=x +CONFIG_XFRM_ALGO=x +CONFIG_INET_ESP=x +CONFIG_IPVLAN=x +CONFIG_MACVLAN=x +CONFIG_DUMMY=x +CONFIG_NF_NAT_FTP=x +CONFIG_NF_CONNTRACK_FTP=x +CONFIG_NF_NAT_TFTP=x +CONFIG_NF_CONNTRACK_TFTP=x +CONFIG_BLK_DEV_DM=x +CONFIG_DM_THIN_PROVISIONING=x +CONFIG_OVERLAY_FS=x + +######## Common customer requirements: +CONFIG_CAN_J1939=x +CONFIG_PTP_1588_CLOCK=x +CONFIG_NETFILTER=x +CONFIG_IPV6=y +#Cell modems: +CONFIG_PPP=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPPOE=m +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_USB_NET_CDCETHER=m +CONFIG_USB_NET_CDC_NCM=m +CONFIG_USB_NET_QMI_WWAN=m + +# Needed for WILC3000 correct operation! +# With powersaving enabled, BLE is completely broken, while Wi-Fi will show +# strange hiccups and subtle breakages sometimes. +CONFIG_CFG80211_DEFAULT_PS=n diff --git a/tests/ts_check_configs/min_graphics_config_requirements b/tests/ts_check_configs/min_graphics_config_requirements new file mode 100644 index 0000000000000..3433971232412 --- /dev/null +++ b/tests/ts_check_configs/min_graphics_config_requirements @@ -0,0 +1,49 @@ +# =y required as compiled in +# =m required as a module +# =x either is fine +# =n Must not be included + +######## Driver frameworks required on all hardware: +CONFIG_SPI_SPIDEV=x + +######## Debug options: +CONFIG_LOCKDEP=n +CONFIG_DEBUG_INFO=n +CONFIG_RUNTIME_TESTING_MENU=n +CONFIG_DEBUG_MISC=n +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=n + +######## Systemd requirements: +CONFIG_DEVTMPFS=x +CONFIG_CGROUPS=x +CONFIG_INOTIFY_USER=x +CONFIG_SIGNALFD=x +CONFIG_TIMERFD=x +CONFIG_EPOLL=x +CONFIG_UNIX =x +CONFIG_SYSFS=x +CONFIG_PROC_FS=x +CONFIG_FHANDLE=x + +######## NFS root requirements: +CONFIG_ROOT_NFS=y +CONFIG_NFS_V3=y +CONFIG_NFS_V2=y +CONFIG_NFS_DISABLE_UDP_SUPPORT=y +CONFIG_IP_PNP_DHCP=y +# Skipped because its huge +CONFIG_NFS_V4=n + +# Support very common input devices +CONFIG_HID_MULTITOUCH=x +CONFIG_INPUT_MOUSEDEV=x +CONFIG_HID_GENERIC=x + +# Support PWM backlight +CONFIG_BACKLIGHT_CLASS_DEVICE=x +CONFIG_BACKLIGHT_PWM=x + +# Needed for WILC3000 correct operation! +# With powersaving enabled, BLE is completely broken, while Wi-Fi will show +# strange hiccups and subtle breakages sometimes. +CONFIG_CFG80211_DEFAULT_PS=n diff --git a/tests/ts_check_configs/min_headless_config_requirements b/tests/ts_check_configs/min_headless_config_requirements new file mode 100644 index 0000000000000..17e1be106bdb3 --- /dev/null +++ b/tests/ts_check_configs/min_headless_config_requirements @@ -0,0 +1,40 @@ +# =y required as compiled in +# =m required as a module +# =x either is fine +# =n Must not be included + +######## Driver frameworks required on all hardware: +CONFIG_SPI_SPIDEV=x + +######## Debug options: +CONFIG_LOCKDEP=n +CONFIG_DEBUG_INFO=n +CONFIG_RUNTIME_TESTING_MENU=n +CONFIG_DEBUG_MISC=n +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=n + +######## Systemd requirements: +CONFIG_DEVTMPFS=x +CONFIG_CGROUPS=x +CONFIG_INOTIFY_USER=x +CONFIG_SIGNALFD=x +CONFIG_TIMERFD=x +CONFIG_EPOLL=x +CONFIG_UNIX =x +CONFIG_SYSFS=x +CONFIG_PROC_FS=x +CONFIG_FHANDLE=x + +######## NFS root requirements: +CONFIG_ROOT_NFS=y +CONFIG_NFS_V3=y +CONFIG_NFS_V2=y +CONFIG_NFS_DISABLE_UDP_SUPPORT=y +CONFIG_IP_PNP_DHCP=y +# Skipped because its huge +CONFIG_NFS_V4=n + +# Needed for WILC3000 correct operation! +# With powersaving enabled, BLE is completely broken, while Wi-Fi will show +# strange hiccups and subtle breakages sometimes. +CONFIG_CFG80211_DEFAULT_PS=n diff --git a/tests/ts_check_configs/run_test.sh b/tests/ts_check_configs/run_test.sh new file mode 100755 index 0000000000000..2649b1ae1e7f6 --- /dev/null +++ b/tests/ts_check_configs/run_test.sh @@ -0,0 +1,51 @@ +#!/bin/bash -e + +full_graphics_config_files=( + "tsimx6_defconfig" +) + +min_graphics_config_files=( + "tsimx6_minimal_defconfig" +) + +full_headless_config_files=( + "tsimx6ul_defconfig" + "tsimx28_defconfig" +) + +min_headless_config_files=( + "tsimx6ul_minimal_defconfig" + "tsimx28_minimal_defconfig" +) + +for config_file in "${full_graphics_config_files[@]}"; do + echo "Testing ${config_file}..." + make "${config_file}" > /dev/null 2>&1 + tests/ts_check_configs/config_check \ + tests/ts_check_configs/full_graphics_config_requirements \ + .config +done + +for config_file in "${min_graphics_config_files[@]}"; do + echo "Testing ${config_file}..." + make "${config_file}" > /dev/null 2>&1 + tests/ts_check_configs/config_check \ + tests/ts_check_configs/min_graphics_config_requirements \ + .config +done + +for config_file in "${full_headless_config_files[@]}"; do + echo "Testing ${config_file}..." + make "${config_file}" > /dev/null 2>&1 + tests/ts_check_configs/config_check \ + tests/ts_check_configs/full_headless_config_requirements \ + .config +done + +for config_file in "${min_headless_config_files[@]}"; do + echo "Testing ${config_file}..." + make "${config_file}" > /dev/null 2>&1 + tests/ts_check_configs/config_check \ + tests/ts_check_configs/min_headless_config_requirements \ + .config +done From f51217aa90f0b7c6d74146deb7cea811bde6a7aa Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Wed, 22 Mar 2023 13:09:03 -0700 Subject: [PATCH 056/244] ARM: dts: imx6: USB Eth as ethernet1 to get MAC from U-Boot Done on TS-7990, TS-TPC-8390-4900, and TS-TPC-8950-4900 Signed-off-by: Kris Bahnsen --- .../dts/nxp/imx/imx6qdl-ts4900-ts8390.dtsi | 19 +++++++++++++++++++ .../dts/nxp/imx/imx6qdl-ts4900-ts8950.dtsi | 19 +++++++++++++++++++ arch/arm/boot/dts/nxp/imx/imx6qdl-ts7990.dtsi | 15 +++++++++++++++ 3 files changed, 53 insertions(+) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900-ts8390.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900-ts8390.dtsi index 6c5d37ff5eeb2..d3313c25adf9d 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900-ts8390.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900-ts8390.dtsi @@ -13,6 +13,7 @@ aliases { ethernet0 = &fec; + ethernet1 = ðernet; i2c3 = &i2c3_gpio; }; @@ -307,3 +308,21 @@ &ssi1 { status = "okay"; }; + +&usbh1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + usb1@1 { + compatible = "usb424,9514"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + ethernet: usbether@1 { + compatible = "usb424,ec00"; + reg = <1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900-ts8950.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900-ts8950.dtsi index 8e69b272aaf6e..c1d5f1ca3c0ed 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900-ts8950.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900-ts8950.dtsi @@ -12,6 +12,7 @@ aliases { ethernet0 = &fec; + ethernet1 = ðernet; }; backlight_lvds: backlight-lvds { @@ -331,3 +332,21 @@ fsl,mode = "i2s-slave"; status = "okay"; }; + +&usbh1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + usb1@1 { + compatible = "usb424,9514"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + ethernet: usbether@1 { + compatible = "usb424,ec00"; + reg = <1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7990.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7990.dtsi index e6dbd0698e7e6..547cbd07b0f38 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7990.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7990.dtsi @@ -14,6 +14,7 @@ aliases { ethernet0 = &fec; + ethernet1 = ðernet; }; backlight0: backlight { @@ -671,7 +672,21 @@ }; &usbh1 { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; + + usb1@1 { + compatible = "usb424,9514"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + ethernet: usbether@1 { + compatible = "usb424,ec00"; + reg = <1>; + }; + }; }; &usbotg { From f0b1a0f7afe7f1ae5573076c252115cf77b315a9 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Wed, 22 Mar 2023 17:24:09 -0700 Subject: [PATCH 057/244] ARM: dts: imx28: Move Eth reset to FEC control While other devices seem to be happy with the PHY driver having the reset connected, the i.MX28 seems to still need it connected to the FEC driver for correct operation under all conditions. Signed-off-by: Kris Bahnsen --- arch/arm/boot/dts/nxp/mxs/imx28-ts7400v2.dts | 6 +++--- arch/arm/boot/dts/nxp/mxs/imx28-ts7670.dts | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-ts7400v2.dts b/arch/arm/boot/dts/nxp/mxs/imx28-ts7400v2.dts index dd62764d1340a..47dab8c0c839a 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-ts7400v2.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-ts7400v2.dts @@ -200,6 +200,9 @@ pinctrl-0 = <&mac0_pins>; phy-supply = <®_enet_3v3>; phy-handle = <ðphy0>; + phy-reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; + phy-reset-duration = <26>; + phy-reset-post-delay = <1>; status = "okay"; mdio { @@ -208,9 +211,6 @@ ethphy0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; - reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; - reset-assert-us = <26000>; - reset-deassert-us = <100>; reg = <0>; }; }; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-ts7670.dts b/arch/arm/boot/dts/nxp/mxs/imx28-ts7670.dts index 27f7ede337eff..0f3719ebd3892 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-ts7670.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-ts7670.dts @@ -226,6 +226,9 @@ pinctrl-0 = <&mac0_pins>; phy-supply = <®_enet_3v3>; phy-handle = <ðphy0>; + phy-reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; + phy-reset-duration = <26>; + phy-reset-post-delay = <1>; status = "okay"; mdio { @@ -234,9 +237,6 @@ ethphy0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; - reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; - reset-assert-us = <26000>; - reset-deassert-us = <100>; reg = <0>; }; }; From d84b42440c0e08a8a01fde6290cab5456e9e19dd Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Fri, 24 Mar 2023 07:57:58 -0700 Subject: [PATCH 058/244] ARM: dts: imx28_minimal: Add pps-gpio support Signed-off-by: Kris Bahnsen --- arch/arm/configs/tsimx28_minimal_defconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/configs/tsimx28_minimal_defconfig b/arch/arm/configs/tsimx28_minimal_defconfig index 81351c73463f8..5872c6b91e14f 100644 --- a/arch/arm/configs/tsimx28_minimal_defconfig +++ b/arch/arm/configs/tsimx28_minimal_defconfig @@ -163,7 +163,8 @@ CONFIG_SPI=y CONFIG_SPI_GPIO=m CONFIG_SPI_MXS=y CONFIG_SPI_SPIDEV=m -CONFIG_PPS=y +CONFIG_PPS=m +CONFIG_PPS_CLIENT_GPIO=m # CONFIG_PTP_1588_CLOCK is not set CONFIG_GPIO_SYSFS=y CONFIG_HWMON=m From d47746fecdecba2e84f036ec45d77fbb41e752c1 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Fri, 24 Mar 2023 12:08:31 -0700 Subject: [PATCH 059/244] ARM: configs: ts: Remove No longer used with each platform config split out Signed-off-by: Kris Bahnsen --- arch/arm/configs/ts_defconfig | 1698 --------------------------------- 1 file changed, 1698 deletions(-) delete mode 100644 arch/arm/configs/ts_defconfig diff --git a/arch/arm/configs/ts_defconfig b/arch/arm/configs/ts_defconfig deleted file mode 100644 index 7fcc1341601f8..0000000000000 --- a/arch/arm/configs/ts_defconfig +++ /dev/null @@ -1,1698 +0,0 @@ -CONFIG_KERNEL_XZ=y -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -CONFIG_USELIB=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_PREEMPT=y -CONFIG_IKCONFIG=m -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=18 -CONFIG_CGROUPS=y -CONFIG_MEMCG=y -CONFIG_BLK_CGROUP=y -CONFIG_CGROUP_SCHED=y -CONFIG_CFS_BANDWIDTH=y -CONFIG_RT_GROUP_SCHED=y -CONFIG_CGROUP_PIDS=y -CONFIG_CGROUP_RDMA=y -CONFIG_CGROUP_FREEZER=y -CONFIG_CPUSETS=y -# CONFIG_PROC_PID_CPUSET is not set -CONFIG_CGROUP_DEVICE=y -CONFIG_CGROUP_CPUACCT=y -CONFIG_CGROUP_PERF=y -CONFIG_CGROUP_BPF=y -CONFIG_CGROUP_DEBUG=y -CONFIG_NAMESPACES=y -CONFIG_USER_NS=y -CONFIG_CHECKPOINT_RESTORE=y -CONFIG_RELAY=y -CONFIG_BLK_DEV_INITRD=y -# CONFIG_RD_LZMA is not set -# CONFIG_RD_LZO is not set -# CONFIG_RD_LZ4 is not set -# CONFIG_RD_ZSTD is not set -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_BPF_SYSCALL=y -CONFIG_EMBEDDED=y -CONFIG_PERF_EVENTS=y -# CONFIG_COMPAT_BRK is not set -CONFIG_ARCH_MXC=y -CONFIG_SOC_IMX6Q=y -CONFIG_SOC_IMX6UL=y -CONFIG_SMP=y -CONFIG_HAVE_ARM_ARCH_TIMER=y -CONFIG_ARM_PSCI=y -CONFIG_HZ_1000=y -CONFIG_HIGHMEM=y -CONFIG_FORCE_MAX_ZONEORDER=14 -CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" -CONFIG_KEXEC=y -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y -CONFIG_ARM_IMX6Q_CPUFREQ=y -CONFIG_CPU_IDLE=y -CONFIG_CPU_IDLE_GOV_MENU=y -CONFIG_CPU_IDLE_GOV_TEO=y -CONFIG_ARM_CPUIDLE=y -CONFIG_ARM_PSCI_CPUIDLE=y -CONFIG_VFP=y -CONFIG_NEON=y -CONFIG_PM_DEBUG=y -CONFIG_PM_TEST_SUSPEND=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -CONFIG_MODULE_COMPRESS=y -CONFIG_MODULE_COMPRESS_XZ=y -CONFIG_BLK_DEV_INTEGRITY=y -CONFIG_BLK_DEV_THROTTLING=y -CONFIG_BLK_CMDLINE_PARSER=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_BINFMT_MISC=y -# CONFIG_COREDUMP is not set -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_PACKET_DIAG=m -CONFIG_UNIX=y -CONFIG_UNIX_DIAG=m -CONFIG_TLS=m -CONFIG_TLS_DEVICE=y -CONFIG_XFRM_USER=m -CONFIG_XFRM_SUB_POLICY=y -CONFIG_XFRM_STATISTICS=y -CONFIG_NET_KEY=m -CONFIG_NET_KEY_MIGRATE=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_ADVANCED_ROUTER=y -CONFIG_IP_FIB_TRIE_STATS=y -CONFIG_IP_MULTIPLE_TABLES=y -CONFIG_IP_ROUTE_MULTIPATH=y -CONFIG_IP_ROUTE_VERBOSE=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -CONFIG_NET_IPIP=m -CONFIG_NET_IPGRE_DEMUX=m -CONFIG_NET_IPGRE=m -CONFIG_NET_IPGRE_BROADCAST=y -CONFIG_IP_MROUTE=y -CONFIG_IP_MROUTE_MULTIPLE_TABLES=y -CONFIG_IP_PIMSM_V1=y -CONFIG_IP_PIMSM_V2=y -CONFIG_NET_IPVTI=m -CONFIG_NET_FOU_IP_TUNNELS=y -CONFIG_INET_AH=m -CONFIG_INET_ESP=m -CONFIG_INET_IPCOMP=m -CONFIG_INET_UDP_DIAG=m -CONFIG_INET_DIAG_DESTROY=y -CONFIG_TCP_CONG_ADVANCED=y -CONFIG_TCP_CONG_HSTCP=m -CONFIG_TCP_CONG_HYBLA=m -CONFIG_TCP_CONG_NV=m -CONFIG_TCP_CONG_SCALABLE=m -CONFIG_TCP_CONG_LP=m -CONFIG_TCP_CONG_VENO=m -CONFIG_TCP_CONG_YEAH=m -CONFIG_TCP_CONG_ILLINOIS=m -CONFIG_TCP_CONG_DCTCP=m -CONFIG_TCP_CONG_CDG=m -CONFIG_TCP_CONG_BBR=m -CONFIG_TCP_MD5SIG=y -CONFIG_IPV6_ROUTER_PREF=y -CONFIG_IPV6_ROUTE_INFO=y -CONFIG_IPV6_OPTIMISTIC_DAD=y -CONFIG_INET6_AH=m -CONFIG_INET6_ESP=m -CONFIG_INET6_IPCOMP=m -CONFIG_IPV6_MIP6=m -CONFIG_IPV6_ILA=m -CONFIG_IPV6_VTI=m -CONFIG_IPV6_SIT=m -CONFIG_IPV6_SIT_6RD=y -CONFIG_IPV6_GRE=m -CONFIG_IPV6_MULTIPLE_TABLES=y -CONFIG_IPV6_SUBTREES=y -CONFIG_IPV6_MROUTE=y -CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y -CONFIG_IPV6_PIMSM_V2=y -CONFIG_NETWORK_SECMARK=y -CONFIG_NETWORK_PHY_TIMESTAMPING=y -CONFIG_NETFILTER=y -CONFIG_BRIDGE_NETFILTER=m -CONFIG_NF_CONNTRACK=m -CONFIG_NF_CONNTRACK_ZONES=y -CONFIG_NF_CONNTRACK_PROCFS=y -CONFIG_NF_CONNTRACK_EVENTS=y -CONFIG_NF_CONNTRACK_TIMEOUT=y -CONFIG_NF_CONNTRACK_TIMESTAMP=y -CONFIG_NF_CONNTRACK_AMANDA=m -CONFIG_NF_CONNTRACK_FTP=m -CONFIG_NF_CONNTRACK_H323=m -CONFIG_NF_CONNTRACK_IRC=m -CONFIG_NF_CONNTRACK_NETBIOS_NS=m -CONFIG_NF_CONNTRACK_SNMP=m -CONFIG_NF_CONNTRACK_PPTP=m -CONFIG_NF_CONNTRACK_SANE=m -CONFIG_NF_CONNTRACK_SIP=m -CONFIG_NF_CONNTRACK_TFTP=m -CONFIG_NF_CT_NETLINK=m -CONFIG_NF_CT_NETLINK_TIMEOUT=m -CONFIG_NETFILTER_NETLINK_GLUE_CT=y -CONFIG_NF_TABLES=m -CONFIG_NFT_NUMGEN=m -CONFIG_NFT_CT=m -CONFIG_NFT_COUNTER=m -CONFIG_NFT_LOG=m -CONFIG_NFT_LIMIT=m -CONFIG_NFT_MASQ=m -CONFIG_NFT_REDIR=m -CONFIG_NFT_QUEUE=m -CONFIG_NFT_QUOTA=m -CONFIG_NFT_REJECT=m -CONFIG_NFT_COMPAT=m -CONFIG_NFT_HASH=m -CONFIG_NETFILTER_XT_SET=m -CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m -CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m -CONFIG_NETFILTER_XT_TARGET_CONNMARK=m -CONFIG_NETFILTER_XT_TARGET_DSCP=m -CONFIG_NETFILTER_XT_TARGET_HMARK=m -CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m -CONFIG_NETFILTER_XT_TARGET_LED=m -CONFIG_NETFILTER_XT_TARGET_LOG=m -CONFIG_NETFILTER_XT_TARGET_MARK=m -CONFIG_NETFILTER_XT_TARGET_NFLOG=m -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m -CONFIG_NETFILTER_XT_TARGET_NOTRACK=m -CONFIG_NETFILTER_XT_TARGET_TEE=m -CONFIG_NETFILTER_XT_TARGET_TPROXY=m -CONFIG_NETFILTER_XT_TARGET_TRACE=m -CONFIG_NETFILTER_XT_TARGET_TCPMSS=m -CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m -CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m -CONFIG_NETFILTER_XT_MATCH_BPF=m -CONFIG_NETFILTER_XT_MATCH_CGROUP=m -CONFIG_NETFILTER_XT_MATCH_CLUSTER=m -CONFIG_NETFILTER_XT_MATCH_COMMENT=m -CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m -CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m -CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m -CONFIG_NETFILTER_XT_MATCH_CONNMARK=m -CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m -CONFIG_NETFILTER_XT_MATCH_CPU=m -CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m -CONFIG_NETFILTER_XT_MATCH_DSCP=m -CONFIG_NETFILTER_XT_MATCH_ESP=m -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m -CONFIG_NETFILTER_XT_MATCH_HELPER=m -CONFIG_NETFILTER_XT_MATCH_IPCOMP=m -CONFIG_NETFILTER_XT_MATCH_IPRANGE=m -CONFIG_NETFILTER_XT_MATCH_IPVS=m -CONFIG_NETFILTER_XT_MATCH_LENGTH=m -CONFIG_NETFILTER_XT_MATCH_LIMIT=m -CONFIG_NETFILTER_XT_MATCH_MAC=m -CONFIG_NETFILTER_XT_MATCH_MARK=m -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m -CONFIG_NETFILTER_XT_MATCH_NFACCT=m -CONFIG_NETFILTER_XT_MATCH_OSF=m -CONFIG_NETFILTER_XT_MATCH_OWNER=m -CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m -CONFIG_NETFILTER_XT_MATCH_QUOTA=m -CONFIG_NETFILTER_XT_MATCH_RATEEST=m -CONFIG_NETFILTER_XT_MATCH_REALM=m -CONFIG_NETFILTER_XT_MATCH_RECENT=m -CONFIG_NETFILTER_XT_MATCH_SOCKET=m -CONFIG_NETFILTER_XT_MATCH_STATE=m -CONFIG_NETFILTER_XT_MATCH_STATISTIC=m -CONFIG_NETFILTER_XT_MATCH_STRING=m -CONFIG_NETFILTER_XT_MATCH_TCPMSS=m -CONFIG_NETFILTER_XT_MATCH_TIME=m -CONFIG_NETFILTER_XT_MATCH_U32=m -CONFIG_IP_SET=m -CONFIG_IP_SET_BITMAP_IP=m -CONFIG_IP_SET_BITMAP_IPMAC=m -CONFIG_IP_SET_BITMAP_PORT=m -CONFIG_IP_SET_HASH_IP=m -CONFIG_IP_SET_HASH_IPMARK=m -CONFIG_IP_SET_HASH_IPPORT=m -CONFIG_IP_SET_HASH_IPPORTIP=m -CONFIG_IP_SET_HASH_IPPORTNET=m -CONFIG_IP_SET_HASH_MAC=m -CONFIG_IP_SET_HASH_NETPORTNET=m -CONFIG_IP_SET_HASH_NET=m -CONFIG_IP_SET_HASH_NETNET=m -CONFIG_IP_SET_HASH_NETPORT=m -CONFIG_IP_SET_HASH_NETIFACE=m -CONFIG_IP_SET_LIST_SET=m -CONFIG_IP_VS=m -CONFIG_IP_VS_IPV6=y -CONFIG_IP_VS_PROTO_TCP=y -CONFIG_IP_VS_PROTO_UDP=y -CONFIG_IP_VS_PROTO_ESP=y -CONFIG_IP_VS_PROTO_AH=y -CONFIG_IP_VS_PROTO_SCTP=y -CONFIG_IP_VS_RR=m -CONFIG_IP_VS_WRR=m -CONFIG_IP_VS_LC=m -CONFIG_IP_VS_WLC=m -CONFIG_IP_VS_FO=m -CONFIG_IP_VS_OVF=m -CONFIG_IP_VS_LBLC=m -CONFIG_IP_VS_LBLCR=m -CONFIG_IP_VS_DH=m -CONFIG_IP_VS_SH=m -CONFIG_IP_VS_SED=m -CONFIG_IP_VS_NQ=m -CONFIG_IP_VS_FTP=m -CONFIG_IP_VS_PE_SIP=m -CONFIG_NF_LOG_ARP=m -CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_AH=m -CONFIG_IP_NF_MATCH_ECN=m -CONFIG_IP_NF_MATCH_RPFILTER=m -CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_FILTER=m -CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_TARGET_SYNPROXY=m -CONFIG_IP_NF_NAT=m -CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_NETMAP=m -CONFIG_IP_NF_TARGET_REDIRECT=m -CONFIG_IP_NF_MANGLE=m -CONFIG_IP_NF_TARGET_CLUSTERIP=m -CONFIG_IP_NF_TARGET_ECN=m -CONFIG_IP_NF_TARGET_TTL=m -CONFIG_IP_NF_RAW=m -CONFIG_IP_NF_ARPTABLES=m -CONFIG_IP_NF_ARPFILTER=m -CONFIG_IP_NF_ARP_MANGLE=m -CONFIG_IP6_NF_IPTABLES=m -CONFIG_IP6_NF_MATCH_AH=m -CONFIG_IP6_NF_MATCH_EUI64=m -CONFIG_IP6_NF_MATCH_FRAG=m -CONFIG_IP6_NF_MATCH_OPTS=m -CONFIG_IP6_NF_MATCH_HL=m -CONFIG_IP6_NF_MATCH_IPV6HEADER=m -CONFIG_IP6_NF_MATCH_MH=m -CONFIG_IP6_NF_MATCH_RPFILTER=m -CONFIG_IP6_NF_MATCH_RT=m -CONFIG_IP6_NF_MATCH_SRH=m -CONFIG_IP6_NF_TARGET_HL=m -CONFIG_IP6_NF_FILTER=m -CONFIG_IP6_NF_TARGET_REJECT=m -CONFIG_IP6_NF_TARGET_SYNPROXY=m -CONFIG_IP6_NF_MANGLE=m -CONFIG_IP6_NF_RAW=m -CONFIG_IP6_NF_NAT=m -CONFIG_IP6_NF_TARGET_MASQUERADE=m -CONFIG_IP6_NF_TARGET_NPT=m -CONFIG_DECNET_NF_GRABULATOR=m -CONFIG_NF_TABLES_BRIDGE=m -CONFIG_NFT_BRIDGE_META=m -CONFIG_NF_LOG_BRIDGE=m -CONFIG_BRIDGE_NF_EBTABLES=m -CONFIG_BRIDGE_EBT_BROUTE=m -CONFIG_BRIDGE_EBT_T_FILTER=m -CONFIG_BRIDGE_EBT_T_NAT=m -CONFIG_BRIDGE_EBT_802_3=m -CONFIG_BRIDGE_EBT_AMONG=m -CONFIG_BRIDGE_EBT_ARP=m -CONFIG_BRIDGE_EBT_IP=m -CONFIG_BRIDGE_EBT_IP6=m -CONFIG_BRIDGE_EBT_LIMIT=m -CONFIG_BRIDGE_EBT_MARK=m -CONFIG_BRIDGE_EBT_PKTTYPE=m -CONFIG_BRIDGE_EBT_STP=m -CONFIG_BRIDGE_EBT_VLAN=m -CONFIG_BRIDGE_EBT_ARPREPLY=m -CONFIG_BRIDGE_EBT_DNAT=m -CONFIG_BRIDGE_EBT_MARK_T=m -CONFIG_BRIDGE_EBT_REDIRECT=m -CONFIG_BRIDGE_EBT_SNAT=m -CONFIG_BRIDGE_EBT_LOG=m -CONFIG_BRIDGE_EBT_NFLOG=m -CONFIG_IP_DCCP=m -CONFIG_IP_SCTP=m -CONFIG_RDS=m -CONFIG_RDS_TCP=m -CONFIG_TIPC=m -CONFIG_ATM=m -CONFIG_ATM_CLIP=m -CONFIG_ATM_LANE=m -CONFIG_ATM_MPOA=m -CONFIG_ATM_BR2684=m -CONFIG_L2TP=m -CONFIG_L2TP_V3=y -CONFIG_L2TP_IP=m -CONFIG_L2TP_ETH=m -CONFIG_BRIDGE=m -CONFIG_BRIDGE_VLAN_FILTERING=y -CONFIG_NET_DSA=m -CONFIG_VLAN_8021Q=m -CONFIG_VLAN_8021Q_GVRP=y -CONFIG_VLAN_8021Q_MVRP=y -CONFIG_DECNET=m -CONFIG_DECNET_ROUTER=y -CONFIG_LLC2=m -CONFIG_ATALK=m -CONFIG_DEV_APPLETALK=m -CONFIG_IPDDP=m -CONFIG_IPDDP_ENCAP=y -CONFIG_X25=m -CONFIG_LAPB=m -CONFIG_PHONET=m -CONFIG_6LOWPAN=m -CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m -CONFIG_6LOWPAN_GHC_UDP=m -CONFIG_6LOWPAN_GHC_ICMPV6=m -CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m -CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m -CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m -CONFIG_IEEE802154=m -CONFIG_IEEE802154_6LOWPAN=m -CONFIG_MAC802154=m -CONFIG_NET_SCHED=y -CONFIG_NET_SCH_CBQ=m -CONFIG_NET_SCH_HTB=m -CONFIG_NET_SCH_HFSC=m -CONFIG_NET_SCH_ATM=m -CONFIG_NET_SCH_PRIO=m -CONFIG_NET_SCH_MULTIQ=m -CONFIG_NET_SCH_RED=m -CONFIG_NET_SCH_SFB=m -CONFIG_NET_SCH_SFQ=m -CONFIG_NET_SCH_TEQL=m -CONFIG_NET_SCH_TBF=m -CONFIG_NET_SCH_GRED=m -CONFIG_NET_SCH_DSMARK=m -CONFIG_NET_SCH_NETEM=m -CONFIG_NET_SCH_DRR=m -CONFIG_NET_SCH_MQPRIO=m -CONFIG_NET_SCH_CHOKE=m -CONFIG_NET_SCH_QFQ=m -CONFIG_NET_SCH_CODEL=m -CONFIG_NET_SCH_FQ_CODEL=m -CONFIG_NET_SCH_FQ=m -CONFIG_NET_SCH_HHF=m -CONFIG_NET_SCH_PIE=m -CONFIG_NET_SCH_INGRESS=m -CONFIG_NET_SCH_PLUG=m -CONFIG_NET_CLS_BASIC=m -CONFIG_NET_CLS_TCINDEX=m -CONFIG_NET_CLS_ROUTE4=m -CONFIG_NET_CLS_FW=m -CONFIG_NET_CLS_U32=m -CONFIG_CLS_U32_PERF=y -CONFIG_CLS_U32_MARK=y -CONFIG_NET_CLS_RSVP=m -CONFIG_NET_CLS_RSVP6=m -CONFIG_NET_CLS_FLOW=m -CONFIG_NET_CLS_CGROUP=m -CONFIG_NET_CLS_BPF=m -CONFIG_NET_CLS_FLOWER=m -CONFIG_NET_CLS_MATCHALL=m -CONFIG_NET_EMATCH=y -CONFIG_NET_EMATCH_CMP=m -CONFIG_NET_EMATCH_NBYTE=m -CONFIG_NET_EMATCH_U32=m -CONFIG_NET_EMATCH_META=m -CONFIG_NET_EMATCH_TEXT=m -CONFIG_NET_EMATCH_CANID=m -CONFIG_NET_EMATCH_IPSET=m -CONFIG_NET_CLS_ACT=y -CONFIG_NET_ACT_POLICE=m -CONFIG_NET_ACT_GACT=m -CONFIG_GACT_PROB=y -CONFIG_NET_ACT_MIRRED=m -CONFIG_NET_ACT_IPT=m -CONFIG_NET_ACT_NAT=m -CONFIG_NET_ACT_PEDIT=m -CONFIG_NET_ACT_SIMP=m -CONFIG_NET_ACT_SKBEDIT=m -CONFIG_NET_ACT_CSUM=m -CONFIG_NET_ACT_VLAN=m -CONFIG_NET_ACT_BPF=m -CONFIG_NET_ACT_CONNMARK=m -CONFIG_NET_ACT_SKBMOD=m -CONFIG_NET_ACT_IFE=m -CONFIG_NET_ACT_TUNNEL_KEY=m -CONFIG_DCB=y -CONFIG_DNS_RESOLVER=y -CONFIG_BATMAN_ADV=m -CONFIG_BATMAN_ADV_NC=y -CONFIG_BATMAN_ADV_DEBUG=y -CONFIG_OPENVSWITCH=m -CONFIG_VSOCKETS=m -CONFIG_NETLINK_DIAG=m -CONFIG_MPLS_ROUTING=m -CONFIG_MPLS_IPTUNNEL=m -CONFIG_HSR=m -CONFIG_NET_NCSI=y -CONFIG_CGROUP_NET_PRIO=y -CONFIG_BPF_JIT=y -CONFIG_CAN=y -CONFIG_CAN_J1939=m -CONFIG_CAN_ISOTP=m -CONFIG_CAN_VCAN=m -CONFIG_CAN_VXCAN=m -CONFIG_CAN_SLCAN=m -CONFIG_CAN_FLEXCAN=y -CONFIG_CAN_8DEV_USB=m -CONFIG_CAN_EMS_USB=m -CONFIG_CAN_ESD_USB2=m -CONFIG_CAN_GS_USB=m -CONFIG_CAN_KVASER_USB=m -CONFIG_CAN_PEAK_USB=m -CONFIG_CAN_UCAN=m -CONFIG_BT=m -CONFIG_BT_RFCOMM=y -CONFIG_BT_RFCOMM_TTY=y -CONFIG_BT_BNEP=y -CONFIG_BT_BNEP_MC_FILTER=y -CONFIG_BT_BNEP_PROTO_FILTER=y -CONFIG_BT_HIDP=y -CONFIG_BT_HS=y -CONFIG_BT_6LOWPAN=m -CONFIG_BT_LEDS=y -CONFIG_BT_HCIBTUSB=m -CONFIG_BT_HCIBTUSB_MTK=y -CONFIG_BT_HCIUART=m -CONFIG_BT_HCIUART_NOKIA=m -CONFIG_BT_HCIUART_BCSP=y -CONFIG_BT_HCIUART_ATH3K=y -CONFIG_BT_HCIUART_LL=y -CONFIG_BT_HCIUART_INTEL=y -CONFIG_BT_HCIUART_BCM=y -CONFIG_BT_HCIUART_RTL=y -CONFIG_BT_HCIUART_QCA=y -CONFIG_BT_HCIUART_AG6XX=y -CONFIG_BT_HCIUART_MRVL=y -CONFIG_BT_HCIBCM203X=m -CONFIG_BT_HCIBPA10X=m -CONFIG_BT_HCIBFUSB=m -CONFIG_BT_HCIVHCI=m -CONFIG_BT_MRVL=m -CONFIG_BT_ATH3K=m -CONFIG_CFG80211=m -# CONFIG_CFG80211_DEFAULT_PS is not set -CONFIG_MAC80211=m -CONFIG_MAC80211_MESH=y -CONFIG_MAC80211_MESSAGE_TRACING=y -CONFIG_RFKILL=m -CONFIG_RFKILL_INPUT=y -CONFIG_RFKILL_GPIO=m -CONFIG_CAIF=m -CONFIG_CAIF_USB=m -CONFIG_NFC=m -CONFIG_NFC_DIGITAL=m -CONFIG_NFC_NCI=m -CONFIG_NFC_NCI_SPI=m -CONFIG_NFC_NCI_UART=m -CONFIG_NFC_HCI=m -CONFIG_NFC_SHDLC=y -CONFIG_NFC_TRF7970A=m -CONFIG_NFC_SIM=m -CONFIG_NFC_PORT100=m -CONFIG_NFC_FDP=m -CONFIG_NFC_FDP_I2C=m -CONFIG_NFC_PN544_I2C=m -CONFIG_NFC_PN533_USB=m -CONFIG_NFC_PN533_I2C=m -CONFIG_NFC_PN532_UART=m -CONFIG_NFC_MICROREAD_I2C=m -CONFIG_NFC_MRVL_USB=m -CONFIG_NFC_MRVL_UART=m -CONFIG_NFC_MRVL_I2C=m -CONFIG_NFC_MRVL_SPI=m -CONFIG_NFC_ST21NFCA_I2C=m -CONFIG_NFC_ST_NCI_I2C=m -CONFIG_NFC_ST_NCI_SPI=m -CONFIG_NFC_NXP_NCI=m -CONFIG_NFC_NXP_NCI_I2C=m -CONFIG_NFC_S3FWRN5_I2C=m -CONFIG_NFC_ST95HF=m -CONFIG_PCI=y -CONFIG_PCI_MSI=y -CONFIG_PCI_IMX6=y -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -# CONFIG_STANDALONE is not set -CONFIG_EXTRA_FIRMWARE="imx/sdma/sdma-imx6q.bin" -CONFIG_EXTRA_FIRMWARE_DIR="firmware" -CONFIG_FW_LOADER_USER_HELPER=y -CONFIG_IMX_WEIM=y -CONFIG_CONNECTOR=y -CONFIG_GNSS=m -CONFIG_GNSS_MTK_SERIAL=m -CONFIG_GNSS_SIRF_SERIAL=m -CONFIG_GNSS_UBX_SERIAL=m -CONFIG_MTD=m -CONFIG_MTD_CMDLINE_PARTS=m -CONFIG_MTD_BLOCK=m -CONFIG_MTD_CFI=m -CONFIG_MTD_JEDECPROBE=m -CONFIG_MTD_CFI_INTELEXT=m -CONFIG_MTD_CFI_AMDSTD=m -CONFIG_MTD_CFI_STAA=m -CONFIG_MTD_DATAFLASH=m -CONFIG_MTD_MCHP23K256=m -CONFIG_MTD_SST25L=m -CONFIG_MTD_SPI_NOR=m -CONFIG_OF_OVERLAY=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_NBD=m -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=65536 -CONFIG_ATA_OVER_ETH=m -CONFIG_BLK_DEV_NVME=m -CONFIG_NVME_TARGET=m -CONFIG_NVME_TARGET_LOOP=m -CONFIG_C2PORT=m -CONFIG_EEPROM_AT24=y -CONFIG_EEPROM_AT25=y -CONFIG_TI_ST=m -CONFIG_RAID_ATTRS=m -# CONFIG_SCSI_PROC_FS is not set -CONFIG_BLK_DEV_SD=y -CONFIG_CHR_DEV_ST=m -CONFIG_BLK_DEV_SR=m -CONFIG_CHR_DEV_SG=m -CONFIG_SCSI_LOGGING=y -CONFIG_SCSI_SCAN_ASYNC=y -CONFIG_SCSI_FC_ATTRS=m -CONFIG_SCSI_ISCSI_ATTRS=m -CONFIG_SCSI_SAS_LIBSAS=m -CONFIG_SCSI_SRP_ATTRS=m -# CONFIG_SCSI_LOWLEVEL is not set -CONFIG_ATA=y -CONFIG_SATA_AHCI_PLATFORM=y -CONFIG_AHCI_IMX=y -CONFIG_PATA_IMX=y -CONFIG_MD=y -CONFIG_MD_LINEAR=m -CONFIG_MD_MULTIPATH=m -CONFIG_BCACHE=m -CONFIG_BLK_DEV_DM=y -CONFIG_DM_CRYPT=y -CONFIG_DM_SNAPSHOT=y -CONFIG_DM_THIN_PROVISIONING=m -CONFIG_DM_CACHE=m -CONFIG_DM_ERA=m -CONFIG_DM_MIRROR=m -CONFIG_DM_LOG_USERSPACE=m -CONFIG_DM_RAID=m -CONFIG_DM_ZERO=m -CONFIG_DM_MULTIPATH=m -CONFIG_DM_MULTIPATH_QL=m -CONFIG_DM_MULTIPATH_ST=m -CONFIG_DM_DELAY=m -CONFIG_DM_FLAKEY=m -CONFIG_DM_VERITY=m -CONFIG_DM_SWITCH=m -CONFIG_DM_LOG_WRITES=m -CONFIG_NETDEVICES=y -CONFIG_BONDING=m -CONFIG_DUMMY=m -CONFIG_WIREGUARD=m -CONFIG_EQUALIZER=m -CONFIG_IFB=m -CONFIG_NET_TEAM=m -CONFIG_NET_TEAM_MODE_BROADCAST=m -CONFIG_NET_TEAM_MODE_ROUNDROBIN=m -CONFIG_NET_TEAM_MODE_RANDOM=m -CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m -CONFIG_NET_TEAM_MODE_LOADBALANCE=m -CONFIG_MACVLAN=m -CONFIG_MACVTAP=m -CONFIG_IPVLAN=m -CONFIG_VXLAN=m -CONFIG_GENEVE=m -CONFIG_GTP=m -CONFIG_MACSEC=m -CONFIG_NETCONSOLE=m -CONFIG_NETCONSOLE_DYNAMIC=y -CONFIG_TUN=m -CONFIG_VETH=m -CONFIG_NLMON=m -CONFIG_NET_VRF=m -# CONFIG_ATM_DRIVERS is not set -CONFIG_NET_DSA_MV88E6060=m -CONFIG_NET_DSA_MV88E6XXX=m -# CONFIG_NET_VENDOR_3COM is not set -# CONFIG_NET_VENDOR_ADAPTEC is not set -# CONFIG_NET_VENDOR_AGERE is not set -# CONFIG_NET_VENDOR_ALACRITECH is not set -# CONFIG_NET_VENDOR_ALTEON is not set -# CONFIG_NET_VENDOR_AMAZON is not set -# CONFIG_NET_VENDOR_AMD is not set -# CONFIG_NET_VENDOR_AQUANTIA is not set -# CONFIG_NET_VENDOR_ARC is not set -CONFIG_ATL2=m -CONFIG_ATL1=m -CONFIG_ATL1E=m -CONFIG_ATL1C=m -CONFIG_ALX=m -# CONFIG_NET_VENDOR_AURORA is not set -# CONFIG_NET_VENDOR_BROADCOM is not set -# CONFIG_NET_VENDOR_BROCADE is not set -# CONFIG_NET_VENDOR_CADENCE is not set -# CONFIG_NET_VENDOR_CAVIUM is not set -# CONFIG_NET_VENDOR_CHELSIO is not set -# CONFIG_NET_VENDOR_CIRRUS is not set -# CONFIG_NET_VENDOR_CISCO is not set -# CONFIG_NET_VENDOR_CORTINA is not set -# CONFIG_NET_VENDOR_DEC is not set -# CONFIG_NET_VENDOR_DLINK is not set -# CONFIG_NET_VENDOR_EMULEX is not set -# CONFIG_NET_VENDOR_EZCHIP is not set -# CONFIG_NET_VENDOR_FARADAY is not set -# CONFIG_NET_VENDOR_GOOGLE is not set -# CONFIG_NET_VENDOR_HISILICON is not set -# CONFIG_NET_VENDOR_HUAWEI is not set -# CONFIG_NET_VENDOR_I825XX is not set -CONFIG_IGB=y -# CONFIG_NET_VENDOR_MARVELL is not set -# CONFIG_NET_VENDOR_MELLANOX is not set -# CONFIG_NET_VENDOR_MICREL is not set -CONFIG_LAN743X=m -# CONFIG_NET_VENDOR_MICROSEMI is not set -# CONFIG_NET_VENDOR_MYRI is not set -# CONFIG_NET_VENDOR_NATSEMI is not set -# CONFIG_NET_VENDOR_NETERION is not set -# CONFIG_NET_VENDOR_NETRONOME is not set -# CONFIG_NET_VENDOR_NI is not set -# CONFIG_NET_VENDOR_NVIDIA is not set -# CONFIG_NET_VENDOR_OKI is not set -CONFIG_ETHOC=m -# CONFIG_NET_VENDOR_PACKET_ENGINES is not set -# CONFIG_NET_VENDOR_PENSANDO is not set -# CONFIG_NET_VENDOR_QLOGIC is not set -CONFIG_QCA7000_SPI=m -CONFIG_QCA7000_UART=m -# CONFIG_NET_VENDOR_RDC is not set -CONFIG_8139CP=m -CONFIG_8139TOO=m -CONFIG_R8169=m -# CONFIG_NET_VENDOR_RENESAS is not set -# CONFIG_NET_VENDOR_ROCKER is not set -# CONFIG_NET_VENDOR_SAMSUNG is not set -# CONFIG_NET_VENDOR_SEEQ is not set -# CONFIG_NET_VENDOR_SOLARFLARE is not set -# CONFIG_NET_VENDOR_SILAN is not set -# CONFIG_NET_VENDOR_SIS is not set -CONFIG_SMC91X=m -CONFIG_EPIC100=m -CONFIG_SMC911X=m -CONFIG_SMSC911X=m -CONFIG_SMSC9420=m -# CONFIG_NET_VENDOR_SOCIONEXT is not set -# CONFIG_NET_VENDOR_STMICRO is not set -# CONFIG_NET_VENDOR_SUN is not set -# CONFIG_NET_VENDOR_SYNOPSYS is not set -# CONFIG_NET_VENDOR_TEHUTI is not set -# CONFIG_NET_VENDOR_TI is not set -# CONFIG_NET_VENDOR_VIA is not set -# CONFIG_NET_VENDOR_WIZNET is not set -CONFIG_XILINX_AXI_EMAC=m -CONFIG_XILINX_LL_TEMAC=m -CONFIG_FDDI=m -CONFIG_DEFXX=m -CONFIG_SKFP=m -CONFIG_MICREL_PHY=y -CONFIG_MICROCHIP_PHY=y -CONFIG_REALTEK_PHY=y -CONFIG_SMSC_PHY=y -CONFIG_MDIO_BITBANG=y -CONFIG_MDIO_GPIO=y -CONFIG_PPP=m -CONFIG_PPP_BSDCOMP=m -CONFIG_PPP_DEFLATE=m -CONFIG_PPP_FILTER=y -CONFIG_PPP_MPPE=m -CONFIG_PPPOATM=m -CONFIG_PPPOE=m -CONFIG_PPTP=m -CONFIG_PPPOL2TP=m -CONFIG_PPP_ASYNC=m -CONFIG_PPP_SYNC_TTY=m -CONFIG_SLIP=m -CONFIG_SLIP_COMPRESSED=y -CONFIG_SLIP_SMART=y -CONFIG_SLIP_MODE_SLIP6=y -CONFIG_USB_CATC=m -CONFIG_USB_KAWETH=m -CONFIG_USB_PEGASUS=m -CONFIG_USB_RTL8150=m -CONFIG_USB_RTL8152=m -CONFIG_USB_LAN78XX=m -CONFIG_USB_NET_CDC_EEM=m -CONFIG_USB_NET_HUAWEI_CDC_NCM=m -CONFIG_USB_NET_CDC_MBIM=m -CONFIG_USB_NET_DM9601=m -CONFIG_USB_NET_SR9700=m -CONFIG_USB_NET_SR9800=m -CONFIG_USB_NET_SMSC75XX=m -CONFIG_USB_NET_SMSC95XX=m -CONFIG_USB_NET_GL620A=m -CONFIG_USB_NET_PLUSB=m -CONFIG_USB_NET_MCS7830=m -CONFIG_USB_ALI_M5632=y -CONFIG_USB_NET_CX82310_ETH=m -CONFIG_USB_NET_KALMIA=m -CONFIG_USB_NET_QMI_WWAN=m -CONFIG_USB_HSO=m -CONFIG_USB_NET_INT51X1=m -CONFIG_USB_CDC_PHONET=m -CONFIG_USB_IPHETH=m -CONFIG_USB_SIERRA_NET=m -CONFIG_USB_VL600=m -CONFIG_USB_NET_CH9200=m -# CONFIG_WLAN_VENDOR_ADMTEK is not set -CONFIG_ATH5K=m -CONFIG_ATH9K=m -# CONFIG_ATH9K_PCOEM is not set -CONFIG_ATH9K_PCI_NO_EEPROM=m -CONFIG_ATH9K_HTC=m -CONFIG_CARL9170=m -CONFIG_ATH6KL=m -CONFIG_ATH6KL_USB=m -CONFIG_AR5523=m -CONFIG_WIL6210=m -CONFIG_ATH10K=m -CONFIG_ATH10K_SDIO=m -CONFIG_WCN36XX=m -CONFIG_ATMEL=m -CONFIG_PCI_ATMEL=m -CONFIG_AT76C50X_USB=m -CONFIG_B43=m -CONFIG_B43LEGACY=m -CONFIG_BRCMSMAC=m -CONFIG_BRCMFMAC=m -CONFIG_BRCMFMAC_USB=y -CONFIG_BRCMFMAC_PCIE=y -# CONFIG_WLAN_VENDOR_CISCO is not set -CONFIG_IPW2100=m -CONFIG_IPW2100_MONITOR=y -CONFIG_IPW2200=m -CONFIG_IPW2200_MONITOR=y -CONFIG_IPW2200_PROMISCUOUS=y -CONFIG_IPW2200_QOS=y -CONFIG_IWL4965=m -CONFIG_IWL3945=m -CONFIG_IWLWIFI=m -CONFIG_IWLDVM=m -CONFIG_IWLMVM=m -CONFIG_IWLWIFI_BCAST_FILTERING=y -CONFIG_HOSTAP=m -CONFIG_HOSTAP_FIRMWARE=y -CONFIG_HOSTAP_PLX=m -CONFIG_HOSTAP_PCI=m -CONFIG_HERMES=m -CONFIG_PLX_HERMES=m -CONFIG_TMD_HERMES=m -CONFIG_NORTEL_HERMES=m -CONFIG_ORINOCO_USB=m -CONFIG_P54_COMMON=m -CONFIG_P54_USB=m -CONFIG_P54_PCI=m -CONFIG_PRISM54=m -CONFIG_LIBERTAS=m -CONFIG_LIBERTAS_USB=m -CONFIG_LIBERTAS_SDIO=m -CONFIG_LIBERTAS_SPI=m -CONFIG_LIBERTAS_THINFIRM=m -CONFIG_LIBERTAS_THINFIRM_USB=m -CONFIG_MWIFIEX=m -CONFIG_MWIFIEX_SDIO=m -CONFIG_MWIFIEX_PCIE=m -CONFIG_MWIFIEX_USB=m -CONFIG_MWL8K=m -CONFIG_MT7601U=m -# CONFIG_WLAN_VENDOR_MICROCHIP is not set -CONFIG_RT2X00=m -CONFIG_RT2400PCI=m -CONFIG_RT2500PCI=m -CONFIG_RT61PCI=m -CONFIG_RT2800PCI=m -CONFIG_RT2500USB=m -CONFIG_RT73USB=m -CONFIG_RT2800USB=m -CONFIG_RT2800USB_RT3573=y -CONFIG_RT2800USB_RT53XX=y -CONFIG_RT2800USB_RT55XX=y -CONFIG_RT2800USB_UNKNOWN=y -CONFIG_RTL8180=m -CONFIG_RTL8187=m -CONFIG_RTL8XXXU=m -CONFIG_RTL8XXXU_UNTESTED=y -CONFIG_WL12XX=m -CONFIG_WLCORE_SDIO=m -# CONFIG_WILINK_PLATFORM_DATA is not set -CONFIG_USB_ZD1201=m -CONFIG_ZD1211RW=m -CONFIG_USB_NET_RNDIS_WLAN=m -CONFIG_IEEE802154_FAKELB=m -CONFIG_IEEE802154_AT86RF230=m -CONFIG_IEEE802154_MRF24J40=m -CONFIG_IEEE802154_CC2520=m -CONFIG_IEEE802154_ATUSB=m -CONFIG_IEEE802154_ADF7242=m -CONFIG_INPUT_JOYDEV=m -CONFIG_INPUT_EVDEV=y -# CONFIG_KEYBOARD_ATKBD is not set -CONFIG_KEYBOARD_GPIO=m -CONFIG_KEYBOARD_GPIO_POLLED=m -CONFIG_KEYBOARD_MATRIX=m -CONFIG_KEYBOARD_SNVS_PWRKEY=y -CONFIG_KEYBOARD_IMX=m -# CONFIG_MOUSE_PS2 is not set -CONFIG_MOUSE_SERIAL=m -CONFIG_MOUSE_APPLETOUCH=m -CONFIG_MOUSE_BCM5974=m -CONFIG_MOUSE_GPIO=m -CONFIG_MOUSE_SYNAPTICS_I2C=m -CONFIG_MOUSE_SYNAPTICS_USB=m -CONFIG_INPUT_JOYSTICK=y -CONFIG_JOYSTICK_ANALOG=m -CONFIG_JOYSTICK_A3D=m -CONFIG_JOYSTICK_ADC=m -CONFIG_JOYSTICK_ADI=m -CONFIG_JOYSTICK_COBRA=m -CONFIG_JOYSTICK_GF2K=m -CONFIG_JOYSTICK_GRIP=m -CONFIG_JOYSTICK_GRIP_MP=m -CONFIG_JOYSTICK_GUILLEMOT=m -CONFIG_JOYSTICK_INTERACT=m -CONFIG_JOYSTICK_SIDEWINDER=m -CONFIG_JOYSTICK_TMDC=m -CONFIG_JOYSTICK_IFORCE=m -CONFIG_JOYSTICK_IFORCE_USB=m -CONFIG_JOYSTICK_IFORCE_232=m -CONFIG_JOYSTICK_WARRIOR=m -CONFIG_JOYSTICK_MAGELLAN=m -CONFIG_JOYSTICK_SPACEORB=m -CONFIG_JOYSTICK_SPACEBALL=m -CONFIG_JOYSTICK_STINGER=m -CONFIG_JOYSTICK_TWIDJOY=m -CONFIG_JOYSTICK_ZHENHUA=m -CONFIG_JOYSTICK_AS5011=m -CONFIG_JOYSTICK_JOYDUMP=m -CONFIG_JOYSTICK_XPAD=m -CONFIG_JOYSTICK_XPAD_FF=y -CONFIG_JOYSTICK_XPAD_LEDS=y -CONFIG_JOYSTICK_PSXPAD_SPI=m -CONFIG_JOYSTICK_PSXPAD_SPI_FF=y -CONFIG_JOYSTICK_PXRC=m -CONFIG_JOYSTICK_FSIA6B=m -CONFIG_INPUT_TABLET=y -CONFIG_TABLET_USB_ACECAD=m -CONFIG_TABLET_USB_AIPTEK=m -CONFIG_TABLET_USB_GTCO=m -CONFIG_TABLET_USB_HANWANG=m -CONFIG_TABLET_USB_KBTAB=m -CONFIG_TABLET_USB_PEGASUS=m -CONFIG_TABLET_SERIAL_WACOM4=m -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_ADS7846=m -CONFIG_TOUCHSCREEN_ADC=m -CONFIG_TOUCHSCREEN_PIXCIR=m -CONFIG_TOUCHSCREEN_TSC2004=m -CONFIG_TOUCHSCREEN_TSC2005=m -CONFIG_TOUCHSCREEN_TSC2007=m -CONFIG_TOUCHSCREEN_TSC2007_IIO=y -CONFIG_INPUT_MISC=y -CONFIG_INPUT_MMA8450=m -CONFIG_SERIO_SERPORT=m -# CONFIG_LEGACY_PTYS is not set -CONFIG_SERIAL_8250=m -# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set -# CONFIG_SERIAL_8250_16550A_VARIANTS is not set -CONFIG_SERIAL_8250_NR_UARTS=24 -CONFIG_SERIAL_8250_RUNTIME_UARTS=24 -CONFIG_SERIAL_OF_PLATFORM=m -CONFIG_SERIAL_MAX3100_TS=m -CONFIG_SERIAL_IMX=y -CONFIG_SERIAL_IMX_CONSOLE=y -CONFIG_SERIAL_FSL_LPUART=y -CONFIG_SERIAL_FSL_LPUART_CONSOLE=y -CONFIG_SERIAL_DEV_BUS=y -# CONFIG_I2C_COMPAT is not set -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_MUX_GPIO=y -CONFIG_I2C_MUX_PINCTRL=y -CONFIG_I2C_MUX_REG=y -CONFIG_I2C_DEMUX_PINCTRL=y -# CONFIG_I2C_HELPER_AUTO is not set -CONFIG_I2C_ALGOPCF=m -CONFIG_I2C_ALGOPCA=m -CONFIG_I2C_GPIO=y -CONFIG_I2C_IMX=y -CONFIG_I2C_OCORES=m -CONFIG_SPI=y -CONFIG_SPI_FSL_QUADSPI=y -CONFIG_SPI_GPIO=y -CONFIG_SPI_IMX=y -CONFIG_SPI_SPIDEV=y -CONFIG_PPS_CLIENT_LDISC=m -CONFIG_PPS_CLIENT_GPIO=m -CONFIG_GPIO_SYSFS=y -CONFIG_GPIO_MXC=y -CONFIG_GPIO_ADP5588=m -CONFIG_GPIO_MAX7300=m -CONFIG_GPIO_MAX732X=m -CONFIG_GPIO_PCA953X=m -CONFIG_GPIO_PCF857X=m -CONFIG_GPIO_TS4900=y -CONFIG_GPIO_74X164=m -CONFIG_GPIO_PISOSR=m -CONFIG_W1=m -CONFIG_W1_MASTER_DS2490=m -CONFIG_W1_MASTER_MXC=m -CONFIG_W1_MASTER_GPIO=m -CONFIG_W1_SLAVE_THERM=m -CONFIG_W1_SLAVE_SMEM=m -CONFIG_W1_SLAVE_DS2408=m -CONFIG_W1_SLAVE_DS2413=m -CONFIG_W1_SLAVE_DS2406=m -CONFIG_W1_SLAVE_DS2423=m -CONFIG_W1_SLAVE_DS2431=m -CONFIG_W1_SLAVE_DS2433=m -CONFIG_W1_SLAVE_DS2780=m -CONFIG_W1_SLAVE_DS2781=m -CONFIG_W1_SLAVE_DS28E04=m -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_SYSCON_POWEROFF=y -CONFIG_THERMAL_STATISTICS=y -CONFIG_THERMAL_WRITABLE_TRIPS=y -CONFIG_CPU_THERMAL=y -CONFIG_IMX_THERMAL=y -CONFIG_WATCHDOG=y -CONFIG_TS_WDT_MICRO=y -CONFIG_IMX2_WDT=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_ANATOP=y -CONFIG_REGULATOR_GPIO=y -CONFIG_RC_CORE=m -CONFIG_RC_DEVICES=y -CONFIG_RC_ATI_REMOTE=m -CONFIG_IR_HIX5HD2=m -CONFIG_IR_IMON=m -CONFIG_IR_IMON_RAW=m -CONFIG_IR_MCEUSB=m -CONFIG_IR_REDRAT3=m -CONFIG_IR_STREAMZAP=m -CONFIG_IR_IGORPLUGUSB=m -CONFIG_IR_IGUANA=m -CONFIG_IR_TTUSBIR=m -CONFIG_RC_LOOPBACK=m -CONFIG_IR_GPIO_CIR=m -CONFIG_IR_SERIAL=m -CONFIG_IR_SERIAL_TRANSMITTER=y -CONFIG_IR_SIR=m -CONFIG_RC_XBOX_DVD=m -CONFIG_IR_TOY=m -CONFIG_MEDIA_SUPPORT=y -CONFIG_MEDIA_SUBDRV_AUTOSELECT=y -CONFIG_VIDEO_DEV=m -# CONFIG_DVB_NET is not set -# CONFIG_DVB_DYNAMIC_MINORS is not set -CONFIG_MEDIA_USB_SUPPORT=y -CONFIG_USB_VIDEO_CLASS=m -CONFIG_USB_M5602=m -CONFIG_USB_STV06XX=m -CONFIG_USB_GL860=m -CONFIG_USB_GSPCA_BENQ=m -CONFIG_USB_GSPCA_CONEX=m -CONFIG_USB_GSPCA_CPIA1=m -CONFIG_USB_GSPCA_DTCS033=m -CONFIG_USB_GSPCA_ETOMS=m -CONFIG_USB_GSPCA_FINEPIX=m -CONFIG_USB_GSPCA_JEILINJ=m -CONFIG_USB_GSPCA_JL2005BCD=m -CONFIG_USB_GSPCA_KINECT=m -CONFIG_USB_GSPCA_KONICA=m -CONFIG_USB_GSPCA_MARS=m -CONFIG_USB_GSPCA_MR97310A=m -CONFIG_USB_GSPCA_NW80X=m -CONFIG_USB_GSPCA_OV519=m -CONFIG_USB_GSPCA_OV534=m -CONFIG_USB_GSPCA_OV534_9=m -CONFIG_USB_GSPCA_PAC207=m -CONFIG_USB_GSPCA_PAC7302=m -CONFIG_USB_GSPCA_PAC7311=m -CONFIG_USB_GSPCA_SE401=m -CONFIG_USB_GSPCA_SN9C2028=m -CONFIG_USB_GSPCA_SN9C20X=m -CONFIG_USB_GSPCA_SONIXB=m -CONFIG_USB_GSPCA_SONIXJ=m -CONFIG_USB_GSPCA_SPCA500=m -CONFIG_USB_GSPCA_SPCA501=m -CONFIG_USB_GSPCA_SPCA505=m -CONFIG_USB_GSPCA_SPCA506=m -CONFIG_USB_GSPCA_SPCA508=m -CONFIG_USB_GSPCA_SPCA561=m -CONFIG_USB_GSPCA_SPCA1528=m -CONFIG_USB_GSPCA_SQ905=m -CONFIG_USB_GSPCA_SQ905C=m -CONFIG_USB_GSPCA_SQ930X=m -CONFIG_USB_GSPCA_STK014=m -CONFIG_USB_GSPCA_STK1135=m -CONFIG_USB_GSPCA_STV0680=m -CONFIG_USB_GSPCA_SUNPLUS=m -CONFIG_USB_GSPCA_T613=m -CONFIG_USB_GSPCA_TOPRO=m -CONFIG_USB_GSPCA_TOUPTEK=m -CONFIG_USB_GSPCA_TV8532=m -CONFIG_USB_GSPCA_VC032X=m -CONFIG_USB_GSPCA_VICAM=m -CONFIG_USB_GSPCA_XIRLINK_CIT=m -CONFIG_USB_GSPCA_ZC3XX=m -CONFIG_USB_PWC=m -CONFIG_VIDEO_CPIA2=m -CONFIG_USB_ZR364XX=m -CONFIG_USB_STKWEBCAM=m -CONFIG_USB_S2255=m -CONFIG_VIDEO_USBTV=m -CONFIG_VIDEO_PVRUSB2=m -CONFIG_VIDEO_HDPVR=m -CONFIG_VIDEO_STK1160_COMMON=m -CONFIG_VIDEO_GO7007=m -CONFIG_VIDEO_GO7007_USB=m -CONFIG_VIDEO_AU0828=m -CONFIG_VIDEO_CX231XX=m -CONFIG_VIDEO_CX231XX_ALSA=m -CONFIG_VIDEO_CX231XX_DVB=m -CONFIG_VIDEO_TM6000=m -CONFIG_VIDEO_TM6000_ALSA=m -CONFIG_VIDEO_TM6000_DVB=m -CONFIG_DVB_USB=m -CONFIG_DVB_USB_A800=m -CONFIG_DVB_USB_DIBUSB_MB=m -CONFIG_DVB_USB_DIBUSB_MC=m -CONFIG_DVB_USB_DIB0700=m -CONFIG_DVB_USB_UMT_010=m -CONFIG_DVB_USB_CXUSB=m -CONFIG_DVB_USB_M920X=m -CONFIG_DVB_USB_DIGITV=m -CONFIG_DVB_USB_VP7045=m -CONFIG_DVB_USB_VP702X=m -CONFIG_DVB_USB_GP8PSK=m -CONFIG_DVB_USB_NOVA_T_USB2=m -CONFIG_DVB_USB_TTUSB2=m -CONFIG_DVB_USB_DTT200U=m -CONFIG_DVB_USB_OPERA1=m -CONFIG_DVB_USB_AF9005=m -CONFIG_DVB_USB_AF9005_REMOTE=m -CONFIG_DVB_USB_PCTV452E=m -CONFIG_DVB_USB_DW2102=m -CONFIG_DVB_USB_CINERGY_T2=m -CONFIG_DVB_USB_DTV5100=m -CONFIG_DVB_USB_AZ6027=m -CONFIG_DVB_USB_TECHNISAT_USB2=m -CONFIG_DVB_USB_V2=m -CONFIG_DVB_USB_AF9015=m -CONFIG_DVB_USB_AF9035=m -CONFIG_DVB_USB_ANYSEE=m -CONFIG_DVB_USB_AU6610=m -CONFIG_DVB_USB_AZ6007=m -CONFIG_DVB_USB_CE6230=m -CONFIG_DVB_USB_EC168=m -CONFIG_DVB_USB_GL861=m -CONFIG_DVB_USB_LME2510=m -CONFIG_DVB_USB_MXL111SF=m -CONFIG_DVB_USB_RTL28XXU=m -CONFIG_DVB_USB_DVBSKY=m -CONFIG_DVB_USB_ZD1301=m -CONFIG_DVB_TTUSB_BUDGET=m -CONFIG_DVB_TTUSB_DEC=m -CONFIG_SMS_USB_DRV=m -CONFIG_DVB_B2C2_FLEXCOP_USB=m -CONFIG_DVB_AS102=m -CONFIG_VIDEO_EM28XX=m -CONFIG_VIDEO_EM28XX_V4L2=m -CONFIG_VIDEO_EM28XX_ALSA=m -CONFIG_VIDEO_EM28XX_DVB=m -CONFIG_USB_AIRSPY=m -CONFIG_USB_HACKRF=m -CONFIG_USB_MSI2500=m -# CONFIG_RADIO_ADAPTERS is not set -CONFIG_V4L_PLATFORM_DRIVERS=y -CONFIG_VIDEO_MUX=m -CONFIG_V4L_MEM2MEM_DRIVERS=y -CONFIG_VIDEO_CODA=m -CONFIG_VIDEO_IMX_PXP=m -CONFIG_VIDEO_ADV7180=m -CONFIG_VIDEO_OV2680=m -CONFIG_VIDEO_OV5640=m -CONFIG_VIDEO_OV5645=m -CONFIG_CXD2880_SPI_DRV=m -CONFIG_MEDIA_TUNER_MT2131=m -CONFIG_MEDIA_TUNER_M88RS6000T=m -CONFIG_MEDIA_TUNER_MXL301RF=m -CONFIG_MEDIA_TUNER_QM1D1B0004=m -CONFIG_DVB_STV0910=m -CONFIG_DVB_STV6111=m -CONFIG_DVB_MXL5XX=m -CONFIG_DVB_CX24110=m -CONFIG_DVB_ZL10036=m -CONFIG_DVB_TDA8261=m -CONFIG_DVB_VES1X93=m -CONFIG_DVB_TUA6100=m -CONFIG_DVB_CX24117=m -CONFIG_DVB_MB86A16=m -CONFIG_DVB_SP8870=m -CONFIG_DVB_SP887X=m -CONFIG_DVB_S5H1432=m -CONFIG_DVB_L64781=m -CONFIG_DVB_DIB9000=m -CONFIG_DVB_STV0367=m -CONFIG_DVB_CXD2880=m -CONFIG_DVB_TDA10021=m -CONFIG_DVB_OR51211=m -CONFIG_DVB_OR51132=m -CONFIG_DVB_MN88443X=m -CONFIG_DVB_LNBH25=m -CONFIG_DVB_LNBH29=m -CONFIG_DVB_ISL6405=m -CONFIG_DVB_LGS8GL5=m -CONFIG_DVB_TDA665x=m -CONFIG_DVB_HORUS3A=m -CONFIG_DVB_ASCOT2E=m -CONFIG_DVB_HELENE=m -CONFIG_DVB_CXD2099=m -# CONFIG_VGA_ARB is not set -CONFIG_IMX_IPUV3_CORE=y -CONFIG_DRM=y -CONFIG_DRM_PANEL_LVDS=y -CONFIG_DRM_PANEL_SIMPLE=y -CONFIG_DRM_TI_TFP410=y -CONFIG_DRM_DW_HDMI_AHB_AUDIO=m -CONFIG_DRM_DW_HDMI_CEC=y -CONFIG_DRM_IMX=y -CONFIG_DRM_IMX_PARALLEL_DISPLAY=y -CONFIG_DRM_IMX_LDB=y -CONFIG_DRM_IMX_HDMI=y -CONFIG_DRM_ETNAVIV=y -CONFIG_DRM_MXSFB=y -CONFIG_FB_MODE_HELPERS=y -# CONFIG_FB_MX3 is not set -CONFIG_FB_ST7565P=m -CONFIG_LCD_CLASS_DEVICE=y -CONFIG_LCD_PLATFORM=y -CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BACKLIGHT_PWM=y -CONFIG_BACKLIGHT_GPIO=y -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_LOGO=y -CONFIG_SOUND=y -CONFIG_SND=m -CONFIG_SND_HRTIMER=m -# CONFIG_SND_PCI is not set -CONFIG_SND_USB_AUDIO=m -CONFIG_SND_USB_UA101=m -CONFIG_SND_USB_CAIAQ=m -CONFIG_SND_USB_6FIRE=m -CONFIG_SND_USB_HIFACE=m -CONFIG_SND_BCD2000=m -CONFIG_SND_USB_POD=m -CONFIG_SND_USB_PODHD=m -CONFIG_SND_USB_TONEPORT=m -CONFIG_SND_USB_VARIAX=m -CONFIG_SND_SOC=m -CONFIG_SND_IMX_SOC=m -CONFIG_SND_SOC_IMX_SGTL5000=m -CONFIG_SND_SOC_FSL_ASOC_CARD=m -CONFIG_SND_SOC_AC97_CODEC=m -CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m -CONFIG_SND_SOC_TLV320AIC23_I2C=m -CONFIG_SND_SOC_TLV320AIC3X=m -CONFIG_SND_SIMPLE_CARD=m -CONFIG_UHID=m -CONFIG_HID_A4TECH=m -CONFIG_HID_ACRUX=m -CONFIG_HID_APPLE=m -CONFIG_HID_APPLEIR=m -CONFIG_HID_AUREAL=m -CONFIG_HID_BELKIN=m -CONFIG_HID_BETOP_FF=m -CONFIG_HID_CHERRY=m -CONFIG_HID_CHICONY=m -CONFIG_HID_CORSAIR=m -CONFIG_HID_PRODIKEYS=m -CONFIG_HID_CMEDIA=m -CONFIG_HID_CYPRESS=m -CONFIG_HID_DRAGONRISE=m -CONFIG_HID_EMS_FF=m -CONFIG_HID_ELECOM=m -CONFIG_HID_ELO=m -CONFIG_HID_EZKEY=m -CONFIG_HID_GEMBIRD=m -CONFIG_HID_GFRM=m -CONFIG_HID_HOLTEK=m -CONFIG_HID_GT683R=m -CONFIG_HID_KEYTOUCH=m -CONFIG_HID_KYE=m -CONFIG_HID_UCLOGIC=m -CONFIG_HID_WALTOP=m -CONFIG_HID_GYRATION=m -CONFIG_HID_ICADE=m -CONFIG_HID_TWINHAN=m -CONFIG_HID_KENSINGTON=m -CONFIG_HID_LCPOWER=m -CONFIG_HID_LENOVO=m -CONFIG_HID_LOGITECH=m -CONFIG_HID_LOGITECH_HIDPP=m -CONFIG_HID_MAGICMOUSE=m -CONFIG_HID_MICROSOFT=m -CONFIG_HID_MONTEREY=m -CONFIG_HID_MULTITOUCH=m -CONFIG_HID_NTRIG=m -CONFIG_HID_ORTEK=m -CONFIG_HID_PANTHERLORD=m -CONFIG_HID_PENMOUNT=m -CONFIG_HID_PETALYNX=m -CONFIG_HID_PICOLCD=m -CONFIG_HID_PLANTRONICS=m -CONFIG_HID_PRIMAX=m -CONFIG_HID_ROCCAT=m -CONFIG_HID_SAITEK=m -CONFIG_HID_SAMSUNG=m -CONFIG_HID_SONY=m -CONFIG_HID_SPEEDLINK=m -CONFIG_HID_STEELSERIES=m -CONFIG_HID_SUNPLUS=m -CONFIG_HID_RMI=m -CONFIG_HID_GREENASIA=m -CONFIG_HID_SMARTJOYPLUS=m -CONFIG_HID_TIVO=m -CONFIG_HID_TOPSEED=m -CONFIG_HID_THINGM=m -CONFIG_HID_THRUSTMASTER=m -CONFIG_HID_WACOM=m -CONFIG_HID_WIIMOTE=m -CONFIG_HID_XINMO=m -CONFIG_HID_ZEROPLUS=m -CONFIG_HID_ZYDACRON=m -CONFIG_HID_ALPS=m -CONFIG_USB_LED_TRIG=y -CONFIG_USB=y -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -CONFIG_USB_OTG=y -CONFIG_USB_OTG_FSM=y -CONFIG_USB_LEDS_TRIGGER_USBPORT=y -CONFIG_USB_MON=m -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_FSL=y -CONFIG_USB_EHCI_MXC=y -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_PRINTER=m -CONFIG_USB_STORAGE=y -CONFIG_USB_STORAGE_REALTEK=m -CONFIG_USB_STORAGE_DATAFAB=m -CONFIG_USB_STORAGE_FREECOM=m -CONFIG_USB_STORAGE_ISD200=m -CONFIG_USB_STORAGE_USBAT=m -CONFIG_USB_STORAGE_SDDR09=m -CONFIG_USB_STORAGE_SDDR55=m -CONFIG_USB_STORAGE_JUMPSHOT=m -CONFIG_USB_STORAGE_ALAUDA=m -CONFIG_USB_STORAGE_ONETOUCH=m -CONFIG_USB_STORAGE_KARMA=m -CONFIG_USB_STORAGE_CYPRESS_ATACB=m -CONFIG_USB_STORAGE_ENE_UB6250=m -CONFIG_USB_UAS=m -CONFIG_USB_MDC800=m -CONFIG_USB_MICROTEK=m -CONFIG_USB_MUSB_HDRC=m -CONFIG_USB_CHIPIDEA=y -CONFIG_USB_CHIPIDEA_UDC=y -CONFIG_USB_CHIPIDEA_HOST=y -CONFIG_USB_SERIAL=m -CONFIG_USB_SERIAL_GENERIC=y -CONFIG_USB_SERIAL_SIMPLE=m -CONFIG_USB_SERIAL_AIRCABLE=m -CONFIG_USB_SERIAL_ARK3116=m -CONFIG_USB_SERIAL_BELKIN=m -CONFIG_USB_SERIAL_CH341=m -CONFIG_USB_SERIAL_WHITEHEAT=m -CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m -CONFIG_USB_SERIAL_CP210X=m -CONFIG_USB_SERIAL_CYPRESS_M8=m -CONFIG_USB_SERIAL_EMPEG=m -CONFIG_USB_SERIAL_FTDI_SIO=m -CONFIG_USB_SERIAL_VISOR=m -CONFIG_USB_SERIAL_IPAQ=m -CONFIG_USB_SERIAL_IR=m -CONFIG_USB_SERIAL_EDGEPORT=m -CONFIG_USB_SERIAL_EDGEPORT_TI=m -CONFIG_USB_SERIAL_F81232=m -CONFIG_USB_SERIAL_GARMIN=m -CONFIG_USB_SERIAL_IPW=m -CONFIG_USB_SERIAL_IUU=m -CONFIG_USB_SERIAL_KEYSPAN_PDA=m -CONFIG_USB_SERIAL_KEYSPAN=m -CONFIG_USB_SERIAL_KLSI=m -CONFIG_USB_SERIAL_KOBIL_SCT=m -CONFIG_USB_SERIAL_MCT_U232=m -CONFIG_USB_SERIAL_METRO=m -CONFIG_USB_SERIAL_MOS7720=m -CONFIG_USB_SERIAL_MOS7840=m -CONFIG_USB_SERIAL_MXUPORT=m -CONFIG_USB_SERIAL_NAVMAN=m -CONFIG_USB_SERIAL_PL2303=m -CONFIG_USB_SERIAL_OTI6858=m -CONFIG_USB_SERIAL_QCAUX=m -CONFIG_USB_SERIAL_QUALCOMM=m -CONFIG_USB_SERIAL_SPCP8X5=m -CONFIG_USB_SERIAL_SAFE=m -CONFIG_USB_SERIAL_SAFE_PADDED=y -CONFIG_USB_SERIAL_SIERRAWIRELESS=m -CONFIG_USB_SERIAL_SYMBOL=m -CONFIG_USB_SERIAL_TI=m -CONFIG_USB_SERIAL_CYBERJACK=m -CONFIG_USB_SERIAL_XIRCOM=m -CONFIG_USB_SERIAL_OPTION=m -CONFIG_USB_SERIAL_OMNINET=m -CONFIG_USB_SERIAL_OPTICON=m -CONFIG_USB_SERIAL_XSENS_MT=m -CONFIG_USB_SERIAL_WISHBONE=m -CONFIG_USB_SERIAL_SSU100=m -CONFIG_USB_SERIAL_QT2=m -CONFIG_USB_SERIAL_DEBUG=m -CONFIG_USB_EMI62=m -CONFIG_USB_EMI26=m -CONFIG_USB_ADUTUX=m -CONFIG_USB_SEVSEG=m -CONFIG_USB_LEGOTOWER=m -CONFIG_USB_LCD=m -CONFIG_USB_CYPRESS_CY7C63=m -CONFIG_USB_CYTHERM=m -CONFIG_USB_IDMOUSE=m -CONFIG_USB_FTDI_ELAN=m -CONFIG_USB_APPLEDISPLAY=m -CONFIG_USB_SISUSBVGA=m -CONFIG_USB_LD=m -CONFIG_USB_TRANCEVIBRATOR=m -CONFIG_USB_IOWARRIOR=m -CONFIG_USB_TEST=m -CONFIG_USB_EHSET_TEST_FIXTURE=m -CONFIG_USB_ISIGHTFW=m -CONFIG_USB_YUREX=m -CONFIG_USB_HSIC_USB3503=m -CONFIG_USB_HSIC_USB4604=m -CONFIG_USB_LINK_LAYER_TEST=m -CONFIG_USB_CHAOSKEY=m -CONFIG_USB_ATM=m -CONFIG_USB_SPEEDTOUCH=m -CONFIG_USB_CXACRU=m -CONFIG_USB_UEAGLEATM=m -CONFIG_USB_XUSBATM=m -CONFIG_FSL_USB2_OTG=y -CONFIG_NOP_USB_XCEIV=y -CONFIG_USB_MXS_PHY=y -CONFIG_USB_GADGET=y -CONFIG_USB_FSL_USB2=y -CONFIG_USB_CONFIGFS=y -CONFIG_USB_CONFIGFS_SERIAL=y -CONFIG_USB_CONFIGFS_ACM=y -CONFIG_USB_CONFIGFS_OBEX=y -CONFIG_USB_CONFIGFS_NCM=y -CONFIG_USB_CONFIGFS_ECM=y -CONFIG_USB_CONFIGFS_ECM_SUBSET=y -CONFIG_USB_CONFIGFS_RNDIS=y -CONFIG_USB_CONFIGFS_EEM=y -CONFIG_USB_CONFIGFS_MASS_STORAGE=y -CONFIG_USB_CONFIGFS_F_LB_SS=y -CONFIG_USB_CONFIGFS_F_FS=y -CONFIG_USB_CONFIGFS_F_UAC1=y -CONFIG_USB_CONFIGFS_F_UAC2=y -CONFIG_USB_CONFIGFS_F_MIDI=y -CONFIG_USB_CONFIGFS_F_HID=y -CONFIG_USB_CONFIGFS_F_UVC=y -CONFIG_USB_CONFIGFS_F_PRINTER=y -CONFIG_USB_ZERO=m -CONFIG_USB_AUDIO=m -CONFIG_USB_ETH=m -CONFIG_USB_G_NCM=m -CONFIG_USB_GADGETFS=m -CONFIG_USB_FUNCTIONFS=m -CONFIG_USB_MASS_STORAGE=m -CONFIG_USB_G_SERIAL=m -CONFIG_USB_MIDI_GADGET=m -CONFIG_USB_G_PRINTER=m -CONFIG_USB_CDC_COMPOSITE=m -CONFIG_USB_G_NOKIA=m -CONFIG_USB_G_ACM_MS=m -CONFIG_USB_G_MULTI=m -CONFIG_USB_G_MULTI_CDC=y -CONFIG_USB_G_HID=m -CONFIG_USB_G_DBGP=m -CONFIG_USB_G_WEBCAM=m -CONFIG_MMC=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MMC_SDHCI_OF_ESDHC=y -CONFIG_MMC_SDHCI_ESDHC_IMX=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_GPIO=y -CONFIG_LEDS_PWM=y -CONFIG_LEDS_SYSCON=y -CONFIG_LEDS_TRIGGER_TIMER=y -CONFIG_LEDS_TRIGGER_ONESHOT=y -CONFIG_LEDS_TRIGGER_DISK=y -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -CONFIG_LEDS_TRIGGER_BACKLIGHT=y -CONFIG_LEDS_TRIGGER_CPU=y -CONFIG_LEDS_TRIGGER_GPIO=y -CONFIG_LEDS_TRIGGER_DEFAULT_ON=y -CONFIG_LEDS_TRIGGER_TRANSIENT=y -CONFIG_LEDS_TRIGGER_CAMERA=y -CONFIG_LEDS_TRIGGER_PANIC=y -CONFIG_LEDS_TRIGGER_NETDEV=y -CONFIG_LEDS_TRIGGER_PATTERN=y -CONFIG_LEDS_TRIGGER_AUDIO=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_INTF_DEV_UIE_EMUL=y -CONFIG_RTC_DRV_DS1307=y -CONFIG_RTC_DRV_ISL12022=y -CONFIG_RTC_DRV_M41T80=y -CONFIG_RTC_DRV_MXC=y -CONFIG_RTC_DRV_SNVS=y -CONFIG_DMADEVICES=y -CONFIG_FSL_EDMA=y -CONFIG_IMX_SDMA=y -CONFIG_MXS_DMA=y -CONFIG_DMATEST=m -CONFIG_UIO=m -CONFIG_UIO_PDRV_GENIRQ=m -CONFIG_UIO_DMEM_GENIRQ=m -CONFIG_UIO_PCI_GENERIC=m -CONFIG_STAGING=y -CONFIG_PRISM2_USB=m -CONFIG_RTL8192U=m -CONFIG_RTLLIB=m -CONFIG_RTL8192E=m -CONFIG_R8712U=m -CONFIG_R8188EU=m -CONFIG_RTS5208=m -CONFIG_VT6655=m -CONFIG_STAGING_MEDIA=y -CONFIG_VIDEO_IMX_MEDIA=m -CONFIG_COMMON_CLK_PWM=y -# CONFIG_IOMMU_SUPPORT is not set -CONFIG_IMX_GPCV2_PM_DOMAINS=y -CONFIG_EXTCON_ADC_JACK=m -CONFIG_EXTCON_GPIO=m -CONFIG_EXTCON_USB_GPIO=m -CONFIG_IIO=y -CONFIG_IIO_TRIGGERED_BUFFER=y -CONFIG_IIO_SW_DEVICE=m -CONFIG_IIO_SW_TRIGGER=m -CONFIG_MMA8452=m -CONFIG_VF610_ADC=m -CONFIG_INV_MPU6050_I2C=m -CONFIG_AK8975=m -CONFIG_IIO_HRTIMER_TRIGGER=m -CONFIG_IIO_INTERRUPT_TRIGGER=m -CONFIG_IIO_TIGHTLOOP_TRIGGER=m -CONFIG_IIO_SYSFS_TRIGGER=m -CONFIG_PWM=y -CONFIG_PWM_FSL_FTM=y -CONFIG_PWM_IMX27=y -CONFIG_PWM_IMX_TPM=y -CONFIG_NVMEM_IMX_OCOTP=y -CONFIG_NVMEM_SNVS_LPGPR=y -CONFIG_TEE=y -CONFIG_OPTEE=y -CONFIG_MUX_MMIO=m -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT2_FS_POSIX_ACL=y -CONFIG_EXT2_FS_SECURITY=y -CONFIG_EXT3_FS=y -CONFIG_EXT3_FS_POSIX_ACL=y -CONFIG_EXT3_FS_SECURITY=y -CONFIG_REISERFS_FS=m -CONFIG_REISERFS_FS_XATTR=y -CONFIG_REISERFS_FS_POSIX_ACL=y -CONFIG_REISERFS_FS_SECURITY=y -CONFIG_JFS_FS=m -CONFIG_JFS_POSIX_ACL=y -CONFIG_JFS_SECURITY=y -CONFIG_XFS_FS=m -CONFIG_XFS_QUOTA=y -CONFIG_XFS_POSIX_ACL=y -CONFIG_XFS_RT=y -CONFIG_GFS2_FS=m -CONFIG_OCFS2_FS=m -CONFIG_BTRFS_FS=m -CONFIG_BTRFS_FS_POSIX_ACL=y -CONFIG_NILFS2_FS=m -CONFIG_F2FS_FS=m -CONFIG_F2FS_FS_SECURITY=y -CONFIG_F2FS_CHECK_FS=y -CONFIG_FANOTIFY=y -CONFIG_QUOTA_NETLINK_INTERFACE=y -# CONFIG_PRINT_QUOTA_WARNING is not set -CONFIG_QFMT_V2=m -CONFIG_AUTOFS4_FS=m -CONFIG_FUSE_FS=m -CONFIG_CUSE=m -CONFIG_OVERLAY_FS=m -CONFIG_ISO9660_FS=m -CONFIG_JOLIET=y -CONFIG_ZISOFS=y -CONFIG_UDF_FS=m -CONFIG_MSDOS_FS=m -CONFIG_VFAT_FS=m -CONFIG_NTFS_FS=m -CONFIG_NTFS_RW=y -CONFIG_TMPFS_POSIX_ACL=y -CONFIG_HFS_FS=m -CONFIG_HFSPLUS_FS=m -CONFIG_CRAMFS=m -CONFIG_SQUASHFS=m -CONFIG_SQUASHFS_LZ4=y -CONFIG_SQUASHFS_LZO=y -CONFIG_SQUASHFS_XZ=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3_ACL=y -CONFIG_NFS_V4=m -CONFIG_NFS_V4_1=y -CONFIG_NFS_V4_2=y -CONFIG_NFS_V4_1_MIGRATION=y -CONFIG_ROOT_NFS=y -CONFIG_NFSD=m -CONFIG_NFSD_V3_ACL=y -CONFIG_NFSD_V4=y -CONFIG_NFSD_BLOCKLAYOUT=y -CONFIG_NFSD_SCSILAYOUT=y -CONFIG_NFSD_FLEXFILELAYOUT=y -CONFIG_CEPH_FS=m -CONFIG_CIFS=m -CONFIG_CODA_FS=m -CONFIG_AFS_FS=m -CONFIG_NLS_DEFAULT="cp437" -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_CODEPAGE_737=m -CONFIG_NLS_CODEPAGE_775=m -CONFIG_NLS_CODEPAGE_850=m -CONFIG_NLS_CODEPAGE_852=m -CONFIG_NLS_CODEPAGE_855=m -CONFIG_NLS_CODEPAGE_857=m -CONFIG_NLS_CODEPAGE_860=m -CONFIG_NLS_CODEPAGE_861=m -CONFIG_NLS_CODEPAGE_862=m -CONFIG_NLS_CODEPAGE_863=m -CONFIG_NLS_CODEPAGE_864=m -CONFIG_NLS_CODEPAGE_865=m -CONFIG_NLS_CODEPAGE_866=m -CONFIG_NLS_CODEPAGE_869=m -CONFIG_NLS_CODEPAGE_936=m -CONFIG_NLS_CODEPAGE_950=m -CONFIG_NLS_CODEPAGE_932=m -CONFIG_NLS_CODEPAGE_949=m -CONFIG_NLS_CODEPAGE_874=m -CONFIG_NLS_ISO8859_8=m -CONFIG_NLS_CODEPAGE_1250=m -CONFIG_NLS_CODEPAGE_1251=m -CONFIG_NLS_ASCII=y -CONFIG_NLS_ISO8859_1=y -CONFIG_NLS_ISO8859_2=m -CONFIG_NLS_ISO8859_3=m -CONFIG_NLS_ISO8859_4=m -CONFIG_NLS_ISO8859_5=m -CONFIG_NLS_ISO8859_6=m -CONFIG_NLS_ISO8859_7=m -CONFIG_NLS_ISO8859_9=m -CONFIG_NLS_ISO8859_13=m -CONFIG_NLS_ISO8859_14=m -CONFIG_NLS_ISO8859_15=m -CONFIG_NLS_KOI8_R=m -CONFIG_NLS_KOI8_U=m -CONFIG_NLS_MAC_ROMAN=m -CONFIG_NLS_MAC_CELTIC=m -CONFIG_NLS_MAC_CENTEURO=m -CONFIG_NLS_MAC_CROATIAN=m -CONFIG_NLS_MAC_CYRILLIC=m -CONFIG_NLS_MAC_GAELIC=m -CONFIG_NLS_MAC_GREEK=m -CONFIG_NLS_MAC_ICELAND=m -CONFIG_NLS_MAC_INUIT=m -CONFIG_NLS_MAC_ROMANIAN=m -CONFIG_NLS_MAC_TURKISH=m -CONFIG_NLS_UTF8=y -CONFIG_CRYPTO_USER=y -# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set -CONFIG_CRYPTO_ECDH=y -CONFIG_CRYPTO_CCM=y -CONFIG_CRYPTO_GCM=y -CONFIG_CRYPTO_SEQIV=y -CONFIG_CRYPTO_ECHAINIV=y -CONFIG_CRYPTO_LRW=y -CONFIG_CRYPTO_CMAC=y -CONFIG_CRYPTO_CRC32=y -CONFIG_CRYPTO_XXHASH=y -CONFIG_CRYPTO_BLAKE2B=y -CONFIG_CRYPTO_MD4=y -CONFIG_CRYPTO_MICHAEL_MIC=y -CONFIG_CRYPTO_RMD128=y -CONFIG_CRYPTO_RMD160=y -CONFIG_CRYPTO_RMD256=y -CONFIG_CRYPTO_RMD320=y -CONFIG_CRYPTO_SHA512=y -CONFIG_CRYPTO_SHA3=y -CONFIG_CRYPTO_TGR192=y -CONFIG_CRYPTO_WP512=y -CONFIG_CRYPTO_BLOWFISH=m -CONFIG_CRYPTO_CAMELLIA=m -CONFIG_CRYPTO_TWOFISH=m -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_LZO=m -CONFIG_CRYPTO_DEV_FSL_CAAM=y -CONFIG_CRYPTO_DEV_SAHARA=y -CONFIG_CRYPTO_DEV_MXS_DCP=y -CONFIG_CRC7=m -CONFIG_LIBCRC32C=y -CONFIG_CMA_SIZE_MBYTES=128 -CONFIG_IRQ_POLL=y -CONFIG_PRINTK_TIME=y -CONFIG_DYNAMIC_DEBUG=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_FS=y -# CONFIG_SCHED_DEBUG is not set -# CONFIG_DEBUG_PREEMPT is not set -CONFIG_PROVE_LOCKING=y -# CONFIG_FTRACE is not set From 7f885040d0a081140318e42474c7801d40f4e160 Mon Sep 17 00:00:00 2001 From: Michael Peters Date: Thu, 16 Mar 2023 14:26:54 -0700 Subject: [PATCH 060/244] mfd: ts78xx_mfd: Initial commit Add support for MFD driver for the TS-78xx series. --- drivers/mfd/Kconfig | 8 ++ drivers/mfd/Makefile | 1 + drivers/mfd/ts78xx_mfd.c | 299 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 308 insertions(+) create mode 100644 drivers/mfd/ts78xx_mfd.c diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 122cb85631125..5babb01ffa1dd 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -64,6 +64,14 @@ config MFD_ACT8945A linear regulators, along with a complete ActivePath battery charger. +config MFD_TS78XX + tristate "TS-78XX series PCIe syscon driver" + select MFD_CORE + select OF_OVERLAY + depends on PCI && OF + help + Support for the TS-7820, TS-7825, TS-7840 pcie syscon driver + config MFD_SUN4I_GPADC tristate "Allwinner sunxi platforms' GPADC MFD driver" select MFD_CORE diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 285cd1a13f4d6..d28897ef39df2 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_MFD_88PM800) += 88pm800.o 88pm80x.o obj-$(CONFIG_MFD_88PM805) += 88pm805.o 88pm80x.o obj-$(CONFIG_MFD_88PM886_PMIC) += 88pm886.o obj-$(CONFIG_MFD_ACT8945A) += act8945a.o +obj-$(CONFIG_MFD_TS78XX) += ts78xx_mfd.o obj-$(CONFIG_MFD_SM501) += sm501.o obj-$(CONFIG_ARCH_BCM2835) += bcm2835-pm.o obj-$(CONFIG_MFD_BCM590XX) += bcm590xx.o diff --git a/drivers/mfd/ts78xx_mfd.c b/drivers/mfd/ts78xx_mfd.c new file mode 100644 index 0000000000000..92cf095dda725 --- /dev/null +++ b/drivers/mfd/ts78xx_mfd.c @@ -0,0 +1,299 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PCI device tree support + * + * Copyright (C) 2022 Mark Featherston + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* If present, IRQC base is 0x200 + * 0x0 = doorbell_adr + * 0x4 = doorbell_msk (1 = enabled) + * 0x8 = irqs + */ + +#define TS7800V2_IRQC 0x200 +#define TS7800V2_IRQC_MASK_REG 0x4 +#define TS7800V2_IRQC_IRQS 0x8 + +#define TS7800V2_PC104_A_MUX 0x30 +#define TS7800V2_PC104_B_MUX 0x34 +#define TS7800V2_PC104_C_MUX 0x38 +#define TS7800V2_PC104_D_MUX 0x3c + +struct tsmfd_of_priv { + struct irq_chip chip; + struct irq_domain *domain; + void __iomem *fpgabase; + int irqnum; + u32 mask; + u32 map[32]; + spinlock_t lock; +}; + +static int tsfpga_add_ranges(struct pci_dev *pdev, struct device_node *np) +{ + struct property *prop; + u32 start, len; + struct of_changeset ocs; + uint32_t *val; + int i; + + prop = devm_kcalloc(&pdev->dev, 1, sizeof(*prop), GFP_KERNEL); + if (!prop) + return -ENOMEM; + + val = devm_kcalloc(&pdev->dev, 1, sizeof(uint32_t)*4*DEVICE_COUNT_RESOURCE, GFP_KERNEL); + if (!val) + return -ENOMEM; + + for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { + start = pci_resource_start(pdev, i); + if (!start) + break; + + len = pci_resource_len(pdev, i); + val[(i * 4)] = cpu_to_be32(i); + val[(i * 4) + 1] = cpu_to_be32(0); + val[(i * 4) + 2] = cpu_to_be32(start); + val[(i * 4) + 3] = cpu_to_be32(len); + } + + prop->name = devm_kstrdup(&pdev->dev, "ranges", GFP_KERNEL); + prop->value = val; + prop->length = sizeof(uint32_t) * 4 * i; + + of_changeset_init(&ocs); + of_changeset_add_property(&ocs, np, prop); + of_changeset_apply(&ocs); + + return 0; +} + +static void tsmfd_chained_irq_handler(struct irq_desc *desc) +{ + struct tsmfd_of_priv *priv = irq_desc_get_handler_data(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); + u32 status = readl(priv->fpgabase + TS7800V2_IRQC + TS7800V2_IRQC_IRQS); + + status &= priv->mask; + + chained_irq_enter(chip, desc); + if (!status) + goto out; + + do { + unsigned int bit = __ffs(status); + int irq = irq_find_mapping(priv->domain, bit); + + status &= ~(1 << bit); + generic_handle_irq(irq); + } while (status); + +out: + chained_irq_exit(chip, desc); +} + +static struct irq_chip pci_irq_chip = { + .name = "tsmfd_irq", +}; + +static int tsmfd_irqdomain_map(struct irq_domain *d, + unsigned int virq, irq_hw_number_t hwirq) +{ + struct tsmfd_of_priv *priv = d->host_data; + + irq_set_chip_and_handler(virq, &pci_irq_chip, + handle_simple_irq); + irq_set_chip_data(virq, priv); + irq_clear_status_flags(virq, IRQ_NOREQUEST); + irq_set_status_flags(virq, IRQ_IS_POLLED); + + return 0; +} + +static const struct irq_domain_ops tsmfd_irqdomain_ops = { + .map = tsmfd_irqdomain_map, + .xlate = irq_domain_xlate_onecell, +}; + +static int ts7800v2_irqc_enable(struct pci_dev *pdev, struct device_node *np, u32 irqnum) +{ + struct tsmfd_of_priv *priv; + struct device *dev = &pdev->dev; + int ret, i; + + priv = devm_kcalloc(dev, 1, sizeof(struct tsmfd_of_priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + ret = pci_alloc_irq_vectors(pdev, irqnum, irqnum, PCI_IRQ_MSI); + if (ret != irqnum) + return -ENODEV; + + spin_lock_init(&priv->lock); + priv->fpgabase = pci_ioremap_bar(pdev, 2); + priv->irqnum = irqnum; + priv->domain = irq_domain_add_linear(np, irqnum, &tsmfd_irqdomain_ops, priv); + if (!priv->domain) { + dev_err(dev, "Couldn't create IRQ domain"); + return -ENODEV; + } + + priv->mask = 0xFFF0000; + writel(priv->mask, priv->fpgabase + TS7800V2_IRQC + TS7800V2_IRQC_MASK_REG); + + for (i = 0; i < irqnum; i++) { + priv->map[i] = pci_irq_vector(pdev, i); + irq_set_chained_handler_and_data(pci_irq_vector(pdev, i), + tsmfd_chained_irq_handler, priv); + } + + return 0; +} + +/* Switch mux registers on TS-7800-V2 from GPIO to a PC104 bus */ +static void ts7800v2_pc104on(struct pci_dev *pdev) +{ + struct device *dev = &pdev->dev; + void __iomem *base = pci_ioremap_bar(pdev, 2); + + dev_info(dev, "Enabling PC104"); + writel(0x55555555, base + TS7800V2_PC104_A_MUX); + writel(0x55555555, base + TS7800V2_PC104_B_MUX); + writel(0x55555, base + TS7800V2_PC104_C_MUX); + writel(0x55555, base + TS7800V2_PC104_D_MUX); +} + +static int tsfpga_pci_probe(struct pci_dev *pdev, + const struct pci_device_id *ent) +{ + struct device_node *np; + struct device *dev = &pdev->dev; + u32 irqnum; + int ret = 0; + + if (pci_enable_device(pdev)) { + ret = -ENODEV; + goto out; + } + np = of_find_compatible_node(NULL, NULL, "technologic,ts78xx-mfd"); + if (np == NULL) { + dev_err(dev, "Couldn't find the device tree node!\n"); + ret = -ENODEV; + goto out_pci_disable_device; + } + + ret = of_property_read_u32(np, "irqnum", &irqnum); + if (ret < 0) + irqnum = 0; + + pdev->dev.of_node = np; + ret = tsfpga_add_ranges(pdev, np); + if (ret) + goto out_pci_disable_device; + + if (irqnum) { + ret = ts7800v2_irqc_enable(pdev, np, irqnum); + if (ret) { + dev_err(dev, "Couldn't enable TS-7800-V2 IRQs\n"); + goto out_pci_disable_device; + } + } + + if (of_property_read_bool(np, "pc104")) + ts7800v2_pc104on(pdev); + + return of_platform_default_populate(np, NULL, &pdev->dev); + +out_pci_disable_device: + pci_free_irq_vectors(pdev); + pci_disable_device(pdev); + pci_release_regions(pdev); + +out: + return ret; +} + +static void tsfpga_pci_remove(struct pci_dev *pdev) +{ + pci_free_irq_vectors(pdev); + pci_disable_device(pdev); + pci_release_regions(pdev); +} + +static int tsfpga_plat_driver_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + const char *name = dev_name(&pdev->dev); + int vendor, device, ret; + struct pci_driver *pci; + struct pci_device_id *id_table; + + ret = of_property_read_u32(np, "vendor", &vendor); + if (ret) { + pr_err("Missing pci vendor id"); + return -EINVAL; + } + + ret = of_property_read_u32(np, "device", &device); + if (ret) { + pr_err("Missing pci device id"); + return -EINVAL; + } + + pci = devm_kzalloc(dev, sizeof(struct pci_driver), GFP_KERNEL); + if (!pci) + return -ENOMEM; + + id_table = devm_kzalloc(dev, sizeof(struct pci_device_id)*2, GFP_KERNEL); + if (!id_table) + return -ENOMEM; + + id_table[0].vendor = vendor; + id_table[0].device = device; + id_table[0].subvendor = PCI_ANY_ID; + id_table[0].subdevice = PCI_ANY_ID; + + pci->name = name; + pci->probe = tsfpga_pci_probe; + pci->remove = tsfpga_pci_remove; + pci->id_table = id_table; + + ret = pci_register_driver(pci); + if (ret) { + pr_err("Could not register pci driver\n"); + return -EINVAL; + } + + return 0; +} + +static const struct of_device_id tsmfd_of_match_table[] = { + { .compatible = "technologic,ts78xx-mfd", }, + {}, +}; + +static struct platform_driver tsmfd_platform_driver = { + .driver = { + .name = "ts78xx_mfd", + .of_match_table = of_match_ptr(tsmfd_of_match_table), + }, + .probe = tsfpga_plat_driver_probe, +}; +module_platform_driver(tsmfd_platform_driver); + +MODULE_AUTHOR("Mark Featherston "); +MODULE_DESCRIPTION("TS-78XX Series FPGA MFD driver"); +MODULE_LICENSE("GPL v2"); From f10088e9dce041a4b426510f625b79a4bb00bc3e Mon Sep 17 00:00:00 2001 From: Michael Peters Date: Thu, 16 Mar 2023 16:04:25 -0700 Subject: [PATCH 061/244] mmc: host: tssdcard: Add support for tssdcore2 controller --- drivers/mmc/host/Kconfig | 7 + drivers/mmc/host/Makefile | 1 + drivers/mmc/host/tssdcard.c | 624 ++++++++ drivers/mmc/host/tssdcore2.c | 2658 ++++++++++++++++++++++++++++++++++ 4 files changed, 3290 insertions(+) create mode 100644 drivers/mmc/host/tssdcard.c create mode 100644 drivers/mmc/host/tssdcore2.c diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index c94ae4794545d..f2c6ebb39ac43 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -5,6 +5,13 @@ comment "MMC/SD/SDIO Host Controller Drivers" +config TS_SDCARD + tristate "SD Card support for embeddedTS sdcore v2" + depends on MFD_TS78XX + help + SD Card support for embeddedTS SD Card core + on TS-7800-V2 platform. + config MMC_DEBUG bool "MMC host drivers debugging" depends on MMC != n diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile index 5057fea8afb69..1c2122614d40c 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -112,5 +112,6 @@ ifeq ($(CONFIG_CB710_DEBUG),y) CFLAGS-cb710-mmc += -DDEBUG endif +obj-$(CONFIG_TS_SDCARD) += tssdcard.o obj-$(CONFIG_MMC_SDHCI_XENON) += sdhci-xenon-driver.o sdhci-xenon-driver-y += sdhci-xenon.o sdhci-xenon-phy.o diff --git a/drivers/mmc/host/tssdcard.c b/drivers/mmc/host/tssdcard.c new file mode 100644 index 0000000000000..c9143f22b3cd4 --- /dev/null +++ b/drivers/mmc/host/tssdcard.c @@ -0,0 +1,624 @@ +// SPDX-License-Identifier: GPL-2.0 + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static int poll_rate = 1; +module_param(poll_rate, int, 0644); +MODULE_PARM_DESC(poll_rate, + "Rate in seconds to poll for SD card. Defaults to 1\n"); + +static int disable_poll; +module_param(disable_poll, int, 0644); +MODULE_PARM_DESC(disable_poll, + "Set to non-zero to only check for SD once on startup\n"); + +#define DRIVER_NAME "tssdcard" + +/* + * Current use of this driver only includes TS-7800-V2 + * but TS-7250-V2 could use up to 3 + */ +#define MAX_SDS 3 + +#define SDPEEK8(sd, x) readb((uint32_t *)((sd)->sd_regstart + (x))) +#define SDPOKE8(sd, x, y) writeb(y, (uint32_t *)((sd)->sd_regstart + (x))) +#define SDPEEK16(sd, x) readw((uint32_t *)((sd)->sd_regstart + (x))) +#define SDPOKE16(sd, x, y) writew(y, (uint32_t *)((sd)->sd_regstart + (x))) +#define SDPEEK32(sd, x) readl((uint32_t *)((sd)->sd_regstart + (x))) +#define SDPOKE32(sd, x, y) writel(y, (uint32_t *)((sd)->sd_regstart + (x))) + +/* Disable probing for eMMC, we only connect this core here to SD */ +#define SD_NOMMC +#define SD_NOAUTOMMC + +/* Layer includes low level hardware support */ +#include "tssdcore2.c" + +static DEFINE_MUTEX(tssdcore_lock); +static struct semaphore sem; +static atomic_t busy; + +struct tssdcard_dev { + struct device *dev; + struct sdcore tssdcore; + char *devname; + sector_t sectors; + struct gendisk *gd; + struct bio *bio; + struct bio *biotail; + spinlock_t lock; + atomic_t users; /* How many users */ + struct task_struct *thread; + wait_queue_head_t event; + struct work_struct diskpoll_work; + struct workqueue_struct *diskpoll_queue; + struct timer_list cd_timer; + unsigned long timeout; + unsigned long lasttimeout; + int cardpresent; + int lasterr; + int major; +}; + +struct tssdcard_host { + struct platform_device *pdev; + struct resource *mem_res; + void __iomem *base; + int numluns; + struct tssdcard_dev luns[MAX_SDS]; +}; + +void tssdcard_debug(void *arg, + unsigned int code, + const char *func, + unsigned int line, ...) +{ + struct tssdcard_dev *dev = (struct tssdcard_dev *)arg; + va_list ap; + unsigned int s, x, y, z; + + /* Only print each message once */ + if (dev->lasterr == code) + return; + dev->lasterr = code; + + va_start(ap, line); + switch (code) { + case SD_HW_TMOUT: + s = va_arg(ap, unsigned int); /* sector */ + x = va_arg(ap, unsigned int); /* reg val */ + pr_info("SD hardware timeout, sect=%u (0x%x)\n", s, x); + break; + case SD_DAT_BAD_CRC: + s = va_arg(ap, unsigned int); /* sector */ + x = va_arg(ap, unsigned int); /* reg val */ + pr_info("SD hw detected bad CRC16, sect=%u (0x%x)\n", s, x); + break; + case READ_FAIL: + s = va_arg(ap, unsigned int); /* sector */ + pr_info("SD read failed, sect=%u\n", s); + break; + case WRITE_FAIL: + s = va_arg(ap, unsigned int); /* sector */ + x = va_arg(ap, unsigned int); /* sdcmd() ret status */ + pr_info("SD write failed, sect=%u (0x%x)\n", s, x); + break; + case SD_STOP_FAIL: + x = va_arg(ap, unsigned int); /* sdcmd() ret status */ + pr_info("SD stop transmission failed (0x%x)\n", x); + break; + case SD_RESP_FAIL: + x = va_arg(ap, unsigned int); /* SD cmd */ + y = va_arg(ap, unsigned int); /* response status */ + pr_info("SD cmd 0x%x resp code has err bits 0x%x\n", x, y); + break; + case SD_RESP_BAD_CRC: + x = va_arg(ap, unsigned int); /* SD cmd */ + y = va_arg(ap, unsigned int); /* calculated */ + z = va_arg(ap, unsigned int); /* rx'ed */ + pr_info("SD cmd 0x%x resp bad crc (0x%x != 0x%x)\n", x, y, z); + break; + case SD_RESP_WRONG_REQ: + x = va_arg(ap, unsigned int); /* SD cmd */ + y = va_arg(ap, unsigned int); /* cmd in response */ + pr_info("SD response for wrong cmd. (0x%x != 0x%x)\n", x, y); + break; + case SD_SW_TMOUT: + if (dev->cardpresent) + pr_info("SD soft timeout(%pS)\n", + __builtin_return_address(0)); + break; + } + va_end(ap); +} + +static void tssdcard_add_bio(struct tssdcard_dev *dev, struct bio *bio) +{ + spin_lock(&dev->lock); + if (dev->biotail) { + dev->biotail->bi_next = bio; + dev->biotail = bio; + } else { + dev->bio = dev->biotail = bio; + } + spin_unlock(&dev->lock); +} + +static struct bio *tssdcard_get_bio(struct tssdcard_dev *dev) +{ + struct bio *bio; + + spin_lock(&dev->lock); + bio = dev->bio; + if (bio) { + if (bio == dev->biotail) + dev->biotail = NULL; + dev->bio = bio->bi_next; + bio->bi_next = NULL; + } + spin_unlock(&dev->lock); + return bio; +} + +static void tssdcard_reset_timeout(void *data) +{ + struct sdcore *sd = (struct sdcore *)data; + struct tssdcard_dev *dev = (struct tssdcard_dev *)sd->os_arg; + + /* SD Spec allows 1 second for cards to answer */ + dev->timeout = jiffies + HZ; +} + +static int tssdcard_transfer(struct tssdcard_dev *dev, unsigned long sector, + unsigned long nsect, char *buffer, int rw) +{ + int ret = 0; + + dev_dbg(dev->dev, "%s size:%lld sector:%lu nsect:%lu rw:%d\n", + __func__, (long long)dev->sectors, sector, nsect, rw); + + tssdcard_reset_timeout(&dev->tssdcore); + switch (rw) { + case WRITE: + ret = sdwrite(&dev->tssdcore, sector, buffer, nsect); + if (ret && !dev->tssdcore.sd_wprot) { + if (sdreset(&dev->tssdcore) != 0) { + tssdcard_reset_timeout(&dev->tssdcore); + ret = sdwrite(&dev->tssdcore, sector, + buffer, nsect); + } + } + break; + + case READ: + //case READA: + ret = sdread(&dev->tssdcore, sector, buffer, nsect); + if (ret) { + if (sdreset(&dev->tssdcore) != 0) { + tssdcard_reset_timeout(&dev->tssdcore); + ret = sdread(&dev->tssdcore, sector, + buffer, nsect); + } + } + } + + return ret; +} + +static void tssdcard_handle_bio(struct tssdcard_dev *dev, struct bio *bio) +{ + struct bio_vec bvec; + struct bvec_iter iter; + sector_t sector, end_sector, n_sectors; + char *buffer; + int ret = 0; + + sector = bio->bi_iter.bi_sector; + end_sector = (bio->bi_iter.bi_sector) + (bio->bi_iter.bi_size >> 9) - 1; + + if ((bio->bi_iter.bi_size % 512) != 0) + panic("Invalid transfer, bi_size 512 != 0\n"); + + bio_for_each_segment(bvec, bio, iter) { + if ((sector + (bvec.bv_len >> 9)) > end_sector) + n_sectors = end_sector - sector + 1; + else + n_sectors = bvec.bv_len >> 9; + if (n_sectors == 0) + continue; + + buffer = kmap(bvec.bv_page) + bvec.bv_offset; + ret = tssdcard_transfer(dev, sector, n_sectors, buffer, + bio_data_dir(bio)); + sector += n_sectors; + kunmap(bvec.bv_page); + } + + bio_endio(bio); + + if (ret) { + dev->cardpresent = 0; + queue_work(dev->diskpoll_queue, + &dev->diskpoll_work); + } +} + +static void tssdcard_delay(void *data, unsigned int us) +{ + if (us > 50000) + msleep_interruptible(us/1000); + else + udelay(us); +} + +static int tssdcard_timeout_relaxed(void *data) +{ + struct sdcore *sd = (struct sdcore *)data; + struct tssdcard_dev *dev = (struct tssdcard_dev *)sd->os_arg; + int ret; + + dev->lasttimeout = jiffies; + + if (jiffies_to_msecs(dev->timeout - jiffies) > 50) + msleep_interruptible(10); + + ret = time_is_before_jiffies(dev->timeout); + + return ret; +} + +static int tssdcard_timeout(void *data) +{ + struct sdcore *sd = (struct sdcore *)data; + struct tssdcard_dev *dev = (struct tssdcard_dev *)sd->os_arg; + int ret; + + dev->lasttimeout = jiffies; + ret = time_is_before_jiffies(dev->timeout); + + return ret; +} + +static void tssdcard_irqwait(void *data, unsigned int x) +{ + struct tssdcard_dev *dev = (struct tssdcard_dev *)data; + uint32_t reg; + + do { +#ifdef CONFIG_PREEMPT_NONE + /* Default marvell kernel config has no preempt, so + * to support that: + */ + cond_resched(); +#endif + reg = readl((uint32_t *)(dev->tssdcore.sd_regstart + 0x108)); + } while ((reg & 4) == 0); +} + +static void tssdcard_release(struct gendisk *disk) +{ + struct tssdcard_dev *dev = disk->private_data; + + atomic_dec(&dev->users); + if (atomic_read(&dev->users) == 0) { + if (dev->thread != NULL) { + char buffer[512]; + int ret; + + kthread_stop(dev->thread); + dev->thread = NULL; + if (dev->sectors) { + tssdcard_reset_timeout(&dev->tssdcore); + ret = sdread(&dev->tssdcore, 0, buffer, 1); + } + } + } +} + +static int tssdcard_peek_bio(struct tssdcard_dev *dev) +{ + int ret = 0; + + spin_lock(&dev->lock); + if (dev->bio != NULL) + ret = 1; + spin_unlock(&dev->lock); + + return ret; +} + +static int tssdcard_thread(void *data) +{ + struct tssdcard_dev *dev = data; + struct bio *bio; + + while (!kthread_should_stop()) { + wait_event_interruptible(dev->event, + tssdcard_peek_bio(dev) || + kthread_should_stop()); + + if (down_interruptible(&sem)) + continue; + + atomic_inc(&busy); + if (atomic_read(&busy) > 1) + panic("recursive make_request!\n"); + + bio = tssdcard_get_bio(dev); + if (bio) + tssdcard_handle_bio(dev, bio); + + atomic_dec(&busy); + up(&sem); + } + + return 0; +} + +static int tssdcard_open(struct gendisk *gd, fmode_t mode) +{ + struct tssdcard_dev *dev = gd->private_data; + + if (!atomic_read(&dev->users)) + disk_check_media_change(gd); + atomic_inc(&dev->users); + if (dev->thread == NULL && atomic_read(&dev->users)) { + dev->thread = kthread_create(tssdcard_thread, + dev, dev->devname); + if (IS_ERR(dev->thread)) + dev->thread = NULL; + else + wake_up_process(dev->thread); + } + + return 0; +} + +static void tssdcard_make_request(struct bio *bio) +{ + struct tssdcard_dev *dev = bio->bi_bdev->bd_disk->private_data; + + tssdcard_add_bio(dev, bio); + wake_up(&dev->event); +} + +static int tssdcard_getgeo(struct block_device *bdev, struct hd_geometry *geo) +{ + struct tssdcard_dev *dev = bdev->bd_disk->private_data; + + geo->cylinders = dev->sectors >> 9 / (4 * 16); + geo->heads = 4; + geo->sectors = 16; + return 0; +} + +static const struct block_device_operations tssdcard_ops = { + .owner = THIS_MODULE, + .open = tssdcard_open, + .release = tssdcard_release, + .getgeo = tssdcard_getgeo, + .submit_bio = tssdcard_make_request, +}; + +static void tssdcard_alloc_disk(struct tssdcard_dev *dev) +{ + dev->bio = dev->biotail = NULL; + + dev->gd = blk_alloc_disk(CONFIG_MMC_BLOCK_MINORS); + if (dev->gd == NULL) { + pr_err(DRIVER_NAME ": Failed to alloc_disk"); + return; + } + + strcpy(dev->gd->disk_name, dev->devname); + + blk_queue_flag_set(QUEUE_FLAG_NONROT, dev->gd->queue); + + set_capacity(dev->gd, dev->sectors); + dev->gd->flags = 0; + dev->gd->fops = &tssdcard_ops; + dev->gd->private_data = dev; + + /* Check disk WP */ + set_disk_ro(dev->gd, dev->tssdcore.sd_wprot); + + /* FIXME: This return should be checked, generates warning right now. */ + add_disk(dev->gd); +} +static void tssdcard_cleanup_disk(struct tssdcard_dev *dev) +{ + pr_info("SD card was removed!\n"); + del_gendisk(dev->gd); + put_disk(dev->gd); + dev->sectors = 0; +} + +static void diskpoll_thread(struct work_struct *work) +{ + struct tssdcard_dev *dev = container_of(work, struct tssdcard_dev, + diskpoll_work); + + if (!dev->cardpresent && dev->sectors != 0) + tssdcard_cleanup_disk(dev); + else + dev->sectors = sdreset(&dev->tssdcore); + + if (dev->sectors == 0) { + dev->tssdcore.os_timeout = tssdcard_timeout_relaxed; + if (!disable_poll) + mod_timer(&dev->cd_timer, jiffies + (HZ * poll_rate)); + } else { + dev->cardpresent = 1; + dev->tssdcore.os_timeout = tssdcard_timeout; + tssdcard_alloc_disk(dev); + } +} + +static void tssdcard_card_poll(struct timer_list *t) +{ + struct tssdcard_dev *dev = from_timer(dev, t, cd_timer); + + queue_work(dev->diskpoll_queue, &dev->diskpoll_work); +} + +static int setup_device(struct tssdcard_host *host, int lun) +{ + int ret = 0; + struct tssdcard_dev *dev = &host->luns[lun]; + + dev->dev = &host->pdev->dev; + /* IO Remapping (use the same virtual address for all LUNs) */ + dev->tssdcore.sd_regstart = (unsigned int)host->base; + dev->tssdcore.sd_lun = lun; + dev->tssdcore.os_timeout = tssdcard_timeout; + dev->tssdcore.os_reset_timeout = tssdcard_reset_timeout; + dev->tssdcore.os_arg = dev; + dev->tssdcore.os_delay = tssdcard_delay; + dev->tssdcore.os_irqwait = tssdcard_irqwait; + dev->tssdcore.sd_writeparking = 1; + dev->tssdcore.debug = tssdcard_debug; + dev->tssdcore.debug_arg = dev; + dev->major = register_blkdev(UNNAMED_MAJOR, DRIVER_NAME); + + dev->devname = kmalloc(32, GFP_KERNEL); + if (!dev->devname) + return -ENOMEM; + snprintf(dev->devname, 32, "%s%c", DRIVER_NAME, lun + 'a'); + + init_waitqueue_head(&dev->event); + sema_init(&sem, 1); + atomic_set(&busy, 0); + spin_lock_init(&dev->lock); + + /* sdreset sleeps so we need our own workqueue */ + dev->diskpoll_queue = alloc_ordered_workqueue(dev->devname, 0); + if (!dev->diskpoll_queue) + return -ENOMEM; + + INIT_WORK(&dev->diskpoll_work, diskpoll_thread); + + timer_setup(&dev->cd_timer, tssdcard_card_poll, 0); + + /* Start polling for the card */ + queue_work(dev->diskpoll_queue, + &dev->diskpoll_work); + + return ret; +} + +static int tssdcard_probe(struct platform_device *pdev) +{ + int i, ret = 0; + struct tssdcard_host *host; + struct resource *res = 0; + + host = kzalloc(sizeof(struct tssdcard_host), GFP_KERNEL); + if (host == NULL) { + ret = -ENOMEM; + goto out; + } + + host->numluns = 1; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!devm_request_mem_region(&pdev->dev, res->start, + resource_size(res), pdev->name)) { + ret = -EBUSY; + goto out; + } + + host->base = devm_ioremap(&pdev->dev, res->start, + resource_size(res)); + if (!host->base) { + ret = -EFAULT; + goto out; + } + + for (i = 0; i < host->numluns; i++) { + ret = setup_device(host, i); + if (ret) + goto out; + } + + platform_set_drvdata(pdev, host); + + return 0; + +out: + return ret; +} + +static int tssdcard_remove(struct platform_device *pdev) +{ + struct tssdcard_host *host = (struct tssdcard_host *)pdev->dev.p; + int i; + + for (i = 0; i < host->numluns; i++) { + struct tssdcard_dev *dev = &host->luns[i]; + + dev_dbg(dev->dev, "dev[%d] ...\n", i); + + if (dev->sectors == 0) + continue; + + if (dev->gd) + put_disk(dev->gd); + + unregister_blkdev(NBD_MAJOR, "nbd"); + kfree(dev->devname); + } + return 0; +} + +static const struct platform_device_id tssdcard_devtype[] = { + { + .name = "tssdcard-mmc", + }, { + /* sentinel */ + } +}; +MODULE_DEVICE_TABLE(platform, tssdcard_devtype); + +static const struct of_device_id tssdcard_of_match[] = { + { + .compatible = "technologic,tssdcard", + } +}; + +static struct platform_driver tssdcard_driver = { + .probe = tssdcard_probe, + .remove = tssdcard_remove, + .driver = { + .name = DRIVER_NAME, + .of_match_table = tssdcard_of_match, + } +}; + +module_platform_driver(tssdcard_driver); + +MODULE_DESCRIPTION("TS-7800-V2 SDHC Driver"); +MODULE_AUTHOR("Ian Coughlan, Technologic Systems"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:tssdcard"); diff --git a/drivers/mmc/host/tssdcore2.c b/drivers/mmc/host/tssdcore2.c new file mode 100644 index 0000000000000..9b81198c1c5f6 --- /dev/null +++ b/drivers/mmc/host/tssdcore2.c @@ -0,0 +1,2658 @@ +/* + * Copyright (c) 2006-2012, Technologic Systems + * All rights reserved. + */ + +/* + * This code is 100% operating system/CPU independent-- not a single global + * reference, external symbol, or #include is required. Centric upon one data + * structure "struct sdcore". OS-specific callbacks for things like DMA + * acceleration and sleeping are defined by function pointers to OS-specific + * code in the struct sdcore. Minimally requires the os_sleep() callback to be + * implemented for proper SD card initialization and a pointer to start + * of SD card registers. Auto-determines TS SD core version. All other + * callback functions may be left NULL-- they are only to allow speed/CPU + * utilization improvements. + * + * 3 main public functions - sdreset(), sdread() and sdwrite(). sdreset() + * returns card size. + * + * Not all SD cards over the years have followed spec perfectly -- many + * don't even check CRC's on the CMD or DAT busses and some have problems + * (lock up) when reading/writing the last sectors with SD read/write multiple + * commands. + * + * The TS SD hardware cores are not much more than GPIO bit-bang cores with + * a few well-placed hardware optimizations to achieve reasonable + * performance goals. In the roughly 2500 lines of code that follow, there + * is support for all distinct TS hardware SD cores on PPC and ARM platforms, + * a generic (private) SD command layer, sdcmd(), and SD flash card + * (public) routines for initialization + read/write + some SD security + * features. + * + */ + +/* Register offset definitions. TS-SDCORE is 4 regs total. */ +#define SDCMD 0 +#define SDGPIO 0 /* version 2 register */ +#define SDDAT 1 +#define SDSTAT2 1 +#define SDSTATE 2 +#define SDCTRL 3 +#define SDDAT2 4 +#define SDCMD2 8 +#define SDCTRL2 12 +#define SDLUN2 2 + +struct sdcore { + /* virtual address of SD block register start, to be filled in + * by client code before calling any sdcore functions. + */ + size_t sd_regstart; + + /* public bits for sd_state bitfield, can be read from client code. + * Do not write! Other bits are used internally. + */ + #define SDDAT_RX (1<<0) + #define SDDAT_TX (1<<1) + #define SDCMD_RX (1<<2) + #define SDCMD_TX (1<<3) + unsigned int sd_state; + + /* Erase hint for subsequent sdwrite() call, used to optimize + * write throughput on multi-sector writes by pre-erasing this + * many sectors. XXX: this doesn't have much benefit on most SDs + */ + unsigned int sd_erasehint; + + int refcnt; + + /* Following this comment are 3 function pointer declarations to + * OS helper functions. The 'os_arg' member is passed as the + * first argument to the helpers and should be set by + * client code before issueing sdreset() + * + * os_dmastream(os_arg, buf, buflen) + * This function should look at sd_state and set up and run an + * appropriate DMA transfer. If buf is NULL, callee doesn't care + * about the actual data sent/received and helper function + * can do whatever it wants. Should return 0 when DMA transfer was + * run and completed successfully. If this function pointer is + * NULL, PIO methods of transfer will be used instead of DMA. + * + * os_dmaprep(os_arg, buf, buflen) + * This function is used to prepare an area of memory for a possible + * DMA transfer. This function is called once per distinct buffer + * passed in. After this function is called, os_dmastream() may be + * called one or more times (for sequential addresses) on subregions + * of the address range passed here. Should write-back or invalidate + * L1 cache lines and possibly look up physical addresses for buf + * passed in if I/O buffers. If 'os_dmaprep' is set to NULL, function + * call will not happen. (though os_dmastream() calls may still) + * + * os_delay(os_arg, microseconds) + * This function is supposed to delay or stall the processor for + * the passed in value number of microseconds. + */ + void *os_arg; + int (*os_dmastream)(void *, unsigned char *, unsigned int); + void (*os_dmaprep)(void *, unsigned char *, unsigned int); + void (*os_delay)(void *, unsigned int); + void (*os_irqwait)(void *, unsigned int); + int (*os_powerok)(void *); + int (*os_timeout)(void *); + void (*os_reset_timeout)(void *); + + /* If the SD card last successfully reset is write protected, this + * member will be non-zero. + */ + unsigned int sd_wprot; + + /* If this card may have been already initialized by TS-SDBOOT, place + * the magic token it placed in the EP93xx SYSCON ScratchReg1 here + * to avoid re-initialization. + */ + unsigned int sdboot_token; + + /* CRC hint for subsequent sdwrite() call, used to optimize + * write throughput while using DMA by pre-calculating CRC's for + * next write + */ + unsigned char *sd_crchint; + + /* The block size of the memory device. Normally 512, but can be 1024 + * for larger cards + */ + unsigned int sd_blocksize; + + /* Password for auto-unlocking in sdreset() + */ + unsigned char *sd_pwd; + + /* If the SD card was password locked, this will be non-zero. + */ + unsigned int sd_locked; + + /* Whether or not writes can be parked. + */ + unsigned int sd_writeparking; + + /* Logical unit number. Some SD cores will have multiple card slots. + */ + unsigned int sd_lun; + + /* Whether or not we use the multiple block SD write command. + */ + unsigned int sd_nomultiwrite; + + /* Debug callback for extra info */ + void (*debug)(void *, unsigned int, const char *, unsigned int, ...); + void *debug_arg; + + /* The rest of these members are for private internal use and should + * not be of interest to client code. + */ + unsigned int sd_rcaarg; + unsigned int sd_csd[17]; + unsigned int sd_crcseq; + unsigned short sd_crcs[4]; + unsigned int sd_crctmp[4]; + unsigned int sd_timeout; + unsigned int parked_sector; + unsigned int hw_version; + unsigned char sd_scr[8]; + unsigned int sd_sz; + unsigned char sd_type; +}; + +enum { WRITE_FAIL, READ_FAIL, SD_RESP_WRONG_REQ, SD_RESP_BAD_CRC, SD_RESP_FAIL, + SD_HW_TMOUT, SD_SW_TMOUT, SD_DAT_BAD_CRC, SD_STOP_FAIL }; + +#ifndef SDCORE_NDEBUG +#define DBG(x, ...) if (sd->debug) sd->debug(sd->debug_arg, x, __FUNCTION__, __LINE__, ## __VA_ARGS__) +#else +#define DBG(x, ...) +#endif + +/* For sdreadv() / sdwritev() */ +struct sdiov { + unsigned char *sdiov_base; + unsigned int sdiov_nsect; +}; + +int sdreset(struct sdcore *); +int sdread(struct sdcore *, unsigned int, unsigned char *, int); +int sdwrite(struct sdcore *, unsigned int, unsigned char *, int); +int sdreadv(struct sdcore *, unsigned int, struct sdiov *, int); +int sdwritev(struct sdcore *, unsigned int, struct sdiov *, int); +int sdsetwprot(struct sdcore *, unsigned int); +#define SDLOCK_UNLOCK 0 +#define SDLOCK_SETPWD 1 +#define SDLOCK_CLRPWD 2 +#define SDLOCK_ERASE 8 +#ifndef SD_NOLOCKSUPPORT +int sdlockctl(struct sdcore *, unsigned int, unsigned char *, unsigned char *); +#endif + +/* + * Everything below here is secret! This code shouldn't have to change + * even for different OS. + */ + +static const unsigned short crc16tbl[256] = { + 0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7, + 0x8108, 0x9129, 0xa14a, 0xb16b, 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef, + 0x1231, 0x0210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6, + 0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de, + 0x2462, 0x3443, 0x0420, 0x1401, 0x64e6, 0x74c7, 0x44a4, 0x5485, + 0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d, + 0x3653, 0x2672, 0x1611, 0x0630, 0x76d7, 0x66f6, 0x5695, 0x46b4, + 0xb75b, 0xa77a, 0x9719, 0x8738, 0xf7df, 0xe7fe, 0xd79d, 0xc7bc, + 0x48c4, 0x58e5, 0x6886, 0x78a7, 0x0840, 0x1861, 0x2802, 0x3823, + 0xc9cc, 0xd9ed, 0xe98e, 0xf9af, 0x8948, 0x9969, 0xa90a, 0xb92b, + 0x5af5, 0x4ad4, 0x7ab7, 0x6a96, 0x1a71, 0x0a50, 0x3a33, 0x2a12, + 0xdbfd, 0xcbdc, 0xfbbf, 0xeb9e, 0x9b79, 0x8b58, 0xbb3b, 0xab1a, + 0x6ca6, 0x7c87, 0x4ce4, 0x5cc5, 0x2c22, 0x3c03, 0x0c60, 0x1c41, + 0xedae, 0xfd8f, 0xcdec, 0xddcd, 0xad2a, 0xbd0b, 0x8d68, 0x9d49, + 0x7e97, 0x6eb6, 0x5ed5, 0x4ef4, 0x3e13, 0x2e32, 0x1e51, 0x0e70, + 0xff9f, 0xefbe, 0xdfdd, 0xcffc, 0xbf1b, 0xaf3a, 0x9f59, 0x8f78, + 0x9188, 0x81a9, 0xb1ca, 0xa1eb, 0xd10c, 0xc12d, 0xf14e, 0xe16f, + 0x1080, 0x00a1, 0x30c2, 0x20e3, 0x5004, 0x4025, 0x7046, 0x6067, + 0x83b9, 0x9398, 0xa3fb, 0xb3da, 0xc33d, 0xd31c, 0xe37f, 0xf35e, + 0x02b1, 0x1290, 0x22f3, 0x32d2, 0x4235, 0x5214, 0x6277, 0x7256, + 0xb5ea, 0xa5cb, 0x95a8, 0x8589, 0xf56e, 0xe54f, 0xd52c, 0xc50d, + 0x34e2, 0x24c3, 0x14a0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405, + 0xa7db, 0xb7fa, 0x8799, 0x97b8, 0xe75f, 0xf77e, 0xc71d, 0xd73c, + 0x26d3, 0x36f2, 0x0691, 0x16b0, 0x6657, 0x7676, 0x4615, 0x5634, + 0xd94c, 0xc96d, 0xf90e, 0xe92f, 0x99c8, 0x89e9, 0xb98a, 0xa9ab, + 0x5844, 0x4865, 0x7806, 0x6827, 0x18c0, 0x08e1, 0x3882, 0x28a3, + 0xcb7d, 0xdb5c, 0xeb3f, 0xfb1e, 0x8bf9, 0x9bd8, 0xabbb, 0xbb9a, + 0x4a75, 0x5a54, 0x6a37, 0x7a16, 0x0af1, 0x1ad0, 0x2ab3, 0x3a92, + 0xfd2e, 0xed0f, 0xdd6c, 0xcd4d, 0xbdaa, 0xad8b, 0x9de8, 0x8dc9, + 0x7c26, 0x6c07, 0x5c64, 0x4c45, 0x3ca2, 0x2c83, 0x1ce0, 0x0cc1, + 0xef1f, 0xff3e, 0xcf5d, 0xdf7c, 0xaf9b, 0xbfba, 0x8fd9, 0x9ff8, + 0x6e17, 0x7e36, 0x4e55, 0x5e74, 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0, +}; + +static const unsigned char destagger[256] = { + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, + 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, + 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, + 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, + 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, + 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, + 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, + 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, + 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, +}; + +#ifndef MAX_SDCORES +#define MAX_SDCORES 64 +#endif +static struct sdcore *sdcores[MAX_SDCORES]; + +#ifndef SD_NOMMC +static int mmcreset2(struct sdcore *); +#endif + +static int sdreset2(struct sdcore *); +static int version(struct sdcore *); +static int sdfastinit(struct sdcore *sd); +static int sdcmd2(struct sdcore *, unsigned short, unsigned int, + unsigned int *, unsigned char **); +static int sdcmd(struct sdcore *, unsigned short, unsigned int, + unsigned int *, unsigned char **); +static void mkcommand(unsigned int, unsigned int, unsigned int *); +static int stop(struct sdcore *); +static int stop2(struct sdcore *); +static int sdread2(struct sdcore *, unsigned int, unsigned char *, int) + __attribute__ ((unused)); +static int do_read2(struct sdcore *, unsigned int, struct sdiov *, + unsigned int); +static int do_read(struct sdcore *, unsigned int, struct sdiov *, + unsigned int); +static int do_write(struct sdcore *, unsigned int, struct sdiov *, + unsigned int); +static int do_write2(struct sdcore *, unsigned int, struct sdiov *, + unsigned int); +static int sdsetwprot2(struct sdcore *, unsigned int); +#ifndef SD_NOLOCKSUPPORT +static int sdlockctl2(struct sdcore *, unsigned int, unsigned char *, + unsigned char *); +#endif + +#ifndef SDPOKE8 +# define SDPOKE8(sd, x, y) \ + *(volatile unsigned char *)((sd)->sd_regstart + (x)) = (y) +#endif +#ifndef SDPOKE32 +# define SDPOKE32(sd, x, y) \ + *(volatile unsigned int *)((sd)->sd_regstart + (x)) = (y) +#endif +#ifndef SDPOKE16 +# define SDPOKE16(sd, x, y) \ + *(volatile unsigned short *)((sd)->sd_regstart + (x)) = (y) +#endif +#ifndef SDPEEK8 +# define SDPEEK8(sd, x) *(volatile unsigned char *)((sd)->sd_regstart + (x)) +#endif +#ifndef SDPEEK32 +# define SDPEEK32(sd, x) *(volatile unsigned int *)((sd)->sd_regstart + (x)) +#endif +#ifndef SDPEEK16 +# define SDPEEK16(sd, x) *(volatile unsigned short *)((sd)->sd_regstart + (x)) +#endif + +#define S_DUMMY_CLK 0 +#define S_SEND_CMD 1 +#define S_WAIT_RESP 2 +#define S_RX_RESP 3 +#define S_WAIT_BUSY 4 +#define S_TX_WRITE 5 +#define S_CRC_CHECK 6 +#define S_OFF 7 + +#define TYPE_SHORTRESP 2 +#define TYPE_LONGRESP 3 +#define TYPE_BSYRESP 4 +#define TYPE_NORESP 1 +#define TYPE_RXDAT 0 +#define TYPE_TXDAT 5 +#define TYPE_ABORT 6 +#define TYPE_RXDAT_IGNRESP 7 + +#define CMD(idx, type) (0x40 | (idx) | ((type)<<8)) + +#define CMD_GO_IDLE_STATE CMD(0, TYPE_NORESP) +#define CMD_MMC_SEND_OP_COND CMD(1, TYPE_SHORTRESP) +#define CMD_ALL_SEND_CID CMD(2, TYPE_LONGRESP) +#define CMD_SEND_RELATIVE_ADDR CMD(3, TYPE_SHORTRESP) +#define CMD_MMC_SET_RELATIVE_ADDR CMD(3, TYPE_SHORTRESP) +#define CMD_MMC_SWITCH CMD(6, TYPE_BSYRESP) +#define CMD_SWITCH_FUNC CMD(6, TYPE_RXDAT) +#define CMD_SWITCH_FUNC2 CMD(6, TYPE_RXDAT_IGNRESP) +#define CMD_SELECT_CARD CMD(7, TYPE_BSYRESP) +#define CMD_DESELECT_CARD CMD(7, TYPE_NORESP) +#define CMD_SEND_IF_COND CMD(8, TYPE_SHORTRESP) +#define CMD_MMC_SEND_EXT_CSD CMD(8, TYPE_RXDAT_IGNRESP) +#define CMD_SEND_CSD CMD(9, TYPE_LONGRESP) +#define CMD_PROGRAM_CSD CMD(27, TYPE_TXDAT) +#define CMD_SET_BLOCKLEN CMD(16, TYPE_SHORTRESP) +#define CMD_LOCK_UNLOCK CMD(42, TYPE_TXDAT) +#define CMD_APP_CMD CMD(55, TYPE_SHORTRESP) +#define CMD_READ_SINGLE_BLOCK CMD(17, TYPE_RXDAT) +#define CMD_READ_MULTIPLE_BLOCK CMD(18, TYPE_RXDAT) +#define CMD_READ_MULTIPLE_BLOCK2 CMD(18, TYPE_RXDAT_IGNRESP) +#define CMD_STOP_TRANSMISSION CMD(12, TYPE_ABORT) +#define CMD_SEND_STATUS CMD(13, TYPE_SHORTRESP) +#define CMD_WRITE_BLOCK CMD(24, TYPE_TXDAT) +#define CMD_WRITE_MULTIPLE_BLOCK CMD(25, TYPE_TXDAT) + +#define ACMD_SD_SEND_OP_COND CMD(41, TYPE_SHORTRESP) +#define ACMD_SET_CLR_CARD_DETECT CMD(42, TYPE_SHORTRESP) +#define ACMD_SET_BUS_WIDTH CMD(6, TYPE_SHORTRESP) +#define ACMD_SET_WR_BLK_ERASE_COUNT CMD(23, TYPE_SHORTRESP) +#define ACMD_SEND_NUM_WR_BLOCKS CMD(22, TYPE_RXDAT) +#define ACMD_SEND_SCR CMD(51, TYPE_RXDAT) +#define ACMD_SEND_SCR2 CMD(51, TYPE_RXDAT_IGNRESP) + +/* Private bits for struct sdcore, sd_state member */ +#define DATSSP_NOCRC (1<<4) +#define DATSSP_4BIT (1<<5) +#define SD_HC (1<<6) +#define SD_HISPEED (1<<7) +#define SD_LOSPEED (1<<8) +#define SD_SELECTED (1<<9) +#define SD_RESET (1<<10) + +#ifndef NULL +#define NULL ((void *)0) +#endif + +static void remember_sdcore(struct sdcore *sd) { + int i, newlun = 0; + + for (i = 0; i < (sizeof(sdcores)/sizeof(sdcores[0])); i++) { + if (sdcores[i] == NULL) { + /* new core, first reset */ + sdcores[i] = sd; + /* core was almost definitely power-cycled on prev lun + * sdreset2(), so we don't need to have the sdreset2() + * do it again. + */ + if (newlun) sd->sd_state = SD_RESET; + break; + } else if (sdcores[i]->sd_regstart == sd->sd_regstart) { + newlun = 1; + if (sdcores[i]->sd_lun == sd->sd_lun) { + sdcores[i] = sd; + break; + } + } + } +} + +#if 0 +static void forget_sdcore(struct sdcore *sd) { + int i, found; + + for (found = i = 0; i < (sizeof(sdcores)/sizeof(sdcores[0])); i++) { + if (sdcores[i] == sd) found = 1; + if (found) sdcores[i] = + (i == sizeof(sdcores)/sizeof(sdcores[0]))?NULL:sdcores[i+1]; + } +} +#endif + +static int activate(struct sdcore *sd) { + int i; + + /* Are we already selected? */ + if ((sd->sd_state & (SD_SELECTED|SD_RESET)) == SD_SELECTED) + return 0; + + /* Find currently activated SD slot for this HW core */ + for (i = 0; i < (sizeof(sdcores)/sizeof(sdcores[0])); i++) { + if (sdcores[i] == NULL) break; + if (sdcores[i]->sd_regstart == sd->sd_regstart && + sdcores[i]->sd_state & SD_SELECTED) break; + } + + /* Stop whatever parked transfer it has going on. */ + if (sdcores[i]) { + stop2(sdcores[i]); + sdcores[i]->sd_state &= ~SD_SELECTED; + } + + /* Change clock routing, mark us as selected */ +#ifdef BIGENDIAN + SDPOKE16(sd, SDLUN2, sd->sd_lun << 8); +#else + SDPOKE16(sd, SDLUN2, sd->sd_lun); +#endif + + if (sd->sd_nomultiwrite) i = 0x8; else i = 0x18; + + /* Change clock frequency */ + if (sd->sd_state & SD_HISPEED) SDPOKE8(sd, SDSTAT2, i | 0x20); + else SDPOKE8(sd, SDSTAT2, i); + + sd->sd_state |= SD_SELECTED; + if (sd->sd_state & SD_RESET) return 1; + else return 0; +} + + +inline static unsigned short +crc16_acc(unsigned short crc, unsigned int b) { + return (crc << 8) ^ crc16tbl[(crc >> 8) ^ b]; +} + + +static void sd_initcrc(struct sdcore *sd) { + int i; + + for (i = 0; i < 4; i++) { + sd->sd_crctmp[i] = 0; + sd->sd_crcs[i] = 0; + } + sd->sd_crcseq = 6; +} + + +static void sd_1bit_feedcrc(struct sdcore *sd, unsigned int dat) { + sd->sd_crcs[0] = crc16_acc(sd->sd_crcs[0], dat); +} + + +static void sd_4bit_feedcrc(struct sdcore *sd, unsigned int dat) { + unsigned int a = 0, b = 0, c = 0, d = 0; + unsigned int shift = (sd->sd_crcseq & 0x7); + + a = sd->sd_crctmp[0]; + b = sd->sd_crctmp[1]; + c = sd->sd_crctmp[2]; + d = sd->sd_crctmp[3]; + + a |= destagger[dat] << shift; + dat >>= 1; + b |= destagger[dat] << shift; + dat >>= 1; + c |= destagger[dat] << shift; + dat >>= 1; + d |= destagger[dat] << shift; + + if (shift == 0) { + sd->sd_crcs[0] = crc16_acc(sd->sd_crcs[0], a); + sd->sd_crcs[1] = crc16_acc(sd->sd_crcs[1], b); + sd->sd_crcs[2] = crc16_acc(sd->sd_crcs[2], c); + sd->sd_crcs[3] = crc16_acc(sd->sd_crcs[3], d); + a = b = c = d = 0; + } + + sd->sd_crcseq -= 2; + sd->sd_crctmp[0] = a; + sd->sd_crctmp[1] = b; + sd->sd_crctmp[2] = c; + sd->sd_crctmp[3] = d; +} + + +/* This should be called 8 times to get the full 8 bytes of CRC generated */ +static unsigned int sd_4bit_getcrc(struct sdcore *sd) +{ + static const unsigned char restaggertbl[4] = { 0x0, 0x1, 0x10, 0x11 }; + static const unsigned char restaggertbl_lsl1[4] = + { 0x0, 0x2, 0x20, 0x22 }; + static const unsigned char restaggertbl_lsl2[4] = + { 0x0, 0x4, 0x40, 0x44 }; + static const unsigned char restaggertbl_lsl3[4] = + { 0x0, 0x8, 0x80, 0x88 }; + unsigned int ret; + + ret = restaggertbl[sd->sd_crcs[0] >> 14]; + sd->sd_crcs[0] <<= 2; + ret |= restaggertbl_lsl1[sd->sd_crcs[1] >> 14]; + sd->sd_crcs[1] <<= 2; + ret |= restaggertbl_lsl2[sd->sd_crcs[2] >> 14]; + sd->sd_crcs[2] <<= 2; + ret |= restaggertbl_lsl3[sd->sd_crcs[3] >> 14]; + sd->sd_crcs[3] <<= 2; + + return ret; +} + + +/* This should be called 2 times to get the full 2 bytes of CRC generated */ +static unsigned int sd_1bit_getcrc(struct sdcore *sd) +{ + unsigned int ret; + + ret = sd->sd_crcs[0] >> 8; + sd->sd_crcs[0] = (sd->sd_crcs[0] & 0xff) << 8; + return ret; +} + + +static inline void datssp_feedcrc(struct sdcore *sd, unsigned int dat) +{ + if (!(sd->sd_state & DATSSP_NOCRC)) { + if (sd->sd_state & DATSSP_4BIT) sd_4bit_feedcrc(sd, dat); + else sd_1bit_feedcrc(sd, dat); + } +} + + +static inline unsigned int datssp_getcrc(struct sdcore *sd) +{ + unsigned int ret = 0; + + if (!(sd->sd_state & DATSSP_NOCRC)) { + if (sd->sd_state & DATSSP_4BIT) ret = sd_4bit_getcrc(sd); + else ret = sd_1bit_getcrc(sd); + } + return ret; +} + + +static inline unsigned int +crc7(unsigned int crc, const unsigned int *pc, unsigned int len) { + unsigned int i; + unsigned char ibit; + unsigned char c; + + for (i = 0; i < len; i++, pc++) { + c = *pc; + for (ibit = 0; ibit < 8; ibit++) { + crc <<= 1; + if ((c ^ crc) & 0x80) crc ^= 0x09; + + c <<= 1; + } + + crc &= 0x7F; + } + + return crc; +} + + +static inline void +mkcommand(unsigned int cmdidx, unsigned int arg, unsigned int *retcmd) { + retcmd[0] = cmdidx; + retcmd[1] = arg >> 24; + retcmd[2] = arg >> 16; + retcmd[3] = arg >> 8; + retcmd[4] = arg; + retcmd[5] = (0x1 | (crc7(0, retcmd, 5) << 1)); +} + + +static inline void reset_timeout(struct sdcore *sd) { + sd->sd_timeout = 0; + if (sd->os_reset_timeout) sd->os_reset_timeout(sd); +} + + +static inline int timeout(struct sdcore *sd) { + int ret = 0; + if (sd->sd_timeout > 1000000) ret = 1; + else if (sd->os_timeout) ret = sd->os_timeout(sd); + else sd->sd_timeout++; + if (ret) DBG(SD_SW_TMOUT); + return ret; +} + + +static unsigned int sdsize(struct sdcore *sd) { + unsigned int csize, csize_mult, rd_bl_len; + + if (sd->sd_sz != 0) return sd->sd_sz; + + if (sd->sd_csd[1] & 0xc0) { + csize = (sd->sd_csd[10] | (sd->sd_csd[9] << 8) | + ((sd->sd_csd[8] & 0x3f) << 16)); + sd->sd_sz = (csize + 1) * 1024; + } else { + rd_bl_len = 1 << ((sd->sd_csd[6] & 0xf) - 9); + csize = ((sd->sd_csd[7] & 0x03) << 10) | + ((sd->sd_csd[8] << 2) | ((sd->sd_csd[9] & 0xc0) >> 6)); + csize_mult = ((sd->sd_csd[10] & 0x03) << 1) | + ((sd->sd_csd[11] & 0x80) >> 7); + sd->sd_sz = (csize + 1) * (1 << (csize_mult + 2)) * rd_bl_len; + } + return sd->sd_sz; +} + + +static unsigned int tend_ssp(struct sdcore *sd, unsigned int **cmdresp, + unsigned char **dat) { + unsigned int d; + unsigned int s = SDPEEK8(sd, SDSTATE); + + if (s & 0x8) { + if (sd->sd_state & SDCMD_RX) { + d = SDPEEK8(sd, SDCMD); + if (cmdresp) { + **cmdresp = d; + *cmdresp = *cmdresp + 1; + reset_timeout(sd); + } + } else if (sd->sd_state & SDCMD_TX) { + SDPOKE8(sd, SDCMD, **cmdresp); + *cmdresp = *cmdresp + 1; + reset_timeout(sd); + } + } + + if (s & 0x10) { + if (sd->sd_state & SDDAT_RX) { + d = SDPEEK8(sd, SDDAT); + if (dat) { + **dat = d; + *dat = *dat + 1; + reset_timeout(sd); + } + } else if (sd->sd_state & SDDAT_TX) { + reset_timeout(sd); + if (dat) { + d = **dat; + *dat = *dat + 1; + SDPOKE8(sd, SDDAT, d); + datssp_feedcrc(sd, d); + } else { + d = datssp_getcrc(sd); + SDPOKE8(sd, SDDAT, d); + } + } + } + + return s; +} + + +static int error(struct sdcore *sd, unsigned int *resp, unsigned short req) { + unsigned int crc, status, ret; + + if ((req & 0x3f) != resp[0]) { + DBG(SD_RESP_WRONG_REQ, req & 0x3f, resp[0]); + return 1; + } + + crc = (0x1 | (crc7(0, resp, 5) << 1)); + if (crc != resp[5]) { + DBG(SD_RESP_BAD_CRC, req & 0x3f, crc, resp[5]); + return 1; + } + + status = resp[1] << 24; + status |= resp[2] << 16; + status |= resp[3] << 8; + status |= resp[4]; + ret = status & 0xfdf90008; + if (ret) DBG(SD_RESP_FAIL, req & 0x3f, ret); + return ret; +} + + +static int +sdcmd2(struct sdcore *sd, unsigned short req, unsigned int arg, + unsigned int *resp, unsigned char **dat) { + unsigned int i, j, s, cmdresp[17]; + unsigned int resplen; + unsigned int type = (req >> 8); + unsigned int cmdidx = req; + unsigned int *cmdptr = cmdresp; + unsigned int *respptr; + unsigned int dly; + int ok32 = (sd->hw_version == 2); + int ok16 = (ok32 || (sd->hw_version == 3)); + int sddat2_8; + + // If no space for response provided by caller, use local buffer + if (resp == NULL) resp = cmdresp; + respptr = resp; + + if (activate(sd)) return 1; + + dly = sd->sd_state & SD_LOSPEED; + + if (!dly) { + unsigned int x; + SDPOKE8(sd, SDGPIO, 0xbf); +#ifdef BIGENDIAN + x = (cmdidx & 0xff); + x |= ((arg >> 24) & 0xff) << 8; + x |= ((arg >> 16) & 0xff) << 16; + x |= ((arg >> 8) & 0xff) << 24; + if (ok32) SDPOKE32(sd, SDCMD2, x); + else if (ok16) { + SDPOKE16(sd, SDCMD2, x); + SDPOKE16(sd, SDCMD2, x >> 16); + } else { + SDPOKE8(sd, SDCMD2, x); + SDPOKE8(sd, SDCMD2, x >> 8); + SDPOKE8(sd, SDCMD2, x >> 16); + SDPOKE8(sd, SDCMD2, x >> 24); + } +#else + x = (cmdidx & 0xff) << 24; + x |= ((arg >> 24) & 0xff) << 16; + x |= ((arg >> 16) & 0xff) << 8; + x |= ((arg >> 8) & 0xff); + if (ok32) SDPOKE32(sd, SDCMD2, x); + else if (ok16) { + SDPOKE16(sd, SDCMD2, x >> 16); + SDPOKE16(sd, SDCMD2, x); + } else { + SDPOKE8(sd, SDCMD2, x >> 24); + SDPOKE8(sd, SDCMD2, x >> 16); + SDPOKE8(sd, SDCMD2, x >> 8); + SDPOKE8(sd, SDCMD2, x); + } +#endif + SDPOKE8(sd, SDCMD2, arg); + } else { + // Build command packet + mkcommand(cmdidx, arg, cmdptr); + + // Send command + for (i = 0; i < 6; i++) { + unsigned int b = *cmdptr++; + unsigned int x; + + if (timeout(sd)) break; + for (j = 0; j < 8; j++) { + x = 0x8f | ((b & 0x80) >> 3); + b = b << 1; + SDPOKE8(sd, SDGPIO, x); // clk negedge + SDPEEK8(sd, SDGPIO); // delay + SDPEEK8(sd, SDGPIO); // delay + x |= 0x20; + SDPOKE8(sd, SDGPIO, x); // clk posedge + SDPEEK8(sd, SDGPIO); // delay + SDPEEK8(sd, SDGPIO); // delay + } + } + } + + if (type == TYPE_NORESP) goto done; + else if (type == TYPE_RXDAT_IGNRESP) goto ignresp; + else if (type == TYPE_LONGRESP) resplen = 17; + else resplen = 6; + + // clock until start bit on CMD pin + while(1) { + if (timeout(sd)) { + goto done; + } + if (req == CMD_SEND_IF_COND) sd->sd_timeout += 100000; + SDPOKE8(sd, SDGPIO, 0xdf); // clk negedge + if (dly) SDPEEK8(sd, SDGPIO); // delay + s = SDPEEK8(sd, SDGPIO); // sample + if ((s & 0x10) == 0x0) break; + SDPOKE8(sd, SDGPIO, 0xff); // clk posedge + if (dly) SDPEEK8(sd, SDGPIO); // delay + } + reset_timeout(sd); + + // Next we receive the response. + if (ok16 && !ok32) sddat2_8 = SDDAT2 + 1; + else sddat2_8 = SDDAT2; + if (dly) for (i = 0; i < resplen; i++) { + unsigned int r = 0; + + for (j = 0; j < 8; j++) { + SDPOKE8(sd, SDGPIO, 0xdf); // clk negedge + SDPEEK8(sd, SDGPIO); // delay + s = SDPEEK8(sd, SDGPIO); // sample + SDPOKE8(sd, SDGPIO, 0xff); // clk posedge + SDPEEK8(sd, SDGPIO); // delay + SDPEEK8(sd, SDGPIO); // delay + r = r << 1; + r |= ((s & 0x10) >> 4); + } + + *respptr++ = r; + } else while (resplen > 0) { + unsigned int r; + +#ifdef BIGENDIAN + if (ok32 && resplen >= 4) { + r = SDPEEK32(sd, SDCMD2); + *respptr++ = r & 0xff; + *respptr++ = (r >> 8) & 0xff; + *respptr++ = (r >> 16) & 0xff; + *respptr++ = (r >> 24); + resplen -= 4; + } else if (ok16 && resplen >= 2) { + r = SDPEEK16(sd, SDCMD2); + *respptr++ = r & 0xff; + *respptr++ = (r >> 8) & 0xff; + + resplen -= 2; + } else { + *respptr++ = SDPEEK8(sd, sddat2_8); + resplen--; + } +#else + if (ok32 && resplen >= 4) { + r = SDPEEK32(sd, SDCMD2); + *respptr++ = (r >> 24); + *respptr++ = (r >> 16) & 0xff; + *respptr++ = (r >> 8) & 0xff; + *respptr++ = r & 0xff; + resplen -= 4; + } else if (ok16 && resplen >= 2) { + r = SDPEEK16(sd, SDCMD2); + *respptr++ = (r >> 8) & 0xff; + *respptr++ = r & 0xff; + resplen -= 2; + } else { + *respptr++ = SDPEEK8(sd, sddat2_8); + resplen--; + } +#endif + } + if (type == TYPE_BSYRESP) { + s = 0; + while ((s & 0x7) != 0x7) { + if (timeout(sd)) break; + SDPOKE8(sd, SDGPIO, 0x9f); // clk negedge + if (dly) SDPEEK8(sd, SDGPIO); // delay + s = s << 1; + s |= SDPEEK8(sd, SDGPIO) & 0x1; + SDPOKE8(sd, SDGPIO, 0xbf); + if (dly) SDPEEK8(sd, SDGPIO); + } + } + +ignresp: + + if (type == TYPE_ABORT) + sd->sd_state &= ~(SDDAT_RX|SDDAT_TX); + +#ifndef SD_READONLYDMA + if (type == TYPE_TXDAT) { + sd->sd_state |= SDDAT_TX; + /* 2 clocks for nWR */ + SDPOKE8(sd, SDGPIO, 0xdf); // clk negedge + if (dly) SDPEEK8(sd, SDGPIO); // delay + if (dly) SDPEEK8(sd, SDGPIO); // delay + SDPOKE8(sd, SDGPIO, 0xff); // clk posedge + if (dly) SDPEEK8(sd, SDGPIO); // delay + if (dly) SDPEEK8(sd, SDGPIO); // delay + SDPOKE8(sd, SDGPIO, 0xdf); // clk negedge + if (dly) SDPEEK8(sd, SDGPIO); // delay + if (dly) SDPEEK8(sd, SDGPIO); // delay + SDPOKE8(sd, SDGPIO, 0xff); // clk posedge + if (dly) SDPEEK8(sd, SDGPIO); // delay + if (dly) SDPEEK8(sd, SDGPIO); // delay + if (sd->sd_state & DATSSP_4BIT) + SDPOKE8(sd, SDGPIO, 0x10); // assert start, clk negedge + else + SDPOKE8(sd, SDGPIO, 0x1e); + if (dly) SDPEEK8(sd, SDGPIO); // delay + if (dly) SDPEEK8(sd, SDGPIO); // delay + if (sd->sd_state & DATSSP_4BIT) + SDPOKE8(sd, SDGPIO, 0x30); // clk posedge + else + SDPOKE8(sd, SDGPIO, 0x3e); + if (dly) SDPEEK8(sd, SDGPIO); // delay + if (dly) SDPEEK8(sd, SDGPIO); // delay + } +#endif + + if (type == TYPE_RXDAT || type == TYPE_RXDAT_IGNRESP) + sd->sd_state |= SDDAT_RX; + +done: + // 8 clocks before stopping + if (!(sd->sd_state & (SDDAT_TX|SDDAT_RX))) { + if (dly) for (i = 0; i < 8; i++) { + SDPOKE8(sd, SDGPIO, 0xdf); + SDPEEK8(sd, SDGPIO); // delay + SDPEEK8(sd, SDGPIO); // delay + SDPOKE8(sd, SDGPIO, 0xff); + SDPEEK8(sd, SDGPIO); // delay + SDPEEK8(sd, SDGPIO); // delay + } else { + SDPOKE8(sd, SDGPIO, 0xff); + SDPOKE8(sd, SDCMD2, 0xff); + } + } + if (timeout(sd)) return 1; + else return 0; + +} + +static int +sdcmd(struct sdcore *sd, unsigned short req, unsigned int arg, + unsigned int *resp, unsigned char **dat) { + unsigned int s, cmdresp[17]; + unsigned int resplen; + unsigned int type = (req >> 8); + unsigned int cmdidx = req; + unsigned int *cmdptr = cmdresp; + unsigned int *cmd = cmdresp; + unsigned int *respptr; + unsigned int ndat; + + if (sd->hw_version != 0) return sdcmd2(sd, req, arg, resp, dat); + + // If no space for response provided by caller, use local buffer + if (resp == NULL) resp = cmdresp; + respptr = resp; + + // Before continuing, we must wait for the FSM to get to the + // S_SEND_CMD state. After a previous command, we may still be + // in S_DUMMY_CLK or in case of an ABORT, we may be in the middle of + // clocking a byte for TX or RX. + s = SDPEEK8(sd, SDSTATE); + while ((s & 0x7) != S_SEND_CMD) { + if (timeout(sd)) break; + s = SDPEEK8(sd, SDSTATE); + } + + // We know we're in S_SEND_CMD, but we may need to change the + // command type. This won't cause a state change. + if ((s & 0xe7) != (S_SEND_CMD | (type << 5))) + SDPOKE8(sd, SDSTATE, S_SEND_CMD | (type << 5)); + + // Build command packet + mkcommand(cmdidx, arg, cmdptr); + + // Next, we loop while tending the SSPs until we get our last + // byte of command data out. We may get a few bytes from the DAT + // SSP if we are aborting a previous data transfer command. If we do + // those get placed in a buffer or thrown away based on the callers + // "dat" parameter. + sd->sd_state |= SDCMD_TX; + while ((cmdptr - cmd) != 6) { + if (timeout(sd)) break; + s = tend_ssp(sd, &cmdptr, dat); + } + sd->sd_state &= ~SDCMD_TX; + + // If we got out of sync with the hardware, that would be bad. + // The hardware should still be in S_SEND_CMD for the last CMDSSP + // byte. + if ((s & 0x7) != S_SEND_CMD) { + SDPOKE8(sd, SDSTATE, S_OFF); + return 1; + } + + if (type == TYPE_NORESP) goto done; + else if (type == TYPE_LONGRESP) resplen = 17; + else resplen = 6; + + // Next state should be S_WAIT_RESP or S_RX_RESP. We may get + // more bytes from the DATSSP while shifting out our last bits of cmd + while (((s & 0x7) != S_WAIT_RESP) && ((s & 0x7) != S_RX_RESP)) { + if (timeout(sd)) break; + if (req == CMD_SEND_IF_COND) sd->sd_timeout += 1000; + s = tend_ssp(sd, NULL, dat); + } + + // Once we're in S_WAIT_RESP or S_RX_RESP though, the DATSSP is only + // active for 2 more clocks at the beginning of the S_WAIT_RESP state. + // This is enough for one more byte in 4-bit mode, though we may have + // 2 bytes already in our DATSSP. + if (sd->sd_state & (SDDAT_RX|SDDAT_TX)) { + do { + if (timeout(sd)) break; + s = tend_ssp(sd, NULL, dat); + } while (!(s & 0x18)); + + // We've now read/wrote one more byte to the DATSSP + // which should allow our FSM to advance to the RX_RESP state. + // If we pick up more than 2 more DATSSP bytes, something is + // wrong. + ndat = 0; + while ((s & 0x7) != S_RX_RESP) { + if (timeout(sd) || ndat > 2) break; + s = tend_ssp(sd, NULL, dat); + if (s & 0x10) ndat++; + } + + if (ndat > 2) { + SDPOKE8(sd, SDSTATE, S_OFF); + return 1; + } + } + + // We're now done with whatever business we had remaining with the + // previous command's DATSSP transfer since we've either just got our + // first byte of response or our last byte of data + sd->sd_state &= ~(SDDAT_RX|SDDAT_TX); + if (type == TYPE_RXDAT) sd->sd_state |= SDDAT_RX; + + // Next we receive the response. If this is TYPE_RXDAT command, + // or an abortion of a previous TYPE_RXDAT command, we may get a + // few bytes from the DAT SSP also. + sd->sd_state |= SDCMD_RX; + while ((respptr - resp) != resplen) { + if (timeout(sd)) break; + s = tend_ssp(sd, &respptr, dat); + if ((s & 0x10) && (resp == respptr)) { + SDPOKE8(sd, SDSTATE, S_OFF); + sd->sd_state &= ~(SDCMD_RX|SDDAT_RX); + return 1; + } + } + sd->sd_state &= ~SDCMD_RX; + + if (type == TYPE_ABORT) + sd->sd_state &= ~(SDDAT_RX|SDDAT_TX); + + if (type == TYPE_TXDAT) sd->sd_state |= SDDAT_TX; + +done: + if (timeout(sd)) return 1; + else return 0; +} + + +static int datssp_stream2(struct sdcore *sd, unsigned char **dat, + unsigned int buflen) { + unsigned char *d; + int ret; +#ifndef SD_READONLYDMA + int ok32; + int ok16; + int sddat2_8; + unsigned int x; +#endif + + if (sd->os_dmastream /* && (sd->sd_state & SDDAT_RX) */) { + d = dat ? *dat : NULL; + ret = sd->os_dmastream(sd->os_arg, d, buflen); + if (!ret && d) *dat += buflen; + return ret; + } + +#ifndef SD_READONLYDMA + d = *dat; + + while (buflen > 512) { + datssp_stream2(sd, dat, 512); + if (sd->os_irqwait) sd->os_irqwait(sd->os_arg, 1); + buflen -= 512; + d = *dat; + } + + ok32 = (sd->hw_version == 2); + ok16 = (ok32 || (sd->hw_version == 3)); + if (ok16 && !ok32) sddat2_8 = SDDAT2 + 1; + else sddat2_8 = SDDAT2; + + if (sd->sd_state & SDDAT_RX) { + + while (((size_t)d & 0x1 && buflen > 0) || buflen == 1) { + *d++ = SDPEEK8(sd, sddat2_8); + buflen--; + } + + if (((size_t)d & 0x2) && buflen >= 2) { + if (ok16) *(unsigned short *)(d) = SDPEEK16(sd, SDDAT2); + else { +#ifdef BIGENDIAN + x = SDPEEK8(sd, sddat2_8) << 8; + x |= SDPEEK8(sd, sddat2_8); +#else + x = SDPEEK8(sd, sddat2_8); + x |= SDPEEK8(sd, sddat2_8) << 8; +#endif + *(unsigned short *)(d) = x; + } + buflen -= 2; + d += 2; + } + + if (ok32) while (buflen >= 4) { + *(unsigned int *)(d) = SDPEEK32(sd, SDDAT2); + buflen -= 4; + d += 4; + } else if (ok16) while (buflen >= 4) { +#ifdef BIGENDIAN + x = SDPEEK16(sd, SDDAT2) << 16; + x |= SDPEEK16(sd, SDDAT2); +#else + x = SDPEEK16(sd, SDDAT2); + x |= SDPEEK16(sd, SDDAT2) << 16; +#endif + buflen -= 4; + *(unsigned int *)(d) = x; + d += 4; + } else while (buflen >= 4) { +#ifdef BIGENDIAN + x = SDPEEK8(sd, sddat2_8) << 24; + x |= SDPEEK8(sd, sddat2_8) << 16; + x |= SDPEEK8(sd, sddat2_8) << 8; + x |= SDPEEK8(sd, sddat2_8); +#else + x = SDPEEK8(sd, sddat2_8); + x |= SDPEEK8(sd, sddat2_8) << 8; + x |= SDPEEK8(sd, sddat2_8) << 16; + x |= SDPEEK8(sd, sddat2_8) << 24; +#endif + buflen -= 4; + *(unsigned int *)(d) = x; + d += 4; + } + } else { + while (((size_t)d & 0x1) || buflen == 1) { + SDPOKE8(sd, SDDAT2, *d++); + buflen--; + } + + if (((size_t)d & 0x2) && buflen >= 2) { + if (ok16) SDPOKE16(sd, SDDAT2, *(unsigned short *)(d)); + else { + x = *(unsigned short *)(d); +#ifdef BIGENDIAN + SDPOKE8(sd, SDDAT2, x >> 8); + SDPOKE8(sd, SDDAT2, x); +#else + SDPOKE8(sd, SDDAT2, x); + SDPOKE8(sd, SDDAT2, x >> 8); +#endif + } + buflen -= 2; + d += 2; + } + + if (ok32) while (buflen >= 4) { + SDPOKE32(sd, SDDAT2, *(unsigned int *)(d)); + buflen -= 4; + d += 4; + } else if (ok16) while (buflen >= 4) { + x = *(unsigned int *)(d); + buflen -= 4; + d += 4; +#ifdef BIGENDIAN + SDPOKE16(sd, SDDAT2, x >> 16); + SDPOKE16(sd, SDDAT2, x); +#else + SDPOKE16(sd, SDDAT2, x); + SDPOKE16(sd, SDDAT2, x >> 16); +#endif + } else while (buflen >= 4) { + x = *(unsigned int *)(d); + buflen -= 4; + d += 4; +#ifdef BIGENDIAN + SDPOKE8(sd, SDDAT2, x >> 24); + SDPOKE8(sd, SDDAT2, x >> 16); + SDPOKE8(sd, SDDAT2, x >> 8); + SDPOKE8(sd, SDDAT2, x); +#else + SDPOKE8(sd, SDDAT2, x); + SDPOKE8(sd, SDDAT2, x >> 8); + SDPOKE8(sd, SDDAT2, x >> 16); + SDPOKE8(sd, SDDAT2, x >> 24); +#endif + } + } + + *dat = d; + + if (buflen > 0) return datssp_stream2(sd, dat, buflen); + else return 0; +#else + return 0; +#endif +} + + +static int datssp_stream(struct sdcore *sd, unsigned char **dat, + unsigned int buflen) { + unsigned int s, t, byte = 0; + unsigned char *d; + + if (((sd->sd_state & SDDAT_RX) && sd->os_dmastream) /* || + ((sd->sd_state & SDDAT_TX) && sd->os_dmastream && dat) */ ) { + unsigned char *d = dat ? *dat : NULL; + int ret = sd->os_dmastream(sd->os_arg, d, buflen); + if (!ret && d) *dat += buflen; + return ret; + } + + if (sd->hw_version > 0) return datssp_stream2(sd, dat, buflen); + + while (buflen) { + if (timeout(sd)) return 1; + s = tend_ssp(sd, NULL, dat); + if (s & 0x10) { + buflen--; + if (byte++ > 7) { + if (sd->sd_state & SDDAT_RX) + goto fastrx; + else goto fasttx; + } + } + } + + // Now we can go faster (PIO) +fastrx: + if (dat) { + d = *dat; + while (buflen) { + s = SDPEEK8(sd, SDDAT); + *d = s; + buflen--; + d++; + } + *dat = d; + } else { + while (buflen--) SDPEEK8(sd, SDDAT); + } + return 0; + +fasttx: + if (dat) { + d = *dat; + while (buflen) { + t = *d; + SDPOKE8(sd, SDDAT, t); + buflen--; + d++; + datssp_feedcrc(sd, t); + } + *dat = d; + } else { + while (buflen--) SDPOKE8(sd, SDDAT, datssp_getcrc(sd)); + } + return 0; +} + + +static int stop(struct sdcore *sd) { + int ret; + unsigned int resp[6]; + + if (sd->hw_version) return stop2(sd); + + if (sd->parked_sector) { + if (sd->sd_state & SDDAT_TX) { + /* wait to get out of S_WAIT_BUSY */ + while ((SDPEEK8(sd, SDSTATE) & 0x7) != S_TX_WRITE) + if (timeout(sd)) break; + + /* abort parked write */ + SDPOKE8(sd, SDSTATE, S_SEND_CMD | (TYPE_ABORT << 5)); + sd->sd_state &= ~SDDAT_TX; + sd->sd_state |= SDDAT_RX; + ret = sdcmd(sd, CMD_STOP_TRANSMISSION, 0, resp, NULL); + sd->sd_state &= ~SDDAT_RX; + SDPOKE8(sd, SDSTATE, S_WAIT_BUSY | (TYPE_BSYRESP << 5)); + } else { + /* abort parked read */ + SDPOKE8(sd, SDSTATE, S_SEND_CMD | (TYPE_ABORT << 5)); + ret = sdcmd(sd, CMD_STOP_TRANSMISSION, 0, resp, NULL); + } + sd->parked_sector = 0; + if (ret||error(sd, resp, CMD_STOP_TRANSMISSION)||timeout(sd)) + return 1; + } + return 0; +} + + +static int stop2(struct sdcore *sd) { + int ret; + unsigned int resp[6]; + + if (sd->parked_sector) { + if (sd->os_irqwait) sd->os_irqwait(sd->os_arg, 0); + if (sd->sd_state & SDDAT_TX) { + /* abort parked write */ + ret = sdcmd2(sd, CMD_STOP_TRANSMISSION, 0, resp, NULL); + SDPOKE8(sd, SDCTRL2, 0x0); + if (sd->os_irqwait) sd->os_irqwait(sd->os_arg, 5); + SDPOKE8(sd, SDGPIO, 0xff); + SDPOKE8(sd, SDCMD2, 0xff); + + /* + while ((SDPEEK8(sd, SDGPIO) & 0xf) != 0xf) { + sd->os_delay(sd->os_arg, 1); + SDPOKE8(sd, SDGPIO, 0xdf); + SDPOKE8(sd, SDGPIO, 0xff); + if (timeout(sd)) return 1; + } + */ + reset_timeout(sd); + } else { + /* abort parked read */ + ret = sdcmd2(sd, CMD_STOP_TRANSMISSION, 0, resp, NULL); + } + sd->parked_sector = 0; + if (ret||error(sd, resp, CMD_STOP_TRANSMISSION)||timeout(sd)) { + DBG(SD_STOP_FAIL, ret); + return 1; + } + } + return 0; +} + + +static int do_read2(struct sdcore *sd, unsigned int sector, struct sdiov *iov, + unsigned int iovcnt) { + unsigned int n, s, sz; + unsigned char *datptr, *dat; + + if (iovcnt == 0) return 0; + + if (activate(sd)) return 1; + + n = iov->sdiov_nsect; + datptr = dat = iov->sdiov_base; + sz = sdsize(sd); + if (sector >= sz) return 0; + + if (sd->parked_sector) { + if (!(sd->sd_state & SDDAT_TX) && sd->parked_sector == sector) { + if (sd->os_irqwait && !sd->os_dmastream) + sd->os_irqwait(sd->os_arg, 3); + goto receive; + } + + stop2(sd); + } + + if (sd->sd_state & SD_HC) + sdcmd2(sd, CMD_READ_MULTIPLE_BLOCK2, sector, NULL, NULL); + else + sdcmd2(sd, CMD_READ_MULTIPLE_BLOCK2, sector * 512, NULL, NULL); + + do { + if (timeout(sd)) { + DBG(READ_FAIL, sector); + return 1; + } + SDPOKE8(sd, SDGPIO, 0xdf); + s = SDPEEK8(sd, SDGPIO); + SDPOKE8(sd, SDGPIO, 0xff); + } while ((s & 0xf) != 0x0); + reset_timeout(sd); + +receive: + if (sd->os_dmaprep && sd->os_dmastream) + sd->os_dmaprep(sd->os_arg, datptr, n * 512); + + SDPOKE8(sd, SDGPIO, 0xdf); + sd->parked_sector = sector + n; + +nextiov: + if (sd->parked_sector >= sz) { + n -= sd->parked_sector - sz; + if (n > 1) datssp_stream2(sd, &datptr, (n - 1) * 512); + /* temp disable rdmult_en bit */ + SDPOKE8(sd, SDSTAT2, SDPEEK8(sd, SDSTAT2) & ~0x8); + datssp_stream2(sd, &datptr, 512); + SDPOKE8(sd, SDSTAT2, SDPEEK8(sd, SDSTAT2) | 0x8); + stop2(sd); + iovcnt = 1; /* Force this iov to be the last */ + } else datssp_stream2(sd, &datptr, n * 512); + + if (--iovcnt) { + ++iov; + n = iov->sdiov_nsect; + datptr = iov->sdiov_base; + sd->parked_sector += n; + if (sd->os_dmaprep && sd->os_dmastream) + sd->os_dmaprep(sd->os_arg, datptr, n * 512); + goto nextiov; + } + + /* s = SDPEEK8(sd, SDSTAT2); + if (s & 0x44) { + sd->sd_timeout = 1000001; + return 1; + } + else */ return 0; +} + + +static int do_read(struct sdcore *sd, unsigned int sector, struct sdiov *iov, + unsigned int iovcnt) { + unsigned int resp[6], ret, n, sz; + unsigned char *datptr, *dat; + + if (iovcnt == 0) return 0; + + n = iov->sdiov_nsect; + datptr = dat = iov->sdiov_base; + sz = sdsize(sd); + if (sector >= sz) return 0; + + if (sd->parked_sector) { + if (!(sd->sd_state & SDDAT_TX) && sd->parked_sector == sector) + goto receive; + + stop(sd); + } + + if (sd->sd_state & SD_HC) + ret = sdcmd(sd, CMD_READ_MULTIPLE_BLOCK, sector, resp, &datptr); + else + ret = sdcmd(sd, CMD_READ_MULTIPLE_BLOCK, sector * 512, resp, &datptr); + if (ret || error(sd, resp, CMD_READ_MULTIPLE_BLOCK)) return 1; + +receive: + if (sd->os_dmaprep && sd->os_dmastream) + sd->os_dmaprep(sd->os_arg, datptr, n * 512 - (datptr - dat)); + + datssp_stream(sd, &datptr, 512 - (datptr - dat)); + datssp_stream(sd, NULL, 6); + + sd->parked_sector = sector + n; + if (sd->parked_sector > sz) { + n -= sd->parked_sector - sz; + sd->parked_sector = sz; + } + n--; + +nextiov: + while (n--) { + SDPOKE8(sd, SDSTATE, S_WAIT_RESP | (TYPE_RXDAT << 5)); + datssp_stream(sd, NULL, 2); // last part of prev CRC + datssp_stream(sd, &datptr, 512); + datssp_stream(sd, NULL, 6); // first part of CRC + } + + if (--iovcnt) { + ++iov; + n = iov->sdiov_nsect; + datptr = iov->sdiov_base; + sd->parked_sector += n; + if (sd->parked_sector > sz) { + n -= sd->parked_sector - sz; + sd->parked_sector = sz; + } + if (sd->os_dmaprep && sd->os_dmastream && n > 0) + sd->os_dmaprep(sd->os_arg, datptr, n * 512); + goto nextiov; + } + + SDPOKE8(sd, SDSTATE, S_WAIT_RESP | (TYPE_RXDAT << 5)); + datssp_stream(sd, NULL, 2); // last part of prev CRC + return 0; +} + + +static int do_write2(struct sdcore *sd, unsigned int sector, struct sdiov *iov, + unsigned int iovcnt) { + unsigned char *datptr; + unsigned int resp[6], ret, n, s, sz; + + if (sd->sd_wprot) return 1; + + if (iovcnt == 0) return 0; + + if (activate(sd)) return 1; + + sz = sdsize(sd); + if (sector >= sz) return 0; + + if (sd->os_powerok) { + int ok = sd->os_powerok(sd); + if (!ok && sd->parked_sector) { + stop2(sd); + return 1; + } else if (!ok) return 1; + } + + if (sd->parked_sector) { + if ((sd->sd_state & SDDAT_TX) && sd->parked_sector == sector) + goto transmit; + + stop2(sd); + } + + if (sd->sd_erasehint) { + sdcmd2(sd, CMD_APP_CMD, sd->sd_rcaarg, NULL, NULL); + ret = sdcmd2(sd, ACMD_SET_WR_BLK_ERASE_COUNT, sd->sd_erasehint, + resp, NULL); + if (ret||error(sd,resp, ACMD_SET_WR_BLK_ERASE_COUNT)) return 1; + sd->sd_erasehint = 0; + } + + if (sd->sd_nomultiwrite || sector == sz - 1) for (;;) { + if (sd->sd_state & SD_HC) + ret = sdcmd2(sd, CMD_WRITE_BLOCK, sector, resp, NULL); + else + ret = sdcmd2(sd, CMD_WRITE_BLOCK, sector * 512, resp, NULL); + + if (ret || error(sd, resp, CMD_WRITE_BLOCK)) return 1; + s = SDPEEK8(sd, SDSTAT2); /* reset crc */ + if (s & 0x10) SDPOKE8(sd, SDSTAT2, s & ~0x10); /* tmp disable multiwrite */ + datptr = iov->sdiov_base; + datssp_stream2(sd, &datptr, 512); + sector++; + if (--iov->sdiov_nsect == 0) { + iovcnt--; + iov++; + } else iov->sdiov_base += 512; + SDPOKE8(sd, SDCTRL2, 0x0); /* busy wait */ + if (sd->os_irqwait) sd->os_irqwait(sd->os_arg, 2); + SDPOKE8(sd, SDGPIO, 0xff); + sd->sd_state &= ~SDDAT_TX; + sd->parked_sector = 0; + if (s & 0x10) { + s = SDPEEK8(sd, SDSTAT2); + SDPOKE8(sd, SDSTAT2, s | 0x10); /* reenab multiwrite */ + } else s = SDPEEK8(sd, SDSTAT2); + if (s & 0x44) { + sd->sd_timeout = 1000001; + return 1; + } else if (iovcnt == 0) return 0; + } + + if (sd->sd_state & SD_HC) + ret = sdcmd2(sd, CMD_WRITE_MULTIPLE_BLOCK, sector, resp, NULL); + else + ret = sdcmd2(sd, CMD_WRITE_MULTIPLE_BLOCK, sector * 512, resp, NULL); + if (ret || error(sd, resp, CMD_WRITE_MULTIPLE_BLOCK)) { + DBG(WRITE_FAIL, sector, ret); + return 1; + } + sd->parked_sector = sector; + SDPEEK8(sd, SDSTAT2); + +transmit: + while (iovcnt--) { + datptr = iov->sdiov_base; + n = iov->sdiov_nsect; + sd->parked_sector += n; + if (sd->parked_sector >= sz) { + struct sdiov riov; + n -= sd->parked_sector - sz; + + if (n > 1) { + datssp_stream2(sd, &datptr, (n - 1) * 512); + ret = stop2(sd); + if (ret) return ret; + } + riov.sdiov_base = datptr; + riov.sdiov_nsect = 1; + ret = do_write2(sd, sz - 1, &riov, 1); + return ret; + } else datssp_stream2(sd, &datptr, n * 512); + iov++; + } + + if (!sd->sd_writeparking || sd->parked_sector == sz - 1) { + ret = stop2(sd); + if (ret) return ret; + } + + if (sd->os_irqwait) sd->os_irqwait(sd->os_arg, 2); + + s = SDPEEK8(sd, SDSTAT2); + if (s & 0x44) { + if (s & 0x40) DBG(SD_HW_TMOUT, sector, s); + if (s & 0x4) DBG(SD_DAT_BAD_CRC, sector, s); + sd->sd_timeout = 1000001; + return 1; + } else { + reset_timeout(sd); + return 0; + } +} + + +static int do_write(struct sdcore *sd, unsigned int sector, struct sdiov *iov, + unsigned int iovcnt) { + unsigned char *datptr, *crcptr, **crcptrptr; + unsigned int resp[6], ret, n, sz; + + if (sd->sd_wprot) return 1; + + if (iovcnt == 0) return 0; + + sz = sdsize(sd); + if (sector >= sz) return 0; + + if (0 /* sd->sd_crchint */) { + // CRC is pre-calculated so don't recalculate + crcptr = sd->sd_crchint; + crcptrptr = &crcptr; + sd->sd_state |= DATSSP_NOCRC; + sd->sd_crchint = NULL; + } else { + crcptrptr = NULL; + sd->sd_state &= ~DATSSP_NOCRC; + } + + if (sd->parked_sector) { + if ((sd->sd_state & SDDAT_TX) && sd->parked_sector == sector) + goto transmit; + + stop(sd); + } + + if (sd->sd_erasehint) { + sdcmd(sd, CMD_APP_CMD, sd->sd_rcaarg, NULL, NULL); + ret = sdcmd(sd, ACMD_SET_WR_BLK_ERASE_COUNT, sd->sd_erasehint, + resp, NULL); + if (ret || error(sd, resp, ACMD_SET_WR_BLK_ERASE_COUNT)) return 1; + sd->sd_erasehint = 0; + } + + if (sd->sd_state & SD_HC) + ret = sdcmd(sd, CMD_WRITE_MULTIPLE_BLOCK, sector, resp, NULL); + else + ret = sdcmd(sd, CMD_WRITE_MULTIPLE_BLOCK, sector * 512, resp, NULL); + if (ret || error(sd, resp, CMD_WRITE_MULTIPLE_BLOCK)) { + return 1; + } + sd->parked_sector = sector; + +transmit: + while (iovcnt--) { + datptr = iov->sdiov_base; + n = iov->sdiov_nsect; + sd->parked_sector += n; + if (sd->parked_sector > sz) { + n -= sd->parked_sector - sz; + sd->parked_sector = sz; + } + while (n--) { + datssp_stream(sd, &datptr, 512); + datssp_stream(sd, crcptrptr, 8); // CRC bytes + SDPOKE8(sd, SDSTATE, S_CRC_CHECK | (TYPE_TXDAT << 5)); + } + iov++; + } + + if (!sd->sd_writeparking) { + stop(sd); + } + + return 0; +} + + +static int sdfastinit(struct sdcore *sd) { + SDPOKE8(sd, SDCTRL, 0x40); + sd->sd_state = DATSSP_4BIT; + + sd->sd_rcaarg = ~sd->sdboot_token; + sdcmd(sd, CMD_DESELECT_CARD, ~sd->sd_rcaarg, NULL, NULL); + sdcmd(sd, CMD_SEND_CSD, sd->sd_rcaarg, sd->sd_csd, NULL); + sdcmd(sd, CMD_SELECT_CARD, sd->sd_rcaarg, NULL, NULL); + + if (sd->os_dmastream) SDPOKE8(sd, SDCTRL, 0x42); + if ((SDPEEK8(sd, SDCTRL) & 0x80) || (sd->sd_csd[15] & 0x30)) + sd->sd_wprot = 1; + sd->sd_blocksize = 1 << ((sd->sd_csd[6] & 0xf)); + if (timeout(sd)) return 0; + else return sdsize(sd); +} + + +static void reset_common(struct sdcore *sd) { + int i; + + reset_timeout(sd); + sd_initcrc(sd); + sd->parked_sector = 0; + sd->sd_wprot = 0; + sd->sd_blocksize = 0; + sd->sd_sz = 0; + for (i = 0; i < 17; i++) sd->sd_csd[i] = 0; + if (sd->hw_version == 0) sd->hw_version = version(sd); + if (sd->hw_version == 0) return; + sd->sd_state &= SD_RESET; + + if (sd->os_irqwait) sd->os_irqwait(sd->os_arg, 4); + remember_sdcore(sd); + activate(sd); + sd->sd_state |= SD_LOSPEED; + + if (!(sd->sd_state & SD_RESET) && (SDPEEK8(sd, SDGPIO) != 0x0)) { + SDPOKE8(sd, SDGPIO, 0x0); +#ifdef BIGENDIAN + for (i = 0; i < 8; i++) SDPOKE16(sd, SDLUN2, i << 8); +#else + for (i = 0; i < 8; i++) SDPOKE16(sd, SDLUN2, i); +#endif + sd->os_delay(sd->os_arg, 100000); + + /* this was a global reset, so let the other luns know */ + for (i = 0; i < (sizeof(sdcores)/sizeof(sdcores[0])); i++) { + if (sdcores[i] == NULL) break; + if (sdcores[i]->sd_regstart == sd->sd_regstart) + sdcores[i]->sd_state |= SD_RESET; + } +#ifdef BIGENDIAN + SDPOKE16(sd, SDLUN2, sd->sd_lun << 8); +#else + SDPOKE16(sd, SDLUN2, sd->sd_lun); +#endif + } + sd->sd_state &= ~SD_RESET; + + // gratuitous clocks + SDPOKE8(sd, SDGPIO, 0xff); + sd->os_delay(sd->os_arg, 5000); + for (i = 0; i < 750; i++) { + SDPOKE8(sd, SDGPIO, 0xff); + SDPEEK8(sd, SDGPIO); /* delay */ + SDPEEK8(sd, SDGPIO); /* delay */ + SDPOKE8(sd, SDGPIO, 0xdf); + SDPEEK8(sd, SDGPIO); /* delay */ + SDPEEK8(sd, SDGPIO); /* delay */ + } + + SDPEEK8(sd, SDSTAT2); /* reset any timeout/crc conditions */ + if (sd->sd_nomultiwrite) SDPOKE8(sd, SDSTAT2, 0x8); + else SDPOKE8(sd, SDSTAT2, 0x18); +} + + +#ifndef SD_NOMMC +static void mmc_enhance(struct sdcore *sd) { + unsigned int s; + unsigned char dat[512], *datptr; + + sdcmd2(sd, CMD_MMC_SEND_EXT_CSD, 0, NULL, NULL); + do { + if (timeout(sd)) break; + SDPOKE8(sd, SDGPIO, 0xdf); + s = SDPEEK8(sd, SDGPIO); + SDPOKE8(sd, SDGPIO, 0xff); + } while ((s & 0xf) == 0xf); + + if (sd->os_dmaprep && sd->os_dmastream) + sd->os_dmaprep(sd->os_arg, dat, 512); + + SDPOKE8(sd, SDGPIO, 0xdf); + datptr = dat; + datssp_stream2(sd, &datptr, 512); + + sd->sd_state &= ~SDDAT_RX; + /* ERASE_GROUP_DEF */ + sdcmd2(sd, CMD_MMC_SWITCH, (175<<16)|(1<<8)|(3<<24), NULL, NULL); + + /* Enable Enhanced User data area, max size */ + sdcmd2(sd, CMD_MMC_SWITCH, (140<<16)|(dat[157]<<8)|(3<<24), NULL, NULL); + sdcmd2(sd, CMD_MMC_SWITCH, (141<<16)|(dat[158]<<8)|(3<<24), NULL, NULL); + sdcmd2(sd, CMD_MMC_SWITCH, (142<<16)|(dat[159]<<8)|(3<<24), NULL, NULL); + sdcmd2(sd, CMD_MMC_SWITCH, (156<<16)|(1<<8)|(3<<24), NULL, NULL); + + /* Enable write reliability */ + sdcmd2(sd, CMD_MMC_SWITCH, (167<<16)|(1<<8)|(3<<24), NULL, NULL); + + /* Partition setting completed */ + sdcmd2(sd, CMD_MMC_SWITCH, (155<<16)|(1<<8)|(3<<24), NULL, NULL); +} + + +static int mmcreset2(struct sdcore *sd) { + unsigned int s, i; + unsigned int resp[17]; + unsigned char dat[512], *datptr; + + reset_common(sd); + if (sd->hw_version == 0) return 0; + + sdcmd2(sd, CMD_GO_IDLE_STATE, 0, NULL, NULL); + + i = 0; + do { + sdcmd2(sd, CMD_MMC_SEND_OP_COND, 0xc0ff8000, resp, NULL); + if (i > 30000) sd->sd_timeout = 1000001; + if (timeout(sd)) break; + i++; + } while (((resp[1] & 0x80) == 0x0)); + + sdcmd2(sd, CMD_ALL_SEND_CID, 0, resp, NULL); + sdcmd2(sd, CMD_MMC_SET_RELATIVE_ADDR, 0x200, resp, NULL); + sd->sd_rcaarg = 0x200; + + sdcmd2(sd, CMD_SELECT_CARD, sd->sd_rcaarg, resp, NULL); + + /* Enable 4-bit data bus, X_CSD byte 183 */ + sdcmd2(sd, CMD_MMC_SWITCH, (183<<16)|(1<<8)|(3<<24), NULL, NULL); + /* Enable highest power, X_CSD byte 187 */ + sdcmd2(sd, CMD_MMC_SWITCH, (187<<16)|(15<<8)|(3<<24), NULL, NULL); + /* Enable high speed 50Mhz data bus, X_CSD byte 185 */ + sdcmd2(sd, CMD_MMC_SWITCH, (185<<16)|(1<<8)|(3<<24), NULL, NULL); + + if (sd->sd_nomultiwrite) SDPOKE8(sd, SDSTAT2, 0x28); + else SDPOKE8(sd, SDSTAT2, 0x38); + + sd->sd_state |= DATSSP_4BIT|SD_HISPEED|SD_HC; + sd->sd_state &= ~SD_LOSPEED; + + sdcmd2(sd, CMD_SET_BLOCKLEN, 512, NULL, NULL); + + sdcmd2(sd, CMD_MMC_SEND_EXT_CSD, 0, NULL, NULL); + do { + if (timeout(sd)) break; + SDPOKE8(sd, SDGPIO, 0xdf); + s = SDPEEK8(sd, SDGPIO); + SDPOKE8(sd, SDGPIO, 0xff); + } while ((s & 0xf) == 0xf); + + if (sd->os_dmaprep && sd->os_dmastream) + sd->os_dmaprep(sd->os_arg, dat, 512); + + SDPOKE8(sd, SDGPIO, 0xdf); + datptr = dat; + datssp_stream2(sd, &datptr, 512); + + sd->sd_state &= ~SDDAT_RX; + sd->sd_sz = dat[212] | (dat[213]<<8) | (dat[214]<<16) | (dat[215]<<24); + + if (timeout(sd)) return 0; + else { + reset_timeout(sd); + if (sd->sd_sz) sd->sd_type = 1; /* eMMC, not SD */ + return sdsize(sd); + } +} +#endif + + +static int sdreset2(struct sdcore *sd) { + unsigned int rca, s, i, x; + unsigned int resp[17]; + +#ifndef SD_NOMMC + if (sd->sd_type == 1) return mmcreset2(sd); /* eMMC chip, not SD */ +#endif + reset_common(sd); + if (sd->hw_version == 0) return 0; + + s = sdcmd2(sd, CMD_SEND_IF_COND, 0x1aa, resp, NULL); + if (s) { + reset_timeout(sd); + x = 0x00ff8000; + } else { + x = 0x50ff8000; + } + + i = 0; + do { + sdcmd2(sd, CMD_APP_CMD, 0, NULL, NULL); + sdcmd2(sd, ACMD_SD_SEND_OP_COND, x, resp, NULL); + if (i > 3000) sd->sd_timeout = 1000001; + if (timeout(sd)) break; + i++; + } while (((resp[1] & 0x80) == 0x0)); + + if ((x & 0x40000000) && (resp[1] & 0x40)) { + sd->sd_state |= SD_HC; + } + + sdcmd2(sd, CMD_ALL_SEND_CID, 0, resp, NULL); + sdcmd2(sd, CMD_SEND_RELATIVE_ADDR, 0, resp, NULL); + rca = resp[1] << 8 | resp[2]; + sd->sd_rcaarg = (rca & 0xff00) << 16 | (rca & 0xff) << 16; + sd->sdboot_token = ~sd->sd_rcaarg; + + sdcmd2(sd, CMD_SEND_CSD, sd->sd_rcaarg, sd->sd_csd, NULL); + sdcmd2(sd, CMD_SELECT_CARD, sd->sd_rcaarg, resp, NULL); + + if ((resp[1] & 0x2)) { + sd->sd_locked = 1; +#ifndef SD_NOLOCKSUPPORT + if (sd->sd_pwd) + sdlockctl2(sd, SDLOCK_UNLOCK, sd->sd_pwd, NULL); +#endif + } else sd->sd_locked = 0; + + sdcmd2(sd, CMD_APP_CMD, sd->sd_rcaarg, NULL, NULL); + sdcmd2(sd, ACMD_SET_CLR_CARD_DETECT, 0, NULL, NULL); + sdcmd2(sd, CMD_SET_BLOCKLEN, 512, NULL, NULL); + sdcmd2(sd, CMD_APP_CMD, sd->sd_rcaarg, NULL, NULL); + sdcmd2(sd, ACMD_SET_BUS_WIDTH, 2, resp, NULL); + sd->sd_state |= DATSSP_4BIT; + sd->sd_state &= ~SD_LOSPEED; + + sdcmd2(sd, CMD_APP_CMD, sd->sd_rcaarg, NULL, NULL); + sdcmd2(sd, ACMD_SEND_SCR2, 0, NULL, NULL); + do { + if (timeout(sd)) break; + SDPOKE8(sd, SDGPIO, 0xdf); + SDPEEK8(sd, SDGPIO); + s = SDPEEK8(sd, SDGPIO); + SDPOKE8(sd, SDGPIO, 0xff); + SDPEEK8(sd, SDGPIO); + } while ((s & 0xf) != 0x0); + for (i = 0; i < 16; i++) { + SDPOKE8(sd, SDGPIO, 0xdf); + SDPEEK8(sd, SDGPIO); + s = (SDPEEK8(sd, SDGPIO) & 0xf) << 4; + SDPOKE8(sd, SDGPIO, 0xff); + SDPEEK8(sd, SDGPIO); + SDPOKE8(sd, SDGPIO, 0xdf); + SDPEEK8(sd, SDGPIO); + s |= (SDPEEK8(sd, SDGPIO) & 0xf); + SDPOKE8(sd, SDGPIO, 0xff); + SDPEEK8(sd, SDGPIO); + if (i < 8) sd->sd_scr[i] = s; + } + for (i = 0; i < 8; i++) { + SDPOKE8(sd, SDGPIO, 0xdf); + SDPEEK8(sd, SDGPIO); + SDPEEK8(sd, SDGPIO); + SDPOKE8(sd, SDGPIO, 0xff); + SDPEEK8(sd, SDGPIO); + } + sd->sd_state &= ~SDDAT_RX; + +#ifndef SD_NOHIGHSPEED + if ((sd->sd_scr[0] & 0xf) >= 1) { // SD version >= 1.10 + unsigned char dat[64]; + sdcmd2(sd, CMD_SWITCH_FUNC2, 0x80fffff1, NULL, NULL); + do { + if (timeout(sd)) break; + SDPOKE8(sd, SDGPIO, 0xdf); + SDPEEK8(sd, SDGPIO); + s = SDPEEK8(sd, SDGPIO); + SDPOKE8(sd, SDGPIO, 0xff); + SDPEEK8(sd, SDGPIO); + } while ((s & 0xf) != 0x0); + for (i = 0; i < 72; i++) { + SDPOKE8(sd, SDGPIO, 0xdf); + SDPEEK8(sd, SDGPIO); + s = (SDPEEK8(sd, SDGPIO) & 0xf) << 4; + SDPOKE8(sd, SDGPIO, 0xff); + SDPEEK8(sd, SDGPIO); + SDPOKE8(sd, SDGPIO, 0xdf); + SDPEEK8(sd, SDGPIO); + s |= (SDPEEK8(sd, SDGPIO) & 0xf); + SDPOKE8(sd, SDGPIO, 0xff); + SDPEEK8(sd, SDGPIO); + if (i < 64) dat[i] = s; + } + for (i = 0; i < 8; i++) { + SDPOKE8(sd, SDGPIO, 0xdf); + SDPEEK8(sd, SDGPIO); + SDPEEK8(sd, SDGPIO); + SDPOKE8(sd, SDGPIO, 0xff); + SDPEEK8(sd, SDGPIO); + } + sd->sd_state &= ~SDDAT_RX; + if (dat[0] | dat[1]) { + if (sd->sd_nomultiwrite) SDPOKE8(sd, SDSTAT2, 0x28); + else SDPOKE8(sd, SDSTAT2, 0x38); + sd->sd_state |= SD_HISPEED; + } + } +#endif + +#ifdef BIGENDIAN + if ((sd->sd_csd[15] & 0x30) || (SDPEEK16(sd, SDGPIO) & 0x2)) +#else + if ((sd->sd_csd[15] & 0x30) || (SDPEEK16(sd, SDGPIO) & 0x200)) +#endif + sd->sd_wprot = 1; + sd->sd_blocksize = 1 << ((sd->sd_csd[6] & 0xf)); +#ifndef SD_NOAUTOMMC + if (timeout(sd) && (sd->sd_type == 0)) { + /* if mmcreset2() works, sd_type is rewritten */ + sd->sd_type = 2; /* SD, no eMMC */ + return mmcreset2(sd); + } +#else + if (timeout(sd)) return 0; +#endif + else { + reset_timeout(sd); + return sdsize(sd); + } +} + + +/* + * return 0 : 8 bit TS-SDCORE v1 + * return 1 : 8 bit 4x8 TS-SDCORE v2 + * return 2 : 32 bit 4x32 TS-SDCORE v2 + * return 3 : 16 bit 4x32 TS-SDCORE v2 + * return 4 : 8 bit 4x32 TS-SDCORE v2 + */ +static int version(struct sdcore *sd) { + int a, b, i; + + +#ifdef SD_FORCEVERSION + return SD_FORCEVERSION; +#endif + for (i = 0; i < (sizeof(sdcores)/sizeof(sdcores[0])); i++) { + if (sdcores[i] == NULL) break; + if (sdcores[i]->sd_regstart == sd->sd_regstart) + return sdcores[i]->hw_version; + } + + a = SDPEEK8(sd, 3); + SDPOKE8(sd, 3, (a ^ 0x40)); + b = SDPEEK8(sd, 3); + SDPOKE8(sd, 3, a); + if ((a & 0x40) ^ (b & 0x40)) return 0; + else if (a & 0x40) return 1; + /* either 2, 3, or 4 */ + a = SDPEEK32(sd, 12); + b = SDPEEK16(sd, 12); +#ifdef BIGENDIAN + if ((a & 0x40000000) && (b & 0x4000)) return 2; +#else + if ((a & 0x40) && (b & 0x40)) return 2; +#endif + a = SDPEEK8(sd, 12); + if (a & 0x40) return 3; + else return 4; +} + + +int sdreset(struct sdcore *sd) { + unsigned int rca, s, x; + unsigned int resp[17]; + int i; + sd->refcnt++; + BUG_ON(sd->refcnt != 1); + + reset_timeout(sd); + sd_initcrc(sd); + sd->parked_sector = 0; + sd->sd_wprot = 0; + sd->sd_blocksize = 0; + sd->sd_sz = 0; + + sd->hw_version = version(sd); + if (sd->hw_version >= 2) { + sd->refcnt--; + return sdreset2(sd); + } + + // check for no SD card present + if (SDPEEK8(sd, SDCTRL) & 0x8){ + sd->refcnt--; + return 0; + } + + if (sd->sdboot_token) { + int ret = sdfastinit(sd); + sd->sdboot_token = 0; + if (ret){ + sd->refcnt--; + return ret; + } + } + + // set controller for 1-bit mode, slow clock + SDPOKE8(sd, SDCTRL, 0x20); + + SDPOKE8(sd, SDSTATE, S_DUMMY_CLK); + sd->sd_state = SDCMD_RX|SDDAT_RX; + s = SDPEEK8(sd, SDSTATE); + while ((s & 0x7) != S_SEND_CMD) { + // If we timeout here, it would be VERY BAD as we have no + // further recourse to set things right if we can't turn + // the SD off. + if (timeout(sd)){ + sd->refcnt--; + return 0; + } + sd->os_delay(sd->os_arg, 10000); + sd->sd_timeout += 10000; + + // We won't be able to change state until both SSPs are empty + s = tend_ssp(sd, NULL, NULL); + } + SDPOKE8(sd, SDSTATE, S_OFF); + sd->sd_state = 0; + + sd->os_delay(sd->os_arg, 50000); + + SDPOKE8(sd, SDSTATE, S_DUMMY_CLK); + sd->os_delay(sd->os_arg, 100000); + if ((SDPEEK8(sd, SDSTATE) & 0x7) == S_OFF) { + // No card present + sd->refcnt--; + return 0; + } + + SDPOKE8(sd, SDSTATE, S_WAIT_RESP); + // clock will freerun waiting for a response that will never come + sd->os_delay(sd->os_arg, 50000); + + SDPOKE8(sd, SDSTATE, S_DUMMY_CLK); + + s = sdcmd(sd, CMD_SEND_IF_COND, 0x1aa, resp, NULL); + if (s) { + reset_timeout(sd); + SDPOKE8(sd, SDSTATE, S_DUMMY_CLK); + x = 0x00ff0000; + } else { + x = 0x50ff0000; + } + + i = 0; + do { + sdcmd(sd, CMD_APP_CMD, 0, NULL, NULL); + sdcmd(sd, ACMD_SD_SEND_OP_COND, x, resp, NULL); + if (i > 3000) sd->sd_timeout = 1000001; + if (timeout(sd)) break; + i++; + } while (((resp[1] & 0x80) == 0x0)); + + if ((x & 0x40000000) && (resp[1] & 0x40)) sd->sd_state |= SD_HC; + + sdcmd(sd, CMD_ALL_SEND_CID, 0, resp, NULL); + sdcmd(sd, CMD_SEND_RELATIVE_ADDR, 0, resp, NULL); + rca = resp[1] << 8 | resp[2]; + sd->sd_rcaarg = (rca & 0xff00) << 16 | (rca & 0xff) << 16; + sd->sdboot_token = ~sd->sd_rcaarg; + + sdcmd(sd, CMD_SEND_CSD, sd->sd_rcaarg, sd->sd_csd, NULL); + sdcmd(sd, CMD_SELECT_CARD, sd->sd_rcaarg, resp, NULL); + + if ((resp[1] & 0x2)) { + unsigned int ret = 1; + sd->sd_locked = 1; +#ifndef SD_NOLOCKSUPPORT + if (sd->sd_pwd) + ret = sdlockctl(sd, SDLOCK_UNLOCK, sd->sd_pwd, NULL); +#endif + if (ret != 0){ + sd->refcnt--; + return 0; + } + } else sd->sd_locked = 0; + + sdcmd(sd, CMD_APP_CMD, sd->sd_rcaarg, NULL, NULL); + sdcmd(sd, ACMD_SET_CLR_CARD_DETECT, 0, NULL, NULL); + /* + sdcmd(sd, CMD_APP_CMD, sd->sd_rcaarg, NULL, NULL); + sdcmd(sd, ACMD_SEND_SCR, 0, NULL, &datptr); + while ((datptr - sd->sd_scr) != 8) { + if (timeout(sd)) return 1; + tend_ssp(sd, NULL, &datptr); + } + datssp_stream(sd, NULL, 3); + SDPOKE8(sd, SDSTATE, (TYPE_ABORT << 5) | S_SEND_CMD); + sd->sd_state |= SDCMD_RX|SDDAT_RX; + while ((SDPEEK8(sd, SDSTATE) & 0x17) != S_SEND_CMD) { + if (timeout(sd)) break; + tend_ssp(sd, NULL, NULL); + } + sd->sd_state &= ~(SDCMD_RX|SDDAT_RX); + if ((sd->sd_scr[0] & 0xf) >= 1) { // SD version >= 1.10 + unsigned char dat[64]; + datptr = dat; + sdcmd(sd, CMD_SWITCH_FUNC, 0x80fffff1, NULL, &datptr); + while ((datptr - dat) != 64) { + if (timeout(sd)) break; + tend_ssp(sd, NULL, &datptr); + } + datssp_stream(sd, NULL, 3); + SDPOKE8(sd, SDSTATE, (TYPE_ABORT << 5) | S_SEND_CMD); + sd->sd_state |= SDCMD_RX|SDDAT_RX; + while ((SDPEEK8(sd, SDSTATE) & 0x7) != S_SEND_CMD) { + if (timeout(sd)) break; + tend_ssp(sd, NULL, NULL); + } + sd->sd_state &= ~(SDCMD_RX|SDDAT_RX); + } + */ + + sdcmd(sd, CMD_SET_BLOCKLEN, 512, NULL, NULL); + sdcmd(sd, CMD_APP_CMD, sd->sd_rcaarg, NULL, NULL); + sdcmd(sd, ACMD_SET_BUS_WIDTH, 2, resp, NULL); + + // set controller for 4-bit mode, fast clock + SDPOKE8(sd, SDCTRL, (0x40 | (sd->os_dmastream ? 0x2 : 0x0))); + sd->sd_state |= DATSSP_4BIT; + + /* + sdcmd(sd, CMD_APP_CMD, sd->sd_rcaarg, NULL, NULL); + sdcmd(sd, ACMD_SEND_SCR, 0, NULL, &datptr); + while ((datptr - sd->sd_scr) != 8) { + if (timeout(sd)) break; + tend_ssp(sd, NULL, &datptr); + } + datssp_stream(sd, NULL, 6); + SDPOKE8(sd, SDSTATE, S_DUMMY_CLK | (TYPE_SHORTRESP << 5)); + bzero(resp, 6 * 4); + sdcmd(sd, CMD_SEND_STATUS, 0, resp, NULL); + */ + + if ((SDPEEK8(sd, SDCTRL) & 0x80) || (sd->sd_csd[15] & 0x30)) + sd->sd_wprot = 1; + sd->sd_blocksize = 1 << ((sd->sd_csd[6] & 0xf)); + if (timeout(sd) || error(sd, resp, ACMD_SET_BUS_WIDTH)){ + sd->refcnt--; + return 0; + } else { + sd->refcnt--; + return sdsize(sd); + } +} + + +static +int sdread2(struct sdcore *sd, unsigned int sector, unsigned char *dat, + int nsectors) { + struct sdiov iov; + int ret; + + iov.sdiov_base = dat; + iov.sdiov_nsect = nsectors; + ret = do_read2(sd, sector, &iov, 1); + return ret; +} + + +int sdread(struct sdcore *sd, unsigned int sector, unsigned char *dat, + int nsectors) { + struct sdiov iov; + int ret; + sd->refcnt++; + BUG_ON(sd->refcnt != 1); + + iov.sdiov_base = dat; + iov.sdiov_nsect = nsectors; + if (sd->hw_version == 0) ret = do_read(sd, sector, &iov, 1); + else ret = do_read2(sd, sector, &iov, 1); + sd->refcnt--; + return ret; +} + + +int sdwrite(struct sdcore *sd, unsigned int sector, unsigned char *dat, + int nsectors) { + struct sdiov iov; + unsigned int ret; + + sd->refcnt++; + BUG_ON(sd->refcnt != 1); + + iov.sdiov_base = dat; + iov.sdiov_nsect = nsectors; + if (sd->hw_version == 0) ret = do_write(sd, sector, &iov, 1); + else ret = do_write2(sd, sector, &iov, 1); + + sd->refcnt--; + return ret; +} + + +int sdreadv(struct sdcore *sd, unsigned int sector, struct sdiov *iov, + int niov) { + if (sd->hw_version == 0) return do_read(sd, sector, iov, niov); + else return do_read2(sd, sector, iov, niov); +} + + +int sdwritev(struct sdcore *sd, unsigned int sector, struct sdiov *iov, + int niov) { + if (sd->hw_version == 0) return do_write(sd, sector, iov, niov); + else return do_write2(sd, sector, iov, niov); +} + + +static int sdsetwprot2(struct sdcore *sd, unsigned int perm) { + int i, ret, s; + unsigned int csd[16], resp[6]; + unsigned char csdchars[16]; + unsigned char *csdptr = csdchars; + + stop2(sd); + + perm = perm ? 0x3 : 0x1; + for (i = 0; i < 16; i++) csd[i] = sd->sd_csd[i + 1]; + csd[14] &= ~(0x3 << 4); + csd[14] |= (perm << 4); + csd[15] = 0x1 | crc7(0, csd, 15) << 1; + for (i = 0; i < 16; i++) csdchars[i] = csd[i]; + + ret = sdcmd2(sd, CMD_PROGRAM_CSD, 0, resp, NULL); + if (ret || error(sd, resp, CMD_PROGRAM_CSD)) return 1; + for (i = 0; i < 16; i++) { + s = *csdptr++; + sd_4bit_feedcrc(sd, s); + SDPOKE8(sd, SDGPIO, (0x10|((s & 0xf0) >> 4))); + SDPEEK8(sd, SDGPIO); + SDPEEK8(sd, SDGPIO); + SDPOKE8(sd, SDGPIO, (0x30|((s & 0xf0) >> 4))); + SDPEEK8(sd, SDGPIO); + SDPOKE8(sd, SDGPIO, (0x10|(s & 0xf))); + SDPEEK8(sd, SDGPIO); + SDPEEK8(sd, SDGPIO); + SDPOKE8(sd, SDGPIO, (0x30|(s & 0xf))); + SDPEEK8(sd, SDGPIO); + } + for (i = 0; i < 8; i++) { + s = sd_4bit_getcrc(sd); + SDPOKE8(sd, SDGPIO, (0x10|((s & 0xf0) >> 4))); + SDPEEK8(sd, SDGPIO); + SDPEEK8(sd, SDGPIO); + SDPOKE8(sd, SDGPIO, (0x30|((s & 0xf0) >> 4))); + SDPEEK8(sd, SDGPIO); + SDPOKE8(sd, SDGPIO, (0x10|(s & 0xf))); + SDPEEK8(sd, SDGPIO); + SDPEEK8(sd, SDGPIO); + SDPOKE8(sd, SDGPIO, (0x30|(s & 0xf))); + SDPEEK8(sd, SDGPIO); + } + // End bit + SDPOKE8(sd, SDGPIO, 0x1f); + SDPEEK8(sd, SDGPIO); + SDPEEK8(sd, SDGPIO); + SDPOKE8(sd, SDGPIO, 0x3f); + SDPEEK8(sd, SDGPIO); + SDPOKE8(sd, SDGPIO, 0xbf); // tristate dat + // CRC ack + s = 0; + for (i = 0; i < 7; i++) { + SDPOKE8(sd, SDGPIO, 0x9f); // clk negedge + SDPEEK8(sd, SDGPIO); // delay + s = s << 1; + s |= (SDPEEK8(sd, SDGPIO) & 0x1); + SDPOKE8(sd, SDGPIO, 0xbf); // clk posedge + } + if ((s & 0xf) != 0x5) return 1; + // wait for unbusy + s = 0; + while ((s & 0x7) != 0x7) { + if (timeout(sd)) break; + SDPOKE8(sd, SDGPIO, 0x9f); // clk negedge + SDPEEK8(sd, SDGPIO); // delay + s = s << 1; + s |= SDPEEK8(sd, SDGPIO) & 0x1; + SDPOKE8(sd, SDGPIO, 0xbf); + } + for (i = 0; i < 8; i++) { + SDPOKE8(sd, SDGPIO, 0x9f); + SDPEEK8(sd, SDGPIO); + SDPEEK8(sd, SDGPIO); + SDPOKE8(sd, SDGPIO, 0xbf); + SDPEEK8(sd, SDGPIO); + } + sd->sd_state &= ~SDDAT_TX; + + sdcmd2(sd, CMD_DESELECT_CARD, ~sd->sd_rcaarg, NULL, NULL); + ret = sdcmd2(sd, CMD_SEND_CSD, sd->sd_rcaarg, sd->sd_csd, NULL); + if (ret || sd->sd_csd[15] != csd[14]) { + return 1; + } + sdcmd2(sd, CMD_SELECT_CARD, sd->sd_rcaarg, resp, NULL); + + sd->sd_wprot = 1; + return 0; +} + + +int sdsetwprot(struct sdcore *sd, unsigned int perm) { + int i, ret; + unsigned int csd[16], resp[6]; + unsigned char csdchars[16]; + unsigned char *csdptr = csdchars; + + if (sd->hw_version) return sdsetwprot2(sd, perm); + + if (stop(sd)) return 1; + + perm = perm ? 0x3 : 0x1; + for (i = 0; i < 16; i++) csd[i] = sd->sd_csd[i + 1]; + csd[14] &= ~(0x3 << 4); + csd[14] |= (perm << 4); + csd[15] = 0x1 | crc7(0, csd, 15) << 1; + for (i = 0; i < 16; i++) csdchars[i] = csd[i]; + + ret = sdcmd(sd, CMD_PROGRAM_CSD, 0, resp, NULL); + if (ret || error(sd, resp, CMD_PROGRAM_CSD)) return 1; + datssp_stream(sd, &csdptr, 16); + datssp_stream(sd, NULL, 8); + SDPOKE8(sd, SDSTATE, S_CRC_CHECK | (TYPE_BSYRESP << 5)); + sd->sd_state &= ~SDDAT_TX; + + sdcmd(sd, CMD_DESELECT_CARD, ~sd->sd_rcaarg, NULL, NULL); + ret = sdcmd(sd, CMD_SEND_CSD, sd->sd_rcaarg, sd->sd_csd, NULL); + if (ret || sd->sd_csd[15] != csd[14]) { + return 1; + } + sdcmd(sd, CMD_SELECT_CARD, sd->sd_rcaarg, resp, NULL); + + sd->sd_wprot = 1; + return 0; +} + + +#ifndef SD_NOLOCKSUPPORT +int sdlockctl(struct sdcore *sd, unsigned int cmd, unsigned char *pwd, + unsigned char *sdbootdat) { + unsigned char pwddat[18]; + unsigned char *pwdptr = pwddat; + unsigned int resp[6]; + int ret, i, len; + int ccc = (sd->sd_csd[5] << 4) | (sd->sd_csd[6] >> 4); + + if (sd->hw_version) return sdlockctl2(sd, cmd, pwd, sdbootdat); + + if (!(ccc & 0x80)) return 1; // Class 7 is lock-unlock commands + + if (pwd == NULL && cmd != SDLOCK_ERASE) return 1; + + if (stop(sd)) return 1; + + if (sd->sd_state & DATSSP_4BIT) { + int oldctrl = SDPEEK8(sd, SDCTRL); + int ret; + + sdcmd(sd, CMD_APP_CMD, sd->sd_rcaarg, NULL, NULL); + sdcmd(sd, ACMD_SET_BUS_WIDTH, 0, NULL, NULL); + SDPOKE8(sd, SDCTRL, 0x20); + sd->sd_state &= ~DATSSP_4BIT; + ret = sdlockctl(sd, cmd, pwd, sdbootdat); + sdcmd(sd, CMD_APP_CMD, sd->sd_rcaarg, NULL, NULL); + sdcmd(sd, ACMD_SET_BUS_WIDTH, 2, NULL, NULL); + sd->sd_state |= DATSSP_4BIT; + SDPOKE8(sd, SDCTRL, oldctrl); + return ret; + } + + pwddat[0] = cmd; + if (cmd != SDLOCK_ERASE) { + pwddat[1] = 16; // length + for (i = 0; i < 16; i++) { + pwddat[2 + i] = pwd[i]; + } + } + + if (cmd == SDLOCK_ERASE) len = 1; else len = 18; + ret = sdcmd(sd, CMD_SET_BLOCKLEN, len, resp, NULL); + if (ret || error(sd, resp, CMD_SET_BLOCKLEN)) return 1; + ret = sdcmd(sd, CMD_LOCK_UNLOCK, 0, resp, NULL); + if (ret || error(sd, resp, CMD_LOCK_UNLOCK)) return 1; + + while ((pwdptr - pwddat) != len) { + if (timeout(sd)) return 1; + tend_ssp(sd, NULL, &pwdptr); + } + + if (sd->sd_state & DATSSP_4BIT) datssp_stream(sd, NULL, 8); + else datssp_stream(sd, NULL, 2); + + SDPOKE8(sd, SDSTATE, S_CRC_CHECK | (TYPE_BSYRESP << 5)); + sd->sd_state &= ~SDDAT_TX; + ret = sdcmd(sd, CMD_SET_BLOCKLEN, 512, resp, NULL); + if (ret || error(sd, resp, CMD_SET_BLOCKLEN)) return 1; + ret = sdcmd(sd, CMD_SEND_STATUS, sd->sd_rcaarg, resp, NULL); + if (ret || error(sd, resp, CMD_SEND_STATUS)) return 1; + + if ((cmd == SDLOCK_ERASE || cmd == SDLOCK_UNLOCK || + cmd == SDLOCK_CLRPWD) && (resp[1] & 0x2)) { + return 1; + } + + if (sdbootdat) { + sdbootdat[0] = SDLOCK_UNLOCK; + for (i = 1; i < 18; i++) { + sdbootdat[i] = pwddat[i]; + sd_1bit_feedcrc(sd, pwddat[i]); + } + sdbootdat[18] = sd_1bit_getcrc(sd); + sdbootdat[19] = sd_1bit_getcrc(sd); + } + + return 0; +} + + +static +int sdlockctl2(struct sdcore *sd, unsigned int cmd, unsigned char *pwd, + unsigned char *sdbootdat) { + unsigned char pwddat[18]; + unsigned char *pwdptr = pwddat; + unsigned int resp[6]; + int ret, i, j, len, s; + int ccc = (sd->sd_csd[5] << 4) | (sd->sd_csd[6] >> 4); + + if (!(ccc & 0x80)) return 1; // Class 7 is lock-unlock commands + + if (pwd == NULL && cmd != SDLOCK_ERASE) return 1; + + stop2(sd); + + if (sd->sd_state & DATSSP_4BIT) { + int ret; + + sdcmd2(sd, CMD_APP_CMD, sd->sd_rcaarg, NULL, NULL); + sdcmd2(sd, ACMD_SET_BUS_WIDTH, 0, NULL, NULL); + sd->sd_state &= ~DATSSP_4BIT; + ret = sdlockctl2(sd, cmd, pwd, sdbootdat); + sdcmd2(sd, CMD_APP_CMD, sd->sd_rcaarg, NULL, NULL); + sdcmd2(sd, ACMD_SET_BUS_WIDTH, 2, NULL, NULL); + sd->sd_state |= DATSSP_4BIT; + return ret; + } + + pwddat[0] = cmd; + if (cmd != SDLOCK_ERASE) { + pwddat[1] = 16; // length + for (i = 0; i < 16; i++) { + pwddat[2 + i] = pwd[i]; + } + } + + if (cmd == SDLOCK_ERASE) len = 1; else len = 18; + ret = sdcmd2(sd, CMD_SET_BLOCKLEN, len, resp, NULL); + if (ret || error(sd, resp, CMD_SET_BLOCKLEN)) return 1; + ret = sdcmd2(sd, CMD_LOCK_UNLOCK, 0, resp, NULL); + if (ret || error(sd, resp, CMD_LOCK_UNLOCK)) return 1; + + for (i = 0; i < len; i++) { + unsigned int b = *pwdptr++; + unsigned int x; + + sd_1bit_feedcrc(sd, b); + for (j = 0; j < 8; j++) { + x = 0x1e | ((b >> 7) & 0x1); + b = b << 1; + SDPOKE8(sd, SDGPIO, x); // clk negedge + SDPEEK8(sd, SDGPIO); + SDPEEK8(sd, SDGPIO); + x |= 0x20; + SDPOKE8(sd, SDGPIO, x); // clk posedge + SDPEEK8(sd, SDGPIO); + } + } + for (i = 0; i < 2; i++) { + unsigned int b = sd_1bit_getcrc(sd); + unsigned int x; + + for (j = 0; j < 8; j++) { + x = 0x1e | ((b >> 7) & 0x1); + b = b << 1; + SDPOKE8(sd, SDGPIO, x); // clk negedge + SDPEEK8(sd, SDGPIO); + SDPEEK8(sd, SDGPIO); + x |= 0x20; + SDPOKE8(sd, SDGPIO, x); // clk posedge + SDPEEK8(sd, SDGPIO); + } + } + // End bit + SDPOKE8(sd, SDGPIO, 0x1f); // clk negedge + SDPEEK8(sd, SDGPIO); + SDPOKE8(sd, SDGPIO, 0xbf); // clk posedge, tristate dat + // CRC ack + s = 0; + for (i = 0; i < 7; i++) { + SDPOKE8(sd, SDGPIO, 0x9f); // clk negedge + SDPEEK8(sd, SDGPIO); // delay + s = s << 1; + s |= SDPEEK8(sd, SDGPIO) & 0x1; + SDPOKE8(sd, SDGPIO, 0xbf); // clk posedge + SDPEEK8(sd, SDGPIO); + } + if ((s & 0xf) != 0x5) return 1; + + // wait for unbusy + s = 0; + while ((s & 0x7) != 0x7) { + if (timeout(sd)) break; + SDPOKE8(sd, SDGPIO, 0x9f); // clk negedge + SDPEEK8(sd, SDGPIO); // delay + s = s << 1; + s |= SDPEEK8(sd, SDGPIO) & 0x1; + SDPOKE8(sd, SDGPIO, 0xbf); + SDPEEK8(sd, SDGPIO); + } + for (i = 0; i < 8; i++) { + SDPOKE8(sd, SDGPIO, 0x9f); + SDPEEK8(sd, SDGPIO); + SDPEEK8(sd, SDGPIO); + SDPOKE8(sd, SDGPIO, 0xbf); + SDPEEK8(sd, SDGPIO); + } + + sd->sd_state &= ~SDDAT_TX; + ret = sdcmd2(sd, CMD_SET_BLOCKLEN, 512, resp, NULL); + if (ret || error(sd, resp, CMD_SET_BLOCKLEN)) { + return 1; + } + ret = sdcmd2(sd, CMD_SEND_STATUS, sd->sd_rcaarg, resp, NULL); + if (ret || error(sd, resp, CMD_SEND_STATUS)) { + return 1; + } + + if ((cmd == SDLOCK_ERASE || cmd == SDLOCK_UNLOCK || + cmd == SDLOCK_CLRPWD) && (resp[1] & 0x2)) { + return 1; + } + + if (sdbootdat) { + sdbootdat[0] = SDLOCK_UNLOCK; + for (i = 1; i < 18; i++) { + sdbootdat[i] = pwddat[i]; + sd_1bit_feedcrc(sd, pwddat[i]); + } + sdbootdat[18] = sd_1bit_getcrc(sd); + sdbootdat[19] = sd_1bit_getcrc(sd); + } + + for (i = 0; i < 8; i++) { + SDPOKE8(sd, SDGPIO, 0x9f); + SDPEEK8(sd, SDGPIO); + SDPEEK8(sd, SDGPIO); + SDPOKE8(sd, SDGPIO, 0xbf); + SDPEEK8(sd, SDGPIO); + } + return 0; +} +#endif +#undef DBG From c3c84806e95fab0daa1aa966e338036efbca15b3 Mon Sep 17 00:00:00 2001 From: Michael Peters Date: Fri, 17 Mar 2023 09:56:47 -0700 Subject: [PATCH 062/244] drivers: gpio: gpio-ts7800-v2: Initial commit Added support for TS-7800-V2 gpio. --- drivers/gpio/Kconfig | 8 + drivers/gpio/Makefile | 1 + drivers/gpio/gpio-ts7800-v2.c | 486 ++++++++++++++++++++++++++++++++++ 3 files changed, 495 insertions(+) create mode 100644 drivers/gpio/gpio-ts7800-v2.c diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 9b4995e1d743f..b60377305995a 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -1747,6 +1747,14 @@ config GPIO_WM8994 Say yes here to access the GPIO signals of WM8994 audio hub CODECs from Wolfson Microelectronics. +config GPIO_TS7800V2 + tristate "embeddedTS TS-7800 FPGA GPIO support" + depends on MFD_TS78XX + select GPIO_GENERIC + default n + help + This driver supports the TS-7800-V2 FPGA GPIO controller. + endmenu menu "PCI GPIO expanders" diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index e94ac4ea68059..6cf4bcb303413 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -192,6 +192,7 @@ obj-$(CONFIG_GPIO_TS4800) += gpio-ts4800.o obj-$(CONFIG_GPIO_TS4900) += gpio-ts4900.o obj-$(CONFIG_GPIO_TS5500) += gpio-ts5500.o obj-$(CONFIG_GPIO_TS71XXWEIM) += gpio-ts71xxweim.o +obj-$(CONFIG_GPIO_TS7800V2) += gpio-ts7800-v2.o obj-$(CONFIG_GPIO_TWL4030) += gpio-twl4030.o obj-$(CONFIG_GPIO_TWL6040) += gpio-twl6040.o obj-$(CONFIG_GPIO_UNIPHIER) += gpio-uniphier.o diff --git a/drivers/gpio/gpio-ts7800-v2.c b/drivers/gpio/gpio-ts7800-v2.c new file mode 100644 index 0000000000000..8c358dde65971 --- /dev/null +++ b/drivers/gpio/gpio-ts7800-v2.c @@ -0,0 +1,486 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Digital I/O driver for Technologic Systems TS-7800-V2 + */ + +#include +#include +#include +#include +#include +#include + +#define TS7800V2_NR_DIO 121 + +#define LCD_DIO_DATA 0x4 +#define LCD_DIO_OUT 0X8 +#define MISC_IO 0xC +#define ROW_A_DATA 0x10 +#define ROW_B_DATA 0x14 +#define ROW_C_DATA 0x18 +#define ROW_D_DATA 0x1C +#define ROW_A_DIR 0x20 +#define ROW_B_DIR 0x24 +#define ROW_C_DIR 0x28 +#define ROW_D_DIR 0x2c + +struct ts7800v2_gpio_priv { + void __iomem *syscon; + struct gpio_chip gpio_chip; + spinlock_t lock; +}; + +/* DIO number : bit position in relevant syscon reg or regs */ +static unsigned int dio_bitpositions[] = { + 0, // 0 DIO_01, CN8 pin 1 + 2, // 1 DIO_03, CN8 pin 3 + 3, // 2 DIO_04, CN8 pin 4 + 4, // 3 DIO_05, CN8 pin 5 + 5, // 4 SPI_FRAME, CN8 pin 6 + 6, // 5 DIO_07, CN8 pin 7 + 7, // 6 DIO_08, CN8 pin 8 + 8, // 7 DIO_09, CN8 pin 9 + 9, // 8 SPI_MISO, CN8 pin 10 (read-only) + 10, // 9 DIO_11, CN8 pin 11 + 11, // 10 SPI_MOSI, CN8 pin 12 + 12, // 11 DIO_13, CN8 pin 13 + 13, // 12 SPI_CLK, CN8 pin 14 + 14, // 13 DIO_15, CN8 pin 15 + + 18, // 14 RS, CN7 pin 3 + 19, // 15 BIAS, CN7 pin 4 + 20, // 16 EN, CN7 pin 5 + 21, // 17 RW, CN7 pin 6 + 22, // 18 DB1, CN7 pin 7 + 23, // 19 DB0, CN7 pin 8 + 24, // 20 DB3, CN7 pin 9 + 25, // 21 DB2, CN7 pin 10 + 26, // 22 DB5, CN7 pin 11 + 27, // 23 DB4, CN7 pin 12 + 28, // 24 DB7, CN7 pin 13 + 29, // 25 DB6, CN7 pin 14 + + 0, // 26 A[0] CN5 pin A1 + 1, // 27 A[1] + 2, // 28 A[2] + 3, // 29 A[3] + 4, // 30 A[4] + 5, // 31 A[5] + 6, // 32 A[6] + 7, // 33 A[7] + 8, // 34 A[8] + 9, // 35 A[9] + 10, // 36 A[10] + 11, // 37 A[11] + 12, // 38 A[12] + 13, // 39 A[13] + 14, // 40 A[14] + 15, // 41 A[15] + 16, // 42 A[16] + 17, // 43 A[17] + 18, // 44 A[18] + 19, // 45 A[19] + 20, // 46 A[20] + 21, // 47 A[21] + 22, // 48 A[22] + 23, // 49 A[23] + 24, // 50 A[24] + 25, // 51 A[25] + 26, // 52 A[26] + 27, // 53 A[27] + 28, // 54 A[28] + 29, // 55 A[28] + 30, // 56 A[30] CN5 pin 31 + 31, // 57 A[31] whoops, there is no A[31] on CN5 + + 1, // 58 B[1] CN5 pin B2 + 3, // 59 B[3] CN5 pin B4 + 5, // 60 B[5] CN5 pin B6 + 6, // 61 B[6] CN5 pin B7 + 7, // 62 B[7] CN5 pin B8 + 10, // 63 B[10] CN5 pin B11 + 11, // 64 B[11] CN5 pin B12 + 12, // 65 B[12] CN5 pin B13 + 13, // 66 B[13] CN5 pin B14 + 14, // 67 B[14] CN5 pin B15 + 15, // 68 B[15] CN5 pin B16 + 16, // 69 B[16] CN5 pin B17 + 17, // 70 B[17] CN5 pin B18 + 18, // 71 B[18] CN5 pin B19 + 19, // 72 B[19] CN5 pin B20 + 20, // 73 B[20] CN5 pin B21 + 21, // 74 B[21] CN5 pin B22 + 22, // 75 B[22] CN5 pin B23 + 23, // 76 B[23] CN5 pin B24 + 24, // 77 B[24] CN5 pin B25 + 25, // 78 B[25] CN5 pin B26 + 26, // 79 B[26] CN5 pin B27 + 27, // 80 B[27] CN5 pin B28 + 29, // 81 B[29] CN5 pin B30 + 31, // 82 B[31] CN5 pin B32 + + 1, // 83 C[1] CN6 pin C1 + 2, // 84 C[2] CN6 pin C2 + 3, // 85 C[3] CN6 pin C3 + 4, // 86 C[4] CN6 pin C4 + 5, // 87 C[5] CN6 pin C5 + 6, // 88 C[6] CN6 pin C6 + 7, // 89 C[7] CN6 pin C7 + 8, // 90 C[8] CN6 pin C8 + 9, // 91 C[9] CN6 pin C9 + 10, // 92 C[10] CN6 pin C10 + 11, // 93 C[11] CN6 pin C11 + 12, // 94 C[12] CN6 pin C12 + 13, // 95 C[13] CN6 pin C13 + 14, // 96 C[14] CN6 pin C14 + 15, // 97 C[15] CN6 pin C15 + 16, // 98 C[16] CN6 pin C16 + 17, // 99 C[17] CN6 pin C17 + 18, // 100 C[18] CN6 pin C18 + + 1, // 101 D[1] CN6 pin D1 + 2, // 102 D[2] CN6 pin D2 + 3, // 103 D[3] CN6 pin D3 + 4, // 104 D[4] CN6 pin D4 (read-only) + 5, // 105 D[5] CN6 pin D5 (read-only) + 6, // 106 D[6] CN6 pin D6 (read-only) + 7, // 107 D[7] CN6 pin D7 (read-only) + 9, // 108 D[9] CN6 pin D9 + 10, // 109 D[10] CN6 pin D10 + 11, // 110 D[11] CN6 pin D11 + 12, // 111 D[12] CN6 pin D12 + 13, // 112 D[13] CN6 pin D13 + 14, // 113 D[14] CN6 pin D14 + 15, // 114 D[15] CN6 pin D15 + 17, // 115 D[17] CN6 pin D17 + + 21, // 116 EN_WIFI_PWR + 22, // 117 WIFI_RESET + + 30, // 118 Green LED Register 0x8 + 20, // 119 Red LED Register 0xC + + 31, // 120 CPU_ACCESS_FPGA_FLASH# Register 0x8 +}; + +static inline struct ts7800v2_gpio_priv *to_gpio_ts7800v2(struct gpio_chip *chip) +{ + return container_of(chip, struct ts7800v2_gpio_priv, gpio_chip); +} + +static int ts7800v2_gpio_get_direction(struct gpio_chip *chip, + unsigned int offset) +{ + struct ts7800v2_gpio_priv *priv = to_gpio_ts7800v2(chip); + unsigned int reg, bit, ret; + + bit = BIT(dio_bitpositions[offset]); + + if (offset >= TS7800V2_NR_DIO) + return -EINVAL; + + /* offset < 26 is special because open drain. */ + if (offset < 26) { + reg = readl(priv->syscon + LCD_DIO_OUT); + ret = !(reg & bit); + } else if (offset < 58) { + reg = readl(priv->syscon + ROW_A_DIR); + ret = !!(reg & bit); + } else if (offset < 83) { + reg = readl(priv->syscon + ROW_B_DIR); + ret = !!(reg & bit); + } else if (offset < 101) { + reg = readl(priv->syscon + ROW_C_DIR); + ret = !!(reg & bit); + } else if (offset < 116) { + reg = readl(priv->syscon + ROW_D_DIR); + ret = !!(reg & bit); + } + /* offset > 116 are all output-only. */ + else + ret = 0; + + return ret; +} + +static int ts7800v2_gpio_direction_input(struct gpio_chip *chip, + unsigned int offset) +{ + struct ts7800v2_gpio_priv *priv = to_gpio_ts7800v2(chip); + unsigned int reg, bit; + unsigned long flags; + int ret = 0; + + if (offset >= TS7800V2_NR_DIO) + return -EINVAL; + + bit = BIT(dio_bitpositions[offset]); + + spin_lock_irqsave(&priv->lock, flags); + + if (offset < 26) { + /* + * The LCD/DIO pins are open-drain with pull-ups, so making + * one an 'input' is the same as setting the pin high + */ + reg = readl(priv->syscon + LCD_DIO_OUT); + reg |= bit; + writel(reg, priv->syscon + LCD_DIO_OUT); + } else if (offset < 58) { + reg = readl(priv->syscon + ROW_A_DIR); + reg &= ~bit; + writel(reg, priv->syscon + ROW_A_DIR); + } else if (offset < 83) { + reg = readl(priv->syscon + ROW_B_DIR); + reg &= ~bit; + writel(reg, priv->syscon + ROW_B_DIR); + } else if (offset < 101) { + reg = readl(priv->syscon + ROW_C_DIR); + reg &= ~bit; + writel(reg, priv->syscon + ROW_C_DIR); + } else if (offset < 116) { + reg = readl(priv->syscon + ROW_D_DIR); + + reg &= ~bit; + writel(reg, priv->syscon + ROW_D_DIR); + } else { + ret = -EINVAL; + } + + spin_unlock_irqrestore(&priv->lock, flags); + + return ret; +} + +static unsigned int ts7800v2_gpio_rmw(unsigned int reg, unsigned int bit, + int value) +{ + if (value) + reg |= bit; + else + reg &= ~bit; + return reg; +} + +static int ts7800v2_gpio_direction_output(struct gpio_chip *chip, + unsigned int offset, int value) +{ + struct ts7800v2_gpio_priv *priv = to_gpio_ts7800v2(chip); + unsigned int reg, bit; + unsigned long flags; + int ret = 0; + + bit = BIT(dio_bitpositions[offset]); + + spin_lock_irqsave(&priv->lock, flags); + + if (offset < 26) { + /* SPI_MISO, read-only pin, can't make an output */ + if (offset == 8) { + ret = -EINVAL; + } else { + reg = readl(priv->syscon + LCD_DIO_OUT); + reg = ts7800v2_gpio_rmw(reg, bit, value); + writel(reg, priv->syscon + LCD_DIO_OUT); + } + } else if (offset < 58) { /* pc/104 Row A */ + reg = readl(priv->syscon + ROW_A_DATA); + reg = ts7800v2_gpio_rmw(reg, bit, value); + writel(reg, priv->syscon + ROW_A_DATA); + reg = readl(priv->syscon + ROW_A_DIR); + reg |= bit; + writel(reg, priv->syscon + ROW_A_DIR); + } else if (offset < 83) { /* pc/104 Row B */ + reg = readl(priv->syscon + ROW_B_DATA); + reg = ts7800v2_gpio_rmw(reg, bit, value); + writel(reg, priv->syscon + ROW_B_DATA); + reg = readl(priv->syscon + ROW_B_DIR); + reg |= bit; + writel(reg, priv->syscon + ROW_B_DIR); + } else if (offset < 101) { /* pc/104 Row C */ + reg = readl(priv->syscon + ROW_C_DATA); + reg = ts7800v2_gpio_rmw(reg, bit, value); + writel(reg, priv->syscon + ROW_C_DATA); + reg = readl(priv->syscon + ROW_C_DIR); + reg |= bit; + writel(reg, priv->syscon + ROW_C_DIR); + } else if (offset < 116) { /* pc/104 Row D */ + if (offset >= 104 && offset <= 107) { + /* D[4..7], read-only pins */ + ret = -EINVAL; + } else { + reg = readl(priv->syscon + ROW_D_DATA); + reg = ts7800v2_gpio_rmw(reg, bit, value); + writel(reg, priv->syscon + ROW_D_DATA); + reg = readl(priv->syscon + ROW_D_DIR); + reg |= bit; + writel(reg, priv->syscon + ROW_D_DIR); + } + } else if (offset < 118) { /* WIFI control bits, nothing to do */ + reg = readl(priv->syscon + MISC_IO); + reg = ts7800v2_gpio_rmw(reg, bit, value); + writel(reg, priv->syscon + MISC_IO); + } else if (offset == 118) { /* Green LED */ + reg = readl(priv->syscon + LCD_DIO_OUT); + reg = ts7800v2_gpio_rmw(reg, bit, value); + writel(reg, priv->syscon + LCD_DIO_OUT); + } else if (offset == 119) { /* Red LED */ + reg = readl(priv->syscon + MISC_IO); + reg = ts7800v2_gpio_rmw(reg, bit, value); + writel(reg, priv->syscon + MISC_IO); + } else if (offset == 120) { /* CPU_ACCESS_FPGA_FLASH */ + reg = readl(priv->syscon + LCD_DIO_OUT); + reg = ts7800v2_gpio_rmw(reg, bit, value); + writel(reg, priv->syscon + LCD_DIO_OUT); + } else { + ret = -EINVAL; + } + + spin_unlock_irqrestore(&priv->lock, flags); + + return ret; +} + +static int ts7800v2_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + struct ts7800v2_gpio_priv *priv = to_gpio_ts7800v2(chip); + unsigned int reg_num, reg, bit; + + bit = BIT(dio_bitpositions[offset]); + + if (offset < 26) + reg_num = LCD_DIO_DATA; + else if (offset < 58) + reg_num = ROW_A_DATA; + else if (offset < 83) + reg_num = ROW_B_DATA; + else if (offset < 101) + reg_num = ROW_C_DATA; + else if (offset < 116) + reg_num = ROW_D_DATA; + else if (offset < 118) + reg_num = MISC_IO; + else + return -1; + + reg = readl(priv->syscon + reg_num); + return !!(reg & bit); +} + +static void ts7800v2_gpio_set(struct gpio_chip *chip, unsigned int offset, + int value) +{ + struct ts7800v2_gpio_priv *priv = to_gpio_ts7800v2(chip); + unsigned int reg_num, reg, bit; + unsigned long flags; + + bit = BIT(dio_bitpositions[offset]); + + if (offset < 26) { /* DIO or LCD header, */ + if (offset == 8) { /* SPI_MISO, read-only pin, can't set */ + dev_info(priv->gpio_chip.parent, "error: DIO #%d, read-only pin, can't be set\n", + priv->gpio_chip.base + offset); + return; + } + reg_num = LCD_DIO_OUT; + } else if (offset < 58) { /* pc/104 Row A */ + reg_num = ROW_A_DATA; + } else if (offset < 83) { /* pc/104 Row B */ + reg_num = ROW_B_DATA; + } else if (offset < 101) { /* pc/104 Row C */ + if (offset >= 104 && offset <= 107) { /* D[4..7], read-only pins */ + return; + } + reg_num = ROW_C_DATA; + } else if (offset < 116) { /* pc/104 Row D */ + reg_num = ROW_D_DATA; + } else if (offset < 118) { /* WIFI control bits */ + reg_num = MISC_IO; + } else if (offset == 118) { /* Green LED */ + reg_num = LCD_DIO_OUT; + } else if (offset == 119) { /* Red LED */ + reg_num = MISC_IO; + } else if (offset == 120) { /* CPU_ACCESS_FPGA_FLASH */ + reg_num = LCD_DIO_OUT; + } else { + return; + } + + spin_lock_irqsave(&priv->lock, flags); + reg = readl(priv->syscon + reg_num); + if (value) + reg |= bit; + else + reg &= ~bit; + writel(reg, priv->syscon + reg_num); + spin_unlock_irqrestore(&priv->lock, flags); +} + +static const struct gpio_chip template_chip = { + .label = "ts7800v2-gpio", + .owner = THIS_MODULE, + .get_direction = ts7800v2_gpio_get_direction, + .direction_input = ts7800v2_gpio_direction_input, + .direction_output = ts7800v2_gpio_direction_output, + .get = ts7800v2_gpio_get, + .set = ts7800v2_gpio_set, + .base = -1, + .can_sleep = false, +}; + +static const struct of_device_id ts7800v2_gpio_of_match_table[] = { + { + .compatible = "technologic,ts7800v2-gpio", + }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, ts7800v2_gpio_of_match_table); + +static int ts7800v2_gpio_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct ts7800v2_gpio_priv *priv; + void __iomem *membase; + struct resource *res; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENXIO; + + membase = devm_ioremap(dev, res->start, resource_size(res)); + + if (IS_ERR(membase)) { + pr_err("Could not map resource\n"); + return -ENOMEM; + } + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->syscon = membase; + spin_lock_init(&priv->lock); + priv->gpio_chip = template_chip; + priv->gpio_chip.label = "ts7800v2-gpio"; + priv->gpio_chip.ngpio = TS7800V2_NR_DIO; + priv->gpio_chip.base = -1; + pdev->dev.platform_data = &priv; + priv->gpio_chip.parent = dev; + + platform_set_drvdata(pdev, priv); + + return devm_gpiochip_add_data(dev, &priv->gpio_chip, priv); +} + +static struct platform_driver ts7800v2_gpio_driver = { + .driver = { + .name = "ts7800v2-gpio", + .of_match_table = of_match_ptr(ts7800v2_gpio_of_match_table), + }, + .probe = ts7800v2_gpio_probe, +}; +module_platform_driver(ts7800v2_gpio_driver); + +MODULE_AUTHOR("Technologic Systems"); +MODULE_DESCRIPTION("GPIO interface for Technologic Systems TS-7800-V2 DIO"); +MODULE_LICENSE("GPL"); From 4da7269ce5903bc326782b41f6861cb287aac2e8 Mon Sep 17 00:00:00 2001 From: Michael Peters Date: Fri, 17 Mar 2023 09:59:33 -0700 Subject: [PATCH 063/244] drivers: gpio: gpio-ts7820: Initial commit Added support for the TS-7820 GPIO. --- drivers/gpio/Kconfig | 9 ++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-ts7820.c | 236 +++++++++++++++++++++++++++++++++++++ 3 files changed, 246 insertions(+) create mode 100644 drivers/gpio/gpio-ts7820.c diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index b60377305995a..17f49be15af7a 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -1755,6 +1755,15 @@ config GPIO_TS7800V2 help This driver supports the TS-7800-V2 FPGA GPIO controller. +config GPIO_TS7820 + tristate "embeddedTS' TS-7820/TS-7840 GPIO Support" + select GPIO_GENERIC + select GPIOLIB_IRQCHIP + depends on MFD_TS78XX + default n + help + Say yes here to support GPIO on the TS-78XX. + endmenu menu "PCI GPIO expanders" diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 6cf4bcb303413..9b2e80bd503ee 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -193,6 +193,7 @@ obj-$(CONFIG_GPIO_TS4900) += gpio-ts4900.o obj-$(CONFIG_GPIO_TS5500) += gpio-ts5500.o obj-$(CONFIG_GPIO_TS71XXWEIM) += gpio-ts71xxweim.o obj-$(CONFIG_GPIO_TS7800V2) += gpio-ts7800-v2.o +obj-$(CONFIG_GPIO_TS7820) += gpio-ts7820.o obj-$(CONFIG_GPIO_TWL4030) += gpio-twl4030.o obj-$(CONFIG_GPIO_TWL6040) += gpio-twl6040.o obj-$(CONFIG_GPIO_UNIPHIER) += gpio-uniphier.o diff --git a/drivers/gpio/gpio-ts7820.c b/drivers/gpio/gpio-ts7820.c new file mode 100644 index 0000000000000..9767445b8391f --- /dev/null +++ b/drivers/gpio/gpio-ts7820.c @@ -0,0 +1,236 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Read Decodes */ +#define TS7820_OE_IN 0x00 +#define TS7820_OUT_DATA 0x08 +#define TS7820_IN 0x0C +/*#define TS7820_IRQ_EN 0x10 */ +#define TS7820_IRQSTATUS 0x14 + +/* Write Decodes */ +#define TS7820_OE_SET 0x00 +#define TS7820_OE_CLR 0x04 +#define TS7820_DAT_SET 0x08 +#define TS7820_DAT_CLR 0x0C +#define TS7820_IRQ_EN 0x10 +#define TS7820_IRQ_NPOL 0x18 /* 1 = active low */ + +struct ts7820_gpio { + void __iomem *base; + struct device *dev; + struct gpio_chip chip; + struct irq_chip irqchip; + raw_spinlock_t lock; + uint32_t npol; + int irq; +}; + +static void ts7820_gpio_set(struct gpio_chip *chip, unsigned int pin, int val) +{ + struct ts7820_gpio *ts7820_gpio = gpiochip_get_data(chip); + + if (val) + writel(BIT(pin), ts7820_gpio->base + TS7820_DAT_SET); + else + writel(BIT(pin), ts7820_gpio->base + TS7820_DAT_CLR); +} + +static void ts7820_gpio_set_multiple(struct gpio_chip *chip, + unsigned long *mask, + unsigned long *bits) +{ + struct ts7820_gpio *ts7820_gpio = gpiochip_get_data(chip); + + writel(*mask & *bits, ts7820_gpio->base + TS7820_DAT_SET); + writel(*mask & (~*bits), ts7820_gpio->base + TS7820_DAT_CLR); +} + +static int ts7820_gpio_get(struct gpio_chip *chip, unsigned int pin) +{ + struct ts7820_gpio *ts7820_gpio = gpiochip_get_data(chip); + + return !!(readl(ts7820_gpio->base + TS7820_IN) & BIT(pin)); +} + +static int ts7820_gpio_direction_input(struct gpio_chip *chip, + unsigned int pin) +{ + struct ts7820_gpio *ts7820_gpio = gpiochip_get_data(chip); + + writel(BIT(pin), ts7820_gpio->base + TS7820_OE_CLR); + return 0; +} + +static int ts7820_gpio_direction_output(struct gpio_chip *chip, + unsigned int pin, int val) +{ + struct ts7820_gpio *ts7820_gpio = gpiochip_get_data(chip); + + ts7820_gpio_set(chip, pin, val); + writel(BIT(pin), ts7820_gpio->base + TS7820_OE_SET); + return 0; +} + +static int ts7820_gpio_direction_get(struct gpio_chip *chip, + unsigned int pin) +{ + struct ts7820_gpio *ts7820_gpio = gpiochip_get_data(chip); + + return !(readl(ts7820_gpio->base + TS7820_OE_IN) & BIT(pin)); +} + +static void gpio_ts7820_irq_disable(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct ts7820_gpio *ts7820_gpio = gpiochip_get_data(gc); + u32 irqen; + + raw_spin_lock(&ts7820_gpio->lock); + irqen = readl(ts7820_gpio->base + TS7820_IRQ_EN); + irqen &= ~BIT(irqd_to_hwirq(d)); + writel(irqen, ts7820_gpio->base + TS7820_IRQ_EN); + raw_spin_unlock(&ts7820_gpio->lock); +} + +static void gpio_ts7820_irq_enable(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct ts7820_gpio *ts7820_gpio = gpiochip_get_data(gc); + u32 irqen; + + raw_spin_lock(&ts7820_gpio->lock); + irqen = readl(ts7820_gpio->base + TS7820_IRQ_EN); + irqen |= BIT(irqd_to_hwirq(d)); + writel(irqen, ts7820_gpio->base + TS7820_IRQ_EN); + raw_spin_unlock(&ts7820_gpio->lock); +} + +static int gpio_ts7820_irq_set_type(struct irq_data *d, unsigned int type) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct ts7820_gpio *ts7820_gpio = gpiochip_get_data(gc); + unsigned int hwirq = irqd_to_hwirq(d); + int ret = 0; + + irq_set_status_flags(d->irq, IRQ_IS_POLLED); + + ts7820_gpio->npol &= ~hwirq; + + switch (type & IRQ_TYPE_SENSE_MASK) { + case IRQ_TYPE_LEVEL_HIGH: + ts7820_gpio->npol &= ~(1 << hwirq); + writel(ts7820_gpio->npol, ts7820_gpio->base + TS7820_IRQ_NPOL); + break; + case IRQ_TYPE_LEVEL_LOW: + ts7820_gpio->npol |= (1 << hwirq); + writel(ts7820_gpio->npol, ts7820_gpio->base + TS7820_IRQ_NPOL); + break; + case IRQ_TYPE_EDGE_FALLING: + default: + ret = -EINVAL; + } + + return ret; +} + +static void gpio_ts7820_irq_handler(struct irq_desc *desc) +{ + struct gpio_chip *gc = irq_desc_get_handler_data(desc); + struct ts7820_gpio *ts7820_gpio = gpiochip_get_data(gc); + struct irq_chip *irqchip = irq_desc_get_chip(desc); + unsigned long status; + u32 bit, girq; + + chained_irq_enter(irqchip, desc); + status = readl(ts7820_gpio->base + TS7820_IRQSTATUS) & + readl(ts7820_gpio->base + TS7820_IRQ_EN); + + for_each_set_bit(bit, &status, 32) { + girq = irq_find_mapping(ts7820_gpio->chip.irq.domain, bit); + generic_handle_irq(girq); + } + chained_irq_exit(irqchip, desc); +} + +static int ts7820_gpio_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct ts7820_gpio *ts7820_gpio; + struct gpio_irq_chip *girq; + + ts7820_gpio = devm_kzalloc(dev, sizeof(struct ts7820_gpio), GFP_KERNEL); + if (!ts7820_gpio) + return -ENOMEM; + + ts7820_gpio->irq = platform_get_irq(pdev, 0); + + ts7820_gpio->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(ts7820_gpio->base)) + return PTR_ERR(ts7820_gpio->base); + + ts7820_gpio->dev = dev; + + raw_spin_lock_init(&ts7820_gpio->lock); + + ts7820_gpio->chip.label = dev_name(dev); + ts7820_gpio->chip.owner = THIS_MODULE; + ts7820_gpio->chip.direction_input = ts7820_gpio_direction_input; + ts7820_gpio->chip.direction_output = ts7820_gpio_direction_output; + ts7820_gpio->chip.get_direction = ts7820_gpio_direction_get; + ts7820_gpio->chip.set = ts7820_gpio_set; + ts7820_gpio->chip.set_multiple = ts7820_gpio_set_multiple; + ts7820_gpio->chip.get = ts7820_gpio_get; + ts7820_gpio->chip.base = -1; + ts7820_gpio->chip.ngpio = 32; + ts7820_gpio->chip.parent = dev; + + if (ts7820_gpio->irq >= 0) { + girq = &ts7820_gpio->chip.irq; + girq->chip = &ts7820_gpio->irqchip; + girq->chip->name = "ts7820-gpio"; + girq->chip->irq_mask = gpio_ts7820_irq_disable; + girq->chip->irq_unmask = gpio_ts7820_irq_enable; + girq->chip->irq_set_type = gpio_ts7820_irq_set_type; + girq->handler = handle_level_irq; + girq->parent_handler = gpio_ts7820_irq_handler; + girq->num_parents = 1; + girq->parents = devm_kcalloc(&pdev->dev, 1, + sizeof(*girq->parents), + GFP_KERNEL); + if (!girq->parents) + return -ENOMEM; + girq->parents[0] = ts7820_gpio->irq; + } + + return devm_gpiochip_add_data(dev, &ts7820_gpio->chip, ts7820_gpio); +} + +static const struct of_device_id ts7820_gpio_of_match[] = { + { .compatible = "technologic,ts7820-gpio", }, + {}, +}; +MODULE_DEVICE_TABLE(of, ts7820_gpio_of_match); + +static struct platform_driver ts7820_gpio_driver = { + .probe = ts7820_gpio_probe, + .driver = { + .name = "ts7820-gpio", + .of_match_table = ts7820_gpio_of_match, + .suppress_bind_attrs = true, + }, +}; +module_platform_driver(ts7820_gpio_driver); + +MODULE_AUTHOR("Mark Featherston "); +MODULE_DESCRIPTION("TS-7820 FPGA GPIO driver"); +MODULE_LICENSE("GPL v2"); From 1bbdb4d1c838da6cc858564520aae3a068ca7c6b Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Wed, 17 Sep 2025 20:58:46 +0000 Subject: [PATCH 064/244] Revert "drivers: gpio: gpio-ts7820: Initial commit" This reverts commit 2c8b48f50889d68c2dd934820228dc77db1a0260. --- drivers/gpio/Kconfig | 9 -- drivers/gpio/Makefile | 1 - drivers/gpio/gpio-ts7820.c | 236 ------------------------------------- 3 files changed, 246 deletions(-) delete mode 100644 drivers/gpio/gpio-ts7820.c diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 17f49be15af7a..b60377305995a 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -1755,15 +1755,6 @@ config GPIO_TS7800V2 help This driver supports the TS-7800-V2 FPGA GPIO controller. -config GPIO_TS7820 - tristate "embeddedTS' TS-7820/TS-7840 GPIO Support" - select GPIO_GENERIC - select GPIOLIB_IRQCHIP - depends on MFD_TS78XX - default n - help - Say yes here to support GPIO on the TS-78XX. - endmenu menu "PCI GPIO expanders" diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 9b2e80bd503ee..6cf4bcb303413 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -193,7 +193,6 @@ obj-$(CONFIG_GPIO_TS4900) += gpio-ts4900.o obj-$(CONFIG_GPIO_TS5500) += gpio-ts5500.o obj-$(CONFIG_GPIO_TS71XXWEIM) += gpio-ts71xxweim.o obj-$(CONFIG_GPIO_TS7800V2) += gpio-ts7800-v2.o -obj-$(CONFIG_GPIO_TS7820) += gpio-ts7820.o obj-$(CONFIG_GPIO_TWL4030) += gpio-twl4030.o obj-$(CONFIG_GPIO_TWL6040) += gpio-twl6040.o obj-$(CONFIG_GPIO_UNIPHIER) += gpio-uniphier.o diff --git a/drivers/gpio/gpio-ts7820.c b/drivers/gpio/gpio-ts7820.c deleted file mode 100644 index 9767445b8391f..0000000000000 --- a/drivers/gpio/gpio-ts7820.c +++ /dev/null @@ -1,236 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* Read Decodes */ -#define TS7820_OE_IN 0x00 -#define TS7820_OUT_DATA 0x08 -#define TS7820_IN 0x0C -/*#define TS7820_IRQ_EN 0x10 */ -#define TS7820_IRQSTATUS 0x14 - -/* Write Decodes */ -#define TS7820_OE_SET 0x00 -#define TS7820_OE_CLR 0x04 -#define TS7820_DAT_SET 0x08 -#define TS7820_DAT_CLR 0x0C -#define TS7820_IRQ_EN 0x10 -#define TS7820_IRQ_NPOL 0x18 /* 1 = active low */ - -struct ts7820_gpio { - void __iomem *base; - struct device *dev; - struct gpio_chip chip; - struct irq_chip irqchip; - raw_spinlock_t lock; - uint32_t npol; - int irq; -}; - -static void ts7820_gpio_set(struct gpio_chip *chip, unsigned int pin, int val) -{ - struct ts7820_gpio *ts7820_gpio = gpiochip_get_data(chip); - - if (val) - writel(BIT(pin), ts7820_gpio->base + TS7820_DAT_SET); - else - writel(BIT(pin), ts7820_gpio->base + TS7820_DAT_CLR); -} - -static void ts7820_gpio_set_multiple(struct gpio_chip *chip, - unsigned long *mask, - unsigned long *bits) -{ - struct ts7820_gpio *ts7820_gpio = gpiochip_get_data(chip); - - writel(*mask & *bits, ts7820_gpio->base + TS7820_DAT_SET); - writel(*mask & (~*bits), ts7820_gpio->base + TS7820_DAT_CLR); -} - -static int ts7820_gpio_get(struct gpio_chip *chip, unsigned int pin) -{ - struct ts7820_gpio *ts7820_gpio = gpiochip_get_data(chip); - - return !!(readl(ts7820_gpio->base + TS7820_IN) & BIT(pin)); -} - -static int ts7820_gpio_direction_input(struct gpio_chip *chip, - unsigned int pin) -{ - struct ts7820_gpio *ts7820_gpio = gpiochip_get_data(chip); - - writel(BIT(pin), ts7820_gpio->base + TS7820_OE_CLR); - return 0; -} - -static int ts7820_gpio_direction_output(struct gpio_chip *chip, - unsigned int pin, int val) -{ - struct ts7820_gpio *ts7820_gpio = gpiochip_get_data(chip); - - ts7820_gpio_set(chip, pin, val); - writel(BIT(pin), ts7820_gpio->base + TS7820_OE_SET); - return 0; -} - -static int ts7820_gpio_direction_get(struct gpio_chip *chip, - unsigned int pin) -{ - struct ts7820_gpio *ts7820_gpio = gpiochip_get_data(chip); - - return !(readl(ts7820_gpio->base + TS7820_OE_IN) & BIT(pin)); -} - -static void gpio_ts7820_irq_disable(struct irq_data *d) -{ - struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct ts7820_gpio *ts7820_gpio = gpiochip_get_data(gc); - u32 irqen; - - raw_spin_lock(&ts7820_gpio->lock); - irqen = readl(ts7820_gpio->base + TS7820_IRQ_EN); - irqen &= ~BIT(irqd_to_hwirq(d)); - writel(irqen, ts7820_gpio->base + TS7820_IRQ_EN); - raw_spin_unlock(&ts7820_gpio->lock); -} - -static void gpio_ts7820_irq_enable(struct irq_data *d) -{ - struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct ts7820_gpio *ts7820_gpio = gpiochip_get_data(gc); - u32 irqen; - - raw_spin_lock(&ts7820_gpio->lock); - irqen = readl(ts7820_gpio->base + TS7820_IRQ_EN); - irqen |= BIT(irqd_to_hwirq(d)); - writel(irqen, ts7820_gpio->base + TS7820_IRQ_EN); - raw_spin_unlock(&ts7820_gpio->lock); -} - -static int gpio_ts7820_irq_set_type(struct irq_data *d, unsigned int type) -{ - struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct ts7820_gpio *ts7820_gpio = gpiochip_get_data(gc); - unsigned int hwirq = irqd_to_hwirq(d); - int ret = 0; - - irq_set_status_flags(d->irq, IRQ_IS_POLLED); - - ts7820_gpio->npol &= ~hwirq; - - switch (type & IRQ_TYPE_SENSE_MASK) { - case IRQ_TYPE_LEVEL_HIGH: - ts7820_gpio->npol &= ~(1 << hwirq); - writel(ts7820_gpio->npol, ts7820_gpio->base + TS7820_IRQ_NPOL); - break; - case IRQ_TYPE_LEVEL_LOW: - ts7820_gpio->npol |= (1 << hwirq); - writel(ts7820_gpio->npol, ts7820_gpio->base + TS7820_IRQ_NPOL); - break; - case IRQ_TYPE_EDGE_FALLING: - default: - ret = -EINVAL; - } - - return ret; -} - -static void gpio_ts7820_irq_handler(struct irq_desc *desc) -{ - struct gpio_chip *gc = irq_desc_get_handler_data(desc); - struct ts7820_gpio *ts7820_gpio = gpiochip_get_data(gc); - struct irq_chip *irqchip = irq_desc_get_chip(desc); - unsigned long status; - u32 bit, girq; - - chained_irq_enter(irqchip, desc); - status = readl(ts7820_gpio->base + TS7820_IRQSTATUS) & - readl(ts7820_gpio->base + TS7820_IRQ_EN); - - for_each_set_bit(bit, &status, 32) { - girq = irq_find_mapping(ts7820_gpio->chip.irq.domain, bit); - generic_handle_irq(girq); - } - chained_irq_exit(irqchip, desc); -} - -static int ts7820_gpio_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct ts7820_gpio *ts7820_gpio; - struct gpio_irq_chip *girq; - - ts7820_gpio = devm_kzalloc(dev, sizeof(struct ts7820_gpio), GFP_KERNEL); - if (!ts7820_gpio) - return -ENOMEM; - - ts7820_gpio->irq = platform_get_irq(pdev, 0); - - ts7820_gpio->base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(ts7820_gpio->base)) - return PTR_ERR(ts7820_gpio->base); - - ts7820_gpio->dev = dev; - - raw_spin_lock_init(&ts7820_gpio->lock); - - ts7820_gpio->chip.label = dev_name(dev); - ts7820_gpio->chip.owner = THIS_MODULE; - ts7820_gpio->chip.direction_input = ts7820_gpio_direction_input; - ts7820_gpio->chip.direction_output = ts7820_gpio_direction_output; - ts7820_gpio->chip.get_direction = ts7820_gpio_direction_get; - ts7820_gpio->chip.set = ts7820_gpio_set; - ts7820_gpio->chip.set_multiple = ts7820_gpio_set_multiple; - ts7820_gpio->chip.get = ts7820_gpio_get; - ts7820_gpio->chip.base = -1; - ts7820_gpio->chip.ngpio = 32; - ts7820_gpio->chip.parent = dev; - - if (ts7820_gpio->irq >= 0) { - girq = &ts7820_gpio->chip.irq; - girq->chip = &ts7820_gpio->irqchip; - girq->chip->name = "ts7820-gpio"; - girq->chip->irq_mask = gpio_ts7820_irq_disable; - girq->chip->irq_unmask = gpio_ts7820_irq_enable; - girq->chip->irq_set_type = gpio_ts7820_irq_set_type; - girq->handler = handle_level_irq; - girq->parent_handler = gpio_ts7820_irq_handler; - girq->num_parents = 1; - girq->parents = devm_kcalloc(&pdev->dev, 1, - sizeof(*girq->parents), - GFP_KERNEL); - if (!girq->parents) - return -ENOMEM; - girq->parents[0] = ts7820_gpio->irq; - } - - return devm_gpiochip_add_data(dev, &ts7820_gpio->chip, ts7820_gpio); -} - -static const struct of_device_id ts7820_gpio_of_match[] = { - { .compatible = "technologic,ts7820-gpio", }, - {}, -}; -MODULE_DEVICE_TABLE(of, ts7820_gpio_of_match); - -static struct platform_driver ts7820_gpio_driver = { - .probe = ts7820_gpio_probe, - .driver = { - .name = "ts7820-gpio", - .of_match_table = ts7820_gpio_of_match, - .suppress_bind_attrs = true, - }, -}; -module_platform_driver(ts7820_gpio_driver); - -MODULE_AUTHOR("Mark Featherston "); -MODULE_DESCRIPTION("TS-7820 FPGA GPIO driver"); -MODULE_LICENSE("GPL v2"); From ca0f146fb71616e3d245bd379d27e35105e3faf7 Mon Sep 17 00:00:00 2001 From: Michael Peters Date: Fri, 17 Mar 2023 10:36:47 -0700 Subject: [PATCH 065/244] dts: armada-385-ts7800-v2: Initial commit Added support for the TS-7800-V2 platform --- arch/arm/boot/dts/marvell/Makefile | 1 + .../boot/dts/marvell/armada-385-ts7800-v2.dts | 500 ++++++++++++++++++ 2 files changed, 501 insertions(+) create mode 100644 arch/arm/boot/dts/marvell/armada-385-ts7800-v2.dts diff --git a/arch/arm/boot/dts/marvell/Makefile b/arch/arm/boot/dts/marvell/Makefile index 1e0f5ff492f78..639edfa934450 100644 --- a/arch/arm/boot/dts/marvell/Makefile +++ b/arch/arm/boot/dts/marvell/Makefile @@ -44,6 +44,7 @@ dtb-$(CONFIG_MACH_ARMADA_38X) += \ armada-385-linksys-rango.dtb \ armada-385-linksys-shelby.dtb \ armada-385-synology-ds116.dtb \ + armada-385-ts7800-v2.dtb \ armada-385-turris-omnia.dtb \ armada-388-clearfog.dtb \ armada-388-clearfog-base.dtb \ diff --git a/arch/arm/boot/dts/marvell/armada-385-ts7800-v2.dts b/arch/arm/boot/dts/marvell/armada-385-ts7800-v2.dts new file mode 100644 index 0000000000000..be4a7cba23ff7 --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-385-ts7800-v2.dts @@ -0,0 +1,500 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Device Tree file for embeddedTS TS-7800-V2 + * Copyright (C) 2017-2022 Technologic Systems, Inc. dba embeddedTS + */ + +/dts-v1/; +#include "armada-385.dtsi" + +#include +#include + +/ { + model = "embeddedTS TS-7800-V2"; + compatible = "embeddedts,a385-ts7800-v2", "marvell,armada385", "marvell,armada380"; + + aliases { + ethernet0 = ð0; + spi0 = &spi0; + + serial1 = &fpga_uart0; + serial2 = &fpga_uart1; + serial3 = &fpga_uart2; + serial4 = &fpga_uart3; + serial5 = &fpga_uart4; + serial6 = &fpga_uart5; + serial7 = &fpga_uart6; + serial8 = &fpga_uart7; + serial9 = &fpga_uart8; + serial10 = &fpga_uart9; + serial11 = &fpga_uart10; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x40000000>; /* 1GB */ + }; + + led-controller { + compatible = "gpio-leds"; + + led-0 { + color = ; + function = LED_FUNCTION_POWER; + gpios = <&ts7800v2_gpio 118 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + led-1 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&ts7800v2_gpio 119 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + mux: mux-controller { + compatible = "gpio-mux"; + #mux-control-cells = <0>; + + mux-gpios = <&ts7800v2_gpio 120 GPIO_ACTIVE_HIGH>; // FPGA_FLASH_SELECT + idle-state = <0>; + }; + + soc { + ranges = ; + }; + + tsfpga_pcie: tsfpga-pcie { + compatible = "technologic,ts78xx-mfd"; + + vendor = <0x1204>; + device = <0x0001>; + irqnum = <32>; + + #address-cells = <2>; + #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <1>; + + pc104; /* Configures PC104 header as the PC104 signals, not GPIO */ + + /* is set in the driver at runtime */ + + can@4c { + compatible = "technologic,sja1000"; + reg = <2 0x4C 4>; + interrupt-parent = <&tsfpga_pcie>; + interrupts = <27>; + reg-io-width = <4>; + nxp,tx-output-config = <0x06>; + nxp,external-clock-frequency = <16000000>; + }; + + fpgarng@2,44 { + compatible = "technologic,ts78xx-rng"; + reg = <2 0x44 4>; + }; + + tssdcore@2,100 { + compatible = "technologic,tssdcard"; + reg = <2 0x100 0x200>; + }; + + /* + * FPGA UARTS + * Intentionally out of order to align with physical locaions and names + * of the original TS-7800. + */ + fpga_uart0: fpga-uart10@2,d0 { + compatible = "ns16550a"; + reg = <2 0xd0 8>; + + interrupt-parent = <&tsfpga_pcie>; + interrupts = <26>; + + clock-frequency = <1843200>; + reg-io-width = <1>; + }; + + fpga_uart1: fpga-uart0@2,80 { + compatible = "ns16550a"; + reg = <2 0x80 8>; + + interrupt-parent = <&tsfpga_pcie>; + interrupts = <16>; + + clock-frequency = <1843200>; + reg-io-width = <1>; + }; + + fpga_uart2: fpga-uart1@2,88 { + compatible = "ns16550a"; + reg = <2 0x88 8>; + + interrupt-parent = <&tsfpga_pcie>; + interrupts = <17>; + + clock-frequency = <1843200>; + reg-io-width = <1>; + }; + + fpga_uart3: fpga-uart2@2,90 { + compatible = "ns16550a"; + reg = <2 0x90 8>; + + interrupt-parent = <&tsfpga_pcie>; + interrupts = <18>; + + clock-frequency = <1843200>; + reg-io-width = <1>; + }; + + fpga_uart4: fpga-uart3@2,98 { + compatible = "ns16550a"; + reg = <2 0x98 8>; + + interrupt-parent = <&tsfpga_pcie>; + interrupts = <19>; + + clock-frequency = <1843200>; + reg-io-width = <1>; + }; + + fpga_uart5: fpga-uart4@2,a0 { + compatible = "ns16550a"; + reg = <2 0xa0 8>; + + interrupt-parent = <&tsfpga_pcie>; + interrupts = <20>; + + clock-frequency = <1843200>; + reg-io-width = <1>; + }; + + fpga_uart6: fpga-uart5@2,a8 { + compatible = "ns16550a"; + reg = <2 0xa8 8>; + + interrupt-parent = <&tsfpga_pcie>; + interrupts = <21>; + + clock-frequency = <1843200>; + reg-io-width = <1>; + }; + + fpga_uart7: fpga-uart6@2,b0 { + compatible = "ns16550a"; + reg = <2 0xb0 8>; + + interrupt-parent = <&tsfpga_pcie>; + interrupts = <22>; + + clock-frequency = <1843200>; + reg-io-width = <1>; + }; + + fpga_uart8: fpga-uart7@2,b8 { + compatible = "ns16550a"; + reg = <2 0xb8 8>; + + interrupt-parent = <&tsfpga_pcie>; + interrupts = <23>; + + clock-frequency = <1843200>; + reg-io-width = <1>; + }; + + fpga_uart9: fpga-uart8@2,c0 { + compatible = "ns16550a"; + reg = <2 0xc0 8>; + + interrupt-parent = <&tsfpga_pcie>; + interrupts = <24>; + + clock-frequency = <1843200>; + reg-io-width = <1>; + }; + + fpga_uart10: fpga-uart9@2,c8 { + compatible = "ns16550a"; + reg = <2 0xc8 8>; + + interrupt-parent = <&tsfpga_pcie>; + interrupts = <25>; + + clock-frequency = <1843200>; + reg-io-width = <1>; + }; + + ts7800v2_gpio: ts7800v2-gpio { + compatible = "technologic,ts7800v2-gpio"; + gpio-controller; + #gpio-cells = <2>; + base = <64>; + ngpios = <118>; + #address-cells = <0x1>; + #size-cells = <0>; + reg = <2 0x0 0x60>; + + gpio-line-names = "DIO_1", "DIO_3", "DIO_04", "DIO_5", + "SPI_FRAME", "DIO_7", "DIO_8", "DIO_9", + "SPI_MISO", "DIO_11", "SPI_MOSI", "DIO_13", + "SPI_CLK", "DIO_15", "LCD_03", "LCD_04", + "LCD_05", "LCD_06", "LCD_07", "LCD_08", + "LCD_09", "LCD_10", "LCD_11", "LCD_12", + "LCD_13", "LCD_14", "ISA_A01", "ISA_DATA_07", + "ISA_DATA_06", "ISA_DATA_05", "ISA_DATA_04", + "ISA_DATA_03", "ISA_DATA_02", "ISA_DATA_01", + "ISA_DATA_00", "ISA_A10", "ISA_A11", "ISA_A12", + "ISA_A13", "ISA_A14", "ISA_A15", "ISA_A16", + "ISA_A17", "ISA_A18", "ISA_A19", "ISA_A20", + "ISA_A21", "ISA_A22", "ISA_A23", "ISA_A24", + "ISA_A25", "ISA_A26", "ISA_A27", "ISA_A28", + "ISA_A29", "ISA_A30", "", "ISA_RESET", + "ISA_B04", "ISA_B06", "", "ISA_B08", "ISA_B11", + "ISA_B12", "ISA_B13", "ISA_B14", "ISA_B15", + "ISA_B16", "ISA_B17", "ISA_B18", "ISA_B19", + "ISA_B20", "IRQ7", "IRQ6", "IRQ5", "ISA_B24", + "ISA_B25", "ISA_B26", "ISA_B27", "ISA_B28", + "ISA_B29", "ISA_B30", "ISA_B32", "ISA_C01", + "ISA_C02", "ISA_C03", "ISA_C04", "ISA_C05", + "ISA_C06", "ISA_C07", "ISA_C08", "ISA_C09", + "ISA_C10", "ISA_DATA_08", "ISA_DATA_09", + "ISA_DATA_10", "ISA_DATA_11", "ISA_DATA_12", + "ISA_DATA_13", "ISA_DATA_14", "ISA_DATA_15", + "ISA_D01", "ISA_D02", "IRQ10", "IRQ11", "IRQ12", + "IRQ15", "IRQ14", "ISA_D09", "ISA_D10", + "ISA_D11", "ISA_D12", "ISA_D13", "ISA_D14", + "ISA_D15", "ISA_D17", "EN_WIFI_PWR", + "WIFI_RESET", "GREEN_LED", "RED_LED", + "CPU_ACCESS_FPGA_FLASH#"; + }; + + isa_mem8: bus@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0 3 0 0x1000000>; + }; + + isa_mem16: bus@1000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0 3 0x1000000 0x1000000>; + }; + + isa_io8: bus@2000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0 3 0x2000000 0x1000000>; + }; + + isa_io16: bus@3000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0 3 0x3000000 0x1000000>; + }; + }; +}; + +&ahci0 { + status = "okay"; +}; + +&bm { + status = "okay"; +}; + +&bm_bppi { + status = "okay"; +}; + +/* magjack/sfp port 0 */ +ð0 { + pinctrl-names = "default"; + pinctrl-0 = <&ge0_rgmii_pins>; + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; + buffer-manager = <&bm>; + bm,pool-long = <0>; + bm,pool-short = <1>; +}; + +&gpio0 { + gpio-line-names = "", "", "", "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "CPU_IRQ", "", "", "", "", "", "", "", + "", "SPI_0_CS3#", "GE_PHY_INT#", "CPU_SPEED_1", "CPU_SPEED_2"; +}; + +&gpio1 { + gpio-line-names = "", "CPU_SPEED_0", "CPU_SPEED_3", "CPU_SPEED_4", + "CPU_TYPE_0", "", "", "", "", "", "EN_EMMC_PWR", "EN_FAN", + "CPU_TYPE_1", "EN_USB_HOST_5V", "FPGA_FLASH_SELECT", "", "", "", + "", "SPREAD_SPECTRUM#", "DETECT_MSATA", "DETECT_9478", "", "", + "", "", "", ""; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clock-frequency = <100000>; + status = "okay"; + + silabs_wdt: watchdog@54 { + compatible = "technologic,ts7100-wdt"; + reg = <0x54>; + enable-early; + }; + + m41t00s: rtc@68 { + compatible = "st,m41t00"; + reg = <0x68>; + }; + + mma8451: accelerometer@1c { + compatible = "fsl,mma8451"; + reg = <0x1c>; + }; +}; + +&mdio { + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; + + phy0: ethernet-phy@0 { + reg = <1>; + }; +}; + +&pciec { + status = "okay"; +}; + +/* Mini PCIe */ +&pcie2 { + status = "okay"; +}; + +/* FPGA */ +&pcie3 { + status = "okay"; +}; + +&pinctrl { + sdhci_pins0: sdhci-pins0 { + marvell,pins = "mpp50", "mpp54", "mpp55", + "mpp57", "mpp58", "mpp59"; + marvell,function = "sd0"; + }; + spi0_pins: spi-pins-0 { + marvell,pins = "mpp22", // SPI_0_MOSI + "mpp23", // SPI_0_CLK + "mpp24", // SPI_0_MISO + "mpp25", // SPI_0_BOOT_CS0#, native CS[0] + "mpp26", // CS1 n/c + "mpp27"; // SPI_0_WIFI_CS2#, native CS[3] + marvell,function = "spi0"; + }; + + spi0_cs_gpio_pins: spi0-cs-gpio-pins { + marvell,pins = "mpp18", // WIFI_IRQ# + "mpp28"; // SPI_0_CS3#, non-native CS[4] + marvell,function = "gpio"; + bias-pull-up; + }; +}; + +/* We use an external RTC rather than the CPU's built in RTC */ +&rtc { + status = "disabled"; +}; + +&sdhci { + bus-width = <4>; + no-1-8-v; + pinctrl-0 = <&sdhci_pins0>; + pinctrl-names = "default"; + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins &spi0_cs_gpio_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + num-cs = <5>; + cs-gpios = <0>, <0>, <0>, <0>, <&gpio0 28 GPIO_ACTIVE_LOW>; + + offboard_flash: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + + wilc: wifi@3 { + compatible = "microchip,wilc3000"; + reg = <3>; + spi-max-frequency = <20000000>; + reset-gpios = <&ts7800v2_gpio 117 GPIO_ACTIVE_HIGH>; /* WIFI_RESET# */ + chip_en-gpios = <&ts7800v2_gpio 116 GPIO_ACTIVE_HIGH>; /* EN_WIFI_PWR */ + interrupt-parent = <&gpio0>; + interrupts = <18 GPIO_ACTIVE_HIGH>; + }; + + spi@4 { /* Muxed between FPGA SPI master and this CPU's SPI */ + compatible = "spi-mux"; + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <1000000>; + mux-controls = <&mux>; + + onboard_flash: flash@1 { + compatible = "jedec,spi-nor"; + reg = <1>; + spi-max-frequency = <1000000>; + }; + }; +}; + +&uart0 { + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +/* We use external watchdog */ +&watchdog { + status = "disabled"; +}; + +&usb0 { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; From 6372cff35875d887a999278f62cad39e40e928e8 Mon Sep 17 00:00:00 2001 From: Michael Peters Date: Fri, 17 Mar 2023 10:42:43 -0700 Subject: [PATCH 066/244] dts: armada-385-ts7840: Initial commit Added support for the TS-7840 SBC. --- arch/arm/boot/dts/marvell/Makefile | 1 + .../boot/dts/marvell/armada-385-ts7840.dts | 732 ++++++++++++++++++ 2 files changed, 733 insertions(+) create mode 100644 arch/arm/boot/dts/marvell/armada-385-ts7840.dts diff --git a/arch/arm/boot/dts/marvell/Makefile b/arch/arm/boot/dts/marvell/Makefile index 639edfa934450..89056a535126c 100644 --- a/arch/arm/boot/dts/marvell/Makefile +++ b/arch/arm/boot/dts/marvell/Makefile @@ -45,6 +45,7 @@ dtb-$(CONFIG_MACH_ARMADA_38X) += \ armada-385-linksys-shelby.dtb \ armada-385-synology-ds116.dtb \ armada-385-ts7800-v2.dtb \ + armada-385-ts7840.dtb \ armada-385-turris-omnia.dtb \ armada-388-clearfog.dtb \ armada-388-clearfog-base.dtb \ diff --git a/arch/arm/boot/dts/marvell/armada-385-ts7840.dts b/arch/arm/boot/dts/marvell/armada-385-ts7840.dts new file mode 100644 index 0000000000000..5de34caf7cfa9 --- /dev/null +++ b/arch/arm/boot/dts/marvell/armada-385-ts7840.dts @@ -0,0 +1,732 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR X11) +/* + * Device Tree file for embeddedTS TS-7840 + * Copyright (C) 2017-2022 Technologic Systems, Inc. dba embeddedTS + */ +/dts-v1/; +#include "armada-385.dtsi" + +#include +#include +#include + +/ { + model = "embeddedTS TS-7840"; + compatible = "technologic,a385-ts7840", "marvell,armada385", "marvell,armada380"; + + aliases { + ethernet0 = ð0; + ethernet1 = ð1; + ethernet2 = ð2; + ethernet3 = &usbethernet; + + gpio2 = &fpga_bank0; + gpio3 = &fpga_bank1; + gpio4 = &fpga_bank2; + + spi0 = &spi0; + spi3 = &opencores_spi0; + spi4 = &opencores_spi1; + + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &sfp0_i2c; + i2c3 = &sfp1_i2c; + i2c4 = &poe_i2c; + i2c5 = &aux_i2c; + i2c6 = &mikro_i2c; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x80000000>; /* 2GB */ + }; + + sfp0_i2c: i2c@2 { + compatible = "i2c-gpio"; + gpios = <&fpga_bank1 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>, /* sda */ + <&fpga_bank1 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* scl */ + #address-cells = <1>; + #size-cells = <0>; + }; + + sfp1_i2c: i2c@3 { + compatible = "i2c-gpio"; + gpios = <&fpga_bank1 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>, /* sda */ + <&fpga_bank1 11 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* scl */ + #address-cells = <1>; + #size-cells = <0>; + }; + + poe_i2c: i2c@4 { + compatible = "i2c-gpio"; + gpios = <&fpga_bank1 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>, /* sda */ + <&fpga_bank1 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* scl */ + #address-cells = <1>; + #size-cells = <0>; + }; + + aux_i2c: i2c@5 { + compatible = "i2c-gpio"; + gpios = <&fpga_bank1 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>, /* sda */ + <&fpga_bank1 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* scl */ + #address-cells = <1>; + #size-cells = <0>; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + color = ; + function = LED_FUNCTION_POWER; + gpios = <&fpga_bank0 19 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + led-1 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&fpga_bank0 20 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-2 { + color = ; + function = LED_FUNCTION_INDICATOR; + gpios = <&fpga_bank0 21 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-3 { + color = ; + function = LED_FUNCTION_INDICATOR; + gpios = <&fpga_bank0 22 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-4 { + color = ; + function = LED_FUNCTION_INDICATOR; + gpios = <&fpga_bank0 23 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-5 { + color = ; + function = LED_FUNCTION_INDICATOR; + gpios = <&fpga_bank0 24 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-6 { + color = ; + function = LED_FUNCTION_INDICATOR; + gpios = <&fpga_bank0 25 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-7 { + color = ; + gpios = <&fpga_bank0 26 GPIO_ACTIVE_LOW>; + function = LED_FUNCTION_INDICATOR; + linux,default-trigger = "f1072004.mdio-mii:01:1Gbps"; + }; + + led-8 { + color = ; + gpios = <&fpga_bank2 20 GPIO_ACTIVE_LOW>; + function = LED_FUNCTION_INDICATOR; + linux,default-trigger = "f1072004.mdio-mii:00:1Gbps"; + }; + }; + + soc { + ranges = ; + }; + + tsfpga_pcie: fpga@2,0 { + compatible = "technologic,ts78xx-mfd"; + #address-cells = <2>; + #size-cells = <1>; + + vendor = <0x1e6d>; + device = <0x7840>; + + /* is set in the driver at runtime */ + + fpga_pll0c1: clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; + + fpga_rng: rng@a4 { + compatible = "technologic,ts7840-rng"; + reg = <0 0xa4 4>; + }; + + fpgairqc: irq-controller@b0 { + compatible = "technologic,ts7840-irqc"; + reg = <0 0xb0 4>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; + }; + + fpga_bank0: gpio@24 { + compatible = "technologic,ts7820-gpio"; + + interrupt-parent = <&fpgairqc>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; + + interrupt-controller; + #interrupt-cells = <2>; + + gpio-controller; + #gpio-cells = <2>; + reg = <0 0x24 0x1c>; + + gpio-line-names = "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "power_fail_3v_pad", + "detect_9478_pad", "", "magjack_1_led_padn", + "blu_led_padn", "right_grn_led_padn", + "right_red_led_padn", "middle_grn_led_padn", + "middle_yel_led_padn", "left_grn_led_padn", + "left_yel_led_padn", "bt_en_pad", "wifi_en_pad", + "prog_silab_clk_padn", "prog_silab_data_pad", + "cpu_push_sw_padn"; + }; + + fpga_bank1: gpio@40 { + compatible = "technologic,ts7820-gpio"; + + interrupt-parent = <&fpgairqc>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; + + interrupt-controller; + #interrupt-cells = <2>; + + gpio-controller; + #gpio-cells = <2>; + reg = <0 0x40 0x1c>; + + gpio-line-names = "DIG_IO_1", "DIG_IO_2", "DIG_IO_3", + "en_hs_sw_pad", "mikro_pwm_pad", + "dio_fault_3v_padn", "en_poe_padn", + "i2c_poe_clk_pad", "i2c_poe_dat", + "spi_0_fpga_cs3_pad", "cage1_sda_pad", + "cage1_scl_pad", "", "", "cage2_sda_pad", + "cage2_scl_pad", "en_nimbel_4v_pad", + "en_nimbel_3v3_pad", "en_emmc_3v3_pad", + "en_modem_5v_pad", "en_usb_5v_pad", + "disable_nim_usb_pad", "mini_pcie_reset_padn", + "ssd_present_padn", "en_xbee_usb_padn", + "aux_i2c_dat_pad", "aux_i2c_clk_pad", "", "", + "", "", ""; + }; + + fpga_bank2: ts7820-gpio@5c { + compatible = "technologic,ts7820-gpio"; + + interrupt-parent = <&fpgairqc>; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; + + interrupt-controller; + #interrupt-cells = <2>; + + gpio-controller; + #gpio-cells = <2>; + reg = <0 0x5c 0x1c>; + + gpio-line-names = "ird_network_rdy_pad", + "ird_modem_on_pad", "eth_100_act_padn", + "eth_100_speed_padn", "ssd_act_padn", + "mini_sr_latch_pad", "", "", "", "", + "mikro_int_pad", "mikro_reset_padn", + "mikro_an_3v_pad", "mikro_i2c_clk_pad", + "mikro_i2c_dat_pad", "alt_mikro_pwm_pad", + "mikro_an_pwm_pad", "comp_pad", "mikro_180_pad", + "en_mini_5v_pad", "magjack_0_led_padn", + "hd10_2_pad", "hd10_4_pad", "hd10_5_pad", + "hd10_6_pad", "hd10_8_pad", "jp1_padn", + "jp2_padn", "", "", "", ""; + }; + + /* COM1 RS-232 */ + fpga_uart0: uart@0,100 { + compatible = "ns16550a"; + reg = <0 0x100 8>; + interrupt-parent = <&fpgairqc>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <1843200>; + reg-io-width = <1>; + fifo-size = <64>; + }; + + /* COM2 RS-232 */ + fpga_uart1: uart@0,108 { + compatible = "ns16550a"; + reg = <0 0x108 8>; + interrupt-parent = <&fpgairqc>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <1843200>; + reg-io-width = <1>; + fifo-size = <64>; + }; + + /* GPS */ + fpga_uart2: uart@0,110 { + compatible = "ns16550a"; + reg = <0 0x110 8>; + interrupt-parent = <&fpgairqc>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <1843200>; + reg-io-width = <1>; + fifo-size = <64>; + }; + + /* Nimbelink */ + fpga_uart3: uart@0,118 { + compatible = "ns16550a"; + reg = <0 0x118 8>; + interrupt-parent = <&fpgairqc>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <1843200>; + reg-io-width = <1>; + fifo-size = <64>; + }; + + /* Iridium Modem */ + fpga_uart4: uart@0,120 { + compatible = "ns16550a"; + reg = <0 0x120 8>; + interrupt-parent = <&fpgairqc>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <1843200>; + reg-io-width = <1>; + fifo-size = <64>; + }; + + /* DSL Modem */ + fpga_uart5: uart@0,128 { + compatible = "ns16550a"; + reg = <0 0x128 8>; + interrupt-parent = <&fpgairqc>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <1843200>; + reg-io-width = <1>; + fifo-size = <64>; + }; + + /* Mikrobus UART */ + fpga_uart6: uart@0,130 { + compatible = "ns16550a"; + reg = <0 0x130 8>; + interrupt-parent = <&fpgairqc>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <1843200>; + reg-io-width = <1>; + fifo-size = <64>; + }; + + /* RS-485 port */ + fpga_uart7: uart@0,138 { + compatible = "ns16550a"; + reg = <0 0x138 8>; + interrupt-parent = <&fpgairqc>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <1843200>; + reg-io-width = <1>; + fifo-size = <64>; + }; + + /* XBEE */ + fpga_uart8: uart@0,140 { + compatible = "ns16550a"; + reg = <0 0x140 8>; + interrupt-parent = <&fpgairqc>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <1843200>; + reg-io-width = <1>; + fifo-size = <64>; + }; + + /* Spare */ + fpga_uart9: uart@0,148 { + compatible = "ns16550a"; + reg = <0 0x148 8>; + interrupt-parent = <&fpgairqc>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <1843200>; + reg-io-width = <1>; + fifo-size = <64>; + }; + + /* Spare */ + fpga_uart10: uart@0,150 { + compatible = "ns16550a"; + reg = <0 0x150 8>; + interrupt-parent = <&fpgairqc>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <1843200>; + reg-io-width = <1>; + fifo-size = <64>; + }; + + can@200 { + compatible = "nxp,sja1000"; + reg = <0 0x200 0x00000100>; + interrupt-parent = <&fpgairqc>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; + reg-io-width = <1>; + nxp,external-clock-frequency = <16000000>; + }; + + opencores_spi0: spi@400 { + compatible = "opencores,spi-oc"; + reg = <0 0x400 32>; + interrupt-parent = <&fpgairqc>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&fpga_pll0c1>; + clock-names ="spi-oc-clk"; + opencores-spi,idx = <0>; + opencores-spi,num-chipselects = <1>; + + #address-cells = <1>; + #size-cells = <0>; + + spifram: spi@0 { + compatible = "cypress,fm25l16b", "atmel,at25"; + reg = <0>; + spi-max-frequency = <19800000>; + size = <0x800>; + address-width = <16>; + pagesize = <64>; + }; + }; + + opencores_spi1: spi@420 { + compatible = "opencores,spi-oc"; + reg = <0 0x420 32>; + interrupt-parent = <&fpgairqc>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&fpga_pll0c1>; + clock-names ="spi-oc-clk"; + opencores-spi,idx = <0>; + opencores-spi,num-chipselects = <1>; + + #address-cells = <1>; + #size-cells = <0>; + + spidev@0 { + compatible = "spidev"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + mikro_i2c: i2c@500 { + compatible = "opencores,i2c-ocores"; + reg = <0 0x500 4>; + interrupt-parent = <&fpgairqc>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&fpga_pll0c1>; + clock-names = "i2c-oc-clk"; + }; + + mikro_pwm: pwm@600 { + compatible = "technologic,pwm"; + reg = <0 0x600 8>; + clocks = <&fpga_pll0c1>; + clock-names = "pwm-input-clk"; + }; + + ts_mmc: mmc@800 { + compatible = "ts,tssdcore2"; + reg = <0 0x800 32>; + //interrupt-parent = <&fpgairqc>; + //interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; + busy-gpios = <&fpga_bank0 15 GPIO_ACTIVE_HIGH>; + debug-gpios = <&fpga_bank1 12 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + mikro_adc0: adc@900 { + compatible = "technologic,ts-simple-adc"; + reg = <0 0x900 4>; + interrupt-parent = <&fpgairqc>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + sfp0: sfp@0 { + compatible = "sff,sfp"; + i2c-bus = <&sfp0_i2c>; + }; + + sfp1: sfp@1 { + compatible = "sff,sfp"; + i2c-bus = <&sfp1_i2c>; + }; +}; + +&ahci0 { + status = "okay"; +}; + +&bm { + status = "okay"; +}; + +&bm_bppi { + status = "okay"; +}; + +/* magjack/sfp port 0 */ +ð0 { + pinctrl-names = "default"; + pinctrl-0 = <&ge0_rgmii_pins>; + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; + buffer-manager = <&bm>; + /*sfp = <&sfp0>;*/ + bm,pool-long = <0>; + bm,pool-short = <1>; +}; + +/* magjack/sfgp port 1 */ +ð1 { + pinctrl-names = "default"; + pinctrl-0 = <&ge1_rgmii_pins>; + status = "okay"; + phy = <&phy1>; + phy-mode = "rgmii-id"; + /*sfp = <&sfp1>;*/ + bm,pool-long = <2>; + bm,pool-short = <1>; + buffer-manager = <&bm>; +}; + +/* sgmii port to eth switch */ +ð2 { + status = "okay"; + phy-mode = "sgmii"; + bm,pool-long = <3>; + bm,pool-short = <1>; + buffer-manager = <&bm>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gpio0 { + gpio-line-names = "", "", "I2C_0_CLK", "I2C_0_DAT", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "WIFI_IRQ_N", "FPGA_RESET", + "", "", "", "", "", "", "", "", "", "", "", ""; +}; + +&gpio1 { + gpio-line-names = "", "CPU_SPEED_0", "CPU_SPEED_3", "CPU_SPEED_4", + "CPU_TYPE_0", "", "", "", "", "", "GPS_PPS", "ETH_SW_INT#", + "CPU_TYPE_1", "", "", "", "", "FPGA_FLASH_SELECT", "EMMC_CMD", + "SPREAD_SPECTRUM#", "", "DETECT_9478", "", "", "", "", "", "", + "", "", "", ""; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clock-frequency = <100000>; + status = "okay"; + + silabs_wdt: watchdog@54 { + compatible = "technologic,ts7100-wdt"; + reg = <0x54>; + enable-early; + }; + + m41t00s: rtc@68 { + compatible = "st,m41t00"; + reg = <0x68>; + }; +}; + +&mdio { + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; + + phy0: ethernet-phy@0 { + reg = <0>; + /* Configure LED[0] to blink for activity */ + marvell,reg-init = <3 16 0 0x1aa4>; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + /* Configure LED[0] to blink for activity */ + marvell,reg-init = <3 16 0 0x1aa4>; + }; + + switch@2 { + compatible = "marvell,mv88e6085"; + + pinctrl-names = "default"; + pinctrl-0 = <&switch_pins0>; + + #address-cells = <1>; + #size-cells = <0>; + dsa,member = <0 0>; + reg = <2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + ports@0 { + reg = <0>; + label = "lan0"; + }; + + ports@1 { + reg = <1>; + label = "lan1"; + }; + + ports@2 { + reg = <2>; + label = "lan2"; + }; + + ports@3 { + reg = <3>; + label = "lan3"; + }; + + ports@4 { + reg = <4>; + label = "lan4"; + }; + + port@5 { + reg = <5>; + label = "cpu"; + ethernet = <ð2>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; +}; + +&pciec { + status = "okay"; +}; + +/* Mini PCIe */ +&pcie2 { + status = "okay"; +}; + +/* FPGA */ +&pcie3 { + status = "okay"; +}; + +&pinctrl { + sdhci_pins0: sdhci-pins0 { + marvell,pins = "mpp50", "mpp54", "mpp55", + "mpp57", "mpp58", "mpp59"; + marvell,function = "sd0"; + }; + + switch_pins0: switch-pins0 { + marvell,pins = "mpp43"; + marvell,function = "gpio"; + }; +}; + +/* We do not use the CPU's built in RTC */ +&rtc { + status = "disabled"; +}; + +&sdhci { + bus-width = <4>; + no-1-8-v; + pinctrl-0 = <&sdhci_pins0>; + pinctrl-names = "default"; + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + status = "okay"; + num-cs = <3>; + cs-gpios = <0>, <&fpga_bank1 9 GPIO_ACTIVE_LOW>; + + offboardspi1: offboardspi@0 { + compatible = "spidev"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + + onboard_flash: flash@1 { + compatible = "jedec,spi-nor"; + reg = <1>; + spi-max-frequency = <20000000>; + }; +}; + +&uart0 { + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; + status = "okay"; + u-boot,dm-pre-reloc; +}; + +/* We use an external watchdog */ +&watchdog { + status = "disabled"; +}; + +&usb0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + usb1@1 { + compatible = "usb424,9514"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + usbethernet: usbether@1 { + compatible = "usb424,ec00"; + reg = <1>; + }; + }; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; From 6d4e12da422440ab706abf94f34362c823c3d13e Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Wed, 17 Sep 2025 21:01:25 +0000 Subject: [PATCH 067/244] Revert "dts: armada-385-ts7840: Initial commit" This reverts commit 4b3085132143aeee70bcee625b716a040514ab8d. --- arch/arm/boot/dts/marvell/Makefile | 1 - .../boot/dts/marvell/armada-385-ts7840.dts | 732 ------------------ 2 files changed, 733 deletions(-) delete mode 100644 arch/arm/boot/dts/marvell/armada-385-ts7840.dts diff --git a/arch/arm/boot/dts/marvell/Makefile b/arch/arm/boot/dts/marvell/Makefile index 89056a535126c..639edfa934450 100644 --- a/arch/arm/boot/dts/marvell/Makefile +++ b/arch/arm/boot/dts/marvell/Makefile @@ -45,7 +45,6 @@ dtb-$(CONFIG_MACH_ARMADA_38X) += \ armada-385-linksys-shelby.dtb \ armada-385-synology-ds116.dtb \ armada-385-ts7800-v2.dtb \ - armada-385-ts7840.dtb \ armada-385-turris-omnia.dtb \ armada-388-clearfog.dtb \ armada-388-clearfog-base.dtb \ diff --git a/arch/arm/boot/dts/marvell/armada-385-ts7840.dts b/arch/arm/boot/dts/marvell/armada-385-ts7840.dts deleted file mode 100644 index 5de34caf7cfa9..0000000000000 --- a/arch/arm/boot/dts/marvell/armada-385-ts7840.dts +++ /dev/null @@ -1,732 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR X11) -/* - * Device Tree file for embeddedTS TS-7840 - * Copyright (C) 2017-2022 Technologic Systems, Inc. dba embeddedTS - */ -/dts-v1/; -#include "armada-385.dtsi" - -#include -#include -#include - -/ { - model = "embeddedTS TS-7840"; - compatible = "technologic,a385-ts7840", "marvell,armada385", "marvell,armada380"; - - aliases { - ethernet0 = ð0; - ethernet1 = ð1; - ethernet2 = ð2; - ethernet3 = &usbethernet; - - gpio2 = &fpga_bank0; - gpio3 = &fpga_bank1; - gpio4 = &fpga_bank2; - - spi0 = &spi0; - spi3 = &opencores_spi0; - spi4 = &opencores_spi1; - - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &sfp0_i2c; - i2c3 = &sfp1_i2c; - i2c4 = &poe_i2c; - i2c5 = &aux_i2c; - i2c6 = &mikro_i2c; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x80000000>; /* 2GB */ - }; - - sfp0_i2c: i2c@2 { - compatible = "i2c-gpio"; - gpios = <&fpga_bank1 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>, /* sda */ - <&fpga_bank1 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* scl */ - #address-cells = <1>; - #size-cells = <0>; - }; - - sfp1_i2c: i2c@3 { - compatible = "i2c-gpio"; - gpios = <&fpga_bank1 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>, /* sda */ - <&fpga_bank1 11 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* scl */ - #address-cells = <1>; - #size-cells = <0>; - }; - - poe_i2c: i2c@4 { - compatible = "i2c-gpio"; - gpios = <&fpga_bank1 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>, /* sda */ - <&fpga_bank1 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* scl */ - #address-cells = <1>; - #size-cells = <0>; - }; - - aux_i2c: i2c@5 { - compatible = "i2c-gpio"; - gpios = <&fpga_bank1 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>, /* sda */ - <&fpga_bank1 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* scl */ - #address-cells = <1>; - #size-cells = <0>; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - color = ; - function = LED_FUNCTION_POWER; - gpios = <&fpga_bank0 19 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - - led-1 { - color = ; - function = LED_FUNCTION_STATUS; - gpios = <&fpga_bank0 20 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-2 { - color = ; - function = LED_FUNCTION_INDICATOR; - gpios = <&fpga_bank0 21 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-3 { - color = ; - function = LED_FUNCTION_INDICATOR; - gpios = <&fpga_bank0 22 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-4 { - color = ; - function = LED_FUNCTION_INDICATOR; - gpios = <&fpga_bank0 23 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-5 { - color = ; - function = LED_FUNCTION_INDICATOR; - gpios = <&fpga_bank0 24 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-6 { - color = ; - function = LED_FUNCTION_INDICATOR; - gpios = <&fpga_bank0 25 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-7 { - color = ; - gpios = <&fpga_bank0 26 GPIO_ACTIVE_LOW>; - function = LED_FUNCTION_INDICATOR; - linux,default-trigger = "f1072004.mdio-mii:01:1Gbps"; - }; - - led-8 { - color = ; - gpios = <&fpga_bank2 20 GPIO_ACTIVE_LOW>; - function = LED_FUNCTION_INDICATOR; - linux,default-trigger = "f1072004.mdio-mii:00:1Gbps"; - }; - }; - - soc { - ranges = ; - }; - - tsfpga_pcie: fpga@2,0 { - compatible = "technologic,ts78xx-mfd"; - #address-cells = <2>; - #size-cells = <1>; - - vendor = <0x1e6d>; - device = <0x7840>; - - /* is set in the driver at runtime */ - - fpga_pll0c1: clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <50000000>; - }; - - fpga_rng: rng@a4 { - compatible = "technologic,ts7840-rng"; - reg = <0 0xa4 4>; - }; - - fpgairqc: irq-controller@b0 { - compatible = "technologic,ts7840-irqc"; - reg = <0 0xb0 4>; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&gpio1>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; - }; - - fpga_bank0: gpio@24 { - compatible = "technologic,ts7820-gpio"; - - interrupt-parent = <&fpgairqc>; - interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; - - interrupt-controller; - #interrupt-cells = <2>; - - gpio-controller; - #gpio-cells = <2>; - reg = <0 0x24 0x1c>; - - gpio-line-names = "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "power_fail_3v_pad", - "detect_9478_pad", "", "magjack_1_led_padn", - "blu_led_padn", "right_grn_led_padn", - "right_red_led_padn", "middle_grn_led_padn", - "middle_yel_led_padn", "left_grn_led_padn", - "left_yel_led_padn", "bt_en_pad", "wifi_en_pad", - "prog_silab_clk_padn", "prog_silab_data_pad", - "cpu_push_sw_padn"; - }; - - fpga_bank1: gpio@40 { - compatible = "technologic,ts7820-gpio"; - - interrupt-parent = <&fpgairqc>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; - - interrupt-controller; - #interrupt-cells = <2>; - - gpio-controller; - #gpio-cells = <2>; - reg = <0 0x40 0x1c>; - - gpio-line-names = "DIG_IO_1", "DIG_IO_2", "DIG_IO_3", - "en_hs_sw_pad", "mikro_pwm_pad", - "dio_fault_3v_padn", "en_poe_padn", - "i2c_poe_clk_pad", "i2c_poe_dat", - "spi_0_fpga_cs3_pad", "cage1_sda_pad", - "cage1_scl_pad", "", "", "cage2_sda_pad", - "cage2_scl_pad", "en_nimbel_4v_pad", - "en_nimbel_3v3_pad", "en_emmc_3v3_pad", - "en_modem_5v_pad", "en_usb_5v_pad", - "disable_nim_usb_pad", "mini_pcie_reset_padn", - "ssd_present_padn", "en_xbee_usb_padn", - "aux_i2c_dat_pad", "aux_i2c_clk_pad", "", "", - "", "", ""; - }; - - fpga_bank2: ts7820-gpio@5c { - compatible = "technologic,ts7820-gpio"; - - interrupt-parent = <&fpgairqc>; - interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; - - interrupt-controller; - #interrupt-cells = <2>; - - gpio-controller; - #gpio-cells = <2>; - reg = <0 0x5c 0x1c>; - - gpio-line-names = "ird_network_rdy_pad", - "ird_modem_on_pad", "eth_100_act_padn", - "eth_100_speed_padn", "ssd_act_padn", - "mini_sr_latch_pad", "", "", "", "", - "mikro_int_pad", "mikro_reset_padn", - "mikro_an_3v_pad", "mikro_i2c_clk_pad", - "mikro_i2c_dat_pad", "alt_mikro_pwm_pad", - "mikro_an_pwm_pad", "comp_pad", "mikro_180_pad", - "en_mini_5v_pad", "magjack_0_led_padn", - "hd10_2_pad", "hd10_4_pad", "hd10_5_pad", - "hd10_6_pad", "hd10_8_pad", "jp1_padn", - "jp2_padn", "", "", "", ""; - }; - - /* COM1 RS-232 */ - fpga_uart0: uart@0,100 { - compatible = "ns16550a"; - reg = <0 0x100 8>; - interrupt-parent = <&fpgairqc>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <1843200>; - reg-io-width = <1>; - fifo-size = <64>; - }; - - /* COM2 RS-232 */ - fpga_uart1: uart@0,108 { - compatible = "ns16550a"; - reg = <0 0x108 8>; - interrupt-parent = <&fpgairqc>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <1843200>; - reg-io-width = <1>; - fifo-size = <64>; - }; - - /* GPS */ - fpga_uart2: uart@0,110 { - compatible = "ns16550a"; - reg = <0 0x110 8>; - interrupt-parent = <&fpgairqc>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <1843200>; - reg-io-width = <1>; - fifo-size = <64>; - }; - - /* Nimbelink */ - fpga_uart3: uart@0,118 { - compatible = "ns16550a"; - reg = <0 0x118 8>; - interrupt-parent = <&fpgairqc>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <1843200>; - reg-io-width = <1>; - fifo-size = <64>; - }; - - /* Iridium Modem */ - fpga_uart4: uart@0,120 { - compatible = "ns16550a"; - reg = <0 0x120 8>; - interrupt-parent = <&fpgairqc>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <1843200>; - reg-io-width = <1>; - fifo-size = <64>; - }; - - /* DSL Modem */ - fpga_uart5: uart@0,128 { - compatible = "ns16550a"; - reg = <0 0x128 8>; - interrupt-parent = <&fpgairqc>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <1843200>; - reg-io-width = <1>; - fifo-size = <64>; - }; - - /* Mikrobus UART */ - fpga_uart6: uart@0,130 { - compatible = "ns16550a"; - reg = <0 0x130 8>; - interrupt-parent = <&fpgairqc>; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <1843200>; - reg-io-width = <1>; - fifo-size = <64>; - }; - - /* RS-485 port */ - fpga_uart7: uart@0,138 { - compatible = "ns16550a"; - reg = <0 0x138 8>; - interrupt-parent = <&fpgairqc>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <1843200>; - reg-io-width = <1>; - fifo-size = <64>; - }; - - /* XBEE */ - fpga_uart8: uart@0,140 { - compatible = "ns16550a"; - reg = <0 0x140 8>; - interrupt-parent = <&fpgairqc>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <1843200>; - reg-io-width = <1>; - fifo-size = <64>; - }; - - /* Spare */ - fpga_uart9: uart@0,148 { - compatible = "ns16550a"; - reg = <0 0x148 8>; - interrupt-parent = <&fpgairqc>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <1843200>; - reg-io-width = <1>; - fifo-size = <64>; - }; - - /* Spare */ - fpga_uart10: uart@0,150 { - compatible = "ns16550a"; - reg = <0 0x150 8>; - interrupt-parent = <&fpgairqc>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <1843200>; - reg-io-width = <1>; - fifo-size = <64>; - }; - - can@200 { - compatible = "nxp,sja1000"; - reg = <0 0x200 0x00000100>; - interrupt-parent = <&fpgairqc>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; - reg-io-width = <1>; - nxp,external-clock-frequency = <16000000>; - }; - - opencores_spi0: spi@400 { - compatible = "opencores,spi-oc"; - reg = <0 0x400 32>; - interrupt-parent = <&fpgairqc>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&fpga_pll0c1>; - clock-names ="spi-oc-clk"; - opencores-spi,idx = <0>; - opencores-spi,num-chipselects = <1>; - - #address-cells = <1>; - #size-cells = <0>; - - spifram: spi@0 { - compatible = "cypress,fm25l16b", "atmel,at25"; - reg = <0>; - spi-max-frequency = <19800000>; - size = <0x800>; - address-width = <16>; - pagesize = <64>; - }; - }; - - opencores_spi1: spi@420 { - compatible = "opencores,spi-oc"; - reg = <0 0x420 32>; - interrupt-parent = <&fpgairqc>; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&fpga_pll0c1>; - clock-names ="spi-oc-clk"; - opencores-spi,idx = <0>; - opencores-spi,num-chipselects = <1>; - - #address-cells = <1>; - #size-cells = <0>; - - spidev@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - mikro_i2c: i2c@500 { - compatible = "opencores,i2c-ocores"; - reg = <0 0x500 4>; - interrupt-parent = <&fpgairqc>; - interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&fpga_pll0c1>; - clock-names = "i2c-oc-clk"; - }; - - mikro_pwm: pwm@600 { - compatible = "technologic,pwm"; - reg = <0 0x600 8>; - clocks = <&fpga_pll0c1>; - clock-names = "pwm-input-clk"; - }; - - ts_mmc: mmc@800 { - compatible = "ts,tssdcore2"; - reg = <0 0x800 32>; - //interrupt-parent = <&fpgairqc>; - //interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; - busy-gpios = <&fpga_bank0 15 GPIO_ACTIVE_HIGH>; - debug-gpios = <&fpga_bank1 12 GPIO_ACTIVE_HIGH>; - status = "disabled"; - }; - - mikro_adc0: adc@900 { - compatible = "technologic,ts-simple-adc"; - reg = <0 0x900 4>; - interrupt-parent = <&fpgairqc>; - interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - sfp0: sfp@0 { - compatible = "sff,sfp"; - i2c-bus = <&sfp0_i2c>; - }; - - sfp1: sfp@1 { - compatible = "sff,sfp"; - i2c-bus = <&sfp1_i2c>; - }; -}; - -&ahci0 { - status = "okay"; -}; - -&bm { - status = "okay"; -}; - -&bm_bppi { - status = "okay"; -}; - -/* magjack/sfp port 0 */ -ð0 { - pinctrl-names = "default"; - pinctrl-0 = <&ge0_rgmii_pins>; - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - buffer-manager = <&bm>; - /*sfp = <&sfp0>;*/ - bm,pool-long = <0>; - bm,pool-short = <1>; -}; - -/* magjack/sfgp port 1 */ -ð1 { - pinctrl-names = "default"; - pinctrl-0 = <&ge1_rgmii_pins>; - status = "okay"; - phy = <&phy1>; - phy-mode = "rgmii-id"; - /*sfp = <&sfp1>;*/ - bm,pool-long = <2>; - bm,pool-short = <1>; - buffer-manager = <&bm>; -}; - -/* sgmii port to eth switch */ -ð2 { - status = "okay"; - phy-mode = "sgmii"; - bm,pool-long = <3>; - bm,pool-short = <1>; - buffer-manager = <&bm>; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gpio0 { - gpio-line-names = "", "", "I2C_0_CLK", "I2C_0_DAT", "", "", "", "", "", - "", "", "", "", "", "", "", "", "", "WIFI_IRQ_N", "FPGA_RESET", - "", "", "", "", "", "", "", "", "", "", "", ""; -}; - -&gpio1 { - gpio-line-names = "", "CPU_SPEED_0", "CPU_SPEED_3", "CPU_SPEED_4", - "CPU_TYPE_0", "", "", "", "", "", "GPS_PPS", "ETH_SW_INT#", - "CPU_TYPE_1", "", "", "", "", "FPGA_FLASH_SELECT", "EMMC_CMD", - "SPREAD_SPECTRUM#", "", "DETECT_9478", "", "", "", "", "", "", - "", "", "", ""; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - clock-frequency = <100000>; - status = "okay"; - - silabs_wdt: watchdog@54 { - compatible = "technologic,ts7100-wdt"; - reg = <0x54>; - enable-early; - }; - - m41t00s: rtc@68 { - compatible = "st,m41t00"; - reg = <0x68>; - }; -}; - -&mdio { - pinctrl-names = "default"; - pinctrl-0 = <&mdio_pins>; - - phy0: ethernet-phy@0 { - reg = <0>; - /* Configure LED[0] to blink for activity */ - marvell,reg-init = <3 16 0 0x1aa4>; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - /* Configure LED[0] to blink for activity */ - marvell,reg-init = <3 16 0 0x1aa4>; - }; - - switch@2 { - compatible = "marvell,mv88e6085"; - - pinctrl-names = "default"; - pinctrl-0 = <&switch_pins0>; - - #address-cells = <1>; - #size-cells = <0>; - dsa,member = <0 0>; - reg = <2>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - ports@0 { - reg = <0>; - label = "lan0"; - }; - - ports@1 { - reg = <1>; - label = "lan1"; - }; - - ports@2 { - reg = <2>; - label = "lan2"; - }; - - ports@3 { - reg = <3>; - label = "lan3"; - }; - - ports@4 { - reg = <4>; - label = "lan4"; - }; - - port@5 { - reg = <5>; - label = "cpu"; - ethernet = <ð2>; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; -}; - -&pciec { - status = "okay"; -}; - -/* Mini PCIe */ -&pcie2 { - status = "okay"; -}; - -/* FPGA */ -&pcie3 { - status = "okay"; -}; - -&pinctrl { - sdhci_pins0: sdhci-pins0 { - marvell,pins = "mpp50", "mpp54", "mpp55", - "mpp57", "mpp58", "mpp59"; - marvell,function = "sd0"; - }; - - switch_pins0: switch-pins0 { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; -}; - -/* We do not use the CPU's built in RTC */ -&rtc { - status = "disabled"; -}; - -&sdhci { - bus-width = <4>; - no-1-8-v; - pinctrl-0 = <&sdhci_pins0>; - pinctrl-names = "default"; - status = "okay"; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>; - status = "okay"; - num-cs = <3>; - cs-gpios = <0>, <&fpga_bank1 9 GPIO_ACTIVE_LOW>; - - offboardspi1: offboardspi@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - - onboard_flash: flash@1 { - compatible = "jedec,spi-nor"; - reg = <1>; - spi-max-frequency = <20000000>; - }; -}; - -&uart0 { - pinctrl-0 = <&uart0_pins>; - pinctrl-names = "default"; - status = "okay"; - u-boot,dm-pre-reloc; -}; - -/* We use an external watchdog */ -&watchdog { - status = "disabled"; -}; - -&usb0 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - usb1@1 { - compatible = "usb424,9514"; - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - usbethernet: usbether@1 { - compatible = "usb424,ec00"; - reg = <1>; - }; - }; -}; - -&usb3_0 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; From 50417b2128b902e82ce0f6c75552f85c3eb68129 Mon Sep 17 00:00:00 2001 From: Michael Peters Date: Fri, 17 Mar 2023 11:36:33 -0700 Subject: [PATCH 068/244] char: hw_random: ts78xx-rng: Initial commit Added support for the FPGA RNG present in the TS-78XX family SBC. --- drivers/char/hw_random/Kconfig | 8 +++ drivers/char/hw_random/Makefile | 1 + drivers/char/hw_random/ts78xx-rng.c | 76 +++++++++++++++++++++++++++++ 3 files changed, 85 insertions(+) create mode 100644 drivers/char/hw_random/ts78xx-rng.c diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig index 492a2a61a65be..cd4a32ece8dfd 100644 --- a/drivers/char/hw_random/Kconfig +++ b/drivers/char/hw_random/Kconfig @@ -244,6 +244,14 @@ config HW_RANDOM_PASEMI If unsure, say Y. +config HW_RANDOM_TS78XX + tristate "TS-78XX FPGA based RNG" + depends on HAS_IOMEM + help + This driver provides kernel support for the FPGA based RNG + device contained in embeddedTS' TS-78XX platforms. The generator + returns a random 32-bit value based on metastability. + config HW_RANDOM_VIRTIO tristate "VirtIO Random Number Generator support" depends on VIRTIO diff --git a/drivers/char/hw_random/Makefile b/drivers/char/hw_random/Makefile index b9132b3f5d210..6d8129c0af716 100644 --- a/drivers/char/hw_random/Makefile +++ b/drivers/char/hw_random/Makefile @@ -52,3 +52,4 @@ obj-$(CONFIG_HW_RANDOM_CN10K) += cn10k-rng.o obj-$(CONFIG_HW_RANDOM_POLARFIRE_SOC) += mpfs-rng.o obj-$(CONFIG_HW_RANDOM_ROCKCHIP) += rockchip-rng.o obj-$(CONFIG_HW_RANDOM_JH7110) += jh7110-trng.o +obj-$(CONFIG_HW_RANDOM_TS78XX) += ts78xx-rng.o diff --git a/drivers/char/hw_random/ts78xx-rng.c b/drivers/char/hw_random/ts78xx-rng.c new file mode 100644 index 0000000000000..606a7d5696639 --- /dev/null +++ b/drivers/char/hw_random/ts78xx-rng.c @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* + * Driver for TS-78XX's FPGA based RNG. This outputs random data + * based on a core that outputs continuous data based on metastability + */ + +#include +#include +#include +#include +#include +#include +#include + +struct ts78xx_rng_priv { + struct hwrng rng; + void __iomem *base; +}; + +static int ts78xx_rng_data_read(struct hwrng *rng, u32 *buffer) +{ + struct ts78xx_rng_priv *priv = (struct ts78xx_rng_priv *)rng->priv; + *buffer = readl(priv->base); + return 4; +} + +static int ts78xx_rng_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + const char *name = dev_name(dev); + struct ts78xx_rng_priv *priv; + struct hwrng *rng; + + priv = devm_kzalloc(dev, sizeof(struct ts78xx_rng_priv), + GFP_KERNEL); + if (!priv) + return -ENOMEM; + + rng = &priv->rng; + + platform_set_drvdata(pdev, priv); + + priv->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) { + dev_err(dev, "failed to remap I/O memory\n"); + return PTR_ERR(priv->base); + } + + rng->name = name; + rng->data_read = ts78xx_rng_data_read; + rng->priv = (unsigned long)priv; + rng->quality = 1000; + + return hwrng_register(rng); +} + +static const struct of_device_id ts78xx_rng_of_match[] = { + { .compatible = "technologic,ts78xx-rng", }, + { .compatible = "technologic,ts7840-rng", }, /* Backwards compatibility */ + {}, +}; +MODULE_DEVICE_TABLE(of, ts78xx_rng_of_match); + +static struct platform_driver ts78xx_rng_driver = { + .probe = ts78xx_rng_probe, + .driver = { + .name = "ts78xx-rng", + .of_match_table = ts78xx_rng_of_match, + }, +}; +module_platform_driver(ts78xx_rng_driver); + +MODULE_AUTHOR("Mark Featherston "); +MODULE_DESCRIPTION("TS-78xx RNG driver"); +MODULE_LICENSE("GPL v2"); From 128d1ee6273deb2ae1c6d88ba8508bf1db9ac750 Mon Sep 17 00:00:00 2001 From: Michael Peters Date: Fri, 17 Mar 2023 11:44:08 -0700 Subject: [PATCH 069/244] watchdog: ts7100_wdt: Initial commit Add support for TS-7100 style FPGA-based watchdog. --- drivers/watchdog/Kconfig | 8 ++ drivers/watchdog/Makefile | 1 + drivers/watchdog/ts7100_wdt.c | 246 ++++++++++++++++++++++++++++++++++ 3 files changed, 255 insertions(+) create mode 100644 drivers/watchdog/ts7100_wdt.c diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 431ca364d9eb9..1e235247df1c8 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -750,6 +750,14 @@ config TS4800_WATCHDOG an external FPGA. Say Y here if you want to support for the watchdog timer on TS-4800 board. +config TS7100_WATCHDOG + tristate "TS-7100 (and compatible) Microcontroller Watchdog" + depends on ARM + select WATCHDOG_CORE + help + Hardware driver for embeddedTS' TS-7100 and compatible + microcontroller watchdog. + config TS72XX_WATCHDOG tristate "TS-72XX SBC Watchdog" depends on MACH_TS72XX || COMPILE_TEST diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 7affedf4c43c4..1d823715e331a 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -65,6 +65,7 @@ obj-$(CONFIG_RN5T618_WATCHDOG) += rn5t618_wdt.o obj-$(CONFIG_NPCM7XX_WATCHDOG) += npcm_wdt.o obj-$(CONFIG_STMP3XXX_RTC_WATCHDOG) += stmp3xxx_rtc_wdt.o obj-$(CONFIG_TS_WDT_MICRO) += ts_wdt.o +obj-$(CONFIG_TS7100_WATCHDOG) += ts7100_wdt.o obj-$(CONFIG_TS4800_WATCHDOG) += ts4800_wdt.o obj-$(CONFIG_TS72XX_WATCHDOG) += ts72xx_wdt.o obj-$(CONFIG_IMX2_WDT) += imx2_wdt.o diff --git a/drivers/watchdog/ts7100_wdt.c b/drivers/watchdog/ts7100_wdt.c new file mode 100644 index 0000000000000..87764c6a7c278 --- /dev/null +++ b/drivers/watchdog/ts7100_wdt.c @@ -0,0 +1,246 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define TS_DEFAULT_TIMEOUT 30 + +static int wdt_timeout; +module_param(wdt_timeout, int, 0); +MODULE_PARM_DESC(wdt_timeout, "Watchdog timeout in seconds"); + +static bool nowayout = WATCHDOG_NOWAYOUT; +module_param(nowayout, bool, 0); +MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started default=" + __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); + +/* This driver supports the embeddedTS 2nd generation WDT in + * microcontroller. + * + * The 2nd gen WDT is still in I2C microcontroller, but follows more "standard" + * WDT layouts. There are separate registers for the timeout, and a single + * register bit for a feed. Additionally, this 2nd gen microcontroller setup + * uses a register mapped address space, similar to a generic I2C EEPROM. + */ + +/* The relevant WDT registers are: + * + * Timeout in centiseconds: + * 0x400: LSB + * 0x401: + * 0x402: + * 0x403: MSB + * + * Control: + * 0x404: + * 7 - Set if last reboot was caused by WDT (RO) + * 6:2 - Reserved + * 1:0 - + * Set to 0x1 to cause a feed of + * Set to 0x2 to sleep for + * + * + * Writing a value of 0 to the Timeout registers and issuing a feed will disable + * the WDT completely. + */ + +#define WDT_TIMEOUT 0x400 +#define WDT_CTRL 0x404 +#define WDT_FEED_CMD 0x01 +#define WDT_SLEEP_CMD 0x02 + +static int ts7100_wdt_write(struct i2c_client *client, u16 reg, u8 *data, + int len) +{ + struct i2c_msg msg; + u8 data_buf[6]; + int ret; + + BUG_ON(len > 4); + + /* MSB of reg is written on the bus first */ + data_buf[0] = ((reg >> 8) & 0xFF); + data_buf[1] = (reg & 0xFF); + memcpy(&data_buf[2], data, len); + + /* Write 16-bit register address */ + msg.addr = client->addr; + msg.flags = 0; + msg.len = len+2; + msg.buf = data_buf; + + dev_dbg(&client->dev, "Writing %d byte(s) to 0x%02X%02X\n", + len, data_buf[0], data_buf[1]); + + ret = i2c_transfer(client->adapter, &msg, 1); + + if (ret != 1) { + dev_err(&client->dev, "%s: write error, ret=%d\n", + __func__, ret); + return ret; + } + + return 0; +} + +/* This sets the timeout to seconds. Does not issue a feed after. */ +static int ts7100_wdt_set_timeout(struct watchdog_device *wdt, + unsigned int timeout) +{ + struct i2c_client *client = to_i2c_client(wdt->parent); + u8 tmp[4]; + + wdt->timeout = timeout; + /* + * WDT has centisecond granularity, kernel is easier with whole + * second increments + */ + timeout *= 100; + tmp[0] = timeout & 0xFF; + tmp[1] = (timeout >> 8) & 0xFF; + tmp[2] = (timeout >> 16) & 0xFF; + tmp[3] = (timeout >> 24) & 0xFF; + + return ts7100_wdt_write(client, WDT_TIMEOUT, tmp, 4); +} + +static int ts7100_wdt_start(struct watchdog_device *wdt) +{ + struct i2c_client *client = to_i2c_client(wdt->parent); + u8 buf = WDT_FEED_CMD; + + dev_dbg(&client->dev, "Feeding WDT with %d s\n", wdt->timeout); + + return ts7100_wdt_write(client, WDT_CTRL, &buf, 1); +} + +static int ts7100_wdt_stop(struct watchdog_device *wdt) +{ + struct i2c_client *client = to_i2c_client(wdt->parent); + u8 buf = WDT_FEED_CMD; + + dev_dbg(&client->dev, "%s\n", __func__); + + /* Feeding with a timeout of 0 will disable WDT */ + ts7100_wdt_set_timeout(wdt, 0); + return ts7100_wdt_write(client, WDT_CTRL, &buf, 1); +} + +static int ts7100_wdt_restart(struct watchdog_device *wdt, + unsigned long a, void *b) +{ + struct i2c_client *client = to_i2c_client(wdt->parent); + u8 buf = WDT_FEED_CMD; + + dev_dbg(&client->dev, "%s\n", __func__); + + /* Set WDT for 1 s timeout and stall CPU */ + ts7100_wdt_set_timeout(wdt, 1); + ts7100_wdt_write(client, WDT_CTRL, &buf, 1); + + while (1) + ; + + return 0; +} + +static struct watchdog_info ts7100_wdt_info = { + .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | + WDIOF_MAGICCLOSE, + .identity = "TS-7100 uC Watchdog", +}; + +/* NOTE: + * If .ping is not provided, .start is used. Both would end up doing the same + * operation anyway. + * WDIOC_KEEPALIVE ioctl() still functions when .ping is not defined (.start is + * called instead), so long as WDIOF_KEEPALIVEPING is set as an option + */ +static struct watchdog_ops ts7100_wdt_ops = { + .owner = THIS_MODULE, + .start = ts7100_wdt_start, + .stop = ts7100_wdt_stop, + .set_timeout = ts7100_wdt_set_timeout, + .restart = ts7100_wdt_restart, +}; + +static struct watchdog_device ts_wdt_wdd = { + .info = &ts7100_wdt_info, + .ops = &ts7100_wdt_ops, + /* + * A timeout of 0 means disable. Due to how the validity of the timeout + * is checked, we need to spec a minimum timeout of 0. This allows the + * FDT to spec a timeout of 0, disabling the WDT on startup. This may + * cause issues in specific scenarios. + */ + .min_timeout = 0, + .max_timeout = 4294967, + .status = WATCHDOG_NOWAYOUT_INIT_STATUS, + .timeout = TS_DEFAULT_TIMEOUT, +}; + +static int ts7100_wdt_probe(struct i2c_client *client) +{ + ts_wdt_wdd.parent = &client->dev; + + /* + * On supported platforms either: + * The bootloader has already armed the WDT. + * -or- + * This platform's bootloader doesn't support starting the WDT and we + * want it started as quickly as possible at boot. + * + * In either case, there is no mechanism to query the WDT running status + * in hardware so we want to ensure the WDT is started and let the WDT + * core know that it is. If CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED is set, + * then the WDT core will know to automatically feed this until + * userspace can take over. If not set, a single feed takes place at + * this point in time.we + */ + + if (of_property_read_bool(client->dev.of_node, "enable-early")) + set_bit(WDOG_HW_RUNNING, &ts_wdt_wdd.status); + + watchdog_set_nowayout(&ts_wdt_wdd, nowayout); + watchdog_set_restart_priority(&ts_wdt_wdd, 128); + + return watchdog_register_device(&ts_wdt_wdd); +} + +static const struct i2c_device_id ts7100_wdt_id[] = { + { "ts7100-wdt", 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, ts7100_wdt_id); + +static const struct of_device_id ts7100_wdt_of_match[] = { + { .compatible = "technologic,ts7100-wdt", }, + { }, +}; +MODULE_DEVICE_TABLE(of, ts7100_wdt_of_match); + +MODULE_ALIAS("platform:ts7100_wdt"); + +static struct i2c_driver ts7100_wdt_driver = { + .driver = { + .name = "ts7100_wdt", + .of_match_table = ts7100_wdt_of_match, + .owner = THIS_MODULE, + }, + .probe = ts7100_wdt_probe, + .id_table = ts7100_wdt_id, +}; +module_i2c_driver(ts7100_wdt_driver); + +MODULE_AUTHOR("Kris Bahnsen "); +MODULE_DESCRIPTION("embeddedTS' TS-7100 (and compat.) WDT driver"); +MODULE_LICENSE("GPL"); From 04460f4c92af4dea99f1d35fb1c6b44c3bbb2112 Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Mon, 27 Mar 2023 12:14:55 -0700 Subject: [PATCH 070/244] irqchip/armada-370-xp: Support all 32 MSI IRQs --- drivers/irqchip/irq-armada-370-xp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c index a44c49e985b75..847945432bd71 100644 --- a/drivers/irqchip/irq-armada-370-xp.c +++ b/drivers/irqchip/irq-armada-370-xp.c @@ -140,7 +140,7 @@ #define IPI_DOORBELL_NR 8 #define IPI_DOORBELL_MASK GENMASK(7, 0) #define PCI_MSI_DOORBELL_START 16 -#define PCI_MSI_DOORBELL_NR 16 +#define PCI_MSI_DOORBELL_NR 32 #define PCI_MSI_DOORBELL_MASK GENMASK(31, 16) /* MSI interrupt definitions for non-IPI platforms */ From 47dc68123ca7feaa1a49967a094c124c8c3a3f69 Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Mon, 27 Mar 2023 13:29:50 -0700 Subject: [PATCH 071/244] irqchip: irq-ts7840: Initial commit Initial commit of TS-7840 IRQ expander support --- drivers/irqchip/Kconfig | 7 ++ drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-ts7840.c | 163 +++++++++++++++++++++++++++++++++++ 3 files changed, 171 insertions(+) create mode 100644 drivers/irqchip/irq-ts7840.c diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 7a93d99fb02b2..17f6387ee7e79 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -345,6 +345,13 @@ config TS4800_IRQ help Support for the TS-4800 FPGA IRQ controller +config TS7840_IRQ + tristate "TS-7840 IRQ controller" + select IRQ_DOMAIN + depends on HAS_IOMEM + help + Support for the TS-7840 FPGA IRQ controller + config TSWEIM_FPGA_INTC tristate "TS-71XX WEIM FPGA IRQ Support" default n diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 077d2d8af7f30..0e8be945c98d1 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -62,6 +62,7 @@ obj-$(CONFIG_ARCH_VT8500) += irq-vt8500.o obj-$(CONFIG_ST_IRQCHIP) += irq-st.o obj-$(CONFIG_TB10X_IRQC) += irq-tb10x.o obj-$(CONFIG_TS4800_IRQ) += irq-ts4800.o +obj-$(CONFIG_TS7840_IRQ) += irq-ts7840.o obj-$(CONFIG_TSWEIM_FPGA_INTC) += irq-ts71xxweim.o obj-$(CONFIG_XTENSA) += irq-xtensa-pic.o obj-$(CONFIG_XTENSA_MX) += irq-xtensa-mx.o diff --git a/drivers/irqchip/irq-ts7840.c b/drivers/irqchip/irq-ts7840.c new file mode 100644 index 0000000000000..094bccc9f98c8 --- /dev/null +++ b/drivers/irqchip/irq-ts7840.c @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Multiplexed-IRQs driver for TS-7840's FPGA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define IRQ_STATUS 0x0 +#define IRQ_MASK 0x4 + +struct ts7840_irq_data { + void __iomem *base; + struct irq_domain *domain; + struct irq_chip irq_chip; + raw_spinlock_t mask_lock; +}; + +static void ts7840_irq_mask(struct irq_data *d) +{ + struct ts7840_irq_data *data = irq_data_get_irq_chip_data(d); + unsigned long flags; + u32 reg; + + raw_spin_lock_irqsave(&data->mask_lock, flags); + reg = readl(data->base + IRQ_MASK); + writel(reg & ~(1 << d->hwirq), data->base + IRQ_MASK); + raw_spin_unlock_irqrestore(&data->mask_lock, flags); +} + +static void ts7840_irq_unmask(struct irq_data *d) +{ + struct ts7840_irq_data *data = irq_data_get_irq_chip_data(d); + unsigned long flags; + u32 reg; + + raw_spin_lock_irqsave(&data->mask_lock, flags); + reg = readl(data->base + IRQ_MASK); + writel(reg | (1 << d->hwirq), data->base + IRQ_MASK); + raw_spin_unlock_irqrestore(&data->mask_lock, flags); +} + +static int ts7840_irqdomain_map(struct irq_domain *d, unsigned int irq, + irq_hw_number_t hwirq) +{ + struct ts7840_irq_data *data = d->host_data; + + irq_set_chip_and_handler(irq, &data->irq_chip, handle_level_irq); + irq_set_chip_data(irq, data); + irq_set_status_flags(irq, IRQ_LEVEL); + irq_set_status_flags(irq, IRQ_IS_POLLED); + + return 0; +} + +static const struct irq_domain_ops ts7840_ic_ops = { + .map = ts7840_irqdomain_map, + .xlate = irq_domain_xlate_onecell, +}; + +static void ts7840_ic_chained_handle_irq(struct irq_desc *desc) +{ + struct ts7840_irq_data *data = irq_desc_get_handler_data(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); + u32 status = readl(data->base + IRQ_STATUS); + + if (status == 0) + return; + + chained_irq_enter(chip, desc); + + while (status) { + unsigned int bit = __ffs(status); + int irq = irq_find_mapping(data->domain, bit); + + status &= ~(1 << bit); + generic_handle_irq(irq); + } + + chained_irq_exit(chip, desc); +} + +static int ts7840_ic_probe(struct platform_device *pdev) +{ + struct device_node *node = pdev->dev.of_node; + struct ts7840_irq_data *data; + struct irq_chip *irq_chip; + struct resource *res; + int parent_irq; + + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + data->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(data->base)) + return PTR_ERR(data->base); + + /* Clear any enabled IRQs */ + writel(0x0, data->base + IRQ_MASK); + + parent_irq = irq_of_parse_and_map(node, 0); + if (!parent_irq) { + dev_err(&pdev->dev, "failed to get parent IRQ\n"); + return -EINVAL; + } + + irq_chip = &data->irq_chip; + irq_chip->name = dev_name(&pdev->dev); + irq_chip->irq_mask = ts7840_irq_mask; + irq_chip->irq_unmask = ts7840_irq_unmask; + raw_spin_lock_init(&data->mask_lock); + + data->domain = irq_domain_add_linear(node, 32, &ts7840_ic_ops, data); + if (!data->domain) { + dev_err(&pdev->dev, "cannot add IRQ domain\n"); + return -ENOMEM; + } + + irq_set_chained_handler_and_data(parent_irq, + ts7840_ic_chained_handle_irq, data); + + platform_set_drvdata(pdev, data); + + return 0; +} + +static void ts7840_ic_remove(struct platform_device *pdev) +{ + struct ts7840_irq_data *data = platform_get_drvdata(pdev); + + irq_domain_remove(data->domain); +} + +static const struct of_device_id ts7840_ic_of_match[] = { + { .compatible = "technologic,ts7840-irqc", }, + {}, +}; +MODULE_DEVICE_TABLE(of, ts7840_ic_of_match); + +static struct platform_driver ts7840_ic_driver = { + .probe = ts7840_ic_probe, + .remove = ts7840_ic_remove, + .driver = { + .name = "ts7840-irqc", + .of_match_table = ts7840_ic_of_match, + }, +}; +module_platform_driver(ts7840_ic_driver); + +MODULE_AUTHOR("Mark Featherston "); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:ts7840_irqc"); From aa6413d4a6cdcc204f14c0b30ff36c7d703fdcd9 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Wed, 17 Sep 2025 21:15:49 +0000 Subject: [PATCH 072/244] Revert "irqchip: irq-ts7840: Initial commit" This reverts commit b2097deff869b56d36cf9bee12b97f979f3f4403. --- drivers/irqchip/Kconfig | 7 -- drivers/irqchip/Makefile | 1 - drivers/irqchip/irq-ts7840.c | 163 ----------------------------------- 3 files changed, 171 deletions(-) delete mode 100644 drivers/irqchip/irq-ts7840.c diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 17f6387ee7e79..7a93d99fb02b2 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -345,13 +345,6 @@ config TS4800_IRQ help Support for the TS-4800 FPGA IRQ controller -config TS7840_IRQ - tristate "TS-7840 IRQ controller" - select IRQ_DOMAIN - depends on HAS_IOMEM - help - Support for the TS-7840 FPGA IRQ controller - config TSWEIM_FPGA_INTC tristate "TS-71XX WEIM FPGA IRQ Support" default n diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 0e8be945c98d1..077d2d8af7f30 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -62,7 +62,6 @@ obj-$(CONFIG_ARCH_VT8500) += irq-vt8500.o obj-$(CONFIG_ST_IRQCHIP) += irq-st.o obj-$(CONFIG_TB10X_IRQC) += irq-tb10x.o obj-$(CONFIG_TS4800_IRQ) += irq-ts4800.o -obj-$(CONFIG_TS7840_IRQ) += irq-ts7840.o obj-$(CONFIG_TSWEIM_FPGA_INTC) += irq-ts71xxweim.o obj-$(CONFIG_XTENSA) += irq-xtensa-pic.o obj-$(CONFIG_XTENSA_MX) += irq-xtensa-mx.o diff --git a/drivers/irqchip/irq-ts7840.c b/drivers/irqchip/irq-ts7840.c deleted file mode 100644 index 094bccc9f98c8..0000000000000 --- a/drivers/irqchip/irq-ts7840.c +++ /dev/null @@ -1,163 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Multiplexed-IRQs driver for TS-7840's FPGA - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define IRQ_STATUS 0x0 -#define IRQ_MASK 0x4 - -struct ts7840_irq_data { - void __iomem *base; - struct irq_domain *domain; - struct irq_chip irq_chip; - raw_spinlock_t mask_lock; -}; - -static void ts7840_irq_mask(struct irq_data *d) -{ - struct ts7840_irq_data *data = irq_data_get_irq_chip_data(d); - unsigned long flags; - u32 reg; - - raw_spin_lock_irqsave(&data->mask_lock, flags); - reg = readl(data->base + IRQ_MASK); - writel(reg & ~(1 << d->hwirq), data->base + IRQ_MASK); - raw_spin_unlock_irqrestore(&data->mask_lock, flags); -} - -static void ts7840_irq_unmask(struct irq_data *d) -{ - struct ts7840_irq_data *data = irq_data_get_irq_chip_data(d); - unsigned long flags; - u32 reg; - - raw_spin_lock_irqsave(&data->mask_lock, flags); - reg = readl(data->base + IRQ_MASK); - writel(reg | (1 << d->hwirq), data->base + IRQ_MASK); - raw_spin_unlock_irqrestore(&data->mask_lock, flags); -} - -static int ts7840_irqdomain_map(struct irq_domain *d, unsigned int irq, - irq_hw_number_t hwirq) -{ - struct ts7840_irq_data *data = d->host_data; - - irq_set_chip_and_handler(irq, &data->irq_chip, handle_level_irq); - irq_set_chip_data(irq, data); - irq_set_status_flags(irq, IRQ_LEVEL); - irq_set_status_flags(irq, IRQ_IS_POLLED); - - return 0; -} - -static const struct irq_domain_ops ts7840_ic_ops = { - .map = ts7840_irqdomain_map, - .xlate = irq_domain_xlate_onecell, -}; - -static void ts7840_ic_chained_handle_irq(struct irq_desc *desc) -{ - struct ts7840_irq_data *data = irq_desc_get_handler_data(desc); - struct irq_chip *chip = irq_desc_get_chip(desc); - u32 status = readl(data->base + IRQ_STATUS); - - if (status == 0) - return; - - chained_irq_enter(chip, desc); - - while (status) { - unsigned int bit = __ffs(status); - int irq = irq_find_mapping(data->domain, bit); - - status &= ~(1 << bit); - generic_handle_irq(irq); - } - - chained_irq_exit(chip, desc); -} - -static int ts7840_ic_probe(struct platform_device *pdev) -{ - struct device_node *node = pdev->dev.of_node; - struct ts7840_irq_data *data; - struct irq_chip *irq_chip; - struct resource *res; - int parent_irq; - - data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); - if (!data) - return -ENOMEM; - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - data->base = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(data->base)) - return PTR_ERR(data->base); - - /* Clear any enabled IRQs */ - writel(0x0, data->base + IRQ_MASK); - - parent_irq = irq_of_parse_and_map(node, 0); - if (!parent_irq) { - dev_err(&pdev->dev, "failed to get parent IRQ\n"); - return -EINVAL; - } - - irq_chip = &data->irq_chip; - irq_chip->name = dev_name(&pdev->dev); - irq_chip->irq_mask = ts7840_irq_mask; - irq_chip->irq_unmask = ts7840_irq_unmask; - raw_spin_lock_init(&data->mask_lock); - - data->domain = irq_domain_add_linear(node, 32, &ts7840_ic_ops, data); - if (!data->domain) { - dev_err(&pdev->dev, "cannot add IRQ domain\n"); - return -ENOMEM; - } - - irq_set_chained_handler_and_data(parent_irq, - ts7840_ic_chained_handle_irq, data); - - platform_set_drvdata(pdev, data); - - return 0; -} - -static void ts7840_ic_remove(struct platform_device *pdev) -{ - struct ts7840_irq_data *data = platform_get_drvdata(pdev); - - irq_domain_remove(data->domain); -} - -static const struct of_device_id ts7840_ic_of_match[] = { - { .compatible = "technologic,ts7840-irqc", }, - {}, -}; -MODULE_DEVICE_TABLE(of, ts7840_ic_of_match); - -static struct platform_driver ts7840_ic_driver = { - .probe = ts7840_ic_probe, - .remove = ts7840_ic_remove, - .driver = { - .name = "ts7840-irqc", - .of_match_table = ts7840_ic_of_match, - }, -}; -module_platform_driver(ts7840_ic_driver); - -MODULE_AUTHOR("Mark Featherston "); -MODULE_LICENSE("GPL v2"); -MODULE_ALIAS("platform:ts7840_irqc"); From 2a0d4cbe73c9a63ab514aed39050cdeaae348850 Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Mon, 27 Mar 2023 15:34:44 -0700 Subject: [PATCH 073/244] mtd: spi-nor: issi: Add is25lq016b support --- drivers/mtd/spi-nor/issi.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/mtd/spi-nor/issi.c b/drivers/mtd/spi-nor/issi.c index 18d9a00aa22eb..8353d513beadf 100644 --- a/drivers/mtd/spi-nor/issi.c +++ b/drivers/mtd/spi-nor/issi.c @@ -80,6 +80,11 @@ static const struct flash_info issi_nor_parts[] = { .name = "is25lp080d", .size = SZ_1M, .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, + }, { + .id = SNOR_ID(0x9d, 0x40, 0x15), + .name = "is25lp016b", + .size = SZ_2M, + .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, }, { .id = SNOR_ID(0x9d, 0x60, 0x15), .name = "is25lp016d", From d57543030d299e14354aeb5e2cd035a21dffd05e Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Tue, 28 Mar 2023 11:04:23 -0700 Subject: [PATCH 074/244] can: sja1000: technologic: Add 32-bit memory window access Signed-off-by: Mark Featherston Signed-off-by: Kris Bahnsen --- drivers/net/can/sja1000/sja1000_platform.c | 57 +++++++++++++++++++++- 1 file changed, 55 insertions(+), 2 deletions(-) diff --git a/drivers/net/can/sja1000/sja1000_platform.c b/drivers/net/can/sja1000/sja1000_platform.c index 2d555f854008b..c8866c6111c3b 100644 --- a/drivers/net/can/sja1000/sja1000_platform.c +++ b/drivers/net/can/sja1000/sja1000_platform.c @@ -94,12 +94,65 @@ static void sp_technologic_write_reg16(const struct sja1000_priv *priv, spin_unlock_irqrestore(&tp->io_lock, flags); } +#define TS_CAN_START BIT(31) +#define TS_CAN_WRITE BIT(30) +static u8 sp_technologic_read_reg32(const struct sja1000_priv *priv, int reg) +{ + struct technologic_priv *tp = priv->priv; + unsigned long flags; + u32 val; + + spin_lock_irqsave(&tp->io_lock, flags); + while (readl(priv->reg_base) & TS_CAN_START) + ; + writel(TS_CAN_START | (u32)reg, priv->reg_base); + + do { + val = readl(priv->reg_base); + } while (val & TS_CAN_START); + + spin_unlock_irqrestore(&tp->io_lock, flags); + + return (u8)((val >> 8) & 0xFF); +} + +static void sp_technologic_write_reg32(const struct sja1000_priv *priv, + int reg, u8 val) +{ + struct technologic_priv *tp = priv->priv; + unsigned long flags; + + spin_lock_irqsave(&tp->io_lock, flags); + while (readl(priv->reg_base) & TS_CAN_START) + ; + + writel(TS_CAN_START | TS_CAN_WRITE | (u32)reg | ((u16)val << 8), + priv->reg_base); + spin_unlock_irqrestore(&tp->io_lock, flags); +} + static void sp_technologic_init(struct sja1000_priv *priv, struct device_node *of) { struct technologic_priv *tp = priv->priv; + int err; + u32 prop; + + err = of_property_read_u32(of, "reg-io-width", &prop); + if (err) + prop = 2; /* 16 bit is default */ + + switch (prop) { + case 4: + priv->read_reg = sp_technologic_read_reg32; + priv->write_reg = sp_technologic_write_reg32; + break; + case 2: + default: + priv->read_reg = sp_technologic_read_reg16; + priv->write_reg = sp_technologic_write_reg16; + break; + } - priv->read_reg = sp_technologic_read_reg16; - priv->write_reg = sp_technologic_write_reg16; spin_lock_init(&tp->io_lock); } From 2549826a5e3ab98d233926c02f3f539735c5fa07 Mon Sep 17 00:00:00 2001 From: Michael Peters Date: Thu, 16 Mar 2023 14:28:43 -0700 Subject: [PATCH 075/244] tsa38x_defconfig: Add new defconfig for embeddedTS Marvell Armada 38x series --- arch/arm/configs/tsa38x_defconfig | 1091 +++++++++++++++++++++++++++++ 1 file changed, 1091 insertions(+) create mode 100644 arch/arm/configs/tsa38x_defconfig diff --git a/arch/arm/configs/tsa38x_defconfig b/arch/arm/configs/tsa38x_defconfig new file mode 100644 index 0000000000000..cbc51bbf797fe --- /dev/null +++ b/arch/arm/configs/tsa38x_defconfig @@ -0,0 +1,1091 @@ +CONFIG_KERNEL_LZO=y +CONFIG_DEFAULT_HOSTNAME="" +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_GENERIC_IRQ_DEBUGFS=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_PREEMPT=y +CONFIG_PSI=y +CONFIG_IKCONFIG=m +CONFIG_IKCONFIG_PROC=y +CONFIG_CGROUPS=y +CONFIG_MEMCG=y +CONFIG_BLK_CGROUP=y +CONFIG_CGROUP_SCHED=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_RDMA=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CPUSETS=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_PERF=y +CONFIG_CGROUP_BPF=y +CONFIG_CGROUP_DEBUG=y +CONFIG_NAMESPACES=y +CONFIG_USER_NS=y +CONFIG_CHECKPOINT_RESTORE=y +CONFIG_BLK_DEV_INITRD=y +# CONFIG_RD_ZSTD is not set +CONFIG_EXPERT=y +CONFIG_PERF_EVENTS=y +CONFIG_SLAB=y +CONFIG_ARCH_MVEBU=y +CONFIG_MACH_ARMADA_38X=y +CONFIG_ARM_THUMBEE=y +# CONFIG_HARDEN_BRANCH_HISTORY is not set +CONFIG_SMP=y +CONFIG_HZ_1000=y +CONFIG_HIGHMEM=y +# CONFIG_ARM_MODULE_PLTS is not set +CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ATAG_DTB_COMPAT=y +CONFIG_EFI=y +# CONFIG_DMI is not set +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y +CONFIG_CPUFREQ_DT=y +CONFIG_CPU_IDLE=y +CONFIG_ARM_MVEBU_V7_CPUIDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_JUMP_LABEL=y +CONFIG_MODULES=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_COMPRESS=y +CONFIG_MODULE_COMPRESS_XZ=y +CONFIG_BLK_DEV_BSGLIB=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_MAC_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_LDM_PARTITION=y +CONFIG_LDM_DEBUG=y +CONFIG_CMDLINE_PARTITION=y +CONFIG_BINFMT_MISC=y +CONFIG_CMA=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_PACKET_DIAG=m +CONFIG_UNIX=y +CONFIG_UNIX_DIAG=m +CONFIG_TLS=m +CONFIG_XFRM_USER=m +CONFIG_XFRM_SUB_POLICY=y +CONFIG_XFRM_MIGRATE=y +CONFIG_XFRM_STATISTICS=y +CONFIG_NET_KEY=m +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_FIB_TRIE_STATS=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE_DEMUX=m +CONFIG_NET_IPGRE=m +CONFIG_NET_IPGRE_BROADCAST=y +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_NET_IPVTI=m +CONFIG_NET_FOU_IP_TUNNELS=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_ESP_OFFLOAD=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_UDP_DIAG=m +CONFIG_INET_RAW_DIAG=m +CONFIG_INET_DIAG_DESTROY=y +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_TCP_MD5SIG=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_ESP_OFFLOAD=m +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_MIP6=m +CONFIG_IPV6_VTI=m +CONFIG_IPV6_SIT_6RD=y +CONFIG_IPV6_GRE=m +CONFIG_IPV6_SUBTREES=y +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y +CONFIG_IPV6_PIMSM_V2=y +CONFIG_IPV6_SEG6_LWTUNNEL=y +CONFIG_IPV6_SEG6_HMAC=y +CONFIG_NETWORK_SECMARK=y +CONFIG_NETWORK_PHY_TIMESTAMPING=y +CONFIG_NETFILTER=y +CONFIG_BRIDGE_NETFILTER=m +CONFIG_NF_CONNTRACK=m +CONFIG_NF_LOG_NETDEV=m +CONFIG_NF_CONNTRACK_SECMARK=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_TIMEOUT=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y +CONFIG_NF_CONNTRACK_AMANDA=m +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_SNMP=m +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_CT_NETLINK=m +CONFIG_NF_CT_NETLINK_TIMEOUT=m +CONFIG_NF_CT_NETLINK_HELPER=m +CONFIG_NETFILTER_NETLINK_GLUE_CT=y +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_INET=y +CONFIG_NF_TABLES_NETDEV=y +CONFIG_NFT_NUMGEN=m +CONFIG_NFT_CT=m +CONFIG_NFT_COUNTER=m +CONFIG_NFT_CONNLIMIT=m +CONFIG_NFT_LOG=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_REDIR=m +CONFIG_NFT_NAT=m +CONFIG_NFT_TUNNEL=m +CONFIG_NFT_OBJREF=m +CONFIG_NFT_QUEUE=m +CONFIG_NFT_QUOTA=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_HASH=m +CONFIG_NFT_XFRM=m +CONFIG_NFT_SOCKET=m +CONFIG_NFT_OSF=m +CONFIG_NFT_TPROXY=m +CONFIG_NFT_SYNPROXY=m +CONFIG_NFT_DUP_NETDEV=m +CONFIG_NFT_FWD_NETDEV=m +CONFIG_NF_FLOW_TABLE_INET=m +CONFIG_NF_FLOW_TABLE=m +CONFIG_NETFILTER_XT_SET=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LED=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_TEE=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFILTER_XT_TARGET_SECMARK=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m +CONFIG_NETFILTER_XT_MATCH_CGROUP=m +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_CPU=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_IPCOMP=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_IPVS=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +CONFIG_IP_SET=y +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPMARK=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_IPMAC=m +CONFIG_IP_SET_HASH_MAC=m +CONFIG_IP_SET_HASH_NETPORTNET=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETNET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m +CONFIG_IP_VS=m +CONFIG_IP_VS_IPV6=y +CONFIG_IP_VS_DEBUG=y +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_AH=y +CONFIG_IP_VS_PROTO_SCTP=y +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_WRR=m +CONFIG_IP_VS_LC=m +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_FO=m +CONFIG_IP_VS_OVF=m +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_MH=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_NQ=m +CONFIG_IP_VS_FTP=m +CONFIG_IP_VS_PE_SIP=m +CONFIG_NFT_DUP_IPV4=m +CONFIG_NFT_FIB_IPV4=m +CONFIG_NF_TABLES_ARP=y +CONFIG_NF_FLOW_TABLE_IPV4=m +CONFIG_NF_LOG_ARP=m +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_SYNPROXY=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NFT_FIB_IPV6=m +CONFIG_NF_FLOW_TABLE_IPV6=m +CONFIG_IP6_NF_IPTABLES=y +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RPFILTER=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_MATCH_SRH=m +CONFIG_IP6_NF_TARGET_HL=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_TARGET_SYNPROXY=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_RAW=m +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_IP6_NF_TARGET_NPT=m +CONFIG_DECNET_NF_GRABULATOR=m +CONFIG_NF_TABLES_BRIDGE=m +CONFIG_NFT_BRIDGE_META=m +CONFIG_NFT_BRIDGE_REJECT=m +CONFIG_NF_LOG_BRIDGE=m +CONFIG_NF_CONNTRACK_BRIDGE=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_IP6=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_NFLOG=m +CONFIG_BPFILTER=y +CONFIG_IP_DCCP=m +CONFIG_IP_DCCP_CCID2_DEBUG=y +CONFIG_IP_DCCP_CCID3_DEBUG=y +CONFIG_IP_SCTP=m +CONFIG_SCTP_COOKIE_HMAC_SHA1=y +CONFIG_RDS=m +CONFIG_RDS_TCP=m +CONFIG_TIPC=m +CONFIG_ATM=m +CONFIG_ATM_CLIP=m +CONFIG_ATM_LANE=m +CONFIG_ATM_MPOA=m +CONFIG_ATM_BR2684=m +CONFIG_L2TP=m +CONFIG_L2TP_V3=y +CONFIG_L2TP_IP=m +CONFIG_L2TP_ETH=m +CONFIG_BRIDGE=m +CONFIG_BRIDGE_VLAN_FILTERING=y +CONFIG_BRIDGE_MRP=y +CONFIG_NET_DSA=m +CONFIG_VLAN_8021Q=m +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_VLAN_8021Q_MVRP=y +CONFIG_DECNET=m +CONFIG_DECNET_ROUTER=y +CONFIG_LLC2=m +CONFIG_ATALK=m +CONFIG_DEV_APPLETALK=m +CONFIG_IPDDP=m +CONFIG_X25=m +CONFIG_LAPB=m +CONFIG_PHONET=m +CONFIG_6LOWPAN=m +CONFIG_6LOWPAN_DEBUGFS=y +CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m +CONFIG_6LOWPAN_GHC_UDP=m +CONFIG_6LOWPAN_GHC_ICMPV6=m +CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m +CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m +CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m +CONFIG_IEEE802154=m +CONFIG_IEEE802154_6LOWPAN=m +CONFIG_MAC802154=m +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_ATM=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_MULTIQ=m +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFB=m +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_DSMARK=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_DRR=m +CONFIG_NET_SCH_MQPRIO=m +CONFIG_NET_SCH_CHOKE=m +CONFIG_NET_SCH_QFQ=m +CONFIG_NET_SCH_CODEL=m +CONFIG_NET_SCH_FQ_CODEL=m +CONFIG_NET_SCH_FQ=m +CONFIG_NET_SCH_HHF=m +CONFIG_NET_SCH_PIE=m +CONFIG_NET_SCH_INGRESS=m +CONFIG_NET_SCH_PLUG=m +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_TCINDEX=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +CONFIG_CLS_U32_PERF=y +CONFIG_CLS_U32_MARK=y +CONFIG_NET_CLS_RSVP=m +CONFIG_NET_CLS_RSVP6=m +CONFIG_NET_CLS_FLOW=m +CONFIG_NET_CLS_CGROUP=m +CONFIG_NET_CLS_BPF=m +CONFIG_NET_CLS_FLOWER=m +CONFIG_NET_CLS_MATCHALL=m +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_CMP=m +CONFIG_NET_EMATCH_NBYTE=m +CONFIG_NET_EMATCH_U32=m +CONFIG_NET_EMATCH_META=m +CONFIG_NET_EMATCH_TEXT=m +CONFIG_NET_EMATCH_IPSET=m +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=m +CONFIG_NET_ACT_GACT=m +CONFIG_GACT_PROB=y +CONFIG_NET_ACT_MIRRED=m +CONFIG_NET_ACT_SAMPLE=m +CONFIG_NET_ACT_IPT=m +CONFIG_NET_ACT_NAT=m +CONFIG_NET_ACT_PEDIT=m +CONFIG_NET_ACT_SIMP=m +CONFIG_NET_ACT_SKBEDIT=m +CONFIG_NET_ACT_CSUM=m +CONFIG_NET_ACT_VLAN=m +CONFIG_NET_ACT_BPF=m +CONFIG_NET_ACT_CONNMARK=m +CONFIG_NET_ACT_SKBMOD=m +CONFIG_NET_ACT_IFE=m +CONFIG_NET_ACT_TUNNEL_KEY=m +CONFIG_DNS_RESOLVER=y +CONFIG_BATMAN_ADV=m +# CONFIG_BATMAN_ADV_BATMAN_V is not set +# CONFIG_BATMAN_ADV_DAT is not set +# CONFIG_BATMAN_ADV_MCAST is not set +CONFIG_BATMAN_ADV_DEBUGFS=y +CONFIG_OPENVSWITCH=m +CONFIG_VSOCKETS=m +CONFIG_NETLINK_DIAG=m +CONFIG_MPLS_ROUTING=m +CONFIG_MPLS_IPTUNNEL=m +CONFIG_HSR=m +CONFIG_NET_NCSI=y +CONFIG_CGROUP_NET_PRIO=y +CONFIG_BPF_JIT=y +CONFIG_BPF_STREAM_PARSER=y +CONFIG_CAN=m +CONFIG_CAN_J1939=m +CONFIG_CAN_ISOTP=m +CONFIG_CAN_VCAN=m +CONFIG_CAN_VXCAN=m +CONFIG_CAN_SLCAN=m +CONFIG_CAN_SJA1000=m +CONFIG_CAN_SJA1000_ISA=m +CONFIG_CAN_SJA1000_PLATFORM=m +CONFIG_CAN_8DEV_USB=m +CONFIG_CAN_EMS_USB=m +CONFIG_CAN_ESD_USB2=m +CONFIG_CAN_GS_USB=m +CONFIG_CAN_KVASER_USB=m +CONFIG_CAN_MCBA_USB=m +CONFIG_CAN_PEAK_USB=m +CONFIG_BT=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_BNEP=m +CONFIG_BT_HIDP=m +CONFIG_BT_HS=y +CONFIG_BT_6LOWPAN=m +CONFIG_BT_LEDS=y +CONFIG_BT_HCIBTUSB=m +CONFIG_BT_HCIBTSDIO=m +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_BCSP=y +CONFIG_BT_HCIUART_ATH3K=y +CONFIG_BT_HCIUART_INTEL=y +CONFIG_BT_HCIUART_AG6XX=y +CONFIG_BT_HCIBCM203X=m +CONFIG_BT_HCIBPA10X=m +CONFIG_BT_HCIBFUSB=m +CONFIG_BT_HCIVHCI=m +CONFIG_BT_MRVL=m +CONFIG_BT_MRVL_SDIO=m +CONFIG_BT_ATH3K=m +CONFIG_AF_RXRPC=m +CONFIG_AF_RXRPC_IPV6=y +CONFIG_AF_KCM=m +CONFIG_CFG80211=y +# CONFIG_CFG80211_DEFAULT_PS is not set +CONFIG_MAC80211=y +CONFIG_MAC80211_MESH=y +CONFIG_RFKILL=y +CONFIG_RFKILL_INPUT=y +CONFIG_RFKILL_GPIO=m +CONFIG_CEPH_LIB=m +CONFIG_NFC=m +CONFIG_NFC_DIGITAL=m +CONFIG_NFC_NCI=m +CONFIG_NFC_NCI_UART=m +CONFIG_NFC_HCI=m +CONFIG_NFC_TRF7970A=m +CONFIG_NFC_SIM=m +CONFIG_NFC_PORT100=m +CONFIG_NFC_FDP=m +CONFIG_NFC_PN533_USB=m +CONFIG_NFC_MRVL_USB=m +CONFIG_NFC_MRVL_UART=m +CONFIG_NFC_ST_NCI_I2C=m +CONFIG_NFC_ST_NCI_SPI=m +CONFIG_NFC_NXP_NCI=m +CONFIG_NFC_ST95HF=m +CONFIG_PCI=y +# CONFIG_PCIEASPM is not set +CONFIG_PCI_MVEBU=y +CONFIG_UEVENT_HELPER=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_CONNECTOR=m +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_SPI_NOR=y +CONFIG_BLK_DEV_PCIESSD_MTIP32XX=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_CRYPTOLOOP=y +CONFIG_BLK_DEV_NBD=m +CONFIG_CDROM_PKTCDVD=m +CONFIG_BLK_DEV_NVME=y +CONFIG_NVME_FC=y +CONFIG_NVME_TARGET=y +CONFIG_NVME_TARGET_LOOP=y +CONFIG_NVME_TARGET_FC=y +CONFIG_NVME_TARGET_FCLOOP=y +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_AT25=y +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_DEV_SR=m +CONFIG_CHR_DEV_SG=m +CONFIG_CHR_DEV_SCH=m +CONFIG_ATA=y +CONFIG_SATA_AHCI=y +CONFIG_AHCI_MVEBU=y +CONFIG_SATA_MV=y +CONFIG_ATA_GENERIC=m +CONFIG_MD=y +CONFIG_BLK_DEV_DM=m +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_NETDEVICES=y +CONFIG_BONDING=m +CONFIG_DUMMY=m +CONFIG_IFB=m +CONFIG_NET_TEAM=m +CONFIG_MACVLAN=m +CONFIG_MACVTAP=m +CONFIG_IPVLAN=m +CONFIG_IPVTAP=m +CONFIG_VXLAN=m +CONFIG_GENEVE=m +CONFIG_GTP=m +CONFIG_MACSEC=m +CONFIG_NETCONSOLE=m +CONFIG_TUN=m +CONFIG_VETH=m +CONFIG_NLMON=m +CONFIG_NET_VRF=m +CONFIG_ARCNET=m +CONFIG_NET_DSA_MV88E6XXX=m +# CONFIG_NET_VENDOR_AURORA is not set +CONFIG_MV643XX_ETH=y +CONFIG_MVNETA=y +CONFIG_MVPP2=y +CONFIG_LED_TRIGGER_PHY=y +CONFIG_SFP=y +CONFIG_MARVELL_PHY=y +CONFIG_MDIO_BITBANG=y +CONFIG_MDIO_GPIO=y +CONFIG_MDIO_BUS_MUX_GPIO=y +CONFIG_MDIO_BUS_MUX_MMIOREG=y +CONFIG_PPP=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPPOATM=m +CONFIG_PPPOE=m +CONFIG_PPTP=m +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_SLIP=m +CONFIG_USB_CATC=m +CONFIG_USB_KAWETH=m +CONFIG_USB_PEGASUS=m +CONFIG_USB_RTL8150=m +CONFIG_USB_RTL8152=m +CONFIG_USB_LAN78XX=m +CONFIG_USB_USBNET=y +CONFIG_USB_NET_AX8817X=m +CONFIG_USB_NET_AX88179_178A=m +CONFIG_USB_NET_CDCETHER=m +CONFIG_USB_NET_CDC_EEM=m +CONFIG_USB_NET_CDC_NCM=m +CONFIG_USB_NET_HUAWEI_CDC_NCM=m +CONFIG_USB_NET_CDC_MBIM=m +CONFIG_USB_NET_DM9601=m +CONFIG_USB_NET_SR9700=m +CONFIG_USB_NET_SR9800=m +CONFIG_USB_NET_SMSC75XX=m +CONFIG_USB_NET_SMSC95XX=y +CONFIG_USB_NET_GL620A=m +CONFIG_USB_NET_NET1080=m +CONFIG_USB_NET_PLUSB=m +CONFIG_USB_NET_MCS7830=m +CONFIG_USB_NET_CDC_SUBSET=m +CONFIG_USB_NET_ZAURUS=m +CONFIG_USB_NET_CX82310_ETH=m +CONFIG_USB_NET_KALMIA=m +CONFIG_USB_NET_QMI_WWAN=m +CONFIG_USB_HSO=m +CONFIG_USB_NET_INT51X1=m +CONFIG_USB_CDC_PHONET=m +CONFIG_USB_IPHETH=m +CONFIG_USB_SIERRA_NET=m +CONFIG_USB_VL600=m +CONFIG_USB_NET_CH9200=m +CONFIG_WIRELESS_WDS=y +CONFIG_ATH5K=m +CONFIG_ATH9K=m +CONFIG_ATH9K_HTC=m +CONFIG_ATH9K_HWRNG=y +CONFIG_CARL9170=m +CONFIG_CARL9170_HWRNG=y +CONFIG_ATH6KL=m +CONFIG_ATH6KL_SDIO=m +CONFIG_ATH6KL_USB=m +CONFIG_AR5523=m +CONFIG_WIL6210=m +CONFIG_WIL6210_TRACING=y +CONFIG_ATH10K=m +CONFIG_ATH10K_PCI=m +CONFIG_ATH10K_USB=m +CONFIG_WCN36XX=m +CONFIG_ATMEL=m +CONFIG_AT76C50X_USB=m +CONFIG_B43=m +CONFIG_B43LEGACY=m +CONFIG_BRCMSMAC=m +CONFIG_BRCMFMAC=m +CONFIG_BRCMFMAC_USB=y +CONFIG_BRCMFMAC_PCIE=y +CONFIG_IPW2100=m +CONFIG_IPW2100_MONITOR=y +CONFIG_IPW2100_DEBUG=y +CONFIG_IPW2200=m +CONFIG_IPW2200_MONITOR=y +CONFIG_IPW2200_PROMISCUOUS=y +CONFIG_IPW2200_QOS=y +CONFIG_IPW2200_DEBUG=y +CONFIG_IWL4965=m +CONFIG_IWL3945=m +CONFIG_IWLWIFI=m +CONFIG_IWLDVM=m +CONFIG_IWLMVM=m +CONFIG_IWLWIFI_BCAST_FILTERING=y +CONFIG_HERMES=m +CONFIG_HERMES_PRISM=y +CONFIG_PLX_HERMES=m +CONFIG_TMD_HERMES=m +CONFIG_NORTEL_HERMES=m +CONFIG_ORINOCO_USB=m +CONFIG_P54_COMMON=m +CONFIG_P54_USB=m +CONFIG_P54_PCI=m +CONFIG_P54_SPI=m +CONFIG_PRISM54=m +CONFIG_LIBERTAS=m +CONFIG_LIBERTAS_USB=m +CONFIG_LIBERTAS_SDIO=m +CONFIG_LIBERTAS_SPI=m +CONFIG_LIBERTAS_MESH=y +CONFIG_LIBERTAS_THINFIRM=m +CONFIG_MWIFIEX=m +CONFIG_MWIFIEX_SDIO=m +CONFIG_MWIFIEX_PCIE=m +CONFIG_MWIFIEX_USB=m +CONFIG_MWL8K=m +CONFIG_RT2X00=m +CONFIG_RT2400PCI=m +CONFIG_RT2500PCI=m +CONFIG_RT61PCI=m +CONFIG_RT2800PCI=m +CONFIG_RT2500USB=m +CONFIG_RT73USB=m +CONFIG_RT2800USB=m +CONFIG_RT2800USB_RT3573=y +CONFIG_RT2800USB_RT53XX=y +CONFIG_RT2800USB_RT55XX=y +CONFIG_RT2800USB_UNKNOWN=y +CONFIG_RTL8180=m +CONFIG_RTL8187=m +CONFIG_RTL_CARDS=m +CONFIG_RTL8192CE=m +CONFIG_RTL8192SE=m +CONFIG_RTL8192DE=m +CONFIG_RTL8723AE=m +CONFIG_RTL8723BE=m +CONFIG_RTL8188EE=m +CONFIG_RTL8192EE=m +CONFIG_RTL8821AE=m +CONFIG_RTL8192CU=m +CONFIG_RTL8XXXU=m +CONFIG_RTL8XXXU_UNTESTED=y +# CONFIG_WLAN_VENDOR_TI is not set +CONFIG_MAC80211_HWSIM=m +CONFIG_USB_NET_RNDIS_WLAN=m +CONFIG_INPUT_POLLDEV=m +CONFIG_INPUT_MOUSEDEV=m +CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_GPIO=y +CONFIG_INPUT_JOYSTICK=y +CONFIG_JOYSTICK_ANALOG=m +CONFIG_JOYSTICK_A3D=m +CONFIG_JOYSTICK_ADI=m +CONFIG_JOYSTICK_COBRA=m +CONFIG_JOYSTICK_GF2K=m +CONFIG_JOYSTICK_GRIP=m +CONFIG_JOYSTICK_GRIP_MP=m +CONFIG_JOYSTICK_GUILLEMOT=m +CONFIG_JOYSTICK_INTERACT=m +CONFIG_JOYSTICK_SIDEWINDER=m +CONFIG_JOYSTICK_TMDC=m +CONFIG_JOYSTICK_IFORCE=m +CONFIG_JOYSTICK_WARRIOR=m +CONFIG_JOYSTICK_MAGELLAN=m +CONFIG_JOYSTICK_SPACEORB=m +CONFIG_JOYSTICK_SPACEBALL=m +CONFIG_JOYSTICK_STINGER=m +CONFIG_JOYSTICK_TWIDJOY=m +CONFIG_JOYSTICK_ZHENHUA=m +CONFIG_JOYSTICK_AS5011=m +CONFIG_JOYSTICK_JOYDUMP=m +CONFIG_JOYSTICK_XPAD=m +CONFIG_JOYSTICK_PSXPAD_SPI=m +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ADS7846=m +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=24 +CONFIG_SERIAL_8250_RUNTIME_UARTS=24 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_8250_DW=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_N_GSM=m +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_OMAP is not set +CONFIG_HW_RANDOM_TS78XX=y +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_GPIO=y +CONFIG_I2C_MV64XXX=y +CONFIG_I2C_OCORES=y +CONFIG_I2C_TINY_USB=m +CONFIG_SPI=y +CONFIG_SPI_GPIO=y +CONFIG_SPI_OCORES=y +CONFIG_SPI_ORION=y +CONFIG_SPI_MUX=y +CONFIG_SPI_SPIDEV=y +CONFIG_PPS=y +CONFIG_PPS_CLIENT_LDISC=y +CONFIG_PPS_CLIENT_GPIO=y +CONFIG_PTP_1588_CLOCK=m +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_PCA953X=y +CONFIG_GPIO_TS7800V2=y +CONFIG_GPIO_TS7820=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_GPIO=y +CONFIG_POWER_SUPPLY_DEBUG=y +CONFIG_CHARGER_GPIO=m +CONFIG_SENSORS_GPIO_FAN=y +CONFIG_THERMAL=y +CONFIG_ARMADA_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_SYSFS=y +CONFIG_ORION_WATCHDOG=y +CONFIG_TS7100_WATCHDOG=y +CONFIG_MFD_TS78XX=y +CONFIG_MFD_SYSCON=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_RC_CORE=y +# CONFIG_VGA_ARB is not set +CONFIG_FB=y +CONFIG_FB_FOREIGN_ENDIAN=y +CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_TILEBLITTING=y +CONFIG_FB_SIMPLE=y +CONFIG_LCD_CLASS_DEVICE=m +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_DUMMY=m +CONFIG_SND_ALOOP=m +CONFIG_SND_SERIAL_U16550=m +CONFIG_SND_MPU401=m +# CONFIG_SND_PCI is not set +# CONFIG_SND_SPI is not set +CONFIG_SND_USB_AUDIO=m +CONFIG_SND_USB_UA101=m +CONFIG_SND_USB_CAIAQ=m +CONFIG_SND_USB_CAIAQ_INPUT=y +CONFIG_SND_USB_6FIRE=m +CONFIG_SND_USB_HIFACE=m +CONFIG_SND_BCD2000=m +CONFIG_SND_USB_POD=m +CONFIG_SND_USB_PODHD=m +CONFIG_SND_USB_TONEPORT=m +CONFIG_SND_USB_VARIAX=m +CONFIG_SND_SOC=y +CONFIG_SND_KIRKWOOD_SOC=y +CONFIG_SND_SOC_CS42L51_I2C=y +CONFIG_SND_SOC_SPDIF=y +CONFIG_SND_SIMPLE_CARD=y +CONFIG_HID_MAGICMOUSE=m +CONFIG_HID_SONY=m +CONFIG_HID_WIIMOTE=m +CONFIG_USB_LED_TRIG=y +CONFIG_USB=y +CONFIG_USB_LEDS_TRIGGER_USBPORT=m +CONFIG_USB_MON=m +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_MVEBU=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_PRINTER=m +CONFIG_USB_TMC=m +CONFIG_USB_STORAGE=y +CONFIG_USB_STORAGE_REALTEK=m +CONFIG_USB_STORAGE_DATAFAB=m +CONFIG_USB_STORAGE_FREECOM=m +CONFIG_USB_STORAGE_ISD200=m +CONFIG_USB_STORAGE_USBAT=m +CONFIG_USB_STORAGE_SDDR09=m +CONFIG_USB_STORAGE_SDDR55=m +CONFIG_USB_STORAGE_JUMPSHOT=m +CONFIG_USB_STORAGE_ALAUDA=m +CONFIG_USB_STORAGE_ONETOUCH=m +CONFIG_USB_STORAGE_KARMA=m +CONFIG_USB_STORAGE_CYPRESS_ATACB=m +CONFIG_USB_STORAGE_ENE_UB6250=m +CONFIG_USB_UAS=m +CONFIG_USBIP_CORE=m +CONFIG_USBIP_VHCI_HCD=m +CONFIG_USBIP_HOST=m +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_SIMPLE=m +CONFIG_USB_SERIAL_AIRCABLE=m +CONFIG_USB_SERIAL_ARK3116=m +CONFIG_USB_SERIAL_BELKIN=m +CONFIG_USB_SERIAL_CH341=m +CONFIG_USB_SERIAL_WHITEHEAT=m +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m +CONFIG_USB_SERIAL_CP210X=m +CONFIG_USB_SERIAL_CYPRESS_M8=m +CONFIG_USB_SERIAL_EMPEG=m +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_VISOR=m +CONFIG_USB_SERIAL_IPAQ=m +CONFIG_USB_SERIAL_IR=m +CONFIG_USB_SERIAL_EDGEPORT=m +CONFIG_USB_SERIAL_EDGEPORT_TI=m +CONFIG_USB_SERIAL_F81232=m +CONFIG_USB_SERIAL_F8153X=m +CONFIG_USB_SERIAL_GARMIN=m +CONFIG_USB_SERIAL_IPW=m +CONFIG_USB_SERIAL_IUU=m +CONFIG_USB_SERIAL_KEYSPAN_PDA=m +CONFIG_USB_SERIAL_KEYSPAN=m +CONFIG_USB_SERIAL_KLSI=m +CONFIG_USB_SERIAL_KOBIL_SCT=m +CONFIG_USB_SERIAL_MCT_U232=m +CONFIG_USB_SERIAL_METRO=m +CONFIG_USB_SERIAL_MOS7720=m +CONFIG_USB_SERIAL_MOS7840=m +CONFIG_USB_SERIAL_MXUPORT=m +CONFIG_USB_SERIAL_NAVMAN=m +CONFIG_USB_SERIAL_PL2303=m +CONFIG_USB_SERIAL_OTI6858=m +CONFIG_USB_SERIAL_QCAUX=m +CONFIG_USB_SERIAL_QUALCOMM=m +CONFIG_USB_SERIAL_SPCP8X5=m +CONFIG_USB_SERIAL_SAFE=m +CONFIG_USB_SERIAL_SAFE_PADDED=y +CONFIG_USB_SERIAL_SIERRAWIRELESS=m +CONFIG_USB_SERIAL_SYMBOL=m +CONFIG_USB_SERIAL_TI=m +CONFIG_USB_SERIAL_CYBERJACK=m +CONFIG_USB_SERIAL_XIRCOM=m +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_SERIAL_OMNINET=m +CONFIG_USB_SERIAL_OPTICON=m +CONFIG_USB_SERIAL_XSENS_MT=m +CONFIG_USB_SERIAL_WISHBONE=m +CONFIG_USB_SERIAL_SSU100=m +CONFIG_USB_SERIAL_QT2=m +CONFIG_USB_SERIAL_UPD78F0730=m +CONFIG_USB_SERIAL_DEBUG=m +CONFIG_USB_EMI62=m +CONFIG_USB_EMI26=m +CONFIG_USB_ADUTUX=m +CONFIG_USB_SEVSEG=m +CONFIG_USB_LEGOTOWER=m +CONFIG_USB_LCD=m +CONFIG_USB_CYPRESS_CY7C63=m +CONFIG_USB_CYTHERM=m +CONFIG_USB_IDMOUSE=m +CONFIG_USB_FTDI_ELAN=m +CONFIG_USB_APPLEDISPLAY=m +CONFIG_USB_SISUSBVGA=m +CONFIG_USB_LD=m +CONFIG_USB_TRANCEVIBRATOR=m +CONFIG_USB_IOWARRIOR=m +CONFIG_USB_TEST=m +CONFIG_USB_EHSET_TEST_FIXTURE=m +CONFIG_USB_ISIGHTFW=m +CONFIG_USB_YUREX=m +CONFIG_USB_HUB_USB251XB=m +CONFIG_USB_LINK_LAYER_TEST=m +CONFIG_USB_CHAOSKEY=m +CONFIG_USB_ATM=m +CONFIG_NOP_USB_XCEIV=y +CONFIG_MMC=y +CONFIG_TS_SDCARD=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_PXAV3=y +CONFIG_MMC_MVSDIO=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_ONESHOT=m +CONFIG_LEDS_TRIGGER_DISK=y +CONFIG_LEDS_TRIGGER_MTD=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=m +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_ACTIVITY=y +CONFIG_LEDS_TRIGGER_GPIO=m +CONFIG_LEDS_TRIGGER_DEFAULT_ON=m +CONFIG_LEDS_TRIGGER_TRANSIENT=m +CONFIG_LEDS_TRIGGER_CAMERA=m +CONFIG_LEDS_TRIGGER_PANIC=y +CONFIG_LEDS_TRIGGER_NETDEV=y +CONFIG_LEDS_TRIGGER_PATTERN=y +CONFIG_LEDS_TRIGGER_AUDIO=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_DS1307=y +CONFIG_RTC_DRV_PCF8563=y +CONFIG_RTC_DRV_S35390A=y +CONFIG_RTC_DRV_MV=y +CONFIG_RTC_DRV_ARMADA38X=y +CONFIG_DMADEVICES=y +CONFIG_MV_XOR=y +CONFIG_UIO=y +CONFIG_UIO_PDRV_GENIRQ=y +CONFIG_UIO_DMEM_GENIRQ=m +CONFIG_UIO_PCI_GENERIC=m +CONFIG_STAGING=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_MEMORY=y +CONFIG_IIO=y +CONFIG_IIO_BUFFER_CB=m +CONFIG_IIO_BUFFER_DMAENGINE=m +CONFIG_IIO_BUFFER_HW_CONSUMER=m +CONFIG_IIO_SW_DEVICE=m +CONFIG_IIO_SW_TRIGGER=m +CONFIG_IIO_TRIGGERED_EVENT=m +CONFIG_MMA8452=m +CONFIG_TS_SIMPLEADC=y +CONFIG_IIO_RESCALE=m +CONFIG_IIO_MUX=m +CONFIG_VL53L0X_I2C=m +CONFIG_PWM=y +CONFIG_PWM_DEBUG=y +CONFIG_PWM_TS=y +CONFIG_RAS=y +CONFIG_FPGA=m +CONFIG_MUX_GPIO=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_REISERFS_FS=m +CONFIG_REISERFS_FS_XATTR=y +CONFIG_REISERFS_FS_POSIX_ACL=y +CONFIG_REISERFS_FS_SECURITY=y +CONFIG_JFS_FS=m +CONFIG_JFS_POSIX_ACL=y +CONFIG_XFS_FS=m +CONFIG_XFS_POSIX_ACL=y +CONFIG_GFS2_FS=m +CONFIG_BTRFS_FS=m +CONFIG_BTRFS_FS_POSIX_ACL=y +CONFIG_NILFS2_FS=m +CONFIG_F2FS_FS=m +CONFIG_FS_ENCRYPTION=y +CONFIG_FANOTIFY=y +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=m +CONFIG_OVERLAY_FS=y +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_NTFS_FS=y +CONFIG_NTFS_RW=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_CONFIGFS_FS=y +CONFIG_EFIVAR_FS=y +CONFIG_NFS_FS=y +CONFIG_ROOT_NFS=y +CONFIG_RPCSEC_GSS_KRB5=m +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +CONFIG_NLS_UTF8=y +CONFIG_CRYPTO_ECDH=y +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_DEV_MARVELL_CESA=y +CONFIG_CRC_ITU_T=y +CONFIG_CRC7=y +CONFIG_DMA_CMA=y +CONFIG_PRINTK_TIME=y +CONFIG_DYNAMIC_DEBUG=y +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_DEBUG_FS=y +# CONFIG_DEBUG_MISC is not set +CONFIG_SOFTLOCKUP_DETECTOR=y +CONFIG_WQ_WATCHDOG=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_PREEMPT is not set +CONFIG_DEBUG_USER=y +# CONFIG_RUNTIME_TESTING_MENU is not set From 21cf6603b1696a0d8f78f52944b88ca791389082 Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Mon, 27 Mar 2023 12:18:27 -0700 Subject: [PATCH 076/244] tsa38x_minimal_defconfig: Initial commit of minimal config for embeddedTS tsa38x based platforms --- arch/arm/configs/tsa38x_minimal_defconfig | 283 ++++++++++++++++++++++ 1 file changed, 283 insertions(+) create mode 100644 arch/arm/configs/tsa38x_minimal_defconfig diff --git a/arch/arm/configs/tsa38x_minimal_defconfig b/arch/arm/configs/tsa38x_minimal_defconfig new file mode 100644 index 0000000000000..f6714eff84f78 --- /dev/null +++ b/arch/arm/configs/tsa38x_minimal_defconfig @@ -0,0 +1,283 @@ +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +# CONFIG_CROSS_MEMORY_ATTACH is not set +CONFIG_HIGH_RES_TIMERS=y +CONFIG_PREEMPT=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_CGROUPS=y +CONFIG_BLK_DEV_INITRD=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +# CONFIG_RD_ZSTD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_EXPERT=y +CONFIG_PERF_EVENTS=y +CONFIG_SLAB=y +CONFIG_ARCH_MVEBU=y +CONFIG_MACH_ARMADA_38X=y +CONFIG_ARM_THUMBEE=y +CONFIG_SMP=y +CONFIG_HIGHMEM=y +CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ATAG_DTB_COMPAT=y +CONFIG_CPU_FREQ=y +CONFIG_CPUFREQ_DT=y +CONFIG_CPU_IDLE=y +CONFIG_ARM_MVEBU_V7_CPUIDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MQ_IOSCHED_KYBER is not set +# CONFIG_COMPACTION is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IPV6 is not set +CONFIG_NET_DSA=y +CONFIG_VLAN_8021Q=y +CONFIG_CAN=m +CONFIG_CAN_SJA1000=m +CONFIG_CAN_SJA1000_ISA=m +CONFIG_CAN_SJA1000_PLATFORM=m +CONFIG_BT=m +CONFIG_BT_MRVL=m +CONFIG_BT_MRVL_SDIO=m +CONFIG_CFG80211=m +# CONFIG_CFG80211_DEFAULT_PS is not set +CONFIG_MAC80211=m +CONFIG_PCI=y +# CONFIG_PCIEASPM is not set +CONFIG_PCI_MVEBU=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD_NAND_MARVELL=y +CONFIG_MTD_SPI_NOR=y +CONFIG_BLK_DEV_NVME=y +CONFIG_EEPROM_AT24=y +CONFIG_BLK_DEV_SD=y +CONFIG_ATA=y +CONFIG_SATA_AHCI=y +CONFIG_AHCI_MVEBU=y +CONFIG_SATA_MV=y +CONFIG_NETDEVICES=y +CONFIG_NET_DSA_MV88E6XXX=y +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_ADAPTEC is not set +# CONFIG_NET_VENDOR_AGERE is not set +# CONFIG_NET_VENDOR_ALACRITECH is not set +# CONFIG_NET_VENDOR_ALTEON is not set +# CONFIG_NET_VENDOR_AMAZON is not set +# CONFIG_NET_VENDOR_AMD is not set +# CONFIG_NET_VENDOR_AQUANTIA is not set +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_ATHEROS is not set +# CONFIG_NET_VENDOR_AURORA is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_BROCADE is not set +# CONFIG_NET_VENDOR_CADENCE is not set +# CONFIG_NET_VENDOR_CAVIUM is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_CISCO is not set +# CONFIG_NET_VENDOR_CORTINA is not set +# CONFIG_NET_VENDOR_DEC is not set +# CONFIG_NET_VENDOR_DLINK is not set +# CONFIG_NET_VENDOR_EMULEX is not set +# CONFIG_NET_VENDOR_EZCHIP is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_GOOGLE is not set +# CONFIG_NET_VENDOR_HISILICON is not set +# CONFIG_NET_VENDOR_HUAWEI is not set +# CONFIG_NET_VENDOR_INTEL is not set +CONFIG_MVNETA=y +# CONFIG_NET_VENDOR_MELLANOX is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_MICROSEMI is not set +# CONFIG_NET_VENDOR_MYRI is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NETERION is not set +# CONFIG_NET_VENDOR_NETRONOME is not set +# CONFIG_NET_VENDOR_NI is not set +# CONFIG_NET_VENDOR_NVIDIA is not set +# CONFIG_NET_VENDOR_OKI is not set +# CONFIG_NET_VENDOR_PACKET_ENGINES is not set +# CONFIG_NET_VENDOR_PENSANDO is not set +# CONFIG_NET_VENDOR_QLOGIC is not set +# CONFIG_NET_VENDOR_QUALCOMM is not set +# CONFIG_NET_VENDOR_RDC is not set +# CONFIG_NET_VENDOR_REALTEK is not set +# CONFIG_NET_VENDOR_RENESAS is not set +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SOLARFLARE is not set +# CONFIG_NET_VENDOR_SILAN is not set +# CONFIG_NET_VENDOR_SIS is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_SOCIONEXT is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SUN is not set +# CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_TEHUTI is not set +# CONFIG_NET_VENDOR_TI is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +# CONFIG_NET_VENDOR_XILINX is not set +CONFIG_SFP=y +CONFIG_MARVELL_PHY=y +CONFIG_USB_NET_DRIVERS=m +CONFIG_USB_USBNET=m +# CONFIG_USB_NET_AX8817X is not set +# CONFIG_USB_NET_AX88179_178A is not set +# CONFIG_USB_NET_CDCETHER is not set +# CONFIG_USB_NET_CDC_NCM is not set +CONFIG_USB_NET_SMSC95XX=m +# CONFIG_USB_NET_NET1080 is not set +# CONFIG_USB_NET_CDC_SUBSET is not set +# CONFIG_USB_NET_ZAURUS is not set +# CONFIG_WLAN_VENDOR_ADMTEK is not set +# CONFIG_WLAN_VENDOR_ATH is not set +# CONFIG_WLAN_VENDOR_ATMEL is not set +# CONFIG_WLAN_VENDOR_BROADCOM is not set +# CONFIG_WLAN_VENDOR_CISCO is not set +# CONFIG_WLAN_VENDOR_INTEL is not set +# CONFIG_WLAN_VENDOR_INTERSIL is not set +# CONFIG_WLAN_VENDOR_MARVELL is not set +# CONFIG_WLAN_VENDOR_MEDIATEK is not set +# CONFIG_WLAN_VENDOR_MICROCHIP is not set +# CONFIG_WLAN_VENDOR_RALINK is not set +# CONFIG_WLAN_VENDOR_REALTEK is not set +# CONFIG_WLAN_VENDOR_RSI is not set +# CONFIG_WLAN_VENDOR_ST is not set +# CONFIG_WLAN_VENDOR_TI is not set +# CONFIG_WLAN_VENDOR_ZYDAS is not set +# CONFIG_WLAN_VENDOR_QUANTENNA is not set +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +CONFIG_SERIO_LIBPS2=y +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=24 +CONFIG_SERIAL_8250_RUNTIME_UARTS=24 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_DW=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_OMAP is not set +CONFIG_HW_RANDOM_TS78XX=y +# CONFIG_DEVPORT is not set +# CONFIG_RANDOM_TRUST_BOOTLOADER is not set +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_GPIO=y +CONFIG_I2C_MV64XXX=y +CONFIG_I2C_OCORES=y +CONFIG_SPI=y +CONFIG_SPI_GPIO=m +CONFIG_SPI_OCORES=m +CONFIG_SPI_ORION=y +CONFIG_SPI_MUX=y +CONFIG_SPI_SPIDEV=m +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_PCA953X=y +CONFIG_GPIO_TS7800V2=y +CONFIG_GPIO_TS7820=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_GPIO=y +CONFIG_POWER_SUPPLY=y +CONFIG_SENSORS_GPIO_FAN=y +CONFIG_SENSORS_PWM_FAN=y +CONFIG_THERMAL=y +CONFIG_ARMADA_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_ORION_WATCHDOG=y +CONFIG_TS7100_WATCHDOG=y +CONFIG_MFD_TS78XX=y +CONFIG_MFD_SYSCON=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +# CONFIG_VGA_ARB is not set +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_MVEBU=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_ACM=m +CONFIG_USB_STORAGE=y +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_NOP_USB_XCEIV=y +CONFIG_MMC=y +CONFIG_TS_SDCARD=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_PXAV3=y +CONFIG_MMC_MVSDIO=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_DS1307=y +CONFIG_DMADEVICES=y +CONFIG_MV_XOR=y +# CONFIG_VIRTIO_MENU is not set +# CONFIG_VHOST_MENU is not set +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_MEMORY=y +CONFIG_IIO=m +CONFIG_MMA8452=m +CONFIG_TS_SIMPLEADC=m +CONFIG_IIO_RESCALE=m +CONFIG_PWM=y +CONFIG_PWM_TS=m +CONFIG_PHY_MVEBU_A38X_COMPHY=y +CONFIG_MUX_GPIO=m +CONFIG_SLIMBUS=m +CONFIG_EXT4_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +# CONFIG_MISC_FILESYSTEMS is not set +CONFIG_NFS_FS=y +CONFIG_ROOT_NFS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +CONFIG_NLS_UTF8=y +CONFIG_CRYPTO_ECDH=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_CMAC=y +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_ZSTD=y +CONFIG_CRYPTO_DEV_MARVELL_CESA=y +CONFIG_CRC_ITU_T=m +CONFIG_CRC7=m +CONFIG_PRINTK_TIME=y +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_DEBUG_MISC is not set +# CONFIG_SCHED_DEBUG is not set +CONFIG_DEBUG_USER=y +# CONFIG_RUNTIME_TESTING_MENU is not set From 9869347675a93d0016bea82929b05715e112b2ae Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Mon, 27 Mar 2023 12:19:02 -0700 Subject: [PATCH 077/244] tests: ts_check_configs: Add tsa38x config support --- tests/ts_check_configs/run_test.sh | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/ts_check_configs/run_test.sh b/tests/ts_check_configs/run_test.sh index 2649b1ae1e7f6..b3585ad47431d 100755 --- a/tests/ts_check_configs/run_test.sh +++ b/tests/ts_check_configs/run_test.sh @@ -9,11 +9,13 @@ min_graphics_config_files=( ) full_headless_config_files=( + "tsa38x_defconfig" "tsimx6ul_defconfig" "tsimx28_defconfig" ) min_headless_config_files=( + "tsa38x_minimal_defconfig" "tsimx6ul_minimal_defconfig" "tsimx28_minimal_defconfig" ) From a42208be005097e108f4920a358b559af35f5d6b Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Tue, 28 Mar 2023 11:43:06 -0700 Subject: [PATCH 078/244] ARM: configs: tsimx6ul: Clean up graphics support Syncs graphics support between the minimal and full, adds SPI mono LCD support in minimal for TS-7553-V2 Signed-off-by: Kris Bahnsen --- arch/arm/configs/tsimx6ul_defconfig | 14 +++++++++++--- arch/arm/configs/tsimx6ul_minimal_defconfig | 20 ++++++++------------ 2 files changed, 19 insertions(+), 15 deletions(-) diff --git a/arch/arm/configs/tsimx6ul_defconfig b/arch/arm/configs/tsimx6ul_defconfig index e96905e13efc5..e2ce10518a8c8 100644 --- a/arch/arm/configs/tsimx6ul_defconfig +++ b/arch/arm/configs/tsimx6ul_defconfig @@ -539,7 +539,6 @@ CONFIG_SERIAL_OF_PLATFORM=y CONFIG_SERIAL_IMX=y CONFIG_SERIAL_IMX_CONSOLE=y CONFIG_SERIAL_DEV_BUS=y -CONFIG_I2C=y # CONFIG_I2C_COMPAT is not set CONFIG_I2C_CHARDEV=y CONFIG_I2C_MUX=y @@ -849,9 +848,19 @@ CONFIG_VIDEO_IMX_PXP=y # CONFIG_DVB_HELENE is not set # CONFIG_DVB_CXD2099 is not set # CONFIG_DVB_SP2 is not set -CONFIG_FB=m +CONFIG_IMX_IPUV3_CORE=y +CONFIG_DRM=y +CONFIG_DRM_PANEL_LVDS=y +CONFIG_DRM_PANEL_SIMPLE=y +CONFIG_DRM_IMX=y +CONFIG_DRM_IMX_PARALLEL_DISPLAY=y +CONFIG_DRM_MXSFB=y CONFIG_FB_MODE_HELPERS=y CONFIG_FB_ST7565P=m +CONFIG_LCD_CLASS_DEVICE=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_PWM=m +CONFIG_BACKLIGHT_GPIO=m CONFIG_SOUND=y CONFIG_SND=y # CONFIG_SND_ARM is not set @@ -1000,7 +1009,6 @@ CONFIG_DMADEVICES=y CONFIG_IMX_SDMA=y # CONFIG_MX3_IPU is not set CONFIG_DMATEST=m -CONFIG_SYNC_FILE=y # CONFIG_VIRTIO_MENU is not set # CONFIG_VHOST_MENU is not set CONFIG_STAGING=y diff --git a/arch/arm/configs/tsimx6ul_minimal_defconfig b/arch/arm/configs/tsimx6ul_minimal_defconfig index 8aadc17546c46..f17ad9cb90d0d 100644 --- a/arch/arm/configs/tsimx6ul_minimal_defconfig +++ b/arch/arm/configs/tsimx6ul_minimal_defconfig @@ -47,6 +47,7 @@ CONFIG_MODULE_SRCVERSION_ALL=y # CONFIG_BLK_DEV_BSG is not set # CONFIG_MQ_IOSCHED_KYBER is not set # CONFIG_COREDUMP is not set +CONFIG_CMA=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y @@ -179,6 +180,7 @@ CONFIG_KEYBOARD_IMX=y CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_ADS7846=m # CONFIG_SERIO is not set +CONFIG_VT_HW_CONSOLE_BINDING=y # CONFIG_LEGACY_PTYS is not set CONFIG_SERIAL_8250=m CONFIG_SERIAL_8250_NR_UARTS=24 @@ -214,6 +216,7 @@ CONFIG_POWER_RESET_TS_SUPERVISOR=y CONFIG_POWER_RESET_SYSCON=y CONFIG_POWER_RESET_SYSCON_POWEROFF=y # CONFIG_HWMON is not set +CONFIG_THERMAL=y CONFIG_THERMAL_STATISTICS=y CONFIG_THERMAL_WRITABLE_TRIPS=y CONFIG_CPU_THERMAL=y @@ -230,23 +233,17 @@ CONFIG_IMX_IPUV3_CORE=y CONFIG_DRM=y CONFIG_DRM_PANEL_LVDS=y CONFIG_DRM_PANEL_SIMPLE=y -CONFIG_DRM_PANEL_SEIKO_43WVF1G=y -CONFIG_DRM_TI_TFP410=y -CONFIG_DRM_DW_HDMI_CEC=y CONFIG_DRM_IMX=y CONFIG_DRM_IMX_PARALLEL_DISPLAY=y -CONFIG_DRM_IMX_TVE=y -CONFIG_DRM_IMX_LDB=y -CONFIG_DRM_IMX_HDMI=y -CONFIG_DRM_ETNAVIV=y CONFIG_DRM_MXSFB=y CONFIG_FB_MODE_HELPERS=y +# CONFIG_FB_MX3 is not set +CONFIG_FB_ST7565P=m CONFIG_LCD_CLASS_DEVICE=y -CONFIG_LCD_L4F00242T03=y CONFIG_LCD_PLATFORM=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BACKLIGHT_PWM=y CONFIG_BACKLIGHT_GPIO=y -CONFIG_FRAMEBUFFER_CONSOLE=y # CONFIG_USB_HID is not set CONFIG_USB=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y @@ -309,6 +306,7 @@ CONFIG_QUOTA_NETLINK_INTERFACE=y CONFIG_AUTOFS4_FS=m CONFIG_FUSE_FS=m CONFIG_VFAT_FS=y +CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y CONFIG_CONFIGFS_FS=y CONFIG_NFS_FS=y @@ -335,10 +333,8 @@ CONFIG_CRC_ITU_T=m CONFIG_CRC7=m CONFIG_LIBCRC32C=m CONFIG_XZ_DEC=y +CONFIG_DMA_CMA=y CONFIG_CMA_SIZE_MBYTES=64 -CONFIG_FONTS=y -CONFIG_FONT_8x8=y -CONFIG_FONT_8x16=y # CONFIG_SYMBOLIC_ERRNAME is not set # CONFIG_DEBUG_BUGVERBOSE is not set # CONFIG_ENABLE_MUST_CHECK is not set From 1acfd8eb220e781340a8502459e2b9ddd6544895 Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Thu, 30 Mar 2023 08:58:32 -0700 Subject: [PATCH 079/244] ARM: configs: tsimx6ul: Enable MTD by default Commonly used for our FPGA spi flash and needed for updating. --- arch/arm/configs/tsimx6ul_minimal_defconfig | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/configs/tsimx6ul_minimal_defconfig b/arch/arm/configs/tsimx6ul_minimal_defconfig index f17ad9cb90d0d..d4040e3da94ff 100644 --- a/arch/arm/configs/tsimx6ul_minimal_defconfig +++ b/arch/arm/configs/tsimx6ul_minimal_defconfig @@ -78,16 +78,16 @@ CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y CONFIG_IMX_WEIM=y CONFIG_TSPC104=y CONFIG_CONNECTOR=y -CONFIG_MTD=m +CONFIG_MTD=y # CONFIG_MTD_OF_PARTS is not set -CONFIG_MTD_BLOCK=m +CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=m CONFIG_MTD_JEDECPROBE=m CONFIG_MTD_CFI_INTELEXT=m CONFIG_MTD_CFI_AMDSTD=m CONFIG_MTD_CFI_STAA=m CONFIG_MTD_SST25L=m -CONFIG_MTD_SPI_NOR=m +CONFIG_MTD_SPI_NOR=y CONFIG_BLK_DEV_LOOP=y CONFIG_EEPROM_AT24=y CONFIG_EEPROM_AT25=y From 0ec1bba4bcd761546aafa6654c9aab9698c45a5e Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Fri, 31 Mar 2023 11:43:21 -0700 Subject: [PATCH 080/244] ARM: configs: tsimx6ul: compile in tssupervisor mfd devices MFD drivers do not end up in the device table so they should be compiled as =y or they require being manually loaded. --- arch/arm/configs/tsimx6ul_minimal_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/configs/tsimx6ul_minimal_defconfig b/arch/arm/configs/tsimx6ul_minimal_defconfig index d4040e3da94ff..46582257d9a9e 100644 --- a/arch/arm/configs/tsimx6ul_minimal_defconfig +++ b/arch/arm/configs/tsimx6ul_minimal_defconfig @@ -291,7 +291,7 @@ CONFIG_SENSORS_ISL29018=y CONFIG_MAG3110=y CONFIG_IIO_ST_MAGN_3AXIS=m CONFIG_MPL3115=y -CONFIG_TS_SUPERVISOR_TEMP=m +CONFIG_TS_SUPERVISOR_TEMP=y CONFIG_PWM=y CONFIG_PWM_IMX27=y CONFIG_PWM_TS=m From a68e63cf0aea670c9fc53828dc2c2e37175e24be Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Wed, 5 Apr 2023 13:32:35 -0700 Subject: [PATCH 081/244] tests: ts_check_configs: Add FTDI and CDC-ACM requirements --- tests/ts_check_configs/full_graphics_config_requirements | 2 ++ tests/ts_check_configs/full_headless_config_requirements | 2 ++ tests/ts_check_configs/min_graphics_config_requirements | 2 ++ tests/ts_check_configs/min_headless_config_requirements | 2 ++ 4 files changed, 8 insertions(+) diff --git a/tests/ts_check_configs/full_graphics_config_requirements b/tests/ts_check_configs/full_graphics_config_requirements index d6c1e297cea95..348f9e280f842 100644 --- a/tests/ts_check_configs/full_graphics_config_requirements +++ b/tests/ts_check_configs/full_graphics_config_requirements @@ -5,6 +5,8 @@ ######## Driver frameworks required on all hardware: CONFIG_SPI_SPIDEV=x +CONFIG_USB_ACM=x +CONFIG_USB_SERIAL_FTDI_SIO=x ######## Debug options: CONFIG_LOCKDEP=n diff --git a/tests/ts_check_configs/full_headless_config_requirements b/tests/ts_check_configs/full_headless_config_requirements index 05126e60cb0c2..b81b3dd1e0f30 100644 --- a/tests/ts_check_configs/full_headless_config_requirements +++ b/tests/ts_check_configs/full_headless_config_requirements @@ -5,6 +5,8 @@ ######## Driver frameworks required on all hardware: CONFIG_SPI_SPIDEV=x +CONFIG_USB_ACM=x +CONFIG_USB_SERIAL_FTDI_SIO=x ######## Debug options: CONFIG_LOCKDEP=n diff --git a/tests/ts_check_configs/min_graphics_config_requirements b/tests/ts_check_configs/min_graphics_config_requirements index 3433971232412..9cc9e9991ac80 100644 --- a/tests/ts_check_configs/min_graphics_config_requirements +++ b/tests/ts_check_configs/min_graphics_config_requirements @@ -5,6 +5,8 @@ ######## Driver frameworks required on all hardware: CONFIG_SPI_SPIDEV=x +CONFIG_USB_ACM=x +CONFIG_USB_SERIAL_FTDI_SIO=x ######## Debug options: CONFIG_LOCKDEP=n diff --git a/tests/ts_check_configs/min_headless_config_requirements b/tests/ts_check_configs/min_headless_config_requirements index 17e1be106bdb3..ca133782a6c8f 100644 --- a/tests/ts_check_configs/min_headless_config_requirements +++ b/tests/ts_check_configs/min_headless_config_requirements @@ -5,6 +5,8 @@ ######## Driver frameworks required on all hardware: CONFIG_SPI_SPIDEV=x +CONFIG_USB_ACM=x +CONFIG_USB_SERIAL_FTDI_SIO=x ######## Debug options: CONFIG_LOCKDEP=n From 5a79df884b783c11f6331ff506aabd57026a47ce Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Wed, 5 Apr 2023 13:34:25 -0700 Subject: [PATCH 082/244] ARM: configs: imx28_minimal: Add FTDI and CDC-ACM support --- arch/arm/configs/tsimx28_minimal_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/configs/tsimx28_minimal_defconfig b/arch/arm/configs/tsimx28_minimal_defconfig index 5872c6b91e14f..3b58eb596544c 100644 --- a/arch/arm/configs/tsimx28_minimal_defconfig +++ b/arch/arm/configs/tsimx28_minimal_defconfig @@ -205,10 +205,13 @@ CONFIG_USB_OTG=y CONFIG_USB_OTG_FSM=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y +CONFIG_USB_ACM=m CONFIG_USB_STORAGE=y CONFIG_USB_CHIPIDEA=y CONFIG_USB_CHIPIDEA_UDC=y CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_FTDI_SIO=m CONFIG_USB_MXS_PHY=y CONFIG_USB_GADGET=y CONFIG_USB_CONFIGFS=m From 816695d2f4caa49a271bbfc0f6d281a6bf0344c4 Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Wed, 5 Apr 2023 13:35:57 -0700 Subject: [PATCH 083/244] ARM: configs: tsimx6_minimal: Add FTDI and CDC-ACM support --- arch/arm/configs/tsimx6_minimal_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/configs/tsimx6_minimal_defconfig b/arch/arm/configs/tsimx6_minimal_defconfig index 805dfcd59ebd3..de744b586c12e 100644 --- a/arch/arm/configs/tsimx6_minimal_defconfig +++ b/arch/arm/configs/tsimx6_minimal_defconfig @@ -288,10 +288,13 @@ CONFIG_USB=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_MXC=y +CONFIG_USB_ACM=m CONFIG_USB_STORAGE=y CONFIG_USB_CHIPIDEA=y CONFIG_USB_CHIPIDEA_UDC=y CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_FTDI_SIO=m CONFIG_NOP_USB_XCEIV=y CONFIG_USB_MXS_PHY=y CONFIG_USB_GADGET=y From efa433e64791fbbe344daeaad06489dca042d87f Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Wed, 5 Apr 2023 13:36:00 -0700 Subject: [PATCH 084/244] ARM: configs: tsimx6ul_minimal: Add FTDI and CDC-ACM support --- arch/arm/configs/tsimx6ul_minimal_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/configs/tsimx6ul_minimal_defconfig b/arch/arm/configs/tsimx6ul_minimal_defconfig index 46582257d9a9e..6109f8da5fd13 100644 --- a/arch/arm/configs/tsimx6ul_minimal_defconfig +++ b/arch/arm/configs/tsimx6ul_minimal_defconfig @@ -249,10 +249,13 @@ CONFIG_USB=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_MXC=y +CONFIG_USB_ACM=m CONFIG_USB_STORAGE=y CONFIG_USB_CHIPIDEA=y CONFIG_USB_CHIPIDEA_UDC=y CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_FTDI_SIO=m CONFIG_NOP_USB_XCEIV=y CONFIG_USB_MXS_PHY=y CONFIG_USB_GADGET=y From d3803ccf13aed85ad52597b54bfe0a40fc261e85 Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Mon, 10 Apr 2023 12:27:18 -0700 Subject: [PATCH 085/244] drivers: watchdog: ts_wdt: Remove wdt_timeout The watchdog core already uses "timeout-sec" instead to customize the default timeout --- drivers/watchdog/ts_wdt.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/watchdog/ts_wdt.c b/drivers/watchdog/ts_wdt.c index 8a923e4f48d50..46c70c2bcf8ab 100644 --- a/drivers/watchdog/ts_wdt.c +++ b/drivers/watchdog/ts_wdt.c @@ -14,10 +14,6 @@ #define TS_DEFAULT_TIMEOUT 30 -static int wdt_timeout; -module_param(wdt_timeout, int, 0); -MODULE_PARM_DESC(wdt_timeout, "Watchdog timeout in seconds"); - static bool nowayout = WATCHDOG_NOWAYOUT; module_param(nowayout, bool, 0); MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started default=" @@ -177,7 +173,6 @@ static int ts_wdt_probe(struct i2c_client *client) wdd->timeout = TS_DEFAULT_TIMEOUT; wdd->parent = &client->dev; - watchdog_init_timeout(wdd, wdt_timeout, &client->dev); if (of_property_read_bool(client->dev.of_node, "enable-early")) enable_early = true; From d15beb1005c1bd09d9ec20e47843d6accffa107a Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Mon, 10 Apr 2023 12:28:19 -0700 Subject: [PATCH 086/244] drivers: watchdog: ts_wdt: Register after WDOG_HW_RUNNING The wdt register call must be made after WDOG_HW_RUNNING is set to take effect --- drivers/watchdog/ts_wdt.c | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/drivers/watchdog/ts_wdt.c b/drivers/watchdog/ts_wdt.c index 46c70c2bcf8ab..bd17701eeb13d 100644 --- a/drivers/watchdog/ts_wdt.c +++ b/drivers/watchdog/ts_wdt.c @@ -180,10 +180,6 @@ static int ts_wdt_probe(struct i2c_client *client) i2c_set_clientdata(client, wdd); - err = watchdog_register_device(wdd); - if (err) - return err; - /* We want this handler to be the first priority handler for reboots */ watchdog_set_restart_priority(wdd, 255); @@ -201,13 +197,8 @@ static int ts_wdt_probe(struct i2c_client *client) * userspace can take over. If not set, a single feed takes place at * this point in time. */ - if (enable_early) { - err = ts_wdt_start(wdd); - if (err) - return err; - + if (enable_early) set_bit(WDOG_HW_RUNNING, &wdd->status); - } /* * On supported platforms, this will generally be the only way to @@ -222,6 +213,10 @@ static int ts_wdt_probe(struct i2c_client *client) pm_power_off = ts_wdt_poweroff; ts_wdt_poweroff_dev = client; + err = watchdog_register_device(wdd); + if (err) + return err; + dev_info(&client->dev, "Registered embeddedTS microcontroller watchdog\n"); return 0; From 9252876d9105127577a39544f7b1346b5ca37bc1 Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Mon, 10 Apr 2023 12:34:26 -0700 Subject: [PATCH 087/244] ARM: configs: tsimx28: Enable WATCHDOG_HANDLE_BOOT_ENABLED --- arch/arm/configs/tsimx28_defconfig | 1 - arch/arm/configs/tsimx28_minimal_defconfig | 1 - 2 files changed, 2 deletions(-) diff --git a/arch/arm/configs/tsimx28_defconfig b/arch/arm/configs/tsimx28_defconfig index 4cff9f55b08bc..4000268e471aa 100644 --- a/arch/arm/configs/tsimx28_defconfig +++ b/arch/arm/configs/tsimx28_defconfig @@ -525,7 +525,6 @@ CONFIG_PPS_CLIENT_GPIO=m CONFIG_GPIO_SYSFS=y CONFIG_HWMON=m CONFIG_WATCHDOG=y -# CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED is not set CONFIG_TS_WDT_MICRO=y CONFIG_MFD_MXS_LRADC=m CONFIG_REGULATOR=y diff --git a/arch/arm/configs/tsimx28_minimal_defconfig b/arch/arm/configs/tsimx28_minimal_defconfig index 3b58eb596544c..aa3048d7860fc 100644 --- a/arch/arm/configs/tsimx28_minimal_defconfig +++ b/arch/arm/configs/tsimx28_minimal_defconfig @@ -169,7 +169,6 @@ CONFIG_PPS_CLIENT_GPIO=m CONFIG_GPIO_SYSFS=y CONFIG_HWMON=m CONFIG_WATCHDOG=y -# CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED is not set CONFIG_TS_WDT_MICRO=y CONFIG_MFD_MXS_LRADC=m CONFIG_REGULATOR=y From e4f5c6f702efe819e2a9a044aa8768e5269db8a3 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Wed, 19 Apr 2023 15:25:16 -0700 Subject: [PATCH 088/244] ARM: configs: tsimx6: Set MTD support to builtin Match other defconfigs Signed-off-by: Kris Bahnsen --- arch/arm/configs/tsimx6_defconfig | 7 ++++--- arch/arm/configs/tsimx6_minimal_defconfig | 6 +++--- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/arch/arm/configs/tsimx6_defconfig b/arch/arm/configs/tsimx6_defconfig index 1d4b80d14d2f8..de10cea633fae 100644 --- a/arch/arm/configs/tsimx6_defconfig +++ b/arch/arm/configs/tsimx6_defconfig @@ -486,9 +486,10 @@ CONFIG_EXTRA_FIRMWARE="imx/sdma/sdma-imx6q.bin" CONFIG_EXTRA_FIRMWARE_DIR="firmware" CONFIG_IMX_WEIM=y CONFIG_CONNECTOR=y -CONFIG_MTD=m +CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=m -CONFIG_MTD_BLOCK=m +CONFIG_MTD_OF_PARTS=m +CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=m CONFIG_MTD_JEDECPROBE=m CONFIG_MTD_CFI_INTELEXT=m @@ -498,7 +499,7 @@ CONFIG_MTD_DATAFLASH=m CONFIG_MTD_SST25L=m CONFIG_MTD_RAW_NAND=m CONFIG_MTD_NAND_MXC=m -CONFIG_MTD_SPI_NOR=m +CONFIG_MTD_SPI_NOR=y CONFIG_MTD_UBI=m CONFIG_MTD_UBI_FASTMAP=y CONFIG_MTD_UBI_BLOCK=y diff --git a/arch/arm/configs/tsimx6_minimal_defconfig b/arch/arm/configs/tsimx6_minimal_defconfig index de744b586c12e..7c745ab46a349 100644 --- a/arch/arm/configs/tsimx6_minimal_defconfig +++ b/arch/arm/configs/tsimx6_minimal_defconfig @@ -76,16 +76,16 @@ CONFIG_EXTRA_FIRMWARE_DIR="firmware" CONFIG_FW_LOADER_USER_HELPER=y CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y CONFIG_CONNECTOR=y -CONFIG_MTD=m +CONFIG_MTD=y # CONFIG_MTD_OF_PARTS is not set -CONFIG_MTD_BLOCK=m +CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=m CONFIG_MTD_JEDECPROBE=m CONFIG_MTD_CFI_INTELEXT=m CONFIG_MTD_CFI_AMDSTD=m CONFIG_MTD_CFI_STAA=m CONFIG_MTD_SST25L=m -CONFIG_MTD_SPI_NOR=m +CONFIG_MTD_SPI_NOR=y CONFIG_BLK_DEV_LOOP=y CONFIG_EEPROM_AT24=y CONFIG_EEPROM_AT25=y From 0035a3b6b1393464d989ab9babd551d8b880dc5d Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Wed, 10 May 2023 15:12:42 -0700 Subject: [PATCH 089/244] ARM: configs: tsimx6: Add QCA BT support Signed-off-by: Kris Bahnsen --- arch/arm/configs/tsimx6_defconfig | 1 + arch/arm/configs/tsimx6_minimal_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/configs/tsimx6_defconfig b/arch/arm/configs/tsimx6_defconfig index de10cea633fae..052167b38d150 100644 --- a/arch/arm/configs/tsimx6_defconfig +++ b/arch/arm/configs/tsimx6_defconfig @@ -462,6 +462,7 @@ CONFIG_BT_HCIUART_NOKIA=m CONFIG_BT_HCIUART_BCSP=y CONFIG_BT_HCIUART_ATH3K=y CONFIG_BT_HCIUART_LL=y +CONFIG_BT_HCIUART_QCA=y CONFIG_CFG80211=m # CONFIG_CFG80211_DEFAULT_PS is not set CONFIG_MAC80211=m diff --git a/arch/arm/configs/tsimx6_minimal_defconfig b/arch/arm/configs/tsimx6_minimal_defconfig index 7c745ab46a349..82db0c41666b2 100644 --- a/arch/arm/configs/tsimx6_minimal_defconfig +++ b/arch/arm/configs/tsimx6_minimal_defconfig @@ -58,6 +58,7 @@ CONFIG_CAN_FLEXCAN=m CONFIG_BT=m CONFIG_BT_HCIUART=m CONFIG_BT_HCIUART_LL=y +CONFIG_BT_HCIUART_QCA=y CONFIG_CFG80211=m # CONFIG_CFG80211_DEFAULT_PS is not set CONFIG_CFG80211_WEXT=y From f2eccf64eb43af2dfdf9ad3e0847a9c4348e9c74 Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Wed, 10 May 2023 17:47:40 -0700 Subject: [PATCH 090/244] tests: ts_check_configs: Require CONFIG_BINFMT_MISC=y This is needed for most recent Debian/Ubuntu distributions to start up systemd without error. Most ditributions start a systemd service to add any binfmts to the kernel on startup. --- tests/ts_check_configs/full_graphics_config_requirements | 3 ++- tests/ts_check_configs/full_headless_config_requirements | 3 ++- tests/ts_check_configs/min_graphics_config_requirements | 3 ++- tests/ts_check_configs/min_headless_config_requirements | 3 ++- 4 files changed, 8 insertions(+), 4 deletions(-) diff --git a/tests/ts_check_configs/full_graphics_config_requirements b/tests/ts_check_configs/full_graphics_config_requirements index 348f9e280f842..61aed7d4bba24 100644 --- a/tests/ts_check_configs/full_graphics_config_requirements +++ b/tests/ts_check_configs/full_graphics_config_requirements @@ -22,10 +22,11 @@ CONFIG_INOTIFY_USER=x CONFIG_SIGNALFD=x CONFIG_TIMERFD=x CONFIG_EPOLL=x -CONFIG_UNIX =x +CONFIG_UNIX=x CONFIG_SYSFS=x CONFIG_PROC_FS=x CONFIG_FHANDLE=x +CONFIG_BINFMT_MISC=y ######## Systemd Optional: #CONFIG_DMIID=x SMBIOS thing, we dont need thsi diff --git a/tests/ts_check_configs/full_headless_config_requirements b/tests/ts_check_configs/full_headless_config_requirements index b81b3dd1e0f30..8b49dce67e3c8 100644 --- a/tests/ts_check_configs/full_headless_config_requirements +++ b/tests/ts_check_configs/full_headless_config_requirements @@ -22,10 +22,11 @@ CONFIG_INOTIFY_USER=x CONFIG_SIGNALFD=x CONFIG_TIMERFD=x CONFIG_EPOLL=x -CONFIG_UNIX =x +CONFIG_UNIX=x CONFIG_SYSFS=x CONFIG_PROC_FS=x CONFIG_FHANDLE=x +CONFIG_BINFMT_MISC=y ######## Systemd Optional: #CONFIG_DMIID=x SMBIOS thing, we dont need thsi diff --git a/tests/ts_check_configs/min_graphics_config_requirements b/tests/ts_check_configs/min_graphics_config_requirements index 9cc9e9991ac80..39c3fe7b94c35 100644 --- a/tests/ts_check_configs/min_graphics_config_requirements +++ b/tests/ts_check_configs/min_graphics_config_requirements @@ -22,10 +22,11 @@ CONFIG_INOTIFY_USER=x CONFIG_SIGNALFD=x CONFIG_TIMERFD=x CONFIG_EPOLL=x -CONFIG_UNIX =x +CONFIG_UNIX=x CONFIG_SYSFS=x CONFIG_PROC_FS=x CONFIG_FHANDLE=x +CONFIG_BINFMT_MISC=y ######## NFS root requirements: CONFIG_ROOT_NFS=y diff --git a/tests/ts_check_configs/min_headless_config_requirements b/tests/ts_check_configs/min_headless_config_requirements index ca133782a6c8f..26f6662e1bff4 100644 --- a/tests/ts_check_configs/min_headless_config_requirements +++ b/tests/ts_check_configs/min_headless_config_requirements @@ -22,10 +22,11 @@ CONFIG_INOTIFY_USER=x CONFIG_SIGNALFD=x CONFIG_TIMERFD=x CONFIG_EPOLL=x -CONFIG_UNIX =x +CONFIG_UNIX=x CONFIG_SYSFS=x CONFIG_PROC_FS=x CONFIG_FHANDLE=x +CONFIG_BINFMT_MISC=y ######## NFS root requirements: CONFIG_ROOT_NFS=y From 08cf9ecbe6841df4cda838ffec3c7ae52a370b39 Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Wed, 10 May 2023 17:49:58 -0700 Subject: [PATCH 091/244] ARM: configs: tsimx6ul: add CONFIG_BINFMT_MISC=y Updated for new requirement in our *_config_requirements --- arch/arm/configs/tsimx6ul_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/configs/tsimx6ul_defconfig b/arch/arm/configs/tsimx6ul_defconfig index e2ce10518a8c8..50ce0a49a9b1d 100644 --- a/arch/arm/configs/tsimx6ul_defconfig +++ b/arch/arm/configs/tsimx6ul_defconfig @@ -67,7 +67,7 @@ CONFIG_MODVERSIONS=y CONFIG_MODULE_SRCVERSION_ALL=y CONFIG_BLK_DEV_BSGLIB=y CONFIG_BLK_DEV_THROTTLING=y -CONFIG_BINFMT_MISC=m +CONFIG_BINFMT_MISC=y CONFIG_CMA=y CONFIG_NET=y CONFIG_PACKET=y From 6e33d4e2c2be3e876b44685a2a924889202eeab3 Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Thu, 11 May 2023 08:27:21 -0700 Subject: [PATCH 092/244] ARM: configs: tsa38x_minimal: add CONFIG_BINFMT_MISC=y Updated for new requirement in our *_config_requirements --- arch/arm/configs/tsa38x_minimal_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/tsa38x_minimal_defconfig b/arch/arm/configs/tsa38x_minimal_defconfig index f6714eff84f78..4ce73ef7c02fe 100644 --- a/arch/arm/configs/tsa38x_minimal_defconfig +++ b/arch/arm/configs/tsa38x_minimal_defconfig @@ -31,6 +31,7 @@ CONFIG_NEON=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_MQ_IOSCHED_KYBER is not set +CONFIG_BINFMT_MISC=y # CONFIG_COMPACTION is not set CONFIG_NET=y CONFIG_PACKET=y From 0002c05a62937abafa75feced1fbde7210cb2561 Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Thu, 11 May 2023 08:27:53 -0700 Subject: [PATCH 093/244] ARM: configs: tsimx28: add CONFIG_BINFMT_MISC=y Updated for new requirement in our *_config_requirements --- arch/arm/configs/tsimx28_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/tsimx28_defconfig b/arch/arm/configs/tsimx28_defconfig index 4000268e471aa..9f8618338cb51 100644 --- a/arch/arm/configs/tsimx28_defconfig +++ b/arch/arm/configs/tsimx28_defconfig @@ -41,6 +41,7 @@ CONFIG_MODULE_FORCE_UNLOAD=y CONFIG_MODVERSIONS=y CONFIG_UNUSED_SYMBOLS=y CONFIG_BLK_DEV_INTEGRITY=y +CONFIG_BINFMT_MISC=y CONFIG_CLEANCACHE=y CONFIG_NET=y CONFIG_PACKET=y From 0ca7e705934296910970778f1c16d59eec4316ab Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Thu, 11 May 2023 08:28:13 -0700 Subject: [PATCH 094/244] ARM: configs: tsimx28_minimal: add CONFIG_BINFMT_MISC=y Updated for new requirement in our *_config_requirements --- arch/arm/configs/tsimx28_minimal_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/tsimx28_minimal_defconfig b/arch/arm/configs/tsimx28_minimal_defconfig index aa3048d7860fc..ef01f92154fe7 100644 --- a/arch/arm/configs/tsimx28_minimal_defconfig +++ b/arch/arm/configs/tsimx28_minimal_defconfig @@ -26,6 +26,7 @@ CONFIG_MODULE_FORCE_UNLOAD=y CONFIG_MODVERSIONS=y CONFIG_UNUSED_SYMBOLS=y CONFIG_BLK_DEV_INTEGRITY=y +CONFIG_BINFMT_MISC=y CONFIG_CLEANCACHE=y CONFIG_NET=y CONFIG_PACKET=y From 9cbeba81feed9f1df72c4690a228a80942e5d00c Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Thu, 11 May 2023 08:28:28 -0700 Subject: [PATCH 095/244] ARM: configs: tsimx6: add CONFIG_BINFMT_MISC=y Updated for new requirement in our *_config_requirements --- arch/arm/configs/tsimx6_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/configs/tsimx6_defconfig b/arch/arm/configs/tsimx6_defconfig index 052167b38d150..0eae2dd5da247 100644 --- a/arch/arm/configs/tsimx6_defconfig +++ b/arch/arm/configs/tsimx6_defconfig @@ -67,7 +67,7 @@ CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODVERSIONS=y CONFIG_MODULE_SRCVERSION_ALL=y -CONFIG_BINFMT_MISC=m +CONFIG_BINFMT_MISC=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_PACKET_DIAG=m From e02a12bdbcabec2037f595123048b53c84e8f345 Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Thu, 11 May 2023 08:28:47 -0700 Subject: [PATCH 096/244] ARM: configs: tsimx6_minimal: add CONFIG_BINFMT_MISC=y Updated for new requirement in our *_config_requirements --- arch/arm/configs/tsimx6_minimal_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/tsimx6_minimal_defconfig b/arch/arm/configs/tsimx6_minimal_defconfig index 82db0c41666b2..54dfb5aaae97e 100644 --- a/arch/arm/configs/tsimx6_minimal_defconfig +++ b/arch/arm/configs/tsimx6_minimal_defconfig @@ -46,6 +46,7 @@ CONFIG_MODVERSIONS=y CONFIG_MODULE_SRCVERSION_ALL=y # CONFIG_BLK_DEV_BSG is not set # CONFIG_MQ_IOSCHED_KYBER is not set +CONFIG_BINFMT_MISC=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y From eb107af70cee52138948af46f73ccf56942de997 Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Thu, 11 May 2023 08:29:04 -0700 Subject: [PATCH 097/244] ARM: configs: tsimx6ul_minimal: add CONFIG_BINFMT_MISC=y Updated for new requirement in our *_config_requirements --- arch/arm/configs/tsimx6ul_minimal_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/tsimx6ul_minimal_defconfig b/arch/arm/configs/tsimx6ul_minimal_defconfig index 6109f8da5fd13..53c6c40e2f1ec 100644 --- a/arch/arm/configs/tsimx6ul_minimal_defconfig +++ b/arch/arm/configs/tsimx6ul_minimal_defconfig @@ -46,6 +46,7 @@ CONFIG_MODVERSIONS=y CONFIG_MODULE_SRCVERSION_ALL=y # CONFIG_BLK_DEV_BSG is not set # CONFIG_MQ_IOSCHED_KYBER is not set +CONFIG_BINFMT_MISC=y # CONFIG_COREDUMP is not set CONFIG_CMA=y CONFIG_NET=y From 9d19493bb91b6a504dec3497cb0186bbe7804293 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Thu, 11 May 2023 15:12:37 -0700 Subject: [PATCH 098/244] ARM: configs: tsimx6_minimal: Remove sysfs FW helper Signed-off-by: Kris Bahnsen --- arch/arm/configs/tsimx6_minimal_defconfig | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/configs/tsimx6_minimal_defconfig b/arch/arm/configs/tsimx6_minimal_defconfig index 54dfb5aaae97e..f7a7293d01056 100644 --- a/arch/arm/configs/tsimx6_minimal_defconfig +++ b/arch/arm/configs/tsimx6_minimal_defconfig @@ -75,8 +75,6 @@ CONFIG_DEVTMPFS_MOUNT=y # CONFIG_STANDALONE is not set CONFIG_EXTRA_FIRMWARE="imx/sdma/sdma-imx6q.bin" CONFIG_EXTRA_FIRMWARE_DIR="firmware" -CONFIG_FW_LOADER_USER_HELPER=y -CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y CONFIG_CONNECTOR=y CONFIG_MTD=y # CONFIG_MTD_OF_PARTS is not set From 2aa4078b8660a7ac2c00f23ecf7638ebfbaa529e Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Thu, 11 May 2023 15:12:59 -0700 Subject: [PATCH 099/244] ARM: configs: tsimx6ul_minimal: Remove sysfs FW helper Signed-off-by: Kris Bahnsen --- arch/arm/configs/tsimx6ul_minimal_defconfig | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/configs/tsimx6ul_minimal_defconfig b/arch/arm/configs/tsimx6ul_minimal_defconfig index 53c6c40e2f1ec..8b593239ee4c1 100644 --- a/arch/arm/configs/tsimx6ul_minimal_defconfig +++ b/arch/arm/configs/tsimx6ul_minimal_defconfig @@ -73,8 +73,6 @@ CONFIG_DEVTMPFS_MOUNT=y # CONFIG_STANDALONE is not set CONFIG_EXTRA_FIRMWARE="imx/sdma/sdma-imx6q.bin" CONFIG_EXTRA_FIRMWARE_DIR="firmware" -CONFIG_FW_LOADER_USER_HELPER=y -CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y # CONFIG_ALLOW_DEV_COREDUMP is not set CONFIG_IMX_WEIM=y CONFIG_TSPC104=y From a36cb92b9b941e97a1a4598c53dcdd780fd1d356 Mon Sep 17 00:00:00 2001 From: "Lionel D. Hummel" Date: Thu, 11 May 2023 17:49:53 -0700 Subject: [PATCH 100/244] ARM: configs: tsimx6ul_minimal: Add SYSFS_TRIGGER --- arch/arm/configs/tsimx6ul_minimal_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/tsimx6ul_minimal_defconfig b/arch/arm/configs/tsimx6ul_minimal_defconfig index 8b593239ee4c1..f367455489da7 100644 --- a/arch/arm/configs/tsimx6ul_minimal_defconfig +++ b/arch/arm/configs/tsimx6ul_minimal_defconfig @@ -292,6 +292,7 @@ CONFIG_IIO_ST_LSM6DSX=m CONFIG_SENSORS_ISL29018=y CONFIG_MAG3110=y CONFIG_IIO_ST_MAGN_3AXIS=m +CONFIG_IIO_SYSFS_TRIGGER=m CONFIG_MPL3115=y CONFIG_TS_SUPERVISOR_TEMP=y CONFIG_PWM=y From d9357690fac54eec4e76c0dfa176fee70a493a06 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Fri, 12 May 2023 10:53:47 -0700 Subject: [PATCH 101/244] ARM: configs: tsa38x_minimal: add PTP support Signed-off-by: Kris Bahnsen --- arch/arm/configs/tsa38x_minimal_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/tsa38x_minimal_defconfig b/arch/arm/configs/tsa38x_minimal_defconfig index 4ce73ef7c02fe..7939e894e43a4 100644 --- a/arch/arm/configs/tsa38x_minimal_defconfig +++ b/arch/arm/configs/tsa38x_minimal_defconfig @@ -196,6 +196,7 @@ CONFIG_SPI_OCORES=m CONFIG_SPI_ORION=y CONFIG_SPI_MUX=y CONFIG_SPI_SPIDEV=m +CONFIG_PTP_1588_CLOCK=m CONFIG_GPIO_SYSFS=y CONFIG_GPIO_PCA953X=y CONFIG_GPIO_TS7800V2=y From 1dada4c7aa264f09d959d08facdeece3f9b619ed Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Fri, 12 May 2023 10:54:28 -0700 Subject: [PATCH 102/244] ARM: configs: tsimx6: add PPS and PTP to both configs Signed-off-by: Kris Bahnsen --- arch/arm/configs/tsimx6_defconfig | 1 + arch/arm/configs/tsimx6_minimal_defconfig | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/configs/tsimx6_defconfig b/arch/arm/configs/tsimx6_defconfig index 0eae2dd5da247..6a6cf500b38d9 100644 --- a/arch/arm/configs/tsimx6_defconfig +++ b/arch/arm/configs/tsimx6_defconfig @@ -716,6 +716,7 @@ CONFIG_SPI_FSL_QUADSPI=y CONFIG_SPI_GPIO=y CONFIG_SPI_IMX=y CONFIG_SPI_SPIDEV=m +CONFIG_PPS_CLIENT_GPIO=m CONFIG_PINCTRL_IMX8MM=y CONFIG_PINCTRL_IMX8MN=y CONFIG_PINCTRL_IMX8MP=y diff --git a/arch/arm/configs/tsimx6_minimal_defconfig b/arch/arm/configs/tsimx6_minimal_defconfig index f7a7293d01056..8e2a7ce877f5f 100644 --- a/arch/arm/configs/tsimx6_minimal_defconfig +++ b/arch/arm/configs/tsimx6_minimal_defconfig @@ -223,7 +223,8 @@ CONFIG_SPI=y CONFIG_SPI_GPIO=y CONFIG_SPI_IMX=y CONFIG_SPI_SPIDEV=m -# CONFIG_PTP_1588_CLOCK is not set +CONFIG_PPS_CLIENT_GPIO=m +CONFIG_PTP_1588_CLOCK=m CONFIG_PINCTRL_IMX8MM=y CONFIG_PINCTRL_IMX8MN=y CONFIG_PINCTRL_IMX8MP=y From cb879d9b91c1c77b73be26575ca60d81b8c8d74b Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Fri, 12 May 2023 10:55:06 -0700 Subject: [PATCH 103/244] ARM: configs: tsimx6ul_minimal: add PTP support Signed-off-by: Kris Bahnsen --- arch/arm/configs/tsimx6ul_minimal_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/configs/tsimx6ul_minimal_defconfig b/arch/arm/configs/tsimx6ul_minimal_defconfig index f367455489da7..bb5c1018a02d1 100644 --- a/arch/arm/configs/tsimx6ul_minimal_defconfig +++ b/arch/arm/configs/tsimx6ul_minimal_defconfig @@ -204,7 +204,7 @@ CONFIG_SPI_GPIO=y CONFIG_SPI_IMX=y CONFIG_SPI_OCORES=m CONFIG_SPI_SPIDEV=m -# CONFIG_PTP_1588_CLOCK is not set +CONFIG_PTP_1588_CLOCK=m CONFIG_GPIO_SYSFS=y CONFIG_GPIO_MXC=y CONFIG_GPIO_TS71XXWEIM=y From d055f50033e3e777644154359ce857a528ea6858 Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Mon, 24 Jul 2023 13:20:55 -0700 Subject: [PATCH 104/244] ARM: dts: imx6: TS-4900 set phy skew Set data to minimum, and clock to maximum. Without this the phy does not link at 1000M on the solo core. --- arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900.dtsi | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900.dtsi index b7c1ed1b5f85f..f61959755e599 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900.dtsi @@ -121,6 +121,27 @@ fsl,err006687-workaround-present; phy-mode = "rgmii"; status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + eth_phy: ethernet-phy@7 { + reg = <0x7>; + txen-skew-ps = <0>; + txc-skew-ps = <3000>; + rxdv-skew-ps = <0>; + rxc-skew-ps = <3000>; + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + txd0-skew-ps = <0>; + txd1-skew-ps = <0>; + txd2-skew-ps = <0>; + txd3-skew-ps = <0>; + }; + }; }; &gpio1 { From d552c8b43066107dcedaa3586e3caeeba79a504a Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Mon, 24 Jul 2023 15:51:25 -0700 Subject: [PATCH 105/244] ARM: configs: tsimx6ul: Add CONFIG_I2C_OCORES=m Needed to support the mikrobus interface on the TS-7250-V3. --- arch/arm/configs/tsimx6ul_defconfig | 1 + arch/arm/configs/tsimx6ul_minimal_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/configs/tsimx6ul_defconfig b/arch/arm/configs/tsimx6ul_defconfig index 50ce0a49a9b1d..3f2fdcbcacf19 100644 --- a/arch/arm/configs/tsimx6ul_defconfig +++ b/arch/arm/configs/tsimx6ul_defconfig @@ -547,6 +547,7 @@ CONFIG_I2C_ALGOPCF=m CONFIG_I2C_ALGOPCA=m CONFIG_I2C_GPIO=y CONFIG_I2C_IMX=y +CONFIG_I2C_OCORES=m CONFIG_SPI=y CONFIG_SPI_FSL_QUADSPI=y CONFIG_SPI_GPIO=y diff --git a/arch/arm/configs/tsimx6ul_minimal_defconfig b/arch/arm/configs/tsimx6ul_minimal_defconfig index bb5c1018a02d1..376c94a1a7658 100644 --- a/arch/arm/configs/tsimx6ul_minimal_defconfig +++ b/arch/arm/configs/tsimx6ul_minimal_defconfig @@ -199,6 +199,7 @@ CONFIG_I2C_ALGOPCF=m CONFIG_I2C_ALGOPCA=m CONFIG_I2C_GPIO=y CONFIG_I2C_IMX=y +CONFIG_I2C_OCORES=m CONFIG_SPI=y CONFIG_SPI_GPIO=y CONFIG_SPI_IMX=y From 8b6fa54111e620f21b763ec6bc0773f3825540f6 Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Wed, 2 Aug 2023 13:45:36 -0700 Subject: [PATCH 106/244] ARM: dts: imx6qdl-ts7990: Add support for REV E This revision removes the mma8451 and replaces it with both the ST Micro IIS2MDCTR magnetometer and ST Micro ISM330DLCTR IMU --- arch/arm/boot/dts/nxp/imx/imx6qdl-ts7990.dtsi | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7990.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7990.dtsi index 547cbd07b0f38..792705fa7abaf 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7990.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7990.dtsi @@ -287,6 +287,15 @@ status = "disabled"; }; + /* Only present on REV E and above */ + magnet: magnetometer@1e { + compatible = "st,lis2mdl"; + reg = <0x1e>; + st,drdy-int-pin = <1>; + interrupt-parent = <&gpio2>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; + }; + m41t00s: rtc@68 { compatible = "m41t00"; reg = <0x68>; @@ -303,6 +312,7 @@ VDDD-supply = <®_1v2>; }; + /* Only present on REV D and below */ mma8451: accelerometer@1c { compatible = "fsl,mma8451"; reg = <0x1c>; @@ -314,6 +324,14 @@ /* INT2 is connected to CPU but is unused */ }; + /* Only present on REV E and above */ + ism330: gyro@6a { + compatible = "st,ism330dlc"; + reg = <0x6a>; + interrupt-parent = <&gpio3>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH>; + }; + gpio8: gpio@28 { compatible = "technologic,ts7970-gpio"; reg = <0x28>; @@ -457,6 +475,8 @@ MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x17059 /* ACCEL_INT */ MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x17059 /* ACCEL_2_INT */ MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x88 /* TOUCH_RESET */ + MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x17059 /* MAGNET_IRQ */ + MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x17059 /* GYRO_IRQ */ >; }; From cdbee9f0108895d500488e36aa9fcdb0c50307d8 Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Wed, 2 Aug 2023 13:48:04 -0700 Subject: [PATCH 107/244] ARM: configs: tsimx6_minimal: add ST LSM6DSX and MAGN_3AXIS The TS-7990 REV E now includes the ST Micro IIS2MDCTR magnetometer and ST Micro ISM330DLCTR IMU --- arch/arm/configs/tsimx6_minimal_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/configs/tsimx6_minimal_defconfig b/arch/arm/configs/tsimx6_minimal_defconfig index 8e2a7ce877f5f..d074e9b8d742a 100644 --- a/arch/arm/configs/tsimx6_minimal_defconfig +++ b/arch/arm/configs/tsimx6_minimal_defconfig @@ -328,8 +328,10 @@ CONFIG_CLK_IMX8MQ=y CONFIG_IMX_GPCV2_PM_DOMAINS=y CONFIG_IIO=y CONFIG_MMA8452=y +CONFIG_IIO_ST_LSM6DSX=m CONFIG_SENSORS_ISL29018=y CONFIG_MAG3110=y +CONFIG_IIO_ST_MAGN_3AXIS=m CONFIG_MPL3115=y CONFIG_PWM=y CONFIG_PWM_IMX27=y From 9108778207b1f062a8c6823bddfef97d82f453a4 Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Fri, 11 Aug 2023 08:39:53 -0700 Subject: [PATCH 108/244] ARM: dts: imx6: TS-7970: Set vmmc-supply as the enable, and specify vqmmc as 1.8v. Without this the older Rev. D and below with the TI wl1271 cannot cycle the interface. This allows operation with either the Silex sdmac+ or TI wl1271. --- arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi | 21 +++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi index 5de0c8cf786c9..99186402b5961 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi @@ -67,6 +67,14 @@ regulator-always-on; }; + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + reg_can1_3v3: regulator-can1-en { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -96,11 +104,11 @@ enable-active-high; }; - reg_wlan_vqmmc: regulator-wlan-vqmmc { + reg_wlan_vmmc: regulator-wlan-vmmc { compatible = "regulator-fixed"; - regulator-name = "WLAN_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; + regulator-name = "WLAN_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; gpio = <&gpio8 14 GPIO_ACTIVE_HIGH>; startup-delay-us = <70000>; enable-active-high; @@ -253,6 +261,7 @@ reg = <0x6f>; btse-minutes = <1>; isil,battery-trip-levels-microvolt = <2550000>, <2250000>; + #clock-cells = <0>; }; isl12022_sram: eeprom@57 { @@ -650,8 +659,8 @@ pinctrl-0 = <&pinctrl_usdhc1>; pinctrl-1 = <&pinctrl_usdhc1_100mhz>; pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - vmmc-supply = <®_3v3>; - vqmmc-supply = <®_wlan_vqmmc>; + vmmc-supply = <®_wlan_vmmc>; + vqmmc-supply = <®_1v8>; bus-width = <4>; fsl,tuning-step = <2>; cap-sdio-irq; From 6fc0d8dca7886d6f0210e5921a4356402783a938 Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Tue, 29 Aug 2023 17:35:05 -0700 Subject: [PATCH 109/244] ARM: configs: tsimx6ul: Set i2c gpio drivers to =m Set this to a module to address some platforms loading i2c gpio controllers before fpga gpio I/O which makes the numbering not match the documentation or older kernels. --- arch/arm/configs/tsimx6ul_defconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/configs/tsimx6ul_defconfig b/arch/arm/configs/tsimx6ul_defconfig index 3f2fdcbcacf19..50481882d9666 100644 --- a/arch/arm/configs/tsimx6ul_defconfig +++ b/arch/arm/configs/tsimx6ul_defconfig @@ -560,8 +560,8 @@ CONFIG_GPIO_SYSFS=y CONFIG_GPIO_MXC=y CONFIG_GPIO_SIOX=m CONFIG_GPIO_TS71XXWEIM=y -CONFIG_GPIO_PCA953X=y -CONFIG_GPIO_PCF857X=y +CONFIG_GPIO_PCA953X=m +CONFIG_GPIO_PCF857X=m CONFIG_GPIO_TS4900=y CONFIG_GPIO_74X164=m CONFIG_POWER_RESET=y From 96f8db0df0ed934c858590ac68ef61a6d9fc1042 Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Fri, 24 Mar 2023 08:52:22 -0700 Subject: [PATCH 110/244] irqchip: irq-ts71xxweim: Remove global private data --- drivers/irqchip/irq-ts71xxweim.c | 57 ++++++++++++++++++++------------ 1 file changed, 36 insertions(+), 21 deletions(-) diff --git a/drivers/irqchip/irq-ts71xxweim.c b/drivers/irqchip/irq-ts71xxweim.c index de96ddc219636..688055f472205 100644 --- a/drivers/irqchip/irq-ts71xxweim.c +++ b/drivers/irqchip/irq-ts71xxweim.c @@ -11,12 +11,16 @@ #define TSWEIM_IRQ_MASK 0x48 #define TSWEIM_NUM_FPGA_IRQ 32 -static struct tsweim_intc_priv { +struct tsweim_intc { void __iomem *syscon; struct irq_domain *irqdomain; - int irq; u32 mask; -} priv; +}; + +static struct tsweim_intc *irq_data_to_priv(struct irq_data *data) +{ + return data->domain->host_data; +} static const struct of_device_id tsweim_intc_of_match_table[] = { {.compatible = "technologic,ts71xxweim-intc", }, @@ -26,31 +30,36 @@ MODULE_DEVICE_TABLE(of, tsweim_intc_of_match_table); static void tsweim_intc_mask(struct irq_data *d) { - priv.mask = readl(priv.syscon + TSWEIM_IRQ_MASK) & ~BIT(d->hwirq); - writel(priv.mask, priv.syscon + TSWEIM_IRQ_MASK); + struct tsweim_intc *priv = irq_data_to_priv(d); + + priv->mask = readl(priv->syscon + TSWEIM_IRQ_MASK) & ~BIT(d->hwirq); + writel(priv->mask, priv->syscon + TSWEIM_IRQ_MASK); } static void tsweim_intc_unmask(struct irq_data *d) { - priv.mask = readl(priv.syscon + TSWEIM_IRQ_MASK) | BIT(d->hwirq); - writel(priv.mask, priv.syscon + TSWEIM_IRQ_MASK); + struct tsweim_intc *priv = irq_data_to_priv(d); + + priv->mask = readl(priv->syscon + TSWEIM_IRQ_MASK) | BIT(d->hwirq); + writel(priv->mask, priv->syscon + TSWEIM_IRQ_MASK); } static void tsweim_irq_handler(struct irq_desc *desc) { struct irq_chip *chip = irq_desc_get_chip(desc); + struct tsweim_intc *priv = irq_desc_get_handler_data(desc); unsigned int irq; unsigned int status; chained_irq_enter(chip, desc); while ((status = - (priv.mask & readl(priv.syscon + TSWEIM_IRQ_STATUS)))) { + (priv->mask & readl(priv->syscon + TSWEIM_IRQ_STATUS)))) { irq = 0; do { if (status & 1) { generic_handle_irq(irq_linear_revmap( - priv.irqdomain, irq)); + priv->irqdomain, irq)); } status >>= 1; irq++; @@ -87,9 +96,14 @@ static int tsweim_intc_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; const struct of_device_id *match; struct device_node *np = pdev->dev.of_node; + struct tsweim_intc *priv; void __iomem *membase; struct resource *res = 0; + priv = devm_kzalloc(dev, sizeof(struct tsweim_intc), GFP_KERNEL); + if (!priv) + return -ENOMEM; + match = of_match_device(tsweim_intc_of_match_table, dev); if (!match) return -EINVAL; @@ -113,37 +127,38 @@ static int tsweim_intc_probe(struct platform_device *pdev) return -EFAULT; } - priv.irq = res->start; - priv.syscon = membase; + priv->syscon = membase; - priv.irqdomain = irq_domain_add_linear( - np, TSWEIM_NUM_FPGA_IRQ, &tsweim_intc_irqdomain_ops, &priv); + priv->irqdomain = irq_domain_add_linear( + np, TSWEIM_NUM_FPGA_IRQ, &tsweim_intc_irqdomain_ops, priv); - if (!priv.irqdomain) { + if (!priv->irqdomain) { pr_err("%s: unable to add irq domain\n", np->name); return -ENOMEM; } - irq_set_handler_data(priv.irq, &priv); - irq_set_chained_handler(priv.irq, tsweim_irq_handler); + irq_set_handler_data(res->start, priv); + irq_set_chained_handler(res->start, tsweim_irq_handler); - platform_set_drvdata(pdev, &priv); + platform_set_drvdata(pdev, priv); return 0; } static int tsweim_intc_remove(struct platform_device *pdev) { - if (priv.irqdomain) { + struct tsweim_intc *priv = dev_get_platdata(&pdev->dev); + + if (priv->irqdomain) { int i, irq; for (i = 0; i < TSWEIM_NUM_FPGA_IRQ; i++) { - irq = irq_find_mapping(priv.irqdomain, i); + irq = irq_find_mapping(priv->irqdomain, i); if (irq > 0) irq_dispose_mapping(irq); } - irq_domain_remove(priv.irqdomain); - priv.irqdomain = NULL; + irq_domain_remove(priv->irqdomain); + priv->irqdomain = NULL; } return 0; From 695f11333c3040e85ad88aa4414a196e36acf13a Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Fri, 24 Mar 2023 09:20:56 -0700 Subject: [PATCH 111/244] irqchip: irq-ts71xxweim: refactor probe Removed manual of_match_device since the pdev already has this of_node mapped. Use devm_platform_ioremap_resource instead of manually getting the resource and mapping it --- drivers/irqchip/irq-ts71xxweim.c | 50 ++++++++++---------------------- 1 file changed, 16 insertions(+), 34 deletions(-) diff --git a/drivers/irqchip/irq-ts71xxweim.c b/drivers/irqchip/irq-ts71xxweim.c index 688055f472205..92c20f852ef6e 100644 --- a/drivers/irqchip/irq-ts71xxweim.c +++ b/drivers/irqchip/irq-ts71xxweim.c @@ -22,12 +22,6 @@ static struct tsweim_intc *irq_data_to_priv(struct irq_data *data) return data->domain->host_data; } -static const struct of_device_id tsweim_intc_of_match_table[] = { - {.compatible = "technologic,ts71xxweim-intc", }, - {}, -}; -MODULE_DEVICE_TABLE(of, tsweim_intc_of_match_table); - static void tsweim_intc_mask(struct irq_data *d) { struct tsweim_intc *priv = irq_data_to_priv(d); @@ -94,51 +88,33 @@ static const struct irq_domain_ops tsweim_intc_irqdomain_ops = { static int tsweim_intc_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; - const struct of_device_id *match; - struct device_node *np = pdev->dev.of_node; struct tsweim_intc *priv; - void __iomem *membase; - struct resource *res = 0; + struct resource *irq = 0; priv = devm_kzalloc(dev, sizeof(struct tsweim_intc), GFP_KERNEL); if (!priv) return -ENOMEM; - match = of_match_device(tsweim_intc_of_match_table, dev); - if (!match) - return -EINVAL; - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - - if (res == NULL) { - pr_err("Can't get device address\n"); - return -EFAULT; - } - - membase = devm_ioremap(&pdev->dev, res->start, resource_size(res)); - if (IS_ERR(membase)) { - pr_err("Could not map resource\n"); - return -ENOMEM; - } + priv->syscon = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->syscon)) + return PTR_ERR(priv->syscon); - res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); - if (res == NULL) { + irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (irq == NULL) { pr_err("Can't get interrupt\n"); return -EFAULT; } - priv->syscon = membase; - priv->irqdomain = irq_domain_add_linear( - np, TSWEIM_NUM_FPGA_IRQ, &tsweim_intc_irqdomain_ops, priv); + dev->of_node, TSWEIM_NUM_FPGA_IRQ, &tsweim_intc_irqdomain_ops, priv); if (!priv->irqdomain) { - pr_err("%s: unable to add irq domain\n", np->name); + pr_err("unable to add irq domain\n"); return -ENOMEM; } - irq_set_handler_data(res->start, priv); - irq_set_chained_handler(res->start, tsweim_irq_handler); + irq_set_handler_data(irq->start, priv); + irq_set_chained_handler(irq->start, tsweim_irq_handler); platform_set_drvdata(pdev, priv); @@ -164,6 +140,12 @@ static int tsweim_intc_remove(struct platform_device *pdev) return 0; } +static const struct of_device_id tsweim_intc_of_match_table[] = { + {.compatible = "technologic,ts71xxweim-intc", }, + {}, +}; +MODULE_DEVICE_TABLE(of, tsweim_intc_of_match_table); + static struct platform_driver tsweim_intc_driver = { .driver = { .name = "tsweim-intc", From ccbbed303676b8c4715d0d4911475e88c87d2651 Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Fri, 24 Mar 2023 09:52:19 -0700 Subject: [PATCH 112/244] irqchip: irq-ts71xxweim: Add polarity support --- drivers/irqchip/irq-ts71xxweim.c | 48 +++++++++++++++++++++++++------- 1 file changed, 38 insertions(+), 10 deletions(-) diff --git a/drivers/irqchip/irq-ts71xxweim.c b/drivers/irqchip/irq-ts71xxweim.c index 92c20f852ef6e..a08ac179ae78e 100644 --- a/drivers/irqchip/irq-ts71xxweim.c +++ b/drivers/irqchip/irq-ts71xxweim.c @@ -8,12 +8,14 @@ #include #define TSWEIM_IRQ_STATUS 0x24 +#define TSWEIM_IRQ_POLARITY 0x28 #define TSWEIM_IRQ_MASK 0x48 #define TSWEIM_NUM_FPGA_IRQ 32 struct tsweim_intc { void __iomem *syscon; struct irq_domain *irqdomain; + struct irq_chip chip; u32 mask; }; @@ -38,6 +40,28 @@ static void tsweim_intc_unmask(struct irq_data *d) writel(priv->mask, priv->syscon + TSWEIM_IRQ_MASK); } +static int tsweim_intc_set_type(struct irq_data *d, unsigned int flow_type) +{ + struct tsweim_intc *priv = irq_data_to_priv(d); + uint32_t polarity = readl(priv->syscon + TSWEIM_IRQ_POLARITY); + uint32_t bit = BIT_MASK(d->hwirq); + + switch (flow_type) { + case IRQ_TYPE_LEVEL_LOW: + polarity |= bit; + break; + case IRQ_TYPE_LEVEL_HIGH: + polarity &= ~bit; + break; + default: + return -EINVAL; + } + + writel(polarity, priv->syscon + TSWEIM_IRQ_POLARITY); + + return 0; +} + static void tsweim_irq_handler(struct irq_desc *desc) { struct irq_chip *chip = irq_desc_get_chip(desc); @@ -63,18 +87,12 @@ static void tsweim_irq_handler(struct irq_desc *desc) chained_irq_exit(chip, desc); } -static struct irq_chip tsweim_irq_chip = { - .name = "tsweim_intc", - .irq_mask = tsweim_intc_mask, - .irq_unmask = tsweim_intc_unmask, -}; - static int tsweim_intc_irqdomain_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hwirq) { - irq_set_chip_and_handler(irq, &tsweim_irq_chip, - handle_level_irq); + struct tsweim_intc *priv = d->host_data; + irq_set_chip_and_handler(irq, &priv->chip, handle_level_irq); irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE); irq_set_status_flags(irq, IRQ_LEVEL); @@ -83,6 +101,7 @@ static int tsweim_intc_irqdomain_map(struct irq_domain *d, static const struct irq_domain_ops tsweim_intc_irqdomain_ops = { .map = tsweim_intc_irqdomain_map, + .xlate = irq_domain_xlate_onetwocell, }; static int tsweim_intc_probe(struct platform_device *pdev) @@ -90,6 +109,7 @@ static int tsweim_intc_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct tsweim_intc *priv; struct resource *irq = 0; + struct irq_chip *chip; priv = devm_kzalloc(dev, sizeof(struct tsweim_intc), GFP_KERNEL); if (!priv) @@ -105,8 +125,16 @@ static int tsweim_intc_probe(struct platform_device *pdev) return -EFAULT; } - priv->irqdomain = irq_domain_add_linear( - dev->of_node, TSWEIM_NUM_FPGA_IRQ, &tsweim_intc_irqdomain_ops, priv); + chip = &priv->chip; + chip->name = dev->of_node->name; + chip->irq_mask = tsweim_intc_mask; + chip->irq_unmask = tsweim_intc_unmask; + + if (of_property_read_bool(dev->of_node, "ts,haspolarity")) + chip->irq_set_type = tsweim_intc_set_type; + + priv->irqdomain = irq_domain_add_linear(dev->of_node, + TSWEIM_NUM_FPGA_IRQ, &tsweim_intc_irqdomain_ops, priv); if (!priv->irqdomain) { pr_err("unable to add irq domain\n"); From a5d16184862805967c581dc034f6b88e42c10849 Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Fri, 24 Mar 2023 09:58:11 -0700 Subject: [PATCH 113/244] dts: imx6ul-ts7250v3: Add support for polarity register. --- arch/arm/boot/dts/nxp/imx/imx6ul-ts7250v3.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7250v3.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7250v3.dts index 9b9afc4cd7180..a8a8ead2502d6 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7250v3.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7250v3.dts @@ -15,3 +15,7 @@ &supervisor_rtc { status = "okay"; }; + +&fpga_intc { + ts,haspolarity; +}; From 008d4a195634b840fb303ab22e8b7264299debf3 Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Fri, 24 Mar 2023 10:01:28 -0700 Subject: [PATCH 114/244] dts: imx6ul-ts7250v3: use two cell for irqs Since polarity was added, we should use two cell by default and specify the polarity for our default IRQs --- .../arm/boot/dts/nxp/imx/imx6ul-ts7250v3.dtsi | 28 +++++++++---------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7250v3.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7250v3.dtsi index bb63f0d0796fe..e880da2786234 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7250v3.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7250v3.dtsi @@ -420,7 +420,7 @@ reg = <0x0 0x50>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; interrupt-parent = <&gpio5>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; @@ -549,7 +549,7 @@ fifo-size = <64>; clock-frequency = <1843200>; interrupt-parent = <&fpga_intc>; - interrupts = <0>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; }; /* COM2 RS-232 */ @@ -564,7 +564,7 @@ fifo-size = <64>; clock-frequency = <1843200>; interrupt-parent = <&fpga_intc>; - interrupts = <1>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; }; /* COM3 RS-232 */ @@ -579,7 +579,7 @@ fifo-size = <64>; clock-frequency = <1843200>; interrupt-parent = <&fpga_intc>; - interrupts = <2>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; }; /* COM2 RS-485 */ @@ -594,7 +594,7 @@ fifo-size = <64>; clock-frequency = <1843200>; interrupt-parent = <&fpga_intc>; - interrupts = <3>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; }; /* COM2 RS-422 */ @@ -609,7 +609,7 @@ fifo-size = <64>; clock-frequency = <1843200>; interrupt-parent = <&fpga_intc>; - interrupts = <4>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; }; /* Mikrobus UART */ @@ -624,7 +624,7 @@ fifo-size = <64>; clock-frequency = <1843200>; interrupt-parent = <&fpga_intc>; - interrupts = <5>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; }; fpga_uart6: serial@60 { @@ -638,7 +638,7 @@ fifo-size = <64>; clock-frequency = <1843200>; interrupt-parent = <&fpga_intc>; - interrupts = <6>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH>; }; fpga_uart7: serial@70 { @@ -652,7 +652,7 @@ fifo-size = <64>; clock-frequency = <1843200>; interrupt-parent = <&fpga_intc>; - interrupts = <7>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; }; fpga_uart8: serial@80 { @@ -666,7 +666,7 @@ fifo-size = <64>; clock-frequency = <1843200>; interrupt-parent = <&fpga_intc>; - interrupts = <8>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; }; opencores_spi0: spi@100 { @@ -675,7 +675,7 @@ #size-cells = <0>; reg = <0x100 32>; interrupt-parent = <&fpga_intc>; - interrupts = <9>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; clocks = <&fpga_clk_weim_bclk>; clock-names = "spi-oc-clk"; opencores-spi,idx = <0>; @@ -710,7 +710,7 @@ #size-cells = <0>; reg = <0x120 32>; interrupt-parent = <&fpga_intc>; - interrupts = <10>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; clocks = <&fpga_clk_weim_bclk>; clock-names = "spi-oc-clk"; opencores-spi,idx = <0>; @@ -727,14 +727,14 @@ compatible = "technologic,ts-simple-adc"; reg = <0x180 4>; interrupt-parent = <&fpga_intc>; - interrupts = <19>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; }; mikro_i2c: mikro_i2c@188 { compatible = "opencores,i2c-ocores"; reg = <0x188 16>; interrupt-parent = <&fpga_intc>; - interrupts = <20>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; clocks = <&fpga_clk_weim_bclk>; clock-names = "i2c-oc-clk"; reg-io-width = <1>; From dbcf6a1cada16eab86498fb50941d8a14b465021 Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Mon, 25 Sep 2023 10:13:23 -0700 Subject: [PATCH 115/244] spi: spidev: Add technologic,spi-header device Used for describing spi headers on embeddedTS boards where we do not know what end device is connected. --- drivers/spi/spidev.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c index 5300c942a2a44..c6e28e2637692 100644 --- a/drivers/spi/spidev.c +++ b/drivers/spi/spidev.c @@ -751,6 +751,7 @@ static const struct of_device_id spidev_dt_ids[] = { { .compatible = "semtech,sx1301", .data = &spidev_of_check }, { .compatible = "silabs,em3581", .data = &spidev_of_check }, { .compatible = "silabs,si3210", .data = &spidev_of_check }, + { .compatible = "technologic,spi-header", .data = &spidev_of_check }, {}, }; MODULE_DEVICE_TABLE(of, spidev_dt_ids); From ccf098dbf2b7207ae25dd656e8a77cd10b855164 Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Mon, 25 Sep 2023 10:14:24 -0700 Subject: [PATCH 116/244] arm: dts: replace spidev with technologic,spi-header Fixes the buggy spidev listed in device tree warnings. --- arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900-ts8390.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900-ts8950.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/imx6qdl-ts7990.dtsi | 4 ++-- arch/arm/boot/dts/nxp/imx/imx6ul-ts4100.dts | 2 +- arch/arm/boot/dts/nxp/imx/imx6ul-ts4100.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/imx6ul-ts7250v3.dtsi | 4 ++-- arch/arm/boot/dts/nxp/imx/imx6ul-ts7553v2.dts | 4 ++-- arch/arm/boot/dts/nxp/mxs/imx28-ts7400v2.dts | 4 ++-- 9 files changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900-ts8390.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900-ts8390.dtsi index d3313c25adf9d..1bde3a9011aec 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900-ts8390.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900-ts8390.dtsi @@ -195,7 +195,7 @@ status = "okay"; offbdspi: spi@1 { - compatible = "spidev"; + compatible = "technologic,spi-header"; reg = <1>; spi-max-frequency = <1000000>; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900-ts8950.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900-ts8950.dtsi index c1d5f1ca3c0ed..5505b934c84b0 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900-ts8950.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900-ts8950.dtsi @@ -160,7 +160,7 @@ }; spidev: spi@2 { - compatible = "spidev"; + compatible = "technologic,spi-header"; reg = <2>; spi-max-frequency = <18000000>; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi index 99186402b5961..8ae233ee42e14 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi @@ -186,7 +186,7 @@ /* CS1# is generic FPGA SPI access, normally unused */ spidevhd1: spi@2 { - compatible = "spidev"; + compatible = "technologic,spi-header"; reg = <2>; spi-max-frequency = <1000000>; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7990.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7990.dtsi index 792705fa7abaf..f4c601eba493b 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7990.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7990.dtsi @@ -212,13 +212,13 @@ }; spidevfpga: spidev@1 { - compatible = "spidev"; + compatible = "technologic,spi-header"; reg = <1>; spi-max-frequency = <1000000>; }; spidevdc1: spidev@2 { - compatible = "spidev"; + compatible = "technologic,spi-header"; reg = <2>; spi-max-frequency = <1000000>; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts4100.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-ts4100.dts index b6ea2fccbc09a..4f4feb4fd873a 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-ts4100.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts4100.dts @@ -18,7 +18,7 @@ &gpio4 10 GPIO_ACTIVE_LOW>; spioffbd: spi@1 { - compatible = "spidev"; + compatible = "technologic,spi-header"; reg = <1>; spi-max-frequency = <1000000>; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts4100.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-ts4100.dtsi index 63c50b39bbc12..238b7c6475dca 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-ts4100.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts4100.dtsi @@ -100,7 +100,7 @@ status = "okay"; spidevfpga: spi@0 { - compatible = "spidev"; + compatible = "technologic,spi-header"; reg = <0>; spi-max-frequency = <1000000>; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7250v3.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7250v3.dtsi index e880da2786234..bc4dc1b04fae9 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7250v3.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7250v3.dtsi @@ -682,7 +682,7 @@ opencores-spi,num-chipselects = <3>; dioheader: spi@0 { - compatible = "spidev"; + compatible = "technologic,spi-header"; spi-max-frequency = <19800000>; reg = <0>; }; @@ -717,7 +717,7 @@ opencores-spi,num-chipselects = <1>; mikrobus: spi@0 { - compatible = "spidev"; + compatible = "technologic,spi-header"; spi-max-frequency = <19800000>; reg = <0>; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7553v2.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7553v2.dts index f49ce18e39921..ab2e833d3c2e4 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7553v2.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7553v2.dts @@ -168,14 +168,14 @@ /* CS# 0 is SPI LCD interface */ spidevlcd: spi@0 { - compatible = "spidev"; + compatible = "technologic,spi-header"; reg = <0>; spi-max-frequency = <5000000>; }; /* CS# 1 is HD1 pin header SPI interface */ hd1_spidev: spidev@1 { - compatible = "spidev"; + compatible = "technologic,spi-header"; reg = <1>; }; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-ts7400v2.dts b/arch/arm/boot/dts/nxp/mxs/imx28-ts7400v2.dts index 47dab8c0c839a..732d2e7542eec 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-ts7400v2.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-ts7400v2.dts @@ -381,8 +381,8 @@ pinctrl-0 = <&pinctrl_spi0>; status = "okay"; - spidevdc: spi@0 { - compatible = "spidev"; + spidc: spi@0 { + compatible = "technologic,spi-header"; reg = <0>; spi-max-frequency = <1000000>; }; From cb1899c1746ba245f29aa145eb07d155990c82ce Mon Sep 17 00:00:00 2001 From: "Lionel D. Hummel" Date: Thu, 27 Apr 2023 16:41:00 -0700 Subject: [PATCH 117/244] ARM: dts: initial port of ts7100 to 5.10 * ts7100.dtsi * remove cma * default to CPU watchdog rather than SMC watchdog, due to issues between ts7100-wdt and SMC on the 7100 and 7180. e.g., using SMC WDT for reset leaves the watchdog running (with nothing tending it) after reboot. * add panel_in and display_out DTS nodes for LCD * io models 0 and 1 * io model 5 for pre-2023 U-Boots * ARM: dts: ts7100: validate "thin" 1 vs. "fat" 5 --- arch/arm/boot/dts/nxp/imx/Makefile | 2 + arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-1.dts | 12 + arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-3.dts | 13 + .../arm/boot/dts/nxp/imx/imx6ul-ts7100-3.dtsi | 186 ++++++ .../arm/boot/dts/nxp/imx/imx6ul-ts7100-z.dtsi | 236 ++++++++ arch/arm/boot/dts/nxp/imx/imx6ul-ts7100.dtsi | 530 ++++++++++++++++++ 6 files changed, 979 insertions(+) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-1.dts create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-3.dts create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-3.dtsi create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-z.dtsi create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-ts7100.dtsi diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx/Makefile index 0f6277c62d288..448654114216d 100644 --- a/arch/arm/boot/dts/nxp/imx/Makefile +++ b/arch/arm/boot/dts/nxp/imx/Makefile @@ -358,6 +358,8 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ul-ts7250v3-reva.dtb \ imx6ul-ts7250v3.dtb \ imx6ul-ts7553v2.dtb \ + imx6ul-ts7100-1.dtb \ + imx6ul-ts7100-3.dtb \ imx6ul-tx6ul-0010.dtb \ imx6ul-tx6ul-0011.dtb \ imx6ul-tx6ul-mainboard.dtb \ diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-1.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-1.dts new file mode 100644 index 0000000000000..a2258958f9275 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-1.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (C) 2023 Technologic Systems, Inc. dba embeddedTS + */ +/dts-v1/; +#include "imx6ul-ts7100.dtsi" +#include "imx6ul-ts7100-z.dtsi" + +/ { + model = "embeddedTS i.MX6UL TS-7100-Z"; + compatible = "technologic,ts7100z", "fsl,imx6ul"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-3.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-3.dts new file mode 100644 index 0000000000000..9ca1ca37b0a9a --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-3.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (C) 2023 Technologic Systems, Inc. dba embeddedTS + */ + +/dts-v1/; +#include "imx6ul-ts7100.dtsi" +#include "imx6ul-ts7100-3.dtsi" + +/ { + model = "embeddedTS i.MX6UL TS-7100 (3)"; + compatible = "technologic,ts7100", "fsl,imx6ul"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-3.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-3.dtsi new file mode 100644 index 0000000000000..a5acbb1c78a33 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-3.dtsi @@ -0,0 +1,186 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (C) 2023 Technologic Systems, Inc. dba embeddedTS + */ + +/ { + leds { + compatible = "gpio-leds"; + + led-2 { + color = ; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpio7 9 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-3 { + color = ; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpio7 8 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; +}; + +&ecspi3 { + num-cs = <1>; + cs-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + status = "okay"; + + wilc3000: wifi@0 { + compatible = "microchip,wilc3000"; + reg = <0>; + spi-max-frequency = <20000000>; + reset-gpios = <&gpio7 7 GPIO_ACTIVE_HIGH>; + chip_en-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio1>; + interrupts = <11 GPIO_ACTIVE_HIGH>; + }; +}; + +&gpio1 { + gpio-line-names = + "RS485_5_TXEN", "RTC_BATT_FAIL", "I2C_1_CLK", "I2C_1_DAT", + "AN_CH0", "AN_CH1", "", "", + "", "AN_CH2", "RS485_2_TXEN", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&ts7100_3_pinctrl_hog>; + + imx6ul-ts7100-3 { + ts7100_3_pinctrl_hog: hoggrp { + fsl,pins = < + /* + * All GPIO should be 0x1b020 unless special + * 0x1b020 == Hyst., 100k PU, 50 mA drive + * 0x1a020 == no pull resistor + * 0x13020 == 100k PD + */ + + /* REV B Strap */ + MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x1b020 + + /* EN_RELAY 1 */ + MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1a020 + /* EN_RELAY 2 */ + MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1a020 + /* NIM_RESET */ + MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b020 + /* NIM Status */ + MX6UL_PAD_LCD_DATA09__GPIO3_IO14 0x1b020 + /* FPGA Spares */ + MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b020 + MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x1b020 + MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b020 + + /* POWER_FAIL */ + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b020 + >; + }; + + pinctrl_adc1: adc1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x1a020 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x1a020 + MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x1a020 + MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x1a020 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x1b020 + MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x1b020 + MX6UL_PAD_NAND_CE0_B__ECSPI3_SCLK 0x1b020 + MX6UL_PAD_NAND_CE1_B__ECSPI3_MOSI 0x1b020 + MX6UL_PAD_NAND_CLE__ECSPI3_MISO 0x1b020 + MX6UL_PAD_NAND_READY_B__GPIO4_IO12 0x1b020 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x13020 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + >; + }; + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1 + MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 + MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x1b020 + MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1 + MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x13020 + MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1 + MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1 + >; + }; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + rts-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + linux,rs485-enabled-at-boot-time; + dma-names = "", ""; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; + uart-has-rtscts; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; + rts-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + uart-has-rtscts; + linux,rs485-enabled-at-boot-time; + dma-names = "", ""; +}; + +&usbotg1 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-z.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-z.dtsi new file mode 100644 index 0000000000000..da5ccd71fc607 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-z.dtsi @@ -0,0 +1,236 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (C) 2023 Technologic Systems, Inc. dba embeddedTS + */ + +/ { + leds { + compatible = "gpio-leds"; + + led-2 { + color = ; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpio7 9 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-3 { + color = ; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpio7 8 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; +}; + +&ecspi3 { + num-cs = <1>; + cs-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + status = "okay"; + + wilc3000: wifi@0 { + compatible = "microchip,wilc3000"; + reg = <0>; + spi-max-frequency = <20000000>; + reset-gpios = <&gpio7 7 GPIO_ACTIVE_HIGH>; + chip_en-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio1>; + interrupts = <11 GPIO_ACTIVE_HIGH>; + }; +}; + +/* gpiochip0; CPU GPIO1: */ +&gpio1 { + gpio-line-names = + "AN_CH4", "RTC_BATT_FAIL", "I2C_1_CLK", "I2C_1_DAT", + "AN_CH0", "AN_CH1", "", "", + "AN_CH2", "AN_CH3", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +/* gpiochip4; CPU GPIO2: */ +&gpio3 { + gpio-line-names = + "POWER_FAIL_3V", "FPGA_IRQ", "", "", + "EN_RELAY_1", "EN_RELAY_2", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +/* gpiochip5; FPGA dio: */ +&gpio4 { + gpio-line-names = + "DIO_1_OUT", "DIO_2_OUT", "DIO_1_IN", "DIO_2_IN", + "DIO_3_IN", "DIO_6", "DIG_IN_1", "DIG_IN_2", + "DIG_IN_3", "EN_CL_1", "EN_CL_2", "EN_CL_3", + "", "", "EN_CL_4", "EN_HS_SW", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +/* gpiochip6; FPGA dio2: */ +&gpio5 { + gpio-line-names = + "EN_EMMC_3V3#", "EN_ADC1_12V", "EN_ADC2_12V", "EN_ADC3_12V", + "EN_ADC4_12V", "EN_USB_HOST_5V", "PHY_RESET#", "WIFI_RESET#", + "IO_RED_LED#", "IO_GREEN_LED#", "", "", + "EN_PROG_SILAB", "DIO_3_OUT", "EN_HSPWM", "EN_LSPWM", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +/* gpiochip7; FPGA dio3: */ +&gpio6 { + gpio-line-names = + "CPU_TOUCH_IRQ#", "", "C6_PAD", "B8_PAD", + "C9_PAD", "C8_PAD", "NIM_3V3#_4V", "DIO_16_PAD", + "NIM_PWR_ON", "SEL_NIM_USB", "DIO_FAULT#", "", + "", "", "EN_BK_LT#", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&ts7100z_pinctrl_hog>; + + imx6ul-ts7100z { + ts7100z_pinctrl_hog: ts7100zhoggrp { + fsl,pins = < + /* + * All GPIO should be 0x1b020 unless special + * 0x1b020 == Hyst., 100k PU, 50 mA drive + * 0x1a020 == no pull resistor + * 0x13020 == 100k PD + */ + /* REV B Strap */ + MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x1b020 + + /* EN_RELAY 1 */ + MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1a020 + /* EN_RELAY 2 */ + MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1a020 + /* NIM_RESET */ + MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b020 + /* NIM Status */ + MX6UL_PAD_LCD_DATA09__GPIO3_IO14 0x1b020 + /* FPGA Spares */ + MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b020 + MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x1b020 + MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b020 + + /* POWER_FAIL */ + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b020 + >; + }; + + pinctrl_adc1: adc1grp{ + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x1a020 + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x1a020 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x1a020 + MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x1a020 + MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x1a020 + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x1a020 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x1b020 + MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x1b020 + MX6UL_PAD_NAND_CE0_B__ECSPI3_SCLK 0x1b020 + MX6UL_PAD_NAND_CE1_B__ECSPI3_MOSI 0x1b020 + MX6UL_PAD_NAND_CLE__ECSPI3_MISO 0x1b020 + MX6UL_PAD_NAND_READY_B__GPIO4_IO12 0x1b020 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1 + MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 + MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x1b020 + MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1 + MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1 + MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1 + >; + }; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; + uart-has-rtscts; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; + rts-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100.dtsi new file mode 100644 index 0000000000000..b198b1f029824 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100.dtsi @@ -0,0 +1,530 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (C) 2023 Technologic Systems, Inc. dba embeddedTS + */ + +#include +#include +#include "imx6ul.dtsi" + +/ { + chosen { + stdout-path = &uart1; + }; + + memory { + /* Set by u-boot */ + reg = <0x80000000 0>; + }; + + leds { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cpu_leds>; + compatible = "gpio-leds"; + + led-0 { + color = ; + function = LED_FUNCTION_POWER; + gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + led-1 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + reg_3v3: rev_3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_lcdif_enable: en-lcdif { + compatible = "regulator-fixed"; + regulator-name = "LCDIF_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio8 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + }; + + vref_adc_2v5: adc { + compatible = "regulator-fixed"; + regulator-name = "ADC_VREF"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-boot-on; + regulator-always-on; + }; + + panel { + label = "st7789v"; + compatible = "panel-dpi"; + panel-timing { + clock-frequency = <7000>; + hactive = <240>; + vactive = <320>; + hfront-porch = <38>; + hback-porch = <10>; + hsync-len = <10>; + vback-porch = <4>; + vfront-porch = <8>; + vsync-len = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + }; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; +}; + +&adc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc1>; + vref-supply = <&vref_adc_2v5>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + phy-supply = <®_3v3>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + clocks = <&clks IMX6UL_CLK_ENET_REF>; + clock-names = "rmii-ref"; + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + }; + + ethphy1: ethernet-phy@1 { + clocks = <&clks IMX6UL_CLK_ENET_REF>; + clock-names = "rmii-ref"; + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + phy-supply = <®_3v3>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + st_magn: magnetometer@1e { + compatible = "st,lis2mdl"; + reg = <0x1e>; + st,drdy-int-pin = <1>; + }; + + m41t00s: rtc@68 { + compatible = "m41t00"; + reg = <0x68>; + }; + + ism330: gyro@6a { + compatible = "st,ism330dlc"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ism330>; + reg = <0x6a>; + interrupt-parent = <&gpio5>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +&iomuxc { + imx6ul-ts7100 { + pinctrl_cpu_leds: cpuledgrp { + fsl,pins = < + /* Red LED */ + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x1b020 + /* Green LED */ + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x1b020 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 + >; + }; + + pinctrl_ism330: ism330grp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b020 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x4001a8b0 + MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x4001a8b0 + >; + }; + + pinctrl_i2c1_gpio: i2c1grpgpio { + fsl,pins = < + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x4001a8b0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x4001a8b0 + >; + }; + + pinctrl_lcd_ctrl: lcd_ctrl { + fsl,pins = < + /* + * All pins are: Hyst., 100k PU, Med. speed, + * High DSE, Fast SR. + */ + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x1b0b9 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x1b0b9 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x1b0b9 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x1b0b9 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x1b0b9 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x1b0b9 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x1b0b9 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x1b0b9 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x1b0b9 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x1b0b9 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x1b0b9 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x1b0b9 + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x1b0b9 + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x1b0b9 + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x1b0b9 + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x1b0b9 + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x1b0b9 + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x1b0b9 + + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x1b0b9 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x1b0b9 + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x1b0b9 + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x1b0b9 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart7: uart7grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA17__UART7_DCE_RX 0x1b0b1 + MX6UL_PAD_LCD_DATA16__UART7_DCE_TX 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_weim_fpga: weimfpgagrp { + fsl,pins = < + MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0xb029 + MX6UL_PAD_CSI_PIXCLK__EIM_OE 0x1b029 + MX6UL_PAD_CSI_VSYNC__EIM_RW 0x1b029 + MX6UL_PAD_CSI_HSYNC__EIM_LBA_B 0x1b029 + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x1b029 + MX6UL_PAD_NAND_DQS__EIM_WAIT 0x1b029 + MX6UL_PAD_NAND_WP_B__EIM_BCLK 0x1b029 + MX6UL_PAD_NAND_DATA07__EIM_AD15 0x1b029 + MX6UL_PAD_NAND_DATA06__EIM_AD14 0x1b029 + MX6UL_PAD_NAND_DATA05__EIM_AD13 0x1b029 + MX6UL_PAD_NAND_DATA04__EIM_AD12 0x1b029 + MX6UL_PAD_NAND_DATA03__EIM_AD11 0x1b029 + MX6UL_PAD_NAND_DATA02__EIM_AD10 0x1b029 + MX6UL_PAD_NAND_DATA01__EIM_AD09 0x1b029 + MX6UL_PAD_NAND_DATA00__EIM_AD08 0x1b029 + MX6UL_PAD_CSI_DATA07__EIM_AD07 0x1b029 + MX6UL_PAD_CSI_DATA06__EIM_AD06 0x1b029 + MX6UL_PAD_CSI_DATA05__EIM_AD05 0x1b029 + MX6UL_PAD_CSI_DATA04__EIM_AD04 0x1b029 + MX6UL_PAD_CSI_DATA03__EIM_AD03 0x1b029 + MX6UL_PAD_CSI_DATA02__EIM_AD02 0x1b029 + MX6UL_PAD_CSI_DATA01__EIM_AD01 0x1b029 + MX6UL_PAD_CSI_DATA00__EIM_AD00 0x1b029 + /* FPGA IRQ */ + MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x1b029 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 + >; + }; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_ctrl>; + lcd-supply = <®_lcdif_enable>; + status = "okay"; + + port { + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; +}; + +&snvs_rtc { + status = "disabled"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart7>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + no-1-8-v; + disable-wp; + broken-cd = <1>; + bus-width = <4>; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + status = "okay"; + fsl,ext-reset-output; +}; + +&weim { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_weim_fpga>; + clocks = <&clks IMX6UL_CLK_EIM>, <&clks IMX6UL_CLK_EIM_SLOW_SEL>; + ranges = <0 0 0x50000000 0x08000000>; + status = "okay"; + + #address-cells = <2>; + #size-cells = <1>; + + fpga: fpgabus@50000000 { + compatible = "simple-bus"; + reg = <0 0x50000000 0x00010000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0x10000>; + + fsl,weim-cs-timing = < + 0x0161030F // EIM_CSnGCR1 @ 0x021b8000 + 0x00000000 // EIM_CSnGCR2 @ 0x021b8004 + 0x03000000 // EIM_CSnRCR1 @ 0x021b8008 + 0x00000000 // EIM_CSnRCR2 @ 0x021b800c + 0x01000000 // EIM_CSnWCR1 @ 0x021b8010 + 0 // EIM_CSnWCR2 @ 0x021b8014 + >; + + fpga_clk_weim_bclk: fpga_clk_weim_bclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <49500000>; + }; + + syscon: syscon@50004000 { + compatible = "simple-bus"; + #address-cells = <0x2>; + #size-cells = <0x1>; + reg = <0x4000 0x58>; + ranges = <0 0 0x4000 0x58>; + + gpio6: gpio@50004010 { + compatible = "technologic,ts71xxweim-gpio"; + reg = <0 0x10 0x08>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio7: gpio@50004040 { + compatible = "technologic,ts71xxweim-gpio"; + reg = <0 0x40 0x08>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio8: gpio@50004050 { + compatible = "technologic,ts71xxweim-gpio"; + reg = <0 0x50 0x08>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + fpga_intc: interrupt-controller@50004024 { + compatible = "technologic,ts71xxweim-intc"; + + interrupt-controller; + #interrupt-cells = <1>; + reg = <0 0x00 0x50>; + + interrupt-parent = <&gpio5>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + fpga_uart0: serial@50000000 { + compatible = "ns16550a"; + device_type = "serial"; + current-speed = <115200>; + reg-shift = <1>; + reg-io-width = <1>; + reg = <0 16>; + clock-frequency = <1843200>; + interrupt-parent = <&fpga_intc>; + interrupts = <0>; + }; + + opencores_spi0: spi@50000100 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "opencores,spi-oc"; + reg = <0x100 32>; + interrupt-parent = <&fpga_intc>; + interrupts = <9>; + clocks = <&fpga_clk_weim_bclk>; + clock-names = "spi-oc-clk"; + opencores-spi,idx = <0>; + opencores-spi,num-chipselects = <2>; + + spifram: eeprom@0 { + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <20000000>; + size = <0x800>; + address-width = <16>; + pagesize = <64>; + }; + + spisplash: spi@1 { + compatible = "jedec,spi-nor"; + reg = <1>; + spi-max-frequency = <20000000>; + }; + }; + + opencores_spi1: spi@50000120 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "opencores,spi-oc"; + reg = <0x120 32>; + interrupt-parent = <&fpga_intc>; + interrupts = <10>; + clocks = <&fpga_clk_weim_bclk>; + clock-names = "spi-oc-clk"; + opencores-spi,idx = <1>; + opencores-spi,num-chipselects = <1>; + + /* Touch screen SPI interface */ + touch_spi: touch_spi@0 { + reg = <0>; + compatible = "ti,tsc2046"; + spi-max-frequency = <1000000>; + interrupt-parent = <&fpga_intc>; + interrupts = <16>; + pendown-gpio = <&gpio8 0 GPIO_ACTIVE_HIGH>; + + ti,vref-mv = /bits/ 16 <3300>; + ti,keep-vref-on; + ti,settle-delay-usec = /bits/ 16 <5000>; + ti,vref-delay-usecs = /bits/ 16 <0>; + ti,x-plate-ohms = /bits/ 16 <292>; + ti,y-plate-ohms = /bits/ 16 <584>; + ti,pressure-min = /bits/ 16 <300>; + linux,wakeup; + }; + }; + }; +}; From 7c5af6d76fc99219162b4ab69fb59b0ea5fc5400 Mon Sep 17 00:00:00 2001 From: "Lionel D. Hummel" Date: Fri, 29 Sep 2023 17:21:35 -0700 Subject: [PATCH 118/244] ARM: configs: tsimx6ul: Add LCD DRM configs for the ts7100 et al. * CONFIG_DRM_FBDEV_EMULATION=y * CONFIG_DRM_PANEL_SITRONIX_ST7789V=y --- arch/arm/configs/tsimx6ul_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/tsimx6ul_defconfig b/arch/arm/configs/tsimx6ul_defconfig index 50481882d9666..ae6088834439d 100644 --- a/arch/arm/configs/tsimx6ul_defconfig +++ b/arch/arm/configs/tsimx6ul_defconfig @@ -858,6 +858,7 @@ CONFIG_DRM_IMX_PARALLEL_DISPLAY=y CONFIG_DRM_MXSFB=y CONFIG_FB_MODE_HELPERS=y CONFIG_FB_ST7565P=m +CONFIG_DRM_FBDEV_EMULATION=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BACKLIGHT_PWM=m From c2585ecd80605a4d379b6d0d3b531182e8ee6893 Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Fri, 29 Sep 2023 10:03:45 -0700 Subject: [PATCH 119/244] serial: 8250: 8250_ts: Check for error instead of returning line Before this change it works when loading a single 8250 port, but with multiple it reports a failure: [ 1.248351] serial8250: ttyS0 at MMIO 0x3e8 (irq = 242, base_baud = 115200) is a 16550A [ 1.251118] serial8250: ttyS1 at MMIO 0x2e8 (irq = 242, base_baud = 115200) is a 16550A [ 1.252223] ts16550: probe of 50004050.fpgaisa:ts16550@2e8 failed with error 1 further UARTs would fail with errors 2, 3, 4, etc. Both ports are still functional, but serial8250_register_8250_port returns the allocated line number (or negative on failure), and not 0 on success as the previous code assumed. This fixes the error message. --- drivers/tty/serial/8250/8250_ts.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/8250/8250_ts.c b/drivers/tty/serial/8250/8250_ts.c index ce17e3469f2d8..b8247cd92fe21 100644 --- a/drivers/tty/serial/8250/8250_ts.c +++ b/drivers/tty/serial/8250/8250_ts.c @@ -29,6 +29,7 @@ static int technologic_ts16550_probe(struct platform_device *pdev) struct uart_8250_port uport; struct uart_port *port; const __be32 *addr_be; + int line; memset(&uport, 0, sizeof(uport)); @@ -52,7 +53,16 @@ static int technologic_ts16550_probe(struct platform_device *pdev) port->serial_in = tsisa_serial_in; port->serial_out = tsisa_serial_out; - return serial8250_register_8250_port(&uport); + line = serial8250_register_8250_port(&uport); + + if (line < 0) { + dev_err(dev, + "serial8250_register_8250_port() 0x%X irq %d failed\n", + port->mapbase, port->irq); + return line; + } + + return 0; } static const struct of_device_id ts16550_of_match[] = { From b331bbde4bcdd706e8c1d8ee2e37ec007ac8c84c Mon Sep 17 00:00:00 2001 From: "Lionel D. Hummel" Date: Wed, 4 Oct 2023 09:24:55 -0700 Subject: [PATCH 120/244] ARM: configs: tsimx6ul_minimal: Add LCD DRM configs for the ts7100 et al. --- arch/arm/configs/tsimx6ul_minimal_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/tsimx6ul_minimal_defconfig b/arch/arm/configs/tsimx6ul_minimal_defconfig index 376c94a1a7658..23d5d6dcde2bb 100644 --- a/arch/arm/configs/tsimx6ul_minimal_defconfig +++ b/arch/arm/configs/tsimx6ul_minimal_defconfig @@ -239,6 +239,7 @@ CONFIG_DRM_MXSFB=y CONFIG_FB_MODE_HELPERS=y # CONFIG_FB_MX3 is not set CONFIG_FB_ST7565P=m +CONFIG_DRM_FBDEV_EMULATION=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_PLATFORM=y CONFIG_BACKLIGHT_CLASS_DEVICE=y From 395e6918bc81eb8f337cd3ff6ed340c763ff39a7 Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Mon, 25 Sep 2023 08:14:25 -0700 Subject: [PATCH 121/244] tests: Removed from tree and moved to internal CI tests --- tests/ts_check_configs/config_check | 64 ------- .../full_graphics_config_requirements | 174 ------------------ .../full_headless_config_requirements | 165 ----------------- .../min_graphics_config_requirements | 52 ------ .../min_headless_config_requirements | 43 ----- tests/ts_check_configs/run_test.sh | 53 ------ 6 files changed, 551 deletions(-) delete mode 100755 tests/ts_check_configs/config_check delete mode 100644 tests/ts_check_configs/full_graphics_config_requirements delete mode 100644 tests/ts_check_configs/full_headless_config_requirements delete mode 100644 tests/ts_check_configs/min_graphics_config_requirements delete mode 100644 tests/ts_check_configs/min_headless_config_requirements delete mode 100755 tests/ts_check_configs/run_test.sh diff --git a/tests/ts_check_configs/config_check b/tests/ts_check_configs/config_check deleted file mode 100755 index 1326b2c709bfa..0000000000000 --- a/tests/ts_check_configs/config_check +++ /dev/null @@ -1,64 +0,0 @@ -#!/usr/bin/env python3 -import sys -import os - -def parse_config_file(file_path): - """ - Parses a Linux kernel .config file and returns a dictionary of options - that have a value of 'y' or 'm'. - - Args: - file_path (str): The path to the .config file to be parsed. - - Returns: - dict: A dictionary containing the names of options that have a value - of 'y' or 'm' as keys, and their values as values. - - Raises: - IOError: If the file at `file_path` cannot be opened. - ValueError: If the contents of the file at `file_path` are not - formatted correctly. - - Example: - >>> parse_config_file('/path/to/config_file.config') - {'CONFIG_THING1': 'y', 'CONFIG_THING2': 'm'} - options = {} - """ - - options = {} - with open(file_path, 'r', encoding='utf-8') as f: - for line in f: - line = line.strip() - if not line or line.startswith('#') or '=' not in line: - continue - option, value = map(str.strip, line.split('=', 1)) - if value in ('y', 'm', 'n'): - options[option] = value - else: - options[option] = 'x' - return options - -if len(sys.argv) != 3: - print("Usage: check_config requirements.config your.config") - sys.exit(1) - -expected_options = parse_config_file(sys.argv[1]) -config_options = parse_config_file(sys.argv[2]) -RESULT = 0 - -# Check if the config options match the expected options -for expected_option, expected_value in expected_options.items(): - if expected_option in config_options: - if expected_value == 'x': - continue - - if expected_value != config_options[expected_option]: - print(f'{expected_option} is set to {config_options[expected_option]} and should be {expected_value}') - RESULT = 1 - else: - if expected_value == 'n': - continue - print(f'{expected_option} is missing') - RESULT = 1 - -sys.exit(RESULT) diff --git a/tests/ts_check_configs/full_graphics_config_requirements b/tests/ts_check_configs/full_graphics_config_requirements deleted file mode 100644 index 61aed7d4bba24..0000000000000 --- a/tests/ts_check_configs/full_graphics_config_requirements +++ /dev/null @@ -1,174 +0,0 @@ -# =y required as compiled in -# =m required as a module -# =x either is fine -# =n Must not be included - -######## Driver frameworks required on all hardware: -CONFIG_SPI_SPIDEV=x -CONFIG_USB_ACM=x -CONFIG_USB_SERIAL_FTDI_SIO=x - -######## Debug options: -CONFIG_LOCKDEP=n -CONFIG_DEBUG_INFO=n -CONFIG_RUNTIME_TESTING_MENU=n -CONFIG_DEBUG_MISC=n -CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=n - -######## Systemd requirements: -CONFIG_DEVTMPFS=x -CONFIG_CGROUPS=x -CONFIG_INOTIFY_USER=x -CONFIG_SIGNALFD=x -CONFIG_TIMERFD=x -CONFIG_EPOLL=x -CONFIG_UNIX=x -CONFIG_SYSFS=x -CONFIG_PROC_FS=x -CONFIG_FHANDLE=x -CONFIG_BINFMT_MISC=y - -######## Systemd Optional: -#CONFIG_DMIID=x SMBIOS thing, we dont need thsi -CONFIG_BLK_DEV_BSG=x -CONFIG_NET_NS=x -CONFIG_USER_NS=x -CONFIG_IPV6=x -CONFIG_AUTOFS_FS=x -CONFIG_TMPFS_XATTR=x -CONFIG_TMPFS_POSIX_ACL=x -CONFIG_EXT4_FS_POSIX_ACL=x -CONFIG_SECCOMP=x -CONFIG_SECCOMP_FILTER=x -CONFIG_CHECKPOINT_RESTORE=x -CONFIG_CGROUP_SCHED=x -CONFIG_FAIR_GROUP_SCHED=x -CONFIG_CFS_BANDWIDTH=x -CONFIG_BPF=x -CONFIG_BPF_SYSCALL=x -CONFIG_BPF_JIT=x -CONFIG_HAVE_EBPF_JIT=x -CONFIG_CGROUP_BPF=x -CONFIG_BPF=x -CONFIG_BPF_SYSCALL=x -CONFIG_BPF_JIT=x -CONFIG_HAVE_EBPF_JIT=x -CONFIG_CGROUP_BPF=x -CONFIG_EFIVAR_FS=x -CONFIG_EFI_PARTITION=x -# Skipping verity thinsg -#CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=x -#CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING=x -#CONFIG_IMA_ARCH_POLICY=x -# Skipping these because they require expensive tracing to be enabled -#CONFIG_BPF=x -#CONFIG_BPF_SYSCALL=x -#CONFIG_BPF_LSM=x -#CONFIG_DEBUG_INFO_BTF=x -CONFIG_PSI=x -CONFIG_RT_GROUP_SCHED=n -CONFIG_AUDIT=n -CONFIG_SYSFS_DEPRECATED=n -CONFIG_FW_LOADER_USER_HELPER=n - -######## NFS root requirements: -CONFIG_ROOT_NFS=y -CONFIG_NFS_V3=y -CONFIG_NFS_V2=y -CONFIG_NFS_DISABLE_UDP_SUPPORT=y -CONFIG_IP_PNP_DHCP=y -# Skipped because its huge -CONFIG_NFS_V4=n - -######## Docker requirements: -CONFIG_NAMESPACES=x -CONFIG_NET_NS=x -CONFIG_PID_NS=x -CONFIG_IPC_NS=x -CONFIG_UTS_NS=x -CONFIG_CGROUPS=x -CONFIG_CGROUP_CPUACCT=x -CONFIG_CGROUP_DEVICE=x -CONFIG_CGROUP_FREEZER=x -CONFIG_CGROUP_SCHED=x -# We do want this, but it wont exist on our configs without smp -#CONFIG_CPUSETS=x -CONFIG_MEMCG=x -CONFIG_KEYS=x -CONFIG_VETH=x -CONFIG_BRIDGE=x -CONFIG_BRIDGE_NETFILTER=x -CONFIG_IP_NF_FILTER=x -CONFIG_IP_NF_TARGET_MASQUERADE=x -CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=x -CONFIG_NETFILTER_XT_MATCH_CONNTRACK=x -CONFIG_NETFILTER_XT_MATCH_IPVS=x -CONFIG_NETFILTER_XT_MARK=x -CONFIG_IP_NF_NAT=x -CONFIG_NF_NAT=x -CONFIG_POSIX_MQUEUE=x - -######## Docker Optional: -CONFIG_USER_NS=x -CONFIG_SECCOMP=x -CONFIG_SECCOMP_FILTER=x -CONFIG_CGROUP_PIDS=x -CONFIG_MEMCG_SWAP=x -CONFIG_EXT4_FS=x -CONFIG_EXT4_FS_POSIX_ACL=x -CONFIG_EXT4_FS_SECURITY=x -CONFIG_BRIDGE_VLAN_FILTERING=x -CONFIG_VXLAN=x -CONFIG_CRYPTO=x -CONFIG_CRYPTO_AEAD=x -CONFIG_CRYPTO_GCM=x -CONFIG_CRYPTO_SEQIV=x -CONFIG_CRYPTO_GHASH=x -CONFIG_XFRM=x -CONFIG_XFRM_USER=x -CONFIG_XFRM_ALGO=x -CONFIG_INET_ESP=x -CONFIG_IPVLAN=x -CONFIG_MACVLAN=x -CONFIG_DUMMY=x -CONFIG_NF_NAT_FTP=x -CONFIG_NF_CONNTRACK_FTP=x -CONFIG_NF_NAT_TFTP=x -CONFIG_NF_CONNTRACK_TFTP=x -CONFIG_BLK_DEV_DM=x -CONFIG_DM_THIN_PROVISIONING=x -CONFIG_OVERLAY_FS=x - -# Support very common input devices -CONFIG_HID_MULTITOUCH=x -CONFIG_INPUT_MOUSEDEV=x -CONFIG_HID_GENERIC=x - -# Support PWM backlight -CONFIG_BACKLIGHT_CLASS_DEVICE=x -CONFIG_BACKLIGHT_PWM=x - -######## Common customer requirements: -CONFIG_CAN_J1939=x -CONFIG_PTP_1588_CLOCK=x -CONFIG_NETFILTER=x -CONFIG_IPV6=y -#Cell modems: -CONFIG_PPP=m -CONFIG_PPP_BSDCOMP=m -CONFIG_PPP_DEFLATE=m -CONFIG_PPP_FILTER=y -CONFIG_PPP_MPPE=m -CONFIG_PPP_MULTILINK=y -CONFIG_PPPOE=m -CONFIG_PPPOL2TP=m -CONFIG_PPP_ASYNC=m -CONFIG_PPP_SYNC_TTY=m -CONFIG_USB_NET_CDCETHER=m -CONFIG_USB_NET_CDC_NCM=m -CONFIG_USB_NET_QMI_WWAN=m - -# Needed for WILC3000 correct operation! -# With powersaving enabled, BLE is completely broken, while Wi-Fi will show -# strange hiccups and subtle breakages sometimes. -CONFIG_CFG80211_DEFAULT_PS=n diff --git a/tests/ts_check_configs/full_headless_config_requirements b/tests/ts_check_configs/full_headless_config_requirements deleted file mode 100644 index 8b49dce67e3c8..0000000000000 --- a/tests/ts_check_configs/full_headless_config_requirements +++ /dev/null @@ -1,165 +0,0 @@ -# =y required as compiled in -# =m required as a module -# =x either is fine -# =n Must not be included - -######## Driver frameworks required on all hardware: -CONFIG_SPI_SPIDEV=x -CONFIG_USB_ACM=x -CONFIG_USB_SERIAL_FTDI_SIO=x - -######## Debug options: -CONFIG_LOCKDEP=n -CONFIG_DEBUG_INFO=n -CONFIG_RUNTIME_TESTING_MENU=n -CONFIG_DEBUG_MISC=n -CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=n - -######## Systemd requirements: -CONFIG_DEVTMPFS=x -CONFIG_CGROUPS=x -CONFIG_INOTIFY_USER=x -CONFIG_SIGNALFD=x -CONFIG_TIMERFD=x -CONFIG_EPOLL=x -CONFIG_UNIX=x -CONFIG_SYSFS=x -CONFIG_PROC_FS=x -CONFIG_FHANDLE=x -CONFIG_BINFMT_MISC=y - -######## Systemd Optional: -#CONFIG_DMIID=x SMBIOS thing, we dont need thsi -CONFIG_BLK_DEV_BSG=x -CONFIG_NET_NS=x -CONFIG_USER_NS=x -CONFIG_IPV6=x -CONFIG_AUTOFS_FS=x -CONFIG_TMPFS_XATTR=x -CONFIG_TMPFS_POSIX_ACL=x -CONFIG_EXT4_FS_POSIX_ACL=x -CONFIG_SECCOMP=x -CONFIG_SECCOMP_FILTER=x -CONFIG_CHECKPOINT_RESTORE=x -CONFIG_CGROUP_SCHED=x -CONFIG_FAIR_GROUP_SCHED=x -CONFIG_CFS_BANDWIDTH=x -CONFIG_BPF=x -CONFIG_BPF_SYSCALL=x -CONFIG_BPF_JIT=x -CONFIG_HAVE_EBPF_JIT=x -CONFIG_CGROUP_BPF=x -CONFIG_BPF=x -CONFIG_BPF_SYSCALL=x -CONFIG_BPF_JIT=x -CONFIG_HAVE_EBPF_JIT=x -CONFIG_CGROUP_BPF=x -CONFIG_EFIVAR_FS=x -CONFIG_EFI_PARTITION=x -# Skipping verity thinsg -#CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=x -#CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING=x -#CONFIG_IMA_ARCH_POLICY=x -# Skipping these because they require expensive tracing to be enabled -#CONFIG_BPF=x -#CONFIG_BPF_SYSCALL=x -#CONFIG_BPF_LSM=x -#CONFIG_DEBUG_INFO_BTF=x -CONFIG_PSI=x -CONFIG_RT_GROUP_SCHED=n -CONFIG_AUDIT=n -CONFIG_SYSFS_DEPRECATED=n -CONFIG_FW_LOADER_USER_HELPER=n - -######## NFS root requirements: -CONFIG_ROOT_NFS=y -CONFIG_NFS_V3=y -CONFIG_NFS_V2=y -CONFIG_NFS_DISABLE_UDP_SUPPORT=y -CONFIG_IP_PNP_DHCP=y -# Skipped because its huge -CONFIG_NFS_V4=n - -######## Docker requirements: -CONFIG_NAMESPACES=x -CONFIG_NET_NS=x -CONFIG_PID_NS=x -CONFIG_IPC_NS=x -CONFIG_UTS_NS=x -CONFIG_CGROUPS=x -CONFIG_CGROUP_CPUACCT=x -CONFIG_CGROUP_DEVICE=x -CONFIG_CGROUP_FREEZER=x -CONFIG_CGROUP_SCHED=x -# We do want this, but it wont exist on our configs without smp -#CONFIG_CPUSETS=x -CONFIG_MEMCG=x -CONFIG_KEYS=x -CONFIG_VETH=x -CONFIG_BRIDGE=x -CONFIG_BRIDGE_NETFILTER=x -CONFIG_IP_NF_FILTER=x -CONFIG_IP_NF_TARGET_MASQUERADE=x -CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=x -CONFIG_NETFILTER_XT_MATCH_CONNTRACK=x -CONFIG_NETFILTER_XT_MATCH_IPVS=x -CONFIG_NETFILTER_XT_MARK=x -CONFIG_IP_NF_NAT=x -CONFIG_NF_NAT=x -CONFIG_POSIX_MQUEUE=x - -######## Docker Optional: -CONFIG_USER_NS=x -CONFIG_SECCOMP=x -CONFIG_SECCOMP_FILTER=x -CONFIG_CGROUP_PIDS=x -CONFIG_MEMCG_SWAP=x -CONFIG_EXT4_FS=x -CONFIG_EXT4_FS_POSIX_ACL=x -CONFIG_EXT4_FS_SECURITY=x -CONFIG_BRIDGE_VLAN_FILTERING=x -CONFIG_VXLAN=x -CONFIG_CRYPTO=x -CONFIG_CRYPTO_AEAD=x -CONFIG_CRYPTO_GCM=x -CONFIG_CRYPTO_SEQIV=x -CONFIG_CRYPTO_GHASH=x -CONFIG_XFRM=x -CONFIG_XFRM_USER=x -CONFIG_XFRM_ALGO=x -CONFIG_INET_ESP=x -CONFIG_IPVLAN=x -CONFIG_MACVLAN=x -CONFIG_DUMMY=x -CONFIG_NF_NAT_FTP=x -CONFIG_NF_CONNTRACK_FTP=x -CONFIG_NF_NAT_TFTP=x -CONFIG_NF_CONNTRACK_TFTP=x -CONFIG_BLK_DEV_DM=x -CONFIG_DM_THIN_PROVISIONING=x -CONFIG_OVERLAY_FS=x - -######## Common customer requirements: -CONFIG_CAN_J1939=x -CONFIG_PTP_1588_CLOCK=x -CONFIG_NETFILTER=x -CONFIG_IPV6=y -#Cell modems: -CONFIG_PPP=m -CONFIG_PPP_BSDCOMP=m -CONFIG_PPP_DEFLATE=m -CONFIG_PPP_FILTER=y -CONFIG_PPP_MPPE=m -CONFIG_PPP_MULTILINK=y -CONFIG_PPPOE=m -CONFIG_PPPOL2TP=m -CONFIG_PPP_ASYNC=m -CONFIG_PPP_SYNC_TTY=m -CONFIG_USB_NET_CDCETHER=m -CONFIG_USB_NET_CDC_NCM=m -CONFIG_USB_NET_QMI_WWAN=m - -# Needed for WILC3000 correct operation! -# With powersaving enabled, BLE is completely broken, while Wi-Fi will show -# strange hiccups and subtle breakages sometimes. -CONFIG_CFG80211_DEFAULT_PS=n diff --git a/tests/ts_check_configs/min_graphics_config_requirements b/tests/ts_check_configs/min_graphics_config_requirements deleted file mode 100644 index 39c3fe7b94c35..0000000000000 --- a/tests/ts_check_configs/min_graphics_config_requirements +++ /dev/null @@ -1,52 +0,0 @@ -# =y required as compiled in -# =m required as a module -# =x either is fine -# =n Must not be included - -######## Driver frameworks required on all hardware: -CONFIG_SPI_SPIDEV=x -CONFIG_USB_ACM=x -CONFIG_USB_SERIAL_FTDI_SIO=x - -######## Debug options: -CONFIG_LOCKDEP=n -CONFIG_DEBUG_INFO=n -CONFIG_RUNTIME_TESTING_MENU=n -CONFIG_DEBUG_MISC=n -CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=n - -######## Systemd requirements: -CONFIG_DEVTMPFS=x -CONFIG_CGROUPS=x -CONFIG_INOTIFY_USER=x -CONFIG_SIGNALFD=x -CONFIG_TIMERFD=x -CONFIG_EPOLL=x -CONFIG_UNIX=x -CONFIG_SYSFS=x -CONFIG_PROC_FS=x -CONFIG_FHANDLE=x -CONFIG_BINFMT_MISC=y - -######## NFS root requirements: -CONFIG_ROOT_NFS=y -CONFIG_NFS_V3=y -CONFIG_NFS_V2=y -CONFIG_NFS_DISABLE_UDP_SUPPORT=y -CONFIG_IP_PNP_DHCP=y -# Skipped because its huge -CONFIG_NFS_V4=n - -# Support very common input devices -CONFIG_HID_MULTITOUCH=x -CONFIG_INPUT_MOUSEDEV=x -CONFIG_HID_GENERIC=x - -# Support PWM backlight -CONFIG_BACKLIGHT_CLASS_DEVICE=x -CONFIG_BACKLIGHT_PWM=x - -# Needed for WILC3000 correct operation! -# With powersaving enabled, BLE is completely broken, while Wi-Fi will show -# strange hiccups and subtle breakages sometimes. -CONFIG_CFG80211_DEFAULT_PS=n diff --git a/tests/ts_check_configs/min_headless_config_requirements b/tests/ts_check_configs/min_headless_config_requirements deleted file mode 100644 index 26f6662e1bff4..0000000000000 --- a/tests/ts_check_configs/min_headless_config_requirements +++ /dev/null @@ -1,43 +0,0 @@ -# =y required as compiled in -# =m required as a module -# =x either is fine -# =n Must not be included - -######## Driver frameworks required on all hardware: -CONFIG_SPI_SPIDEV=x -CONFIG_USB_ACM=x -CONFIG_USB_SERIAL_FTDI_SIO=x - -######## Debug options: -CONFIG_LOCKDEP=n -CONFIG_DEBUG_INFO=n -CONFIG_RUNTIME_TESTING_MENU=n -CONFIG_DEBUG_MISC=n -CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=n - -######## Systemd requirements: -CONFIG_DEVTMPFS=x -CONFIG_CGROUPS=x -CONFIG_INOTIFY_USER=x -CONFIG_SIGNALFD=x -CONFIG_TIMERFD=x -CONFIG_EPOLL=x -CONFIG_UNIX=x -CONFIG_SYSFS=x -CONFIG_PROC_FS=x -CONFIG_FHANDLE=x -CONFIG_BINFMT_MISC=y - -######## NFS root requirements: -CONFIG_ROOT_NFS=y -CONFIG_NFS_V3=y -CONFIG_NFS_V2=y -CONFIG_NFS_DISABLE_UDP_SUPPORT=y -CONFIG_IP_PNP_DHCP=y -# Skipped because its huge -CONFIG_NFS_V4=n - -# Needed for WILC3000 correct operation! -# With powersaving enabled, BLE is completely broken, while Wi-Fi will show -# strange hiccups and subtle breakages sometimes. -CONFIG_CFG80211_DEFAULT_PS=n diff --git a/tests/ts_check_configs/run_test.sh b/tests/ts_check_configs/run_test.sh deleted file mode 100755 index b3585ad47431d..0000000000000 --- a/tests/ts_check_configs/run_test.sh +++ /dev/null @@ -1,53 +0,0 @@ -#!/bin/bash -e - -full_graphics_config_files=( - "tsimx6_defconfig" -) - -min_graphics_config_files=( - "tsimx6_minimal_defconfig" -) - -full_headless_config_files=( - "tsa38x_defconfig" - "tsimx6ul_defconfig" - "tsimx28_defconfig" -) - -min_headless_config_files=( - "tsa38x_minimal_defconfig" - "tsimx6ul_minimal_defconfig" - "tsimx28_minimal_defconfig" -) - -for config_file in "${full_graphics_config_files[@]}"; do - echo "Testing ${config_file}..." - make "${config_file}" > /dev/null 2>&1 - tests/ts_check_configs/config_check \ - tests/ts_check_configs/full_graphics_config_requirements \ - .config -done - -for config_file in "${min_graphics_config_files[@]}"; do - echo "Testing ${config_file}..." - make "${config_file}" > /dev/null 2>&1 - tests/ts_check_configs/config_check \ - tests/ts_check_configs/min_graphics_config_requirements \ - .config -done - -for config_file in "${full_headless_config_files[@]}"; do - echo "Testing ${config_file}..." - make "${config_file}" > /dev/null 2>&1 - tests/ts_check_configs/config_check \ - tests/ts_check_configs/full_headless_config_requirements \ - .config -done - -for config_file in "${min_headless_config_files[@]}"; do - echo "Testing ${config_file}..." - make "${config_file}" > /dev/null 2>&1 - tests/ts_check_configs/config_check \ - tests/ts_check_configs/min_headless_config_requirements \ - .config -done From e47dbe6ecdf654a45af5a2ec007a0ed9f661b438 Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Wed, 11 Oct 2023 21:17:27 -0700 Subject: [PATCH 122/244] ARM: dts: imx6: TS-4900 Fix typo --- arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900.dtsi index f61959755e599..49f4c5829ec3f 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900.dtsi @@ -26,7 +26,7 @@ red-1 { color = ; - functino = LED_FUNCTION_STATUS; + function = LED_FUNCTION_STATUS; gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; default-state = "off"; }; From fc8e22657eb09b23d9538dbdfa1b6dc1084b2676 Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Wed, 18 Oct 2023 16:51:20 -0700 Subject: [PATCH 123/244] Kernel config fixup (#44) * ARM: configs: ts: updated configs to match tested requirements * Removed nand * Removed VTE * Removed lpuarts * Added OTG support * Removed PCIe ASPM * Removed debug * Added rfkill_input --- arch/arm/configs/tsa38x_defconfig | 662 ++++++------------- arch/arm/configs/tsa38x_minimal_defconfig | 24 +- arch/arm/configs/tsimx28_defconfig | 204 ++++-- arch/arm/configs/tsimx28_minimal_defconfig | 27 +- arch/arm/configs/tsimx6_defconfig | 632 +++++++----------- arch/arm/configs/tsimx6_minimal_defconfig | 41 +- arch/arm/configs/tsimx6ul_defconfig | 685 +++++++------------- arch/arm/configs/tsimx6ul_minimal_defconfig | 45 +- 8 files changed, 909 insertions(+), 1411 deletions(-) diff --git a/arch/arm/configs/tsa38x_defconfig b/arch/arm/configs/tsa38x_defconfig index cbc51bbf797fe..5d29c5f02652e 100644 --- a/arch/arm/configs/tsa38x_defconfig +++ b/arch/arm/configs/tsa38x_defconfig @@ -1,72 +1,57 @@ -CONFIG_KERNEL_LZO=y -CONFIG_DEFAULT_HOSTNAME="" CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y -CONFIG_GENERIC_IRQ_DEBUGFS=y +# CONFIG_CROSS_MEMORY_ATTACH is not set CONFIG_HIGH_RES_TIMERS=y CONFIG_PREEMPT=y CONFIG_PSI=y -CONFIG_IKCONFIG=m -CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CGROUPS=y CONFIG_MEMCG=y -CONFIG_BLK_CGROUP=y CONFIG_CGROUP_SCHED=y CONFIG_CFS_BANDWIDTH=y CONFIG_CGROUP_PIDS=y -CONFIG_CGROUP_RDMA=y CONFIG_CGROUP_FREEZER=y CONFIG_CPUSETS=y CONFIG_CGROUP_DEVICE=y CONFIG_CGROUP_CPUACCT=y -CONFIG_CGROUP_PERF=y CONFIG_CGROUP_BPF=y -CONFIG_CGROUP_DEBUG=y CONFIG_NAMESPACES=y CONFIG_USER_NS=y CONFIG_CHECKPOINT_RESTORE=y CONFIG_BLK_DEV_INITRD=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set # CONFIG_RD_ZSTD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_EXPERT=y +CONFIG_BPF_SYSCALL=y CONFIG_PERF_EVENTS=y CONFIG_SLAB=y CONFIG_ARCH_MVEBU=y CONFIG_MACH_ARMADA_38X=y CONFIG_ARM_THUMBEE=y -# CONFIG_HARDEN_BRANCH_HISTORY is not set CONFIG_SMP=y CONFIG_HZ_1000=y -CONFIG_HIGHMEM=y -# CONFIG_ARM_MODULE_PLTS is not set CONFIG_ARM_APPENDED_DTB=y CONFIG_ARM_ATAG_DTB_COMPAT=y CONFIG_EFI=y -# CONFIG_DMI is not set CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y CONFIG_CPUFREQ_DT=y CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_MENU=y CONFIG_ARM_MVEBU_V7_CPUIDLE=y CONFIG_VFP=y CONFIG_NEON=y -CONFIG_JUMP_LABEL=y CONFIG_MODULES=y -CONFIG_MODULE_FORCE_LOAD=y CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y CONFIG_MODVERSIONS=y CONFIG_MODULE_COMPRESS=y CONFIG_MODULE_COMPRESS_XZ=y -CONFIG_BLK_DEV_BSGLIB=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_MAC_PARTITION=y -CONFIG_BSD_DISKLABEL=y -CONFIG_MINIX_SUBPARTITION=y -CONFIG_LDM_PARTITION=y -CONFIG_LDM_DEBUG=y -CONFIG_CMDLINE_PARTITION=y +# CONFIG_MQ_IOSCHED_KYBER is not set CONFIG_BINFMT_MISC=y -CONFIG_CMA=y +# CONFIG_COMPACTION is not set CONFIG_NET=y CONFIG_PACKET=y CONFIG_PACKET_DIAG=m @@ -74,21 +59,20 @@ CONFIG_UNIX=y CONFIG_UNIX_DIAG=m CONFIG_TLS=m CONFIG_XFRM_USER=m +CONFIG_XFRM_INTERFACE=m CONFIG_XFRM_SUB_POLICY=y -CONFIG_XFRM_MIGRATE=y -CONFIG_XFRM_STATISTICS=y CONFIG_NET_KEY=m +CONFIG_NET_KEY_MIGRATE=y +CONFIG_XDP_SOCKETS=y +CONFIG_XDP_SOCKETS_DIAG=m CONFIG_INET=y CONFIG_IP_MULTICAST=y CONFIG_IP_ADVANCED_ROUTER=y -CONFIG_IP_FIB_TRIE_STATS=y CONFIG_IP_MULTIPLE_TABLES=y CONFIG_IP_ROUTE_MULTIPATH=y CONFIG_IP_ROUTE_VERBOSE=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y CONFIG_NET_IPIP=m CONFIG_NET_IPGRE_DEMUX=m CONFIG_NET_IPGRE=m @@ -101,22 +85,35 @@ CONFIG_NET_IPVTI=m CONFIG_NET_FOU_IP_TUNNELS=y CONFIG_INET_AH=m CONFIG_INET_ESP=m -CONFIG_INET_ESP_OFFLOAD=m +CONFIG_INET_ESPINTCP=y CONFIG_INET_IPCOMP=m CONFIG_INET_UDP_DIAG=m CONFIG_INET_RAW_DIAG=m CONFIG_INET_DIAG_DESTROY=y CONFIG_TCP_CONG_ADVANCED=y +CONFIG_TCP_CONG_HSTCP=m +CONFIG_TCP_CONG_HYBLA=m +CONFIG_TCP_CONG_NV=m +CONFIG_TCP_CONG_SCALABLE=m +CONFIG_TCP_CONG_LP=m +CONFIG_TCP_CONG_VENO=m +CONFIG_TCP_CONG_YEAH=m +CONFIG_TCP_CONG_ILLINOIS=m +CONFIG_TCP_CONG_DCTCP=m +CONFIG_TCP_CONG_CDG=m +CONFIG_TCP_CONG_BBR=m CONFIG_TCP_MD5SIG=y CONFIG_IPV6_ROUTER_PREF=y CONFIG_IPV6_ROUTE_INFO=y CONFIG_IPV6_OPTIMISTIC_DAD=y CONFIG_INET6_AH=m CONFIG_INET6_ESP=m -CONFIG_INET6_ESP_OFFLOAD=m +CONFIG_INET6_ESPINTCP=y CONFIG_INET6_IPCOMP=m CONFIG_IPV6_MIP6=m +CONFIG_IPV6_ILA=m CONFIG_IPV6_VTI=m +CONFIG_IPV6_SIT=m CONFIG_IPV6_SIT_6RD=y CONFIG_IPV6_GRE=m CONFIG_IPV6_SUBTREES=y @@ -125,13 +122,16 @@ CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y CONFIG_IPV6_PIMSM_V2=y CONFIG_IPV6_SEG6_LWTUNNEL=y CONFIG_IPV6_SEG6_HMAC=y +CONFIG_IPV6_RPL_LWTUNNEL=y +CONFIG_MPTCP=y CONFIG_NETWORK_SECMARK=y -CONFIG_NETWORK_PHY_TIMESTAMPING=y CONFIG_NETFILTER=y CONFIG_BRIDGE_NETFILTER=m CONFIG_NF_CONNTRACK=m CONFIG_NF_LOG_NETDEV=m CONFIG_NF_CONNTRACK_SECMARK=y +CONFIG_NF_CONNTRACK_ZONES=y +CONFIG_NF_CONNTRACK_PROCFS=y CONFIG_NF_CONNTRACK_EVENTS=y CONFIG_NF_CONNTRACK_TIMEOUT=y CONFIG_NF_CONNTRACK_TIMESTAMP=y @@ -154,6 +154,7 @@ CONFIG_NF_TABLES_INET=y CONFIG_NF_TABLES_NETDEV=y CONFIG_NFT_NUMGEN=m CONFIG_NFT_CT=m +CONFIG_NFT_FLOW_OFFLOAD=m CONFIG_NFT_COUNTER=m CONFIG_NFT_CONNLIMIT=m CONFIG_NFT_LOG=m @@ -168,6 +169,7 @@ CONFIG_NFT_QUOTA=m CONFIG_NFT_REJECT=m CONFIG_NFT_COMPAT=m CONFIG_NFT_HASH=m +CONFIG_NFT_FIB_INET=m CONFIG_NFT_XFRM=m CONFIG_NFT_SOCKET=m CONFIG_NFT_OSF=m @@ -175,6 +177,7 @@ CONFIG_NFT_TPROXY=m CONFIG_NFT_SYNPROXY=m CONFIG_NFT_DUP_NETDEV=m CONFIG_NFT_FWD_NETDEV=m +CONFIG_NFT_FIB_NETDEV=m CONFIG_NF_FLOW_TABLE_INET=m CONFIG_NF_FLOW_TABLE=m CONFIG_NETFILTER_XT_SET=m @@ -182,6 +185,7 @@ CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m CONFIG_NETFILTER_XT_TARGET_CONNMARK=m CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m +CONFIG_NETFILTER_XT_TARGET_CT=m CONFIG_NETFILTER_XT_TARGET_DSCP=m CONFIG_NETFILTER_XT_TARGET_HMARK=m CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m @@ -190,7 +194,6 @@ CONFIG_NETFILTER_XT_TARGET_LOG=m CONFIG_NETFILTER_XT_TARGET_MARK=m CONFIG_NETFILTER_XT_TARGET_NFLOG=m CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m -CONFIG_NETFILTER_XT_TARGET_NOTRACK=m CONFIG_NETFILTER_XT_TARGET_TEE=m CONFIG_NETFILTER_XT_TARGET_TPROXY=m CONFIG_NETFILTER_XT_TARGET_TRACE=m @@ -231,6 +234,7 @@ CONFIG_NETFILTER_XT_MATCH_QUOTA=m CONFIG_NETFILTER_XT_MATCH_RATEEST=m CONFIG_NETFILTER_XT_MATCH_REALM=m CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SCTP=m CONFIG_NETFILTER_XT_MATCH_SOCKET=m CONFIG_NETFILTER_XT_MATCH_STATE=m CONFIG_NETFILTER_XT_MATCH_STATISTIC=m @@ -238,7 +242,7 @@ CONFIG_NETFILTER_XT_MATCH_STRING=m CONFIG_NETFILTER_XT_MATCH_TCPMSS=m CONFIG_NETFILTER_XT_MATCH_TIME=m CONFIG_NETFILTER_XT_MATCH_U32=m -CONFIG_IP_SET=y +CONFIG_IP_SET=m CONFIG_IP_SET_BITMAP_IP=m CONFIG_IP_SET_BITMAP_IPMAC=m CONFIG_IP_SET_BITMAP_PORT=m @@ -283,7 +287,7 @@ CONFIG_NFT_FIB_IPV4=m CONFIG_NF_TABLES_ARP=y CONFIG_NF_FLOW_TABLE_IPV4=m CONFIG_NF_LOG_ARP=m -CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_IPTABLES=m CONFIG_IP_NF_MATCH_AH=m CONFIG_IP_NF_MATCH_ECN=m CONFIG_IP_NF_MATCH_RPFILTER=m @@ -306,7 +310,7 @@ CONFIG_IP_NF_ARP_MANGLE=m CONFIG_NFT_DUP_IPV6=m CONFIG_NFT_FIB_IPV6=m CONFIG_NF_FLOW_TABLE_IPV6=m -CONFIG_IP6_NF_IPTABLES=y +CONFIG_IP6_NF_IPTABLES=m CONFIG_IP6_NF_MATCH_AH=m CONFIG_IP6_NF_MATCH_EUI64=m CONFIG_IP6_NF_MATCH_FRAG=m @@ -326,7 +330,6 @@ CONFIG_IP6_NF_RAW=m CONFIG_IP6_NF_NAT=m CONFIG_IP6_NF_TARGET_MASQUERADE=m CONFIG_IP6_NF_TARGET_NPT=m -CONFIG_DECNET_NF_GRABULATOR=m CONFIG_NF_TABLES_BRIDGE=m CONFIG_NFT_BRIDGE_META=m CONFIG_NFT_BRIDGE_REJECT=m @@ -355,18 +358,8 @@ CONFIG_BRIDGE_EBT_LOG=m CONFIG_BRIDGE_EBT_NFLOG=m CONFIG_BPFILTER=y CONFIG_IP_DCCP=m -CONFIG_IP_DCCP_CCID2_DEBUG=y -CONFIG_IP_DCCP_CCID3_DEBUG=y -CONFIG_IP_SCTP=m -CONFIG_SCTP_COOKIE_HMAC_SHA1=y CONFIG_RDS=m CONFIG_RDS_TCP=m -CONFIG_TIPC=m -CONFIG_ATM=m -CONFIG_ATM_CLIP=m -CONFIG_ATM_LANE=m -CONFIG_ATM_MPOA=m -CONFIG_ATM_BR2684=m CONFIG_L2TP=m CONFIG_L2TP_V3=y CONFIG_L2TP_IP=m @@ -378,104 +371,18 @@ CONFIG_NET_DSA=m CONFIG_VLAN_8021Q=m CONFIG_VLAN_8021Q_GVRP=y CONFIG_VLAN_8021Q_MVRP=y -CONFIG_DECNET=m -CONFIG_DECNET_ROUTER=y CONFIG_LLC2=m -CONFIG_ATALK=m -CONFIG_DEV_APPLETALK=m -CONFIG_IPDDP=m -CONFIG_X25=m -CONFIG_LAPB=m -CONFIG_PHONET=m CONFIG_6LOWPAN=m -CONFIG_6LOWPAN_DEBUGFS=y -CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m -CONFIG_6LOWPAN_GHC_UDP=m -CONFIG_6LOWPAN_GHC_ICMPV6=m -CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m -CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m -CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m CONFIG_IEEE802154=m CONFIG_IEEE802154_6LOWPAN=m CONFIG_MAC802154=m -CONFIG_NET_SCHED=y -CONFIG_NET_SCH_CBQ=m -CONFIG_NET_SCH_HTB=m -CONFIG_NET_SCH_HFSC=m -CONFIG_NET_SCH_ATM=m -CONFIG_NET_SCH_PRIO=m -CONFIG_NET_SCH_MULTIQ=m -CONFIG_NET_SCH_RED=m -CONFIG_NET_SCH_SFB=m -CONFIG_NET_SCH_SFQ=m -CONFIG_NET_SCH_TEQL=m -CONFIG_NET_SCH_TBF=m -CONFIG_NET_SCH_GRED=m -CONFIG_NET_SCH_DSMARK=m -CONFIG_NET_SCH_NETEM=m -CONFIG_NET_SCH_DRR=m -CONFIG_NET_SCH_MQPRIO=m -CONFIG_NET_SCH_CHOKE=m -CONFIG_NET_SCH_QFQ=m -CONFIG_NET_SCH_CODEL=m -CONFIG_NET_SCH_FQ_CODEL=m -CONFIG_NET_SCH_FQ=m -CONFIG_NET_SCH_HHF=m -CONFIG_NET_SCH_PIE=m -CONFIG_NET_SCH_INGRESS=m -CONFIG_NET_SCH_PLUG=m -CONFIG_NET_CLS_BASIC=m -CONFIG_NET_CLS_TCINDEX=m -CONFIG_NET_CLS_ROUTE4=m -CONFIG_NET_CLS_FW=m -CONFIG_NET_CLS_U32=m -CONFIG_CLS_U32_PERF=y -CONFIG_CLS_U32_MARK=y -CONFIG_NET_CLS_RSVP=m -CONFIG_NET_CLS_RSVP6=m -CONFIG_NET_CLS_FLOW=m -CONFIG_NET_CLS_CGROUP=m -CONFIG_NET_CLS_BPF=m -CONFIG_NET_CLS_FLOWER=m -CONFIG_NET_CLS_MATCHALL=m -CONFIG_NET_EMATCH=y -CONFIG_NET_EMATCH_CMP=m -CONFIG_NET_EMATCH_NBYTE=m -CONFIG_NET_EMATCH_U32=m -CONFIG_NET_EMATCH_META=m -CONFIG_NET_EMATCH_TEXT=m -CONFIG_NET_EMATCH_IPSET=m -CONFIG_NET_CLS_ACT=y -CONFIG_NET_ACT_POLICE=m -CONFIG_NET_ACT_GACT=m -CONFIG_GACT_PROB=y -CONFIG_NET_ACT_MIRRED=m -CONFIG_NET_ACT_SAMPLE=m -CONFIG_NET_ACT_IPT=m -CONFIG_NET_ACT_NAT=m -CONFIG_NET_ACT_PEDIT=m -CONFIG_NET_ACT_SIMP=m -CONFIG_NET_ACT_SKBEDIT=m -CONFIG_NET_ACT_CSUM=m -CONFIG_NET_ACT_VLAN=m -CONFIG_NET_ACT_BPF=m -CONFIG_NET_ACT_CONNMARK=m -CONFIG_NET_ACT_SKBMOD=m -CONFIG_NET_ACT_IFE=m -CONFIG_NET_ACT_TUNNEL_KEY=m CONFIG_DNS_RESOLVER=y CONFIG_BATMAN_ADV=m -# CONFIG_BATMAN_ADV_BATMAN_V is not set -# CONFIG_BATMAN_ADV_DAT is not set -# CONFIG_BATMAN_ADV_MCAST is not set -CONFIG_BATMAN_ADV_DEBUGFS=y +CONFIG_BATMAN_ADV_NC=y CONFIG_OPENVSWITCH=m CONFIG_VSOCKETS=m CONFIG_NETLINK_DIAG=m -CONFIG_MPLS_ROUTING=m -CONFIG_MPLS_IPTUNNEL=m CONFIG_HSR=m -CONFIG_NET_NCSI=y CONFIG_CGROUP_NET_PRIO=y CONFIG_BPF_JIT=y CONFIG_BPF_STREAM_PARSER=y @@ -495,62 +402,48 @@ CONFIG_CAN_GS_USB=m CONFIG_CAN_KVASER_USB=m CONFIG_CAN_MCBA_USB=m CONFIG_CAN_PEAK_USB=m +CONFIG_CAN_UCAN=m CONFIG_BT=m CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y CONFIG_BT_HIDP=m CONFIG_BT_HS=y CONFIG_BT_6LOWPAN=m CONFIG_BT_LEDS=y +CONFIG_BT_MSFTEXT=y CONFIG_BT_HCIBTUSB=m -CONFIG_BT_HCIBTSDIO=m +CONFIG_BT_HCIBTUSB_MTK=y CONFIG_BT_HCIUART=m -CONFIG_BT_HCIUART_BCSP=y CONFIG_BT_HCIUART_ATH3K=y +CONFIG_BT_HCIUART_LL=y CONFIG_BT_HCIUART_INTEL=y +CONFIG_BT_HCIUART_BCM=y +CONFIG_BT_HCIUART_RTL=y +CONFIG_BT_HCIUART_QCA=y CONFIG_BT_HCIUART_AG6XX=y +CONFIG_BT_HCIUART_MRVL=y CONFIG_BT_HCIBCM203X=m CONFIG_BT_HCIBPA10X=m CONFIG_BT_HCIBFUSB=m CONFIG_BT_HCIVHCI=m CONFIG_BT_MRVL=m -CONFIG_BT_MRVL_SDIO=m CONFIG_BT_ATH3K=m -CONFIG_AF_RXRPC=m -CONFIG_AF_RXRPC_IPV6=y -CONFIG_AF_KCM=m -CONFIG_CFG80211=y +CONFIG_BT_MTKUART=m +CONFIG_CFG80211=m # CONFIG_CFG80211_DEFAULT_PS is not set -CONFIG_MAC80211=y +CONFIG_MAC80211=m CONFIG_MAC80211_MESH=y -CONFIG_RFKILL=y +CONFIG_RFKILL=m CONFIG_RFKILL_INPUT=y -CONFIG_RFKILL_GPIO=m -CONFIG_CEPH_LIB=m -CONFIG_NFC=m -CONFIG_NFC_DIGITAL=m -CONFIG_NFC_NCI=m -CONFIG_NFC_NCI_UART=m -CONFIG_NFC_HCI=m -CONFIG_NFC_TRF7970A=m -CONFIG_NFC_SIM=m -CONFIG_NFC_PORT100=m -CONFIG_NFC_FDP=m -CONFIG_NFC_PN533_USB=m -CONFIG_NFC_MRVL_USB=m -CONFIG_NFC_MRVL_UART=m -CONFIG_NFC_ST_NCI_I2C=m -CONFIG_NFC_ST_NCI_SPI=m -CONFIG_NFC_NXP_NCI=m -CONFIG_NFC_ST95HF=m +CONFIG_FAILOVER=m CONFIG_PCI=y # CONFIG_PCIEASPM is not set CONFIG_PCI_MVEBU=y -CONFIG_UEVENT_HELPER=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y -CONFIG_CONNECTOR=m CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_BLOCK=y @@ -559,175 +452,177 @@ CONFIG_MTD_CFI_INTELEXT=y CONFIG_MTD_CFI_AMDSTD=y CONFIG_MTD_CFI_STAA=y CONFIG_MTD_SPI_NOR=y -CONFIG_BLK_DEV_PCIESSD_MTIP32XX=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_CRYPTOLOOP=y -CONFIG_BLK_DEV_NBD=m -CONFIG_CDROM_PKTCDVD=m +CONFIG_BLK_DEV_LOOP=m CONFIG_BLK_DEV_NVME=y -CONFIG_NVME_FC=y -CONFIG_NVME_TARGET=y -CONFIG_NVME_TARGET_LOOP=y -CONFIG_NVME_TARGET_FC=y -CONFIG_NVME_TARGET_FCLOOP=y CONFIG_EEPROM_AT24=y CONFIG_EEPROM_AT25=y CONFIG_BLK_DEV_SD=y -CONFIG_BLK_DEV_SR=m -CONFIG_CHR_DEV_SG=m -CONFIG_CHR_DEV_SCH=m CONFIG_ATA=y CONFIG_SATA_AHCI=y CONFIG_AHCI_MVEBU=y CONFIG_SATA_MV=y -CONFIG_ATA_GENERIC=m CONFIG_MD=y CONFIG_BLK_DEV_DM=m CONFIG_DM_THIN_PROVISIONING=m CONFIG_NETDEVICES=y CONFIG_BONDING=m CONFIG_DUMMY=m -CONFIG_IFB=m +CONFIG_WIREGUARD=m +CONFIG_EQUALIZER=m CONFIG_NET_TEAM=m +CONFIG_NET_TEAM_MODE_BROADCAST=m +CONFIG_NET_TEAM_MODE_ROUNDROBIN=m +CONFIG_NET_TEAM_MODE_RANDOM=m +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m +CONFIG_NET_TEAM_MODE_LOADBALANCE=m CONFIG_MACVLAN=m CONFIG_MACVTAP=m CONFIG_IPVLAN=m CONFIG_IPVTAP=m CONFIG_VXLAN=m CONFIG_GENEVE=m -CONFIG_GTP=m +CONFIG_BAREUDP=m CONFIG_MACSEC=m -CONFIG_NETCONSOLE=m CONFIG_TUN=m CONFIG_VETH=m CONFIG_NLMON=m CONFIG_NET_VRF=m -CONFIG_ARCNET=m CONFIG_NET_DSA_MV88E6XXX=m +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_ADAPTEC is not set +# CONFIG_NET_VENDOR_AGERE is not set +# CONFIG_NET_VENDOR_ALACRITECH is not set +# CONFIG_NET_VENDOR_ALTEON is not set +# CONFIG_NET_VENDOR_AMAZON is not set +# CONFIG_NET_VENDOR_AMD is not set +# CONFIG_NET_VENDOR_AQUANTIA is not set +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_ATHEROS is not set # CONFIG_NET_VENDOR_AURORA is not set -CONFIG_MV643XX_ETH=y +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_BROCADE is not set +# CONFIG_NET_VENDOR_CADENCE is not set +# CONFIG_NET_VENDOR_CAVIUM is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_CISCO is not set +# CONFIG_NET_VENDOR_CORTINA is not set +# CONFIG_NET_VENDOR_DEC is not set +# CONFIG_NET_VENDOR_DLINK is not set +# CONFIG_NET_VENDOR_EMULEX is not set +# CONFIG_NET_VENDOR_EZCHIP is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_GOOGLE is not set +# CONFIG_NET_VENDOR_HISILICON is not set +# CONFIG_NET_VENDOR_HUAWEI is not set +# CONFIG_NET_VENDOR_INTEL is not set CONFIG_MVNETA=y -CONFIG_MVPP2=y -CONFIG_LED_TRIGGER_PHY=y +# CONFIG_NET_VENDOR_MELLANOX is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_MICROSEMI is not set +# CONFIG_NET_VENDOR_MYRI is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NETERION is not set +# CONFIG_NET_VENDOR_NETRONOME is not set +# CONFIG_NET_VENDOR_NI is not set +# CONFIG_NET_VENDOR_NVIDIA is not set +# CONFIG_NET_VENDOR_OKI is not set +# CONFIG_NET_VENDOR_PACKET_ENGINES is not set +# CONFIG_NET_VENDOR_PENSANDO is not set +# CONFIG_NET_VENDOR_QLOGIC is not set +# CONFIG_NET_VENDOR_QUALCOMM is not set +# CONFIG_NET_VENDOR_RDC is not set +# CONFIG_NET_VENDOR_REALTEK is not set +# CONFIG_NET_VENDOR_RENESAS is not set +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SOLARFLARE is not set +# CONFIG_NET_VENDOR_SILAN is not set +# CONFIG_NET_VENDOR_SIS is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_SOCIONEXT is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SUN is not set +# CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_TEHUTI is not set +# CONFIG_NET_VENDOR_TI is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +# CONFIG_NET_VENDOR_XILINX is not set CONFIG_SFP=y CONFIG_MARVELL_PHY=y -CONFIG_MDIO_BITBANG=y -CONFIG_MDIO_GPIO=y -CONFIG_MDIO_BUS_MUX_GPIO=y -CONFIG_MDIO_BUS_MUX_MMIOREG=y CONFIG_PPP=m CONFIG_PPP_BSDCOMP=m CONFIG_PPP_DEFLATE=m CONFIG_PPP_FILTER=y CONFIG_PPP_MPPE=m CONFIG_PPP_MULTILINK=y -CONFIG_PPPOATM=m CONFIG_PPPOE=m -CONFIG_PPTP=m CONFIG_PPPOL2TP=m CONFIG_PPP_ASYNC=m CONFIG_PPP_SYNC_TTY=m -CONFIG_SLIP=m -CONFIG_USB_CATC=m -CONFIG_USB_KAWETH=m -CONFIG_USB_PEGASUS=m -CONFIG_USB_RTL8150=m -CONFIG_USB_RTL8152=m -CONFIG_USB_LAN78XX=m -CONFIG_USB_USBNET=y -CONFIG_USB_NET_AX8817X=m -CONFIG_USB_NET_AX88179_178A=m -CONFIG_USB_NET_CDCETHER=m +CONFIG_USB_NET_DRIVERS=m +CONFIG_USB_USBNET=m CONFIG_USB_NET_CDC_EEM=m -CONFIG_USB_NET_CDC_NCM=m CONFIG_USB_NET_HUAWEI_CDC_NCM=m CONFIG_USB_NET_CDC_MBIM=m CONFIG_USB_NET_DM9601=m CONFIG_USB_NET_SR9700=m CONFIG_USB_NET_SR9800=m CONFIG_USB_NET_SMSC75XX=m -CONFIG_USB_NET_SMSC95XX=y +CONFIG_USB_NET_SMSC95XX=m CONFIG_USB_NET_GL620A=m -CONFIG_USB_NET_NET1080=m CONFIG_USB_NET_PLUSB=m CONFIG_USB_NET_MCS7830=m -CONFIG_USB_NET_CDC_SUBSET=m -CONFIG_USB_NET_ZAURUS=m +CONFIG_USB_NET_RNDIS_HOST=m CONFIG_USB_NET_CX82310_ETH=m CONFIG_USB_NET_KALMIA=m CONFIG_USB_NET_QMI_WWAN=m -CONFIG_USB_HSO=m CONFIG_USB_NET_INT51X1=m -CONFIG_USB_CDC_PHONET=m -CONFIG_USB_IPHETH=m -CONFIG_USB_SIERRA_NET=m -CONFIG_USB_VL600=m CONFIG_USB_NET_CH9200=m -CONFIG_WIRELESS_WDS=y -CONFIG_ATH5K=m +CONFIG_USB_NET_AQC111=m +# CONFIG_WLAN_VENDOR_ADMTEK is not set CONFIG_ATH9K=m CONFIG_ATH9K_HTC=m -CONFIG_ATH9K_HWRNG=y CONFIG_CARL9170=m -CONFIG_CARL9170_HWRNG=y -CONFIG_ATH6KL=m -CONFIG_ATH6KL_SDIO=m -CONFIG_ATH6KL_USB=m CONFIG_AR5523=m -CONFIG_WIL6210=m -CONFIG_WIL6210_TRACING=y CONFIG_ATH10K=m CONFIG_ATH10K_PCI=m CONFIG_ATH10K_USB=m -CONFIG_WCN36XX=m -CONFIG_ATMEL=m +CONFIG_ATH11K=m +CONFIG_ATH11K_PCI=m CONFIG_AT76C50X_USB=m -CONFIG_B43=m -CONFIG_B43LEGACY=m CONFIG_BRCMSMAC=m CONFIG_BRCMFMAC=m +# CONFIG_BRCMFMAC_SDIO is not set CONFIG_BRCMFMAC_USB=y CONFIG_BRCMFMAC_PCIE=y +# CONFIG_WLAN_VENDOR_CISCO is not set CONFIG_IPW2100=m -CONFIG_IPW2100_MONITOR=y -CONFIG_IPW2100_DEBUG=y CONFIG_IPW2200=m -CONFIG_IPW2200_MONITOR=y -CONFIG_IPW2200_PROMISCUOUS=y -CONFIG_IPW2200_QOS=y -CONFIG_IPW2200_DEBUG=y CONFIG_IWL4965=m CONFIG_IWL3945=m CONFIG_IWLWIFI=m CONFIG_IWLDVM=m CONFIG_IWLMVM=m -CONFIG_IWLWIFI_BCAST_FILTERING=y -CONFIG_HERMES=m -CONFIG_HERMES_PRISM=y -CONFIG_PLX_HERMES=m -CONFIG_TMD_HERMES=m -CONFIG_NORTEL_HERMES=m -CONFIG_ORINOCO_USB=m -CONFIG_P54_COMMON=m -CONFIG_P54_USB=m -CONFIG_P54_PCI=m -CONFIG_P54_SPI=m -CONFIG_PRISM54=m -CONFIG_LIBERTAS=m -CONFIG_LIBERTAS_USB=m -CONFIG_LIBERTAS_SDIO=m -CONFIG_LIBERTAS_SPI=m -CONFIG_LIBERTAS_MESH=y -CONFIG_LIBERTAS_THINFIRM=m +# CONFIG_WLAN_VENDOR_INTERSIL is not set CONFIG_MWIFIEX=m -CONFIG_MWIFIEX_SDIO=m CONFIG_MWIFIEX_PCIE=m CONFIG_MWIFIEX_USB=m CONFIG_MWL8K=m +CONFIG_MT7601U=m +CONFIG_MT76x0U=m +CONFIG_MT76x0E=m +CONFIG_MT76x2E=m +CONFIG_MT76x2U=m +CONFIG_MT7603E=m +CONFIG_MT7615E=m +CONFIG_MT7663U=m +CONFIG_MT7915E=m +# CONFIG_WLAN_VENDOR_MICROCHIP is not set CONFIG_RT2X00=m -CONFIG_RT2400PCI=m -CONFIG_RT2500PCI=m -CONFIG_RT61PCI=m CONFIG_RT2800PCI=m CONFIG_RT2500USB=m CONFIG_RT73USB=m @@ -736,9 +631,7 @@ CONFIG_RT2800USB_RT3573=y CONFIG_RT2800USB_RT53XX=y CONFIG_RT2800USB_RT55XX=y CONFIG_RT2800USB_UNKNOWN=y -CONFIG_RTL8180=m CONFIG_RTL8187=m -CONFIG_RTL_CARDS=m CONFIG_RTL8192CE=m CONFIG_RTL8192SE=m CONFIG_RTL8192DE=m @@ -750,48 +643,30 @@ CONFIG_RTL8821AE=m CONFIG_RTL8192CU=m CONFIG_RTL8XXXU=m CONFIG_RTL8XXXU_UNTESTED=y +CONFIG_RTW88=m +CONFIG_RTW88_8822BE=m +CONFIG_RTW88_8822CE=m +CONFIG_RTW88_8723DE=m +CONFIG_RTW88_8821CE=m +CONFIG_RSI_91X=m +# CONFIG_RSI_SDIO is not set +# CONFIG_WLAN_VENDOR_ST is not set # CONFIG_WLAN_VENDOR_TI is not set -CONFIG_MAC80211_HWSIM=m -CONFIG_USB_NET_RNDIS_WLAN=m -CONFIG_INPUT_POLLDEV=m -CONFIG_INPUT_MOUSEDEV=m -CONFIG_INPUT_EVDEV=y -CONFIG_KEYBOARD_GPIO=y -CONFIG_INPUT_JOYSTICK=y -CONFIG_JOYSTICK_ANALOG=m -CONFIG_JOYSTICK_A3D=m -CONFIG_JOYSTICK_ADI=m -CONFIG_JOYSTICK_COBRA=m -CONFIG_JOYSTICK_GF2K=m -CONFIG_JOYSTICK_GRIP=m -CONFIG_JOYSTICK_GRIP_MP=m -CONFIG_JOYSTICK_GUILLEMOT=m -CONFIG_JOYSTICK_INTERACT=m -CONFIG_JOYSTICK_SIDEWINDER=m -CONFIG_JOYSTICK_TMDC=m -CONFIG_JOYSTICK_IFORCE=m -CONFIG_JOYSTICK_WARRIOR=m -CONFIG_JOYSTICK_MAGELLAN=m -CONFIG_JOYSTICK_SPACEORB=m -CONFIG_JOYSTICK_SPACEBALL=m -CONFIG_JOYSTICK_STINGER=m -CONFIG_JOYSTICK_TWIDJOY=m -CONFIG_JOYSTICK_ZHENHUA=m -CONFIG_JOYSTICK_AS5011=m -CONFIG_JOYSTICK_JOYDUMP=m -CONFIG_JOYSTICK_XPAD=m -CONFIG_JOYSTICK_PSXPAD_SPI=m -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_ADS7846=m +CONFIG_USB_ZD1201=m +CONFIG_ZD1211RW=m +CONFIG_QTNFMAC_PCIE=m +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +CONFIG_SERIO_LIBPS2=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_NR_UARTS=24 CONFIG_SERIAL_8250_RUNTIME_UARTS=24 CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_8250_MANY_PORTS=y CONFIG_SERIAL_8250_DW=y CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_N_GSM=m +CONFIG_SERIAL_DEV_BUS=y CONFIG_HW_RANDOM=y # CONFIG_HW_RANDOM_OMAP is not set CONFIG_HW_RANDOM_TS78XX=y @@ -800,16 +675,12 @@ CONFIG_I2C_CHARDEV=y CONFIG_I2C_GPIO=y CONFIG_I2C_MV64XXX=y CONFIG_I2C_OCORES=y -CONFIG_I2C_TINY_USB=m CONFIG_SPI=y -CONFIG_SPI_GPIO=y -CONFIG_SPI_OCORES=y +CONFIG_SPI_GPIO=m +CONFIG_SPI_OCORES=m CONFIG_SPI_ORION=y CONFIG_SPI_MUX=y CONFIG_SPI_SPIDEV=y -CONFIG_PPS=y -CONFIG_PPS_CLIENT_LDISC=y -CONFIG_PPS_CLIENT_GPIO=y CONFIG_PTP_1588_CLOCK=m CONFIG_GPIO_SYSFS=y CONFIG_GPIO_PCA953X=y @@ -817,82 +688,34 @@ CONFIG_GPIO_TS7800V2=y CONFIG_GPIO_TS7820=y CONFIG_POWER_RESET=y CONFIG_POWER_RESET_GPIO=y -CONFIG_POWER_SUPPLY_DEBUG=y -CONFIG_CHARGER_GPIO=m +CONFIG_POWER_SUPPLY=y CONFIG_SENSORS_GPIO_FAN=y +CONFIG_SENSORS_PWM_FAN=y CONFIG_THERMAL=y CONFIG_ARMADA_THERMAL=y CONFIG_WATCHDOG=y -CONFIG_WATCHDOG_SYSFS=y CONFIG_ORION_WATCHDOG=y CONFIG_TS7100_WATCHDOG=y CONFIG_MFD_TS78XX=y CONFIG_MFD_SYSCON=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_RC_CORE=y -# CONFIG_VGA_ARB is not set -CONFIG_FB=y -CONFIG_FB_FOREIGN_ENDIAN=y -CONFIG_FB_MODE_HELPERS=y -CONFIG_FB_TILEBLITTING=y -CONFIG_FB_SIMPLE=y -CONFIG_LCD_CLASS_DEVICE=m -CONFIG_SOUND=y -CONFIG_SND=y -CONFIG_SND_DUMMY=m -CONFIG_SND_ALOOP=m -CONFIG_SND_SERIAL_U16550=m -CONFIG_SND_MPU401=m +CONFIG_SOUND=m +CONFIG_SND=m +CONFIG_SND_HRTIMER=m +# CONFIG_SND_DRIVERS is not set # CONFIG_SND_PCI is not set +# CONFIG_SND_ARM is not set # CONFIG_SND_SPI is not set CONFIG_SND_USB_AUDIO=m -CONFIG_SND_USB_UA101=m -CONFIG_SND_USB_CAIAQ=m -CONFIG_SND_USB_CAIAQ_INPUT=y -CONFIG_SND_USB_6FIRE=m -CONFIG_SND_USB_HIFACE=m -CONFIG_SND_BCD2000=m -CONFIG_SND_USB_POD=m -CONFIG_SND_USB_PODHD=m -CONFIG_SND_USB_TONEPORT=m -CONFIG_SND_USB_VARIAX=m -CONFIG_SND_SOC=y -CONFIG_SND_KIRKWOOD_SOC=y -CONFIG_SND_SOC_CS42L51_I2C=y -CONFIG_SND_SOC_SPDIF=y -CONFIG_SND_SIMPLE_CARD=y -CONFIG_HID_MAGICMOUSE=m -CONFIG_HID_SONY=m -CONFIG_HID_WIIMOTE=m -CONFIG_USB_LED_TRIG=y +CONFIG_USB_HID=m CONFIG_USB=y -CONFIG_USB_LEDS_TRIGGER_USBPORT=m -CONFIG_USB_MON=m CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_MVEBU=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_ROOT_HUB_TT=y -CONFIG_USB_PRINTER=m -CONFIG_USB_TMC=m +CONFIG_USB_ACM=m CONFIG_USB_STORAGE=y -CONFIG_USB_STORAGE_REALTEK=m -CONFIG_USB_STORAGE_DATAFAB=m -CONFIG_USB_STORAGE_FREECOM=m -CONFIG_USB_STORAGE_ISD200=m -CONFIG_USB_STORAGE_USBAT=m -CONFIG_USB_STORAGE_SDDR09=m -CONFIG_USB_STORAGE_SDDR55=m -CONFIG_USB_STORAGE_JUMPSHOT=m -CONFIG_USB_STORAGE_ALAUDA=m -CONFIG_USB_STORAGE_ONETOUCH=m -CONFIG_USB_STORAGE_KARMA=m -CONFIG_USB_STORAGE_CYPRESS_ATACB=m -CONFIG_USB_STORAGE_ENE_UB6250=m -CONFIG_USB_UAS=m -CONFIG_USBIP_CORE=m -CONFIG_USBIP_VHCI_HCD=m -CONFIG_USBIP_HOST=m CONFIG_USB_SERIAL=m CONFIG_USB_SERIAL_GENERIC=y CONFIG_USB_SERIAL_SIMPLE=m @@ -932,7 +755,6 @@ CONFIG_USB_SERIAL_QCAUX=m CONFIG_USB_SERIAL_QUALCOMM=m CONFIG_USB_SERIAL_SPCP8X5=m CONFIG_USB_SERIAL_SAFE=m -CONFIG_USB_SERIAL_SAFE_PADDED=y CONFIG_USB_SERIAL_SIERRAWIRELESS=m CONFIG_USB_SERIAL_SYMBOL=m CONFIG_USB_SERIAL_TI=m @@ -946,30 +768,6 @@ CONFIG_USB_SERIAL_WISHBONE=m CONFIG_USB_SERIAL_SSU100=m CONFIG_USB_SERIAL_QT2=m CONFIG_USB_SERIAL_UPD78F0730=m -CONFIG_USB_SERIAL_DEBUG=m -CONFIG_USB_EMI62=m -CONFIG_USB_EMI26=m -CONFIG_USB_ADUTUX=m -CONFIG_USB_SEVSEG=m -CONFIG_USB_LEGOTOWER=m -CONFIG_USB_LCD=m -CONFIG_USB_CYPRESS_CY7C63=m -CONFIG_USB_CYTHERM=m -CONFIG_USB_IDMOUSE=m -CONFIG_USB_FTDI_ELAN=m -CONFIG_USB_APPLEDISPLAY=m -CONFIG_USB_SISUSBVGA=m -CONFIG_USB_LD=m -CONFIG_USB_TRANCEVIBRATOR=m -CONFIG_USB_IOWARRIOR=m -CONFIG_USB_TEST=m -CONFIG_USB_EHSET_TEST_FIXTURE=m -CONFIG_USB_ISIGHTFW=m -CONFIG_USB_YUREX=m -CONFIG_USB_HUB_USB251XB=m -CONFIG_USB_LINK_LAYER_TEST=m -CONFIG_USB_CHAOSKEY=m -CONFIG_USB_ATM=m CONFIG_NOP_USB_XCEIV=y CONFIG_MMC=y CONFIG_TS_SDCARD=y @@ -982,110 +780,74 @@ CONFIG_LEDS_GPIO=y CONFIG_LEDS_TRIGGER_TIMER=y CONFIG_LEDS_TRIGGER_ONESHOT=m CONFIG_LEDS_TRIGGER_DISK=y -CONFIG_LEDS_TRIGGER_MTD=y CONFIG_LEDS_TRIGGER_HEARTBEAT=y -CONFIG_LEDS_TRIGGER_BACKLIGHT=m CONFIG_LEDS_TRIGGER_CPU=y -CONFIG_LEDS_TRIGGER_ACTIVITY=y +CONFIG_LEDS_TRIGGER_ACTIVITY=m CONFIG_LEDS_TRIGGER_GPIO=m -CONFIG_LEDS_TRIGGER_DEFAULT_ON=m +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y CONFIG_LEDS_TRIGGER_TRANSIENT=m -CONFIG_LEDS_TRIGGER_CAMERA=m CONFIG_LEDS_TRIGGER_PANIC=y -CONFIG_LEDS_TRIGGER_NETDEV=y -CONFIG_LEDS_TRIGGER_PATTERN=y -CONFIG_LEDS_TRIGGER_AUDIO=y +CONFIG_LEDS_TRIGGER_NETDEV=m +CONFIG_LEDS_TRIGGER_PATTERN=m CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_DS1307=y -CONFIG_RTC_DRV_PCF8563=y -CONFIG_RTC_DRV_S35390A=y -CONFIG_RTC_DRV_MV=y -CONFIG_RTC_DRV_ARMADA38X=y CONFIG_DMADEVICES=y CONFIG_MV_XOR=y -CONFIG_UIO=y -CONFIG_UIO_PDRV_GENIRQ=y -CONFIG_UIO_DMEM_GENIRQ=m -CONFIG_UIO_PCI_GENERIC=m -CONFIG_STAGING=y +# CONFIG_VIRTIO_MENU is not set +# CONFIG_VHOST_MENU is not set # CONFIG_IOMMU_SUPPORT is not set CONFIG_MEMORY=y -CONFIG_IIO=y -CONFIG_IIO_BUFFER_CB=m -CONFIG_IIO_BUFFER_DMAENGINE=m -CONFIG_IIO_BUFFER_HW_CONSUMER=m -CONFIG_IIO_SW_DEVICE=m -CONFIG_IIO_SW_TRIGGER=m -CONFIG_IIO_TRIGGERED_EVENT=m +CONFIG_IIO=m CONFIG_MMA8452=m -CONFIG_TS_SIMPLEADC=y +CONFIG_TS_SIMPLEADC=m CONFIG_IIO_RESCALE=m -CONFIG_IIO_MUX=m -CONFIG_VL53L0X_I2C=m CONFIG_PWM=y -CONFIG_PWM_DEBUG=y -CONFIG_PWM_TS=y -CONFIG_RAS=y -CONFIG_FPGA=m -CONFIG_MUX_GPIO=y -CONFIG_EXT4_FS=y -CONFIG_EXT4_FS_POSIX_ACL=y -CONFIG_EXT4_FS_SECURITY=y -CONFIG_REISERFS_FS=m -CONFIG_REISERFS_FS_XATTR=y -CONFIG_REISERFS_FS_POSIX_ACL=y -CONFIG_REISERFS_FS_SECURITY=y -CONFIG_JFS_FS=m -CONFIG_JFS_POSIX_ACL=y -CONFIG_XFS_FS=m -CONFIG_XFS_POSIX_ACL=y -CONFIG_GFS2_FS=m -CONFIG_BTRFS_FS=m -CONFIG_BTRFS_FS_POSIX_ACL=y -CONFIG_NILFS2_FS=m -CONFIG_F2FS_FS=m -CONFIG_FS_ENCRYPTION=y -CONFIG_FANOTIFY=y -CONFIG_AUTOFS4_FS=y -CONFIG_FUSE_FS=m -CONFIG_OVERLAY_FS=y -CONFIG_ISO9660_FS=y -CONFIG_JOLIET=y -CONFIG_UDF_FS=m +CONFIG_PWM_TS=m +CONFIG_PHY_MVEBU_A38X_COMPHY=y +CONFIG_MUX_GPIO=m +CONFIG_SLIMBUS=m +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_F2FS_FS=y +CONFIG_F2FS_FS_SECURITY=y +CONFIG_AUTOFS_FS=m +CONFIG_OVERLAY_FS=m CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y -CONFIG_NTFS_FS=y +CONFIG_EXFAT_FS=y +CONFIG_NTFS_FS=m CONFIG_NTFS_RW=y CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y -CONFIG_CONFIGFS_FS=y -CONFIG_EFIVAR_FS=y +# CONFIG_MISC_FILESYSTEMS is not set CONFIG_NFS_FS=y CONFIG_ROOT_NFS=y -CONFIG_RPCSEC_GSS_KRB5=m +CONFIG_CIFS=m CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_CODEPAGE_850=y -CONFIG_NLS_ASCII=y CONFIG_NLS_ISO8859_1=y CONFIG_NLS_ISO8859_2=y CONFIG_NLS_UTF8=y CONFIG_CRYPTO_ECDH=y -CONFIG_CRYPTO_SEQIV=y -CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_CMAC=y +CONFIG_CRYPTO_AES=y CONFIG_CRYPTO_DEFLATE=y CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_ZSTD=y CONFIG_CRYPTO_DEV_MARVELL_CESA=y -CONFIG_CRC_ITU_T=y -CONFIG_CRC7=y -CONFIG_DMA_CMA=y +CONFIG_CRC7=m CONFIG_PRINTK_TIME=y -CONFIG_DYNAMIC_DEBUG=y -# CONFIG_ENABLE_MUST_CHECK is not set CONFIG_DEBUG_FS=y # CONFIG_DEBUG_MISC is not set -CONFIG_SOFTLOCKUP_DETECTOR=y -CONFIG_WQ_WATCHDOG=y -# CONFIG_SCHED_DEBUG is not set # CONFIG_DEBUG_PREEMPT is not set +CONFIG_STACKTRACE=y +# CONFIG_FTRACE is not set CONFIG_DEBUG_USER=y # CONFIG_RUNTIME_TESTING_MENU is not set diff --git a/arch/arm/configs/tsa38x_minimal_defconfig b/arch/arm/configs/tsa38x_minimal_defconfig index 7939e894e43a4..3145255a7eb7f 100644 --- a/arch/arm/configs/tsa38x_minimal_defconfig +++ b/arch/arm/configs/tsa38x_minimal_defconfig @@ -5,6 +5,7 @@ CONFIG_HIGH_RES_TIMERS=y CONFIG_PREEMPT=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_CGROUPS=y +CONFIG_NAMESPACES=y CONFIG_BLK_DEV_INITRD=y # CONFIG_RD_BZIP2 is not set # CONFIG_RD_LZMA is not set @@ -19,17 +20,20 @@ CONFIG_ARCH_MVEBU=y CONFIG_MACH_ARMADA_38X=y CONFIG_ARM_THUMBEE=y CONFIG_SMP=y -CONFIG_HIGHMEM=y +CONFIG_HZ_1000=y CONFIG_ARM_APPENDED_DTB=y CONFIG_ARM_ATAG_DTB_COMPAT=y CONFIG_CPU_FREQ=y CONFIG_CPUFREQ_DT=y CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_MENU=y CONFIG_ARM_MVEBU_V7_CPUIDLE=y CONFIG_VFP=y CONFIG_NEON=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_COMPRESS=y +CONFIG_MODULE_COMPRESS_XZ=y # CONFIG_MQ_IOSCHED_KYBER is not set CONFIG_BINFMT_MISC=y # CONFIG_COMPACTION is not set @@ -39,7 +43,6 @@ CONFIG_UNIX=y CONFIG_INET=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y # CONFIG_IPV6 is not set CONFIG_NET_DSA=y CONFIG_VLAN_8021Q=y @@ -48,8 +51,7 @@ CONFIG_CAN_SJA1000=m CONFIG_CAN_SJA1000_ISA=m CONFIG_CAN_SJA1000_PLATFORM=m CONFIG_BT=m -CONFIG_BT_MRVL=m -CONFIG_BT_MRVL_SDIO=m +CONFIG_BT_HCIUART=m CONFIG_CFG80211=m # CONFIG_CFG80211_DEFAULT_PS is not set CONFIG_MAC80211=m @@ -65,11 +67,11 @@ CONFIG_MTD_CFI=y CONFIG_MTD_CFI_INTELEXT=y CONFIG_MTD_CFI_AMDSTD=y CONFIG_MTD_CFI_STAA=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_NAND_MARVELL=y CONFIG_MTD_SPI_NOR=y +CONFIG_BLK_DEV_LOOP=m CONFIG_BLK_DEV_NVME=y CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_AT25=y CONFIG_BLK_DEV_SD=y CONFIG_ATA=y CONFIG_SATA_AHCI=y @@ -195,7 +197,7 @@ CONFIG_SPI_GPIO=m CONFIG_SPI_OCORES=m CONFIG_SPI_ORION=y CONFIG_SPI_MUX=y -CONFIG_SPI_SPIDEV=m +CONFIG_SPI_SPIDEV=y CONFIG_PTP_1588_CLOCK=m CONFIG_GPIO_SYSFS=y CONFIG_GPIO_PCA953X=y @@ -215,7 +217,6 @@ CONFIG_MFD_TS78XX=y CONFIG_MFD_SYSCON=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y -# CONFIG_VGA_ARB is not set CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_MVEBU=y @@ -237,7 +238,7 @@ CONFIG_LEDS_CLASS=y CONFIG_LEDS_GPIO=y CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_TIMER=y -CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_DS1307=y CONFIG_DMADEVICES=y @@ -277,9 +278,8 @@ CONFIG_CRYPTO_ZSTD=y CONFIG_CRYPTO_DEV_MARVELL_CESA=y CONFIG_CRC_ITU_T=m CONFIG_CRC7=m -CONFIG_PRINTK_TIME=y -# CONFIG_DEBUG_BUGVERBOSE is not set # CONFIG_DEBUG_MISC is not set -# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_PREEMPT is not set +# CONFIG_FTRACE is not set CONFIG_DEBUG_USER=y # CONFIG_RUNTIME_TESTING_MENU is not set diff --git a/arch/arm/configs/tsimx28_defconfig b/arch/arm/configs/tsimx28_defconfig index 9f8618338cb51..5d77a03d434e7 100644 --- a/arch/arm/configs/tsimx28_defconfig +++ b/arch/arm/configs/tsimx28_defconfig @@ -1,6 +1,7 @@ CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y -CONFIG_NO_HZ=y +# CONFIG_CROSS_MEMORY_ATTACH is not set +CONFIG_NO_HZ_IDLE=y CONFIG_HIGH_RES_TIMERS=y CONFIG_PREEMPT=y CONFIG_TASKSTATS=y @@ -8,19 +9,14 @@ CONFIG_TASK_DELAY_ACCT=y CONFIG_TASK_XACCT=y CONFIG_TASK_IO_ACCOUNTING=y CONFIG_PSI=y -CONFIG_IKCONFIG=m -CONFIG_IKCONFIG_PROC=y CONFIG_CGROUPS=y CONFIG_MEMCG=y -CONFIG_BLK_CGROUP=y CONFIG_CGROUP_SCHED=y CONFIG_CFS_BANDWIDTH=y CONFIG_CGROUP_PIDS=y -CONFIG_CGROUP_RDMA=y CONFIG_CGROUP_FREEZER=y CONFIG_CGROUP_DEVICE=y CONFIG_CGROUP_CPUACCT=y -CONFIG_CGROUP_PERF=y CONFIG_CGROUP_BPF=y CONFIG_USER_NS=y CONFIG_CHECKPOINT_RESTORE=y @@ -30,8 +26,11 @@ CONFIG_BLK_DEV_INITRD=y CONFIG_BPF_SYSCALL=y CONFIG_PERF_EVENTS=y # CONFIG_COMPAT_BRK is not set +CONFIG_SLAB=y +# CONFIG_SLAB_MERGE_DEFAULT is not set # CONFIG_ARCH_MULTI_V7 is not set CONFIG_ARCH_MXS=y +CONFIG_HZ_1000=y CONFIG_AEABI=y CONFIG_EFI=y CONFIG_MODULES=y @@ -39,6 +38,8 @@ CONFIG_MODULE_FORCE_LOAD=y CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y CONFIG_MODVERSIONS=y +CONFIG_MODULE_COMPRESS=y +CONFIG_MODULE_COMPRESS_XZ=y CONFIG_UNUSED_SYMBOLS=y CONFIG_BLK_DEV_INTEGRITY=y CONFIG_BINFMT_MISC=y @@ -52,20 +53,18 @@ CONFIG_TLS=m CONFIG_XFRM_USER=m CONFIG_XFRM_INTERFACE=m CONFIG_XFRM_SUB_POLICY=y -CONFIG_XFRM_STATISTICS=y CONFIG_NET_KEY=m CONFIG_NET_KEY_MIGRATE=y +CONFIG_XDP_SOCKETS=y +CONFIG_XDP_SOCKETS_DIAG=m CONFIG_INET=y CONFIG_IP_MULTICAST=y CONFIG_IP_ADVANCED_ROUTER=y -CONFIG_IP_FIB_TRIE_STATS=y CONFIG_IP_MULTIPLE_TABLES=y CONFIG_IP_ROUTE_MULTIPATH=y CONFIG_IP_ROUTE_VERBOSE=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y CONFIG_NET_IPIP=m CONFIG_NET_IPGRE_DEMUX=m CONFIG_NET_IPGRE=m @@ -75,18 +74,32 @@ CONFIG_IP_MROUTE_MULTIPLE_TABLES=y CONFIG_IP_PIMSM_V1=y CONFIG_IP_PIMSM_V2=y CONFIG_NET_IPVTI=m +CONFIG_NET_FOU_IP_TUNNELS=y CONFIG_INET_AH=m CONFIG_INET_ESP=m +CONFIG_INET_ESPINTCP=y CONFIG_INET_IPCOMP=m -CONFIG_INET_DIAG=m CONFIG_INET_UDP_DIAG=m CONFIG_INET_RAW_DIAG=m +CONFIG_INET_DIAG_DESTROY=y +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_TCP_CONG_HSTCP=m +CONFIG_TCP_CONG_HYBLA=m +CONFIG_TCP_CONG_NV=m +CONFIG_TCP_CONG_SCALABLE=m +CONFIG_TCP_CONG_LP=m +CONFIG_TCP_CONG_VENO=m +CONFIG_TCP_CONG_YEAH=m +CONFIG_TCP_CONG_ILLINOIS=m +CONFIG_TCP_CONG_DCTCP=m +CONFIG_TCP_CONG_CDG=m +CONFIG_TCP_CONG_BBR=m +CONFIG_TCP_MD5SIG=y CONFIG_IPV6_ROUTER_PREF=y CONFIG_IPV6_ROUTE_INFO=y CONFIG_IPV6_OPTIMISTIC_DAD=y CONFIG_INET6_AH=m CONFIG_INET6_ESP=m -CONFIG_INET6_ESP_OFFLOAD=m CONFIG_INET6_ESPINTCP=y CONFIG_INET6_IPCOMP=m CONFIG_IPV6_MIP6=m @@ -103,11 +116,17 @@ CONFIG_IPV6_SEG6_LWTUNNEL=y CONFIG_IPV6_SEG6_HMAC=y CONFIG_IPV6_RPL_LWTUNNEL=y CONFIG_MPTCP=y -CONFIG_NETWORK_PHY_TIMESTAMPING=y +CONFIG_NETWORK_SECMARK=y CONFIG_NETFILTER=y CONFIG_BRIDGE_NETFILTER=m CONFIG_NF_CONNTRACK=m CONFIG_NF_LOG_NETDEV=m +CONFIG_NF_CONNTRACK_SECMARK=y +CONFIG_NF_CONNTRACK_ZONES=y +CONFIG_NF_CONNTRACK_PROCFS=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_TIMEOUT=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y CONFIG_NF_CONNTRACK_AMANDA=m CONFIG_NF_CONNTRACK_FTP=m CONFIG_NF_CONNTRACK_H323=m @@ -119,6 +138,9 @@ CONFIG_NF_CONNTRACK_SANE=m CONFIG_NF_CONNTRACK_SIP=m CONFIG_NF_CONNTRACK_TFTP=m CONFIG_NF_CT_NETLINK=m +CONFIG_NF_CT_NETLINK_TIMEOUT=m +CONFIG_NF_CT_NETLINK_HELPER=m +CONFIG_NETFILTER_NETLINK_GLUE_CT=y CONFIG_NF_TABLES=m CONFIG_NF_TABLES_INET=y CONFIG_NF_TABLES_NETDEV=y @@ -139,6 +161,7 @@ CONFIG_NFT_QUOTA=m CONFIG_NFT_REJECT=m CONFIG_NFT_COMPAT=m CONFIG_NFT_HASH=m +CONFIG_NFT_FIB_INET=m CONFIG_NFT_XFRM=m CONFIG_NFT_SOCKET=m CONFIG_NFT_OSF=m @@ -146,12 +169,15 @@ CONFIG_NFT_TPROXY=m CONFIG_NFT_SYNPROXY=m CONFIG_NFT_DUP_NETDEV=m CONFIG_NFT_FWD_NETDEV=m +CONFIG_NFT_FIB_NETDEV=m CONFIG_NF_FLOW_TABLE_INET=m CONFIG_NF_FLOW_TABLE=m CONFIG_NETFILTER_XT_SET=m CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m +CONFIG_NETFILTER_XT_TARGET_CT=m CONFIG_NETFILTER_XT_TARGET_DSCP=m CONFIG_NETFILTER_XT_TARGET_HMARK=m CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m @@ -160,10 +186,10 @@ CONFIG_NETFILTER_XT_TARGET_LOG=m CONFIG_NETFILTER_XT_TARGET_MARK=m CONFIG_NETFILTER_XT_TARGET_NFLOG=m CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m -CONFIG_NETFILTER_XT_TARGET_NOTRACK=m CONFIG_NETFILTER_XT_TARGET_TEE=m CONFIG_NETFILTER_XT_TARGET_TPROXY=m CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFILTER_XT_TARGET_SECMARK=m CONFIG_NETFILTER_XT_TARGET_TCPMSS=m CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m @@ -177,7 +203,6 @@ CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m CONFIG_NETFILTER_XT_MATCH_CONNMARK=m CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m CONFIG_NETFILTER_XT_MATCH_CPU=m -CONFIG_NETFILTER_XT_MATCH_DCCP=m CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m CONFIG_NETFILTER_XT_MATCH_DSCP=m CONFIG_NETFILTER_XT_MATCH_ESP=m @@ -228,6 +253,7 @@ CONFIG_IP_SET_HASH_NETIFACE=m CONFIG_IP_SET_LIST_SET=m CONFIG_IP_VS=m CONFIG_IP_VS_IPV6=y +CONFIG_IP_VS_DEBUG=y CONFIG_IP_VS_PROTO_TCP=y CONFIG_IP_VS_PROTO_UDP=y CONFIG_IP_VS_PROTO_ESP=y @@ -246,6 +272,8 @@ CONFIG_IP_VS_SH=m CONFIG_IP_VS_MH=m CONFIG_IP_VS_SED=m CONFIG_IP_VS_NQ=m +CONFIG_IP_VS_FTP=m +CONFIG_IP_VS_PE_SIP=m CONFIG_NFT_DUP_IPV4=m CONFIG_NFT_FIB_IPV4=m CONFIG_NF_TABLES_ARP=y @@ -321,6 +349,9 @@ CONFIG_BRIDGE_EBT_SNAT=m CONFIG_BRIDGE_EBT_LOG=m CONFIG_BRIDGE_EBT_NFLOG=m CONFIG_BPFILTER=y +CONFIG_IP_DCCP=m +CONFIG_RDS=m +CONFIG_RDS_TCP=m CONFIG_L2TP=m CONFIG_L2TP_V3=y CONFIG_L2TP_IP=m @@ -328,20 +359,39 @@ CONFIG_L2TP_ETH=m CONFIG_BRIDGE=m CONFIG_BRIDGE_VLAN_FILTERING=y CONFIG_BRIDGE_MRP=y -CONFIG_NET_DSA=m CONFIG_VLAN_8021Q=m +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_VLAN_8021Q_MVRP=y +CONFIG_LLC2=m CONFIG_6LOWPAN=m +CONFIG_IEEE802154=m +CONFIG_IEEE802154_6LOWPAN=m +CONFIG_MAC802154=m CONFIG_DNS_RESOLVER=y CONFIG_BATMAN_ADV=m +CONFIG_BATMAN_ADV_NC=y +CONFIG_OPENVSWITCH=m +CONFIG_VSOCKETS=m CONFIG_NETLINK_DIAG=m -CONFIG_NET_NCSI=y +CONFIG_HSR=m CONFIG_CGROUP_NET_PRIO=y CONFIG_BPF_JIT=y +CONFIG_BPF_STREAM_PARSER=y CONFIG_CAN=m CONFIG_CAN_J1939=m CONFIG_CAN_ISOTP=m CONFIG_CAN_VCAN=m +CONFIG_CAN_VXCAN=m +CONFIG_CAN_SLCAN=m CONFIG_CAN_FLEXCAN=m +CONFIG_CAN_8DEV_USB=m +CONFIG_CAN_EMS_USB=m +CONFIG_CAN_ESD_USB2=m +CONFIG_CAN_GS_USB=m +CONFIG_CAN_KVASER_USB=m +CONFIG_CAN_MCBA_USB=m +CONFIG_CAN_PEAK_USB=m +CONFIG_CAN_UCAN=m CONFIG_BT=m CONFIG_BT_RFCOMM=m CONFIG_BT_RFCOMM_TTY=y @@ -349,19 +399,35 @@ CONFIG_BT_BNEP=m CONFIG_BT_BNEP_MC_FILTER=y CONFIG_BT_BNEP_PROTO_FILTER=y CONFIG_BT_HIDP=m +CONFIG_BT_HS=y CONFIG_BT_6LOWPAN=m +CONFIG_BT_LEDS=y +CONFIG_BT_MSFTEXT=y CONFIG_BT_HCIBTUSB=m +CONFIG_BT_HCIBTUSB_MTK=y CONFIG_BT_HCIUART=m -CONFIG_BT_HCIUART_BCSP=y CONFIG_BT_HCIUART_ATH3K=y +CONFIG_BT_HCIUART_LL=y +CONFIG_BT_HCIUART_INTEL=y +CONFIG_BT_HCIUART_BCM=y +CONFIG_BT_HCIUART_RTL=y +CONFIG_BT_HCIUART_QCA=y +CONFIG_BT_HCIUART_AG6XX=y +CONFIG_BT_HCIUART_MRVL=y CONFIG_BT_HCIBCM203X=m CONFIG_BT_HCIBPA10X=m CONFIG_BT_HCIBFUSB=m CONFIG_BT_HCIVHCI=m +CONFIG_BT_MRVL=m +CONFIG_BT_ATH3K=m +CONFIG_BT_MTKUART=m CONFIG_CFG80211=m # CONFIG_CFG80211_DEFAULT_PS is not set CONFIG_CFG80211_WEXT=y CONFIG_MAC80211=m +CONFIG_MAC80211_MESH=y +CONFIG_RFKILL=m +CONFIG_FAILOVER=m CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_GNSS=y @@ -380,14 +446,28 @@ CONFIG_MD=y CONFIG_BLK_DEV_DM=m CONFIG_DM_THIN_PROVISIONING=m CONFIG_NETDEVICES=y +CONFIG_BONDING=m CONFIG_DUMMY=m CONFIG_WIREGUARD=m +CONFIG_EQUALIZER=m +CONFIG_NET_TEAM=m +CONFIG_NET_TEAM_MODE_BROADCAST=m +CONFIG_NET_TEAM_MODE_ROUNDROBIN=m +CONFIG_NET_TEAM_MODE_RANDOM=m +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m +CONFIG_NET_TEAM_MODE_LOADBALANCE=m CONFIG_MACVLAN=m +CONFIG_MACVTAP=m CONFIG_IPVLAN=m +CONFIG_IPVTAP=m CONFIG_VXLAN=m +CONFIG_GENEVE=m +CONFIG_BAREUDP=m +CONFIG_MACSEC=m CONFIG_TUN=m CONFIG_VETH=m -CONFIG_NET_DSA_MV88E6XXX=m +CONFIG_NLMON=m +CONFIG_NET_VRF=m # CONFIG_NET_VENDOR_ALACRITECH is not set # CONFIG_NET_VENDOR_AMAZON is not set # CONFIG_NET_VENDOR_AQUANTIA is not set @@ -426,6 +506,7 @@ CONFIG_NET_DSA_MV88E6XXX=m # CONFIG_NET_VENDOR_VIA is not set # CONFIG_NET_VENDOR_WIZNET is not set # CONFIG_NET_VENDOR_XILINX is not set +CONFIG_MICROCHIP_PHY=m CONFIG_SMSC_PHY=y CONFIG_PPP=m CONFIG_PPP_BSDCOMP=m @@ -434,16 +515,10 @@ CONFIG_PPP_FILTER=y CONFIG_PPP_MPPE=m CONFIG_PPP_MULTILINK=y CONFIG_PPPOE=m -CONFIG_PPTP=m CONFIG_PPPOL2TP=m CONFIG_PPP_ASYNC=m CONFIG_PPP_SYNC_TTY=m -CONFIG_USB_CATC=m -CONFIG_USB_KAWETH=m -CONFIG_USB_PEGASUS=m -CONFIG_USB_RTL8150=m -CONFIG_USB_RTL8152=m -CONFIG_USB_LAN78XX=m +CONFIG_USB_NET_DRIVERS=m CONFIG_USB_USBNET=m CONFIG_USB_NET_CDC_EEM=m CONFIG_USB_NET_HUAWEI_CDC_NCM=m @@ -461,28 +536,27 @@ CONFIG_USB_NET_CX82310_ETH=m CONFIG_USB_NET_KALMIA=m CONFIG_USB_NET_QMI_WWAN=m CONFIG_USB_NET_INT51X1=m -CONFIG_USB_IPHETH=m -CONFIG_USB_SIERRA_NET=m -CONFIG_USB_VL600=m CONFIG_USB_NET_CH9200=m CONFIG_USB_NET_AQC111=m # CONFIG_WLAN_VENDOR_ADMTEK is not set -CONFIG_ATH9K=m CONFIG_ATH9K_HTC=m CONFIG_CARL9170=m -CONFIG_ATH6KL=m -CONFIG_ATH6KL_USB=m CONFIG_AR5523=m CONFIG_ATH10K=m CONFIG_ATH10K_USB=m -CONFIG_WCN36XX=m CONFIG_AT76C50X_USB=m -# CONFIG_WLAN_VENDOR_BROADCOM is not set +CONFIG_BRCMFMAC=m +# CONFIG_BRCMFMAC_SDIO is not set +CONFIG_BRCMFMAC_USB=y # CONFIG_WLAN_VENDOR_CISCO is not set # CONFIG_WLAN_VENDOR_INTEL is not set # CONFIG_WLAN_VENDOR_INTERSIL is not set -# CONFIG_WLAN_VENDOR_MARVELL is not set -# CONFIG_WLAN_VENDOR_MEDIATEK is not set +CONFIG_MWIFIEX=m +CONFIG_MWIFIEX_USB=m +CONFIG_MT7601U=m +CONFIG_MT76x0U=m +CONFIG_MT76x2U=m +CONFIG_MT7663U=m # CONFIG_WLAN_VENDOR_MICROCHIP is not set CONFIG_RT2X00=m CONFIG_RT2500USB=m @@ -492,18 +566,18 @@ CONFIG_RT2800USB_RT3573=y CONFIG_RT2800USB_RT53XX=y CONFIG_RT2800USB_RT55XX=y CONFIG_RT2800USB_UNKNOWN=y +CONFIG_RTL8187=m CONFIG_RTL8192CU=m CONFIG_RTL8XXXU=m CONFIG_RTL8XXXU_UNTESTED=y -# CONFIG_WLAN_VENDOR_RSI is not set +CONFIG_RSI_91X=m +# CONFIG_RSI_SDIO is not set # CONFIG_WLAN_VENDOR_ST is not set CONFIG_WL12XX=m CONFIG_WLCORE_SDIO=m CONFIG_USB_ZD1201=m CONFIG_ZD1211RW=m -CONFIG_INPUT_MOUSEDEV=m -CONFIG_INPUT_JOYDEV=m -CONFIG_INPUT_EVDEV=m +# CONFIG_WLAN_VENDOR_QUANTENNA is not set # CONFIG_INPUT_KEYBOARD is not set # CONFIG_INPUT_MOUSE is not set # CONFIG_SERIO is not set @@ -521,29 +595,21 @@ CONFIG_I2C_MXS=y CONFIG_SPI=y CONFIG_SPI_GPIO=m CONFIG_SPI_MXS=y -CONFIG_SPI_SPIDEV=m +CONFIG_SPI_SPIDEV=y CONFIG_PPS_CLIENT_GPIO=m +CONFIG_PTP_1588_CLOCK=m CONFIG_GPIO_SYSFS=y -CONFIG_HWMON=m CONFIG_WATCHDOG=y CONFIG_TS_WDT_MICRO=y CONFIG_MFD_MXS_LRADC=m CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_SOUND=y -CONFIG_SND=y +CONFIG_SOUND=m +CONFIG_SND=m +CONFIG_SND_HRTIMER=m # CONFIG_SND_ARM is not set # CONFIG_SND_SPI is not set CONFIG_SND_USB_AUDIO=m -CONFIG_SND_USB_UA101=m -CONFIG_SND_USB_CAIAQ=m -CONFIG_SND_USB_6FIRE=m -CONFIG_SND_USB_HIFACE=m -CONFIG_SND_BCD2000=m -CONFIG_SND_USB_POD=m -CONFIG_SND_USB_PODHD=m -CONFIG_SND_USB_TONEPORT=m -CONFIG_SND_USB_VARIAX=m # CONFIG_HID_A4TECH is not set # CONFIG_HID_APPLE is not set # CONFIG_HID_BELKIN is not set @@ -555,12 +621,14 @@ CONFIG_SND_USB_VARIAX=m # CONFIG_HID_LOGITECH is not set # CONFIG_HID_MICROSOFT is not set # CONFIG_HID_MONTEREY is not set +CONFIG_USB_HID=m CONFIG_USB=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y CONFIG_USB_OTG=y CONFIG_USB_OTG_FSM=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y +CONFIG_USB_ACM=m CONFIG_USB_STORAGE=y CONFIG_USB_CHIPIDEA=y CONFIG_USB_CHIPIDEA_UDC=y @@ -617,7 +685,6 @@ CONFIG_USB_SERIAL_WISHBONE=m CONFIG_USB_SERIAL_SSU100=m CONFIG_USB_SERIAL_QT2=m CONFIG_USB_SERIAL_UPD78F0730=m -CONFIG_USB_SERIAL_DEBUG=m CONFIG_USB_MXS_PHY=y CONFIG_USB_GADGET=y CONFIG_USB_CONFIGFS=m @@ -639,6 +706,7 @@ CONFIG_USB_CONFIGFS_F_HID=y CONFIG_USB_CONFIGFS_F_PRINTER=y CONFIG_USB_ZERO=m CONFIG_USB_ETH=m +CONFIG_USB_G_NCM=m CONFIG_USB_GADGETFS=m CONFIG_USB_FUNCTIONFS=m CONFIG_USB_MASS_STORAGE=m @@ -650,6 +718,7 @@ CONFIG_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_MXS=y +CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y CONFIG_LEDS_GPIO=y CONFIG_LEDS_TRIGGER_TIMER=y @@ -657,14 +726,20 @@ CONFIG_LEDS_TRIGGER_ONESHOT=y CONFIG_LEDS_TRIGGER_HEARTBEAT=y CONFIG_LEDS_TRIGGER_BACKLIGHT=y CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_ACTIVITY=m CONFIG_LEDS_TRIGGER_GPIO=y CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_LEDS_TRIGGER_TRANSIENT=m CONFIG_LEDS_TRIGGER_PANIC=y +CONFIG_LEDS_TRIGGER_NETDEV=m +CONFIG_LEDS_TRIGGER_PATTERN=m CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_DS1307=y CONFIG_RTC_DRV_ISL12022=m CONFIG_DMADEVICES=y CONFIG_MXS_DMA=y +# CONFIG_VIRTIO_MENU is not set +# CONFIG_VHOST_MENU is not set CONFIG_COMMON_CLK_PWM=y CONFIG_IIO=m CONFIG_MMA8452=m @@ -672,21 +747,26 @@ CONFIG_MXS_LRADC_ADC=m CONFIG_PWM=y CONFIG_PWM_MXS=y CONFIG_NVMEM_MXS_OCOTP=m -CONFIG_EXT4_FS=y -CONFIG_EXT4_FS_POSIX_ACL=y -CONFIG_EXT4_FS_SECURITY=y +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_F2FS_FS=y +CONFIG_F2FS_FS_SECURITY=y +# CONFIG_DNOTIFY is not set CONFIG_FANOTIFY=y CONFIG_AUTOFS4_FS=y -CONFIG_FUSE_FS=m -CONFIG_CUSE=m CONFIG_OVERLAY_FS=m -CONFIG_MSDOS_FS=m CONFIG_VFAT_FS=y -CONFIG_EXFAT_FS=m +CONFIG_EXFAT_FS=y CONFIG_NTFS_FS=m CONFIG_NTFS_RW=y CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y +# CONFIG_MISC_FILESYSTEMS is not set CONFIG_NFS_FS=y CONFIG_NFS_V3_ACL=y CONFIG_ROOT_NFS=y @@ -695,6 +775,7 @@ CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_CODEPAGE_850=y CONFIG_NLS_ISO8859_1=y CONFIG_NLS_ISO8859_15=y +CONFIG_CRYPTO_GCM=y CONFIG_CRYPTO_DEFLATE=y CONFIG_CRYPTO_LZO=y CONFIG_CRYPTO_DEV_MXS_DCP=y @@ -703,6 +784,5 @@ CONFIG_PRINTK_TIME=y CONFIG_FRAME_WARN=2048 CONFIG_DEBUG_FS=y CONFIG_STACKTRACE=y -CONFIG_STRICT_DEVMEM=y CONFIG_DEBUG_USER=y # CONFIG_RUNTIME_TESTING_MENU is not set diff --git a/arch/arm/configs/tsimx28_minimal_defconfig b/arch/arm/configs/tsimx28_minimal_defconfig index ef01f92154fe7..09cb02764fe02 100644 --- a/arch/arm/configs/tsimx28_minimal_defconfig +++ b/arch/arm/configs/tsimx28_minimal_defconfig @@ -1,8 +1,9 @@ # CONFIG_SWAP is not set +CONFIG_SYSVIPC=y # CONFIG_CROSS_MEMORY_ATTACH is not set -CONFIG_NO_HZ=y +CONFIG_NO_HZ_IDLE=y CONFIG_HIGH_RES_TIMERS=y -CONFIG_PREEMPT_VOLUNTARY=y +CONFIG_PREEMPT=y CONFIG_TASKSTATS=y CONFIG_TASK_DELAY_ACCT=y CONFIG_TASK_XACCT=y @@ -10,20 +11,23 @@ CONFIG_TASK_IO_ACCOUNTING=y CONFIG_CGROUPS=y # CONFIG_UTS_NS is not set # CONFIG_PID_NS is not set +CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y # CONFIG_RD_ZSTD is not set -CONFIG_KALLSYMS_ALL=y CONFIG_PERF_EVENTS=y # CONFIG_COMPAT_BRK is not set +CONFIG_SLAB=y # CONFIG_SLAB_MERGE_DEFAULT is not set # CONFIG_ARCH_MULTI_V7 is not set CONFIG_ARCH_MXS=y +CONFIG_HZ_1000=y CONFIG_AEABI=y CONFIG_MODULES=y CONFIG_MODULE_FORCE_LOAD=y CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_MODVERSIONS=y +CONFIG_MODULE_COMPRESS=y +CONFIG_MODULE_COMPRESS_XZ=y CONFIG_UNUSED_SYMBOLS=y CONFIG_BLK_DEV_INTEGRITY=y CONFIG_BINFMT_MISC=y @@ -51,14 +55,8 @@ CONFIG_BT_BNEP=m CONFIG_BT_BNEP_MC_FILTER=y CONFIG_BT_BNEP_PROTO_FILTER=y CONFIG_BT_HIDP=m -CONFIG_BT_HCIBTUSB=m CONFIG_BT_HCIUART=m -CONFIG_BT_HCIUART_BCSP=y -CONFIG_BT_HCIUART_ATH3K=y -CONFIG_BT_HCIBCM203X=m -CONFIG_BT_HCIBPA10X=m -CONFIG_BT_HCIBFUSB=m -CONFIG_BT_HCIVHCI=m +CONFIG_BT_HCIUART_H4=y CONFIG_CFG80211=m # CONFIG_CFG80211_DEFAULT_PS is not set CONFIG_CFG80211_WEXT=y @@ -163,12 +161,11 @@ CONFIG_I2C_MXS=y CONFIG_SPI=y CONFIG_SPI_GPIO=m CONFIG_SPI_MXS=y -CONFIG_SPI_SPIDEV=m +CONFIG_SPI_SPIDEV=y CONFIG_PPS=m CONFIG_PPS_CLIENT_GPIO=m # CONFIG_PTP_1588_CLOCK is not set CONFIG_GPIO_SYSFS=y -CONFIG_HWMON=m CONFIG_WATCHDOG=y CONFIG_TS_WDT_MICRO=y CONFIG_MFD_MXS_LRADC=m @@ -290,10 +287,6 @@ CONFIG_CRYPTO_DEV_MXS_DCP=y CONFIG_CRC_CCITT=m CONFIG_CRC_ITU_T=m CONFIG_CRC7=m -CONFIG_PRINTK_TIME=y CONFIG_FRAME_WARN=2048 -CONFIG_DEBUG_KERNEL=y -# CONFIG_DEBUG_MISC is not set -CONFIG_BLK_DEV_IO_TRACE=y CONFIG_DEBUG_USER=y # CONFIG_RUNTIME_TESTING_MENU is not set diff --git a/arch/arm/configs/tsimx6_defconfig b/arch/arm/configs/tsimx6_defconfig index 6a6cf500b38d9..fc423db19acb9 100644 --- a/arch/arm/configs/tsimx6_defconfig +++ b/arch/arm/configs/tsimx6_defconfig @@ -1,72 +1,64 @@ CONFIG_KERNEL_LZO=y CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y -CONFIG_NO_HZ=y +# CONFIG_CROSS_MEMORY_ATTACH is not set +CONFIG_NO_HZ_IDLE=y CONFIG_HIGH_RES_TIMERS=y CONFIG_PREEMPT=y -CONFIG_IRQ_TIME_ACCOUNTING=y CONFIG_PSI=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y +# CONFIG_CPU_ISOLATION is not set CONFIG_LOG_BUF_SHIFT=18 CONFIG_CGROUPS=y CONFIG_MEMCG=y -CONFIG_BLK_CGROUP=y CONFIG_CGROUP_SCHED=y CONFIG_CFS_BANDWIDTH=y CONFIG_CGROUP_PIDS=y -CONFIG_CGROUP_RDMA=y CONFIG_CGROUP_FREEZER=y CONFIG_CPUSETS=y -# CONFIG_PROC_PID_CPUSET is not set CONFIG_CGROUP_DEVICE=y CONFIG_CGROUP_CPUACCT=y -CONFIG_CGROUP_PERF=y CONFIG_CGROUP_BPF=y -CONFIG_CGROUP_DEBUG=y -CONFIG_NAMESPACES=y CONFIG_USER_NS=y CONFIG_CHECKPOINT_RESTORE=y -CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y -# CONFIG_RD_ZSTD is not set -CONFIG_EXPERT=y -CONFIG_KALLSYMS_ALL=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_BPF_SYSCALL=y -# CONFIG_SLUB_DEBUG is not set # CONFIG_COMPAT_BRK is not set -CONFIG_PROFILING=y +CONFIG_SLAB=y +# CONFIG_SLAB_MERGE_DEFAULT is not set +CONFIG_ARCH_MULTI_V6=y CONFIG_ARCH_MXC=y CONFIG_SOC_IMX6Q=y CONFIG_ARM_ERRATA_814220=y CONFIG_SMP=y CONFIG_HAVE_ARM_ARCH_TIMER=y +CONFIG_HOTPLUG_CPU=y CONFIG_ARM_PSCI=y -CONFIG_HIGHMEM=y +CONFIG_HZ_1000=y CONFIG_FORCE_MAX_ZONEORDER=14 CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" -CONFIG_KEXEC=y CONFIG_EFI=y CONFIG_CPU_FREQ=y CONFIG_CPU_FREQ_STAT=y CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y CONFIG_CPU_FREQ_GOV_POWERSAVE=y CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y CONFIG_CPUFREQ_DT=y CONFIG_ARM_IMX6Q_CPUFREQ=y -CONFIG_ARM_IMX_CPUFREQ_DT=y CONFIG_CPU_IDLE=y CONFIG_ARM_CPUIDLE=y CONFIG_ARM_PSCI_CPUIDLE=y CONFIG_VFP=y CONFIG_NEON=y +# CONFIG_SUSPEND is not set +CONFIG_PM=y CONFIG_PM_DEBUG=y -CONFIG_PM_TEST_SUSPEND=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_MODULE_COMPRESS=y +CONFIG_MODULE_COMPRESS_XZ=y +# CONFIG_MQ_IOSCHED_KYBER is not set CONFIG_BINFMT_MISC=y CONFIG_NET=y CONFIG_PACKET=y @@ -74,15 +66,13 @@ CONFIG_PACKET_DIAG=m CONFIG_UNIX=y CONFIG_UNIX_DIAG=m CONFIG_TLS=m -CONFIG_TLS_DEVICE=y -CONFIG_TLS_TOE=y CONFIG_XFRM_USER=m CONFIG_XFRM_INTERFACE=m CONFIG_XFRM_SUB_POLICY=y -CONFIG_XFRM_STATISTICS=y CONFIG_NET_KEY=m CONFIG_NET_KEY_MIGRATE=y CONFIG_XDP_SOCKETS=y +CONFIG_XDP_SOCKETS_DIAG=m CONFIG_INET=y CONFIG_IP_MULTICAST=y CONFIG_IP_ADVANCED_ROUTER=y @@ -91,8 +81,6 @@ CONFIG_IP_ROUTE_MULTIPATH=y CONFIG_IP_ROUTE_VERBOSE=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y CONFIG_NET_IPIP=m CONFIG_NET_IPGRE_DEMUX=m CONFIG_NET_IPGRE=m @@ -102,11 +90,9 @@ CONFIG_IP_MROUTE_MULTIPLE_TABLES=y CONFIG_IP_PIMSM_V1=y CONFIG_IP_PIMSM_V2=y CONFIG_NET_IPVTI=m -CONFIG_NET_FOU=y CONFIG_NET_FOU_IP_TUNNELS=y CONFIG_INET_AH=m CONFIG_INET_ESP=m -CONFIG_INET_ESP_OFFLOAD=m CONFIG_INET_ESPINTCP=y CONFIG_INET_IPCOMP=m CONFIG_INET_UDP_DIAG=m @@ -130,7 +116,6 @@ CONFIG_IPV6_ROUTE_INFO=y CONFIG_IPV6_OPTIMISTIC_DAD=y CONFIG_INET6_AH=m CONFIG_INET6_ESP=m -CONFIG_INET6_ESP_OFFLOAD=m CONFIG_INET6_ESPINTCP=y CONFIG_INET6_IPCOMP=m CONFIG_IPV6_MIP6=m @@ -148,11 +133,11 @@ CONFIG_IPV6_SEG6_HMAC=y CONFIG_IPV6_RPL_LWTUNNEL=y CONFIG_MPTCP=y CONFIG_NETWORK_SECMARK=y -CONFIG_NETWORK_PHY_TIMESTAMPING=y CONFIG_NETFILTER=y CONFIG_BRIDGE_NETFILTER=m CONFIG_NF_CONNTRACK=m CONFIG_NF_LOG_NETDEV=m +CONFIG_NF_CONNTRACK_SECMARK=y CONFIG_NF_CONNTRACK_ZONES=y CONFIG_NF_CONNTRACK_PROCFS=y CONFIG_NF_CONNTRACK_EVENTS=y @@ -200,12 +185,15 @@ CONFIG_NFT_TPROXY=m CONFIG_NFT_SYNPROXY=m CONFIG_NFT_DUP_NETDEV=m CONFIG_NFT_FWD_NETDEV=m +CONFIG_NFT_FIB_NETDEV=m CONFIG_NF_FLOW_TABLE_INET=m CONFIG_NF_FLOW_TABLE=m CONFIG_NETFILTER_XT_SET=m CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m +CONFIG_NETFILTER_XT_TARGET_CT=m CONFIG_NETFILTER_XT_TARGET_DSCP=m CONFIG_NETFILTER_XT_TARGET_HMARK=m CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m @@ -214,7 +202,6 @@ CONFIG_NETFILTER_XT_TARGET_LOG=m CONFIG_NETFILTER_XT_TARGET_MARK=m CONFIG_NETFILTER_XT_TARGET_NFLOG=m CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m -CONFIG_NETFILTER_XT_TARGET_NOTRACK=m CONFIG_NETFILTER_XT_TARGET_TEE=m CONFIG_NETFILTER_XT_TARGET_TPROXY=m CONFIG_NETFILTER_XT_TARGET_TRACE=m @@ -255,6 +242,7 @@ CONFIG_NETFILTER_XT_MATCH_QUOTA=m CONFIG_NETFILTER_XT_MATCH_RATEEST=m CONFIG_NETFILTER_XT_MATCH_REALM=m CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SCTP=m CONFIG_NETFILTER_XT_MATCH_SOCKET=m CONFIG_NETFILTER_XT_MATCH_STATE=m CONFIG_NETFILTER_XT_MATCH_STATISTIC=m @@ -350,7 +338,6 @@ CONFIG_IP6_NF_RAW=m CONFIG_IP6_NF_NAT=m CONFIG_IP6_NF_TARGET_MASQUERADE=m CONFIG_IP6_NF_TARGET_NPT=m -CONFIG_DECNET_NF_GRABULATOR=m CONFIG_NF_TABLES_BRIDGE=m CONFIG_NFT_BRIDGE_META=m CONFIG_NFT_BRIDGE_REJECT=m @@ -379,14 +366,8 @@ CONFIG_BRIDGE_EBT_LOG=m CONFIG_BRIDGE_EBT_NFLOG=m CONFIG_BPFILTER=y CONFIG_IP_DCCP=m -CONFIG_IP_SCTP=m CONFIG_RDS=m CONFIG_RDS_TCP=m -CONFIG_TIPC=m -CONFIG_ATM=m -CONFIG_ATM_CLIP=m -CONFIG_ATM_LANE=m -CONFIG_ATM_BR2684=m CONFIG_L2TP=m CONFIG_L2TP_V3=y CONFIG_L2TP_IP=m @@ -394,43 +375,24 @@ CONFIG_L2TP_ETH=m CONFIG_BRIDGE=m CONFIG_BRIDGE_VLAN_FILTERING=y CONFIG_BRIDGE_MRP=y -CONFIG_NET_DSA=m CONFIG_VLAN_8021Q=m CONFIG_VLAN_8021Q_GVRP=y CONFIG_VLAN_8021Q_MVRP=y -CONFIG_DECNET=m CONFIG_LLC2=m -CONFIG_ATALK=m -CONFIG_X25=m -CONFIG_LAPB=m -CONFIG_PHONET=m CONFIG_6LOWPAN=m -CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m -CONFIG_6LOWPAN_GHC_UDP=m -CONFIG_6LOWPAN_GHC_ICMPV6=m -CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m -CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m -CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m CONFIG_IEEE802154=m CONFIG_IEEE802154_6LOWPAN=m CONFIG_MAC802154=m -CONFIG_NET_SCHED=y -CONFIG_DCB=y CONFIG_DNS_RESOLVER=y CONFIG_BATMAN_ADV=m CONFIG_BATMAN_ADV_NC=y CONFIG_OPENVSWITCH=m CONFIG_VSOCKETS=m CONFIG_NETLINK_DIAG=m -CONFIG_MPLS_ROUTING=m -CONFIG_MPLS_IPTUNNEL=m CONFIG_HSR=m -CONFIG_QRTR=m -CONFIG_QRTR_TUN=m -CONFIG_NET_NCSI=y -CONFIG_NCSI_OEM_CMD_GET_MAC=y CONFIG_CGROUP_NET_PRIO=y CONFIG_BPF_JIT=y +CONFIG_BPF_STREAM_PARSER=y CONFIG_CAN=m CONFIG_CAN_J1939=m CONFIG_CAN_ISOTP=m @@ -452,31 +414,35 @@ CONFIG_BT_RFCOMM_TTY=y CONFIG_BT_BNEP=m CONFIG_BT_BNEP_MC_FILTER=y CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=m CONFIG_BT_HS=y +CONFIG_BT_6LOWPAN=m CONFIG_BT_LEDS=y CONFIG_BT_MSFTEXT=y CONFIG_BT_HCIBTUSB=m CONFIG_BT_HCIBTUSB_MTK=y CONFIG_BT_HCIUART=m -CONFIG_BT_HCIUART_NOKIA=m -CONFIG_BT_HCIUART_BCSP=y CONFIG_BT_HCIUART_ATH3K=y CONFIG_BT_HCIUART_LL=y +CONFIG_BT_HCIUART_INTEL=y +CONFIG_BT_HCIUART_BCM=y +CONFIG_BT_HCIUART_RTL=y CONFIG_BT_HCIUART_QCA=y +CONFIG_BT_HCIUART_AG6XX=y +CONFIG_BT_HCIUART_MRVL=y +CONFIG_BT_HCIBCM203X=m +CONFIG_BT_HCIBPA10X=m +CONFIG_BT_HCIBFUSB=m +CONFIG_BT_HCIVHCI=m +CONFIG_BT_MRVL=m +CONFIG_BT_ATH3K=m +CONFIG_BT_MTKUART=m CONFIG_CFG80211=m # CONFIG_CFG80211_DEFAULT_PS is not set CONFIG_MAC80211=m +CONFIG_MAC80211_MESH=y CONFIG_RFKILL=m -CONFIG_RFKILL_INPUT=y -CONFIG_NFC=m -CONFIG_NFC_DIGITAL=m -CONFIG_NFC_NCI=m -CONFIG_NFC_NCI_SPI=m -CONFIG_NFC_NCI_UART=m -CONFIG_NFC_HCI=m -CONFIG_NFC_PN533_USB=m -CONFIG_NFC_NXP_NCI=m -CONFIG_NFC_ST95HF=m +CONFIG_FAILOVER=m CONFIG_PCI=y CONFIG_PCI_MSI=y CONFIG_PCI_IMX6=y @@ -485,31 +451,20 @@ CONFIG_DEVTMPFS_MOUNT=y # CONFIG_STANDALONE is not set CONFIG_EXTRA_FIRMWARE="imx/sdma/sdma-imx6q.bin" CONFIG_EXTRA_FIRMWARE_DIR="firmware" -CONFIG_IMX_WEIM=y CONFIG_CONNECTOR=y CONFIG_MTD=y -CONFIG_MTD_CMDLINE_PARTS=m -CONFIG_MTD_OF_PARTS=m +# CONFIG_MTD_OF_PARTS is not set CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=m CONFIG_MTD_JEDECPROBE=m CONFIG_MTD_CFI_INTELEXT=m CONFIG_MTD_CFI_AMDSTD=m CONFIG_MTD_CFI_STAA=m -CONFIG_MTD_DATAFLASH=m CONFIG_MTD_SST25L=m -CONFIG_MTD_RAW_NAND=m -CONFIG_MTD_NAND_MXC=m CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_UBI=m -CONFIG_MTD_UBI_FASTMAP=y -CONFIG_MTD_UBI_BLOCK=y CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=65536 CONFIG_EEPROM_AT24=y CONFIG_EEPROM_AT25=y -CONFIG_MISC_RTSX_USB=m # CONFIG_SCSI_PROC_FS is not set CONFIG_BLK_DEV_SD=y CONFIG_SCSI_CONSTANTS=y @@ -524,31 +479,90 @@ CONFIG_MD=y CONFIG_BLK_DEV_DM=m CONFIG_DM_THIN_PROVISIONING=m CONFIG_NETDEVICES=y +CONFIG_BONDING=m CONFIG_DUMMY=m CONFIG_WIREGUARD=m +CONFIG_EQUALIZER=m +CONFIG_NET_TEAM=m +CONFIG_NET_TEAM_MODE_BROADCAST=m +CONFIG_NET_TEAM_MODE_ROUNDROBIN=m +CONFIG_NET_TEAM_MODE_RANDOM=m +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m +CONFIG_NET_TEAM_MODE_LOADBALANCE=m CONFIG_MACVLAN=m CONFIG_MACVTAP=m CONFIG_IPVLAN=m CONFIG_IPVTAP=m CONFIG_VXLAN=m +CONFIG_GENEVE=m +CONFIG_BAREUDP=m +CONFIG_MACSEC=m +CONFIG_TUN=m CONFIG_VETH=m +CONFIG_NLMON=m +CONFIG_NET_VRF=m +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_ADAPTEC is not set +# CONFIG_NET_VENDOR_AGERE is not set +# CONFIG_NET_VENDOR_ALACRITECH is not set +# CONFIG_NET_VENDOR_ALTEON is not set +# CONFIG_NET_VENDOR_AMAZON is not set +# CONFIG_NET_VENDOR_AMD is not set +# CONFIG_NET_VENDOR_AQUANTIA is not set +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_ATHEROS is not set +# CONFIG_NET_VENDOR_AURORA is not set # CONFIG_NET_VENDOR_BROADCOM is not set -CONFIG_CS89x0=y -CONFIG_CS89x0_PLATFORM=y +# CONFIG_NET_VENDOR_BROCADE is not set +# CONFIG_NET_VENDOR_CADENCE is not set +# CONFIG_NET_VENDOR_CAVIUM is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_CISCO is not set +# CONFIG_NET_VENDOR_CORTINA is not set +# CONFIG_NET_VENDOR_DEC is not set +# CONFIG_NET_VENDOR_DLINK is not set +# CONFIG_NET_VENDOR_EMULEX is not set +# CONFIG_NET_VENDOR_EZCHIP is not set # CONFIG_NET_VENDOR_FARADAY is not set CONFIG_IGB=m # CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MELLANOX is not set # CONFIG_NET_VENDOR_MICREL is not set # CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_MICROSEMI is not set +# CONFIG_NET_VENDOR_MYRI is not set # CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NETERION is not set +# CONFIG_NET_VENDOR_NETRONOME is not set +# CONFIG_NET_VENDOR_NI is not set +# CONFIG_NET_VENDOR_NVIDIA is not set +# CONFIG_NET_VENDOR_OKI is not set +# CONFIG_NET_VENDOR_PACKET_ENGINES is not set +# CONFIG_NET_VENDOR_PENSANDO is not set +# CONFIG_NET_VENDOR_QLOGIC is not set +# CONFIG_NET_VENDOR_QUALCOMM is not set +# CONFIG_NET_VENDOR_RDC is not set +# CONFIG_NET_VENDOR_REALTEK is not set +# CONFIG_NET_VENDOR_RENESAS is not set +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set # CONFIG_NET_VENDOR_SEEQ is not set -CONFIG_SMC91X=y -CONFIG_SMC911X=y -CONFIG_SMSC911X=y +# CONFIG_NET_VENDOR_SOLARFLARE is not set +# CONFIG_NET_VENDOR_SILAN is not set +# CONFIG_NET_VENDOR_SIS is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_SOCIONEXT is not set # CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SUN is not set +# CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_TEHUTI is not set +# CONFIG_NET_VENDOR_TI is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +# CONFIG_NET_VENDOR_XILINX is not set CONFIG_MICREL_PHY=y CONFIG_MICROCHIP_PHY=y -CONFIG_AT803X_PHY=y CONFIG_SMSC_PHY=y CONFIG_PPP=m CONFIG_PPP_BSDCOMP=m @@ -556,18 +570,12 @@ CONFIG_PPP_DEFLATE=m CONFIG_PPP_FILTER=y CONFIG_PPP_MPPE=m CONFIG_PPP_MULTILINK=y -CONFIG_PPPOATM=m CONFIG_PPPOE=m -CONFIG_PPTP=m CONFIG_PPPOL2TP=m CONFIG_PPP_ASYNC=m CONFIG_PPP_SYNC_TTY=m -CONFIG_USB_CATC=m -CONFIG_USB_KAWETH=m -CONFIG_USB_PEGASUS=m -CONFIG_USB_RTL8150=m -CONFIG_USB_RTL8152=m -CONFIG_USB_LAN78XX=m +CONFIG_USB_NET_DRIVERS=m +CONFIG_USB_USBNET=m CONFIG_USB_NET_CDC_EEM=m CONFIG_USB_NET_HUAWEI_CDC_NCM=m CONFIG_USB_NET_CDC_MBIM=m @@ -579,29 +587,32 @@ CONFIG_USB_NET_SMSC95XX=m CONFIG_USB_NET_GL620A=m CONFIG_USB_NET_PLUSB=m CONFIG_USB_NET_MCS7830=m +CONFIG_USB_NET_RNDIS_HOST=m CONFIG_USB_NET_CX82310_ETH=m CONFIG_USB_NET_KALMIA=m CONFIG_USB_NET_QMI_WWAN=m -CONFIG_USB_HSO=m CONFIG_USB_NET_INT51X1=m -CONFIG_USB_IPHETH=m -CONFIG_USB_SIERRA_NET=m -CONFIG_USB_VL600=m CONFIG_USB_NET_CH9200=m CONFIG_USB_NET_AQC111=m -CONFIG_ATH5K_PCI=y +# CONFIG_WLAN_VENDOR_ADMTEK is not set CONFIG_ATH9K=m +CONFIG_ATH9K_HTC=m +CONFIG_CARL9170=m +CONFIG_AR5523=m CONFIG_ATH10K=m CONFIG_ATH10K_SDIO=m +CONFIG_ATH10K_USB=m +CONFIG_ATH11K=m +CONFIG_ATH11K_PCI=m CONFIG_AT76C50X_USB=m +CONFIG_BRCMSMAC=m CONFIG_BRCMFMAC=m # CONFIG_BRCMFMAC_SDIO is not set CONFIG_BRCMFMAC_USB=y +CONFIG_BRCMFMAC_PCIE=y +# CONFIG_WLAN_VENDOR_CISCO is not set CONFIG_IPW2100=m -CONFIG_IPW2100_MONITOR=y CONFIG_IPW2200=m -CONFIG_IPW2200_MONITOR=y -CONFIG_IPW2200_PROMISCUOUS=y CONFIG_IWL4965=m CONFIG_IWL3945=m CONFIG_IWLWIFI=m @@ -609,7 +620,6 @@ CONFIG_IWLDVM=m CONFIG_IWLMVM=m # CONFIG_WLAN_VENDOR_INTERSIL is not set CONFIG_MWIFIEX=m -CONFIG_MWIFIEX_SDIO=m CONFIG_MWIFIEX_PCIE=m CONFIG_MWIFIEX_USB=m CONFIG_MWL8K=m @@ -621,10 +631,13 @@ CONFIG_MT76x2U=m CONFIG_MT7603E=m CONFIG_MT7615E=m CONFIG_MT7663U=m -CONFIG_MT7663S=m CONFIG_MT7915E=m # CONFIG_WLAN_VENDOR_MICROCHIP is not set CONFIG_RT2X00=m +CONFIG_RT2400PCI=m +CONFIG_RT2500PCI=m +CONFIG_RT61PCI=m +CONFIG_RT2800PCI=m CONFIG_RT2500USB=m CONFIG_RT73USB=m CONFIG_RT2800USB=m @@ -634,6 +647,16 @@ CONFIG_RT2800USB_RT55XX=y CONFIG_RT2800USB_UNKNOWN=y CONFIG_RTL8180=m CONFIG_RTL8187=m +CONFIG_RTL8192CE=m +CONFIG_RTL8192SE=m +CONFIG_RTL8192DE=m +CONFIG_RTL8723AE=m +CONFIG_RTL8723BE=m +CONFIG_RTL8188EE=m +CONFIG_RTL8192EE=m +CONFIG_RTL8821AE=m +CONFIG_RTL8192CU=m +# CONFIG_RTLWIFI_DEBUG is not set CONFIG_RTL8XXXU=m CONFIG_RTL8XXXU_UNTESTED=y CONFIG_RTW88=m @@ -647,61 +670,27 @@ CONFIG_RSI_91X=m CONFIG_WL12XX=m CONFIG_WLCORE_SDIO=m # CONFIG_WILINK_PLATFORM_DATA is not set +CONFIG_USB_ZD1201=m CONFIG_ZD1211RW=m CONFIG_QTNFMAC_PCIE=m -CONFIG_USB_NET_RNDIS_WLAN=m -CONFIG_VIRT_WIFI=m +# CONFIG_INPUT_LEDS is not set CONFIG_INPUT_MOUSEDEV=m -CONFIG_INPUT_JOYDEV=m CONFIG_INPUT_EVDEV=y +# CONFIG_KEYBOARD_ATKBD is not set CONFIG_KEYBOARD_GPIO=y -CONFIG_KEYBOARD_SNVS_PWRKEY=y -CONFIG_KEYBOARD_IMX=y -CONFIG_MOUSE_PS2=m -CONFIG_MOUSE_PS2_ELANTECH=y -CONFIG_INPUT_JOYSTICK=y -CONFIG_JOYSTICK_ANALOG=m -CONFIG_JOYSTICK_A3D=m -CONFIG_JOYSTICK_ADC=m -CONFIG_JOYSTICK_ADI=m -CONFIG_JOYSTICK_COBRA=m -CONFIG_JOYSTICK_GF2K=m -CONFIG_JOYSTICK_GRIP=m -CONFIG_JOYSTICK_GRIP_MP=m -CONFIG_JOYSTICK_GUILLEMOT=m -CONFIG_JOYSTICK_INTERACT=m -CONFIG_JOYSTICK_SIDEWINDER=m -CONFIG_JOYSTICK_TMDC=m -CONFIG_JOYSTICK_IFORCE=m -CONFIG_JOYSTICK_WARRIOR=m -CONFIG_JOYSTICK_MAGELLAN=m -CONFIG_JOYSTICK_SPACEORB=m -CONFIG_JOYSTICK_SPACEBALL=m -CONFIG_JOYSTICK_STINGER=m -CONFIG_JOYSTICK_TWIDJOY=m -CONFIG_JOYSTICK_ZHENHUA=m -CONFIG_JOYSTICK_AS5011=m -CONFIG_JOYSTICK_JOYDUMP=m -CONFIG_JOYSTICK_XPAD=m -CONFIG_JOYSTICK_PSXPAD_SPI=m -CONFIG_JOYSTICK_PXRC=m -CONFIG_JOYSTICK_FSIA6B=m +# CONFIG_MOUSE_PS2 is not set CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_ADS7846=y -CONFIG_TOUCHSCREEN_AD7879=y -CONFIG_TOUCHSCREEN_AD7879_I2C=y -CONFIG_TOUCHSCREEN_IMX6UL_TSC=m CONFIG_TOUCHSCREEN_PIXCIR=y -CONFIG_TOUCHSCREEN_TSC2004=y -CONFIG_INPUT_MISC=y -CONFIG_INPUT_MMA8450=y -CONFIG_SERIO_SERPORT=m +# CONFIG_SERIO is not set # CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_MAX3100_TS=y CONFIG_SERIAL_IMX=y CONFIG_SERIAL_IMX_CONSOLE=y CONFIG_SERIAL_FSL_LPUART=y CONFIG_SERIAL_FSL_LPUART_CONSOLE=y CONFIG_SERIAL_DEV_BUS=y +# CONFIG_RANDOM_TRUST_BOOTLOADER is not set # CONFIG_I2C_COMPAT is not set CONFIG_I2C_CHARDEV=y CONFIG_I2C_MUX=y @@ -712,172 +701,37 @@ CONFIG_I2C_ALGOPCA=m CONFIG_I2C_GPIO=y CONFIG_I2C_IMX=y CONFIG_SPI=y -CONFIG_SPI_FSL_QUADSPI=y CONFIG_SPI_GPIO=y CONFIG_SPI_IMX=y -CONFIG_SPI_SPIDEV=m +CONFIG_SPI_SPIDEV=y CONFIG_PPS_CLIENT_GPIO=m +CONFIG_PTP_1588_CLOCK=m CONFIG_PINCTRL_IMX8MM=y CONFIG_PINCTRL_IMX8MN=y CONFIG_PINCTRL_IMX8MP=y CONFIG_PINCTRL_IMX8MQ=y CONFIG_GPIO_SYSFS=y CONFIG_GPIO_MXC=y -CONFIG_GPIO_MAX732X=y -CONFIG_GPIO_PCA953X=y -CONFIG_GPIO_PCF857X=y CONFIG_GPIO_TS4900=y -CONFIG_GPIO_74X164=y CONFIG_POWER_RESET=y CONFIG_POWER_RESET_SYSCON=y CONFIG_POWER_RESET_SYSCON_POWEROFF=y -CONFIG_POWER_SUPPLY=y -CONFIG_SENSORS_GPIO_FAN=y -CONFIG_SENSORS_IIO_HWMON=m CONFIG_THERMAL_STATISTICS=y CONFIG_THERMAL_WRITABLE_TRIPS=y CONFIG_CPU_THERMAL=y CONFIG_IMX_THERMAL=y CONFIG_WATCHDOG=y CONFIG_IMX2_WDT=y +CONFIG_MFD_DA9052_I2C=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_USERSPACE_CONSUMER=m CONFIG_REGULATOR_ANATOP=y CONFIG_REGULATOR_GPIO=y -CONFIG_RC_CORE=m -CONFIG_RC_DEVICES=y -CONFIG_IR_GPIO_CIR=m -CONFIG_MEDIA_SUPPORT=m -CONFIG_MEDIA_USB_SUPPORT=y -CONFIG_USB_VIDEO_CLASS=m -CONFIG_USB_M5602=m -CONFIG_USB_STV06XX=m -CONFIG_USB_GL860=m -CONFIG_USB_GSPCA_BENQ=m -CONFIG_USB_GSPCA_CONEX=m -CONFIG_USB_GSPCA_CPIA1=m -CONFIG_USB_GSPCA_DTCS033=m -CONFIG_USB_GSPCA_ETOMS=m -CONFIG_USB_GSPCA_FINEPIX=m -CONFIG_USB_GSPCA_JEILINJ=m -CONFIG_USB_GSPCA_JL2005BCD=m -CONFIG_USB_GSPCA_KINECT=m -CONFIG_USB_GSPCA_KONICA=m -CONFIG_USB_GSPCA_MARS=m -CONFIG_USB_GSPCA_MR97310A=m -CONFIG_USB_GSPCA_NW80X=m -CONFIG_USB_GSPCA_OV519=m -CONFIG_USB_GSPCA_OV534=m -CONFIG_USB_GSPCA_OV534_9=m -CONFIG_USB_GSPCA_PAC207=m -CONFIG_USB_GSPCA_PAC7302=m -CONFIG_USB_GSPCA_PAC7311=m -CONFIG_USB_GSPCA_SE401=m -CONFIG_USB_GSPCA_SN9C2028=m -CONFIG_USB_GSPCA_SN9C20X=m -CONFIG_USB_GSPCA_SONIXB=m -CONFIG_USB_GSPCA_SONIXJ=m -CONFIG_USB_GSPCA_SPCA500=m -CONFIG_USB_GSPCA_SPCA501=m -CONFIG_USB_GSPCA_SPCA505=m -CONFIG_USB_GSPCA_SPCA506=m -CONFIG_USB_GSPCA_SPCA508=m -CONFIG_USB_GSPCA_SPCA561=m -CONFIG_USB_GSPCA_SPCA1528=m -CONFIG_USB_GSPCA_SQ905=m -CONFIG_USB_GSPCA_SQ905C=m -CONFIG_USB_GSPCA_SQ930X=m -CONFIG_USB_GSPCA_STK014=m -CONFIG_USB_GSPCA_STK1135=m -CONFIG_USB_GSPCA_STV0680=m -CONFIG_USB_GSPCA_SUNPLUS=m -CONFIG_USB_GSPCA_T613=m -CONFIG_USB_GSPCA_TOPRO=m -CONFIG_USB_GSPCA_TOUPTEK=m -CONFIG_USB_GSPCA_TV8532=m -CONFIG_USB_GSPCA_VC032X=m -CONFIG_USB_GSPCA_VICAM=m -CONFIG_USB_GSPCA_XIRLINK_CIT=m -CONFIG_USB_GSPCA_ZC3XX=m -CONFIG_USB_PWC=m -CONFIG_VIDEO_CPIA2=m -CONFIG_USB_ZR364XX=m -CONFIG_USB_STKWEBCAM=m -CONFIG_USB_S2255=m -CONFIG_VIDEO_USBTV=m -CONFIG_VIDEO_PVRUSB2=m -CONFIG_VIDEO_HDPVR=m -CONFIG_VIDEO_STK1160_COMMON=m -CONFIG_VIDEO_GO7007=m -CONFIG_VIDEO_AU0828=m -CONFIG_VIDEO_CX231XX=m -CONFIG_VIDEO_TM6000=m -CONFIG_VIDEO_TM6000_ALSA=m -CONFIG_VIDEO_TM6000_DVB=m -CONFIG_DVB_USB=m -CONFIG_DVB_USB_A800=m -CONFIG_DVB_USB_DIBUSB_MB=m -CONFIG_DVB_USB_DIBUSB_MC=m -CONFIG_DVB_USB_DIB0700=m -CONFIG_DVB_USB_UMT_010=m -CONFIG_DVB_USB_CXUSB=m -CONFIG_DVB_USB_M920X=m -CONFIG_DVB_USB_DIGITV=m -CONFIG_DVB_USB_VP7045=m -CONFIG_DVB_USB_VP702X=m -CONFIG_DVB_USB_GP8PSK=m -CONFIG_DVB_USB_NOVA_T_USB2=m -CONFIG_DVB_USB_TTUSB2=m -CONFIG_DVB_USB_DTT200U=m -CONFIG_DVB_USB_OPERA1=m -CONFIG_DVB_USB_AF9005=m -CONFIG_DVB_USB_AF9005_REMOTE=m -CONFIG_DVB_USB_PCTV452E=m -CONFIG_DVB_USB_DW2102=m -CONFIG_DVB_USB_CINERGY_T2=m -CONFIG_DVB_USB_DTV5100=m -CONFIG_DVB_USB_AZ6027=m -CONFIG_DVB_USB_TECHNISAT_USB2=m -CONFIG_DVB_USB_V2=m -CONFIG_DVB_USB_AF9015=m -CONFIG_DVB_USB_AF9035=m -CONFIG_DVB_USB_ANYSEE=m -CONFIG_DVB_USB_AU6610=m -CONFIG_DVB_USB_AZ6007=m -CONFIG_DVB_USB_CE6230=m -CONFIG_DVB_USB_EC168=m -CONFIG_DVB_USB_GL861=m -CONFIG_DVB_USB_LME2510=m -CONFIG_DVB_USB_MXL111SF=m -CONFIG_DVB_USB_RTL28XXU=m -CONFIG_DVB_USB_DVBSKY=m -CONFIG_DVB_USB_ZD1301=m -CONFIG_DVB_TTUSB_BUDGET=m -CONFIG_DVB_TTUSB_DEC=m -CONFIG_SMS_USB_DRV=m -CONFIG_DVB_B2C2_FLEXCOP_USB=m -CONFIG_DVB_AS102=m -CONFIG_VIDEO_EM28XX=m -CONFIG_VIDEO_EM28XX_V4L2=m -CONFIG_VIDEO_EM28XX_ALSA=m -CONFIG_VIDEO_EM28XX_DVB=m -CONFIG_USB_AIRSPY=m -CONFIG_USB_HACKRF=m -CONFIG_USB_MSI2500=m -CONFIG_V4L_PLATFORM_DRIVERS=y -CONFIG_VIDEO_MUX=m -CONFIG_V4L_MEM2MEM_DRIVERS=y -CONFIG_VIDEO_CODA=m -CONFIG_VIDEO_IMX_PXP=m -CONFIG_VIDEO_ADV7180=m -CONFIG_VIDEO_OV2680=m -CONFIG_VIDEO_OV5640=m -CONFIG_VIDEO_OV5645=m CONFIG_IMX_IPUV3_CORE=y CONFIG_DRM=y CONFIG_DRM_PANEL_LVDS=y CONFIG_DRM_PANEL_SIMPLE=y +CONFIG_DRM_PANEL_SEIKO_43WVF1G=y CONFIG_DRM_TI_TFP410=y CONFIG_DRM_DW_HDMI_AHB_AUDIO=m CONFIG_DRM_DW_HDMI_CEC=y @@ -886,18 +740,17 @@ CONFIG_DRM_IMX_PARALLEL_DISPLAY=y CONFIG_DRM_IMX_LDB=y CONFIG_DRM_IMX_HDMI=y CONFIG_DRM_ETNAVIV=y -CONFIG_DRM_MXSFB=y CONFIG_FB_MODE_HELPERS=y CONFIG_LCD_CLASS_DEVICE=y +CONFIG_LCD_L4F00242T03=y CONFIG_LCD_PLATFORM=y -CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BACKLIGHT_PWM=y -CONFIG_BACKLIGHT_GPIO=m -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_LOGO=y +CONFIG_BACKLIGHT_GPIO=y CONFIG_SOUND=m CONFIG_SND=m +CONFIG_SND_HRTIMER=m # CONFIG_SND_PCI is not set +# CONFIG_SND_SPI is not set CONFIG_SND_USB_AUDIO=m CONFIG_SND_SOC=m CONFIG_SND_SOC_FSL_ASRC=m @@ -907,55 +760,92 @@ CONFIG_SND_SOC_IMX_ES8328=m CONFIG_SND_SOC_IMX_SGTL5000=m CONFIG_SND_SOC_IMX_SPDIF=m CONFIG_SND_SOC_FSL_ASOC_CARD=m -CONFIG_SND_SOC_AC97_CODEC=m -CONFIG_SND_SOC_CS42XX8_I2C=m -CONFIG_SND_SOC_TLV320AIC3X=m -CONFIG_SND_SOC_WM8960=m -CONFIG_SND_SOC_WM8962=m CONFIG_SND_SIMPLE_CARD=m -CONFIG_HID_MULTITOUCH=y +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_ITE is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_REDRAGON is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MONTEREY is not set +CONFIG_HID_MULTITOUCH=m +CONFIG_USB_HID=m CONFIG_USB=y +# CONFIG_USB_PCI is not set CONFIG_USB_ANNOUNCE_NEW_DEVICES=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_MXC=y +CONFIG_USB_ACM=m CONFIG_USB_STORAGE=y CONFIG_USB_CHIPIDEA=y CONFIG_USB_CHIPIDEA_UDC=y CONFIG_USB_CHIPIDEA_HOST=y CONFIG_USB_SERIAL=m CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_SIMPLE=m +CONFIG_USB_SERIAL_AIRCABLE=m +CONFIG_USB_SERIAL_ARK3116=m +CONFIG_USB_SERIAL_BELKIN=m +CONFIG_USB_SERIAL_CH341=m +CONFIG_USB_SERIAL_WHITEHEAT=m +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m +CONFIG_USB_SERIAL_CP210X=m +CONFIG_USB_SERIAL_CYPRESS_M8=m +CONFIG_USB_SERIAL_EMPEG=m CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_VISOR=m +CONFIG_USB_SERIAL_IPAQ=m +CONFIG_USB_SERIAL_IR=m +CONFIG_USB_SERIAL_EDGEPORT=m +CONFIG_USB_SERIAL_EDGEPORT_TI=m +CONFIG_USB_SERIAL_F81232=m +CONFIG_USB_SERIAL_F8153X=m +CONFIG_USB_SERIAL_GARMIN=m +CONFIG_USB_SERIAL_IPW=m +CONFIG_USB_SERIAL_IUU=m +CONFIG_USB_SERIAL_KEYSPAN_PDA=m +CONFIG_USB_SERIAL_KEYSPAN=m +CONFIG_USB_SERIAL_KLSI=m +CONFIG_USB_SERIAL_KOBIL_SCT=m +CONFIG_USB_SERIAL_MCT_U232=m +CONFIG_USB_SERIAL_METRO=m +CONFIG_USB_SERIAL_MOS7720=m +CONFIG_USB_SERIAL_MOS7840=m +CONFIG_USB_SERIAL_MXUPORT=m +CONFIG_USB_SERIAL_NAVMAN=m +CONFIG_USB_SERIAL_PL2303=m +CONFIG_USB_SERIAL_OTI6858=m +CONFIG_USB_SERIAL_QCAUX=m +CONFIG_USB_SERIAL_QUALCOMM=m +CONFIG_USB_SERIAL_SPCP8X5=m +CONFIG_USB_SERIAL_SAFE=m +CONFIG_USB_SERIAL_SIERRAWIRELESS=m +CONFIG_USB_SERIAL_SYMBOL=m +CONFIG_USB_SERIAL_TI=m +CONFIG_USB_SERIAL_CYBERJACK=m +CONFIG_USB_SERIAL_XIRCOM=m CONFIG_USB_SERIAL_OPTION=m -CONFIG_USB_TEST=m -CONFIG_USB_EHSET_TEST_FIXTURE=m +CONFIG_USB_SERIAL_OMNINET=m +CONFIG_USB_SERIAL_OPTICON=m +CONFIG_USB_SERIAL_XSENS_MT=m +CONFIG_USB_SERIAL_WISHBONE=m +CONFIG_USB_SERIAL_SSU100=m +CONFIG_USB_SERIAL_QT2=m +CONFIG_USB_SERIAL_UPD78F0730=m CONFIG_NOP_USB_XCEIV=y CONFIG_USB_MXS_PHY=y CONFIG_USB_GADGET=y CONFIG_USB_FSL_USB2=y -CONFIG_USB_CONFIGFS=y -CONFIG_USB_CONFIGFS_SERIAL=y -CONFIG_USB_CONFIGFS_ACM=y -CONFIG_USB_CONFIGFS_OBEX=y -CONFIG_USB_CONFIGFS_NCM=y -CONFIG_USB_CONFIGFS_ECM=y -CONFIG_USB_CONFIGFS_ECM_SUBSET=y -CONFIG_USB_CONFIGFS_RNDIS=y -CONFIG_USB_CONFIGFS_EEM=y -CONFIG_USB_CONFIGFS_MASS_STORAGE=y -CONFIG_USB_CONFIGFS_F_LB_SS=y -CONFIG_USB_CONFIGFS_F_FS=y -CONFIG_USB_CONFIGFS_F_UAC1=y -CONFIG_USB_CONFIGFS_F_UAC2=y -CONFIG_USB_CONFIGFS_F_MIDI=y -CONFIG_USB_CONFIGFS_F_HID=y -CONFIG_USB_CONFIGFS_F_UVC=y -CONFIG_USB_CONFIGFS_F_PRINTER=y -CONFIG_USB_ZERO=m -CONFIG_USB_AUDIO=m +CONFIG_USB_CONFIGFS=m CONFIG_USB_ETH=m CONFIG_USB_G_NCM=m CONFIG_USB_GADGETFS=m -CONFIG_USB_FUNCTIONFS=m CONFIG_USB_MASS_STORAGE=m CONFIG_USB_G_SERIAL=m CONFIG_MMC=y @@ -966,65 +856,48 @@ CONFIG_LEDS_CLASS=y CONFIG_LEDS_GPIO=y CONFIG_LEDS_PWM=y CONFIG_LEDS_TRIGGER_TIMER=y -CONFIG_LEDS_TRIGGER_ONESHOT=y -CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_ONESHOT=m +CONFIG_LEDS_TRIGGER_DISK=y +CONFIG_LEDS_TRIGGER_MTD=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=m CONFIG_LEDS_TRIGGER_BACKLIGHT=y -CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_ACTIVITY=m +CONFIG_LEDS_TRIGGER_GPIO=m CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_LEDS_TRIGGER_TRANSIENT=m +CONFIG_LEDS_TRIGGER_PANIC=y +CONFIG_LEDS_TRIGGER_NETDEV=m +CONFIG_LEDS_TRIGGER_PATTERN=m CONFIG_RTC_CLASS=y CONFIG_RTC_INTF_DEV_UIE_EMUL=y CONFIG_RTC_DRV_DS1307=y CONFIG_RTC_DRV_ISL12022=y -CONFIG_RTC_DRV_PCF8563=y -CONFIG_RTC_DRV_M41T80=y CONFIG_DMADEVICES=y CONFIG_IMX_SDMA=y -# CONFIG_MX3_IPU is not set -CONFIG_DMATEST=m -CONFIG_UIO=m -CONFIG_UIO_PDRV_GENIRQ=m -CONFIG_UIO_DMEM_GENIRQ=m -CONFIG_UIO_PCI_GENERIC=m -CONFIG_STAGING=y +# CONFIG_VIRTIO_MENU is not set +# CONFIG_VHOST_MENU is not set CONFIG_COMMON_CLK_PWM=y CONFIG_CLK_IMX8MM=y CONFIG_CLK_IMX8MN=y CONFIG_CLK_IMX8MP=y CONFIG_CLK_IMX8MQ=y +# CONFIG_IOMMU_SUPPORT is not set CONFIG_IMX_GPCV2_PM_DOMAINS=y -CONFIG_SOC_IMX8M=y -CONFIG_PM_DEVFREQ=y -CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=m -CONFIG_DEVFREQ_GOV_PERFORMANCE=m -CONFIG_DEVFREQ_GOV_POWERSAVE=m -CONFIG_DEVFREQ_GOV_PASSIVE=m -CONFIG_ARM_IMX_BUS_DEVFREQ=m -CONFIG_PM_DEVFREQ_EVENT=y -CONFIG_IIO=m -CONFIG_IIO_BUFFER_DMAENGINE=m -CONFIG_IIO_BUFFER_HW_CONSUMER=m -CONFIG_IIO_SW_DEVICE=m -CONFIG_IIO_SW_TRIGGER=m -CONFIG_IIO_TRIGGERED_EVENT=m -CONFIG_IIO_ST_ACCEL_3AXIS=m -CONFIG_MMA8452=m -CONFIG_IMX7D_ADC=m -CONFIG_MCP320X=m -CONFIG_VF610_ADC=m -CONFIG_IIO_RESCALE=m +CONFIG_IIO=y +CONFIG_MMA8452=y +CONFIG_MCP3422=m CONFIG_IIO_ST_LSM6DSX=m -CONFIG_SENSORS_ISL29018=m -CONFIG_MAG3110=m +CONFIG_SENSORS_ISL29018=y +CONFIG_MAG3110=y CONFIG_IIO_ST_MAGN_3AXIS=m -CONFIG_MPL3115=m +CONFIG_IIO_MUX=m +CONFIG_MPL3115=y CONFIG_PWM=y -CONFIG_PWM_FSL_FTM=y CONFIG_PWM_IMX27=y -CONFIG_PWM_IMX_TPM=y CONFIG_NVMEM_IMX_OCOTP=y CONFIG_NVMEM_SNVS_LPGPR=y CONFIG_MUX_GPIO=m -CONFIG_MUX_MMIO=m CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y @@ -1032,35 +905,21 @@ CONFIG_EXT2_FS_SECURITY=y CONFIG_EXT3_FS=y CONFIG_EXT3_FS_POSIX_ACL=y CONFIG_EXT3_FS_SECURITY=y -CONFIG_JFS_FS=m -CONFIG_XFS_FS=m -CONFIG_BTRFS_FS=m +CONFIG_F2FS_FS=y +CONFIG_F2FS_FS_SECURITY=y CONFIG_QUOTA=y CONFIG_QUOTA_NETLINK_INTERFACE=y # CONFIG_PRINT_QUOTA_WARNING is not set -CONFIG_AUTOFS4_FS=m -CONFIG_FUSE_FS=m -CONFIG_CUSE=m -CONFIG_VIRTIO_FS=m +CONFIG_AUTOFS4_FS=y CONFIG_OVERLAY_FS=m -CONFIG_ISO9660_FS=m -CONFIG_JOLIET=y -CONFIG_ZISOFS=y -CONFIG_UDF_FS=m -CONFIG_MSDOS_FS=m CONFIG_VFAT_FS=y -CONFIG_EXFAT_FS=m +CONFIG_EXFAT_FS=y CONFIG_NTFS_FS=m CONFIG_NTFS_RW=y CONFIG_TMPFS_POSIX_ACL=y -CONFIG_CRAMFS=m -CONFIG_SQUASHFS=m -CONFIG_SQUASHFS_LZ4=y -CONFIG_SQUASHFS_LZO=y -CONFIG_SQUASHFS_XZ=y -CONFIG_ROMFS_FS=m +CONFIG_CONFIGFS_FS=y +# CONFIG_MISC_FILESYSTEMS is not set CONFIG_NFS_FS=y -CONFIG_NFS_V3_ACL=y CONFIG_ROOT_NFS=y CONFIG_CIFS=m CONFIG_NLS_DEFAULT="cp437" @@ -1069,15 +928,15 @@ CONFIG_NLS_ASCII=y CONFIG_NLS_ISO8859_1=y CONFIG_NLS_ISO8859_15=m CONFIG_NLS_UTF8=y -CONFIG_SECURITYFS=y CONFIG_CRYPTO_ECDH=y CONFIG_CRYPTO_CCM=y CONFIG_CRYPTO_GCM=y -CONFIG_CRYPTO_CBC=y CONFIG_CRYPTO_CMAC=y -CONFIG_CRYPTO_AES=y -CONFIG_CRYPTO_LZO=m +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y CONFIG_CRYPTO_DEV_FSL_CAAM=y +CONFIG_CRYPTO_DEV_SAHARA=y +CONFIG_CRYPTO_DEV_MXS_DCP=y CONFIG_CRC_T10DIF=y CONFIG_CRC7=m CONFIG_CMA_SIZE_MBYTES=64 @@ -1085,11 +944,8 @@ CONFIG_FONTS=y CONFIG_FONT_8x8=y CONFIG_FONT_8x16=y CONFIG_PRINTK_TIME=y -# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_SYMBOLIC_ERRNAME is not set +# CONFIG_ENABLE_MUST_CHECK is not set CONFIG_DEBUG_FS=y -# CONFIG_DEBUG_MISC is not set -# CONFIG_SCHED_DEBUG is not set -# CONFIG_DEBUG_PREEMPT is not set CONFIG_STACKTRACE=y -# CONFIG_FTRACE is not set # CONFIG_RUNTIME_TESTING_MENU is not set diff --git a/arch/arm/configs/tsimx6_minimal_defconfig b/arch/arm/configs/tsimx6_minimal_defconfig index d074e9b8d742a..0b4622fe3069d 100644 --- a/arch/arm/configs/tsimx6_minimal_defconfig +++ b/arch/arm/configs/tsimx6_minimal_defconfig @@ -1,5 +1,6 @@ CONFIG_KERNEL_LZO=y # CONFIG_SWAP is not set +CONFIG_SYSVIPC=y # CONFIG_CROSS_MEMORY_ATTACH is not set CONFIG_NO_HZ_IDLE=y CONFIG_HIGH_RES_TIMERS=y @@ -8,12 +9,8 @@ CONFIG_PREEMPT=y CONFIG_LOG_BUF_SHIFT=18 CONFIG_CGROUPS=y CONFIG_CC_OPTIMIZE_FOR_SIZE=y -# CONFIG_KALLSYMS is not set -# CONFIG_RSEQ is not set -CONFIG_EMBEDDED=y -# CONFIG_VM_EVENT_COUNTERS is not set # CONFIG_COMPAT_BRK is not set -CONFIG_SLOB=y +CONFIG_SLAB=y # CONFIG_SLAB_MERGE_DEFAULT is not set CONFIG_ARCH_MULTI_V6=y CONFIG_ARCH_MXC=y @@ -23,6 +20,7 @@ CONFIG_SMP=y CONFIG_HAVE_ARM_ARCH_TIMER=y CONFIG_HOTPLUG_CPU=y CONFIG_ARM_PSCI=y +CONFIG_HZ_1000=y CONFIG_FORCE_MAX_ZONEORDER=14 CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" CONFIG_CPU_FREQ=y @@ -42,8 +40,8 @@ CONFIG_PM=y CONFIG_PM_DEBUG=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_MODULE_COMPRESS=y +CONFIG_MODULE_COMPRESS_XZ=y # CONFIG_BLK_DEV_BSG is not set # CONFIG_MQ_IOSCHED_KYBER is not set CONFIG_BINFMT_MISC=y @@ -65,7 +63,6 @@ CONFIG_CFG80211=m CONFIG_CFG80211_WEXT=y CONFIG_MAC80211=m CONFIG_RFKILL=m -CONFIG_RFKILL_INPUT=y # CONFIG_ETHTOOL_NETLINK is not set CONFIG_PCI=y CONFIG_PCI_MSI=y @@ -222,7 +219,7 @@ CONFIG_I2C_IMX=y CONFIG_SPI=y CONFIG_SPI_GPIO=y CONFIG_SPI_IMX=y -CONFIG_SPI_SPIDEV=m +CONFIG_SPI_SPIDEV=y CONFIG_PPS_CLIENT_GPIO=m CONFIG_PTP_1588_CLOCK=m CONFIG_PINCTRL_IMX8MM=y @@ -235,7 +232,6 @@ CONFIG_GPIO_TS4900=y CONFIG_POWER_RESET=y CONFIG_POWER_RESET_SYSCON=y CONFIG_POWER_RESET_SYSCON_POWEROFF=y -# CONFIG_HWMON is not set CONFIG_THERMAL_STATISTICS=y CONFIG_THERMAL_WRITABLE_TRIPS=y CONFIG_CPU_THERMAL=y @@ -257,18 +253,15 @@ CONFIG_DRM_DW_HDMI_AHB_AUDIO=m CONFIG_DRM_DW_HDMI_CEC=y CONFIG_DRM_IMX=y CONFIG_DRM_IMX_PARALLEL_DISPLAY=y -CONFIG_DRM_IMX_TVE=y CONFIG_DRM_IMX_LDB=y CONFIG_DRM_IMX_HDMI=y CONFIG_DRM_ETNAVIV=y -CONFIG_DRM_MXSFB=y CONFIG_FB_MODE_HELPERS=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_L4F00242T03=y CONFIG_LCD_PLATFORM=y CONFIG_BACKLIGHT_PWM=y CONFIG_BACKLIGHT_GPIO=y -CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_SOUND=m CONFIG_SND=m # CONFIG_SND_PCI is not set @@ -283,6 +276,19 @@ CONFIG_SND_SOC_IMX_SGTL5000=m CONFIG_SND_SOC_IMX_SPDIF=m CONFIG_SND_SOC_FSL_ASOC_CARD=m CONFIG_SND_SIMPLE_CARD=m +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_ITE is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_REDRAGON is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MONTEREY is not set CONFIG_HID_MULTITOUCH=m CONFIG_USB=y # CONFIG_USB_PCI is not set @@ -309,6 +315,7 @@ CONFIG_LEDS_CLASS=y CONFIG_LEDS_GPIO=y CONFIG_LEDS_PWM=y CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y CONFIG_LEDS_TRIGGER_BACKLIGHT=y CONFIG_LEDS_TRIGGER_DEFAULT_ON=y CONFIG_RTC_CLASS=y @@ -332,11 +339,13 @@ CONFIG_IIO_ST_LSM6DSX=m CONFIG_SENSORS_ISL29018=y CONFIG_MAG3110=y CONFIG_IIO_ST_MAGN_3AXIS=m +CONFIG_IIO_MUX=m CONFIG_MPL3115=y CONFIG_PWM=y CONFIG_PWM_IMX27=y CONFIG_NVMEM_IMX_OCOTP=y CONFIG_NVMEM_SNVS_LPGPR=y +CONFIG_MUX_GPIO=m CONFIG_EXT4_FS=y CONFIG_EXT4_FS_POSIX_ACL=y CONFIG_QUOTA=y @@ -376,11 +385,5 @@ CONFIG_FONTS=y CONFIG_FONT_8x8=y CONFIG_FONT_8x16=y # CONFIG_SYMBOLIC_ERRNAME is not set -# CONFIG_DEBUG_BUGVERBOSE is not set # CONFIG_ENABLE_MUST_CHECK is not set -# CONFIG_DEBUG_MISC is not set -# CONFIG_SCHED_DEBUG is not set -# CONFIG_DEBUG_PREEMPT is not set -# CONFIG_RCU_TRACE is not set -# CONFIG_FTRACE is not set # CONFIG_RUNTIME_TESTING_MENU is not set diff --git a/arch/arm/configs/tsimx6ul_defconfig b/arch/arm/configs/tsimx6ul_defconfig index ae6088834439d..415b90b2804c8 100644 --- a/arch/arm/configs/tsimx6ul_defconfig +++ b/arch/arm/configs/tsimx6ul_defconfig @@ -1,12 +1,11 @@ CONFIG_KERNEL_LZO=y CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y -CONFIG_NO_HZ=y +# CONFIG_CROSS_MEMORY_ATTACH is not set +CONFIG_NO_HZ_IDLE=y CONFIG_HIGH_RES_TIMERS=y CONFIG_PREEMPT=y CONFIG_PSI=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=18 CONFIG_CGROUPS=y CONFIG_MEMCG=y @@ -16,42 +15,32 @@ CONFIG_CFS_BANDWIDTH=y CONFIG_CGROUP_PIDS=y CONFIG_CGROUP_RDMA=y CONFIG_CGROUP_FREEZER=y -CONFIG_CPUSETS=y CONFIG_CGROUP_DEVICE=y CONFIG_CGROUP_CPUACCT=y -CONFIG_CGROUP_PERF=y CONFIG_CGROUP_BPF=y -CONFIG_NAMESPACES=y CONFIG_USER_NS=y CONFIG_CHECKPOINT_RESTORE=y -CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y -CONFIG_EXPERT=y -CONFIG_KALLSYMS_ALL=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_BPF_SYSCALL=y -CONFIG_PC104=y -CONFIG_PERF_EVENTS=y -# CONFIG_SLUB_DEBUG is not set # CONFIG_COMPAT_BRK is not set +CONFIG_SLAB=y +# CONFIG_SLAB_MERGE_DEFAULT is not set CONFIG_ARCH_MXC=y CONFIG_SOC_IMX6UL=y CONFIG_ARM_ERRATA_754322=y -CONFIG_ARM_ERRATA_764369=y CONFIG_ARM_ERRATA_775420=y -CONFIG_SMP=y CONFIG_HAVE_ARM_ARCH_TIMER=y CONFIG_ARM_PSCI=y -CONFIG_HIGHMEM=y +CONFIG_HZ_1000=y CONFIG_FORCE_MAX_ZONEORDER=14 CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" -CONFIG_KEXEC=y CONFIG_EFI=y CONFIG_CPU_FREQ=y CONFIG_CPU_FREQ_STAT=y CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y CONFIG_CPU_FREQ_GOV_POWERSAVE=y CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y CONFIG_CPUFREQ_DT=y CONFIG_ARM_IMX6Q_CPUFREQ=y CONFIG_CPU_IDLE=y @@ -59,38 +48,98 @@ CONFIG_ARM_CPUIDLE=y CONFIG_ARM_PSCI_CPUIDLE=y CONFIG_VFP=y CONFIG_NEON=y +# CONFIG_SUSPEND is not set +CONFIG_PM=y CONFIG_PM_DEBUG=y -CONFIG_PM_TEST_SUSPEND=y +# CONFIG_STACKPROTECTOR is not set CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -CONFIG_BLK_DEV_BSGLIB=y -CONFIG_BLK_DEV_THROTTLING=y +CONFIG_MODULE_COMPRESS=y +CONFIG_MODULE_COMPRESS_XZ=y +# CONFIG_MQ_IOSCHED_KYBER is not set CONFIG_BINFMT_MISC=y CONFIG_CMA=y CONFIG_NET=y CONFIG_PACKET=y +CONFIG_PACKET_DIAG=m CONFIG_UNIX=y +CONFIG_UNIX_DIAG=m CONFIG_TLS=m CONFIG_XFRM_USER=m +CONFIG_XFRM_INTERFACE=m +CONFIG_XFRM_SUB_POLICY=y +CONFIG_XFRM_STATISTICS=y +CONFIG_NET_KEY=m +CONFIG_NET_KEY_MIGRATE=y +CONFIG_XDP_SOCKETS=y +CONFIG_XDP_SOCKETS_DIAG=m CONFIG_INET=y CONFIG_IP_MULTICAST=y CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_FIB_TRIE_STATS=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_NET_IPIP=m CONFIG_NET_IPGRE_DEMUX=m CONFIG_NET_IPGRE=m +CONFIG_NET_IPGRE_BROADCAST=y +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y CONFIG_NET_IPVTI=m -CONFIG_NET_FOU=m +CONFIG_NET_FOU_IP_TUNNELS=y +CONFIG_INET_AH=m CONFIG_INET_ESP=m +CONFIG_INET_ESPINTCP=y CONFIG_INET_IPCOMP=m +CONFIG_INET_UDP_DIAG=m +CONFIG_INET_RAW_DIAG=m +CONFIG_INET_DIAG_DESTROY=y +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_TCP_CONG_HSTCP=m +CONFIG_TCP_CONG_HYBLA=m +CONFIG_TCP_CONG_NV=m +CONFIG_TCP_CONG_SCALABLE=m +CONFIG_TCP_CONG_LP=m +CONFIG_TCP_CONG_VENO=m +CONFIG_TCP_CONG_YEAH=m +CONFIG_TCP_CONG_ILLINOIS=m +CONFIG_TCP_CONG_DCTCP=m +CONFIG_TCP_CONG_CDG=m +CONFIG_TCP_CONG_BBR=m +CONFIG_TCP_MD5SIG=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_ESPINTCP=y +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_MIP6=m +CONFIG_IPV6_ILA=m +CONFIG_IPV6_VTI=m +CONFIG_IPV6_SIT=m +CONFIG_IPV6_SIT_6RD=y +CONFIG_IPV6_GRE=m +CONFIG_IPV6_SUBTREES=y +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y +CONFIG_IPV6_PIMSM_V2=y +CONFIG_IPV6_SEG6_LWTUNNEL=y +CONFIG_IPV6_SEG6_HMAC=y +CONFIG_IPV6_RPL_LWTUNNEL=y CONFIG_MPTCP=y +CONFIG_NETWORK_SECMARK=y CONFIG_NETFILTER=y CONFIG_BRIDGE_NETFILTER=m CONFIG_NF_CONNTRACK=m CONFIG_NF_LOG_NETDEV=m +CONFIG_NF_CONNTRACK_SECMARK=y CONFIG_NF_CONNTRACK_ZONES=y CONFIG_NF_CONNTRACK_PROCFS=y CONFIG_NF_CONNTRACK_EVENTS=y @@ -145,6 +194,8 @@ CONFIG_NETFILTER_XT_SET=m CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m +CONFIG_NETFILTER_XT_TARGET_CT=m CONFIG_NETFILTER_XT_TARGET_DSCP=m CONFIG_NETFILTER_XT_TARGET_HMARK=m CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m @@ -153,10 +204,10 @@ CONFIG_NETFILTER_XT_TARGET_LOG=m CONFIG_NETFILTER_XT_TARGET_MARK=m CONFIG_NETFILTER_XT_TARGET_NFLOG=m CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m -CONFIG_NETFILTER_XT_TARGET_NOTRACK=m CONFIG_NETFILTER_XT_TARGET_TEE=m CONFIG_NETFILTER_XT_TARGET_TPROXY=m CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFILTER_XT_TARGET_SECMARK=m CONFIG_NETFILTER_XT_TARGET_TCPMSS=m CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m @@ -170,7 +221,6 @@ CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m CONFIG_NETFILTER_XT_MATCH_CONNMARK=m CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m CONFIG_NETFILTER_XT_MATCH_CPU=m -CONFIG_NETFILTER_XT_MATCH_DCCP=m CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m CONFIG_NETFILTER_XT_MATCH_DSCP=m CONFIG_NETFILTER_XT_MATCH_ESP=m @@ -203,6 +253,22 @@ CONFIG_NETFILTER_XT_MATCH_TCPMSS=m CONFIG_NETFILTER_XT_MATCH_TIME=m CONFIG_NETFILTER_XT_MATCH_U32=m CONFIG_IP_SET=m +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPMARK=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_IPMAC=m +CONFIG_IP_SET_HASH_MAC=m +CONFIG_IP_SET_HASH_NETPORTNET=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETNET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m CONFIG_IP_VS=m CONFIG_IP_VS_IPV6=y CONFIG_IP_VS_DEBUG=y @@ -224,7 +290,8 @@ CONFIG_IP_VS_SH=m CONFIG_IP_VS_MH=m CONFIG_IP_VS_SED=m CONFIG_IP_VS_NQ=m -CONFIG_IP_VS_NFCT=y +CONFIG_IP_VS_FTP=m +CONFIG_IP_VS_PE_SIP=m CONFIG_NFT_DUP_IPV4=m CONFIG_NFT_FIB_IPV4=m CONFIG_NF_TABLES_ARP=y @@ -300,13 +367,20 @@ CONFIG_BRIDGE_EBT_SNAT=m CONFIG_BRIDGE_EBT_LOG=m CONFIG_BRIDGE_EBT_NFLOG=m CONFIG_BPFILTER=y +CONFIG_IP_DCCP=m +CONFIG_RDS=m +CONFIG_RDS_TCP=m CONFIG_L2TP=m CONFIG_L2TP_V3=y CONFIG_L2TP_IP=m CONFIG_L2TP_ETH=m CONFIG_BRIDGE=m CONFIG_BRIDGE_VLAN_FILTERING=y +CONFIG_BRIDGE_MRP=y CONFIG_VLAN_8021Q=m +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_VLAN_8021Q_MVRP=y +CONFIG_LLC2=m CONFIG_6LOWPAN=m CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m CONFIG_6LOWPAN_GHC_UDP=m @@ -314,13 +388,30 @@ CONFIG_6LOWPAN_GHC_ICMPV6=m CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m +CONFIG_IEEE802154=m +CONFIG_IEEE802154_NL802154_EXPERIMENTAL=y +CONFIG_IEEE802154_6LOWPAN=m +CONFIG_MAC802154=m +CONFIG_NET_SCHED=y CONFIG_DNS_RESOLVER=y +CONFIG_BATMAN_ADV=m +CONFIG_BATMAN_ADV_NC=y +CONFIG_BATMAN_ADV_DEBUG=y +CONFIG_BATMAN_ADV_SYSFS=y +CONFIG_OPENVSWITCH=m +CONFIG_VSOCKETS=m +CONFIG_NETLINK_DIAG=m +CONFIG_HSR=m +CONFIG_CGROUP_NET_PRIO=y CONFIG_BPF_JIT=y -CONFIG_CAN=y +CONFIG_BPF_STREAM_PARSER=y +CONFIG_CAN=m CONFIG_CAN_J1939=m CONFIG_CAN_ISOTP=m CONFIG_CAN_VCAN=m -CONFIG_CAN_FLEXCAN=y +CONFIG_CAN_VXCAN=m +CONFIG_CAN_SLCAN=m +CONFIG_CAN_FLEXCAN=m CONFIG_CAN_8DEV_USB=m CONFIG_CAN_EMS_USB=m CONFIG_CAN_ESD_USB2=m @@ -329,16 +420,42 @@ CONFIG_CAN_KVASER_USB=m CONFIG_CAN_MCBA_USB=m CONFIG_CAN_PEAK_USB=m CONFIG_CAN_UCAN=m -CONFIG_BT=y +CONFIG_BT=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y CONFIG_BT_BNEP=m -CONFIG_BT_HCIUART=y +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=m +CONFIG_BT_HS=y +CONFIG_BT_6LOWPAN=m +CONFIG_BT_LEDS=y +CONFIG_BT_MSFTEXT=y +CONFIG_BT_HCIBTUSB=m +CONFIG_BT_HCIBTUSB_MTK=y +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_ATH3K=y CONFIG_BT_HCIUART_LL=y -CONFIG_CFG80211=y +CONFIG_BT_HCIUART_INTEL=y +CONFIG_BT_HCIUART_BCM=y +CONFIG_BT_HCIUART_RTL=y +CONFIG_BT_HCIUART_QCA=y +CONFIG_BT_HCIUART_AG6XX=y +CONFIG_BT_HCIUART_MRVL=y +CONFIG_BT_HCIBCM203X=m +CONFIG_BT_HCIBPA10X=m +CONFIG_BT_HCIBFUSB=m +CONFIG_BT_HCIVHCI=m +CONFIG_BT_MRVL=m +CONFIG_BT_ATH3K=m +CONFIG_BT_MTKUART=m +CONFIG_CFG80211=m # CONFIG_CFG80211_DEFAULT_PS is not set CONFIG_CFG80211_WEXT=y -CONFIG_MAC80211=y -CONFIG_RFKILL=y -CONFIG_RFKILL_INPUT=y +CONFIG_MAC80211=m +CONFIG_MAC80211_MESH=y +CONFIG_RFKILL=m +CONFIG_FAILOVER=m CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y # CONFIG_STANDALONE is not set @@ -348,24 +465,16 @@ CONFIG_IMX_WEIM=y CONFIG_TSPC104=y CONFIG_CONNECTOR=y CONFIG_MTD=y -CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_OF_PARTS is not set CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_JEDECPROBE=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_CFI_STAA=y -CONFIG_MTD_DATAFLASH=y -CONFIG_MTD_SST25L=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_NAND_MXC=y +CONFIG_MTD_CFI=m +CONFIG_MTD_JEDECPROBE=m +CONFIG_MTD_CFI_INTELEXT=m +CONFIG_MTD_CFI_AMDSTD=m +CONFIG_MTD_CFI_STAA=m +CONFIG_MTD_SST25L=m CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_FASTMAP=y -CONFIG_MTD_UBI_BLOCK=y CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=65536 CONFIG_EEPROM_AT24=y CONFIG_EEPROM_AT25=y CONFIG_SCSI=y @@ -382,12 +491,25 @@ CONFIG_NETDEVICES=y CONFIG_BONDING=m CONFIG_DUMMY=m CONFIG_WIREGUARD=m +CONFIG_EQUALIZER=m +CONFIG_NET_TEAM=m +CONFIG_NET_TEAM_MODE_BROADCAST=m +CONFIG_NET_TEAM_MODE_ROUNDROBIN=m +CONFIG_NET_TEAM_MODE_RANDOM=m +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m +CONFIG_NET_TEAM_MODE_LOADBALANCE=m CONFIG_MACVLAN=m +CONFIG_MACVTAP=m CONFIG_IPVLAN=m +CONFIG_IPVTAP=m CONFIG_VXLAN=m CONFIG_GENEVE=m +CONFIG_BAREUDP=m +CONFIG_MACSEC=m CONFIG_TUN=m CONFIG_VETH=m +CONFIG_NLMON=m +CONFIG_NET_VRF=m # CONFIG_NET_VENDOR_ALACRITECH is not set # CONFIG_NET_VENDOR_AMAZON is not set # CONFIG_NET_VENDOR_AQUANTIA is not set @@ -447,6 +569,7 @@ CONFIG_USB_PEGASUS=m CONFIG_USB_RTL8150=m CONFIG_USB_RTL8152=m CONFIG_USB_LAN78XX=m +CONFIG_USB_USBNET=m CONFIG_USB_NET_CDC_EEM=m CONFIG_USB_NET_HUAWEI_CDC_NCM=m CONFIG_USB_NET_CDC_MBIM=m @@ -458,6 +581,11 @@ CONFIG_USB_NET_SMSC95XX=m CONFIG_USB_NET_GL620A=m CONFIG_USB_NET_PLUSB=m CONFIG_USB_NET_MCS7830=m +CONFIG_USB_NET_RNDIS_HOST=m +CONFIG_USB_ALI_M5632=y +CONFIG_USB_AN2720=y +CONFIG_USB_EPSON2888=y +CONFIG_USB_KC2190=y CONFIG_USB_NET_CX82310_ETH=m CONFIG_USB_NET_KALMIA=m CONFIG_USB_NET_QMI_WWAN=m @@ -469,76 +597,70 @@ CONFIG_USB_VL600=m CONFIG_USB_NET_CH9200=m CONFIG_USB_NET_AQC111=m # CONFIG_WLAN_VENDOR_ADMTEK is not set -CONFIG_ATH9K=m CONFIG_ATH9K_HTC=m CONFIG_CARL9170=m CONFIG_AR5523=m CONFIG_ATH10K=m CONFIG_ATH10K_USB=m -CONFIG_WCN36XX=m -# CONFIG_WLAN_VENDOR_ATMEL is not set +CONFIG_AT76C50X_USB=m CONFIG_BRCMFMAC=m +# CONFIG_BRCMFMAC_SDIO is not set CONFIG_BRCMFMAC_USB=y # CONFIG_WLAN_VENDOR_CISCO is not set # CONFIG_WLAN_VENDOR_INTEL is not set # CONFIG_WLAN_VENDOR_INTERSIL is not set -# CONFIG_WLAN_VENDOR_MARVELL is not set +CONFIG_MWIFIEX=m +CONFIG_MWIFIEX_USB=m CONFIG_MT7601U=m CONFIG_MT76x0U=m CONFIG_MT76x2U=m CONFIG_MT7663U=m # CONFIG_WLAN_VENDOR_MICROCHIP is not set CONFIG_RT2X00=m +CONFIG_RT2500USB=m +CONFIG_RT73USB=m +CONFIG_RT2800USB=m +CONFIG_RT2800USB_RT3573=y +CONFIG_RT2800USB_RT53XX=y +CONFIG_RT2800USB_RT55XX=y +CONFIG_RT2800USB_UNKNOWN=y CONFIG_RTL8187=m -CONFIG_RTL_CARDS=m CONFIG_RTL8192CU=m # CONFIG_RTLWIFI_DEBUG is not set CONFIG_RTL8XXXU=m CONFIG_RTL8XXXU_UNTESTED=y CONFIG_RTW88=m -# CONFIG_WLAN_VENDOR_RSI is not set +CONFIG_RSI_91X=m +# CONFIG_RSI_DEBUGFS is not set +# CONFIG_RSI_SDIO is not set # CONFIG_WLAN_VENDOR_ST is not set CONFIG_WL12XX=m CONFIG_WLCORE_SDIO=m # CONFIG_WILINK_PLATFORM_DATA is not set CONFIG_USB_ZD1201=m -CONFIG_USB_NET_RNDIS_WLAN=m -CONFIG_INPUT_EVDEV=y -CONFIG_INPUT_EVBUG=m +CONFIG_ZD1211RW=m +# CONFIG_WLAN_VENDOR_QUANTENNA is not set +# CONFIG_INPUT_LEDS is not set +CONFIG_INPUT_MOUSEDEV=m +CONFIG_INPUT_EVDEV=m +# CONFIG_KEYBOARD_ATKBD is not set CONFIG_KEYBOARD_GPIO=y CONFIG_KEYBOARD_MATRIX=m CONFIG_KEYBOARD_SNVS_PWRKEY=y CONFIG_KEYBOARD_IMX=y -CONFIG_MOUSE_PS2=m -CONFIG_MOUSE_PS2_ELANTECH=y +# CONFIG_MOUSE_PS2 is not set CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_ADS7846=y -CONFIG_TOUCHSCREEN_AD7879=y -CONFIG_TOUCHSCREEN_AD7879_I2C=y -CONFIG_TOUCHSCREEN_ATMEL_MXT=y -CONFIG_TOUCHSCREEN_EGALAX=y -CONFIG_TOUCHSCREEN_GOODIX=y -CONFIG_TOUCHSCREEN_ILI210X=y -CONFIG_TOUCHSCREEN_MAX11801=y -CONFIG_TOUCHSCREEN_IMX6UL_TSC=y -CONFIG_TOUCHSCREEN_EDT_FT5X06=y -CONFIG_TOUCHSCREEN_TSC2004=y -CONFIG_TOUCHSCREEN_TSC2007=y -CONFIG_TOUCHSCREEN_SX8654=y -CONFIG_TOUCHSCREEN_COLIBRI_VF50=y -CONFIG_INPUT_MISC=y -CONFIG_INPUT_MMA8450=y -CONFIG_SERIO_SERPORT=m -CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_TOUCHSCREEN_ADS7846=m +# CONFIG_SERIO is not set # CONFIG_LEGACY_PTYS is not set -CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250=m CONFIG_SERIAL_8250_NR_UARTS=24 CONFIG_SERIAL_8250_RUNTIME_UARTS=24 -CONFIG_SERIAL_8250_TS=m -CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_OF_PLATFORM=m CONFIG_SERIAL_IMX=y CONFIG_SERIAL_IMX_CONSOLE=y CONFIG_SERIAL_DEV_BUS=y +# CONFIG_RANDOM_TRUST_BOOTLOADER is not set # CONFIG_I2C_COMPAT is not set CONFIG_I2C_CHARDEV=y CONFIG_I2C_MUX=y @@ -549,27 +671,20 @@ CONFIG_I2C_GPIO=y CONFIG_I2C_IMX=y CONFIG_I2C_OCORES=m CONFIG_SPI=y -CONFIG_SPI_FSL_QUADSPI=y CONFIG_SPI_GPIO=y CONFIG_SPI_IMX=y CONFIG_SPI_OCORES=m CONFIG_SPI_SPIDEV=y -CONFIG_PPS_CLIENT_LDISC=m -CONFIG_PPS_CLIENT_GPIO=m +CONFIG_PTP_1588_CLOCK=m CONFIG_GPIO_SYSFS=y CONFIG_GPIO_MXC=y -CONFIG_GPIO_SIOX=m CONFIG_GPIO_TS71XXWEIM=y CONFIG_GPIO_PCA953X=m -CONFIG_GPIO_PCF857X=m CONFIG_GPIO_TS4900=y -CONFIG_GPIO_74X164=m CONFIG_POWER_RESET=y CONFIG_POWER_RESET_TS_SUPERVISOR=y CONFIG_POWER_RESET_SYSCON=y CONFIG_POWER_RESET_SYSCON_POWEROFF=y -CONFIG_POWER_SUPPLY=y -CONFIG_SENSORS_GPIO_FAN=y CONFIG_SENSORS_IIO_HWMON=y CONFIG_THERMAL=y CONFIG_THERMAL_STATISTICS=y @@ -579,276 +694,11 @@ CONFIG_IMX_THERMAL=y CONFIG_WATCHDOG=y CONFIG_TS_WDT_MICRO=y CONFIG_IMX2_WDT=y -CONFIG_IMX7ULP_WDT=y CONFIG_MFD_TS_SUPERVISOR=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_ANATOP=y CONFIG_REGULATOR_GPIO=y -CONFIG_REGULATOR_PFUZE100=y -CONFIG_RC_CORE=y -CONFIG_RC_DEVICES=y -CONFIG_IR_GPIO_CIR=y -# CONFIG_MEDIA_CEC_SUPPORT is not set -CONFIG_MEDIA_SUPPORT=y -CONFIG_MEDIA_USB_SUPPORT=y -CONFIG_USB_VIDEO_CLASS=m -CONFIG_USB_M5602=m -CONFIG_USB_STV06XX=m -CONFIG_USB_GL860=m -CONFIG_USB_GSPCA_BENQ=m -CONFIG_USB_GSPCA_CONEX=m -CONFIG_USB_GSPCA_CPIA1=m -CONFIG_USB_GSPCA_DTCS033=m -CONFIG_USB_GSPCA_ETOMS=m -CONFIG_USB_GSPCA_FINEPIX=m -CONFIG_USB_GSPCA_JEILINJ=m -CONFIG_USB_GSPCA_JL2005BCD=m -CONFIG_USB_GSPCA_KINECT=m -CONFIG_USB_GSPCA_KONICA=m -CONFIG_USB_GSPCA_MARS=m -CONFIG_USB_GSPCA_MR97310A=m -CONFIG_USB_GSPCA_NW80X=m -CONFIG_USB_GSPCA_OV519=m -CONFIG_USB_GSPCA_OV534=m -CONFIG_USB_GSPCA_OV534_9=m -CONFIG_USB_GSPCA_PAC207=m -CONFIG_USB_GSPCA_PAC7302=m -CONFIG_USB_GSPCA_PAC7311=m -CONFIG_USB_GSPCA_SE401=m -CONFIG_USB_GSPCA_SN9C2028=m -CONFIG_USB_GSPCA_SN9C20X=m -CONFIG_USB_GSPCA_SONIXB=m -CONFIG_USB_GSPCA_SONIXJ=m -CONFIG_USB_GSPCA_SPCA500=m -CONFIG_USB_GSPCA_SPCA501=m -CONFIG_USB_GSPCA_SPCA505=m -CONFIG_USB_GSPCA_SPCA506=m -CONFIG_USB_GSPCA_SPCA508=m -CONFIG_USB_GSPCA_SPCA561=m -CONFIG_USB_GSPCA_SPCA1528=m -CONFIG_USB_GSPCA_SQ905=m -CONFIG_USB_GSPCA_SQ905C=m -CONFIG_USB_GSPCA_SQ930X=m -CONFIG_USB_GSPCA_STK014=m -CONFIG_USB_GSPCA_STK1135=m -CONFIG_USB_GSPCA_STV0680=m -CONFIG_USB_GSPCA_SUNPLUS=m -CONFIG_USB_GSPCA_T613=m -CONFIG_USB_GSPCA_TOPRO=m -CONFIG_USB_GSPCA_TOUPTEK=m -CONFIG_USB_GSPCA_TV8532=m -CONFIG_USB_GSPCA_VC032X=m -CONFIG_USB_GSPCA_VICAM=m -CONFIG_USB_GSPCA_XIRLINK_CIT=m -CONFIG_USB_GSPCA_ZC3XX=m -CONFIG_USB_PWC=m -CONFIG_VIDEO_CPIA2=m -CONFIG_USB_ZR364XX=m -CONFIG_USB_STKWEBCAM=m -CONFIG_USB_S2255=m -CONFIG_VIDEO_USBTV=m -CONFIG_VIDEO_PVRUSB2=m -CONFIG_VIDEO_HDPVR=m -CONFIG_VIDEO_STK1160_COMMON=m -CONFIG_VIDEO_GO7007=m -CONFIG_VIDEO_AU0828=m -CONFIG_VIDEO_CX231XX=m -CONFIG_VIDEO_TM6000=m -CONFIG_DVB_USB=m -CONFIG_DVB_USB_A800=m -CONFIG_DVB_USB_DIBUSB_MB=m -CONFIG_DVB_USB_DIBUSB_MC=m -CONFIG_DVB_USB_DIB0700=m -CONFIG_DVB_USB_UMT_010=m -CONFIG_DVB_USB_CXUSB=m -CONFIG_DVB_USB_M920X=m -CONFIG_DVB_USB_DIGITV=m -CONFIG_DVB_USB_VP7045=m -CONFIG_DVB_USB_VP702X=m -CONFIG_DVB_USB_GP8PSK=m -CONFIG_DVB_USB_NOVA_T_USB2=m -CONFIG_DVB_USB_TTUSB2=m -CONFIG_DVB_USB_DTT200U=m -CONFIG_DVB_USB_OPERA1=m -CONFIG_DVB_USB_AF9005=m -CONFIG_DVB_USB_AF9005_REMOTE=m -CONFIG_DVB_USB_PCTV452E=m -CONFIG_DVB_USB_DW2102=m -CONFIG_DVB_USB_CINERGY_T2=m -CONFIG_DVB_USB_DTV5100=m -CONFIG_DVB_USB_AZ6027=m -CONFIG_DVB_USB_TECHNISAT_USB2=m -CONFIG_DVB_USB_V2=m -CONFIG_DVB_USB_AF9015=m -CONFIG_DVB_USB_AF9035=m -CONFIG_DVB_USB_ANYSEE=m -CONFIG_DVB_USB_AU6610=m -CONFIG_DVB_USB_AZ6007=m -CONFIG_DVB_USB_CE6230=m -CONFIG_DVB_USB_EC168=m -CONFIG_DVB_USB_GL861=m -CONFIG_DVB_USB_LME2510=m -CONFIG_DVB_USB_MXL111SF=m -CONFIG_DVB_USB_RTL28XXU=m -CONFIG_DVB_USB_DVBSKY=m -CONFIG_DVB_USB_ZD1301=m -CONFIG_SMS_USB_DRV=m -CONFIG_DVB_B2C2_FLEXCOP_USB=m -CONFIG_DVB_AS102=m -CONFIG_VIDEO_EM28XX=m -CONFIG_VIDEO_EM28XX_V4L2=m -CONFIG_VIDEO_EM28XX_ALSA=m -CONFIG_VIDEO_EM28XX_DVB=m -CONFIG_USB_AIRSPY=m -CONFIG_USB_HACKRF=m -CONFIG_USB_MSI2500=m -CONFIG_V4L_PLATFORM_DRIVERS=y -CONFIG_VIDEO_MUX=y -CONFIG_V4L_MEM2MEM_DRIVERS=y -CONFIG_VIDEO_CODA=m -CONFIG_VIDEO_IMX_PXP=y -# CONFIG_VIDEO_IR_I2C is not set -# CONFIG_CXD2880_SPI_DRV is not set -# CONFIG_MEDIA_TUNER_SIMPLE is not set -# CONFIG_MEDIA_TUNER_TDA18250 is not set -# CONFIG_MEDIA_TUNER_TDA8290 is not set -# CONFIG_MEDIA_TUNER_TDA827X is not set -# CONFIG_MEDIA_TUNER_TDA18271 is not set -# CONFIG_MEDIA_TUNER_TDA9887 is not set -# CONFIG_MEDIA_TUNER_TEA5761 is not set -# CONFIG_MEDIA_TUNER_TEA5767 is not set -# CONFIG_MEDIA_TUNER_MT20XX is not set -# CONFIG_MEDIA_TUNER_MT2060 is not set -# CONFIG_MEDIA_TUNER_MT2063 is not set -# CONFIG_MEDIA_TUNER_MT2266 is not set -# CONFIG_MEDIA_TUNER_MT2131 is not set -# CONFIG_MEDIA_TUNER_QT1010 is not set -# CONFIG_MEDIA_TUNER_XC4000 is not set -# CONFIG_MEDIA_TUNER_MXL5005S is not set -# CONFIG_MEDIA_TUNER_MXL5007T is not set -# CONFIG_MEDIA_TUNER_MC44S803 is not set -# CONFIG_MEDIA_TUNER_MAX2165 is not set -# CONFIG_MEDIA_TUNER_TDA18218 is not set -# CONFIG_MEDIA_TUNER_FC0011 is not set -# CONFIG_MEDIA_TUNER_FC0012 is not set -# CONFIG_MEDIA_TUNER_FC0013 is not set -# CONFIG_MEDIA_TUNER_TDA18212 is not set -# CONFIG_MEDIA_TUNER_E4000 is not set -# CONFIG_MEDIA_TUNER_FC2580 is not set -# CONFIG_MEDIA_TUNER_M88RS6000T is not set -# CONFIG_MEDIA_TUNER_TUA9001 is not set -# CONFIG_MEDIA_TUNER_SI2157 is not set -# CONFIG_MEDIA_TUNER_IT913X is not set -# CONFIG_MEDIA_TUNER_R820T is not set -# CONFIG_MEDIA_TUNER_MXL301RF is not set -# CONFIG_MEDIA_TUNER_QM1D1C0042 is not set -# CONFIG_MEDIA_TUNER_QM1D1B0004 is not set -# CONFIG_DVB_STB0899 is not set -# CONFIG_DVB_STB6100 is not set -# CONFIG_DVB_STV090x is not set -# CONFIG_DVB_STV0910 is not set -# CONFIG_DVB_STV6110x is not set -# CONFIG_DVB_STV6111 is not set -# CONFIG_DVB_MXL5XX is not set -# CONFIG_DVB_M88DS3103 is not set -# CONFIG_DVB_DRXK is not set -# CONFIG_DVB_TDA18271C2DD is not set -# CONFIG_DVB_SI2165 is not set -# CONFIG_DVB_MN88472 is not set -# CONFIG_DVB_MN88473 is not set -# CONFIG_DVB_CX24110 is not set -# CONFIG_DVB_CX24123 is not set -# CONFIG_DVB_MT312 is not set -# CONFIG_DVB_ZL10036 is not set -# CONFIG_DVB_ZL10039 is not set -# CONFIG_DVB_S5H1420 is not set -# CONFIG_DVB_STV0288 is not set -# CONFIG_DVB_STB6000 is not set -# CONFIG_DVB_STV0299 is not set -# CONFIG_DVB_STV6110 is not set -# CONFIG_DVB_STV0900 is not set -# CONFIG_DVB_TDA8083 is not set -# CONFIG_DVB_TDA10086 is not set -# CONFIG_DVB_TDA8261 is not set -# CONFIG_DVB_VES1X93 is not set -# CONFIG_DVB_TUNER_ITD1000 is not set -# CONFIG_DVB_TUNER_CX24113 is not set -# CONFIG_DVB_TDA826X is not set -# CONFIG_DVB_TUA6100 is not set -# CONFIG_DVB_CX24116 is not set -# CONFIG_DVB_CX24117 is not set -# CONFIG_DVB_CX24120 is not set -# CONFIG_DVB_SI21XX is not set -# CONFIG_DVB_TS2020 is not set -# CONFIG_DVB_DS3000 is not set -# CONFIG_DVB_MB86A16 is not set -# CONFIG_DVB_TDA10071 is not set -# CONFIG_DVB_SP8870 is not set -# CONFIG_DVB_SP887X is not set -# CONFIG_DVB_CX22700 is not set -# CONFIG_DVB_CX22702 is not set -# CONFIG_DVB_S5H1432 is not set -# CONFIG_DVB_DRXD is not set -# CONFIG_DVB_L64781 is not set -# CONFIG_DVB_TDA1004X is not set -# CONFIG_DVB_NXT6000 is not set -# CONFIG_DVB_MT352 is not set -# CONFIG_DVB_DIB7000M is not set -# CONFIG_DVB_DIB7000P is not set -# CONFIG_DVB_DIB9000 is not set -# CONFIG_DVB_TDA10048 is not set -# CONFIG_DVB_STV0367 is not set -# CONFIG_DVB_CXD2820R is not set -# CONFIG_DVB_CXD2841ER is not set -# CONFIG_DVB_RTL2832_SDR is not set -# CONFIG_DVB_SI2168 is not set -# CONFIG_DVB_ZD1301_DEMOD is not set -# CONFIG_DVB_CXD2880 is not set -# CONFIG_DVB_VES1820 is not set -# CONFIG_DVB_TDA10021 is not set -# CONFIG_DVB_TDA10023 is not set -# CONFIG_DVB_STV0297 is not set -# CONFIG_DVB_NXT200X is not set -# CONFIG_DVB_OR51211 is not set -# CONFIG_DVB_OR51132 is not set -# CONFIG_DVB_BCM3510 is not set -# CONFIG_DVB_LGDT330X is not set -# CONFIG_DVB_LGDT3305 is not set -# CONFIG_DVB_LGDT3306A is not set -# CONFIG_DVB_LG2160 is not set -# CONFIG_DVB_S5H1409 is not set -# CONFIG_DVB_AU8522_DTV is not set -# CONFIG_DVB_AU8522_V4L is not set -# CONFIG_DVB_S5H1411 is not set -# CONFIG_DVB_S921 is not set -# CONFIG_DVB_DIB8000 is not set -# CONFIG_DVB_MB86A20S is not set -# CONFIG_DVB_TC90522 is not set -# CONFIG_DVB_MN88443X is not set -# CONFIG_DVB_PLL is not set -# CONFIG_DVB_TUNER_DIB0070 is not set -# CONFIG_DVB_TUNER_DIB0090 is not set -# CONFIG_DVB_DRX39XYJ is not set -# CONFIG_DVB_LNBH25 is not set -# CONFIG_DVB_LNBH29 is not set -# CONFIG_DVB_LNBP21 is not set -# CONFIG_DVB_LNBP22 is not set -# CONFIG_DVB_ISL6405 is not set -# CONFIG_DVB_ISL6421 is not set -# CONFIG_DVB_ISL6423 is not set -# CONFIG_DVB_A8293 is not set -# CONFIG_DVB_LGS8GL5 is not set -# CONFIG_DVB_LGS8GXX is not set -# CONFIG_DVB_ATBM8830 is not set -# CONFIG_DVB_TDA665x is not set -# CONFIG_DVB_IX2505V is not set -# CONFIG_DVB_M88RS2000 is not set -# CONFIG_DVB_HORUS3A is not set -# CONFIG_DVB_ASCOT2E is not set -# CONFIG_DVB_HELENE is not set -# CONFIG_DVB_CXD2099 is not set -# CONFIG_DVB_SP2 is not set CONFIG_IMX_IPUV3_CORE=y CONFIG_DRM=y CONFIG_DRM_PANEL_LVDS=y @@ -857,26 +707,40 @@ CONFIG_DRM_IMX=y CONFIG_DRM_IMX_PARALLEL_DISPLAY=y CONFIG_DRM_MXSFB=y CONFIG_FB_MODE_HELPERS=y +# CONFIG_FB_MX3 is not set CONFIG_FB_ST7565P=m -CONFIG_DRM_FBDEV_EMULATION=y CONFIG_LCD_CLASS_DEVICE=y +CONFIG_LCD_PLATFORM=y CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BACKLIGHT_PWM=m -CONFIG_BACKLIGHT_GPIO=m -CONFIG_SOUND=y -CONFIG_SND=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_BACKLIGHT_GPIO=y +CONFIG_SOUND=m +CONFIG_SND=m +CONFIG_SND_HRTIMER=m # CONFIG_SND_ARM is not set # CONFIG_SND_SPI is not set CONFIG_SND_USB_AUDIO=m -CONFIG_HID_MULTITOUCH=y +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_ITE is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_REDRAGON is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MONTEREY is not set +CONFIG_HID_MULTITOUCH=m +CONFIG_USB_HID=m CONFIG_USB=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y CONFIG_USB_OTG=y CONFIG_USB_OTG_FSM=m -CONFIG_USB_LEDS_TRIGGER_USBPORT=m CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_MXC=y -CONFIG_USB_PRINTER=m CONFIG_USB_STORAGE=y CONFIG_USB_CHIPIDEA=y CONFIG_USB_CHIPIDEA_UDC=y @@ -933,51 +797,16 @@ CONFIG_USB_SERIAL_WISHBONE=m CONFIG_USB_SERIAL_SSU100=m CONFIG_USB_SERIAL_QT2=m CONFIG_USB_SERIAL_UPD78F0730=m -CONFIG_USB_SERIAL_DEBUG=m -CONFIG_USB_TEST=m -CONFIG_USB_EHSET_TEST_FIXTURE=m CONFIG_NOP_USB_XCEIV=y CONFIG_USB_MXS_PHY=y CONFIG_USB_GADGET=y CONFIG_USB_FSL_USB2=y -CONFIG_USB_CONFIGFS=y -CONFIG_USB_CONFIGFS_SERIAL=y -CONFIG_USB_CONFIGFS_ACM=y -CONFIG_USB_CONFIGFS_OBEX=y -CONFIG_USB_CONFIGFS_NCM=y -CONFIG_USB_CONFIGFS_ECM=y -CONFIG_USB_CONFIGFS_ECM_SUBSET=y -CONFIG_USB_CONFIGFS_RNDIS=y -CONFIG_USB_CONFIGFS_EEM=y -CONFIG_USB_CONFIGFS_MASS_STORAGE=y -CONFIG_USB_CONFIGFS_F_LB_SS=y -CONFIG_USB_CONFIGFS_F_FS=y -CONFIG_USB_CONFIGFS_F_UAC1=y -CONFIG_USB_CONFIGFS_F_UAC2=y -CONFIG_USB_CONFIGFS_F_MIDI=y -CONFIG_USB_CONFIGFS_F_HID=y -CONFIG_USB_CONFIGFS_F_UVC=y -CONFIG_USB_CONFIGFS_F_PRINTER=y -CONFIG_USB_ZERO=m -CONFIG_USB_AUDIO=m +CONFIG_USB_CONFIGFS=m CONFIG_USB_ETH=m CONFIG_USB_G_NCM=m CONFIG_USB_GADGETFS=m -CONFIG_USB_FUNCTIONFS=m -CONFIG_USB_FUNCTIONFS_ETH=y -CONFIG_USB_FUNCTIONFS_RNDIS=y -CONFIG_USB_FUNCTIONFS_GENERIC=y CONFIG_USB_MASS_STORAGE=m CONFIG_USB_G_SERIAL=m -CONFIG_USB_MIDI_GADGET=m -CONFIG_USB_G_PRINTER=m -CONFIG_USB_CDC_COMPOSITE=m -CONFIG_USB_G_ACM_MS=m -CONFIG_USB_G_MULTI=m -CONFIG_USB_G_HID=m -CONFIG_USB_G_DBGP=m -CONFIG_USB_G_WEBCAM=m -CONFIG_USB_RAW_GADGET=m CONFIG_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y @@ -986,46 +815,33 @@ CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y CONFIG_LEDS_GPIO=y CONFIG_LEDS_PWM=y -CONFIG_LEDS_USER=y CONFIG_LEDS_TRIGGER_TIMER=y -CONFIG_LEDS_TRIGGER_ONESHOT=y -CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_ONESHOT=m +CONFIG_LEDS_TRIGGER_HEARTBEAT=m CONFIG_LEDS_TRIGGER_BACKLIGHT=y CONFIG_LEDS_TRIGGER_CPU=y CONFIG_LEDS_TRIGGER_ACTIVITY=m -CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_LEDS_TRIGGER_GPIO=m CONFIG_LEDS_TRIGGER_DEFAULT_ON=y CONFIG_LEDS_TRIGGER_TRANSIENT=m -CONFIG_LEDS_TRIGGER_CAMERA=m CONFIG_LEDS_TRIGGER_PANIC=y CONFIG_LEDS_TRIGGER_NETDEV=m CONFIG_LEDS_TRIGGER_PATTERN=m -CONFIG_LEDS_TRIGGER_AUDIO=m CONFIG_RTC_CLASS=y +# CONFIG_RTC_NVMEM is not set CONFIG_RTC_INTF_DEV_UIE_EMUL=y CONFIG_RTC_DRV_DS1307=y CONFIG_RTC_DRV_TSSUPERVISOR=y -CONFIG_RTC_DRV_MXC=y CONFIG_RTC_DRV_SNVS=y CONFIG_DMADEVICES=y CONFIG_IMX_SDMA=y -# CONFIG_MX3_IPU is not set -CONFIG_DMATEST=m # CONFIG_VIRTIO_MENU is not set # CONFIG_VHOST_MENU is not set -CONFIG_STAGING=y -CONFIG_STAGING_MEDIA=y CONFIG_COMMON_CLK_PWM=y +# CONFIG_IOMMU_SUPPORT is not set CONFIG_IMX_GPCV2_PM_DOMAINS=y CONFIG_IIO=y -CONFIG_IIO_BUFFER_CB=m -CONFIG_IIO_BUFFER_DMAENGINE=m -CONFIG_IIO_BUFFER_HW_CONSUMER=m -CONFIG_IIO_SW_DEVICE=m -CONFIG_IIO_SW_TRIGGER=m -CONFIG_IIO_TRIGGERED_EVENT=m CONFIG_MMA8452=y -CONFIG_IMX7D_ADC=y CONFIG_TS_SIMPLEADC=y CONFIG_TS_SUPERVISOR_ADC=y CONFIG_VF610_ADC=y @@ -1034,24 +850,15 @@ CONFIG_IIO_ST_LSM6DSX=m CONFIG_SENSORS_ISL29018=y CONFIG_MAG3110=y CONFIG_IIO_ST_MAGN_3AXIS=m -CONFIG_IIO_MUX=m -CONFIG_IIO_INTERRUPT_TRIGGER=m CONFIG_IIO_SYSFS_TRIGGER=m CONFIG_MPL3115=y CONFIG_TS_SUPERVISOR_TEMP=y CONFIG_PWM=y -CONFIG_PWM_FSL_FTM=y CONFIG_PWM_IMX27=y -CONFIG_PWM_IMX_TPM=y -CONFIG_PWM_TS=y +CONFIG_PWM_TS=m CONFIG_TSWEIM_FPGA_INTC=y CONFIG_NVMEM_IMX_OCOTP=y CONFIG_NVMEM_SNVS_LPGPR=y -CONFIG_TEE=y -CONFIG_OPTEE=y -CONFIG_MUX_MMIO=y -CONFIG_SIOX=m -CONFIG_SIOX_BUS_GPIO=m CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y @@ -1059,33 +866,34 @@ CONFIG_EXT2_FS_SECURITY=y CONFIG_EXT3_FS=y CONFIG_EXT3_FS_POSIX_ACL=y CONFIG_EXT3_FS_SECURITY=y +CONFIG_F2FS_FS=y +CONFIG_F2FS_FS_SECURITY=y CONFIG_QUOTA=y CONFIG_QUOTA_NETLINK_INTERFACE=y # CONFIG_PRINT_QUOTA_WARNING is not set -CONFIG_AUTOFS4_FS=y -CONFIG_FUSE_FS=y +CONFIG_AUTOFS4_FS=m +CONFIG_FUSE_FS=m CONFIG_OVERLAY_FS=m -CONFIG_ISO9660_FS=m -CONFIG_JOLIET=y -CONFIG_ZISOFS=y -CONFIG_UDF_FS=m -CONFIG_MSDOS_FS=m CONFIG_VFAT_FS=y -CONFIG_EXFAT_FS=m +CONFIG_EXFAT_FS=y CONFIG_NTFS_FS=m CONFIG_NTFS_RW=y CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y +CONFIG_CONFIGFS_FS=y CONFIG_NFS_FS=y -CONFIG_NFS_V3_ACL=y CONFIG_ROOT_NFS=y +CONFIG_CIFS=m CONFIG_NLS_DEFAULT="cp437" CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ASCII=y CONFIG_NLS_ISO8859_1=y CONFIG_NLS_ISO8859_15=m CONFIG_NLS_UTF8=y -CONFIG_SECURITYFS=y +CONFIG_CRYPTO_ECDH=y +CONFIG_CRYPTO_CCM=y +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_CMAC=y CONFIG_CRYPTO_DEFLATE=y CONFIG_CRYPTO_LZO=y CONFIG_CRYPTO_DEV_FSL_CAAM=y @@ -1096,11 +904,8 @@ CONFIG_CRC7=m CONFIG_DMA_CMA=y CONFIG_CMA_SIZE_MBYTES=64 CONFIG_PRINTK_TIME=y -# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_SYMBOLIC_ERRNAME is not set +# CONFIG_ENABLE_MUST_CHECK is not set CONFIG_DEBUG_FS=y -# CONFIG_DEBUG_MISC is not set -# CONFIG_SCHED_DEBUG is not set -# CONFIG_DEBUG_PREEMPT is not set CONFIG_STACKTRACE=y -# CONFIG_FTRACE is not set # CONFIG_RUNTIME_TESTING_MENU is not set diff --git a/arch/arm/configs/tsimx6ul_minimal_defconfig b/arch/arm/configs/tsimx6ul_minimal_defconfig index 23d5d6dcde2bb..62876caaa17bf 100644 --- a/arch/arm/configs/tsimx6ul_minimal_defconfig +++ b/arch/arm/configs/tsimx6ul_minimal_defconfig @@ -1,5 +1,6 @@ CONFIG_KERNEL_LZO=y # CONFIG_SWAP is not set +CONFIG_SYSVIPC=y # CONFIG_CROSS_MEMORY_ATTACH is not set CONFIG_NO_HZ_IDLE=y CONFIG_HIGH_RES_TIMERS=y @@ -7,12 +8,8 @@ CONFIG_PREEMPT=y CONFIG_LOG_BUF_SHIFT=18 CONFIG_CGROUPS=y CONFIG_CC_OPTIMIZE_FOR_SIZE=y -# CONFIG_KALLSYMS is not set -# CONFIG_RSEQ is not set -CONFIG_EMBEDDED=y -# CONFIG_VM_EVENT_COUNTERS is not set # CONFIG_COMPAT_BRK is not set -CONFIG_SLOB=y +CONFIG_SLAB=y # CONFIG_SLAB_MERGE_DEFAULT is not set CONFIG_ARCH_MXC=y CONFIG_SOC_IMX6UL=y @@ -20,7 +17,7 @@ CONFIG_ARM_ERRATA_754322=y CONFIG_ARM_ERRATA_775420=y CONFIG_HAVE_ARM_ARCH_TIMER=y CONFIG_ARM_PSCI=y -CONFIG_HIGHMEM=y +CONFIG_HZ_1000=y CONFIG_FORCE_MAX_ZONEORDER=14 CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" CONFIG_CPU_FREQ=y @@ -42,12 +39,11 @@ CONFIG_PM_DEBUG=y # CONFIG_STACKPROTECTOR is not set CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_MODULE_COMPRESS=y +CONFIG_MODULE_COMPRESS_XZ=y # CONFIG_BLK_DEV_BSG is not set # CONFIG_MQ_IOSCHED_KYBER is not set CONFIG_BINFMT_MISC=y -# CONFIG_COREDUMP is not set CONFIG_CMA=y CONFIG_NET=y CONFIG_PACKET=y @@ -66,14 +62,12 @@ CONFIG_CFG80211=m CONFIG_CFG80211_WEXT=y CONFIG_MAC80211=m CONFIG_RFKILL=m -CONFIG_RFKILL_INPUT=y # CONFIG_ETHTOOL_NETLINK is not set CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y # CONFIG_STANDALONE is not set CONFIG_EXTRA_FIRMWARE="imx/sdma/sdma-imx6q.bin" CONFIG_EXTRA_FIRMWARE_DIR="firmware" -# CONFIG_ALLOW_DEV_COREDUMP is not set CONFIG_IMX_WEIM=y CONFIG_TSPC104=y CONFIG_CONNECTOR=y @@ -179,7 +173,6 @@ CONFIG_KEYBOARD_IMX=y CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_ADS7846=m # CONFIG_SERIO is not set -CONFIG_VT_HW_CONSOLE_BINDING=y # CONFIG_LEGACY_PTYS is not set CONFIG_SERIAL_8250=m CONFIG_SERIAL_8250_NR_UARTS=24 @@ -187,8 +180,6 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=24 CONFIG_SERIAL_OF_PLATFORM=m CONFIG_SERIAL_IMX=y CONFIG_SERIAL_IMX_CONSOLE=y -CONFIG_SERIAL_FSL_LPUART=y -CONFIG_SERIAL_FSL_LPUART_CONSOLE=y CONFIG_SERIAL_DEV_BUS=y # CONFIG_RANDOM_TRUST_BOOTLOADER is not set # CONFIG_I2C_COMPAT is not set @@ -204,7 +195,7 @@ CONFIG_SPI=y CONFIG_SPI_GPIO=y CONFIG_SPI_IMX=y CONFIG_SPI_OCORES=m -CONFIG_SPI_SPIDEV=m +CONFIG_SPI_SPIDEV=y CONFIG_PTP_1588_CLOCK=m CONFIG_GPIO_SYSFS=y CONFIG_GPIO_MXC=y @@ -215,7 +206,7 @@ CONFIG_POWER_RESET=y CONFIG_POWER_RESET_TS_SUPERVISOR=y CONFIG_POWER_RESET_SYSCON=y CONFIG_POWER_RESET_SYSCON_POWEROFF=y -# CONFIG_HWMON is not set +CONFIG_SENSORS_IIO_HWMON=y CONFIG_THERMAL=y CONFIG_THERMAL_STATISTICS=y CONFIG_THERMAL_WRITABLE_TRIPS=y @@ -239,15 +230,27 @@ CONFIG_DRM_MXSFB=y CONFIG_FB_MODE_HELPERS=y # CONFIG_FB_MX3 is not set CONFIG_FB_ST7565P=m -CONFIG_DRM_FBDEV_EMULATION=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_PLATFORM=y CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BACKLIGHT_PWM=y CONFIG_BACKLIGHT_GPIO=y +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_ITE is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_REDRAGON is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MONTEREY is not set # CONFIG_USB_HID is not set CONFIG_USB=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_OTG=y +CONFIG_USB_OTG_FSM=m CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_MXC=y CONFIG_USB_ACM=m @@ -270,6 +273,7 @@ CONFIG_LEDS_CLASS=y CONFIG_LEDS_GPIO=y CONFIG_LEDS_PWM=y CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y CONFIG_LEDS_TRIGGER_BACKLIGHT=y CONFIG_LEDS_TRIGGER_DEFAULT_ON=y CONFIG_RTC_CLASS=y @@ -277,6 +281,7 @@ CONFIG_RTC_CLASS=y CONFIG_RTC_INTF_DEV_UIE_EMUL=y CONFIG_RTC_DRV_DS1307=y CONFIG_RTC_DRV_TSSUPERVISOR=y +CONFIG_RTC_DRV_SNVS=y CONFIG_DMADEVICES=y CONFIG_IMX_SDMA=y # CONFIG_VIRTIO_MENU is not set @@ -341,11 +346,5 @@ CONFIG_XZ_DEC=y CONFIG_DMA_CMA=y CONFIG_CMA_SIZE_MBYTES=64 # CONFIG_SYMBOLIC_ERRNAME is not set -# CONFIG_DEBUG_BUGVERBOSE is not set # CONFIG_ENABLE_MUST_CHECK is not set -# CONFIG_DEBUG_MISC is not set -# CONFIG_SCHED_DEBUG is not set -# CONFIG_DEBUG_PREEMPT is not set -# CONFIG_RCU_TRACE is not set -# CONFIG_FTRACE is not set # CONFIG_RUNTIME_TESTING_MENU is not set From 5674955493207c348f3341ca33669c6f670f41a8 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Fri, 20 Oct 2023 13:36:45 -0700 Subject: [PATCH 124/244] ARM: configs: tsa38x_minimal: Add H4 HCI UART support Signed-off-by: Kris Bahnsen --- arch/arm/configs/tsa38x_minimal_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/tsa38x_minimal_defconfig b/arch/arm/configs/tsa38x_minimal_defconfig index 3145255a7eb7f..e88dc37399a3e 100644 --- a/arch/arm/configs/tsa38x_minimal_defconfig +++ b/arch/arm/configs/tsa38x_minimal_defconfig @@ -52,6 +52,7 @@ CONFIG_CAN_SJA1000_ISA=m CONFIG_CAN_SJA1000_PLATFORM=m CONFIG_BT=m CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_H4=y CONFIG_CFG80211=m # CONFIG_CFG80211_DEFAULT_PS is not set CONFIG_MAC80211=m From 7aa3aede06f2ea74b7db3c79737bcec8e92bb5ba Mon Sep 17 00:00:00 2001 From: Michael Peters Date: Tue, 14 Nov 2023 11:19:56 -0700 Subject: [PATCH 125/244] Add highmem to tsa38x_* defconfigs. --- arch/arm/configs/tsa38x_defconfig | 2 +- arch/arm/configs/tsa38x_minimal_defconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/configs/tsa38x_defconfig b/arch/arm/configs/tsa38x_defconfig index 5d29c5f02652e..562da50f092a6 100644 --- a/arch/arm/configs/tsa38x_defconfig +++ b/arch/arm/configs/tsa38x_defconfig @@ -34,6 +34,7 @@ CONFIG_MACH_ARMADA_38X=y CONFIG_ARM_THUMBEE=y CONFIG_SMP=y CONFIG_HZ_1000=y +CONFIG_HIGHMEM=y CONFIG_ARM_APPENDED_DTB=y CONFIG_ARM_ATAG_DTB_COMPAT=y CONFIG_EFI=y @@ -846,7 +847,6 @@ CONFIG_CRC7=m CONFIG_PRINTK_TIME=y CONFIG_DEBUG_FS=y # CONFIG_DEBUG_MISC is not set -# CONFIG_DEBUG_PREEMPT is not set CONFIG_STACKTRACE=y # CONFIG_FTRACE is not set CONFIG_DEBUG_USER=y diff --git a/arch/arm/configs/tsa38x_minimal_defconfig b/arch/arm/configs/tsa38x_minimal_defconfig index e88dc37399a3e..25cdd15c4f2a2 100644 --- a/arch/arm/configs/tsa38x_minimal_defconfig +++ b/arch/arm/configs/tsa38x_minimal_defconfig @@ -21,6 +21,7 @@ CONFIG_MACH_ARMADA_38X=y CONFIG_ARM_THUMBEE=y CONFIG_SMP=y CONFIG_HZ_1000=y +CONFIG_HIGHMEM=y CONFIG_ARM_APPENDED_DTB=y CONFIG_ARM_ATAG_DTB_COMPAT=y CONFIG_CPU_FREQ=y @@ -280,7 +281,6 @@ CONFIG_CRYPTO_DEV_MARVELL_CESA=y CONFIG_CRC_ITU_T=m CONFIG_CRC7=m # CONFIG_DEBUG_MISC is not set -# CONFIG_DEBUG_PREEMPT is not set # CONFIG_FTRACE is not set CONFIG_DEBUG_USER=y # CONFIG_RUNTIME_TESTING_MENU is not set From cf82fd0eec3c7ebec23a98c5baa540a0c37f8fad Mon Sep 17 00:00:00 2001 From: Michael Peters Date: Tue, 14 Nov 2023 12:12:11 -0700 Subject: [PATCH 126/244] Add HIGHMEM to all embeddedTS defconfigs. --- arch/arm/configs/tsimx28_defconfig | 1 + arch/arm/configs/tsimx28_minimal_defconfig | 1 + arch/arm/configs/tsimx6_defconfig | 1 + arch/arm/configs/tsimx6_minimal_defconfig | 1 + arch/arm/configs/tsimx6ul_defconfig | 1 + arch/arm/configs/tsimx6ul_minimal_defconfig | 1 + 6 files changed, 6 insertions(+) diff --git a/arch/arm/configs/tsimx28_defconfig b/arch/arm/configs/tsimx28_defconfig index 5d77a03d434e7..3bbff5ef2ad7d 100644 --- a/arch/arm/configs/tsimx28_defconfig +++ b/arch/arm/configs/tsimx28_defconfig @@ -32,6 +32,7 @@ CONFIG_SLAB=y CONFIG_ARCH_MXS=y CONFIG_HZ_1000=y CONFIG_AEABI=y +CONFIG_HIGHMEM=y CONFIG_EFI=y CONFIG_MODULES=y CONFIG_MODULE_FORCE_LOAD=y diff --git a/arch/arm/configs/tsimx28_minimal_defconfig b/arch/arm/configs/tsimx28_minimal_defconfig index 09cb02764fe02..e30d95b07f1d9 100644 --- a/arch/arm/configs/tsimx28_minimal_defconfig +++ b/arch/arm/configs/tsimx28_minimal_defconfig @@ -22,6 +22,7 @@ CONFIG_SLAB=y CONFIG_ARCH_MXS=y CONFIG_HZ_1000=y CONFIG_AEABI=y +CONFIG_HIGHMEM=y CONFIG_MODULES=y CONFIG_MODULE_FORCE_LOAD=y CONFIG_MODULE_UNLOAD=y diff --git a/arch/arm/configs/tsimx6_defconfig b/arch/arm/configs/tsimx6_defconfig index fc423db19acb9..6f2ca151eb285 100644 --- a/arch/arm/configs/tsimx6_defconfig +++ b/arch/arm/configs/tsimx6_defconfig @@ -35,6 +35,7 @@ CONFIG_HAVE_ARM_ARCH_TIMER=y CONFIG_HOTPLUG_CPU=y CONFIG_ARM_PSCI=y CONFIG_HZ_1000=y +CONFIG_HIGHMEM=y CONFIG_FORCE_MAX_ZONEORDER=14 CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" CONFIG_EFI=y diff --git a/arch/arm/configs/tsimx6_minimal_defconfig b/arch/arm/configs/tsimx6_minimal_defconfig index 0b4622fe3069d..df8e66c65f89d 100644 --- a/arch/arm/configs/tsimx6_minimal_defconfig +++ b/arch/arm/configs/tsimx6_minimal_defconfig @@ -21,6 +21,7 @@ CONFIG_HAVE_ARM_ARCH_TIMER=y CONFIG_HOTPLUG_CPU=y CONFIG_ARM_PSCI=y CONFIG_HZ_1000=y +CONFIG_HIGHMEM=y CONFIG_FORCE_MAX_ZONEORDER=14 CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" CONFIG_CPU_FREQ=y diff --git a/arch/arm/configs/tsimx6ul_defconfig b/arch/arm/configs/tsimx6ul_defconfig index 415b90b2804c8..6790454c2904e 100644 --- a/arch/arm/configs/tsimx6ul_defconfig +++ b/arch/arm/configs/tsimx6ul_defconfig @@ -33,6 +33,7 @@ CONFIG_ARM_ERRATA_775420=y CONFIG_HAVE_ARM_ARCH_TIMER=y CONFIG_ARM_PSCI=y CONFIG_HZ_1000=y +CONFIG_HIGHMEM=y CONFIG_FORCE_MAX_ZONEORDER=14 CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" CONFIG_EFI=y diff --git a/arch/arm/configs/tsimx6ul_minimal_defconfig b/arch/arm/configs/tsimx6ul_minimal_defconfig index 62876caaa17bf..2b7865b0b8d60 100644 --- a/arch/arm/configs/tsimx6ul_minimal_defconfig +++ b/arch/arm/configs/tsimx6ul_minimal_defconfig @@ -18,6 +18,7 @@ CONFIG_ARM_ERRATA_775420=y CONFIG_HAVE_ARM_ARCH_TIMER=y CONFIG_ARM_PSCI=y CONFIG_HZ_1000=y +CONFIG_HIGHMEM=y CONFIG_FORCE_MAX_ZONEORDER=14 CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" CONFIG_CPU_FREQ=y From 4fedb60327e54efe646e02b5c61d4883da778b33 Mon Sep 17 00:00:00 2001 From: "Lionel D. Hummel" Date: Tue, 14 Nov 2023 12:07:50 -0700 Subject: [PATCH 127/244] ts7100: dts: Fix the amount of padding in gpio-line-names Some of these went in with too much "padding", throwing off the corresponding string offsets. --- .../arm/boot/dts/nxp/imx/imx6ul-ts7100-3.dtsi | 2 +- .../arm/boot/dts/nxp/imx/imx6ul-ts7100-z.dtsi | 20 +++---------------- 2 files changed, 4 insertions(+), 18 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-3.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-3.dtsi index a5acbb1c78a33..0e02d8d207e34 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-3.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-3.dtsi @@ -45,7 +45,7 @@ gpio-line-names = "RS485_5_TXEN", "RTC_BATT_FAIL", "I2C_1_CLK", "I2C_1_DAT", "AN_CH0", "AN_CH1", "", "", - "", "AN_CH2", "RS485_2_TXEN", "", + "AN_CH2", "RS485_2_TXEN", "", "", "", "", "", "", "", "", "", "", "", "", "", "", diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-z.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-z.dtsi index da5ccd71fc607..bbc273ca11fd9 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-z.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-z.dtsi @@ -64,8 +64,6 @@ "", "", "", "", "", "", "", "", "", "", "", "", - "", "", "", "", - "", "", "", "", "", "", "", ""; }; @@ -75,11 +73,7 @@ "DIO_1_OUT", "DIO_2_OUT", "DIO_1_IN", "DIO_2_IN", "DIO_3_IN", "DIO_6", "DIG_IN_1", "DIG_IN_2", "DIG_IN_3", "EN_CL_1", "EN_CL_2", "EN_CL_3", - "", "", "EN_CL_4", "EN_HS_SW", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", ""; + "", "", "EN_CL_4", "EN_HS_SW"; }; /* gpiochip6; FPGA dio2: */ @@ -88,11 +82,7 @@ "EN_EMMC_3V3#", "EN_ADC1_12V", "EN_ADC2_12V", "EN_ADC3_12V", "EN_ADC4_12V", "EN_USB_HOST_5V", "PHY_RESET#", "WIFI_RESET#", "IO_RED_LED#", "IO_GREEN_LED#", "", "", - "EN_PROG_SILAB", "DIO_3_OUT", "EN_HSPWM", "EN_LSPWM", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", ""; + "EN_PROG_SILAB", "DIO_3_OUT", "EN_HSPWM", "EN_LSPWM"; }; /* gpiochip7; FPGA dio3: */ @@ -101,11 +91,7 @@ "CPU_TOUCH_IRQ#", "", "C6_PAD", "B8_PAD", "C9_PAD", "C8_PAD", "NIM_3V3#_4V", "DIO_16_PAD", "NIM_PWR_ON", "SEL_NIM_USB", "DIO_FAULT#", "", - "", "", "EN_BK_LT#", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", ""; + "", "", "EN_BK_LT#", ""; }; &iomuxc { From 4670027475211e802cd4965117e69f08d8874726 Mon Sep 17 00:00:00 2001 From: "Lionel D. Hummel" Date: Fri, 17 Nov 2023 15:37:20 -0700 Subject: [PATCH 128/244] ts7100: dts: GPIO controller alias corrections These worked in 4.9. Not sure what changed, other than based on the "ground truth" of arch/arm/boot/dts/nxp/imx/imx6ul.dtsi, several of these were never correct. It must have been luck that CPU GPIO5 was being assigned to gpiochip4 despite being associated with `&gpio3` instead of `&gpio5`. It could have been that GPIO was always using the documented chip/pin numbers directly rather than using any kind of look-up. Likewise, the FPGA aliases need to start after the CPU aliases (i.e., start with '&gpio6'). As it had been from the start, both the CPU and the FPGA mistakenly used the '&gpio4' and '&gpio5' aliases. --- .../arm/boot/dts/nxp/imx/imx6ul-ts7100-3.dtsi | 1 + .../arm/boot/dts/nxp/imx/imx6ul-ts7100-z.dtsi | 29 ++++++++++++++----- 2 files changed, 22 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-3.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-3.dtsi index 0e02d8d207e34..d8ae6bc173b73 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-3.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-3.dtsi @@ -41,6 +41,7 @@ }; }; +/* CPU GPIO1: 209c000.gpio */ &gpio1 { gpio-line-names = "RS485_5_TXEN", "RTC_BATT_FAIL", "I2C_1_CLK", "I2C_1_DAT", diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-z.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-z.dtsi index bbc273ca11fd9..88dcbfa0cc26e 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-z.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-z.dtsi @@ -41,7 +41,7 @@ }; }; -/* gpiochip0; CPU GPIO1: */ +/* CPU GPIO1: 209c000.gpio */ &gpio1 { gpio-line-names = "AN_CH4", "RTC_BATT_FAIL", "I2C_1_CLK", "I2C_1_DAT", @@ -54,8 +54,21 @@ "", "", "", ""; }; -/* gpiochip4; CPU GPIO2: */ +/* CPU GPIO3: 20a4000.gpio */ &gpio3 { + gpio-line-names = + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "NIM_STATUS", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +/* CPU GPIO5: 20ac000.gpio */ +&gpio5 { gpio-line-names = "POWER_FAIL_3V", "FPGA_IRQ", "", "", "EN_RELAY_1", "EN_RELAY_2", "", "", @@ -67,8 +80,8 @@ "", "", "", ""; }; -/* gpiochip5; FPGA dio: */ -&gpio4 { +/* FPGA dio: 50004010.gpio */ +&gpio6 { gpio-line-names = "DIO_1_OUT", "DIO_2_OUT", "DIO_1_IN", "DIO_2_IN", "DIO_3_IN", "DIO_6", "DIG_IN_1", "DIG_IN_2", @@ -76,8 +89,8 @@ "", "", "EN_CL_4", "EN_HS_SW"; }; -/* gpiochip6; FPGA dio2: */ -&gpio5 { +/* FPGA dio2: 50004040.gpio */ +&gpio7 { gpio-line-names = "EN_EMMC_3V3#", "EN_ADC1_12V", "EN_ADC2_12V", "EN_ADC3_12V", "EN_ADC4_12V", "EN_USB_HOST_5V", "PHY_RESET#", "WIFI_RESET#", @@ -85,8 +98,8 @@ "EN_PROG_SILAB", "DIO_3_OUT", "EN_HSPWM", "EN_LSPWM"; }; -/* gpiochip7; FPGA dio3: */ -&gpio6 { +/* FPGA dio3: 50004050.gpio */ +&gpio8 { gpio-line-names = "CPU_TOUCH_IRQ#", "", "C6_PAD", "B8_PAD", "C9_PAD", "C8_PAD", "NIM_3V3#_4V", "DIO_16_PAD", From f4325880cd0025cd3f8774c118a6a91927ea8bab Mon Sep 17 00:00:00 2001 From: "Lionel D. Hummel" Date: Fri, 17 Nov 2023 15:40:03 -0700 Subject: [PATCH 129/244] ts7100: dts: Add new GPIOs present on Rev B: NIM_STATUS & NIM_RESET - Added NIM_STATUS and NIM_RESET gpio-line-names - Re-arranged the hoggrp in order of GPIO chip/line, because that is the order they are reflected in the pinmux registers. - Changed the NIM_STATUS iomux value from pull-up to pull down; necessary to detect when the modem drops the line (i.e., due to power-off or going to sleep) --- arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-3.dtsi | 10 +++++----- arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-z.dtsi | 13 +++++++------ 2 files changed, 12 insertions(+), 11 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-3.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-3.dtsi index d8ae6bc173b73..b968d84bf4407 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-3.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-3.dtsi @@ -71,21 +71,21 @@ /* REV B Strap */ MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x1b020 + /* NIM_STATUS - set to drop when modem is no longer driving it high */ + MX6UL_PAD_LCD_DATA09__GPIO3_IO14 0x13020 + + /* POWER_FAIL */ + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b020 /* EN_RELAY 1 */ MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1a020 /* EN_RELAY 2 */ MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1a020 /* NIM_RESET */ MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b020 - /* NIM Status */ - MX6UL_PAD_LCD_DATA09__GPIO3_IO14 0x1b020 /* FPGA Spares */ MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b020 MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x1b020 MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b020 - - /* POWER_FAIL */ - MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b020 >; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-z.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-z.dtsi index 88dcbfa0cc26e..b2f5f730e5d0c 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-z.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-z.dtsi @@ -71,7 +71,7 @@ &gpio5 { gpio-line-names = "POWER_FAIL_3V", "FPGA_IRQ", "", "", - "EN_RELAY_1", "EN_RELAY_2", "", "", + "EN_RELAY_1", "EN_RELAY_2", "NIM_RESET", "", "", "", "", "", "", "", "", "", "", "", "", "", @@ -120,24 +120,25 @@ * 0x1a020 == no pull resistor * 0x13020 == 100k PD */ + /* REV B Strap */ MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x1b020 + /* NIM_STATUS - set to drop when modem is no longer driving it high */ + MX6UL_PAD_LCD_DATA09__GPIO3_IO14 0x13020 + + /* POWER_FAIL */ + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b020 /* EN_RELAY 1 */ MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1a020 /* EN_RELAY 2 */ MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1a020 /* NIM_RESET */ MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b020 - /* NIM Status */ - MX6UL_PAD_LCD_DATA09__GPIO3_IO14 0x1b020 /* FPGA Spares */ MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b020 MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x1b020 MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b020 - - /* POWER_FAIL */ - MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b020 >; }; From 2440cb3a78b5e027d0eacca58a0a211066f84e71 Mon Sep 17 00:00:00 2001 From: "Lionel D. Hummel" Date: Mon, 20 Nov 2023 17:35:27 -0700 Subject: [PATCH 130/244] ts7100: dts: Try to keep gpio-line-names common across IO models --- .../arm/boot/dts/nxp/imx/imx6ul-ts7100-3.dtsi | 53 +++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-3.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-3.dtsi index b968d84bf4407..84053b3370a22 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-3.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-3.dtsi @@ -54,6 +54,59 @@ "", "", "", ""; }; +/* CPU GPIO3: 20a4000.gpio */ +&gpio3 { + gpio-line-names = + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "NIM_STATUS", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +/* CPU GPIO5: 20ac000.gpio */ +&gpio5 { + gpio-line-names = + "POWER_FAIL_3V", "FPGA_IRQ", "", "", + "EN_RELAY_1", "EN_RELAY_2", "NIM_RESET", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +/* FPGA dio: 50004010.gpio */ +&gpio6 { + gpio-line-names = + "DIO_1_OUT", "DIO_2_OUT", "DIO_1_IN", "DIO_2_IN", + "DIO_3_IN", "DIO_6", "DIG_IN_1", "DIG_IN_2", + "DIG_IN_3", "EN_CL_1", "EN_CL_2", "EN_CL_3", + "", "", "EN_CL_4", "EN_HS_SW"; +}; + +/* FPGA dio2: 50004040.gpio */ +&gpio7 { + gpio-line-names = + "EN_EMMC_3V3#", "EN_ADC1_12V", "EN_ADC2_12V", "EN_ADC3_12V", + "EN_ADC4_12V", "EN_USB_HOST_5V", "PHY_RESET#", "WIFI_RESET#", + "IO_RED_LED#", "IO_GREEN_LED#", "", "", + "EN_PROG_SILAB", "DIO_3_OUT", "EN_HSPWM", "EN_LSPWM"; +}; + +/* FPGA dio3: 50004050.gpio */ +&gpio8 { + gpio-line-names = + "CPU_TOUCH_IRQ#", "", "C6_PAD", "B8_PAD", + "C9_PAD", "C8_PAD", "NIM_3V3#_4V", "DIO_16_PAD", + "NIM_PWR_ON", "SEL_NIM_USB", "DIO_FAULT#", "", + "", "", "EN_BK_LT#", ""; +}; + &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&ts7100_3_pinctrl_hog>; From f542e4f4adb5d9361d4bd7106374648925c141a2 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Tue, 12 Dec 2023 17:15:01 -0700 Subject: [PATCH 131/244] ARM: dts: ts7400v2: Remove mmc aliases There is a long history as to why the aliases were there, they worked on the stock kernel for the TS-7400-V2, did not work in 4.9, and again work in 5.10. The issue is that the U-Boot binary expects the eMMC to be at mmcblk1. This U-Boot was created specifically for the 4.9 kernel. In 5.10 where the alias was honored, it was showing up at mmcblk2 and resulting in a hang waiting for a non-existant device node. Signed-off-by: Kris Bahnsen --- arch/arm/boot/dts/nxp/mxs/imx28-ts7400v2.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-ts7400v2.dts b/arch/arm/boot/dts/nxp/mxs/imx28-ts7400v2.dts index 732d2e7542eec..9c56ca93c4363 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-ts7400v2.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-ts7400v2.dts @@ -14,8 +14,6 @@ compatible = "fsl,imx28-ts7400v2", "fsl,imx28"; aliases { - mmc0 = &ssp0; - mmc2 = &ssp1; spi0 = &ssp2; i2c0 = &i2c0; }; From 94bac53ab8f7bacd5b3b71b908ba56a3d7f7328e Mon Sep 17 00:00:00 2001 From: "Lionel D. Hummel" Date: Tue, 9 Jan 2024 17:18:44 -0700 Subject: [PATCH 132/244] ARM: dts: ts7100: LCD panel clock-frequency is 7 MHz (units: Hz) --- arch/arm/boot/dts/nxp/imx/imx6ul-ts7100.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100.dtsi index b198b1f029824..cafc01e31426e 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100.dtsi @@ -68,7 +68,7 @@ label = "st7789v"; compatible = "panel-dpi"; panel-timing { - clock-frequency = <7000>; + clock-frequency = <7000000>; hactive = <240>; vactive = <320>; hfront-porch = <38>; From fa91d38341cae1b15a70ac93915d1e34e3ff7218 Mon Sep 17 00:00:00 2001 From: randytsi369 Date: Fri, 21 Aug 2020 13:41:47 -0700 Subject: [PATCH 133/244] ARM: dtb: ts7180: Initial commit for port to linux-lts kernel repo Supports Rev C PCBs and later. Summary roll-up of commits previously in the embeddedts/linux-4.9.y tree plus commits added during the port to 5.10: * SHIP? ARM: dts: ts7180: Add vdd-supply to gyro/accel and magn * pull vdd-supply that SUPPOSEDLY should not be needed for gyro/magn to configure * ARM: dts: ts7180: Use rts-gpios not uart-tx-enable-gpios; omit fsl (for UARTs) The 4.1 kernel didn't have txen support, so we added it using the old gpios string. To pick it up now in 4.9, we need rts-gpios intead. * ARM: dts: ts7180: fix GPIO name EN_AUX_PWR to EN_CELL_MODEM_PWR To match the schematic. * ARM: dtb: ts7180: Add Silabs C2 pin iomux definitions * ARM: dtb: ts7180: Added PPS GPIO connected to the GPS PPS output. This requires FPGA revision 15 or greater. * ARM: dts: TS: Update FDTs for new WILC driver * ARM: dts: ts7180: Corrected node for bit-banged I2C - Should be GPIO_ACTIVE_HIGH (high is 1 on i2c), not GPIO_ACTIVE_LOW. With I2C, 0 is *driven* low, but writing a 0 bit still outputs 0. So it is active high. - sda-open-drain and scl-open-drain must not be set, even when open-drain is enabled on the GPIO. - Disable un-needed internal pull-ups for HD12 I2C * ARM: dts: ts7180: Rename HD1 signals split out onto HD12 as of Rev C * ARM: dts: ts7180: renames to embeddedTS * ARM: dts: ts7180: Disable line driver for GPIO3_IO18 (PUSH_SW_CPU#) For some reason, this change enables the push switch to work, even though it continues to work if the line driver enabled after boot. * ARM: dts: ts7180: Add ts7100-wdt (watchdog) on i2c1 This is always needed, because otherwise a timeout set in U-Boot will not be cancelled and the board will reboot. The entry's comment includes a breadcrumb to explain why the timeout that is read back from hardware is likely to differ from whatever is set here: Userspace procs can still start feeding with different values later - watchdog(8) defaults to 60 seconds. The CPU's builtin watchdog (wdog1) has a trace enabling it to assert RST# (analogous to EXT_RESET#/PWR_CYCLE# on the C99). We disable the watchdog, but leave the pinmux settings in place. wdog1 should be disabled, because otherwise both it and the ts7100-wdt will have a 60-second timeout, making it possibly random which reset circuitry will fire first. Don't enable wdog1 unless ts7100-wdt is disabled or is given a different timeout. * ARM: dts: ts7180: rearrange DTS for easier diff w/7250v3 &cpu0 and &gpc are two interesting ones in the 7180 tree that aren't in the 7250v3. Neither is in particularly alphabetical order. The remaining i2c entries aren't even adjacent to &i2c1. * ARM: ts7180: dts: Move the regulators out of their sub-level * dts: rename leds to led-controller nodes * ARM: dts: ts7180: follow the convention of aliases at head of dtsi else dts * ARM: dts: ts7180: update copyright before shipping * ARM: dts: ts7180: reserved-memory does not belong in DTS and can break CMA w/7250v3 config * memory@80000000 and device_type=memory to match other TS boards * ARM: dts: ts7180: pxp_v4l2 does not belong anymore * ARM: dts: ts7180: ethernet needs a fixed- rather than dummy-regulator The regulator made the difference for ethernet * ARM: dts: ts7180: get st_magn with compat string of lis2mdl, not lis2mdl_magn * ARM: dts: ts7180: The ism330dlc now handled by the lsm6dsx gyro/accel driver * ARM: dts: ts7180: The lis2mdl_magn is (now) handled by the st_magn driver - the ISM330 driver initializes the chips as level-high, not edge-triggered - fix typo inherited from 7250v3 * ARM: dts: ts7180: use ts7100-wdt rather than ts-wdt * The great alphabeticalization * columnize gpio6 (on the FPGA) * columnize gpio1 through gpio5, all on the 6ul * remove dvfs (not used outside NXP's kernel) * remove delay-us for i2c-gpio * use fsl,num-cs rather than spi-num-chipselects * By default, use the CPU watchdog rather than the SMC watchdog * ARM: dts: ts7180: FRAM SPI CLK 20 -> 1 MHz b/c it is shared offboard * ARM: dts: ts7180: uart-has-rtscts should never have been on UART with GPIO flow control --- arch/arm/boot/dts/nxp/imx/Makefile | 1 + arch/arm/boot/dts/nxp/imx/imx6ul-ts7180.dts | 784 ++++++++++++++++++++ 2 files changed, 785 insertions(+) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-ts7180.dts diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx/Makefile index 448654114216d..c499ce6a55731 100644 --- a/arch/arm/boot/dts/nxp/imx/Makefile +++ b/arch/arm/boot/dts/nxp/imx/Makefile @@ -360,6 +360,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ul-ts7553v2.dtb \ imx6ul-ts7100-1.dtb \ imx6ul-ts7100-3.dtb \ + imx6ul-ts7180.dtb \ imx6ul-tx6ul-0010.dtb \ imx6ul-tx6ul-0011.dtb \ imx6ul-tx6ul-mainboard.dtb \ diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7180.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7180.dts new file mode 100644 index 0000000000000..c1675bb83c36a --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7180.dts @@ -0,0 +1,784 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (C) 2021-2023 Technologic Systems, Inc. dba embeddedTS + */ + +/dts-v1/; +#include +#include +#include "imx6ul.dtsi" + +/ { + model = "embeddedTS i.MX6UL TS-7180"; + compatible = "technologic,ts7180", "fsl,imx6ul"; + + aliases { + ethernet0 = &fec2; + ethernet1 = &fec1; + }; + + chosen { + stdout-path = &uart1; + }; + + memory@80000000 { + device_type = "memory"; + /* Memory size is to be filled in by U-Boot */ + reg = <0x80000000 0>; + }; + + led-controller { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + compatible = "gpio-leds"; + + led-2 { + color = ; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpio4 23 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-3 { + color = ; + function = LED_FUNCTION_POWER; + gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + led-4 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-6 { + color = ; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + reg_adc_vref: adc_vref { + compatible = "regulator-fixed"; + regulator-name = "ADC_VREF"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_flexcan_3v3: en-can { + compatible = "regulator-fixed"; + regulator-name = "CAN_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio6 20 GPIO_ACTIVE_HIGH>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + i2c_gpio: i2c { + compatible = "i2c-gpio"; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_gpio>; + scl-gpios = <&gpio3 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* I2C_CLK on HD12 pin 6 */ + sda-gpios = <&gpio3 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* I2C_DAT on HD12 pin 1 */ + #address-cells = <1>; + #size-cells = <0>; + }; + + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ppsgpio>; + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + }; +}; + +&adc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc>; + vref-supply = <®_adc_vref>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_flexcan_3v3>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_flexcan_3v3>; + status = "okay"; +}; + +&ecspi3 { + fsl,num-cs = <3>; + cs-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>, <&gpio3 0 GPIO_ACTIVE_LOW>, <&gpio4 27 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + status = "okay"; + + spidevfpga: spi@0 { + compatible = "technologic,spi-header"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + + spioffbd: spi@1 { + compatible = "technologic,spi-header"; + reg = <1>; + spi-cs-high; + spi-max-frequency = <1000000>; + }; + + /* This is actually the FRAM, which is compatible with the AT25 SPI EEPROM */ + fm25l16b: eeprom@2 { + compatible = "atmel,at25"; + reg = <2>; + spi-max-frequency = <1000000>; + size = <0x800>; + address-width = <16>; + pagesize = <64>; + }; +}; + +&ecspi4 { + fsl,num-cs = <1>; + cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4>; + status = "okay"; + + wilc3000: wifi@0 { + compatible = "microchip,wilc3000"; + reg = <0>; + spi-max-frequency = <48000000>; + reset-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; + chip_en-gpios = <&gpio6 1 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio5>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + phy-supply = <®_3v3>; + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + phy-supply = <®_3v3>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@2 { + clocks = <&clks IMX6UL_CLK_ENET_REF>; + clock-names = "rmii-ref"; + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + }; + + ethphy1: ethernet-phy@1 { + clocks = <&clks IMX6UL_CLK_ENET_REF>; + clock-names = "rmii-ref"; + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&gpio1 { + gpio-line-names = + "BOOT_MODE_0", "", "I2C_1_CLK", "I2C_1_DAT", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "SPARE_1", "EN_485", + "", "", "", "", + "", "", "UART3_CTS#", "UART3_RTS#", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + "HD12_SPI_CS", "JTAG_FPGA_TCK", "JTAG_FPGA_TMS", "JTAG_FPGA_TDI", + "WDOG#", "I2C_3_DAT", "I2C_3_CLK", "", + "HD12_I2C_CLK", "HD12_I2C_DAT", "HD12_DIG_INPUT", "NO_CHRG_JMP#", + "EN_NIM_USB#", "", "", "XBEE_CTS#", + "U_BOOT_JMP#", "", "PUSH_SW_CPU#", "NIMBEL_PWR_ON", + "", "", "", "ID4", + "JTAG_FPGA_TDO", "", "", "ID1", + "ETH_PHY_RESET#", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", + "", "", "SPI_4_CLK", "SPI_4_MOSI", + "SPI_4_MISO", "SPI_4_CS#", "MAG_N_IRQ", "FPGA_RESET#", + "SPI_3_FPGA_CS#", "SPI_3_CLK", "SPI_3_MOSI", "SPI_3_MISO", + "PWM_5", "", "", "ID5", + "GYRO_INT", "6UL_FORCE_5V_ON", "EN_EMMC_3.3V#", "EN_YEL_LED#", + "EN_RED_LED#", "EN_GRN_LED#", "EN_BLU_LED", "FRAM_SPI_CS#", + "SD_VSEL_1.8V", "", "", ""; +}; + +&gpio5 { + gpio-line-names = + "POWER_FAIL", "GPS_PPS_OUT", "", "GPIO_DVFS", + "", "SILAB_C2_CLK", "SILAB_C2_DATA", "SILAB_C2_RESET", + "SPARE_4", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + /* + * Reference: Documentation/devicetree/bindings/iio/st-sensors.txt + * + * - MAG_N_IRQ enters NAND_ALE/SD2_RST#/PWM3 pad B4 + * - as well as the FPGA + */ + st_magn: magnetometer@1e { + compatible = "st,lis2mdl"; + reg = <0x1e>; + st,drdy-int-pin = <1>; + interrupt-parent = <&gpio4>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; /* See MX6UL_PAD_NAND_ALE__GPIO4_IO10 */ + }; + + supervisor: wdt@54 { + compatible = "technologic,ts7100-wdt"; + enable-early; + /* 5min timeout default, in case of slow userspace. + * Set to 0 to disable WDT at startup. Userspace procs + * can still start feeding with different values later - + * watchdog(8) defaults to 60 seconds. + */ + timeout-sec = <300>; + reg = <0x54>; + + /* + * Not using uC WDT by default any longer. If you need features + * provided by this, such as a real poweroff state, an external + * WDT, or proper feedback from the uC on the platform's reboot + * source (via tsmicroctl), then enable this driver (and disable + * the CPU driver, wdog1, unless you want both active). + */ + + status = "disabled"; + }; + + m41t00s: rtc@68 { + compatible = "st,m41t00"; + reg = <0x68>; + }; + + /* + * Reference: Documentation/devicetree/bindings/iio/imu/st_lsm6dsx.txt + * + * - GYRO_INT enters CSI_HSYNC (pad F3) + */ + ism330: gyro@6a { + compatible = "st,ism330dlc"; + reg = <0x6a>; + interrupt-parent = <&gpio4>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; /* See MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 */ + }; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + status = "okay"; + scl-gpios = <&gpio3 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio3 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + gpio6: gpio@28 { + compatible = "technologic,ts4900-gpio"; + reg = <0x28>; + #gpio-cells = <2>; + gpio-controller; + base = <160>; + ngpios = <64>; + gpio-line-names = + "WIFI_RESET#", "EN_WIFI_PWR", "", "", + "", "FRAM_WP#", "EN_CL_1", "EN_CL_2", + "EN_CL_3", "EN_CL_4", "EN_ADC1_10V", "EN_ADC2_10V", + "EN_ADC3_10V", "EN_ADC4_10V", "EN_SD_POWER", "EN_USB_HOST_5V", + "EN_OFF_BD_5V", "EN_CELL_MODEM_PWR", "EN_NIMBEL_3.3V", "EN_GPS_PWR#", + "EN_CAN_XVR#", "EN_232_XVR", "EN_LS_OUT_1", "EN_LS_OUT_2", + "EN_LS_OUT_3", "EN_LS_OUT_4", "EN_LS_OUT_5", "EN_LS_OUT_6", + "EN_LS_OUT_7", "MT_RESET#", "", "", + "DIG_IN_1", "DIG_IN_2", "DIG_IN_3", "DIG_IN_4", + "SD_BOOT_JMP#", "DIO_1_IN", "DIO_2_IN", "DIO_3_IN", + "DIO_4_IN", "DIO_5_IN", "DIO_6_IN", "DIO_7_IN", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + imx6ul-ts7180 { + pinctrl_gpio_leds: leds1grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x1b020 /* EN_YEL_LED# */ + MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x1b020 /* EN_RED_LED# */ + MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x1b020 /* EN_GREEN_LED# */ + MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x1b020 /* EN_BLUE_LED */ + >; + }; + + /* Pins that are always GPIO */ + pinctrl_hog: hoggrp { + fsl,pins = < + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x1b020 /* SPARE_1 */ + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x10020 /* POWER_FAIL */ + MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x10020 /* SILAB_C2_CLK */ + MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x10020 /* SILAB_C2_DAT */ + MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x10020 /* SILAB_C2_RESET */ + MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b020 /* EN_FPGA_PWR on REV C and below */ + MX6UL_PAD_LCD_DATA05__GPIO3_IO10 0x10020 /* HD12_DIG_INPUT */ + MX6UL_PAD_LCD_DATA06__GPIO3_IO11 0x10020 /* NO_CHRG_JMP# */ + MX6UL_PAD_LCD_DATA07__GPIO3_IO12 0x10020 /* EN_NIM_USB# */ + MX6UL_PAD_LCD_DATA11__GPIO3_IO16 0x10020 /* U_BOOT_JMP# */ + MX6UL_PAD_LCD_DATA13__GPIO3_IO18 0x10000 /* PUSH_SW_CPU# */ + MX6UL_PAD_LCD_DATA14__GPIO3_IO19 0x1b020 /* NIMBEL_PWR_ON */ + MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x1b020 /* ID4 */ + MX6UL_PAD_LCD_DATA22__GPIO3_IO27 0x1b020 /* ID1 */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x03020 /* MAG_N_IRQ */ + MX6UL_PAD_NAND_WP_B__GPIO4_IO11 0x1b020 /* FPGA_RESET# */ + MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x1b020 /* JTAG_FPGA_TDO */ + MX6UL_PAD_LCD_VSYNC__GPIO3_IO03 0x1b020 /* JTAG_FPGA_TDI */ + MX6UL_PAD_LCD_HSYNC__GPIO3_IO02 0x1b020 /* JTAG_FPGA_TMS */ + MX6UL_PAD_LCD_ENABLE__GPIO3_IO01 0x1b020 /* JTAG_FPGA_TCK */ + MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x10020 /* 6UL_FORCE_5V_ON */ + /* EN_YEL_LED# in pinctrl_gpio_leds */ + /* EN_RED_LED# in pinctrl_gpio_leds */ + /* EN_GREEN_LED# in pinctrl_gpio_leds */ + /* EN_BLUE_LED in pinctrl_gpio_leds */ + MX6UL_PAD_LCD_DATA06__GPIO3_IO11 0x1b020 /* NO_CHRG_JMP# */ + MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x1b020 /* ID5 */ + MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x03020 /* GYRO_INT */ + >; + }; + + pinctrl_ppsgpio: ppsgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x1a020 + >; + }; + + pinctrl_pwm5: ts7180pwm5 { + fsl,pins = < + MX6UL_PAD_NAND_DQS__PWM5_OUT 0x13020 /* SPARE_3 */ + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_flexcan1: flexcan1grp{ + fsl,pins = < + MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX 0x1b020 + MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX 0x1b020 + >; + }; + + pinctrl_flexcan2: flexcan2grp{ + fsl,pins = < + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 + MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 + MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1 + MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1 + MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x13020 /* SPARE_2 EN_485 */ + + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1 + MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1 + >; + }; + + pinctrl_uart6: uart6grp { + fsl,pins = < + MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x1b0b1 + MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x1b0b1 + >; + }; + + pinctrl_uart7: uart7grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA17__UART7_DCE_RX 0x1b0b1 + MX6UL_PAD_LCD_DATA16__UART7_DCE_TX 0x1b0b1 + >; + }; + + pinctrl_uart8: uart8grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA21__UART8_DCE_RX 0x1b0b1 /* RXD_GPS */ + MX6UL_PAD_LCD_DATA20__UART8_DCE_TX 0x1b0b1 /* TXD_GPS */ + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_LCD_DATA23__GPIO3_IO28 0x1a020 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c1_gpio: i2c1grpgpio { + fsl,pins = < + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x4001b8b0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x4001b8b0 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA01__I2C3_SCL 0x4001b8b0 + MX6UL_PAD_LCD_DATA00__I2C3_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c3_gpio: i2c3grpgpio { + fsl,pins = < + MX6UL_PAD_LCD_DATA01__GPIO3_IO06 0x4001b8b0 + MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x4001b8b0 + >; + }; + + pinctrl_i2c_gpio: i2cgrpgpio { + fsl,pins = < + MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0x000108b0 /* HD12_I2C_CLK */ + MX6UL_PAD_LCD_DATA04__GPIO3_IO09 0x000108b0 /* HD12_I2C_DAT */ + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + + MX6UL_PAD_CSI_DATA07__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 + >; + }; + + pinctrl_adc: adcgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x1b020 /* ADC_1 */ + MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x1b020 /* ADC_2 */ + MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x1b020 /* ADC_3 */ + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x1b020 /* ADC_4 */ + + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + /* EN_EMMC */ + MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x1b020 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6UL_PAD_NAND_READY_B__GPIO4_IO12 0x10b0 // SPI_3_FPGA_CS# + MX6UL_PAD_NAND_CE0_B__ECSPI3_SCLK 0x10b0 // SPI_3_CLK + MX6UL_PAD_NAND_CE1_B__ECSPI3_MOSI 0x10b0 // SPI_3_MOSI + MX6UL_PAD_NAND_CLE__ECSPI3_MISO 0x10b0 // SPI_3_MISO + MX6UL_PAD_LCD_CLK__GPIO3_IO00 0x10b0 // HD12_SPI_CS (active high) + MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x10b0 // FRAM_SPI_CS# + >; + }; + + pinctrl_ecspi4: ecspi4grp { + fsl,pins = < + MX6UL_PAD_NAND_DATA04__ECSPI4_SCLK 0x10b0 + MX6UL_PAD_NAND_DATA05__ECSPI4_MOSI 0x10b0 + MX6UL_PAD_NAND_DATA06__ECSPI4_MISO 0x10b0 + MX6UL_PAD_NAND_DATA07__GPIO4_IO09 0x10b0 // WIFI chip select + MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x1b020 // SPARE_4/WIFI_IRQ + >; + }; + + pinctrl_dvfs: dvfsgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79 + >; + }; + }; +}; + +&pwm5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm5>; + status = "okay"; +}; + +&snvs_rtc { + status = "disabled"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; + uart-has-rtscts; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; + rts-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>; + linux,rs485-enabled-at-boot-time; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart7>; + status = "okay"; +}; + +&uart8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart8>; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + max-frequency = <208000000>; + keep-power-in-suspend; + enable-sdio-wakeup; + disable-wp; + cap-sd-highspeed; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + sd-uhs-ddr50; + broken-cd = <1>; + bus-width = <4>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + no-1-8-v; + disable-wp; + broken-cd = <1>; + enable-sdio-wakeup; + bus-width = <4>; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + status = "okay"; + fsl,ext-reset-output; +}; From fcd909e9c490ec3b25e2824bad7b5f62e8c91a4e Mon Sep 17 00:00:00 2001 From: "Lionel D. Hummel" Date: Sun, 24 Sep 2023 16:56:17 -0700 Subject: [PATCH 134/244] ARM: configs: tsimx6ul: Add CONFIG_PPS=m for models with GPS/PPS --- arch/arm/configs/tsimx6ul_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/configs/tsimx6ul_defconfig b/arch/arm/configs/tsimx6ul_defconfig index 6790454c2904e..ee2d2643c4f0f 100644 --- a/arch/arm/configs/tsimx6ul_defconfig +++ b/arch/arm/configs/tsimx6ul_defconfig @@ -676,6 +676,9 @@ CONFIG_SPI_GPIO=y CONFIG_SPI_IMX=y CONFIG_SPI_OCORES=m CONFIG_SPI_SPIDEV=y +CONFIG_PPS=m +CONFIG_PPS_CLIENT_LDISC=m +CONFIG_PPS_CLIENT_GPIO=m CONFIG_PTP_1588_CLOCK=m CONFIG_GPIO_SYSFS=y CONFIG_GPIO_MXC=y From 17d95db2651980a1fa832799c912acd9cd9f4fde Mon Sep 17 00:00:00 2001 From: "Lionel D. Hummel" Date: Sun, 24 Sep 2023 16:56:29 -0700 Subject: [PATCH 135/244] ARM: configs: tsimx6ul_minimal: GPS/PPS models need CONFIG_PPS=m --- arch/arm/configs/tsimx6ul_minimal_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/configs/tsimx6ul_minimal_defconfig b/arch/arm/configs/tsimx6ul_minimal_defconfig index 2b7865b0b8d60..8af602b6f622f 100644 --- a/arch/arm/configs/tsimx6ul_minimal_defconfig +++ b/arch/arm/configs/tsimx6ul_minimal_defconfig @@ -197,6 +197,9 @@ CONFIG_SPI_GPIO=y CONFIG_SPI_IMX=y CONFIG_SPI_OCORES=m CONFIG_SPI_SPIDEV=y +CONFIG_PPS=m +CONFIG_PPS_CLIENT_LDISC=m +CONFIG_PPS_CLIENT_GPIO=m CONFIG_PTP_1588_CLOCK=m CONFIG_GPIO_SYSFS=y CONFIG_GPIO_MXC=y From 98dad76332a0f8c489f8ec0205c05fa9f10adfaf Mon Sep 17 00:00:00 2001 From: "Lionel D. Hummel" Date: Tue, 3 Oct 2023 15:50:51 -0700 Subject: [PATCH 136/244] ARM: dts: ts7180: cleanup style post-debug/pre-alphabeticalization - Remove comment: /* EN_485 is the TX enable signal */ - Co-authored-by: Kris Bahnsen - turn off DMA for rs-485 (uart4) - usdhc1 as tested plus cleanup - usdhc2 cleanup - pinctrl node names should end in "grp" - num-cs for ecspi[34] do not need fsl - gpio2 is unused (remove node with all-empty gpio-line-names) - Preferred name for ts4900-gpio (i2c) is gpio-controller@28, not gpio@28 - Identify gpio controllers asssociated with gpio-line-names (faster than looking up) - Remove trailing whitespace from all gpio-line-names sections - For the i2c gpio controller, specifying "base" is no longer needed nor allowed - For off-board SPI, remove spi-cs-high because it is not (and breaks in 5.10) - Number leds from 0 rather than following reference designators --- arch/arm/boot/dts/nxp/imx/imx6ul-ts7180.dts | 88 ++++++++------------- 1 file changed, 35 insertions(+), 53 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7180.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7180.dts index c1675bb83c36a..3e233c44ef443 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7180.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7180.dts @@ -32,28 +32,28 @@ pinctrl-0 = <&pinctrl_gpio_leds>; compatible = "gpio-leds"; - led-2 { + led-0 { color = ; function = LED_FUNCTION_INDICATOR; gpios = <&gpio4 23 GPIO_ACTIVE_LOW>; default-state = "off"; }; - led-3 { + led-1 { color = ; function = LED_FUNCTION_POWER; gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; default-state = "on"; }; - led-4 { + led-2 { color = ; function = LED_FUNCTION_STATUS; gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; default-state = "off"; }; - led-6 { + led-3 { color = ; function = LED_FUNCTION_INDICATOR; gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; @@ -126,7 +126,7 @@ }; &ecspi3 { - fsl,num-cs = <3>; + num-cs = <3>; cs-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>, <&gpio3 0 GPIO_ACTIVE_LOW>, <&gpio4 27 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi3>; @@ -141,7 +141,6 @@ spioffbd: spi@1 { compatible = "technologic,spi-header"; reg = <1>; - spi-cs-high; spi-max-frequency = <1000000>; }; @@ -157,7 +156,7 @@ }; &ecspi4 { - fsl,num-cs = <1>; + num-cs = <1>; cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi4>; @@ -211,6 +210,7 @@ }; }; +/* CPU GPIO1: 209c000.gpio */ &gpio1 { gpio-line-names = "BOOT_MODE_0", "", "I2C_1_CLK", "I2C_1_DAT", @@ -231,14 +231,7 @@ "", "", "", ""; }; -&gpio2 { - gpio-line-names = - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - +/* CPU GPIO3: 20a4000.gpio */ &gpio3 { gpio-line-names = "HD12_SPI_CS", "JTAG_FPGA_TCK", "JTAG_FPGA_TMS", "JTAG_FPGA_TDI", @@ -251,6 +244,7 @@ "ETH_PHY_RESET#", "", "", ""; }; +/* CPU GPIO4: 20a8000.gpio */ &gpio4 { gpio-line-names = "", "", "", "", @@ -263,6 +257,7 @@ "SD_VSEL_1.8V", "", "", ""; }; +/* CPU GPIO5: 20ac000.gpio */ &gpio5 { gpio-line-names = "POWER_FAIL", "GPS_PPS_OUT", "", "GPIO_DVFS", @@ -284,12 +279,6 @@ sda-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; - /* - * Reference: Documentation/devicetree/bindings/iio/st-sensors.txt - * - * - MAG_N_IRQ enters NAND_ALE/SD2_RST#/PWM3 pad B4 - * - as well as the FPGA - */ st_magn: magnetometer@1e { compatible = "st,lis2mdl"; reg = <0x1e>; @@ -325,11 +314,6 @@ reg = <0x68>; }; - /* - * Reference: Documentation/devicetree/bindings/iio/imu/st_lsm6dsx.txt - * - * - GYRO_INT enters CSI_HSYNC (pad F3) - */ ism330: gyro@6a { compatible = "st,ism330dlc"; reg = <0x6a>; @@ -347,12 +331,11 @@ scl-gpios = <&gpio3 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio3 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - gpio6: gpio@28 { + gpio6: gpio-controller@28 { compatible = "technologic,ts4900-gpio"; reg = <0x28>; #gpio-cells = <2>; gpio-controller; - base = <160>; ngpios = <64>; gpio-line-names = "WIFI_RESET#", "EN_WIFI_PWR", "", "", @@ -411,10 +394,6 @@ MX6UL_PAD_LCD_HSYNC__GPIO3_IO02 0x1b020 /* JTAG_FPGA_TMS */ MX6UL_PAD_LCD_ENABLE__GPIO3_IO01 0x1b020 /* JTAG_FPGA_TCK */ MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x10020 /* 6UL_FORCE_5V_ON */ - /* EN_YEL_LED# in pinctrl_gpio_leds */ - /* EN_RED_LED# in pinctrl_gpio_leds */ - /* EN_GREEN_LED# in pinctrl_gpio_leds */ - /* EN_BLUE_LED in pinctrl_gpio_leds */ MX6UL_PAD_LCD_DATA06__GPIO3_IO11 0x1b020 /* NO_CHRG_JMP# */ MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x1b020 /* ID5 */ MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x03020 /* GYRO_INT */ @@ -427,7 +406,7 @@ >; }; - pinctrl_pwm5: ts7180pwm5 { + pinctrl_pwm5: ts7180pwm5grp { fsl,pins = < MX6UL_PAD_NAND_DQS__PWM5_OUT 0x13020 /* SPARE_3 */ >; @@ -549,7 +528,7 @@ >; }; - pinctrl_i2c1_gpio: i2c1grpgpio { + pinctrl_i2c1_gpio: i2c1gpiogrp { fsl,pins = < MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x4001b8b0 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x4001b8b0 @@ -563,14 +542,14 @@ >; }; - pinctrl_i2c3_gpio: i2c3grpgpio { + pinctrl_i2c3_gpio: i2c3gpiogrp { fsl,pins = < MX6UL_PAD_LCD_DATA01__GPIO3_IO06 0x4001b8b0 MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x4001b8b0 >; }; - pinctrl_i2c_gpio: i2cgrpgpio { + pinctrl_i2c_gpio: i2cgpiogrp { fsl,pins = < MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0x000108b0 /* HD12_I2C_CLK */ MX6UL_PAD_LCD_DATA04__GPIO3_IO09 0x000108b0 /* HD12_I2C_DAT */ @@ -608,25 +587,26 @@ pinctrl_usdhc1_100mhz: usdhc1grp100mhz { fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 >; }; pinctrl_usdhc1_200mhz: usdhc1grp200mhz { fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 >; }; + pinctrl_usdhc2: usdhc2grp { fsl,pins = < MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 @@ -694,8 +674,8 @@ &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; uart-has-rtscts; + status = "okay"; }; &uart4 { @@ -704,6 +684,8 @@ status = "okay"; rts-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>; linux,rs485-enabled-at-boot-time; + dma-names = "", ""; + status = "okay"; }; &uart5 { @@ -753,14 +735,14 @@ max-frequency = <208000000>; keep-power-in-suspend; enable-sdio-wakeup; - disable-wp; cap-sd-highspeed; sd-uhs-sdr12; sd-uhs-sdr25; sd-uhs-sdr50; sd-uhs-sdr104; sd-uhs-ddr50; - broken-cd = <1>; + disable-wp; + broken-cd; bus-width = <4>; status = "okay"; }; @@ -770,8 +752,8 @@ pinctrl-0 = <&pinctrl_usdhc2>; no-1-8-v; disable-wp; - broken-cd = <1>; - enable-sdio-wakeup; + non-removable; + broken-cd; bus-width = <4>; status = "okay"; }; From 67f46ec596b52966cb7230b6581901da6a736e4a Mon Sep 17 00:00:00 2001 From: "Lionel D. Hummel" Date: Fri, 19 Jan 2024 17:29:10 -0700 Subject: [PATCH 137/244] ARM: dts: ts7180: Alphabetize as much as is reasonable, but not more --- arch/arm/boot/dts/nxp/imx/imx6ul-ts7180.dts | 289 ++++++++++---------- 1 file changed, 145 insertions(+), 144 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7180.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7180.dts index 3e233c44ef443..f3ed2d01bbe10 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7180.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7180.dts @@ -27,6 +27,17 @@ reg = <0x80000000 0>; }; + i2c_gpio: i2c { + compatible = "i2c-gpio"; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_gpio>; + scl-gpios = <&gpio3 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* I2C_CLK on HD12 pin 6 */ + sda-gpios = <&gpio3 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* I2C_DAT on HD12 pin 1 */ + #address-cells = <1>; + #size-cells = <0>; + }; + led-controller { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_leds>; @@ -61,6 +72,21 @@ }; }; + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ppsgpio>; + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + reg_adc_vref: adc_vref { compatible = "regulator-fixed"; regulator-name = "ADC_VREF"; @@ -76,32 +102,6 @@ regulator-max-microvolt = <3300000>; gpio = <&gpio6 20 GPIO_ACTIVE_HIGH>; }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - i2c_gpio: i2c { - compatible = "i2c-gpio"; - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c_gpio>; - scl-gpios = <&gpio3 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* I2C_CLK on HD12 pin 6 */ - sda-gpios = <&gpio3 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* I2C_DAT on HD12 pin 1 */ - #address-cells = <1>; - #size-cells = <0>; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ppsgpio>; - gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; - }; }; &adc1 { @@ -361,6 +361,121 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; imx6ul-ts7180 { + pinctrl_adc: adcgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x1b020 /* ADC_1 */ + MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x1b020 /* ADC_2 */ + MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x1b020 /* ADC_3 */ + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x1b020 /* ADC_4 */ + + >; + }; + + pinctrl_dvfs: dvfsgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6UL_PAD_NAND_READY_B__GPIO4_IO12 0x10b0 // SPI_3_FPGA_CS# + MX6UL_PAD_NAND_CE0_B__ECSPI3_SCLK 0x10b0 // SPI_3_CLK + MX6UL_PAD_NAND_CE1_B__ECSPI3_MOSI 0x10b0 // SPI_3_MOSI + MX6UL_PAD_NAND_CLE__ECSPI3_MISO 0x10b0 // SPI_3_MISO + MX6UL_PAD_LCD_CLK__GPIO3_IO00 0x10b0 // HD12_SPI_CS (active high) + MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x10b0 // FRAM_SPI_CS# + >; + }; + + pinctrl_ecspi4: ecspi4grp { + fsl,pins = < + MX6UL_PAD_NAND_DATA04__ECSPI4_SCLK 0x10b0 + MX6UL_PAD_NAND_DATA05__ECSPI4_MOSI 0x10b0 + MX6UL_PAD_NAND_DATA06__ECSPI4_MISO 0x10b0 + MX6UL_PAD_NAND_DATA07__GPIO4_IO09 0x10b0 // WIFI chip select + MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x1b020 // SPARE_4/WIFI_IRQ + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_LCD_DATA23__GPIO3_IO28 0x1a020 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + >; + }; + + pinctrl_flexcan1: flexcan1grp{ + fsl,pins = < + MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX 0x1b020 + MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX 0x1b020 + >; + }; + + pinctrl_flexcan2: flexcan2grp{ + fsl,pins = < + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x4001b8b0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x4001b8b0 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA01__I2C3_SCL 0x4001b8b0 + MX6UL_PAD_LCD_DATA00__I2C3_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA01__GPIO3_IO06 0x4001b8b0 + MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x4001b8b0 + >; + }; + + pinctrl_i2c_gpio: i2cgpiogrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0x000108b0 /* HD12_I2C_CLK */ + MX6UL_PAD_LCD_DATA04__GPIO3_IO09 0x000108b0 /* HD12_I2C_DAT */ + >; + }; + pinctrl_gpio_leds: leds1grp { fsl,pins = < MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x1b020 /* EN_YEL_LED# */ @@ -412,26 +527,6 @@ >; }; - pinctrl_usb_otg1_id: usbotg1idgrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 - >; - }; - - pinctrl_flexcan1: flexcan1grp{ - fsl,pins = < - MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX 0x1b020 - MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX 0x1b020 - >; - }; - - pinctrl_flexcan2: flexcan2grp{ - fsl,pins = < - MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 - MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 - >; - }; - pinctrl_uart1: uart1grp { fsl,pins = < MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 @@ -492,67 +587,9 @@ >; }; - pinctrl_enet1: enet1grp { - fsl,pins = < - MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 - MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 - >; - }; - - pinctrl_enet2: enet2grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 - MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 - MX6UL_PAD_LCD_DATA23__GPIO3_IO28 0x1a020 - MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 - MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x4001b8b0 - MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x4001b8b0 - >; - }; - - pinctrl_i2c1_gpio: i2c1gpiogrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x4001b8b0 - MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x4001b8b0 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6UL_PAD_LCD_DATA01__I2C3_SCL 0x4001b8b0 - MX6UL_PAD_LCD_DATA00__I2C3_SDA 0x4001b8b0 - >; - }; - - pinctrl_i2c3_gpio: i2c3gpiogrp { - fsl,pins = < - MX6UL_PAD_LCD_DATA01__GPIO3_IO06 0x4001b8b0 - MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x4001b8b0 - >; - }; - - pinctrl_i2c_gpio: i2cgpiogrp { + pinctrl_usb_otg1_id: usbotg1idgrp { fsl,pins = < - MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0x000108b0 /* HD12_I2C_CLK */ - MX6UL_PAD_LCD_DATA04__GPIO3_IO09 0x000108b0 /* HD12_I2C_DAT */ + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 >; }; @@ -569,22 +606,6 @@ >; }; - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 - >; - }; - - pinctrl_adc: adcgrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x1b020 /* ADC_1 */ - MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x1b020 /* ADC_2 */ - MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x1b020 /* ADC_3 */ - MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x1b020 /* ADC_4 */ - - >; - }; - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { fsl,pins = < MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 @@ -620,32 +641,12 @@ >; }; - pinctrl_ecspi3: ecspi3grp { - fsl,pins = < - MX6UL_PAD_NAND_READY_B__GPIO4_IO12 0x10b0 // SPI_3_FPGA_CS# - MX6UL_PAD_NAND_CE0_B__ECSPI3_SCLK 0x10b0 // SPI_3_CLK - MX6UL_PAD_NAND_CE1_B__ECSPI3_MOSI 0x10b0 // SPI_3_MOSI - MX6UL_PAD_NAND_CLE__ECSPI3_MISO 0x10b0 // SPI_3_MISO - MX6UL_PAD_LCD_CLK__GPIO3_IO00 0x10b0 // HD12_SPI_CS (active high) - MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x10b0 // FRAM_SPI_CS# - >; - }; - - pinctrl_ecspi4: ecspi4grp { + pinctrl_wdog: wdoggrp { fsl,pins = < - MX6UL_PAD_NAND_DATA04__ECSPI4_SCLK 0x10b0 - MX6UL_PAD_NAND_DATA05__ECSPI4_MOSI 0x10b0 - MX6UL_PAD_NAND_DATA06__ECSPI4_MISO 0x10b0 - MX6UL_PAD_NAND_DATA07__GPIO4_IO09 0x10b0 // WIFI chip select - MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x1b020 // SPARE_4/WIFI_IRQ + MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 >; }; - pinctrl_dvfs: dvfsgrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79 - >; - }; }; }; From 958ccd99db5e514b37a6dc8963fa50874b4d0544 Mon Sep 17 00:00:00 2001 From: "Lionel D. Hummel" Date: Tue, 23 Jan 2024 12:43:30 -0700 Subject: [PATCH 138/244] ARM: dts: ts7180: fix merge typo --- arch/arm/boot/dts/nxp/imx/imx6ul-ts7180.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7180.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7180.dts index f3ed2d01bbe10..0c422e5d2e3a6 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7180.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7180.dts @@ -682,7 +682,6 @@ &uart4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; rts-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>; linux,rs485-enabled-at-boot-time; dma-names = "", ""; From 2f932970fe910a0d805c50bee0228b1825c34348 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Thu, 15 Feb 2024 22:19:05 +0000 Subject: [PATCH 139/244] ARM: tsimx6ul: remap fbcon via cmdline extend While DRM has emulation for fbdev, by default this also enables FRAMEBUFFER_CONSOLE which cannot be disabled without much additional work and consideration as it requires CONFIG_EXPERT. Instead, using fbcon kernel commandline arguments, its possible to remap the tty to a different /dev/fb* device. In this case, using fbcon=map:31, we can force a tty to not spawn on any /dev/fb* below /dev/fb30 In order to work around this across all devices, this cmdline option is instead moved to the kernel's builtin default cmdline, and the default cmdline is then set to extend the cmdline passed by the bootloader. This is needed as the i.MX6UL platforms span many U-Boot releases each with their own way of handling the kernel commandline. Adding the fbcon option to the commandline would require touching multiple types of U-Boot scripts. Signed-off-by: Kris Bahnsen --- arch/arm/configs/tsimx6ul_defconfig | 4 ++-- arch/arm/configs/tsimx6ul_minimal_defconfig | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/configs/tsimx6ul_defconfig b/arch/arm/configs/tsimx6ul_defconfig index ee2d2643c4f0f..fb4aea96e3ea2 100644 --- a/arch/arm/configs/tsimx6ul_defconfig +++ b/arch/arm/configs/tsimx6ul_defconfig @@ -35,7 +35,8 @@ CONFIG_ARM_PSCI=y CONFIG_HZ_1000=y CONFIG_HIGHMEM=y CONFIG_FORCE_MAX_ZONEORDER=14 -CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" +CONFIG_CMDLINE="fbcon=map:31" +CONFIG_CMDLINE_EXTEND=y CONFIG_EFI=y CONFIG_CPU_FREQ=y CONFIG_CPU_FREQ_STAT=y @@ -676,7 +677,6 @@ CONFIG_SPI_GPIO=y CONFIG_SPI_IMX=y CONFIG_SPI_OCORES=m CONFIG_SPI_SPIDEV=y -CONFIG_PPS=m CONFIG_PPS_CLIENT_LDISC=m CONFIG_PPS_CLIENT_GPIO=m CONFIG_PTP_1588_CLOCK=m diff --git a/arch/arm/configs/tsimx6ul_minimal_defconfig b/arch/arm/configs/tsimx6ul_minimal_defconfig index 8af602b6f622f..65088589a7426 100644 --- a/arch/arm/configs/tsimx6ul_minimal_defconfig +++ b/arch/arm/configs/tsimx6ul_minimal_defconfig @@ -20,7 +20,8 @@ CONFIG_ARM_PSCI=y CONFIG_HZ_1000=y CONFIG_HIGHMEM=y CONFIG_FORCE_MAX_ZONEORDER=14 -CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" +CONFIG_CMDLINE="fbcon=map:31" +CONFIG_CMDLINE_EXTEND=y CONFIG_CPU_FREQ=y CONFIG_CPU_FREQ_STAT=y CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y @@ -197,7 +198,6 @@ CONFIG_SPI_GPIO=y CONFIG_SPI_IMX=y CONFIG_SPI_OCORES=m CONFIG_SPI_SPIDEV=y -CONFIG_PPS=m CONFIG_PPS_CLIENT_LDISC=m CONFIG_PPS_CLIENT_GPIO=m CONFIG_PTP_1588_CLOCK=m From bbad52737ea1a16e40d2cf6693262645a273d43b Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Tue, 23 Apr 2024 22:11:48 +0000 Subject: [PATCH 140/244] ARM: dts: imx28: fix enet flapping issue The net system is (intentionally) designed to only ever issue a hardware reset once. While there have been some hacks over the years to try and bring in a runtime PHY reset control, for example to reduce power by turning everything off when the interface is down; these are unused by many drivers and look to be slowly ripped out over time. The FEC driver, while aware of the imx28 ENET_CLK out, still ends up turning it off at points. Because of the above design choice to only ever reset once, this means the PHY has its clock turned off and back on without a real reset. And in the case of the imx28 MAC, this defaults to 25 MHz, then goes to 50 MHz, when there is a MAC restart. By connecting the enet-out clock to the ethphy handle, this gets connected to the PHY driver which never turns it off. This keeps the clock refcount always positive, and the clock will never turn off. Testing has shown this to eliminate the ethernet PHY link cycling/flapping issue on out i.MX28 platforms. Signed-off-by: Kris Bahnsen --- arch/arm/boot/dts/nxp/mxs/imx28-ts7400v2.dts | 5 ++++- arch/arm/boot/dts/nxp/mxs/imx28-ts7670.dts | 5 ++++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-ts7400v2.dts b/arch/arm/boot/dts/nxp/mxs/imx28-ts7400v2.dts index 9c56ca93c4363..a0855f3981184 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-ts7400v2.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-ts7400v2.dts @@ -199,7 +199,7 @@ phy-supply = <®_enet_3v3>; phy-handle = <ðphy0>; phy-reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; - phy-reset-duration = <26>; + phy-reset-duration = <100>; phy-reset-post-delay = <1>; status = "okay"; @@ -209,6 +209,9 @@ ethphy0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; + /* magic number "64" is enet out from CPU */ + clocks = <&clks 64>; + clock-names = "rmii-ref"; reg = <0>; }; }; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-ts7670.dts b/arch/arm/boot/dts/nxp/mxs/imx28-ts7670.dts index 0f3719ebd3892..87d1d5604a8aa 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-ts7670.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-ts7670.dts @@ -227,7 +227,7 @@ phy-supply = <®_enet_3v3>; phy-handle = <ðphy0>; phy-reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; - phy-reset-duration = <26>; + phy-reset-duration = <100>; phy-reset-post-delay = <1>; status = "okay"; @@ -237,6 +237,9 @@ ethphy0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; + /* magic number "64" is enet out from CPU */ + clocks = <&clks 64>; + clock-names = "rmii-ref"; reg = <0>; }; }; From 8403de8cdc2715b3382d0d54adb9f0c4f85ffa5b Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Wed, 24 Apr 2024 10:52:55 -0700 Subject: [PATCH 141/244] pwm: pwm-ts: Fix inversed before enabling pwm (#75) This allows inversed to be set without first turning on the PWM. This also removes the state in the ts object that was tracking state, and now the calc function sets the registers. Removed the spinlock which is not used or needed. --- drivers/pwm/pwm-ts.c | 57 +++++++++++++------------------------------- 1 file changed, 17 insertions(+), 40 deletions(-) diff --git a/drivers/pwm/pwm-ts.c b/drivers/pwm/pwm-ts.c index 48e8af3295693..491ec3fb372a9 100644 --- a/drivers/pwm/pwm-ts.c +++ b/drivers/pwm/pwm-ts.c @@ -16,7 +16,6 @@ #include #include #include -#include /* Enabled bit is the only one that applies immediately. All other registers * take effect when apply is set @@ -37,11 +36,6 @@ struct ts_pwm { struct pwm_chip chip; void __iomem *base; - spinlock_t lock; - u16 duty; - u16 period; - u8 shift; - struct pwm_state state; struct clk *clk; }; @@ -56,7 +50,9 @@ static int ts_pwm_calc(struct ts_pwm *ts, { unsigned long clk_rate = clk_get_rate(ts->clk); unsigned long long cycle; - unsigned int shift, cnt, duty_cnt; + unsigned int cnt, duty_cnt; + u16 duty_reg; + u8 shift; /* Calc shift & period reg */ for (shift = 0; shift < SHIFT_MAX; shift++) { @@ -73,14 +69,11 @@ static int ts_pwm_calc(struct ts_pwm *ts, dev_dbg(ts->chip.dev, "cycle=%llu shift=%u cnt=%u\n", cycle, shift, cnt); + if (duty == period) { - ts->shift = shift; - ts->period = cnt; - ts->duty = cnt; + duty_reg = cnt; } else if (duty == 0) { - ts->shift = shift; - ts->period = cnt; - ts->duty = 0; + duty_reg = 0; } else { duty_cnt = DIV_ROUND_CLOSEST(duty * 100, (unsigned int)cycle); if (duty_cnt > CYCLE_MASK) { @@ -90,12 +83,13 @@ static int ts_pwm_calc(struct ts_pwm *ts, dev_dbg(ts->chip.dev, "shift=%u cnt=%u duty_cnt=%u\n", shift, cnt, duty_cnt); - - ts->shift = shift; - ts->period = cnt; - ts->duty = cnt - duty_cnt; + duty_reg = cnt - duty_cnt; } + writew(cnt, ts->base + REG_PERIOD); + writew(duty_reg, ts->base + REG_DUTY); + writew(shift, ts->base + REG_SHIFT); + return 0; } @@ -103,36 +97,20 @@ static int ts_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, const struct pwm_state *state) { struct ts_pwm *ts = to_ts_pwm(chip); - u16 value = 0; int err; + u16 ctrl = 0; - BUG_ON(!state); - - if (!state->enabled) { - writel(0x0, ts->base + REG_CONFIG); - ts->state.enabled = false; - return 0; - } - - if (state->polarity == PWM_POLARITY_NORMAL) - value &= ~(INVERSED); - else - value |= INVERSED; + if (state->polarity != PWM_POLARITY_NORMAL) + ctrl |= INVERSED; + if (state->enabled) + ctrl |= ENABLED; err = ts_pwm_calc(ts, state->duty_cycle, state->period); if (err < 0) return err; - ts->state.polarity = state->polarity; - ts->state.period = state->period; - ts->state.duty_cycle = state->duty_cycle; - ts->state.enabled = true; - - writew(ts->period, ts->base + REG_PERIOD); - writew(ts->duty, ts->base + REG_DUTY); - writew(ts->shift, ts->base + REG_SHIFT); - writew(value | ENABLED, ts->base + REG_CONFIG); + writew(ctrl, ts->base + REG_CONFIG); return 0; } @@ -171,7 +149,6 @@ static int ts_pwm_probe(struct platform_device *pdev) platform_set_drvdata(pdev, ts); - spin_lock_init(&ts->lock); ts->chip.dev = &pdev->dev; ts->chip.ops = &ts_pwm_ops; ts->chip.base = -1; From cc058c67b941c77f9661c43bdf9250308a42f90d Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Wed, 24 Apr 2024 10:50:48 -0700 Subject: [PATCH 142/244] ARM: dts: imx6qdl-ts7990: Add i2c pinctrl and sda/scl gpios for recovery Set default speed, and added i2c recovery gpio. --- arch/arm/boot/dts/nxp/imx/imx6qdl-ts7990.dtsi | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7990.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7990.dtsi index f4c601eba493b..f7f48d9e5ed47 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7990.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7990.dtsi @@ -262,9 +262,13 @@ }; &i2c1 { - status = "okay"; - pinctrl-names = "default"; + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; pixcir_tangoc: touchscreen@5c { compatible = "pixcir,pixcir_tangoc"; @@ -284,7 +288,6 @@ */ invert-int-output; wakeup-source; - status = "disabled"; }; /* Only present on REV E and above */ @@ -361,10 +364,13 @@ }; &i2c2 { - status = "okay"; clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; }; &iomuxc { From 42f5160cd4c0caf65281778d233c2945e4935e17 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Tue, 14 May 2024 23:30:36 +0000 Subject: [PATCH 143/244] ARM: dts: ts4100-8551: reduce SPI speed to FRAM Due to it being offboard, the added connections and trace lengths cause rare glitches at the full bus speed Signed-off-by: Kris Bahnsen --- arch/arm/boot/dts/nxp/imx/imx6ul-ts4100-ts8551.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts4100-ts8551.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-ts4100-ts8551.dtsi index bd385ebf41806..0803888877ed5 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-ts4100-ts8551.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts4100-ts8551.dtsi @@ -17,7 +17,7 @@ spifram: eeprom@1 { compatible = "atmel,at25", "cypress,fm25l16b"; reg = <1>; - spi-max-frequency = <20000000>; + spi-max-frequency = <2000000>; size = <0x800>; address-width = <16>; pagesize = <64>; From fb070b75bd366942ce960ee2893b9a9cda710cb0 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Thu, 23 May 2024 22:33:35 +0000 Subject: [PATCH 144/244] ARM: configs: tsa38x: updates for 6.6 Signed-off-by: Kris Bahnsen --- arch/arm/configs/tsa38x_defconfig | 60 +++++++++++++------------------ 1 file changed, 25 insertions(+), 35 deletions(-) diff --git a/arch/arm/configs/tsa38x_defconfig b/arch/arm/configs/tsa38x_defconfig index 562da50f092a6..e1bb33964d6ef 100644 --- a/arch/arm/configs/tsa38x_defconfig +++ b/arch/arm/configs/tsa38x_defconfig @@ -2,6 +2,8 @@ CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y # CONFIG_CROSS_MEMORY_ATTACH is not set CONFIG_HIGH_RES_TIMERS=y +CONFIG_BPF_SYSCALL=y +CONFIG_BPF_JIT=y CONFIG_PREEMPT=y CONFIG_PSI=y CONFIG_LOG_BUF_SHIFT=14 @@ -26,9 +28,7 @@ CONFIG_BLK_DEV_INITRD=y # CONFIG_RD_ZSTD is not set CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_EXPERT=y -CONFIG_BPF_SYSCALL=y CONFIG_PERF_EVENTS=y -CONFIG_SLAB=y CONFIG_ARCH_MVEBU=y CONFIG_MACH_ARMADA_38X=y CONFIG_ARM_THUMBEE=y @@ -48,7 +48,6 @@ CONFIG_NEON=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODVERSIONS=y -CONFIG_MODULE_COMPRESS=y CONFIG_MODULE_COMPRESS_XZ=y # CONFIG_MQ_IOSCHED_KYBER is not set CONFIG_BINFMT_MISC=y @@ -129,7 +128,6 @@ CONFIG_NETWORK_SECMARK=y CONFIG_NETFILTER=y CONFIG_BRIDGE_NETFILTER=m CONFIG_NF_CONNTRACK=m -CONFIG_NF_LOG_NETDEV=m CONFIG_NF_CONNTRACK_SECMARK=y CONFIG_NF_CONNTRACK_ZONES=y CONFIG_NF_CONNTRACK_PROCFS=y @@ -156,7 +154,6 @@ CONFIG_NF_TABLES_NETDEV=y CONFIG_NFT_NUMGEN=m CONFIG_NFT_CT=m CONFIG_NFT_FLOW_OFFLOAD=m -CONFIG_NFT_COUNTER=m CONFIG_NFT_CONNLIMIT=m CONFIG_NFT_LOG=m CONFIG_NFT_LIMIT=m @@ -164,7 +161,6 @@ CONFIG_NFT_MASQ=m CONFIG_NFT_REDIR=m CONFIG_NFT_NAT=m CONFIG_NFT_TUNNEL=m -CONFIG_NFT_OBJREF=m CONFIG_NFT_QUEUE=m CONFIG_NFT_QUOTA=m CONFIG_NFT_REJECT=m @@ -286,8 +282,8 @@ CONFIG_IP_VS_PE_SIP=m CONFIG_NFT_DUP_IPV4=m CONFIG_NFT_FIB_IPV4=m CONFIG_NF_TABLES_ARP=y -CONFIG_NF_FLOW_TABLE_IPV4=m CONFIG_NF_LOG_ARP=m +CONFIG_NF_LOG_IPV4=m CONFIG_IP_NF_IPTABLES=m CONFIG_IP_NF_MATCH_AH=m CONFIG_IP_NF_MATCH_ECN=m @@ -301,7 +297,6 @@ CONFIG_IP_NF_TARGET_MASQUERADE=m CONFIG_IP_NF_TARGET_NETMAP=m CONFIG_IP_NF_TARGET_REDIRECT=m CONFIG_IP_NF_MANGLE=m -CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_TARGET_ECN=m CONFIG_IP_NF_TARGET_TTL=m CONFIG_IP_NF_RAW=m @@ -310,7 +305,6 @@ CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m CONFIG_NFT_DUP_IPV6=m CONFIG_NFT_FIB_IPV6=m -CONFIG_NF_FLOW_TABLE_IPV6=m CONFIG_IP6_NF_IPTABLES=m CONFIG_IP6_NF_MATCH_AH=m CONFIG_IP6_NF_MATCH_EUI64=m @@ -334,7 +328,6 @@ CONFIG_IP6_NF_TARGET_NPT=m CONFIG_NF_TABLES_BRIDGE=m CONFIG_NFT_BRIDGE_META=m CONFIG_NFT_BRIDGE_REJECT=m -CONFIG_NF_LOG_BRIDGE=m CONFIG_NF_CONNTRACK_BRIDGE=m CONFIG_BRIDGE_NF_EBTABLES=m CONFIG_BRIDGE_EBT_BROUTE=m @@ -385,25 +378,10 @@ CONFIG_VSOCKETS=m CONFIG_NETLINK_DIAG=m CONFIG_HSR=m CONFIG_CGROUP_NET_PRIO=y -CONFIG_BPF_JIT=y CONFIG_BPF_STREAM_PARSER=y CONFIG_CAN=m CONFIG_CAN_J1939=m CONFIG_CAN_ISOTP=m -CONFIG_CAN_VCAN=m -CONFIG_CAN_VXCAN=m -CONFIG_CAN_SLCAN=m -CONFIG_CAN_SJA1000=m -CONFIG_CAN_SJA1000_ISA=m -CONFIG_CAN_SJA1000_PLATFORM=m -CONFIG_CAN_8DEV_USB=m -CONFIG_CAN_EMS_USB=m -CONFIG_CAN_ESD_USB2=m -CONFIG_CAN_GS_USB=m -CONFIG_CAN_KVASER_USB=m -CONFIG_CAN_MCBA_USB=m -CONFIG_CAN_PEAK_USB=m -CONFIG_CAN_UCAN=m CONFIG_BT=m CONFIG_BT_RFCOMM=m CONFIG_BT_RFCOMM_TTY=y @@ -499,9 +477,7 @@ CONFIG_NET_DSA_MV88E6XXX=m # CONFIG_NET_VENDOR_AQUANTIA is not set # CONFIG_NET_VENDOR_ARC is not set # CONFIG_NET_VENDOR_ATHEROS is not set -# CONFIG_NET_VENDOR_AURORA is not set # CONFIG_NET_VENDOR_BROADCOM is not set -# CONFIG_NET_VENDOR_BROCADE is not set # CONFIG_NET_VENDOR_CADENCE is not set # CONFIG_NET_VENDOR_CAVIUM is not set # CONFIG_NET_VENDOR_CHELSIO is not set @@ -523,15 +499,16 @@ CONFIG_MVNETA=y # CONFIG_NET_VENDOR_MICROCHIP is not set # CONFIG_NET_VENDOR_MICROSEMI is not set # CONFIG_NET_VENDOR_MYRI is not set +# CONFIG_NET_VENDOR_NI is not set # CONFIG_NET_VENDOR_NATSEMI is not set # CONFIG_NET_VENDOR_NETERION is not set # CONFIG_NET_VENDOR_NETRONOME is not set -# CONFIG_NET_VENDOR_NI is not set # CONFIG_NET_VENDOR_NVIDIA is not set # CONFIG_NET_VENDOR_OKI is not set # CONFIG_NET_VENDOR_PACKET_ENGINES is not set # CONFIG_NET_VENDOR_PENSANDO is not set # CONFIG_NET_VENDOR_QLOGIC is not set +# CONFIG_NET_VENDOR_BROCADE is not set # CONFIG_NET_VENDOR_QUALCOMM is not set # CONFIG_NET_VENDOR_RDC is not set # CONFIG_NET_VENDOR_REALTEK is not set @@ -539,9 +516,9 @@ CONFIG_MVNETA=y # CONFIG_NET_VENDOR_ROCKER is not set # CONFIG_NET_VENDOR_SAMSUNG is not set # CONFIG_NET_VENDOR_SEEQ is not set -# CONFIG_NET_VENDOR_SOLARFLARE is not set # CONFIG_NET_VENDOR_SILAN is not set # CONFIG_NET_VENDOR_SIS is not set +# CONFIG_NET_VENDOR_SOLARFLARE is not set # CONFIG_NET_VENDOR_SMSC is not set # CONFIG_NET_VENDOR_SOCIONEXT is not set # CONFIG_NET_VENDOR_STMICRO is not set @@ -554,6 +531,20 @@ CONFIG_MVNETA=y # CONFIG_NET_VENDOR_XILINX is not set CONFIG_SFP=y CONFIG_MARVELL_PHY=y +CONFIG_CAN_VCAN=m +CONFIG_CAN_VXCAN=m +CONFIG_CAN_SLCAN=m +CONFIG_CAN_SJA1000=m +CONFIG_CAN_SJA1000_ISA=m +CONFIG_CAN_SJA1000_PLATFORM=m +CONFIG_CAN_8DEV_USB=m +CONFIG_CAN_EMS_USB=m +CONFIG_CAN_ESD_USB=m +CONFIG_CAN_GS_USB=m +CONFIG_CAN_KVASER_USB=m +CONFIG_CAN_MCBA_USB=m +CONFIG_CAN_PEAK_USB=m +CONFIG_CAN_UCAN=m CONFIG_PPP=m CONFIG_PPP_BSDCOMP=m CONFIG_PPP_DEFLATE=m @@ -671,6 +662,7 @@ CONFIG_SERIAL_DEV_BUS=y CONFIG_HW_RANDOM=y # CONFIG_HW_RANDOM_OMAP is not set CONFIG_HW_RANDOM_TS78XX=y +# CONFIG_DEVPORT is not set CONFIG_I2C=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_GPIO=y @@ -760,7 +752,6 @@ CONFIG_USB_SERIAL_SIERRAWIRELESS=m CONFIG_USB_SERIAL_SYMBOL=m CONFIG_USB_SERIAL_TI=m CONFIG_USB_SERIAL_CYBERJACK=m -CONFIG_USB_SERIAL_XIRCOM=m CONFIG_USB_SERIAL_OPTION=m CONFIG_USB_SERIAL_OMNINET=m CONFIG_USB_SERIAL_OPTICON=m @@ -776,6 +767,7 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_PXAV3=y CONFIG_MMC_MVSDIO=y +CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y CONFIG_LEDS_GPIO=y CONFIG_LEDS_TRIGGER_TIMER=y @@ -784,7 +776,6 @@ CONFIG_LEDS_TRIGGER_DISK=y CONFIG_LEDS_TRIGGER_HEARTBEAT=y CONFIG_LEDS_TRIGGER_CPU=y CONFIG_LEDS_TRIGGER_ACTIVITY=m -CONFIG_LEDS_TRIGGER_GPIO=m CONFIG_LEDS_TRIGGER_DEFAULT_ON=y CONFIG_LEDS_TRIGGER_TRANSIENT=m CONFIG_LEDS_TRIGGER_PANIC=y @@ -835,19 +826,18 @@ CONFIG_NLS_ISO8859_1=y CONFIG_NLS_ISO8859_2=y CONFIG_NLS_UTF8=y CONFIG_CRYPTO_ECDH=y -CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_AES=y CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_GCM=y CONFIG_CRYPTO_CMAC=y -CONFIG_CRYPTO_AES=y CONFIG_CRYPTO_DEFLATE=y CONFIG_CRYPTO_LZO=y CONFIG_CRYPTO_ZSTD=y CONFIG_CRYPTO_DEV_MARVELL_CESA=y CONFIG_CRC7=m CONFIG_PRINTK_TIME=y -CONFIG_DEBUG_FS=y # CONFIG_DEBUG_MISC is not set -CONFIG_STACKTRACE=y +CONFIG_DEBUG_FS=y # CONFIG_FTRACE is not set CONFIG_DEBUG_USER=y # CONFIG_RUNTIME_TESTING_MENU is not set From 6f8c929c66306e225da388982a90c19353b32e74 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Thu, 23 May 2024 22:40:18 +0000 Subject: [PATCH 145/244] ARM: configs: tsa38x_minimal: updates for 6.6 Signed-off-by: Kris Bahnsen --- arch/arm/configs/tsa38x_minimal_defconfig | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/arch/arm/configs/tsa38x_minimal_defconfig b/arch/arm/configs/tsa38x_minimal_defconfig index 25cdd15c4f2a2..4d35aca8fbe52 100644 --- a/arch/arm/configs/tsa38x_minimal_defconfig +++ b/arch/arm/configs/tsa38x_minimal_defconfig @@ -1,4 +1,3 @@ -# CONFIG_SWAP is not set CONFIG_SYSVIPC=y # CONFIG_CROSS_MEMORY_ATTACH is not set CONFIG_HIGH_RES_TIMERS=y @@ -15,7 +14,6 @@ CONFIG_BLK_DEV_INITRD=y CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_EXPERT=y CONFIG_PERF_EVENTS=y -CONFIG_SLAB=y CONFIG_ARCH_MVEBU=y CONFIG_MACH_ARMADA_38X=y CONFIG_ARM_THUMBEE=y @@ -33,10 +31,10 @@ CONFIG_VFP=y CONFIG_NEON=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_COMPRESS=y CONFIG_MODULE_COMPRESS_XZ=y # CONFIG_MQ_IOSCHED_KYBER is not set CONFIG_BINFMT_MISC=y +# CONFIG_SWAP is not set # CONFIG_COMPACTION is not set CONFIG_NET=y CONFIG_PACKET=y @@ -48,9 +46,6 @@ CONFIG_IP_PNP_DHCP=y CONFIG_NET_DSA=y CONFIG_VLAN_8021Q=y CONFIG_CAN=m -CONFIG_CAN_SJA1000=m -CONFIG_CAN_SJA1000_ISA=m -CONFIG_CAN_SJA1000_PLATFORM=m CONFIG_BT=m CONFIG_BT_HCIUART=m CONFIG_BT_HCIUART_H4=y @@ -91,9 +86,7 @@ CONFIG_NET_DSA_MV88E6XXX=y # CONFIG_NET_VENDOR_AQUANTIA is not set # CONFIG_NET_VENDOR_ARC is not set # CONFIG_NET_VENDOR_ATHEROS is not set -# CONFIG_NET_VENDOR_AURORA is not set # CONFIG_NET_VENDOR_BROADCOM is not set -# CONFIG_NET_VENDOR_BROCADE is not set # CONFIG_NET_VENDOR_CADENCE is not set # CONFIG_NET_VENDOR_CAVIUM is not set # CONFIG_NET_VENDOR_CHELSIO is not set @@ -115,15 +108,16 @@ CONFIG_MVNETA=y # CONFIG_NET_VENDOR_MICROCHIP is not set # CONFIG_NET_VENDOR_MICROSEMI is not set # CONFIG_NET_VENDOR_MYRI is not set +# CONFIG_NET_VENDOR_NI is not set # CONFIG_NET_VENDOR_NATSEMI is not set # CONFIG_NET_VENDOR_NETERION is not set # CONFIG_NET_VENDOR_NETRONOME is not set -# CONFIG_NET_VENDOR_NI is not set # CONFIG_NET_VENDOR_NVIDIA is not set # CONFIG_NET_VENDOR_OKI is not set # CONFIG_NET_VENDOR_PACKET_ENGINES is not set # CONFIG_NET_VENDOR_PENSANDO is not set # CONFIG_NET_VENDOR_QLOGIC is not set +# CONFIG_NET_VENDOR_BROCADE is not set # CONFIG_NET_VENDOR_QUALCOMM is not set # CONFIG_NET_VENDOR_RDC is not set # CONFIG_NET_VENDOR_REALTEK is not set @@ -131,9 +125,9 @@ CONFIG_MVNETA=y # CONFIG_NET_VENDOR_ROCKER is not set # CONFIG_NET_VENDOR_SAMSUNG is not set # CONFIG_NET_VENDOR_SEEQ is not set -# CONFIG_NET_VENDOR_SOLARFLARE is not set # CONFIG_NET_VENDOR_SILAN is not set # CONFIG_NET_VENDOR_SIS is not set +# CONFIG_NET_VENDOR_SOLARFLARE is not set # CONFIG_NET_VENDOR_SMSC is not set # CONFIG_NET_VENDOR_SOCIONEXT is not set # CONFIG_NET_VENDOR_STMICRO is not set @@ -146,6 +140,9 @@ CONFIG_MVNETA=y # CONFIG_NET_VENDOR_XILINX is not set CONFIG_SFP=y CONFIG_MARVELL_PHY=y +CONFIG_CAN_SJA1000=m +CONFIG_CAN_SJA1000_ISA=m +CONFIG_CAN_SJA1000_PLATFORM=m CONFIG_USB_NET_DRIVERS=m CONFIG_USB_USBNET=m # CONFIG_USB_NET_AX8817X is not set @@ -188,7 +185,6 @@ CONFIG_HW_RANDOM=y # CONFIG_HW_RANDOM_OMAP is not set CONFIG_HW_RANDOM_TS78XX=y # CONFIG_DEVPORT is not set -# CONFIG_RANDOM_TRUST_BOOTLOADER is not set CONFIG_I2C=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_GPIO=y @@ -271,9 +267,9 @@ CONFIG_NLS_ISO8859_1=y CONFIG_NLS_ISO8859_2=y CONFIG_NLS_UTF8=y CONFIG_CRYPTO_ECDH=y +CONFIG_CRYPTO_AES=y CONFIG_CRYPTO_ECB=y CONFIG_CRYPTO_CMAC=y -CONFIG_CRYPTO_AES=y CONFIG_CRYPTO_DEFLATE=y CONFIG_CRYPTO_LZO=y CONFIG_CRYPTO_ZSTD=y @@ -281,6 +277,7 @@ CONFIG_CRYPTO_DEV_MARVELL_CESA=y CONFIG_CRC_ITU_T=m CONFIG_CRC7=m # CONFIG_DEBUG_MISC is not set +# CONFIG_SLUB_DEBUG is not set # CONFIG_FTRACE is not set CONFIG_DEBUG_USER=y # CONFIG_RUNTIME_TESTING_MENU is not set From 17d84a315b816f01ce51cfcae4dc65ee368a2922 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Thu, 23 May 2024 22:56:40 +0000 Subject: [PATCH 146/244] ARM: configs: tsimx6: updates for 6.6 Signed-off-by: Kris Bahnsen --- arch/arm/configs/tsimx6_defconfig | 102 ++++++++++++------------------ 1 file changed, 42 insertions(+), 60 deletions(-) diff --git a/arch/arm/configs/tsimx6_defconfig b/arch/arm/configs/tsimx6_defconfig index 6f2ca151eb285..5d8a10366272a 100644 --- a/arch/arm/configs/tsimx6_defconfig +++ b/arch/arm/configs/tsimx6_defconfig @@ -4,6 +4,8 @@ CONFIG_POSIX_MQUEUE=y # CONFIG_CROSS_MEMORY_ATTACH is not set CONFIG_NO_HZ_IDLE=y CONFIG_HIGH_RES_TIMERS=y +CONFIG_BPF_SYSCALL=y +CONFIG_BPF_JIT=y CONFIG_PREEMPT=y CONFIG_PSI=y # CONFIG_CPU_ISOLATION is not set @@ -22,10 +24,6 @@ CONFIG_USER_NS=y CONFIG_CHECKPOINT_RESTORE=y CONFIG_BLK_DEV_INITRD=y CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_BPF_SYSCALL=y -# CONFIG_COMPAT_BRK is not set -CONFIG_SLAB=y -# CONFIG_SLAB_MERGE_DEFAULT is not set CONFIG_ARCH_MULTI_V6=y CONFIG_ARCH_MXC=y CONFIG_SOC_IMX6Q=y @@ -36,7 +34,6 @@ CONFIG_HOTPLUG_CPU=y CONFIG_ARM_PSCI=y CONFIG_HZ_1000=y CONFIG_HIGHMEM=y -CONFIG_FORCE_MAX_ZONEORDER=14 CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" CONFIG_EFI=y CONFIG_CPU_FREQ=y @@ -57,10 +54,11 @@ CONFIG_PM_DEBUG=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODVERSIONS=y -CONFIG_MODULE_COMPRESS=y CONFIG_MODULE_COMPRESS_XZ=y # CONFIG_MQ_IOSCHED_KYBER is not set CONFIG_BINFMT_MISC=y +# CONFIG_SLAB_MERGE_DEFAULT is not set +# CONFIG_COMPAT_BRK is not set CONFIG_NET=y CONFIG_PACKET=y CONFIG_PACKET_DIAG=m @@ -137,7 +135,6 @@ CONFIG_NETWORK_SECMARK=y CONFIG_NETFILTER=y CONFIG_BRIDGE_NETFILTER=m CONFIG_NF_CONNTRACK=m -CONFIG_NF_LOG_NETDEV=m CONFIG_NF_CONNTRACK_SECMARK=y CONFIG_NF_CONNTRACK_ZONES=y CONFIG_NF_CONNTRACK_PROCFS=y @@ -164,7 +161,6 @@ CONFIG_NF_TABLES_NETDEV=y CONFIG_NFT_NUMGEN=m CONFIG_NFT_CT=m CONFIG_NFT_FLOW_OFFLOAD=m -CONFIG_NFT_COUNTER=m CONFIG_NFT_CONNLIMIT=m CONFIG_NFT_LOG=m CONFIG_NFT_LIMIT=m @@ -172,7 +168,6 @@ CONFIG_NFT_MASQ=m CONFIG_NFT_REDIR=m CONFIG_NFT_NAT=m CONFIG_NFT_TUNNEL=m -CONFIG_NFT_OBJREF=m CONFIG_NFT_QUEUE=m CONFIG_NFT_QUOTA=m CONFIG_NFT_REJECT=m @@ -294,8 +289,8 @@ CONFIG_IP_VS_PE_SIP=m CONFIG_NFT_DUP_IPV4=m CONFIG_NFT_FIB_IPV4=m CONFIG_NF_TABLES_ARP=y -CONFIG_NF_FLOW_TABLE_IPV4=m CONFIG_NF_LOG_ARP=m +CONFIG_NF_LOG_IPV4=m CONFIG_IP_NF_IPTABLES=m CONFIG_IP_NF_MATCH_AH=m CONFIG_IP_NF_MATCH_ECN=m @@ -309,7 +304,6 @@ CONFIG_IP_NF_TARGET_MASQUERADE=m CONFIG_IP_NF_TARGET_NETMAP=m CONFIG_IP_NF_TARGET_REDIRECT=m CONFIG_IP_NF_MANGLE=m -CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_TARGET_ECN=m CONFIG_IP_NF_TARGET_TTL=m CONFIG_IP_NF_RAW=m @@ -318,7 +312,6 @@ CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m CONFIG_NFT_DUP_IPV6=m CONFIG_NFT_FIB_IPV6=m -CONFIG_NF_FLOW_TABLE_IPV6=m CONFIG_IP6_NF_IPTABLES=m CONFIG_IP6_NF_MATCH_AH=m CONFIG_IP6_NF_MATCH_EUI64=m @@ -342,7 +335,6 @@ CONFIG_IP6_NF_TARGET_NPT=m CONFIG_NF_TABLES_BRIDGE=m CONFIG_NFT_BRIDGE_META=m CONFIG_NFT_BRIDGE_REJECT=m -CONFIG_NF_LOG_BRIDGE=m CONFIG_NF_CONNTRACK_BRIDGE=m CONFIG_BRIDGE_NF_EBTABLES=m CONFIG_BRIDGE_EBT_BROUTE=m @@ -392,23 +384,10 @@ CONFIG_VSOCKETS=m CONFIG_NETLINK_DIAG=m CONFIG_HSR=m CONFIG_CGROUP_NET_PRIO=y -CONFIG_BPF_JIT=y CONFIG_BPF_STREAM_PARSER=y CONFIG_CAN=m CONFIG_CAN_J1939=m CONFIG_CAN_ISOTP=m -CONFIG_CAN_VCAN=m -CONFIG_CAN_VXCAN=m -CONFIG_CAN_SLCAN=m -CONFIG_CAN_FLEXCAN=m -CONFIG_CAN_8DEV_USB=m -CONFIG_CAN_EMS_USB=m -CONFIG_CAN_ESD_USB2=m -CONFIG_CAN_GS_USB=m -CONFIG_CAN_KVASER_USB=m -CONFIG_CAN_MCBA_USB=m -CONFIG_CAN_PEAK_USB=m -CONFIG_CAN_UCAN=m CONFIG_BT=m CONFIG_BT_RFCOMM=m CONFIG_BT_RFCOMM_TTY=y @@ -446,7 +425,7 @@ CONFIG_RFKILL=m CONFIG_FAILOVER=m CONFIG_PCI=y CONFIG_PCI_MSI=y -CONFIG_PCI_IMX6=y +CONFIG_PCI_IMX6_HOST=y CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y # CONFIG_STANDALONE is not set @@ -511,37 +490,46 @@ CONFIG_NET_VRF=m # CONFIG_NET_VENDOR_AMD is not set # CONFIG_NET_VENDOR_AQUANTIA is not set # CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_ASIX is not set # CONFIG_NET_VENDOR_ATHEROS is not set -# CONFIG_NET_VENDOR_AURORA is not set # CONFIG_NET_VENDOR_BROADCOM is not set -# CONFIG_NET_VENDOR_BROCADE is not set # CONFIG_NET_VENDOR_CADENCE is not set # CONFIG_NET_VENDOR_CAVIUM is not set # CONFIG_NET_VENDOR_CHELSIO is not set # CONFIG_NET_VENDOR_CIRRUS is not set # CONFIG_NET_VENDOR_CISCO is not set # CONFIG_NET_VENDOR_CORTINA is not set +# CONFIG_NET_VENDOR_DAVICOM is not set # CONFIG_NET_VENDOR_DEC is not set # CONFIG_NET_VENDOR_DLINK is not set # CONFIG_NET_VENDOR_EMULEX is not set +# CONFIG_NET_VENDOR_ENGLEDER is not set # CONFIG_NET_VENDOR_EZCHIP is not set # CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_FUNGIBLE is not set +# CONFIG_NET_VENDOR_GOOGLE is not set +# CONFIG_NET_VENDOR_HISILICON is not set +# CONFIG_NET_VENDOR_HUAWEI is not set CONFIG_IGB=m +# CONFIG_NET_VENDOR_ADI is not set +# CONFIG_NET_VENDOR_LITEX is not set # CONFIG_NET_VENDOR_MARVELL is not set # CONFIG_NET_VENDOR_MELLANOX is not set # CONFIG_NET_VENDOR_MICREL is not set # CONFIG_NET_VENDOR_MICROCHIP is not set # CONFIG_NET_VENDOR_MICROSEMI is not set +# CONFIG_NET_VENDOR_MICROSOFT is not set # CONFIG_NET_VENDOR_MYRI is not set +# CONFIG_NET_VENDOR_NI is not set # CONFIG_NET_VENDOR_NATSEMI is not set # CONFIG_NET_VENDOR_NETERION is not set # CONFIG_NET_VENDOR_NETRONOME is not set -# CONFIG_NET_VENDOR_NI is not set # CONFIG_NET_VENDOR_NVIDIA is not set # CONFIG_NET_VENDOR_OKI is not set # CONFIG_NET_VENDOR_PACKET_ENGINES is not set # CONFIG_NET_VENDOR_PENSANDO is not set # CONFIG_NET_VENDOR_QLOGIC is not set +# CONFIG_NET_VENDOR_BROCADE is not set # CONFIG_NET_VENDOR_QUALCOMM is not set # CONFIG_NET_VENDOR_RDC is not set # CONFIG_NET_VENDOR_REALTEK is not set @@ -549,9 +537,9 @@ CONFIG_IGB=m # CONFIG_NET_VENDOR_ROCKER is not set # CONFIG_NET_VENDOR_SAMSUNG is not set # CONFIG_NET_VENDOR_SEEQ is not set -# CONFIG_NET_VENDOR_SOLARFLARE is not set # CONFIG_NET_VENDOR_SILAN is not set # CONFIG_NET_VENDOR_SIS is not set +# CONFIG_NET_VENDOR_SOLARFLARE is not set # CONFIG_NET_VENDOR_SMSC is not set # CONFIG_NET_VENDOR_SOCIONEXT is not set # CONFIG_NET_VENDOR_STMICRO is not set @@ -559,12 +547,27 @@ CONFIG_IGB=m # CONFIG_NET_VENDOR_SYNOPSYS is not set # CONFIG_NET_VENDOR_TEHUTI is not set # CONFIG_NET_VENDOR_TI is not set +# CONFIG_NET_VENDOR_VERTEXCOM is not set # CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WANGXUN is not set # CONFIG_NET_VENDOR_WIZNET is not set # CONFIG_NET_VENDOR_XILINX is not set +CONFIG_AX88796B_PHY=y CONFIG_MICREL_PHY=y CONFIG_MICROCHIP_PHY=y CONFIG_SMSC_PHY=y +CONFIG_CAN_VCAN=m +CONFIG_CAN_VXCAN=m +CONFIG_CAN_FLEXCAN=m +CONFIG_CAN_SLCAN=m +CONFIG_CAN_8DEV_USB=m +CONFIG_CAN_EMS_USB=m +CONFIG_CAN_ESD_USB=m +CONFIG_CAN_GS_USB=m +CONFIG_CAN_KVASER_USB=m +CONFIG_CAN_MCBA_USB=m +CONFIG_CAN_PEAK_USB=m +CONFIG_CAN_UCAN=m CONFIG_PPP=m CONFIG_PPP_BSDCOMP=m CONFIG_PPP_DEFLATE=m @@ -670,11 +673,9 @@ CONFIG_RSI_91X=m # CONFIG_WLAN_VENDOR_ST is not set CONFIG_WL12XX=m CONFIG_WLCORE_SDIO=m -# CONFIG_WILINK_PLATFORM_DATA is not set CONFIG_USB_ZD1201=m CONFIG_ZD1211RW=m CONFIG_QTNFMAC_PCIE=m -# CONFIG_INPUT_LEDS is not set CONFIG_INPUT_MOUSEDEV=m CONFIG_INPUT_EVDEV=y # CONFIG_KEYBOARD_ATKBD is not set @@ -691,7 +692,6 @@ CONFIG_SERIAL_IMX_CONSOLE=y CONFIG_SERIAL_FSL_LPUART=y CONFIG_SERIAL_FSL_LPUART_CONSOLE=y CONFIG_SERIAL_DEV_BUS=y -# CONFIG_RANDOM_TRUST_BOOTLOADER is not set # CONFIG_I2C_COMPAT is not set CONFIG_I2C_CHARDEV=y CONFIG_I2C_MUX=y @@ -706,12 +706,7 @@ CONFIG_SPI_GPIO=y CONFIG_SPI_IMX=y CONFIG_SPI_SPIDEV=y CONFIG_PPS_CLIENT_GPIO=m -CONFIG_PTP_1588_CLOCK=m -CONFIG_PINCTRL_IMX8MM=y -CONFIG_PINCTRL_IMX8MN=y -CONFIG_PINCTRL_IMX8MP=y -CONFIG_PINCTRL_IMX8MQ=y -CONFIG_GPIO_SYSFS=y +CONFIG_PTP_1588_CLOCK_KVM=m CONFIG_GPIO_MXC=y CONFIG_GPIO_TS4900=y CONFIG_POWER_RESET=y @@ -730,9 +725,8 @@ CONFIG_REGULATOR_ANATOP=y CONFIG_REGULATOR_GPIO=y CONFIG_IMX_IPUV3_CORE=y CONFIG_DRM=y +CONFIG_DRM_FBDEV_EMULATION=y CONFIG_DRM_PANEL_LVDS=y -CONFIG_DRM_PANEL_SIMPLE=y -CONFIG_DRM_PANEL_SEIKO_43WVF1G=y CONFIG_DRM_TI_TFP410=y CONFIG_DRM_DW_HDMI_AHB_AUDIO=m CONFIG_DRM_DW_HDMI_CEC=y @@ -741,10 +735,11 @@ CONFIG_DRM_IMX_PARALLEL_DISPLAY=y CONFIG_DRM_IMX_LDB=y CONFIG_DRM_IMX_HDMI=y CONFIG_DRM_ETNAVIV=y -CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_DEVICE=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_L4F00242T03=y CONFIG_LCD_PLATFORM=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BACKLIGHT_PWM=y CONFIG_BACKLIGHT_GPIO=y CONFIG_SOUND=m @@ -763,7 +758,6 @@ CONFIG_SND_SOC_IMX_SPDIF=m CONFIG_SND_SOC_FSL_ASOC_CARD=m CONFIG_SND_SIMPLE_CARD=m # CONFIG_HID_A4TECH is not set -# CONFIG_HID_APPLE is not set # CONFIG_HID_BELKIN is not set # CONFIG_HID_CHERRY is not set # CONFIG_HID_CHICONY is not set @@ -771,7 +765,6 @@ CONFIG_SND_SIMPLE_CARD=m # CONFIG_HID_EZKEY is not set # CONFIG_HID_ITE is not set # CONFIG_HID_KENSINGTON is not set -# CONFIG_HID_LOGITECH is not set # CONFIG_HID_REDRAGON is not set # CONFIG_HID_MICROSOFT is not set # CONFIG_HID_MONTEREY is not set @@ -781,7 +774,6 @@ CONFIG_USB=y # CONFIG_USB_PCI is not set CONFIG_USB_ANNOUNCE_NEW_DEVICES=y CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_MXC=y CONFIG_USB_ACM=m CONFIG_USB_STORAGE=y CONFIG_USB_CHIPIDEA=y @@ -830,7 +822,6 @@ CONFIG_USB_SERIAL_SIERRAWIRELESS=m CONFIG_USB_SERIAL_SYMBOL=m CONFIG_USB_SERIAL_TI=m CONFIG_USB_SERIAL_CYBERJACK=m -CONFIG_USB_SERIAL_XIRCOM=m CONFIG_USB_SERIAL_OPTION=m CONFIG_USB_SERIAL_OMNINET=m CONFIG_USB_SERIAL_OPTICON=m @@ -842,7 +833,6 @@ CONFIG_USB_SERIAL_UPD78F0730=m CONFIG_NOP_USB_XCEIV=y CONFIG_USB_MXS_PHY=y CONFIG_USB_GADGET=y -CONFIG_USB_FSL_USB2=y CONFIG_USB_CONFIGFS=m CONFIG_USB_ETH=m CONFIG_USB_G_NCM=m @@ -853,18 +843,16 @@ CONFIG_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_ESDHC_IMX=y +CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y CONFIG_LEDS_GPIO=y -CONFIG_LEDS_PWM=y CONFIG_LEDS_TRIGGER_TIMER=y -CONFIG_LEDS_TRIGGER_ONESHOT=m +CONFIG_LEDS_TRIGGER_ONESHOT=y CONFIG_LEDS_TRIGGER_DISK=y -CONFIG_LEDS_TRIGGER_MTD=y -CONFIG_LEDS_TRIGGER_HEARTBEAT=m +CONFIG_LEDS_TRIGGER_HEARTBEAT=y CONFIG_LEDS_TRIGGER_BACKLIGHT=y CONFIG_LEDS_TRIGGER_CPU=y CONFIG_LEDS_TRIGGER_ACTIVITY=m -CONFIG_LEDS_TRIGGER_GPIO=m CONFIG_LEDS_TRIGGER_DEFAULT_ON=y CONFIG_LEDS_TRIGGER_TRANSIENT=m CONFIG_LEDS_TRIGGER_PANIC=y @@ -910,8 +898,7 @@ CONFIG_F2FS_FS=y CONFIG_F2FS_FS_SECURITY=y CONFIG_QUOTA=y CONFIG_QUOTA_NETLINK_INTERFACE=y -# CONFIG_PRINT_QUOTA_WARNING is not set -CONFIG_AUTOFS4_FS=y +CONFIG_AUTOFS_FS=m CONFIG_OVERLAY_FS=m CONFIG_VFAT_FS=y CONFIG_EXFAT_FS=y @@ -941,12 +928,7 @@ CONFIG_CRYPTO_DEV_MXS_DCP=y CONFIG_CRC_T10DIF=y CONFIG_CRC7=m CONFIG_CMA_SIZE_MBYTES=64 -CONFIG_FONTS=y -CONFIG_FONT_8x8=y -CONFIG_FONT_8x16=y CONFIG_PRINTK_TIME=y # CONFIG_SYMBOLIC_ERRNAME is not set -# CONFIG_ENABLE_MUST_CHECK is not set CONFIG_DEBUG_FS=y -CONFIG_STACKTRACE=y # CONFIG_RUNTIME_TESTING_MENU is not set From 7f9f0e4134b426a4e72554ff6e5eefbbf403027e Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Thu, 23 May 2024 23:15:20 +0000 Subject: [PATCH 147/244] ARM: configs: tsimx6ul: updates for 6.6 Signed-off-by: Kris Bahnsen --- arch/arm/configs/tsimx6ul_defconfig | 80 ++++++++++++----------------- 1 file changed, 33 insertions(+), 47 deletions(-) diff --git a/arch/arm/configs/tsimx6ul_defconfig b/arch/arm/configs/tsimx6ul_defconfig index fb4aea96e3ea2..956896ab6048f 100644 --- a/arch/arm/configs/tsimx6ul_defconfig +++ b/arch/arm/configs/tsimx6ul_defconfig @@ -4,6 +4,8 @@ CONFIG_POSIX_MQUEUE=y # CONFIG_CROSS_MEMORY_ATTACH is not set CONFIG_NO_HZ_IDLE=y CONFIG_HIGH_RES_TIMERS=y +CONFIG_BPF_SYSCALL=y +CONFIG_BPF_JIT=y CONFIG_PREEMPT=y CONFIG_PSI=y CONFIG_LOG_BUF_SHIFT=18 @@ -22,10 +24,6 @@ CONFIG_USER_NS=y CONFIG_CHECKPOINT_RESTORE=y CONFIG_BLK_DEV_INITRD=y CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_BPF_SYSCALL=y -# CONFIG_COMPAT_BRK is not set -CONFIG_SLAB=y -# CONFIG_SLAB_MERGE_DEFAULT is not set CONFIG_ARCH_MXC=y CONFIG_SOC_IMX6UL=y CONFIG_ARM_ERRATA_754322=y @@ -34,7 +32,6 @@ CONFIG_HAVE_ARM_ARCH_TIMER=y CONFIG_ARM_PSCI=y CONFIG_HZ_1000=y CONFIG_HIGHMEM=y -CONFIG_FORCE_MAX_ZONEORDER=14 CONFIG_CMDLINE="fbcon=map:31" CONFIG_CMDLINE_EXTEND=y CONFIG_EFI=y @@ -57,10 +54,11 @@ CONFIG_PM_DEBUG=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODVERSIONS=y -CONFIG_MODULE_COMPRESS=y CONFIG_MODULE_COMPRESS_XZ=y # CONFIG_MQ_IOSCHED_KYBER is not set CONFIG_BINFMT_MISC=y +# CONFIG_SLAB_MERGE_DEFAULT is not set +# CONFIG_COMPAT_BRK is not set CONFIG_CMA=y CONFIG_NET=y CONFIG_PACKET=y @@ -140,7 +138,6 @@ CONFIG_NETWORK_SECMARK=y CONFIG_NETFILTER=y CONFIG_BRIDGE_NETFILTER=m CONFIG_NF_CONNTRACK=m -CONFIG_NF_LOG_NETDEV=m CONFIG_NF_CONNTRACK_SECMARK=y CONFIG_NF_CONNTRACK_ZONES=y CONFIG_NF_CONNTRACK_PROCFS=y @@ -167,7 +164,6 @@ CONFIG_NF_TABLES_NETDEV=y CONFIG_NFT_NUMGEN=m CONFIG_NFT_CT=m CONFIG_NFT_FLOW_OFFLOAD=m -CONFIG_NFT_COUNTER=m CONFIG_NFT_CONNLIMIT=m CONFIG_NFT_LOG=m CONFIG_NFT_LIMIT=m @@ -175,7 +171,6 @@ CONFIG_NFT_MASQ=m CONFIG_NFT_REDIR=m CONFIG_NFT_NAT=m CONFIG_NFT_TUNNEL=m -CONFIG_NFT_OBJREF=m CONFIG_NFT_QUEUE=m CONFIG_NFT_QUOTA=m CONFIG_NFT_REJECT=m @@ -297,8 +292,8 @@ CONFIG_IP_VS_PE_SIP=m CONFIG_NFT_DUP_IPV4=m CONFIG_NFT_FIB_IPV4=m CONFIG_NF_TABLES_ARP=y -CONFIG_NF_FLOW_TABLE_IPV4=m CONFIG_NF_LOG_ARP=m +CONFIG_NF_LOG_IPV4=m CONFIG_IP_NF_IPTABLES=m CONFIG_IP_NF_MATCH_AH=m CONFIG_IP_NF_MATCH_ECN=m @@ -312,7 +307,6 @@ CONFIG_IP_NF_TARGET_MASQUERADE=m CONFIG_IP_NF_TARGET_NETMAP=m CONFIG_IP_NF_TARGET_REDIRECT=m CONFIG_IP_NF_MANGLE=m -CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_TARGET_ECN=m CONFIG_IP_NF_TARGET_TTL=m CONFIG_IP_NF_RAW=m @@ -321,7 +315,6 @@ CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m CONFIG_NFT_DUP_IPV6=m CONFIG_NFT_FIB_IPV6=m -CONFIG_NF_FLOW_TABLE_IPV6=m CONFIG_IP6_NF_IPTABLES=m CONFIG_IP6_NF_MATCH_AH=m CONFIG_IP6_NF_MATCH_EUI64=m @@ -345,7 +338,6 @@ CONFIG_IP6_NF_TARGET_NPT=m CONFIG_NF_TABLES_BRIDGE=m CONFIG_NFT_BRIDGE_META=m CONFIG_NFT_BRIDGE_REJECT=m -CONFIG_NF_LOG_BRIDGE=m CONFIG_NF_CONNTRACK_BRIDGE=m CONFIG_BRIDGE_NF_EBTABLES=m CONFIG_BRIDGE_EBT_BROUTE=m @@ -399,29 +391,15 @@ CONFIG_DNS_RESOLVER=y CONFIG_BATMAN_ADV=m CONFIG_BATMAN_ADV_NC=y CONFIG_BATMAN_ADV_DEBUG=y -CONFIG_BATMAN_ADV_SYSFS=y CONFIG_OPENVSWITCH=m CONFIG_VSOCKETS=m CONFIG_NETLINK_DIAG=m CONFIG_HSR=m CONFIG_CGROUP_NET_PRIO=y -CONFIG_BPF_JIT=y CONFIG_BPF_STREAM_PARSER=y CONFIG_CAN=m CONFIG_CAN_J1939=m CONFIG_CAN_ISOTP=m -CONFIG_CAN_VCAN=m -CONFIG_CAN_VXCAN=m -CONFIG_CAN_SLCAN=m -CONFIG_CAN_FLEXCAN=m -CONFIG_CAN_8DEV_USB=m -CONFIG_CAN_EMS_USB=m -CONFIG_CAN_ESD_USB2=m -CONFIG_CAN_GS_USB=m -CONFIG_CAN_KVASER_USB=m -CONFIG_CAN_MCBA_USB=m -CONFIG_CAN_PEAK_USB=m -CONFIG_CAN_UCAN=m CONFIG_BT=m CONFIG_BT_RFCOMM=m CONFIG_BT_RFCOMM_TTY=y @@ -516,26 +494,32 @@ CONFIG_NET_VRF=m # CONFIG_NET_VENDOR_AMAZON is not set # CONFIG_NET_VENDOR_AQUANTIA is not set # CONFIG_NET_VENDOR_ARC is not set -# CONFIG_NET_VENDOR_AURORA is not set +# CONFIG_NET_VENDOR_ASIX is not set # CONFIG_NET_VENDOR_BROADCOM is not set # CONFIG_NET_VENDOR_CADENCE is not set # CONFIG_NET_VENDOR_CAVIUM is not set # CONFIG_NET_VENDOR_CIRRUS is not set # CONFIG_NET_VENDOR_CORTINA is not set +# CONFIG_NET_VENDOR_DAVICOM is not set +# CONFIG_NET_VENDOR_ENGLEDER is not set # CONFIG_NET_VENDOR_EZCHIP is not set # CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_FUNGIBLE is not set # CONFIG_NET_VENDOR_GOOGLE is not set # CONFIG_NET_VENDOR_HISILICON is not set # CONFIG_NET_VENDOR_HUAWEI is not set # CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_ADI is not set +# CONFIG_NET_VENDOR_LITEX is not set # CONFIG_NET_VENDOR_MARVELL is not set # CONFIG_NET_VENDOR_MELLANOX is not set # CONFIG_NET_VENDOR_MICREL is not set # CONFIG_NET_VENDOR_MICROCHIP is not set # CONFIG_NET_VENDOR_MICROSEMI is not set +# CONFIG_NET_VENDOR_MICROSOFT is not set +# CONFIG_NET_VENDOR_NI is not set # CONFIG_NET_VENDOR_NATSEMI is not set # CONFIG_NET_VENDOR_NETRONOME is not set -# CONFIG_NET_VENDOR_NI is not set # CONFIG_NET_VENDOR_PENSANDO is not set # CONFIG_NET_VENDOR_QUALCOMM is not set # CONFIG_NET_VENDOR_RENESAS is not set @@ -547,12 +531,27 @@ CONFIG_NET_VRF=m # CONFIG_NET_VENDOR_SOCIONEXT is not set # CONFIG_NET_VENDOR_STMICRO is not set # CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_VERTEXCOM is not set # CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WANGXUN is not set # CONFIG_NET_VENDOR_WIZNET is not set # CONFIG_NET_VENDOR_XILINX is not set +CONFIG_AX88796B_PHY=y CONFIG_MICREL_PHY=y CONFIG_MICROCHIP_PHY=y CONFIG_SMSC_PHY=y +CONFIG_CAN_VCAN=m +CONFIG_CAN_VXCAN=m +CONFIG_CAN_FLEXCAN=m +CONFIG_CAN_SLCAN=m +CONFIG_CAN_8DEV_USB=m +CONFIG_CAN_EMS_USB=m +CONFIG_CAN_ESD_USB=m +CONFIG_CAN_GS_USB=m +CONFIG_CAN_KVASER_USB=m +CONFIG_CAN_MCBA_USB=m +CONFIG_CAN_PEAK_USB=m +CONFIG_CAN_UCAN=m CONFIG_PPP=m CONFIG_PPP_BSDCOMP=m CONFIG_PPP_DEFLATE=m @@ -638,7 +637,6 @@ CONFIG_RSI_91X=m # CONFIG_WLAN_VENDOR_ST is not set CONFIG_WL12XX=m CONFIG_WLCORE_SDIO=m -# CONFIG_WILINK_PLATFORM_DATA is not set CONFIG_USB_ZD1201=m CONFIG_ZD1211RW=m # CONFIG_WLAN_VENDOR_QUANTENNA is not set @@ -662,7 +660,6 @@ CONFIG_SERIAL_OF_PLATFORM=m CONFIG_SERIAL_IMX=y CONFIG_SERIAL_IMX_CONSOLE=y CONFIG_SERIAL_DEV_BUS=y -# CONFIG_RANDOM_TRUST_BOOTLOADER is not set # CONFIG_I2C_COMPAT is not set CONFIG_I2C_CHARDEV=y CONFIG_I2C_MUX=y @@ -679,8 +676,7 @@ CONFIG_SPI_OCORES=m CONFIG_SPI_SPIDEV=y CONFIG_PPS_CLIENT_LDISC=m CONFIG_PPS_CLIENT_GPIO=m -CONFIG_PTP_1588_CLOCK=m -CONFIG_GPIO_SYSFS=y +CONFIG_PTP_1588_CLOCK_KVM=m CONFIG_GPIO_MXC=y CONFIG_GPIO_TS71XXWEIM=y CONFIG_GPIO_PCA953X=m @@ -703,16 +699,12 @@ CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_ANATOP=y CONFIG_REGULATOR_GPIO=y -CONFIG_IMX_IPUV3_CORE=y CONFIG_DRM=y +CONFIG_DRM_FBDEV_EMULATION=y CONFIG_DRM_PANEL_LVDS=y CONFIG_DRM_PANEL_SIMPLE=y -CONFIG_DRM_IMX=y -CONFIG_DRM_IMX_PARALLEL_DISPLAY=y CONFIG_DRM_MXSFB=y -CONFIG_FB_MODE_HELPERS=y -# CONFIG_FB_MX3 is not set -CONFIG_FB_ST7565P=m +CONFIG_FB_DEVICE=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_PLATFORM=y CONFIG_BACKLIGHT_CLASS_DEVICE=y @@ -744,7 +736,7 @@ CONFIG_USB_ANNOUNCE_NEW_DEVICES=y CONFIG_USB_OTG=y CONFIG_USB_OTG_FSM=m CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_MXC=y +CONFIG_USB_EHCI_FSL=y CONFIG_USB_STORAGE=y CONFIG_USB_CHIPIDEA=y CONFIG_USB_CHIPIDEA_UDC=y @@ -792,7 +784,6 @@ CONFIG_USB_SERIAL_SIERRAWIRELESS=m CONFIG_USB_SERIAL_SYMBOL=m CONFIG_USB_SERIAL_TI=m CONFIG_USB_SERIAL_CYBERJACK=m -CONFIG_USB_SERIAL_XIRCOM=m CONFIG_USB_SERIAL_OPTION=m CONFIG_USB_SERIAL_OMNINET=m CONFIG_USB_SERIAL_OPTICON=m @@ -804,7 +795,6 @@ CONFIG_USB_SERIAL_UPD78F0730=m CONFIG_NOP_USB_XCEIV=y CONFIG_USB_MXS_PHY=y CONFIG_USB_GADGET=y -CONFIG_USB_FSL_USB2=y CONFIG_USB_CONFIGFS=m CONFIG_USB_ETH=m CONFIG_USB_G_NCM=m @@ -825,7 +815,6 @@ CONFIG_LEDS_TRIGGER_HEARTBEAT=m CONFIG_LEDS_TRIGGER_BACKLIGHT=y CONFIG_LEDS_TRIGGER_CPU=y CONFIG_LEDS_TRIGGER_ACTIVITY=m -CONFIG_LEDS_TRIGGER_GPIO=m CONFIG_LEDS_TRIGGER_DEFAULT_ON=y CONFIG_LEDS_TRIGGER_TRANSIENT=m CONFIG_LEDS_TRIGGER_PANIC=y @@ -874,8 +863,7 @@ CONFIG_F2FS_FS=y CONFIG_F2FS_FS_SECURITY=y CONFIG_QUOTA=y CONFIG_QUOTA_NETLINK_INTERFACE=y -# CONFIG_PRINT_QUOTA_WARNING is not set -CONFIG_AUTOFS4_FS=m +CONFIG_AUTOFS_FS=m CONFIG_FUSE_FS=m CONFIG_OVERLAY_FS=m CONFIG_VFAT_FS=y @@ -909,7 +897,5 @@ CONFIG_DMA_CMA=y CONFIG_CMA_SIZE_MBYTES=64 CONFIG_PRINTK_TIME=y # CONFIG_SYMBOLIC_ERRNAME is not set -# CONFIG_ENABLE_MUST_CHECK is not set CONFIG_DEBUG_FS=y -CONFIG_STACKTRACE=y # CONFIG_RUNTIME_TESTING_MENU is not set From 7fce7b2e9122d9849b75e7b5d2045319a2c1f0fb Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Thu, 23 May 2024 23:21:43 +0000 Subject: [PATCH 148/244] ARM: configs: tsimx28: updates for 6.6 Signed-off-by: Kris Bahnsen --- arch/arm/configs/tsimx28_defconfig | 55 +++++++++++------------------- 1 file changed, 19 insertions(+), 36 deletions(-) diff --git a/arch/arm/configs/tsimx28_defconfig b/arch/arm/configs/tsimx28_defconfig index 3bbff5ef2ad7d..51739f09a9d9f 100644 --- a/arch/arm/configs/tsimx28_defconfig +++ b/arch/arm/configs/tsimx28_defconfig @@ -3,6 +3,8 @@ CONFIG_POSIX_MQUEUE=y # CONFIG_CROSS_MEMORY_ATTACH is not set CONFIG_NO_HZ_IDLE=y CONFIG_HIGH_RES_TIMERS=y +CONFIG_BPF_SYSCALL=y +CONFIG_BPF_JIT=y CONFIG_PREEMPT=y CONFIG_TASKSTATS=y CONFIG_TASK_DELAY_ACCT=y @@ -23,11 +25,7 @@ CONFIG_CHECKPOINT_RESTORE=y CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y # CONFIG_RD_ZSTD is not set -CONFIG_BPF_SYSCALL=y CONFIG_PERF_EVENTS=y -# CONFIG_COMPAT_BRK is not set -CONFIG_SLAB=y -# CONFIG_SLAB_MERGE_DEFAULT is not set # CONFIG_ARCH_MULTI_V7 is not set CONFIG_ARCH_MXS=y CONFIG_HZ_1000=y @@ -39,12 +37,11 @@ CONFIG_MODULE_FORCE_LOAD=y CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y CONFIG_MODVERSIONS=y -CONFIG_MODULE_COMPRESS=y CONFIG_MODULE_COMPRESS_XZ=y -CONFIG_UNUSED_SYMBOLS=y CONFIG_BLK_DEV_INTEGRITY=y CONFIG_BINFMT_MISC=y -CONFIG_CLEANCACHE=y +# CONFIG_SLAB_MERGE_DEFAULT is not set +# CONFIG_COMPAT_BRK is not set CONFIG_NET=y CONFIG_PACKET=y CONFIG_PACKET_DIAG=m @@ -121,7 +118,6 @@ CONFIG_NETWORK_SECMARK=y CONFIG_NETFILTER=y CONFIG_BRIDGE_NETFILTER=m CONFIG_NF_CONNTRACK=m -CONFIG_NF_LOG_NETDEV=m CONFIG_NF_CONNTRACK_SECMARK=y CONFIG_NF_CONNTRACK_ZONES=y CONFIG_NF_CONNTRACK_PROCFS=y @@ -148,7 +144,6 @@ CONFIG_NF_TABLES_NETDEV=y CONFIG_NFT_NUMGEN=m CONFIG_NFT_CT=m CONFIG_NFT_FLOW_OFFLOAD=m -CONFIG_NFT_COUNTER=m CONFIG_NFT_CONNLIMIT=m CONFIG_NFT_LOG=m CONFIG_NFT_LIMIT=m @@ -156,7 +151,6 @@ CONFIG_NFT_MASQ=m CONFIG_NFT_REDIR=m CONFIG_NFT_NAT=m CONFIG_NFT_TUNNEL=m -CONFIG_NFT_OBJREF=m CONFIG_NFT_QUEUE=m CONFIG_NFT_QUOTA=m CONFIG_NFT_REJECT=m @@ -278,8 +272,8 @@ CONFIG_IP_VS_PE_SIP=m CONFIG_NFT_DUP_IPV4=m CONFIG_NFT_FIB_IPV4=m CONFIG_NF_TABLES_ARP=y -CONFIG_NF_FLOW_TABLE_IPV4=m CONFIG_NF_LOG_ARP=m +CONFIG_NF_LOG_IPV4=m CONFIG_IP_NF_IPTABLES=m CONFIG_IP_NF_MATCH_AH=m CONFIG_IP_NF_MATCH_ECN=m @@ -293,7 +287,6 @@ CONFIG_IP_NF_TARGET_MASQUERADE=m CONFIG_IP_NF_TARGET_NETMAP=m CONFIG_IP_NF_TARGET_REDIRECT=m CONFIG_IP_NF_MANGLE=m -CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_TARGET_ECN=m CONFIG_IP_NF_TARGET_TTL=m CONFIG_IP_NF_RAW=m @@ -302,7 +295,6 @@ CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m CONFIG_NFT_DUP_IPV6=m CONFIG_NFT_FIB_IPV6=m -CONFIG_NF_FLOW_TABLE_IPV6=m CONFIG_IP6_NF_IPTABLES=m CONFIG_IP6_NF_MATCH_AH=m CONFIG_IP6_NF_MATCH_EUI64=m @@ -326,7 +318,6 @@ CONFIG_IP6_NF_TARGET_NPT=m CONFIG_NF_TABLES_BRIDGE=m CONFIG_NFT_BRIDGE_META=m CONFIG_NFT_BRIDGE_REJECT=m -CONFIG_NF_LOG_BRIDGE=m CONFIG_NF_CONNTRACK_BRIDGE=m CONFIG_BRIDGE_NF_EBTABLES=m CONFIG_BRIDGE_EBT_BROUTE=m @@ -376,23 +367,10 @@ CONFIG_VSOCKETS=m CONFIG_NETLINK_DIAG=m CONFIG_HSR=m CONFIG_CGROUP_NET_PRIO=y -CONFIG_BPF_JIT=y CONFIG_BPF_STREAM_PARSER=y CONFIG_CAN=m CONFIG_CAN_J1939=m CONFIG_CAN_ISOTP=m -CONFIG_CAN_VCAN=m -CONFIG_CAN_VXCAN=m -CONFIG_CAN_SLCAN=m -CONFIG_CAN_FLEXCAN=m -CONFIG_CAN_8DEV_USB=m -CONFIG_CAN_EMS_USB=m -CONFIG_CAN_ESD_USB2=m -CONFIG_CAN_GS_USB=m -CONFIG_CAN_KVASER_USB=m -CONFIG_CAN_MCBA_USB=m -CONFIG_CAN_PEAK_USB=m -CONFIG_CAN_UCAN=m CONFIG_BT=m CONFIG_BT_RFCOMM=m CONFIG_BT_RFCOMM_TTY=y @@ -434,7 +412,6 @@ CONFIG_DEVTMPFS_MOUNT=y CONFIG_GNSS=y CONFIG_GNSS_NMEA_SERIAL=y CONFIG_BLK_DEV_LOOP=m -CONFIG_BLK_DEV_CRYPTOLOOP=m CONFIG_BLK_DEV_NBD=m CONFIG_BLK_DEV_RAM=m CONFIG_EEPROM_AT24=m @@ -473,7 +450,6 @@ CONFIG_NET_VRF=m # CONFIG_NET_VENDOR_AMAZON is not set # CONFIG_NET_VENDOR_AQUANTIA is not set # CONFIG_NET_VENDOR_ARC is not set -# CONFIG_NET_VENDOR_AURORA is not set # CONFIG_NET_VENDOR_BROADCOM is not set # CONFIG_NET_VENDOR_CADENCE is not set # CONFIG_NET_VENDOR_CAVIUM is not set @@ -490,9 +466,9 @@ CONFIG_NET_VRF=m # CONFIG_NET_VENDOR_MICREL is not set # CONFIG_NET_VENDOR_MICROCHIP is not set # CONFIG_NET_VENDOR_MICROSEMI is not set +# CONFIG_NET_VENDOR_NI is not set # CONFIG_NET_VENDOR_NATSEMI is not set # CONFIG_NET_VENDOR_NETRONOME is not set -# CONFIG_NET_VENDOR_NI is not set # CONFIG_NET_VENDOR_PENSANDO is not set # CONFIG_NET_VENDOR_QUALCOMM is not set # CONFIG_NET_VENDOR_RENESAS is not set @@ -508,7 +484,18 @@ CONFIG_NET_VRF=m # CONFIG_NET_VENDOR_WIZNET is not set # CONFIG_NET_VENDOR_XILINX is not set CONFIG_MICROCHIP_PHY=m -CONFIG_SMSC_PHY=y +CONFIG_CAN_VCAN=m +CONFIG_CAN_VXCAN=m +CONFIG_CAN_FLEXCAN=m +CONFIG_CAN_SLCAN=m +CONFIG_CAN_8DEV_USB=m +CONFIG_CAN_EMS_USB=m +CONFIG_CAN_ESD_USB=m +CONFIG_CAN_GS_USB=m +CONFIG_CAN_KVASER_USB=m +CONFIG_CAN_MCBA_USB=m +CONFIG_CAN_PEAK_USB=m +CONFIG_CAN_UCAN=m CONFIG_PPP=m CONFIG_PPP_BSDCOMP=m CONFIG_PPP_DEFLATE=m @@ -599,7 +586,6 @@ CONFIG_SPI_MXS=y CONFIG_SPI_SPIDEV=y CONFIG_PPS_CLIENT_GPIO=m CONFIG_PTP_1588_CLOCK=m -CONFIG_GPIO_SYSFS=y CONFIG_WATCHDOG=y CONFIG_TS_WDT_MICRO=y CONFIG_MFD_MXS_LRADC=m @@ -677,7 +663,6 @@ CONFIG_USB_SERIAL_SIERRAWIRELESS=m CONFIG_USB_SERIAL_SYMBOL=m CONFIG_USB_SERIAL_TI=m CONFIG_USB_SERIAL_CYBERJACK=m -CONFIG_USB_SERIAL_XIRCOM=m CONFIG_USB_SERIAL_OPTION=m CONFIG_USB_SERIAL_OMNINET=m CONFIG_USB_SERIAL_OPTICON=m @@ -728,7 +713,6 @@ CONFIG_LEDS_TRIGGER_HEARTBEAT=y CONFIG_LEDS_TRIGGER_BACKLIGHT=y CONFIG_LEDS_TRIGGER_CPU=y CONFIG_LEDS_TRIGGER_ACTIVITY=m -CONFIG_LEDS_TRIGGER_GPIO=y CONFIG_LEDS_TRIGGER_DEFAULT_ON=y CONFIG_LEDS_TRIGGER_TRANSIENT=m CONFIG_LEDS_TRIGGER_PANIC=y @@ -759,7 +743,7 @@ CONFIG_F2FS_FS=y CONFIG_F2FS_FS_SECURITY=y # CONFIG_DNOTIFY is not set CONFIG_FANOTIFY=y -CONFIG_AUTOFS4_FS=y +CONFIG_AUTOFS_FS=m CONFIG_OVERLAY_FS=m CONFIG_VFAT_FS=y CONFIG_EXFAT_FS=y @@ -784,6 +768,5 @@ CONFIG_CRC7=m CONFIG_PRINTK_TIME=y CONFIG_FRAME_WARN=2048 CONFIG_DEBUG_FS=y -CONFIG_STACKTRACE=y CONFIG_DEBUG_USER=y # CONFIG_RUNTIME_TESTING_MENU is not set From da7c09a5f9fcac0cac276961907520d9528550fd Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Thu, 23 May 2024 23:40:32 +0000 Subject: [PATCH 149/244] ARM: configs: tsimx28_minimal: updates for 6.6 Signed-off-by: Kris Bahnsen --- arch/arm/configs/tsimx28_minimal_defconfig | 19 +++++-------------- 1 file changed, 5 insertions(+), 14 deletions(-) diff --git a/arch/arm/configs/tsimx28_minimal_defconfig b/arch/arm/configs/tsimx28_minimal_defconfig index e30d95b07f1d9..55262f141a176 100644 --- a/arch/arm/configs/tsimx28_minimal_defconfig +++ b/arch/arm/configs/tsimx28_minimal_defconfig @@ -1,4 +1,3 @@ -# CONFIG_SWAP is not set CONFIG_SYSVIPC=y # CONFIG_CROSS_MEMORY_ATTACH is not set CONFIG_NO_HZ_IDLE=y @@ -15,9 +14,6 @@ CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y # CONFIG_RD_ZSTD is not set CONFIG_PERF_EVENTS=y -# CONFIG_COMPAT_BRK is not set -CONFIG_SLAB=y -# CONFIG_SLAB_MERGE_DEFAULT is not set # CONFIG_ARCH_MULTI_V7 is not set CONFIG_ARCH_MXS=y CONFIG_HZ_1000=y @@ -27,12 +23,12 @@ CONFIG_MODULES=y CONFIG_MODULE_FORCE_LOAD=y CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_MODULE_COMPRESS=y CONFIG_MODULE_COMPRESS_XZ=y -CONFIG_UNUSED_SYMBOLS=y CONFIG_BLK_DEV_INTEGRITY=y CONFIG_BINFMT_MISC=y -CONFIG_CLEANCACHE=y +# CONFIG_SWAP is not set +# CONFIG_SLAB_MERGE_DEFAULT is not set +# CONFIG_COMPAT_BRK is not set CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y @@ -48,7 +44,6 @@ CONFIG_IPV6=m CONFIG_IPV6_VTI=m CONFIG_DNS_RESOLVER=y CONFIG_CAN=m -CONFIG_CAN_FLEXCAN=m CONFIG_BT=m CONFIG_BT_RFCOMM=m CONFIG_BT_RFCOMM_TTY=y @@ -68,7 +63,6 @@ CONFIG_DEVTMPFS_MOUNT=y CONFIG_GNSS=y CONFIG_GNSS_NMEA_SERIAL=y CONFIG_BLK_DEV_LOOP=m -CONFIG_BLK_DEV_CRYPTOLOOP=m CONFIG_BLK_DEV_NBD=m CONFIG_BLK_DEV_RAM=m CONFIG_EEPROM_AT24=m @@ -82,7 +76,6 @@ CONFIG_NETDEVICES=y # CONFIG_NET_VENDOR_AMAZON is not set # CONFIG_NET_VENDOR_AQUANTIA is not set # CONFIG_NET_VENDOR_ARC is not set -# CONFIG_NET_VENDOR_AURORA is not set # CONFIG_NET_VENDOR_BROADCOM is not set # CONFIG_NET_VENDOR_CADENCE is not set # CONFIG_NET_VENDOR_CAVIUM is not set @@ -99,9 +92,9 @@ CONFIG_NETDEVICES=y # CONFIG_NET_VENDOR_MICREL is not set # CONFIG_NET_VENDOR_MICROCHIP is not set # CONFIG_NET_VENDOR_MICROSEMI is not set +# CONFIG_NET_VENDOR_NI is not set # CONFIG_NET_VENDOR_NATSEMI is not set # CONFIG_NET_VENDOR_NETRONOME is not set -# CONFIG_NET_VENDOR_NI is not set # CONFIG_NET_VENDOR_PENSANDO is not set # CONFIG_NET_VENDOR_QUALCOMM is not set # CONFIG_NET_VENDOR_RENESAS is not set @@ -118,6 +111,7 @@ CONFIG_NETDEVICES=y # CONFIG_NET_VENDOR_XILINX is not set CONFIG_MICROCHIP_PHY=m CONFIG_SMSC_PHY=y +CONFIG_CAN_FLEXCAN=m CONFIG_USB_USBNET=m # CONFIG_USB_NET_AX8817X is not set # CONFIG_USB_NET_AX88179_178A is not set @@ -166,7 +160,6 @@ CONFIG_SPI_SPIDEV=y CONFIG_PPS=m CONFIG_PPS_CLIENT_GPIO=m # CONFIG_PTP_1588_CLOCK is not set -CONFIG_GPIO_SYSFS=y CONFIG_WATCHDOG=y CONFIG_TS_WDT_MICRO=y CONFIG_MFD_MXS_LRADC=m @@ -249,7 +242,6 @@ CONFIG_LEDS_TRIGGER_ONESHOT=y CONFIG_LEDS_TRIGGER_HEARTBEAT=y CONFIG_LEDS_TRIGGER_BACKLIGHT=y CONFIG_LEDS_TRIGGER_CPU=y -CONFIG_LEDS_TRIGGER_GPIO=y CONFIG_LEDS_TRIGGER_DEFAULT_ON=y CONFIG_LEDS_TRIGGER_PANIC=y CONFIG_RTC_CLASS=y @@ -269,7 +261,6 @@ CONFIG_NVMEM_MXS_OCOTP=m CONFIG_EXT4_FS=y # CONFIG_DNOTIFY is not set CONFIG_FANOTIFY=y -CONFIG_AUTOFS4_FS=y CONFIG_VFAT_FS=y CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y From b91f0d50cd91209f1b2ef9c1d94ca02e62b40556 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Thu, 23 May 2024 23:55:50 +0000 Subject: [PATCH 150/244] ARM: configs: tsimx6ul_minimal: updates for 6.6 Signed-off-by: Kris Bahnsen --- arch/arm/configs/tsimx6ul_minimal_defconfig | 44 +++++++++------------ 1 file changed, 19 insertions(+), 25 deletions(-) diff --git a/arch/arm/configs/tsimx6ul_minimal_defconfig b/arch/arm/configs/tsimx6ul_minimal_defconfig index 65088589a7426..08ea9fbd54978 100644 --- a/arch/arm/configs/tsimx6ul_minimal_defconfig +++ b/arch/arm/configs/tsimx6ul_minimal_defconfig @@ -1,5 +1,4 @@ CONFIG_KERNEL_LZO=y -# CONFIG_SWAP is not set CONFIG_SYSVIPC=y # CONFIG_CROSS_MEMORY_ATTACH is not set CONFIG_NO_HZ_IDLE=y @@ -8,9 +7,6 @@ CONFIG_PREEMPT=y CONFIG_LOG_BUF_SHIFT=18 CONFIG_CGROUPS=y CONFIG_CC_OPTIMIZE_FOR_SIZE=y -# CONFIG_COMPAT_BRK is not set -CONFIG_SLAB=y -# CONFIG_SLAB_MERGE_DEFAULT is not set CONFIG_ARCH_MXC=y CONFIG_SOC_IMX6UL=y CONFIG_ARM_ERRATA_754322=y @@ -19,7 +15,6 @@ CONFIG_HAVE_ARM_ARCH_TIMER=y CONFIG_ARM_PSCI=y CONFIG_HZ_1000=y CONFIG_HIGHMEM=y -CONFIG_FORCE_MAX_ZONEORDER=14 CONFIG_CMDLINE="fbcon=map:31" CONFIG_CMDLINE_EXTEND=y CONFIG_CPU_FREQ=y @@ -41,11 +36,12 @@ CONFIG_PM_DEBUG=y # CONFIG_STACKPROTECTOR is not set CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_COMPRESS=y CONFIG_MODULE_COMPRESS_XZ=y -# CONFIG_BLK_DEV_BSG is not set # CONFIG_MQ_IOSCHED_KYBER is not set CONFIG_BINFMT_MISC=y +# CONFIG_SWAP is not set +# CONFIG_SLAB_MERGE_DEFAULT is not set +# CONFIG_COMPAT_BRK is not set CONFIG_CMA=y CONFIG_NET=y CONFIG_PACKET=y @@ -55,7 +51,6 @@ CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y # CONFIG_IPV6 is not set CONFIG_CAN=m -CONFIG_CAN_FLEXCAN=m CONFIG_BT=m CONFIG_BT_HCIUART=m CONFIG_BT_HCIUART_LL=y @@ -89,6 +84,7 @@ CONFIG_EEPROM_AT25=y CONFIG_SCSI=y # CONFIG_SCSI_PROC_FS is not set CONFIG_BLK_DEV_SD=y +# CONFIG_BLK_DEV_BSG is not set CONFIG_SCSI_CONSTANTS=y CONFIG_SCSI_LOGGING=y CONFIG_SCSI_SCAN_ASYNC=y @@ -98,26 +94,32 @@ CONFIG_NETDEVICES=y # CONFIG_NET_VENDOR_AMAZON is not set # CONFIG_NET_VENDOR_AQUANTIA is not set # CONFIG_NET_VENDOR_ARC is not set -# CONFIG_NET_VENDOR_AURORA is not set +# CONFIG_NET_VENDOR_ASIX is not set # CONFIG_NET_VENDOR_BROADCOM is not set # CONFIG_NET_VENDOR_CADENCE is not set # CONFIG_NET_VENDOR_CAVIUM is not set # CONFIG_NET_VENDOR_CIRRUS is not set # CONFIG_NET_VENDOR_CORTINA is not set +# CONFIG_NET_VENDOR_DAVICOM is not set +# CONFIG_NET_VENDOR_ENGLEDER is not set # CONFIG_NET_VENDOR_EZCHIP is not set # CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_FUNGIBLE is not set # CONFIG_NET_VENDOR_GOOGLE is not set # CONFIG_NET_VENDOR_HISILICON is not set # CONFIG_NET_VENDOR_HUAWEI is not set # CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_ADI is not set +# CONFIG_NET_VENDOR_LITEX is not set # CONFIG_NET_VENDOR_MARVELL is not set # CONFIG_NET_VENDOR_MELLANOX is not set # CONFIG_NET_VENDOR_MICREL is not set # CONFIG_NET_VENDOR_MICROCHIP is not set # CONFIG_NET_VENDOR_MICROSEMI is not set +# CONFIG_NET_VENDOR_MICROSOFT is not set +# CONFIG_NET_VENDOR_NI is not set # CONFIG_NET_VENDOR_NATSEMI is not set # CONFIG_NET_VENDOR_NETRONOME is not set -# CONFIG_NET_VENDOR_NI is not set # CONFIG_NET_VENDOR_PENSANDO is not set # CONFIG_NET_VENDOR_QUALCOMM is not set # CONFIG_NET_VENDOR_RENESAS is not set @@ -129,12 +131,15 @@ CONFIG_NETDEVICES=y # CONFIG_NET_VENDOR_SOCIONEXT is not set # CONFIG_NET_VENDOR_STMICRO is not set # CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_VERTEXCOM is not set # CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WANGXUN is not set # CONFIG_NET_VENDOR_WIZNET is not set # CONFIG_NET_VENDOR_XILINX is not set CONFIG_MICREL_PHY=y CONFIG_MICROCHIP_PHY=y CONFIG_SMSC_PHY=y +CONFIG_CAN_FLEXCAN=m CONFIG_USB_NET_DRIVERS=m CONFIG_USB_USBNET=m # CONFIG_USB_NET_AX8817X is not set @@ -161,7 +166,6 @@ CONFIG_USB_NET_SMSC95XX=m # CONFIG_WLAN_VENDOR_ST is not set CONFIG_WL12XX=m CONFIG_WLCORE_SDIO=m -# CONFIG_WILINK_PLATFORM_DATA is not set # CONFIG_WLAN_VENDOR_ZYDAS is not set # CONFIG_WLAN_VENDOR_QUANTENNA is not set # CONFIG_INPUT_LEDS is not set @@ -183,7 +187,6 @@ CONFIG_SERIAL_OF_PLATFORM=m CONFIG_SERIAL_IMX=y CONFIG_SERIAL_IMX_CONSOLE=y CONFIG_SERIAL_DEV_BUS=y -# CONFIG_RANDOM_TRUST_BOOTLOADER is not set # CONFIG_I2C_COMPAT is not set CONFIG_I2C_CHARDEV=y CONFIG_I2C_MUX=y @@ -200,8 +203,7 @@ CONFIG_SPI_OCORES=m CONFIG_SPI_SPIDEV=y CONFIG_PPS_CLIENT_LDISC=m CONFIG_PPS_CLIENT_GPIO=m -CONFIG_PTP_1588_CLOCK=m -CONFIG_GPIO_SYSFS=y +CONFIG_PTP_1588_CLOCK_KVM=m CONFIG_GPIO_MXC=y CONFIG_GPIO_TS71XXWEIM=y CONFIG_GPIO_PCA953X=m @@ -224,16 +226,12 @@ CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_ANATOP=y CONFIG_REGULATOR_GPIO=y -CONFIG_IMX_IPUV3_CORE=y CONFIG_DRM=y +CONFIG_DRM_FBDEV_EMULATION=y CONFIG_DRM_PANEL_LVDS=y CONFIG_DRM_PANEL_SIMPLE=y -CONFIG_DRM_IMX=y -CONFIG_DRM_IMX_PARALLEL_DISPLAY=y CONFIG_DRM_MXSFB=y -CONFIG_FB_MODE_HELPERS=y -# CONFIG_FB_MX3 is not set -CONFIG_FB_ST7565P=m +CONFIG_FB_DEVICE=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_PLATFORM=y CONFIG_BACKLIGHT_CLASS_DEVICE=y @@ -256,7 +254,7 @@ CONFIG_USB_ANNOUNCE_NEW_DEVICES=y CONFIG_USB_OTG=y CONFIG_USB_OTG_FSM=m CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_MXC=y +CONFIG_USB_EHCI_FSL=y CONFIG_USB_ACM=m CONFIG_USB_STORAGE=y CONFIG_USB_CHIPIDEA=y @@ -267,7 +265,6 @@ CONFIG_USB_SERIAL_FTDI_SIO=m CONFIG_NOP_USB_XCEIV=y CONFIG_USB_MXS_PHY=y CONFIG_USB_GADGET=y -CONFIG_USB_FSL_USB2=y CONFIG_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y @@ -316,8 +313,6 @@ CONFIG_EXT4_FS=y CONFIG_EXT4_FS_POSIX_ACL=y CONFIG_QUOTA=y CONFIG_QUOTA_NETLINK_INTERFACE=y -# CONFIG_PRINT_QUOTA_WARNING is not set -CONFIG_AUTOFS4_FS=m CONFIG_FUSE_FS=m CONFIG_VFAT_FS=y CONFIG_TMPFS=y @@ -350,5 +345,4 @@ CONFIG_XZ_DEC=y CONFIG_DMA_CMA=y CONFIG_CMA_SIZE_MBYTES=64 # CONFIG_SYMBOLIC_ERRNAME is not set -# CONFIG_ENABLE_MUST_CHECK is not set # CONFIG_RUNTIME_TESTING_MENU is not set From f8a665fafcc65b50a98900a4e00e309474b3a82c Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Thu, 23 May 2024 23:56:15 +0000 Subject: [PATCH 151/244] ARM: configs: tsimx6_minimal: updates for 6.6 Signed-off-by: Kris Bahnsen --- arch/arm/configs/tsimx6_minimal_defconfig | 56 ++++++++++------------- 1 file changed, 24 insertions(+), 32 deletions(-) diff --git a/arch/arm/configs/tsimx6_minimal_defconfig b/arch/arm/configs/tsimx6_minimal_defconfig index df8e66c65f89d..c1f9a7ed48828 100644 --- a/arch/arm/configs/tsimx6_minimal_defconfig +++ b/arch/arm/configs/tsimx6_minimal_defconfig @@ -1,5 +1,4 @@ CONFIG_KERNEL_LZO=y -# CONFIG_SWAP is not set CONFIG_SYSVIPC=y # CONFIG_CROSS_MEMORY_ATTACH is not set CONFIG_NO_HZ_IDLE=y @@ -9,9 +8,6 @@ CONFIG_PREEMPT=y CONFIG_LOG_BUF_SHIFT=18 CONFIG_CGROUPS=y CONFIG_CC_OPTIMIZE_FOR_SIZE=y -# CONFIG_COMPAT_BRK is not set -CONFIG_SLAB=y -# CONFIG_SLAB_MERGE_DEFAULT is not set CONFIG_ARCH_MULTI_V6=y CONFIG_ARCH_MXC=y CONFIG_SOC_IMX6Q=y @@ -22,7 +18,6 @@ CONFIG_HOTPLUG_CPU=y CONFIG_ARM_PSCI=y CONFIG_HZ_1000=y CONFIG_HIGHMEM=y -CONFIG_FORCE_MAX_ZONEORDER=14 CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" CONFIG_CPU_FREQ=y CONFIG_CPU_FREQ_STAT=y @@ -41,11 +36,12 @@ CONFIG_PM=y CONFIG_PM_DEBUG=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_COMPRESS=y CONFIG_MODULE_COMPRESS_XZ=y -# CONFIG_BLK_DEV_BSG is not set # CONFIG_MQ_IOSCHED_KYBER is not set CONFIG_BINFMT_MISC=y +# CONFIG_SWAP is not set +# CONFIG_SLAB_MERGE_DEFAULT is not set +# CONFIG_COMPAT_BRK is not set CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y @@ -54,7 +50,6 @@ CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y # CONFIG_IPV6 is not set CONFIG_CAN=m -CONFIG_CAN_FLEXCAN=m CONFIG_BT=m CONFIG_BT_HCIUART=m CONFIG_BT_HCIUART_LL=y @@ -67,7 +62,7 @@ CONFIG_RFKILL=m # CONFIG_ETHTOOL_NETLINK is not set CONFIG_PCI=y CONFIG_PCI_MSI=y -CONFIG_PCI_IMX6=y +CONFIG_PCI_IMX6_HOST=y CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y # CONFIG_STANDALONE is not set @@ -89,6 +84,7 @@ CONFIG_EEPROM_AT24=y CONFIG_EEPROM_AT25=y # CONFIG_SCSI_PROC_FS is not set CONFIG_BLK_DEV_SD=y +# CONFIG_BLK_DEV_BSG is not set CONFIG_SCSI_CONSTANTS=y CONFIG_SCSI_LOGGING=y CONFIG_SCSI_SCAN_ASYNC=y @@ -107,37 +103,45 @@ CONFIG_NETDEVICES=y # CONFIG_NET_VENDOR_AMD is not set # CONFIG_NET_VENDOR_AQUANTIA is not set # CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_ASIX is not set # CONFIG_NET_VENDOR_ATHEROS is not set -# CONFIG_NET_VENDOR_AURORA is not set # CONFIG_NET_VENDOR_BROADCOM is not set -# CONFIG_NET_VENDOR_BROCADE is not set # CONFIG_NET_VENDOR_CADENCE is not set # CONFIG_NET_VENDOR_CAVIUM is not set # CONFIG_NET_VENDOR_CHELSIO is not set # CONFIG_NET_VENDOR_CIRRUS is not set # CONFIG_NET_VENDOR_CISCO is not set # CONFIG_NET_VENDOR_CORTINA is not set +# CONFIG_NET_VENDOR_DAVICOM is not set # CONFIG_NET_VENDOR_DEC is not set # CONFIG_NET_VENDOR_DLINK is not set # CONFIG_NET_VENDOR_EMULEX is not set +# CONFIG_NET_VENDOR_ENGLEDER is not set # CONFIG_NET_VENDOR_EZCHIP is not set # CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_FUNGIBLE is not set +# CONFIG_NET_VENDOR_GOOGLE is not set +# CONFIG_NET_VENDOR_HISILICON is not set CONFIG_IGB=m +# CONFIG_NET_VENDOR_ADI is not set +# CONFIG_NET_VENDOR_LITEX is not set # CONFIG_NET_VENDOR_MARVELL is not set # CONFIG_NET_VENDOR_MELLANOX is not set # CONFIG_NET_VENDOR_MICREL is not set # CONFIG_NET_VENDOR_MICROCHIP is not set # CONFIG_NET_VENDOR_MICROSEMI is not set +# CONFIG_NET_VENDOR_MICROSOFT is not set # CONFIG_NET_VENDOR_MYRI is not set +# CONFIG_NET_VENDOR_NI is not set # CONFIG_NET_VENDOR_NATSEMI is not set # CONFIG_NET_VENDOR_NETERION is not set # CONFIG_NET_VENDOR_NETRONOME is not set -# CONFIG_NET_VENDOR_NI is not set # CONFIG_NET_VENDOR_NVIDIA is not set # CONFIG_NET_VENDOR_OKI is not set # CONFIG_NET_VENDOR_PACKET_ENGINES is not set # CONFIG_NET_VENDOR_PENSANDO is not set # CONFIG_NET_VENDOR_QLOGIC is not set +# CONFIG_NET_VENDOR_BROCADE is not set # CONFIG_NET_VENDOR_QUALCOMM is not set # CONFIG_NET_VENDOR_RDC is not set # CONFIG_NET_VENDOR_REALTEK is not set @@ -145,9 +149,9 @@ CONFIG_IGB=m # CONFIG_NET_VENDOR_ROCKER is not set # CONFIG_NET_VENDOR_SAMSUNG is not set # CONFIG_NET_VENDOR_SEEQ is not set -# CONFIG_NET_VENDOR_SOLARFLARE is not set # CONFIG_NET_VENDOR_SILAN is not set # CONFIG_NET_VENDOR_SIS is not set +# CONFIG_NET_VENDOR_SOLARFLARE is not set # CONFIG_NET_VENDOR_SMSC is not set # CONFIG_NET_VENDOR_SOCIONEXT is not set # CONFIG_NET_VENDOR_STMICRO is not set @@ -155,12 +159,15 @@ CONFIG_IGB=m # CONFIG_NET_VENDOR_SYNOPSYS is not set # CONFIG_NET_VENDOR_TEHUTI is not set # CONFIG_NET_VENDOR_TI is not set +# CONFIG_NET_VENDOR_VERTEXCOM is not set # CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WANGXUN is not set # CONFIG_NET_VENDOR_WIZNET is not set # CONFIG_NET_VENDOR_XILINX is not set CONFIG_MICREL_PHY=y CONFIG_MICROCHIP_PHY=y CONFIG_SMSC_PHY=y +CONFIG_CAN_FLEXCAN=m CONFIG_USB_USBNET=m # CONFIG_USB_NET_AX8817X is not set # CONFIG_USB_NET_AX88179_178A is not set @@ -187,7 +194,6 @@ CONFIG_ATH10K_SDIO=m # CONFIG_WLAN_VENDOR_ST is not set CONFIG_WL12XX=m CONFIG_WLCORE_SDIO=m -# CONFIG_WILINK_PLATFORM_DATA is not set # CONFIG_WLAN_VENDOR_ZYDAS is not set # CONFIG_WLAN_VENDOR_QUANTENNA is not set # CONFIG_INPUT_LEDS is not set @@ -207,7 +213,6 @@ CONFIG_SERIAL_IMX_CONSOLE=y CONFIG_SERIAL_FSL_LPUART=y CONFIG_SERIAL_FSL_LPUART_CONSOLE=y CONFIG_SERIAL_DEV_BUS=y -# CONFIG_RANDOM_TRUST_BOOTLOADER is not set # CONFIG_I2C_COMPAT is not set CONFIG_I2C_CHARDEV=y CONFIG_I2C_MUX=y @@ -222,12 +227,7 @@ CONFIG_SPI_GPIO=y CONFIG_SPI_IMX=y CONFIG_SPI_SPIDEV=y CONFIG_PPS_CLIENT_GPIO=m -CONFIG_PTP_1588_CLOCK=m -CONFIG_PINCTRL_IMX8MM=y -CONFIG_PINCTRL_IMX8MN=y -CONFIG_PINCTRL_IMX8MP=y -CONFIG_PINCTRL_IMX8MQ=y -CONFIG_GPIO_SYSFS=y +CONFIG_PTP_1588_CLOCK_KVM=m CONFIG_GPIO_MXC=y CONFIG_GPIO_TS4900=y CONFIG_POWER_RESET=y @@ -246,9 +246,8 @@ CONFIG_REGULATOR_ANATOP=y CONFIG_REGULATOR_GPIO=y CONFIG_IMX_IPUV3_CORE=y CONFIG_DRM=y +CONFIG_DRM_FBDEV_EMULATION=y CONFIG_DRM_PANEL_LVDS=y -CONFIG_DRM_PANEL_SIMPLE=y -CONFIG_DRM_PANEL_SEIKO_43WVF1G=y CONFIG_DRM_TI_TFP410=y CONFIG_DRM_DW_HDMI_AHB_AUDIO=m CONFIG_DRM_DW_HDMI_CEC=y @@ -257,10 +256,11 @@ CONFIG_DRM_IMX_PARALLEL_DISPLAY=y CONFIG_DRM_IMX_LDB=y CONFIG_DRM_IMX_HDMI=y CONFIG_DRM_ETNAVIV=y -CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_DEVICE=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_L4F00242T03=y CONFIG_LCD_PLATFORM=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BACKLIGHT_PWM=y CONFIG_BACKLIGHT_GPIO=y CONFIG_SOUND=m @@ -295,7 +295,6 @@ CONFIG_USB=y # CONFIG_USB_PCI is not set CONFIG_USB_ANNOUNCE_NEW_DEVICES=y CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_MXC=y CONFIG_USB_ACM=m CONFIG_USB_STORAGE=y CONFIG_USB_CHIPIDEA=y @@ -306,7 +305,6 @@ CONFIG_USB_SERIAL_FTDI_SIO=m CONFIG_NOP_USB_XCEIV=y CONFIG_USB_MXS_PHY=y CONFIG_USB_GADGET=y -CONFIG_USB_FSL_USB2=y CONFIG_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y @@ -351,8 +349,6 @@ CONFIG_EXT4_FS=y CONFIG_EXT4_FS_POSIX_ACL=y CONFIG_QUOTA=y CONFIG_QUOTA_NETLINK_INTERFACE=y -# CONFIG_PRINT_QUOTA_WARNING is not set -CONFIG_AUTOFS4_FS=y CONFIG_VFAT_FS=y CONFIG_TMPFS_POSIX_ACL=y CONFIG_CONFIGFS_FS=y @@ -382,9 +378,5 @@ CONFIG_CRC7=m CONFIG_LIBCRC32C=m CONFIG_XZ_DEC=y CONFIG_CMA_SIZE_MBYTES=64 -CONFIG_FONTS=y -CONFIG_FONT_8x8=y -CONFIG_FONT_8x16=y # CONFIG_SYMBOLIC_ERRNAME is not set -# CONFIG_ENABLE_MUST_CHECK is not set # CONFIG_RUNTIME_TESTING_MENU is not set From 429aa7a2d1a78c7be0e3ad21390b46e5fb2626fe Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Thu, 6 Jun 2024 00:41:09 +0000 Subject: [PATCH 152/244] drivers: irqchip: ts71xxweim: fixes for 6.6 port Signed-off-by: Kris Bahnsen --- drivers/irqchip/irq-ts71xxweim.c | 75 +++++++++++++++++--------------- 1 file changed, 40 insertions(+), 35 deletions(-) diff --git a/drivers/irqchip/irq-ts71xxweim.c b/drivers/irqchip/irq-ts71xxweim.c index a08ac179ae78e..26e02278383d2 100644 --- a/drivers/irqchip/irq-ts71xxweim.c +++ b/drivers/irqchip/irq-ts71xxweim.c @@ -1,11 +1,15 @@ // SPDX-License-Identifier: GPL-2.0 +#include #include #include +#include #include #include #include #include +#include +#include #define TSWEIM_IRQ_STATUS 0x24 #define TSWEIM_IRQ_POLARITY 0x28 @@ -15,18 +19,13 @@ struct tsweim_intc { void __iomem *syscon; struct irq_domain *irqdomain; - struct irq_chip chip; + struct platform_device *pdev; u32 mask; }; -static struct tsweim_intc *irq_data_to_priv(struct irq_data *data) -{ - return data->domain->host_data; -} - static void tsweim_intc_mask(struct irq_data *d) { - struct tsweim_intc *priv = irq_data_to_priv(d); + struct tsweim_intc *priv = irq_data_get_irq_chip_data(d); priv->mask = readl(priv->syscon + TSWEIM_IRQ_MASK) & ~BIT(d->hwirq); writel(priv->mask, priv->syscon + TSWEIM_IRQ_MASK); @@ -34,15 +33,22 @@ static void tsweim_intc_mask(struct irq_data *d) static void tsweim_intc_unmask(struct irq_data *d) { - struct tsweim_intc *priv = irq_data_to_priv(d); + struct tsweim_intc *priv = irq_data_get_irq_chip_data(d); priv->mask = readl(priv->syscon + TSWEIM_IRQ_MASK) | BIT(d->hwirq); writel(priv->mask, priv->syscon + TSWEIM_IRQ_MASK); } +static void tsweim_intc_print_chip(struct irq_data *d, struct seq_file *p) +{ + struct tsweim_intc *priv = irq_data_get_irq_chip_data(d); + + seq_printf(p, "%s", dev_name(&priv->pdev->dev)); +} + static int tsweim_intc_set_type(struct irq_data *d, unsigned int flow_type) { - struct tsweim_intc *priv = irq_data_to_priv(d); + struct tsweim_intc *priv = irq_data_get_irq_chip_data(d); uint32_t polarity = readl(priv->syscon + TSWEIM_IRQ_POLARITY); uint32_t bit = BIT_MASK(d->hwirq); @@ -62,6 +68,12 @@ static int tsweim_intc_set_type(struct irq_data *d, unsigned int flow_type) return 0; } +static struct irq_chip tsweim_intc_chip = { + .irq_mask = tsweim_intc_mask, + .irq_unmask = tsweim_intc_unmask, + .irq_print_chip = tsweim_intc_print_chip, +}; + static void tsweim_irq_handler(struct irq_desc *desc) { struct irq_chip *chip = irq_desc_get_chip(desc); @@ -75,10 +87,8 @@ static void tsweim_irq_handler(struct irq_desc *desc) (priv->mask & readl(priv->syscon + TSWEIM_IRQ_STATUS)))) { irq = 0; do { - if (status & 1) { - generic_handle_irq(irq_linear_revmap( - priv->irqdomain, irq)); - } + if (status & 1) + generic_handle_domain_irq(priv->irqdomain, irq); status >>= 1; irq++; } while (status); @@ -90,9 +100,8 @@ static void tsweim_irq_handler(struct irq_desc *desc) static int tsweim_intc_irqdomain_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hwirq) { - struct tsweim_intc *priv = d->host_data; - - irq_set_chip_and_handler(irq, &priv->chip, handle_level_irq); + irq_set_chip_and_handler(irq, &tsweim_intc_chip, handle_level_irq); + irq_set_chip_data(irq, d->host_data); irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE); irq_set_status_flags(irq, IRQ_LEVEL); @@ -108,8 +117,11 @@ static int tsweim_intc_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct tsweim_intc *priv; - struct resource *irq = 0; - struct irq_chip *chip; + int irq = 0; + + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; priv = devm_kzalloc(dev, sizeof(struct tsweim_intc), GFP_KERNEL); if (!priv) @@ -119,37 +131,32 @@ static int tsweim_intc_probe(struct platform_device *pdev) if (IS_ERR(priv->syscon)) return PTR_ERR(priv->syscon); - irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); - if (irq == NULL) { - pr_err("Can't get interrupt\n"); - return -EFAULT; - } - - chip = &priv->chip; - chip->name = dev->of_node->name; - chip->irq_mask = tsweim_intc_mask; - chip->irq_unmask = tsweim_intc_unmask; + priv->pdev = pdev; if (of_property_read_bool(dev->of_node, "ts,haspolarity")) - chip->irq_set_type = tsweim_intc_set_type; + tsweim_intc_chip.irq_set_type = tsweim_intc_set_type; priv->irqdomain = irq_domain_add_linear(dev->of_node, TSWEIM_NUM_FPGA_IRQ, &tsweim_intc_irqdomain_ops, priv); - if (!priv->irqdomain) { pr_err("unable to add irq domain\n"); return -ENOMEM; } - irq_set_handler_data(irq->start, priv); - irq_set_chained_handler(irq->start, tsweim_irq_handler); + if (devm_request_irq(dev, irq, no_action, IRQF_NO_THREAD, + dev_name(dev), NULL)) { + irq_domain_remove(priv->irqdomain); + return -ENOENT; + } + + irq_set_chained_handler_and_data(irq, tsweim_irq_handler, priv); platform_set_drvdata(pdev, priv); return 0; } -static int tsweim_intc_remove(struct platform_device *pdev) +static void tsweim_intc_remove(struct platform_device *pdev) { struct tsweim_intc *priv = dev_get_platdata(&pdev->dev); @@ -164,8 +171,6 @@ static int tsweim_intc_remove(struct platform_device *pdev) irq_domain_remove(priv->irqdomain); priv->irqdomain = NULL; } - - return 0; } static const struct of_device_id tsweim_intc_of_match_table[] = { From 2a1c239019df3f85e4a0e8a05e25fdd737f30fe9 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Tue, 4 Jun 2024 00:44:13 +0000 Subject: [PATCH 153/244] gpio: ts71xxweim: add gpio_chip parent Needed for gpiolib to properly set up details about the driver's GPIOs at runtime Signed-off-by: Kris Bahnsen --- drivers/gpio/gpio-ts71xxweim.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpio/gpio-ts71xxweim.c b/drivers/gpio/gpio-ts71xxweim.c index 6f11d6013c77a..069bc5adbf38d 100644 --- a/drivers/gpio/gpio-ts71xxweim.c +++ b/drivers/gpio/gpio-ts71xxweim.c @@ -133,6 +133,7 @@ static int tsweim_gpio_probe(struct platform_device *pdev) priv->gpio_chip = template_chip; priv->gpio_chip.label = dev_name(dev); priv->gpio_chip.ngpio = TSWEIM_NR_DIO; + priv->gpio_chip.parent = dev; pdev->dev.platform_data = &priv; return devm_gpiochip_add_data(&pdev->dev, &priv->gpio_chip, &priv); From a5e2f885f0b8ce5c55be93684efba68a5bc28013 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Wed, 5 Jun 2024 19:57:19 +0000 Subject: [PATCH 154/244] ARM: dts: imx6ul: ts7100: updates Signed-off-by: Kris Bahnsen --- arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-1.dts | 1 + arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-3.dts | 1 + .../arm/boot/dts/nxp/imx/imx6ul-ts7100-3.dtsi | 20 +++++--- .../arm/boot/dts/nxp/imx/imx6ul-ts7100-z.dtsi | 20 +++++--- arch/arm/boot/dts/nxp/imx/imx6ul-ts7100.dtsi | 51 ++++++++++--------- 5 files changed, 56 insertions(+), 37 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-1.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-1.dts index a2258958f9275..581430d45c34e 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-1.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-1.dts @@ -3,6 +3,7 @@ * Copyright (C) 2023 Technologic Systems, Inc. dba embeddedTS */ /dts-v1/; +#include "imx6ul.dtsi" #include "imx6ul-ts7100.dtsi" #include "imx6ul-ts7100-z.dtsi" diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-3.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-3.dts index 9ca1ca37b0a9a..6acaacf8647a8 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-3.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-3.dts @@ -4,6 +4,7 @@ */ /dts-v1/; +#include "imx6ul.dtsi" #include "imx6ul-ts7100.dtsi" #include "imx6ul-ts7100-3.dtsi" diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-3.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-3.dtsi index 84053b3370a22..7b40675d8f16d 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-3.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-3.dtsi @@ -4,20 +4,26 @@ */ / { - leds { + aliases { + gpio5 = &fpga_gpio0; + gpio6 = &fpga_gpio1; + gpio7 = &fpga_gpio2; + }; + + led-controller { compatible = "gpio-leds"; led-2 { color = ; function = LED_FUNCTION_INDICATOR; - gpios = <&gpio7 9 GPIO_ACTIVE_LOW>; + gpios = <&fpga_gpio1 9 GPIO_ACTIVE_LOW>; default-state = "off"; }; led-3 { color = ; function = LED_FUNCTION_INDICATOR; - gpios = <&gpio7 8 GPIO_ACTIVE_LOW>; + gpios = <&fpga_gpio1 8 GPIO_ACTIVE_LOW>; default-state = "off"; }; }; @@ -34,7 +40,7 @@ compatible = "microchip,wilc3000"; reg = <0>; spi-max-frequency = <20000000>; - reset-gpios = <&gpio7 7 GPIO_ACTIVE_HIGH>; + reset-gpios = <&fpga_gpio1 7 GPIO_ACTIVE_HIGH>; chip_en-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; interrupt-parent = <&gpio1>; interrupts = <11 GPIO_ACTIVE_HIGH>; @@ -81,7 +87,7 @@ }; /* FPGA dio: 50004010.gpio */ -&gpio6 { +&fpga_gpio0 { gpio-line-names = "DIO_1_OUT", "DIO_2_OUT", "DIO_1_IN", "DIO_2_IN", "DIO_3_IN", "DIO_6", "DIG_IN_1", "DIG_IN_2", @@ -90,7 +96,7 @@ }; /* FPGA dio2: 50004040.gpio */ -&gpio7 { +&fpga_gpio1 { gpio-line-names = "EN_EMMC_3V3#", "EN_ADC1_12V", "EN_ADC2_12V", "EN_ADC3_12V", "EN_ADC4_12V", "EN_USB_HOST_5V", "PHY_RESET#", "WIFI_RESET#", @@ -99,7 +105,7 @@ }; /* FPGA dio3: 50004050.gpio */ -&gpio8 { +&fpga_gpio2 { gpio-line-names = "CPU_TOUCH_IRQ#", "", "C6_PAD", "B8_PAD", "C9_PAD", "C8_PAD", "NIM_3V3#_4V", "DIO_16_PAD", diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-z.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-z.dtsi index b2f5f730e5d0c..293ec7af4109a 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-z.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-z.dtsi @@ -4,20 +4,26 @@ */ / { - leds { + aliases { + gpio5 = &fpga_gpio0; + gpio6 = &fpga_gpio1; + gpio7 = &fpga_gpio2; + }; + + led-controller { compatible = "gpio-leds"; led-2 { color = ; function = LED_FUNCTION_INDICATOR; - gpios = <&gpio7 9 GPIO_ACTIVE_LOW>; + gpios = <&fpga_gpio1 9 GPIO_ACTIVE_LOW>; default-state = "off"; }; led-3 { color = ; function = LED_FUNCTION_INDICATOR; - gpios = <&gpio7 8 GPIO_ACTIVE_LOW>; + gpios = <&fpga_gpio1 8 GPIO_ACTIVE_LOW>; default-state = "off"; }; }; @@ -34,7 +40,7 @@ compatible = "microchip,wilc3000"; reg = <0>; spi-max-frequency = <20000000>; - reset-gpios = <&gpio7 7 GPIO_ACTIVE_HIGH>; + reset-gpios = <&fpga_gpio1 7 GPIO_ACTIVE_HIGH>; chip_en-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; interrupt-parent = <&gpio1>; interrupts = <11 GPIO_ACTIVE_HIGH>; @@ -81,7 +87,7 @@ }; /* FPGA dio: 50004010.gpio */ -&gpio6 { +&fpga_gpio0 { gpio-line-names = "DIO_1_OUT", "DIO_2_OUT", "DIO_1_IN", "DIO_2_IN", "DIO_3_IN", "DIO_6", "DIG_IN_1", "DIG_IN_2", @@ -90,7 +96,7 @@ }; /* FPGA dio2: 50004040.gpio */ -&gpio7 { +&fpga_gpio1 { gpio-line-names = "EN_EMMC_3V3#", "EN_ADC1_12V", "EN_ADC2_12V", "EN_ADC3_12V", "EN_ADC4_12V", "EN_USB_HOST_5V", "PHY_RESET#", "WIFI_RESET#", @@ -99,7 +105,7 @@ }; /* FPGA dio3: 50004050.gpio */ -&gpio8 { +&fpga_gpio2 { gpio-line-names = "CPU_TOUCH_IRQ#", "", "C6_PAD", "B8_PAD", "C9_PAD", "C8_PAD", "NIM_3V3#_4V", "DIO_16_PAD", diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100.dtsi index cafc01e31426e..10ba4adcfa1a1 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100.dtsi @@ -5,7 +5,6 @@ #include #include -#include "imx6ul.dtsi" / { chosen { @@ -13,11 +12,12 @@ }; memory { + device_type = "memory"; /* Set by u-boot */ reg = <0x80000000 0>; }; - leds { + led-controller { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_cpu_leds>; compatible = "gpio-leds"; @@ -37,25 +37,25 @@ }; }; - reg_3v3: rev_3v3 { + reg_3v3: regulator-3v3 { compatible = "regulator-fixed"; regulator-name = "3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - reg_lcdif_enable: en-lcdif { + reg_lcdif_enable: regulator-lcdif-en { compatible = "regulator-fixed"; regulator-name = "LCDIF_EN"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&gpio8 1 GPIO_ACTIVE_HIGH>; + gpio = <&fpga_gpio2 1 GPIO_ACTIVE_HIGH>; enable-active-high; regulator-boot-on; regulator-always-on; }; - vref_adc_2v5: adc { + reg_adc_vref_2v5: regulator-adc-vref { compatible = "regulator-fixed"; regulator-name = "ADC_VREF"; regulator-min-microvolt = <2500000>; @@ -64,6 +64,12 @@ regulator-always-on; }; + fpga_clk_weim_bclk: fpga_clk_weim_bclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <49500000>; + }; + panel { label = "st7789v"; compatible = "panel-dpi"; @@ -93,7 +99,7 @@ &adc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_adc1>; - vref-supply = <&vref_adc_2v5>; + vref-supply = <®_adc_vref_2v5>; status = "okay"; }; @@ -151,12 +157,17 @@ st_magn: magnetometer@1e { compatible = "st,lis2mdl"; - reg = <0x1e>; + /* This option isn't valid on this part as it only supports + * a single drdy pin. However, the driver defaults to int2 if + * not drdy pin is specified which the driver errors on if int2 + * is set for this specific part. + */ st,drdy-int-pin = <1>; + reg = <0x1e>; }; m41t00s: rtc@68 { - compatible = "m41t00"; + compatible = "st,m41t00"; reg = <0x68>; }; @@ -365,7 +376,7 @@ pinctrl-0 = <&pinctrl_usdhc1>; no-1-8-v; disable-wp; - broken-cd = <1>; + broken-cd; bus-width = <4>; status = "okay"; }; @@ -387,7 +398,7 @@ #address-cells = <2>; #size-cells = <1>; - fpga: fpgabus@50000000 { + fpga: bus@50000000 { compatible = "simple-bus"; reg = <0 0x50000000 0x00010000>; #address-cells = <1>; @@ -403,20 +414,14 @@ 0 // EIM_CSnWCR2 @ 0x021b8014 >; - fpga_clk_weim_bclk: fpga_clk_weim_bclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <49500000>; - }; - - syscon: syscon@50004000 { + fpga_syscon: bus@50004000 { compatible = "simple-bus"; #address-cells = <0x2>; #size-cells = <0x1>; reg = <0x4000 0x58>; ranges = <0 0 0x4000 0x58>; - gpio6: gpio@50004010 { + fpga_gpio0: gpio@50004010 { compatible = "technologic,ts71xxweim-gpio"; reg = <0 0x10 0x08>; gpio-controller; @@ -425,7 +430,7 @@ #interrupt-cells = <1>; }; - gpio7: gpio@50004040 { + fpga_gpio1: gpio@50004040 { compatible = "technologic,ts71xxweim-gpio"; reg = <0 0x40 0x08>; gpio-controller; @@ -434,7 +439,7 @@ #interrupt-cells = <1>; }; - gpio8: gpio@50004050 { + fpga_gpio2: gpio@50004050 { compatible = "technologic,ts71xxweim-gpio"; reg = <0 0x50 0x08>; gpio-controller; @@ -488,7 +493,7 @@ pagesize = <64>; }; - spisplash: spi@1 { + spisplash: flash@1 { compatible = "jedec,spi-nor"; reg = <1>; spi-max-frequency = <20000000>; @@ -514,7 +519,7 @@ spi-max-frequency = <1000000>; interrupt-parent = <&fpga_intc>; interrupts = <16>; - pendown-gpio = <&gpio8 0 GPIO_ACTIVE_HIGH>; + pendown-gpio = <&fpga_gpio2 0 GPIO_ACTIVE_HIGH>; ti,vref-mv = /bits/ 16 <3300>; ti,keep-vref-on; From 54a5e3bd53d7f915fa60348bda0bced12d21d2b5 Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Wed, 12 Jun 2024 22:10:26 +0000 Subject: [PATCH 155/244] gpio: ts4900: connect GPIO label to dev name Current GPIO label is fixed, so can't distinguish different GPIO controllers through labels. Use dev name instead. --- drivers/gpio/gpio-ts4900.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpio/gpio-ts4900.c b/drivers/gpio/gpio-ts4900.c index 7f6ce22b9d039..2560777a65265 100644 --- a/drivers/gpio/gpio-ts4900.c +++ b/drivers/gpio/gpio-ts4900.c @@ -155,7 +155,7 @@ static int ts4900_gpio_probe(struct i2c_client *client) return -ENOMEM; priv->gpio_chip = template_chip; - priv->gpio_chip.label = "ts4900-gpio"; + priv->gpio_chip.label = dev_name(&client->dev); priv->gpio_chip.ngpio = ngpio; priv->gpio_chip.base = base; priv->gpio_chip.parent = &client->dev; From 405e9dd0a23537e91c65f14928d9a069396237ae Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Thu, 18 Jul 2024 09:21:17 -0700 Subject: [PATCH 156/244] serial: 8250: 8250_ts: Enable RS-485 through RTS --- drivers/tty/serial/8250/8250_ts.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/tty/serial/8250/8250_ts.c b/drivers/tty/serial/8250/8250_ts.c index b8247cd92fe21..4a8228590bd7b 100644 --- a/drivers/tty/serial/8250/8250_ts.c +++ b/drivers/tty/serial/8250/8250_ts.c @@ -8,6 +8,8 @@ #include #include +#include "8250.h" + static unsigned int tsisa_serial_in(struct uart_port *p, int offset) { struct tspc104_bus *bus = (struct tspc104_bus *)p->private_data; @@ -52,6 +54,9 @@ static int technologic_ts16550_probe(struct platform_device *pdev) port->type = PORT_16550A; port->serial_in = tsisa_serial_in; port->serial_out = tsisa_serial_out; + port->rs485_config = serial8250_em485_config; + uport.rs485_start_tx = serial8250_em485_start_tx; + uport.rs485_stop_tx = serial8250_em485_stop_tx; line = serial8250_register_8250_port(&uport); From 7abbfb578681a2aa1ff40e70b253d26238701ef9 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Thu, 17 Jul 2025 17:20:43 +0000 Subject: [PATCH 157/244] pwm: mxs: don't reset block if any channels are active Fixes: 020162d6f49f ("pwm: mxs: Don't modify HW state in .probe() after the PWM chip was registered") Signed-off-by: Kris Bahnsen --- drivers/pwm/pwm-mxs.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/drivers/pwm/pwm-mxs.c b/drivers/pwm/pwm-mxs.c index 8cad214b1c299..4c64578b00bb4 100644 --- a/drivers/pwm/pwm-mxs.c +++ b/drivers/pwm/pwm-mxs.c @@ -3,6 +3,8 @@ * Copyright 2012 Freescale Semiconductor, Inc. */ +#include +#include #include #include #include @@ -19,6 +21,8 @@ #define TOG 0xc #define PWM_CTRL 0x0 +#define CTRL_PRESENT_MASK GENMASK(29, 22) +#define CTRL_ENABLE_MASK GENMASK(7, 0) #define PWM_ACTIVE0 0x10 #define PWM_PERIOD0 0x20 #define PERIOD_PERIOD(p) ((p) & 0xffff) @@ -125,6 +129,7 @@ static int mxs_pwm_probe(struct platform_device *pdev) struct pwm_chip *chip; struct mxs_pwm_chip *mxs; u32 npwm; + u32 ctrl_reg; int ret; ret = of_property_read_u32(np, "fsl,pwm-number", &npwm); @@ -148,10 +153,18 @@ static int mxs_pwm_probe(struct platform_device *pdev) chip->ops = &mxs_pwm_ops; - /* FIXME: Only do this if the PWM isn't already running */ - ret = stmp_reset_block(mxs->base); - if (ret) - return dev_err_probe(&pdev->dev, ret, "failed to reset PWM\n"); + /* + * If any of the PWM channels are present and enabled, skip resetting + * the PWM block as it can safely be assumed the bootloader configured + * them. + */ + ctrl_reg = readl(mxs->base + PWM_CTRL); + if (!(FIELD_GET(CTRL_PRESENT_MASK, ctrl_reg) & + FIELD_GET(CTRL_ENABLE_MASK, ctrl_reg))) { + ret = stmp_reset_block(mxs->base); + if (ret) + return dev_err_probe(&pdev->dev, ret, "failed to reset PWM\n"); + } ret = devm_pwmchip_add(&pdev->dev, chip); if (ret < 0) { From 2dede6ee264648e9b575df3d15ffc447e70e655b Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Wed, 14 Jan 2026 18:02:17 +0000 Subject: [PATCH 158/244] clk: mxs: imx28: ungate PWM clock as part of clock control This is a hack that is a bit easier to apply to the clock controller driver rather than the PWM and clock drivers as we have in the past. The real, long-term solution will be a dummy clock consumer. Signed-off-by: Kris Bahnsen --- drivers/clk/mxs/clk-imx28.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/mxs/clk-imx28.c b/drivers/clk/mxs/clk-imx28.c index 62146ea4d5b8d..0262cd602d655 100644 --- a/drivers/clk/mxs/clk-imx28.c +++ b/drivers/clk/mxs/clk-imx28.c @@ -146,7 +146,7 @@ static struct clk *clks[clk_max]; static struct clk_onecell_data clk_data; static enum imx28_clk clks_init_on[] __initdata = { - cpu, hbus, xbus, emi, uart, + cpu, hbus, xbus, emi, uart, pwm, }; static void __init mx28_clocks_init(struct device_node *np) From e6b0828261485097d2b6f5fe97a2bfe28f518478 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Fri, 30 Jun 2023 12:29:08 -0700 Subject: [PATCH 159/244] drivers: gpio: add SOC_IMX28 to CONFIG_TS4900 The TS-7680, i.MX28 CPU, also uses an FPGA with a compatible GPIO register layout Signed-off-by: Kris Bahnsen --- drivers/gpio/Kconfig | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index b60377305995a..88e064d6f20fa 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -1266,11 +1266,12 @@ config GPIO_TPIC2810 config GPIO_TS4900 tristate "Technologic Systems FPGA I2C GPIO" - depends on SOC_IMX6 || COMPILE_TEST + depends on SOC_IMX6 || SOC_IMX28 || COMPILE_TEST select REGMAP_I2C help Say yes here to enabled the GPIO driver for Technologic's FPGA core. - Series supported include TS-4100, TS-4900, TS-7970 and TS-7990. + Series supported include TS-4100, TS-4900, TS-7680, TS-7970, + and TS-7990. endmenu From 7de8f35739d3d28966fcc455f4274582d83187ce Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Wed, 1 May 2024 20:59:39 +0000 Subject: [PATCH 160/244] net: dsa: mv88e6xxx: add external clock support Systems using a clock that is not an always-on oscillator driving the clock input to the switch IC need a way to enable the clock before the switch IC is un-reset. Signed-off-by: Kris Bahnsen --- drivers/net/dsa/mv88e6xxx/chip.c | 10 ++++++++++ drivers/net/dsa/mv88e6xxx/chip.h | 3 +++ 2 files changed, 13 insertions(+) diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c index b4d48997bf467..88e0250fdc984 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.c +++ b/drivers/net/dsa/mv88e6xxx/chip.c @@ -11,6 +11,7 @@ */ #include +#include #include #include #include @@ -7324,6 +7325,13 @@ static int mv88e6xxx_probe(struct mdio_device *mdiodev) chip->info = compat_info; + chip->clk = devm_clk_get_optional(dev, "switch"); + if (IS_ERR(chip->clk)) { + err = PTR_ERR(chip->clk); + goto out; + } + clk_prepare_enable(chip->clk); + chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); if (IS_ERR(chip->reset)) { err = PTR_ERR(chip->reset); @@ -7457,6 +7465,8 @@ static void mv88e6xxx_remove(struct mdio_device *mdiodev) mv88e6xxx_irq_poll_free(chip); mv88e6xxx_phy_destroy(chip); + + clk_disable_unprepare(chip->clk); } static void mv88e6xxx_shutdown(struct mdio_device *mdiodev) diff --git a/drivers/net/dsa/mv88e6xxx/chip.h b/drivers/net/dsa/mv88e6xxx/chip.h index 2f211e55cb47b..247291358fe0b 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.h +++ b/drivers/net/dsa/mv88e6xxx/chip.h @@ -381,6 +381,9 @@ struct mv88e6xxx_chip { */ struct gpio_desc *reset; + /* Optional clock to drive the switch */ + struct clk *clk; + /* set to size of eeprom if supported by the switch */ u32 eeprom_len; From 8e41c825aab1d210bfc5d656e429493c4cdb62b7 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Wed, 1 May 2024 22:26:04 +0000 Subject: [PATCH 161/244] net: dsa: mv88e6xxx: support OF reset assert/deassert times This also moves to using fsleep() for these operations to better handle ranges. Some chips in this series need longer reset deassertion times, or they specify a range with a typical that the static reset times in probe/reset did not always meet. Signed-off-by: Kris Bahnsen --- drivers/net/dsa/mv88e6xxx/chip.c | 16 +++++++++++++--- drivers/net/dsa/mv88e6xxx/chip.h | 4 ++++ 2 files changed, 17 insertions(+), 3 deletions(-) diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c index 88e0250fdc984..0dab3087a1bbc 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.c +++ b/drivers/net/dsa/mv88e6xxx/chip.c @@ -3172,9 +3172,9 @@ static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) } gpiod_set_value_cansleep(gpiod, 1); - usleep_range(10000, 20000); + fsleep(chip->reset_assert_us); gpiod_set_value_cansleep(gpiod, 0); - usleep_range(10000, 20000); + fsleep(chip->reset_deassert_us); if (chip->info->ops->hardware_reset_post) { err = chip->info->ops->hardware_reset_post(chip); @@ -7337,8 +7337,18 @@ static int mv88e6xxx_probe(struct mdio_device *mdiodev) err = PTR_ERR(chip->reset); goto out; } + if (chip->reset) { + of_property_read_u32(np, "reset-assert-us", + &chip->reset_assert_us); + if (IS_ERR(&chip->reset_assert_us)) + chip->reset_assert_us = 10000; + of_property_read_u32(np, "reset-deassert-us", + &chip->reset_deassert_us); + if (IS_ERR(&chip->reset_deassert_us)) + chip->reset_deassert_us = 10000; + } if (chip->reset) - usleep_range(10000, 20000); + fsleep(chip->reset_deassert_us); /* Detect if the device is configured in single chip addressing mode, * otherwise continue with address specific smi init/detection. diff --git a/drivers/net/dsa/mv88e6xxx/chip.h b/drivers/net/dsa/mv88e6xxx/chip.h index 247291358fe0b..499fbb31866e0 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.h +++ b/drivers/net/dsa/mv88e6xxx/chip.h @@ -381,6 +381,10 @@ struct mv88e6xxx_chip { */ struct gpio_desc *reset; + /* Optional reset assertion and deassertion delays */ + int reset_assert_us; + int reset_deassert_us; + /* Optional clock to drive the switch */ struct clk *clk; From e134823535a0be1f9efad90e47c0f622a5b06178 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Wed, 1 May 2024 22:45:06 +0000 Subject: [PATCH 162/244] net: dsa: mv88e6xxx: add switch-needs-reset OF property Previously, the probe process expected that the switch: - Was properly reset and the clock has not turned off since unreset or - Is held in a reset state with a valid clock In cases where the bootloader may not have given a real hardware reset to the switch, or the clock was turned off between the bootloader and probe() of this driver, a real reset needs to be given by the driver before any of the detection calls will work properly. This real reset is gated behind an OF property so as to not break existing platforms using this driver that do not want to issue a hardware reset at the time of early probe. Signed-off-by: Kris Bahnsen --- drivers/net/dsa/mv88e6xxx/chip.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c index 0dab3087a1bbc..f3eafbae6abc9 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.c +++ b/drivers/net/dsa/mv88e6xxx/chip.c @@ -7347,6 +7347,16 @@ static int mv88e6xxx_probe(struct mdio_device *mdiodev) if (IS_ERR(&chip->reset_deassert_us)) chip->reset_deassert_us = 10000; } + /* In the case where the chip may be in an invalid state, we issue a + * hardware reset. We cannot use the mv88e6xxx_switch_reset() function + * as this queries the EEPROM interface. Doing so requires the switch IC + * to have been properly reset previously. + */ + if (chip->reset && of_property_read_bool(np, "switch-needs-reset")) { + gpiod_set_value_cansleep(chip->reset, 1); + fsleep(chip->reset_assert_us); + gpiod_set_value_cansleep(chip->reset, 0); + } if (chip->reset) fsleep(chip->reset_deassert_us); From 450372fffa9df47129f490829db0c959a4dbd477 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Tue, 11 Jul 2023 12:28:48 -0700 Subject: [PATCH 163/244] ARM: tsimx28_minimal: add support for TS-7680 Adds GPIO driver as well as DSA Signed-off-by: Kris Bahnsen --- arch/arm/configs/tsimx28_minimal_defconfig | 37 ++++++---------------- 1 file changed, 10 insertions(+), 27 deletions(-) diff --git a/arch/arm/configs/tsimx28_minimal_defconfig b/arch/arm/configs/tsimx28_minimal_defconfig index 55262f141a176..2ee068ac41b8c 100644 --- a/arch/arm/configs/tsimx28_minimal_defconfig +++ b/arch/arm/configs/tsimx28_minimal_defconfig @@ -40,8 +40,10 @@ CONFIG_IP_PNP_DHCP=y CONFIG_NET_IPIP=m CONFIG_SYN_COOKIES=y # CONFIG_INET_DIAG is not set -CONFIG_IPV6=m CONFIG_IPV6_VTI=m +CONFIG_IPV6_SIT=m +CONFIG_BRIDGE=y +CONFIG_NET_DSA=y CONFIG_DNS_RESOLVER=y CONFIG_CAN=m CONFIG_BT=m @@ -52,12 +54,11 @@ CONFIG_BT_BNEP_MC_FILTER=y CONFIG_BT_BNEP_PROTO_FILTER=y CONFIG_BT_HIDP=m CONFIG_BT_HCIUART=m -CONFIG_BT_HCIUART_H4=y +CONFIG_BT_HCIUART_LL=y CONFIG_CFG80211=m # CONFIG_CFG80211_DEFAULT_PS is not set CONFIG_CFG80211_WEXT=y CONFIG_MAC80211=m -CONFIG_MAC80211_LEDS=y CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_GNSS=y @@ -72,6 +73,7 @@ CONFIG_BLK_DEV_SD=y CONFIG_BLK_DEV_SR=m CONFIG_CHR_DEV_SG=m CONFIG_NETDEVICES=y +CONFIG_NET_DSA_MV88E6XXX=y # CONFIG_NET_VENDOR_ALACRITECH is not set # CONFIG_NET_VENDOR_AMAZON is not set # CONFIG_NET_VENDOR_AQUANTIA is not set @@ -112,6 +114,8 @@ CONFIG_NETDEVICES=y CONFIG_MICROCHIP_PHY=m CONFIG_SMSC_PHY=y CONFIG_CAN_FLEXCAN=m +CONFIG_MDIO_BITBANG=y +CONFIG_MDIO_GPIO=y CONFIG_USB_USBNET=m # CONFIG_USB_NET_AX8817X is not set # CONFIG_USB_NET_AX88179_178A is not set @@ -160,34 +164,19 @@ CONFIG_SPI_SPIDEV=y CONFIG_PPS=m CONFIG_PPS_CLIENT_GPIO=m # CONFIG_PTP_1588_CLOCK is not set +CONFIG_GPIO_TS4900=y CONFIG_WATCHDOG=y CONFIG_TS_WDT_MICRO=y CONFIG_MFD_MXS_LRADC=m CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_SOUND=y -CONFIG_SND=y -# CONFIG_SND_ARM is not set -# CONFIG_SND_SPI is not set -CONFIG_SND_USB_AUDIO=m -CONFIG_SND_USB_UA101=m -CONFIG_SND_USB_CAIAQ=m -CONFIG_SND_USB_6FIRE=m -CONFIG_SND_USB_HIFACE=m -CONFIG_SND_BCD2000=m -CONFIG_SND_USB_POD=m -CONFIG_SND_USB_PODHD=m -CONFIG_SND_USB_TONEPORT=m -CONFIG_SND_USB_VARIAX=m # CONFIG_HID_A4TECH is not set -# CONFIG_HID_APPLE is not set # CONFIG_HID_BELKIN is not set # CONFIG_HID_CHERRY is not set # CONFIG_HID_CHICONY is not set # CONFIG_HID_CYPRESS is not set # CONFIG_HID_EZKEY is not set # CONFIG_HID_KENSINGTON is not set -# CONFIG_HID_LOGITECH is not set # CONFIG_HID_MICROSOFT is not set # CONFIG_HID_MONTEREY is not set CONFIG_USB=y @@ -217,9 +206,6 @@ CONFIG_USB_CONFIGFS_EEM=y CONFIG_USB_CONFIGFS_MASS_STORAGE=y CONFIG_USB_CONFIGFS_F_LB_SS=y CONFIG_USB_CONFIGFS_F_FS=y -CONFIG_USB_CONFIGFS_F_UAC1=y -CONFIG_USB_CONFIGFS_F_UAC2=y -CONFIG_USB_CONFIGFS_F_MIDI=y CONFIG_USB_CONFIGFS_F_HID=y CONFIG_USB_CONFIGFS_F_PRINTER=y CONFIG_USB_ZERO=m @@ -235,15 +221,12 @@ CONFIG_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_MXS=y +CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y CONFIG_LEDS_GPIO=y +CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_TIMER=y -CONFIG_LEDS_TRIGGER_ONESHOT=y -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -CONFIG_LEDS_TRIGGER_BACKLIGHT=y -CONFIG_LEDS_TRIGGER_CPU=y CONFIG_LEDS_TRIGGER_DEFAULT_ON=y -CONFIG_LEDS_TRIGGER_PANIC=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_DS1307=y CONFIG_RTC_DRV_ISL12022=m From c85a6ce9dfb2ac169725e10f3d978faab71f9b1b Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Tue, 11 Jul 2023 12:29:53 -0700 Subject: [PATCH 164/244] ARM: tsimx28: add support for TS-7680 Adds GPIO driver as well as DSA Signed-off-by: Kris Bahnsen --- arch/arm/configs/tsimx28_defconfig | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/arch/arm/configs/tsimx28_defconfig b/arch/arm/configs/tsimx28_defconfig index 51739f09a9d9f..b33e4f4f8edc9 100644 --- a/arch/arm/configs/tsimx28_defconfig +++ b/arch/arm/configs/tsimx28_defconfig @@ -348,9 +348,10 @@ CONFIG_L2TP=m CONFIG_L2TP_V3=y CONFIG_L2TP_IP=m CONFIG_L2TP_ETH=m -CONFIG_BRIDGE=m +CONFIG_BRIDGE=y CONFIG_BRIDGE_VLAN_FILTERING=y CONFIG_BRIDGE_MRP=y +CONFIG_NET_DSA=y CONFIG_VLAN_8021Q=m CONFIG_VLAN_8021Q_GVRP=y CONFIG_VLAN_8021Q_MVRP=y @@ -365,7 +366,7 @@ CONFIG_BATMAN_ADV_NC=y CONFIG_OPENVSWITCH=m CONFIG_VSOCKETS=m CONFIG_NETLINK_DIAG=m -CONFIG_HSR=m +CONFIG_HSR=y CONFIG_CGROUP_NET_PRIO=y CONFIG_BPF_STREAM_PARSER=y CONFIG_CAN=m @@ -378,7 +379,6 @@ CONFIG_BT_BNEP=m CONFIG_BT_BNEP_MC_FILTER=y CONFIG_BT_BNEP_PROTO_FILTER=y CONFIG_BT_HIDP=m -CONFIG_BT_HS=y CONFIG_BT_6LOWPAN=m CONFIG_BT_LEDS=y CONFIG_BT_MSFTEXT=y @@ -446,6 +446,7 @@ CONFIG_TUN=m CONFIG_VETH=m CONFIG_NLMON=m CONFIG_NET_VRF=m +CONFIG_NET_DSA_MV88E6XXX=y # CONFIG_NET_VENDOR_ALACRITECH is not set # CONFIG_NET_VENDOR_AMAZON is not set # CONFIG_NET_VENDOR_AQUANTIA is not set @@ -496,6 +497,8 @@ CONFIG_CAN_KVASER_USB=m CONFIG_CAN_MCBA_USB=m CONFIG_CAN_PEAK_USB=m CONFIG_CAN_UCAN=m +CONFIG_MDIO_BITBANG=y +CONFIG_MDIO_GPIO=y CONFIG_PPP=m CONFIG_PPP_BSDCOMP=m CONFIG_PPP_DEFLATE=m @@ -585,7 +588,7 @@ CONFIG_SPI_GPIO=m CONFIG_SPI_MXS=y CONFIG_SPI_SPIDEV=y CONFIG_PPS_CLIENT_GPIO=m -CONFIG_PTP_1588_CLOCK=m +CONFIG_GPIO_TS4900=y CONFIG_WATCHDOG=y CONFIG_TS_WDT_MICRO=y CONFIG_MFD_MXS_LRADC=m @@ -597,6 +600,15 @@ CONFIG_SND_HRTIMER=m # CONFIG_SND_ARM is not set # CONFIG_SND_SPI is not set CONFIG_SND_USB_AUDIO=m +CONFIG_SND_USB_UA101=m +CONFIG_SND_USB_CAIAQ=m +CONFIG_SND_USB_6FIRE=m +CONFIG_SND_USB_HIFACE=m +CONFIG_SND_BCD2000=m +CONFIG_SND_USB_POD=m +CONFIG_SND_USB_PODHD=m +CONFIG_SND_USB_TONEPORT=m +CONFIG_SND_USB_VARIAX=m # CONFIG_HID_A4TECH is not set # CONFIG_HID_APPLE is not set # CONFIG_HID_BELKIN is not set @@ -704,7 +716,6 @@ CONFIG_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_MXS=y -CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y CONFIG_LEDS_GPIO=y CONFIG_LEDS_TRIGGER_TIMER=y @@ -739,11 +750,12 @@ CONFIG_EXT2_FS_SECURITY=y CONFIG_EXT3_FS=y CONFIG_EXT3_FS_POSIX_ACL=y CONFIG_EXT3_FS_SECURITY=y -CONFIG_F2FS_FS=y +CONFIG_F2FS_FS=m CONFIG_F2FS_FS_SECURITY=y # CONFIG_DNOTIFY is not set CONFIG_FANOTIFY=y CONFIG_AUTOFS_FS=m +CONFIG_FUSE_FS=m CONFIG_OVERLAY_FS=m CONFIG_VFAT_FS=y CONFIG_EXFAT_FS=y @@ -761,6 +773,7 @@ CONFIG_NLS_CODEPAGE_850=y CONFIG_NLS_ISO8859_1=y CONFIG_NLS_ISO8859_15=y CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_CRC32=y CONFIG_CRYPTO_DEFLATE=y CONFIG_CRYPTO_LZO=y CONFIG_CRYPTO_DEV_MXS_DCP=y From 20643f897976c5cb5a747b4d39d645c8c89e2396 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Mon, 26 Jun 2023 13:51:14 -0700 Subject: [PATCH 165/244] ARM: dts: imx28: inital TS-7680 support Signed-off-by: Kris Bahnsen --- arch/arm/boot/dts/nxp/mxs/Makefile | 1 + arch/arm/boot/dts/nxp/mxs/imx28-ts7680.dts | 555 +++++++++++++++++++++ 2 files changed, 556 insertions(+) create mode 100644 arch/arm/boot/dts/nxp/mxs/imx28-ts7680.dts diff --git a/arch/arm/boot/dts/nxp/mxs/Makefile b/arch/arm/boot/dts/nxp/mxs/Makefile index 63c307c12e3e9..b59211c072854 100644 --- a/arch/arm/boot/dts/nxp/mxs/Makefile +++ b/arch/arm/boot/dts/nxp/mxs/Makefile @@ -33,5 +33,6 @@ dtb-$(CONFIG_ARCH_MXS) += \ imx28-ts4600.dtb \ imx28-ts7400v2.dtb \ imx28-ts7670.dtb \ + imx28-ts7680.dtb \ imx28-tx28.dtb \ imx28-xea.dtb diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-ts7680.dts b/arch/arm/boot/dts/nxp/mxs/imx28-ts7680.dts new file mode 100644 index 0000000000000..381300eaedceb --- /dev/null +++ b/arch/arm/boot/dts/nxp/mxs/imx28-ts7680.dts @@ -0,0 +1,555 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (C) 2024 Technologic Systems, Inc. dba embeddedTS + */ + +/dts-v1/; +#include +#include +#include +#include "imx28.dtsi" + + +/ { + + model = "embeddedTS i.MX28 TS-7680 (Default Device Tree)"; + compatible = "fsl,imx28-ts7680", "fsl,imx28"; + + aliases { + mmc0 = &ssp0; + mmc2 = &ssp1; + i2c0 = &i2c0; + mdio-gpio0 = &mdio_gpio; + }; + + memory { + reg = <0x40000000 0x0>; // Filled in by U-Boot + }; + + led-controller { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + + led-0 { + color = ; + function = LED_FUNCTION_POWER; + gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + led-1 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-2 { + color = ; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpio1 26 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-3 { + color = ; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_can_3v3: regulator-can-en@0 { + compatible = "regulator-fixed"; + regulator-name = "CAN_EN"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio3 30 GPIO_ACTIVE_LOW>; + }; + + reg_enet_3v3: regulator-enet-3v3 { + compatible = "regulator-fixed"; + regulator-name = "ENET_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_sd_vmmc: regulator-sd-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd_vmmc>; + regulator-name = "SD_VMMC"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 28 GPIO_ACTIVE_LOW>; + }; + + reg_wl12xx_vmmc: regulator-wl12xx-en { + compatible = "regulator-fixed"; + regulator-name = "WLAN_EN"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio8 44 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; + }; + + mdio_gpio: mdio-gpio { + compatible = "virtual,mdio-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mac0_mdio_gpio>; + gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>, /* mdc */ + <&gpio4 1 GPIO_ACTIVE_HIGH>; /* mdio */ + + #address-cells = <1>; + #size-cells = <0>; + + ethernet-switch@16 { + compatible = "marvell,mv88e6250"; /* mv88e6020 */ + reset-gpios = <&gpio8 43 GPIO_ACTIVE_LOW>; + reset-assert-us = <22000>; + reset-deassert-us = <30000>; + switch-needs-reset; + clocks = <&clks 64>; + clock-names = "switch"; + reg = <16>; + dsa,member = <0 0>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + sw_phy16: ethernet-phy@16 { + reg = <16>; + }; + + sw_phy17: ethernet-phy@17 { + reg = <17>; + }; + }; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + ethernet-port@0 { + reg = <0>; + label = "lan0"; + phy-handle = <&sw_phy16>; + phy-mode = "internal"; + }; + + ethernet-port@1 { + reg = <1>; + label = "lan1"; + phy-handle = <&sw_phy17>; + phy-mode = "internal"; + }; + + ethernet-port@5 { + reg = <5>; + label = "cpu"; + ethernet = <&mac0>; + phy-mode = "rmii"; + + fixed-link { + speed = <100>; + full-duplex; + }; + }; + }; + }; + }; + + fpga_clock { + /* Note that for this to work, modifications to clk-pwm and + * pwm-mxs must be in place to prevent the clock from resetting + * at any point, as well as to fix a math error when running the + * PWM at 12 MHz, which is its uppper limit. + */ + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + clock-output-names = "fpga_12mhz"; + pwms = <&pwm 2 83 0>; // 1 / 83 ns = 12ish MHz + }; +}; + +&auart0 { + pinctrl-names = "default"; + pinctrl-0 = <&auart0_pins_a>; + status = "okay"; + + bluetooth { + compatible = "ti,wl1271-st"; + enable-gpios = <&gpio8 45 GPIO_ACTIVE_HIGH>; + }; +}; + +&auart1 { + pinctrl-names = "default"; + pinctrl-0 = <&auart1_2pins_a>; + status = "okay"; +}; + +&auart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_auart2>; + status = "okay"; +}; + +&auart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_auart3>; + status = "okay"; +}; + +&auart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_auart4>; + status = "okay"; +}; + +&can0 { + pinctrl-names = "default"; + pinctrl-0 = <&can0_pins_a>; + xceiver-supply = <®_can_3v3>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&can1_pins_a>; + xceiver-supply = <®_can_3v3>; + status = "okay"; +}; + +&duart { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_a>; + status = "okay"; +}; + +&gpio1 { + gpio-line-names = "", "", "", "", "", "", "", "HD1_14", "HD1_9", "HD1_7", + "", "", "", "", "", "", "", "", "", "", "PSWITCH", "", "", "", "", + "", "", "EN_HOST_USB_5V"; +}; + +&gpio2 { + gpio-line-names = "", "", "", "", "", "", "", "", "", "POWER_FAIL"; +}; + +&gpio3 { + gpio-line-names = "", "", "", "", "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", + "HD4_21"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + clock-frequency = <100000>; + status = "okay"; + + rtc: m41t00s@68 { + compatible = "m41t00"; + reg = <0x68>; + }; + + gpio8: ts7680gpio@28 { + compatible = "technologic,ts7970-gpio"; + ngpios = <64>; + reg = <0x28>; + #gpio-cells = <2>; + gpio-controller; + + gpio-line-names = "HD4_22", "HD4_23", "HD4_24", "HD4_25", "HD4_26", + "HD4_27", "HD4_28", "HD4_29", "HD4_30", "HD4_31", "HD4_32", + "HD4_33", "HD4_34", "HD4_35", "", "HD4_13/T_4 LS Out", + "HD4_11/T_5 LS Out", "HD4_9/T_6 LS Out", "RELAY1", "RELAY2", + "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", + "AD0_PU#", "AD1_PU#", "AD2_PU#", "AD3_PU#", "AD01_CL", + "AD23_CL", "EN_DC_5V"; + }; + + silabs: silabs@78 { + compatible = "ts-wdt"; + reg = <0x78>; + timeout-sec = <500>; + enable-early; + }; + + accel: mma8451@1c { + compatible = "fsl,mma8451"; + reg = <0x1c>; + position = <0>; + vdd-supply = <®_3v3>; + vddio-supply = <®_3v3>; + interrupt-parent = <&gpio0>; + interrupts = <20 6>; + interrupt-route = <1>; + }; +}; + +&lradc { + status = "okay"; +}; + +&mac0 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mac0>; + phy-supply = <®_enet_3v3>; + status = "okay"; + + fixed-link { + speed = <100>; + full-duplex; + }; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + reg = <0>; + fsl,pinmux-ids = < + //USB 5V EN + MX28_PAD_LCD_CS__GPIO_1_27 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + pinctrl_auart2: auart2grp { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP2_SCK__AUART2_RX + MX28_PAD_SSP2_MOSI__AUART2_TX + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + pinctrl_auart3: auart3grp { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP2_MISO__AUART3_RX + MX28_PAD_SSP2_SS0__AUART3_TX + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + pinctrl_auart4: auart4grp { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SAIF0_BITCLK__AUART4_RX + MX28_PAD_SAIF0_SDATA0__AUART4_TX + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + pinctrl_flexcan_3v3: en-cangrp { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_RESET__GPIO_3_30 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + pinctrl_gpio_leds: gpio-ledgrp { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_D05__GPIO_0_5 + MX28_PAD_GPMI_D07__GPIO_0_7 + MX28_PAD_LCD_RS__GPIO_1_26 + MX28_PAD_LCD_RD_E__GPIO_1_24 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + pinctrl_mac0: mac0grp { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_ENET0_RX_EN__ENET0_RX_EN + MX28_PAD_ENET0_RXD0__ENET0_RXD0 + MX28_PAD_ENET0_RXD1__ENET0_RXD1 + MX28_PAD_ENET0_TX_EN__ENET0_TX_EN + MX28_PAD_ENET0_TXD0__ENET0_TXD0 + MX28_PAD_ENET0_TXD1__ENET0_TXD1 + MX28_PAD_ENET_CLK__CLKCTRL_ENET + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + pinctrl_mac0_mdio_gpio: mac0-mdiogrp { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_ENET0_MDC__GPIO_4_0 + MX28_PAD_ENET0_MDIO__GPIO_4_1 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsp,pull-up = ; + }; + + pinctrl_mmc0_4bit: mmc0-4bitgrp { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP0_DATA0__SSP0_D0 + MX28_PAD_SSP0_DATA1__SSP0_D1 + MX28_PAD_SSP0_DATA2__SSP0_D2 + MX28_PAD_SSP0_DATA3__SSP0_D3 + MX28_PAD_SSP0_CMD__SSP0_CMD + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + pinctrl_mmc1_4bit: mmc1-4bitgrp { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_RDY1__SSP1_CMD + MX28_PAD_GPMI_D00__SSP1_D0 + MX28_PAD_GPMI_D01__SSP1_D1 + MX28_PAD_GPMI_D02__SSP1_D2 + MX28_PAD_GPMI_D03__SSP1_D3 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + pinctrl_mmc2_4bit: mmc2-4bitgrp { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP0_DATA4__SSP2_D0 + MX28_PAD_SSP2_SS1__SSP2_D1 + MX28_PAD_SSP2_SS2__SSP2_D2 + MX28_PAD_SSP0_DATA5__SSP2_D3 + MX28_PAD_SSP0_DATA6__SSP2_CMD + MX28_PAD_LCD_D22__GPIO_1_22 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + pinctrl_mmc2_sck: mmc2-sckgrp { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP0_DATA7__SSP2_SCK + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + pinctrl_sd_vmmc: sd-vmmcgrp { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_PWM3__GPIO_3_28 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_pins_a>; + status = "okay"; +}; + +&ssp0 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc0_4bit + &mmc0_sck_cfg>; /* in DTSI */ + bus-width = <4>; + broken-cd; + disable-wp; + vmmc-supply = <®_sd_vmmc>; + status = "okay"; +}; + +&ssp1 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc1_4bit + &mmc1_sck_cfg>; /* in DTSI */ + bus-width = <4>; + broken-cd; + disable-wp; + vmmc-supply = <®_3v3>; + status = "okay"; +}; + +&ssp2 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc2_4bit + &pinctrl_mmc2_sck>; + vmmc-supply = <®_wl12xx_vmmc>; + bus-width = <4>; + non-removable; + cap-power-off-card; + status = "okay"; + + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + reg = <2>; + interrupt-parent = <&gpio1>; + interrupts = <22 IRQ_TYPE_EDGE_RISING>; + ref-clock-frequency = <38400000>; + }; +}; + +&usb0 { + disable-over-current; + dr_mode = "host"; + status = "okay"; +}; + +&usb1 { + disable-over-current; + dr_mode = "host"; + status = "okay"; +}; + +&usbphy0 { + status = "okay"; +}; + +&usbphy1 { + status = "okay"; +}; From b2e698417463394de6523522b44133383f1f809b Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Wed, 14 Aug 2024 08:39:14 -0700 Subject: [PATCH 166/244] ARM: dts: imx6qdl-ts7990: Replace ISM330DLCTR with ISM330DHCXTR --- arch/arm/boot/dts/nxp/imx/imx6qdl-ts7990.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7990.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7990.dtsi index f7f48d9e5ed47..e49bd967c1f95 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7990.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7990.dtsi @@ -329,7 +329,7 @@ /* Only present on REV E and above */ ism330: gyro@6a { - compatible = "st,ism330dlc"; + compatible = "st,ism330dhcx"; reg = <0x6a>; interrupt-parent = <&gpio3>; interrupts = <15 IRQ_TYPE_LEVEL_HIGH>; From bb2715ba72dfc126c62510bac44996f7d99ed1d7 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Fri, 16 Aug 2024 19:29:31 +0000 Subject: [PATCH 167/244] ARM: configs: tsimx6ul: Add IMU support as modules Needed on TS-7553-V2 Signed-off-by: Kris Bahnsen --- arch/arm/configs/tsimx6ul_defconfig | 2 ++ arch/arm/configs/tsimx6ul_minimal_defconfig | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm/configs/tsimx6ul_defconfig b/arch/arm/configs/tsimx6ul_defconfig index 956896ab6048f..b11bd878a1c82 100644 --- a/arch/arm/configs/tsimx6ul_defconfig +++ b/arch/arm/configs/tsimx6ul_defconfig @@ -839,8 +839,10 @@ CONFIG_TS_SIMPLEADC=y CONFIG_TS_SUPERVISOR_ADC=y CONFIG_VF610_ADC=y CONFIG_IIO_RESCALE=m +CONFIG_INV_MPU6050_I2C=m CONFIG_IIO_ST_LSM6DSX=m CONFIG_SENSORS_ISL29018=y +CONFIG_AK8975=m CONFIG_MAG3110=y CONFIG_IIO_ST_MAGN_3AXIS=m CONFIG_IIO_SYSFS_TRIGGER=m diff --git a/arch/arm/configs/tsimx6ul_minimal_defconfig b/arch/arm/configs/tsimx6ul_minimal_defconfig index 08ea9fbd54978..731954f3b00c8 100644 --- a/arch/arm/configs/tsimx6ul_minimal_defconfig +++ b/arch/arm/configs/tsimx6ul_minimal_defconfig @@ -296,8 +296,10 @@ CONFIG_TS_SIMPLEADC=y CONFIG_TS_SUPERVISOR_ADC=y CONFIG_VF610_ADC=y CONFIG_IIO_RESCALE=m +CONFIG_INV_MPU6050_I2C=m CONFIG_IIO_ST_LSM6DSX=m CONFIG_SENSORS_ISL29018=y +CONFIG_AK8975=m CONFIG_MAG3110=y CONFIG_IIO_ST_MAGN_3AXIS=m CONFIG_IIO_SYSFS_TRIGGER=m From 3b015b326651aaf03da96a763202a1e03420e7b8 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Fri, 16 Aug 2024 19:41:06 +0000 Subject: [PATCH 168/244] ARM: configs: tsimx28: Add cpufreq governor Signed-off-by: Kris Bahnsen --- arch/arm/configs/tsimx28_defconfig | 4 ++++ arch/arm/configs/tsimx28_minimal_defconfig | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/arch/arm/configs/tsimx28_defconfig b/arch/arm/configs/tsimx28_defconfig index b33e4f4f8edc9..067324e642a3b 100644 --- a/arch/arm/configs/tsimx28_defconfig +++ b/arch/arm/configs/tsimx28_defconfig @@ -32,6 +32,10 @@ CONFIG_HZ_1000=y CONFIG_AEABI=y CONFIG_HIGHMEM=y CONFIG_EFI=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y CONFIG_MODULES=y CONFIG_MODULE_FORCE_LOAD=y CONFIG_MODULE_UNLOAD=y diff --git a/arch/arm/configs/tsimx28_minimal_defconfig b/arch/arm/configs/tsimx28_minimal_defconfig index 2ee068ac41b8c..6b8ebd1fcbacd 100644 --- a/arch/arm/configs/tsimx28_minimal_defconfig +++ b/arch/arm/configs/tsimx28_minimal_defconfig @@ -19,6 +19,10 @@ CONFIG_ARCH_MXS=y CONFIG_HZ_1000=y CONFIG_AEABI=y CONFIG_HIGHMEM=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y CONFIG_MODULES=y CONFIG_MODULE_FORCE_LOAD=y CONFIG_MODULE_UNLOAD=y From 29298389c8355c624b7c308b8530a44f250251b5 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Sat, 17 Aug 2024 00:39:17 +0000 Subject: [PATCH 169/244] ARM: configs: tsimx6ul: Add UART GNSS support for TS-7180 Signed-off-by: Kris Bahnsen --- arch/arm/configs/tsimx6ul_defconfig | 2 ++ arch/arm/configs/tsimx6ul_minimal_defconfig | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm/configs/tsimx6ul_defconfig b/arch/arm/configs/tsimx6ul_defconfig index b11bd878a1c82..e698f39f544e9 100644 --- a/arch/arm/configs/tsimx6ul_defconfig +++ b/arch/arm/configs/tsimx6ul_defconfig @@ -444,6 +444,8 @@ CONFIG_EXTRA_FIRMWARE_DIR="firmware" CONFIG_IMX_WEIM=y CONFIG_TSPC104=y CONFIG_CONNECTOR=y +CONFIG_GNSS=y +CONFIG_GNSS_NMEA_SERIAL=y CONFIG_MTD=y # CONFIG_MTD_OF_PARTS is not set CONFIG_MTD_BLOCK=y diff --git a/arch/arm/configs/tsimx6ul_minimal_defconfig b/arch/arm/configs/tsimx6ul_minimal_defconfig index 731954f3b00c8..36a8284956f4e 100644 --- a/arch/arm/configs/tsimx6ul_minimal_defconfig +++ b/arch/arm/configs/tsimx6ul_minimal_defconfig @@ -68,6 +68,8 @@ CONFIG_EXTRA_FIRMWARE_DIR="firmware" CONFIG_IMX_WEIM=y CONFIG_TSPC104=y CONFIG_CONNECTOR=y +CONFIG_GNSS=y +CONFIG_GNSS_NMEA_SERIAL=y CONFIG_MTD=y # CONFIG_MTD_OF_PARTS is not set CONFIG_MTD_BLOCK=y From e950d4726c560ed5c4cfb84b940e88698b39fef2 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Sat, 17 Aug 2024 00:39:49 +0000 Subject: [PATCH 170/244] ARM: dts: imx6ul: ts7180: Configure UART GNSS Signed-off-by: Kris Bahnsen --- arch/arm/boot/dts/nxp/imx/imx6ul-ts7180.dts | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7180.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7180.dts index 0c422e5d2e3a6..4bb207fdb5e16 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7180.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7180.dts @@ -100,7 +100,16 @@ regulator-name = "CAN_EN"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&gpio6 20 GPIO_ACTIVE_HIGH>; + gpio = <&gpio6 20 GPIO_ACTIVE_LOW>; + }; + + reg_gps_3v3: regulator-gps-3v3 { + compatible = "regulator-fixed"; + regulator-name = "GPS_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio6 19 GPIO_ACTIVE_HIGH>; + enable-active-high; }; }; @@ -710,6 +719,13 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart8>; status = "okay"; + + gnss { + compatible = "gnss,nmea-serial"; + current-speed = <9600>; + vcc-supply = <®_gps_3v3>; + timepulse-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + }; }; &usbotg1 { From e8c9fda6a93141ab9c1f431d0ad5413e2836dd1a Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Thu, 22 Aug 2024 09:45:49 -0700 Subject: [PATCH 171/244] ARM: dts: imx6: Fix polarity of tsc2046/ads7843 pendown Fixed on TS-TPC-8390 / TS-TPC-8950 / TS-TPC-7990 --- arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900-ts8390.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900-ts8950.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/imx6qdl-ts7990.dtsi | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900-ts8390.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900-ts8390.dtsi index 1bde3a9011aec..4d92b34386eab 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900-ts8390.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900-ts8390.dtsi @@ -165,7 +165,7 @@ interrupts = <11 IRQ_TYPE_EDGE_FALLING>; vcc-supply = <®_3v3>; spi-max-frequency = <100000>; - pendown-gpio = <&gpio3 11 GPIO_ACTIVE_HIGH>; + pendown-gpio = <&gpio3 11 GPIO_ACTIVE_LOW>; touchscreen-swapped-x-y; ti,vref-mv = /bits/ 16 <3300>; ti,keep-vref-on; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900-ts8950.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900-ts8950.dtsi index 5505b934c84b0..1eaafb1f73d76 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900-ts8950.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900-ts8950.dtsi @@ -144,7 +144,7 @@ interrupt-parent = <&gpio4>; interrupts = <25 IRQ_TYPE_EDGE_FALLING>; spi-max-frequency = <2000000>; - pendown-gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; + pendown-gpio = <&gpio4 25 GPIO_ACTIVE_LOW>; vcc-supply = <®_3v3>; ti,swap-xy; ti,keep-vref-on; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7990.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7990.dtsi index e49bd967c1f95..94683d1abf198 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7990.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7990.dtsi @@ -137,7 +137,7 @@ interrupts = <12 IRQ_TYPE_EDGE_FALLING>; vcc-supply = <®_3v3>; spi-max-frequency = <100000>; - pendown-gpio = <&gpio3 12 0>; + pendown-gpio = <&gpio3 12 GPIO_ACTIVE_LOW>; ti,penirq-recheck-delay-usecs = /bits/ 16 <5000>; ti,vref-mv = <3300>; ti,swap-xy; From 58926ca3ad4bbbf39d6252ff178e99375d926aef Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Mon, 30 Sep 2024 18:40:49 +0000 Subject: [PATCH 172/244] drivers: mmc: tssdcard: fix rare oops on startup On rare instances, an oops would occur that originated deep within slab allocation. It appeared to be a race condition that looks like it was caused by some improper function arguments and calls. This removes calls to register_blkdev (no longer needed) and passes correct args to blk_alloc_disk. Signed-off-by: Kris Bahnsen --- drivers/mmc/host/tssdcard.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/mmc/host/tssdcard.c b/drivers/mmc/host/tssdcard.c index c9143f22b3cd4..27bdaf84d591b 100644 --- a/drivers/mmc/host/tssdcard.c +++ b/drivers/mmc/host/tssdcard.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include @@ -79,7 +78,6 @@ struct tssdcard_dev { unsigned long lasttimeout; int cardpresent; int lasterr; - int major; }; struct tssdcard_host { @@ -426,7 +424,7 @@ static void tssdcard_alloc_disk(struct tssdcard_dev *dev) { dev->bio = dev->biotail = NULL; - dev->gd = blk_alloc_disk(CONFIG_MMC_BLOCK_MINORS); + dev->gd = blk_alloc_disk(NUMA_NO_NODE); if (dev->gd == NULL) { pr_err(DRIVER_NAME ": Failed to alloc_disk"); return; @@ -500,7 +498,6 @@ static int setup_device(struct tssdcard_host *host, int lun) dev->tssdcore.sd_writeparking = 1; dev->tssdcore.debug = tssdcard_debug; dev->tssdcore.debug_arg = dev; - dev->major = register_blkdev(UNNAMED_MAJOR, DRIVER_NAME); dev->devname = kmalloc(32, GFP_KERNEL); if (!dev->devname) @@ -586,7 +583,6 @@ static int tssdcard_remove(struct platform_device *pdev) if (dev->gd) put_disk(dev->gd); - unregister_blkdev(NBD_MAJOR, "nbd"); kfree(dev->devname); } return 0; From 0a999cc6b6d0744b73db70f7a8d5d1d8c9c3ff1a Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Tue, 1 Oct 2024 22:37:30 +0000 Subject: [PATCH 173/244] video: st7565p: port from 5.10 with fixups for building Signed-off-by: Kris Bahnsen --- drivers/video/fbdev/ts-st7565p-fb.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/video/fbdev/ts-st7565p-fb.c b/drivers/video/fbdev/ts-st7565p-fb.c index f6a391f297a89..6fd0d762cd225 100644 --- a/drivers/video/fbdev/ts-st7565p-fb.c +++ b/drivers/video/fbdev/ts-st7565p-fb.c @@ -408,7 +408,9 @@ static int st7565p_mmap(struct fb_info *info, size = 0; } - vma->vm_flags |= (VM_DONTEXPAND | VM_DONTDUMP); /* avoid to swap out this VMA */ + /* Avoid swapping out this VMA */ + vm_flags_set(vma, (VM_DONTEXPAND | VM_DONTDUMP)); + return 0; } @@ -469,7 +471,6 @@ static int __init st7565p_probe(struct platform_device *dev) info->fix = st7565p_fix; info->pseudo_palette = info->par; info->par = NULL; - info->flags = FBINFO_FLAG_DEFAULT; retval = fb_alloc_cmap(&info->cmap, 256, 0); if (retval < 0) @@ -493,7 +494,7 @@ static int __init st7565p_probe(struct platform_device *dev) return retval; } -static int st7565p_remove(struct platform_device *dev) +static void st7565p_remove(struct platform_device *dev) { struct fb_info *info = platform_get_drvdata(dev); @@ -502,7 +503,6 @@ static int st7565p_remove(struct platform_device *dev) rvfree(videomemory, videomemorysize); framebuffer_release(info); } - return 0; } static struct platform_driver st7565p_driver = { From 5c547cacd130501f07d13afb20e4b2f17a0d0e6c Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Tue, 1 Oct 2024 22:38:50 +0000 Subject: [PATCH 174/244] ARM: configs: tsimx6ul: support st7565p LCD Signed-off-by: Kris Bahnsen --- arch/arm/configs/tsimx6ul_defconfig | 5 ++--- arch/arm/configs/tsimx6ul_minimal_defconfig | 4 ++-- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/arch/arm/configs/tsimx6ul_defconfig b/arch/arm/configs/tsimx6ul_defconfig index e698f39f544e9..cdcb2ce3e6e58 100644 --- a/arch/arm/configs/tsimx6ul_defconfig +++ b/arch/arm/configs/tsimx6ul_defconfig @@ -407,7 +407,6 @@ CONFIG_BT_BNEP=m CONFIG_BT_BNEP_MC_FILTER=y CONFIG_BT_BNEP_PROTO_FILTER=y CONFIG_BT_HIDP=m -CONFIG_BT_HS=y CONFIG_BT_6LOWPAN=m CONFIG_BT_LEDS=y CONFIG_BT_MSFTEXT=y @@ -702,11 +701,11 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_ANATOP=y CONFIG_REGULATOR_GPIO=y CONFIG_DRM=y -CONFIG_DRM_FBDEV_EMULATION=y CONFIG_DRM_PANEL_LVDS=y CONFIG_DRM_PANEL_SIMPLE=y CONFIG_DRM_MXSFB=y -CONFIG_FB_DEVICE=y +CONFIG_FB=y +CONFIG_FB_ST7565P=m CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_PLATFORM=y CONFIG_BACKLIGHT_CLASS_DEVICE=y diff --git a/arch/arm/configs/tsimx6ul_minimal_defconfig b/arch/arm/configs/tsimx6ul_minimal_defconfig index 36a8284956f4e..a13760877a7d2 100644 --- a/arch/arm/configs/tsimx6ul_minimal_defconfig +++ b/arch/arm/configs/tsimx6ul_minimal_defconfig @@ -229,11 +229,11 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_ANATOP=y CONFIG_REGULATOR_GPIO=y CONFIG_DRM=y -CONFIG_DRM_FBDEV_EMULATION=y CONFIG_DRM_PANEL_LVDS=y CONFIG_DRM_PANEL_SIMPLE=y CONFIG_DRM_MXSFB=y -CONFIG_FB_DEVICE=y +CONFIG_FB=y +CONFIG_FB_ST7565P=m CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_PLATFORM=y CONFIG_BACKLIGHT_CLASS_DEVICE=y From 9a81a1c9039c052a948a15f1bd1b69833d5aa607 Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Thu, 16 Jan 2025 21:35:35 -0700 Subject: [PATCH 175/244] dts: armada-385-ts7800-v2: correct base compatible vendor --- arch/arm/boot/dts/marvell/armada-385-ts7800-v2.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/marvell/armada-385-ts7800-v2.dts b/arch/arm/boot/dts/marvell/armada-385-ts7800-v2.dts index be4a7cba23ff7..bbea310e8e90f 100644 --- a/arch/arm/boot/dts/marvell/armada-385-ts7800-v2.dts +++ b/arch/arm/boot/dts/marvell/armada-385-ts7800-v2.dts @@ -12,7 +12,7 @@ / { model = "embeddedTS TS-7800-V2"; - compatible = "embeddedts,a385-ts7800-v2", "marvell,armada385", "marvell,armada380"; + compatible = "technologic,a385-ts7800-v2", "marvell,armada385", "marvell,armada380"; aliases { ethernet0 = ð0; From b9db58d047bd3dbf88859ff5dce89ad2f226106a Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Fri, 7 Feb 2025 12:23:15 -0700 Subject: [PATCH 176/244] ARM: dts: imx6ul-tscustom-0: initial commit --- arch/arm/boot/dts/nxp/imx/Makefile | 1 + .../boot/dts/nxp/imx/imx6ul-tscustom-0.dts | 573 ++++++++++++++++++ 2 files changed, 574 insertions(+) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-tscustom-0.dts diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx/Makefile index c499ce6a55731..2df173db33064 100644 --- a/arch/arm/boot/dts/nxp/imx/Makefile +++ b/arch/arm/boot/dts/nxp/imx/Makefile @@ -361,6 +361,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ul-ts7100-1.dtb \ imx6ul-ts7100-3.dtb \ imx6ul-ts7180.dtb \ + imx6ul-tscustom-0.dtb \ imx6ul-tx6ul-0010.dtb \ imx6ul-tx6ul-0011.dtb \ imx6ul-tx6ul-mainboard.dtb \ diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-tscustom-0.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-tscustom-0.dts new file mode 100644 index 0000000000000..84812fb8a94b9 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-tscustom-0.dts @@ -0,0 +1,573 @@ +/* + * Copyright (C) 2020-2022 Technologic Systems, Inc. dba embeddedTS + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; +#include +#include +#include "imx6ul.dtsi" + +/ { + model = "embeddedTS i.MX6UL TS Custom 0"; + compatible = "technologic,tscustom0", "fsl,imx6ul"; + + aliases { + ethernet0 = &fec2; + ethernet1 = &fec1; + i2c0 = &i2c1gpio; + i2c1 = &i2c2gpio; + }; + + chosen { + stdout-path = &uart1; + }; + + memory { + reg = <0x80000000 0x20000000>; + }; + + i2c1gpio: i2c1gpio { + compatible = "i2c-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_gpio>; + gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>, /* sda */ + <&gpio1 2 GPIO_ACTIVE_HIGH>; /* scl */ + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + rtc: m41t00s@68 { + compatible = "m41t00"; + reg = <0x68>; + }; + + silabs: silabs@54 { + compatible = "technologic,ts7100-wdt"; + enable-early; + /* 5min timeout default, in case of slow userspace. + * Set to 0 to disable WDT at startup. Userspace procs + * can still start feeding later. + */ + timeout-sec = <300>; + reg = <0x54>; + }; + }; + + i2c2gpio: i2c2gpio { + compatible = "i2c-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2gpio>; + gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>, /* sda */ + <&gpio1 0 GPIO_ACTIVE_HIGH>; /* scl */ + i2c-gpio,delay-us = <2>; /* 100khz*/ + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + }; + + leds { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + compatible = "gpio-leds"; + + led-0 { + color = ; + function = LED_FUNCTION_POWER; + gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + led-1 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-2 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-3 { + color = ; + function = LED_FUNCTION_FAULT; + gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; + default-state = "off"; + /* panic-indicator; */ + }; + + led-4 { + color = ; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-5 { + color = ; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + /* The following are meant to be userspace controlled IO. The + * kernel does not allow setting default state of GPIO, but + * the default state of LEDs can be set, which is why the LED + * subsystem is used. + */ + en-oled-3v3 { + label = "en-oled-3v3"; + gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + en-usb-5v { + label = "en-usb-5v"; + gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + en-rf-24v { + label = "en-rf-24v"; + gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + en-iso485-term { + label = "en-iso485-term"; + gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x14000000>; + linux,cma-default; + }; + }; + + + reg_enet_3v3: regulator-phy@0 { + compatible = "regulator-fixed"; + regulator-name = "enet_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_gpio_dvfs: regulator-gpio { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dvfs>; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1400000>; + regulator-name = "gpio_dvfs"; + regulator-type = "voltage"; + gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; + states = <1300000 0x1 1400000 0x0>; + }; + + reg_sd1_vmmc: sd1_vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +&ecspi2 { + num-cs = <1>; + cs-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + status = "okay"; + + spinor: spi@0 { + compatible = "issi,is25lp064", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <18000000>; + }; +}; + +&ecspi3 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + status = "okay"; + + wilc_spi@0 { + compatible = "microchip,wilc1000", "microchip,wilc3000"; + reg = <0>; + spi-max-frequency = <18000000>; + reset-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; + chip_en-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio1>; + interrupts = <11 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&ecspi4 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4>; + status = "okay"; + + /* OLED is on this bus */ + spidevlcd: spi@0 { + compatible = "spidev"; + reg = <0>; + spi-max-frequency = <5000000>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + phy-supply = <®_3v3>; + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + phy-supply = <®_3v3>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@2 { + clocks = <&clks IMX6UL_CLK_ENET_REF>; + clock-names = "rmii-ref"; + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + }; + + ethphy1: ethernet-phy@1 { + clocks = <&clks IMX6UL_CLK_ENET2_REF>; + clock-names = "rmii-ref"; + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx6ul-ts7180 { + pinctrl_hog: hoggrp { + fsl,pins = < + /* + * All GPIO should be 0x1b020 unless special + * 0x1b020 == Hyst., 100k PU, 50 mA drive + * 0x1a020 == no pull resistor + * 0x13020 == 100k PD + */ + MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x1b020 + MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x1b020 + MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x1b020 + /* DETECT_9471 */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x1b020 + /* POWER_FAIL */ + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b020 + /* Add silab clk, data, en_prog */ + /* Add strap pins! */ + + /* RES_STRAP_0 */ + MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x1b020 + /* RES_STRAP_1 */ + MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x1b020 + /* RES_STRAP_2 */ + MX6UL_PAD_LCD_DATA22__GPIO3_IO27 0x1b020 + /* RES_STRAP_3 */ + MX6UL_PAD_LCD_DATA23__GPIO3_IO28 0x1b020 + >; + }; + + pinctrl_gpio_leds: gpioledgrp { + fsl,pins = < + /* Red LED */ + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x1b020 + /* Green LED */ + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x1b020 + /* Status LED */ + MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x1b020 + /* Fault LED */ + MX6UL_PAD_LCD_DATA13__GPIO3_IO18 0x1b020 + /* RS-485 LED */ + MX6UL_PAD_LCD_DATA14__GPIO3_IO19 0x1b020 + /* Eth SPD LED (unused) */ + MX6UL_PAD_LCD_DATA15__GPIO3_IO20 0x1b020 + + /* En. OLED 3.3 V */ + MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0x1b020 + /* En. Host USB 5 V (unused) */ + MX6UL_PAD_LCD_DATA09__GPIO3_IO14 0x1b020 + /* En. RF Switched 24 V */ + MX6UL_PAD_LCD_DATA05__GPIO3_IO10 0x1b020 + /* En. ISO485 Termination */ + MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x1b020 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1 + MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 + MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 + MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1 + MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1 + MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1 + /* TXEN */ + MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b0b1 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x1f0b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x4001a8b0 + MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x4001a8b0 + >; + }; + + pinctrl_i2c1_gpio: i2c1grpgpio { + fsl,pins = < + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x4001a8b0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x4001a8b0 + >; + }; + + pinctrl_i2c2gpio: i2c2grpgpio { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x4001a8b0 + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x4001a8b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + >; + }; + + pinctrl_ecspi2: exspi2grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x1b020 + MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x1b020 + MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x1b020 + + /* SPI flash CS# */ + MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x1b020 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6UL_PAD_NAND_CE0_B__ECSPI3_SCLK 0x1b020 + MX6UL_PAD_NAND_CE1_B__ECSPI3_MOSI 0x1b020 + MX6UL_PAD_NAND_CLE__ECSPI3_MISO 0x1b820 + /* WIFI_CS# CS0 */ + MX6UL_PAD_NAND_READY_B__GPIO4_IO12 0x1b020 + + /* WIFI_IRQ# */ + MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x1b020 + /* CHIP_EN (EN_WIFI_PWR) */ + MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x1b020 + /* WIFI_RESET# */ + MX6UL_PAD_LCD_DATA08__GPIO3_IO13 0x1b020 + >; + }; + + pinctrl_ecspi4: ecspi4grp { + fsl,pins = < + MX6UL_PAD_NAND_DATA04__ECSPI4_SCLK 0x1b020 + MX6UL_PAD_NAND_DATA05__ECSPI4_MOSI 0x1b020 + MX6UL_PAD_NAND_DATA06__ECSPI4_MISO 0x1b020 + + /* OLED CS# */ + MX6UL_PAD_NAND_DATA07__GPIO4_IO09 0x1b020 + >; + }; + + pinctrl_dvfs: dvfsgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0a0 + >; + }; + }; +}; + +&snvs_rtc { + status = "disabled"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* RF */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + status = "okay"; +}; + +/* BT */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +/* RS-485 */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + rts-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; + linux,rs485-enabled-at-boot-time; + uart-has-rtscts; + dma-names = "", ""; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "device"; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +/* eMMC */ +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + no-1-8-v; + disable-wp; + non-removable; + bus-width = <4>; + status = "okay"; +}; + +/* SD */ +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + no-1-8-v; + disable-wp; + broken-cd = <1>; + bus-width = <4>; + status = "okay"; +}; + +/* WDT is in the uC, but we need to explicitly disable CPU WDT */ +&wdog1 { + status = "disabled"; +}; From db1516e57339b7e083e082381ef1434a28ab82cc Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Fri, 14 Feb 2025 00:27:48 +0000 Subject: [PATCH 177/244] ARM: tsimx28: add SMSC PHY as builtin This allows the PHY clock to be enabled early and remain enabled even when the interface is brought down. Signed-off-by: Kris Bahnsen --- arch/arm/configs/tsimx28_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/tsimx28_defconfig b/arch/arm/configs/tsimx28_defconfig index 067324e642a3b..304208f76e565 100644 --- a/arch/arm/configs/tsimx28_defconfig +++ b/arch/arm/configs/tsimx28_defconfig @@ -489,6 +489,7 @@ CONFIG_NET_DSA_MV88E6XXX=y # CONFIG_NET_VENDOR_WIZNET is not set # CONFIG_NET_VENDOR_XILINX is not set CONFIG_MICROCHIP_PHY=m +CONFIG_SMSC_PHY=y CONFIG_CAN_VCAN=m CONFIG_CAN_VXCAN=m CONFIG_CAN_FLEXCAN=m From 9da09ea3db661e77e033b7c3e06231707431e7d5 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Fri, 14 Feb 2025 23:23:26 +0000 Subject: [PATCH 178/244] ARM: tsimx28: add TTY ledtrig as module Useful for the LED labeled as MODBUS Signed-off-by: Kris Bahnsen --- arch/arm/configs/tsimx28_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/tsimx28_defconfig b/arch/arm/configs/tsimx28_defconfig index 304208f76e565..b395e4373f8bf 100644 --- a/arch/arm/configs/tsimx28_defconfig +++ b/arch/arm/configs/tsimx28_defconfig @@ -734,6 +734,7 @@ CONFIG_LEDS_TRIGGER_TRANSIENT=m CONFIG_LEDS_TRIGGER_PANIC=y CONFIG_LEDS_TRIGGER_NETDEV=m CONFIG_LEDS_TRIGGER_PATTERN=m +CONFIG_LEDS_TRIGGER_TTY=m CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_DS1307=y CONFIG_RTC_DRV_ISL12022=m From 742b9dc32196ea7913dafec8926f37e55a370cc2 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Mon, 17 Feb 2025 23:12:00 +0000 Subject: [PATCH 179/244] ARM: dts: imx28-ts7400v2: make i2c0 GPIO While not an issue with function, using the hardware I2C controller here would cause a handful of kernel warnings on shutdown due to the driver not having an atomic handler. Since the WDT via I2C is involved in halt and reboot, using the peripheral driver would work but would generate those warnings. The move to using GPIO pins is mostly aesthetic so as to not have that warning on halt/reboot. Signed-off-by: Kris Bahnsen --- arch/arm/boot/dts/nxp/mxs/imx28-ts7400v2.dts | 83 ++++++++++++-------- 1 file changed, 50 insertions(+), 33 deletions(-) diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-ts7400v2.dts b/arch/arm/boot/dts/nxp/mxs/imx28-ts7400v2.dts index a0855f3981184..dd3410eaca443 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-ts7400v2.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-ts7400v2.dts @@ -13,13 +13,48 @@ model = "embeddedTS i.MX28 TS-7400-V2 (Default Device Tree)"; compatible = "fsl,imx28-ts7400v2", "fsl,imx28"; + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x08000000>; /* 128MB */ + }; + aliases { spi0 = &ssp2; - i2c0 = &i2c0; + i2c0 = &i2c0_gpio; }; - memory { - reg = <0x40000000 0x08000000>; /* 128MB */ + i2c0_gpio: i2c { + compatible = "i2c-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_gpio>; + #address-cells = <1>; + #size-cells = <0>; + scl-gpios = <&gpio3 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio3 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + clock-frequency = <100000>; + + isl12022: rtc@6f { + compatible = "isil,isl12022"; + btse-minutes = <1>; + isil,battery-trip-levels-microvolt = <2550000>, <2250000>; + reg = <0x6f>; + }; + + isl12022_sram: eeprom@57 { + compatible = "atmel,24c01"; + reg = <0x57>; + label = "isl12022-SRAM"; + pagesize = <128>; + size = <128>; + address-width = <8>; + }; + + silabs: watchdog@78 { + compatible = "ts-wdt"; + timeout-sec = <500>; + enable-early; + reg = <0x78>; + }; }; led-controller { @@ -158,36 +193,6 @@ "I2S_TXD", "I2C_CLK", "I2C_DAT", "I2S_RXD", "", "", "DIO_15"; }; -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - clock-frequency = <100000>; - status = "okay"; - - isl12022: rtc@6f { - compatible = "isil,isl12022"; - btse-minutes = <1>; - isil,battery-trip-levels-microvolt = <2550000>, <2250000>; - reg = <0x6f>; - }; - - isl12022_sram: eeprom@57 { - compatible = "atmel,24c01"; - reg = <0x57>; - label = "isl12022-SRAM"; - pagesize = <128>; - size = <128>; - address-width = <8>; - }; - - silabs: watchdog@78 { - compatible = "ts-wdt"; - timeout-sec = <500>; - enable-early; - reg = <0x78>; - }; -}; - &lradc { status = "okay"; }; @@ -243,6 +248,18 @@ fsl,pull-up = ; }; + i2c0_pins_gpio: i2c-gpio-pins@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_I2C0_SCL__GPIO_3_24 + MX28_PAD_I2C0_SDA__GPIO_3_25 + >; + fsl,drive-strength = ; + fsl,voltage = ; + /* This pin uses PULL_DISABLE == 0 == Enable Keeper */ + fsl,pull-up = ; + }; + mmc0_4bit_pins: mmc0-4bit@0 { reg = <0>; fsl,pinmux-ids = < From 3cb54dcfb29bf20e12cdc35afe3afa5a7e343267 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Tue, 18 Feb 2025 18:54:09 +0000 Subject: [PATCH 180/244] ARM: dts: imx28-ts7680: make i2c0 GPIO While not an issue with function, using the hardware I2C controller here would cause a handful of kernel warnings on shutdown due to the driver not having an atomic handler. Since the WDT via I2C is involved in halt and reboot, using the peripheral driver would work but would generate those warnings. The move to using GPIO pins is mostly aesthetic so as to not have that warning on halt/reboot. Signed-off-by: Kris Bahnsen --- arch/arm/boot/dts/nxp/mxs/imx28-ts7680.dts | 118 +++++++++++++-------- 1 file changed, 72 insertions(+), 46 deletions(-) diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-ts7680.dts b/arch/arm/boot/dts/nxp/mxs/imx28-ts7680.dts index 381300eaedceb..cfce0d2b7dc4d 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-ts7680.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-ts7680.dts @@ -15,15 +15,66 @@ model = "embeddedTS i.MX28 TS-7680 (Default Device Tree)"; compatible = "fsl,imx28-ts7680", "fsl,imx28"; + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x0>; // Filled in by U-Boot + }; + aliases { mmc0 = &ssp0; mmc2 = &ssp1; - i2c0 = &i2c0; + i2c0 = &i2c0_gpio; mdio-gpio0 = &mdio_gpio; }; - memory { - reg = <0x40000000 0x0>; // Filled in by U-Boot + i2c0_gpio: i2c { + compatible = "i2c-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_pins_gpio>; + #address-cells = <1>; + #size-cells = <0>; + scl-gpios = <&gpio3 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio3 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + clock-frequency = <100000>; + + m41t00s: rtc@68 { + compatible = "st,m41t00"; + reg = <0x68>; + }; + + gpio8: gpio-controller@28 { + compatible = "technologic,ts7970-gpio"; + ngpios = <64>; + reg = <0x28>; + #gpio-cells = <2>; + gpio-controller; + + gpio-line-names = "HD4_22", "HD4_23", "HD4_24", "HD4_25", "HD4_26", + "HD4_27", "HD4_28", "HD4_29", "HD4_30", "HD4_31", "HD4_32", + "HD4_33", "HD4_34", "HD4_35", "", "HD4_13/T_4 LS Out", + "HD4_11/T_5 LS Out", "HD4_9/T_6 LS Out", "RELAY1", "RELAY2", + "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", + "AD0_PU#", "AD1_PU#", "AD2_PU#", "AD3_PU#", "AD01_CL", + "AD23_CL", "EN_DC_5V"; + }; + + silabs: watchdog@78 { + compatible = "ts-wdt"; + reg = <0x78>; + timeout-sec = <500>; + enable-early; + }; + + mma8451: accelerometer@1c { + compatible = "fsl,mma8451"; + reg = <0x1c>; + position = <0>; + vdd-supply = <®_3v3>; + vddio-supply = <®_3v3>; + interrupt-parent = <&gpio0>; + interrupts = <20 IRQ_TYPE_NONE>; + interrupt-names = "INT1"; + }; }; led-controller { @@ -41,7 +92,7 @@ led-1 { color = ; - function = LED_FUNCTION_STATUS; + function = LED_FUNCTION_INDICATOR; gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; default-state = "off"; }; @@ -70,8 +121,10 @@ regulator-always-on; }; - reg_can_3v3: regulator-can-en@0 { + reg_can_3v3: regulator-can-en { compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan_3v3>; regulator-name = "CAN_EN"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; @@ -264,45 +317,6 @@ pinctrl-0 = <&i2c0_pins_a>; clock-frequency = <100000>; status = "okay"; - - rtc: m41t00s@68 { - compatible = "m41t00"; - reg = <0x68>; - }; - - gpio8: ts7680gpio@28 { - compatible = "technologic,ts7970-gpio"; - ngpios = <64>; - reg = <0x28>; - #gpio-cells = <2>; - gpio-controller; - - gpio-line-names = "HD4_22", "HD4_23", "HD4_24", "HD4_25", "HD4_26", - "HD4_27", "HD4_28", "HD4_29", "HD4_30", "HD4_31", "HD4_32", - "HD4_33", "HD4_34", "HD4_35", "", "HD4_13/T_4 LS Out", - "HD4_11/T_5 LS Out", "HD4_9/T_6 LS Out", "RELAY1", "RELAY2", - "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", - "AD0_PU#", "AD1_PU#", "AD2_PU#", "AD3_PU#", "AD01_CL", - "AD23_CL", "EN_DC_5V"; - }; - - silabs: silabs@78 { - compatible = "ts-wdt"; - reg = <0x78>; - timeout-sec = <500>; - enable-early; - }; - - accel: mma8451@1c { - compatible = "fsl,mma8451"; - reg = <0x1c>; - position = <0>; - vdd-supply = <®_3v3>; - vddio-supply = <®_3v3>; - interrupt-parent = <&gpio0>; - interrupts = <20 6>; - interrupt-route = <1>; - }; }; &lradc { @@ -393,6 +407,18 @@ fsl,pull-up = ; }; + pinctrl_i2c0_pins_gpio: i2c-gpiogrp { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_I2C0_SCL__GPIO_3_24 + MX28_PAD_I2C0_SDA__GPIO_3_25 + >; + fsl,drive-strength = ; + fsl,voltage = ; + /* This pin uses PULL_DISABLE == 0 == Enable Keeper */ + fsl,pull-up = ; + }; + pinctrl_mac0: mac0grp { reg = <0>; fsl,pinmux-ids = < @@ -417,7 +443,7 @@ >; fsl,drive-strength = ; fsl,voltage = ; - fsp,pull-up = ; + fsl,pull-up = ; }; pinctrl_mmc0_4bit: mmc0-4bitgrp { @@ -525,7 +551,7 @@ cap-power-off-card; status = "okay"; - wlcore: wlcore@2 { + wlcore: wifi@2 { compatible = "ti,wl1271"; reg = <2>; interrupt-parent = <&gpio1>; From b73ee0150f9a5e052078c4da2017021c45f024d8 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Tue, 18 Feb 2025 19:14:23 +0000 Subject: [PATCH 181/244] ARM: dts: imx28-ts7670: fixup memory node Signed-off-by: Kris Bahnsen --- arch/arm/boot/dts/nxp/mxs/imx28-ts7670.dts | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-ts7670.dts b/arch/arm/boot/dts/nxp/mxs/imx28-ts7670.dts index 87d1d5604a8aa..83801a052dbfc 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-ts7670.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-ts7670.dts @@ -13,6 +13,11 @@ model = "embeddedTS i.MX28 TS-7670 (Default Device Tree)"; compatible = "fsl,imx28-ts7670", "fsl,imx28"; + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x08000000>; /* 128MB */ + }; + aliases { i2c0 = &i2c0_gpio; }; @@ -51,10 +56,6 @@ }; }; - memory { - reg = <0x40000000 0x08000000>; /* 128MB */ - }; - led-controller { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_leds>; From f0f932bdd883ad5063337bbf8bd5d13776519625 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Tue, 18 Feb 2025 19:14:43 +0000 Subject: [PATCH 182/244] ARM: dts: imx6ul-ts4100: fixup memory node Signed-off-by: Kris Bahnsen --- arch/arm/boot/dts/nxp/imx/imx6ul-ts4100.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts4100.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-ts4100.dtsi index 238b7c6475dca..3281e55e34061 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-ts4100.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts4100.dtsi @@ -36,8 +36,9 @@ }; }; - memory { + memory@80000000 { /* Memory size to be filled in by U-Boot */ + device_type = "memory"; reg = <0x80000000 0>; }; From 723525d0edc01a115a8db2964ee593390d11a506 Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Fri, 21 Mar 2025 12:18:16 -0700 Subject: [PATCH 183/244] ARM: dts: imx6ul: ts7100: Switch to CPU IO for touch IRQ 6.6 no longer is supporting our IRQ controller which only supports level being used in this case incorrectly with an edge. Instead, FPGA rev 27 and later include an additional mapping directly to a CPU GPIO so this can be used as an edge triggered IRQ. --- arch/arm/boot/dts/nxp/imx/imx6ul-ts7100.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100.dtsi index 10ba4adcfa1a1..51919c9839f0e 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100.dtsi @@ -517,9 +517,9 @@ reg = <0>; compatible = "ti,tsc2046"; spi-max-frequency = <1000000>; - interrupt-parent = <&fpga_intc>; - interrupts = <16>; - pendown-gpio = <&fpga_gpio2 0 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio5>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + pendown-gpio = <&gpio5 9 GPIO_ACTIVE_LOW>; ti,vref-mv = /bits/ 16 <3300>; ti,keep-vref-on; From 7a8b81c8d9d4d3b771a1034aba099d87819fa113 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Wed, 23 Apr 2025 16:25:54 -0700 Subject: [PATCH 184/244] ARM: dts: imx6ul: ts7100-3: Enable uart2 and uart5 These were never explicitly enabled in the devicetree. Also configures rts-gpio for both ports with the correct polarity needed. Signed-off-by: Kris Bahnsen --- arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-3.dtsi | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-3.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-3.dtsi index 7b40675d8f16d..24a0419607f1d 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-3.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-3.dtsi @@ -205,10 +205,10 @@ &uart2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; - rts-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + rts-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; linux,rs485-enabled-at-boot-time; dma-names = "", ""; + status = "okay"; }; &uart3 { @@ -228,9 +228,10 @@ &uart5 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart5>; - uart-has-rtscts; + rts-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; linux,rs485-enabled-at-boot-time; dma-names = "", ""; + status = "okay"; }; &usbotg1 { From b35e5bb99fcb18e7d6f1cb9d1a1b24e350a4ee87 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Mon, 9 Jun 2025 21:09:13 +0000 Subject: [PATCH 185/244] ARM: dts: imx6ul: ts7180: invert CS polarity for HD12/8 In order to be 5 V tolerant, this CS is actually driven through a FET which causes a logical polarity inversion. Signed-off-by: Kris Bahnsen --- arch/arm/boot/dts/nxp/imx/imx6ul-ts7180.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7180.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7180.dts index 4bb207fdb5e16..abff1314928f5 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7180.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7180.dts @@ -136,7 +136,7 @@ &ecspi3 { num-cs = <3>; - cs-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>, <&gpio3 0 GPIO_ACTIVE_LOW>, <&gpio4 27 GPIO_ACTIVE_LOW>; + cs-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>, <&gpio3 0 GPIO_ACTIVE_HIGH>, <&gpio4 27 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi3>; status = "okay"; From 4c519f1fdbb12e2128cf726dae9d875bdd494006 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Tue, 10 Jun 2025 19:27:10 +0000 Subject: [PATCH 186/244] ARM: dts: imx6ul: ts7180: add spi-cs-high property to DC node For SPI to use an inverted CS polarity with cs-gpios, both the GPIO needs to be specified with GPIO_ACTIVE_HIGH -and- the device node needs the spi-cs-high property. Signed-off-by: Kris Bahnsen --- arch/arm/boot/dts/nxp/imx/imx6ul-ts7180.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7180.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7180.dts index abff1314928f5..5b3e50fdf53f5 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7180.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7180.dts @@ -151,6 +151,7 @@ compatible = "technologic,spi-header"; reg = <1>; spi-max-frequency = <1000000>; + spi-cs-high; }; /* This is actually the FRAM, which is compatible with the AT25 SPI EEPROM */ From 34239bde6adfb0efd284c10ce951e8dc200dea95 Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Tue, 1 Jul 2025 13:01:26 -0700 Subject: [PATCH 187/244] ARM: dts: imx6ul: ts7553v2: Add Rev E support Adds 2 new nimbelink control pins Changes from mpu9250a to st,lis2mdl/st,ism330dhcx. --- arch/arm/boot/dts/nxp/imx/imx6ul-ts7553v2.dts | 44 ++++++++++++++++--- 1 file changed, 38 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7553v2.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7553v2.dts index ab2e833d3c2e4..6dffc5437b21c 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7553v2.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7553v2.dts @@ -126,6 +126,17 @@ sda-gpios = <&gpio5 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; scl-gpios = <&gpio5 4 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + lis2mdl: magnetometer@1e { + compatible = "st,lis2mdl"; + reg = <0x1e>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_magn_gpio>; + st,drdy-int-pin = <1>; + interrupt-parent = <&gpio1>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; + }; + + /* Only present on REV D and below */ mpu9250a: imu@68 { compatible = "invensense,mpu9250"; reg = <0x68>; @@ -140,6 +151,15 @@ }; }; }; + + ism330: gyro@6a { + compatible = "st,ism330dhcx"; + reg = <0x6a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gyro_gpio>; + interrupt-parent = <&gpio3>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; + }; }; }; @@ -263,10 +283,10 @@ }; &gpio3 { - gpio-line-names = "USB_HUB_RESET#", "", "", "", "", "", "", - "USB_MUX_CPU_OTG", "", "", "", "NO_CHRG_JMP#", "", "", "", "", - "", "SD_BOOT_JMP#", "PUSH_SW_CPU#", "U_BOOT_JMP#", "XBEE_RESET#", - "", "", "RES_STRAP_0", "RES_STRAP_1", "", "", + gpio-line-names = "USB_HUB_RESET#", "", "NIMBEL_PIN13", "NIMBEL_PIN20", + "", "", "", "USB_MUX_CPU_OTG", "", "", "", "NO_CHRG_JMP#", "", + "", "", "", "", "SD_BOOT_JMP#", "PUSH_SW_CPU#", "U_BOOT_JMP#", + "XBEE_RESET#", "", "", "RES_STRAP_0", "RES_STRAP_1", "", "", "RES_STRAP_2", "RES-STRAP_3"; }; @@ -315,7 +335,6 @@ MX6UL_PAD_LCD_DATA05__GPIO3_IO10 0x1a020 MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x13020 MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x1b020 - MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x1b020 MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x1b020 MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x1b020 MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x1a020 @@ -349,6 +368,8 @@ MX6UL_PAD_LCD_DATA13__GPIO3_IO18 0x1a020 /* PUSH_SW_CPU# */ MX6UL_PAD_UART2_RTS_B__GPIO1_IO23 0x1b020 /* 232_TRANS_EN */ MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b020 /* POWER_FAIL */ + MX6UL_PAD_LCD_HSYNC__GPIO3_IO02 0x1b020 /* NIMBEL_PIN13 */ + MX6UL_PAD_LCD_VSYNC__GPIO3_IO03 0x1a020 /* NIMBEL_PIN20 */ >; }; @@ -436,6 +457,12 @@ >; }; + pinctrl_gyro_gpio: gyrogrp { + fsl,pins = < + MX6UL_PAD_LCD_ENABLE__GPIO3_IO01 0x13020 + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x4001a8b0 @@ -454,7 +481,12 @@ fsl,pins = < MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x4001a8b0 MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x4001a8b0 - MX6UL_PAD_LCD_ENABLE__GPIO3_IO01 0x13020 /* IMU IRQ */ + >; + }; + + pinctrl_magn_gpio: magngrp { + fsl,pins = < + MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x13020 >; }; From 00ba69b7c36649b4e98997646177a13a99b2dbc6 Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Thu, 3 Jul 2025 11:30:57 -0700 Subject: [PATCH 188/244] ARM: dts: imx6qdl-ts7990: Use correct compatible for ST Micro IIS2MDCTR --- arch/arm/boot/dts/nxp/imx/imx6qdl-ts7990.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7990.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7990.dtsi index 94683d1abf198..2b5e359e93ecc 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7990.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7990.dtsi @@ -292,7 +292,7 @@ /* Only present on REV E and above */ magnet: magnetometer@1e { - compatible = "st,lis2mdl"; + compatible = "st,iis2mdc"; reg = <0x1e>; st,drdy-int-pin = <1>; interrupt-parent = <&gpio2>; From cbdc889ad62b99529eabd1e069371b5f76f286fb Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Thu, 3 Jul 2025 11:31:25 -0700 Subject: [PATCH 189/244] ARM: dts: imx6ul: ts7100: Use correct compatible for ST Micro IIS2MDCTR --- arch/arm/boot/dts/nxp/imx/imx6ul-ts7100.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100.dtsi index 51919c9839f0e..11715c552340a 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100.dtsi @@ -156,7 +156,7 @@ status = "okay"; st_magn: magnetometer@1e { - compatible = "st,lis2mdl"; + compatible = "st,iis2mdc"; /* This option isn't valid on this part as it only supports * a single drdy pin. However, the driver defaults to int2 if * not drdy pin is specified which the driver errors on if int2 From 98dcc5e53c698a55cef650af447985dfbe0ced60 Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Thu, 3 Jul 2025 11:32:27 -0700 Subject: [PATCH 190/244] ARM: dts: imx6ul: ts7180: Use correct compatible for ST Micro IIS2MDCTR --- arch/arm/boot/dts/nxp/imx/imx6ul-ts7180.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7180.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7180.dts index 5b3e50fdf53f5..5b3ace31069ff 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7180.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7180.dts @@ -290,7 +290,7 @@ status = "okay"; st_magn: magnetometer@1e { - compatible = "st,lis2mdl"; + compatible = "st,iis2mdc"; reg = <0x1e>; st,drdy-int-pin = <1>; interrupt-parent = <&gpio4>; From 1e6aef642b982828e3541761dfe4973256480a51 Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Thu, 3 Jul 2025 11:32:36 -0700 Subject: [PATCH 191/244] ARM: dts: imx6ul: ts7250v3: Use correct compatible for ST Micro IIS2MDCTR --- arch/arm/boot/dts/nxp/imx/imx6ul-ts7250v3.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7250v3.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7250v3.dtsi index bc4dc1b04fae9..1e7bd45855251 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7250v3.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7250v3.dtsi @@ -137,7 +137,7 @@ status = "okay"; magnet: magnetometer@1e { - compatible = "st,lis2mdl"; + compatible = "st,iis2mdc"; reg = <0x1e>; st,drdy-int-pin = <1>; interrupt-parent = <&gpio1>; From f2b268e9053ee48b563f300be7768dddd666e556 Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Thu, 3 Jul 2025 11:32:45 -0700 Subject: [PATCH 192/244] ARM: dts: imx6ul: ts7553v2: Use correct compatible for ST Micro IIS2MDCTR --- arch/arm/boot/dts/nxp/imx/imx6ul-ts7553v2.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7553v2.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7553v2.dts index 6dffc5437b21c..99f7af4738be3 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7553v2.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7553v2.dts @@ -126,8 +126,8 @@ sda-gpios = <&gpio5 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; scl-gpios = <&gpio5 4 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - lis2mdl: magnetometer@1e { - compatible = "st,lis2mdl"; + iis2mdc: magnetometer@1e { + compatible = "st,iis2mdc"; reg = <0x1e>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_magn_gpio>; From 02d923cea489c2518a90c85e18ae76c835fa8c8d Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Fri, 18 Jul 2025 23:58:12 +0000 Subject: [PATCH 193/244] ARM: configs: tsimx28: updates for 6.18 Signed-off-by: Kris Bahnsen --- arch/arm/configs/tsimx28_defconfig | 47 ++++-------------------------- 1 file changed, 5 insertions(+), 42 deletions(-) diff --git a/arch/arm/configs/tsimx28_defconfig b/arch/arm/configs/tsimx28_defconfig index b395e4373f8bf..cd3cc0c509e54 100644 --- a/arch/arm/configs/tsimx28_defconfig +++ b/arch/arm/configs/tsimx28_defconfig @@ -32,15 +32,10 @@ CONFIG_HZ_1000=y CONFIG_AEABI=y CONFIG_HIGHMEM=y CONFIG_EFI=y -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y CONFIG_MODULES=y -CONFIG_MODULE_FORCE_LOAD=y CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y CONFIG_MODVERSIONS=y +CONFIG_MODULE_COMPRESS=y CONFIG_MODULE_COMPRESS_XZ=y CONFIG_BLK_DEV_INTEGRITY=y CONFIG_BINFMT_MISC=y @@ -187,7 +182,6 @@ CONFIG_NETFILTER_XT_TARGET_NFLOG=m CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m CONFIG_NETFILTER_XT_TARGET_TEE=m CONFIG_NETFILTER_XT_TARGET_TPROXY=m -CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER_XT_TARGET_SECMARK=m CONFIG_NETFILTER_XT_TARGET_TCPMSS=m CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m @@ -283,19 +277,9 @@ CONFIG_IP_NF_MATCH_AH=m CONFIG_IP_NF_MATCH_ECN=m CONFIG_IP_NF_MATCH_RPFILTER=m CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m CONFIG_IP_NF_TARGET_SYNPROXY=m -CONFIG_IP_NF_NAT=m -CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_NETMAP=m -CONFIG_IP_NF_TARGET_REDIRECT=m -CONFIG_IP_NF_MANGLE=m CONFIG_IP_NF_TARGET_ECN=m -CONFIG_IP_NF_TARGET_TTL=m -CONFIG_IP_NF_RAW=m -CONFIG_IP_NF_ARPTABLES=m -CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m CONFIG_NFT_DUP_IPV6=m CONFIG_NFT_FIB_IPV6=m @@ -310,23 +294,14 @@ CONFIG_IP6_NF_MATCH_MH=m CONFIG_IP6_NF_MATCH_RPFILTER=m CONFIG_IP6_NF_MATCH_RT=m CONFIG_IP6_NF_MATCH_SRH=m -CONFIG_IP6_NF_TARGET_HL=m -CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_TARGET_SYNPROXY=m -CONFIG_IP6_NF_MANGLE=m -CONFIG_IP6_NF_RAW=m -CONFIG_IP6_NF_NAT=m -CONFIG_IP6_NF_TARGET_MASQUERADE=m CONFIG_IP6_NF_TARGET_NPT=m CONFIG_NF_TABLES_BRIDGE=m CONFIG_NFT_BRIDGE_META=m CONFIG_NFT_BRIDGE_REJECT=m CONFIG_NF_CONNTRACK_BRIDGE=m CONFIG_BRIDGE_NF_EBTABLES=m -CONFIG_BRIDGE_EBT_BROUTE=m -CONFIG_BRIDGE_EBT_T_FILTER=m -CONFIG_BRIDGE_EBT_T_NAT=m CONFIG_BRIDGE_EBT_802_3=m CONFIG_BRIDGE_EBT_AMONG=m CONFIG_BRIDGE_EBT_ARP=m @@ -344,8 +319,6 @@ CONFIG_BRIDGE_EBT_REDIRECT=m CONFIG_BRIDGE_EBT_SNAT=m CONFIG_BRIDGE_EBT_LOG=m CONFIG_BRIDGE_EBT_NFLOG=m -CONFIG_BPFILTER=y -CONFIG_IP_DCCP=m CONFIG_RDS=m CONFIG_RDS_TCP=m CONFIG_L2TP=m @@ -366,7 +339,6 @@ CONFIG_IEEE802154_6LOWPAN=m CONFIG_MAC802154=m CONFIG_DNS_RESOLVER=y CONFIG_BATMAN_ADV=m -CONFIG_BATMAN_ADV_NC=y CONFIG_OPENVSWITCH=m CONFIG_VSOCKETS=m CONFIG_NETLINK_DIAG=m @@ -544,7 +516,6 @@ CONFIG_AT76C50X_USB=m CONFIG_BRCMFMAC=m # CONFIG_BRCMFMAC_SDIO is not set CONFIG_BRCMFMAC_USB=y -# CONFIG_WLAN_VENDOR_CISCO is not set # CONFIG_WLAN_VENDOR_INTEL is not set # CONFIG_WLAN_VENDOR_INTERSIL is not set CONFIG_MWIFIEX=m @@ -571,7 +542,6 @@ CONFIG_RSI_91X=m # CONFIG_WLAN_VENDOR_ST is not set CONFIG_WL12XX=m CONFIG_WLCORE_SDIO=m -CONFIG_USB_ZD1201=m CONFIG_ZD1211RW=m # CONFIG_WLAN_VENDOR_QUANTENNA is not set # CONFIG_INPUT_KEYBOARD is not set @@ -622,7 +592,6 @@ CONFIG_SND_USB_VARIAX=m # CONFIG_HID_CYPRESS is not set # CONFIG_HID_EZKEY is not set # CONFIG_HID_KENSINGTON is not set -# CONFIG_HID_LOGITECH is not set # CONFIG_HID_MICROSOFT is not set # CONFIG_HID_MONTEREY is not set CONFIG_USB_HID=m @@ -749,13 +718,9 @@ CONFIG_MXS_LRADC_ADC=m CONFIG_PWM=y CONFIG_PWM_MXS=y CONFIG_NVMEM_MXS_OCOTP=m -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT2_FS_POSIX_ACL=y -CONFIG_EXT2_FS_SECURITY=y -CONFIG_EXT3_FS=y -CONFIG_EXT3_FS_POSIX_ACL=y -CONFIG_EXT3_FS_SECURITY=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y CONFIG_F2FS_FS=m CONFIG_F2FS_FS_SECURITY=y # CONFIG_DNOTIFY is not set @@ -765,8 +730,7 @@ CONFIG_FUSE_FS=m CONFIG_OVERLAY_FS=m CONFIG_VFAT_FS=y CONFIG_EXFAT_FS=y -CONFIG_NTFS_FS=m -CONFIG_NTFS_RW=y +CONFIG_NTFS3_FS=m CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y # CONFIG_MISC_FILESYSTEMS is not set @@ -783,7 +747,6 @@ CONFIG_CRYPTO_CRC32=y CONFIG_CRYPTO_DEFLATE=y CONFIG_CRYPTO_LZO=y CONFIG_CRYPTO_DEV_MXS_DCP=y -CONFIG_CRC7=m CONFIG_PRINTK_TIME=y CONFIG_FRAME_WARN=2048 CONFIG_DEBUG_FS=y From 9cc55faf4f8cc5d7d20fa843749296905b0debe2 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Fri, 18 Jul 2025 23:58:24 +0000 Subject: [PATCH 194/244] ARM: configs: tsimx28_minimal: updates for 6.18 Signed-off-by: Kris Bahnsen --- arch/arm/configs/tsimx28_minimal_defconfig | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/arch/arm/configs/tsimx28_minimal_defconfig b/arch/arm/configs/tsimx28_minimal_defconfig index 6b8ebd1fcbacd..4117e61f07528 100644 --- a/arch/arm/configs/tsimx28_minimal_defconfig +++ b/arch/arm/configs/tsimx28_minimal_defconfig @@ -19,14 +19,9 @@ CONFIG_ARCH_MXS=y CONFIG_HZ_1000=y CONFIG_AEABI=y CONFIG_HIGHMEM=y -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y CONFIG_MODULES=y -CONFIG_MODULE_FORCE_LOAD=y CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODULE_COMPRESS=y CONFIG_MODULE_COMPRESS_XZ=y CONFIG_BLK_DEV_INTEGRITY=y CONFIG_BINFMT_MISC=y @@ -133,7 +128,6 @@ CONFIG_USB_NET_SMSC95XX=m # CONFIG_WLAN_VENDOR_ATH is not set # CONFIG_WLAN_VENDOR_ATMEL is not set # CONFIG_WLAN_VENDOR_BROADCOM is not set -# CONFIG_WLAN_VENDOR_CISCO is not set # CONFIG_WLAN_VENDOR_INTEL is not set # CONFIG_WLAN_VENDOR_INTERSIL is not set # CONFIG_WLAN_VENDOR_MARVELL is not set @@ -246,6 +240,7 @@ CONFIG_PWM=y CONFIG_PWM_MXS=y CONFIG_NVMEM_MXS_OCOTP=m CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y # CONFIG_DNOTIFY is not set CONFIG_FANOTIFY=y CONFIG_VFAT_FS=y @@ -263,9 +258,6 @@ CONFIG_CRYPTO_SHA1=m CONFIG_CRYPTO_DEFLATE=y CONFIG_CRYPTO_LZO=y CONFIG_CRYPTO_DEV_MXS_DCP=y -CONFIG_CRC_CCITT=m -CONFIG_CRC_ITU_T=m -CONFIG_CRC7=m CONFIG_FRAME_WARN=2048 CONFIG_DEBUG_USER=y # CONFIG_RUNTIME_TESTING_MENU is not set From 6ce5759f593c9731c324b25e16750ec2d7542dde Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Tue, 22 Jul 2025 21:41:12 +0000 Subject: [PATCH 195/244] gpio: ts71xxweim: fixups for 6.18 Signed-off-by: Kris Bahnsen --- drivers/gpio/gpio-ts71xxweim.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpio/gpio-ts71xxweim.c b/drivers/gpio/gpio-ts71xxweim.c index 069bc5adbf38d..e6b812d8948d3 100644 --- a/drivers/gpio/gpio-ts71xxweim.c +++ b/drivers/gpio/gpio-ts71xxweim.c @@ -5,8 +5,10 @@ */ #include +#include #include #include +#include #include /* Most that this driver can currently support in a single bank is 16. This is @@ -74,18 +76,20 @@ static int tsweim_gpio_get(struct gpio_chip *chip, unsigned int offset) return !!(reg & (1 << offset)); } -static void tsweim_gpio_set(struct gpio_chip *chip, unsigned int offset, +static int tsweim_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) { struct tsweim_gpio_priv *priv = to_gpio_tsweim(chip); if (!(offset < priv->gpio_chip.ngpio)) - return; + return -EINVAL; if (value) writew((1 << offset), priv->syscon + TSWEIM_SET_REG); else writew((1 << offset), priv->syscon + TSWEIM_CLR_REG); + + return 0; } static const struct gpio_chip template_chip = { From 7531bd9dcda826d31b3990071068395a36a5fc72 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Wed, 23 Jul 2025 01:20:23 +0000 Subject: [PATCH 196/244] pwm: ts: fixups for 6.12 Signed-off-by: Kris Bahnsen --- drivers/pwm/pwm-ts.c | 74 +++++++++++++++----------------------------- 1 file changed, 25 insertions(+), 49 deletions(-) diff --git a/drivers/pwm/pwm-ts.c b/drivers/pwm/pwm-ts.c index 491ec3fb372a9..5fe0d7eeb2c07 100644 --- a/drivers/pwm/pwm-ts.c +++ b/drivers/pwm/pwm-ts.c @@ -34,20 +34,14 @@ #define SHIFT_MAX 12 struct ts_pwm { - struct pwm_chip chip; void __iomem *base; struct clk *clk; }; -static inline struct ts_pwm *to_ts_pwm(struct pwm_chip *chip) -{ - return container_of(chip, struct ts_pwm, chip); -} - -static int ts_pwm_calc(struct ts_pwm *ts, - unsigned int duty, +static int ts_pwm_calc(struct pwm_chip *chip, unsigned int duty, unsigned int period) { + struct ts_pwm *ts = pwmchip_get_drvdata(chip); unsigned long clk_rate = clk_get_rate(ts->clk); unsigned long long cycle; unsigned int cnt, duty_cnt; @@ -66,7 +60,7 @@ static int ts_pwm_calc(struct ts_pwm *ts, if (cnt > CYCLE_MASK) return -EINVAL; - dev_dbg(ts->chip.dev, "cycle=%llu shift=%u cnt=%u\n", + dev_dbg(pwmchip_parent(chip), "cycle=%llu shift=%u cnt=%u\n", cycle, shift, cnt); @@ -77,11 +71,11 @@ static int ts_pwm_calc(struct ts_pwm *ts, } else { duty_cnt = DIV_ROUND_CLOSEST(duty * 100, (unsigned int)cycle); if (duty_cnt > CYCLE_MASK) { - dev_err(ts->chip.dev, "unable to get duty cycle\n"); + dev_err(pwmchip_parent(chip), "unable to get duty cycle\n"); return -EINVAL; } - dev_dbg(ts->chip.dev, "shift=%u cnt=%u duty_cnt=%u\n", + dev_dbg(pwmchip_parent(chip), "shift=%u cnt=%u duty_cnt=%u\n", shift, cnt, duty_cnt); duty_reg = cnt - duty_cnt; } @@ -96,7 +90,7 @@ static int ts_pwm_calc(struct ts_pwm *ts, static int ts_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, const struct pwm_state *state) { - struct ts_pwm *ts = to_ts_pwm(chip); + struct ts_pwm *ts = pwmchip_get_drvdata(chip); int err; u16 ctrl = 0; @@ -106,7 +100,7 @@ static int ts_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, if (state->enabled) ctrl |= ENABLED; - err = ts_pwm_calc(ts, state->duty_cycle, state->period); + err = ts_pwm_calc(chip, state->duty_cycle, state->period); if (err < 0) return err; @@ -117,27 +111,20 @@ static int ts_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, static const struct pwm_ops ts_pwm_ops = { .apply = ts_pwm_apply, - .owner = THIS_MODULE, }; -static const struct of_device_id ts_pwm_matches[] = { - { .compatible = "technologic,pwm", }, - {}, -}; -MODULE_DEVICE_TABLE(of, ts_pwm_matches); - static int ts_pwm_probe(struct platform_device *pdev) { struct ts_pwm *ts; - struct resource *regs; - int err; + struct pwm_chip *chip; + int ret; - ts = devm_kzalloc(&pdev->dev, sizeof(*ts), GFP_KERNEL); - if (!ts) - return -ENOMEM; + chip = devm_pwmchip_alloc(&pdev->dev, 1, sizeof(*ts)); + if (IS_ERR(chip)) + return PTR_ERR(chip); + ts = pwmchip_get_drvdata(chip); - regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); - ts->base = devm_ioremap_resource(&pdev->dev, regs); + ts->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(ts->base)) return PTR_ERR(ts->base); @@ -147,29 +134,20 @@ static int ts_pwm_probe(struct platform_device *pdev) return PTR_ERR(ts->clk); } - platform_set_drvdata(pdev, ts); - - ts->chip.dev = &pdev->dev; - ts->chip.ops = &ts_pwm_ops; - ts->chip.base = -1; - ts->chip.npwm = 1; + chip->ops = &ts_pwm_ops; - pm_runtime_enable(&pdev->dev); + ret = devm_pm_runtime_enable(&pdev->dev); + if (ret < 0) + return ret; - err = pwmchip_add(&ts->chip); - if (err < 0) { - dev_err(&pdev->dev, "failed to register PWM chip: %d\n", err); - return err; - } - - return 0; + return devm_pwmchip_add(&pdev->dev, chip); } -static void ts_pwm_remove(struct platform_device *pdev) -{ - struct ts_pwm *ts = platform_get_drvdata(pdev); - pwmchip_remove(&ts->chip); -} +static const struct of_device_id ts_pwm_matches[] = { + { .compatible = "technologic,pwm", }, + {}, +}; +MODULE_DEVICE_TABLE(of, ts_pwm_matches); static struct platform_driver ts_pwm_driver = { .driver = { @@ -177,11 +155,9 @@ static struct platform_driver ts_pwm_driver = { .of_match_table = ts_pwm_matches, }, .probe = ts_pwm_probe, - .remove_new = ts_pwm_remove, }; module_platform_driver(ts_pwm_driver); -MODULE_ALIAS("platform:ts-pwm"); -MODULE_DESCRIPTION("embeddedTS PS"); +MODULE_DESCRIPTION("embeddedTS PWM driver"); MODULE_AUTHOR("Mark Featherston "); MODULE_LICENSE("GPL"); From ba9c4188763afac5a236beb495e628d6754549ea Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Fri, 1 Aug 2025 20:50:58 +0000 Subject: [PATCH 197/244] spi: spi-oc: temporary fix NEEDS TESTING Signed-off-by: Kris Bahnsen --- drivers/spi/spi-oc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/spi-oc.c b/drivers/spi/spi-oc.c index 7d37028d9b915..f1ebae9820b38 100644 --- a/drivers/spi/spi-oc.c +++ b/drivers/spi/spi-oc.c @@ -82,7 +82,7 @@ static inline void spioc_write(struct spioc *spioc, unsigned int offset, static void spioc_chipselect(struct spioc *controller, struct spi_device *spi) { if (spi) - spioc_write(controller, SPIOC_SS, 1 << spi->chip_select); + spioc_write(controller, SPIOC_SS, 1 << spi->chip_select[0]); else spioc_write(controller, SPIOC_SS, 0); } From ed4daad54f95624ffc634892adac7d9b1921a5f1 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Mon, 4 Aug 2025 20:40:39 +0000 Subject: [PATCH 198/244] ARM: dts: imx6ul: ts7553v2: fix GPIO name typo Signed-off-by: Kris Bahnsen --- arch/arm/boot/dts/nxp/imx/imx6ul-ts7553v2.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7553v2.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7553v2.dts index 99f7af4738be3..6d8035cfc84f2 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7553v2.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7553v2.dts @@ -287,7 +287,7 @@ "", "", "", "USB_MUX_CPU_OTG", "", "", "", "NO_CHRG_JMP#", "", "", "", "", "", "SD_BOOT_JMP#", "PUSH_SW_CPU#", "U_BOOT_JMP#", "XBEE_RESET#", "", "", "RES_STRAP_0", "RES_STRAP_1", "", "", - "RES_STRAP_2", "RES-STRAP_3"; + "RES_STRAP_2", "RES_STRAP_3"; }; &gpio5 { From 9cdfb3745536691097e3b61b04479884d90a4edc Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Mon, 4 Aug 2025 20:41:02 +0000 Subject: [PATCH 199/244] ARM: configs: tsimx6ul: updates for 6.18 Adds unused TI wifi driver to force inclusion of CRC7 module that is needed by the external wilc3000 driver. Signed-off-by: Kris Bahnsen --- arch/arm/configs/tsimx6ul_defconfig | 46 ++++------------------------- 1 file changed, 6 insertions(+), 40 deletions(-) diff --git a/arch/arm/configs/tsimx6ul_defconfig b/arch/arm/configs/tsimx6ul_defconfig index cdcb2ce3e6e58..3d4a9e7305ea8 100644 --- a/arch/arm/configs/tsimx6ul_defconfig +++ b/arch/arm/configs/tsimx6ul_defconfig @@ -40,7 +40,6 @@ CONFIG_CPU_FREQ_STAT=y CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y CONFIG_CPU_FREQ_GOV_POWERSAVE=y CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPUFREQ_DT=y CONFIG_ARM_IMX6Q_CPUFREQ=y CONFIG_CPU_IDLE=y CONFIG_ARM_CPUIDLE=y @@ -54,6 +53,7 @@ CONFIG_PM_DEBUG=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODVERSIONS=y +CONFIG_MODULE_COMPRESS=y CONFIG_MODULE_COMPRESS_XZ=y # CONFIG_MQ_IOSCHED_KYBER is not set CONFIG_BINFMT_MISC=y @@ -203,7 +203,6 @@ CONFIG_NETFILTER_XT_TARGET_NFLOG=m CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m CONFIG_NETFILTER_XT_TARGET_TEE=m CONFIG_NETFILTER_XT_TARGET_TPROXY=m -CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER_XT_TARGET_SECMARK=m CONFIG_NETFILTER_XT_TARGET_TCPMSS=m CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m @@ -299,19 +298,9 @@ CONFIG_IP_NF_MATCH_AH=m CONFIG_IP_NF_MATCH_ECN=m CONFIG_IP_NF_MATCH_RPFILTER=m CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m CONFIG_IP_NF_TARGET_SYNPROXY=m -CONFIG_IP_NF_NAT=m -CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_NETMAP=m -CONFIG_IP_NF_TARGET_REDIRECT=m -CONFIG_IP_NF_MANGLE=m CONFIG_IP_NF_TARGET_ECN=m -CONFIG_IP_NF_TARGET_TTL=m -CONFIG_IP_NF_RAW=m -CONFIG_IP_NF_ARPTABLES=m -CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m CONFIG_NFT_DUP_IPV6=m CONFIG_NFT_FIB_IPV6=m @@ -326,23 +315,14 @@ CONFIG_IP6_NF_MATCH_MH=m CONFIG_IP6_NF_MATCH_RPFILTER=m CONFIG_IP6_NF_MATCH_RT=m CONFIG_IP6_NF_MATCH_SRH=m -CONFIG_IP6_NF_TARGET_HL=m -CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_TARGET_SYNPROXY=m -CONFIG_IP6_NF_MANGLE=m -CONFIG_IP6_NF_RAW=m -CONFIG_IP6_NF_NAT=m -CONFIG_IP6_NF_TARGET_MASQUERADE=m CONFIG_IP6_NF_TARGET_NPT=m CONFIG_NF_TABLES_BRIDGE=m CONFIG_NFT_BRIDGE_META=m CONFIG_NFT_BRIDGE_REJECT=m CONFIG_NF_CONNTRACK_BRIDGE=m CONFIG_BRIDGE_NF_EBTABLES=m -CONFIG_BRIDGE_EBT_BROUTE=m -CONFIG_BRIDGE_EBT_T_FILTER=m -CONFIG_BRIDGE_EBT_T_NAT=m CONFIG_BRIDGE_EBT_802_3=m CONFIG_BRIDGE_EBT_AMONG=m CONFIG_BRIDGE_EBT_ARP=m @@ -360,8 +340,6 @@ CONFIG_BRIDGE_EBT_REDIRECT=m CONFIG_BRIDGE_EBT_SNAT=m CONFIG_BRIDGE_EBT_LOG=m CONFIG_BRIDGE_EBT_NFLOG=m -CONFIG_BPFILTER=y -CONFIG_IP_DCCP=m CONFIG_RDS=m CONFIG_RDS_TCP=m CONFIG_L2TP=m @@ -389,7 +367,6 @@ CONFIG_MAC802154=m CONFIG_NET_SCHED=y CONFIG_DNS_RESOLVER=y CONFIG_BATMAN_ADV=m -CONFIG_BATMAN_ADV_NC=y CONFIG_BATMAN_ADV_DEBUG=y CONFIG_OPENVSWITCH=m CONFIG_VSOCKETS=m @@ -608,7 +585,6 @@ CONFIG_AT76C50X_USB=m CONFIG_BRCMFMAC=m # CONFIG_BRCMFMAC_SDIO is not set CONFIG_BRCMFMAC_USB=y -# CONFIG_WLAN_VENDOR_CISCO is not set # CONFIG_WLAN_VENDOR_INTEL is not set # CONFIG_WLAN_VENDOR_INTERSIL is not set CONFIG_MWIFIEX=m @@ -637,8 +613,8 @@ CONFIG_RSI_91X=m # CONFIG_RSI_SDIO is not set # CONFIG_WLAN_VENDOR_ST is not set CONFIG_WL12XX=m +CONFIG_WLCORE_SPI=m CONFIG_WLCORE_SDIO=m -CONFIG_USB_ZD1201=m CONFIG_ZD1211RW=m # CONFIG_WLAN_VENDOR_QUANTENNA is not set # CONFIG_INPUT_LEDS is not set @@ -661,7 +637,6 @@ CONFIG_SERIAL_OF_PLATFORM=m CONFIG_SERIAL_IMX=y CONFIG_SERIAL_IMX_CONSOLE=y CONFIG_SERIAL_DEV_BUS=y -# CONFIG_I2C_COMPAT is not set CONFIG_I2C_CHARDEV=y CONFIG_I2C_MUX=y # CONFIG_I2C_HELPER_AUTO is not set @@ -689,7 +664,6 @@ CONFIG_POWER_RESET_SYSCON_POWEROFF=y CONFIG_SENSORS_IIO_HWMON=y CONFIG_THERMAL=y CONFIG_THERMAL_STATISTICS=y -CONFIG_THERMAL_WRITABLE_TRIPS=y CONFIG_CPU_THERMAL=y CONFIG_IMX_THERMAL=y CONFIG_WATCHDOG=y @@ -726,7 +700,6 @@ CONFIG_SND_USB_AUDIO=m # CONFIG_HID_EZKEY is not set # CONFIG_HID_ITE is not set # CONFIG_HID_KENSINGTON is not set -# CONFIG_HID_LOGITECH is not set # CONFIG_HID_REDRAGON is not set # CONFIG_HID_MICROSOFT is not set # CONFIG_HID_MONTEREY is not set @@ -855,13 +828,9 @@ CONFIG_PWM_TS=m CONFIG_TSWEIM_FPGA_INTC=y CONFIG_NVMEM_IMX_OCOTP=y CONFIG_NVMEM_SNVS_LPGPR=y -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT2_FS_POSIX_ACL=y -CONFIG_EXT2_FS_SECURITY=y -CONFIG_EXT3_FS=y -CONFIG_EXT3_FS_POSIX_ACL=y -CONFIG_EXT3_FS_SECURITY=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y CONFIG_F2FS_FS=y CONFIG_F2FS_FS_SECURITY=y CONFIG_QUOTA=y @@ -871,8 +840,7 @@ CONFIG_FUSE_FS=m CONFIG_OVERLAY_FS=m CONFIG_VFAT_FS=y CONFIG_EXFAT_FS=y -CONFIG_NTFS_FS=m -CONFIG_NTFS_RW=y +CONFIG_NTFS3_FS=m CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y CONFIG_CONFIGFS_FS=y @@ -894,8 +862,6 @@ CONFIG_CRYPTO_LZO=y CONFIG_CRYPTO_DEV_FSL_CAAM=y CONFIG_CRYPTO_DEV_SAHARA=y CONFIG_CRYPTO_DEV_MXS_DCP=y -CONFIG_CRC_T10DIF=y -CONFIG_CRC7=m CONFIG_DMA_CMA=y CONFIG_CMA_SIZE_MBYTES=64 CONFIG_PRINTK_TIME=y From b78a99336487d8c5f2cf074b5201a800c968b44a Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Mon, 4 Aug 2025 21:41:44 +0000 Subject: [PATCH 200/244] ARM: configs: tsimx6ul_minimal: updates for 6.18 Adds unused TI wifi driver to force inclusion of CRC7 module that is needed by the external wilc3000 driver. Signed-off-by: Kris Bahnsen --- arch/arm/configs/tsimx6ul_minimal_defconfig | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/arch/arm/configs/tsimx6ul_minimal_defconfig b/arch/arm/configs/tsimx6ul_minimal_defconfig index a13760877a7d2..8ed1a8d903a75 100644 --- a/arch/arm/configs/tsimx6ul_minimal_defconfig +++ b/arch/arm/configs/tsimx6ul_minimal_defconfig @@ -36,6 +36,7 @@ CONFIG_PM_DEBUG=y # CONFIG_STACKPROTECTOR is not set CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_COMPRESS=y CONFIG_MODULE_COMPRESS_XZ=y # CONFIG_MQ_IOSCHED_KYBER is not set CONFIG_BINFMT_MISC=y @@ -156,7 +157,6 @@ CONFIG_USB_NET_SMSC95XX=m # CONFIG_WLAN_VENDOR_ATH is not set # CONFIG_WLAN_VENDOR_ATMEL is not set # CONFIG_WLAN_VENDOR_BROADCOM is not set -# CONFIG_WLAN_VENDOR_CISCO is not set # CONFIG_WLAN_VENDOR_INTEL is not set # CONFIG_WLAN_VENDOR_INTERSIL is not set # CONFIG_WLAN_VENDOR_MARVELL is not set @@ -167,6 +167,7 @@ CONFIG_USB_NET_SMSC95XX=m # CONFIG_WLAN_VENDOR_RSI is not set # CONFIG_WLAN_VENDOR_ST is not set CONFIG_WL12XX=m +CONFIG_WLCORE_SPI=m CONFIG_WLCORE_SDIO=m # CONFIG_WLAN_VENDOR_ZYDAS is not set # CONFIG_WLAN_VENDOR_QUANTENNA is not set @@ -189,7 +190,6 @@ CONFIG_SERIAL_OF_PLATFORM=m CONFIG_SERIAL_IMX=y CONFIG_SERIAL_IMX_CONSOLE=y CONFIG_SERIAL_DEV_BUS=y -# CONFIG_I2C_COMPAT is not set CONFIG_I2C_CHARDEV=y CONFIG_I2C_MUX=y # CONFIG_I2C_HELPER_AUTO is not set @@ -217,7 +217,6 @@ CONFIG_POWER_RESET_SYSCON_POWEROFF=y CONFIG_SENSORS_IIO_HWMON=y CONFIG_THERMAL=y CONFIG_THERMAL_STATISTICS=y -CONFIG_THERMAL_WRITABLE_TRIPS=y CONFIG_CPU_THERMAL=y CONFIG_IMX_THERMAL=y CONFIG_WATCHDOG=y @@ -340,11 +339,6 @@ CONFIG_CRYPTO_LZO=y CONFIG_CRYPTO_DEV_FSL_CAAM=y CONFIG_CRYPTO_DEV_SAHARA=y CONFIG_CRYPTO_DEV_MXS_DCP=y -CONFIG_CRC_CCITT=m -CONFIG_CRC_T10DIF=y -CONFIG_CRC_ITU_T=m -CONFIG_CRC7=m -CONFIG_LIBCRC32C=m CONFIG_XZ_DEC=y CONFIG_DMA_CMA=y CONFIG_CMA_SIZE_MBYTES=64 From 7eb4d0fd97c8d8f05bb5855c30ebbe8f43da34d9 Mon Sep 17 00:00:00 2001 From: Michael D Peters Date: Mon, 11 Aug 2025 10:14:56 -0700 Subject: [PATCH 201/244] ARM: embeddedts: rename tssupervisor subsystem to tswizard (#225) * refactor(arch/arm/boot/dts/nxp/imx/): Rename supervisor to wizard * refactor(arch/arm/configs/): Rename supervisor to wizard * refactor(include/linux/mfd/): Rename supervisor to wizard * refactor(drivers/mfd/): Rename sueprvisor to wizard * refactor(drivers/power/reset/): Rename supervisor to wizard * refactor(drivers/iio/temperature/): Rename supervisor to wizard * refactor(drivers/iio/adc/): Rename supervisor to wizard * refactor(drivers/rtc): Rename supervisor to wizard --- arch/arm/boot/dts/nxp/imx/imx6ul-ts7180.dts | 2 +- arch/arm/boot/dts/nxp/imx/imx6ul-ts7250v3.dts | 4 +- .../arm/boot/dts/nxp/imx/imx6ul-ts7250v3.dtsi | 34 ++-- arch/arm/configs/tsimx6ul_defconfig | 10 +- arch/arm/configs/tsimx6ul_minimal_defconfig | 10 +- drivers/iio/adc/Kconfig | 8 +- drivers/iio/adc/Makefile | 2 +- .../{tssupervisor_adc.c => tswizard_adc.c} | 108 ++++++------- drivers/iio/temperature/Kconfig | 8 +- drivers/iio/temperature/Makefile | 2 +- .../{tssupervisor_temp.c => tswizard_temp.c} | 18 +-- drivers/mfd/Kconfig | 6 +- drivers/mfd/Makefile | 2 +- .../{tssupervisor-core.c => tswizard-core.c} | 152 +++++++++--------- drivers/power/reset/Kconfig | 6 +- drivers/power/reset/Makefile | 2 +- ...{tssupervisor-reset.c => tswizard-reset.c} | 66 ++++---- drivers/rtc/Kconfig | 6 +- drivers/rtc/Makefile | 2 +- .../{rtc-tssupervisor.c => rtc-tswizard.c} | 140 ++++++++-------- .../mfd/{ts_supervisor.h => ts_wizard.h} | 50 +++--- 21 files changed, 319 insertions(+), 319 deletions(-) rename drivers/iio/adc/{tssupervisor_adc.c => tswizard_adc.c} (57%) rename drivers/iio/temperature/{tssupervisor_temp.c => tswizard_temp.c} (80%) rename drivers/mfd/{tssupervisor-core.c => tswizard-core.c} (55%) rename drivers/power/reset/{tssupervisor-reset.c => tswizard-reset.c} (58%) rename drivers/rtc/{rtc-tssupervisor.c => rtc-tswizard.c} (57%) rename include/linux/mfd/{ts_supervisor.h => ts_wizard.h} (53%) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7180.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7180.dts index 5b3ace31069ff..868783dfb2084 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7180.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7180.dts @@ -297,7 +297,7 @@ interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; /* See MX6UL_PAD_NAND_ALE__GPIO4_IO10 */ }; - supervisor: wdt@54 { + wizard: wdt@54 { compatible = "technologic,ts7100-wdt"; enable-early; /* 5min timeout default, in case of slow userspace. diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7250v3.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7250v3.dts index a8a8ead2502d6..1d1380a386513 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7250v3.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7250v3.dts @@ -8,11 +8,11 @@ #include #include "imx6ul-ts7250v3.dtsi" -&supervisor { +&wizard { status = "okay"; }; -&supervisor_rtc { +&wizard_rtc { status = "okay"; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7250v3.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7250v3.dtsi index 1e7bd45855251..3d113bd5e26ce 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7250v3.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7250v3.dtsi @@ -81,7 +81,7 @@ an_3p3v: an_3p3v { compatible = "voltage-divider"; - io-channels = <&supervisor_adc 0>; + io-channels = <&wizard_adc 0>; label = "3.3V"; output-ohms = <100000>; /* R2 (100k) */ full-ohms = <110700>; /* R1 (10.7k) + R2 (100k) */ @@ -90,7 +90,7 @@ an_5v: an_5v { compatible = "voltage-divider"; - io-channels = <&supervisor_adc 3>; + io-channels = <&wizard_adc 3>; label = "5V_A"; output-ohms = <42200>; /* R2 (42.2k) */ full-ohms = <84400>; /* R1 (42.2k) + R2 (42.2k) */ @@ -99,7 +99,7 @@ an_8v_48v: an_8v_48v { compatible = "voltage-divider"; - io-channels = <&supervisor_adc 4>; + io-channels = <&wizard_adc 4>; label = "8V_48V"; output-ohms = <10700>; /* R2 (10.7k) */ full-ohms = <247700>; /* R1 (237K) + R2 (10.7k) */ @@ -111,18 +111,18 @@ * that can be consumed within the kernel. The hwmon device is disabled * until this is resolved */ - supervisor-adcs { + wizard-adcs { compatible = "iio-hwmon"; - io-channels = <&an_3p3v>, <&supervisor_adc 1>, <&supervisor_adc 2>, - <&supervisor_adc 3>, <&an_5v>, <&an_8v_48v>; + io-channels = <&an_3p3v>, <&wizard_adc 1>, <&wizard_adc 2>, + <&wizard_adc 3>, <&an_5v>, <&an_8v_48v>; io-channel-names = "3.3V", "VDD_ARM_CAP", "VDD_SOC_CAP", "5V_A", "8V_48V"; status = "disabled"; }; - supervisor-temp { + wizard-temp { compatible = "iio-hwmon"; - io-channels = <&supervisor_temp>; - io-channel-names = "Supervisor Temp"; + io-channels = <&wizard_temp>; + io-channel-names = "Wizard Temp"; status = "okay"; }; }; @@ -155,18 +155,18 @@ status = "disabled"; }; - supervisor: supervisor@10 { - compatible = "technologic,supervisor"; + wizard: wizard@10 { + compatible = "technologic,wizard"; reg = <0x10>; status = "disabled"; - supervisor_adc: supervisor_adc { - compatible = "technologic,supervisor-adc"; + wizard_adc: wizard_adc { + compatible = "technologic,wizard-adc"; #io-channel-cells = <1>; }; - supervisor_temp: supervisor_temp { - compatible = "technologic,supervisor-temp"; + wizard_temp: wizard_temp { + compatible = "technologic,wizard-temp"; #io-channel-cells = <0>; }; }; @@ -177,8 +177,8 @@ status = "disabled"; }; - supervisor_rtc: rtc@68 { - compatible = "technologic,supervisor-rtc"; + wizard_rtc: rtc@68 { + compatible = "technologic,wizard-rtc"; reg = <0x68>; wakeup-source; status = "disabled"; diff --git a/arch/arm/configs/tsimx6ul_defconfig b/arch/arm/configs/tsimx6ul_defconfig index 3d4a9e7305ea8..8f992851b39b3 100644 --- a/arch/arm/configs/tsimx6ul_defconfig +++ b/arch/arm/configs/tsimx6ul_defconfig @@ -658,7 +658,7 @@ CONFIG_GPIO_TS71XXWEIM=y CONFIG_GPIO_PCA953X=m CONFIG_GPIO_TS4900=y CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_TS_SUPERVISOR=y +CONFIG_POWER_RESET_TS_WIZARD=y CONFIG_POWER_RESET_SYSCON=y CONFIG_POWER_RESET_SYSCON_POWEROFF=y CONFIG_SENSORS_IIO_HWMON=y @@ -669,7 +669,7 @@ CONFIG_IMX_THERMAL=y CONFIG_WATCHDOG=y CONFIG_TS_WDT_MICRO=y CONFIG_IMX2_WDT=y -CONFIG_MFD_TS_SUPERVISOR=y +CONFIG_MFD_TS_WIZARD=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_ANATOP=y @@ -798,7 +798,7 @@ CONFIG_RTC_CLASS=y # CONFIG_RTC_NVMEM is not set CONFIG_RTC_INTF_DEV_UIE_EMUL=y CONFIG_RTC_DRV_DS1307=y -CONFIG_RTC_DRV_TSSUPERVISOR=y +CONFIG_RTC_DRV_TSWIZARD=y CONFIG_RTC_DRV_SNVS=y CONFIG_DMADEVICES=y CONFIG_IMX_SDMA=y @@ -810,7 +810,7 @@ CONFIG_IMX_GPCV2_PM_DOMAINS=y CONFIG_IIO=y CONFIG_MMA8452=y CONFIG_TS_SIMPLEADC=y -CONFIG_TS_SUPERVISOR_ADC=y +CONFIG_TS_WIZARD_ADC=y CONFIG_VF610_ADC=y CONFIG_IIO_RESCALE=m CONFIG_INV_MPU6050_I2C=m @@ -821,7 +821,7 @@ CONFIG_MAG3110=y CONFIG_IIO_ST_MAGN_3AXIS=m CONFIG_IIO_SYSFS_TRIGGER=m CONFIG_MPL3115=y -CONFIG_TS_SUPERVISOR_TEMP=y +CONFIG_TS_WIZARD_TEMP=y CONFIG_PWM=y CONFIG_PWM_IMX27=y CONFIG_PWM_TS=m diff --git a/arch/arm/configs/tsimx6ul_minimal_defconfig b/arch/arm/configs/tsimx6ul_minimal_defconfig index 8ed1a8d903a75..7d01cf9e97745 100644 --- a/arch/arm/configs/tsimx6ul_minimal_defconfig +++ b/arch/arm/configs/tsimx6ul_minimal_defconfig @@ -211,7 +211,7 @@ CONFIG_GPIO_TS71XXWEIM=y CONFIG_GPIO_PCA953X=m CONFIG_GPIO_TS4900=y CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_TS_SUPERVISOR=y +CONFIG_POWER_RESET_TS_WIZARD=y CONFIG_POWER_RESET_SYSCON=y CONFIG_POWER_RESET_SYSCON_POWEROFF=y CONFIG_SENSORS_IIO_HWMON=y @@ -222,7 +222,7 @@ CONFIG_IMX_THERMAL=y CONFIG_WATCHDOG=y CONFIG_TS_WDT_MICRO=y CONFIG_IMX2_WDT=y -CONFIG_MFD_TS_SUPERVISOR=y +CONFIG_MFD_TS_WIZARD=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_ANATOP=y @@ -282,7 +282,7 @@ CONFIG_RTC_CLASS=y # CONFIG_RTC_NVMEM is not set CONFIG_RTC_INTF_DEV_UIE_EMUL=y CONFIG_RTC_DRV_DS1307=y -CONFIG_RTC_DRV_TSSUPERVISOR=y +CONFIG_RTC_DRV_TSWIZARD=y CONFIG_RTC_DRV_SNVS=y CONFIG_DMADEVICES=y CONFIG_IMX_SDMA=y @@ -294,7 +294,7 @@ CONFIG_IMX_GPCV2_PM_DOMAINS=y CONFIG_IIO=y CONFIG_MMA8452=y CONFIG_TS_SIMPLEADC=y -CONFIG_TS_SUPERVISOR_ADC=y +CONFIG_TS_WIZARD_ADC=y CONFIG_VF610_ADC=y CONFIG_IIO_RESCALE=m CONFIG_INV_MPU6050_I2C=m @@ -305,7 +305,7 @@ CONFIG_MAG3110=y CONFIG_IIO_ST_MAGN_3AXIS=m CONFIG_IIO_SYSFS_TRIGGER=m CONFIG_MPL3115=y -CONFIG_TS_SUPERVISOR_TEMP=y +CONFIG_TS_WIZARD_TEMP=y CONFIG_PWM=y CONFIG_PWM_IMX27=y CONFIG_PWM_TS=m diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 2cf0fa10ad773..933e4ea022343 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -1805,12 +1805,12 @@ config TS_SIMPLEADC help Say yes here to build support for embeddedTS FPGA based ADC. -config TS_SUPERVISOR_ADC - tristate "embeddedTS Supervisory Microcontroller ADC" +config TS_WIZARD_ADC + tristate "embeddedTS Wizard Microcontroller ADC" depends on OF - depends on MFD_TS_SUPERVISOR + depends on MFD_TS_WIZARD help - Say yes here to build support for embeddedTS supervisory + Say yes here to build support for embeddedTS wizard microcontroller ADC. config TWL4030_MADC diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index 4dc1c19e0d8e8..33008eed64040 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -157,7 +157,7 @@ obj-$(CONFIG_TI_LMP92064) += ti-lmp92064.o obj-$(CONFIG_TI_TLC4541) += ti-tlc4541.o obj-$(CONFIG_TI_TSC2046) += ti-tsc2046.o obj-$(CONFIG_TS_SIMPLEADC) += ts_simple_adc.o -obj-$(CONFIG_TS_SUPERVISOR_ADC) += tssupervisor_adc.o +obj-$(CONFIG_TS_WIZARD_ADC) += tswizard_adc.o obj-$(CONFIG_TWL4030_MADC) += twl4030-madc.o obj-$(CONFIG_TWL6030_GPADC) += twl6030-gpadc.o obj-$(CONFIG_VF610_ADC) += vf610_adc.o diff --git a/drivers/iio/adc/tssupervisor_adc.c b/drivers/iio/adc/tswizard_adc.c similarity index 57% rename from drivers/iio/adc/tssupervisor_adc.c rename to drivers/iio/adc/tswizard_adc.c index dd65e35ac6643..4cbed7874f8a0 100644 --- a/drivers/iio/adc/tssupervisor_adc.c +++ b/drivers/iio/adc/tswizard_adc.c @@ -13,16 +13,16 @@ #include #include #include -#include +#include -#define TS_SUPERVISOR_MAX_ADC 32 +#define TS_WIZARD_MAX_ADC 32 struct ts_adc { - struct ts_supervisor *super; + struct ts_wizard *wiz; uint16_t channel_count; }; -#define SUPERVISOR_CHAN(index) \ +#define WIZARD_CHAN(index) \ { \ .type = IIO_VOLTAGE, \ .indexed = 1, \ @@ -38,39 +38,39 @@ struct ts_adc { }, \ } -static const struct iio_chan_spec tssupervisor_channels[] = { - SUPERVISOR_CHAN(0), - SUPERVISOR_CHAN(1), - SUPERVISOR_CHAN(2), - SUPERVISOR_CHAN(3), - SUPERVISOR_CHAN(4), - SUPERVISOR_CHAN(5), - SUPERVISOR_CHAN(6), - SUPERVISOR_CHAN(7), - SUPERVISOR_CHAN(8), - SUPERVISOR_CHAN(9), - SUPERVISOR_CHAN(10), - SUPERVISOR_CHAN(11), - SUPERVISOR_CHAN(12), - SUPERVISOR_CHAN(13), - SUPERVISOR_CHAN(14), - SUPERVISOR_CHAN(15), - SUPERVISOR_CHAN(16), - SUPERVISOR_CHAN(17), - SUPERVISOR_CHAN(18), - SUPERVISOR_CHAN(19), - SUPERVISOR_CHAN(20), - SUPERVISOR_CHAN(21), - SUPERVISOR_CHAN(22), - SUPERVISOR_CHAN(23), - SUPERVISOR_CHAN(24), - SUPERVISOR_CHAN(25), - SUPERVISOR_CHAN(26), - SUPERVISOR_CHAN(27), - SUPERVISOR_CHAN(28), - SUPERVISOR_CHAN(29), - SUPERVISOR_CHAN(30), - SUPERVISOR_CHAN(31), +static const struct iio_chan_spec tswizard_channels[] = { + WIZARD_CHAN(0), + WIZARD_CHAN(1), + WIZARD_CHAN(2), + WIZARD_CHAN(3), + WIZARD_CHAN(4), + WIZARD_CHAN(5), + WIZARD_CHAN(6), + WIZARD_CHAN(7), + WIZARD_CHAN(8), + WIZARD_CHAN(9), + WIZARD_CHAN(10), + WIZARD_CHAN(11), + WIZARD_CHAN(12), + WIZARD_CHAN(13), + WIZARD_CHAN(14), + WIZARD_CHAN(15), + WIZARD_CHAN(16), + WIZARD_CHAN(17), + WIZARD_CHAN(18), + WIZARD_CHAN(19), + WIZARD_CHAN(20), + WIZARD_CHAN(21), + WIZARD_CHAN(22), + WIZARD_CHAN(23), + WIZARD_CHAN(24), + WIZARD_CHAN(25), + WIZARD_CHAN(26), + WIZARD_CHAN(27), + WIZARD_CHAN(28), + WIZARD_CHAN(29), + WIZARD_CHAN(30), + WIZARD_CHAN(31), }; static int ts_adc_iio_read_raw(struct iio_dev *iio_dev, @@ -84,8 +84,8 @@ static int ts_adc_iio_read_raw(struct iio_dev *iio_dev, switch (mask) { case IIO_CHAN_INFO_RAW: - addr = SUPER_ADC_BASE + chan->channel; - ret = regmap_read(adc->super->regmap, addr, &data); + addr = WIZ_ADC_BASE + chan->channel; + ret = regmap_read(adc->wiz->regmap, addr, &data); if (ret < 0) return ret; *val = data; @@ -104,22 +104,22 @@ static const struct iio_info ts_adc_info = { .read_raw = &ts_adc_iio_read_raw, }; -static int ts_supervisor_adc_probe(struct platform_device *pdev) +static int ts_wizard_adc_probe(struct platform_device *pdev) { - struct ts_supervisor *super = dev_get_drvdata(pdev->dev.parent); + struct ts_wizard *wiz = dev_get_drvdata(pdev->dev.parent); struct ts_adc *adc; struct device *dev = &pdev->dev; struct iio_dev *indio_dev; uint32_t chan_count; int ret; - ret = regmap_read(super->regmap, SUPER_ADC_CHAN_ADV, &chan_count); + ret = regmap_read(wiz->regmap, WIZ_ADC_CHAN_ADV, &chan_count); if (ret < 0) { - dev_err(dev, "error reading reg %u", SUPER_ADC_CHAN_ADV); + dev_err(dev, "error reading reg %u", WIZ_ADC_CHAN_ADV); return ret; } - /* This supervisor does not support ADC channels */ + /* This wizard does not support ADC channels */ if (chan_count == 0) return 0; @@ -127,7 +127,7 @@ static int ts_supervisor_adc_probe(struct platform_device *pdev) if (indio_dev == NULL) return -ENOMEM; adc = iio_priv(indio_dev); - adc->super = super; + adc->wiz = wiz; adc->channel_count = chan_count; /* @@ -135,12 +135,12 @@ static int ts_supervisor_adc_probe(struct platform_device *pdev) * be up to 32 channels depending on muxes onboard and channels that * need to be sampled, but most will be < 7 channels. */ - if (adc->channel_count > TS_SUPERVISOR_MAX_ADC) { + if (adc->channel_count > TS_WIZARD_MAX_ADC) { dev_warn(dev, "The ADC device is advertising more ADC than supported!"); - adc->channel_count = TS_SUPERVISOR_MAX_ADC; + adc->channel_count = TS_WIZARD_MAX_ADC; } indio_dev->num_channels = adc->channel_count; - indio_dev->channels = tssupervisor_channels; + indio_dev->channels = tswizard_channels; indio_dev->name = dev_name(&pdev->dev); indio_dev->dev.of_node = pdev->dev.of_node; @@ -149,21 +149,21 @@ static int ts_supervisor_adc_probe(struct platform_device *pdev) return devm_iio_device_register(&pdev->dev, indio_dev); } -static const struct of_device_id tssupervisor_of_match[] = { - { .compatible = "technologic,tssupervisor-adc", }, +static const struct of_device_id tswizard_of_match[] = { + { .compatible = "technologic,tswizard-adc", }, { } }; MODULE_DEVICE_TABLE(of, tsadc_of_match); static struct platform_driver tsadc_driver = { .driver = { - .name = "tssupervisor-adc", - .of_match_table = tssupervisor_of_match, + .name = "tswizard-adc", + .of_match_table = tswizard_of_match, }, - .probe = ts_supervisor_adc_probe, + .probe = ts_wizard_adc_probe, }; module_platform_driver(tsadc_driver); -MODULE_DESCRIPTION("embeddedTS supervisor adc controller driver"); +MODULE_DESCRIPTION("embeddedTS wizard adc controller driver"); MODULE_AUTHOR("Mark Featherston "); MODULE_LICENSE("GPL"); diff --git a/drivers/iio/temperature/Kconfig b/drivers/iio/temperature/Kconfig index 8dc396e0ef5b1..c84ad1ce1cc86 100644 --- a/drivers/iio/temperature/Kconfig +++ b/drivers/iio/temperature/Kconfig @@ -152,12 +152,12 @@ config MAX30208 This driver can also be built as a module. If so, the module will be called max30208. -config TS_SUPERVISOR_TEMP - tristate "embeddedTS Supervisory Microcontroller TEMP" +config TS_WIZARD_TEMP + tristate "embeddedTS Wizard Microcontroller TEMP" depends on OF - depends on MFD_TS_SUPERVISOR + depends on MFD_TS_WIZARD help - Say yes here to build support for embeddedTS supervisory + Say yes here to build support for embeddedTS wizard microcontroller temperature sensor. config MAX31856 diff --git a/drivers/iio/temperature/Makefile b/drivers/iio/temperature/Makefile index 023d5306d8c47..fa9e8a0e70b2b 100644 --- a/drivers/iio/temperature/Makefile +++ b/drivers/iio/temperature/Makefile @@ -17,6 +17,6 @@ obj-$(CONFIG_MLX90632) += mlx90635.o obj-$(CONFIG_TMP006) += tmp006.o obj-$(CONFIG_TMP007) += tmp007.o obj-$(CONFIG_TMP117) += tmp117.o -obj-$(CONFIG_TS_SUPERVISOR_TEMP) += tssupervisor_temp.o +obj-$(CONFIG_TS_WIZARD_TEMP) += tswizard_temp.o obj-$(CONFIG_TSYS01) += tsys01.o obj-$(CONFIG_TSYS02D) += tsys02d.o diff --git a/drivers/iio/temperature/tssupervisor_temp.c b/drivers/iio/temperature/tswizard_temp.c similarity index 80% rename from drivers/iio/temperature/tssupervisor_temp.c rename to drivers/iio/temperature/tswizard_temp.c index 5f2e754b1d4e7..3da8197c7cee7 100644 --- a/drivers/iio/temperature/tssupervisor_temp.c +++ b/drivers/iio/temperature/tswizard_temp.c @@ -13,10 +13,10 @@ #include #include #include -#include +#include struct ts_temp_adc { - struct ts_supervisor *super; + struct ts_wizard *wiz; }; static const struct iio_chan_spec ts_temp_channel = @@ -33,7 +33,7 @@ static int ts_temp_iio_read_raw(struct iio_dev *iio_dev, int32_t data; int ret; - ret = regmap_read(adc->super->regmap, SUPER_TEMPERATURE, &data); + ret = regmap_read(adc->wiz->regmap, WIZ_TEMPERATURE, &data); if (ret < 0) return ret; @@ -50,9 +50,9 @@ static const struct iio_info ts_adc_info = { .read_raw = &ts_temp_iio_read_raw, }; -static int ts_supervisor_temp_probe(struct platform_device *pdev) +static int ts_wizard_temp_probe(struct platform_device *pdev) { - struct ts_supervisor *super = dev_get_drvdata(pdev->dev.parent); + struct ts_wizard *wiz = dev_get_drvdata(pdev->dev.parent); struct ts_temp_adc *adc; struct device *dev = &pdev->dev; struct iio_dev *indio_dev; @@ -61,7 +61,7 @@ static int ts_supervisor_temp_probe(struct platform_device *pdev) if (indio_dev == NULL) return -ENOMEM; adc = iio_priv(indio_dev); - adc->super = super; + adc->wiz = wiz; /* ADC Channels + 1 temperature sensor */ indio_dev->num_channels = 1; @@ -77,12 +77,12 @@ static int ts_supervisor_temp_probe(struct platform_device *pdev) static struct platform_driver tsadc_driver = { .driver = { - .name = "tssupervisor-temp", + .name = "tswizard-temp", }, - .probe = ts_supervisor_temp_probe, + .probe = ts_wizard_temp_probe, }; module_platform_driver(tsadc_driver); -MODULE_DESCRIPTION("embeddedTS supervisor temperature sensor"); +MODULE_DESCRIPTION("embeddedTS wizard temperature sensor"); MODULE_AUTHOR("Mark Featherston "); MODULE_LICENSE("GPL"); diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 5babb01ffa1dd..19ca96a7397c9 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -2040,13 +2040,13 @@ config MFD_TC3589X additional drivers must be enabled in order to use the functionality of the device. -config MFD_TS_SUPERVISOR - tristate "embeddedTS Supervisor" +config MFD_TS_WIZARD + tristate "embeddedTS Wizard" select MFD_CORE select REGMAP_I2C depends on I2C && OF help - Support for embeddedTS supervisory controller. This includes an adc + Support for embeddedTS wizard controller. This includes an adc driver for system rails, supercap backup management, and some misc controls. diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index d28897ef39df2..e68d56f193eb0 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -34,7 +34,7 @@ obj-$(CONFIG_STMPE_I2C) += stmpe-i2c.o obj-$(CONFIG_STMPE_SPI) += stmpe-spi.o obj-$(CONFIG_MFD_SUN6I_PRCM) += sun6i-prcm.o obj-$(CONFIG_MFD_TC3589X) += tc3589x.o -obj-$(CONFIG_MFD_TS_SUPERVISOR) += tssupervisor-core.o +obj-$(CONFIG_MFD_TS_WIZARD) += tswizard-core.o obj-$(CONFIG_MFD_TQMX86) += tqmx86.o obj-$(CONFIG_MFD_LOCHNAGAR) += lochnagar-i2c.o diff --git a/drivers/mfd/tssupervisor-core.c b/drivers/mfd/tswizard-core.c similarity index 55% rename from drivers/mfd/tssupervisor-core.c rename to drivers/mfd/tswizard-core.c index 423375dd88dbc..d54c9b7df551f 100644 --- a/drivers/mfd/tssupervisor-core.c +++ b/drivers/mfd/tswizard-core.c @@ -7,28 +7,28 @@ #include #include #include -#include +#include #define MODEL_TS_7250_V3 0x7250 -static struct mfd_cell tssupervisor_devs[] = { +static struct mfd_cell tswizard_devs[] = { { - .name = "tssupervisor-reset", + .name = "tswizard-reset", .id = -1, }, { - .name = "tssupervisor-temp", - .of_compatible = "technologic,supervisor-temp", + .name = "tswizard-temp", + .of_compatible = "technologic,wizard-temp", .id = -1, }, { - .name = "tssupervisor-adc", - .of_compatible = "technologic,supervisor-adc", + .name = "tswizard-adc", + .of_compatible = "technologic,wizard-adc", .id = -1, } }; -static const struct regmap_range ts_supervisor_read_regs[] = { +static const struct regmap_range ts_wizard_read_regs[] = { regmap_reg_range(0, 3), /* model/version/advertisements */ regmap_reg_range(16, 16), /* flags */ regmap_reg_range(24, 24), /* inputs */ @@ -37,46 +37,46 @@ static const struct regmap_range ts_supervisor_read_regs[] = { regmap_reg_range(128, 160), /* ADCs+temp */ }; -static const struct regmap_range ts_supervisor_write_regs[] = { +static const struct regmap_range ts_wizard_write_regs[] = { regmap_reg_range(8, 8), /* cmds */ regmap_reg_range(16, 16), /* flags */ regmap_reg_range(34, 37), /* serial */ }; -const struct regmap_access_table ts_supervisor_read_register_set = { - .yes_ranges = ts_supervisor_read_regs, - .n_yes_ranges = ARRAY_SIZE(ts_supervisor_read_regs), +const struct regmap_access_table ts_wizard_read_register_set = { + .yes_ranges = ts_wizard_read_regs, + .n_yes_ranges = ARRAY_SIZE(ts_wizard_read_regs), }; -const struct regmap_access_table ts_supervisor_write_register_set = { - .yes_ranges = ts_supervisor_write_regs, - .n_yes_ranges = ARRAY_SIZE(ts_supervisor_write_regs), +const struct regmap_access_table ts_wizard_write_register_set = { + .yes_ranges = ts_wizard_write_regs, + .n_yes_ranges = ARRAY_SIZE(ts_wizard_write_regs), }; -const struct regmap_config ts_supervisor_i2c_regmap = { +const struct regmap_config ts_wizard_i2c_regmap = { .reg_bits = 16, .val_bits = 16, .can_multi_write = true, .reg_format_endian = REGMAP_ENDIAN_LITTLE, .val_format_endian = REGMAP_ENDIAN_LITTLE, - .wr_table = &ts_supervisor_write_register_set, - .rd_table = &ts_supervisor_read_register_set, - .volatile_table = &ts_supervisor_read_register_set, + .wr_table = &ts_wizard_write_register_set, + .rd_table = &ts_wizard_read_register_set, + .volatile_table = &ts_wizard_read_register_set, .disable_locking = true, .cache_type = REGCACHE_NONE, }; -EXPORT_SYMBOL_GPL(ts_supervisor_i2c_regmap); +EXPORT_SYMBOL_GPL(ts_wizard_i2c_regmap); static ssize_t vbus_present_show(struct device *dev, struct device_attribute *attr, char *buf) { - struct ts_supervisor *super = dev_get_drvdata(dev); + struct ts_wizard *wiz = dev_get_drvdata(dev); unsigned int reg; int ret; - ret = regmap_read(super->regmap, SUPER_INPUTS, ®); + ret = regmap_read(wiz->regmap, WIZ_INPUTS, ®); if (ret) return ret; ret = sprintf(buf, "%d\n", !!(reg & INPUTS_USB_VBUS)); @@ -87,7 +87,7 @@ static DEVICE_ATTR_RO(vbus_present); static ssize_t wake_en_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { - struct ts_supervisor *super = dev_get_drvdata(dev); + struct ts_wizard *wiz = dev_get_drvdata(dev); unsigned int ctrl_reg = 0; bool en; int ret; @@ -99,7 +99,7 @@ static ssize_t wake_en_store(struct device *dev, struct device_attribute *attr, if (en) ctrl_reg |= FLG_WAKE_EN; - ret = regmap_update_bits(super->regmap, SUPER_FLAGS, + ret = regmap_update_bits(wiz->regmap, WIZ_FLAGS, FLG_WAKE_EN, ctrl_reg); @@ -109,11 +109,11 @@ static ssize_t wake_en_store(struct device *dev, struct device_attribute *attr, static ssize_t wake_en_show(struct device *dev, struct device_attribute *attr, char *buf) { - struct ts_supervisor *super = dev_get_drvdata(dev); + struct ts_wizard *wiz = dev_get_drvdata(dev); unsigned int reg; int ret; - ret = regmap_read(super->regmap, SUPER_FLAGS, ®); + ret = regmap_read(wiz->regmap, WIZ_FLAGS, ®); if (ret) return ret; ret = sprintf(buf, "%d\n", !!(reg & FLG_WAKE_EN)); @@ -124,17 +124,17 @@ static DEVICE_ATTR_RW(wake_en); static ssize_t serial_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { - struct ts_supervisor *super = dev_get_drvdata(dev); + struct ts_wizard *wiz = dev_get_drvdata(dev); unsigned int ctrl = 0; u8 sn[6], verify[6]; int ret; - ret = regmap_read(super->regmap, SUPER_SERIAL_CTRL, &ctrl); + ret = regmap_read(wiz->regmap, WIZ_SERIAL_CTRL, &ctrl); if (ret) return ret; /* Dont write the SN if its already written */ - if (ctrl & SUPER_SN_LOCKED) + if (ctrl & WIZ_SN_LOCKED) return -EEXIST; if (count < 17) @@ -144,21 +144,21 @@ static ssize_t serial_store(struct device *dev, struct device_attribute *attr, &sn[0], &sn[1], &sn[2], &sn[3], &sn[4], &sn[5]) != 6) return -EINVAL; - ret = regmap_bulk_write(super->regmap, SUPER_SERIAL0, sn, 3); + ret = regmap_bulk_write(wiz->regmap, WIZ_SERIAL0, sn, 3); if (ret) return ret; /* Verify data before commiting OTP SN */ - ret = regmap_bulk_read(super->regmap, SUPER_SERIAL0, verify, 3); + ret = regmap_bulk_read(wiz->regmap, WIZ_SERIAL0, verify, 3); if (ret) return ret; if (memcmp(verify, sn, 6) != 0) return -EIO; - ret = regmap_update_bits(super->regmap, SUPER_SERIAL_CTRL, - SUPER_SN_LOCKED, - SUPER_SN_LOCKED); + ret = regmap_update_bits(wiz->regmap, WIZ_SERIAL_CTRL, + WIZ_SN_LOCKED, + WIZ_SN_LOCKED); return ret ? ret : count; } @@ -166,20 +166,20 @@ static ssize_t serial_store(struct device *dev, struct device_attribute *attr, static ssize_t serial_show(struct device *dev, struct device_attribute *attr, char *buf) { - struct ts_supervisor *super = dev_get_drvdata(dev); + struct ts_wizard *wiz = dev_get_drvdata(dev); unsigned int ctrl; u8 sn[6]; int ret; - ret = regmap_read(super->regmap, SUPER_SERIAL_CTRL, &ctrl); + ret = regmap_read(wiz->regmap, WIZ_SERIAL_CTRL, &ctrl); if (ret) return ret; /* Dont show the serial number if its not written yet */ - if (!(ctrl & SUPER_SN_LOCKED)) + if (!(ctrl & WIZ_SN_LOCKED)) return -EINVAL; - ret = regmap_bulk_read(super->regmap, SUPER_SERIAL0, sn, 3); + ret = regmap_bulk_read(wiz->regmap, WIZ_SERIAL0, sn, 3); if (ret) return ret; ret = sprintf(buf, "%02x:%02x:%02x:%02x:%02x:%02x\n", @@ -192,7 +192,7 @@ static DEVICE_ATTR_RW(serial); static ssize_t console_cfg_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { - struct ts_supervisor *super = dev_get_drvdata(dev); + struct ts_wizard *wiz = dev_get_drvdata(dev); unsigned int ctrl_reg; int ret; @@ -203,7 +203,7 @@ static ssize_t console_cfg_store(struct device *dev, struct device_attribute *at else return -EINVAL; - ret = regmap_update_bits(super->regmap, SUPER_FLAGS, FLG_FORCE_USB_CON, + ret = regmap_update_bits(wiz->regmap, WIZ_FLAGS, FLG_FORCE_USB_CON, ctrl_reg); return ret ? ret : count; @@ -212,11 +212,11 @@ static ssize_t console_cfg_store(struct device *dev, struct device_attribute *at static ssize_t console_cfg_show(struct device *dev, struct device_attribute *attr, char *buf) { - struct ts_supervisor *super = dev_get_drvdata(dev); + struct ts_wizard *wiz = dev_get_drvdata(dev); unsigned int reg; int ret; - ret = regmap_read(super->regmap, SUPER_FLAGS, ®); + ret = regmap_read(wiz->regmap, WIZ_FLAGS, ®); if (ret) return ret; @@ -249,37 +249,37 @@ static struct attribute_group serial_attr_group = { .attrs = serial_sysfs_entries, }; -static int ts_supervisor_i2c_probe(struct i2c_client *client) +static int ts_wizard_i2c_probe(struct i2c_client *client) { - struct ts_supervisor *super; + struct ts_wizard *wiz; struct device *dev = &client->dev; int err = 0, i; uint32_t model, revision, features; - super = devm_kzalloc(dev, sizeof(struct ts_supervisor), + wiz = devm_kzalloc(dev, sizeof(struct ts_wizard), GFP_KERNEL); - if (!super) + if (!wiz) return -ENOMEM; - dev_set_drvdata(dev, super); + dev_set_drvdata(dev, wiz); - super->client = client; - super->regmap = devm_regmap_init_i2c(client, &ts_supervisor_i2c_regmap); - if (IS_ERR(super->regmap)) { - err = PTR_ERR(super->regmap); + wiz->client = client; + wiz->regmap = devm_regmap_init_i2c(client, &ts_wizard_i2c_regmap); + if (IS_ERR(wiz->regmap)) { + err = PTR_ERR(wiz->regmap); dev_err(dev, "Failed to allocate register map: %d\n", err); return err; } - err = regmap_read(super->regmap, SUPER_MODEL, &model); + err = regmap_read(wiz->regmap, WIZ_MODEL, &model); if (err < 0) - dev_err(dev, "error reading reg %u", SUPER_MODEL); - err = regmap_read(super->regmap, SUPER_REV_INFO, &revision); + dev_err(dev, "error reading reg %u", WIZ_MODEL); + err = regmap_read(wiz->regmap, WIZ_REV_INFO, &revision); if (err < 0) - dev_err(dev, "error reading reg %u", SUPER_REV_INFO); - err = regmap_read(super->regmap, SUPER_FEATURES0, &features); + dev_err(dev, "error reading reg %u", WIZ_REV_INFO); + err = regmap_read(wiz->regmap, WIZ_FEATURES0, &features); if (err < 0) - dev_err(dev, "error reading reg %u", SUPER_FEATURES0); + dev_err(dev, "error reading reg %u", WIZ_FEATURES0); dev_info(&client->dev, "Model %04X rev %d%s\n", model, revision & 0x7fff, @@ -291,44 +291,44 @@ static int ts_supervisor_i2c_probe(struct i2c_client *client) dev_warn(dev, "error creating sysfs entries\n"); } - if (features & SUPER_FEAT_SN) { + if (features & WIZ_FEAT_SN) { err = sysfs_create_group(&dev->kobj, &serial_attr_group); if (err) dev_warn(dev, "error creating sysfs entries\n"); } /* Set up and register the platform devices. */ - for (i = 0; i < ARRAY_SIZE(tssupervisor_devs); i++) { - tssupervisor_devs[i].platform_data = super; - tssupervisor_devs[i].pdata_size = sizeof(struct ts_supervisor); + for (i = 0; i < ARRAY_SIZE(tswizard_devs); i++) { + tswizard_devs[i].platform_data = wiz; + tswizard_devs[i].pdata_size = sizeof(struct ts_wizard); } - return mfd_add_devices(dev, 0, tssupervisor_devs, - ARRAY_SIZE(tssupervisor_devs), NULL, 0, NULL); + return mfd_add_devices(dev, 0, tswizard_devs, + ARRAY_SIZE(tswizard_devs), NULL, 0, NULL); } -static const struct i2c_device_id ts_supervisor_i2c_id[] = { - { "tssupervisor", 0 }, +static const struct i2c_device_id ts_wizard_i2c_id[] = { + { "tswizard", 0 }, { /* sentinel */ } }; -MODULE_DEVICE_TABLE(i2c, ts_supervisor_i2c_id); +MODULE_DEVICE_TABLE(i2c, ts_wizard_i2c_id); -static const struct of_device_id ts_supervisor_i2c_of_match[] = { - { .compatible = "technologic,supervisor", }, +static const struct of_device_id ts_wizard_i2c_of_match[] = { + { .compatible = "technologic,wizard", }, { /* sentinel */ }, }; -MODULE_DEVICE_TABLE(of, ts_supervisor_i2c_of_match); +MODULE_DEVICE_TABLE(of, ts_wizard_i2c_of_match); -static struct i2c_driver ts_supervisor_i2c_driver = { +static struct i2c_driver ts_wizard_i2c_driver = { .driver = { - .name = "tssupervisor-core", - .of_match_table = of_match_ptr(ts_supervisor_i2c_of_match), + .name = "tswizard-core", + .of_match_table = of_match_ptr(ts_wizard_i2c_of_match), }, - .probe = ts_supervisor_i2c_probe, - .id_table = ts_supervisor_i2c_id, + .probe = ts_wizard_i2c_probe, + .id_table = ts_wizard_i2c_id, }; -module_i2c_driver(ts_supervisor_i2c_driver); +module_i2c_driver(ts_wizard_i2c_driver); MODULE_AUTHOR("Mark Featherston "); -MODULE_DESCRIPTION("Core driver for embeddedTS Supervisory microcontroller"); +MODULE_DESCRIPTION("Core driver for embeddedTS Wizard microcontroller"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig index a45187d44a51f..bee67b13deae1 100644 --- a/drivers/power/reset/Kconfig +++ b/drivers/power/reset/Kconfig @@ -252,9 +252,9 @@ config POWER_RESET_TPS65086 help This driver adds support for resetting the TPS65086 PMIC on restart. -config POWER_RESET_TS_SUPERVISOR - bool "embeddedTS Supervisory reset driver" - depends on MFD_TS_SUPERVISOR +config POWER_RESET_TS_WIZARD + bool "embeddedTS Wizard reset driver" + depends on MFD_TS_WIZARD help Reset support for embeddedTS boards diff --git a/drivers/power/reset/Makefile b/drivers/power/reset/Makefile index 50c82f9f63417..38004fa00bf30 100644 --- a/drivers/power/reset/Makefile +++ b/drivers/power/reset/Makefile @@ -28,7 +28,7 @@ obj-$(CONFIG_POWER_RESET_ST) += st-poweroff.o obj-$(CONFIG_POWER_RESET_TH1520_AON) += th1520-aon-reboot.o obj-$(CONFIG_POWER_RESET_TORADEX_EC) += tdx-ec-poweroff.o obj-$(CONFIG_POWER_RESET_TPS65086) += tps65086-restart.o -obj-$(CONFIG_POWER_RESET_TS_SUPERVISOR) += tssupervisor-reset.o +obj-$(CONFIG_POWER_RESET_TS_WIZARD) += tswizard-reset.o obj-$(CONFIG_POWER_RESET_VERSATILE) += arm-versatile-reboot.o obj-$(CONFIG_POWER_RESET_VEXPRESS) += vexpress-poweroff.o obj-$(CONFIG_POWER_RESET_XGENE) += xgene-reboot.o diff --git a/drivers/power/reset/tssupervisor-reset.c b/drivers/power/reset/tswizard-reset.c similarity index 58% rename from drivers/power/reset/tssupervisor-reset.c rename to drivers/power/reset/tswizard-reset.c index 284f67f73147c..615d8e9d7e030 100644 --- a/drivers/power/reset/tssupervisor-reset.c +++ b/drivers/power/reset/tswizard-reset.c @@ -6,7 +6,7 @@ #include #include #include -#include +#include /* We need a static device to support this for shutdown/reboot hooks */ static struct device *ts_rstc_device; @@ -15,13 +15,13 @@ static atomic_t ts_restart_nb_refcnt = ATOMIC_INIT(0); static ssize_t reboot_reason_show(struct device *dev, struct device_attribute *attr, char *buf) { - struct ts_supervisor *super = dev_get_drvdata(dev); + struct ts_wizard *wiz = dev_get_drvdata(dev); uint32_t reason; int len, err; - err = regmap_read(super->regmap, SUPER_REBOOT_REASON, &reason); + err = regmap_read(wiz->regmap, WIZ_REBOOT_REASON, &reason); if (err < 0) - dev_err(dev, "error reading reg %u", SUPER_REBOOT_REASON); + dev_err(dev, "error reading reg %u", WIZ_REBOOT_REASON); switch (reason) { case REBOOT_REASON_POR: @@ -60,24 +60,24 @@ static ssize_t reboot_reason_show(struct device *dev, } static DEVICE_ATTR_RO(reboot_reason); -static struct attribute *ts_supervisor_sysfs_entries[] = { +static struct attribute *ts_wizard_sysfs_entries[] = { &dev_attr_reboot_reason.attr, NULL, }; -static struct attribute_group ts_supervisor_attr_group = { - .attrs = ts_supervisor_sysfs_entries, +static struct attribute_group ts_wizard_attr_group = { + .attrs = ts_wizard_sysfs_entries, }; -static int ts_supervisor_restart(struct notifier_block *this, +static int ts_wizard_restart(struct notifier_block *this, unsigned long mode, void *cmd) { int err = -ENOENT; - struct ts_supervisor *super = dev_get_drvdata(ts_rstc_device); + struct ts_wizard *wiz = dev_get_drvdata(ts_rstc_device); - if (super) { - err = regmap_write(super->regmap, SUPER_CMDS, I2C_REBOOT); + if (wiz) { + err = regmap_write(wiz->regmap, WIZ_CMDS, I2C_REBOOT); if (!err) mdelay(1000); } @@ -87,18 +87,18 @@ static int ts_supervisor_restart(struct notifier_block *this, return NOTIFY_DONE; } -static struct notifier_block ts_supervisor_restart_nb = { - .notifier_call = ts_supervisor_restart, +static struct notifier_block ts_wizard_restart_nb = { + .notifier_call = ts_wizard_restart, .priority = 128, }; -static void ts_supervisor_poweroff(void) +static void ts_wizard_poweroff(void) { int err = -ENOENT; - struct ts_supervisor *super = dev_get_drvdata(ts_rstc_device); + struct ts_wizard *wiz = dev_get_drvdata(ts_rstc_device); - if (super) { - err = regmap_write(super->regmap, SUPER_CMDS, I2C_HALT); + if (wiz) { + err = regmap_write(wiz->regmap, WIZ_CMDS, I2C_HALT); if (!err) mdelay(1000); } @@ -106,28 +106,28 @@ static void ts_supervisor_poweroff(void) dev_emerg(ts_rstc_device, "Unable to call halt (%d)", err); } -static int ts_supervisor_rstc_probe(struct platform_device *pdev) +static int ts_wizard_rstc_probe(struct platform_device *pdev) { - struct ts_supervisor *super = dev_get_drvdata(pdev->dev.parent); + struct ts_wizard *wiz = dev_get_drvdata(pdev->dev.parent); struct device *dev = &pdev->dev; uint32_t features; int err = 0; - err = regmap_read(super->regmap, SUPER_FEATURES0, &features); + err = regmap_read(wiz->regmap, WIZ_FEATURES0, &features); if (err < 0) - dev_err(dev, "error reading reg %u", SUPER_FEATURES0); + dev_err(dev, "error reading reg %u", WIZ_FEATURES0); - if ((features & SUPER_FEAT_RSTC) == 0) { - /* Reset controller not supported on this supervisor */ + if ((features & WIZ_FEAT_RSTC) == 0) { + /* Reset controller not supported on this wizard */ return 0; } - dev_set_drvdata(dev, super); + dev_set_drvdata(dev, wiz); if (atomic_inc_return(&ts_restart_nb_refcnt) == 1) { ts_rstc_device = dev; - pm_power_off = ts_supervisor_poweroff; + pm_power_off = ts_wizard_poweroff; - err = register_restart_handler(&ts_supervisor_restart_nb); + err = register_restart_handler(&ts_wizard_restart_nb); if (err) { dev_err(dev, "cannot register restart handler (err=%d)\n", err); atomic_dec(&ts_restart_nb_refcnt); @@ -138,24 +138,24 @@ static int ts_supervisor_rstc_probe(struct platform_device *pdev) dev_err(dev, "rstc already registered"); } - err = sysfs_create_group(&dev->kobj, &ts_supervisor_attr_group); + err = sysfs_create_group(&dev->kobj, &ts_wizard_attr_group); if (err) dev_warn(dev, "error creating sysfs entries\n"); - dev_info(dev, "Using supervisor for reset controller"); + dev_info(dev, "Using wizard for reset controller"); return 0; } -static struct platform_driver tssupervisor_rstc_driver = { +static struct platform_driver tswizard_rstc_driver = { .driver = { - .name = "tssupervisor-reset", + .name = "tswizard-reset", }, - .probe = ts_supervisor_rstc_probe, + .probe = ts_wizard_rstc_probe, }; -module_platform_driver(tssupervisor_rstc_driver); +module_platform_driver(tswizard_rstc_driver); -MODULE_DESCRIPTION("embeddedTS supervisor reset controller driver"); +MODULE_DESCRIPTION("embeddedTS wizard reset controller driver"); MODULE_AUTHOR("Mark Featherston "); MODULE_LICENSE("GPL"); diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 1be6242ff727e..2f59236c01eac 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -575,11 +575,11 @@ config RTC_DRV_BQ32K This driver can also be built as a module. If so, the module will be called rtc-bq32k. -config RTC_DRV_TSSUPERVISOR - tristate "embeddedTS Supervisory Microcontroller RTC" +config RTC_DRV_TSWIZARD + tristate "embeddedTS Wizard Microcontroller RTC" select REGMAP_I2C help - Supports the RTC on embeddedTS Supervisory microcontroller + Supports the RTC on embeddedTS Wizard microcontroller config RTC_DRV_TWL92330 bool "TI TWL92330/Menelaus" diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index f5f06a9d520ae..9ff21c9c23d71 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -189,7 +189,7 @@ obj-$(CONFIG_RTC_DRV_TI_K3) += rtc-ti-k3.o obj-$(CONFIG_RTC_DRV_TPS6586X) += rtc-tps6586x.o obj-$(CONFIG_RTC_DRV_TPS6594) += rtc-tps6594.o obj-$(CONFIG_RTC_DRV_TPS65910) += rtc-tps65910.o -obj-$(CONFIG_RTC_DRV_TSSUPERVISOR) += rtc-tssupervisor.o +obj-$(CONFIG_RTC_DRV_TSWIZARD) += rtc-tswizard.o obj-$(CONFIG_RTC_DRV_TWL4030) += rtc-twl.o obj-$(CONFIG_RTC_DRV_VT8500) += rtc-vt8500.o obj-$(CONFIG_RTC_DRV_WILCO_EC) += rtc-wilco-ec.o diff --git a/drivers/rtc/rtc-tssupervisor.c b/drivers/rtc/rtc-tswizard.c similarity index 57% rename from drivers/rtc/rtc-tssupervisor.c rename to drivers/rtc/rtc-tswizard.c index ae114e2c59cef..0b7996403cc9e 100644 --- a/drivers/rtc/rtc-tssupervisor.c +++ b/drivers/rtc/rtc-tswizard.c @@ -1,8 +1,8 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * RTC for embeddedts's supervisory microcontroller + * RTC for embeddedts's wizard microcontroller * Alarm does not have an IRQ, controls wakeup or reset from the external - * supervisory microcontroller. + * wizard microcontroller. */ #include @@ -43,21 +43,21 @@ #define RTC_PPB_CTL_SIGN (1 << 1) /* 1 = positive, 0 = negative */ #define RTC_PPB_CTL_EN (1 << 0) /* Calibration is applied anytime this is 1*/ -struct supervisor_rtc { +struct wizard_rtc { struct device *dev; struct regmap *regmap; const char *name; struct rtc_device *rtc; }; -static int supervisor_rtc_get_time(struct device *dev, struct rtc_time *tm) +static int wizard_rtc_get_time(struct device *dev, struct rtc_time *tm) { - struct supervisor_rtc *super = dev_get_drvdata(dev); + struct wizard_rtc *wiz = dev_get_drvdata(dev); time64_t timestamp = 0; unsigned int reg; int ret; - ret = regmap_read(super->regmap, RTC_FLAGS, ®); + ret = regmap_read(wiz->regmap, RTC_FLAGS, ®); if (ret) return ret; @@ -65,7 +65,7 @@ static int supervisor_rtc_get_time(struct device *dev, struct rtc_time *tm) if (reg & RTC_FLAGS_OF) return -EINVAL; - ret = regmap_bulk_read(super->regmap, RTC_EPOCH_0, ×tamp, 4); + ret = regmap_bulk_read(wiz->regmap, RTC_EPOCH_0, ×tamp, 4); if (ret) return ret; @@ -74,26 +74,26 @@ static int supervisor_rtc_get_time(struct device *dev, struct rtc_time *tm) return 0; } -static int supervisor_rtc_set_time(struct device *dev, struct rtc_time *tm) +static int wizard_rtc_set_time(struct device *dev, struct rtc_time *tm) { - struct supervisor_rtc *super = dev_get_drvdata(dev); + struct wizard_rtc *wiz = dev_get_drvdata(dev); time64_t timestamp = rtc_tm_to_time64(tm); - return regmap_bulk_write(super->regmap, RTC_EPOCH_0, ×tamp, 4); + return regmap_bulk_write(wiz->regmap, RTC_EPOCH_0, ×tamp, 4); } -static int supervisor_rtc_read_offset(struct device *dev, long *offset) +static int wizard_rtc_read_offset(struct device *dev, long *offset) { - struct supervisor_rtc *super = dev_get_drvdata(dev); + struct wizard_rtc *wiz = dev_get_drvdata(dev); unsigned int ctrl_reg; uint32_t ppb; int ret; - ret = regmap_bulk_read(super->regmap, RTC_PPB_0, &ppb, sizeof(ppb)); + ret = regmap_bulk_read(wiz->regmap, RTC_PPB_0, &ppb, sizeof(ppb)); if (ret) return ret; - ret = regmap_read(super->regmap, RTC_PPB_CTL, &ctrl_reg); + ret = regmap_read(wiz->regmap, RTC_PPB_CTL, &ctrl_reg); if (ret) return ret; @@ -106,30 +106,30 @@ static int supervisor_rtc_read_offset(struct device *dev, long *offset) return 0; } -static int supervisor_rtc_set_offset(struct device *dev, long offset) +static int wizard_rtc_set_offset(struct device *dev, long offset) { - struct supervisor_rtc *super = dev_get_drvdata(dev); + struct wizard_rtc *wiz = dev_get_drvdata(dev); unsigned int ctrl_reg = RTC_PPB_CTL_EN; u32 ppb = (uint32_t)offset; int ret; - ret = regmap_bulk_write(super->regmap, RTC_PPB_0, &ppb, sizeof(ppb)); + ret = regmap_bulk_write(wiz->regmap, RTC_PPB_0, &ppb, sizeof(ppb)); if (ret) return ret; if (offset >= 0) ctrl_reg |= RTC_PPB_CTL_SIGN; - return regmap_update_bits(super->regmap, RTC_FLAGS, + return regmap_update_bits(wiz->regmap, RTC_FLAGS, RTC_PPB_CTL_SIGN | RTC_PPB_CTL_EN, ctrl_reg); } -static const struct rtc_class_ops supervisor_rtc_ops = { - .read_time = supervisor_rtc_get_time, - .set_time = supervisor_rtc_set_time, - .read_offset = supervisor_rtc_read_offset, - .set_offset = supervisor_rtc_set_offset, +static const struct rtc_class_ops wizard_rtc_ops = { + .read_time = wizard_rtc_get_time, + .set_time = wizard_rtc_set_time, + .read_offset = wizard_rtc_read_offset, + .set_offset = wizard_rtc_set_offset, }; static const struct regmap_config regmap_config = { @@ -142,7 +142,7 @@ static ssize_t alarm_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { - struct supervisor_rtc *super = dev_get_drvdata(dev); + struct wizard_rtc *wiz = dev_get_drvdata(dev); unsigned long timestamp; int ret; @@ -150,7 +150,7 @@ static ssize_t alarm_store(struct device *dev, if (ret) return ret; - ret = regmap_bulk_write(super->regmap, RTC_ALARM_0, ×tamp, 4); + ret = regmap_bulk_write(wiz->regmap, RTC_ALARM_0, ×tamp, 4); if (ret) return ret; @@ -160,12 +160,12 @@ static ssize_t alarm_store(struct device *dev, static ssize_t alarm_show(struct device *dev, struct device_attribute *attr, char *buf) { - struct supervisor_rtc *super = dev_get_drvdata(dev); + struct wizard_rtc *wiz = dev_get_drvdata(dev); u32 timestamp; int len; int ret; - ret = regmap_bulk_read(super->regmap, RTC_ALARM_0, ×tamp, 4); + ret = regmap_bulk_read(wiz->regmap, RTC_ALARM_0, ×tamp, 4); if (ret) return ret; @@ -178,7 +178,7 @@ static DEVICE_ATTR_RW(alarm); static ssize_t alarm_en_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { - struct supervisor_rtc *super = dev_get_drvdata(dev); + struct wizard_rtc *wiz = dev_get_drvdata(dev); unsigned int ctrl_reg = 0; bool en; int ret; @@ -190,7 +190,7 @@ static ssize_t alarm_en_store(struct device *dev, struct device_attribute *attr, if (en) ctrl_reg |= RTC_FLAGS_ALARM_EN; - ret = regmap_update_bits(super->regmap, RTC_FLAGS, + ret = regmap_update_bits(wiz->regmap, RTC_FLAGS, RTC_FLAGS_ALARM_EN, ctrl_reg); @@ -200,11 +200,11 @@ static ssize_t alarm_en_store(struct device *dev, struct device_attribute *attr, static ssize_t alarm_en_show(struct device *dev, struct device_attribute *attr, char *buf) { - struct supervisor_rtc *super = dev_get_drvdata(dev); + struct wizard_rtc *wiz = dev_get_drvdata(dev); unsigned int reg; int ret; - ret = regmap_read(super->regmap, RTC_FLAGS, ®); + ret = regmap_read(wiz->regmap, RTC_FLAGS, ®); if (ret) return ret; ret = sprintf(buf, "%d\n", !!(reg & RTC_FLAGS_ALARM_EN)); @@ -216,7 +216,7 @@ static ssize_t alarm_cause_reboot_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { - struct supervisor_rtc *super = dev_get_drvdata(dev); + struct wizard_rtc *wiz = dev_get_drvdata(dev); unsigned int ctrl_reg = 0; bool en; int ret; @@ -228,7 +228,7 @@ static ssize_t alarm_cause_reboot_store(struct device *dev, if (en) ctrl_reg |= RTC_FLAGS_ALARM_REBOOT; - ret = regmap_update_bits(super->regmap, RTC_FLAGS, + ret = regmap_update_bits(wiz->regmap, RTC_FLAGS, RTC_FLAGS_ALARM_REBOOT, ctrl_reg); @@ -238,11 +238,11 @@ static ssize_t alarm_cause_reboot_store(struct device *dev, static ssize_t alarm_cause_reboot_show(struct device *dev, struct device_attribute *attr, char *buf) { - struct supervisor_rtc *super = dev_get_drvdata(dev); + struct wizard_rtc *wiz = dev_get_drvdata(dev); unsigned int reg; int ret; - ret = regmap_read(super->regmap, RTC_FLAGS, ®); + ret = regmap_read(wiz->regmap, RTC_FLAGS, ®); if (ret) return ret; ret = sprintf(buf, "%d\n", !!(reg & RTC_FLAGS_ALARM_REBOOT)); @@ -253,11 +253,11 @@ static DEVICE_ATTR_RW(alarm_cause_reboot); static ssize_t batt_present_show(struct device *dev, struct device_attribute *attr, char *buf) { - struct supervisor_rtc *super = dev_get_drvdata(dev); + struct wizard_rtc *wiz = dev_get_drvdata(dev); unsigned int reg; int ret; - ret = regmap_read(super->regmap, RTC_FLAGS, ®); + ret = regmap_read(wiz->regmap, RTC_FLAGS, ®); if (ret) return ret; ret = sprintf(buf, "%d\n", !!(reg & RTC_FLAGS_BATT_PRESENT)); @@ -265,7 +265,7 @@ static ssize_t batt_present_show(struct device *dev, } static DEVICE_ATTR_RO(batt_present); -static struct attribute *supervisor_rtc_sysfs_entries[] = { +static struct attribute *wizard_rtc_sysfs_entries[] = { &dev_attr_alarm_en.attr, &dev_attr_alarm.attr, &dev_attr_alarm_cause_reboot.attr, @@ -273,69 +273,69 @@ static struct attribute *supervisor_rtc_sysfs_entries[] = { NULL, }; -static struct attribute_group supervisor_rtc_attr_group = { - .attrs = supervisor_rtc_sysfs_entries, +static struct attribute_group wizard_rtc_attr_group = { + .attrs = wizard_rtc_sysfs_entries, }; -static int supervisor_rtc_probe(struct i2c_client *client) +static int wizard_rtc_probe(struct i2c_client *client) { - struct supervisor_rtc *super; + struct wizard_rtc *wiz; struct device *dev = &client->dev; int err = -ENODEV; - super = devm_kzalloc(dev, sizeof(struct supervisor_rtc), GFP_KERNEL); - if (!super) + wiz = devm_kzalloc(dev, sizeof(struct wizard_rtc), GFP_KERNEL); + if (!wiz) return -ENOMEM; - dev_set_drvdata(dev, super); - super->dev = dev; - super->name = client->name; - super->regmap = devm_regmap_init_i2c(client, ®map_config); - if (IS_ERR(super->regmap)) { + dev_set_drvdata(dev, wiz); + wiz->dev = dev; + wiz->name = client->name; + wiz->regmap = devm_regmap_init_i2c(client, ®map_config); + if (IS_ERR(wiz->regmap)) { dev_err(dev, "regmap allocation failed\n"); - return PTR_ERR(super->regmap); + return PTR_ERR(wiz->regmap); } - i2c_set_clientdata(client, super); + i2c_set_clientdata(client, wiz); - super->rtc = devm_rtc_allocate_device(dev); - if (IS_ERR(super->rtc)) - return PTR_ERR(super->rtc); + wiz->rtc = devm_rtc_allocate_device(dev); + if (IS_ERR(wiz->rtc)) + return PTR_ERR(wiz->rtc); - err = sysfs_create_group(&dev->kobj, &supervisor_rtc_attr_group); + err = sysfs_create_group(&dev->kobj, &wizard_rtc_attr_group); if (err) dev_warn(dev, "error creating sysfs entries\n"); - super->rtc->ops = &supervisor_rtc_ops; - err = devm_rtc_register_device(super->rtc); + wiz->rtc->ops = &wizard_rtc_ops; + err = devm_rtc_register_device(wiz->rtc); if (err) return err; return 0; } -static const struct i2c_device_id tssupervisor_rtc_id[] = { - { "tssupervisor_rtc", 0 }, +static const struct i2c_device_id tswizard_rtc_id[] = { + { "tswizard_rtc", 0 }, { } }; -MODULE_DEVICE_TABLE(i2c, tssupervisor_rtc_id); +MODULE_DEVICE_TABLE(i2c, tswizard_rtc_id); -static const struct of_device_id tssupervisor_rtc_of_match[] = { - { .compatible = "technologic,supervisor-rtc", }, +static const struct of_device_id tswizard_rtc_of_match[] = { + { .compatible = "technologic,wizard-rtc", }, { } }; -MODULE_DEVICE_TABLE(of, tssupervisor_rtc_of_match); +MODULE_DEVICE_TABLE(of, tswizard_rtc_of_match); -static struct i2c_driver supervisor_rtc_driver = { +static struct i2c_driver wizard_rtc_driver = { .driver = { - .name = "rtc-tssupervisor", - .of_match_table = of_match_ptr(tssupervisor_rtc_of_match), + .name = "rtc-tswizard", + .of_match_table = of_match_ptr(tswizard_rtc_of_match), }, - .probe = supervisor_rtc_probe, - .id_table = tssupervisor_rtc_id, + .probe = wizard_rtc_probe, + .id_table = tswizard_rtc_id, }; -module_i2c_driver(supervisor_rtc_driver); +module_i2c_driver(wizard_rtc_driver); -MODULE_DESCRIPTION("RTC driver for embeddedTS supervisory microcontroller"); +MODULE_DESCRIPTION("RTC driver for embeddedTS wizard microcontroller"); MODULE_LICENSE("GPL"); diff --git a/include/linux/mfd/ts_supervisor.h b/include/linux/mfd/ts_wizard.h similarity index 53% rename from include/linux/mfd/ts_supervisor.h rename to include/linux/mfd/ts_wizard.h index d29feaa3bc47e..6ce7b173249b2 100644 --- a/include/linux/mfd/ts_supervisor.h +++ b/include/linux/mfd/ts_wizard.h @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#ifndef __LINUX_MFD_TS_SUPERVISOR_H -#define __LINUX_MFD_TS_SUPERVISOR_H +#ifndef __LINUX_MFD_TS_WIZARD_H +#define __LINUX_MFD_TS_WIZARD_H -struct ts_supervisor { +struct ts_wizard { struct i2c_client *client; struct regmap *regmap; struct platform_device *rstc_pdev; @@ -11,21 +11,21 @@ struct ts_supervisor { }; /* I2C Register addresses */ -#define SUPER_MODEL 0 -#define SUPER_REV_INFO 1 -#define SUPER_ADC_CHAN_ADV 2 -#define SUPER_FEATURES0 3 -#define SUPER_CMDS 8 -#define SUPER_FLAGS 16 -#define SUPER_INPUTS 24 -#define SUPER_REBOOT_REASON 32 -#define SUPER_SERIAL0 34 -#define SUPER_SERIAL1 35 -#define SUPER_SERIAL2 36 -#define SUPER_SERIAL_CTRL 37 -#define SUPER_ADC_BASE 128 -#define SUPER_ADC_LAST 159 -#define SUPER_TEMPERATURE 160 +#define WIZ_MODEL 0 +#define WIZ_REV_INFO 1 +#define WIZ_ADC_CHAN_ADV 2 +#define WIZ_FEATURES0 3 +#define WIZ_CMDS 8 +#define WIZ_FLAGS 16 +#define WIZ_INPUTS 24 +#define WIZ_REBOOT_REASON 32 +#define WIZ_SERIAL0 34 +#define WIZ_SERIAL1 35 +#define WIZ_SERIAL2 36 +#define WIZ_SERIAL_CTRL 37 +#define WIZ_ADC_BASE 128 +#define WIZ_ADC_LAST 159 +#define WIZ_TEMPERATURE 160 enum gen_flags_t { FLG_FORCE_USB_CON = (1 << 4), @@ -38,10 +38,10 @@ enum gen_inputs_t { INPUTS_USB_VBUS = (1 << 0), }; -enum super_features_t { - SUPER_FEAT_SN = (1 << 2), - SUPER_FEAT_FWUPD = (1 << 1), - SUPER_FEAT_RSTC = (1 << 0), +enum wiz_features_t { + WIZ_FEAT_SN = (1 << 2), + WIZ_FEAT_FWUPD = (1 << 1), + WIZ_FEAT_RSTC = (1 << 0), }; enum reboot_reasons_t { @@ -56,13 +56,13 @@ enum reboot_reasons_t { REBOOT_REASON_WAKE_FROM_USB_VBUS = 8, }; -enum super_cmds_t { +enum wiz_cmds_t { I2C_REBOOT = (1 << 0), I2C_HALT = (1 << 1), }; -enum super_serial_ctrl_t { - SUPER_SN_LOCKED = (1 << 0), +enum wiz_serial_ctrl_t { + WIZ_SN_LOCKED = (1 << 0), }; #endif \ No newline at end of file From 2e15571ed3412c56d182de21885c42e863fe8553 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Fri, 15 Aug 2025 21:31:27 +0000 Subject: [PATCH 202/244] DELETE ME! Tracking changes to max3100-ts the "hard" way by diffing .c and -ts.c in 6.6 and applying those changes here. Saving this now to instead test copying in -ts.c from 6.6 and apply the patches between 6.6 and 6.12 to .c to the -ts.c file. Hoping this would be an easier route. Signed-off-by: Kris Bahnsen --- max3100-ts.c | 853 ++++++++++++++++++++++++++++++++++++ max3100-ts.c.rej | 882 +++++++++++++++++++++++++++++++++++++ max3100.diff | 1076 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 2811 insertions(+) create mode 100644 max3100-ts.c create mode 100644 max3100-ts.c.rej create mode 100644 max3100.diff diff --git a/max3100-ts.c b/max3100-ts.c new file mode 100644 index 0000000000000..dc27c84f4d235 --- /dev/null +++ b/max3100-ts.c @@ -0,0 +1,853 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2008 Christian Pellegrin + * + * Notes: the MAX3100 doesn't provide an interrupt on CTS so we have + * to use polling for flow control. TX empty IRQ is unusable, since + * writing conf clears FIFO buffer and we cannot have this interrupt + * always asking us for attention. + * + * The initial minor number is 209 in the low-density serial port: + * mknod /dev/ttyMAX0 c 204 209 + */ + + /* + Modified from the original max3100.c to support the embeddedTS + MAX3100 extended UARTs. This device puts 3 MAX3100-like uarts in one + chip, but with only a single CS# line going to the chip, and a single + IRQ pin. This requires that all SPI transactions are preceded by a byte + to indicate which of the 3 uarts is being accessed. On an interrupt, + there's no way to tell which of the uarts generated it, so we have to + check 'em all. + */ + +#define MAX3100_MAJOR 204 +#define MAX3100_MINOR 209 + /* + One max3100ts may contain up to 64 uarts. + This driver supports only one max3100ts + */ +#define MAX_MAX3100 64 + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define MAX3100_C (1<<14) +#define MAX3100_D (0<<14) +#define MAX3100_W (1<<15) +#define MAX3100_RX (0<<15) + +#define MAX3100_WC (MAX3100_W | MAX3100_C) +#define MAX3100_RC (MAX3100_RX | MAX3100_C) +#define MAX3100_WD (MAX3100_W | MAX3100_D) +#define MAX3100_RD (MAX3100_RX | MAX3100_D) +#define MAX3100_CMD (3 << 14) + +#define MAX3100_T (1<<14) +#define MAX3100_R (1<<15) + +#define MAX3100_FEN (1<<13) +#define MAX3100_SHDN (1<<12) +#define MAX3100_TM (1<<11) +#define MAX3100_RM (1<<10) +#define MAX3100_PM (1<<9) +#define MAX3100_RAM (1<<8) +#define MAX3100_IR (1<<7) +#define MAX3100_ST (1<<6) +#define MAX3100_PE (1<<5) +#define MAX3100_L (1<<4) +#define MAX3100_BAUD (0xf) + +#define MAX3100_TE (1<<10) +#define MAX3100_RAFE (1<<10) +#define MAX3100_RTS (1<<9) +#define MAX3100_CTS (1<<9) +#define MAX3100_PT (1<<8) +#define MAX3100_DATA (0xff) + +#define MAX3100_RT (MAX3100_R | MAX3100_T) +#define MAX3100_RTC (MAX3100_RT | MAX3100_CTS | MAX3100_RAFE) + +/* the following simulate a status reg for ignore_status_mask */ +#define MAX3100_STATUS_PE 1 +#define MAX3100_STATUS_FE 2 +#define MAX3100_STATUS_OE 4 + +#define MAX3100_CSI 0xc0 + +struct max3100ts_port { + struct uart_port port; + //struct spi_device *spi; + + int cts; /* last CTS received for flow ctrl */ + int tx_empty; /* last TX empty bit */ + + int conf_commit; /* need to make changes */ + int conf; /* configuration for the MAX31000 + * (bits 0-7, bits 8-11 are irqs) */ + int rts_commit; /* need to change rts */ + int rts; /* rts status */ + int baud; /* current baud rate */ + + int parity; /* keeps track if we should send parity */ +#define MAX3100_PARITY_ON 1 +#define MAX3100_PARITY_ODD 2 +#define MAX3100_7BIT 4 + int rx_enabled; /* if we should rx chars */ + + int minor; /* minor number */ + int loopback_commit; /* need to change loopback */ + int loopback; /* 1 if we are in loopback mode */ + + /* for handling irqs: need workqueue since we do spi_sync */ + struct workqueue_struct *workqueue; + struct work_struct work; + /* set to 1 to make the workhandler exit as soon as possible */ + int force_end_work; + /* need to know we are suspending to avoid deadlock on workqueue */ + int suspending; + + struct timer_list timer; +}; + +static inline struct max3100_port *to_max3100_port(struct uart_port *port) +{ + return container_of(port, struct max3100_port, port); +} + +static struct max3100_port *max3100s[MAX_MAX3100]; /* the chips */ +static DEFINE_MUTEX(max3100s_lock); /* race on probe */ + +static int max3100_do_parity(struct max3100_port *s, u16 c) +{ + int parity; + + if (s->parity & MAX3100_PARITY_ODD) + parity = 1; + else + parity = 0; + + if (s->parity & MAX3100_7BIT) + c &= 0x7f; + else + c &= 0xff; + + parity = parity ^ (hweight8(c) & 1); + return parity; +} + +static int max3100_check_parity(struct max3100ts_port *s, u16 c) +{ + return max3100_do_parity(s, c) == ((c >> 8) & 1); +} + +static void max3100_calc_parity(struct max3100ts_port *s, u16 * c) +{ + if (s->parity & MAX3100_7BIT) + *c &= 0x7f; + else + *c &= 0xff; + + if (s->parity & MAX3100_PARITY_ON) + *c |= max3100_do_parity(s, *c) << 8; +} + +static int max3100_sr(struct max3100_port *s, u16 tx, u16 *rx) +{ + struct spi_message message; + __be16 etx, erx; + int status; + struct spi_transfer tran = { + .tx_buf = &etx, + .rx_buf = &erx, + .len = 2, + }; + + etx = cpu_to_be16(tx); + spi_message_init(&message); + spi_message_add_tail(&tran, &message); + status = spi_sync(s->spi, &message); + if (status) { + dev_warn(&s->spi->dev, "error while calling spi_sync\n"); + return -EIO; + } + *rx = be16_to_cpu(erx); + s->tx_empty = (*rx & MAX3100_T) > 0; + dev_dbg(&s->spi->dev, "%04x - %04x\n", tx, *rx); + return 0; +} + +static int max3100_handlerx_unlocked(struct max3100_port *s, u16 rx) +{ + unsigned int status = 0; + int ret = 0, cts; + u8 ch, flg; + + if (rx & MAX3100_R && s->rx_enabled) { + dev_dbg(&s->spi->dev, "%s\n", __func__); + ch = rx & (s->parity & MAX3100_7BIT ? 0x7f : 0xff); + if (rx & MAX3100_RAFE) { + s->port.icount.frame++; + flg = TTY_FRAME; + status |= MAX3100_STATUS_FE; + } else { + if (s->parity & MAX3100_PARITY_ON) { + if (max3100_check_parity(s, rx)) { + s->port.icount.rx++; + flg = TTY_NORMAL; + } else { + s->port.icount.parity++; + flg = TTY_PARITY; + status |= MAX3100_STATUS_PE; + } + } else { + s->port.icount.rx++; + flg = TTY_NORMAL; + } + } + uart_insert_char(&s->port, status, MAX3100_STATUS_OE, ch, flg); + ret = 1; + } + + cts = (rx & MAX3100_CTS) > 0; + if (s->cts != cts) { + s->cts = cts; + uart_handle_cts_change(&s->port, cts); + } + + return ret; +} + +static int max3100_handlerx(struct max3100_port *s, u16 rx) +{ + unsigned long flags; + int ret; + + uart_port_lock_irqsave(&s->port, &flags); + ret = max3100_handlerx_unlocked(s, rx); + uart_port_unlock_irqrestore(&s->port, flags); + return ret; +} + +static void max3100_work(struct work_struct *w) +{ + struct max3100_port *s = container_of(w, struct max3100_port, work); + struct tty_port *tport = &s->port.state->port; + unsigned char ch; + int conf, cconf, cloopback, crts; + int rxchars; + u16 tx, rx; + + dev_dbg(&s->spi->dev, "%s\n", __func__); + + rxchars = 0; + do { + spin_lock(&s->conf_lock); + conf = s->conf; + cconf = s->conf_commit; + s->conf_commit = 0; + cloopback = s->loopback_commit; + s->loopback_commit = 0; + crts = s->rts_commit; + s->rts_commit = 0; + spin_unlock(&s->conf_lock); + if (cconf) + max3100_sr(s, MAX3100_WC | conf, &rx); + if (cloopback) + max3100_sr(s, 0x4001, &rx); + if (crts) { + max3100_sr(s, MAX3100_WD | MAX3100_TE | + (s->rts ? MAX3100_RTS : 0), &rx); + rxchars += max3100_handlerx(s, rx); + } + + max3100_sr(s, MAX3100_RD, &rx); + rxchars += max3100_handlerx(s, rx); + + if (rx & MAX3100_T) { + tx = 0xffff; + if (s->port.x_char) { + tx = s->port.x_char; + s->port.icount.tx++; + s->port.x_char = 0; + } else if (!uart_tx_stopped(&s->port) && + uart_fifo_get(&s->port, &ch)) { + tx = ch; + } + if (tx != 0xffff) { + max3100_calc_parity(s, &tx); + tx |= MAX3100_WD | (s->rts ? MAX3100_RTS : 0); + max3100_sr(s, tx, &rx); + rxchars += max3100_handlerx(s, rx); + } + } + + if (rxchars > 16) { + tty_flip_buffer_push(&s->port.state->port); + rxchars = 0; + } + if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) + uart_write_wakeup(&s->port); + + } while (!s->force_end_work && + !freezing(current) && + ((rx & MAX3100_R) || + (!kfifo_is_empty(&tport->xmit_fifo) && + !uart_tx_stopped(&s->port)))); + + if (rxchars > 0) + tty_flip_buffer_push(&s->port.state->port); +} + +static void max3100_dowork(struct max3100_port *s) +{ + if (!s->force_end_work && !freezing(current) && !s->suspending) + queue_work(s->workqueue, &s->work); +} + +static void max3100_timeout(struct timer_list *t) +{ + struct max3100_port *s = from_timer(s, t, timer); + + max3100_dowork(s); + mod_timer(&s->timer, jiffies + uart_poll_timeout(&s->port)); +} + +static irqreturn_t max3100_irq(int irqno, void *dev_id) +{ + struct max3100_port *s = dev_id; + + dev_dbg(&s->spi->dev, "%s\n", __func__); + + max3100_dowork(s); + return IRQ_HANDLED; +} + +static void max3100_enable_ms(struct uart_port *port) +{ + struct max3100_port *s = to_max3100_port(port); + + mod_timer(&s->timer, jiffies); + dev_dbg(&s->spi->dev, "%s\n", __func__); +} + +static void max3100_start_tx(struct uart_port *port) +{ + struct max3100_port *s = to_max3100_port(port); + + dev_dbg(&s->spi->dev, "%s\n", __func__); + + max3100_dowork(s); +} + +static void max3100_stop_rx(struct uart_port *port) +{ + struct max3100_port *s = to_max3100_port(port); + + dev_dbg(&s->spi->dev, "%s\n", __func__); + + s->rx_enabled = 0; + spin_lock(&s->conf_lock); + s->conf &= ~MAX3100_RM; + s->conf_commit = 1; + spin_unlock(&s->conf_lock); + max3100_dowork(s); +} + +static unsigned int max3100_tx_empty(struct uart_port *port) +{ + struct max3100_port *s = to_max3100_port(port); + + dev_dbg(&s->spi->dev, "%s\n", __func__); + + /* may not be truly up-to-date */ + max3100_dowork(s); + return s->tx_empty; +} + +static unsigned int max3100_get_mctrl(struct uart_port *port) +{ + struct max3100_port *s = to_max3100_port(port); + + dev_dbg(&s->spi->dev, "%s\n", __func__); + + /* may not be truly up-to-date */ + max3100_dowork(s); + /* always assert DCD and DSR since these lines are not wired */ + return (s->cts ? TIOCM_CTS : 0) | TIOCM_DSR | TIOCM_CAR; +} + +static void max3100_set_mctrl(struct uart_port *port, unsigned int mctrl) +{ + struct max3100_port *s = to_max3100_port(port); + int loopback, rts; + + dev_dbg(&s->spi->dev, "%s\n", __func__); + + loopback = (mctrl & TIOCM_LOOP) > 0; + rts = (mctrl & TIOCM_RTS) > 0; + + spin_lock(&s->conf_lock); + if (s->loopback != loopback) { + s->loopback = loopback; + s->loopback_commit = 1; + } + if (s->rts != rts) { + s->rts = rts; + s->rts_commit = 1; + } + if (s->loopback_commit || s->rts_commit) + max3100_dowork(s); + spin_unlock(&s->conf_lock); +} + +static void +max3100_set_termios(struct uart_port *port, struct ktermios *termios, + const struct ktermios *old) +{ + struct max3100_port *s = to_max3100_port(port); + unsigned int baud = port->uartclk / 16; + unsigned int baud230400 = (baud == 230400) ? 1 : 0; + unsigned cflag; + u32 param_new, param_mask, parity = 0; + + dev_dbg(&s->spi->dev, "%s\n", __func__); + + cflag = termios->c_cflag; + param_mask = 0; + + baud = tty_termios_baud_rate(termios); + param_new = s->conf & MAX3100_BAUD; + switch (baud) { + case 300: + if (baud230400) + baud = s->baud; + else + param_new = 15; + break; + case 600: + param_new = 14 + baud230400; + break; + case 1200: + param_new = 13 + baud230400; + break; + case 2400: + param_new = 12 + baud230400; + break; + case 4800: + param_new = 11 + baud230400; + break; + case 9600: + param_new = 10 + baud230400; + break; + case 19200: + param_new = 9 + baud230400; + break; + case 38400: + param_new = 8 + baud230400; + break; + case 57600: + param_new = 1 + baud230400; + break; + case 115200: + param_new = 0 + baud230400; + break; + case 230400: + if (baud230400) + param_new = 0; + else + baud = s->baud; + break; + default: + baud = s->baud; + } + tty_termios_encode_baud_rate(termios, baud, baud); + s->baud = baud; + param_mask |= MAX3100_BAUD; + + if ((cflag & CSIZE) == CS8) { + param_new &= ~MAX3100_L; + parity &= ~MAX3100_7BIT; + } else { + param_new |= MAX3100_L; + parity |= MAX3100_7BIT; + cflag = (cflag & ~CSIZE) | CS7; + } + param_mask |= MAX3100_L; + + if (cflag & CSTOPB) + param_new |= MAX3100_ST; + else + param_new &= ~MAX3100_ST; + param_mask |= MAX3100_ST; + + if (cflag & PARENB) { + param_new |= MAX3100_PE; + parity |= MAX3100_PARITY_ON; + } else { + param_new &= ~MAX3100_PE; + parity &= ~MAX3100_PARITY_ON; + } + param_mask |= MAX3100_PE; + + if (cflag & PARODD) + parity |= MAX3100_PARITY_ODD; + else + parity &= ~MAX3100_PARITY_ODD; + + /* mask termios capabilities we don't support */ + cflag &= ~CMSPAR; + termios->c_cflag = cflag; + + s->port.ignore_status_mask = 0; + if (termios->c_iflag & IGNPAR) + s->port.ignore_status_mask |= + MAX3100_STATUS_PE | MAX3100_STATUS_FE | + MAX3100_STATUS_OE; + + del_timer_sync(&s->timer); + uart_update_timeout(port, termios->c_cflag, baud); + + spin_lock(&s->conf_lock); + s->conf = (s->conf & ~param_mask) | (param_new & param_mask); + s->conf_commit = 1; + s->parity = parity; + spin_unlock(&s->conf_lock); + max3100_dowork(s); + + if (UART_ENABLE_MS(&s->port, termios->c_cflag)) + max3100_enable_ms(&s->port); +} + +static void max3100_shutdown(struct uart_port *port) +{ + struct max3100_port *s = to_max3100_port(port); + u16 rx; + + dev_dbg(&s->spi->dev, "%s\n", __func__); + + if (s->suspending) + return; + + s->force_end_work = 1; + + del_timer_sync(&s->timer); + + if (s->workqueue) { + destroy_workqueue(s->workqueue); + s->workqueue = NULL; + } + if (port->irq) + free_irq(port->irq, s); + + /* set shutdown mode to save power */ + max3100_sr(s, MAX3100_WC | MAX3100_SHDN, &rx); +} + +static int max3100_startup(struct uart_port *port) +{ + struct max3100_port *s = to_max3100_port(port); + char b[12]; + int ret; + + dev_dbg(&s->spi->dev, "%s\n", __func__); + + s->conf = MAX3100_RM; + s->baud = port->uartclk / 16; + s->rx_enabled = 1; + + if (s->suspending) + return 0; + + s->force_end_work = 0; + s->parity = 0; + s->rts = 0; + + sprintf(b, "max3100-%d", s->minor); + s->workqueue = create_freezable_workqueue(b); + if (!s->workqueue) { + dev_warn(&s->spi->dev, "cannot create workqueue\n"); + return -EBUSY; + } + INIT_WORK(&s->work, max3100_work); + + ret = request_irq(port->irq, max3100_irq, IRQF_TRIGGER_FALLING, "max3100", s); + if (ret < 0) { + dev_warn(&s->spi->dev, "cannot allocate irq %d\n", port->irq); + port->irq = 0; + destroy_workqueue(s->workqueue); + s->workqueue = NULL; + return -EBUSY; + } + + s->conf_commit = 1; + max3100_dowork(s); + /* wait for clock to settle */ + msleep(50); + + max3100_enable_ms(&s->port); + + return 0; +} + +static const char *max3100_type(struct uart_port *port) +{ + struct max3100_port *s = to_max3100_port(port); + + dev_dbg(&s->spi->dev, "%s\n", __func__); + + return s->port.type == PORT_MAX3100 ? "MAX3100" : NULL; +} + +static void max3100_release_port(struct uart_port *port) +{ + struct max3100_port *s = to_max3100_port(port); + + dev_dbg(&s->spi->dev, "%s\n", __func__); +} + +static void max3100_config_port(struct uart_port *port, int flags) +{ + struct max3100_port *s = to_max3100_port(port); + + dev_dbg(&s->spi->dev, "%s\n", __func__); + + if (flags & UART_CONFIG_TYPE) + s->port.type = PORT_MAX3100; +} + +static int max3100_verify_port(struct uart_port *port, + struct serial_struct *ser) +{ + struct max3100_port *s = to_max3100_port(port); + int ret = -EINVAL; + + dev_dbg(&s->spi->dev, "%s\n", __func__); + + if (ser->type == PORT_UNKNOWN || ser->type == PORT_MAX3100) + ret = 0; + return ret; +} + +static void max3100_stop_tx(struct uart_port *port) +{ + struct max3100_port *s = to_max3100_port(port); + + dev_dbg(&s->spi->dev, "%s\n", __func__); +} + +static int max3100_request_port(struct uart_port *port) +{ + struct max3100_port *s = to_max3100_port(port); + + dev_dbg(&s->spi->dev, "%s\n", __func__); + return 0; +} + +static void max3100_break_ctl(struct uart_port *port, int break_state) +{ + struct max3100_port *s = to_max3100_port(port); + + dev_dbg(&s->spi->dev, "%s\n", __func__); +} + +static const struct uart_ops max3100_ops = { + .tx_empty = max3100_tx_empty, + .set_mctrl = max3100_set_mctrl, + .get_mctrl = max3100_get_mctrl, + .stop_tx = max3100_stop_tx, + .start_tx = max3100_start_tx, + .stop_rx = max3100_stop_rx, + .enable_ms = max3100_enable_ms, + .break_ctl = max3100_break_ctl, + .startup = max3100_startup, + .shutdown = max3100_shutdown, + .set_termios = max3100_set_termios, + .type = max3100_type, + .release_port = max3100_release_port, + .request_port = max3100_request_port, + .config_port = max3100_config_port, + .verify_port = max3100_verify_port, +}; + +static struct uart_driver max3100_uart_driver = { + .owner = THIS_MODULE, + .driver_name = "ttyMAX", + .dev_name = "ttyMAX", + .major = MAX3100_MAJOR, + .minor = MAX3100_MINOR, + .nr = MAX_MAX3100, +}; +static int uart_driver_registered; + +static int max3100_probe(struct spi_device *spi) +{ + struct device *dev = &spi->dev; + int i, retval; + u16 rx; + + mutex_lock(&max3100s_lock); + + if (!uart_driver_registered) { + retval = uart_register_driver(&max3100_uart_driver); + if (retval) { + mutex_unlock(&max3100s_lock); + return dev_err_probe(dev, retval, "Couldn't register max3100 uart driver\n"); + } + + uart_driver_registered = 1; + } + + for (i = 0; i < MAX_MAX3100; i++) + if (!max3100s[i]) + break; + if (i == MAX_MAX3100) { + mutex_unlock(&max3100s_lock); + return dev_err_probe(dev, -ENOMEM, "too many MAX3100 chips\n"); + } + + max3100s[i] = kzalloc(sizeof(struct max3100_port), GFP_KERNEL); + if (!max3100s[i]) { + mutex_unlock(&max3100s_lock); + return -ENOMEM; + } + max3100s[i]->spi = spi; + spin_lock_init(&max3100s[i]->conf_lock); + spi_set_drvdata(spi, max3100s[i]); + max3100s[i]->minor = i; + timer_setup(&max3100s[i]->timer, max3100_timeout, 0); + + dev_dbg(&spi->dev, "%s: adding port %d\n", __func__, i); + max3100s[i]->port.irq = spi->irq; + max3100s[i]->port.fifosize = 16; + max3100s[i]->port.ops = &max3100_ops; + max3100s[i]->port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF; + max3100s[i]->port.line = i; + max3100s[i]->port.type = PORT_MAX3100; + max3100s[i]->port.dev = &spi->dev; + + /* Read clock frequency from a property, uart_add_one_port() will fail if it's not set */ + device_property_read_u32(dev, "clock-frequency", &max3100s[i]->port.uartclk); + + retval = uart_add_one_port(&max3100_uart_driver, &max3100s[i]->port); + if (retval < 0) + dev_err_probe(dev, retval, "uart_add_one_port failed for line %d\n", i); + + /* set shutdown mode to save power. Will be woken-up on open */ + max3100_sr(max3100s[i], MAX3100_WC | MAX3100_SHDN, &rx); + mutex_unlock(&max3100s_lock); + return 0; +} + +static void max3100_remove(struct spi_device *spi) +{ + struct max3100_port *s = spi_get_drvdata(spi); + int i; + + mutex_lock(&max3100s_lock); + + /* find out the index for the chip we are removing */ + for (i = 0; i < MAX_MAX3100; i++) + if (max3100s[i] == s) { + dev_dbg(&spi->dev, "%s: removing port %d\n", __func__, i); + uart_remove_one_port(&max3100_uart_driver, &max3100s[i]->port); + kfree(max3100s[i]); + max3100s[i] = NULL; + break; + } + + WARN_ON(i == MAX_MAX3100); + + /* check if this is the last chip we have */ + for (i = 0; i < MAX_MAX3100; i++) + if (max3100s[i]) { + mutex_unlock(&max3100s_lock); + return; + } + pr_debug("removing max3100 driver\n"); + uart_unregister_driver(&max3100_uart_driver); + uart_driver_registered = 0; + + mutex_unlock(&max3100s_lock); +} + +static int max3100_suspend(struct device *dev) +{ + struct max3100_port *s = dev_get_drvdata(dev); + u16 rx; + + dev_dbg(&s->spi->dev, "%s\n", __func__); + + disable_irq(s->port.irq); + + s->suspending = 1; + uart_suspend_port(&max3100_uart_driver, &s->port); + + /* no HW suspend, so do SW one */ + max3100_sr(s, MAX3100_WC | MAX3100_SHDN, &rx); + return 0; +} + +static int max3100_resume(struct device *dev) +{ + struct max3100_port *s = dev_get_drvdata(dev); + + dev_dbg(&s->spi->dev, "%s\n", __func__); + + uart_resume_port(&max3100_uart_driver, &s->port); + s->suspending = 0; + + enable_irq(s->port.irq); + + s->conf_commit = 1; + if (s->workqueue) + max3100_dowork(s); + + return 0; +} + +static DEFINE_SIMPLE_DEV_PM_OPS(max3100_pm_ops, max3100_suspend, max3100_resume); + +static const struct spi_device_id max3100_spi_id[] = { + { "max3100" }, + { } +}; +MODULE_DEVICE_TABLE(spi, max3100_spi_id); + +static const struct of_device_id max3100_of_match[] = { + { .compatible = "maxim,max3100" }, + { } +}; +MODULE_DEVICE_TABLE(of, max3100_of_match); + +static struct spi_driver max3100_driver = { + .driver = { + .name = "max3100", + .of_match_table = max3100_of_match, + .pm = pm_sleep_ptr(&max3100_pm_ops), + }, + .probe = max3100_probe, + .remove = max3100_remove, + .id_table = max3100_spi_id, +}; + +module_spi_driver(max3100_driver); + +MODULE_DESCRIPTION("MAX3100 driver"); +MODULE_AUTHOR("Christian Pellegrin "); +MODULE_LICENSE("GPL"); diff --git a/max3100-ts.c.rej b/max3100-ts.c.rej new file mode 100644 index 0000000000000..b437433315803 --- /dev/null +++ b/max3100-ts.c.rej @@ -0,0 +1,882 @@ +--- drivers/tty/serial/max3100-ts.c 2025-08-15 19:06:13.131568176 +0000 ++++ drivers/tty/serial/max3100-ts.c 2025-08-15 19:06:13.131568176 +0000 +-static int max3100_handlerx_unlocked(struct max3100_port *s, u16 rx) ++static int max3100_handlerx(struct max3100ts_port *s, u16 rx) + { +- unsigned int status = 0; ++ unsigned int ch, flg, status = 0; + int ret = 0, cts; +- u8 ch, flg; ++ unsigned long flags; + + if (rx & MAX3100_R && s->rx_enabled) { +- dev_dbg(&s->spi->dev, "%s\n", __func__); ++ dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); ++ + ch = rx & (s->parity & MAX3100_7BIT ? 0x7f : 0xff); ++ spin_lock_irqsave(&s->port.lock, flags); + if (rx & MAX3100_RAFE) { + s->port.icount.frame++; + flg = TTY_FRAME; +@@ -258,49 +312,49 @@ + flg = TTY_NORMAL; + } + } ++ spin_unlock_irqrestore(&s->port.lock, flags); ++ + uart_insert_char(&s->port, status, MAX3100_STATUS_OE, ch, flg); + ret = 1; + } + + cts = (rx & MAX3100_CTS) > 0; + if (s->cts != cts) { ++ spin_lock_irqsave(&s->port.lock, flags); + s->cts = cts; +- uart_handle_cts_change(&s->port, cts); ++ uart_handle_cts_change(&s->port, cts ? 1 : 0); ++ spin_unlock_irqrestore(&s->port.lock, flags); + } + + return ret; + } + +-static int max3100_handlerx(struct max3100_port *s, u16 rx) ++static void max3100_port_dowork(struct max3100ts_port *s) + { +- unsigned long flags; +- int ret; +- +- uart_port_lock_irqsave(&s->port, &flags); +- ret = max3100_handlerx_unlocked(s, rx); +- uart_port_unlock_irqrestore(&s->port, flags); +- return ret; +-} +- +-static void max3100_work(struct work_struct *w) +-{ +- struct max3100_port *s = container_of(w, struct max3100_port, work); +- int rxchars; ++ int rxchars, x; + u16 tx, rx; + int conf, cconf, crts; ++ unsigned long flags; + struct circ_buf *xmit = &s->port.state->xmit; + +- dev_dbg(&s->spi->dev, "%s\n", __func__); ++ dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + + rxchars = 0; ++ ++ /* Since the do/while loop has its while conditional at the end which ++ * some of the calls are dependant on holding the lock, each loop must ++ * start with the lock held since we need the lock when the while is ++ * checked. ++ */ ++ spin_lock_irqsave(&s->port.lock, flags); + do { +- spin_lock(&s->conf_lock); + conf = s->conf; + cconf = s->conf_commit; + s->conf_commit = 0; + crts = s->rts_commit; + s->rts_commit = 0; +- spin_unlock(&s->conf_lock); ++ spin_unlock_irqrestore(&s->port.lock, flags); ++ + if (cconf) + max3100_sr(s, MAX3100_WC | conf, &rx); + if (crts) { +@@ -309,152 +363,191 @@ + rxchars += max3100_handlerx(s, rx); + } + +- max3100_sr(s, MAX3100_RD, &rx); +- rxchars += max3100_handlerx(s, rx); +- +- if (rx & MAX3100_T) { +- tx = 0xffff; ++ x = 0; ++ /* Lock in case we need to call uart_circ_empty() */ ++ spin_lock_irqsave(&s->port.lock, flags); + if (s->port.x_char) { + tx = s->port.x_char; +- s->port.icount.tx++; +- s->port.x_char = 0; +- } else if (!uart_circ_empty(xmit) && +- !uart_tx_stopped(&s->port)) { ++ x = 1; ++ } else{ ++ if(!s->force_end_work){ ++ if (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) { + tx = xmit->buf[xmit->tail]; +- uart_xmit_advance(&s->port, 1); ++ x = 2; ++ } + } +- if (tx != 0xffff) { ++ } ++ spin_unlock_irqrestore(&s->port.lock, flags); ++ ++ if (x) { /* we have something to send, so send it! */ + max3100_calc_parity(s, &tx); + tx |= MAX3100_WD | (s->rts ? MAX3100_RTS : 0); + max3100_sr(s, tx, &rx); + rxchars += max3100_handlerx(s, rx); ++ ++ if (rx & MAX3100_T) { /* Tx buffer is/was empty, so tx was sent */ ++ spin_lock_irqsave(&s->port.lock, flags); ++ if (x == 1) { ++ s->port.icount.tx++; ++ s->port.x_char = 0; ++ } else if (x == 2) { ++ xmit->tail = (xmit->tail + 1) & ++ (UART_XMIT_SIZE - 1); ++ s->port.icount.tx++; + } ++ spin_unlock_irqrestore(&s->port.lock, flags); ++ } ++ } else { ++ max3100_sr(s, MAX3100_RD, &rx); ++ rxchars += max3100_handlerx(s, rx); + } + +- if (rxchars > 16) { ++ /* A balance between servicing the UART and getting data to ++ * userspace */ ++ if (rxchars > 31) { + tty_flip_buffer_push(&s->port.state->port); + rxchars = 0; + } +- if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) ++ ++ /* This is a bit funky, but, according to docs, all xmit ++ * head/tail accesses need to be inside of the port->lock. ++ * Grab the lock now, and if we break out of the while ++ * loop, then release the lock. This hopefully should reduce ++ * number of acquisitions for a bit of a performance gain. ++ */ ++ spin_lock_irqsave(&s->port.lock, flags); ++ if (uart_circ_chars_pending(xmit) < 4){ ++ if(s->port.state->port.tty) + uart_write_wakeup(&s->port); ++ } + + } while (!s->force_end_work && + !freezing(current) && + ((rx & MAX3100_R) || +- (!uart_circ_empty(xmit) && +- !uart_tx_stopped(&s->port)))); ++ (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)))); + +- if (rxchars > 0) ++ spin_unlock_irqrestore(&s->port.lock, flags); ++ ++ if (rxchars) + tty_flip_buffer_push(&s->port.state->port); + } + +-static irqreturn_t max3100_irq(int irqno, void *dev_id) ++static void max3100_port_work(struct work_struct *w) + { +- struct max3100_port *s = dev_id; ++ struct max3100ts_port *s = container_of(w, struct max3100ts_port, work); ++ mutex_lock(&max3100ts_common.portlock); ++ max3100_port_dowork(s); ++ mutex_unlock(&max3100ts_common.portlock); ++} + +- dev_dbg(&s->spi->dev, "%s\n", __func__); ++/* Threaded handler called in a sleepable context */ ++static irqreturn_t max3100_thread_irq(int irqno, void *dev_id) ++{ ++ int i; ++ ++ dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); ++ ++ for (i = 0; i < max3100ts_common.uart_count; i++) { ++ struct max3100ts_port *s = max3100ts_common.max3100ts[i]; ++ mutex_lock(&max3100ts_common.portlock); ++ max3100_port_dowork(s); ++ mutex_unlock(&max3100ts_common.portlock); ++ } + +- max3100_dowork(s); + return IRQ_HANDLED; + } + + static void max3100_enable_ms(struct uart_port *port) + { +- struct max3100_port *s = container_of(port, +- struct max3100_port, ++ struct max3100ts_port *s = container_of(port, ++ struct max3100ts_port, + port); + + if (s->poll_time > 0) + mod_timer(&s->timer, jiffies); +- dev_dbg(&s->spi->dev, "%s\n", __func__); ++ dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + } + + static void max3100_start_tx(struct uart_port *port) + { +- struct max3100_port *s = container_of(port, +- struct max3100_port, ++ struct max3100ts_port *s = container_of(port, ++ struct max3100ts_port, + port); + +- dev_dbg(&s->spi->dev, "%s\n", __func__); ++ dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + +- max3100_dowork(s); ++ max3100_schedule_work(s); + } + + static void max3100_stop_rx(struct uart_port *port) + { +- struct max3100_port *s = container_of(port, +- struct max3100_port, ++ struct max3100ts_port *s = container_of(port, ++ struct max3100ts_port, + port); + +- dev_dbg(&s->spi->dev, "%s\n", __func__); ++ dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + ++ /* NOTE: port->lock already taken when this function is called */ + s->rx_enabled = 0; +- spin_lock(&s->conf_lock); + s->conf &= ~MAX3100_RM; + s->conf_commit = 1; +- spin_unlock(&s->conf_lock); +- max3100_dowork(s); + } + + static unsigned int max3100_tx_empty(struct uart_port *port) + { +- struct max3100_port *s = container_of(port, +- struct max3100_port, ++ struct max3100ts_port *s = container_of(port, ++ struct max3100ts_port, + port); + +- dev_dbg(&s->spi->dev, "%s\n", __func__); ++ dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + + /* may not be truly up-to-date */ +- max3100_dowork(s); ++ max3100_schedule_work(s); + return s->tx_empty; + } + + static unsigned int max3100_get_mctrl(struct uart_port *port) + { +- struct max3100_port *s = container_of(port, +- struct max3100_port, ++ struct max3100ts_port *s = container_of(port, ++ struct max3100ts_port, + port); + +- dev_dbg(&s->spi->dev, "%s\n", __func__); ++ dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + +- /* may not be truly up-to-date */ +- max3100_dowork(s); + /* always assert DCD and DSR since these lines are not wired */ + return (s->cts ? TIOCM_CTS : 0) | TIOCM_DSR | TIOCM_CAR; + } + + static void max3100_set_mctrl(struct uart_port *port, unsigned int mctrl) + { +- struct max3100_port *s = container_of(port, +- struct max3100_port, ++ struct max3100ts_port *s = container_of(port, ++ struct max3100ts_port, + port); + int rts; + +- dev_dbg(&s->spi->dev, "%s\n", __func__); ++ dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + + rts = (mctrl & TIOCM_RTS) > 0; + +- spin_lock(&s->conf_lock); + if (s->rts != rts) { + s->rts = rts; + s->rts_commit = 1; +- max3100_dowork(s); + } +- spin_unlock(&s->conf_lock); + } + + static void + max3100_set_termios(struct uart_port *port, struct ktermios *termios, + const struct ktermios *old) + { +- struct max3100_port *s = container_of(port, +- struct max3100_port, ++ struct max3100ts_port *s = container_of(port, ++ struct max3100ts_port, + port); + int baud = 0; + unsigned cflag; ++ unsigned long flags; + u32 param_new, param_mask, parity = 0; + +- dev_dbg(&s->spi->dev, "%s\n", __func__); ++ dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + + cflag = termios->c_cflag; + param_mask = 0; +@@ -545,20 +638,22 @@ + s->port.ignore_status_mask = 0; + if (termios->c_iflag & IGNPAR) + s->port.ignore_status_mask |= +- MAX3100_STATUS_PE | MAX3100_STATUS_FE | +- MAX3100_STATUS_OE; ++ MAX3100_STATUS_PE | MAX3100_STATUS_FE | MAX3100_STATUS_OE; + + if (s->poll_time > 0) + del_timer_sync(&s->timer); + + uart_update_timeout(port, termios->c_cflag, baud); + +- spin_lock(&s->conf_lock); ++ spin_lock_irqsave(&s->port.lock, flags); + s->conf = (s->conf & ~param_mask) | (param_new & param_mask); + s->conf_commit = 1; + s->parity = parity; +- spin_unlock(&s->conf_lock); +- max3100_dowork(s); ++ spin_unlock_irqrestore(&s->port.lock, flags); ++ ++ mutex_lock(&max3100ts_common.portlock); ++ max3100_port_dowork(s); ++ mutex_unlock(&max3100ts_common.portlock); + + if (UART_ENABLE_MS(&s->port, termios->c_cflag)) + max3100_enable_ms(&s->port); +@@ -566,26 +661,28 @@ + + static void max3100_shutdown(struct uart_port *port) + { +- struct max3100_port *s = container_of(port, +- struct max3100_port, ++ struct max3100ts_port *s = container_of(port, ++ struct max3100ts_port, + port); + +- dev_dbg(&s->spi->dev, "%s\n", __func__); ++ dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + + if (s->suspending) + return; + ++ /* Make sure any dowork from the irq thread are finished */ + s->force_end_work = 1; ++ mutex_lock(&max3100ts_common.portlock); ++ mutex_unlock(&max3100ts_common.portlock); + + if (s->poll_time > 0) + del_timer_sync(&s->timer); + + if (s->workqueue) { ++ flush_workqueue(s->workqueue); + destroy_workqueue(s->workqueue); + s->workqueue = NULL; + } +- if (s->irq) +- free_irq(s->irq, s); + + /* set shutdown mode to save power */ + if (s->max3100_hw_suspend) +@@ -594,20 +691,22 @@ + u16 tx, rx; + + tx = MAX3100_WC | MAX3100_SHDN; ++ mutex_lock(&max3100ts_common.portlock); + max3100_sr(s, tx, &rx); ++ mutex_unlock(&max3100ts_common.portlock); + } + } + + static int max3100_startup(struct uart_port *port) + { +- struct max3100_port *s = container_of(port, +- struct max3100_port, ++ struct max3100ts_port *s = container_of(port, ++ struct max3100ts_port, + port); + char b[12]; + +- dev_dbg(&s->spi->dev, "%s\n", __func__); ++ dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + +- s->conf = MAX3100_RM; ++ s->conf = MAX3100_RM | MAX3100_TM; + s->baud = s->crystal ? 230400 : 115200; + s->rx_enabled = 1; + +@@ -619,33 +718,28 @@ + s->rts = 0; + + sprintf(b, "max3100-%d", s->minor); +- s->workqueue = create_freezable_workqueue(b); ++ s->workqueue = create_singlethread_workqueue(b); + if (!s->workqueue) { +- dev_warn(&s->spi->dev, "cannot create workqueue\n"); +- return -EBUSY; +- } +- INIT_WORK(&s->work, max3100_work); +- +- if (request_irq(s->irq, max3100_irq, +- IRQF_TRIGGER_FALLING, "max3100", s) < 0) { +- dev_warn(&s->spi->dev, "cannot allocate irq %d\n", s->irq); +- s->irq = 0; +- destroy_workqueue(s->workqueue); +- s->workqueue = NULL; ++ dev_warn(&max3100ts_common.spi->dev, ++ "cannot create workqueue\n"); + return -EBUSY; + } ++ INIT_WORK(&s->work, max3100_port_work); + + if (s->loopback) { + u16 tx, rx; + tx = 0x4001; ++ mutex_lock(&max3100ts_common.portlock); + max3100_sr(s, tx, &rx); ++ mutex_unlock(&max3100ts_common.portlock); + } + + if (s->max3100_hw_suspend) + s->max3100_hw_suspend(0); + s->conf_commit = 1; +- max3100_dowork(s); ++ + /* wait for clock to settle */ ++ if (s->port.line == 0) + msleep(50); + + max3100_enable_ms(&s->port); +@@ -655,31 +749,27 @@ + + static const char *max3100_type(struct uart_port *port) + { +- struct max3100_port *s = container_of(port, +- struct max3100_port, ++ struct max3100ts_port *s = container_of(port, ++ struct max3100ts_port, + port); + +- dev_dbg(&s->spi->dev, "%s\n", __func__); ++ dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + + return s->port.type == PORT_MAX3100 ? "MAX3100" : NULL; + } + + static void max3100_release_port(struct uart_port *port) + { +- struct max3100_port *s = container_of(port, +- struct max3100_port, +- port); +- +- dev_dbg(&s->spi->dev, "%s\n", __func__); ++ dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + } + + static void max3100_config_port(struct uart_port *port, int flags) + { +- struct max3100_port *s = container_of(port, +- struct max3100_port, ++ struct max3100ts_port *s = container_of(port, ++ struct max3100ts_port, + port); + +- dev_dbg(&s->spi->dev, "%s\n", __func__); ++ dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + + if (flags & UART_CONFIG_TYPE) + s->port.type = PORT_MAX3100; +@@ -688,12 +778,9 @@ + static int max3100_verify_port(struct uart_port *port, + struct serial_struct *ser) + { +- struct max3100_port *s = container_of(port, +- struct max3100_port, +- port); + int ret = -EINVAL; + +- dev_dbg(&s->spi->dev, "%s\n", __func__); ++ dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + + if (ser->type == PORT_UNKNOWN || ser->type == PORT_MAX3100) + ret = 0; +@@ -702,33 +789,21 @@ + + static void max3100_stop_tx(struct uart_port *port) + { +- struct max3100_port *s = container_of(port, +- struct max3100_port, +- port); +- +- dev_dbg(&s->spi->dev, "%s\n", __func__); ++ dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + } + + static int max3100_request_port(struct uart_port *port) + { +- struct max3100_port *s = container_of(port, +- struct max3100_port, +- port); +- +- dev_dbg(&s->spi->dev, "%s\n", __func__); ++ dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + return 0; + } + + static void max3100_break_ctl(struct uart_port *port, int break_state) + { +- struct max3100_port *s = container_of(port, +- struct max3100_port, +- port); +- +- dev_dbg(&s->spi->dev, "%s\n", __func__); ++ dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + } + +-static const struct uart_ops max3100_ops = { ++static struct uart_ops max3100_ops = { + .tx_empty = max3100_tx_empty, + .set_mctrl = max3100_set_mctrl, + .get_mctrl = max3100_get_mctrl, +@@ -755,124 +830,215 @@ + .minor = MAX3100_MINOR, + .nr = MAX_MAX3100, + }; ++ + static int uart_driver_registered; + ++#ifdef CONFIG_OF ++static const struct of_device_id max3100_dt_ids[] = { ++ {.compatible = "technologic,max3100-ts"}, ++ {} ++}; ++ ++MODULE_DEVICE_TABLE(of, max3100_dt_ids); ++ ++static const struct plat_max3100 *max3100_probe_dt(struct device *dev) ++{ ++ struct plat_max3100 *pdata; ++ struct device_node *node = dev->of_node; ++ const struct of_device_id *match; ++ ++ if (!node) { ++ dev_err(dev, "Device does not have associated DT data\n"); ++ return ERR_PTR(-EINVAL); ++ } ++ ++ match = of_match_device(max3100_dt_ids, dev); ++ if (!match) { ++ dev_err(dev, "Unknown device model\n"); ++ return ERR_PTR(-EINVAL); ++ } ++ ++ pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); ++ if (!pdata) ++ return ERR_PTR(-ENOMEM); ++ ++ // Force MAX310 into loopback ++ of_property_read_u32(node, "loopback", &pdata->loopback); ++ // Crystal <1 = 3.6864MHz> <0 = 1.8432MHz> ++ of_property_read_u32(node, "crystal", &pdata->crystal); ++ // Poll time in ms, 0 disables CTS, 100 typical ++ of_property_read_u32(node, "poll-time", &pdata->poll_time); ++ // Size of the Tx FIFO, in bytes ++ of_property_read_u32(node, "tx-fifo-size", &pdata->tx_fifo_size); ++ // Size of the Rx FIFO, in bytes ++ of_property_read_u32(node, "rx-fifo-size", &pdata->rx_fifo_size); ++ return pdata; ++} ++ ++#else ++ ++static const struct plat_max3100 *max3100_probe_dt(struct device *dev) ++{ ++ dev_err(dev, "no platform data defined\n"); ++ return ERR_PTR(-EINVAL); ++} ++ ++#endif ++ + static int max3100_probe(struct spi_device *spi) + { + int i, retval; +- struct plat_max3100 *pdata; ++ const struct plat_max3100 *pdata; + u16 tx, rx; + +- mutex_lock(&max3100s_lock); ++ mutex_init(&max3100ts_common.max3100ts_lock); ++ mutex_init(&max3100ts_common.portlock); ++ ++ mutex_lock(&max3100ts_common.max3100ts_lock); + + if (!uart_driver_registered) { ++ uart_driver_registered = 1; + retval = uart_register_driver(&max3100_uart_driver); + if (retval) { +- printk(KERN_ERR "Couldn't register max3100 uart driver\n"); +- mutex_unlock(&max3100s_lock); ++ printk(KERN_ERR ++ "Couldn't register max3100 uart driver\n"); ++ mutex_unlock(&max3100ts_common.max3100ts_lock); + return retval; + } +- +- uart_driver_registered = 1; + } + +- for (i = 0; i < MAX_MAX3100; i++) +- if (!max3100s[i]) +- break; +- if (i == MAX_MAX3100) { +- dev_warn(&spi->dev, "too many MAX3100 chips\n"); +- mutex_unlock(&max3100s_lock); +- return -ENOMEM; ++ pdata = max3100_probe_dt(&spi->dev); ++ if (IS_ERR(pdata)) { ++ mutex_unlock(&max3100ts_common.max3100ts_lock); ++ return PTR_ERR(pdata); + } + +- max3100s[i] = kzalloc(sizeof(struct max3100_port), GFP_KERNEL); +- if (!max3100s[i]) { ++ max3100ts_common.spi = spi; ++ max3100ts_common.irq = spi->irq; ++ max3100ts_common.uart_idx = -1; ++ max3100ts_common.uart_count = 0; ++ ++ for (i = 0; i < MAX_MAX3100; i++) { ++ max3100ts_common.max3100ts[i] = ++ kzalloc(sizeof(struct max3100ts_port), GFP_KERNEL); ++ if (!max3100ts_common.max3100ts[i]) { + dev_warn(&spi->dev, +- "kmalloc for max3100 structure %d failed!\n", i); +- mutex_unlock(&max3100s_lock); ++ "kmalloc for max3100 structure %d failed!\n", ++ i); ++ mutex_unlock(&max3100ts_common.max3100ts_lock); + return -ENOMEM; + } +- max3100s[i]->spi = spi; +- max3100s[i]->irq = spi->irq; +- spin_lock_init(&max3100s[i]->conf_lock); +- spi_set_drvdata(spi, max3100s[i]); +- pdata = dev_get_platdata(&spi->dev); +- max3100s[i]->crystal = pdata->crystal; +- max3100s[i]->loopback = pdata->loopback; +- max3100s[i]->poll_time = msecs_to_jiffies(pdata->poll_time); +- if (pdata->poll_time > 0 && max3100s[i]->poll_time == 0) +- max3100s[i]->poll_time = 1; +- max3100s[i]->max3100_hw_suspend = pdata->max3100_hw_suspend; +- max3100s[i]->minor = i; +- timer_setup(&max3100s[i]->timer, max3100_timeout, 0); ++ ++ spi_set_drvdata(spi, max3100ts_common.max3100ts[i]); ++ ++ max3100ts_common.max3100ts[i]->minor = i; ++ ++ tx = MAX3100_WC | MAX3100_SHDN | 5; ++ mutex_lock(&max3100ts_common.portlock); ++ max3100_sr(max3100ts_common.max3100ts[i], tx, &rx); ++ tx = MAX3100_RC; ++ rx = 0; ++ max3100_sr(max3100ts_common.max3100ts[i], tx, &rx); ++ mutex_unlock(&max3100ts_common.portlock); ++ if ((rx & MAX3100_BAUD) != 5) { ++ kfree(max3100ts_common.max3100ts[i]); ++ max3100ts_common.max3100ts[i] = NULL; ++ break; ++ } else ++ max3100ts_common.uart_count++; ++ ++ max3100ts_common.max3100ts[i]->crystal = pdata->crystal; ++ max3100ts_common.max3100ts[i]->loopback = pdata->loopback; ++ max3100ts_common.max3100ts[i]->poll_time = ++ pdata->poll_time * HZ / 1000; ++ if (pdata->poll_time > 0 ++ && max3100ts_common.max3100ts[i]->poll_time == 0) ++ max3100ts_common.max3100ts[i]->poll_time = 1; ++ max3100ts_common.max3100ts[i]->max3100_hw_suspend = ++ pdata->max3100_hw_suspend; ++ timer_setup(&max3100ts_common.max3100ts[i]->timer, ++ max3100_timeout, 0); + + dev_dbg(&spi->dev, "%s: adding port %d\n", __func__, i); +- max3100s[i]->port.irq = max3100s[i]->irq; +- max3100s[i]->port.uartclk = max3100s[i]->crystal ? 3686400 : 1843200; +- max3100s[i]->port.fifosize = 16; +- max3100s[i]->port.ops = &max3100_ops; +- max3100s[i]->port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF; +- max3100s[i]->port.line = i; +- max3100s[i]->port.type = PORT_MAX3100; +- max3100s[i]->port.dev = &spi->dev; +- retval = uart_add_one_port(&max3100_uart_driver, &max3100s[i]->port); ++ max3100ts_common.max3100ts[i]->port.irq = max3100ts_common.irq; ++ max3100ts_common.max3100ts[i]->port.uartclk = ++ max3100ts_common.max3100ts[i]->crystal ? 3686400 : 1843200; ++ max3100ts_common.max3100ts[i]->port.fifosize = 16; ++ max3100ts_common.max3100ts[i]->port.ops = &max3100_ops; ++ max3100ts_common.max3100ts[i]->port.flags = ++ UPF_SKIP_TEST | UPF_BOOT_AUTOCONF; ++ max3100ts_common.max3100ts[i]->port.line = i; ++ max3100ts_common.max3100ts[i]->port.type = PORT_MAX3100; ++ max3100ts_common.max3100ts[i]->port.dev = &spi->dev; ++ ++ retval = ++ uart_add_one_port(&max3100_uart_driver, ++ &max3100ts_common.max3100ts[i]->port); + if (retval < 0) + dev_warn(&spi->dev, + "uart_add_one_port failed for line %d with error %d\n", + i, retval); +- +- /* set shutdown mode to save power. Will be woken-up on open */ +- if (max3100s[i]->max3100_hw_suspend) +- max3100s[i]->max3100_hw_suspend(1); +- else { + tx = MAX3100_WC | MAX3100_SHDN; +- max3100_sr(max3100s[i], tx, &rx); ++ mutex_lock(&max3100ts_common.portlock); ++ max3100_sr(max3100ts_common.max3100ts[i], tx, &rx); ++ mutex_unlock(&max3100ts_common.portlock); ++ } ++ ++ mutex_unlock(&max3100ts_common.max3100ts_lock); ++ ++ retval = devm_request_threaded_irq(&spi->dev, spi->irq, NULL, max3100_thread_irq, ++ IRQF_TRIGGER_LOW | IRQF_ONESHOT, "max3100-ts", ++ &max3100ts_common); ++ ++ if (retval) { ++ dev_warn(&spi->dev, "cannot allocate irq %d\n", spi->irq); ++ return retval; + } +- mutex_unlock(&max3100s_lock); ++ ++ dev_info(&spi->dev, "Detected %d uarts\n", max3100ts_common.uart_count); + return 0; + } + + static void max3100_remove(struct spi_device *spi) + { +- struct max3100_port *s = spi_get_drvdata(spi); + int i; + +- mutex_lock(&max3100s_lock); ++ mutex_lock(&max3100ts_common.max3100ts_lock); + + /* find out the index for the chip we are removing */ +- for (i = 0; i < MAX_MAX3100; i++) +- if (max3100s[i] == s) { +- dev_dbg(&spi->dev, "%s: removing port %d\n", __func__, i); +- uart_remove_one_port(&max3100_uart_driver, &max3100s[i]->port); +- kfree(max3100s[i]); +- max3100s[i] = NULL; +- break; +- } ++ for (i = MAX_MAX3100 - 1; i >= 0; i--) ++ if (max3100ts_common.max3100ts[i]) { + +- WARN_ON(i == MAX_MAX3100); ++ dev_dbg(&spi->dev, "%s: removing port %d\n", __func__, ++ i); ++ uart_remove_one_port(&max3100_uart_driver, ++ &max3100ts_common.max3100ts[i]-> ++ port); + +- /* check if this is the last chip we have */ +- for (i = 0; i < MAX_MAX3100; i++) +- if (max3100s[i]) { +- mutex_unlock(&max3100s_lock); +- return; ++ kfree(max3100ts_common.max3100ts[i]); ++ max3100ts_common.max3100ts[i] = NULL; ++ } ++ ++ if (max3100ts_common.irq) { ++ free_irq(max3100ts_common.irq, &max3100ts_common); ++ max3100ts_common.irq = 0; + } ++ + pr_debug("removing max3100 driver\n"); + uart_unregister_driver(&max3100_uart_driver); +- uart_driver_registered = 0; + +- mutex_unlock(&max3100s_lock); ++ mutex_unlock(&max3100ts_common.max3100ts_lock); + } + + #ifdef CONFIG_PM_SLEEP + + static int max3100_suspend(struct device *dev) + { +- struct max3100_port *s = dev_get_drvdata(dev); ++ struct max3100ts_port *s = dev_get_drvdata(dev); + +- dev_dbg(&s->spi->dev, "%s\n", __func__); ++ dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + +- disable_irq(s->irq); ++ disable_irq(max3100ts_common.irq); + + s->suspending = 1; + uart_suspend_port(&max3100_uart_driver, &s->port); +@@ -882,29 +1048,30 @@ + else { + /* no HW suspend, so do SW one */ + u16 tx, rx; +- + tx = MAX3100_WC | MAX3100_SHDN; ++ mutex_lock(&max3100ts_common.portlock); + max3100_sr(s, tx, &rx); ++ mutex_unlock(&max3100ts_common.portlock); + } + return 0; + } + + static int max3100_resume(struct device *dev) + { +- struct max3100_port *s = dev_get_drvdata(dev); ++ struct max3100ts_port *s = dev_get_drvdata(dev); + +- dev_dbg(&s->spi->dev, "%s\n", __func__); ++ dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + + if (s->max3100_hw_suspend) + s->max3100_hw_suspend(0); + uart_resume_port(&max3100_uart_driver, &s->port); + s->suspending = 0; + +- enable_irq(s->irq); ++ enable_irq(max3100ts_common.irq); + + s->conf_commit = 1; + if (s->workqueue) +- max3100_dowork(s); ++ max3100_schedule_work(s); + + return 0; + } +@@ -918,7 +1085,8 @@ + + static struct spi_driver max3100_driver = { + .driver = { +- .name = "max3100", ++ .name = "max3100-ts", ++ .owner = THIS_MODULE, + .pm = MAX3100_PM_OPS, + }, + .probe = max3100_probe, diff --git a/max3100.diff b/max3100.diff new file mode 100644 index 0000000000000..854bb6b7eeddb --- /dev/null +++ b/max3100.diff @@ -0,0 +1,1076 @@ +--- drivers/tty/serial/max3100-ts.c 2025-08-15 19:06:13.131568176 +0000 ++++ drivers/tty/serial/max3100-ts.c 2025-08-15 19:06:13.131568176 +0000 +@@ -30,10 +30,23 @@ + * mknod /dev/ttyMAX0 c 204 209 + */ + ++ /* ++ Modified from the original max3100.c to support the embeddedTS ++ MAX3100 extended UARTs. This device puts 3 MAX3100-like uarts in one ++ chip, but with only a single CS# line going to the chip, and a single ++ IRQ pin. This requires that all SPI transactions are preceded by a byte ++ to indicate which of the 3 uarts is being accessed. On an interrupt, ++ there's no way to tell which of the uarts generated it, so we have to ++ check 'em all. ++ */ ++ + #define MAX3100_MAJOR 204 + #define MAX3100_MINOR 209 +-/* 4 MAX3100s should be enough for everyone */ +-#define MAX_MAX3100 4 ++ /* ++ One max3100ts may contain up to 64 uarts. ++ This driver supports only one max3100ts ++ */ ++#define MAX_MAX3100 64 + + #include + #include +@@ -45,9 +58,9 @@ + #include + #include + #include +-#include +- +-#include ++#include ++#include ++#include + + #include + +@@ -92,14 +105,15 @@ + #define MAX3100_STATUS_FE 2 + #define MAX3100_STATUS_OE 4 + +-struct max3100_port { ++#define MAX3100_CSI 0xc0 ++ ++struct max3100ts_port { + struct uart_port port; +- struct spi_device *spi; ++ //struct spi_device *spi; + + int cts; /* last CTS received for flow ctrl */ + int tx_empty; /* last TX empty bit */ + +- spinlock_t conf_lock; /* shared data */ + int conf_commit; /* need to make changes */ + int conf; /* configuration for the MAX31000 + * (bits 0-7, bits 8-11 are irqs) */ +@@ -113,7 +127,7 @@ + #define MAX3100_7BIT 4 + int rx_enabled; /* if we should rx chars */ + +- int irq; /* irq assigned to the max3100 */ ++ //int irq; /* irq assigned to the max3100 */ + + int minor; /* minor number */ + int crystal; /* 1 if 3.6864Mhz crystal 0 for 1.8432 */ +@@ -134,12 +148,23 @@ + int poll_time; + /* and its timer */ + struct timer_list timer; ++ ++ int tx_fifo_size; ++ int rx_fifo_size; ++ + }; + +-static struct max3100_port *max3100s[MAX_MAX3100]; /* the chips */ +-static DEFINE_MUTEX(max3100s_lock); /* race on probe */ ++static struct s_max3100ts_common { ++ struct max3100ts_port *max3100ts[MAX_MAX3100]; /* the chip */ ++ struct mutex portlock; /* race on port usage */ ++ struct mutex max3100ts_lock; /* race on probe */ ++ struct spi_device *spi; /* all our uarts are on one spi */ ++ int irq; /* single irq assigned to the max3100-ts */ ++ int uart_idx; /* index into max3100ts[ ] */ ++ int uart_count; /* number of uarts detected */ ++} max3100ts_common; + +-static int max3100_do_parity(struct max3100_port *s, u16 c) ++static int max3100_do_parity(struct max3100ts_port *s, u16 c) + { + int parity; + +@@ -157,12 +182,12 @@ + return parity; + } + +-static int max3100_check_parity(struct max3100_port *s, u16 c) ++static int max3100_check_parity(struct max3100ts_port *s, u16 c) + { + return max3100_do_parity(s, c) == ((c >> 8) & 1); + } + +-static void max3100_calc_parity(struct max3100_port *s, u16 *c) ++static void max3100_calc_parity(struct max3100ts_port *s, u16 * c) + { + if (s->parity & MAX3100_7BIT) + *c &= 0x7f; +@@ -173,58 +198,87 @@ + *c |= max3100_do_parity(s, *c) << 8; + } + +-static void max3100_work(struct work_struct *w); ++static void max3100_port_work(struct work_struct *w); + +-static void max3100_dowork(struct max3100_port *s) ++static void max3100_schedule_work(struct max3100ts_port *s) + { +- if (!s->force_end_work && !freezing(current) && !s->suspending) ++ if(!work_pending(&s->work)){ + queue_work(s->workqueue, &s->work); ++ } + } + + static void max3100_timeout(struct timer_list *t) + { +- struct max3100_port *s = from_timer(s, t, timer); +- ++ struct max3100ts_port *s = from_timer(s, t, timer); + if (s->port.state) { +- max3100_dowork(s); ++ max3100_schedule_work(s); + mod_timer(&s->timer, jiffies + s->poll_time); + } + } + +-static int max3100_sr(struct max3100_port *s, u16 tx, u16 *rx) ++static int max3100_sr(struct max3100ts_port *s, u16 tx, u16 * rx) + { + struct spi_message message; +- __be16 etx, erx; ++ u16 etx, erx; + int status; + struct spi_transfer tran = { + .tx_buf = &etx, + .rx_buf = &erx, + .len = 2, + }; ++ struct spi_transfer idx = { ++ .rx_buf = NULL, ++ .len = 1, ++ }; ++ ++ /* The SPI functions provide a locking mechanism that we could use ++ * here, however, we don't have access to struct spi_controller (that ++ * I am aware of), so we would use the portlock around these functions. ++ * It is critical that if two SPI transfers happen, they have no ++ * interruptions between them. */ ++ if (max3100ts_common.uart_idx != s->minor) { ++ u8 cs = s->minor | MAX3100_CSI; ++ idx.tx_buf = &cs; ++ spi_message_init(&message); ++ spi_message_add_tail(&idx, &message); ++ status = spi_sync(max3100ts_common.spi, &message); ++ if (status) { ++ dev_warn(&max3100ts_common.spi->dev, ++ "error while calling spi_sync\n"); ++ mutex_unlock(&max3100ts_common.portlock); ++ return -EIO; ++ } ++ max3100ts_common.uart_idx = s->minor; ++ } + + etx = cpu_to_be16(tx); ++ + spi_message_init(&message); + spi_message_add_tail(&tran, &message); +- status = spi_sync(s->spi, &message); ++ status = spi_sync(max3100ts_common.spi, &message); + if (status) { +- dev_warn(&s->spi->dev, "error while calling spi_sync\n"); ++ dev_warn(&max3100ts_common.spi->dev, ++ "error while calling spi_sync\n"); + return -EIO; + } + *rx = be16_to_cpu(erx); + s->tx_empty = (*rx & MAX3100_T) > 0; +- dev_dbg(&s->spi->dev, "%04x - %04x\n", tx, *rx); ++ ++ dev_dbg(&max3100ts_common.spi->dev, "%04x - %04x\n", tx, *rx); + return 0; + } + +-static int max3100_handlerx_unlocked(struct max3100_port *s, u16 rx) ++static int max3100_handlerx(struct max3100ts_port *s, u16 rx) + { +- unsigned int status = 0; ++ unsigned int ch, flg, status = 0; + int ret = 0, cts; +- u8 ch, flg; ++ unsigned long flags; + + if (rx & MAX3100_R && s->rx_enabled) { +- dev_dbg(&s->spi->dev, "%s\n", __func__); ++ dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); ++ + ch = rx & (s->parity & MAX3100_7BIT ? 0x7f : 0xff); ++ spin_lock_irqsave(&s->port.lock, flags); + if (rx & MAX3100_RAFE) { + s->port.icount.frame++; + flg = TTY_FRAME; +@@ -244,49 +298,49 @@ + flg = TTY_NORMAL; + } + } ++ spin_unlock_irqrestore(&s->port.lock, flags); ++ + uart_insert_char(&s->port, status, MAX3100_STATUS_OE, ch, flg); + ret = 1; + } + + cts = (rx & MAX3100_CTS) > 0; + if (s->cts != cts) { ++ spin_lock_irqsave(&s->port.lock, flags); + s->cts = cts; +- uart_handle_cts_change(&s->port, cts); ++ uart_handle_cts_change(&s->port, cts ? 1 : 0); ++ spin_unlock_irqrestore(&s->port.lock, flags); + } + + return ret; + } + +-static int max3100_handlerx(struct max3100_port *s, u16 rx) ++static void max3100_port_dowork(struct max3100ts_port *s) + { +- unsigned long flags; +- int ret; +- +- uart_port_lock_irqsave(&s->port, &flags); +- ret = max3100_handlerx_unlocked(s, rx); +- uart_port_unlock_irqrestore(&s->port, flags); +- return ret; +-} +- +-static void max3100_work(struct work_struct *w) +-{ +- struct max3100_port *s = container_of(w, struct max3100_port, work); +- int rxchars; ++ int rxchars, x; + u16 tx, rx; + int conf, cconf, crts; ++ unsigned long flags; + struct circ_buf *xmit = &s->port.state->xmit; + +- dev_dbg(&s->spi->dev, "%s\n", __func__); ++ dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + + rxchars = 0; ++ ++ /* Since the do/while loop has its while conditional at the end which ++ * some of the calls are dependant on holding the lock, each loop must ++ * start with the lock held since we need the lock when the while is ++ * checked. ++ */ ++ spin_lock_irqsave(&s->port.lock, flags); + do { +- spin_lock(&s->conf_lock); + conf = s->conf; + cconf = s->conf_commit; + s->conf_commit = 0; + crts = s->rts_commit; + s->rts_commit = 0; +- spin_unlock(&s->conf_lock); ++ spin_unlock_irqrestore(&s->port.lock, flags); ++ + if (cconf) + max3100_sr(s, MAX3100_WC | conf, &rx); + if (crts) { +@@ -295,152 +349,191 @@ + rxchars += max3100_handlerx(s, rx); + } + +- max3100_sr(s, MAX3100_RD, &rx); +- rxchars += max3100_handlerx(s, rx); +- +- if (rx & MAX3100_T) { +- tx = 0xffff; ++ x = 0; ++ /* Lock in case we need to call uart_circ_empty() */ ++ spin_lock_irqsave(&s->port.lock, flags); + if (s->port.x_char) { + tx = s->port.x_char; +- s->port.icount.tx++; +- s->port.x_char = 0; +- } else if (!uart_circ_empty(xmit) && +- !uart_tx_stopped(&s->port)) { ++ x = 1; ++ } else{ ++ if(!s->force_end_work){ ++ if (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) { + tx = xmit->buf[xmit->tail]; +- uart_xmit_advance(&s->port, 1); ++ x = 2; ++ } + } +- if (tx != 0xffff) { ++ } ++ spin_unlock_irqrestore(&s->port.lock, flags); ++ ++ if (x) { /* we have something to send, so send it! */ + max3100_calc_parity(s, &tx); + tx |= MAX3100_WD | (s->rts ? MAX3100_RTS : 0); + max3100_sr(s, tx, &rx); + rxchars += max3100_handlerx(s, rx); ++ ++ if (rx & MAX3100_T) { /* Tx buffer is/was empty, so tx was sent */ ++ spin_lock_irqsave(&s->port.lock, flags); ++ if (x == 1) { ++ s->port.icount.tx++; ++ s->port.x_char = 0; ++ } else if (x == 2) { ++ xmit->tail = (xmit->tail + 1) & ++ (UART_XMIT_SIZE - 1); ++ s->port.icount.tx++; + } ++ spin_unlock_irqrestore(&s->port.lock, flags); ++ } ++ } else { ++ max3100_sr(s, MAX3100_RD, &rx); ++ rxchars += max3100_handlerx(s, rx); + } + +- if (rxchars > 16) { ++ /* A balance between servicing the UART and getting data to ++ * userspace */ ++ if (rxchars > 31) { + tty_flip_buffer_push(&s->port.state->port); + rxchars = 0; + } +- if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) ++ ++ /* This is a bit funky, but, according to docs, all xmit ++ * head/tail accesses need to be inside of the port->lock. ++ * Grab the lock now, and if we break out of the while ++ * loop, then release the lock. This hopefully should reduce ++ * number of acquisitions for a bit of a performance gain. ++ */ ++ spin_lock_irqsave(&s->port.lock, flags); ++ if (uart_circ_chars_pending(xmit) < 4){ ++ if(s->port.state->port.tty) + uart_write_wakeup(&s->port); ++ } + + } while (!s->force_end_work && + !freezing(current) && + ((rx & MAX3100_R) || +- (!uart_circ_empty(xmit) && +- !uart_tx_stopped(&s->port)))); ++ (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)))); + +- if (rxchars > 0) ++ spin_unlock_irqrestore(&s->port.lock, flags); ++ ++ if (rxchars) + tty_flip_buffer_push(&s->port.state->port); + } + +-static irqreturn_t max3100_irq(int irqno, void *dev_id) ++static void max3100_port_work(struct work_struct *w) + { +- struct max3100_port *s = dev_id; ++ struct max3100ts_port *s = container_of(w, struct max3100ts_port, work); ++ mutex_lock(&max3100ts_common.portlock); ++ max3100_port_dowork(s); ++ mutex_unlock(&max3100ts_common.portlock); ++} + +- dev_dbg(&s->spi->dev, "%s\n", __func__); ++/* Threaded handler called in a sleepable context */ ++static irqreturn_t max3100_thread_irq(int irqno, void *dev_id) ++{ ++ int i; ++ ++ dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); ++ ++ for (i = 0; i < max3100ts_common.uart_count; i++) { ++ struct max3100ts_port *s = max3100ts_common.max3100ts[i]; ++ mutex_lock(&max3100ts_common.portlock); ++ max3100_port_dowork(s); ++ mutex_unlock(&max3100ts_common.portlock); ++ } + +- max3100_dowork(s); + return IRQ_HANDLED; + } + + static void max3100_enable_ms(struct uart_port *port) + { +- struct max3100_port *s = container_of(port, +- struct max3100_port, ++ struct max3100ts_port *s = container_of(port, ++ struct max3100ts_port, + port); + + if (s->poll_time > 0) + mod_timer(&s->timer, jiffies); +- dev_dbg(&s->spi->dev, "%s\n", __func__); ++ dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + } + + static void max3100_start_tx(struct uart_port *port) + { +- struct max3100_port *s = container_of(port, +- struct max3100_port, ++ struct max3100ts_port *s = container_of(port, ++ struct max3100ts_port, + port); + +- dev_dbg(&s->spi->dev, "%s\n", __func__); ++ dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + +- max3100_dowork(s); ++ max3100_schedule_work(s); + } + + static void max3100_stop_rx(struct uart_port *port) + { +- struct max3100_port *s = container_of(port, +- struct max3100_port, ++ struct max3100ts_port *s = container_of(port, ++ struct max3100ts_port, + port); + +- dev_dbg(&s->spi->dev, "%s\n", __func__); ++ dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + ++ /* NOTE: port->lock already taken when this function is called */ + s->rx_enabled = 0; +- spin_lock(&s->conf_lock); + s->conf &= ~MAX3100_RM; + s->conf_commit = 1; +- spin_unlock(&s->conf_lock); +- max3100_dowork(s); + } + + static unsigned int max3100_tx_empty(struct uart_port *port) + { +- struct max3100_port *s = container_of(port, +- struct max3100_port, ++ struct max3100ts_port *s = container_of(port, ++ struct max3100ts_port, + port); + +- dev_dbg(&s->spi->dev, "%s\n", __func__); ++ dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + + /* may not be truly up-to-date */ +- max3100_dowork(s); ++ max3100_schedule_work(s); + return s->tx_empty; + } + + static unsigned int max3100_get_mctrl(struct uart_port *port) + { +- struct max3100_port *s = container_of(port, +- struct max3100_port, ++ struct max3100ts_port *s = container_of(port, ++ struct max3100ts_port, + port); + +- dev_dbg(&s->spi->dev, "%s\n", __func__); ++ dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + +- /* may not be truly up-to-date */ +- max3100_dowork(s); + /* always assert DCD and DSR since these lines are not wired */ + return (s->cts ? TIOCM_CTS : 0) | TIOCM_DSR | TIOCM_CAR; + } + + static void max3100_set_mctrl(struct uart_port *port, unsigned int mctrl) + { +- struct max3100_port *s = container_of(port, +- struct max3100_port, ++ struct max3100ts_port *s = container_of(port, ++ struct max3100ts_port, + port); + int rts; + +- dev_dbg(&s->spi->dev, "%s\n", __func__); ++ dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + + rts = (mctrl & TIOCM_RTS) > 0; + +- spin_lock(&s->conf_lock); + if (s->rts != rts) { + s->rts = rts; + s->rts_commit = 1; +- max3100_dowork(s); + } +- spin_unlock(&s->conf_lock); + } + + static void + max3100_set_termios(struct uart_port *port, struct ktermios *termios, + const struct ktermios *old) + { +- struct max3100_port *s = container_of(port, +- struct max3100_port, ++ struct max3100ts_port *s = container_of(port, ++ struct max3100ts_port, + port); + int baud = 0; + unsigned cflag; ++ unsigned long flags; + u32 param_new, param_mask, parity = 0; + +- dev_dbg(&s->spi->dev, "%s\n", __func__); ++ dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + + cflag = termios->c_cflag; + param_mask = 0; +@@ -531,20 +624,22 @@ + s->port.ignore_status_mask = 0; + if (termios->c_iflag & IGNPAR) + s->port.ignore_status_mask |= +- MAX3100_STATUS_PE | MAX3100_STATUS_FE | +- MAX3100_STATUS_OE; ++ MAX3100_STATUS_PE | MAX3100_STATUS_FE | MAX3100_STATUS_OE; + + if (s->poll_time > 0) + del_timer_sync(&s->timer); + + uart_update_timeout(port, termios->c_cflag, baud); + +- spin_lock(&s->conf_lock); ++ spin_lock_irqsave(&s->port.lock, flags); + s->conf = (s->conf & ~param_mask) | (param_new & param_mask); + s->conf_commit = 1; + s->parity = parity; +- spin_unlock(&s->conf_lock); +- max3100_dowork(s); ++ spin_unlock_irqrestore(&s->port.lock, flags); ++ ++ mutex_lock(&max3100ts_common.portlock); ++ max3100_port_dowork(s); ++ mutex_unlock(&max3100ts_common.portlock); + + if (UART_ENABLE_MS(&s->port, termios->c_cflag)) + max3100_enable_ms(&s->port); +@@ -552,26 +647,28 @@ + + static void max3100_shutdown(struct uart_port *port) + { +- struct max3100_port *s = container_of(port, +- struct max3100_port, ++ struct max3100ts_port *s = container_of(port, ++ struct max3100ts_port, + port); + +- dev_dbg(&s->spi->dev, "%s\n", __func__); ++ dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + + if (s->suspending) + return; + ++ /* Make sure any dowork from the irq thread are finished */ + s->force_end_work = 1; ++ mutex_lock(&max3100ts_common.portlock); ++ mutex_unlock(&max3100ts_common.portlock); + + if (s->poll_time > 0) + del_timer_sync(&s->timer); + + if (s->workqueue) { ++ flush_workqueue(s->workqueue); + destroy_workqueue(s->workqueue); + s->workqueue = NULL; + } +- if (s->irq) +- free_irq(s->irq, s); + + /* set shutdown mode to save power */ + if (s->max3100_hw_suspend) +@@ -580,20 +677,22 @@ + u16 tx, rx; + + tx = MAX3100_WC | MAX3100_SHDN; ++ mutex_lock(&max3100ts_common.portlock); + max3100_sr(s, tx, &rx); ++ mutex_unlock(&max3100ts_common.portlock); + } + } + + static int max3100_startup(struct uart_port *port) + { +- struct max3100_port *s = container_of(port, +- struct max3100_port, ++ struct max3100ts_port *s = container_of(port, ++ struct max3100ts_port, + port); + char b[12]; + +- dev_dbg(&s->spi->dev, "%s\n", __func__); ++ dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + +- s->conf = MAX3100_RM; ++ s->conf = MAX3100_RM | MAX3100_TM; + s->baud = s->crystal ? 230400 : 115200; + s->rx_enabled = 1; + +@@ -605,33 +704,28 @@ + s->rts = 0; + + sprintf(b, "max3100-%d", s->minor); +- s->workqueue = create_freezable_workqueue(b); ++ s->workqueue = create_singlethread_workqueue(b); + if (!s->workqueue) { +- dev_warn(&s->spi->dev, "cannot create workqueue\n"); +- return -EBUSY; +- } +- INIT_WORK(&s->work, max3100_work); +- +- if (request_irq(s->irq, max3100_irq, +- IRQF_TRIGGER_FALLING, "max3100", s) < 0) { +- dev_warn(&s->spi->dev, "cannot allocate irq %d\n", s->irq); +- s->irq = 0; +- destroy_workqueue(s->workqueue); +- s->workqueue = NULL; ++ dev_warn(&max3100ts_common.spi->dev, ++ "cannot create workqueue\n"); + return -EBUSY; + } ++ INIT_WORK(&s->work, max3100_port_work); + + if (s->loopback) { + u16 tx, rx; + tx = 0x4001; ++ mutex_lock(&max3100ts_common.portlock); + max3100_sr(s, tx, &rx); ++ mutex_unlock(&max3100ts_common.portlock); + } + + if (s->max3100_hw_suspend) + s->max3100_hw_suspend(0); + s->conf_commit = 1; +- max3100_dowork(s); ++ + /* wait for clock to settle */ ++ if (s->port.line == 0) + msleep(50); + + max3100_enable_ms(&s->port); +@@ -641,31 +735,27 @@ + + static const char *max3100_type(struct uart_port *port) + { +- struct max3100_port *s = container_of(port, +- struct max3100_port, ++ struct max3100ts_port *s = container_of(port, ++ struct max3100ts_port, + port); + +- dev_dbg(&s->spi->dev, "%s\n", __func__); ++ dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + + return s->port.type == PORT_MAX3100 ? "MAX3100" : NULL; + } + + static void max3100_release_port(struct uart_port *port) + { +- struct max3100_port *s = container_of(port, +- struct max3100_port, +- port); +- +- dev_dbg(&s->spi->dev, "%s\n", __func__); ++ dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + } + + static void max3100_config_port(struct uart_port *port, int flags) + { +- struct max3100_port *s = container_of(port, +- struct max3100_port, ++ struct max3100ts_port *s = container_of(port, ++ struct max3100ts_port, + port); + +- dev_dbg(&s->spi->dev, "%s\n", __func__); ++ dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + + if (flags & UART_CONFIG_TYPE) + s->port.type = PORT_MAX3100; +@@ -674,12 +764,9 @@ + static int max3100_verify_port(struct uart_port *port, + struct serial_struct *ser) + { +- struct max3100_port *s = container_of(port, +- struct max3100_port, +- port); + int ret = -EINVAL; + +- dev_dbg(&s->spi->dev, "%s\n", __func__); ++ dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + + if (ser->type == PORT_UNKNOWN || ser->type == PORT_MAX3100) + ret = 0; +@@ -688,33 +775,21 @@ + + static void max3100_stop_tx(struct uart_port *port) + { +- struct max3100_port *s = container_of(port, +- struct max3100_port, +- port); +- +- dev_dbg(&s->spi->dev, "%s\n", __func__); ++ dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + } + + static int max3100_request_port(struct uart_port *port) + { +- struct max3100_port *s = container_of(port, +- struct max3100_port, +- port); +- +- dev_dbg(&s->spi->dev, "%s\n", __func__); ++ dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + return 0; + } + + static void max3100_break_ctl(struct uart_port *port, int break_state) + { +- struct max3100_port *s = container_of(port, +- struct max3100_port, +- port); +- +- dev_dbg(&s->spi->dev, "%s\n", __func__); ++ dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + } + +-static const struct uart_ops max3100_ops = { ++static struct uart_ops max3100_ops = { + .tx_empty = max3100_tx_empty, + .set_mctrl = max3100_set_mctrl, + .get_mctrl = max3100_get_mctrl, +@@ -741,124 +816,215 @@ + .minor = MAX3100_MINOR, + .nr = MAX_MAX3100, + }; ++ + static int uart_driver_registered; + ++#ifdef CONFIG_OF ++static const struct of_device_id max3100_dt_ids[] = { ++ {.compatible = "technologic,max3100-ts"}, ++ {} ++}; ++ ++MODULE_DEVICE_TABLE(of, max3100_dt_ids); ++ ++static const struct plat_max3100 *max3100_probe_dt(struct device *dev) ++{ ++ struct plat_max3100 *pdata; ++ struct device_node *node = dev->of_node; ++ const struct of_device_id *match; ++ ++ if (!node) { ++ dev_err(dev, "Device does not have associated DT data\n"); ++ return ERR_PTR(-EINVAL); ++ } ++ ++ match = of_match_device(max3100_dt_ids, dev); ++ if (!match) { ++ dev_err(dev, "Unknown device model\n"); ++ return ERR_PTR(-EINVAL); ++ } ++ ++ pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); ++ if (!pdata) ++ return ERR_PTR(-ENOMEM); ++ ++ // Force MAX310 into loopback ++ of_property_read_u32(node, "loopback", &pdata->loopback); ++ // Crystal <1 = 3.6864MHz> <0 = 1.8432MHz> ++ of_property_read_u32(node, "crystal", &pdata->crystal); ++ // Poll time in ms, 0 disables CTS, 100 typical ++ of_property_read_u32(node, "poll-time", &pdata->poll_time); ++ // Size of the Tx FIFO, in bytes ++ of_property_read_u32(node, "tx-fifo-size", &pdata->tx_fifo_size); ++ // Size of the Rx FIFO, in bytes ++ of_property_read_u32(node, "rx-fifo-size", &pdata->rx_fifo_size); ++ return pdata; ++} ++ ++#else ++ ++static const struct plat_max3100 *max3100_probe_dt(struct device *dev) ++{ ++ dev_err(dev, "no platform data defined\n"); ++ return ERR_PTR(-EINVAL); ++} ++ ++#endif ++ + static int max3100_probe(struct spi_device *spi) + { + int i, retval; +- struct plat_max3100 *pdata; ++ const struct plat_max3100 *pdata; + u16 tx, rx; + +- mutex_lock(&max3100s_lock); ++ mutex_init(&max3100ts_common.max3100ts_lock); ++ mutex_init(&max3100ts_common.portlock); ++ ++ mutex_lock(&max3100ts_common.max3100ts_lock); + + if (!uart_driver_registered) { ++ uart_driver_registered = 1; + retval = uart_register_driver(&max3100_uart_driver); + if (retval) { +- printk(KERN_ERR "Couldn't register max3100 uart driver\n"); +- mutex_unlock(&max3100s_lock); ++ printk(KERN_ERR ++ "Couldn't register max3100 uart driver\n"); ++ mutex_unlock(&max3100ts_common.max3100ts_lock); + return retval; + } +- +- uart_driver_registered = 1; + } + +- for (i = 0; i < MAX_MAX3100; i++) +- if (!max3100s[i]) +- break; +- if (i == MAX_MAX3100) { +- dev_warn(&spi->dev, "too many MAX3100 chips\n"); +- mutex_unlock(&max3100s_lock); +- return -ENOMEM; ++ pdata = max3100_probe_dt(&spi->dev); ++ if (IS_ERR(pdata)) { ++ mutex_unlock(&max3100ts_common.max3100ts_lock); ++ return PTR_ERR(pdata); + } + +- max3100s[i] = kzalloc(sizeof(struct max3100_port), GFP_KERNEL); +- if (!max3100s[i]) { ++ max3100ts_common.spi = spi; ++ max3100ts_common.irq = spi->irq; ++ max3100ts_common.uart_idx = -1; ++ max3100ts_common.uart_count = 0; ++ ++ for (i = 0; i < MAX_MAX3100; i++) { ++ max3100ts_common.max3100ts[i] = ++ kzalloc(sizeof(struct max3100ts_port), GFP_KERNEL); ++ if (!max3100ts_common.max3100ts[i]) { + dev_warn(&spi->dev, +- "kmalloc for max3100 structure %d failed!\n", i); +- mutex_unlock(&max3100s_lock); ++ "kmalloc for max3100 structure %d failed!\n", ++ i); ++ mutex_unlock(&max3100ts_common.max3100ts_lock); + return -ENOMEM; + } +- max3100s[i]->spi = spi; +- max3100s[i]->irq = spi->irq; +- spin_lock_init(&max3100s[i]->conf_lock); +- spi_set_drvdata(spi, max3100s[i]); +- pdata = dev_get_platdata(&spi->dev); +- max3100s[i]->crystal = pdata->crystal; +- max3100s[i]->loopback = pdata->loopback; +- max3100s[i]->poll_time = msecs_to_jiffies(pdata->poll_time); +- if (pdata->poll_time > 0 && max3100s[i]->poll_time == 0) +- max3100s[i]->poll_time = 1; +- max3100s[i]->max3100_hw_suspend = pdata->max3100_hw_suspend; +- max3100s[i]->minor = i; +- timer_setup(&max3100s[i]->timer, max3100_timeout, 0); ++ ++ spi_set_drvdata(spi, max3100ts_common.max3100ts[i]); ++ ++ max3100ts_common.max3100ts[i]->minor = i; ++ ++ tx = MAX3100_WC | MAX3100_SHDN | 5; ++ mutex_lock(&max3100ts_common.portlock); ++ max3100_sr(max3100ts_common.max3100ts[i], tx, &rx); ++ tx = MAX3100_RC; ++ rx = 0; ++ max3100_sr(max3100ts_common.max3100ts[i], tx, &rx); ++ mutex_unlock(&max3100ts_common.portlock); ++ if ((rx & MAX3100_BAUD) != 5) { ++ kfree(max3100ts_common.max3100ts[i]); ++ max3100ts_common.max3100ts[i] = NULL; ++ break; ++ } else ++ max3100ts_common.uart_count++; ++ ++ max3100ts_common.max3100ts[i]->crystal = pdata->crystal; ++ max3100ts_common.max3100ts[i]->loopback = pdata->loopback; ++ max3100ts_common.max3100ts[i]->poll_time = ++ pdata->poll_time * HZ / 1000; ++ if (pdata->poll_time > 0 ++ && max3100ts_common.max3100ts[i]->poll_time == 0) ++ max3100ts_common.max3100ts[i]->poll_time = 1; ++ max3100ts_common.max3100ts[i]->max3100_hw_suspend = ++ pdata->max3100_hw_suspend; ++ timer_setup(&max3100ts_common.max3100ts[i]->timer, ++ max3100_timeout, 0); + + dev_dbg(&spi->dev, "%s: adding port %d\n", __func__, i); +- max3100s[i]->port.irq = max3100s[i]->irq; +- max3100s[i]->port.uartclk = max3100s[i]->crystal ? 3686400 : 1843200; +- max3100s[i]->port.fifosize = 16; +- max3100s[i]->port.ops = &max3100_ops; +- max3100s[i]->port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF; +- max3100s[i]->port.line = i; +- max3100s[i]->port.type = PORT_MAX3100; +- max3100s[i]->port.dev = &spi->dev; +- retval = uart_add_one_port(&max3100_uart_driver, &max3100s[i]->port); ++ max3100ts_common.max3100ts[i]->port.irq = max3100ts_common.irq; ++ max3100ts_common.max3100ts[i]->port.uartclk = ++ max3100ts_common.max3100ts[i]->crystal ? 3686400 : 1843200; ++ max3100ts_common.max3100ts[i]->port.fifosize = 16; ++ max3100ts_common.max3100ts[i]->port.ops = &max3100_ops; ++ max3100ts_common.max3100ts[i]->port.flags = ++ UPF_SKIP_TEST | UPF_BOOT_AUTOCONF; ++ max3100ts_common.max3100ts[i]->port.line = i; ++ max3100ts_common.max3100ts[i]->port.type = PORT_MAX3100; ++ max3100ts_common.max3100ts[i]->port.dev = &spi->dev; ++ ++ retval = ++ uart_add_one_port(&max3100_uart_driver, ++ &max3100ts_common.max3100ts[i]->port); + if (retval < 0) + dev_warn(&spi->dev, + "uart_add_one_port failed for line %d with error %d\n", + i, retval); +- +- /* set shutdown mode to save power. Will be woken-up on open */ +- if (max3100s[i]->max3100_hw_suspend) +- max3100s[i]->max3100_hw_suspend(1); +- else { + tx = MAX3100_WC | MAX3100_SHDN; +- max3100_sr(max3100s[i], tx, &rx); ++ mutex_lock(&max3100ts_common.portlock); ++ max3100_sr(max3100ts_common.max3100ts[i], tx, &rx); ++ mutex_unlock(&max3100ts_common.portlock); ++ } ++ ++ mutex_unlock(&max3100ts_common.max3100ts_lock); ++ ++ retval = devm_request_threaded_irq(&spi->dev, spi->irq, NULL, max3100_thread_irq, ++ IRQF_TRIGGER_LOW | IRQF_ONESHOT, "max3100-ts", ++ &max3100ts_common); ++ ++ if (retval) { ++ dev_warn(&spi->dev, "cannot allocate irq %d\n", spi->irq); ++ return retval; + } +- mutex_unlock(&max3100s_lock); ++ ++ dev_info(&spi->dev, "Detected %d uarts\n", max3100ts_common.uart_count); + return 0; + } + + static void max3100_remove(struct spi_device *spi) + { +- struct max3100_port *s = spi_get_drvdata(spi); + int i; + +- mutex_lock(&max3100s_lock); ++ mutex_lock(&max3100ts_common.max3100ts_lock); + + /* find out the index for the chip we are removing */ +- for (i = 0; i < MAX_MAX3100; i++) +- if (max3100s[i] == s) { +- dev_dbg(&spi->dev, "%s: removing port %d\n", __func__, i); +- uart_remove_one_port(&max3100_uart_driver, &max3100s[i]->port); +- kfree(max3100s[i]); +- max3100s[i] = NULL; +- break; +- } ++ for (i = MAX_MAX3100 - 1; i >= 0; i--) ++ if (max3100ts_common.max3100ts[i]) { + +- WARN_ON(i == MAX_MAX3100); ++ dev_dbg(&spi->dev, "%s: removing port %d\n", __func__, ++ i); ++ uart_remove_one_port(&max3100_uart_driver, ++ &max3100ts_common.max3100ts[i]-> ++ port); + +- /* check if this is the last chip we have */ +- for (i = 0; i < MAX_MAX3100; i++) +- if (max3100s[i]) { +- mutex_unlock(&max3100s_lock); +- return; ++ kfree(max3100ts_common.max3100ts[i]); ++ max3100ts_common.max3100ts[i] = NULL; ++ } ++ ++ if (max3100ts_common.irq) { ++ free_irq(max3100ts_common.irq, &max3100ts_common); ++ max3100ts_common.irq = 0; + } ++ + pr_debug("removing max3100 driver\n"); + uart_unregister_driver(&max3100_uart_driver); +- uart_driver_registered = 0; + +- mutex_unlock(&max3100s_lock); ++ mutex_unlock(&max3100ts_common.max3100ts_lock); + } + + #ifdef CONFIG_PM_SLEEP + + static int max3100_suspend(struct device *dev) + { +- struct max3100_port *s = dev_get_drvdata(dev); ++ struct max3100ts_port *s = dev_get_drvdata(dev); + +- dev_dbg(&s->spi->dev, "%s\n", __func__); ++ dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + +- disable_irq(s->irq); ++ disable_irq(max3100ts_common.irq); + + s->suspending = 1; + uart_suspend_port(&max3100_uart_driver, &s->port); +@@ -868,29 +1034,30 @@ + else { + /* no HW suspend, so do SW one */ + u16 tx, rx; +- + tx = MAX3100_WC | MAX3100_SHDN; ++ mutex_lock(&max3100ts_common.portlock); + max3100_sr(s, tx, &rx); ++ mutex_unlock(&max3100ts_common.portlock); + } + return 0; + } + + static int max3100_resume(struct device *dev) + { +- struct max3100_port *s = dev_get_drvdata(dev); ++ struct max3100ts_port *s = dev_get_drvdata(dev); + +- dev_dbg(&s->spi->dev, "%s\n", __func__); ++ dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + + if (s->max3100_hw_suspend) + s->max3100_hw_suspend(0); + uart_resume_port(&max3100_uart_driver, &s->port); + s->suspending = 0; + +- enable_irq(s->irq); ++ enable_irq(max3100ts_common.irq); + + s->conf_commit = 1; + if (s->workqueue) +- max3100_dowork(s); ++ max3100_schedule_work(s); + + return 0; + } +@@ -904,7 +1071,8 @@ + + static struct spi_driver max3100_driver = { + .driver = { +- .name = "max3100", ++ .name = "max3100-ts", ++ .owner = THIS_MODULE, + .pm = MAX3100_PM_OPS, + }, + .probe = max3100_probe, From 18cead916072c3ef92c6ae88130cbd510a14ea36 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Tue, 11 Oct 2022 11:06:45 -0700 Subject: [PATCH 203/244] serial: max3100-ts: Initial commit code from linux-tsimx This is the support as it existed in our linux-tsimx kernel, it does not correctly function in this commit. It is left here as a reference to track diffs that occurred. Signed-off-by: Kris Bahnsen --- drivers/tty/serial/Kconfig | 8 + drivers/tty/serial/Makefile | 1 + drivers/tty/serial/max3100-ts.c | 1062 +++++++++++++++++++++++++++++++ 3 files changed, 1071 insertions(+) create mode 100644 drivers/tty/serial/max3100-ts.c diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index 282116765e648..47da5479cdbdb 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -320,6 +320,14 @@ config SERIAL_MAX3100 Say Y here if you want to support these ICs. +config SERIAL_MAX3100_TS + tristate "MAX3100-TS embeddedTS Extended UART" + depends on SPI + select SERIAL_CORE + help + Support for the embeddedTS FPGA-based MAX3100 multiple-uarts. This + allows multiple emulated MAX3100 UARTs on a single chip-select. + config SERIAL_MAX310X tristate "MAX310X support" depends on SPI_MASTER diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile index a2ccbc508ec57..4db5ccace98ee 100644 --- a/drivers/tty/serial/Makefile +++ b/drivers/tty/serial/Makefile @@ -50,6 +50,7 @@ obj-$(CONFIG_SERIAL_LANTIQ) += lantiq.o obj-$(CONFIG_SERIAL_LITEUART) += liteuart.o obj-$(CONFIG_SERIAL_HS_LPC32XX) += lpc32xx_hs.o obj-$(CONFIG_SERIAL_MAX3100) += max3100.o +obj-$(CONFIG_SERIAL_MAX3100_TS) += max3100-ts.o obj-$(CONFIG_SERIAL_MAX310X) += max310x.o obj-$(CONFIG_SERIAL_MCF) += mcf.o obj-$(CONFIG_SERIAL_MEN_Z135) += men_z135_uart.o diff --git a/drivers/tty/serial/max3100-ts.c b/drivers/tty/serial/max3100-ts.c new file mode 100644 index 0000000000000..a3bc1460f2b76 --- /dev/null +++ b/drivers/tty/serial/max3100-ts.c @@ -0,0 +1,1062 @@ +/* + * + * Copyright (C) 2008 Christian Pellegrin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * + * Notes: the MAX3100 doesn't provide an interrupt on CTS so we have + * to use polling for flow control. TX empty IRQ is unusable, since + * writing conf clears FIFO buffer and we cannot have this interrupt + * always asking us for attention. + * + * Example platform data: + + static struct plat_max3100 max3100_plat_data = { + .loopback = 0, + .crystal = 0, + .poll_time = 100, + }; + + static struct spi_board_info spi_board_info[] = { + { + .modalias = "max3100", + .platform_data = &max3100_plat_data, + .irq = IRQ_EINT12, + .max_speed_hz = 5*1000*1000, + .chip_select = 0, + }, + }; + + * The initial minor number is 209 in the low-density serial port: + * mknod /dev/ttyMAX0 c 204 209 + */ + + /* + Modified from the original max3100.c to support the embeddedTS + MAX3100 extended UARTs. This device puts 3 MAX3100-like uarts in one + chip, but with only a single CS# line going to the chip, and a single + IRQ pin. This requires that all SPI transactions are preceded by a byte + to indicate which of the 3 uarts is being accessed. On an interrupt, + there's no way to tell which of the uarts generated it, so we have to + check 'em all. + */ + +#define MAX3100_MAJOR 204 +#define MAX3100_MINOR 209 + /* + One max3100ts may contain up to 64 uarts. + This driver supports only one max3100ts + */ +#define MAX_MAX3100 64 + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define MAX3100_C (1<<14) +#define MAX3100_D (0<<14) +#define MAX3100_W (1<<15) +#define MAX3100_RX (0<<15) + +#define MAX3100_WC (MAX3100_W | MAX3100_C) +#define MAX3100_RC (MAX3100_RX | MAX3100_C) +#define MAX3100_WD (MAX3100_W | MAX3100_D) +#define MAX3100_RD (MAX3100_RX | MAX3100_D) +#define MAX3100_CMD (3 << 14) + +#define MAX3100_T (1<<14) +#define MAX3100_R (1<<15) + +#define MAX3100_FEN (1<<13) +#define MAX3100_SHDN (1<<12) +#define MAX3100_TM (1<<11) +#define MAX3100_RM (1<<10) +#define MAX3100_PM (1<<9) +#define MAX3100_RAM (1<<8) +#define MAX3100_IR (1<<7) +#define MAX3100_ST (1<<6) +#define MAX3100_PE (1<<5) +#define MAX3100_L (1<<4) +#define MAX3100_BAUD (0xf) + +#define MAX3100_TE (1<<10) +#define MAX3100_RAFE (1<<10) +#define MAX3100_RTS (1<<9) +#define MAX3100_CTS (1<<9) +#define MAX3100_PT (1<<8) +#define MAX3100_DATA (0xff) + +#define MAX3100_RT (MAX3100_R | MAX3100_T) +#define MAX3100_RTC (MAX3100_RT | MAX3100_CTS | MAX3100_RAFE) + +/* the following simulate a status reg for ignore_status_mask */ +#define MAX3100_STATUS_PE 1 +#define MAX3100_STATUS_FE 2 +#define MAX3100_STATUS_OE 4 + +#define MAX3100_CSI 0xc0 + +struct max3100ts_port { + struct uart_port port; + //struct spi_device *spi; + + int cts; /* last CTS received for flow ctrl */ + int tx_empty; /* last TX empty bit */ + + spinlock_t conf_lock; /* shared data */ + int conf_commit; /* need to make changes */ + int conf; /* configuration for the MAX31000 + * (bits 0-7, bits 8-11 are irqs) */ + int rts_commit; /* need to change rts */ + int rts; /* rts status */ + int baud; /* current baud rate */ + + int parity; /* keeps track if we should send parity */ +#define MAX3100_PARITY_ON 1 +#define MAX3100_PARITY_ODD 2 +#define MAX3100_7BIT 4 + int rx_enabled; /* if we should rx chars */ + + //int irq; /* irq assigned to the max3100 */ + + int minor; /* minor number */ + int crystal; /* 1 if 3.6864Mhz crystal 0 for 1.8432 */ + int loopback; /* 1 if we are in loopback mode */ + + /* for handling irqs: need workqueue since we do spi_sync */ + struct workqueue_struct *workqueue; + struct work_struct work; + /* set to 1 to make the workhandler exit as soon as possible */ + int force_end_work; + /* need to know we are suspending to avoid deadlock on workqueue */ + int suspending; + + /* hook for suspending MAX3100 via dedicated pin */ + void (*max3100_hw_suspend) (int suspend); + + /* poll time (in ms) for ctrl lines */ + int poll_time; + /* and its timer */ + struct timer_list timer; + + int tx_fifo_size; + int rx_fifo_size; + +}; + +static struct s_max3100ts_common { + struct max3100ts_port *max3100ts[MAX_MAX3100]; /* the chip */ + struct mutex portlock; /* race on port usage */ + struct mutex max3100ts_lock; /* race on probe */ + struct spi_device *spi; /* all our uarts are on one spi */ + int irq; /* single irq assigned to the max3100-ts */ + int uart_idx; /* index into max3100ts[ ] */ + int uart_count; /* number of uarts detected */ +} max3100ts_common; + +static int max3100_do_parity(struct max3100ts_port *s, u16 c) +{ + int parity; + + if (s->parity & MAX3100_PARITY_ODD) + parity = 1; + else + parity = 0; + + if (s->parity & MAX3100_7BIT) + c &= 0x7f; + else + c &= 0xff; + + parity = parity ^ (hweight8(c) & 1); + return parity; +} + +static int max3100_check_parity(struct max3100ts_port *s, u16 c) +{ + return max3100_do_parity(s, c) == ((c >> 8) & 1); +} + +static void max3100_calc_parity(struct max3100ts_port *s, u16 * c) +{ + if (s->parity & MAX3100_7BIT) + *c &= 0x7f; + else + *c &= 0xff; + + if (s->parity & MAX3100_PARITY_ON) + *c |= max3100_do_parity(s, *c) << 8; +} + +static void max3100_port_work(struct work_struct *w); + +static void max3100_dowork(struct max3100ts_port *s) +{ + if(!work_pending(&s->work)){ + queue_work(s->workqueue, &s->work); + } +} + +static void max3100_timeout(unsigned long data) +{ + struct max3100ts_port *s = (struct max3100ts_port *)data; + if (s->port.state) { + max3100_dowork(s); + mod_timer(&s->timer, jiffies + s->poll_time); + } +} + +static int max3100_sr(struct max3100ts_port *s, u16 tx, u16 * rx) +{ + struct spi_message message; + u16 etx, erx; + int status; + struct spi_transfer tran = { + .tx_buf = &etx, + .rx_buf = &erx, + .len = 2, + }; + struct spi_transfer idx = { + .rx_buf = NULL, + .len = 1, + }; + + if (max3100ts_common.uart_idx != s->minor) { + u8 cs = s->minor | MAX3100_CSI; + idx.tx_buf = &cs; + spi_message_init(&message); + spi_message_add_tail(&idx, &message); + status = spi_sync(max3100ts_common.spi, &message); + if (status) { + dev_warn(&max3100ts_common.spi->dev, + "error while calling spi_sync\n"); + return -EIO; + } + max3100ts_common.uart_idx = s->minor; + } + + etx = cpu_to_be16(tx); + + spi_message_init(&message); + spi_message_add_tail(&tran, &message); + status = spi_sync(max3100ts_common.spi, &message); + if (status) { + dev_warn(&max3100ts_common.spi->dev, + "error while calling spi_sync\n"); + return -EIO; + } + *rx = be16_to_cpu(erx); + s->tx_empty = (*rx & MAX3100_T) > 0; + + dev_dbg(&max3100ts_common.spi->dev, "%04x - %04x\n", tx, *rx); + return 0; +} + +static int max3100_handlerx(struct max3100ts_port *s, u16 rx) +{ + unsigned int ch, flg, status = 0; + int ret = 0, cts; + + if (rx & MAX3100_R && s->rx_enabled) { + dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + + ch = rx & (s->parity & MAX3100_7BIT ? 0x7f : 0xff); + if (rx & MAX3100_RAFE) { + s->port.icount.frame++; + flg = TTY_FRAME; + status |= MAX3100_STATUS_FE; + } else { + if (s->parity & MAX3100_PARITY_ON) { + if (max3100_check_parity(s, rx)) { + s->port.icount.rx++; + flg = TTY_NORMAL; + } else { + s->port.icount.parity++; + flg = TTY_PARITY; + status |= MAX3100_STATUS_PE; + } + } else { + s->port.icount.rx++; + flg = TTY_NORMAL; + } + } + uart_insert_char(&s->port, status, MAX3100_STATUS_OE, ch, flg); + ret = 1; + } + + cts = (rx & MAX3100_CTS) > 0; + if (s->cts != cts) { + s->cts = cts; + uart_handle_cts_change(&s->port, cts ? TIOCM_CTS : 0); + } + + return ret; +} + +static void max3100_port_dowork(struct max3100ts_port *s) +{ + int rxchars, x; + u16 tx, rx; + int conf, cconf, rts, crts; + struct circ_buf *xmit = &s->port.state->xmit; + + dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + + rxchars = 0; + do { + spin_lock(&s->conf_lock); + conf = s->conf; + cconf = s->conf_commit; + s->conf_commit = 0; + rts = s->rts; + crts = s->rts_commit; + s->rts_commit = 0; + spin_unlock(&s->conf_lock); + + if (cconf) + max3100_sr(s, MAX3100_WC | conf, &rx); + if (crts) { + max3100_sr(s, MAX3100_WD | MAX3100_TE | + (s->rts ? MAX3100_RTS : 0), &rx); + rxchars += max3100_handlerx(s, rx); + } + + x = 0; + if (s->port.x_char) { + tx = s->port.x_char; + x = 1; + } else{ + if(!s->force_end_work){ + if (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) { + tx = xmit->buf[xmit->tail]; + x = 2; + } + } + } + if (x) { /* we have something to send, so send it! */ + max3100_calc_parity(s, &tx); + tx |= MAX3100_WD | (s->rts ? MAX3100_RTS : 0); + max3100_sr(s, tx, &rx); + rxchars += max3100_handlerx(s, rx); + + if (rx & MAX3100_T) { /* Tx buffer is/was empty, so tx was sent */ + if (x == 1) { + s->port.icount.tx++; + s->port.x_char = 0; + } else if (x == 2) { + xmit->tail = (xmit->tail + 1) & + (UART_XMIT_SIZE - 1); + s->port.icount.tx++; + } + } + } else { + max3100_sr(s, MAX3100_RD, &rx); + rxchars += max3100_handlerx(s, rx); + } + + if (rxchars > 16) { + tty_flip_buffer_push(&s->port.state->port); + rxchars = 0; + } + + if (uart_circ_chars_pending(xmit) < 4){ + if(s->port.state->port.tty) + uart_write_wakeup(&s->port); + } + } while (!s->force_end_work && + !freezing(current) && + ((rx & MAX3100_R) || + (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)))); + if (rxchars > 0){ + tty_flip_buffer_push(&s->port.state->port); + } +} + +static void max3100_port_work(struct work_struct *w) +{ + struct max3100ts_port *s = container_of(w, struct max3100ts_port, work); + mutex_lock(&max3100ts_common.portlock); + max3100_port_dowork(s); + mutex_unlock(&max3100ts_common.portlock); +} + +static irqreturn_t max3100_thread_irq(int irqno, void *dev_id) +{ + int i; + + dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + + for (i = 0; i < max3100ts_common.uart_count; i++) { + struct max3100ts_port *s = max3100ts_common.max3100ts[i]; + mutex_lock(&max3100ts_common.portlock); + max3100_port_dowork(s); + mutex_unlock(&max3100ts_common.portlock); + } + + return IRQ_HANDLED; +} + +static void max3100_enable_ms(struct uart_port *port) +{ + struct max3100ts_port *s = container_of(port, + struct max3100ts_port, + port); + + if (s->poll_time > 0) + mod_timer(&s->timer, jiffies); + dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); +} + +static void max3100_start_tx(struct uart_port *port) +{ + struct max3100ts_port *s = container_of(port, + struct max3100ts_port, + port); + + dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + + max3100_dowork(s); +} + +static void max3100_stop_rx(struct uart_port *port) +{ + struct max3100ts_port *s = container_of(port, + struct max3100ts_port, + port); + + dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + + s->rx_enabled = 0; + spin_lock(&s->conf_lock); + s->conf &= ~MAX3100_RM; + s->conf_commit = 1; + spin_unlock(&s->conf_lock); +} + +static unsigned int max3100_tx_empty(struct uart_port *port) +{ + struct max3100ts_port *s = container_of(port, + struct max3100ts_port, + port); + + dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + + /* may not be truly up-to-date */ + max3100_dowork(s); + return s->tx_empty; +} + +static unsigned int max3100_get_mctrl(struct uart_port *port) +{ + struct max3100ts_port *s = container_of(port, + struct max3100ts_port, + port); + + dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + + /* always assert DCD and DSR since these lines are not wired */ + return (s->cts ? TIOCM_CTS : 0) | TIOCM_DSR | TIOCM_CAR; +} + +static void max3100_set_mctrl(struct uart_port *port, unsigned int mctrl) +{ + struct max3100ts_port *s = container_of(port, + struct max3100ts_port, + port); + int rts; + + dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + + rts = (mctrl & TIOCM_RTS) > 0; + + spin_lock(&s->conf_lock); + if (s->rts != rts) { + s->rts = rts; + s->rts_commit = 1; + } + spin_unlock(&s->conf_lock); +} + +static void +max3100_set_termios(struct uart_port *port, struct ktermios *termios, + struct ktermios *old) +{ + struct max3100ts_port *s = container_of(port, + struct max3100ts_port, + port); + int baud = 0; + int i; + unsigned cflag; + u32 param_new, param_mask, parity = 0; + + dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + + cflag = termios->c_cflag; + param_new = 0; + param_mask = 0; + + baud = tty_termios_baud_rate(termios); + param_new = s->conf & MAX3100_BAUD; + switch (baud) { + case 300: + if (s->crystal) + baud = s->baud; + else + param_new = 15; + break; + case 600: + param_new = 14 + s->crystal; + break; + case 1200: + param_new = 13 + s->crystal; + break; + case 2400: + param_new = 12 + s->crystal; + break; + case 4800: + param_new = 11 + s->crystal; + break; + case 9600: + param_new = 10 + s->crystal; + break; + case 19200: + param_new = 9 + s->crystal; + break; + case 38400: + param_new = 8 + s->crystal; + break; + case 57600: + param_new = 1 + s->crystal; + break; + case 115200: + param_new = 0 + s->crystal; + break; + case 230400: + if (s->crystal) + param_new = 0; + else + baud = s->baud; + break; + default: + baud = s->baud; + } + tty_termios_encode_baud_rate(termios, baud, baud); + s->baud = baud; + param_mask |= MAX3100_BAUD; + + if ((cflag & CSIZE) == CS8) { + param_new &= ~MAX3100_L; + parity &= ~MAX3100_7BIT; + } else { + param_new |= MAX3100_L; + parity |= MAX3100_7BIT; + cflag = (cflag & ~CSIZE) | CS7; + } + param_mask |= MAX3100_L; + + if (cflag & CSTOPB) + param_new |= MAX3100_ST; + else + param_new &= ~MAX3100_ST; + param_mask |= MAX3100_ST; + + if (cflag & PARENB) { + param_new |= MAX3100_PE; + parity |= MAX3100_PARITY_ON; + } else { + param_new &= ~MAX3100_PE; + parity &= ~MAX3100_PARITY_ON; + } + param_mask |= MAX3100_PE; + + if (cflag & PARODD) + parity |= MAX3100_PARITY_ODD; + else + parity &= ~MAX3100_PARITY_ODD; + + /* mask termios capabilities we don't support */ + cflag &= ~CMSPAR; + termios->c_cflag = cflag; + + s->port.ignore_status_mask = 0; + if (termios->c_iflag & IGNPAR) + s->port.ignore_status_mask |= + MAX3100_STATUS_PE | MAX3100_STATUS_FE | MAX3100_STATUS_OE; + + /* we are sending char from a workqueue so enable */ + s->port.state->port.low_latency = 1; + + if (s->poll_time > 0) + del_timer_sync(&s->timer); + + uart_update_timeout(port, termios->c_cflag, baud); + + spin_lock(&s->conf_lock); + s->conf = (s->conf & ~param_mask) | (param_new & param_mask); + s->conf_commit = 1; + s->parity = parity; + spin_unlock(&s->conf_lock); + + for (i = 0; i < max3100ts_common.uart_count; i++) { + struct max3100ts_port *s = max3100ts_common.max3100ts[i]; + max3100_port_dowork(s); + } + + if (UART_ENABLE_MS(&s->port, termios->c_cflag)) + max3100_enable_ms(&s->port); +} + +static void max3100_shutdown(struct uart_port *port) +{ + struct max3100ts_port *s = container_of(port, + struct max3100ts_port, + port); + + dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + + if (s->suspending) + return; + + /* Make sure any dowork from the irq thread are finished */ + s->force_end_work = 1; + mutex_lock(&max3100ts_common.portlock); + mutex_unlock(&max3100ts_common.portlock); + + if (s->poll_time > 0) + del_timer_sync(&s->timer); + + if (s->workqueue) { + flush_workqueue(s->workqueue); + destroy_workqueue(s->workqueue); + s->workqueue = NULL; + } + + /* set shutdown mode to save power */ + if (s->max3100_hw_suspend) + s->max3100_hw_suspend(1); + else { + u16 tx, rx; + + tx = MAX3100_WC | MAX3100_SHDN; + mutex_lock(&max3100ts_common.portlock); + max3100_sr(s, tx, &rx); + mutex_unlock(&max3100ts_common.portlock); + } +} + +static int max3100_startup(struct uart_port *port) +{ + struct max3100ts_port *s = container_of(port, + struct max3100ts_port, + port); + char b[12]; + + dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + + s->conf = MAX3100_RM | MAX3100_TM; + s->baud = s->crystal ? 230400 : 115200; + s->rx_enabled = 1; + + if (s->suspending) + return 0; + + s->force_end_work = 0; + s->parity = 0; + s->rts = 0; + + sprintf(b, "max3100-%d", s->minor); + s->workqueue = create_singlethread_workqueue(b); + if (!s->workqueue) { + dev_warn(&max3100ts_common.spi->dev, + "cannot create workqueue\n"); + return -EBUSY; + } + INIT_WORK(&s->work, max3100_port_work); + + if (s->loopback) { + u16 tx, rx; + tx = 0x4001; + max3100_sr(s, tx, &rx); + } + + if (s->max3100_hw_suspend) + s->max3100_hw_suspend(0); + s->conf_commit = 1; + + /* wait for clock to settle */ + if (s->port.line == 0) + msleep(50); + + max3100_enable_ms(&s->port); + + return 0; +} + +static const char *max3100_type(struct uart_port *port) +{ + struct max3100ts_port *s = container_of(port, + struct max3100ts_port, + port); + + dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + + return s->port.type == PORT_MAX3100 ? "MAX3100" : NULL; +} + +static void max3100_release_port(struct uart_port *port) +{ + dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); +} + +static void max3100_config_port(struct uart_port *port, int flags) +{ + struct max3100ts_port *s = container_of(port, + struct max3100ts_port, + port); + + dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + + if (flags & UART_CONFIG_TYPE) + s->port.type = PORT_MAX3100; +} + +static int max3100_verify_port(struct uart_port *port, + struct serial_struct *ser) +{ + int ret = -EINVAL; + + dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + + if (ser->type == PORT_UNKNOWN || ser->type == PORT_MAX3100) + ret = 0; + return ret; +} + +static void max3100_stop_tx(struct uart_port *port) +{ + dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); +} + +static int max3100_request_port(struct uart_port *port) +{ + dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + return 0; +} + +static void max3100_break_ctl(struct uart_port *port, int break_state) +{ + dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); +} + +static struct uart_ops max3100_ops = { + .tx_empty = max3100_tx_empty, + .set_mctrl = max3100_set_mctrl, + .get_mctrl = max3100_get_mctrl, + .stop_tx = max3100_stop_tx, + .start_tx = max3100_start_tx, + .stop_rx = max3100_stop_rx, + .enable_ms = max3100_enable_ms, + .break_ctl = max3100_break_ctl, + .startup = max3100_startup, + .shutdown = max3100_shutdown, + .set_termios = max3100_set_termios, + .type = max3100_type, + .release_port = max3100_release_port, + .request_port = max3100_request_port, + .config_port = max3100_config_port, + .verify_port = max3100_verify_port, +}; + +static struct uart_driver max3100_uart_driver = { + .owner = THIS_MODULE, + .driver_name = "ttyMAX", + .dev_name = "ttyMAX", + .major = MAX3100_MAJOR, + .minor = MAX3100_MINOR, + .nr = MAX_MAX3100, +}; + +static int uart_driver_registered; + +#ifdef CONFIG_OF +static const struct of_device_id max3100_dt_ids[] = { + {.compatible = "max3100-ts"}, + {} +}; + +MODULE_DEVICE_TABLE(of, max3100_dt_ids); + +static const struct plat_max3100 *max3100_probe_dt(struct device *dev) +{ + struct plat_max3100 *pdata; + struct device_node *node = dev->of_node; + const struct of_device_id *match; + + if (!node) { + dev_err(dev, "Device does not have associated DT data\n"); + return ERR_PTR(-EINVAL); + } + + match = of_match_device(max3100_dt_ids, dev); + if (!match) { + dev_err(dev, "Unknown device model\n"); + return ERR_PTR(-EINVAL); + } + + pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); + if (!pdata) + return ERR_PTR(-ENOMEM); + + // Force MAX310 into loopback + of_property_read_u32(node, "loopback", &pdata->loopback); + // Crystal <1 = 3.6864MHz> <0 = 1.8432MHz> + of_property_read_u32(node, "crystal", &pdata->crystal); + // Poll time in ms, 0 disables CTS, 100 typical + of_property_read_u32(node, "poll-time", &pdata->poll_time); + // Size of the Tx FIFO, in bytes + of_property_read_u32(node, "tx-fifo-size", &pdata->tx_fifo_size); + // Size of the Rx FIFO, in bytes + of_property_read_u32(node, "rx-fifo-size", &pdata->rx_fifo_size); + return pdata; +} + +#else + +static const struct plat_max3100 *max3100_probe_dt(struct device *dev) +{ + dev_err(dev, "no platform data defined\n"); + return ERR_PTR(-EINVAL); +} + +#endif + +static int max3100_probe(struct spi_device *spi) +{ + int i, retval; + const struct plat_max3100 *pdata; + u16 tx, rx; + + mutex_init(&max3100ts_common.max3100ts_lock); + mutex_init(&max3100ts_common.portlock); + + mutex_lock(&max3100ts_common.max3100ts_lock); + + if (!uart_driver_registered) { + uart_driver_registered = 1; + retval = uart_register_driver(&max3100_uart_driver); + if (retval) { + printk(KERN_ERR + "Couldn't register max3100 uart driver\n"); + mutex_unlock(&max3100ts_common.max3100ts_lock); + return retval; + } + } + + pdata = max3100_probe_dt(&spi->dev); + if (IS_ERR(pdata)) { + mutex_unlock(&max3100ts_common.max3100ts_lock); + return PTR_ERR(pdata); + } + + max3100ts_common.spi = spi; + max3100ts_common.irq = spi->irq; + max3100ts_common.uart_idx = -1; + max3100ts_common.uart_count = 0; + + for (i = 0; i < MAX_MAX3100; i++) { + max3100ts_common.max3100ts[i] = + kzalloc(sizeof(struct max3100ts_port), GFP_KERNEL); + if (!max3100ts_common.max3100ts[i]) { + dev_warn(&spi->dev, + "kmalloc for max3100 structure %d failed!\n", + i); + mutex_unlock(&max3100ts_common.max3100ts_lock); + return -ENOMEM; + } + + spin_lock_init(&max3100ts_common.max3100ts[i]->conf_lock); + spi_set_drvdata(spi, max3100ts_common.max3100ts[i]); + + max3100ts_common.max3100ts[i]->minor = i; + + tx = MAX3100_WC | MAX3100_SHDN | 5; + max3100_sr(max3100ts_common.max3100ts[i], tx, &rx); + tx = MAX3100_RC; + rx = 0; + max3100_sr(max3100ts_common.max3100ts[i], tx, &rx); + if ((rx & MAX3100_BAUD) != 5) { + kfree(max3100ts_common.max3100ts[i]); + max3100ts_common.max3100ts[i] = NULL; + break; + } else + max3100ts_common.uart_count++; + + max3100ts_common.max3100ts[i]->crystal = pdata->crystal; + max3100ts_common.max3100ts[i]->loopback = pdata->loopback; + max3100ts_common.max3100ts[i]->poll_time = + pdata->poll_time * HZ / 1000; + if (pdata->poll_time > 0 + && max3100ts_common.max3100ts[i]->poll_time == 0) + max3100ts_common.max3100ts[i]->poll_time = 1; + max3100ts_common.max3100ts[i]->max3100_hw_suspend = + pdata->max3100_hw_suspend; + init_timer(&max3100ts_common.max3100ts[i]->timer); + max3100ts_common.max3100ts[i]->timer.function = max3100_timeout; + max3100ts_common.max3100ts[i]->timer.data = + (unsigned long)max3100ts_common.max3100ts[i]; + + dev_dbg(&spi->dev, "%s: adding port %d\n", __func__, i); + max3100ts_common.max3100ts[i]->port.irq = max3100ts_common.irq; + max3100ts_common.max3100ts[i]->port.uartclk = + max3100ts_common.max3100ts[i]->crystal ? 3686400 : 1843200; + max3100ts_common.max3100ts[i]->port.fifosize = 16; + max3100ts_common.max3100ts[i]->port.ops = &max3100_ops; + max3100ts_common.max3100ts[i]->port.flags = + UPF_SKIP_TEST | UPF_BOOT_AUTOCONF; + max3100ts_common.max3100ts[i]->port.line = i; + max3100ts_common.max3100ts[i]->port.type = PORT_MAX3100; + max3100ts_common.max3100ts[i]->port.dev = &spi->dev; + + retval = + uart_add_one_port(&max3100_uart_driver, + &max3100ts_common.max3100ts[i]->port); + if (retval < 0) + dev_warn(&spi->dev, + "uart_add_one_port failed for line %d with error %d\n", + i, retval); + tx = MAX3100_WC | MAX3100_SHDN; + max3100_sr(max3100ts_common.max3100ts[i], tx, &rx); + } + + mutex_unlock(&max3100ts_common.max3100ts_lock); + + retval = devm_request_threaded_irq(&spi->dev, spi->irq, NULL, max3100_thread_irq, + IRQF_TRIGGER_LOW | IRQF_ONESHOT, "max3100-ts", + &max3100ts_common); + + if (retval) { + dev_warn(&spi->dev, "cannot allocate irq %d\n", spi->irq); + return retval; + } + + dev_info(&spi->dev, "Detected %d uarts\n", max3100ts_common.uart_count); + return 0; +} + +static int max3100_remove(struct spi_device *spi) +{ + int i; + + mutex_lock(&max3100ts_common.max3100ts_lock); + + /* find out the index for the chip we are removing */ + for (i = MAX_MAX3100 - 1; i >= 0; i--) + if (max3100ts_common.max3100ts[i]) { + + dev_dbg(&spi->dev, "%s: removing port %d\n", __func__, + i); + uart_remove_one_port(&max3100_uart_driver, + &max3100ts_common.max3100ts[i]-> + port); + + kfree(max3100ts_common.max3100ts[i]); + max3100ts_common.max3100ts[i] = NULL; + } + + if (max3100ts_common.irq) { + free_irq(max3100ts_common.irq, &max3100ts_common); + max3100ts_common.irq = 0; + } + + pr_debug("removing max3100 driver\n"); + uart_unregister_driver(&max3100_uart_driver); + + mutex_unlock(&max3100ts_common.max3100ts_lock); + return 0; +} + +#ifdef CONFIG_PM_SLEEP + +static int max3100_suspend(struct device *dev) +{ + struct max3100ts_port *s = dev_get_drvdata(dev); + + dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + + disable_irq(max3100ts_common.irq); + + s->suspending = 1; + uart_suspend_port(&max3100_uart_driver, &s->port); + + if (s->max3100_hw_suspend) + s->max3100_hw_suspend(1); + else { + /* no HW suspend, so do SW one */ + u16 tx, rx; + tx = MAX3100_WC | MAX3100_SHDN; + mutex_lock(&max3100ts_common.portlock); + max3100_sr(s, tx, &rx); + mutex_unlock(&max3100ts_common.portlock); + } + return 0; +} + +static int max3100_resume(struct device *dev) +{ + struct max3100ts_port *s = dev_get_drvdata(dev); + + dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + + if (s->max3100_hw_suspend) + s->max3100_hw_suspend(0); + uart_resume_port(&max3100_uart_driver, &s->port); + s->suspending = 0; + + enable_irq(max3100ts_common.irq); + + s->conf_commit = 1; + if (s->workqueue) + max3100_dowork(s); + + return 0; +} + +static SIMPLE_DEV_PM_OPS(max3100_pm_ops, max3100_suspend, max3100_resume); +#define MAX3100_PM_OPS (&max3100_pm_ops) + +#else +#define MAX3100_PM_OPS NULL +#endif + +static struct spi_driver max3100_driver = { + .driver = { + .name = "max3100-ts", + .owner = THIS_MODULE, + .pm = MAX3100_PM_OPS, + }, + .probe = max3100_probe, + .remove = max3100_remove, +}; + +module_spi_driver(max3100_driver); + +MODULE_DESCRIPTION("MAX3100 driver"); +MODULE_AUTHOR("Christian Pellegrin "); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("spi:max3100"); \ No newline at end of file From 9a206759a54489e087ccccd3c9431dde8e60b8e3 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Tue, 11 Oct 2022 11:20:59 -0700 Subject: [PATCH 204/244] serial: max3100-ts: Multiple fixes Merged in changes that happened to serial (specifically max3100.c) over time since 4.9; most of the changes were to the timer code. Removed conf_lock use and instead use port->lock for all of these accesses, Linux serial docs indicate that this is preferred for local locking. The portlock mutex was shifted to lock SPI access only since this is sleepable. Added port->lock locking to code that was accessing uart_port members that should have been protected by that lock. Renamed work scheduling function to be more obvious. Updated compatible string. Signed-off-by: Kris Bahnsen --- drivers/tty/serial/max3100-ts.c | 121 +++++++++++++++++++------------- 1 file changed, 73 insertions(+), 48 deletions(-) diff --git a/drivers/tty/serial/max3100-ts.c b/drivers/tty/serial/max3100-ts.c index a3bc1460f2b76..c908ac6df8ac9 100644 --- a/drivers/tty/serial/max3100-ts.c +++ b/drivers/tty/serial/max3100-ts.c @@ -1,13 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * * Copyright (C) 2008 Christian Pellegrin * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * * Notes: the MAX3100 doesn't provide an interrupt on CTS so we have * to use polling for flow control. TX empty IRQ is unusable, since * writing conf clears FIFO buffer and we cannot have this interrupt @@ -119,7 +114,6 @@ struct max3100ts_port { int cts; /* last CTS received for flow ctrl */ int tx_empty; /* last TX empty bit */ - spinlock_t conf_lock; /* shared data */ int conf_commit; /* need to make changes */ int conf; /* configuration for the MAX31000 * (bits 0-7, bits 8-11 are irqs) */ @@ -206,18 +200,18 @@ static void max3100_calc_parity(struct max3100ts_port *s, u16 * c) static void max3100_port_work(struct work_struct *w); -static void max3100_dowork(struct max3100ts_port *s) +static void max3100_schedule_work(struct max3100ts_port *s) { if(!work_pending(&s->work)){ queue_work(s->workqueue, &s->work); } } -static void max3100_timeout(unsigned long data) +static void max3100_timeout(struct timer_list *t) { - struct max3100ts_port *s = (struct max3100ts_port *)data; + struct max3100ts_port *s = from_timer(s, t, timer); if (s->port.state) { - max3100_dowork(s); + max3100_schedule_work(s); mod_timer(&s->timer, jiffies + s->poll_time); } } @@ -237,6 +231,11 @@ static int max3100_sr(struct max3100ts_port *s, u16 tx, u16 * rx) .len = 1, }; + /* The SPI functions provide a locking mechanism that we could use + * here, however, we don't have access to struct spi_controller (that + * I am aware of), so we would use the portlock around these functions. + * It is critical that if two SPI transfers happen, they have no + * interruptions between them. */ if (max3100ts_common.uart_idx != s->minor) { u8 cs = s->minor | MAX3100_CSI; idx.tx_buf = &cs; @@ -246,6 +245,7 @@ static int max3100_sr(struct max3100ts_port *s, u16 tx, u16 * rx) if (status) { dev_warn(&max3100ts_common.spi->dev, "error while calling spi_sync\n"); + mutex_unlock(&max3100ts_common.portlock); return -EIO; } max3100ts_common.uart_idx = s->minor; @@ -272,11 +272,13 @@ static int max3100_handlerx(struct max3100ts_port *s, u16 rx) { unsigned int ch, flg, status = 0; int ret = 0, cts; + unsigned long flags; if (rx & MAX3100_R && s->rx_enabled) { dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); ch = rx & (s->parity & MAX3100_7BIT ? 0x7f : 0xff); + spin_lock_irqsave(&s->port.lock, flags); if (rx & MAX3100_RAFE) { s->port.icount.frame++; flg = TTY_FRAME; @@ -296,14 +298,18 @@ static int max3100_handlerx(struct max3100ts_port *s, u16 rx) flg = TTY_NORMAL; } } + spin_unlock_irqrestore(&s->port.lock, flags); + uart_insert_char(&s->port, status, MAX3100_STATUS_OE, ch, flg); ret = 1; } cts = (rx & MAX3100_CTS) > 0; if (s->cts != cts) { + spin_lock_irqsave(&s->port.lock, flags); s->cts = cts; - uart_handle_cts_change(&s->port, cts ? TIOCM_CTS : 0); + uart_handle_cts_change(&s->port, cts ? 1 : 0); + spin_unlock_irqrestore(&s->port.lock, flags); } return ret; @@ -313,21 +319,27 @@ static void max3100_port_dowork(struct max3100ts_port *s) { int rxchars, x; u16 tx, rx; - int conf, cconf, rts, crts; + int conf, cconf, crts; + unsigned long flags; struct circ_buf *xmit = &s->port.state->xmit; dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); rxchars = 0; + + /* Since the do/while loop has its while conditional at the end which + * some of the calls are dependant on holding the lock, each loop must + * start with the lock held since we need the lock when the while is + * checked. + */ + spin_lock_irqsave(&s->port.lock, flags); do { - spin_lock(&s->conf_lock); conf = s->conf; cconf = s->conf_commit; s->conf_commit = 0; - rts = s->rts; crts = s->rts_commit; s->rts_commit = 0; - spin_unlock(&s->conf_lock); + spin_unlock_irqrestore(&s->port.lock, flags); if (cconf) max3100_sr(s, MAX3100_WC | conf, &rx); @@ -338,6 +350,8 @@ static void max3100_port_dowork(struct max3100ts_port *s) } x = 0; + /* Lock in case we need to call uart_circ_empty() */ + spin_lock_irqsave(&s->port.lock, flags); if (s->port.x_char) { tx = s->port.x_char; x = 1; @@ -349,6 +363,8 @@ static void max3100_port_dowork(struct max3100ts_port *s) } } } + spin_unlock_irqrestore(&s->port.lock, flags); + if (x) { /* we have something to send, so send it! */ max3100_calc_parity(s, &tx); tx |= MAX3100_WD | (s->rts ? MAX3100_RTS : 0); @@ -356,6 +372,7 @@ static void max3100_port_dowork(struct max3100ts_port *s) rxchars += max3100_handlerx(s, rx); if (rx & MAX3100_T) { /* Tx buffer is/was empty, so tx was sent */ + spin_lock_irqsave(&s->port.lock, flags); if (x == 1) { s->port.icount.tx++; s->port.x_char = 0; @@ -364,28 +381,41 @@ static void max3100_port_dowork(struct max3100ts_port *s) (UART_XMIT_SIZE - 1); s->port.icount.tx++; } + spin_unlock_irqrestore(&s->port.lock, flags); } } else { max3100_sr(s, MAX3100_RD, &rx); rxchars += max3100_handlerx(s, rx); } - if (rxchars > 16) { + /* A balance between servicing the UART and getting data to + * userspace */ + if (rxchars > 31) { tty_flip_buffer_push(&s->port.state->port); rxchars = 0; } + /* This is a bit funky, but, according to docs, all xmit + * head/tail accesses need to be inside of the port->lock. + * Grab the lock now, and if we break out of the while + * loop, then release the lock. This hopefully should reduce + * number of acquisitions for a bit of a performance gain. + */ + spin_lock_irqsave(&s->port.lock, flags); if (uart_circ_chars_pending(xmit) < 4){ if(s->port.state->port.tty) uart_write_wakeup(&s->port); } + } while (!s->force_end_work && !freezing(current) && ((rx & MAX3100_R) || - (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)))); - if (rxchars > 0){ + (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)))); + + spin_unlock_irqrestore(&s->port.lock, flags); + + if (rxchars) tty_flip_buffer_push(&s->port.state->port); - } } static void max3100_port_work(struct work_struct *w) @@ -396,6 +426,7 @@ static void max3100_port_work(struct work_struct *w) mutex_unlock(&max3100ts_common.portlock); } +/* Threaded handler called in a sleepable context */ static irqreturn_t max3100_thread_irq(int irqno, void *dev_id) { int i; @@ -431,7 +462,7 @@ static void max3100_start_tx(struct uart_port *port) dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); - max3100_dowork(s); + max3100_schedule_work(s); } static void max3100_stop_rx(struct uart_port *port) @@ -442,11 +473,10 @@ static void max3100_stop_rx(struct uart_port *port) dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); + /* NOTE: port->lock already taken when this function is called */ s->rx_enabled = 0; - spin_lock(&s->conf_lock); s->conf &= ~MAX3100_RM; s->conf_commit = 1; - spin_unlock(&s->conf_lock); } static unsigned int max3100_tx_empty(struct uart_port *port) @@ -458,7 +488,7 @@ static unsigned int max3100_tx_empty(struct uart_port *port) dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); /* may not be truly up-to-date */ - max3100_dowork(s); + max3100_schedule_work(s); return s->tx_empty; } @@ -485,30 +515,27 @@ static void max3100_set_mctrl(struct uart_port *port, unsigned int mctrl) rts = (mctrl & TIOCM_RTS) > 0; - spin_lock(&s->conf_lock); if (s->rts != rts) { s->rts = rts; s->rts_commit = 1; } - spin_unlock(&s->conf_lock); } static void max3100_set_termios(struct uart_port *port, struct ktermios *termios, - struct ktermios *old) + const struct ktermios *old) { struct max3100ts_port *s = container_of(port, struct max3100ts_port, port); int baud = 0; - int i; unsigned cflag; + unsigned long flags; u32 param_new, param_mask, parity = 0; dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); cflag = termios->c_cflag; - param_new = 0; param_mask = 0; baud = tty_termios_baud_rate(termios); @@ -599,24 +626,20 @@ max3100_set_termios(struct uart_port *port, struct ktermios *termios, s->port.ignore_status_mask |= MAX3100_STATUS_PE | MAX3100_STATUS_FE | MAX3100_STATUS_OE; - /* we are sending char from a workqueue so enable */ - s->port.state->port.low_latency = 1; - if (s->poll_time > 0) del_timer_sync(&s->timer); uart_update_timeout(port, termios->c_cflag, baud); - spin_lock(&s->conf_lock); + spin_lock_irqsave(&s->port.lock, flags); s->conf = (s->conf & ~param_mask) | (param_new & param_mask); s->conf_commit = 1; s->parity = parity; - spin_unlock(&s->conf_lock); + spin_unlock_irqrestore(&s->port.lock, flags); - for (i = 0; i < max3100ts_common.uart_count; i++) { - struct max3100ts_port *s = max3100ts_common.max3100ts[i]; - max3100_port_dowork(s); - } + mutex_lock(&max3100ts_common.portlock); + max3100_port_dowork(s); + mutex_unlock(&max3100ts_common.portlock); if (UART_ENABLE_MS(&s->port, termios->c_cflag)) max3100_enable_ms(&s->port); @@ -692,7 +715,9 @@ static int max3100_startup(struct uart_port *port) if (s->loopback) { u16 tx, rx; tx = 0x4001; + mutex_lock(&max3100ts_common.portlock); max3100_sr(s, tx, &rx); + mutex_unlock(&max3100ts_common.portlock); } if (s->max3100_hw_suspend) @@ -796,7 +821,7 @@ static int uart_driver_registered; #ifdef CONFIG_OF static const struct of_device_id max3100_dt_ids[] = { - {.compatible = "max3100-ts"}, + {.compatible = "technologic,max3100-ts"}, {} }; @@ -890,16 +915,17 @@ static int max3100_probe(struct spi_device *spi) return -ENOMEM; } - spin_lock_init(&max3100ts_common.max3100ts[i]->conf_lock); spi_set_drvdata(spi, max3100ts_common.max3100ts[i]); max3100ts_common.max3100ts[i]->minor = i; tx = MAX3100_WC | MAX3100_SHDN | 5; + mutex_lock(&max3100ts_common.portlock); max3100_sr(max3100ts_common.max3100ts[i], tx, &rx); tx = MAX3100_RC; rx = 0; max3100_sr(max3100ts_common.max3100ts[i], tx, &rx); + mutex_unlock(&max3100ts_common.portlock); if ((rx & MAX3100_BAUD) != 5) { kfree(max3100ts_common.max3100ts[i]); max3100ts_common.max3100ts[i] = NULL; @@ -916,10 +942,8 @@ static int max3100_probe(struct spi_device *spi) max3100ts_common.max3100ts[i]->poll_time = 1; max3100ts_common.max3100ts[i]->max3100_hw_suspend = pdata->max3100_hw_suspend; - init_timer(&max3100ts_common.max3100ts[i]->timer); - max3100ts_common.max3100ts[i]->timer.function = max3100_timeout; - max3100ts_common.max3100ts[i]->timer.data = - (unsigned long)max3100ts_common.max3100ts[i]; + timer_setup(&max3100ts_common.max3100ts[i]->timer, + max3100_timeout, 0); dev_dbg(&spi->dev, "%s: adding port %d\n", __func__, i); max3100ts_common.max3100ts[i]->port.irq = max3100ts_common.irq; @@ -941,7 +965,9 @@ static int max3100_probe(struct spi_device *spi) "uart_add_one_port failed for line %d with error %d\n", i, retval); tx = MAX3100_WC | MAX3100_SHDN; + mutex_lock(&max3100ts_common.portlock); max3100_sr(max3100ts_common.max3100ts[i], tx, &rx); + mutex_unlock(&max3100ts_common.portlock); } mutex_unlock(&max3100ts_common.max3100ts_lock); @@ -959,7 +985,7 @@ static int max3100_probe(struct spi_device *spi) return 0; } -static int max3100_remove(struct spi_device *spi) +static void max3100_remove(struct spi_device *spi) { int i; @@ -988,7 +1014,6 @@ static int max3100_remove(struct spi_device *spi) uart_unregister_driver(&max3100_uart_driver); mutex_unlock(&max3100ts_common.max3100ts_lock); - return 0; } #ifdef CONFIG_PM_SLEEP @@ -1032,7 +1057,7 @@ static int max3100_resume(struct device *dev) s->conf_commit = 1; if (s->workqueue) - max3100_dowork(s); + max3100_schedule_work(s); return 0; } @@ -1059,4 +1084,4 @@ module_spi_driver(max3100_driver); MODULE_DESCRIPTION("MAX3100 driver"); MODULE_AUTHOR("Christian Pellegrin "); MODULE_LICENSE("GPL"); -MODULE_ALIAS("spi:max3100"); \ No newline at end of file +MODULE_ALIAS("spi:max3100"); From f446622e346ef56a15ee2380f6db8a559e829d54 Mon Sep 17 00:00:00 2001 From: "Jiri Slaby (SUSE)" Date: Fri, 5 Apr 2024 08:08:23 +0200 Subject: [PATCH 205/244] tty: serial: switch from circ_buf to kfifo MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Switch from struct circ_buf to proper kfifo. kfifo provides much better API, esp. when wrap-around of the buffer needs to be taken into account. Look at pl011_dma_tx_refill() or cpm_uart_tx_pump() changes for example. Kfifo API can also fill in scatter-gather DMA structures, so it easier for that use case too. Look at lpuart_dma_tx() for example. Note that not all drivers can be converted to that (like atmel_serial), they handle DMA specially. Note that usb-serial uses kfifo for TX for ages. omap needed a bit more care as it needs to put a char into FIFO to start the DMA transfer when OMAP_DMA_TX_KICK is set. In that case, we have to do kfifo_dma_out_prepare twice: once to find out the tx_size (to find out if it is worths to do DMA at all -- size >= 4), the second time for the actual transfer. All traces of circ_buf are removed from serial_core.h (and its struct uart_state). Signed-off-by: Jiri Slaby (SUSE) Cc: Al Cooper Cc: Matthias Brugger Cc: AngeloGioacchino Del Regno Cc: Kumaravel Thiagarajan Cc: Tharun Kumar P Cc: Russell King Cc: Vineet Gupta Cc: Richard Genoud Cc: Nicolas Ferre Cc: Alexandre Belloni Cc: Claudiu Beznea Cc: Alexander Shiyan Cc: Baruch Siach Cc: Maciej W. Rozycki Cc: Shawn Guo Cc: Sascha Hauer Cc: Fabio Estevam Cc: Neil Armstrong Cc: Kevin Hilman Cc: Jerome Brunet Cc: Martin Blumenstingl Cc: Taichi Sugaya Cc: Takao Orito Cc: Bjorn Andersson Cc: Konrad Dybcio Cc: Pali Rohár Cc: Michael Ellerman Cc: Nicholas Piggin Cc: Christophe Leroy Cc: Aneesh Kumar K.V Cc: Naveen N. Rao Cc: Manivannan Sadhasivam Cc: Krzysztof Kozlowski Cc: Alim Akhtar Cc: Laxman Dewangan Cc: Thierry Reding Cc: Jonathan Hunter Cc: Orson Zhai Cc: Baolin Wang Cc: Chunyan Zhang Cc: Patrice Chotard Cc: Maxime Coquelin Cc: Alexandre Torgue Cc: David S. Miller Cc: Hammer Hsieh Cc: Peter Korsgaard Cc: Timur Tabi Cc: Michal Simek Cc: Sumit Semwal Cc: Christian König Link: https://lore.kernel.org/r/20240405060826.2521-13-jirislaby@kernel.org Signed-off-by: Greg Kroah-Hartman --- drivers/tty/serial/max3100-ts.c | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/drivers/tty/serial/max3100-ts.c b/drivers/tty/serial/max3100-ts.c index c908ac6df8ac9..6b75574461fb0 100644 --- a/drivers/tty/serial/max3100-ts.c +++ b/drivers/tty/serial/max3100-ts.c @@ -317,11 +317,12 @@ static int max3100_handlerx(struct max3100ts_port *s, u16 rx) static void max3100_port_dowork(struct max3100ts_port *s) { + struct tty_port *tport = &s->port.state->port; + unsigned char ch; int rxchars, x; u16 tx, rx; int conf, cconf, crts; unsigned long flags; - struct circ_buf *xmit = &s->port.state->xmit; dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); @@ -351,14 +352,18 @@ static void max3100_port_dowork(struct max3100ts_port *s) x = 0; /* Lock in case we need to call uart_circ_empty() */ + /* XXX: Does this mean we need to actually use the UART port lock + * rather than our own locking? + */ spin_lock_irqsave(&s->port.lock, flags); if (s->port.x_char) { tx = s->port.x_char; x = 1; - } else{ + } else { if(!s->force_end_work){ - if (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) { - tx = xmit->buf[xmit->tail]; + if (!uart_tx_stopped(&s->port) && + uart_fifo_get(&s->port, &ch)) { + tx = ch; x = 2; } } @@ -377,8 +382,6 @@ static void max3100_port_dowork(struct max3100ts_port *s) s->port.icount.tx++; s->port.x_char = 0; } else if (x == 2) { - xmit->tail = (xmit->tail + 1) & - (UART_XMIT_SIZE - 1); s->port.icount.tx++; } spin_unlock_irqrestore(&s->port.lock, flags); @@ -402,7 +405,7 @@ static void max3100_port_dowork(struct max3100ts_port *s) * number of acquisitions for a bit of a performance gain. */ spin_lock_irqsave(&s->port.lock, flags); - if (uart_circ_chars_pending(xmit) < 4){ + if (kfifo_len(&tport->xmit_fifo) < 4){ if(s->port.state->port.tty) uart_write_wakeup(&s->port); } @@ -410,7 +413,8 @@ static void max3100_port_dowork(struct max3100ts_port *s) } while (!s->force_end_work && !freezing(current) && ((rx & MAX3100_R) || - (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)))); + (!kfifo_is_empty(&tport->xmit_fifo) && + !uart_tx_stopped(&s->port)))); spin_unlock_irqrestore(&s->port.lock, flags); From 081c156b3fafd2ab7ba3318eebc4a8ac0ae8b0cb Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 2 Apr 2024 22:50:28 +0300 Subject: [PATCH 206/244] serial: max3100: Lock port->lock when calling uart_handle_cts_change() XXX: THIS MAY NOT BE NEEDED AND MAY BREAK PORT LOCKING WE ADDED uart_handle_cts_change() has to be called with port lock taken, Since we run it in a separate work, the lock may not be taken at the time of running. Make sure that it's taken by explicitly doing that. Without it we got a splat: WARNING: CPU: 0 PID: 10 at drivers/tty/serial/serial_core.c:3491 uart_handle_cts_change+0xa6/0xb0 ... Workqueue: max3100-0 max3100_work [max3100] RIP: 0010:uart_handle_cts_change+0xa6/0xb0 ... max3100_handlerx+0xc5/0x110 [max3100] max3100_work+0x12a/0x340 [max3100] Fixes: 7831d56b0a35 ("tty: MAX3100") Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20240402195306.269276-2-andriy.shevchenko@linux.intel.com Signed-off-by: Greg Kroah-Hartman --- drivers/tty/serial/max3100-ts.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/max3100-ts.c b/drivers/tty/serial/max3100-ts.c index 6b75574461fb0..8e42c5bbd4f6a 100644 --- a/drivers/tty/serial/max3100-ts.c +++ b/drivers/tty/serial/max3100-ts.c @@ -268,7 +268,7 @@ static int max3100_sr(struct max3100ts_port *s, u16 tx, u16 * rx) return 0; } -static int max3100_handlerx(struct max3100ts_port *s, u16 rx) +static int max3100_handlerx_unlocked(struct max3100ts_port *s, u16 rx) { unsigned int ch, flg, status = 0; int ret = 0, cts; @@ -315,6 +315,17 @@ static int max3100_handlerx(struct max3100ts_port *s, u16 rx) return ret; } +static int max3100_handlerx(struct max3100ts_port *s, u16 rx) +{ + unsigned long flags; + int ret; + + uart_port_lock_irqsave(&s->port, &flags); + ret = max3100_handlerx_unlocked(s, rx); + uart_port_unlock_irqrestore(&s->port, flags); + return ret; +} + static void max3100_port_dowork(struct max3100ts_port *s) { struct tty_port *tport = &s->port.state->port; From 3b62765be96c84d3036f2d10d5a21de13015779d Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 2 Apr 2024 22:50:29 +0300 Subject: [PATCH 207/244] serial: max3100: Update uart_driver_registered on driver removal MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The removal of the last MAX3100 device triggers the removal of the driver. However, code doesn't update the respective global variable and after insmod — rmmod — insmod cycle the kernel oopses: max3100 spi-PRP0001:01: max3100_probe: adding port 0 BUG: kernel NULL pointer dereference, address: 0000000000000408 ... RIP: 0010:serial_core_register_port+0xa0/0x840 ... max3100_probe+0x1b6/0x280 [max3100] spi_probe+0x8d/0xb0 Update the actual state so next time UART driver will be registered again. Hugo also noticed, that the error path in the probe also affected by having the variable set, and not cleared. Instead of clearing it move the assignment after the successfull uart_register_driver() call. Fixes: 7831d56b0a35 ("tty: MAX3100") Signed-off-by: Andy Shevchenko Reviewed-by: Hugo Villeneuve Link: https://lore.kernel.org/r/20240402195306.269276-3-andriy.shevchenko@linux.intel.com Signed-off-by: Greg Kroah-Hartman --- drivers/tty/serial/max3100-ts.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/max3100-ts.c b/drivers/tty/serial/max3100-ts.c index 8e42c5bbd4f6a..ee505546526d4 100644 --- a/drivers/tty/serial/max3100-ts.c +++ b/drivers/tty/serial/max3100-ts.c @@ -898,7 +898,6 @@ static int max3100_probe(struct spi_device *spi) mutex_lock(&max3100ts_common.max3100ts_lock); if (!uart_driver_registered) { - uart_driver_registered = 1; retval = uart_register_driver(&max3100_uart_driver); if (retval) { printk(KERN_ERR @@ -906,6 +905,8 @@ static int max3100_probe(struct spi_device *spi) mutex_unlock(&max3100ts_common.max3100ts_lock); return retval; } + + uart_driver_registered = 1; } pdata = max3100_probe_dt(&spi->dev); @@ -1027,6 +1028,7 @@ static void max3100_remove(struct spi_device *spi) pr_debug("removing max3100 driver\n"); uart_unregister_driver(&max3100_uart_driver); + uart_driver_registered = 0; mutex_unlock(&max3100ts_common.max3100ts_lock); } From cf4a414234ab52f7838cb78618e5d64429170feb Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 2 Apr 2024 22:50:30 +0300 Subject: [PATCH 208/244] serial: max3100: Fix bitwise types Sparse is not happy about misuse of bitwise types: .../max3100-ts.c:194:13: warning: incorrect type in assignment (different base types) .../max3100-ts.c:194:13: expected unsigned short [addressable] [usertype] etx .../max3100-ts.c:194:13: got restricted __be16 [usertype] .../max3100-ts.c:202:15: warning: cast to restricted __be16 Fix this by choosing proper types for the respective variables. Fixes: 7831d56b0a35 ("tty: MAX3100") Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20240402195306.269276-4-andriy.shevchenko@linux.intel.com Signed-off-by: Greg Kroah-Hartman --- drivers/tty/serial/max3100-ts.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/max3100-ts.c b/drivers/tty/serial/max3100-ts.c index ee505546526d4..81bc1e4c3afa9 100644 --- a/drivers/tty/serial/max3100-ts.c +++ b/drivers/tty/serial/max3100-ts.c @@ -58,6 +58,10 @@ #include #include #include +#include + +#include + #include #include #include @@ -219,7 +223,7 @@ static void max3100_timeout(struct timer_list *t) static int max3100_sr(struct max3100ts_port *s, u16 tx, u16 * rx) { struct spi_message message; - u16 etx, erx; + __be16 etx, erx; int status; struct spi_transfer tran = { .tx_buf = &etx, From 0ebb9d91ee69dbea6672fb274532f93c9337e219 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 2 Apr 2024 22:50:31 +0300 Subject: [PATCH 209/244] serial: max3100: Make struct plat_max3100 local There is no user of the struct plat_max3100 outside the driver. Inline its contents into the driver. While at it, drop outdated example in the comment. Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20240402195306.269276-5-andriy.shevchenko@linux.intel.com Signed-off-by: Greg Kroah-Hartman --- drivers/tty/serial/max3100-ts.c | 46 +++++++++++++-------------------- 1 file changed, 18 insertions(+), 28 deletions(-) diff --git a/drivers/tty/serial/max3100-ts.c b/drivers/tty/serial/max3100-ts.c index 81bc1e4c3afa9..9574f32532456 100644 --- a/drivers/tty/serial/max3100-ts.c +++ b/drivers/tty/serial/max3100-ts.c @@ -1,6 +1,5 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * * Copyright (C) 2008 Christian Pellegrin * * Notes: the MAX3100 doesn't provide an interrupt on CTS so we have @@ -8,24 +7,6 @@ * writing conf clears FIFO buffer and we cannot have this interrupt * always asking us for attention. * - * Example platform data: - - static struct plat_max3100 max3100_plat_data = { - .loopback = 0, - .crystal = 0, - .poll_time = 100, - }; - - static struct spi_board_info spi_board_info[] = { - { - .modalias = "max3100", - .platform_data = &max3100_plat_data, - .irq = IRQ_EINT12, - .max_speed_hz = 5*1000*1000, - .chip_select = 0, - }, - }; - * The initial minor number is 209 in the low-density serial port: * mknod /dev/ttyMAX0 c 204 209 */ @@ -66,7 +47,24 @@ #include #include -#include +/** + * struct plat_max3100 - MAX3100 SPI UART platform data + * @loopback: force MAX3100 in loopback + * @crystal: 1 for 3.6864 Mhz, 0 for 1.8432 + * @max3100_hw_suspend: MAX3100 has a shutdown pin. This is a hook + * called on suspend and resume to activate it. + * @poll_time: poll time for CTS signal in ms, 0 disables (so no hw + * flow ctrl is possible but you have less CPU usage) + * + * You should use this structure in your machine description to specify + * how the MAX3100 is connected. + */ +struct plat_max3100 { + int loopback; + int crystal; + void (*max3100_hw_suspend) (int suspend); + int poll_time; +}; #define MAX3100_C (1<<14) #define MAX3100_D (0<<14) @@ -152,10 +150,6 @@ struct max3100ts_port { int poll_time; /* and its timer */ struct timer_list timer; - - int tx_fifo_size; - int rx_fifo_size; - }; static struct s_max3100ts_common { @@ -873,10 +867,6 @@ static const struct plat_max3100 *max3100_probe_dt(struct device *dev) of_property_read_u32(node, "crystal", &pdata->crystal); // Poll time in ms, 0 disables CTS, 100 typical of_property_read_u32(node, "poll-time", &pdata->poll_time); - // Size of the Tx FIFO, in bytes - of_property_read_u32(node, "tx-fifo-size", &pdata->tx_fifo_size); - // Size of the Rx FIFO, in bytes - of_property_read_u32(node, "rx-fifo-size", &pdata->rx_fifo_size); return pdata; } From 6d08ca25d5f2c7e298ba5ef6bdb4bfb94020bb0a Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 2 Apr 2024 22:50:41 +0300 Subject: [PATCH 210/244] serial: max3100: Remove unneeded forward declaration There is no code using max3100_work() before the definition of it. Remove unneeded forward declaration. While at it, move max3100_dowork() and max3100_timeout() down in the code to be after actual max3100_work() implementation. Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20240402195306.269276-15-andriy.shevchenko@linux.intel.com Signed-off-by: Greg Kroah-Hartman --- drivers/tty/serial/max3100-ts.c | 34 ++++++++++++++++----------------- 1 file changed, 16 insertions(+), 18 deletions(-) diff --git a/drivers/tty/serial/max3100-ts.c b/drivers/tty/serial/max3100-ts.c index 9574f32532456..53d9fe04b49e7 100644 --- a/drivers/tty/serial/max3100-ts.c +++ b/drivers/tty/serial/max3100-ts.c @@ -196,24 +196,6 @@ static void max3100_calc_parity(struct max3100ts_port *s, u16 * c) *c |= max3100_do_parity(s, *c) << 8; } -static void max3100_port_work(struct work_struct *w); - -static void max3100_schedule_work(struct max3100ts_port *s) -{ - if(!work_pending(&s->work)){ - queue_work(s->workqueue, &s->work); - } -} - -static void max3100_timeout(struct timer_list *t) -{ - struct max3100ts_port *s = from_timer(s, t, timer); - if (s->port.state) { - max3100_schedule_work(s); - mod_timer(&s->timer, jiffies + s->poll_time); - } -} - static int max3100_sr(struct max3100ts_port *s, u16 tx, u16 * rx) { struct spi_message message; @@ -439,6 +421,22 @@ static void max3100_port_work(struct work_struct *w) mutex_unlock(&max3100ts_common.portlock); } +static void max3100_schedule_work(struct max3100ts_port *s) +{ + if(!work_pending(&s->work)){ + queue_work(s->workqueue, &s->work); + } +} + +static void max3100_timeout(struct timer_list *t) +{ + struct max3100ts_port *s = from_timer(s, t, timer); + if (s->port.state) { + max3100_schedule_work(s); + mod_timer(&s->timer, jiffies + s->poll_time); + } +} + /* Threaded handler called in a sleepable context */ static irqreturn_t max3100_thread_irq(int irqno, void *dev_id) { From 3e826e780d2326c6ded9a592b0a8a73d7aafea83 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 9 Apr 2024 17:45:52 +0300 Subject: [PATCH 211/244] serial: max3100: Replace MODULE_ALIAS() with respective ID tables MODULE_ALIAS() in most cases is a pure hack to avoid placing ID tables. Replace it with the respective ID tables. Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20240409144721.638326-6-andriy.shevchenko@linux.intel.com Signed-off-by: Greg Kroah-Hartman --- drivers/tty/serial/max3100-ts.c | 44 +++++++++++++-------------------- 1 file changed, 17 insertions(+), 27 deletions(-) diff --git a/drivers/tty/serial/max3100-ts.c b/drivers/tty/serial/max3100-ts.c index 53d9fe04b49e7..58b356b22be31 100644 --- a/drivers/tty/serial/max3100-ts.c +++ b/drivers/tty/serial/max3100-ts.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include #include @@ -830,31 +831,16 @@ static struct uart_driver max3100_uart_driver = { static int uart_driver_registered; -#ifdef CONFIG_OF -static const struct of_device_id max3100_dt_ids[] = { - {.compatible = "technologic,max3100-ts"}, - {} -}; - -MODULE_DEVICE_TABLE(of, max3100_dt_ids); - static const struct plat_max3100 *max3100_probe_dt(struct device *dev) { struct plat_max3100 *pdata; struct device_node *node = dev->of_node; - const struct of_device_id *match; if (!node) { dev_err(dev, "Device does not have associated DT data\n"); return ERR_PTR(-EINVAL); } - match = of_match_device(max3100_dt_ids, dev); - if (!match) { - dev_err(dev, "Unknown device model\n"); - return ERR_PTR(-EINVAL); - } - pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); if (!pdata) return ERR_PTR(-ENOMEM); @@ -868,16 +854,6 @@ static const struct plat_max3100 *max3100_probe_dt(struct device *dev) return pdata; } -#else - -static const struct plat_max3100 *max3100_probe_dt(struct device *dev) -{ - dev_err(dev, "no platform data defined\n"); - return ERR_PTR(-EINVAL); -} - -#endif - static int max3100_probe(struct spi_device *spi) { int i, retval; @@ -1078,14 +1054,29 @@ static SIMPLE_DEV_PM_OPS(max3100_pm_ops, max3100_suspend, max3100_resume); #define MAX3100_PM_OPS NULL #endif +static const struct spi_device_id max3100ts_spi_id[] = { + { "max3100-ts" }, + { } +}; + +MODULE_DEVICE_TABLE(spi, max3100ts_spi_id); + +static const struct of_device_id max3100ts_of_match[] = { + { .compatible = "technologic,max3100-ts"}, + { } +}; + +MODULE_DEVICE_TABLE(of, max3100ts_of_match); + static struct spi_driver max3100_driver = { .driver = { .name = "max3100-ts", - .owner = THIS_MODULE, + .of_match_table = max3100ts_of_match, .pm = MAX3100_PM_OPS, }, .probe = max3100_probe, .remove = max3100_remove, + .id_table = max3100ts_spi_id, }; module_spi_driver(max3100_driver); @@ -1093,4 +1084,3 @@ module_spi_driver(max3100_driver); MODULE_DESCRIPTION("MAX3100 driver"); MODULE_AUTHOR("Christian Pellegrin "); MODULE_LICENSE("GPL"); -MODULE_ALIAS("spi:max3100"); From a89da144175456b048c1530e6318e011761af20b Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 9 Apr 2024 17:45:53 +0300 Subject: [PATCH 212/244] serial: max3100: Switch to DEFINE_SIMPLE_DEV_PM_OPS() The SIMPLE_DEV_PM_OPS() is deprecated, replace it with the DEFINE_SIMPLE_DEV_PM_OPS() and use pm_sleep_ptr() for setting the driver's PM routines. Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20240409144721.638326-7-andriy.shevchenko@linux.intel.com Signed-off-by: Greg Kroah-Hartman --- drivers/tty/serial/max3100-ts.c | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) diff --git a/drivers/tty/serial/max3100-ts.c b/drivers/tty/serial/max3100-ts.c index 58b356b22be31..f82c9028e2787 100644 --- a/drivers/tty/serial/max3100-ts.c +++ b/drivers/tty/serial/max3100-ts.c @@ -34,6 +34,7 @@ #include #include #include +#include #include #include #include @@ -1001,8 +1002,6 @@ static void max3100_remove(struct spi_device *spi) mutex_unlock(&max3100ts_common.max3100ts_lock); } -#ifdef CONFIG_PM_SLEEP - static int max3100_suspend(struct device *dev) { struct max3100ts_port *s = dev_get_drvdata(dev); @@ -1047,12 +1046,7 @@ static int max3100_resume(struct device *dev) return 0; } -static SIMPLE_DEV_PM_OPS(max3100_pm_ops, max3100_suspend, max3100_resume); -#define MAX3100_PM_OPS (&max3100_pm_ops) - -#else -#define MAX3100_PM_OPS NULL -#endif +static DEFINE_SIMPLE_DEV_PM_OPS(max3100_pm_ops, max3100_suspend, max3100_resume); static const struct spi_device_id max3100ts_spi_id[] = { { "max3100-ts" }, @@ -1070,10 +1064,10 @@ MODULE_DEVICE_TABLE(of, max3100ts_of_match); static struct spi_driver max3100_driver = { .driver = { - .name = "max3100-ts", - .of_match_table = max3100ts_of_match, - .pm = MAX3100_PM_OPS, - }, + .name = "max3100-ts", + .of_match_table = max3100ts_of_match, + .pm = pm_sleep_ptr(&max3100_pm_ops), + }, .probe = max3100_probe, .remove = max3100_remove, .id_table = max3100ts_spi_id, From 78939603846a49332388ccfe0d48946dbd26b2f8 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 9 Apr 2024 17:45:54 +0300 Subject: [PATCH 213/244] serial: max3100: Extract to_max3100_port() helper macro Instead of using container_of() explicitly, introduce a helper macro. This saves a lot of lines of code. Signed-off-by: Andy Shevchenko Reviewed-by: Hugo Villeneuve Link: https://lore.kernel.org/r/20240409144721.638326-8-andriy.shevchenko@linux.intel.com Signed-off-by: Greg Kroah-Hartman --- drivers/tty/serial/max3100-ts.c | 47 ++++++++++----------------------- 1 file changed, 14 insertions(+), 33 deletions(-) diff --git a/drivers/tty/serial/max3100-ts.c b/drivers/tty/serial/max3100-ts.c index f82c9028e2787..7b871acafb157 100644 --- a/drivers/tty/serial/max3100-ts.c +++ b/drivers/tty/serial/max3100-ts.c @@ -29,6 +29,7 @@ */ #define MAX_MAX3100 64 +#include #include #include #include @@ -154,6 +155,8 @@ struct max3100ts_port { struct timer_list timer; }; +#define to_max3100_port(port) container_of(port, struct max3100ts_port, port) + static struct s_max3100ts_common { struct max3100ts_port *max3100ts[MAX_MAX3100]; /* the chip */ struct mutex portlock; /* race on port usage */ @@ -458,9 +461,7 @@ static irqreturn_t max3100_thread_irq(int irqno, void *dev_id) static void max3100_enable_ms(struct uart_port *port) { - struct max3100ts_port *s = container_of(port, - struct max3100ts_port, - port); + struct max3100ts_port *s = to_max3100_port(port); if (s->poll_time > 0) mod_timer(&s->timer, jiffies); @@ -469,9 +470,7 @@ static void max3100_enable_ms(struct uart_port *port) static void max3100_start_tx(struct uart_port *port) { - struct max3100ts_port *s = container_of(port, - struct max3100ts_port, - port); + struct max3100ts_port *s = to_max3100_port(port); dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); @@ -480,9 +479,7 @@ static void max3100_start_tx(struct uart_port *port) static void max3100_stop_rx(struct uart_port *port) { - struct max3100ts_port *s = container_of(port, - struct max3100ts_port, - port); + struct max3100ts_port *s = to_max3100_port(port); dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); @@ -494,9 +491,7 @@ static void max3100_stop_rx(struct uart_port *port) static unsigned int max3100_tx_empty(struct uart_port *port) { - struct max3100ts_port *s = container_of(port, - struct max3100ts_port, - port); + struct max3100ts_port *s = to_max3100_port(port); dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); @@ -507,9 +502,7 @@ static unsigned int max3100_tx_empty(struct uart_port *port) static unsigned int max3100_get_mctrl(struct uart_port *port) { - struct max3100ts_port *s = container_of(port, - struct max3100ts_port, - port); + struct max3100ts_port *s = to_max3100_port(port); dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); @@ -519,9 +512,7 @@ static unsigned int max3100_get_mctrl(struct uart_port *port) static void max3100_set_mctrl(struct uart_port *port, unsigned int mctrl) { - struct max3100ts_port *s = container_of(port, - struct max3100ts_port, - port); + struct max3100ts_port *s = to_max3100_port(port); int rts; dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); @@ -538,9 +529,7 @@ static void max3100_set_termios(struct uart_port *port, struct ktermios *termios, const struct ktermios *old) { - struct max3100ts_port *s = container_of(port, - struct max3100ts_port, - port); + struct max3100ts_port *s = to_max3100_port(port); int baud = 0; unsigned cflag; unsigned long flags; @@ -660,9 +649,7 @@ max3100_set_termios(struct uart_port *port, struct ktermios *termios, static void max3100_shutdown(struct uart_port *port) { - struct max3100ts_port *s = container_of(port, - struct max3100ts_port, - port); + struct max3100ts_port *s = to_max3100_port(port); dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); @@ -698,9 +685,7 @@ static void max3100_shutdown(struct uart_port *port) static int max3100_startup(struct uart_port *port) { - struct max3100ts_port *s = container_of(port, - struct max3100ts_port, - port); + struct max3100ts_port *s = to_max3100_port(port); char b[12]; dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); @@ -748,9 +733,7 @@ static int max3100_startup(struct uart_port *port) static const char *max3100_type(struct uart_port *port) { - struct max3100ts_port *s = container_of(port, - struct max3100ts_port, - port); + struct max3100ts_port *s = to_max3100_port(port); dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); @@ -764,9 +747,7 @@ static void max3100_release_port(struct uart_port *port) static void max3100_config_port(struct uart_port *port, int flags) { - struct max3100ts_port *s = container_of(port, - struct max3100ts_port, - port); + struct max3100ts_port *s = to_max3100_port(port); dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); From ed2f2645c43cca44cccccfd87d6e12166d0d999e Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 9 Apr 2024 17:45:55 +0300 Subject: [PATCH 214/244] serial: max3100: Sort headers Sort the headers in alphabetic order in order to ease the maintenance for this part. Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20240409144721.638326-9-andriy.shevchenko@linux.intel.com Signed-off-by: Greg Kroah-Hartman --- drivers/tty/serial/max3100-ts.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/tty/serial/max3100-ts.c b/drivers/tty/serial/max3100-ts.c index 7b871acafb157..6ddd54528579f 100644 --- a/drivers/tty/serial/max3100-ts.c +++ b/drivers/tty/serial/max3100-ts.c @@ -31,17 +31,17 @@ #include #include -#include #include +#include #include #include #include #include #include +#include #include -#include -#include #include +#include #include #include From dbd0f2af4a4e84d1d364b6dd4c90de75480b9399 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Wed, 10 Apr 2024 17:11:35 +0300 Subject: [PATCH 215/244] serial: max3100: Convert to_max3100_port() to be static inline MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit As Jiri rightfully pointed out the current to_max3100_port() macro implementation is fragile in a sense that it expects the variable name to be port, otherwise it blow up the build. Change this to be static inline to prevent bad compilation. Suggested-by: Jiri Slaby Signed-off-by: Andy Shevchenko Reviewed-by: Ilpo Järvinen Link: https://lore.kernel.org/r/20240410141135.1378948-1-andriy.shevchenko@linux.intel.com Signed-off-by: Greg Kroah-Hartman --- drivers/tty/serial/max3100-ts.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/max3100-ts.c b/drivers/tty/serial/max3100-ts.c index 6ddd54528579f..ecab92bbad8d5 100644 --- a/drivers/tty/serial/max3100-ts.c +++ b/drivers/tty/serial/max3100-ts.c @@ -155,7 +155,10 @@ struct max3100ts_port { struct timer_list timer; }; -#define to_max3100_port(port) container_of(port, struct max3100ts_port, port) +static inline struct max3100ts_port *to_max3100_port(struct uart_port *port) +{ + return container_of(port, struct max3100ts_port, port); +} static struct s_max3100ts_common { struct max3100ts_port *max3100ts[MAX_MAX3100]; /* the chip */ From f6dd3899c7c454946fa0ce41acd65fd62c7ed631 Mon Sep 17 00:00:00 2001 From: Al Viro Date: Tue, 1 Oct 2024 15:35:57 -0400 Subject: [PATCH 216/244] move asm/unaligned.h to linux/unaligned.h asm/unaligned.h is always an include of asm-generic/unaligned.h; might as well move that thing to linux/unaligned.h and include that - there's nothing arch-specific in that header. auto-generated by the following: for i in `git grep -l -w asm/unaligned.h`; do sed -i -e "s/asm\/unaligned.h/linux\/unaligned.h/" $i done for i in `git grep -l -w asm-generic/unaligned.h`; do sed -i -e "s/asm-generic\/unaligned.h/linux\/unaligned.h/" $i done git mv include/asm-generic/unaligned.h include/linux/unaligned.h git mv tools/include/asm-generic/unaligned.h tools/include/linux/unaligned.h sed -i -e "/unaligned.h/d" include/asm-generic/Kbuild sed -i -e "s/__ASM_GENERIC/__LINUX/" include/linux/unaligned.h tools/include/linux/unaligned.h --- drivers/tty/serial/max3100-ts.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/tty/serial/max3100-ts.c b/drivers/tty/serial/max3100-ts.c index ecab92bbad8d5..ef3fe4cd465a9 100644 --- a/drivers/tty/serial/max3100-ts.c +++ b/drivers/tty/serial/max3100-ts.c @@ -44,7 +44,7 @@ #include #include -#include +#include #include #include From c2b9c0f16ef7c109bf74770994fee322845534c1 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Fri, 22 Aug 2025 23:54:50 +0000 Subject: [PATCH 217/244] ARM: configs: tsimx6: updates for 6.18 Adds unused TI wifi driver to force inclusion of CRC7 module that is needed by the external wilc3000 driver. Signed-off-by: Kris Bahnsen --- arch/arm/configs/tsimx6_defconfig | 46 ++++--------------------------- 1 file changed, 6 insertions(+), 40 deletions(-) diff --git a/arch/arm/configs/tsimx6_defconfig b/arch/arm/configs/tsimx6_defconfig index 5d8a10366272a..08c3f97c45e93 100644 --- a/arch/arm/configs/tsimx6_defconfig +++ b/arch/arm/configs/tsimx6_defconfig @@ -54,6 +54,7 @@ CONFIG_PM_DEBUG=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODVERSIONS=y +CONFIG_MODULE_COMPRESS=y CONFIG_MODULE_COMPRESS_XZ=y # CONFIG_MQ_IOSCHED_KYBER is not set CONFIG_BINFMT_MISC=y @@ -200,7 +201,6 @@ CONFIG_NETFILTER_XT_TARGET_NFLOG=m CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m CONFIG_NETFILTER_XT_TARGET_TEE=m CONFIG_NETFILTER_XT_TARGET_TPROXY=m -CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER_XT_TARGET_SECMARK=m CONFIG_NETFILTER_XT_TARGET_TCPMSS=m CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m @@ -296,19 +296,9 @@ CONFIG_IP_NF_MATCH_AH=m CONFIG_IP_NF_MATCH_ECN=m CONFIG_IP_NF_MATCH_RPFILTER=m CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m CONFIG_IP_NF_TARGET_SYNPROXY=m -CONFIG_IP_NF_NAT=m -CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_NETMAP=m -CONFIG_IP_NF_TARGET_REDIRECT=m -CONFIG_IP_NF_MANGLE=m CONFIG_IP_NF_TARGET_ECN=m -CONFIG_IP_NF_TARGET_TTL=m -CONFIG_IP_NF_RAW=m -CONFIG_IP_NF_ARPTABLES=m -CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m CONFIG_NFT_DUP_IPV6=m CONFIG_NFT_FIB_IPV6=m @@ -323,23 +313,14 @@ CONFIG_IP6_NF_MATCH_MH=m CONFIG_IP6_NF_MATCH_RPFILTER=m CONFIG_IP6_NF_MATCH_RT=m CONFIG_IP6_NF_MATCH_SRH=m -CONFIG_IP6_NF_TARGET_HL=m -CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_TARGET_SYNPROXY=m -CONFIG_IP6_NF_MANGLE=m -CONFIG_IP6_NF_RAW=m -CONFIG_IP6_NF_NAT=m -CONFIG_IP6_NF_TARGET_MASQUERADE=m CONFIG_IP6_NF_TARGET_NPT=m CONFIG_NF_TABLES_BRIDGE=m CONFIG_NFT_BRIDGE_META=m CONFIG_NFT_BRIDGE_REJECT=m CONFIG_NF_CONNTRACK_BRIDGE=m CONFIG_BRIDGE_NF_EBTABLES=m -CONFIG_BRIDGE_EBT_BROUTE=m -CONFIG_BRIDGE_EBT_T_FILTER=m -CONFIG_BRIDGE_EBT_T_NAT=m CONFIG_BRIDGE_EBT_802_3=m CONFIG_BRIDGE_EBT_AMONG=m CONFIG_BRIDGE_EBT_ARP=m @@ -357,8 +338,6 @@ CONFIG_BRIDGE_EBT_REDIRECT=m CONFIG_BRIDGE_EBT_SNAT=m CONFIG_BRIDGE_EBT_LOG=m CONFIG_BRIDGE_EBT_NFLOG=m -CONFIG_BPFILTER=y -CONFIG_IP_DCCP=m CONFIG_RDS=m CONFIG_RDS_TCP=m CONFIG_L2TP=m @@ -378,7 +357,6 @@ CONFIG_IEEE802154_6LOWPAN=m CONFIG_MAC802154=m CONFIG_DNS_RESOLVER=y CONFIG_BATMAN_ADV=m -CONFIG_BATMAN_ADV_NC=y CONFIG_OPENVSWITCH=m CONFIG_VSOCKETS=m CONFIG_NETLINK_DIAG=m @@ -395,7 +373,6 @@ CONFIG_BT_BNEP=m CONFIG_BT_BNEP_MC_FILTER=y CONFIG_BT_BNEP_PROTO_FILTER=y CONFIG_BT_HIDP=m -CONFIG_BT_HS=y CONFIG_BT_6LOWPAN=m CONFIG_BT_LEDS=y CONFIG_BT_MSFTEXT=y @@ -614,7 +591,6 @@ CONFIG_BRCMFMAC=m # CONFIG_BRCMFMAC_SDIO is not set CONFIG_BRCMFMAC_USB=y CONFIG_BRCMFMAC_PCIE=y -# CONFIG_WLAN_VENDOR_CISCO is not set CONFIG_IPW2100=m CONFIG_IPW2200=m CONFIG_IWL4965=m @@ -672,8 +648,8 @@ CONFIG_RSI_91X=m # CONFIG_RSI_SDIO is not set # CONFIG_WLAN_VENDOR_ST is not set CONFIG_WL12XX=m +CONFIG_WLCORE_SPI=m CONFIG_WLCORE_SDIO=m -CONFIG_USB_ZD1201=m CONFIG_ZD1211RW=m CONFIG_QTNFMAC_PCIE=m CONFIG_INPUT_MOUSEDEV=m @@ -692,7 +668,6 @@ CONFIG_SERIAL_IMX_CONSOLE=y CONFIG_SERIAL_FSL_LPUART=y CONFIG_SERIAL_FSL_LPUART_CONSOLE=y CONFIG_SERIAL_DEV_BUS=y -# CONFIG_I2C_COMPAT is not set CONFIG_I2C_CHARDEV=y CONFIG_I2C_MUX=y CONFIG_I2C_MUX_GPIO=y @@ -713,7 +688,6 @@ CONFIG_POWER_RESET=y CONFIG_POWER_RESET_SYSCON=y CONFIG_POWER_RESET_SYSCON_POWEROFF=y CONFIG_THERMAL_STATISTICS=y -CONFIG_THERMAL_WRITABLE_TRIPS=y CONFIG_CPU_THERMAL=y CONFIG_IMX_THERMAL=y CONFIG_WATCHDOG=y @@ -754,7 +728,6 @@ CONFIG_SND_IMX_SOC=m CONFIG_SND_SOC_EUKREA_TLV320=m CONFIG_SND_SOC_IMX_ES8328=m CONFIG_SND_SOC_IMX_SGTL5000=m -CONFIG_SND_SOC_IMX_SPDIF=m CONFIG_SND_SOC_FSL_ASOC_CARD=m CONFIG_SND_SIMPLE_CARD=m # CONFIG_HID_A4TECH is not set @@ -887,13 +860,9 @@ CONFIG_PWM_IMX27=y CONFIG_NVMEM_IMX_OCOTP=y CONFIG_NVMEM_SNVS_LPGPR=y CONFIG_MUX_GPIO=m -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT2_FS_POSIX_ACL=y -CONFIG_EXT2_FS_SECURITY=y -CONFIG_EXT3_FS=y -CONFIG_EXT3_FS_POSIX_ACL=y -CONFIG_EXT3_FS_SECURITY=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y CONFIG_F2FS_FS=y CONFIG_F2FS_FS_SECURITY=y CONFIG_QUOTA=y @@ -902,8 +871,7 @@ CONFIG_AUTOFS_FS=m CONFIG_OVERLAY_FS=m CONFIG_VFAT_FS=y CONFIG_EXFAT_FS=y -CONFIG_NTFS_FS=m -CONFIG_NTFS_RW=y +CONFIG_NTFS3_FS=m CONFIG_TMPFS_POSIX_ACL=y CONFIG_CONFIGFS_FS=y # CONFIG_MISC_FILESYSTEMS is not set @@ -925,8 +893,6 @@ CONFIG_CRYPTO_LZO=y CONFIG_CRYPTO_DEV_FSL_CAAM=y CONFIG_CRYPTO_DEV_SAHARA=y CONFIG_CRYPTO_DEV_MXS_DCP=y -CONFIG_CRC_T10DIF=y -CONFIG_CRC7=m CONFIG_CMA_SIZE_MBYTES=64 CONFIG_PRINTK_TIME=y # CONFIG_SYMBOLIC_ERRNAME is not set From 2a2735f7fa06fe7feba162dccc7c9ac36442d34f Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Fri, 22 Aug 2025 23:55:24 +0000 Subject: [PATCH 218/244] ARM: configs: tsimx6_minimal: updates for 6.18 Adds unused TI wifi driver to force inclusion of CRC7 module that is needed by the external wilc3000 driver. Signed-off-by: Kris Bahnsen --- arch/arm/configs/tsimx6_minimal_defconfig | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/arch/arm/configs/tsimx6_minimal_defconfig b/arch/arm/configs/tsimx6_minimal_defconfig index c1f9a7ed48828..8c63d3d92bac4 100644 --- a/arch/arm/configs/tsimx6_minimal_defconfig +++ b/arch/arm/configs/tsimx6_minimal_defconfig @@ -36,6 +36,7 @@ CONFIG_PM=y CONFIG_PM_DEBUG=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_COMPRESS=y CONFIG_MODULE_COMPRESS_XZ=y # CONFIG_MQ_IOSCHED_KYBER is not set CONFIG_BINFMT_MISC=y @@ -182,7 +183,6 @@ CONFIG_ATH10K=m CONFIG_ATH10K_SDIO=m # CONFIG_WLAN_VENDOR_ATMEL is not set # CONFIG_WLAN_VENDOR_BROADCOM is not set -# CONFIG_WLAN_VENDOR_CISCO is not set # CONFIG_WLAN_VENDOR_INTEL is not set # CONFIG_WLAN_VENDOR_INTERSIL is not set # CONFIG_WLAN_VENDOR_MARVELL is not set @@ -193,6 +193,7 @@ CONFIG_ATH10K_SDIO=m # CONFIG_WLAN_VENDOR_RSI is not set # CONFIG_WLAN_VENDOR_ST is not set CONFIG_WL12XX=m +CONFIG_WLCORE_SPI=m CONFIG_WLCORE_SDIO=m # CONFIG_WLAN_VENDOR_ZYDAS is not set # CONFIG_WLAN_VENDOR_QUANTENNA is not set @@ -213,7 +214,6 @@ CONFIG_SERIAL_IMX_CONSOLE=y CONFIG_SERIAL_FSL_LPUART=y CONFIG_SERIAL_FSL_LPUART_CONSOLE=y CONFIG_SERIAL_DEV_BUS=y -# CONFIG_I2C_COMPAT is not set CONFIG_I2C_CHARDEV=y CONFIG_I2C_MUX=y CONFIG_I2C_MUX_GPIO=y @@ -234,7 +234,6 @@ CONFIG_POWER_RESET=y CONFIG_POWER_RESET_SYSCON=y CONFIG_POWER_RESET_SYSCON_POWEROFF=y CONFIG_THERMAL_STATISTICS=y -CONFIG_THERMAL_WRITABLE_TRIPS=y CONFIG_CPU_THERMAL=y CONFIG_IMX_THERMAL=y CONFIG_WATCHDOG=y @@ -274,7 +273,6 @@ CONFIG_SND_IMX_SOC=m CONFIG_SND_SOC_EUKREA_TLV320=m CONFIG_SND_SOC_IMX_ES8328=m CONFIG_SND_SOC_IMX_SGTL5000=m -CONFIG_SND_SOC_IMX_SPDIF=m CONFIG_SND_SOC_FSL_ASOC_CARD=m CONFIG_SND_SIMPLE_CARD=m # CONFIG_HID_A4TECH is not set @@ -286,7 +284,6 @@ CONFIG_SND_SIMPLE_CARD=m # CONFIG_HID_EZKEY is not set # CONFIG_HID_ITE is not set # CONFIG_HID_KENSINGTON is not set -# CONFIG_HID_LOGITECH is not set # CONFIG_HID_REDRAGON is not set # CONFIG_HID_MICROSOFT is not set # CONFIG_HID_MONTEREY is not set @@ -371,11 +368,6 @@ CONFIG_CRYPTO_LZO=y CONFIG_CRYPTO_DEV_FSL_CAAM=y CONFIG_CRYPTO_DEV_SAHARA=y CONFIG_CRYPTO_DEV_MXS_DCP=y -CONFIG_CRC_CCITT=m -CONFIG_CRC_T10DIF=y -CONFIG_CRC_ITU_T=m -CONFIG_CRC7=m -CONFIG_LIBCRC32C=m CONFIG_XZ_DEC=y CONFIG_CMA_SIZE_MBYTES=64 # CONFIG_SYMBOLIC_ERRNAME is not set From 1e05b79d41d7ec8540bbe06f9b78d9b97f8e369f Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Wed, 17 Sep 2025 19:24:39 +0000 Subject: [PATCH 219/244] drivers: mmc: tssdcard: fixes for 6.12.y Signed-off-by: Kris Bahnsen --- drivers/mmc/host/tssdcard.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/mmc/host/tssdcard.c b/drivers/mmc/host/tssdcard.c index 27bdaf84d591b..a889892f5293e 100644 --- a/drivers/mmc/host/tssdcard.c +++ b/drivers/mmc/host/tssdcard.c @@ -88,7 +88,7 @@ struct tssdcard_host { struct tssdcard_dev luns[MAX_SDS]; }; -void tssdcard_debug(void *arg, +static void tssdcard_debug(void *arg, unsigned int code, const char *func, unsigned int line, ...) @@ -424,7 +424,7 @@ static void tssdcard_alloc_disk(struct tssdcard_dev *dev) { dev->bio = dev->biotail = NULL; - dev->gd = blk_alloc_disk(NUMA_NO_NODE); + dev->gd = blk_alloc_disk(NULL, NUMA_NO_NODE); if (dev->gd == NULL) { pr_err(DRIVER_NAME ": Failed to alloc_disk"); return; @@ -432,8 +432,6 @@ static void tssdcard_alloc_disk(struct tssdcard_dev *dev) strcpy(dev->gd->disk_name, dev->devname); - blk_queue_flag_set(QUEUE_FLAG_NONROT, dev->gd->queue); - set_capacity(dev->gd, dev->sectors); dev->gd->flags = 0; dev->gd->fops = &tssdcard_ops; @@ -567,7 +565,7 @@ static int tssdcard_probe(struct platform_device *pdev) return ret; } -static int tssdcard_remove(struct platform_device *pdev) +static void tssdcard_remove(struct platform_device *pdev) { struct tssdcard_host *host = (struct tssdcard_host *)pdev->dev.p; int i; @@ -585,7 +583,6 @@ static int tssdcard_remove(struct platform_device *pdev) kfree(dev->devname); } - return 0; } static const struct platform_device_id tssdcard_devtype[] = { From ab2607d7b35c3ddc55a02a4fdd295e0dab1cad4e Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Thu, 18 Sep 2025 23:26:32 +0000 Subject: [PATCH 220/244] ARM: configs: tsa38x: updates for 6.18 Adds unused TI wifi driver to force inclusion of CRC7 module that is needed by the external wilc3000 driver. Signed-off-by: Kris Bahnsen --- arch/arm/configs/tsa38x_defconfig | 45 +++++-------------------------- 1 file changed, 6 insertions(+), 39 deletions(-) diff --git a/arch/arm/configs/tsa38x_defconfig b/arch/arm/configs/tsa38x_defconfig index e1bb33964d6ef..231122a011fb9 100644 --- a/arch/arm/configs/tsa38x_defconfig +++ b/arch/arm/configs/tsa38x_defconfig @@ -48,6 +48,7 @@ CONFIG_NEON=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODVERSIONS=y +CONFIG_MODULE_COMPRESS=y CONFIG_MODULE_COMPRESS_XZ=y # CONFIG_MQ_IOSCHED_KYBER is not set CONFIG_BINFMT_MISC=y @@ -193,7 +194,6 @@ CONFIG_NETFILTER_XT_TARGET_NFLOG=m CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m CONFIG_NETFILTER_XT_TARGET_TEE=m CONFIG_NETFILTER_XT_TARGET_TPROXY=m -CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER_XT_TARGET_SECMARK=m CONFIG_NETFILTER_XT_TARGET_TCPMSS=m CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m @@ -289,19 +289,9 @@ CONFIG_IP_NF_MATCH_AH=m CONFIG_IP_NF_MATCH_ECN=m CONFIG_IP_NF_MATCH_RPFILTER=m CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m CONFIG_IP_NF_TARGET_SYNPROXY=m -CONFIG_IP_NF_NAT=m -CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_NETMAP=m -CONFIG_IP_NF_TARGET_REDIRECT=m -CONFIG_IP_NF_MANGLE=m CONFIG_IP_NF_TARGET_ECN=m -CONFIG_IP_NF_TARGET_TTL=m -CONFIG_IP_NF_RAW=m -CONFIG_IP_NF_ARPTABLES=m -CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m CONFIG_NFT_DUP_IPV6=m CONFIG_NFT_FIB_IPV6=m @@ -316,23 +306,14 @@ CONFIG_IP6_NF_MATCH_MH=m CONFIG_IP6_NF_MATCH_RPFILTER=m CONFIG_IP6_NF_MATCH_RT=m CONFIG_IP6_NF_MATCH_SRH=m -CONFIG_IP6_NF_TARGET_HL=m -CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_TARGET_SYNPROXY=m -CONFIG_IP6_NF_MANGLE=m -CONFIG_IP6_NF_RAW=m -CONFIG_IP6_NF_NAT=m -CONFIG_IP6_NF_TARGET_MASQUERADE=m CONFIG_IP6_NF_TARGET_NPT=m CONFIG_NF_TABLES_BRIDGE=m CONFIG_NFT_BRIDGE_META=m CONFIG_NFT_BRIDGE_REJECT=m CONFIG_NF_CONNTRACK_BRIDGE=m CONFIG_BRIDGE_NF_EBTABLES=m -CONFIG_BRIDGE_EBT_BROUTE=m -CONFIG_BRIDGE_EBT_T_FILTER=m -CONFIG_BRIDGE_EBT_T_NAT=m CONFIG_BRIDGE_EBT_802_3=m CONFIG_BRIDGE_EBT_AMONG=m CONFIG_BRIDGE_EBT_ARP=m @@ -350,8 +331,6 @@ CONFIG_BRIDGE_EBT_REDIRECT=m CONFIG_BRIDGE_EBT_SNAT=m CONFIG_BRIDGE_EBT_LOG=m CONFIG_BRIDGE_EBT_NFLOG=m -CONFIG_BPFILTER=y -CONFIG_IP_DCCP=m CONFIG_RDS=m CONFIG_RDS_TCP=m CONFIG_L2TP=m @@ -372,7 +351,6 @@ CONFIG_IEEE802154_6LOWPAN=m CONFIG_MAC802154=m CONFIG_DNS_RESOLVER=y CONFIG_BATMAN_ADV=m -CONFIG_BATMAN_ADV_NC=y CONFIG_OPENVSWITCH=m CONFIG_VSOCKETS=m CONFIG_NETLINK_DIAG=m @@ -389,7 +367,6 @@ CONFIG_BT_BNEP=m CONFIG_BT_BNEP_MC_FILTER=y CONFIG_BT_BNEP_PROTO_FILTER=y CONFIG_BT_HIDP=m -CONFIG_BT_HS=y CONFIG_BT_6LOWPAN=m CONFIG_BT_LEDS=y CONFIG_BT_MSFTEXT=y @@ -591,7 +568,6 @@ CONFIG_BRCMFMAC=m # CONFIG_BRCMFMAC_SDIO is not set CONFIG_BRCMFMAC_USB=y CONFIG_BRCMFMAC_PCIE=y -# CONFIG_WLAN_VENDOR_CISCO is not set CONFIG_IPW2100=m CONFIG_IPW2200=m CONFIG_IWL4965=m @@ -643,8 +619,7 @@ CONFIG_RTW88_8821CE=m CONFIG_RSI_91X=m # CONFIG_RSI_SDIO is not set # CONFIG_WLAN_VENDOR_ST is not set -# CONFIG_WLAN_VENDOR_TI is not set -CONFIG_USB_ZD1201=m +CONFIG_WL1251=m CONFIG_ZD1211RW=m CONFIG_QTNFMAC_PCIE=m # CONFIG_INPUT_KEYBOARD is not set @@ -678,7 +653,6 @@ CONFIG_PTP_1588_CLOCK=m CONFIG_GPIO_SYSFS=y CONFIG_GPIO_PCA953X=y CONFIG_GPIO_TS7800V2=y -CONFIG_GPIO_TS7820=y CONFIG_POWER_RESET=y CONFIG_POWER_RESET_GPIO=y CONFIG_POWER_SUPPLY=y @@ -798,13 +772,9 @@ CONFIG_PWM_TS=m CONFIG_PHY_MVEBU_A38X_COMPHY=y CONFIG_MUX_GPIO=m CONFIG_SLIMBUS=m -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT2_FS_POSIX_ACL=y -CONFIG_EXT2_FS_SECURITY=y -CONFIG_EXT3_FS=y -CONFIG_EXT3_FS_POSIX_ACL=y -CONFIG_EXT3_FS_SECURITY=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y CONFIG_F2FS_FS=y CONFIG_F2FS_FS_SECURITY=y CONFIG_AUTOFS_FS=m @@ -812,8 +782,7 @@ CONFIG_OVERLAY_FS=m CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y CONFIG_EXFAT_FS=y -CONFIG_NTFS_FS=m -CONFIG_NTFS_RW=y +CONFIG_NTFS3_FS=m CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y # CONFIG_MISC_FILESYSTEMS is not set @@ -827,14 +796,12 @@ CONFIG_NLS_ISO8859_2=y CONFIG_NLS_UTF8=y CONFIG_CRYPTO_ECDH=y CONFIG_CRYPTO_AES=y -CONFIG_CRYPTO_ECB=y CONFIG_CRYPTO_GCM=y CONFIG_CRYPTO_CMAC=y CONFIG_CRYPTO_DEFLATE=y CONFIG_CRYPTO_LZO=y CONFIG_CRYPTO_ZSTD=y CONFIG_CRYPTO_DEV_MARVELL_CESA=y -CONFIG_CRC7=m CONFIG_PRINTK_TIME=y # CONFIG_DEBUG_MISC is not set CONFIG_DEBUG_FS=y From e8a168db154d201387c9f67e9b1388761194ae67 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Thu, 18 Sep 2025 23:30:24 +0000 Subject: [PATCH 221/244] ARM: configs: tsa38x_minimal: updates for 6.18 Adds unused TI wifi driver to force inclusion of CRC7 module that is needed by the external wilc3000 driver. Signed-off-by: Kris Bahnsen --- arch/arm/configs/tsa38x_minimal_defconfig | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/arch/arm/configs/tsa38x_minimal_defconfig b/arch/arm/configs/tsa38x_minimal_defconfig index 4d35aca8fbe52..e7678922fc385 100644 --- a/arch/arm/configs/tsa38x_minimal_defconfig +++ b/arch/arm/configs/tsa38x_minimal_defconfig @@ -31,6 +31,7 @@ CONFIG_VFP=y CONFIG_NEON=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_COMPRESS=y CONFIG_MODULE_COMPRESS_XZ=y # CONFIG_MQ_IOSCHED_KYBER is not set CONFIG_BINFMT_MISC=y @@ -157,7 +158,6 @@ CONFIG_USB_NET_SMSC95XX=m # CONFIG_WLAN_VENDOR_ATH is not set # CONFIG_WLAN_VENDOR_ATMEL is not set # CONFIG_WLAN_VENDOR_BROADCOM is not set -# CONFIG_WLAN_VENDOR_CISCO is not set # CONFIG_WLAN_VENDOR_INTEL is not set # CONFIG_WLAN_VENDOR_INTERSIL is not set # CONFIG_WLAN_VENDOR_MARVELL is not set @@ -167,7 +167,7 @@ CONFIG_USB_NET_SMSC95XX=m # CONFIG_WLAN_VENDOR_REALTEK is not set # CONFIG_WLAN_VENDOR_RSI is not set # CONFIG_WLAN_VENDOR_ST is not set -# CONFIG_WLAN_VENDOR_TI is not set +CONFIG_WL1251=m # CONFIG_WLAN_VENDOR_ZYDAS is not set # CONFIG_WLAN_VENDOR_QUANTENNA is not set # CONFIG_INPUT_KEYBOARD is not set @@ -200,7 +200,6 @@ CONFIG_PTP_1588_CLOCK=m CONFIG_GPIO_SYSFS=y CONFIG_GPIO_PCA953X=y CONFIG_GPIO_TS7800V2=y -CONFIG_GPIO_TS7820=y CONFIG_POWER_RESET=y CONFIG_POWER_RESET_GPIO=y CONFIG_POWER_SUPPLY=y @@ -255,6 +254,7 @@ CONFIG_PHY_MVEBU_A38X_COMPHY=y CONFIG_MUX_GPIO=m CONFIG_SLIMBUS=m CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y CONFIG_TMPFS=y @@ -268,14 +268,11 @@ CONFIG_NLS_ISO8859_2=y CONFIG_NLS_UTF8=y CONFIG_CRYPTO_ECDH=y CONFIG_CRYPTO_AES=y -CONFIG_CRYPTO_ECB=y CONFIG_CRYPTO_CMAC=y CONFIG_CRYPTO_DEFLATE=y CONFIG_CRYPTO_LZO=y CONFIG_CRYPTO_ZSTD=y CONFIG_CRYPTO_DEV_MARVELL_CESA=y -CONFIG_CRC_ITU_T=m -CONFIG_CRC7=m # CONFIG_DEBUG_MISC is not set # CONFIG_SLUB_DEBUG is not set # CONFIG_FTRACE is not set From 4362aed7fb81f868f8126cc319e0aaeebf3290ea Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Thu, 18 Sep 2025 23:32:26 +0000 Subject: [PATCH 222/244] ARM: dts: marvell: armada-385: ts7800v2: remove dead SPI node Originally used in production, no longer needed or used Signed-off-by: Kris Bahnsen --- arch/arm/boot/dts/marvell/armada-385-ts7800-v2.dts | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/arm/boot/dts/marvell/armada-385-ts7800-v2.dts b/arch/arm/boot/dts/marvell/armada-385-ts7800-v2.dts index bbea310e8e90f..2a147cb077078 100644 --- a/arch/arm/boot/dts/marvell/armada-385-ts7800-v2.dts +++ b/arch/arm/boot/dts/marvell/armada-385-ts7800-v2.dts @@ -444,12 +444,6 @@ num-cs = <5>; cs-gpios = <0>, <0>, <0>, <0>, <&gpio0 28 GPIO_ACTIVE_LOW>; - offboard_flash: flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - wilc: wifi@3 { compatible = "microchip,wilc3000"; reg = <3>; From 7a7c6912e2c744a36b2432911148500b0adeb662 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Mon, 22 Sep 2025 23:31:49 +0000 Subject: [PATCH 223/244] Revert "move asm/unaligned.h to linux/unaligned.h" This reverts commit cfa2fe73b025e4eabf60f152af1624d7aa3bad9d. --- drivers/tty/serial/max3100-ts.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/tty/serial/max3100-ts.c b/drivers/tty/serial/max3100-ts.c index ef3fe4cd465a9..ecab92bbad8d5 100644 --- a/drivers/tty/serial/max3100-ts.c +++ b/drivers/tty/serial/max3100-ts.c @@ -44,7 +44,7 @@ #include #include -#include +#include #include #include From 6aaa5e8279d74aad63c204683f154274663dafc5 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Mon, 22 Sep 2025 23:31:49 +0000 Subject: [PATCH 224/244] Revert "serial: max3100: Convert to_max3100_port() to be static inline" This reverts commit abb540f27a1c9356435975201b8cd9df1ac16741. --- drivers/tty/serial/max3100-ts.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/tty/serial/max3100-ts.c b/drivers/tty/serial/max3100-ts.c index ecab92bbad8d5..6ddd54528579f 100644 --- a/drivers/tty/serial/max3100-ts.c +++ b/drivers/tty/serial/max3100-ts.c @@ -155,10 +155,7 @@ struct max3100ts_port { struct timer_list timer; }; -static inline struct max3100ts_port *to_max3100_port(struct uart_port *port) -{ - return container_of(port, struct max3100ts_port, port); -} +#define to_max3100_port(port) container_of(port, struct max3100ts_port, port) static struct s_max3100ts_common { struct max3100ts_port *max3100ts[MAX_MAX3100]; /* the chip */ From 7e7d5e4078ed48f5a8be86c30022674f113bfe31 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Mon, 22 Sep 2025 23:31:49 +0000 Subject: [PATCH 225/244] Revert "serial: max3100: Sort headers" This reverts commit 5d6113b99ff98c22b373dfc749575b08b0e71d67. --- drivers/tty/serial/max3100-ts.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/tty/serial/max3100-ts.c b/drivers/tty/serial/max3100-ts.c index 6ddd54528579f..7b871acafb157 100644 --- a/drivers/tty/serial/max3100-ts.c +++ b/drivers/tty/serial/max3100-ts.c @@ -31,17 +31,17 @@ #include #include +#include #include -#include #include #include #include #include #include -#include #include -#include +#include #include +#include #include #include From 3128bb3491ce4e82d9e693c7d69fff3856ca0fb1 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Mon, 22 Sep 2025 23:31:49 +0000 Subject: [PATCH 226/244] Revert "serial: max3100: Extract to_max3100_port() helper macro" This reverts commit dcac30f8f97aef076a359dd27f43ca3cebc9b601. --- drivers/tty/serial/max3100-ts.c | 47 +++++++++++++++++++++++---------- 1 file changed, 33 insertions(+), 14 deletions(-) diff --git a/drivers/tty/serial/max3100-ts.c b/drivers/tty/serial/max3100-ts.c index 7b871acafb157..f82c9028e2787 100644 --- a/drivers/tty/serial/max3100-ts.c +++ b/drivers/tty/serial/max3100-ts.c @@ -29,7 +29,6 @@ */ #define MAX_MAX3100 64 -#include #include #include #include @@ -155,8 +154,6 @@ struct max3100ts_port { struct timer_list timer; }; -#define to_max3100_port(port) container_of(port, struct max3100ts_port, port) - static struct s_max3100ts_common { struct max3100ts_port *max3100ts[MAX_MAX3100]; /* the chip */ struct mutex portlock; /* race on port usage */ @@ -461,7 +458,9 @@ static irqreturn_t max3100_thread_irq(int irqno, void *dev_id) static void max3100_enable_ms(struct uart_port *port) { - struct max3100ts_port *s = to_max3100_port(port); + struct max3100ts_port *s = container_of(port, + struct max3100ts_port, + port); if (s->poll_time > 0) mod_timer(&s->timer, jiffies); @@ -470,7 +469,9 @@ static void max3100_enable_ms(struct uart_port *port) static void max3100_start_tx(struct uart_port *port) { - struct max3100ts_port *s = to_max3100_port(port); + struct max3100ts_port *s = container_of(port, + struct max3100ts_port, + port); dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); @@ -479,7 +480,9 @@ static void max3100_start_tx(struct uart_port *port) static void max3100_stop_rx(struct uart_port *port) { - struct max3100ts_port *s = to_max3100_port(port); + struct max3100ts_port *s = container_of(port, + struct max3100ts_port, + port); dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); @@ -491,7 +494,9 @@ static void max3100_stop_rx(struct uart_port *port) static unsigned int max3100_tx_empty(struct uart_port *port) { - struct max3100ts_port *s = to_max3100_port(port); + struct max3100ts_port *s = container_of(port, + struct max3100ts_port, + port); dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); @@ -502,7 +507,9 @@ static unsigned int max3100_tx_empty(struct uart_port *port) static unsigned int max3100_get_mctrl(struct uart_port *port) { - struct max3100ts_port *s = to_max3100_port(port); + struct max3100ts_port *s = container_of(port, + struct max3100ts_port, + port); dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); @@ -512,7 +519,9 @@ static unsigned int max3100_get_mctrl(struct uart_port *port) static void max3100_set_mctrl(struct uart_port *port, unsigned int mctrl) { - struct max3100ts_port *s = to_max3100_port(port); + struct max3100ts_port *s = container_of(port, + struct max3100ts_port, + port); int rts; dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); @@ -529,7 +538,9 @@ static void max3100_set_termios(struct uart_port *port, struct ktermios *termios, const struct ktermios *old) { - struct max3100ts_port *s = to_max3100_port(port); + struct max3100ts_port *s = container_of(port, + struct max3100ts_port, + port); int baud = 0; unsigned cflag; unsigned long flags; @@ -649,7 +660,9 @@ max3100_set_termios(struct uart_port *port, struct ktermios *termios, static void max3100_shutdown(struct uart_port *port) { - struct max3100ts_port *s = to_max3100_port(port); + struct max3100ts_port *s = container_of(port, + struct max3100ts_port, + port); dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); @@ -685,7 +698,9 @@ static void max3100_shutdown(struct uart_port *port) static int max3100_startup(struct uart_port *port) { - struct max3100ts_port *s = to_max3100_port(port); + struct max3100ts_port *s = container_of(port, + struct max3100ts_port, + port); char b[12]; dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); @@ -733,7 +748,9 @@ static int max3100_startup(struct uart_port *port) static const char *max3100_type(struct uart_port *port) { - struct max3100ts_port *s = to_max3100_port(port); + struct max3100ts_port *s = container_of(port, + struct max3100ts_port, + port); dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); @@ -747,7 +764,9 @@ static void max3100_release_port(struct uart_port *port) static void max3100_config_port(struct uart_port *port, int flags) { - struct max3100ts_port *s = to_max3100_port(port); + struct max3100ts_port *s = container_of(port, + struct max3100ts_port, + port); dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); From fb2485702860abd6f584ff1c4e15e10d3b0c3302 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Mon, 22 Sep 2025 23:31:49 +0000 Subject: [PATCH 227/244] Revert "serial: max3100: Switch to DEFINE_SIMPLE_DEV_PM_OPS()" This reverts commit 907dbc5f41b1bf1b6e4f4cd231a1d0bc284dbc32. --- drivers/tty/serial/max3100-ts.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/tty/serial/max3100-ts.c b/drivers/tty/serial/max3100-ts.c index f82c9028e2787..58b356b22be31 100644 --- a/drivers/tty/serial/max3100-ts.c +++ b/drivers/tty/serial/max3100-ts.c @@ -34,7 +34,6 @@ #include #include #include -#include #include #include #include @@ -1002,6 +1001,8 @@ static void max3100_remove(struct spi_device *spi) mutex_unlock(&max3100ts_common.max3100ts_lock); } +#ifdef CONFIG_PM_SLEEP + static int max3100_suspend(struct device *dev) { struct max3100ts_port *s = dev_get_drvdata(dev); @@ -1046,7 +1047,12 @@ static int max3100_resume(struct device *dev) return 0; } -static DEFINE_SIMPLE_DEV_PM_OPS(max3100_pm_ops, max3100_suspend, max3100_resume); +static SIMPLE_DEV_PM_OPS(max3100_pm_ops, max3100_suspend, max3100_resume); +#define MAX3100_PM_OPS (&max3100_pm_ops) + +#else +#define MAX3100_PM_OPS NULL +#endif static const struct spi_device_id max3100ts_spi_id[] = { { "max3100-ts" }, @@ -1064,10 +1070,10 @@ MODULE_DEVICE_TABLE(of, max3100ts_of_match); static struct spi_driver max3100_driver = { .driver = { - .name = "max3100-ts", - .of_match_table = max3100ts_of_match, - .pm = pm_sleep_ptr(&max3100_pm_ops), - }, + .name = "max3100-ts", + .of_match_table = max3100ts_of_match, + .pm = MAX3100_PM_OPS, + }, .probe = max3100_probe, .remove = max3100_remove, .id_table = max3100ts_spi_id, From dde3f1e5a298336a2d55858ae06034c6785573c6 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Mon, 22 Sep 2025 23:31:49 +0000 Subject: [PATCH 228/244] Revert "serial: max3100: Replace MODULE_ALIAS() with respective ID tables" This reverts commit cfe3c2ba2d2c2bb6f2369a06b4a13c60c3172f02. --- drivers/tty/serial/max3100-ts.c | 44 ++++++++++++++++++++------------- 1 file changed, 27 insertions(+), 17 deletions(-) diff --git a/drivers/tty/serial/max3100-ts.c b/drivers/tty/serial/max3100-ts.c index 58b356b22be31..53d9fe04b49e7 100644 --- a/drivers/tty/serial/max3100-ts.c +++ b/drivers/tty/serial/max3100-ts.c @@ -32,7 +32,6 @@ #include #include #include -#include #include #include #include @@ -831,16 +830,31 @@ static struct uart_driver max3100_uart_driver = { static int uart_driver_registered; +#ifdef CONFIG_OF +static const struct of_device_id max3100_dt_ids[] = { + {.compatible = "technologic,max3100-ts"}, + {} +}; + +MODULE_DEVICE_TABLE(of, max3100_dt_ids); + static const struct plat_max3100 *max3100_probe_dt(struct device *dev) { struct plat_max3100 *pdata; struct device_node *node = dev->of_node; + const struct of_device_id *match; if (!node) { dev_err(dev, "Device does not have associated DT data\n"); return ERR_PTR(-EINVAL); } + match = of_match_device(max3100_dt_ids, dev); + if (!match) { + dev_err(dev, "Unknown device model\n"); + return ERR_PTR(-EINVAL); + } + pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); if (!pdata) return ERR_PTR(-ENOMEM); @@ -854,6 +868,16 @@ static const struct plat_max3100 *max3100_probe_dt(struct device *dev) return pdata; } +#else + +static const struct plat_max3100 *max3100_probe_dt(struct device *dev) +{ + dev_err(dev, "no platform data defined\n"); + return ERR_PTR(-EINVAL); +} + +#endif + static int max3100_probe(struct spi_device *spi) { int i, retval; @@ -1054,29 +1078,14 @@ static SIMPLE_DEV_PM_OPS(max3100_pm_ops, max3100_suspend, max3100_resume); #define MAX3100_PM_OPS NULL #endif -static const struct spi_device_id max3100ts_spi_id[] = { - { "max3100-ts" }, - { } -}; - -MODULE_DEVICE_TABLE(spi, max3100ts_spi_id); - -static const struct of_device_id max3100ts_of_match[] = { - { .compatible = "technologic,max3100-ts"}, - { } -}; - -MODULE_DEVICE_TABLE(of, max3100ts_of_match); - static struct spi_driver max3100_driver = { .driver = { .name = "max3100-ts", - .of_match_table = max3100ts_of_match, + .owner = THIS_MODULE, .pm = MAX3100_PM_OPS, }, .probe = max3100_probe, .remove = max3100_remove, - .id_table = max3100ts_spi_id, }; module_spi_driver(max3100_driver); @@ -1084,3 +1093,4 @@ module_spi_driver(max3100_driver); MODULE_DESCRIPTION("MAX3100 driver"); MODULE_AUTHOR("Christian Pellegrin "); MODULE_LICENSE("GPL"); +MODULE_ALIAS("spi:max3100"); From fca638d04b45167a9fe80b4771e34329e892cb65 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Mon, 22 Sep 2025 23:31:50 +0000 Subject: [PATCH 229/244] Revert "serial: max3100: Remove unneeded forward declaration" This reverts commit bfa4e78aba18aed5a03e47af29d65fd171c34423. --- drivers/tty/serial/max3100-ts.c | 34 +++++++++++++++++---------------- 1 file changed, 18 insertions(+), 16 deletions(-) diff --git a/drivers/tty/serial/max3100-ts.c b/drivers/tty/serial/max3100-ts.c index 53d9fe04b49e7..9574f32532456 100644 --- a/drivers/tty/serial/max3100-ts.c +++ b/drivers/tty/serial/max3100-ts.c @@ -196,6 +196,24 @@ static void max3100_calc_parity(struct max3100ts_port *s, u16 * c) *c |= max3100_do_parity(s, *c) << 8; } +static void max3100_port_work(struct work_struct *w); + +static void max3100_schedule_work(struct max3100ts_port *s) +{ + if(!work_pending(&s->work)){ + queue_work(s->workqueue, &s->work); + } +} + +static void max3100_timeout(struct timer_list *t) +{ + struct max3100ts_port *s = from_timer(s, t, timer); + if (s->port.state) { + max3100_schedule_work(s); + mod_timer(&s->timer, jiffies + s->poll_time); + } +} + static int max3100_sr(struct max3100ts_port *s, u16 tx, u16 * rx) { struct spi_message message; @@ -421,22 +439,6 @@ static void max3100_port_work(struct work_struct *w) mutex_unlock(&max3100ts_common.portlock); } -static void max3100_schedule_work(struct max3100ts_port *s) -{ - if(!work_pending(&s->work)){ - queue_work(s->workqueue, &s->work); - } -} - -static void max3100_timeout(struct timer_list *t) -{ - struct max3100ts_port *s = from_timer(s, t, timer); - if (s->port.state) { - max3100_schedule_work(s); - mod_timer(&s->timer, jiffies + s->poll_time); - } -} - /* Threaded handler called in a sleepable context */ static irqreturn_t max3100_thread_irq(int irqno, void *dev_id) { From 659a0e455a8a0315fc00a960c2aa8f22ca3ebd95 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Mon, 22 Sep 2025 23:31:50 +0000 Subject: [PATCH 230/244] Revert "serial: max3100: Make struct plat_max3100 local" This reverts commit 52b10a8b173a88d0d8a1cbbeba26d387a04d1a74. --- drivers/tty/serial/max3100-ts.c | 46 ++++++++++++++++++++------------- 1 file changed, 28 insertions(+), 18 deletions(-) diff --git a/drivers/tty/serial/max3100-ts.c b/drivers/tty/serial/max3100-ts.c index 9574f32532456..81bc1e4c3afa9 100644 --- a/drivers/tty/serial/max3100-ts.c +++ b/drivers/tty/serial/max3100-ts.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* + * * Copyright (C) 2008 Christian Pellegrin * * Notes: the MAX3100 doesn't provide an interrupt on CTS so we have @@ -7,6 +8,24 @@ * writing conf clears FIFO buffer and we cannot have this interrupt * always asking us for attention. * + * Example platform data: + + static struct plat_max3100 max3100_plat_data = { + .loopback = 0, + .crystal = 0, + .poll_time = 100, + }; + + static struct spi_board_info spi_board_info[] = { + { + .modalias = "max3100", + .platform_data = &max3100_plat_data, + .irq = IRQ_EINT12, + .max_speed_hz = 5*1000*1000, + .chip_select = 0, + }, + }; + * The initial minor number is 209 in the low-density serial port: * mknod /dev/ttyMAX0 c 204 209 */ @@ -47,24 +66,7 @@ #include #include -/** - * struct plat_max3100 - MAX3100 SPI UART platform data - * @loopback: force MAX3100 in loopback - * @crystal: 1 for 3.6864 Mhz, 0 for 1.8432 - * @max3100_hw_suspend: MAX3100 has a shutdown pin. This is a hook - * called on suspend and resume to activate it. - * @poll_time: poll time for CTS signal in ms, 0 disables (so no hw - * flow ctrl is possible but you have less CPU usage) - * - * You should use this structure in your machine description to specify - * how the MAX3100 is connected. - */ -struct plat_max3100 { - int loopback; - int crystal; - void (*max3100_hw_suspend) (int suspend); - int poll_time; -}; +#include #define MAX3100_C (1<<14) #define MAX3100_D (0<<14) @@ -150,6 +152,10 @@ struct max3100ts_port { int poll_time; /* and its timer */ struct timer_list timer; + + int tx_fifo_size; + int rx_fifo_size; + }; static struct s_max3100ts_common { @@ -867,6 +873,10 @@ static const struct plat_max3100 *max3100_probe_dt(struct device *dev) of_property_read_u32(node, "crystal", &pdata->crystal); // Poll time in ms, 0 disables CTS, 100 typical of_property_read_u32(node, "poll-time", &pdata->poll_time); + // Size of the Tx FIFO, in bytes + of_property_read_u32(node, "tx-fifo-size", &pdata->tx_fifo_size); + // Size of the Rx FIFO, in bytes + of_property_read_u32(node, "rx-fifo-size", &pdata->rx_fifo_size); return pdata; } From 0d2b0dd69fc9c2ea66238d6a482f3fddbaa740b6 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Mon, 22 Sep 2025 23:31:50 +0000 Subject: [PATCH 231/244] Revert "serial: max3100: Fix bitwise types" This reverts commit 97e96517733b8401618b41221343d9d7337332e9. --- drivers/tty/serial/max3100-ts.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/tty/serial/max3100-ts.c b/drivers/tty/serial/max3100-ts.c index 81bc1e4c3afa9..ee505546526d4 100644 --- a/drivers/tty/serial/max3100-ts.c +++ b/drivers/tty/serial/max3100-ts.c @@ -58,10 +58,6 @@ #include #include #include -#include - -#include - #include #include #include @@ -223,7 +219,7 @@ static void max3100_timeout(struct timer_list *t) static int max3100_sr(struct max3100ts_port *s, u16 tx, u16 * rx) { struct spi_message message; - __be16 etx, erx; + u16 etx, erx; int status; struct spi_transfer tran = { .tx_buf = &etx, From 306d8b33c16a012584c987cb39cac80996124aa7 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Mon, 22 Sep 2025 23:31:50 +0000 Subject: [PATCH 232/244] Revert "serial: max3100: Update uart_driver_registered on driver removal" This reverts commit 4763c9176b6b35fb0887bef81d2c9379c2b016d0. --- drivers/tty/serial/max3100-ts.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/tty/serial/max3100-ts.c b/drivers/tty/serial/max3100-ts.c index ee505546526d4..8e42c5bbd4f6a 100644 --- a/drivers/tty/serial/max3100-ts.c +++ b/drivers/tty/serial/max3100-ts.c @@ -898,6 +898,7 @@ static int max3100_probe(struct spi_device *spi) mutex_lock(&max3100ts_common.max3100ts_lock); if (!uart_driver_registered) { + uart_driver_registered = 1; retval = uart_register_driver(&max3100_uart_driver); if (retval) { printk(KERN_ERR @@ -905,8 +906,6 @@ static int max3100_probe(struct spi_device *spi) mutex_unlock(&max3100ts_common.max3100ts_lock); return retval; } - - uart_driver_registered = 1; } pdata = max3100_probe_dt(&spi->dev); @@ -1028,7 +1027,6 @@ static void max3100_remove(struct spi_device *spi) pr_debug("removing max3100 driver\n"); uart_unregister_driver(&max3100_uart_driver); - uart_driver_registered = 0; mutex_unlock(&max3100ts_common.max3100ts_lock); } From 930814868b7219e567bb9a96b3c09fcb2a149906 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Mon, 22 Sep 2025 23:31:50 +0000 Subject: [PATCH 233/244] Revert "serial: max3100: Lock port->lock when calling uart_handle_cts_change()" This reverts commit 7ff648e4b6bd5493884a4648a96d15f540956662. --- drivers/tty/serial/max3100-ts.c | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/drivers/tty/serial/max3100-ts.c b/drivers/tty/serial/max3100-ts.c index 8e42c5bbd4f6a..6b75574461fb0 100644 --- a/drivers/tty/serial/max3100-ts.c +++ b/drivers/tty/serial/max3100-ts.c @@ -268,7 +268,7 @@ static int max3100_sr(struct max3100ts_port *s, u16 tx, u16 * rx) return 0; } -static int max3100_handlerx_unlocked(struct max3100ts_port *s, u16 rx) +static int max3100_handlerx(struct max3100ts_port *s, u16 rx) { unsigned int ch, flg, status = 0; int ret = 0, cts; @@ -315,17 +315,6 @@ static int max3100_handlerx_unlocked(struct max3100ts_port *s, u16 rx) return ret; } -static int max3100_handlerx(struct max3100ts_port *s, u16 rx) -{ - unsigned long flags; - int ret; - - uart_port_lock_irqsave(&s->port, &flags); - ret = max3100_handlerx_unlocked(s, rx); - uart_port_unlock_irqrestore(&s->port, flags); - return ret; -} - static void max3100_port_dowork(struct max3100ts_port *s) { struct tty_port *tport = &s->port.state->port; From e9bb97d4d2b8e72697fe37e0aa22a2db43f9d67e Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Mon, 22 Sep 2025 23:31:50 +0000 Subject: [PATCH 234/244] Revert "tty: serial: switch from circ_buf to kfifo" This reverts commit 480423fa68e92336780a6c625a14115fe1189e7f. --- drivers/tty/serial/max3100-ts.c | 20 ++++++++------------ 1 file changed, 8 insertions(+), 12 deletions(-) diff --git a/drivers/tty/serial/max3100-ts.c b/drivers/tty/serial/max3100-ts.c index 6b75574461fb0..c908ac6df8ac9 100644 --- a/drivers/tty/serial/max3100-ts.c +++ b/drivers/tty/serial/max3100-ts.c @@ -317,12 +317,11 @@ static int max3100_handlerx(struct max3100ts_port *s, u16 rx) static void max3100_port_dowork(struct max3100ts_port *s) { - struct tty_port *tport = &s->port.state->port; - unsigned char ch; int rxchars, x; u16 tx, rx; int conf, cconf, crts; unsigned long flags; + struct circ_buf *xmit = &s->port.state->xmit; dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); @@ -352,18 +351,14 @@ static void max3100_port_dowork(struct max3100ts_port *s) x = 0; /* Lock in case we need to call uart_circ_empty() */ - /* XXX: Does this mean we need to actually use the UART port lock - * rather than our own locking? - */ spin_lock_irqsave(&s->port.lock, flags); if (s->port.x_char) { tx = s->port.x_char; x = 1; - } else { + } else{ if(!s->force_end_work){ - if (!uart_tx_stopped(&s->port) && - uart_fifo_get(&s->port, &ch)) { - tx = ch; + if (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) { + tx = xmit->buf[xmit->tail]; x = 2; } } @@ -382,6 +377,8 @@ static void max3100_port_dowork(struct max3100ts_port *s) s->port.icount.tx++; s->port.x_char = 0; } else if (x == 2) { + xmit->tail = (xmit->tail + 1) & + (UART_XMIT_SIZE - 1); s->port.icount.tx++; } spin_unlock_irqrestore(&s->port.lock, flags); @@ -405,7 +402,7 @@ static void max3100_port_dowork(struct max3100ts_port *s) * number of acquisitions for a bit of a performance gain. */ spin_lock_irqsave(&s->port.lock, flags); - if (kfifo_len(&tport->xmit_fifo) < 4){ + if (uart_circ_chars_pending(xmit) < 4){ if(s->port.state->port.tty) uart_write_wakeup(&s->port); } @@ -413,8 +410,7 @@ static void max3100_port_dowork(struct max3100ts_port *s) } while (!s->force_end_work && !freezing(current) && ((rx & MAX3100_R) || - (!kfifo_is_empty(&tport->xmit_fifo) && - !uart_tx_stopped(&s->port)))); + (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)))); spin_unlock_irqrestore(&s->port.lock, flags); From 46a2ff60c4e5e0b1e6e414670ae3337f00d6c211 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Mon, 22 Sep 2025 23:31:50 +0000 Subject: [PATCH 235/244] Revert "serial: max3100-ts: Multiple fixes" This reverts commit ddb4b97a93f76f8d2c753bd0f9f7fd393b1802e9. --- drivers/tty/serial/max3100-ts.c | 121 +++++++++++++------------------- 1 file changed, 48 insertions(+), 73 deletions(-) diff --git a/drivers/tty/serial/max3100-ts.c b/drivers/tty/serial/max3100-ts.c index c908ac6df8ac9..a3bc1460f2b76 100644 --- a/drivers/tty/serial/max3100-ts.c +++ b/drivers/tty/serial/max3100-ts.c @@ -1,8 +1,13 @@ -// SPDX-License-Identifier: GPL-2.0+ /* * * Copyright (C) 2008 Christian Pellegrin * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * * Notes: the MAX3100 doesn't provide an interrupt on CTS so we have * to use polling for flow control. TX empty IRQ is unusable, since * writing conf clears FIFO buffer and we cannot have this interrupt @@ -114,6 +119,7 @@ struct max3100ts_port { int cts; /* last CTS received for flow ctrl */ int tx_empty; /* last TX empty bit */ + spinlock_t conf_lock; /* shared data */ int conf_commit; /* need to make changes */ int conf; /* configuration for the MAX31000 * (bits 0-7, bits 8-11 are irqs) */ @@ -200,18 +206,18 @@ static void max3100_calc_parity(struct max3100ts_port *s, u16 * c) static void max3100_port_work(struct work_struct *w); -static void max3100_schedule_work(struct max3100ts_port *s) +static void max3100_dowork(struct max3100ts_port *s) { if(!work_pending(&s->work)){ queue_work(s->workqueue, &s->work); } } -static void max3100_timeout(struct timer_list *t) +static void max3100_timeout(unsigned long data) { - struct max3100ts_port *s = from_timer(s, t, timer); + struct max3100ts_port *s = (struct max3100ts_port *)data; if (s->port.state) { - max3100_schedule_work(s); + max3100_dowork(s); mod_timer(&s->timer, jiffies + s->poll_time); } } @@ -231,11 +237,6 @@ static int max3100_sr(struct max3100ts_port *s, u16 tx, u16 * rx) .len = 1, }; - /* The SPI functions provide a locking mechanism that we could use - * here, however, we don't have access to struct spi_controller (that - * I am aware of), so we would use the portlock around these functions. - * It is critical that if two SPI transfers happen, they have no - * interruptions between them. */ if (max3100ts_common.uart_idx != s->minor) { u8 cs = s->minor | MAX3100_CSI; idx.tx_buf = &cs; @@ -245,7 +246,6 @@ static int max3100_sr(struct max3100ts_port *s, u16 tx, u16 * rx) if (status) { dev_warn(&max3100ts_common.spi->dev, "error while calling spi_sync\n"); - mutex_unlock(&max3100ts_common.portlock); return -EIO; } max3100ts_common.uart_idx = s->minor; @@ -272,13 +272,11 @@ static int max3100_handlerx(struct max3100ts_port *s, u16 rx) { unsigned int ch, flg, status = 0; int ret = 0, cts; - unsigned long flags; if (rx & MAX3100_R && s->rx_enabled) { dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); ch = rx & (s->parity & MAX3100_7BIT ? 0x7f : 0xff); - spin_lock_irqsave(&s->port.lock, flags); if (rx & MAX3100_RAFE) { s->port.icount.frame++; flg = TTY_FRAME; @@ -298,18 +296,14 @@ static int max3100_handlerx(struct max3100ts_port *s, u16 rx) flg = TTY_NORMAL; } } - spin_unlock_irqrestore(&s->port.lock, flags); - uart_insert_char(&s->port, status, MAX3100_STATUS_OE, ch, flg); ret = 1; } cts = (rx & MAX3100_CTS) > 0; if (s->cts != cts) { - spin_lock_irqsave(&s->port.lock, flags); s->cts = cts; - uart_handle_cts_change(&s->port, cts ? 1 : 0); - spin_unlock_irqrestore(&s->port.lock, flags); + uart_handle_cts_change(&s->port, cts ? TIOCM_CTS : 0); } return ret; @@ -319,27 +313,21 @@ static void max3100_port_dowork(struct max3100ts_port *s) { int rxchars, x; u16 tx, rx; - int conf, cconf, crts; - unsigned long flags; + int conf, cconf, rts, crts; struct circ_buf *xmit = &s->port.state->xmit; dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); rxchars = 0; - - /* Since the do/while loop has its while conditional at the end which - * some of the calls are dependant on holding the lock, each loop must - * start with the lock held since we need the lock when the while is - * checked. - */ - spin_lock_irqsave(&s->port.lock, flags); do { + spin_lock(&s->conf_lock); conf = s->conf; cconf = s->conf_commit; s->conf_commit = 0; + rts = s->rts; crts = s->rts_commit; s->rts_commit = 0; - spin_unlock_irqrestore(&s->port.lock, flags); + spin_unlock(&s->conf_lock); if (cconf) max3100_sr(s, MAX3100_WC | conf, &rx); @@ -350,8 +338,6 @@ static void max3100_port_dowork(struct max3100ts_port *s) } x = 0; - /* Lock in case we need to call uart_circ_empty() */ - spin_lock_irqsave(&s->port.lock, flags); if (s->port.x_char) { tx = s->port.x_char; x = 1; @@ -363,8 +349,6 @@ static void max3100_port_dowork(struct max3100ts_port *s) } } } - spin_unlock_irqrestore(&s->port.lock, flags); - if (x) { /* we have something to send, so send it! */ max3100_calc_parity(s, &tx); tx |= MAX3100_WD | (s->rts ? MAX3100_RTS : 0); @@ -372,7 +356,6 @@ static void max3100_port_dowork(struct max3100ts_port *s) rxchars += max3100_handlerx(s, rx); if (rx & MAX3100_T) { /* Tx buffer is/was empty, so tx was sent */ - spin_lock_irqsave(&s->port.lock, flags); if (x == 1) { s->port.icount.tx++; s->port.x_char = 0; @@ -381,41 +364,28 @@ static void max3100_port_dowork(struct max3100ts_port *s) (UART_XMIT_SIZE - 1); s->port.icount.tx++; } - spin_unlock_irqrestore(&s->port.lock, flags); } } else { max3100_sr(s, MAX3100_RD, &rx); rxchars += max3100_handlerx(s, rx); } - /* A balance between servicing the UART and getting data to - * userspace */ - if (rxchars > 31) { + if (rxchars > 16) { tty_flip_buffer_push(&s->port.state->port); rxchars = 0; } - /* This is a bit funky, but, according to docs, all xmit - * head/tail accesses need to be inside of the port->lock. - * Grab the lock now, and if we break out of the while - * loop, then release the lock. This hopefully should reduce - * number of acquisitions for a bit of a performance gain. - */ - spin_lock_irqsave(&s->port.lock, flags); if (uart_circ_chars_pending(xmit) < 4){ if(s->port.state->port.tty) uart_write_wakeup(&s->port); } - } while (!s->force_end_work && !freezing(current) && ((rx & MAX3100_R) || - (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)))); - - spin_unlock_irqrestore(&s->port.lock, flags); - - if (rxchars) + (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)))); + if (rxchars > 0){ tty_flip_buffer_push(&s->port.state->port); + } } static void max3100_port_work(struct work_struct *w) @@ -426,7 +396,6 @@ static void max3100_port_work(struct work_struct *w) mutex_unlock(&max3100ts_common.portlock); } -/* Threaded handler called in a sleepable context */ static irqreturn_t max3100_thread_irq(int irqno, void *dev_id) { int i; @@ -462,7 +431,7 @@ static void max3100_start_tx(struct uart_port *port) dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); - max3100_schedule_work(s); + max3100_dowork(s); } static void max3100_stop_rx(struct uart_port *port) @@ -473,10 +442,11 @@ static void max3100_stop_rx(struct uart_port *port) dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); - /* NOTE: port->lock already taken when this function is called */ s->rx_enabled = 0; + spin_lock(&s->conf_lock); s->conf &= ~MAX3100_RM; s->conf_commit = 1; + spin_unlock(&s->conf_lock); } static unsigned int max3100_tx_empty(struct uart_port *port) @@ -488,7 +458,7 @@ static unsigned int max3100_tx_empty(struct uart_port *port) dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); /* may not be truly up-to-date */ - max3100_schedule_work(s); + max3100_dowork(s); return s->tx_empty; } @@ -515,27 +485,30 @@ static void max3100_set_mctrl(struct uart_port *port, unsigned int mctrl) rts = (mctrl & TIOCM_RTS) > 0; + spin_lock(&s->conf_lock); if (s->rts != rts) { s->rts = rts; s->rts_commit = 1; } + spin_unlock(&s->conf_lock); } static void max3100_set_termios(struct uart_port *port, struct ktermios *termios, - const struct ktermios *old) + struct ktermios *old) { struct max3100ts_port *s = container_of(port, struct max3100ts_port, port); int baud = 0; + int i; unsigned cflag; - unsigned long flags; u32 param_new, param_mask, parity = 0; dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); cflag = termios->c_cflag; + param_new = 0; param_mask = 0; baud = tty_termios_baud_rate(termios); @@ -626,20 +599,24 @@ max3100_set_termios(struct uart_port *port, struct ktermios *termios, s->port.ignore_status_mask |= MAX3100_STATUS_PE | MAX3100_STATUS_FE | MAX3100_STATUS_OE; + /* we are sending char from a workqueue so enable */ + s->port.state->port.low_latency = 1; + if (s->poll_time > 0) del_timer_sync(&s->timer); uart_update_timeout(port, termios->c_cflag, baud); - spin_lock_irqsave(&s->port.lock, flags); + spin_lock(&s->conf_lock); s->conf = (s->conf & ~param_mask) | (param_new & param_mask); s->conf_commit = 1; s->parity = parity; - spin_unlock_irqrestore(&s->port.lock, flags); + spin_unlock(&s->conf_lock); - mutex_lock(&max3100ts_common.portlock); - max3100_port_dowork(s); - mutex_unlock(&max3100ts_common.portlock); + for (i = 0; i < max3100ts_common.uart_count; i++) { + struct max3100ts_port *s = max3100ts_common.max3100ts[i]; + max3100_port_dowork(s); + } if (UART_ENABLE_MS(&s->port, termios->c_cflag)) max3100_enable_ms(&s->port); @@ -715,9 +692,7 @@ static int max3100_startup(struct uart_port *port) if (s->loopback) { u16 tx, rx; tx = 0x4001; - mutex_lock(&max3100ts_common.portlock); max3100_sr(s, tx, &rx); - mutex_unlock(&max3100ts_common.portlock); } if (s->max3100_hw_suspend) @@ -821,7 +796,7 @@ static int uart_driver_registered; #ifdef CONFIG_OF static const struct of_device_id max3100_dt_ids[] = { - {.compatible = "technologic,max3100-ts"}, + {.compatible = "max3100-ts"}, {} }; @@ -915,17 +890,16 @@ static int max3100_probe(struct spi_device *spi) return -ENOMEM; } + spin_lock_init(&max3100ts_common.max3100ts[i]->conf_lock); spi_set_drvdata(spi, max3100ts_common.max3100ts[i]); max3100ts_common.max3100ts[i]->minor = i; tx = MAX3100_WC | MAX3100_SHDN | 5; - mutex_lock(&max3100ts_common.portlock); max3100_sr(max3100ts_common.max3100ts[i], tx, &rx); tx = MAX3100_RC; rx = 0; max3100_sr(max3100ts_common.max3100ts[i], tx, &rx); - mutex_unlock(&max3100ts_common.portlock); if ((rx & MAX3100_BAUD) != 5) { kfree(max3100ts_common.max3100ts[i]); max3100ts_common.max3100ts[i] = NULL; @@ -942,8 +916,10 @@ static int max3100_probe(struct spi_device *spi) max3100ts_common.max3100ts[i]->poll_time = 1; max3100ts_common.max3100ts[i]->max3100_hw_suspend = pdata->max3100_hw_suspend; - timer_setup(&max3100ts_common.max3100ts[i]->timer, - max3100_timeout, 0); + init_timer(&max3100ts_common.max3100ts[i]->timer); + max3100ts_common.max3100ts[i]->timer.function = max3100_timeout; + max3100ts_common.max3100ts[i]->timer.data = + (unsigned long)max3100ts_common.max3100ts[i]; dev_dbg(&spi->dev, "%s: adding port %d\n", __func__, i); max3100ts_common.max3100ts[i]->port.irq = max3100ts_common.irq; @@ -965,9 +941,7 @@ static int max3100_probe(struct spi_device *spi) "uart_add_one_port failed for line %d with error %d\n", i, retval); tx = MAX3100_WC | MAX3100_SHDN; - mutex_lock(&max3100ts_common.portlock); max3100_sr(max3100ts_common.max3100ts[i], tx, &rx); - mutex_unlock(&max3100ts_common.portlock); } mutex_unlock(&max3100ts_common.max3100ts_lock); @@ -985,7 +959,7 @@ static int max3100_probe(struct spi_device *spi) return 0; } -static void max3100_remove(struct spi_device *spi) +static int max3100_remove(struct spi_device *spi) { int i; @@ -1014,6 +988,7 @@ static void max3100_remove(struct spi_device *spi) uart_unregister_driver(&max3100_uart_driver); mutex_unlock(&max3100ts_common.max3100ts_lock); + return 0; } #ifdef CONFIG_PM_SLEEP @@ -1057,7 +1032,7 @@ static int max3100_resume(struct device *dev) s->conf_commit = 1; if (s->workqueue) - max3100_schedule_work(s); + max3100_dowork(s); return 0; } @@ -1084,4 +1059,4 @@ module_spi_driver(max3100_driver); MODULE_DESCRIPTION("MAX3100 driver"); MODULE_AUTHOR("Christian Pellegrin "); MODULE_LICENSE("GPL"); -MODULE_ALIAS("spi:max3100"); +MODULE_ALIAS("spi:max3100"); \ No newline at end of file From c25ac25b612198c77deefde4b809775c2c474131 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Mon, 22 Sep 2025 23:31:51 +0000 Subject: [PATCH 236/244] Revert "serial: max3100-ts: Initial commit code from linux-tsimx" This reverts commit 518e104da2e807e54a0001ee26efc0e6d246f5a9. --- drivers/tty/serial/Kconfig | 8 - drivers/tty/serial/Makefile | 1 - drivers/tty/serial/max3100-ts.c | 1062 ------------------------------- 3 files changed, 1071 deletions(-) delete mode 100644 drivers/tty/serial/max3100-ts.c diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index 47da5479cdbdb..282116765e648 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -320,14 +320,6 @@ config SERIAL_MAX3100 Say Y here if you want to support these ICs. -config SERIAL_MAX3100_TS - tristate "MAX3100-TS embeddedTS Extended UART" - depends on SPI - select SERIAL_CORE - help - Support for the embeddedTS FPGA-based MAX3100 multiple-uarts. This - allows multiple emulated MAX3100 UARTs on a single chip-select. - config SERIAL_MAX310X tristate "MAX310X support" depends on SPI_MASTER diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile index 4db5ccace98ee..a2ccbc508ec57 100644 --- a/drivers/tty/serial/Makefile +++ b/drivers/tty/serial/Makefile @@ -50,7 +50,6 @@ obj-$(CONFIG_SERIAL_LANTIQ) += lantiq.o obj-$(CONFIG_SERIAL_LITEUART) += liteuart.o obj-$(CONFIG_SERIAL_HS_LPC32XX) += lpc32xx_hs.o obj-$(CONFIG_SERIAL_MAX3100) += max3100.o -obj-$(CONFIG_SERIAL_MAX3100_TS) += max3100-ts.o obj-$(CONFIG_SERIAL_MAX310X) += max310x.o obj-$(CONFIG_SERIAL_MCF) += mcf.o obj-$(CONFIG_SERIAL_MEN_Z135) += men_z135_uart.o diff --git a/drivers/tty/serial/max3100-ts.c b/drivers/tty/serial/max3100-ts.c deleted file mode 100644 index a3bc1460f2b76..0000000000000 --- a/drivers/tty/serial/max3100-ts.c +++ /dev/null @@ -1,1062 +0,0 @@ -/* - * - * Copyright (C) 2008 Christian Pellegrin - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * - * Notes: the MAX3100 doesn't provide an interrupt on CTS so we have - * to use polling for flow control. TX empty IRQ is unusable, since - * writing conf clears FIFO buffer and we cannot have this interrupt - * always asking us for attention. - * - * Example platform data: - - static struct plat_max3100 max3100_plat_data = { - .loopback = 0, - .crystal = 0, - .poll_time = 100, - }; - - static struct spi_board_info spi_board_info[] = { - { - .modalias = "max3100", - .platform_data = &max3100_plat_data, - .irq = IRQ_EINT12, - .max_speed_hz = 5*1000*1000, - .chip_select = 0, - }, - }; - - * The initial minor number is 209 in the low-density serial port: - * mknod /dev/ttyMAX0 c 204 209 - */ - - /* - Modified from the original max3100.c to support the embeddedTS - MAX3100 extended UARTs. This device puts 3 MAX3100-like uarts in one - chip, but with only a single CS# line going to the chip, and a single - IRQ pin. This requires that all SPI transactions are preceded by a byte - to indicate which of the 3 uarts is being accessed. On an interrupt, - there's no way to tell which of the uarts generated it, so we have to - check 'em all. - */ - -#define MAX3100_MAJOR 204 -#define MAX3100_MINOR 209 - /* - One max3100ts may contain up to 64 uarts. - This driver supports only one max3100ts - */ -#define MAX_MAX3100 64 - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#define MAX3100_C (1<<14) -#define MAX3100_D (0<<14) -#define MAX3100_W (1<<15) -#define MAX3100_RX (0<<15) - -#define MAX3100_WC (MAX3100_W | MAX3100_C) -#define MAX3100_RC (MAX3100_RX | MAX3100_C) -#define MAX3100_WD (MAX3100_W | MAX3100_D) -#define MAX3100_RD (MAX3100_RX | MAX3100_D) -#define MAX3100_CMD (3 << 14) - -#define MAX3100_T (1<<14) -#define MAX3100_R (1<<15) - -#define MAX3100_FEN (1<<13) -#define MAX3100_SHDN (1<<12) -#define MAX3100_TM (1<<11) -#define MAX3100_RM (1<<10) -#define MAX3100_PM (1<<9) -#define MAX3100_RAM (1<<8) -#define MAX3100_IR (1<<7) -#define MAX3100_ST (1<<6) -#define MAX3100_PE (1<<5) -#define MAX3100_L (1<<4) -#define MAX3100_BAUD (0xf) - -#define MAX3100_TE (1<<10) -#define MAX3100_RAFE (1<<10) -#define MAX3100_RTS (1<<9) -#define MAX3100_CTS (1<<9) -#define MAX3100_PT (1<<8) -#define MAX3100_DATA (0xff) - -#define MAX3100_RT (MAX3100_R | MAX3100_T) -#define MAX3100_RTC (MAX3100_RT | MAX3100_CTS | MAX3100_RAFE) - -/* the following simulate a status reg for ignore_status_mask */ -#define MAX3100_STATUS_PE 1 -#define MAX3100_STATUS_FE 2 -#define MAX3100_STATUS_OE 4 - -#define MAX3100_CSI 0xc0 - -struct max3100ts_port { - struct uart_port port; - //struct spi_device *spi; - - int cts; /* last CTS received for flow ctrl */ - int tx_empty; /* last TX empty bit */ - - spinlock_t conf_lock; /* shared data */ - int conf_commit; /* need to make changes */ - int conf; /* configuration for the MAX31000 - * (bits 0-7, bits 8-11 are irqs) */ - int rts_commit; /* need to change rts */ - int rts; /* rts status */ - int baud; /* current baud rate */ - - int parity; /* keeps track if we should send parity */ -#define MAX3100_PARITY_ON 1 -#define MAX3100_PARITY_ODD 2 -#define MAX3100_7BIT 4 - int rx_enabled; /* if we should rx chars */ - - //int irq; /* irq assigned to the max3100 */ - - int minor; /* minor number */ - int crystal; /* 1 if 3.6864Mhz crystal 0 for 1.8432 */ - int loopback; /* 1 if we are in loopback mode */ - - /* for handling irqs: need workqueue since we do spi_sync */ - struct workqueue_struct *workqueue; - struct work_struct work; - /* set to 1 to make the workhandler exit as soon as possible */ - int force_end_work; - /* need to know we are suspending to avoid deadlock on workqueue */ - int suspending; - - /* hook for suspending MAX3100 via dedicated pin */ - void (*max3100_hw_suspend) (int suspend); - - /* poll time (in ms) for ctrl lines */ - int poll_time; - /* and its timer */ - struct timer_list timer; - - int tx_fifo_size; - int rx_fifo_size; - -}; - -static struct s_max3100ts_common { - struct max3100ts_port *max3100ts[MAX_MAX3100]; /* the chip */ - struct mutex portlock; /* race on port usage */ - struct mutex max3100ts_lock; /* race on probe */ - struct spi_device *spi; /* all our uarts are on one spi */ - int irq; /* single irq assigned to the max3100-ts */ - int uart_idx; /* index into max3100ts[ ] */ - int uart_count; /* number of uarts detected */ -} max3100ts_common; - -static int max3100_do_parity(struct max3100ts_port *s, u16 c) -{ - int parity; - - if (s->parity & MAX3100_PARITY_ODD) - parity = 1; - else - parity = 0; - - if (s->parity & MAX3100_7BIT) - c &= 0x7f; - else - c &= 0xff; - - parity = parity ^ (hweight8(c) & 1); - return parity; -} - -static int max3100_check_parity(struct max3100ts_port *s, u16 c) -{ - return max3100_do_parity(s, c) == ((c >> 8) & 1); -} - -static void max3100_calc_parity(struct max3100ts_port *s, u16 * c) -{ - if (s->parity & MAX3100_7BIT) - *c &= 0x7f; - else - *c &= 0xff; - - if (s->parity & MAX3100_PARITY_ON) - *c |= max3100_do_parity(s, *c) << 8; -} - -static void max3100_port_work(struct work_struct *w); - -static void max3100_dowork(struct max3100ts_port *s) -{ - if(!work_pending(&s->work)){ - queue_work(s->workqueue, &s->work); - } -} - -static void max3100_timeout(unsigned long data) -{ - struct max3100ts_port *s = (struct max3100ts_port *)data; - if (s->port.state) { - max3100_dowork(s); - mod_timer(&s->timer, jiffies + s->poll_time); - } -} - -static int max3100_sr(struct max3100ts_port *s, u16 tx, u16 * rx) -{ - struct spi_message message; - u16 etx, erx; - int status; - struct spi_transfer tran = { - .tx_buf = &etx, - .rx_buf = &erx, - .len = 2, - }; - struct spi_transfer idx = { - .rx_buf = NULL, - .len = 1, - }; - - if (max3100ts_common.uart_idx != s->minor) { - u8 cs = s->minor | MAX3100_CSI; - idx.tx_buf = &cs; - spi_message_init(&message); - spi_message_add_tail(&idx, &message); - status = spi_sync(max3100ts_common.spi, &message); - if (status) { - dev_warn(&max3100ts_common.spi->dev, - "error while calling spi_sync\n"); - return -EIO; - } - max3100ts_common.uart_idx = s->minor; - } - - etx = cpu_to_be16(tx); - - spi_message_init(&message); - spi_message_add_tail(&tran, &message); - status = spi_sync(max3100ts_common.spi, &message); - if (status) { - dev_warn(&max3100ts_common.spi->dev, - "error while calling spi_sync\n"); - return -EIO; - } - *rx = be16_to_cpu(erx); - s->tx_empty = (*rx & MAX3100_T) > 0; - - dev_dbg(&max3100ts_common.spi->dev, "%04x - %04x\n", tx, *rx); - return 0; -} - -static int max3100_handlerx(struct max3100ts_port *s, u16 rx) -{ - unsigned int ch, flg, status = 0; - int ret = 0, cts; - - if (rx & MAX3100_R && s->rx_enabled) { - dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); - - ch = rx & (s->parity & MAX3100_7BIT ? 0x7f : 0xff); - if (rx & MAX3100_RAFE) { - s->port.icount.frame++; - flg = TTY_FRAME; - status |= MAX3100_STATUS_FE; - } else { - if (s->parity & MAX3100_PARITY_ON) { - if (max3100_check_parity(s, rx)) { - s->port.icount.rx++; - flg = TTY_NORMAL; - } else { - s->port.icount.parity++; - flg = TTY_PARITY; - status |= MAX3100_STATUS_PE; - } - } else { - s->port.icount.rx++; - flg = TTY_NORMAL; - } - } - uart_insert_char(&s->port, status, MAX3100_STATUS_OE, ch, flg); - ret = 1; - } - - cts = (rx & MAX3100_CTS) > 0; - if (s->cts != cts) { - s->cts = cts; - uart_handle_cts_change(&s->port, cts ? TIOCM_CTS : 0); - } - - return ret; -} - -static void max3100_port_dowork(struct max3100ts_port *s) -{ - int rxchars, x; - u16 tx, rx; - int conf, cconf, rts, crts; - struct circ_buf *xmit = &s->port.state->xmit; - - dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); - - rxchars = 0; - do { - spin_lock(&s->conf_lock); - conf = s->conf; - cconf = s->conf_commit; - s->conf_commit = 0; - rts = s->rts; - crts = s->rts_commit; - s->rts_commit = 0; - spin_unlock(&s->conf_lock); - - if (cconf) - max3100_sr(s, MAX3100_WC | conf, &rx); - if (crts) { - max3100_sr(s, MAX3100_WD | MAX3100_TE | - (s->rts ? MAX3100_RTS : 0), &rx); - rxchars += max3100_handlerx(s, rx); - } - - x = 0; - if (s->port.x_char) { - tx = s->port.x_char; - x = 1; - } else{ - if(!s->force_end_work){ - if (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) { - tx = xmit->buf[xmit->tail]; - x = 2; - } - } - } - if (x) { /* we have something to send, so send it! */ - max3100_calc_parity(s, &tx); - tx |= MAX3100_WD | (s->rts ? MAX3100_RTS : 0); - max3100_sr(s, tx, &rx); - rxchars += max3100_handlerx(s, rx); - - if (rx & MAX3100_T) { /* Tx buffer is/was empty, so tx was sent */ - if (x == 1) { - s->port.icount.tx++; - s->port.x_char = 0; - } else if (x == 2) { - xmit->tail = (xmit->tail + 1) & - (UART_XMIT_SIZE - 1); - s->port.icount.tx++; - } - } - } else { - max3100_sr(s, MAX3100_RD, &rx); - rxchars += max3100_handlerx(s, rx); - } - - if (rxchars > 16) { - tty_flip_buffer_push(&s->port.state->port); - rxchars = 0; - } - - if (uart_circ_chars_pending(xmit) < 4){ - if(s->port.state->port.tty) - uart_write_wakeup(&s->port); - } - } while (!s->force_end_work && - !freezing(current) && - ((rx & MAX3100_R) || - (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)))); - if (rxchars > 0){ - tty_flip_buffer_push(&s->port.state->port); - } -} - -static void max3100_port_work(struct work_struct *w) -{ - struct max3100ts_port *s = container_of(w, struct max3100ts_port, work); - mutex_lock(&max3100ts_common.portlock); - max3100_port_dowork(s); - mutex_unlock(&max3100ts_common.portlock); -} - -static irqreturn_t max3100_thread_irq(int irqno, void *dev_id) -{ - int i; - - dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); - - for (i = 0; i < max3100ts_common.uart_count; i++) { - struct max3100ts_port *s = max3100ts_common.max3100ts[i]; - mutex_lock(&max3100ts_common.portlock); - max3100_port_dowork(s); - mutex_unlock(&max3100ts_common.portlock); - } - - return IRQ_HANDLED; -} - -static void max3100_enable_ms(struct uart_port *port) -{ - struct max3100ts_port *s = container_of(port, - struct max3100ts_port, - port); - - if (s->poll_time > 0) - mod_timer(&s->timer, jiffies); - dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); -} - -static void max3100_start_tx(struct uart_port *port) -{ - struct max3100ts_port *s = container_of(port, - struct max3100ts_port, - port); - - dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); - - max3100_dowork(s); -} - -static void max3100_stop_rx(struct uart_port *port) -{ - struct max3100ts_port *s = container_of(port, - struct max3100ts_port, - port); - - dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); - - s->rx_enabled = 0; - spin_lock(&s->conf_lock); - s->conf &= ~MAX3100_RM; - s->conf_commit = 1; - spin_unlock(&s->conf_lock); -} - -static unsigned int max3100_tx_empty(struct uart_port *port) -{ - struct max3100ts_port *s = container_of(port, - struct max3100ts_port, - port); - - dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); - - /* may not be truly up-to-date */ - max3100_dowork(s); - return s->tx_empty; -} - -static unsigned int max3100_get_mctrl(struct uart_port *port) -{ - struct max3100ts_port *s = container_of(port, - struct max3100ts_port, - port); - - dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); - - /* always assert DCD and DSR since these lines are not wired */ - return (s->cts ? TIOCM_CTS : 0) | TIOCM_DSR | TIOCM_CAR; -} - -static void max3100_set_mctrl(struct uart_port *port, unsigned int mctrl) -{ - struct max3100ts_port *s = container_of(port, - struct max3100ts_port, - port); - int rts; - - dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); - - rts = (mctrl & TIOCM_RTS) > 0; - - spin_lock(&s->conf_lock); - if (s->rts != rts) { - s->rts = rts; - s->rts_commit = 1; - } - spin_unlock(&s->conf_lock); -} - -static void -max3100_set_termios(struct uart_port *port, struct ktermios *termios, - struct ktermios *old) -{ - struct max3100ts_port *s = container_of(port, - struct max3100ts_port, - port); - int baud = 0; - int i; - unsigned cflag; - u32 param_new, param_mask, parity = 0; - - dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); - - cflag = termios->c_cflag; - param_new = 0; - param_mask = 0; - - baud = tty_termios_baud_rate(termios); - param_new = s->conf & MAX3100_BAUD; - switch (baud) { - case 300: - if (s->crystal) - baud = s->baud; - else - param_new = 15; - break; - case 600: - param_new = 14 + s->crystal; - break; - case 1200: - param_new = 13 + s->crystal; - break; - case 2400: - param_new = 12 + s->crystal; - break; - case 4800: - param_new = 11 + s->crystal; - break; - case 9600: - param_new = 10 + s->crystal; - break; - case 19200: - param_new = 9 + s->crystal; - break; - case 38400: - param_new = 8 + s->crystal; - break; - case 57600: - param_new = 1 + s->crystal; - break; - case 115200: - param_new = 0 + s->crystal; - break; - case 230400: - if (s->crystal) - param_new = 0; - else - baud = s->baud; - break; - default: - baud = s->baud; - } - tty_termios_encode_baud_rate(termios, baud, baud); - s->baud = baud; - param_mask |= MAX3100_BAUD; - - if ((cflag & CSIZE) == CS8) { - param_new &= ~MAX3100_L; - parity &= ~MAX3100_7BIT; - } else { - param_new |= MAX3100_L; - parity |= MAX3100_7BIT; - cflag = (cflag & ~CSIZE) | CS7; - } - param_mask |= MAX3100_L; - - if (cflag & CSTOPB) - param_new |= MAX3100_ST; - else - param_new &= ~MAX3100_ST; - param_mask |= MAX3100_ST; - - if (cflag & PARENB) { - param_new |= MAX3100_PE; - parity |= MAX3100_PARITY_ON; - } else { - param_new &= ~MAX3100_PE; - parity &= ~MAX3100_PARITY_ON; - } - param_mask |= MAX3100_PE; - - if (cflag & PARODD) - parity |= MAX3100_PARITY_ODD; - else - parity &= ~MAX3100_PARITY_ODD; - - /* mask termios capabilities we don't support */ - cflag &= ~CMSPAR; - termios->c_cflag = cflag; - - s->port.ignore_status_mask = 0; - if (termios->c_iflag & IGNPAR) - s->port.ignore_status_mask |= - MAX3100_STATUS_PE | MAX3100_STATUS_FE | MAX3100_STATUS_OE; - - /* we are sending char from a workqueue so enable */ - s->port.state->port.low_latency = 1; - - if (s->poll_time > 0) - del_timer_sync(&s->timer); - - uart_update_timeout(port, termios->c_cflag, baud); - - spin_lock(&s->conf_lock); - s->conf = (s->conf & ~param_mask) | (param_new & param_mask); - s->conf_commit = 1; - s->parity = parity; - spin_unlock(&s->conf_lock); - - for (i = 0; i < max3100ts_common.uart_count; i++) { - struct max3100ts_port *s = max3100ts_common.max3100ts[i]; - max3100_port_dowork(s); - } - - if (UART_ENABLE_MS(&s->port, termios->c_cflag)) - max3100_enable_ms(&s->port); -} - -static void max3100_shutdown(struct uart_port *port) -{ - struct max3100ts_port *s = container_of(port, - struct max3100ts_port, - port); - - dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); - - if (s->suspending) - return; - - /* Make sure any dowork from the irq thread are finished */ - s->force_end_work = 1; - mutex_lock(&max3100ts_common.portlock); - mutex_unlock(&max3100ts_common.portlock); - - if (s->poll_time > 0) - del_timer_sync(&s->timer); - - if (s->workqueue) { - flush_workqueue(s->workqueue); - destroy_workqueue(s->workqueue); - s->workqueue = NULL; - } - - /* set shutdown mode to save power */ - if (s->max3100_hw_suspend) - s->max3100_hw_suspend(1); - else { - u16 tx, rx; - - tx = MAX3100_WC | MAX3100_SHDN; - mutex_lock(&max3100ts_common.portlock); - max3100_sr(s, tx, &rx); - mutex_unlock(&max3100ts_common.portlock); - } -} - -static int max3100_startup(struct uart_port *port) -{ - struct max3100ts_port *s = container_of(port, - struct max3100ts_port, - port); - char b[12]; - - dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); - - s->conf = MAX3100_RM | MAX3100_TM; - s->baud = s->crystal ? 230400 : 115200; - s->rx_enabled = 1; - - if (s->suspending) - return 0; - - s->force_end_work = 0; - s->parity = 0; - s->rts = 0; - - sprintf(b, "max3100-%d", s->minor); - s->workqueue = create_singlethread_workqueue(b); - if (!s->workqueue) { - dev_warn(&max3100ts_common.spi->dev, - "cannot create workqueue\n"); - return -EBUSY; - } - INIT_WORK(&s->work, max3100_port_work); - - if (s->loopback) { - u16 tx, rx; - tx = 0x4001; - max3100_sr(s, tx, &rx); - } - - if (s->max3100_hw_suspend) - s->max3100_hw_suspend(0); - s->conf_commit = 1; - - /* wait for clock to settle */ - if (s->port.line == 0) - msleep(50); - - max3100_enable_ms(&s->port); - - return 0; -} - -static const char *max3100_type(struct uart_port *port) -{ - struct max3100ts_port *s = container_of(port, - struct max3100ts_port, - port); - - dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); - - return s->port.type == PORT_MAX3100 ? "MAX3100" : NULL; -} - -static void max3100_release_port(struct uart_port *port) -{ - dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); -} - -static void max3100_config_port(struct uart_port *port, int flags) -{ - struct max3100ts_port *s = container_of(port, - struct max3100ts_port, - port); - - dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); - - if (flags & UART_CONFIG_TYPE) - s->port.type = PORT_MAX3100; -} - -static int max3100_verify_port(struct uart_port *port, - struct serial_struct *ser) -{ - int ret = -EINVAL; - - dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); - - if (ser->type == PORT_UNKNOWN || ser->type == PORT_MAX3100) - ret = 0; - return ret; -} - -static void max3100_stop_tx(struct uart_port *port) -{ - dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); -} - -static int max3100_request_port(struct uart_port *port) -{ - dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); - return 0; -} - -static void max3100_break_ctl(struct uart_port *port, int break_state) -{ - dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); -} - -static struct uart_ops max3100_ops = { - .tx_empty = max3100_tx_empty, - .set_mctrl = max3100_set_mctrl, - .get_mctrl = max3100_get_mctrl, - .stop_tx = max3100_stop_tx, - .start_tx = max3100_start_tx, - .stop_rx = max3100_stop_rx, - .enable_ms = max3100_enable_ms, - .break_ctl = max3100_break_ctl, - .startup = max3100_startup, - .shutdown = max3100_shutdown, - .set_termios = max3100_set_termios, - .type = max3100_type, - .release_port = max3100_release_port, - .request_port = max3100_request_port, - .config_port = max3100_config_port, - .verify_port = max3100_verify_port, -}; - -static struct uart_driver max3100_uart_driver = { - .owner = THIS_MODULE, - .driver_name = "ttyMAX", - .dev_name = "ttyMAX", - .major = MAX3100_MAJOR, - .minor = MAX3100_MINOR, - .nr = MAX_MAX3100, -}; - -static int uart_driver_registered; - -#ifdef CONFIG_OF -static const struct of_device_id max3100_dt_ids[] = { - {.compatible = "max3100-ts"}, - {} -}; - -MODULE_DEVICE_TABLE(of, max3100_dt_ids); - -static const struct plat_max3100 *max3100_probe_dt(struct device *dev) -{ - struct plat_max3100 *pdata; - struct device_node *node = dev->of_node; - const struct of_device_id *match; - - if (!node) { - dev_err(dev, "Device does not have associated DT data\n"); - return ERR_PTR(-EINVAL); - } - - match = of_match_device(max3100_dt_ids, dev); - if (!match) { - dev_err(dev, "Unknown device model\n"); - return ERR_PTR(-EINVAL); - } - - pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); - if (!pdata) - return ERR_PTR(-ENOMEM); - - // Force MAX310 into loopback - of_property_read_u32(node, "loopback", &pdata->loopback); - // Crystal <1 = 3.6864MHz> <0 = 1.8432MHz> - of_property_read_u32(node, "crystal", &pdata->crystal); - // Poll time in ms, 0 disables CTS, 100 typical - of_property_read_u32(node, "poll-time", &pdata->poll_time); - // Size of the Tx FIFO, in bytes - of_property_read_u32(node, "tx-fifo-size", &pdata->tx_fifo_size); - // Size of the Rx FIFO, in bytes - of_property_read_u32(node, "rx-fifo-size", &pdata->rx_fifo_size); - return pdata; -} - -#else - -static const struct plat_max3100 *max3100_probe_dt(struct device *dev) -{ - dev_err(dev, "no platform data defined\n"); - return ERR_PTR(-EINVAL); -} - -#endif - -static int max3100_probe(struct spi_device *spi) -{ - int i, retval; - const struct plat_max3100 *pdata; - u16 tx, rx; - - mutex_init(&max3100ts_common.max3100ts_lock); - mutex_init(&max3100ts_common.portlock); - - mutex_lock(&max3100ts_common.max3100ts_lock); - - if (!uart_driver_registered) { - uart_driver_registered = 1; - retval = uart_register_driver(&max3100_uart_driver); - if (retval) { - printk(KERN_ERR - "Couldn't register max3100 uart driver\n"); - mutex_unlock(&max3100ts_common.max3100ts_lock); - return retval; - } - } - - pdata = max3100_probe_dt(&spi->dev); - if (IS_ERR(pdata)) { - mutex_unlock(&max3100ts_common.max3100ts_lock); - return PTR_ERR(pdata); - } - - max3100ts_common.spi = spi; - max3100ts_common.irq = spi->irq; - max3100ts_common.uart_idx = -1; - max3100ts_common.uart_count = 0; - - for (i = 0; i < MAX_MAX3100; i++) { - max3100ts_common.max3100ts[i] = - kzalloc(sizeof(struct max3100ts_port), GFP_KERNEL); - if (!max3100ts_common.max3100ts[i]) { - dev_warn(&spi->dev, - "kmalloc for max3100 structure %d failed!\n", - i); - mutex_unlock(&max3100ts_common.max3100ts_lock); - return -ENOMEM; - } - - spin_lock_init(&max3100ts_common.max3100ts[i]->conf_lock); - spi_set_drvdata(spi, max3100ts_common.max3100ts[i]); - - max3100ts_common.max3100ts[i]->minor = i; - - tx = MAX3100_WC | MAX3100_SHDN | 5; - max3100_sr(max3100ts_common.max3100ts[i], tx, &rx); - tx = MAX3100_RC; - rx = 0; - max3100_sr(max3100ts_common.max3100ts[i], tx, &rx); - if ((rx & MAX3100_BAUD) != 5) { - kfree(max3100ts_common.max3100ts[i]); - max3100ts_common.max3100ts[i] = NULL; - break; - } else - max3100ts_common.uart_count++; - - max3100ts_common.max3100ts[i]->crystal = pdata->crystal; - max3100ts_common.max3100ts[i]->loopback = pdata->loopback; - max3100ts_common.max3100ts[i]->poll_time = - pdata->poll_time * HZ / 1000; - if (pdata->poll_time > 0 - && max3100ts_common.max3100ts[i]->poll_time == 0) - max3100ts_common.max3100ts[i]->poll_time = 1; - max3100ts_common.max3100ts[i]->max3100_hw_suspend = - pdata->max3100_hw_suspend; - init_timer(&max3100ts_common.max3100ts[i]->timer); - max3100ts_common.max3100ts[i]->timer.function = max3100_timeout; - max3100ts_common.max3100ts[i]->timer.data = - (unsigned long)max3100ts_common.max3100ts[i]; - - dev_dbg(&spi->dev, "%s: adding port %d\n", __func__, i); - max3100ts_common.max3100ts[i]->port.irq = max3100ts_common.irq; - max3100ts_common.max3100ts[i]->port.uartclk = - max3100ts_common.max3100ts[i]->crystal ? 3686400 : 1843200; - max3100ts_common.max3100ts[i]->port.fifosize = 16; - max3100ts_common.max3100ts[i]->port.ops = &max3100_ops; - max3100ts_common.max3100ts[i]->port.flags = - UPF_SKIP_TEST | UPF_BOOT_AUTOCONF; - max3100ts_common.max3100ts[i]->port.line = i; - max3100ts_common.max3100ts[i]->port.type = PORT_MAX3100; - max3100ts_common.max3100ts[i]->port.dev = &spi->dev; - - retval = - uart_add_one_port(&max3100_uart_driver, - &max3100ts_common.max3100ts[i]->port); - if (retval < 0) - dev_warn(&spi->dev, - "uart_add_one_port failed for line %d with error %d\n", - i, retval); - tx = MAX3100_WC | MAX3100_SHDN; - max3100_sr(max3100ts_common.max3100ts[i], tx, &rx); - } - - mutex_unlock(&max3100ts_common.max3100ts_lock); - - retval = devm_request_threaded_irq(&spi->dev, spi->irq, NULL, max3100_thread_irq, - IRQF_TRIGGER_LOW | IRQF_ONESHOT, "max3100-ts", - &max3100ts_common); - - if (retval) { - dev_warn(&spi->dev, "cannot allocate irq %d\n", spi->irq); - return retval; - } - - dev_info(&spi->dev, "Detected %d uarts\n", max3100ts_common.uart_count); - return 0; -} - -static int max3100_remove(struct spi_device *spi) -{ - int i; - - mutex_lock(&max3100ts_common.max3100ts_lock); - - /* find out the index for the chip we are removing */ - for (i = MAX_MAX3100 - 1; i >= 0; i--) - if (max3100ts_common.max3100ts[i]) { - - dev_dbg(&spi->dev, "%s: removing port %d\n", __func__, - i); - uart_remove_one_port(&max3100_uart_driver, - &max3100ts_common.max3100ts[i]-> - port); - - kfree(max3100ts_common.max3100ts[i]); - max3100ts_common.max3100ts[i] = NULL; - } - - if (max3100ts_common.irq) { - free_irq(max3100ts_common.irq, &max3100ts_common); - max3100ts_common.irq = 0; - } - - pr_debug("removing max3100 driver\n"); - uart_unregister_driver(&max3100_uart_driver); - - mutex_unlock(&max3100ts_common.max3100ts_lock); - return 0; -} - -#ifdef CONFIG_PM_SLEEP - -static int max3100_suspend(struct device *dev) -{ - struct max3100ts_port *s = dev_get_drvdata(dev); - - dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); - - disable_irq(max3100ts_common.irq); - - s->suspending = 1; - uart_suspend_port(&max3100_uart_driver, &s->port); - - if (s->max3100_hw_suspend) - s->max3100_hw_suspend(1); - else { - /* no HW suspend, so do SW one */ - u16 tx, rx; - tx = MAX3100_WC | MAX3100_SHDN; - mutex_lock(&max3100ts_common.portlock); - max3100_sr(s, tx, &rx); - mutex_unlock(&max3100ts_common.portlock); - } - return 0; -} - -static int max3100_resume(struct device *dev) -{ - struct max3100ts_port *s = dev_get_drvdata(dev); - - dev_dbg(&max3100ts_common.spi->dev, "%s\n", __func__); - - if (s->max3100_hw_suspend) - s->max3100_hw_suspend(0); - uart_resume_port(&max3100_uart_driver, &s->port); - s->suspending = 0; - - enable_irq(max3100ts_common.irq); - - s->conf_commit = 1; - if (s->workqueue) - max3100_dowork(s); - - return 0; -} - -static SIMPLE_DEV_PM_OPS(max3100_pm_ops, max3100_suspend, max3100_resume); -#define MAX3100_PM_OPS (&max3100_pm_ops) - -#else -#define MAX3100_PM_OPS NULL -#endif - -static struct spi_driver max3100_driver = { - .driver = { - .name = "max3100-ts", - .owner = THIS_MODULE, - .pm = MAX3100_PM_OPS, - }, - .probe = max3100_probe, - .remove = max3100_remove, -}; - -module_spi_driver(max3100_driver); - -MODULE_DESCRIPTION("MAX3100 driver"); -MODULE_AUTHOR("Christian Pellegrin "); -MODULE_LICENSE("GPL"); -MODULE_ALIAS("spi:max3100"); \ No newline at end of file From cd6494c9a664ad77508d1c236aa9666686d4ef5d Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Mon, 22 Sep 2025 23:54:38 +0000 Subject: [PATCH 237/244] initial commit of max3100-ts Signed-off-by: Kris Bahnsen --- drivers/tty/serial/Kconfig | 8 + drivers/tty/serial/Makefile | 1 + drivers/tty/serial/max3100-ts.c | 841 ++++++++++++++++++++++++++++++++ 3 files changed, 850 insertions(+) create mode 100644 drivers/tty/serial/max3100-ts.c diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index 282116765e648..7b728294ec452 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -334,6 +334,14 @@ config SERIAL_MAX310X Say Y here if you want to support this ICs. +config SERIAL_MAX3100_TS + tristate "MAX3100 embeddedTS extended UART" + depends on SPI + select SERIAL_CORE + help + Support for the embeddedTS FPGA-based MAX3100 multiple-uarts. This + allows multiple emulated MAX3100 UARTs on a single chip-select. + config SERIAL_DZ bool "DECstation DZ serial driver" depends on MACH_DECSTATION && 32BIT diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile index a2ccbc508ec57..3906bc4004d2e 100644 --- a/drivers/tty/serial/Makefile +++ b/drivers/tty/serial/Makefile @@ -51,6 +51,7 @@ obj-$(CONFIG_SERIAL_LITEUART) += liteuart.o obj-$(CONFIG_SERIAL_HS_LPC32XX) += lpc32xx_hs.o obj-$(CONFIG_SERIAL_MAX3100) += max3100.o obj-$(CONFIG_SERIAL_MAX310X) += max310x.o +obj-$(CONFIG_SERIAL_MAX3100_TS) += max3100-ts.o obj-$(CONFIG_SERIAL_MCF) += mcf.o obj-$(CONFIG_SERIAL_MEN_Z135) += men_z135_uart.o obj-$(CONFIG_SERIAL_MILBEAUT_USIO) += milbeaut_usio.o diff --git a/drivers/tty/serial/max3100-ts.c b/drivers/tty/serial/max3100-ts.c new file mode 100644 index 0000000000000..a7cb9185769ad --- /dev/null +++ b/drivers/tty/serial/max3100-ts.c @@ -0,0 +1,841 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2008 Christian Pellegrin + * + * Notes: the MAX3100 doesn't provide an interrupt on CTS so we have + * to use polling for flow control. TX empty IRQ is unusable, since + * writing conf clears FIFO buffer and we cannot have this interrupt + * always asking us for attention. + * + * The initial minor number is 209 in the low-density serial port: + * mknod /dev/ttyMAX0 c 204 209 + */ + +#define MAX3100_MAJOR 204 +#define MAX3100_MINOR 209 +/* 4 MAX3100s should be enough for everyone */ +#define MAX_MAX3100 4 + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define MAX3100_C (1<<14) +#define MAX3100_D (0<<14) +#define MAX3100_W (1<<15) +#define MAX3100_RX (0<<15) + +#define MAX3100_WC (MAX3100_W | MAX3100_C) +#define MAX3100_RC (MAX3100_RX | MAX3100_C) +#define MAX3100_WD (MAX3100_W | MAX3100_D) +#define MAX3100_RD (MAX3100_RX | MAX3100_D) +#define MAX3100_CMD (3 << 14) + +#define MAX3100_T (1<<14) +#define MAX3100_R (1<<15) + +#define MAX3100_FEN (1<<13) +#define MAX3100_SHDN (1<<12) +#define MAX3100_TM (1<<11) +#define MAX3100_RM (1<<10) +#define MAX3100_PM (1<<9) +#define MAX3100_RAM (1<<8) +#define MAX3100_IR (1<<7) +#define MAX3100_ST (1<<6) +#define MAX3100_PE (1<<5) +#define MAX3100_L (1<<4) +#define MAX3100_BAUD (0xf) + +#define MAX3100_TE (1<<10) +#define MAX3100_RAFE (1<<10) +#define MAX3100_RTS (1<<9) +#define MAX3100_CTS (1<<9) +#define MAX3100_PT (1<<8) +#define MAX3100_DATA (0xff) + +#define MAX3100_RT (MAX3100_R | MAX3100_T) +#define MAX3100_RTC (MAX3100_RT | MAX3100_CTS | MAX3100_RAFE) + +/* the following simulate a status reg for ignore_status_mask */ +#define MAX3100_STATUS_PE 1 +#define MAX3100_STATUS_FE 2 +#define MAX3100_STATUS_OE 4 + +struct max3100_port { + struct uart_port port; + struct spi_device *spi; + + int cts; /* last CTS received for flow ctrl */ + int tx_empty; /* last TX empty bit */ + + spinlock_t conf_lock; /* shared data */ + int conf_commit; /* need to make changes */ + int conf; /* configuration for the MAX31000 + * (bits 0-7, bits 8-11 are irqs) */ + int rts_commit; /* need to change rts */ + int rts; /* rts status */ + int baud; /* current baud rate */ + + int parity; /* keeps track if we should send parity */ +#define MAX3100_PARITY_ON 1 +#define MAX3100_PARITY_ODD 2 +#define MAX3100_7BIT 4 + int rx_enabled; /* if we should rx chars */ + + int minor; /* minor number */ + int loopback_commit; /* need to change loopback */ + int loopback; /* 1 if we are in loopback mode */ + + /* for handling irqs: need workqueue since we do spi_sync */ + struct workqueue_struct *workqueue; + struct work_struct work; + /* set to 1 to make the workhandler exit as soon as possible */ + int force_end_work; + /* need to know we are suspending to avoid deadlock on workqueue */ + int suspending; + + struct timer_list timer; +}; + +static inline struct max3100_port *to_max3100_port(struct uart_port *port) +{ + return container_of(port, struct max3100_port, port); +} + +static struct max3100_port *max3100s[MAX_MAX3100]; /* the chips */ +static DEFINE_MUTEX(max3100s_lock); /* race on probe */ + +static int max3100_do_parity(struct max3100_port *s, u16 c) +{ + int parity; + + if (s->parity & MAX3100_PARITY_ODD) + parity = 1; + else + parity = 0; + + if (s->parity & MAX3100_7BIT) + c &= 0x7f; + else + c &= 0xff; + + parity = parity ^ (hweight8(c) & 1); + return parity; +} + +static int max3100_check_parity(struct max3100_port *s, u16 c) +{ + return max3100_do_parity(s, c) == ((c >> 8) & 1); +} + +static void max3100_calc_parity(struct max3100_port *s, u16 *c) +{ + if (s->parity & MAX3100_7BIT) + *c &= 0x7f; + else + *c &= 0xff; + + if (s->parity & MAX3100_PARITY_ON) + *c |= max3100_do_parity(s, *c) << 8; +} + +static int max3100_sr(struct max3100_port *s, u16 tx, u16 *rx) +{ + struct spi_message message; + __be16 etx, erx; + int status; + struct spi_transfer tran = { + .tx_buf = &etx, + .rx_buf = &erx, + .len = 2, + }; + + etx = cpu_to_be16(tx); + spi_message_init(&message); + spi_message_add_tail(&tran, &message); + status = spi_sync(s->spi, &message); + if (status) { + dev_warn(&s->spi->dev, "error while calling spi_sync\n"); + return -EIO; + } + *rx = be16_to_cpu(erx); + s->tx_empty = (*rx & MAX3100_T) > 0; + dev_dbg(&s->spi->dev, "%04x - %04x\n", tx, *rx); + return 0; +} + +static int max3100_handlerx_unlocked(struct max3100_port *s, u16 rx) +{ + unsigned int status = 0; + int ret = 0, cts; + u8 ch, flg; + + if (rx & MAX3100_R && s->rx_enabled) { + dev_dbg(&s->spi->dev, "%s\n", __func__); + ch = rx & (s->parity & MAX3100_7BIT ? 0x7f : 0xff); + if (rx & MAX3100_RAFE) { + s->port.icount.frame++; + flg = TTY_FRAME; + status |= MAX3100_STATUS_FE; + } else { + if (s->parity & MAX3100_PARITY_ON) { + if (max3100_check_parity(s, rx)) { + s->port.icount.rx++; + flg = TTY_NORMAL; + } else { + s->port.icount.parity++; + flg = TTY_PARITY; + status |= MAX3100_STATUS_PE; + } + } else { + s->port.icount.rx++; + flg = TTY_NORMAL; + } + } + uart_insert_char(&s->port, status, MAX3100_STATUS_OE, ch, flg); + ret = 1; + } + + cts = (rx & MAX3100_CTS) > 0; + if (s->cts != cts) { + s->cts = cts; + uart_handle_cts_change(&s->port, cts); + } + + return ret; +} + +static int max3100_handlerx(struct max3100_port *s, u16 rx) +{ + unsigned long flags; + int ret; + + uart_port_lock_irqsave(&s->port, &flags); + ret = max3100_handlerx_unlocked(s, rx); + uart_port_unlock_irqrestore(&s->port, flags); + return ret; +} + +static void max3100_work(struct work_struct *w) +{ + struct max3100_port *s = container_of(w, struct max3100_port, work); + struct tty_port *tport = &s->port.state->port; + unsigned char ch; + int conf, cconf, cloopback, crts; + int rxchars; + u16 tx, rx; + + dev_dbg(&s->spi->dev, "%s\n", __func__); + + rxchars = 0; + do { + spin_lock(&s->conf_lock); + conf = s->conf; + cconf = s->conf_commit; + s->conf_commit = 0; + cloopback = s->loopback_commit; + s->loopback_commit = 0; + crts = s->rts_commit; + s->rts_commit = 0; + spin_unlock(&s->conf_lock); + if (cconf) + max3100_sr(s, MAX3100_WC | conf, &rx); + if (cloopback) + max3100_sr(s, 0x4001, &rx); + if (crts) { + max3100_sr(s, MAX3100_WD | MAX3100_TE | + (s->rts ? MAX3100_RTS : 0), &rx); + rxchars += max3100_handlerx(s, rx); + } + + max3100_sr(s, MAX3100_RD, &rx); + rxchars += max3100_handlerx(s, rx); + + if (rx & MAX3100_T) { + tx = 0xffff; + if (s->port.x_char) { + tx = s->port.x_char; + s->port.icount.tx++; + s->port.x_char = 0; + } else if (!uart_tx_stopped(&s->port) && + uart_fifo_get(&s->port, &ch)) { + tx = ch; + } + if (tx != 0xffff) { + max3100_calc_parity(s, &tx); + tx |= MAX3100_WD | (s->rts ? MAX3100_RTS : 0); + max3100_sr(s, tx, &rx); + rxchars += max3100_handlerx(s, rx); + } + } + + if (rxchars > 16) { + tty_flip_buffer_push(&s->port.state->port); + rxchars = 0; + } + if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) + uart_write_wakeup(&s->port); + + } while (!s->force_end_work && + !freezing(current) && + ((rx & MAX3100_R) || + (!kfifo_is_empty(&tport->xmit_fifo) && + !uart_tx_stopped(&s->port)))); + + if (rxchars > 0) + tty_flip_buffer_push(&s->port.state->port); +} + +static void max3100_dowork(struct max3100_port *s) +{ + if (!s->force_end_work && !freezing(current) && !s->suspending) + queue_work(s->workqueue, &s->work); +} + +static void max3100_timeout(struct timer_list *t) +{ + struct max3100_port *s = from_timer(s, t, timer); + + max3100_dowork(s); + mod_timer(&s->timer, jiffies + uart_poll_timeout(&s->port)); +} + +static irqreturn_t max3100_irq(int irqno, void *dev_id) +{ + struct max3100_port *s = dev_id; + + dev_dbg(&s->spi->dev, "%s\n", __func__); + + max3100_dowork(s); + return IRQ_HANDLED; +} + +static void max3100_enable_ms(struct uart_port *port) +{ + struct max3100_port *s = to_max3100_port(port); + + mod_timer(&s->timer, jiffies); + dev_dbg(&s->spi->dev, "%s\n", __func__); +} + +static void max3100_start_tx(struct uart_port *port) +{ + struct max3100_port *s = to_max3100_port(port); + + dev_dbg(&s->spi->dev, "%s\n", __func__); + + max3100_dowork(s); +} + +static void max3100_stop_rx(struct uart_port *port) +{ + struct max3100_port *s = to_max3100_port(port); + + dev_dbg(&s->spi->dev, "%s\n", __func__); + + s->rx_enabled = 0; + spin_lock(&s->conf_lock); + s->conf &= ~MAX3100_RM; + s->conf_commit = 1; + spin_unlock(&s->conf_lock); + max3100_dowork(s); +} + +static unsigned int max3100_tx_empty(struct uart_port *port) +{ + struct max3100_port *s = to_max3100_port(port); + + dev_dbg(&s->spi->dev, "%s\n", __func__); + + /* may not be truly up-to-date */ + max3100_dowork(s); + return s->tx_empty; +} + +static unsigned int max3100_get_mctrl(struct uart_port *port) +{ + struct max3100_port *s = to_max3100_port(port); + + dev_dbg(&s->spi->dev, "%s\n", __func__); + + /* may not be truly up-to-date */ + max3100_dowork(s); + /* always assert DCD and DSR since these lines are not wired */ + return (s->cts ? TIOCM_CTS : 0) | TIOCM_DSR | TIOCM_CAR; +} + +static void max3100_set_mctrl(struct uart_port *port, unsigned int mctrl) +{ + struct max3100_port *s = to_max3100_port(port); + int loopback, rts; + + dev_dbg(&s->spi->dev, "%s\n", __func__); + + loopback = (mctrl & TIOCM_LOOP) > 0; + rts = (mctrl & TIOCM_RTS) > 0; + + spin_lock(&s->conf_lock); + if (s->loopback != loopback) { + s->loopback = loopback; + s->loopback_commit = 1; + } + if (s->rts != rts) { + s->rts = rts; + s->rts_commit = 1; + } + if (s->loopback_commit || s->rts_commit) + max3100_dowork(s); + spin_unlock(&s->conf_lock); +} + +static void +max3100_set_termios(struct uart_port *port, struct ktermios *termios, + const struct ktermios *old) +{ + struct max3100_port *s = to_max3100_port(port); + unsigned int baud = port->uartclk / 16; + unsigned int baud230400 = (baud == 230400) ? 1 : 0; + unsigned cflag; + u32 param_new, param_mask, parity = 0; + + dev_dbg(&s->spi->dev, "%s\n", __func__); + + cflag = termios->c_cflag; + param_mask = 0; + + baud = tty_termios_baud_rate(termios); + param_new = s->conf & MAX3100_BAUD; + switch (baud) { + case 300: + if (baud230400) + baud = s->baud; + else + param_new = 15; + break; + case 600: + param_new = 14 + baud230400; + break; + case 1200: + param_new = 13 + baud230400; + break; + case 2400: + param_new = 12 + baud230400; + break; + case 4800: + param_new = 11 + baud230400; + break; + case 9600: + param_new = 10 + baud230400; + break; + case 19200: + param_new = 9 + baud230400; + break; + case 38400: + param_new = 8 + baud230400; + break; + case 57600: + param_new = 1 + baud230400; + break; + case 115200: + param_new = 0 + baud230400; + break; + case 230400: + if (baud230400) + param_new = 0; + else + baud = s->baud; + break; + default: + baud = s->baud; + } + tty_termios_encode_baud_rate(termios, baud, baud); + s->baud = baud; + param_mask |= MAX3100_BAUD; + + if ((cflag & CSIZE) == CS8) { + param_new &= ~MAX3100_L; + parity &= ~MAX3100_7BIT; + } else { + param_new |= MAX3100_L; + parity |= MAX3100_7BIT; + cflag = (cflag & ~CSIZE) | CS7; + } + param_mask |= MAX3100_L; + + if (cflag & CSTOPB) + param_new |= MAX3100_ST; + else + param_new &= ~MAX3100_ST; + param_mask |= MAX3100_ST; + + if (cflag & PARENB) { + param_new |= MAX3100_PE; + parity |= MAX3100_PARITY_ON; + } else { + param_new &= ~MAX3100_PE; + parity &= ~MAX3100_PARITY_ON; + } + param_mask |= MAX3100_PE; + + if (cflag & PARODD) + parity |= MAX3100_PARITY_ODD; + else + parity &= ~MAX3100_PARITY_ODD; + + /* mask termios capabilities we don't support */ + cflag &= ~CMSPAR; + termios->c_cflag = cflag; + + s->port.ignore_status_mask = 0; + if (termios->c_iflag & IGNPAR) + s->port.ignore_status_mask |= + MAX3100_STATUS_PE | MAX3100_STATUS_FE | + MAX3100_STATUS_OE; + + del_timer_sync(&s->timer); + uart_update_timeout(port, termios->c_cflag, baud); + + spin_lock(&s->conf_lock); + s->conf = (s->conf & ~param_mask) | (param_new & param_mask); + s->conf_commit = 1; + s->parity = parity; + spin_unlock(&s->conf_lock); + max3100_dowork(s); + + if (UART_ENABLE_MS(&s->port, termios->c_cflag)) + max3100_enable_ms(&s->port); +} + +static void max3100_shutdown(struct uart_port *port) +{ + struct max3100_port *s = to_max3100_port(port); + u16 rx; + + dev_dbg(&s->spi->dev, "%s\n", __func__); + + if (s->suspending) + return; + + s->force_end_work = 1; + + del_timer_sync(&s->timer); + + if (s->workqueue) { + destroy_workqueue(s->workqueue); + s->workqueue = NULL; + } + if (port->irq) + free_irq(port->irq, s); + + /* set shutdown mode to save power */ + max3100_sr(s, MAX3100_WC | MAX3100_SHDN, &rx); +} + +static int max3100_startup(struct uart_port *port) +{ + struct max3100_port *s = to_max3100_port(port); + char b[12]; + int ret; + + dev_dbg(&s->spi->dev, "%s\n", __func__); + + s->conf = MAX3100_RM; + s->baud = port->uartclk / 16; + s->rx_enabled = 1; + + if (s->suspending) + return 0; + + s->force_end_work = 0; + s->parity = 0; + s->rts = 0; + + sprintf(b, "max3100-%d", s->minor); + s->workqueue = create_freezable_workqueue(b); + if (!s->workqueue) { + dev_warn(&s->spi->dev, "cannot create workqueue\n"); + return -EBUSY; + } + INIT_WORK(&s->work, max3100_work); + + ret = request_irq(port->irq, max3100_irq, IRQF_TRIGGER_FALLING, "max3100", s); + if (ret < 0) { + dev_warn(&s->spi->dev, "cannot allocate irq %d\n", port->irq); + port->irq = 0; + destroy_workqueue(s->workqueue); + s->workqueue = NULL; + return -EBUSY; + } + + s->conf_commit = 1; + max3100_dowork(s); + /* wait for clock to settle */ + msleep(50); + + max3100_enable_ms(&s->port); + + return 0; +} + +static const char *max3100_type(struct uart_port *port) +{ + struct max3100_port *s = to_max3100_port(port); + + dev_dbg(&s->spi->dev, "%s\n", __func__); + + return s->port.type == PORT_MAX3100 ? "MAX3100" : NULL; +} + +static void max3100_release_port(struct uart_port *port) +{ + struct max3100_port *s = to_max3100_port(port); + + dev_dbg(&s->spi->dev, "%s\n", __func__); +} + +static void max3100_config_port(struct uart_port *port, int flags) +{ + struct max3100_port *s = to_max3100_port(port); + + dev_dbg(&s->spi->dev, "%s\n", __func__); + + if (flags & UART_CONFIG_TYPE) + s->port.type = PORT_MAX3100; +} + +static int max3100_verify_port(struct uart_port *port, + struct serial_struct *ser) +{ + struct max3100_port *s = to_max3100_port(port); + int ret = -EINVAL; + + dev_dbg(&s->spi->dev, "%s\n", __func__); + + if (ser->type == PORT_UNKNOWN || ser->type == PORT_MAX3100) + ret = 0; + return ret; +} + +static void max3100_stop_tx(struct uart_port *port) +{ + struct max3100_port *s = to_max3100_port(port); + + dev_dbg(&s->spi->dev, "%s\n", __func__); +} + +static int max3100_request_port(struct uart_port *port) +{ + struct max3100_port *s = to_max3100_port(port); + + dev_dbg(&s->spi->dev, "%s\n", __func__); + return 0; +} + +static void max3100_break_ctl(struct uart_port *port, int break_state) +{ + struct max3100_port *s = to_max3100_port(port); + + dev_dbg(&s->spi->dev, "%s\n", __func__); +} + +static const struct uart_ops max3100_ops = { + .tx_empty = max3100_tx_empty, + .set_mctrl = max3100_set_mctrl, + .get_mctrl = max3100_get_mctrl, + .stop_tx = max3100_stop_tx, + .start_tx = max3100_start_tx, + .stop_rx = max3100_stop_rx, + .enable_ms = max3100_enable_ms, + .break_ctl = max3100_break_ctl, + .startup = max3100_startup, + .shutdown = max3100_shutdown, + .set_termios = max3100_set_termios, + .type = max3100_type, + .release_port = max3100_release_port, + .request_port = max3100_request_port, + .config_port = max3100_config_port, + .verify_port = max3100_verify_port, +}; + +static struct uart_driver max3100_uart_driver = { + .owner = THIS_MODULE, + .driver_name = "ttyMAX", + .dev_name = "ttyMAX", + .major = MAX3100_MAJOR, + .minor = MAX3100_MINOR, + .nr = MAX_MAX3100, +}; +static int uart_driver_registered; + +static int max3100_probe(struct spi_device *spi) +{ + struct device *dev = &spi->dev; + int i, retval; + u16 rx; + + mutex_lock(&max3100s_lock); + + if (!uart_driver_registered) { + retval = uart_register_driver(&max3100_uart_driver); + if (retval) { + mutex_unlock(&max3100s_lock); + return dev_err_probe(dev, retval, "Couldn't register max3100 uart driver\n"); + } + + uart_driver_registered = 1; + } + + for (i = 0; i < MAX_MAX3100; i++) + if (!max3100s[i]) + break; + if (i == MAX_MAX3100) { + mutex_unlock(&max3100s_lock); + return dev_err_probe(dev, -ENOMEM, "too many MAX3100 chips\n"); + } + + max3100s[i] = kzalloc(sizeof(struct max3100_port), GFP_KERNEL); + if (!max3100s[i]) { + mutex_unlock(&max3100s_lock); + return -ENOMEM; + } + max3100s[i]->spi = spi; + spin_lock_init(&max3100s[i]->conf_lock); + spi_set_drvdata(spi, max3100s[i]); + max3100s[i]->minor = i; + timer_setup(&max3100s[i]->timer, max3100_timeout, 0); + + dev_dbg(&spi->dev, "%s: adding port %d\n", __func__, i); + max3100s[i]->port.irq = spi->irq; + max3100s[i]->port.fifosize = 16; + max3100s[i]->port.ops = &max3100_ops; + max3100s[i]->port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF; + max3100s[i]->port.line = i; + max3100s[i]->port.type = PORT_MAX3100; + max3100s[i]->port.dev = &spi->dev; + + /* Read clock frequency from a property, uart_add_one_port() will fail if it's not set */ + device_property_read_u32(dev, "clock-frequency", &max3100s[i]->port.uartclk); + + retval = uart_add_one_port(&max3100_uart_driver, &max3100s[i]->port); + if (retval < 0) + dev_err_probe(dev, retval, "uart_add_one_port failed for line %d\n", i); + + /* set shutdown mode to save power. Will be woken-up on open */ + max3100_sr(max3100s[i], MAX3100_WC | MAX3100_SHDN, &rx); + mutex_unlock(&max3100s_lock); + return 0; +} + +static void max3100_remove(struct spi_device *spi) +{ + struct max3100_port *s = spi_get_drvdata(spi); + int i; + + mutex_lock(&max3100s_lock); + + /* find out the index for the chip we are removing */ + for (i = 0; i < MAX_MAX3100; i++) + if (max3100s[i] == s) { + dev_dbg(&spi->dev, "%s: removing port %d\n", __func__, i); + uart_remove_one_port(&max3100_uart_driver, &max3100s[i]->port); + kfree(max3100s[i]); + max3100s[i] = NULL; + break; + } + + WARN_ON(i == MAX_MAX3100); + + /* check if this is the last chip we have */ + for (i = 0; i < MAX_MAX3100; i++) + if (max3100s[i]) { + mutex_unlock(&max3100s_lock); + return; + } + pr_debug("removing max3100 driver\n"); + uart_unregister_driver(&max3100_uart_driver); + uart_driver_registered = 0; + + mutex_unlock(&max3100s_lock); +} + +static int max3100_suspend(struct device *dev) +{ + struct max3100_port *s = dev_get_drvdata(dev); + u16 rx; + + dev_dbg(&s->spi->dev, "%s\n", __func__); + + disable_irq(s->port.irq); + + s->suspending = 1; + uart_suspend_port(&max3100_uart_driver, &s->port); + + /* no HW suspend, so do SW one */ + max3100_sr(s, MAX3100_WC | MAX3100_SHDN, &rx); + return 0; +} + +static int max3100_resume(struct device *dev) +{ + struct max3100_port *s = dev_get_drvdata(dev); + + dev_dbg(&s->spi->dev, "%s\n", __func__); + + uart_resume_port(&max3100_uart_driver, &s->port); + s->suspending = 0; + + enable_irq(s->port.irq); + + s->conf_commit = 1; + if (s->workqueue) + max3100_dowork(s); + + return 0; +} + +static DEFINE_SIMPLE_DEV_PM_OPS(max3100_pm_ops, max3100_suspend, max3100_resume); + +static const struct spi_device_id max3100_spi_id[] = { + { "max3100-ts" }, + { } +}; +MODULE_DEVICE_TABLE(spi, max3100_spi_id); + +static const struct of_device_id max3100_of_match[] = { + { .compatible = "technologic,max3100-ts" }, + { } +}; +MODULE_DEVICE_TABLE(of, max3100_of_match); + +static struct spi_driver max3100_driver = { + .driver = { + .name = "max3100-ts", + .of_match_table = max3100_of_match, + .pm = pm_sleep_ptr(&max3100_pm_ops), + }, + .probe = max3100_probe, + .remove = max3100_remove, + .id_table = max3100_spi_id, +}; + +module_spi_driver(max3100_driver); + +MODULE_DESCRIPTION("MAX3100 embeddedTS extended driver"); +MODULE_AUTHOR("Christian Pellegrin "); +MODULE_AUTHOR("Mark Featherston "); +MODULE_AUTHOR("Kris Bahnsen "); +MODULE_LICENSE("GPL"); From f34cb514f200e69c77025ac9f5774a5558c65eec Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Fri, 19 Sep 2025 20:56:05 +0000 Subject: [PATCH 238/244] ARM: dts: imx6ul-ts7100-3: support rev C TS-7100-3 Adds RS-485 termination resistor control via ioctl Signed-off-by: Kris Bahnsen --- .../arm/boot/dts/nxp/imx/imx6ul-ts7100-3.dtsi | 33 ++++++++----------- 1 file changed, 13 insertions(+), 20 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-3.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-3.dtsi index 24a0419607f1d..53b9226127ee1 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-3.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-3.dtsi @@ -9,24 +9,6 @@ gpio6 = &fpga_gpio1; gpio7 = &fpga_gpio2; }; - - led-controller { - compatible = "gpio-leds"; - - led-2 { - color = ; - function = LED_FUNCTION_INDICATOR; - gpios = <&fpga_gpio1 9 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-3 { - color = ; - function = LED_FUNCTION_INDICATOR; - gpios = <&fpga_gpio1 8 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; }; &ecspi3 { @@ -47,6 +29,12 @@ }; }; +&fpga_uart0 { + /* GPIO hog configures this pin */ + /* IO set to keeper since transceiver has PD */ + rs485-term-gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; +}; + /* CPU GPIO1: 209c000.gpio */ &gpio1 { gpio-line-names = @@ -100,7 +88,7 @@ gpio-line-names = "EN_EMMC_3V3#", "EN_ADC1_12V", "EN_ADC2_12V", "EN_ADC3_12V", "EN_ADC4_12V", "EN_USB_HOST_5V", "PHY_RESET#", "WIFI_RESET#", - "IO_RED_LED#", "IO_GREEN_LED#", "", "", + "", "", "", "", "EN_PROG_SILAB", "DIO_3_OUT", "EN_HSPWM", "EN_LSPWM"; }; @@ -124,6 +112,7 @@ * All GPIO should be 0x1b020 unless special * 0x1b020 == Hyst., 100k PU, 50 mA drive * 0x1a020 == no pull resistor + * 0x11020 == keeper * 0x13020 == 100k PD */ @@ -142,7 +131,7 @@ /* NIM_RESET */ MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b020 /* FPGA Spares */ - MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b020 + MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x11020 MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x1b020 MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b020 >; @@ -207,6 +196,8 @@ pinctrl-0 = <&pinctrl_uart2>; rts-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; linux,rs485-enabled-at-boot-time; + /* No configuration of pin needed, no pull in FPGA, relies on pull in xceiver */ + rs485-term-gpios = <&fpga_gpio1 8 GPIO_ACTIVE_HIGH>; dma-names = "", ""; status = "okay"; }; @@ -230,6 +221,8 @@ pinctrl-0 = <&pinctrl_uart5>; rts-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; linux,rs485-enabled-at-boot-time; + /* No configuration of pin needed, no pull in FPGA, relies on pull in xceiver */ + rs485-term-gpios = <&fpga_gpio1 9 GPIO_ACTIVE_HIGH>; dma-names = "", ""; status = "okay"; }; From db6a273b3786a4f523697c0f86498c73353ad26f Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Thu, 20 Nov 2025 14:34:06 -0700 Subject: [PATCH 239/244] ARM: dts: imx6ul-ts7100-z: Fix nimbel cts pin which should be an input Signed-off-by: Mark Featherston --- arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-z.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-z.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-z.dtsi index 293ec7af4109a..70bff7d6c18b2 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-z.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-z.dtsi @@ -220,7 +220,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart4>; status = "okay"; - rts-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + cts-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; }; &uart5 { From 69a932a6818f59d32bb4f6901f3b07abad4dcba5 Mon Sep 17 00:00:00 2001 From: Mark Featherston Date: Thu, 20 Nov 2025 14:33:56 -0700 Subject: [PATCH 240/244] ARM: dts: imx6ul-ts7100-3: Fix nimbel cts pin which should be an input Signed-off-by: Mark Featherston --- arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-3.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-3.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-3.dtsi index 53b9226127ee1..a835d6eaee7ad 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-3.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7100-3.dtsi @@ -213,7 +213,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart4>; status = "okay"; - rts-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + cts-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; }; &uart5 { From 7ce13cc578c3fc61ffa6eb51f067564c66a2e802 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Wed, 14 Jan 2026 19:08:31 +0000 Subject: [PATCH 241/244] drivers: bus: tspc104: updates for 6.18.y Signed-off-by: Kris Bahnsen --- drivers/bus/ts-pc104.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/bus/ts-pc104.c b/drivers/bus/ts-pc104.c index 3bee38f75a644..6390d552c3b8f 100644 --- a/drivers/bus/ts-pc104.c +++ b/drivers/bus/ts-pc104.c @@ -100,7 +100,7 @@ static int ts_pc104bus_init_pdata(struct platform_device *pdev, } static ssize_t isa_io8_read(struct file *filp, struct kobject *kobj, - struct bin_attribute *bin_attr, + const struct bin_attribute *bin_attr, char *buf, loff_t off, size_t count) { struct device *dev = container_of(kobj, struct device, kobj); @@ -117,7 +117,7 @@ static ssize_t isa_io8_read(struct file *filp, struct kobject *kobj, } static ssize_t isa_io8_write(struct file *filp, struct kobject *kobj, - struct bin_attribute *bin_attr, + const struct bin_attribute *bin_attr, char *buf, loff_t off, size_t count) { struct device *dev = container_of(kobj, struct device, kobj); @@ -134,7 +134,7 @@ static ssize_t isa_io8_write(struct file *filp, struct kobject *kobj, } static ssize_t isa_mem8_read(struct file *filp, struct kobject *kobj, - struct bin_attribute *bin_attr, + const struct bin_attribute *bin_attr, char *buf, loff_t off, size_t count) { struct device *dev = container_of(kobj, struct device, kobj); @@ -151,7 +151,7 @@ static ssize_t isa_mem8_read(struct file *filp, struct kobject *kobj, } static ssize_t isa_mem8_write(struct file *filp, struct kobject *kobj, - struct bin_attribute *bin_attr, + const struct bin_attribute *bin_attr, char *buf, loff_t off, size_t count) { struct device *dev = container_of(kobj, struct device, kobj); @@ -168,7 +168,7 @@ static ssize_t isa_mem8_write(struct file *filp, struct kobject *kobj, } static ssize_t isa_io16_read(struct file *filp, struct kobject *kobj, - struct bin_attribute *bin_attr, + const struct bin_attribute *bin_attr, char *buf, loff_t off, size_t count) { struct device *dev = container_of(kobj, struct device, kobj); @@ -187,7 +187,7 @@ static ssize_t isa_io16_read(struct file *filp, struct kobject *kobj, } static ssize_t isa_io16_write(struct file *filp, struct kobject *kobj, - struct bin_attribute *bin_attr, + const struct bin_attribute *bin_attr, char *buf, loff_t off, size_t count) { struct device *dev = container_of(kobj, struct device, kobj); @@ -207,7 +207,7 @@ static ssize_t isa_io16_write(struct file *filp, struct kobject *kobj, } static ssize_t isa_mem16_read(struct file *filp, struct kobject *kobj, - struct bin_attribute *bin_attr, + const struct bin_attribute *bin_attr, char *buf, loff_t off, size_t count) { struct device *dev = container_of(kobj, struct device, kobj); @@ -226,7 +226,7 @@ static ssize_t isa_mem16_read(struct file *filp, struct kobject *kobj, } static ssize_t isa_mem16_write(struct file *filp, struct kobject *kobj, - struct bin_attribute *bin_attr, + const struct bin_attribute *bin_attr, char *buf, loff_t off, size_t count) { struct device *dev = container_of(kobj, struct device, kobj); @@ -246,7 +246,7 @@ static ssize_t isa_mem16_write(struct file *filp, struct kobject *kobj, } static ssize_t isa_io16alt_read(struct file *filp, struct kobject *kobj, - struct bin_attribute *bin_attr, + const struct bin_attribute *bin_attr, char *buf, loff_t off, size_t count) { struct device *dev = container_of(kobj, struct device, kobj); @@ -265,7 +265,7 @@ static ssize_t isa_io16alt_read(struct file *filp, struct kobject *kobj, } static ssize_t isa_io16alt_write(struct file *filp, struct kobject *kobj, - struct bin_attribute *bin_attr, + const struct bin_attribute *bin_attr, char *buf, loff_t off, size_t count) { struct device *dev = container_of(kobj, struct device, kobj); @@ -285,7 +285,7 @@ static ssize_t isa_io16alt_write(struct file *filp, struct kobject *kobj, } static ssize_t isa_mem16alt_read(struct file *filp, struct kobject *kobj, - struct bin_attribute *bin_attr, + const struct bin_attribute *bin_attr, char *buf, loff_t off, size_t count) { struct device *dev = container_of(kobj, struct device, kobj); @@ -304,7 +304,7 @@ static ssize_t isa_mem16alt_read(struct file *filp, struct kobject *kobj, } static ssize_t isa_mem16alt_write(struct file *filp, struct kobject *kobj, - struct bin_attribute *bin_attr, + const struct bin_attribute *bin_attr, char *buf, loff_t off, size_t count) { struct device *dev = container_of(kobj, struct device, kobj); @@ -383,7 +383,7 @@ struct bin_attribute isa_mem16alt_attr = { .write = isa_mem16alt_write, }; -static struct bin_attribute *tsisa_sysfs_bin_attrs[] = { +static const struct bin_attribute *tsisa_sysfs_bin_attrs[] = { &isa_io8_attr, &isa_mem8_attr, &isa_io16_attr, From 3450d3f2103549ec393c01974b5842174384d988 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Wed, 14 Jan 2026 19:59:35 +0000 Subject: [PATCH 242/244] FIXME! This needs correct Fixes: tags commit 3bf8a0dd956b9e45ec1f52371958ceff189de231 Author: Michael D Peters Date: Mon Aug 11 10:14:56 2025 -0700 ARM: embeddedts: rename tssupervisor subsystem to tswizard (#225) * refactor(arch/arm/boot/dts/nxp/imx/): Rename supervisor to wizard * refactor(arch/arm/configs/): Rename supervisor to wizard * refactor(include/linux/mfd/): Rename supervisor to wizard * refactor(drivers/mfd/): Rename sueprvisor to wizard * refactor(drivers/power/reset/): Rename supervisor to wizard * refactor(drivers/iio/temperature/): Rename supervisor to wizard * refactor(drivers/iio/adc/): Rename supervisor to wizard * refactor(drivers/rtc): Rename supervisor to wizard commit ac2b0806325bf35207d92f3d1d96e1e78e5a705c Author: Mark Featherston Date: Wed Mar 8 08:54:19 2023 -0700 iio: tssupervisor-adc: Initial commit of embeddedTS supervisory microcontroller ADC Cleans up MODULE_DEVICE_TABLE call Signed-off-by: Kris Bahnsen --- drivers/iio/adc/tswizard_adc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iio/adc/tswizard_adc.c b/drivers/iio/adc/tswizard_adc.c index 4cbed7874f8a0..8a6a48da70df4 100644 --- a/drivers/iio/adc/tswizard_adc.c +++ b/drivers/iio/adc/tswizard_adc.c @@ -153,7 +153,7 @@ static const struct of_device_id tswizard_of_match[] = { { .compatible = "technologic,tswizard-adc", }, { } }; -MODULE_DEVICE_TABLE(of, tsadc_of_match); +MODULE_DEVICE_TABLE(of, tswizard_of_match); static struct platform_driver tsadc_driver = { .driver = { From 4f6f3b389b480380fd68b75c9649f89a78386066 Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Wed, 14 Jan 2026 20:31:37 +0000 Subject: [PATCH 243/244] gpio: ts7800v2: updates for 6.18.y Signed-off-by: Kris Bahnsen --- drivers/gpio/gpio-ts7800-v2.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/gpio/gpio-ts7800-v2.c b/drivers/gpio/gpio-ts7800-v2.c index 8c358dde65971..ccd59eb46f30c 100644 --- a/drivers/gpio/gpio-ts7800-v2.c +++ b/drivers/gpio/gpio-ts7800-v2.c @@ -367,7 +367,7 @@ static int ts7800v2_gpio_get(struct gpio_chip *chip, unsigned int offset) return !!(reg & bit); } -static void ts7800v2_gpio_set(struct gpio_chip *chip, unsigned int offset, +static int ts7800v2_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) { struct ts7800v2_gpio_priv *priv = to_gpio_ts7800v2(chip); @@ -380,7 +380,7 @@ static void ts7800v2_gpio_set(struct gpio_chip *chip, unsigned int offset, if (offset == 8) { /* SPI_MISO, read-only pin, can't set */ dev_info(priv->gpio_chip.parent, "error: DIO #%d, read-only pin, can't be set\n", priv->gpio_chip.base + offset); - return; + return -EINVAL; } reg_num = LCD_DIO_OUT; } else if (offset < 58) { /* pc/104 Row A */ @@ -389,7 +389,7 @@ static void ts7800v2_gpio_set(struct gpio_chip *chip, unsigned int offset, reg_num = ROW_B_DATA; } else if (offset < 101) { /* pc/104 Row C */ if (offset >= 104 && offset <= 107) { /* D[4..7], read-only pins */ - return; + return -EINVAL; } reg_num = ROW_C_DATA; } else if (offset < 116) { /* pc/104 Row D */ @@ -403,7 +403,7 @@ static void ts7800v2_gpio_set(struct gpio_chip *chip, unsigned int offset, } else if (offset == 120) { /* CPU_ACCESS_FPGA_FLASH */ reg_num = LCD_DIO_OUT; } else { - return; + return -EINVAL; } spin_lock_irqsave(&priv->lock, flags); @@ -414,6 +414,8 @@ static void ts7800v2_gpio_set(struct gpio_chip *chip, unsigned int offset, reg &= ~bit; writel(reg, priv->syscon + reg_num); spin_unlock_irqrestore(&priv->lock, flags); + + return 0; } static const struct gpio_chip template_chip = { From a7eff5b66bce91bec7eb3aa3d884f1cd15f1d89f Mon Sep 17 00:00:00 2001 From: Kris Bahnsen Date: Thu, 15 Jan 2026 19:29:32 +0000 Subject: [PATCH 244/244] ARM: boot: dts: embeddedTS treewide: normalize LED function Standardize on all of our platforms using POWER for green, STATUS for red, and then INDICATOR for all other colors. Signed-off-by: Kris Bahnsen --- arch/arm/boot/dts/nxp/imx/imx6ul-ts4100.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/imx6ul-ts7180.dts | 16 ++++++++-------- arch/arm/boot/dts/nxp/imx/imx6ul-ts7250v3.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/imx6ul-ts7553v2.dts | 2 +- arch/arm/boot/dts/nxp/mxs/imx28-ts7400v2.dts | 2 +- arch/arm/boot/dts/nxp/mxs/imx28-ts7670.dts | 2 +- arch/arm/boot/dts/nxp/mxs/imx28-ts7680.dts | 2 +- 7 files changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts4100.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-ts4100.dtsi index 3281e55e34061..c84da8db18094 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-ts4100.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts4100.dtsi @@ -30,7 +30,7 @@ led-1 { color = ; - function = LED_FUNCTION_INDICATOR; + function = LED_FUNCTION_STATUS; gpios = <&gpio6 28 GPIO_ACTIVE_LOW>; default-state = "off"; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7180.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7180.dts index 868783dfb2084..fb0a2f4155908 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7180.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7180.dts @@ -44,26 +44,26 @@ compatible = "gpio-leds"; led-0 { - color = ; - function = LED_FUNCTION_INDICATOR; - gpios = <&gpio4 23 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-1 { color = ; function = LED_FUNCTION_POWER; gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; default-state = "on"; }; - led-2 { + led-1 { color = ; function = LED_FUNCTION_STATUS; gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; default-state = "off"; }; + led-2 { + color = ; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpio4 23 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + led-3 { color = ; function = LED_FUNCTION_INDICATOR; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7250v3.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7250v3.dtsi index 3d113bd5e26ce..0e4d6c1f6b50f 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7250v3.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7250v3.dtsi @@ -59,7 +59,7 @@ led-1 { color = ; - function = LED_FUNCTION_INDICATOR; + function = LED_FUNCTION_STATUS; gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; default-state = "off"; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7553v2.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7553v2.dts index 6d8035cfc84f2..a49d4fe73530a 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-ts7553v2.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ts7553v2.dts @@ -35,7 +35,7 @@ led-1 { color = ; - function = LED_FUNCTION_INDICATOR; + function = LED_FUNCTION_STATUS; gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; default-state = "off"; }; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-ts7400v2.dts b/arch/arm/boot/dts/nxp/mxs/imx28-ts7400v2.dts index dd3410eaca443..d9dad4222e0f5 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-ts7400v2.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-ts7400v2.dts @@ -71,7 +71,7 @@ led-1 { color = ; - function = LED_FUNCTION_INDICATOR; + function = LED_FUNCTION_STATUS; gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; default-state = "off"; }; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-ts7670.dts b/arch/arm/boot/dts/nxp/mxs/imx28-ts7670.dts index 83801a052dbfc..f331bc8f4222c 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-ts7670.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-ts7670.dts @@ -70,7 +70,7 @@ led-1 { color = ; - function = LED_FUNCTION_INDICATOR; + function = LED_FUNCTION_STATUS; gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; default-state = "off"; }; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-ts7680.dts b/arch/arm/boot/dts/nxp/mxs/imx28-ts7680.dts index cfce0d2b7dc4d..d31eba215f441 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-ts7680.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-ts7680.dts @@ -92,7 +92,7 @@ led-1 { color = ; - function = LED_FUNCTION_INDICATOR; + function = LED_FUNCTION_STATUS; gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; default-state = "off"; };