No support for Apple Silicon and fails on virtualized x86_64 (EC2)

[jakeaglass]

I'm unable to get this to run successfully on Apple Silicon because of an illegal hardware instruction error, which comes from the use of vpcmpistri, an AVX instruction not supported by Apple Rosetta. I've tried using dub with LDC2, GDC, and DMD to build with the same issue at runtime.

Here's the problematic assembly from lldb:

Process 25914 stopped
* thread #1, queue = 'com.apple.main-thread', stop reason = EXC_BAD_INSTRUCTION (code=EXC_I386_INVOP, subcode=0x0)
    frame #0: 0x000000010000d275 app`_D4fast7parsing__T10vpcmpistriTaVyAaa2_225cVEQBrQBp9Operationi0VEQClQCj8Polarityi0Vbi0ZQCrFNaNbNiKPxaZv(p=0x000000030456ae38) at parsing.d:817
   814                                          movdqu      XMM0, [RAX];
   815                                          mov         RAX, [RDI];
   816                                  L1:
-> 817                                          vpcmpistri  XMM0, [RAX], mode;
   818                                          add         RAX, 16;
   819                                          cmp         ECX, 16;
   820                                          je          L1;

I have a use case for parsing JSON as fast as possible to sequentially load a massive pile of JSON files into a processing queue, so I decided to try this on an Xeon EC2 instance (which does support AVX-512) – the same line of assembly throws a SIGSEGV on an m5.xlarge EC2 running Ubuntu with the following trace:

* thread #1, name = 'historical-load', stop reason = signal SIGSEGV: address access protected (fault address: 0x7ffff6d2e000)
    frame #0: 0x000055555568ac21 app`_D4fast7parsing__T10vpcmpistriTaVyAaa3_227b7dVEQBtQBr9Operationi0VEQCnQCl8Polarityi0Vbi0ZQCtFNaNbNiKPxaZv(p=0x00007fffffffdcf8) at parsing.d:817
   814                                          movdqu      XMM0, [RAX];
   815                                          mov         RAX, [RDI];
   816                                  L1:
-> 817                                          vpcmpistri  XMM0, [RAX], mode;
   818                                          add         RAX, 16;
   819                                          cmp         ECX, 16;
   820                                          je          L1;

I also tried this on an m5.metal EC2 instance and got the same result.

My simple test implementation:

auto parsedJSON = parseJSON(`{"now":10}`);
writeln(parsedJSON.singleKey!"now");

Is there any plan to provide broader CPU architecture support?

[mleise]

Hello Jake,

Unfortunately I'm no longer developing the library, but that was a good find. I'm 100% sure when I wrote that code, I didn't realize the v prefix uses an AVX encoding of the pcmpistri instruction. It was supposed to be all SSE4.2. It is only used explicitly in the code for DMD though, so I wonder if for GDC and LDC2 you can disable AVX and they would emit the SSE4.2 version instead.
In any case, if the m5.xlarge instance is running on Skylake 8175M or Cascade Lake 8259CL they should in theory support both versions anyways, unless Amazon disables AVX, in which case only the SSE4.2 variant works.