diff --git a/ADL/events/alderlake_goldencove_core.json b/ADL/events/alderlake_goldencove_core.json index 6e5e0bf4..3b4bde02 100644 --- a/ADL/events/alderlake_goldencove_core.json +++ b/ADL/events/alderlake_goldencove_core.json @@ -1,9 +1,9 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.35", - "DatePublished": "10/17/2025", - "Version": "1.35", + "Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.36", + "DatePublished": "11/17/2025", + "Version": "1.36", "Legend": "" }, "Events": [ @@ -3132,6 +3132,56 @@ "PDISTCounter": "NA", "Speculative": "1" }, + { + "EventCode": "0x83", + "UMask": "0x08", + "EventName": "ICACHE_TAG.STALLS_ISB", + "BriefDescription": "ICACHE_TAG.STALLS_ISB", + "PublicDescription": "ICACHE_TAG.STALLS_ISB", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x83", + "UMask": "0x10", + "EventName": "ICACHE_TAG.STALLS_INUSE", + "BriefDescription": "ICACHE_TAG.STALLS_INUSE", + "PublicDescription": "ICACHE_TAG.STALLS_INUSE", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, { "EventCode": "0x87", "UMask": "0x01", diff --git a/ADL/events/alderlake_gracemont_core.json b/ADL/events/alderlake_gracemont_core.json index 9041fb38..7cfefad5 100644 --- a/ADL/events/alderlake_gracemont_core.json +++ b/ADL/events/alderlake_gracemont_core.json @@ -1,9 +1,9 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.35", - "DatePublished": "10/17/2025", - "Version": "1.35", + "Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.36", + "DatePublished": "11/17/2025", + "Version": "1.36", "Legend": "" }, "Events": [ @@ -61,7 +61,7 @@ "EventCode": "0x00", "UMask": "0x02", "EventName": "CPU_CLK_UNHALTED.THREAD", - "BriefDescription": "Counts the number of unhalted core clock cycles. (Fixed event)", + "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.CORE]", "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1.", "Counter": "Fixed counter 1", "PEBScounters": "33", @@ -861,7 +861,7 @@ "EventCode": "0x3c", "UMask": "0x00", "EventName": "CPU_CLK_UNHALTED.THREAD_P", - "BriefDescription": "Counts the number of unhalted core clock cycles.", + "BriefDescription": "Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.CORE_P]", "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses a programmable general purpose performance counter.", "Counter": "0,1,2,3,4,5", "PEBScounters": "0,1,2,3,4,5", @@ -3082,6 +3082,31 @@ "PDISTCounter": "NA", "Speculative": "0" }, + { + "EventCode": "0xc4", + "UMask": "0xef", + "EventName": "BR_INST_RETIRED.INDIRECT_JMP", + "BriefDescription": "Counts the number of near indirect JMP branch instructions retired.", + "PublicDescription": "Counts the number of near indirect JMP branch instructions retired.", + "Counter": "0,1,2,3,4,5", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, { "EventCode": "0xc4", "UMask": "0xf7", @@ -3457,6 +3482,31 @@ "PDISTCounter": "NA", "Speculative": "0" }, + { + "EventCode": "0xc5", + "UMask": "0xef", + "EventName": "BR_MISP_RETIRED.INDIRECT_JMP", + "BriefDescription": "Counts the number of mispredicted near indirect JMP branch instructions retired.", + "PublicDescription": "Counts the number of mispredicted near indirect JMP branch instructions retired.", + "Counter": "0,1,2,3,4,5", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, { "EventCode": "0xc5", "UMask": "0xf7", @@ -3614,12 +3664,12 @@ "BriefDescription": "Counts the number of cycles any of the two integer dividers are active.", "PublicDescription": "Counts the number of cycles any of the two integer dividers are active.", "Counter": "0,1,2,3,4,5", - "PEBScounters": "NA", + "PEBScounters": "0,1,2,3,4,5", "SampleAfterValue": "1000003", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "0", - "CollectPEBSRecord": "0", + "CollectPEBSRecord": "2", "TakenAlone": "0", "CounterMask": "1", "Invert": "0", @@ -3664,12 +3714,12 @@ "BriefDescription": "Counts the number of cycles when any of the floating point or integer dividers are active.", "PublicDescription": "Counts the number of cycles when any of the floating point or integer dividers are active.", "Counter": "0,1,2,3,4,5", - "PEBScounters": "NA", + "PEBScounters": "0,1,2,3,4,5", "SampleAfterValue": "1000003", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "0", - "CollectPEBSRecord": "0", + "CollectPEBSRecord": "2", "TakenAlone": "0", "CounterMask": "1", "Invert": "0", @@ -3786,8 +3836,8 @@ "EventCode": "0xd0", "UMask": "0x05", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4", - "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 4 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", - "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 4 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 4. Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 4. Only counts with PEBS enabled.", "Counter": "0,1", "PEBScounters": "0,1", "SampleAfterValue": "1000003", @@ -3811,8 +3861,8 @@ "EventCode": "0xd0", "UMask": "0x05", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128", - "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 128 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", - "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 128 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 128. Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 128. Only counts with PEBS enabled.", "Counter": "0,1", "PEBScounters": "0,1", "SampleAfterValue": "1000003", @@ -3836,8 +3886,8 @@ "EventCode": "0xd0", "UMask": "0x05", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64", - "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 64 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", - "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 64 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 64. Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 64. Only counts with PEBS enabled.", "Counter": "0,1", "PEBScounters": "0,1", "SampleAfterValue": "1000003", @@ -3861,8 +3911,8 @@ "EventCode": "0xd0", "UMask": "0x05", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32", - "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 32 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", - "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 32 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 32. Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 32. Only counts with PEBS enabled.", "Counter": "0,1", "PEBScounters": "0,1", "SampleAfterValue": "1000003", @@ -3886,8 +3936,8 @@ "EventCode": "0xd0", "UMask": "0x05", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16", - "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 16 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", - "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 16 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 16. Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 16. Only counts with PEBS enabled.", "Counter": "0,1", "PEBScounters": "0,1", "SampleAfterValue": "1000003", @@ -3911,8 +3961,8 @@ "EventCode": "0xd0", "UMask": "0x05", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8", - "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 8 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", - "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 8 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 8. Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 8. Only counts with PEBS enabled.", "Counter": "0,1", "PEBScounters": "0,1", "SampleAfterValue": "1000003", @@ -3936,8 +3986,8 @@ "EventCode": "0xd0", "UMask": "0x05", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512", - "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 512 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", - "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 512 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 512. Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 512. Only counts with PEBS enabled.", "Counter": "0,1", "PEBScounters": "0,1", "SampleAfterValue": "1000003", @@ -3961,8 +4011,8 @@ "EventCode": "0xd0", "UMask": "0x05", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256", - "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 256 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", - "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 256 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 256. Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 256. Only counts with PEBS enabled.", "Counter": "0,1", "PEBScounters": "0,1", "SampleAfterValue": "1000003", @@ -3986,8 +4036,8 @@ "EventCode": "0xd0", "UMask": "0x06", "EventName": "MEM_UOPS_RETIRED.STORE_LATENCY", - "BriefDescription": "Counts the number of stores uops retired. Counts with or without PEBS enabled.", - "PublicDescription": "Counts the number of stores uops retired. Counts with or without PEBS enabled. If PEBS is enabled and a PEBS record is generated, will populate PEBS Latency and PEBS Data Source fields accordingly.", + "BriefDescription": "Counts the number of stores uops retired.", + "PublicDescription": "Counts the number of stores uops retired.", "Counter": "0,1,2,3,4,5", "PEBScounters": "0,1,2,3,4,5", "SampleAfterValue": "1000003", @@ -4482,6 +4532,106 @@ "PDISTCounter": "NA", "Speculative": "0" }, + { + "EventCode": "0xe0", + "UMask": "0x02", + "EventName": "MISC_RETIRED1.LFENCE", + "BriefDescription": "Counts the number of LFENCE instructions retired.", + "PublicDescription": "Counts the number of LFENCE instructions retired.", + "Counter": "0,1,2,3,4,5", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xe0", + "UMask": "0xff", + "EventName": "MISC_RETIRED1.CL_INST", + "BriefDescription": "Counts the number of CLFLUSH, CLWB, and CLDEMOTE instructions retired.", + "PublicDescription": "Counts the number of CLFLUSH, CLWB, and CLDEMOTE instructions retired.", + "Counter": "0,1,2,3,4,5", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xe1", + "UMask": "0x10", + "EventName": "MISC_RETIRED2.KEYLOCKER_ACCESS", + "BriefDescription": "Counts the number of accesses to KeyLocker cache.", + "PublicDescription": "Counts the number of accesses to KeyLocker cache.", + "Counter": "0,1,2,3,4,5", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xe1", + "UMask": "0x11", + "EventName": "MISC_RETIRED2.KEYLOCKER_MISS", + "BriefDescription": "Counts the number of misses to KeyLocker cache.", + "PublicDescription": "Counts the number of misses to KeyLocker cache.", + "Counter": "0,1,2,3,4,5", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, { "EventCode": "0xe4", "UMask": "0x01", diff --git a/ADL/events/alderlake_uncore.json b/ADL/events/alderlake_uncore.json index dc45ea20..2bf7db3b 100644 --- a/ADL/events/alderlake_uncore.json +++ b/ADL/events/alderlake_uncore.json @@ -1,9 +1,9 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.35", - "DatePublished": "10/17/2025", - "Version": "1.35", + "Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.36", + "DatePublished": "11/17/2025", + "Version": "1.36", "Legend": "" }, "Events": [ diff --git a/ADL/events/alderlake_uncore_experimental.json b/ADL/events/alderlake_uncore_experimental.json index 7b3ebc9e..0cc62d72 100644 --- a/ADL/events/alderlake_uncore_experimental.json +++ b/ADL/events/alderlake_uncore_experimental.json @@ -1,9 +1,9 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.35", - "DatePublished": "10/17/2025", - "Version": "1.35", + "Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.36", + "DatePublished": "11/17/2025", + "Version": "1.36", "Legend": "" }, "Events": [ diff --git a/ARL/events/arrowlake_crestmont_core.json b/ARL/events/arrowlake_crestmont_core.json index 3589d9cb..400305ae 100644 --- a/ARL/events/arrowlake_crestmont_core.json +++ b/ARL/events/arrowlake_crestmont_core.json @@ -1,9 +1,9 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.14", - "DatePublished": "10/17/2025", - "Version": "1.14", + "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.15", + "DatePublished": "11/20/2025", + "Version": "1.15", "Legend": "" }, "Events": [ @@ -66,8 +66,8 @@ "UMask": "0x02", "UMaskExt": "0x00", "EventName": "CPU_CLK_UNHALTED.THREAD", - "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles", - "PublicDescription": "Fixed Counter: Counts the number of unhalted core clock cycles", + "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.CORE]", + "PublicDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.CORE]", "Counter": "Fixed counter 1", "PEBScounters": "33", "SampleAfterValue": "2000003", @@ -1033,6 +1033,33 @@ "PDISTCounter": "NA", "Speculative": "1" }, + { + "EventCode": "0x34", + "UMask": "0x50", + "UMaskExt": "0x00", + "EventName": "MEM_BOUND_STALLS_LOAD.LLC_MISS_LOCALMEM", + "BriefDescription": "Counts the number of unhalted cycles when the core is stalled to a demand load miss and the data was provided from an unknown source. If the core has access to an L3 cache, an LLC miss refers to an L3 cache miss, otherwise it is an L2 cache miss.", + "PublicDescription": "Counts the number of unhalted cycles when the core is stalled to a demand load miss and the data was provided from an unknown source. If the core has access to an L3 cache, an LLC miss refers to an L3 cache miss, otherwise it is an L2 cache miss.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, { "EventCode": "0x34", "UMask": "0x78", @@ -1168,6 +1195,33 @@ "PDISTCounter": "NA", "Speculative": "1" }, + { + "EventCode": "0x35", + "UMask": "0x7f", + "UMaskExt": "0x00", + "EventName": "MEM_BOUND_STALLS_IFETCH.ALL", + "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an instruction cache or TLB miss.", + "PublicDescription": "Counts the number of unhalted cycles when the core is stalled due to an instruction cache or TLB miss.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, { "EventCode": "0x3c", "UMask": "0x00", @@ -2491,6 +2545,33 @@ "PDISTCounter": "NA", "Speculative": "0" }, + { + "EventCode": "0xc3", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "MACHINE_CLEARS.ANY", + "BriefDescription": "Counts the total number of machine clears for any reason including, but not limited to, memory ordering, memory disambiguation, SMC, and FP assist.", + "PublicDescription": "Counts the total number of machine clears for any reason including, but not limited to, memory ordering, memory disambiguation, SMC, and FP assist.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "20003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, { "EventCode": "0xc3", "UMask": "0x01", @@ -3741,12 +3822,12 @@ "BriefDescription": "Counts the number of cycles when any of the floating point dividers are active.", "PublicDescription": "Counts the number of cycles when any of the floating point dividers are active.", "Counter": "0,1,2,3,4,5,6,7", - "PEBScounters": "NA", + "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "1000003", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "0", - "CollectPEBSRecord": "0", + "CollectPEBSRecord": "2", "TakenAlone": "0", "CounterMask": "1", "Invert": "0", @@ -3768,12 +3849,12 @@ "BriefDescription": "Counts the number of cycles when any of the floating point or integer dividers are active.", "PublicDescription": "Counts the number of cycles when any of the floating point or integer dividers are active.", "Counter": "0,1,2,3,4,5,6,7", - "PEBScounters": "NA", + "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "1000003", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "0", - "CollectPEBSRecord": "0", + "CollectPEBSRecord": "2", "TakenAlone": "0", "CounterMask": "1", "Invert": "0", @@ -3792,8 +3873,8 @@ "UMask": "0x05", "UMaskExt": "0x00", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 8. Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 8. Only counts with PEBS enabled.", "Counter": "0,1", "PEBScounters": "0,1", "SampleAfterValue": "1000003", @@ -3819,8 +3900,8 @@ "UMask": "0x05", "UMaskExt": "0x00", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 64. Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 64. Only counts with PEBS enabled.", "Counter": "0,1", "PEBScounters": "0,1", "SampleAfterValue": "1000003", @@ -3846,8 +3927,8 @@ "UMask": "0x05", "UMaskExt": "0x00", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 512. Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 512. Only counts with PEBS enabled.", "Counter": "0,1", "PEBScounters": "0,1", "SampleAfterValue": "1000003", @@ -3873,8 +3954,8 @@ "UMask": "0x05", "UMaskExt": "0x00", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 4. Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 4. Only counts with PEBS enabled.", "Counter": "0,1", "PEBScounters": "0,1", "SampleAfterValue": "1000003", @@ -3900,8 +3981,8 @@ "UMask": "0x05", "UMaskExt": "0x00", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 32. Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 32. Only counts with PEBS enabled.", "Counter": "0,1", "PEBScounters": "0,1", "SampleAfterValue": "1000003", @@ -3927,8 +4008,8 @@ "UMask": "0x05", "UMaskExt": "0x00", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 256. Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 256. Only counts with PEBS enabled.", "Counter": "0,1", "PEBScounters": "0,1", "SampleAfterValue": "1000003", @@ -3954,8 +4035,8 @@ "UMask": "0x05", "UMaskExt": "0x00", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 16. Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 16. Only counts with PEBS enabled.", "Counter": "0,1", "PEBScounters": "0,1", "SampleAfterValue": "1000003", @@ -3981,8 +4062,8 @@ "UMask": "0x05", "UMaskExt": "0x00", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 128. Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 128. Only counts with PEBS enabled.", "Counter": "0,1", "PEBScounters": "0,1", "SampleAfterValue": "1000003", @@ -4008,8 +4089,8 @@ "UMask": "0x05", "UMaskExt": "0x00", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_2048", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 2048. Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 2048. Only counts with PEBS enabled.", "Counter": "0,1", "PEBScounters": "0,1", "SampleAfterValue": "1000003", @@ -4035,8 +4116,8 @@ "UMask": "0x05", "UMaskExt": "0x00", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_1024", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 1024. Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 1024. Only counts with PEBS enabled.", "Counter": "0,1", "PEBScounters": "0,1", "SampleAfterValue": "1000003", @@ -4062,8 +4143,8 @@ "UMask": "0x06", "UMaskExt": "0x00", "EventName": "MEM_UOPS_RETIRED.STORE_LATENCY", - "BriefDescription": "Counts the number of stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES", - "PublicDescription": "Counts the number of stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES", + "BriefDescription": "Counts the number of stores uops retired.", + "PublicDescription": "Counts the number of stores uops retired.", "Counter": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "1000003", @@ -4516,6 +4597,60 @@ "PDISTCounter": "NA", "Speculative": "0" }, + { + "EventCode": "0xe0", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "MISC_RETIRED1.LFENCE", + "BriefDescription": "Counts the number of LFENCE instructions retired.", + "PublicDescription": "Counts the number of LFENCE instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xe0", + "UMask": "0xff", + "UMaskExt": "0x00", + "EventName": "MISC_RETIRED1.CL_INST", + "BriefDescription": "Counts the number of CLFLUSH, CLWB, and CLDEMOTE instructions retired.", + "PublicDescription": "Counts the number of CLFLUSH, CLWB, and CLDEMOTE instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, { "EventCode": "0xe4", "UMask": "0x01", diff --git a/ARL/events/arrowlake_lioncove_core.json b/ARL/events/arrowlake_lioncove_core.json index cd2a2bcf..fbd6aed2 100644 --- a/ARL/events/arrowlake_lioncove_core.json +++ b/ARL/events/arrowlake_lioncove_core.json @@ -1,9 +1,9 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.14", - "DatePublished": "10/17/2025", - "Version": "1.14", + "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.15", + "DatePublished": "11/20/2025", + "Version": "1.15", "Legend": "" }, "Events": [ @@ -3193,6 +3193,60 @@ "PDISTCounter": "NA", "Speculative": "1" }, + { + "EventCode": "0x83", + "UMask": "0x08", + "UMaskExt": "0x00", + "EventName": "ICACHE_TAG.STALLS_ISB", + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache ISB-full", + "PublicDescription": "Cycles where a code fetch is stalled due to L1 instruction cache ISB-full", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x83", + "UMask": "0x10", + "UMaskExt": "0x00", + "EventName": "ICACHE_TAG.STALLS_INUSE", + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache In use-full", + "PublicDescription": "Cycles where a code fetch is stalled due to L1 instruction cache In use-full", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, { "EventCode": "0x87", "UMask": "0x01", diff --git a/ARL/events/arrowlake_skymont_core.json b/ARL/events/arrowlake_skymont_core.json index d8a69b56..ba03111c 100644 --- a/ARL/events/arrowlake_skymont_core.json +++ b/ARL/events/arrowlake_skymont_core.json @@ -1,9 +1,9 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.14", - "DatePublished": "10/17/2025", - "Version": "1.14", + "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.15", + "DatePublished": "11/20/2025", + "Version": "1.15", "Legend": "" }, "Events": [ @@ -66,8 +66,8 @@ "UMask": "0x02", "UMaskExt": "0x00", "EventName": "CPU_CLK_UNHALTED.THREAD", - "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles.", - "PublicDescription": "Fixed Counter: Counts the number of unhalted core clock cycles.", + "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.CORE]", + "PublicDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.CORE]", "Counter": "Fixed counter 1", "PEBScounters": "33", "SampleAfterValue": "2000003", @@ -1924,6 +1924,60 @@ "PDISTCounter": "NA", "Speculative": "1" }, + { + "EventCode": "0x34", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "MEM_BOUND_STALLS_LOAD.LLC_HIT_NOSNOOP", + "BriefDescription": "Counts the number of unhalted cycles that the core is stalled due to a demand load miss which hit in the LLC, no snoop was required, and the LLC provided data", + "PublicDescription": "Counts the number of unhalted cycles that the core is stalled due to a demand load miss which hit in the LLC, no snoop was required, and the LLC provided data", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x34", + "UMask": "0x04", + "UMaskExt": "0x00", + "EventName": "MEM_BOUND_STALLS_LOAD.LLC_HIT_SNOOP", + "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which hit in the LLC, a snoop was required, the snoop misses or the snoop hits but no fwd. LLC provides the data", + "PublicDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which hit in the LLC, a snoop was required, the snoop misses or the snoop hits but no fwd. LLC provides the data", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, { "EventCode": "0x34", "UMask": "0x06", @@ -1951,6 +2005,33 @@ "PDISTCounter": "NA", "Speculative": "1" }, + { + "EventCode": "0x34", + "UMask": "0x50", + "UMaskExt": "0x00", + "EventName": "MEM_BOUND_STALLS_LOAD.LLC_MISS_LOCALMEM", + "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which missed all the caches. DRAM, MMIO or other LOCAL memory type provides the data", + "PublicDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which missed all the caches. DRAM, MMIO or other LOCAL memory type provides the data", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, { "EventCode": "0x34", "UMask": "0x78", @@ -2935,7 +3016,7 @@ "SampleAfterValue": "1000003", "MSRIndex": "0x00", "MSRValue": "0x00", - "Precise": "1", + "Precise": "0", "CollectPEBSRecord": "2", "TakenAlone": "0", "CounterMask": "0", @@ -6144,12 +6225,12 @@ "BriefDescription": "Counts the number of cycles when any of the integer dividers are active.", "PublicDescription": "Counts the number of cycles when any of the integer dividers are active.", "Counter": "0,1,2,3,4,5,6,7", - "PEBScounters": "NA", + "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "1000003", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "0", - "CollectPEBSRecord": "0", + "CollectPEBSRecord": "2", "TakenAlone": "0", "CounterMask": "1", "Invert": "0", @@ -6198,12 +6279,12 @@ "BriefDescription": "Counts the number of cycles when any of the floating point dividers are active.", "PublicDescription": "Counts the number of cycles when any of the floating point dividers are active.", "Counter": "0,1,2,3,4,5,6,7", - "PEBScounters": "NA", + "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "1000003", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "0", - "CollectPEBSRecord": "0", + "CollectPEBSRecord": "2", "TakenAlone": "0", "CounterMask": "1", "Invert": "0", @@ -6225,12 +6306,12 @@ "BriefDescription": "Counts the number of cycles when any of the floating point or integer dividers are active.", "PublicDescription": "Counts the number of cycles when any of the floating point or integer dividers are active.", "Counter": "0,1,2,3,4,5,6,7", - "PEBScounters": "NA", + "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "1000003", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "0", - "CollectPEBSRecord": "0", + "CollectPEBSRecord": "2", "TakenAlone": "0", "CounterMask": "1", "Invert": "0", @@ -6303,8 +6384,8 @@ "UMask": "0x05", "UMaskExt": "0x00", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 8.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 8.", "Counter": "0,1", "PEBScounters": "0,1", "SampleAfterValue": "200003", @@ -6330,8 +6411,8 @@ "UMask": "0x05", "UMaskExt": "0x00", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 64.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 64.", "Counter": "0,1", "PEBScounters": "0,1", "SampleAfterValue": "200003", @@ -6357,8 +6438,8 @@ "UMask": "0x05", "UMaskExt": "0x00", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 512.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 512.", "Counter": "0,1", "PEBScounters": "0,1", "SampleAfterValue": "200003", @@ -6384,8 +6465,8 @@ "UMask": "0x05", "UMaskExt": "0x00", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 4.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 4.", "Counter": "0,1", "PEBScounters": "0,1", "SampleAfterValue": "200003", @@ -6411,8 +6492,8 @@ "UMask": "0x05", "UMaskExt": "0x00", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 32.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 32.", "Counter": "0,1", "PEBScounters": "0,1", "SampleAfterValue": "200003", @@ -6438,8 +6519,8 @@ "UMask": "0x05", "UMaskExt": "0x00", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 256.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 256.", "Counter": "0,1", "PEBScounters": "0,1", "SampleAfterValue": "200003", @@ -6465,8 +6546,8 @@ "UMask": "0x05", "UMaskExt": "0x00", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 16.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 16.", "Counter": "0,1", "PEBScounters": "0,1", "SampleAfterValue": "200003", @@ -6492,8 +6573,8 @@ "UMask": "0x05", "UMaskExt": "0x00", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 128.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 128.", "Counter": "0,1", "PEBScounters": "0,1", "SampleAfterValue": "200003", @@ -6519,8 +6600,8 @@ "UMask": "0x06", "UMaskExt": "0x00", "EventName": "MEM_UOPS_RETIRED.STORE_LATENCY", - "BriefDescription": "Counts the number of stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES", - "PublicDescription": "Counts the number of stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES", + "BriefDescription": "Counts the number of stores uops retired.", + "PublicDescription": "Counts the number of stores uops retired.", "Counter": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "200003", @@ -6919,6 +7000,33 @@ "PDISTCounter": "NA", "Speculative": "0" }, + { + "EventCode": "0xd1", + "UMask": "0x04", + "UMaskExt": "0x00", + "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT_NO_SNOOP", + "BriefDescription": "Counts the number of load ops retired that hit in the L3 cache in which no snoop was required", + "PublicDescription": "Counts the number of load ops retired that hit in the L3 cache in which no snoop was required", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, { "EventCode": "0xd1", "UMask": "0x1c", @@ -7027,6 +7135,33 @@ "PDISTCounter": "NA", "Speculative": "0" }, + { + "EventCode": "0xd4", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "MEM_LOAD_UOPS_MISC_RETIRED.LOCAL_DRAM", + "BriefDescription": "Counts the number of retired load ops with an unknown source", + "PublicDescription": "Counts the number of retired load ops with an unknown source", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, { "EventCode": "0xe0", "UMask": "0x00", diff --git a/ARL/events/arrowlake_uncore.json b/ARL/events/arrowlake_uncore.json index eeb402f0..25f8e716 100644 --- a/ARL/events/arrowlake_uncore.json +++ b/ARL/events/arrowlake_uncore.json @@ -1,9 +1,9 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.14", - "DatePublished": "10/17/2025", - "Version": "1.14", + "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.15", + "DatePublished": "11/20/2025", + "Version": "1.15", "Legend": "" }, "Events": [ diff --git a/ARL/events/arrowlake_uncore_experimental.json b/ARL/events/arrowlake_uncore_experimental.json index b70e3696..0ddaf7cf 100644 --- a/ARL/events/arrowlake_uncore_experimental.json +++ b/ARL/events/arrowlake_uncore_experimental.json @@ -1,9 +1,9 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.14", - "DatePublished": "10/17/2025", - "Version": "1.14", + "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.15", + "DatePublished": "11/20/2025", + "Version": "1.15", "Legend": "" }, "Events": [ diff --git a/EMR/events/emeraldrapids_core.json b/EMR/events/emeraldrapids_core.json index adbf82fe..1a3c2899 100644 --- a/EMR/events/emeraldrapids_core.json +++ b/EMR/events/emeraldrapids_core.json @@ -1,9 +1,9 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for 5th Generation Intel(R) Xeon(R) Processor Scalable Family - V1.20", - "DatePublished": "09/16/2025", - "Version": "1.20", + "Info": "Performance Monitoring Events for 5th Generation Intel(R) Xeon(R) Processor Scalable Family - V1.21", + "DatePublished": "11/20/2025", + "Version": "1.21", "Legend": "" }, "Events": [ @@ -3032,6 +3032,56 @@ "PDISTCounter": "NA", "Speculative": "1" }, + { + "EventCode": "0x83", + "UMask": "0x08", + "EventName": "ICACHE_TAG.STALLS_ISB", + "BriefDescription": "ICACHE_TAG.STALLS_ISB", + "PublicDescription": "ICACHE_TAG.STALLS_ISB", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x83", + "UMask": "0x10", + "EventName": "ICACHE_TAG.STALLS_INUSE", + "BriefDescription": "ICACHE_TAG.STALLS_INUSE", + "PublicDescription": "ICACHE_TAG.STALLS_INUSE", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, { "EventCode": "0x87", "UMask": "0x01", @@ -7840,7 +7890,7 @@ "PublicDescription": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM", "Counter": "0,1,2,3", "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", + "SampleAfterValue": "100007", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "1", @@ -7865,7 +7915,7 @@ "PublicDescription": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM", "Counter": "0,1,2,3", "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", + "SampleAfterValue": "100007", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "1", diff --git a/EMR/events/emeraldrapids_uncore.json b/EMR/events/emeraldrapids_uncore.json index e85ccbf0..ed2842df 100644 --- a/EMR/events/emeraldrapids_uncore.json +++ b/EMR/events/emeraldrapids_uncore.json @@ -1,9 +1,9 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for 5th Generation Intel(R) Xeon(R) Processor Scalable Family - V1.20", - "DatePublished": "09/16/2025", - "Version": "1.20", + "Info": "Performance Monitoring Events for 5th Generation Intel(R) Xeon(R) Processor Scalable Family - V1.21", + "DatePublished": "11/20/2025", + "Version": "1.21", "Legend": "" }, "Events": [ diff --git a/EMR/events/emeraldrapids_uncore_experimental.json b/EMR/events/emeraldrapids_uncore_experimental.json index d7bbfa14..4fbdbc59 100644 --- a/EMR/events/emeraldrapids_uncore_experimental.json +++ b/EMR/events/emeraldrapids_uncore_experimental.json @@ -1,9 +1,9 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for 5th Generation Intel(R) Xeon(R) Processor Scalable Family - V1.20", - "DatePublished": "09/16/2025", - "Version": "1.20", + "Info": "Performance Monitoring Events for 5th Generation Intel(R) Xeon(R) Processor Scalable Family - V1.21", + "DatePublished": "11/20/2025", + "Version": "1.21", "Legend": "" }, "Events": [ @@ -6334,7 +6334,7 @@ "UMaskExt": "0x00000000", "EventName": "UNC_CHA_SNOOP_RESP.RSPIFWD", "BriefDescription": "RspIFwd Snoop Responses Received", - "PublicDescription": "Counts when a a transaction with the opcode type RspIFwd Snoop Response was received which indicates a remote caching agent forwarded the data and the requesting agent is able to acquire the data in E (Exclusive) or M (modified) states. This is commonly returned with RFO (the Read for Ownership issued before a write) transactions. The snoop could have either been to a cacheline in the M,E,F (Modified, Exclusive or Forward) states.", + "PublicDescription": "Counts when a transaction with the opcode type RspIFwd Snoop Response was received which indicates a remote caching agent forwarded the data and the requesting agent is able to acquire the data in E (Exclusive) or M (modified) states. This is commonly returned with RFO (the Read for Ownership issued before a write) transactions. The snoop could have either been to a cacheline in the M,E,F (Modified, Exclusive or Forward) states.", "Counter": "0,1,2,3", "ELLC": "0", "Filter": "na", @@ -6370,7 +6370,7 @@ "UMaskExt": "0x00000000", "EventName": "UNC_CHA_SNOOP_RESP.RSPSFWD", "BriefDescription": "RspSFwd Snoop Responses Received", - "PublicDescription": "Counts when a a transaction with the opcode type RspSFwd Snoop Response was received which indicates a remote caching agent forwarded the data but held on to its current copy. This is common for data and code reads that hit in a remote socket in E (Exclusive) or F (Forward) state.", + "PublicDescription": "Counts when a transaction with the opcode type RspSFwd Snoop Response was received which indicates a remote caching agent forwarded the data but held on to its current copy. This is common for data and code reads that hit in a remote socket in E (Exclusive) or F (Forward) state.", "Counter": "0,1,2,3", "ELLC": "0", "Filter": "na", @@ -18425,7 +18425,7 @@ "Unit": "IIO", "EventCode": "0xd5", "UMask": "0x01", - "PortMask": "0x0000", + "PortMask": "0x01", "FCMask": "0x07", "UMaskExt": "0x00070000", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0", @@ -18443,7 +18443,7 @@ "Unit": "IIO", "EventCode": "0xd5", "UMask": "0x80", - "PortMask": "0x0000", + "PortMask": "0x80", "FCMask": "0x07", "UMaskExt": "0x00070000", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART7", @@ -18461,7 +18461,7 @@ "Unit": "IIO", "EventCode": "0xd5", "UMask": "0x40", - "PortMask": "0x0000", + "PortMask": "0x40", "FCMask": "0x07", "UMaskExt": "0x00070000", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART6", @@ -18479,7 +18479,7 @@ "Unit": "IIO", "EventCode": "0xd5", "UMask": "0x20", - "PortMask": "0x0000", + "PortMask": "0x20", "FCMask": "0x07", "UMaskExt": "0x00070000", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART5", @@ -18497,7 +18497,7 @@ "Unit": "IIO", "EventCode": "0xd5", "UMask": "0x10", - "PortMask": "0x0000", + "PortMask": "0x10", "FCMask": "0x07", "UMaskExt": "0x00070000", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART4", @@ -18515,7 +18515,7 @@ "Unit": "IIO", "EventCode": "0xd5", "UMask": "0x08", - "PortMask": "0x0000", + "PortMask": "0x08", "FCMask": "0x07", "UMaskExt": "0x00070000", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3", @@ -18533,7 +18533,7 @@ "Unit": "IIO", "EventCode": "0xd5", "UMask": "0x04", - "PortMask": "0x0000", + "PortMask": "0x04", "FCMask": "0x07", "UMaskExt": "0x00070000", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2", @@ -18551,7 +18551,7 @@ "Unit": "IIO", "EventCode": "0xd5", "UMask": "0x02", - "PortMask": "0x0000", + "PortMask": "0x02", "FCMask": "0x07", "UMaskExt": "0x00070000", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1", @@ -18569,7 +18569,7 @@ "Unit": "IIO", "EventCode": "0xd5", "UMask": "0xff", - "PortMask": "0x00", + "PortMask": "0xff", "FCMask": "0x07", "UMaskExt": "0x00000000", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS", diff --git a/GLM/events/goldmont_core.json b/GLM/events/goldmont_core.json index da584b04..e65bc1b8 100644 --- a/GLM/events/goldmont_core.json +++ b/GLM/events/goldmont_core.json @@ -768,7 +768,7 @@ "UMask": "0x01", "EventName": "MACHINE_CLEARS.SMC", "BriefDescription": "Self-Modifying Code detected", - "PublicDescription": "Counts the number of times that the processor detects that a program is writing to a code section and has to perform a machine clear because of that modification. Self-modifying code (SMC) causes a severe penalty in all Intel® architecture processors.", + "PublicDescription": "Counts the number of times that the processor detects that a program is writing to a code section and has to perform a machine clear because of that modification. Self-modifying code (SMC) causes a severe penalty in all Intel(R) architecture processors.", "Counter": "0,1,2,3", "PEBScounters": "0", "SampleAfterValue": "200003", diff --git a/GLP/events/goldmontplus_core.json b/GLP/events/goldmontplus_core.json index 1216c0d2..d8309daa 100644 --- a/GLP/events/goldmontplus_core.json +++ b/GLP/events/goldmontplus_core.json @@ -1068,7 +1068,7 @@ "UMask": "0x01", "EventName": "MACHINE_CLEARS.SMC", "BriefDescription": "Self-Modifying Code detected", - "PublicDescription": "Counts the number of times that the processor detects that a program is writing to a code section and has to perform a machine clear because of that modification. Self-modifying code (SMC) causes a severe penalty in all Intel® architecture processors.", + "PublicDescription": "Counts the number of times that the processor detects that a program is writing to a code section and has to perform a machine clear because of that modification. Self-modifying code (SMC) causes a severe penalty in all Intel(R) architecture processors.", "Counter": "0,1,2,3", "PEBScounters": "0,1,2,3", "SampleAfterValue": "20003", diff --git a/GNR/events/graniterapids_core.json b/GNR/events/graniterapids_core.json index 0a7d0af2..524c8fc9 100644 --- a/GNR/events/graniterapids_core.json +++ b/GNR/events/graniterapids_core.json @@ -1,9 +1,9 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Xeon(R) 6 Processor with P-cores - V1.16", - "DatePublished": "10/17/2025", - "Version": "1.16", + "Info": "Performance Monitoring Events for Intel(R) Xeon(R) 6 Processor with P-cores - V1.17", + "DatePublished": "11/19/2025", + "Version": "1.17", "Legend": "" }, "Events": [ @@ -2932,6 +2932,56 @@ "PDISTCounter": "NA", "Speculative": "1" }, + { + "EventCode": "0x83", + "UMask": "0x08", + "EventName": "ICACHE_TAG.STALLS_ISB", + "BriefDescription": "ICACHE_TAG.STALLS_ISB", + "PublicDescription": "ICACHE_TAG.STALLS_ISB", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x83", + "UMask": "0x10", + "EventName": "ICACHE_TAG.STALLS_INUSE", + "BriefDescription": "ICACHE_TAG.STALLS_INUSE", + "PublicDescription": "ICACHE_TAG.STALLS_INUSE", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, { "EventCode": "0x87", "UMask": "0x01", diff --git a/GNR/events/graniterapids_uncore.json b/GNR/events/graniterapids_uncore.json index f3306f45..9d05bd7e 100644 --- a/GNR/events/graniterapids_uncore.json +++ b/GNR/events/graniterapids_uncore.json @@ -1,9 +1,9 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Xeon(R) 6 Processor with P-cores - V1.16", - "DatePublished": "10/17/2025", - "Version": "1.16", + "Info": "Performance Monitoring Events for Intel(R) Xeon(R) 6 Processor with P-cores - V1.17", + "DatePublished": "11/19/2025", + "Version": "1.17", "Legend": "" }, "Events": [ diff --git a/GNR/events/graniterapids_uncore_experimental.json b/GNR/events/graniterapids_uncore_experimental.json index 87284c88..af5a080a 100644 --- a/GNR/events/graniterapids_uncore_experimental.json +++ b/GNR/events/graniterapids_uncore_experimental.json @@ -1,9 +1,9 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Xeon(R) 6 Processor with P-cores - V1.16", - "DatePublished": "10/17/2025", - "Version": "1.16", + "Info": "Performance Monitoring Events for Intel(R) Xeon(R) 6 Processor with P-cores - V1.17", + "DatePublished": "11/19/2025", + "Version": "1.17", "Legend": "" }, "Events": [ diff --git a/LNL/events/lunarlake_lioncove_core.json b/LNL/events/lunarlake_lioncove_core.json index 7f1e5566..0823b168 100644 --- a/LNL/events/lunarlake_lioncove_core.json +++ b/LNL/events/lunarlake_lioncove_core.json @@ -1,9 +1,9 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Lunar Lake performance hybrid architecture - V1.19", - "DatePublished": "10/17/2025", - "Version": "1.19", + "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Lunar Lake performance hybrid architecture - V1.20", + "DatePublished": "11/17/2025", + "Version": "1.20", "Legend": "" }, "Events": [ @@ -3220,6 +3220,60 @@ "PDISTCounter": "NA", "Speculative": "1" }, + { + "EventCode": "0x83", + "UMask": "0x08", + "UMaskExt": "0x00", + "EventName": "ICACHE_TAG.STALLS_ISB", + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache ISB-full", + "PublicDescription": "Cycles where a code fetch is stalled due to L1 instruction cache ISB-full", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x83", + "UMask": "0x10", + "UMaskExt": "0x00", + "EventName": "ICACHE_TAG.STALLS_INUSE", + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache In use-full", + "PublicDescription": "Cycles where a code fetch is stalled due to L1 instruction cache In use-full", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, { "EventCode": "0x87", "UMask": "0x01", diff --git a/LNL/events/lunarlake_skymont_core.json b/LNL/events/lunarlake_skymont_core.json index 4c856c4e..f43eb698 100644 --- a/LNL/events/lunarlake_skymont_core.json +++ b/LNL/events/lunarlake_skymont_core.json @@ -1,9 +1,9 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Lunar Lake performance hybrid architecture - V1.19", - "DatePublished": "10/17/2025", - "Version": "1.19", + "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Lunar Lake performance hybrid architecture - V1.20", + "DatePublished": "11/17/2025", + "Version": "1.20", "Legend": "" }, "Events": [ @@ -66,8 +66,8 @@ "UMask": "0x02", "UMaskExt": "0x00", "EventName": "CPU_CLK_UNHALTED.THREAD", - "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles.", - "PublicDescription": "Fixed Counter: Counts the number of unhalted core clock cycles.", + "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.CORE]", + "PublicDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.CORE]", "Counter": "Fixed counter 1", "PEBScounters": "33", "SampleAfterValue": "2000003", @@ -2113,6 +2113,60 @@ "PDISTCounter": "NA", "Speculative": "1" }, + { + "EventCode": "0x35", + "UMask": "0x50", + "UMaskExt": "0x00", + "EventName": "MEM_BOUND_STALLS_IFETCH.LLC_MISS_LOCALMEM", + "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an icache or itlb miss which missed all the caches. Local DRAM, MMIO or other local memory type provides the data.", + "PublicDescription": "Counts the number of unhalted cycles when the core is stalled due to an icache or itlb miss which missed all the caches. Local DRAM, MMIO or other local memory type provides the data.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x35", + "UMask": "0x78", + "UMaskExt": "0x00", + "EventName": "MEM_BOUND_STALLS_IFETCH.LLC_MISS", + "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an icache or itlb miss which missed all the caches.", + "PublicDescription": "Counts the number of unhalted cycles when the core is stalled due to an icache or itlb miss which missed all the caches.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, { "EventCode": "0x35", "UMask": "0x7e", @@ -2935,7 +2989,7 @@ "SampleAfterValue": "1000003", "MSRIndex": "0x00", "MSRValue": "0x00", - "Precise": "1", + "Precise": "0", "CollectPEBSRecord": "2", "TakenAlone": "0", "CounterMask": "0", @@ -6379,6 +6433,33 @@ "PDISTCounter": "NA", "Speculative": "0" }, + { + "EventCode": "0xc9", + "UMask": "0x0e", + "UMaskExt": "0x00", + "EventName": "FRONTEND_RETIRED_SOURCE.ICACHE_L2_MISS", + "BriefDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to Instruction L1 cache miss, that missed in the L2 cache.", + "PublicDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to Instruction L1 cache miss, that missed in the L2 cache.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, { "EventCode": "0xc9", "UMask": "0x10", @@ -6468,12 +6549,12 @@ "BriefDescription": "Counts the number of cycles when any of the integer dividers are active.", "PublicDescription": "Counts the number of cycles when any of the integer dividers are active.", "Counter": "0,1,2,3,4,5,6,7", - "PEBScounters": "NA", + "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "1000003", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "0", - "CollectPEBSRecord": "0", + "CollectPEBSRecord": "2", "TakenAlone": "0", "CounterMask": "1", "Invert": "0", @@ -6522,12 +6603,12 @@ "BriefDescription": "Counts the number of cycles when any of the floating point dividers are active.", "PublicDescription": "Counts the number of cycles when any of the floating point dividers are active.", "Counter": "0,1,2,3,4,5,6,7", - "PEBScounters": "NA", + "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "1000003", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "0", - "CollectPEBSRecord": "0", + "CollectPEBSRecord": "2", "TakenAlone": "0", "CounterMask": "1", "Invert": "0", @@ -6549,12 +6630,12 @@ "BriefDescription": "Counts the number of cycles when any of the floating point or integer dividers are active.", "PublicDescription": "Counts the number of cycles when any of the floating point or integer dividers are active.", "Counter": "0,1,2,3,4,5,6,7", - "PEBScounters": "NA", + "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "1000003", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "0", - "CollectPEBSRecord": "0", + "CollectPEBSRecord": "2", "TakenAlone": "0", "CounterMask": "1", "Invert": "0", @@ -6681,8 +6762,8 @@ "UMask": "0x05", "UMaskExt": "0x00", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 8.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 8.", "Counter": "0,1", "PEBScounters": "0,1", "SampleAfterValue": "200003", @@ -6708,8 +6789,8 @@ "UMask": "0x05", "UMaskExt": "0x00", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 64.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 64.", "Counter": "0,1", "PEBScounters": "0,1", "SampleAfterValue": "200003", @@ -6735,8 +6816,8 @@ "UMask": "0x05", "UMaskExt": "0x00", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 512.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 512.", "Counter": "0,1", "PEBScounters": "0,1", "SampleAfterValue": "200003", @@ -6762,8 +6843,8 @@ "UMask": "0x05", "UMaskExt": "0x00", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 4.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 4.", "Counter": "0,1", "PEBScounters": "0,1", "SampleAfterValue": "200003", @@ -6789,8 +6870,8 @@ "UMask": "0x05", "UMaskExt": "0x00", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 32.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 32.", "Counter": "0,1", "PEBScounters": "0,1", "SampleAfterValue": "200003", @@ -6816,8 +6897,8 @@ "UMask": "0x05", "UMaskExt": "0x00", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 256.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 256.", "Counter": "0,1", "PEBScounters": "0,1", "SampleAfterValue": "200003", @@ -6843,8 +6924,8 @@ "UMask": "0x05", "UMaskExt": "0x00", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 16.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 16.", "Counter": "0,1", "PEBScounters": "0,1", "SampleAfterValue": "200003", @@ -6870,8 +6951,8 @@ "UMask": "0x05", "UMaskExt": "0x00", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 128.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 128.", "Counter": "0,1", "PEBScounters": "0,1", "SampleAfterValue": "200003", @@ -6897,8 +6978,8 @@ "UMask": "0x06", "UMaskExt": "0x00", "EventName": "MEM_UOPS_RETIRED.STORE_LATENCY", - "BriefDescription": "Counts the number of stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES", - "PublicDescription": "Counts the number of stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES", + "BriefDescription": "Counts the number of stores uops retired.", + "PublicDescription": "Counts the number of stores uops retired.", "Counter": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "200003", diff --git a/LNL/events/lunarlake_uncore.json b/LNL/events/lunarlake_uncore.json index da94e1d2..3e14dd67 100644 --- a/LNL/events/lunarlake_uncore.json +++ b/LNL/events/lunarlake_uncore.json @@ -1,9 +1,9 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Lunar Lake performance hybrid architecture - V1.19", - "DatePublished": "10/17/2025", - "Version": "1.19", + "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Lunar Lake performance hybrid architecture - V1.20", + "DatePublished": "11/17/2025", + "Version": "1.20", "Legend": "" }, "Events": [ diff --git a/LNL/events/lunarlake_uncore_experimental.json b/LNL/events/lunarlake_uncore_experimental.json index 2c2fb003..2a96c05c 100644 --- a/LNL/events/lunarlake_uncore_experimental.json +++ b/LNL/events/lunarlake_uncore_experimental.json @@ -1,9 +1,9 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Lunar Lake performance hybrid architecture - V1.19", - "DatePublished": "10/17/2025", - "Version": "1.19", + "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Lunar Lake performance hybrid architecture - V1.20", + "DatePublished": "11/17/2025", + "Version": "1.20", "Legend": "" }, "Events": [ diff --git a/MTL/events/meteorlake_crestmont_core.json b/MTL/events/meteorlake_crestmont_core.json index a573a128..921ba995 100644 --- a/MTL/events/meteorlake_crestmont_core.json +++ b/MTL/events/meteorlake_crestmont_core.json @@ -1,9 +1,9 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Meteor Lake performance hybrid architecture - V1.18", - "DatePublished": "10/17/2025", - "Version": "1.18", + "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Meteor Lake performance hybrid architecture - V1.19", + "DatePublished": "11/17/2025", + "Version": "1.19", "Legend": "" }, "Events": [ @@ -61,8 +61,8 @@ "EventCode": "0x00", "UMask": "0x02", "EventName": "CPU_CLK_UNHALTED.THREAD", - "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles", - "PublicDescription": "Fixed Counter: Counts the number of unhalted core clock cycles", + "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.CORE]", + "PublicDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.CORE]", "Counter": "Fixed counter 1", "PEBScounters": "33", "SampleAfterValue": "2000003", @@ -957,6 +957,56 @@ "PDISTCounter": "NA", "Speculative": "1" }, + { + "EventCode": "0x34", + "UMask": "0x02", + "EventName": "MEM_BOUND_STALLS_LOAD.LLC_HIT_NOSNOOP", + "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which hit in the LLC, no snoop was required. LLC provides the data. If the core has access to an L3 cache, an LLC hit refers to an L3 cache hit, otherwise it counts zeros.", + "PublicDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which hit in the LLC, no snoop was required. LLC provides the data. If the core has access to an L3 cache, an LLC hit refers to an L3 cache hit, otherwise it counts zeros.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x34", + "UMask": "0x04", + "EventName": "MEM_BOUND_STALLS_LOAD.LLC_HIT_SNOOP", + "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which hit in the LLC, a snoop was required, the snoop misses or the snoop hits but NO_FWD. LLC provides the data. If the core has access to an L3 cache, an LLC hit refers to an L3 cache hit, otherwise it counts zeros.", + "PublicDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which hit in the LLC, a snoop was required, the snoop misses or the snoop hits but NO_FWD. LLC provides the data. If the core has access to an L3 cache, an LLC hit refers to an L3 cache hit, otherwise it counts zeros.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, { "EventCode": "0x34", "UMask": "0x06", @@ -982,6 +1032,31 @@ "PDISTCounter": "NA", "Speculative": "1" }, + { + "EventCode": "0x34", + "UMask": "0x50", + "EventName": "MEM_BOUND_STALLS_LOAD.LLC_MISS_LOCALMEM", + "BriefDescription": "Counts the number of unhalted cycles when the core is stalled to a demand load miss and the data was provided from an unknown source. If the core has access to an L3 cache, an LLC miss refers to an L3 cache miss, otherwise it is an L2 cache miss.", + "PublicDescription": "Counts the number of unhalted cycles when the core is stalled to a demand load miss and the data was provided from an unknown source. If the core has access to an L3 cache, an LLC miss refers to an L3 cache miss, otherwise it is an L2 cache miss.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, { "EventCode": "0x34", "UMask": "0x78", @@ -1107,6 +1182,31 @@ "PDISTCounter": "NA", "Speculative": "1" }, + { + "EventCode": "0x35", + "UMask": "0x02", + "EventName": "MEM_BOUND_STALLS_IFETCH.LLC_HIT_NOSNOOP", + "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an ICACHE or ITLB miss which hit in the LLC, no snoop was required. LLC provides the data. If the core has access to an L3 cache, an LLC hit refers to an L3 cache hit, otherwise it counts zeros.", + "PublicDescription": "Counts the number of unhalted cycles when the core is stalled due to an ICACHE or ITLB miss which hit in the LLC, no snoop was required. LLC provides the data. If the core has access to an L3 cache, an LLC hit refers to an L3 cache hit, otherwise it counts zeros.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, { "EventCode": "0x35", "UMask": "0x06", @@ -1132,6 +1232,31 @@ "PDISTCounter": "NA", "Speculative": "1" }, + { + "EventCode": "0x35", + "UMask": "0x50", + "EventName": "MEM_BOUND_STALLS_IFETCH.LLC_MISS_LOCALMEM", + "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an ICACHE or ITLB miss which missed all the caches. DRAM, MMIO or other LOCAL memory type provides the data. If the core has access to an L3 cache, an LLC miss refers to an L3 cache miss, otherwise it is an L2 cache miss.", + "PublicDescription": "Counts the number of unhalted cycles when the core is stalled due to an ICACHE or ITLB miss which missed all the caches. DRAM, MMIO or other LOCAL memory type provides the data. If the core has access to an L3 cache, an LLC miss refers to an L3 cache miss, otherwise it is an L2 cache miss.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, { "EventCode": "0x35", "UMask": "0x78", @@ -4314,12 +4439,12 @@ "BriefDescription": "Counts the number of cycles when any of the floating point dividers are active.", "PublicDescription": "Counts the number of cycles when any of the floating point dividers are active.", "Counter": "0,1,2,3,4,5,6,7", - "PEBScounters": "NA", + "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "1000003", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "0", - "CollectPEBSRecord": "0", + "CollectPEBSRecord": "2", "TakenAlone": "0", "CounterMask": "1", "Invert": "0", @@ -4339,12 +4464,12 @@ "BriefDescription": "Counts the number of cycles when any of the floating point or integer dividers are active.", "PublicDescription": "Counts the number of cycles when any of the floating point or integer dividers are active.", "Counter": "0,1,2,3,4,5,6,7", - "PEBScounters": "NA", + "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "1000003", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "0", - "CollectPEBSRecord": "0", + "CollectPEBSRecord": "2", "TakenAlone": "0", "CounterMask": "1", "Invert": "0", @@ -4361,8 +4486,8 @@ "EventCode": "0xd0", "UMask": "0x05", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 8. Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 8. Only counts with PEBS enabled.", "Counter": "0,1", "PEBScounters": "0,1", "SampleAfterValue": "1000003", @@ -4386,8 +4511,8 @@ "EventCode": "0xd0", "UMask": "0x05", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 64. Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 64. Only counts with PEBS enabled.", "Counter": "0,1", "PEBScounters": "0,1", "SampleAfterValue": "1000003", @@ -4411,8 +4536,8 @@ "EventCode": "0xd0", "UMask": "0x05", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 512. Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 512. Only counts with PEBS enabled.", "Counter": "0,1", "PEBScounters": "0,1", "SampleAfterValue": "1000003", @@ -4436,8 +4561,8 @@ "EventCode": "0xd0", "UMask": "0x05", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 4. Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 4. Only counts with PEBS enabled.", "Counter": "0,1", "PEBScounters": "0,1", "SampleAfterValue": "1000003", @@ -4461,8 +4586,8 @@ "EventCode": "0xd0", "UMask": "0x05", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 32. Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 32. Only counts with PEBS enabled.", "Counter": "0,1", "PEBScounters": "0,1", "SampleAfterValue": "1000003", @@ -4486,8 +4611,8 @@ "EventCode": "0xd0", "UMask": "0x05", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 256. Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 256. Only counts with PEBS enabled.", "Counter": "0,1", "PEBScounters": "0,1", "SampleAfterValue": "1000003", @@ -4511,8 +4636,8 @@ "EventCode": "0xd0", "UMask": "0x05", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 16. Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 16. Only counts with PEBS enabled.", "Counter": "0,1", "PEBScounters": "0,1", "SampleAfterValue": "1000003", @@ -4536,8 +4661,8 @@ "EventCode": "0xd0", "UMask": "0x05", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 128. Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 128. Only counts with PEBS enabled.", "Counter": "0,1", "PEBScounters": "0,1", "SampleAfterValue": "1000003", @@ -4561,8 +4686,8 @@ "EventCode": "0xd0", "UMask": "0x05", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_2048", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 2048. Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 2048. Only counts with PEBS enabled.", "Counter": "0,1", "PEBScounters": "0,1", "SampleAfterValue": "1000003", @@ -4586,8 +4711,8 @@ "EventCode": "0xd0", "UMask": "0x05", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_1024", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 1024. Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 1024. Only counts with PEBS enabled.", "Counter": "0,1", "PEBScounters": "0,1", "SampleAfterValue": "1000003", @@ -4611,8 +4736,8 @@ "EventCode": "0xd0", "UMask": "0x06", "EventName": "MEM_UOPS_RETIRED.STORE_LATENCY", - "BriefDescription": "Counts the number of stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES", - "PublicDescription": "Counts the number of stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES", + "BriefDescription": "Counts the number of stores uops retired.", + "PublicDescription": "Counts the number of stores uops retired.", "Counter": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "1000003", @@ -5032,6 +5157,106 @@ "PDISTCounter": "NA", "Speculative": "0" }, + { + "EventCode": "0xe0", + "UMask": "0x02", + "EventName": "MISC_RETIRED1.LFENCE", + "BriefDescription": "Counts the number of LFENCE instructions retired.", + "PublicDescription": "Counts the number of LFENCE instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xe0", + "UMask": "0xff", + "EventName": "MISC_RETIRED1.CL_INST", + "BriefDescription": "Counts the number of CLFLUSH, CLWB, and CLDEMOTE instructions retired.", + "PublicDescription": "Counts the number of CLFLUSH, CLWB, and CLDEMOTE instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xe1", + "UMask": "0x10", + "EventName": "MISC_RETIRED2.KEYLOCKER_ACCESS", + "BriefDescription": "Counts the number of accesses to KeyLocker cache.", + "PublicDescription": "Counts the number of accesses to KeyLocker cache.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xe1", + "UMask": "0x11", + "EventName": "MISC_RETIRED2.KEYLOCKER_MISS", + "BriefDescription": "Counts the number of misses to KeyLocker cache.", + "PublicDescription": "Counts the number of misses to KeyLocker cache.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, { "EventCode": "0xe4", "UMask": "0x01", diff --git a/MTL/events/meteorlake_redwoodcove_core.json b/MTL/events/meteorlake_redwoodcove_core.json index 5e31623f..acf7a9c3 100644 --- a/MTL/events/meteorlake_redwoodcove_core.json +++ b/MTL/events/meteorlake_redwoodcove_core.json @@ -1,9 +1,9 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Meteor Lake performance hybrid architecture - V1.18", - "DatePublished": "10/17/2025", - "Version": "1.18", + "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Meteor Lake performance hybrid architecture - V1.19", + "DatePublished": "11/17/2025", + "Version": "1.19", "Legend": "" }, "Events": [ @@ -3157,6 +3157,56 @@ "PDISTCounter": "NA", "Speculative": "1" }, + { + "EventCode": "0x83", + "UMask": "0x08", + "EventName": "ICACHE_TAG.STALLS_ISB", + "BriefDescription": "ICACHE_TAG.STALLS_ISB", + "PublicDescription": "ICACHE_TAG.STALLS_ISB", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x83", + "UMask": "0x10", + "EventName": "ICACHE_TAG.STALLS_INUSE", + "BriefDescription": "ICACHE_TAG.STALLS_INUSE", + "PublicDescription": "ICACHE_TAG.STALLS_INUSE", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, { "EventCode": "0x87", "UMask": "0x01", diff --git a/MTL/events/meteorlake_uncore.json b/MTL/events/meteorlake_uncore.json index b2a8d5f0..2064371e 100644 --- a/MTL/events/meteorlake_uncore.json +++ b/MTL/events/meteorlake_uncore.json @@ -1,9 +1,9 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Meteor Lake performance hybrid architecture - V1.18", - "DatePublished": "10/17/2025", - "Version": "1.18", + "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Meteor Lake performance hybrid architecture - V1.19", + "DatePublished": "11/17/2025", + "Version": "1.19", "Legend": "" }, "Events": [ diff --git a/MTL/events/meteorlake_uncore_experimental.json b/MTL/events/meteorlake_uncore_experimental.json index f9d9cca5..3edb6dc0 100644 --- a/MTL/events/meteorlake_uncore_experimental.json +++ b/MTL/events/meteorlake_uncore_experimental.json @@ -1,9 +1,9 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Meteor Lake performance hybrid architecture - V1.18", - "DatePublished": "10/17/2025", - "Version": "1.18", + "Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Meteor Lake performance hybrid architecture - V1.19", + "DatePublished": "11/17/2025", + "Version": "1.19", "Legend": "" }, "Events": [ diff --git a/PTL/events/pantherlake_cougarcove_core.json b/PTL/events/pantherlake_cougarcove_core.json index 8349b548..57929169 100644 --- a/PTL/events/pantherlake_cougarcove_core.json +++ b/PTL/events/pantherlake_cougarcove_core.json @@ -1,9 +1,9 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Core(TM) Ultra series 3 processors (codenamed Panther Lake) - V1.02", - "DatePublished": "10/16/2025", - "Version": "1.02", + "Info": "Performance Monitoring Events for Intel(R) Core(TM) Ultra series 3 processors (codenamed Panther Lake) - V1.03", + "DatePublished": "11/14/2025", + "Version": "1.03", "Legend": "" }, "Events": [ @@ -3247,6 +3247,60 @@ "PDISTCounter": "NA", "Speculative": "1" }, + { + "EventCode": "0x83", + "UMask": "0x08", + "UMaskExt": "0x00", + "EventName": "ICACHE_TAG.STALLS_ISB", + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache ISB-full", + "PublicDescription": "Cycles where a code fetch is stalled due to L1 instruction cache ISB-full", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x83", + "UMask": "0x10", + "UMaskExt": "0x00", + "EventName": "ICACHE_TAG.STALLS_INUSE", + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache In use-full", + "PublicDescription": "Cycles where a code fetch is stalled due to L1 instruction cache In use-full", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "PEBScounters": "0,1,2,3,4,5,6,7,8,9", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, { "EventCode": "0x87", "UMask": "0x01", @@ -5871,7 +5925,7 @@ "UMask": "0xfb", "UMaskExt": "0x00", "EventName": "BR_INST_RETIRED.NEAR_TAKEN", - "BriefDescription": "Taken branch instructions retired.", + "BriefDescription": "Near Taken branch instructions retired.", "PublicDescription": "Counts taken branch instructions retired.", "Counter": "0,1,2,3,4,5,6,7,8,9", "PEBScounters": "0,1,2,3,4,5,6,7,8,9", diff --git a/PTL/events/pantherlake_darkmont_core.json b/PTL/events/pantherlake_darkmont_core.json index ba36a7a0..bb650201 100644 --- a/PTL/events/pantherlake_darkmont_core.json +++ b/PTL/events/pantherlake_darkmont_core.json @@ -1,9 +1,9 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Core(TM) Ultra series 3 processors (codenamed Panther Lake) - V1.02", - "DatePublished": "10/16/2025", - "Version": "1.02", + "Info": "Performance Monitoring Events for Intel(R) Core(TM) Ultra series 3 processors (codenamed Panther Lake) - V1.03", + "DatePublished": "11/14/2025", + "Version": "1.03", "Legend": "" }, "Events": [ @@ -439,6 +439,33 @@ "PDISTCounter": "NA", "Speculative": "1" }, + { + "EventCode": "0x05", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "LD_HEAD.L1_MISS", + "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a DL1 miss.", + "PublicDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a DL1 miss.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, { "EventCode": "0x05", "UMask": "0x02", @@ -466,6 +493,60 @@ "PDISTCounter": "NA", "Speculative": "1" }, + { + "EventCode": "0x05", + "UMask": "0x81", + "UMaskExt": "0x00", + "EventName": "LD_HEAD.L1_MISS_AT_RET", + "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DL1 miss.", + "PublicDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DL1 miss.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x05", + "UMask": "0x82", + "UMaskExt": "0x00", + "EventName": "LD_HEAD.WCB_FULL_AT_RET", + "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to request buffers full or lock in progress.", + "PublicDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to request buffers full or lock in progress.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, { "EventCode": "0x05", "UMask": "0xf4", @@ -520,6 +601,33 @@ "PDISTCounter": "NA", "Speculative": "1" }, + { + "EventCode": "0x08", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", + "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 4K page.", + "PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, { "EventCode": "0x08", "UMask": "0x0e", @@ -574,6 +682,33 @@ "PDISTCounter": "NA", "Speculative": "1" }, + { + "EventCode": "0x0e", + "UMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UOPS_ISSUED.ANY", + "BriefDescription": "Counts the number of uops issued by the front end every cycle.", + "PublicDescription": "Counts the number of uops issued by the front end every cycle. When 4-uops are requested and only 2-uops are delivered, the event counts 2. Uops_issued correlates to the number of ROB entries. If uop takes 2 ROB slots it counts as 2 uops_issued.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, { "EventCode": "0x13", "UMask": "0x02", @@ -628,6 +763,114 @@ "PDISTCounter": "0,1", "Speculative": "0" }, + { + "EventCode": "0x24", + "UMask": "0x41", + "UMaskExt": "0x00", + "EventName": "L2_REQUEST.DEMAND_DATA_RD_MISS", + "BriefDescription": "Counts the number of L2 cache accesses from front door Demand Data Read requests that resulted in a Miss. Does not include rejects or recycles, per core event.", + "PublicDescription": "Counts the number of L2 cache accesses from front door Demand Data Read requests that resulted in a Miss. Does not include rejects or recycles, per core event.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0x42", + "UMaskExt": "0x00", + "EventName": "L2_REQUEST.DEMAND_RFO_MISS", + "BriefDescription": "Counts the number of L2 cache accesses from front door Demand RFO requests that resulted in a Miss. Does not include rejects or recycles, per core event.", + "PublicDescription": "Counts the number of L2 cache accesses from front door Demand RFO requests that resulted in a Miss. Does not include rejects or recycles, per core event.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0x44", + "UMaskExt": "0x00", + "EventName": "L2_REQUEST.DEMAND_CODE_RD_MISS", + "BriefDescription": "Counts the number of L2 cache accesses from front door Demand Code Read requests that resulted in a Miss. Does not include rejects or recycles, per core event.", + "PublicDescription": "Counts the number of L2 cache accesses from front door Demand Code Read requests that resulted in a Miss. Does not include rejects or recycles, per core event.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0x7f", + "UMaskExt": "0x01", + "EventName": "L2_REQUEST.MISS", + "BriefDescription": "Counts the number of L2 cache accesses from front door requests that resulted in a Miss. Does not include rejects or recycles, per core event.", + "PublicDescription": "Counts the number of L2 cache accesses from front door requests that resulted in a Miss. Does not include rejects or recycles, per core event.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, { "EventCode": "0x24", "UMask": "0xbf", @@ -655,6 +898,87 @@ "PDISTCounter": "NA", "Speculative": "1" }, + { + "EventCode": "0x24", + "UMask": "0xc1", + "UMaskExt": "0x00", + "EventName": "L2_REQUEST.DEMAND_DATA_RD", + "BriefDescription": "Counts the number of L2 cache accesses from front door Demand Data Read requests. Does not include rejects or recycles, per core event.", + "PublicDescription": "Counts the number of L2 cache accesses from front door Demand Data Read requests. Does not include rejects or recycles, per core event.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xc2", + "UMaskExt": "0x00", + "EventName": "L2_REQUEST.DEMAND_RFO", + "BriefDescription": "Counts the number of L2 cache accesses from front door Demand RFO requests. Does not include rejects or recycles, per core event.", + "PublicDescription": "Counts the number of L2 cache accesses from front door Demand RFO requests. Does not include rejects or recycles, per core event.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xc4", + "UMaskExt": "0x00", + "EventName": "L2_REQUEST.DEMAND_CODE_RD", + "BriefDescription": "Counts the number of L2 cache accesses from front door Demand Code Read requests. Does not include rejects or recycles, per core event.", + "PublicDescription": "Counts the number of L2 cache accesses from front door Demand Code Read requests. Does not include rejects or recycles, per core event.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, { "EventCode": "0x24", "UMask": "0xff", @@ -790,6 +1114,60 @@ "PDISTCounter": "NA", "Speculative": "1" }, + { + "EventCode": "0x34", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "MEM_BOUND_STALLS_LOAD.LLC_HIT_NOSNOOP", + "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which hit in the LLC, no snoop was required. LLC provided data.", + "PublicDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which hit in the LLC, no snoop was required. LLC provided data.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x34", + "UMask": "0x04", + "UMaskExt": "0x00", + "EventName": "MEM_BOUND_STALLS_LOAD.LLC_HIT_SNOOP", + "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which hit in the LLC, a snoop was required, the snoop misses or the snoop hits but no fwd. LLC provides the data.", + "PublicDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which hit in the LLC, a snoop was required, the snoop misses or the snoop hits but no fwd. LLC provides the data.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, { "EventCode": "0x34", "UMask": "0x06", @@ -1060,6 +1438,33 @@ "PDISTCounter": "NA", "Speculative": "1" }, + { + "EventCode": "0x49", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", + "BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 4K page.", + "PublicDescription": "Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, { "EventCode": "0x49", "UMask": "0x0e", @@ -1438,6 +1843,33 @@ "PDISTCounter": "NA", "Speculative": "1" }, + { + "EventCode": "0x73", + "UMask": "0x03", + "UMaskExt": "0x00", + "EventName": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS", + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.", + "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, { "EventCode": "0x73", "UMask": "0x04", @@ -1573,6 +2005,33 @@ "PDISTCounter": "NA", "Speculative": "1" }, + { + "EventCode": "0x74", + "UMask": "0x40", + "UMaskExt": "0x00", + "EventName": "TOPDOWN_BE_BOUND.REORDER_BUFFER", + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to ROB full", + "PublicDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to ROB full", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, { "EventCode": "0x74", "UMask": "0x80", @@ -1736,12 +2195,39 @@ "Speculative": "1" }, { - "EventCode": "0x80", - "UMask": "0x03", + "EventCode": "0x80", + "UMask": "0x03", + "UMaskExt": "0x00", + "EventName": "ICACHE.ACCESSES", + "BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump.", + "PublicDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x85", + "UMask": "0x01", "UMaskExt": "0x00", - "EventName": "ICACHE.ACCESSES", - "BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump.", - "PublicDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump.", + "EventName": "ITLB_MISSES.MISS_CAUSED_WALK", + "BriefDescription": "Counts the number of page walks initiated by a instruction fetch that missed the first and second level TLBs.", + "PublicDescription": "Counts the number of page walks initiated by a instruction fetch that missed the first and second level TLBs.", "Counter": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "1000003", @@ -1764,11 +2250,11 @@ }, { "EventCode": "0x85", - "UMask": "0x01", + "UMask": "0x02", "UMaskExt": "0x00", - "EventName": "ITLB_MISSES.MISS_CAUSED_WALK", - "BriefDescription": "Counts the number of page walks initiated by a instruction fetch that missed the first and second level TLBs.", - "PublicDescription": "Counts the number of page walks initiated by a instruction fetch that missed the first and second level TLBs.", + "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", + "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to a 4K page.", + "PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault.", "Counter": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "1000003", @@ -2599,6 +3085,33 @@ "PDISTCounter": "NA", "Speculative": "0" }, + { + "EventCode": "0xc2", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "UOPS_RETIRED.EOM", + "BriefDescription": "Counts the number of uops retired that are the last uop of a macro-instruction.", + "PublicDescription": "Counts the number of uops retired that are the last uop of a macro-instruction. EOM uops indicate the 'end of a macro-instruction' and play a crucial role in the processor's control flow and recovery mechanisms.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, { "EventCode": "0xc2", "UMask": "0x02", @@ -2653,6 +3166,60 @@ "PDISTCounter": "NA", "Speculative": "0" }, + { + "EventCode": "0xc2", + "UMask": "0x08", + "UMaskExt": "0x00", + "EventName": "UOPS_RETIRED.NANO_CODE", + "BriefDescription": "UOPS_RETIRED.NANO_CODE", + "PublicDescription": "UOPS_RETIRED.NANO_CODE", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc2", + "UMask": "0x20", + "UMaskExt": "0x00", + "EventName": "UOPS_RETIRED.LSD", + "BriefDescription": "Counts the number of uops retired that originated from a loop stream detector.", + "PublicDescription": "Counts the number of uops retired that originated from a loop stream detector.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, { "EventCode": "0xc2", "UMask": "0x40", @@ -3413,15 +3980,204 @@ "EventCode": "0xc9", "UMask": "0x10", "UMaskExt": "0x00", - "EventName": "FRONTEND_RETIRED_SOURCE.ITLB_STLB_HIT", - "BriefDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss that hit in the second level TLB.", - "PublicDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss that hit in the second level TLB.", + "EventName": "FRONTEND_RETIRED_SOURCE.ITLB_STLB_HIT", + "BriefDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss that hit in the second level TLB.", + "PublicDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss that hit in the second level TLB.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xc9", + "UMask": "0x20", + "UMaskExt": "0x00", + "EventName": "FRONTEND_RETIRED_SOURCE.ITLB_STLB_MISS", + "BriefDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss that also missed the second level TLB.", + "PublicDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss that also missed the second level TLB.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "ARITH.IDIV_OCCUPANCY", + "BriefDescription": "Counts number of active integer dividers per cycle.", + "PublicDescription": "Counts number of active integer dividers per cycle.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "ARITH.IDIV_ACTIVE", + "BriefDescription": "Counts the number of cycles when any of the integer dividers are active.", + "PublicDescription": "Counts the number of cycles when any of the integer dividers are active.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xcd", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "ARITH.FPDIV_OCCUPANCY", + "BriefDescription": "Counts the number of floating point dividers per cycle in the loop stage.", + "PublicDescription": "Counts the number of floating point dividers per cycle in the loop stage.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xcd", + "UMask": "0x02", + "UMaskExt": "0x00", + "EventName": "ARITH.FPDIV_ACTIVE", + "BriefDescription": "Counts the number of cycles when any of the floating point dividers are active.", + "PublicDescription": "Counts the number of cycles when any of the floating point dividers are active.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xcd", + "UMask": "0x03", + "UMaskExt": "0x00", + "EventName": "ARITH.DIV_ACTIVE", + "BriefDescription": "Counts the number of cycles when any of the floating point or integer dividers are active.", + "PublicDescription": "Counts the number of cycles when any of the floating point or integer dividers are active.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xcd", + "UMask": "0x04", + "UMaskExt": "0x00", + "EventName": "ARITH.IDIV_UOPS", + "BriefDescription": "Counts the number of integer divider uops executed per cycle.", + "PublicDescription": "Counts the number of integer divider uops executed per cycle.", "Counter": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "1000003", "MSRIndex": "0x00", "MSRValue": "0x00", - "Precise": "1", + "Precise": "0", "CollectPEBSRecord": "2", "TakenAlone": "0", "CounterMask": "0", @@ -3433,22 +4189,22 @@ "Offcore": "0", "Deprecated": "0", "Equal": "0", - "PDISTCounter": "0,1", - "Speculative": "0" + "PDISTCounter": "NA", + "Speculative": "1" }, { - "EventCode": "0xc9", - "UMask": "0x20", + "EventCode": "0xcd", + "UMask": "0x08", "UMaskExt": "0x00", - "EventName": "FRONTEND_RETIRED_SOURCE.ITLB_STLB_MISS", - "BriefDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss that also missed the second level TLB.", - "PublicDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss that also missed the second level TLB.", + "EventName": "ARITH.FPDIV_UOPS", + "BriefDescription": "Counts the number of floating point divider uops executed per cycle.", + "PublicDescription": "Counts the number of floating point divider uops executed per cycle.", "Counter": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "1000003", "MSRIndex": "0x00", "MSRValue": "0x00", - "Precise": "1", + "Precise": "0", "CollectPEBSRecord": "2", "TakenAlone": "0", "CounterMask": "0", @@ -3460,8 +4216,8 @@ "Offcore": "0", "Deprecated": "0", "Equal": "0", - "PDISTCounter": "0,1", - "Speculative": "0" + "PDISTCounter": "NA", + "Speculative": "1" }, { "EventCode": "0xd0", @@ -3481,8 +4237,8 @@ "CounterMask": "0", "Invert": "0", "EdgeDetect": "0", - "Data_LA": "0", - "L1_Hit_Indication": "0", + "Data_LA": "1", + "L1_Hit_Indication": "1", "Errata": "null", "Offcore": "0", "Deprecated": "0", @@ -3508,8 +4264,8 @@ "CounterMask": "0", "Invert": "0", "EdgeDetect": "0", - "Data_LA": "0", - "L1_Hit_Indication": "0", + "Data_LA": "1", + "L1_Hit_Indication": "1", "Errata": "null", "Offcore": "0", "Deprecated": "0", @@ -3535,8 +4291,8 @@ "CounterMask": "0", "Invert": "0", "EdgeDetect": "0", - "Data_LA": "0", - "L1_Hit_Indication": "0", + "Data_LA": "1", + "L1_Hit_Indication": "1", "Errata": "null", "Offcore": "0", "Deprecated": "0", @@ -3562,8 +4318,8 @@ "CounterMask": "0", "Invert": "0", "EdgeDetect": "0", - "Data_LA": "0", - "L1_Hit_Indication": "0", + "Data_LA": "1", + "L1_Hit_Indication": "1", "Errata": "null", "Offcore": "0", "Deprecated": "0", @@ -3589,8 +4345,8 @@ "CounterMask": "0", "Invert": "0", "EdgeDetect": "0", - "Data_LA": "0", - "L1_Hit_Indication": "0", + "Data_LA": "1", + "L1_Hit_Indication": "1", "Errata": "null", "Offcore": "0", "Deprecated": "0", @@ -3616,8 +4372,8 @@ "CounterMask": "0", "Invert": "0", "EdgeDetect": "0", - "Data_LA": "0", - "L1_Hit_Indication": "0", + "Data_LA": "1", + "L1_Hit_Indication": "1", "Errata": "null", "Offcore": "0", "Deprecated": "0", @@ -3643,8 +4399,8 @@ "CounterMask": "0", "Invert": "0", "EdgeDetect": "0", - "Data_LA": "0", - "L1_Hit_Indication": "0", + "Data_LA": "1", + "L1_Hit_Indication": "1", "Errata": "null", "Offcore": "0", "Deprecated": "0", @@ -3670,8 +4426,8 @@ "CounterMask": "0", "Invert": "0", "EdgeDetect": "0", - "Data_LA": "0", - "L1_Hit_Indication": "0", + "Data_LA": "1", + "L1_Hit_Indication": "1", "Errata": "null", "Offcore": "0", "Deprecated": "0", @@ -3697,8 +4453,8 @@ "CounterMask": "0", "Invert": "0", "EdgeDetect": "0", - "Data_LA": "0", - "L1_Hit_Indication": "0", + "Data_LA": "1", + "L1_Hit_Indication": "1", "Errata": "null", "Offcore": "0", "Deprecated": "0", @@ -3724,8 +4480,8 @@ "CounterMask": "0", "Invert": "0", "EdgeDetect": "0", - "Data_LA": "0", - "L1_Hit_Indication": "0", + "Data_LA": "1", + "L1_Hit_Indication": "1", "Errata": "null", "Offcore": "0", "Deprecated": "0", @@ -3751,8 +4507,8 @@ "CounterMask": "0", "Invert": "0", "EdgeDetect": "0", - "Data_LA": "0", - "L1_Hit_Indication": "0", + "Data_LA": "1", + "L1_Hit_Indication": "1", "Errata": "null", "Offcore": "0", "Deprecated": "0", @@ -4084,6 +4840,60 @@ "PDISTCounter": "0,1", "Speculative": "0" }, + { + "EventCode": "0xd1", + "UMask": "0x04", + "UMaskExt": "0x00", + "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT_NO_SNOOP", + "BriefDescription": "Counts the number of load ops retired that hit in the L3 cache in which no snoop was required.", + "PublicDescription": "Counts the number of load ops retired that hit in the L3 cache in which no snoop was required.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x10", + "UMaskExt": "0x00", + "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT_SNOOP_HIT", + "BriefDescription": "Counts the number of load ops retired that hit in the L3 cache in which a snoop was required and it hit and forwarded data, it hit and did not forward data, or it hit and the forwarded data was modified.", + "PublicDescription": "Counts the number of load ops retired that hit in the L3 cache in which a snoop was required and it hit and forwarded data, it hit and did not forward data, or it hit and the forwarded data was modified.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, { "EventCode": "0xd1", "UMask": "0x1c", @@ -4219,6 +5029,33 @@ "PDISTCounter": "0,1", "Speculative": "0" }, + { + "EventCode": "0xd3", + "UMask": "0xff", + "UMaskExt": "0x00", + "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.ALL", + "BriefDescription": "Counts the total number of load ops retired that miss the L3 cache.", + "PublicDescription": "Counts the total number of load ops retired that miss the L3 cache.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, { "EventCode": "0xd4", "UMask": "0x08", @@ -4246,6 +5083,60 @@ "PDISTCounter": "0,1", "Speculative": "0" }, + { + "EventCode": "0xd4", + "UMask": "0x10", + "UMaskExt": "0x00", + "EventName": "MEM_LOAD_UOPS_MISC_RETIRED.L3_HIT_SNOOP_WITH_FWD", + "BriefDescription": "Counts the number of load ops retired that hit in the L3 cache in which a snoop was required and non-modified data was forwarded.", + "PublicDescription": "Counts the number of load ops retired that hit in the L3 cache in which a snoop was required and non-modified data was forwarded.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, + { + "EventCode": "0xd4", + "UMask": "0x20", + "UMaskExt": "0x00", + "EventName": "MEM_LOAD_UOPS_MISC_RETIRED.L3_HIT_SNOOP_NO_FWD", + "BriefDescription": "Counts the number of load ops retired that hit in the L3 cache in which a snoop was required and no data was forwarded.", + "PublicDescription": "Counts the number of load ops retired that hit in the L3 cache in which a snoop was required and no data was forwarded.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, { "EventCode": "0xe0", "UMask": "0x02", @@ -4273,6 +5164,33 @@ "PDISTCounter": "0,1", "Speculative": "0" }, + { + "EventCode": "0xe0", + "UMask": "0xff", + "UMaskExt": "0x00", + "EventName": "MISC_RETIRED1.CL_INST", + "BriefDescription": "Counts the number of CLFLUSH, CLWB, and CLDEMOTE instructions retired.", + "PublicDescription": "Counts the number of CLFLUSH, CLWB, and CLDEMOTE instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "0,1", + "Speculative": "0" + }, { "EventCode": "0xe1", "UMask": "0x10", @@ -4488,6 +5406,87 @@ "Equal": "0", "PDISTCounter": "NA", "Speculative": "1" + }, + { + "EventCode": "0xe7", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "MS_DECODED.MS_ENTRY", + "BriefDescription": "Counts the number of times entered into a ucode flow in the FEC. Includes inserted flows due to front-end detected faults or assists.", + "PublicDescription": "Counts the number of times entered into a ucode flow in the FEC. Includes inserted flows due to front-end detected faults or assists.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xe7", + "UMask": "0x04", + "UMaskExt": "0x00", + "EventName": "MS_DECODED.MS_BUSY", + "BriefDescription": "Counts the number of cycles that the micro-sequencer is busy.", + "PublicDescription": "Counts the number of cycles that the micro-sequencer is busy.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xe8", + "UMask": "0x01", + "UMaskExt": "0x00", + "EventName": "PREDICTION.BTCLEAR", + "BriefDescription": "Counts the total number of BTCLEARS.", + "PublicDescription": "Counts the total number of BTCLEARS which occurs when the Branch Target Buffer (BTB) predicts a taken branch.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Equal": "0", + "PDISTCounter": "NA", + "Speculative": "1" } ] } \ No newline at end of file diff --git a/PTL/events/pantherlake_uncore.json b/PTL/events/pantherlake_uncore.json index 66e14d87..5230fb8d 100644 --- a/PTL/events/pantherlake_uncore.json +++ b/PTL/events/pantherlake_uncore.json @@ -1,9 +1,9 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Core(TM) Ultra series 3 processors (codenamed Panther Lake) - V1.02", - "DatePublished": "10/16/2025", - "Version": "1.02", + "Info": "Performance Monitoring Events for Intel(R) Core(TM) Ultra series 3 processors (codenamed Panther Lake) - V1.03", + "DatePublished": "11/14/2025", + "Version": "1.03", "Legend": "" }, "Events": [ diff --git a/SPR/events/sapphirerapids_core.json b/SPR/events/sapphirerapids_core.json index 91a6b308..b201647a 100644 --- a/SPR/events/sapphirerapids_core.json +++ b/SPR/events/sapphirerapids_core.json @@ -1,9 +1,9 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for 4th Generation Intel(R) Xeon(R) Processor Scalable Family based on Sapphire Rapids microarchitecture - V1.35", - "DatePublished": "09/16/2025", - "Version": "1.35", + "Info": "Performance Monitoring Events for 4th Generation Intel(R) Xeon(R) Processor Scalable Family based on Sapphire Rapids microarchitecture - V1.36", + "DatePublished": "11/20/2025", + "Version": "1.36", "Legend": "" }, "Events": [ @@ -3032,6 +3032,56 @@ "PDISTCounter": "NA", "Speculative": "1" }, + { + "EventCode": "0x83", + "UMask": "0x08", + "EventName": "ICACHE_TAG.STALLS_ISB", + "BriefDescription": "ICACHE_TAG.STALLS_ISB", + "PublicDescription": "ICACHE_TAG.STALLS_ISB", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x83", + "UMask": "0x10", + "EventName": "ICACHE_TAG.STALLS_INUSE", + "BriefDescription": "ICACHE_TAG.STALLS_INUSE", + "PublicDescription": "ICACHE_TAG.STALLS_INUSE", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, { "EventCode": "0x87", "UMask": "0x01", @@ -7865,7 +7915,7 @@ "PublicDescription": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM", "Counter": "0,1,2,3", "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", + "SampleAfterValue": "100007", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "1", @@ -7890,7 +7940,7 @@ "PublicDescription": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM", "Counter": "0,1,2,3", "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", + "SampleAfterValue": "100007", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "1", diff --git a/SPR/events/sapphirerapids_uncore.json b/SPR/events/sapphirerapids_uncore.json index 9d1c467d..c961d02a 100644 --- a/SPR/events/sapphirerapids_uncore.json +++ b/SPR/events/sapphirerapids_uncore.json @@ -1,9 +1,9 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for 4th Generation Intel(R) Xeon(R) Processor Scalable Family based on Sapphire Rapids microarchitecture - V1.35", - "DatePublished": "09/16/2025", - "Version": "1.35", + "Info": "Performance Monitoring Events for 4th Generation Intel(R) Xeon(R) Processor Scalable Family based on Sapphire Rapids microarchitecture - V1.36", + "DatePublished": "11/20/2025", + "Version": "1.36", "Legend": "" }, "Events": [ diff --git a/SPR/events/sapphirerapids_uncore_experimental.json b/SPR/events/sapphirerapids_uncore_experimental.json index 7ea82998..4406682e 100644 --- a/SPR/events/sapphirerapids_uncore_experimental.json +++ b/SPR/events/sapphirerapids_uncore_experimental.json @@ -1,9 +1,9 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for 4th Generation Intel(R) Xeon(R) Processor Scalable Family based on Sapphire Rapids microarchitecture - V1.35", - "DatePublished": "09/16/2025", - "Version": "1.35", + "Info": "Performance Monitoring Events for 4th Generation Intel(R) Xeon(R) Processor Scalable Family based on Sapphire Rapids microarchitecture - V1.36", + "DatePublished": "11/20/2025", + "Version": "1.36", "Legend": "" }, "Events": [ @@ -5938,7 +5938,7 @@ "UMaskExt": "0x00000000", "EventName": "UNC_CHA_SNOOP_RESP.RSPIFWD", "BriefDescription": "RspIFwd Snoop Responses Received", - "PublicDescription": "Counts when a a transaction with the opcode type RspIFwd Snoop Response was received which indicates a remote caching agent forwarded the data and the requesting agent is able to acquire the data in E (Exclusive) or M (modified) states. This is commonly returned with RFO (the Read for Ownership issued before a write) transactions. The snoop could have either been to a cacheline in the M,E,F (Modified, Exclusive or Forward) states.", + "PublicDescription": "Counts when a transaction with the opcode type RspIFwd Snoop Response was received which indicates a remote caching agent forwarded the data and the requesting agent is able to acquire the data in E (Exclusive) or M (modified) states. This is commonly returned with RFO (the Read for Ownership issued before a write) transactions. The snoop could have either been to a cacheline in the M,E,F (Modified, Exclusive or Forward) states.", "Counter": "0,1,2,3", "ELLC": "0", "Filter": "na", @@ -5974,7 +5974,7 @@ "UMaskExt": "0x00000000", "EventName": "UNC_CHA_SNOOP_RESP.RSPSFWD", "BriefDescription": "RspSFwd Snoop Responses Received", - "PublicDescription": "Counts when a a transaction with the opcode type RspSFwd Snoop Response was received which indicates a remote caching agent forwarded the data but held on to its current copy. This is common for data and code reads that hit in a remote socket in E (Exclusive) or F (Forward) state.", + "PublicDescription": "Counts when a transaction with the opcode type RspSFwd Snoop Response was received which indicates a remote caching agent forwarded the data but held on to its current copy. This is common for data and code reads that hit in a remote socket in E (Exclusive) or F (Forward) state.", "Counter": "0,1,2,3", "ELLC": "0", "Filter": "na", @@ -18029,7 +18029,7 @@ "Unit": "IIO", "EventCode": "0xd5", "UMask": "0x01", - "PortMask": "0x0000", + "PortMask": "0x01", "FCMask": "0x07", "UMaskExt": "0x00070000", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0", @@ -18047,7 +18047,7 @@ "Unit": "IIO", "EventCode": "0xd5", "UMask": "0x80", - "PortMask": "0x0000", + "PortMask": "0x80", "FCMask": "0x07", "UMaskExt": "0x00070000", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART7", @@ -18065,7 +18065,7 @@ "Unit": "IIO", "EventCode": "0xd5", "UMask": "0x40", - "PortMask": "0x0000", + "PortMask": "0x40", "FCMask": "0x07", "UMaskExt": "0x00070000", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART6", @@ -18083,7 +18083,7 @@ "Unit": "IIO", "EventCode": "0xd5", "UMask": "0x20", - "PortMask": "0x0000", + "PortMask": "0x20", "FCMask": "0x07", "UMaskExt": "0x00070000", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART5", @@ -18101,7 +18101,7 @@ "Unit": "IIO", "EventCode": "0xd5", "UMask": "0x10", - "PortMask": "0x0000", + "PortMask": "0x10", "FCMask": "0x07", "UMaskExt": "0x00070000", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART4", @@ -18119,7 +18119,7 @@ "Unit": "IIO", "EventCode": "0xd5", "UMask": "0x08", - "PortMask": "0x0000", + "PortMask": "0x08", "FCMask": "0x07", "UMaskExt": "0x00070000", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3", @@ -18137,7 +18137,7 @@ "Unit": "IIO", "EventCode": "0xd5", "UMask": "0x04", - "PortMask": "0x0000", + "PortMask": "0x04", "FCMask": "0x07", "UMaskExt": "0x00070000", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2", @@ -18155,7 +18155,7 @@ "Unit": "IIO", "EventCode": "0xd5", "UMask": "0x02", - "PortMask": "0x0000", + "PortMask": "0x02", "FCMask": "0x07", "UMaskExt": "0x00070000", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1", @@ -18173,7 +18173,7 @@ "Unit": "IIO", "EventCode": "0xd5", "UMask": "0xff", - "PortMask": "0x00", + "PortMask": "0xff", "FCMask": "0x07", "UMaskExt": "0x00000000", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS", diff --git a/SRF/events/sierraforest_core.json b/SRF/events/sierraforest_core.json index cc1087b7..7abf4bc1 100644 --- a/SRF/events/sierraforest_core.json +++ b/SRF/events/sierraforest_core.json @@ -1,9 +1,9 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Xeon(R) 6 Processor with E-cores - V1.13", - "DatePublished": "10/17/2025", - "Version": "1.13", + "Info": "Performance Monitoring Events for Intel(R) Xeon(R) 6 Processor with E-cores - V1.14", + "DatePublished": "11/19/2025", + "Version": "1.14", "Legend": "" }, "Events": [ @@ -61,8 +61,8 @@ "EventCode": "0x00", "UMask": "0x02", "EventName": "CPU_CLK_UNHALTED.THREAD", - "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles", - "PublicDescription": "Fixed Counter: Counts the number of unhalted core clock cycles", + "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.CORE]", + "PublicDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.CORE]", "Counter": "Fixed counter 1", "PEBScounters": "33", "SampleAfterValue": "2000003", @@ -3664,12 +3664,12 @@ "BriefDescription": "Counts the number of cycles when any of the floating point dividers are active.", "PublicDescription": "Counts the number of cycles when any of the floating point dividers are active.", "Counter": "0,1,2,3,4,5,6,7", - "PEBScounters": "NA", + "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "1000003", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "0", - "CollectPEBSRecord": "0", + "CollectPEBSRecord": "2", "TakenAlone": "0", "CounterMask": "1", "Invert": "0", @@ -3689,12 +3689,12 @@ "BriefDescription": "Counts the number of cycles when any of the floating point or integer dividers are active.", "PublicDescription": "Counts the number of cycles when any of the floating point or integer dividers are active.", "Counter": "0,1,2,3,4,5,6,7", - "PEBScounters": "NA", + "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "1000003", "MSRIndex": "0x00", "MSRValue": "0x00", "Precise": "0", - "CollectPEBSRecord": "0", + "CollectPEBSRecord": "2", "TakenAlone": "0", "CounterMask": "1", "Invert": "0", @@ -3711,8 +3711,8 @@ "EventCode": "0xd0", "UMask": "0x05", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 8. Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 8. Only counts with PEBS enabled.", "Counter": "0,1", "PEBScounters": "0,1", "SampleAfterValue": "1000003", @@ -3736,8 +3736,8 @@ "EventCode": "0xd0", "UMask": "0x05", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 64. Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 64. Only counts with PEBS enabled.", "Counter": "0,1", "PEBScounters": "0,1", "SampleAfterValue": "1000003", @@ -3761,8 +3761,8 @@ "EventCode": "0xd0", "UMask": "0x05", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 512. Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 512. Only counts with PEBS enabled.", "Counter": "0,1", "PEBScounters": "0,1", "SampleAfterValue": "1000003", @@ -3786,8 +3786,8 @@ "EventCode": "0xd0", "UMask": "0x05", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 4. Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 4. Only counts with PEBS enabled.", "Counter": "0,1", "PEBScounters": "0,1", "SampleAfterValue": "1000003", @@ -3811,8 +3811,8 @@ "EventCode": "0xd0", "UMask": "0x05", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 32. Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 32. Only counts with PEBS enabled.", "Counter": "0,1", "PEBScounters": "0,1", "SampleAfterValue": "1000003", @@ -3836,8 +3836,8 @@ "EventCode": "0xd0", "UMask": "0x05", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 256. Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 256. Only counts with PEBS enabled.", "Counter": "0,1", "PEBScounters": "0,1", "SampleAfterValue": "1000003", @@ -3861,8 +3861,8 @@ "EventCode": "0xd0", "UMask": "0x05", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 16. Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 16. Only counts with PEBS enabled.", "Counter": "0,1", "PEBScounters": "0,1", "SampleAfterValue": "1000003", @@ -3886,8 +3886,8 @@ "EventCode": "0xd0", "UMask": "0x05", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 128. Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 128. Only counts with PEBS enabled.", "Counter": "0,1", "PEBScounters": "0,1", "SampleAfterValue": "1000003", @@ -3911,8 +3911,8 @@ "EventCode": "0xd0", "UMask": "0x05", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_2048", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 2048. Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 2048. Only counts with PEBS enabled.", "Counter": "0,1", "PEBScounters": "0,1", "SampleAfterValue": "1000003", @@ -3936,8 +3936,8 @@ "EventCode": "0xd0", "UMask": "0x05", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_1024", - "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", - "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 1024. Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 1024. Only counts with PEBS enabled.", "Counter": "0,1", "PEBScounters": "0,1", "SampleAfterValue": "1000003", @@ -3961,8 +3961,8 @@ "EventCode": "0xd0", "UMask": "0x06", "EventName": "MEM_UOPS_RETIRED.STORE_LATENCY", - "BriefDescription": "Counts the number of stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES", - "PublicDescription": "Counts the number of stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES", + "BriefDescription": "Counts the number of stores uops retired.", + "PublicDescription": "Counts the number of stores uops retired.", "Counter": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "1000003", diff --git a/SRF/events/sierraforest_uncore.json b/SRF/events/sierraforest_uncore.json index 90bd6417..069516f9 100644 --- a/SRF/events/sierraforest_uncore.json +++ b/SRF/events/sierraforest_uncore.json @@ -1,9 +1,9 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Xeon(R) 6 Processor with E-cores - V1.13", - "DatePublished": "10/17/2025", - "Version": "1.13", + "Info": "Performance Monitoring Events for Intel(R) Xeon(R) 6 Processor with E-cores - V1.14", + "DatePublished": "11/19/2025", + "Version": "1.14", "Legend": "" }, "Events": [ diff --git a/SRF/events/sierraforest_uncore_experimental.json b/SRF/events/sierraforest_uncore_experimental.json index 55d9fae6..6d67851e 100644 --- a/SRF/events/sierraforest_uncore_experimental.json +++ b/SRF/events/sierraforest_uncore_experimental.json @@ -1,9 +1,9 @@ { "Header": { "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", - "Info": "Performance Monitoring Events for Intel(R) Xeon(R) 6 Processor with E-cores - V1.13", - "DatePublished": "10/17/2025", - "Version": "1.13", + "Info": "Performance Monitoring Events for Intel(R) Xeon(R) 6 Processor with E-cores - V1.14", + "DatePublished": "11/19/2025", + "Version": "1.14", "Legend": "" }, "Events": [ diff --git a/mapfile.csv b/mapfile.csv index 8f0db884..0fb6b44c 100644 --- a/mapfile.csv +++ b/mapfile.csv @@ -139,13 +139,13 @@ GenuineIntel-6-8C,V1.19,/TGL/events/tigerlake_uncore_experimental.json,uncore ex GenuineIntel-6-8D,V1.19,/TGL/events/tigerlake_uncore_experimental.json,uncore experimental,,, GenuineIntel-6-8C,V1.1,/TGL/metrics/tigerlake_metrics.json,metrics,,, GenuineIntel-6-8D,V1.1,/TGL/metrics/tigerlake_metrics.json,metrics,,, -GenuineIntel-6-8F,V1.35,/SPR/events/sapphirerapids_core.json,core,,, -GenuineIntel-6-8F,V1.35,/SPR/events/sapphirerapids_uncore.json,uncore,,, -GenuineIntel-6-8F,V1.35,/SPR/events/sapphirerapids_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-8F,V1.36,/SPR/events/sapphirerapids_core.json,core,,, +GenuineIntel-6-8F,V1.36,/SPR/events/sapphirerapids_uncore.json,uncore,,, +GenuineIntel-6-8F,V1.36,/SPR/events/sapphirerapids_uncore_experimental.json,uncore experimental,,, GenuineIntel-6-8F,V1.2,/SPR/metrics/sapphirerapids_metrics.json,metrics,,, -GenuineIntel-6-CF,V1.20,/EMR/events/emeraldrapids_core.json,core,,, -GenuineIntel-6-CF,V1.20,/EMR/events/emeraldrapids_uncore.json,uncore,,, -GenuineIntel-6-CF,V1.20,/EMR/events/emeraldrapids_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-CF,V1.21,/EMR/events/emeraldrapids_core.json,core,,, +GenuineIntel-6-CF,V1.21,/EMR/events/emeraldrapids_uncore.json,uncore,,, +GenuineIntel-6-CF,V1.21,/EMR/events/emeraldrapids_uncore_experimental.json,uncore experimental,,, GenuineIntel-6-CF,V1.2,/EMR/metrics/emeraldrapids_metrics.json,metrics,,, GenuineIntel-6-6A,V1.30,/ICX/events/icelakex_core.json,core,,, GenuineIntel-6-6A,V1.30,/ICX/events/icelakex_uncore.json,uncore,,, @@ -157,84 +157,84 @@ GenuineIntel-6-6C,V1.30,/ICX/events/icelakex_uncore_experimental.json,uncore exp GenuineIntel-6-6C,V1.1,/ICX/metrics/icelakex_metrics.json,metrics,,, GenuineIntel-6-96,V1.05,/EHL/events/elkhartlake_core.json,core,,, GenuineIntel-6-9C,V1.05,/EHL/events/elkhartlake_core.json,core,,, -GenuineIntel-6-97,V1.35,/ADL/events/alderlake_gracemont_core.json,hybridcore,0x20,0x000001,Atom -GenuineIntel-6-97,V1.35,/ADL/events/alderlake_goldencove_core.json,hybridcore,0x40,0x000001,Core -GenuineIntel-6-97,V1.35,/ADL/events/alderlake_uncore.json,uncore,,, -GenuineIntel-6-97,V1.35,/ADL/events/alderlake_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-97,V1.36,/ADL/events/alderlake_gracemont_core.json,hybridcore,0x20,0x000001,Atom +GenuineIntel-6-97,V1.36,/ADL/events/alderlake_goldencove_core.json,hybridcore,0x40,0x000001,Core +GenuineIntel-6-97,V1.36,/ADL/events/alderlake_uncore.json,uncore,,, +GenuineIntel-6-97,V1.36,/ADL/events/alderlake_uncore_experimental.json,uncore experimental,,, GenuineIntel-6-97,V1.1,/ADL/metrics/alderlake_metrics_goldencove_core.json,metrics,0x40,0x000001,Core -GenuineIntel-6-9A,V1.35,/ADL/events/alderlake_gracemont_core.json,hybridcore,0x20,0x000001,Atom -GenuineIntel-6-9A,V1.35,/ADL/events/alderlake_goldencove_core.json,hybridcore,0x40,0x000001,Core -GenuineIntel-6-9A,V1.35,/ADL/events/alderlake_uncore.json,uncore,,, -GenuineIntel-6-9A,V1.35,/ADL/events/alderlake_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-9A,V1.36,/ADL/events/alderlake_gracemont_core.json,hybridcore,0x20,0x000001,Atom +GenuineIntel-6-9A,V1.36,/ADL/events/alderlake_goldencove_core.json,hybridcore,0x40,0x000001,Core +GenuineIntel-6-9A,V1.36,/ADL/events/alderlake_uncore.json,uncore,,, +GenuineIntel-6-9A,V1.36,/ADL/events/alderlake_uncore_experimental.json,uncore experimental,,, GenuineIntel-6-9A,V1.1,/ADL/metrics/alderlake_metrics_goldencove_core.json,metrics,0x40,0x000001,Core -GenuineIntel-6-B7,V1.35,/ADL/events/alderlake_gracemont_core.json,hybridcore,0x20,0x000001,Atom -GenuineIntel-6-B7,V1.35,/ADL/events/alderlake_goldencove_core.json,hybridcore,0x40,0x000001,Core -GenuineIntel-6-B7,V1.35,/ADL/events/alderlake_uncore.json,uncore,,, -GenuineIntel-6-B7,V1.35,/ADL/events/alderlake_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-B7,V1.36,/ADL/events/alderlake_gracemont_core.json,hybridcore,0x20,0x000001,Atom +GenuineIntel-6-B7,V1.36,/ADL/events/alderlake_goldencove_core.json,hybridcore,0x40,0x000001,Core +GenuineIntel-6-B7,V1.36,/ADL/events/alderlake_uncore.json,uncore,,, +GenuineIntel-6-B7,V1.36,/ADL/events/alderlake_uncore_experimental.json,uncore experimental,,, GenuineIntel-6-B7,V1.1,/ADL/metrics/alderlake_metrics_goldencove_core.json,metrics,0x40,0x000001,Core -GenuineIntel-6-BA,V1.35,/ADL/events/alderlake_gracemont_core.json,hybridcore,0x20,0x000001,Atom -GenuineIntel-6-BA,V1.35,/ADL/events/alderlake_goldencove_core.json,hybridcore,0x40,0x000001,Core -GenuineIntel-6-BA,V1.35,/ADL/events/alderlake_uncore.json,uncore,,, -GenuineIntel-6-BA,V1.35,/ADL/events/alderlake_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-BA,V1.36,/ADL/events/alderlake_gracemont_core.json,hybridcore,0x20,0x000001,Atom +GenuineIntel-6-BA,V1.36,/ADL/events/alderlake_goldencove_core.json,hybridcore,0x40,0x000001,Core +GenuineIntel-6-BA,V1.36,/ADL/events/alderlake_uncore.json,uncore,,, +GenuineIntel-6-BA,V1.36,/ADL/events/alderlake_uncore_experimental.json,uncore experimental,,, GenuineIntel-6-BA,V1.1,/ADL/metrics/alderlake_metrics_goldencove_core.json,metrics,0x40,0x000001,Core -GenuineIntel-6-BF,V1.35,/ADL/events/alderlake_gracemont_core.json,hybridcore,0x20,0x000001,Atom -GenuineIntel-6-BF,V1.35,/ADL/events/alderlake_goldencove_core.json,hybridcore,0x40,0x000001,Core -GenuineIntel-6-BF,V1.35,/ADL/events/alderlake_uncore.json,uncore,,, -GenuineIntel-6-BF,V1.35,/ADL/events/alderlake_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-BF,V1.36,/ADL/events/alderlake_gracemont_core.json,hybridcore,0x20,0x000001,Atom +GenuineIntel-6-BF,V1.36,/ADL/events/alderlake_goldencove_core.json,hybridcore,0x40,0x000001,Core +GenuineIntel-6-BF,V1.36,/ADL/events/alderlake_uncore.json,uncore,,, +GenuineIntel-6-BF,V1.36,/ADL/events/alderlake_uncore_experimental.json,uncore experimental,,, GenuineIntel-6-BF,V1.1,/ADL/metrics/alderlake_metrics_goldencove_core.json,metrics,0x40,0x000001,Core -GenuineIntel-6-BE,V1.35,/ADL/events/alderlake_gracemont_core.json,core,,, -GenuineIntel-6-BE,V1.35,/ADL/events/alderlake_uncore.json,uncore,,, -GenuineIntel-6-BE,V1.35,/ADL/events/alderlake_uncore_experimental.json,uncore experimental,,, -GenuineIntel-6-AA,V1.18,/MTL/events/meteorlake_crestmont_core.json,hybridcore,0x20,0x000002,Atom -GenuineIntel-6-AA,V1.18,/MTL/events/meteorlake_redwoodcove_core.json,hybridcore,0x40,0x000002,Core -GenuineIntel-6-AA,V1.18,/MTL/events/meteorlake_uncore.json,uncore,,, -GenuineIntel-6-AA,V1.18,/MTL/events/meteorlake_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-BE,V1.36,/ADL/events/alderlake_gracemont_core.json,core,,, +GenuineIntel-6-BE,V1.36,/ADL/events/alderlake_uncore.json,uncore,,, +GenuineIntel-6-BE,V1.36,/ADL/events/alderlake_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-AA,V1.19,/MTL/events/meteorlake_crestmont_core.json,hybridcore,0x20,0x000002,Atom +GenuineIntel-6-AA,V1.19,/MTL/events/meteorlake_redwoodcove_core.json,hybridcore,0x40,0x000002,Core +GenuineIntel-6-AA,V1.19,/MTL/events/meteorlake_uncore.json,uncore,,, +GenuineIntel-6-AA,V1.19,/MTL/events/meteorlake_uncore_experimental.json,uncore experimental,,, GenuineIntel-6-AA,V1.1,/MTL/metrics/meteorlake_metrics_redwoodcove_core.json,metrics,0x40,0x000002,Core -GenuineIntel-6-AC,V1.18,/MTL/events/meteorlake_crestmont_core.json,hybridcore,0x20,0x000002,Atom -GenuineIntel-6-AC,V1.18,/MTL/events/meteorlake_redwoodcove_core.json,hybridcore,0x40,0x000002,Core -GenuineIntel-6-AC,V1.18,/MTL/events/meteorlake_uncore.json,uncore,,, -GenuineIntel-6-AC,V1.18,/MTL/events/meteorlake_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-AC,V1.19,/MTL/events/meteorlake_crestmont_core.json,hybridcore,0x20,0x000002,Atom +GenuineIntel-6-AC,V1.19,/MTL/events/meteorlake_redwoodcove_core.json,hybridcore,0x40,0x000002,Core +GenuineIntel-6-AC,V1.19,/MTL/events/meteorlake_uncore.json,uncore,,, +GenuineIntel-6-AC,V1.19,/MTL/events/meteorlake_uncore_experimental.json,uncore experimental,,, GenuineIntel-6-AC,V1.1,/MTL/metrics/meteorlake_metrics_redwoodcove_core.json,metrics,0x40,0x000002,Core -GenuineIntel-6-B5,V1.18,/MTL/events/meteorlake_crestmont_core.json,hybridcore,0x20,0x000002,Atom -GenuineIntel-6-B5,V1.18,/MTL/events/meteorlake_redwoodcove_core.json,hybridcore,0x40,0x000002,Core -GenuineIntel-6-B5,V1.18,/MTL/events/meteorlake_uncore.json,uncore,,, -GenuineIntel-6-B5,V1.18,/MTL/events/meteorlake_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-B5,V1.19,/MTL/events/meteorlake_crestmont_core.json,hybridcore,0x20,0x000002,Atom +GenuineIntel-6-B5,V1.19,/MTL/events/meteorlake_redwoodcove_core.json,hybridcore,0x40,0x000002,Core +GenuineIntel-6-B5,V1.19,/MTL/events/meteorlake_uncore.json,uncore,,, +GenuineIntel-6-B5,V1.19,/MTL/events/meteorlake_uncore_experimental.json,uncore experimental,,, GenuineIntel-6-B5,V1.1,/MTL/metrics/meteorlake_metrics_redwoodcove_core.json,metrics,0x40,0x000002,Core -GenuineIntel-6-AD,V1.16,/GNR/events/graniterapids_core.json,core,,, -GenuineIntel-6-AD,V1.16,/GNR/events/graniterapids_uncore.json,uncore,,, -GenuineIntel-6-AD,V1.16,/GNR/events/graniterapids_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-AD,V1.17,/GNR/events/graniterapids_core.json,core,,, +GenuineIntel-6-AD,V1.17,/GNR/events/graniterapids_uncore.json,uncore,,, +GenuineIntel-6-AD,V1.17,/GNR/events/graniterapids_uncore_experimental.json,uncore experimental,,, GenuineIntel-6-AD,V1.1,/GNR/metrics/graniterapids_metrics.json,metrics,,, GenuineIntel-6-AD,V1.08,/GNR/metrics/graniterapids_retire_latency.json,retire latency,,, -GenuineIntel-6-AE,V1.16,/GNR/events/graniterapids_core.json,core,,, -GenuineIntel-6-AE,V1.16,/GNR/events/graniterapids_uncore.json,uncore,,, -GenuineIntel-6-AE,V1.16,/GNR/events/graniterapids_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-AE,V1.17,/GNR/events/graniterapids_core.json,core,,, +GenuineIntel-6-AE,V1.17,/GNR/events/graniterapids_uncore.json,uncore,,, +GenuineIntel-6-AE,V1.17,/GNR/events/graniterapids_uncore_experimental.json,uncore experimental,,, GenuineIntel-6-AE,V1.1,/GNR/metrics/graniterapids_metrics.json,metrics,,, GenuineIntel-6-AE,V1.08,/GNR/metrics/graniterapids_retire_latency.json,retire latency,,, -GenuineIntel-6-AF,V1.13,/SRF/events/sierraforest_core.json,core,,, -GenuineIntel-6-AF,V1.13,/SRF/events/sierraforest_uncore.json,uncore,,, -GenuineIntel-6-AF,V1.13,/SRF/events/sierraforest_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-AF,V1.14,/SRF/events/sierraforest_core.json,core,,, +GenuineIntel-6-AF,V1.14,/SRF/events/sierraforest_uncore.json,uncore,,, +GenuineIntel-6-AF,V1.14,/SRF/events/sierraforest_uncore_experimental.json,uncore experimental,,, GenuineIntel-6-AF,V1.02,/SRF/metrics/sierraforest_metrics.json,metrics,,, GenuineIntel-6-B6,V1.10,/GRR/events/grandridge_core.json,core,,, GenuineIntel-6-B6,V1.10,/GRR/events/grandridge_uncore.json,uncore,,, GenuineIntel-6-B6,V1.10,/GRR/events/grandridge_uncore_experimental.json,uncore experimental,,, GenuineIntel-6-B6,V1.02,/GRR/metrics/grandridge_metrics.json,metrics,,, -GenuineIntel-6-BD,V1.19,/LNL/events/lunarlake_skymont_core.json,hybridcore,0x20,0x000003,Atom -GenuineIntel-6-BD,V1.19,/LNL/events/lunarlake_lioncove_core.json,hybridcore,0x40,0x000003,Core -GenuineIntel-6-BD,V1.19,/LNL/events/lunarlake_uncore.json,uncore,,, -GenuineIntel-6-BD,V1.19,/LNL/events/lunarlake_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-BD,V1.20,/LNL/events/lunarlake_skymont_core.json,hybridcore,0x20,0x000003,Atom +GenuineIntel-6-BD,V1.20,/LNL/events/lunarlake_lioncove_core.json,hybridcore,0x40,0x000003,Core +GenuineIntel-6-BD,V1.20,/LNL/events/lunarlake_uncore.json,uncore,,, +GenuineIntel-6-BD,V1.20,/LNL/events/lunarlake_uncore_experimental.json,uncore experimental,,, GenuineIntel-6-BD,V1.1,/LNL/metrics/lunarlake_metrics_lioncove_core.json,metrics,0x40,0x000003,Core -GenuineIntel-6-C5,V1.14,/ARL/events/arrowlake_skymont_core.json,hybridcore,0x20,0x000003,Atom -GenuineIntel-6-C5,V1.14,/ARL/events/arrowlake_crestmont_core.json,hybridcore,0x20,0x000002,LowPower_Atom -GenuineIntel-6-C5,V1.14,/ARL/events/arrowlake_lioncove_core.json,hybridcore,0x40,0x000003,Core -GenuineIntel-6-C5,V1.14,/ARL/events/arrowlake_uncore.json,uncore,,, -GenuineIntel-6-C5,V1.14,/ARL/events/arrowlake_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-C5,V1.15,/ARL/events/arrowlake_skymont_core.json,hybridcore,0x20,0x000003,Atom +GenuineIntel-6-C5,V1.15,/ARL/events/arrowlake_crestmont_core.json,hybridcore,0x20,0x000002,LowPower_Atom +GenuineIntel-6-C5,V1.15,/ARL/events/arrowlake_lioncove_core.json,hybridcore,0x40,0x000003,Core +GenuineIntel-6-C5,V1.15,/ARL/events/arrowlake_uncore.json,uncore,,, +GenuineIntel-6-C5,V1.15,/ARL/events/arrowlake_uncore_experimental.json,uncore experimental,,, GenuineIntel-6-C5,V1.1,/ARL/metrics/arrowlake_metrics_lioncove_core.json,metrics,0x40,0x000003,Core -GenuineIntel-6-C6,V1.14,/ARL/events/arrowlake_skymont_core.json,hybridcore,0x20,0x000003,Atom -GenuineIntel-6-C6,V1.14,/ARL/events/arrowlake_lioncove_core.json,hybridcore,0x40,0x000003,Core -GenuineIntel-6-C6,V1.14,/ARL/events/arrowlake_uncore.json,uncore,,, -GenuineIntel-6-C6,V1.14,/ARL/events/arrowlake_uncore_experimental.json,uncore experimental,,, +GenuineIntel-6-C6,V1.15,/ARL/events/arrowlake_skymont_core.json,hybridcore,0x20,0x000003,Atom +GenuineIntel-6-C6,V1.15,/ARL/events/arrowlake_lioncove_core.json,hybridcore,0x40,0x000003,Core +GenuineIntel-6-C6,V1.15,/ARL/events/arrowlake_uncore.json,uncore,,, +GenuineIntel-6-C6,V1.15,/ARL/events/arrowlake_uncore_experimental.json,uncore experimental,,, GenuineIntel-6-C6,V1.1,/ARL/metrics/arrowlake_metrics_lioncove_core.json,metrics,0x40,0x000003,Core -GenuineIntel-6-CC,V1.02,/PTL/events/pantherlake_darkmont_core.json,hybridcore,0x20,0x000004,Atom -GenuineIntel-6-CC,V1.02,/PTL/events/pantherlake_cougarcove_core.json,hybridcore,0x40,0x000004,Core -GenuineIntel-6-CC,V1.02,/PTL/events/pantherlake_uncore.json,uncore,,, +GenuineIntel-6-CC,V1.03,/PTL/events/pantherlake_darkmont_core.json,hybridcore,0x20,0x000004,Atom +GenuineIntel-6-CC,V1.03,/PTL/events/pantherlake_cougarcove_core.json,hybridcore,0x40,0x000004,Core +GenuineIntel-6-CC,V1.03,/PTL/events/pantherlake_uncore.json,uncore,,, GenuineIntel-6-DD,V1.00,/CWF/events/clearwaterforest_core.json,core,,,