From d864dbbb74f2b9ad984c6ce7886abc24f1130478 Mon Sep 17 00:00:00 2001 From: Dmitry Bushev Date: Thu, 26 Nov 2020 16:07:07 +0300 Subject: [PATCH 01/81] Add passing CMEntry attribute through CM Adaptor CMEntry attribute now is passing through CM Adaptor and is converted to VCFCEntry --- GenXIntrinsics/include/llvm/GenXIntrinsics/GenXMetadata.h | 2 ++ GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp | 4 ++++ GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp | 4 ++++ 3 files changed, 10 insertions(+) diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXMetadata.h b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXMetadata.h index 7ec895e8..0003ab8d 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXMetadata.h +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXMetadata.h @@ -43,6 +43,7 @@ static constexpr const char GenXVolatile[] = "genx_volatile"; static constexpr const char CMGenXMain[] = "CMGenxMain"; static constexpr const char CMStackCall[] = "CMStackCall"; static constexpr const char CMCallable[] = "CMCallable"; +static constexpr const char CMEntry[] = "CMEntry"; static constexpr const char CMFloatControl[] = "CMFloatControl"; static constexpr const char CMGenxSIMT[] = "CMGenxSIMT"; static constexpr const char CMGenxReplicateMask[] = "CMGenxReplicateMask"; @@ -60,6 +61,7 @@ namespace VCFunctionMD { static constexpr const char VCFunction[] = "VCFunction"; static constexpr const char VCStackCall[] = "VCStackCall"; static constexpr const char VCCallable[] = "VCCallable"; +static constexpr const char VCFCEntry[] = "VCFCEntry"; static constexpr const char VCArgumentIOKind[] = "VCArgumentIOKind"; static constexpr const char VCFloatControl[] = "VCFloatControl"; static constexpr const char VCSLMSize[] = "VCSLMSize"; diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp index ab170a89..ee633c6c 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp @@ -441,6 +441,10 @@ bool GenXSPIRVReaderAdaptor::runOnFunction(Function &F) { F.addFnAttr(FunctionMD::CMCallable); } + if (Attrs.hasFnAttribute(VCFunctionMD::VCFCEntry)) { + F.addFnAttr(FunctionMD::CMEntry); + } + if (Attrs.hasFnAttribute(VCFunctionMD::VCSIMTCall)) { auto SIMTMode = StringRef(); SIMTMode = Attrs diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp index a6504283..16cc246d 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp @@ -492,6 +492,10 @@ bool GenXSPIRVWriterAdaptorImpl::runOnFunction(Function &F) { F.addFnAttr(VCFunctionMD::VCCallable); } + if (Attrs.hasFnAttribute(FunctionMD::CMEntry)) { + F.addFnAttr(VCFunctionMD::VCFCEntry); + } + if (Attrs.hasFnAttribute(FunctionMD::CMGenxSIMT)) { auto SIMTMode = StringRef(); SIMTMode = From ae497dcd2d86351feb1afa3479c06cdec61cb5c4 Mon Sep 17 00:00:00 2001 From: Aleksander Us Date: Tue, 23 Mar 2021 15:55:49 +0300 Subject: [PATCH 02/81] Sync changes Add gitignore. Update licences. --- .gitignore | 60 +++++++++++++++++++ CMakeLists.txt | 2 - .../llvm/GenXIntrinsics/GenXIntrinsicInst.h | 2 +- .../llvm/GenXIntrinsics/GenXIntrinsics.h | 3 +- .../llvm/GenXIntrinsics/GenXMetadata.h | 2 +- .../GenXIntrinsics/GenXSPIRVReaderAdaptor.h | 2 +- .../GenXIntrinsics/GenXSPIRVWriterAdaptor.h | 2 +- .../llvm/GenXIntrinsics/GenXSimdCFLowering.h | 2 +- .../GenXIntrinsics/Intrinsic_definitions.py | 2 +- .../include/llvm/GenXIntrinsics/Intrinsics.py | 2 +- .../include/llvmVCWrapper/IR/DerivedTypes.h | 2 +- .../include/llvmVCWrapper/IR/Function.h | 2 +- .../include/llvmVCWrapper/IR/GlobalValue.h | 2 +- .../include/llvmVCWrapper/IR/InstrTypes.h | 2 +- .../include/llvmVCWrapper/IR/Instructions.h | 2 +- .../include/llvmVCWrapper/Support/Alignment.h | 2 +- .../lib/GenXIntrinsics/AdaptorsCommon.h | 2 +- .../lib/GenXIntrinsics/GenXIntrinsics.cpp | 2 +- .../GenXIntrinsics/GenXRestoreIntrAttr.cpp | 2 +- .../GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp | 2 +- .../GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp | 2 +- .../lib/GenXIntrinsics/GenXSimdCFLowering.cpp | 2 +- .../GenXSingleElementVectorUtil.cpp | 2 +- .../GenXSingleElementVectorUtil.h | 2 +- GenXIntrinsics/test/Plugin/Plugin.cpp | 2 +- .../GenXIntrinsics/GenXIntrinsicsTest.cpp | 2 +- 26 files changed, 85 insertions(+), 26 deletions(-) create mode 100644 .gitignore diff --git a/.gitignore b/.gitignore new file mode 100644 index 00000000..5b8464f1 --- /dev/null +++ b/.gitignore @@ -0,0 +1,60 @@ +#==============================================================================# +# This file specifies intentionally untracked files that git should ignore. +# See: http://www.kernel.org/pub/software/scm/git/docs/gitignore.html +# +# This file is intentionally different from the output of `git svn show-ignore`, +# as most of those are useless. +#==============================================================================# + +#==============================================================================# +# File extensions to be ignored anywhere in the tree. +#==============================================================================# +# Temp files created by most text editors. +*~ +# Merge files created by git. +*.orig +# Byte compiled python modules. +*.pyc +# vim swap files +.*.sw? +.sw? +#OS X specific files. +.DS_store + +# Nested build directory +/build + +#==============================================================================# +# Explicit files to ignore (only matches one). +#==============================================================================# +# Various tag programs +/tags +/TAGS +/GPATH +/GRTAGS +/GSYMS +/GTAGS +.gitusers +autom4te.cache +cscope.files +cscope.out +autoconf/aclocal.m4 +autoconf/autom4te.cache +/compile_commands.json +tags +# Visual Studio built-in CMake configuration +/CMakeSettings.json +# CLion project configuration +/.idea + +#==============================================================================# +# Directories to ignore (do not add trailing '/'s, they skip symlinks). +#==============================================================================# +# Sphinx build tree, if building in-source dir. +GenXIntrinsics/docs/_build +GenXIntrinsics/docs/autogenerated +# VS2017 and VSCode config files. +.vscode +.vs +# clangd index +.clangd diff --git a/CMakeLists.txt b/CMakeLists.txt index 4dffb68e..914e9068 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -59,5 +59,3 @@ endif() add_subdirectory(GenXIntrinsics) - - diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsicInst.h b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsicInst.h index a3a4ec88..38619aed 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsicInst.h +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsicInst.h @@ -1,6 +1,6 @@ /*===================== begin_copyright_notice ================================== - Copyright (c) 2020, Intel Corporation + Copyright (c) 2021, Intel Corporation Permission is hereby granted, free of charge, to any person obtaining a diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h index 0fe1ea65..aea38859 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h @@ -1,6 +1,6 @@ /*===================== begin_copyright_notice ================================== - Copyright (c) 2020, Intel Corporation + Copyright (c) 2021, Intel Corporation Permission is hereby granted, free of charge, to any person obtaining a @@ -417,6 +417,7 @@ static inline bool isReadWritePredefReg(const Function *F) { isReadPredefReg(getGenXIntrinsicID(F)); } + } // namespace GenXIntrinsic // todo: delete this diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXMetadata.h b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXMetadata.h index 0003ab8d..25dfb058 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXMetadata.h +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXMetadata.h @@ -1,6 +1,6 @@ /*===================== begin_copyright_notice ================================== - Copyright (c) 2020, Intel Corporation + Copyright (c) 2021, Intel Corporation Permission is hereby granted, free of charge, to any person obtaining a diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSPIRVReaderAdaptor.h b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSPIRVReaderAdaptor.h index cec6737f..2b53908e 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSPIRVReaderAdaptor.h +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSPIRVReaderAdaptor.h @@ -1,6 +1,6 @@ /*===================== begin_copyright_notice ================================== - Copyright (c) 2020, Intel Corporation + Copyright (c) 2021, Intel Corporation Permission is hereby granted, free of charge, to any person obtaining a diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSPIRVWriterAdaptor.h b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSPIRVWriterAdaptor.h index c96a61bd..7afa646b 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSPIRVWriterAdaptor.h +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSPIRVWriterAdaptor.h @@ -1,6 +1,6 @@ /*===================== begin_copyright_notice ================================== - Copyright (c) 2020, Intel Corporation + Copyright (c) 2021, Intel Corporation Permission is hereby granted, free of charge, to any person obtaining a diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSimdCFLowering.h b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSimdCFLowering.h index 8b0b8056..9d1712fe 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSimdCFLowering.h +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSimdCFLowering.h @@ -1,6 +1,6 @@ /*===================== begin_copyright_notice ================================== - Copyright (c) 2020, Intel Corporation + Copyright (c) 2021, Intel Corporation Permission is hereby granted, free of charge, to any person obtaining a diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py index bfd22262..5f272a6c 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py @@ -1,7 +1,7 @@ #===================== begin_copyright_notice ================================== -#Copyright (c) 2020, Intel Corporation +#Copyright (c) 2021, Intel Corporation #Permission is hereby granted, free of charge, to any person obtaining a diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py index 49d4f682..19a46ed6 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py @@ -2,7 +2,7 @@ #===================== begin_copyright_notice ================================== -#Copyright (c) 2020, Intel Corporation +#Copyright (c) 2021, Intel Corporation #Permission is hereby granted, free of charge, to any person obtaining a diff --git a/GenXIntrinsics/include/llvmVCWrapper/IR/DerivedTypes.h b/GenXIntrinsics/include/llvmVCWrapper/IR/DerivedTypes.h index 56ce6c33..b6d7c27c 100644 --- a/GenXIntrinsics/include/llvmVCWrapper/IR/DerivedTypes.h +++ b/GenXIntrinsics/include/llvmVCWrapper/IR/DerivedTypes.h @@ -1,6 +1,6 @@ /*===================== begin_copyright_notice ================================== - Copyright (c) 2020, Intel Corporation + Copyright (c) 2021, Intel Corporation Permission is hereby granted, free of charge, to any person obtaining a diff --git a/GenXIntrinsics/include/llvmVCWrapper/IR/Function.h b/GenXIntrinsics/include/llvmVCWrapper/IR/Function.h index 6ed092e7..c649c3c2 100644 --- a/GenXIntrinsics/include/llvmVCWrapper/IR/Function.h +++ b/GenXIntrinsics/include/llvmVCWrapper/IR/Function.h @@ -1,6 +1,6 @@ /*===================== begin_copyright_notice ================================== - Copyright (c) 2020, Intel Corporation + Copyright (c) 2021, Intel Corporation Permission is hereby granted, free of charge, to any person obtaining a diff --git a/GenXIntrinsics/include/llvmVCWrapper/IR/GlobalValue.h b/GenXIntrinsics/include/llvmVCWrapper/IR/GlobalValue.h index 98a88f3a..820e16d2 100644 --- a/GenXIntrinsics/include/llvmVCWrapper/IR/GlobalValue.h +++ b/GenXIntrinsics/include/llvmVCWrapper/IR/GlobalValue.h @@ -1,6 +1,6 @@ /*===================== begin_copyright_notice ================================== - Copyright (c) 2020, Intel Corporation + Copyright (c) 2021, Intel Corporation Permission is hereby granted, free of charge, to any person obtaining a diff --git a/GenXIntrinsics/include/llvmVCWrapper/IR/InstrTypes.h b/GenXIntrinsics/include/llvmVCWrapper/IR/InstrTypes.h index a7fadef3..ebaac916 100644 --- a/GenXIntrinsics/include/llvmVCWrapper/IR/InstrTypes.h +++ b/GenXIntrinsics/include/llvmVCWrapper/IR/InstrTypes.h @@ -1,6 +1,6 @@ /*===================== begin_copyright_notice ================================== - Copyright (c) 2020, Intel Corporation + Copyright (c) 2021, Intel Corporation Permission is hereby granted, free of charge, to any person obtaining a diff --git a/GenXIntrinsics/include/llvmVCWrapper/IR/Instructions.h b/GenXIntrinsics/include/llvmVCWrapper/IR/Instructions.h index 1f1e08e3..119604c0 100644 --- a/GenXIntrinsics/include/llvmVCWrapper/IR/Instructions.h +++ b/GenXIntrinsics/include/llvmVCWrapper/IR/Instructions.h @@ -1,6 +1,6 @@ /*===================== begin_copyright_notice ================================== - Copyright (c) 2020, Intel Corporation + Copyright (c) 2021, Intel Corporation Permission is hereby granted, free of charge, to any person obtaining a diff --git a/GenXIntrinsics/include/llvmVCWrapper/Support/Alignment.h b/GenXIntrinsics/include/llvmVCWrapper/Support/Alignment.h index be2b8a4a..e36a5cf9 100644 --- a/GenXIntrinsics/include/llvmVCWrapper/Support/Alignment.h +++ b/GenXIntrinsics/include/llvmVCWrapper/Support/Alignment.h @@ -1,6 +1,6 @@ /*===================== begin_copyright_notice ================================== - Copyright (c) 2020, Intel Corporation + Copyright (c) 2021, Intel Corporation Permission is hereby granted, free of charge, to any person obtaining a diff --git a/GenXIntrinsics/lib/GenXIntrinsics/AdaptorsCommon.h b/GenXIntrinsics/lib/GenXIntrinsics/AdaptorsCommon.h index 82d1be7a..182a8fe4 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/AdaptorsCommon.h +++ b/GenXIntrinsics/lib/GenXIntrinsics/AdaptorsCommon.h @@ -1,6 +1,6 @@ /*===================== begin_copyright_notice ================================== - Copyright (c) 2020, Intel Corporation + Copyright (c) 2021, Intel Corporation Permission is hereby granted, free of charge, to any person obtaining a diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp index 1e7107e3..8a602277 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp @@ -1,6 +1,6 @@ /*===================== begin_copyright_notice ================================== - Copyright (c) 2020, Intel Corporation + Copyright (c) 2021, Intel Corporation Permission is hereby granted, free of charge, to any person obtaining a diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXRestoreIntrAttr.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXRestoreIntrAttr.cpp index c8fb6ce3..26ff2284 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXRestoreIntrAttr.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXRestoreIntrAttr.cpp @@ -1,6 +1,6 @@ /*===================== begin_copyright_notice ================================== - Copyright (c) 2020, Intel Corporation + Copyright (c) 2021, Intel Corporation Permission is hereby granted, free of charge, to any person obtaining a diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp index ee633c6c..9152f0d0 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp @@ -1,6 +1,6 @@ /*===================== begin_copyright_notice ================================== - Copyright (c) 2020, Intel Corporation + Copyright (c) 2021, Intel Corporation Permission is hereby granted, free of charge, to any person obtaining a diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp index 16cc246d..0c468b5e 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp @@ -1,6 +1,6 @@ /*===================== begin_copyright_notice ================================== - Copyright (c) 2020, Intel Corporation + Copyright (c) 2021, Intel Corporation Permission is hereby granted, free of charge, to any person obtaining a diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSimdCFLowering.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSimdCFLowering.cpp index 37f94706..42c32977 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSimdCFLowering.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSimdCFLowering.cpp @@ -1,6 +1,6 @@ /*===================== begin_copyright_notice ================================== - Copyright (c) 2020, Intel Corporation + Copyright (c) 2021, Intel Corporation Permission is hereby granted, free of charge, to any person obtaining a diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp index 6a22e479..a9ba783b 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp @@ -1,6 +1,6 @@ /*===================== begin_copyright_notice ================================== - Copyright (c) 2020, Intel Corporation + Copyright (c) 2021, Intel Corporation Permission is hereby granted, free of charge, to any person obtaining a diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.h b/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.h index 0378f630..9d94cbff 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.h +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.h @@ -1,6 +1,6 @@ /*===================== begin_copyright_notice ================================== - Copyright (c) 2020, Intel Corporation + Copyright (c) 2021, Intel Corporation Permission is hereby granted, free of charge, to any person obtaining a diff --git a/GenXIntrinsics/test/Plugin/Plugin.cpp b/GenXIntrinsics/test/Plugin/Plugin.cpp index 8ef522d4..38dd10f0 100644 --- a/GenXIntrinsics/test/Plugin/Plugin.cpp +++ b/GenXIntrinsics/test/Plugin/Plugin.cpp @@ -1,6 +1,6 @@ /*===================== begin_copyright_notice ================================== - Copyright (c) 2020, Intel Corporation + Copyright (c) 2021, Intel Corporation Permission is hereby granted, free of charge, to any person obtaining a diff --git a/GenXIntrinsics/unittests/GenXIntrinsics/GenXIntrinsicsTest.cpp b/GenXIntrinsics/unittests/GenXIntrinsics/GenXIntrinsicsTest.cpp index 8c8980ee..60a899e5 100644 --- a/GenXIntrinsics/unittests/GenXIntrinsics/GenXIntrinsicsTest.cpp +++ b/GenXIntrinsics/unittests/GenXIntrinsics/GenXIntrinsicsTest.cpp @@ -1,6 +1,6 @@ /*===================== begin_copyright_notice ================================== - Copyright (c) 2020, Intel Corporation + Copyright (c) 2021, Intel Corporation Permission is hereby granted, free of charge, to any person obtaining a From 0d75203e1e117334852cf43e5d3b7aa4c788500a Mon Sep 17 00:00:00 2001 From: Dmitry Bushev Date: Mon, 30 Nov 2020 15:59:12 +0300 Subject: [PATCH 03/81] Add interface to exctract hash commit of the build Added new GenXVersion.h file that contains up-to-date commit hash and repository url that sources came from. --- CMakeLists.txt | 2 + GenXIntrinsics/CMakeLists.txt | 2 + .../llvm/GenXIntrinsics/CMakeLists.txt | 30 ++++++++++++ .../GenXIntrinsics/ConfigureVersionFile.cmake | 14 ++++++ .../llvm/GenXIntrinsics/GenXIntrinsics.h | 1 + .../include/llvm/GenXIntrinsics/GenXVersion.h | 47 +++++++++++++++++++ .../lib/GenXIntrinsics/CMakeLists.txt | 2 + .../lib/GenXIntrinsics/GenXVersion.cpp | 47 +++++++++++++++++++ 8 files changed, 145 insertions(+) create mode 100644 GenXIntrinsics/include/llvm/GenXIntrinsics/ConfigureVersionFile.cmake create mode 100644 GenXIntrinsics/include/llvm/GenXIntrinsics/GenXVersion.h create mode 100644 GenXIntrinsics/lib/GenXIntrinsics/GenXVersion.cpp diff --git a/CMakeLists.txt b/CMakeLists.txt index 914e9068..10695079 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -2,6 +2,8 @@ cmake_minimum_required(VERSION 3.13.4) set(LLVM_GENX_INTRINSICS_VERSION 1.0) +set(LLVM_GENX_INTRINSICS_ROOT_DIR ${CMAKE_CURRENT_SOURCE_DIR}) + # check if we build inside llvm or not if(CMAKE_SOURCE_DIR STREQUAL CMAKE_CURRENT_SOURCE_DIR) get_filename_component(LLVM_CMAKE_PATH ${LLVM_DIR} ABSOLUTE BASE_DIR ${CMAKE_BINARY_DIR}) diff --git a/GenXIntrinsics/CMakeLists.txt b/GenXIntrinsics/CMakeLists.txt index 35c135ea..f30d74dd 100644 --- a/GenXIntrinsics/CMakeLists.txt +++ b/GenXIntrinsics/CMakeLists.txt @@ -3,6 +3,8 @@ include(GNUInstallDirs) set(GENX_INTRINSICS_MAIN_INCLUDE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/include) +set(GENX_INTRINSICS_MAIN_DIR ${CMAKE_CURRENT_SOURCE_DIR}) + if(IGC_INFRA) set(GENX_INTRINSICS_MAIN_INCLUDE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/include PARENT_SCOPE) endif() diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/CMakeLists.txt b/GenXIntrinsics/include/llvm/GenXIntrinsics/CMakeLists.txt index 1b4b9714..da4cc3f0 100755 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/CMakeLists.txt +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/CMakeLists.txt @@ -10,8 +10,38 @@ add_custom_command( COMMENT "Building ${GENX_INTRINSICS_DESCRIPTION}..." ) +find_first_existing_vc_file(intrinsics_vc "${GENX_INTRINSICS_MAIN_DIR}") + +set(version_inc ${CMAKE_CURRENT_BINARY_DIR}/GenXVersion.inc) + +if(${LLVM_VERSION_MAJOR} LESS 9) + find_file(FOUND_VCS GetSVN.cmake PATHS ${LLVM_CMAKE_DIR} REQUIRED) + add_custom_command( + OUTPUT "${version_inc}" + COMMAND + ${CMAKE_COMMAND} "-DSOURCE_DIRS=${LLVM_GENX_INTRINSICS_ROOT_DIR}" + "-DNAMES=VCI" + "-DHEADER_FILE=${version_inc}" + -P "${FOUND_VCS}") +else() + find_file(FOUND_VCS VersionFromVCS.cmake PATHS ${LLVM_CMAKE_DIR} REQUIRED) + add_custom_command( + OUTPUT "${version_inc}" + COMMAND + ${CMAKE_COMMAND} "-DSOURCE_DIR=${LLVM_GENX_INTRINSICS_ROOT_DIR}" + "-DNAME=VCI" + "-DHEADER_FILE=${version_inc}" + "-DVCS_SCRIPT=${FOUND_VCS}" + -P "${CMAKE_CURRENT_SOURCE_DIR}/ConfigureVersionFile.cmake") +endif() + +set_source_files_properties("${version_inc}" + PROPERTIES GENERATED TRUE + HEADER_FILE_ONLY TRUE) + add_custom_target(GenXIntrinsicDescriptionGen DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/${GENX_INTRINSICS_DESCRIPTION} + ${version_inc} ) add_custom_target(GenXIntrinsicsGen) add_dependencies(GenXIntrinsicsGen GenXIntrinsicDescriptionGen) diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/ConfigureVersionFile.cmake b/GenXIntrinsics/include/llvm/GenXIntrinsics/ConfigureVersionFile.cmake new file mode 100644 index 00000000..5516daa8 --- /dev/null +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/ConfigureVersionFile.cmake @@ -0,0 +1,14 @@ +include(${VCS_SCRIPT}) + +function(generate_version_file output_file) + get_source_info(${SOURCE_DIR} rev repo) + file(APPEND "${output_file}.txt" "#define ${NAME}_REVISION \"${rev}\"\n") + file(APPEND "${output_file}.txt" "#define ${NAME}_REPOSITORY \"${repo}\"\n") + execute_process(COMMAND ${CMAKE_COMMAND} -E copy_if_different + "${output_file}.txt" "${output_file}") + file(REMOVE "${output_file}.txt") + +endfunction() + +generate_version_file(${HEADER_FILE}) + diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h index aea38859..7b49da08 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h @@ -40,6 +40,7 @@ #include "llvm/IR/Function.h" #include "llvm/IR/Intrinsics.h" #include "llvm/IR/Instructions.h" +#include "llvm/GenXIntrinsics/GenXVersion.h" namespace llvm { diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXVersion.h b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXVersion.h new file mode 100644 index 00000000..d13a8ef3 --- /dev/null +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXVersion.h @@ -0,0 +1,47 @@ +/*===================== begin_copyright_notice ================================== + + Copyright (c) 2021, Intel Corporation + + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + OTHER DEALINGS IN THE SOFTWARE. +======================= end_copyright_notice ==================================*/ + + +//===----------------------------------------------------------------------===// +// +// This file declares interface functions used to aquire version info. +// +//===----------------------------------------------------------------------===// + +#ifndef GENX_VERSION +#define GENX_VERSION + +#include + +namespace llvm { + +namespace GenXIntrinsic { + +std::string getVCIntrinsicsRevision(); +std::string getVCIntrinsicsRepository(); + +}; // namespace GenXIntrinsic +}; // namespace llvm + +#endif diff --git a/GenXIntrinsics/lib/GenXIntrinsics/CMakeLists.txt b/GenXIntrinsics/lib/GenXIntrinsics/CMakeLists.txt index 33de403b..d0c9cbb8 100755 --- a/GenXIntrinsics/lib/GenXIntrinsics/CMakeLists.txt +++ b/GenXIntrinsics/lib/GenXIntrinsics/CMakeLists.txt @@ -13,6 +13,7 @@ if(BUILD_EXTERNAL) GenXSingleElementVectorUtil.cpp GenXSPIRVReaderAdaptor.cpp GenXSPIRVWriterAdaptor.cpp + GenXVersion.cpp ) llvm_update_compile_flags(LLVMGenXIntrinsics) add_dependencies(LLVMGenXIntrinsics GenXIntrinsicsGen) @@ -38,6 +39,7 @@ else() GenXSingleElementVectorUtil.cpp GenXSPIRVReaderAdaptor.cpp GenXSPIRVWriterAdaptor.cpp + GenXVersion.cpp ADDITIONAL_HEADER_DIRS ${GENX_INTRINSICS_MAIN_INCLUDE_DIR}/llvm/GenXIntrinsics diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXVersion.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXVersion.cpp new file mode 100644 index 00000000..5a43047f --- /dev/null +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXVersion.cpp @@ -0,0 +1,47 @@ +/*===================== begin_copyright_notice ================================== + + Copyright (c) 2021, Intel Corporation + + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + OTHER DEALINGS IN THE SOFTWARE. +======================= end_copyright_notice ==================================*/ + +/// +/// GenXVersion.cpp +/// --------------- +/// This source file defines interface functions to retrive version info. + +#include "llvm/GenXIntrinsics/GenXVersion.h" +#include "llvm/GenXIntrinsics/GenXVersion.inc" + +std::string llvm::GenXIntrinsic::getVCIntrinsicsRevision() { +#ifdef VCI_REVISION + return VCI_REVISION; +#else + return ""; +#endif +} + +std::string llvm::GenXIntrinsic::getVCIntrinsicsRepository() { +#ifdef VCI_REPOSITORY + return VCI_REPOSITORY; +#else + return ""; +#endif +} From a2869bbb76f43b3cbbb7d24893f142e91ee10e99 Mon Sep 17 00:00:00 2001 From: Dmitry Bushev Date: Thu, 3 Dec 2020 16:45:18 +0300 Subject: [PATCH 04/81] Fix in-tree GenXIntrinsics build fail Replacing usage of cmake variable not defined if built in-tree --- CMakeLists.txt | 2 -- GenXIntrinsics/include/llvm/GenXIntrinsics/CMakeLists.txt | 4 ++-- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 10695079..914e9068 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -2,8 +2,6 @@ cmake_minimum_required(VERSION 3.13.4) set(LLVM_GENX_INTRINSICS_VERSION 1.0) -set(LLVM_GENX_INTRINSICS_ROOT_DIR ${CMAKE_CURRENT_SOURCE_DIR}) - # check if we build inside llvm or not if(CMAKE_SOURCE_DIR STREQUAL CMAKE_CURRENT_SOURCE_DIR) get_filename_component(LLVM_CMAKE_PATH ${LLVM_DIR} ABSOLUTE BASE_DIR ${CMAKE_BINARY_DIR}) diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/CMakeLists.txt b/GenXIntrinsics/include/llvm/GenXIntrinsics/CMakeLists.txt index da4cc3f0..e1a14a5c 100755 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/CMakeLists.txt +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/CMakeLists.txt @@ -19,7 +19,7 @@ if(${LLVM_VERSION_MAJOR} LESS 9) add_custom_command( OUTPUT "${version_inc}" COMMAND - ${CMAKE_COMMAND} "-DSOURCE_DIRS=${LLVM_GENX_INTRINSICS_ROOT_DIR}" + ${CMAKE_COMMAND} "-DSOURCE_DIRS=${GENX_INTRINSICS_MAIN_DIR}" "-DNAMES=VCI" "-DHEADER_FILE=${version_inc}" -P "${FOUND_VCS}") @@ -28,7 +28,7 @@ else() add_custom_command( OUTPUT "${version_inc}" COMMAND - ${CMAKE_COMMAND} "-DSOURCE_DIR=${LLVM_GENX_INTRINSICS_ROOT_DIR}" + ${CMAKE_COMMAND} "-DSOURCE_DIR=${GENX_INTRINSICS_MAIN_DIR}" "-DNAME=VCI" "-DHEADER_FILE=${version_inc}" "-DVCS_SCRIPT=${FOUND_VCS}" From 3b10484a2c476e929c3a7eb2bd5f2302890d0f09 Mon Sep 17 00:00:00 2001 From: Dmitry Bushev Date: Fri, 12 Feb 2021 14:47:48 +0300 Subject: [PATCH 05/81] Fix version info collection Fix problem causing git version not being collected --- CMakeLists.txt | 2 ++ .../include/llvm/GenXIntrinsics/CMakeLists.txt | 10 ++++++++-- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 914e9068..10695079 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -2,6 +2,8 @@ cmake_minimum_required(VERSION 3.13.4) set(LLVM_GENX_INTRINSICS_VERSION 1.0) +set(LLVM_GENX_INTRINSICS_ROOT_DIR ${CMAKE_CURRENT_SOURCE_DIR}) + # check if we build inside llvm or not if(CMAKE_SOURCE_DIR STREQUAL CMAKE_CURRENT_SOURCE_DIR) get_filename_component(LLVM_CMAKE_PATH ${LLVM_DIR} ABSOLUTE BASE_DIR ${CMAKE_BINARY_DIR}) diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/CMakeLists.txt b/GenXIntrinsics/include/llvm/GenXIntrinsics/CMakeLists.txt index e1a14a5c..ed16edba 100755 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/CMakeLists.txt +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/CMakeLists.txt @@ -14,12 +14,18 @@ find_first_existing_vc_file(intrinsics_vc "${GENX_INTRINSICS_MAIN_DIR}") set(version_inc ${CMAKE_CURRENT_BINARY_DIR}/GenXVersion.inc) +if(LLVM_GENX_INTRINSICS_ROOT_DIR) + set(LLVM_GENX_INTRINSICS_REPO_DIR ${LLVM_GENX_INTRINSICS_ROOT_DIR}) +else() + set(LLVM_GENX_INTRINSICS_REPO_DIR ${GENX_INTRINSICS_MAIN_DIR}) +endif() + if(${LLVM_VERSION_MAJOR} LESS 9) find_file(FOUND_VCS GetSVN.cmake PATHS ${LLVM_CMAKE_DIR} REQUIRED) add_custom_command( OUTPUT "${version_inc}" COMMAND - ${CMAKE_COMMAND} "-DSOURCE_DIRS=${GENX_INTRINSICS_MAIN_DIR}" + ${CMAKE_COMMAND} "-DSOURCE_DIRS=${LLVM_GENX_INTRINSICS_REPO_DIR}" "-DNAMES=VCI" "-DHEADER_FILE=${version_inc}" -P "${FOUND_VCS}") @@ -28,7 +34,7 @@ else() add_custom_command( OUTPUT "${version_inc}" COMMAND - ${CMAKE_COMMAND} "-DSOURCE_DIR=${GENX_INTRINSICS_MAIN_DIR}" + ${CMAKE_COMMAND} "-DSOURCE_DIR=${LLVM_GENX_INTRINSICS_REPO_DIR}" "-DNAME=VCI" "-DHEADER_FILE=${version_inc}" "-DVCS_SCRIPT=${FOUND_VCS}" From 577fb7b7f4f4de6df252478e1740fca2eed0985c Mon Sep 17 00:00:00 2001 From: Anton Sidorenko Date: Thu, 18 Feb 2021 21:05:10 +0300 Subject: [PATCH 06/81] Remove unnecessary semicolons that throw warnings --- GenXIntrinsics/include/llvm/GenXIntrinsics/GenXVersion.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXVersion.h b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXVersion.h index d13a8ef3..2e03d82d 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXVersion.h +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXVersion.h @@ -41,7 +41,7 @@ namespace GenXIntrinsic { std::string getVCIntrinsicsRevision(); std::string getVCIntrinsicsRepository(); -}; // namespace GenXIntrinsic -}; // namespace llvm +} // namespace GenXIntrinsic +} // namespace llvm #endif From d547de9478277e14896fa6418f6bb07ac07d7a1b Mon Sep 17 00:00:00 2001 From: Dmitry Bushev Date: Thu, 4 Mar 2021 15:18:18 +0300 Subject: [PATCH 07/81] Fix for build that skips root vc-intrinsics dir Fix version retrive fail when building from GenXIntrinsics directory directly --- GenXIntrinsics/include/llvm/GenXIntrinsics/CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/CMakeLists.txt b/GenXIntrinsics/include/llvm/GenXIntrinsics/CMakeLists.txt index ed16edba..603b564d 100755 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/CMakeLists.txt +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/CMakeLists.txt @@ -17,7 +17,7 @@ set(version_inc ${CMAKE_CURRENT_BINARY_DIR}/GenXVersion.inc) if(LLVM_GENX_INTRINSICS_ROOT_DIR) set(LLVM_GENX_INTRINSICS_REPO_DIR ${LLVM_GENX_INTRINSICS_ROOT_DIR}) else() - set(LLVM_GENX_INTRINSICS_REPO_DIR ${GENX_INTRINSICS_MAIN_DIR}) + set(LLVM_GENX_INTRINSICS_REPO_DIR ${GENX_INTRINSICS_MAIN_DIR}/..) endif() if(${LLVM_VERSION_MAJOR} LESS 9) From e657f3bcec627d8c70524a8a282d706e2d0e16f2 Mon Sep 17 00:00:00 2001 From: Alexander Us Date: Mon, 29 Mar 2021 16:28:31 +0300 Subject: [PATCH 08/81] Small cleanup in intrinsics cmake Move add_definitions and include_directories to intrinsics CMake from other places. --- CMakeLists.txt | 4 ---- GenXIntrinsics/CMakeLists.txt | 6 ++++++ GenXIntrinsics/lib/CMakeLists.txt | 2 -- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 10695079..4a04dd89 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -41,10 +41,6 @@ else(CMAKE_SOURCE_DIR STREQUAL CMAKE_CURRENT_SOURCE_DIR) if (NOT LLVM_CMAKE_DIR) set(LLVM_CMAKE_DIR ${LLVM_CMAKE_PATH}) endif() - - # we require include_directories because other components may include intrinsics headers. - include_directories(${CMAKE_CURRENT_SOURCE_DIR}/GenXIntrinsics/include) - include_directories(${CMAKE_CURRENT_BINARY_DIR}/GenXIntrinsics/include) endif(CMAKE_SOURCE_DIR STREQUAL CMAKE_CURRENT_SOURCE_DIR) include(FindPythonInterp) diff --git a/GenXIntrinsics/CMakeLists.txt b/GenXIntrinsics/CMakeLists.txt index f30d74dd..409f152e 100644 --- a/GenXIntrinsics/CMakeLists.txt +++ b/GenXIntrinsics/CMakeLists.txt @@ -11,6 +11,12 @@ endif() include(cmake/utils.cmake) +# Global config. +add_compile_definitions(VC_INTR_LLVM_VERSION_MAJOR=${LLVM_VERSION_MAJOR}) + +include_directories(${CMAKE_CURRENT_SOURCE_DIR}/GenXIntrinsics/include) +include_directories(${CMAKE_CURRENT_BINARY_DIR}/GenXIntrinsics/include) + set(GENX_INTRINSICS_DESCRIPTION "GenXIntrinsicDescription.gen") add_subdirectory(include/llvm) diff --git a/GenXIntrinsics/lib/CMakeLists.txt b/GenXIntrinsics/lib/CMakeLists.txt index 76198d0d..d279a88a 100644 --- a/GenXIntrinsics/lib/CMakeLists.txt +++ b/GenXIntrinsics/lib/CMakeLists.txt @@ -1,3 +1 @@ -add_definitions(-DVC_INTR_LLVM_VERSION_MAJOR=${LLVM_VERSION_MAJOR}) - add_subdirectory(GenXIntrinsics) From 069ced1e8a408d8b602b3b210017603792df6260 Mon Sep 17 00:00:00 2001 From: Anatoly Parshintsev Date: Fri, 2 Apr 2021 09:47:11 +0300 Subject: [PATCH 09/81] implemented utility function to help with genx_XXmul construction --- .../include/llvm/GenXIntrinsics/GenXIntrinsics.h | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h index 7b49da08..d32aad88 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h @@ -271,7 +271,14 @@ static inline Function *getAnyDeclaration(Module *M, unsigned id, } } - +/// GenXIntrinsic::getGenXMulIID(S1, S2) - returns GenXIntrinsic::ID for +/// the enx_XXmul opertation, where XX is is defined by the input arguments +/// which represent signs of the operands +static inline GenXIntrinsic::ID getGenXMulIID(bool LHSign, bool RHSign) { + return LHSign + ? (RHSign ? GenXIntrinsic::genx_ssmul : GenXIntrinsic::genx_sumul) + : (RHSign ? GenXIntrinsic::genx_usmul : GenXIntrinsic::genx_uumul); +} static inline bool isRdRegion(unsigned IntrinID) { switch (IntrinID) { From 2d0795c6799d262a464e5e8b8f74b09dd3ec1054 Mon Sep 17 00:00:00 2001 From: Nikita Rudenko Date: Wed, 28 Apr 2021 14:48:21 +0300 Subject: [PATCH 10/81] Preserve comdat info in GenXSPIRV adaptors when rewrite types --- GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp | 1 + GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp | 1 + 2 files changed, 2 insertions(+) diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp index 9152f0d0..73c718b3 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp @@ -320,6 +320,7 @@ transformKernelSignature(Function &F, const std::vector &Descs) { NewF->copyAttributesFrom(&F); NewF->takeName(&F); NewF->copyMetadata(&F, 0); + NewF->setComdat(F.getComdat()); // Set appropriate argument attributes related to kind and desc. std::string ArgDesc; diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp index 0c468b5e..f835f42e 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp @@ -205,6 +205,7 @@ transformKernelSignature(Function &F, const std::vector &Descs) { NewF->copyAttributesFrom(&F); NewF->takeName(&F); NewF->copyMetadata(&F, 0); + NewF->setComdat(F.getComdat()); // Remove no more needed attributes. for (int i = 0, e = Descs.size(); i != e; ++i) { From 93d676bda36edd749472a610b756e33bfaf0e48b Mon Sep 17 00:00:00 2001 From: gvsharap Date: Mon, 7 Jun 2021 19:02:25 +0000 Subject: [PATCH 11/81] Fix comments --- .../include/llvm/GenXIntrinsics/Intrinsic_definitions.py | 1 - GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py | 1 - 2 files changed, 2 deletions(-) diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py index 5f272a6c..b82d278f 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py @@ -23,7 +23,6 @@ #TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE #SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - #======================= end_copyright_notice ================================== diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py index 19a46ed6..9f9e8077 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py @@ -24,7 +24,6 @@ #TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE #SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - #======================= end_copyright_notice ================================== From a94249a381a3797f2de087f2b24013778d02c912 Mon Sep 17 00:00:00 2001 From: Kirill Zhavoronkov Date: Wed, 2 Jun 2021 11:40:19 +0000 Subject: [PATCH 12/81] Update licenses --- CMakeLists.txt | 26 +++++++ GenXIntrinsics/CMakeLists.txt | 26 +++++++ GenXIntrinsics/cmake/utils.cmake | 26 +++++++ GenXIntrinsics/docs/GenXLangRef.rst | 27 +++++++ GenXIntrinsics/docs/LangRefIndex.rst | 27 +++++++ GenXIntrinsics/docs/Makefile.sphinx | 26 +++++++ GenXIntrinsics/docs/ReadMe.txt | 26 +++++++ GenXIntrinsics/docs/conf.py | 26 +++++++ GenXIntrinsics/include/llvm/CMakeLists.txt | 26 +++++++ .../llvm/GenXIntrinsics/CMakeLists.txt | 26 +++++++ .../GenXIntrinsics/ConfigureVersionFile.cmake | 26 +++++++ .../llvm/GenXIntrinsics/GenXIntrOpts.h | 44 ++++++++--- .../llvm/GenXIntrinsics/GenXIntrinsicInst.h | 49 ++++++------ .../llvm/GenXIntrinsics/GenXIntrinsics.h | 49 ++++++------ .../llvm/GenXIntrinsics/GenXMetadata.h | 49 ++++++------ .../GenXIntrinsics/GenXSPIRVReaderAdaptor.h | 48 ++++++------ .../GenXIntrinsics/GenXSPIRVWriterAdaptor.h | 38 +++++----- .../llvm/GenXIntrinsics/GenXSimdCFLowering.h | 61 +++++++-------- .../include/llvm/GenXIntrinsics/GenXVersion.h | 43 +++++------ .../GenXIntrinsics/Intrinsic_definitions.py | 53 +++++++------ .../include/llvm/GenXIntrinsics/Intrinsics.py | 52 +++++++------ .../include/llvmVCWrapper/IR/DerivedTypes.h | 39 +++++----- .../include/llvmVCWrapper/IR/Function.h | 49 ++++++------ .../include/llvmVCWrapper/IR/GlobalValue.h | 49 ++++++------ .../include/llvmVCWrapper/IR/InstrTypes.h | 49 ++++++------ .../include/llvmVCWrapper/IR/Instructions.h | 39 +++++----- .../include/llvmVCWrapper/Support/Alignment.h | 49 ++++++------ GenXIntrinsics/lib/CMakeLists.txt | 26 +++++++ .../lib/GenXIntrinsics/AdaptorsCommon.h | 43 +++++------ .../lib/GenXIntrinsics/CMakeLists.txt | 26 +++++++ .../lib/GenXIntrinsics/GenXIntrinsics.cpp | 74 +++++++++---------- .../GenXIntrinsics/GenXRestoreIntrAttr.cpp | 51 ++++++------- .../GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp | 55 +++++++------- .../GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp | 55 +++++++------- .../lib/GenXIntrinsics/GenXSimdCFLowering.cpp | 42 ++++++----- .../GenXSingleElementVectorUtil.cpp | 45 ++++++----- .../GenXSingleElementVectorUtil.h | 45 ++++++----- .../lib/GenXIntrinsics/GenXVersion.cpp | 55 +++++++------- .../test/Adaptors/annot_mess_writer.ll | 26 +++++++ .../Adaptors/annotated_args_mixed_reader.ll | 26 +++++++ .../Adaptors/annotated_args_no_conv_reader.ll | 26 +++++++ .../Adaptors/annotated_args_no_conv_writer.ll | 26 +++++++ .../test/Adaptors/annotated_args_reader.ll | 26 +++++++ .../test/Adaptors/annotated_args_writer.ll | 26 +++++++ .../test/Adaptors/combined_args_reader.ll | 26 +++++++ .../test/Adaptors/combined_args_writer.ll | 26 +++++++ .../test/Adaptors/empty_kernel_writer.ll | 26 +++++++ .../test/Adaptors/no_vcfunction_reader.ll | 26 +++++++ .../test/Adaptors/non_global_ptr_reader.ll | 26 +++++++ .../Adaptors/old_decorated_args_reader.ll | 26 +++++++ .../test/Adaptors/plain_args_reader.ll | 26 +++++++ .../test/Adaptors/plain_args_writer.ll | 26 +++++++ .../test/Adaptors/sev_signature_reader.ll | 26 +++++++ .../test/Adaptors/sev_signature_writer.ll | 26 +++++++ .../test/Adaptors/surface_access_reader.ll | 26 +++++++ .../test/Adaptors/surface_access_writer.ll | 26 +++++++ .../test/Adaptors/unknown_arg_reader.ll | 26 +++++++ .../test/Adaptors/unknown_arg_writer.ll | 26 +++++++ GenXIntrinsics/test/CMakeLists.txt | 26 +++++++ GenXIntrinsics/test/Plugin/CMakeLists.txt | 26 +++++++ GenXIntrinsics/test/Plugin/Plugin.cpp | 49 ++++++------ .../SimdCFLowering/bitcast_between_wrrs.ll | 26 +++++++ .../SimdCFLowering/predicate_masked_gather.ll | 26 +++++++ .../test/SimdCFLowering/replicate_mask.ll | 26 +++++++ .../replicate_mask_masked_gather4.ll | 26 +++++++ .../update_mask_masked_gather4.ll | 26 +++++++ GenXIntrinsics/test/lit.cfg.py | 26 +++++++ GenXIntrinsics/test/lit.site.cfg.py.in | 26 +++++++ GenXIntrinsics/unittests/CMakeLists.txt | 26 +++++++ .../unittests/GenXIntrinsics/CMakeLists.txt | 26 +++++++ .../GenXIntrinsics/GenXIntrinsicsTest.cpp | 49 ++++++------ License.md | 21 ------ Readme.md | 26 +++++++ 73 files changed, 1840 insertions(+), 676 deletions(-) create mode 100644 GenXIntrinsics/docs/ReadMe.txt mode change 100644 => 100755 GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsicInst.h mode change 100644 => 100755 GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h mode change 100644 => 100755 GenXIntrinsics/include/llvm/GenXIntrinsics/GenXMetadata.h mode change 100644 => 100755 GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSPIRVReaderAdaptor.h mode change 100644 => 100755 GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSPIRVWriterAdaptor.h mode change 100644 => 100755 GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py mode change 100644 => 100755 GenXIntrinsics/include/llvmVCWrapper/IR/Instructions.h mode change 100644 => 100755 GenXIntrinsics/include/llvmVCWrapper/Support/Alignment.h mode change 100644 => 100755 GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp mode change 100644 => 100755 GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp mode change 100644 => 100755 GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp mode change 100644 => 100755 GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp mode change 100644 => 100755 GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.h delete mode 100644 License.md diff --git a/CMakeLists.txt b/CMakeLists.txt index 4a04dd89..bb35d667 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -1,3 +1,29 @@ +#=========================== begin_copyright_notice ============================ +# +# Copyright (C) 2019-2021 Intel Corporation +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice (including the next +# paragraph) shall be included in all copies or substantial portions of the +# Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +# IN THE SOFTWARE. +# +# SPDX-License-Identifier: MIT +#============================ end_copyright_notice ============================= + cmake_minimum_required(VERSION 3.13.4) set(LLVM_GENX_INTRINSICS_VERSION 1.0) diff --git a/GenXIntrinsics/CMakeLists.txt b/GenXIntrinsics/CMakeLists.txt index 409f152e..1bd9896a 100644 --- a/GenXIntrinsics/CMakeLists.txt +++ b/GenXIntrinsics/CMakeLists.txt @@ -1,3 +1,29 @@ +#=========================== begin_copyright_notice ============================ +# +# Copyright (C) 2019-2021 Intel Corporation +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice (including the next +# paragraph) shall be included in all copies or substantial portions of the +# Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +# IN THE SOFTWARE. +# +# SPDX-License-Identifier: MIT +#============================ end_copyright_notice ============================= + cmake_minimum_required(VERSION 3.13.4) include(GNUInstallDirs) diff --git a/GenXIntrinsics/cmake/utils.cmake b/GenXIntrinsics/cmake/utils.cmake index b42a539c..07debda3 100644 --- a/GenXIntrinsics/cmake/utils.cmake +++ b/GenXIntrinsics/cmake/utils.cmake @@ -1,3 +1,29 @@ +#=========================== begin_copyright_notice ============================ +# +# Copyright (C) 2020-2021 Intel Corporation +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice (including the next +# paragraph) shall be included in all copies or substantial portions of the +# Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +# IN THE SOFTWARE. +# +# SPDX-License-Identifier: MIT +#============================ end_copyright_notice ============================= + # Convenience function to get list of LLVM components for # target_link_library. If LLVM was configured with llvm dylib, then # included in dylib llvm targets should be replaced with LLVM diff --git a/GenXIntrinsics/docs/GenXLangRef.rst b/GenXIntrinsics/docs/GenXLangRef.rst index ebab2ead..77290ac2 100644 --- a/GenXIntrinsics/docs/GenXLangRef.rst +++ b/GenXIntrinsics/docs/GenXLangRef.rst @@ -1,3 +1,30 @@ +.. + ========================== begin_copyright_notice ============================ + + Copyright (C) 2015-2021 Intel Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice (including the next + paragraph) shall be included in all copies or substantial portions of the + Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + IN THE SOFTWARE. + + SPDX-License-Identifier: MIT + =========================== end_copyright_notice ============================= + ============================ LLVM IR for the GenX backend ============================ diff --git a/GenXIntrinsics/docs/LangRefIndex.rst b/GenXIntrinsics/docs/LangRefIndex.rst index 7db6fedd..4f9682c2 100644 --- a/GenXIntrinsics/docs/LangRefIndex.rst +++ b/GenXIntrinsics/docs/LangRefIndex.rst @@ -1,3 +1,30 @@ +.. + ========================== begin_copyright_notice ============================ + + Copyright (C) 2019-2021 Intel Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice (including the next + paragraph) shall be included in all copies or substantial portions of the + Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + IN THE SOFTWARE. + + SPDX-License-Identifier: MIT + =========================== end_copyright_notice ============================= + VC Intrinsics documentation (language reference) ================================================== diff --git a/GenXIntrinsics/docs/Makefile.sphinx b/GenXIntrinsics/docs/Makefile.sphinx index 788f6e7e..8e86fbcf 100644 --- a/GenXIntrinsics/docs/Makefile.sphinx +++ b/GenXIntrinsics/docs/Makefile.sphinx @@ -1,3 +1,29 @@ +#=========================== begin_copyright_notice ============================ +# +# Copyright (C) 2019-2021 Intel Corporation +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice (including the next +# paragraph) shall be included in all copies or substantial portions of the +# Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +# IN THE SOFTWARE. +# +# SPDX-License-Identifier: MIT +#============================ end_copyright_notice ============================= + # Minimal makefile for Sphinx documentation # diff --git a/GenXIntrinsics/docs/ReadMe.txt b/GenXIntrinsics/docs/ReadMe.txt new file mode 100644 index 00000000..497212ab --- /dev/null +++ b/GenXIntrinsics/docs/ReadMe.txt @@ -0,0 +1,26 @@ + + diff --git a/GenXIntrinsics/docs/conf.py b/GenXIntrinsics/docs/conf.py index 64af9243..6f22f09f 100644 --- a/GenXIntrinsics/docs/conf.py +++ b/GenXIntrinsics/docs/conf.py @@ -1,3 +1,29 @@ +#=========================== begin_copyright_notice ============================ +# +# Copyright (C) 2019-2021 Intel Corporation +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice (including the next +# paragraph) shall be included in all copies or substantial portions of the +# Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +# IN THE SOFTWARE. +# +# SPDX-License-Identifier: MIT +#============================ end_copyright_notice ============================= + # -*- coding: utf-8 -*- # # VC Intrinsics documentation build configuration file. diff --git a/GenXIntrinsics/include/llvm/CMakeLists.txt b/GenXIntrinsics/include/llvm/CMakeLists.txt index d279a88a..9d617432 100644 --- a/GenXIntrinsics/include/llvm/CMakeLists.txt +++ b/GenXIntrinsics/include/llvm/CMakeLists.txt @@ -1 +1,27 @@ +#=========================== begin_copyright_notice ============================ +# +# Copyright (C) 2019-2021 Intel Corporation +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice (including the next +# paragraph) shall be included in all copies or substantial portions of the +# Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +# IN THE SOFTWARE. +# +# SPDX-License-Identifier: MIT +#============================ end_copyright_notice ============================= + add_subdirectory(GenXIntrinsics) diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/CMakeLists.txt b/GenXIntrinsics/include/llvm/GenXIntrinsics/CMakeLists.txt index 603b564d..ec65369b 100755 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/CMakeLists.txt +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/CMakeLists.txt @@ -1,3 +1,29 @@ +#=========================== begin_copyright_notice ============================ +# +# Copyright (C) 2019-2021 Intel Corporation +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice (including the next +# paragraph) shall be included in all copies or substantial portions of the +# Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +# IN THE SOFTWARE. +# +# SPDX-License-Identifier: MIT +#============================ end_copyright_notice ============================= + add_custom_command( OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${GENX_INTRINSICS_DESCRIPTION} COMMAND ${PYTHON_EXECUTABLE} -B diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/ConfigureVersionFile.cmake b/GenXIntrinsics/include/llvm/GenXIntrinsics/ConfigureVersionFile.cmake index 5516daa8..212490a9 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/ConfigureVersionFile.cmake +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/ConfigureVersionFile.cmake @@ -1,3 +1,29 @@ +#=========================== begin_copyright_notice ============================ +# +# Copyright (C) 2020-2021 Intel Corporation +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice (including the next +# paragraph) shall be included in all copies or substantial portions of the +# Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +# IN THE SOFTWARE. +# +# SPDX-License-Identifier: MIT +#============================ end_copyright_notice ============================= + include(${VCS_SCRIPT}) function(generate_version_file output_file) diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrOpts.h b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrOpts.h index 4441f784..f8296a52 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrOpts.h +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrOpts.h @@ -1,16 +1,38 @@ -//===-- GenXIntrOpts.h - GenX Transformations -------------------*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// +/*========================== begin_copyright_notice ============================ + +Copyright (C) 2020-2021 Intel Corporation + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +the rights to use, copy, modify, merge, publish, distribute, sublicense, +and/or sell copies of the Software, and to permit persons to whom the +Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +IN THE SOFTWARE. + +SPDX-License-Identifier: MIT +============================= end_copyright_notice ===========================*/ + +/*========================== begin_copyright_notice ============================ + +This file is distributed under the University of Illinois Open Source License. +See LICENSE.TXT for details. + +============================= end_copyright_notice ===========================*/ + // This header file defines prototypes for accessor functions that expose passes // in the GenX Intrinsics transformations library. -// -//===----------------------------------------------------------------------===// #ifndef LLVM_GENX_INTR_OPTS_H #define LLVM_GENX_INTR_OPTS_H diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsicInst.h b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsicInst.h old mode 100644 new mode 100755 index 38619aed..3d828568 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsicInst.h +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsicInst.h @@ -1,27 +1,28 @@ -/*===================== begin_copyright_notice ================================== - - Copyright (c) 2021, Intel Corporation - - - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - OTHER DEALINGS IN THE SOFTWARE. -======================= end_copyright_notice ==================================*/ - +/*========================== begin_copyright_notice ============================ + +Copyright (C) 2019-2021 Intel Corporation + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +the rights to use, copy, modify, merge, publish, distribute, sublicense, +and/or sell copies of the Software, and to permit persons to whom the +Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +IN THE SOFTWARE. + +SPDX-License-Identifier: MIT +============================= end_copyright_notice ===========================*/ //===----------------------------------------------------------------------===// // diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h old mode 100644 new mode 100755 index d32aad88..9f877fc8 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h @@ -1,27 +1,28 @@ -/*===================== begin_copyright_notice ================================== - - Copyright (c) 2021, Intel Corporation - - - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - OTHER DEALINGS IN THE SOFTWARE. -======================= end_copyright_notice ==================================*/ - +/*========================== begin_copyright_notice ============================ + +Copyright (C) 2019-2021 Intel Corporation + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +the rights to use, copy, modify, merge, publish, distribute, sublicense, +and/or sell copies of the Software, and to permit persons to whom the +Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +IN THE SOFTWARE. + +SPDX-License-Identifier: MIT +============================= end_copyright_notice ===========================*/ //===----------------------------------------------------------------------===// // diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXMetadata.h b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXMetadata.h old mode 100644 new mode 100755 index 25dfb058..122c8ed5 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXMetadata.h +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXMetadata.h @@ -1,27 +1,28 @@ -/*===================== begin_copyright_notice ================================== - - Copyright (c) 2021, Intel Corporation - - - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - OTHER DEALINGS IN THE SOFTWARE. -======================= end_copyright_notice ==================================*/ - +/*========================== begin_copyright_notice ============================ + +Copyright (C) 2020-2021 Intel Corporation + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +the rights to use, copy, modify, merge, publish, distribute, sublicense, +and/or sell copies of the Software, and to permit persons to whom the +Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +IN THE SOFTWARE. + +SPDX-License-Identifier: MIT +============================= end_copyright_notice ===========================*/ //===----------------------------------------------------------------------===// // diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSPIRVReaderAdaptor.h b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSPIRVReaderAdaptor.h old mode 100644 new mode 100755 index 2b53908e..a21b0d9a --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSPIRVReaderAdaptor.h +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSPIRVReaderAdaptor.h @@ -1,26 +1,28 @@ -/*===================== begin_copyright_notice ================================== - - Copyright (c) 2021, Intel Corporation - - - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - OTHER DEALINGS IN THE SOFTWARE. -======================= end_copyright_notice ==================================*/ +/*========================== begin_copyright_notice ============================ + +Copyright (C) 2020-2021 Intel Corporation + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +the rights to use, copy, modify, merge, publish, distribute, sublicense, +and/or sell copies of the Software, and to permit persons to whom the +Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +IN THE SOFTWARE. + +SPDX-License-Identifier: MIT +============================= end_copyright_notice ===========================*/ /// /// GenXSPIRVReaderAdaptor diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSPIRVWriterAdaptor.h b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSPIRVWriterAdaptor.h old mode 100644 new mode 100755 index 7afa646b..b877f76b --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSPIRVWriterAdaptor.h +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSPIRVWriterAdaptor.h @@ -1,26 +1,28 @@ -/*===================== begin_copyright_notice ================================== +/*========================== begin_copyright_notice ============================ - Copyright (c) 2021, Intel Corporation +Copyright (C) 2020-2021 Intel Corporation +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +the rights to use, copy, modify, merge, publish, distribute, sublicense, +and/or sell copies of the Software, and to permit persons to whom the +Software is furnished to do so, subject to the following conditions: - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +IN THE SOFTWARE. - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - OTHER DEALINGS IN THE SOFTWARE. -======================= end_copyright_notice ==================================*/ +SPDX-License-Identifier: MIT +============================= end_copyright_notice ===========================*/ /// /// GenXSPIRVWriterAdaptor diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSimdCFLowering.h b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSimdCFLowering.h index 9d1712fe..a10de7e6 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSimdCFLowering.h +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSimdCFLowering.h @@ -1,36 +1,31 @@ -/*===================== begin_copyright_notice ================================== - - Copyright (c) 2021, Intel Corporation - - - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - OTHER DEALINGS IN THE SOFTWARE. -======================= end_copyright_notice ==================================*/ - -//===----------------------------------------------------------------------===// -// -/// LowerCMSimdCF -/// ------------- -/// -/// This is the worker class to lowers CM SIMD control flow into a form where -/// the IR reflects the semantics. See CMSimdCFLowering.cpp for details. -/// -//===----------------------------------------------------------------------===// +/*========================== begin_copyright_notice ============================ + +Copyright (C) 2019-2021 Intel Corporation + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +the rights to use, copy, modify, merge, publish, distribute, sublicense, +and/or sell copies of the Software, and to permit persons to whom the +Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +IN THE SOFTWARE. + +SPDX-License-Identifier: MIT +============================= end_copyright_notice ===========================*/ + +// This is the worker class to lowers CM SIMD control flow into a form where +// the IR reflects the semantics. See CMSimdCFLowering.cpp for details. #ifndef CMSIMDCF_LOWER_H #define CMSIMDCF_LOWER_H diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXVersion.h b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXVersion.h index 2e03d82d..6d8b136d 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXVersion.h +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXVersion.h @@ -1,33 +1,30 @@ -/*===================== begin_copyright_notice ================================== +/*========================== begin_copyright_notice ============================ - Copyright (c) 2021, Intel Corporation +Copyright (C) 2020-2021 Intel Corporation +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +the rights to use, copy, modify, merge, publish, distribute, sublicense, +and/or sell copies of the Software, and to permit persons to whom the +Software is furnished to do so, subject to the following conditions: - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +IN THE SOFTWARE. - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - OTHER DEALINGS IN THE SOFTWARE. -======================= end_copyright_notice ==================================*/ +SPDX-License-Identifier: MIT +============================= end_copyright_notice ===========================*/ - -//===----------------------------------------------------------------------===// -// // This file declares interface functions used to aquire version info. -// -//===----------------------------------------------------------------------===// #ifndef GENX_VERSION #define GENX_VERSION diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py index b82d278f..a3afe361 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py @@ -1,31 +1,28 @@ - -#===================== begin_copyright_notice ================================== - -#Copyright (c) 2021, Intel Corporation - - -#Permission is hereby granted, free of charge, to any person obtaining a -#copy of this software and associated documentation files (the -#"Software"), to deal in the Software without restriction, including -#without limitation the rights to use, copy, modify, merge, publish, -#distribute, sublicense, and/or sell copies of the Software, and to -#permit persons to whom the Software is furnished to do so, subject to -#the following conditions: - -#The above copyright notice and this permission notice shall be included -#in all copies or substantial portions of the Software. - -#THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS -#OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -#MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -#IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY -#CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -#TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE -#SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -#======================= end_copyright_notice ================================== - - +#=========================== begin_copyright_notice ============================ +# +# Copyright (C) 2019-2021 Intel Corporation +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice (including the next +# paragraph) shall be included in all copies or substantial portions of the +# Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +# IN THE SOFTWARE. +# +# SPDX-License-Identifier: MIT +#============================ end_copyright_notice ============================= #===----------------------------------------------------------------------===// # diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py old mode 100644 new mode 100755 index 9f9e8077..94cbd7dc --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py @@ -1,32 +1,30 @@ #!/usr/bin/env python -#===================== begin_copyright_notice ================================== - -#Copyright (c) 2021, Intel Corporation - - -#Permission is hereby granted, free of charge, to any person obtaining a -#copy of this software and associated documentation files (the -#"Software"), to deal in the Software without restriction, including -#without limitation the rights to use, copy, modify, merge, publish, -#distribute, sublicense, and/or sell copies of the Software, and to -#permit persons to whom the Software is furnished to do so, subject to -#the following conditions: - -#The above copyright notice and this permission notice shall be included -#in all copies or substantial portions of the Software. - -#THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS -#OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -#MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -#IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY -#CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -#TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE -#SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -#======================= end_copyright_notice ================================== - - +#=========================== begin_copyright_notice ============================ +# +# Copyright (C) 2019-2021 Intel Corporation +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice (including the next +# paragraph) shall be included in all copies or substantial portions of the +# Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +# IN THE SOFTWARE. +# +# SPDX-License-Identifier: MIT +#============================ end_copyright_notice ============================= import os import sys diff --git a/GenXIntrinsics/include/llvmVCWrapper/IR/DerivedTypes.h b/GenXIntrinsics/include/llvmVCWrapper/IR/DerivedTypes.h index b6d7c27c..63e4b9b0 100644 --- a/GenXIntrinsics/include/llvmVCWrapper/IR/DerivedTypes.h +++ b/GenXIntrinsics/include/llvmVCWrapper/IR/DerivedTypes.h @@ -1,27 +1,28 @@ -/*===================== begin_copyright_notice ================================== +/*========================== begin_copyright_notice ============================ - Copyright (c) 2021, Intel Corporation +Copyright (C) 2020-2021 Intel Corporation +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +the rights to use, copy, modify, merge, publish, distribute, sublicense, +and/or sell copies of the Software, and to permit persons to whom the +Software is furnished to do so, subject to the following conditions: - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - OTHER DEALINGS IN THE SOFTWARE. -======================= end_copyright_notice ==================================*/ +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +IN THE SOFTWARE. +SPDX-License-Identifier: MIT +============================= end_copyright_notice ===========================*/ #ifndef VCINTR_IR_DERIVEDYPES_H #define VCINTR_IR_DERIVEDYPES_H diff --git a/GenXIntrinsics/include/llvmVCWrapper/IR/Function.h b/GenXIntrinsics/include/llvmVCWrapper/IR/Function.h index c649c3c2..076fe512 100644 --- a/GenXIntrinsics/include/llvmVCWrapper/IR/Function.h +++ b/GenXIntrinsics/include/llvmVCWrapper/IR/Function.h @@ -1,27 +1,28 @@ -/*===================== begin_copyright_notice ================================== - - Copyright (c) 2021, Intel Corporation - - - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - OTHER DEALINGS IN THE SOFTWARE. -======================= end_copyright_notice ==================================*/ - +/*========================== begin_copyright_notice ============================ + +Copyright (C) 2020-2021 Intel Corporation + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +the rights to use, copy, modify, merge, publish, distribute, sublicense, +and/or sell copies of the Software, and to permit persons to whom the +Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +IN THE SOFTWARE. + +SPDX-License-Identifier: MIT +============================= end_copyright_notice ===========================*/ #ifndef VCINTR_IR_FUNCTION_H #define VCINTR_IR_FUNCTION_H diff --git a/GenXIntrinsics/include/llvmVCWrapper/IR/GlobalValue.h b/GenXIntrinsics/include/llvmVCWrapper/IR/GlobalValue.h index 820e16d2..de2f016c 100644 --- a/GenXIntrinsics/include/llvmVCWrapper/IR/GlobalValue.h +++ b/GenXIntrinsics/include/llvmVCWrapper/IR/GlobalValue.h @@ -1,27 +1,28 @@ -/*===================== begin_copyright_notice ================================== - - Copyright (c) 2021, Intel Corporation - - - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - OTHER DEALINGS IN THE SOFTWARE. -======================= end_copyright_notice ==================================*/ - +/*========================== begin_copyright_notice ============================ + +Copyright (C) 2020-2021 Intel Corporation + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +the rights to use, copy, modify, merge, publish, distribute, sublicense, +and/or sell copies of the Software, and to permit persons to whom the +Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +IN THE SOFTWARE. + +SPDX-License-Identifier: MIT +============================= end_copyright_notice ===========================*/ #ifndef VCINTR_IR_GLOBALVALUE_H #define VCINTR_IR_GLOBALVALUE_H diff --git a/GenXIntrinsics/include/llvmVCWrapper/IR/InstrTypes.h b/GenXIntrinsics/include/llvmVCWrapper/IR/InstrTypes.h index ebaac916..cfcfa2c3 100644 --- a/GenXIntrinsics/include/llvmVCWrapper/IR/InstrTypes.h +++ b/GenXIntrinsics/include/llvmVCWrapper/IR/InstrTypes.h @@ -1,27 +1,28 @@ -/*===================== begin_copyright_notice ================================== - - Copyright (c) 2021, Intel Corporation - - - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - OTHER DEALINGS IN THE SOFTWARE. -======================= end_copyright_notice ==================================*/ - +/*========================== begin_copyright_notice ============================ + +Copyright (C) 2020-2021 Intel Corporation + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +the rights to use, copy, modify, merge, publish, distribute, sublicense, +and/or sell copies of the Software, and to permit persons to whom the +Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +IN THE SOFTWARE. + +SPDX-License-Identifier: MIT +============================= end_copyright_notice ===========================*/ #ifndef VCINTR_IR_INSTRTYPES_H #define VCINTR_IR_INSTRTYPES_H diff --git a/GenXIntrinsics/include/llvmVCWrapper/IR/Instructions.h b/GenXIntrinsics/include/llvmVCWrapper/IR/Instructions.h old mode 100644 new mode 100755 index 119604c0..144c24dd --- a/GenXIntrinsics/include/llvmVCWrapper/IR/Instructions.h +++ b/GenXIntrinsics/include/llvmVCWrapper/IR/Instructions.h @@ -1,27 +1,28 @@ -/*===================== begin_copyright_notice ================================== +/*========================== begin_copyright_notice ============================ - Copyright (c) 2021, Intel Corporation +Copyright (C) 2020-2021 Intel Corporation +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +the rights to use, copy, modify, merge, publish, distribute, sublicense, +and/or sell copies of the Software, and to permit persons to whom the +Software is furnished to do so, subject to the following conditions: - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - OTHER DEALINGS IN THE SOFTWARE. -======================= end_copyright_notice ==================================*/ +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +IN THE SOFTWARE. +SPDX-License-Identifier: MIT +============================= end_copyright_notice ===========================*/ #ifndef VCINTR_IR_INSTRUCTIONS_H #define VCINTR_IR_INSTRUCTIONS_H diff --git a/GenXIntrinsics/include/llvmVCWrapper/Support/Alignment.h b/GenXIntrinsics/include/llvmVCWrapper/Support/Alignment.h old mode 100644 new mode 100755 index e36a5cf9..ddaa03c8 --- a/GenXIntrinsics/include/llvmVCWrapper/Support/Alignment.h +++ b/GenXIntrinsics/include/llvmVCWrapper/Support/Alignment.h @@ -1,27 +1,28 @@ -/*===================== begin_copyright_notice ================================== - - Copyright (c) 2021, Intel Corporation - - - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - OTHER DEALINGS IN THE SOFTWARE. -======================= end_copyright_notice ==================================*/ - +/*========================== begin_copyright_notice ============================ + +Copyright (C) 2020-2021 Intel Corporation + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +the rights to use, copy, modify, merge, publish, distribute, sublicense, +and/or sell copies of the Software, and to permit persons to whom the +Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +IN THE SOFTWARE. + +SPDX-License-Identifier: MIT +============================= end_copyright_notice ===========================*/ #ifndef VCINTR_IR_ALIGNMENT_H #define VCINTR_IR_ALIGNMENT_H diff --git a/GenXIntrinsics/lib/CMakeLists.txt b/GenXIntrinsics/lib/CMakeLists.txt index d279a88a..9d617432 100644 --- a/GenXIntrinsics/lib/CMakeLists.txt +++ b/GenXIntrinsics/lib/CMakeLists.txt @@ -1 +1,27 @@ +#=========================== begin_copyright_notice ============================ +# +# Copyright (C) 2019-2021 Intel Corporation +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice (including the next +# paragraph) shall be included in all copies or substantial portions of the +# Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +# IN THE SOFTWARE. +# +# SPDX-License-Identifier: MIT +#============================ end_copyright_notice ============================= + add_subdirectory(GenXIntrinsics) diff --git a/GenXIntrinsics/lib/GenXIntrinsics/AdaptorsCommon.h b/GenXIntrinsics/lib/GenXIntrinsics/AdaptorsCommon.h index 182a8fe4..d88163c2 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/AdaptorsCommon.h +++ b/GenXIntrinsics/lib/GenXIntrinsics/AdaptorsCommon.h @@ -1,33 +1,30 @@ -/*===================== begin_copyright_notice ================================== +/*========================== begin_copyright_notice ============================ - Copyright (c) 2021, Intel Corporation +Copyright (C) 2020-2021 Intel Corporation +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +the rights to use, copy, modify, merge, publish, distribute, sublicense, +and/or sell copies of the Software, and to permit persons to whom the +Software is furnished to do so, subject to the following conditions: - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +IN THE SOFTWARE. - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - OTHER DEALINGS IN THE SOFTWARE. -======================= end_copyright_notice ==================================*/ +SPDX-License-Identifier: MIT +============================= end_copyright_notice ===========================*/ - -//===----------------------------------------------------------------------===// -// // This file defines common constants for writer/reader spirv adaptors. -// -//===----------------------------------------------------------------------===// namespace llvm { namespace genx { diff --git a/GenXIntrinsics/lib/GenXIntrinsics/CMakeLists.txt b/GenXIntrinsics/lib/GenXIntrinsics/CMakeLists.txt index d0c9cbb8..e6dbd6ab 100755 --- a/GenXIntrinsics/lib/GenXIntrinsics/CMakeLists.txt +++ b/GenXIntrinsics/lib/GenXIntrinsics/CMakeLists.txt @@ -1,3 +1,29 @@ +#=========================== begin_copyright_notice ============================ +# +# Copyright (C) 2019-2021 Intel Corporation +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice (including the next +# paragraph) shall be included in all copies or substantial portions of the +# Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +# IN THE SOFTWARE. +# +# SPDX-License-Identifier: MIT +#============================ end_copyright_notice ============================= + set(LLVM_COMPONENTS CodeGen Support diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp old mode 100644 new mode 100755 index 8a602277..5a82441d --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp @@ -1,42 +1,40 @@ -/*===================== begin_copyright_notice ================================== - - Copyright (c) 2021, Intel Corporation - - - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - OTHER DEALINGS IN THE SOFTWARE. -======================= end_copyright_notice ==================================*/ - - -/** Originated from llvm source lib/IR/Function.cpp **/ - -//===- Function.cpp - Implement the Global object classes -----------------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// +/*========================== begin_copyright_notice ============================ + +Copyright (C) 2019-2021 Intel Corporation + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +the rights to use, copy, modify, merge, publish, distribute, sublicense, +and/or sell copies of the Software, and to permit persons to whom the +Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +IN THE SOFTWARE. + +SPDX-License-Identifier: MIT +============================= end_copyright_notice ===========================*/ + +/*========================== begin_copyright_notice ============================ + +This file is distributed under the University of Illinois Open Source License. +See LICENSE.TXT for details. + +============================= end_copyright_notice ===========================*/ + +// Originated from llvm source lib/IR/Function.cpp +// Function.cpp - Implement the Global object classes + // Implementation of methods declared in llvm/GenXIntrinsics/GenXIntrinsics.h -// -//===----------------------------------------------------------------------===// #include "llvm/GenXIntrinsics/GenXIntrinsics.h" diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXRestoreIntrAttr.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXRestoreIntrAttr.cpp index 26ff2284..9627ac5f 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXRestoreIntrAttr.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXRestoreIntrAttr.cpp @@ -1,35 +1,36 @@ -/*===================== begin_copyright_notice ================================== +/*========================== begin_copyright_notice ============================ - Copyright (c) 2021, Intel Corporation +Copyright (C) 2020-2021 Intel Corporation +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +the rights to use, copy, modify, merge, publish, distribute, sublicense, +and/or sell copies of the Software, and to permit persons to whom the +Software is furnished to do so, subject to the following conditions: - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +IN THE SOFTWARE. - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - OTHER DEALINGS IN THE SOFTWARE. -======================= end_copyright_notice ==================================*/ +SPDX-License-Identifier: MIT +============================= end_copyright_notice ===========================*/ +/*========================== begin_copyright_notice ============================ + +This file is distributed under the University of Illinois Open Source License. +See LICENSE.TXT for details. + +============================= end_copyright_notice ===========================*/ -//===-- GenXRestoreIntrAttr.cpp - GenX Restore Intrinsics' attributes pass --===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// //===----------------------------------------------------------------------===// // /// GenXRestoreIntrAttr diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp old mode 100644 new mode 100755 index 73c718b3..1224ce77 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp @@ -1,31 +1,30 @@ -/*===================== begin_copyright_notice ================================== - - Copyright (c) 2021, Intel Corporation - - - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - OTHER DEALINGS IN THE SOFTWARE. -======================= end_copyright_notice ==================================*/ - -/// -/// GenXSPIRVReaderAdaptor -/// --------------------------- -/// This pass converts metadata from SPIRV format to whichever used in backend +/*========================== begin_copyright_notice ============================ + +Copyright (C) 2020-2021 Intel Corporation + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +the rights to use, copy, modify, merge, publish, distribute, sublicense, +and/or sell copies of the Software, and to permit persons to whom the +Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +IN THE SOFTWARE. + +SPDX-License-Identifier: MIT +============================= end_copyright_notice ===========================*/ + +// This pass converts metadata from SPIRV format to whichever used in backend. #include "AdaptorsCommon.h" #include "GenXSingleElementVectorUtil.h" diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp old mode 100644 new mode 100755 index f835f42e..8cbf1227 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp @@ -1,31 +1,30 @@ -/*===================== begin_copyright_notice ================================== - - Copyright (c) 2021, Intel Corporation - - - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - OTHER DEALINGS IN THE SOFTWARE. -======================= end_copyright_notice ==================================*/ - -/// -/// GenXSPIRVWriterAdaptor -/// --------------------------- -/// This pass converts metadata to SPIRV format from whichever used in frontend +/*========================== begin_copyright_notice ============================ + +Copyright (C) 2020-2021 Intel Corporation + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +the rights to use, copy, modify, merge, publish, distribute, sublicense, +and/or sell copies of the Software, and to permit persons to whom the +Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +IN THE SOFTWARE. + +SPDX-License-Identifier: MIT +============================= end_copyright_notice ===========================*/ + +// This pass converts metadata to SPIRV format from whichever used in frontend. #include "AdaptorsCommon.h" #include "GenXSingleElementVectorUtil.h" diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSimdCFLowering.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSimdCFLowering.cpp index 42c32977..baa6ebf8 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSimdCFLowering.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSimdCFLowering.cpp @@ -1,29 +1,31 @@ -/*===================== begin_copyright_notice ================================== +/*========================== begin_copyright_notice ============================ - Copyright (c) 2021, Intel Corporation +Copyright (C) 2015-2021 Intel Corporation +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +the rights to use, copy, modify, merge, publish, distribute, sublicense, +and/or sell copies of the Software, and to permit persons to whom the +Software is furnished to do so, subject to the following conditions: - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +IN THE SOFTWARE. - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - OTHER DEALINGS IN THE SOFTWARE. -======================= end_copyright_notice ==================================*/ +SPDX-License-Identifier: MIT +============================= end_copyright_notice ===========================*/ + +// Lower CM SIMD control flow -//===----------------------------------------------------------------------===// -// /// CMSimdCFLowering /// ---------------- /// diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp old mode 100644 new mode 100755 index a9ba783b..6232ee0b --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp @@ -1,34 +1,31 @@ -/*===================== begin_copyright_notice ================================== +/*========================== begin_copyright_notice ============================ - Copyright (c) 2021, Intel Corporation +Copyright (C) 2020-2021 Intel Corporation +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +the rights to use, copy, modify, merge, publish, distribute, sublicense, +and/or sell copies of the Software, and to permit persons to whom the +Software is furnished to do so, subject to the following conditions: - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +IN THE SOFTWARE. - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - OTHER DEALINGS IN THE SOFTWARE. -======================= end_copyright_notice ==================================*/ +SPDX-License-Identifier: MIT +============================= end_copyright_notice ===========================*/ - -//===----------------------------------------------------------------------===// -// // This file defines common functions for rewriting single element vectors -// in GenXSPIRV adaptors -// -//===----------------------------------------------------------------------===// +// in GenXSPIRV adaptors. #include "GenXSingleElementVectorUtil.h" #include "llvm/GenXIntrinsics/GenXIntrinsics.h" diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.h b/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.h old mode 100644 new mode 100755 index 9d94cbff..ec5c9b0c --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.h +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.h @@ -1,34 +1,31 @@ -/*===================== begin_copyright_notice ================================== +/*========================== begin_copyright_notice ============================ - Copyright (c) 2021, Intel Corporation +Copyright (C) 2020-2021 Intel Corporation +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +the rights to use, copy, modify, merge, publish, distribute, sublicense, +and/or sell copies of the Software, and to permit persons to whom the +Software is furnished to do so, subject to the following conditions: - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +IN THE SOFTWARE. - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - OTHER DEALINGS IN THE SOFTWARE. -======================= end_copyright_notice ==================================*/ +SPDX-License-Identifier: MIT +============================= end_copyright_notice ===========================*/ - -//===----------------------------------------------------------------------===// -// // This file declares functions for rewriting single element vectors -// in GenXSPIRV adaptors -// -//===----------------------------------------------------------------------===// +// in GenXSPIRV adaptors. #include "llvm/IR/Module.h" diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXVersion.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXVersion.cpp index 5a43047f..d4f63c25 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXVersion.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXVersion.cpp @@ -1,31 +1,30 @@ -/*===================== begin_copyright_notice ================================== - - Copyright (c) 2021, Intel Corporation - - - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - OTHER DEALINGS IN THE SOFTWARE. -======================= end_copyright_notice ==================================*/ - -/// -/// GenXVersion.cpp -/// --------------- -/// This source file defines interface functions to retrive version info. +/*========================== begin_copyright_notice ============================ + +Copyright (C) 2020-2021 Intel Corporation + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +the rights to use, copy, modify, merge, publish, distribute, sublicense, +and/or sell copies of the Software, and to permit persons to whom the +Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +IN THE SOFTWARE. + +SPDX-License-Identifier: MIT +============================= end_copyright_notice ===========================*/ + +// This source file defines interface functions to retrive version info. #include "llvm/GenXIntrinsics/GenXVersion.h" #include "llvm/GenXIntrinsics/GenXVersion.inc" diff --git a/GenXIntrinsics/test/Adaptors/annot_mess_writer.ll b/GenXIntrinsics/test/Adaptors/annot_mess_writer.ll index 9f817005..e5e3cd15 100644 --- a/GenXIntrinsics/test/Adaptors/annot_mess_writer.ll +++ b/GenXIntrinsics/test/Adaptors/annot_mess_writer.ll @@ -1,3 +1,29 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2020-2021 Intel Corporation +; +; Permission is hereby granted, free of charge, to any person obtaining a copy +; of this software and associated documentation files (the "Software"), +; to deal in the Software without restriction, including without limitation +; the rights to use, copy, modify, merge, publish, distribute, sublicense, +; and/or sell copies of the Software, and to permit persons to whom the +; Software is furnished to do so, subject to the following conditions: +; +; The above copyright notice and this permission notice (including the next +; paragraph) shall be included in all copies or substantial portions of the +; Software. +; +; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +; FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +; IN THE SOFTWARE. +; +; SPDX-License-Identifier: MIT +;============================ end_copyright_notice ============================= + ; Test messy annnotations translation in writer. First valid ; annotation should be matched. diff --git a/GenXIntrinsics/test/Adaptors/annotated_args_mixed_reader.ll b/GenXIntrinsics/test/Adaptors/annotated_args_mixed_reader.ll index 59f0f74a..daadd393 100644 --- a/GenXIntrinsics/test/Adaptors/annotated_args_mixed_reader.ll +++ b/GenXIntrinsics/test/Adaptors/annotated_args_mixed_reader.ll @@ -1,3 +1,29 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2020-2021 Intel Corporation +; +; Permission is hereby granted, free of charge, to any person obtaining a copy +; of this software and associated documentation files (the "Software"), +; to deal in the Software without restriction, including without limitation +; the rights to use, copy, modify, merge, publish, distribute, sublicense, +; and/or sell copies of the Software, and to permit persons to whom the +; Software is furnished to do so, subject to the following conditions: +; +; The above copyright notice and this permission notice (including the next +; paragraph) shall be included in all copies or substantial portions of the +; Software. +; +; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +; FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +; IN THE SOFTWARE. +; +; SPDX-License-Identifier: MIT +;============================ end_copyright_notice ============================= + ; XFAIL: llvm13 ; Test that reader can cope with mixed mode when some ; arguments use address convert and some do not. diff --git a/GenXIntrinsics/test/Adaptors/annotated_args_no_conv_reader.ll b/GenXIntrinsics/test/Adaptors/annotated_args_no_conv_reader.ll index 0408dc42..ac01a656 100644 --- a/GenXIntrinsics/test/Adaptors/annotated_args_no_conv_reader.ll +++ b/GenXIntrinsics/test/Adaptors/annotated_args_no_conv_reader.ll @@ -1,3 +1,29 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2020-2021 Intel Corporation +; +; Permission is hereby granted, free of charge, to any person obtaining a copy +; of this software and associated documentation files (the "Software"), +; to deal in the Software without restriction, including without limitation +; the rights to use, copy, modify, merge, publish, distribute, sublicense, +; and/or sell copies of the Software, and to permit persons to whom the +; Software is furnished to do so, subject to the following conditions: +; +; The above copyright notice and this permission notice (including the next +; paragraph) shall be included in all copies or substantial portions of the +; Software. +; +; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +; FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +; IN THE SOFTWARE. +; +; SPDX-License-Identifier: MIT +;============================ end_copyright_notice ============================= + ; XFAIL: llvm13 ; Test that reader correctly restores metadata and does ; not change other things if there is no address conversion diff --git a/GenXIntrinsics/test/Adaptors/annotated_args_no_conv_writer.ll b/GenXIntrinsics/test/Adaptors/annotated_args_no_conv_writer.ll index 377b628f..020d8cde 100644 --- a/GenXIntrinsics/test/Adaptors/annotated_args_no_conv_writer.ll +++ b/GenXIntrinsics/test/Adaptors/annotated_args_no_conv_writer.ll @@ -1,3 +1,29 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2020-2021 Intel Corporation +; +; Permission is hereby granted, free of charge, to any person obtaining a copy +; of this software and associated documentation files (the "Software"), +; to deal in the Software without restriction, including without limitation +; the rights to use, copy, modify, merge, publish, distribute, sublicense, +; and/or sell copies of the Software, and to permit persons to whom the +; Software is furnished to do so, subject to the following conditions: +; +; The above copyright notice and this permission notice (including the next +; paragraph) shall be included in all copies or substantial portions of the +; Software. +; +; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +; FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +; IN THE SOFTWARE. +; +; SPDX-License-Identifier: MIT +;============================ end_copyright_notice ============================= + ; Test that writer does not changes signature if correct ; types are already used. Just drop all annotations. diff --git a/GenXIntrinsics/test/Adaptors/annotated_args_reader.ll b/GenXIntrinsics/test/Adaptors/annotated_args_reader.ll index a1a4d987..90c1aa81 100644 --- a/GenXIntrinsics/test/Adaptors/annotated_args_reader.ll +++ b/GenXIntrinsics/test/Adaptors/annotated_args_reader.ll @@ -1,3 +1,29 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2020-2021 Intel Corporation +; +; Permission is hereby granted, free of charge, to any person obtaining a copy +; of this software and associated documentation files (the "Software"), +; to deal in the Software without restriction, including without limitation +; the rights to use, copy, modify, merge, publish, distribute, sublicense, +; and/or sell copies of the Software, and to permit persons to whom the +; Software is furnished to do so, subject to the following conditions: +; +; The above copyright notice and this permission notice (including the next +; paragraph) shall be included in all copies or substantial portions of the +; Software. +; +; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +; FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +; IN THE SOFTWARE. +; +; SPDX-License-Identifier: MIT +;============================ end_copyright_notice ============================= + ; XFAIL: llvm13 ; Test kernel argument translation from new style with opaque types ; that SPIRV translator can understand to old style with diff --git a/GenXIntrinsics/test/Adaptors/annotated_args_writer.ll b/GenXIntrinsics/test/Adaptors/annotated_args_writer.ll index c9f6fe9e..2b5852c4 100644 --- a/GenXIntrinsics/test/Adaptors/annotated_args_writer.ll +++ b/GenXIntrinsics/test/Adaptors/annotated_args_writer.ll @@ -1,3 +1,29 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2020-2021 Intel Corporation +; +; Permission is hereby granted, free of charge, to any person obtaining a copy +; of this software and associated documentation files (the "Software"), +; to deal in the Software without restriction, including without limitation +; the rights to use, copy, modify, merge, publish, distribute, sublicense, +; and/or sell copies of the Software, and to permit persons to whom the +; Software is furnished to do so, subject to the following conditions: +; +; The above copyright notice and this permission notice (including the next +; paragraph) shall be included in all copies or substantial portions of the +; Software. +; +; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +; FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +; IN THE SOFTWARE. +; +; SPDX-License-Identifier: MIT +;============================ end_copyright_notice ============================= + ; Test kernel arguments translation from old style with metadata to ; new style with opaque types that SPIRV translator can ; understand. Here annotations for OCL runtime are used. diff --git a/GenXIntrinsics/test/Adaptors/combined_args_reader.ll b/GenXIntrinsics/test/Adaptors/combined_args_reader.ll index 0940c0bf..775b5fab 100644 --- a/GenXIntrinsics/test/Adaptors/combined_args_reader.ll +++ b/GenXIntrinsics/test/Adaptors/combined_args_reader.ll @@ -1,3 +1,29 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2020-2021 Intel Corporation +; +; Permission is hereby granted, free of charge, to any person obtaining a copy +; of this software and associated documentation files (the "Software"), +; to deal in the Software without restriction, including without limitation +; the rights to use, copy, modify, merge, publish, distribute, sublicense, +; and/or sell copies of the Software, and to permit persons to whom the +; Software is furnished to do so, subject to the following conditions: +; +; The above copyright notice and this permission notice (including the next +; paragraph) shall be included in all copies or substantial portions of the +; Software. +; +; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +; FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +; IN THE SOFTWARE. +; +; SPDX-License-Identifier: MIT +;============================ end_copyright_notice ============================= + ; XFAIL: llvm13 ; Test combined reader translation: kernel has both native SPIRV types ; and impicit arguments. Implicit arguments would not show in normal diff --git a/GenXIntrinsics/test/Adaptors/combined_args_writer.ll b/GenXIntrinsics/test/Adaptors/combined_args_writer.ll index 0b7b9e60..06a6f05a 100644 --- a/GenXIntrinsics/test/Adaptors/combined_args_writer.ll +++ b/GenXIntrinsics/test/Adaptors/combined_args_writer.ll @@ -1,3 +1,29 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2020-2021 Intel Corporation +; +; Permission is hereby granted, free of charge, to any person obtaining a copy +; of this software and associated documentation files (the "Software"), +; to deal in the Software without restriction, including without limitation +; the rights to use, copy, modify, merge, publish, distribute, sublicense, +; and/or sell copies of the Software, and to permit persons to whom the +; Software is furnished to do so, subject to the following conditions: +; +; The above copyright notice and this permission notice (including the next +; paragraph) shall be included in all copies or substantial portions of the +; Software. +; +; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +; FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +; IN THE SOFTWARE. +; +; SPDX-License-Identifier: MIT +;============================ end_copyright_notice ============================= + ; Test combined writer translation: kernel has both annotated explicit ; arguments and impicit arguments. Implicit arguments would not show ; in normal flow, though they appear in old cmc. diff --git a/GenXIntrinsics/test/Adaptors/empty_kernel_writer.ll b/GenXIntrinsics/test/Adaptors/empty_kernel_writer.ll index 0c211f00..0960a00d 100644 --- a/GenXIntrinsics/test/Adaptors/empty_kernel_writer.ll +++ b/GenXIntrinsics/test/Adaptors/empty_kernel_writer.ll @@ -1,3 +1,29 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2020-2021 Intel Corporation +; +; Permission is hereby granted, free of charge, to any person obtaining a copy +; of this software and associated documentation files (the "Software"), +; to deal in the Software without restriction, including without limitation +; the rights to use, copy, modify, merge, publish, distribute, sublicense, +; and/or sell copies of the Software, and to permit persons to whom the +; Software is furnished to do so, subject to the following conditions: +; +; The above copyright notice and this permission notice (including the next +; paragraph) shall be included in all copies or substantial portions of the +; Software. +; +; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +; FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +; IN THE SOFTWARE. +; +; SPDX-License-Identifier: MIT +;============================ end_copyright_notice ============================= + ; Test empty kernel metadata translation: old -> new. ; RUN: opt -S -GenXSPIRVWriterAdaptor < %s | FileCheck %s diff --git a/GenXIntrinsics/test/Adaptors/no_vcfunction_reader.ll b/GenXIntrinsics/test/Adaptors/no_vcfunction_reader.ll index 48a77d38..a51cbd8a 100644 --- a/GenXIntrinsics/test/Adaptors/no_vcfunction_reader.ll +++ b/GenXIntrinsics/test/Adaptors/no_vcfunction_reader.ll @@ -1,3 +1,29 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2020-2021 Intel Corporation +; +; Permission is hereby granted, free of charge, to any person obtaining a copy +; of this software and associated documentation files (the "Software"), +; to deal in the Software without restriction, including without limitation +; the rights to use, copy, modify, merge, publish, distribute, sublicense, +; and/or sell copies of the Software, and to permit persons to whom the +; Software is furnished to do so, subject to the following conditions: +; +; The above copyright notice and this permission notice (including the next +; paragraph) shall be included in all copies or substantial portions of the +; Software. +; +; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +; FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +; IN THE SOFTWARE. +; +; SPDX-License-Identifier: MIT +;============================ end_copyright_notice ============================= + ; XFAIL: llvm13 ; Test that reader ignores signature rewriting for kernels ; that are not VCFunction. diff --git a/GenXIntrinsics/test/Adaptors/non_global_ptr_reader.ll b/GenXIntrinsics/test/Adaptors/non_global_ptr_reader.ll index 135c1a2f..8b25e179 100644 --- a/GenXIntrinsics/test/Adaptors/non_global_ptr_reader.ll +++ b/GenXIntrinsics/test/Adaptors/non_global_ptr_reader.ll @@ -1,3 +1,29 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2020-2021 Intel Corporation +; +; Permission is hereby granted, free of charge, to any person obtaining a copy +; of this software and associated documentation files (the "Software"), +; to deal in the Software without restriction, including without limitation +; the rights to use, copy, modify, merge, publish, distribute, sublicense, +; and/or sell copies of the Software, and to permit persons to whom the +; Software is furnished to do so, subject to the following conditions: +; +; The above copyright notice and this permission notice (including the next +; paragraph) shall be included in all copies or substantial portions of the +; Software. +; +; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +; FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +; IN THE SOFTWARE. +; +; SPDX-License-Identifier: MIT +;============================ end_copyright_notice ============================= + ; XFAIL: llvm13 ; Test that reader treats only global pointer as svmptr type ; and ignores other address spaces. diff --git a/GenXIntrinsics/test/Adaptors/old_decorated_args_reader.ll b/GenXIntrinsics/test/Adaptors/old_decorated_args_reader.ll index 9721c710..e997c9bc 100644 --- a/GenXIntrinsics/test/Adaptors/old_decorated_args_reader.ll +++ b/GenXIntrinsics/test/Adaptors/old_decorated_args_reader.ll @@ -1,3 +1,29 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2020-2021 Intel Corporation +; +; Permission is hereby granted, free of charge, to any person obtaining a copy +; of this software and associated documentation files (the "Software"), +; to deal in the Software without restriction, including without limitation +; the rights to use, copy, modify, merge, publish, distribute, sublicense, +; and/or sell copies of the Software, and to permit persons to whom the +; Software is furnished to do so, subject to the following conditions: +; +; The above copyright notice and this permission notice (including the next +; paragraph) shall be included in all copies or substantial portions of the +; Software. +; +; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +; FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +; IN THE SOFTWARE. +; +; SPDX-License-Identifier: MIT +;============================ end_copyright_notice ============================= + ; XFAIL: llvm13 ; Test reader translation of old-style decorated arguments. ; Annotations for these are directly translated from attributes to diff --git a/GenXIntrinsics/test/Adaptors/plain_args_reader.ll b/GenXIntrinsics/test/Adaptors/plain_args_reader.ll index 43137295..0978f803 100644 --- a/GenXIntrinsics/test/Adaptors/plain_args_reader.ll +++ b/GenXIntrinsics/test/Adaptors/plain_args_reader.ll @@ -1,3 +1,29 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2020-2021 Intel Corporation +; +; Permission is hereby granted, free of charge, to any person obtaining a copy +; of this software and associated documentation files (the "Software"), +; to deal in the Software without restriction, including without limitation +; the rights to use, copy, modify, merge, publish, distribute, sublicense, +; and/or sell copies of the Software, and to permit persons to whom the +; Software is furnished to do so, subject to the following conditions: +; +; The above copyright notice and this permission notice (including the next +; paragraph) shall be included in all copies or substantial portions of the +; Software. +; +; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +; FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +; IN THE SOFTWARE. +; +; SPDX-License-Identifier: MIT +;============================ end_copyright_notice ============================= + ; XFAIL: llvm13 ; Test kernel argument translation from new style with opaque types ; that SPIRV translator can understand to old style with diff --git a/GenXIntrinsics/test/Adaptors/plain_args_writer.ll b/GenXIntrinsics/test/Adaptors/plain_args_writer.ll index d322df80..803f3bb9 100644 --- a/GenXIntrinsics/test/Adaptors/plain_args_writer.ll +++ b/GenXIntrinsics/test/Adaptors/plain_args_writer.ll @@ -1,3 +1,29 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2020-2021 Intel Corporation +; +; Permission is hereby granted, free of charge, to any person obtaining a copy +; of this software and associated documentation files (the "Software"), +; to deal in the Software without restriction, including without limitation +; the rights to use, copy, modify, merge, publish, distribute, sublicense, +; and/or sell copies of the Software, and to permit persons to whom the +; Software is furnished to do so, subject to the following conditions: +; +; The above copyright notice and this permission notice (including the next +; paragraph) shall be included in all copies or substantial portions of the +; Software. +; +; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +; FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +; IN THE SOFTWARE. +; +; SPDX-License-Identifier: MIT +;============================ end_copyright_notice ============================= + ; Test kernel arguments translation from old style with metadata to ; new style with opaque types that SPIRV translator can ; understand. Arguments without annotations are used here (CMRT like). diff --git a/GenXIntrinsics/test/Adaptors/sev_signature_reader.ll b/GenXIntrinsics/test/Adaptors/sev_signature_reader.ll index c311d315..e1edf14b 100644 --- a/GenXIntrinsics/test/Adaptors/sev_signature_reader.ll +++ b/GenXIntrinsics/test/Adaptors/sev_signature_reader.ll @@ -1,3 +1,29 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2020-2021 Intel Corporation +; +; Permission is hereby granted, free of charge, to any person obtaining a copy +; of this software and associated documentation files (the "Software"), +; to deal in the Software without restriction, including without limitation +; the rights to use, copy, modify, merge, publish, distribute, sublicense, +; and/or sell copies of the Software, and to permit persons to whom the +; Software is furnished to do so, subject to the following conditions: +; +; The above copyright notice and this permission notice (including the next +; paragraph) shall be included in all copies or substantial portions of the +; Software. +; +; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +; FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +; IN THE SOFTWARE. +; +; SPDX-License-Identifier: MIT +;============================ end_copyright_notice ============================= + ; XFAIL: llvm13 ; Test simple signatures tranform diff --git a/GenXIntrinsics/test/Adaptors/sev_signature_writer.ll b/GenXIntrinsics/test/Adaptors/sev_signature_writer.ll index 64dfbd29..4ee2eddc 100644 --- a/GenXIntrinsics/test/Adaptors/sev_signature_writer.ll +++ b/GenXIntrinsics/test/Adaptors/sev_signature_writer.ll @@ -1,3 +1,29 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2020-2021 Intel Corporation +; +; Permission is hereby granted, free of charge, to any person obtaining a copy +; of this software and associated documentation files (the "Software"), +; to deal in the Software without restriction, including without limitation +; the rights to use, copy, modify, merge, publish, distribute, sublicense, +; and/or sell copies of the Software, and to permit persons to whom the +; Software is furnished to do so, subject to the following conditions: +; +; The above copyright notice and this permission notice (including the next +; paragraph) shall be included in all copies or substantial portions of the +; Software. +; +; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +; FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +; IN THE SOFTWARE. +; +; SPDX-License-Identifier: MIT +;============================ end_copyright_notice ============================= + ; Test simple signatures tranform ; RUN: opt -S -GenXSPIRVWriterAdaptor < %s | FileCheck %s diff --git a/GenXIntrinsics/test/Adaptors/surface_access_reader.ll b/GenXIntrinsics/test/Adaptors/surface_access_reader.ll index f34792a4..f703922e 100644 --- a/GenXIntrinsics/test/Adaptors/surface_access_reader.ll +++ b/GenXIntrinsics/test/Adaptors/surface_access_reader.ll @@ -1,3 +1,29 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2020-2021 Intel Corporation +; +; Permission is hereby granted, free of charge, to any person obtaining a copy +; of this software and associated documentation files (the "Software"), +; to deal in the Software without restriction, including without limitation +; the rights to use, copy, modify, merge, publish, distribute, sublicense, +; and/or sell copies of the Software, and to permit persons to whom the +; Software is furnished to do so, subject to the following conditions: +; +; The above copyright notice and this permission notice (including the next +; paragraph) shall be included in all copies or substantial portions of the +; Software. +; +; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +; FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +; IN THE SOFTWARE. +; +; SPDX-License-Identifier: MIT +;============================ end_copyright_notice ============================= + ; XFAIL: llvm13 ; Test kernel surface argument translation from new style with opaque ; types that SPIRV translator can understand to old style with diff --git a/GenXIntrinsics/test/Adaptors/surface_access_writer.ll b/GenXIntrinsics/test/Adaptors/surface_access_writer.ll index 5f2d4065..e431201a 100644 --- a/GenXIntrinsics/test/Adaptors/surface_access_writer.ll +++ b/GenXIntrinsics/test/Adaptors/surface_access_writer.ll @@ -1,3 +1,29 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2020-2021 Intel Corporation +; +; Permission is hereby granted, free of charge, to any person obtaining a copy +; of this software and associated documentation files (the "Software"), +; to deal in the Software without restriction, including without limitation +; the rights to use, copy, modify, merge, publish, distribute, sublicense, +; and/or sell copies of the Software, and to permit persons to whom the +; Software is furnished to do so, subject to the following conditions: +; +; The above copyright notice and this permission notice (including the next +; paragraph) shall be included in all copies or substantial portions of the +; Software. +; +; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +; FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +; IN THE SOFTWARE. +; +; SPDX-License-Identifier: MIT +;============================ end_copyright_notice ============================= + ; Test kernel surface argument translation from old style with ; metadata to new style with opaque types that SPIRV translator can ; understand. This test checks access qualifiers translation. diff --git a/GenXIntrinsics/test/Adaptors/unknown_arg_reader.ll b/GenXIntrinsics/test/Adaptors/unknown_arg_reader.ll index 71e2a800..f74727c7 100644 --- a/GenXIntrinsics/test/Adaptors/unknown_arg_reader.ll +++ b/GenXIntrinsics/test/Adaptors/unknown_arg_reader.ll @@ -1,3 +1,29 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2020-2021 Intel Corporation +; +; Permission is hereby granted, free of charge, to any person obtaining a copy +; of this software and associated documentation files (the "Software"), +; to deal in the Software without restriction, including without limitation +; the rights to use, copy, modify, merge, publish, distribute, sublicense, +; and/or sell copies of the Software, and to permit persons to whom the +; Software is furnished to do so, subject to the following conditions: +; +; The above copyright notice and this permission notice (including the next +; paragraph) shall be included in all copies or substantial portions of the +; Software. +; +; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +; FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +; IN THE SOFTWARE. +; +; SPDX-License-Identifier: MIT +;============================ end_copyright_notice ============================= + ; XFAIL: llvm13 ; Test reader translation of implicit argument with argument kind ; decoration. diff --git a/GenXIntrinsics/test/Adaptors/unknown_arg_writer.ll b/GenXIntrinsics/test/Adaptors/unknown_arg_writer.ll index 8a196767..0f3bf1ba 100644 --- a/GenXIntrinsics/test/Adaptors/unknown_arg_writer.ll +++ b/GenXIntrinsics/test/Adaptors/unknown_arg_writer.ll @@ -1,3 +1,29 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2020-2021 Intel Corporation +; +; Permission is hereby granted, free of charge, to any person obtaining a copy +; of this software and associated documentation files (the "Software"), +; to deal in the Software without restriction, including without limitation +; the rights to use, copy, modify, merge, publish, distribute, sublicense, +; and/or sell copies of the Software, and to permit persons to whom the +; Software is furnished to do so, subject to the following conditions: +; +; The above copyright notice and this permission notice (including the next +; paragraph) shall be included in all copies or substantial portions of the +; Software. +; +; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +; FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +; IN THE SOFTWARE. +; +; SPDX-License-Identifier: MIT +;============================ end_copyright_notice ============================= + ; Test writer translation of implicit argument. Implicit arguments ; should not appear in current form after transition from cmc. diff --git a/GenXIntrinsics/test/CMakeLists.txt b/GenXIntrinsics/test/CMakeLists.txt index c6f8bdb2..d8ef4a4c 100644 --- a/GenXIntrinsics/test/CMakeLists.txt +++ b/GenXIntrinsics/test/CMakeLists.txt @@ -1,3 +1,29 @@ +#=========================== begin_copyright_notice ============================ +# +# Copyright (C) 2020-2021 Intel Corporation +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice (including the next +# paragraph) shall be included in all copies or substantial portions of the +# Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +# IN THE SOFTWARE. +# +# SPDX-License-Identifier: MIT +#============================ end_copyright_notice ============================= + if(BUILD_EXTERNAL) if(NOT EXISTS ${LLVM_EXTERNAL_LIT}) message(FATAL_ERROR "External build requires LLVM_EXTERNAL_LIT to be defined to lit executable") diff --git a/GenXIntrinsics/test/Plugin/CMakeLists.txt b/GenXIntrinsics/test/Plugin/CMakeLists.txt index e0f15e9b..78136b63 100644 --- a/GenXIntrinsics/test/Plugin/CMakeLists.txt +++ b/GenXIntrinsics/test/Plugin/CMakeLists.txt @@ -1,3 +1,29 @@ +#=========================== begin_copyright_notice ============================ +# +# Copyright (C) 2020-2021 Intel Corporation +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice (including the next +# paragraph) shall be included in all copies or substantial portions of the +# Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +# IN THE SOFTWARE. +# +# SPDX-License-Identifier: MIT +#============================ end_copyright_notice ============================= + set(PLUGIN_SOURCES Plugin.cpp ) diff --git a/GenXIntrinsics/test/Plugin/Plugin.cpp b/GenXIntrinsics/test/Plugin/Plugin.cpp index 38dd10f0..c2e69f06 100644 --- a/GenXIntrinsics/test/Plugin/Plugin.cpp +++ b/GenXIntrinsics/test/Plugin/Plugin.cpp @@ -1,27 +1,28 @@ -/*===================== begin_copyright_notice ================================== - - Copyright (c) 2021, Intel Corporation - - - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - OTHER DEALINGS IN THE SOFTWARE. -======================= end_copyright_notice ==================================*/ - +/*========================== begin_copyright_notice ============================ + +Copyright (C) 2020-2021 Intel Corporation + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +the rights to use, copy, modify, merge, publish, distribute, sublicense, +and/or sell copies of the Software, and to permit persons to whom the +Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +IN THE SOFTWARE. + +SPDX-License-Identifier: MIT +============================= end_copyright_notice ===========================*/ #include "llvm/GenXIntrinsics/GenXSimdCFLowering.h" #include "llvm/GenXIntrinsics/GenXSPIRVReaderAdaptor.h" diff --git a/GenXIntrinsics/test/SimdCFLowering/bitcast_between_wrrs.ll b/GenXIntrinsics/test/SimdCFLowering/bitcast_between_wrrs.ll index 862e3589..ba47f077 100644 --- a/GenXIntrinsics/test/SimdCFLowering/bitcast_between_wrrs.ll +++ b/GenXIntrinsics/test/SimdCFLowering/bitcast_between_wrrs.ll @@ -1,3 +1,29 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2020-2021 Intel Corporation +; +; Permission is hereby granted, free of charge, to any person obtaining a copy +; of this software and associated documentation files (the "Software"), +; to deal in the Software without restriction, including without limitation +; the rights to use, copy, modify, merge, publish, distribute, sublicense, +; and/or sell copies of the Software, and to permit persons to whom the +; Software is furnished to do so, subject to the following conditions: +; +; The above copyright notice and this permission notice (including the next +; paragraph) shall be included in all copies or substantial portions of the +; Software. +; +; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +; FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +; IN THE SOFTWARE. +; +; SPDX-License-Identifier: MIT +;============================ end_copyright_notice ============================= + ; XFAIL: llvm13 ; RUN: opt -S -cmsimdcflowering < %s | FileCheck %s diff --git a/GenXIntrinsics/test/SimdCFLowering/predicate_masked_gather.ll b/GenXIntrinsics/test/SimdCFLowering/predicate_masked_gather.ll index a192f52a..634279ee 100644 --- a/GenXIntrinsics/test/SimdCFLowering/predicate_masked_gather.ll +++ b/GenXIntrinsics/test/SimdCFLowering/predicate_masked_gather.ll @@ -1,3 +1,29 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2020-2021 Intel Corporation +; +; Permission is hereby granted, free of charge, to any person obtaining a copy +; of this software and associated documentation files (the "Software"), +; to deal in the Software without restriction, including without limitation +; the rights to use, copy, modify, merge, publish, distribute, sublicense, +; and/or sell copies of the Software, and to permit persons to whom the +; Software is furnished to do so, subject to the following conditions: +; +; The above copyright notice and this permission notice (including the next +; paragraph) shall be included in all copies or substantial portions of the +; Software. +; +; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +; FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +; IN THE SOFTWARE. +; +; SPDX-License-Identifier: MIT +;============================ end_copyright_notice ============================= + ; XFAIL: llvm13 ; RUN: opt -S -cmsimdcflowering < %s | FileCheck %s diff --git a/GenXIntrinsics/test/SimdCFLowering/replicate_mask.ll b/GenXIntrinsics/test/SimdCFLowering/replicate_mask.ll index f976d0cd..98ebac41 100644 --- a/GenXIntrinsics/test/SimdCFLowering/replicate_mask.ll +++ b/GenXIntrinsics/test/SimdCFLowering/replicate_mask.ll @@ -1,3 +1,29 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2020-2021 Intel Corporation +; +; Permission is hereby granted, free of charge, to any person obtaining a copy +; of this software and associated documentation files (the "Software"), +; to deal in the Software without restriction, including without limitation +; the rights to use, copy, modify, merge, publish, distribute, sublicense, +; and/or sell copies of the Software, and to permit persons to whom the +; Software is furnished to do so, subject to the following conditions: +; +; The above copyright notice and this permission notice (including the next +; paragraph) shall be included in all copies or substantial portions of the +; Software. +; +; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +; FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +; IN THE SOFTWARE. +; +; SPDX-License-Identifier: MIT +;============================ end_copyright_notice ============================= + ; XFAIL: llvm13 ; RUN: opt -S -cmsimdcflowering < %s | FileCheck %s diff --git a/GenXIntrinsics/test/SimdCFLowering/replicate_mask_masked_gather4.ll b/GenXIntrinsics/test/SimdCFLowering/replicate_mask_masked_gather4.ll index a4f47591..0266744c 100644 --- a/GenXIntrinsics/test/SimdCFLowering/replicate_mask_masked_gather4.ll +++ b/GenXIntrinsics/test/SimdCFLowering/replicate_mask_masked_gather4.ll @@ -1,3 +1,29 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2021 Intel Corporation +; +; Permission is hereby granted, free of charge, to any person obtaining a copy +; of this software and associated documentation files (the "Software"), +; to deal in the Software without restriction, including without limitation +; the rights to use, copy, modify, merge, publish, distribute, sublicense, +; and/or sell copies of the Software, and to permit persons to whom the +; Software is furnished to do so, subject to the following conditions: +; +; The above copyright notice and this permission notice (including the next +; paragraph) shall be included in all copies or substantial portions of the +; Software. +; +; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +; FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +; IN THE SOFTWARE. +; +; SPDX-License-Identifier: MIT +;============================ end_copyright_notice ============================= + ; XFAIL: llvm13 ; RUN: opt -S -cmsimdcflowering < %s | FileCheck %s diff --git a/GenXIntrinsics/test/SimdCFLowering/update_mask_masked_gather4.ll b/GenXIntrinsics/test/SimdCFLowering/update_mask_masked_gather4.ll index 3a19baf4..14440284 100644 --- a/GenXIntrinsics/test/SimdCFLowering/update_mask_masked_gather4.ll +++ b/GenXIntrinsics/test/SimdCFLowering/update_mask_masked_gather4.ll @@ -1,3 +1,29 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2020-2021 Intel Corporation +; +; Permission is hereby granted, free of charge, to any person obtaining a copy +; of this software and associated documentation files (the "Software"), +; to deal in the Software without restriction, including without limitation +; the rights to use, copy, modify, merge, publish, distribute, sublicense, +; and/or sell copies of the Software, and to permit persons to whom the +; Software is furnished to do so, subject to the following conditions: +; +; The above copyright notice and this permission notice (including the next +; paragraph) shall be included in all copies or substantial portions of the +; Software. +; +; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +; FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +; IN THE SOFTWARE. +; +; SPDX-License-Identifier: MIT +;============================ end_copyright_notice ============================= + ; XFAIL: llvm13 ; RUN: opt -S -cmsimdcflowering < %s | FileCheck %s diff --git a/GenXIntrinsics/test/lit.cfg.py b/GenXIntrinsics/test/lit.cfg.py index 3a26cfa6..092a6aa2 100644 --- a/GenXIntrinsics/test/lit.cfg.py +++ b/GenXIntrinsics/test/lit.cfg.py @@ -1,3 +1,29 @@ +#=========================== begin_copyright_notice ============================ +# +# Copyright (C) 2020-2021 Intel Corporation +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice (including the next +# paragraph) shall be included in all copies or substantial portions of the +# Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +# IN THE SOFTWARE. +# +# SPDX-License-Identifier: MIT +#============================ end_copyright_notice ============================= + # -*- Python -*- import lit.formats diff --git a/GenXIntrinsics/test/lit.site.cfg.py.in b/GenXIntrinsics/test/lit.site.cfg.py.in index 35b4aa42..1eb2237b 100644 --- a/GenXIntrinsics/test/lit.site.cfg.py.in +++ b/GenXIntrinsics/test/lit.site.cfg.py.in @@ -1,3 +1,29 @@ +#=========================== begin_copyright_notice ============================ +# +# Copyright (C) 2020-2021 Intel Corporation +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice (including the next +# paragraph) shall be included in all copies or substantial portions of the +# Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +# IN THE SOFTWARE. +# +# SPDX-License-Identifier: MIT +#============================ end_copyright_notice ============================= + @LIT_SITE_CFG_IN_HEADER@ import sys diff --git a/GenXIntrinsics/unittests/CMakeLists.txt b/GenXIntrinsics/unittests/CMakeLists.txt index b011d537..c8751204 100644 --- a/GenXIntrinsics/unittests/CMakeLists.txt +++ b/GenXIntrinsics/unittests/CMakeLists.txt @@ -1,3 +1,29 @@ +#=========================== begin_copyright_notice ============================ +# +# Copyright (C) 2019-2021 Intel Corporation +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice (including the next +# paragraph) shall be included in all copies or substantial portions of the +# Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +# IN THE SOFTWARE. +# +# SPDX-License-Identifier: MIT +#============================ end_copyright_notice ============================= + add_custom_target(GenXIntrinsicsUnitTests) set_target_properties(GenXIntrinsicsUnitTests PROPERTIES FOLDER "GenXIntrinsicsTests") diff --git a/GenXIntrinsics/unittests/GenXIntrinsics/CMakeLists.txt b/GenXIntrinsics/unittests/GenXIntrinsics/CMakeLists.txt index e44c3b4e..5afdde7d 100644 --- a/GenXIntrinsics/unittests/GenXIntrinsics/CMakeLists.txt +++ b/GenXIntrinsics/unittests/GenXIntrinsics/CMakeLists.txt @@ -1,3 +1,29 @@ +#=========================== begin_copyright_notice ============================ +# +# Copyright (C) 2019-2021 Intel Corporation +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice (including the next +# paragraph) shall be included in all copies or substantial portions of the +# Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +# IN THE SOFTWARE. +# +# SPDX-License-Identifier: MIT +#============================ end_copyright_notice ============================= + set(LLVM_LINK_COMPONENTS Core Support diff --git a/GenXIntrinsics/unittests/GenXIntrinsics/GenXIntrinsicsTest.cpp b/GenXIntrinsics/unittests/GenXIntrinsics/GenXIntrinsicsTest.cpp index 60a899e5..78309dd4 100644 --- a/GenXIntrinsics/unittests/GenXIntrinsics/GenXIntrinsicsTest.cpp +++ b/GenXIntrinsics/unittests/GenXIntrinsics/GenXIntrinsicsTest.cpp @@ -1,27 +1,28 @@ -/*===================== begin_copyright_notice ================================== - - Copyright (c) 2021, Intel Corporation - - - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - OTHER DEALINGS IN THE SOFTWARE. -======================= end_copyright_notice ==================================*/ - +/*========================== begin_copyright_notice ============================ + +Copyright (C) 2019-2021 Intel Corporation + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +the rights to use, copy, modify, merge, publish, distribute, sublicense, +and/or sell copies of the Software, and to permit persons to whom the +Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +IN THE SOFTWARE. + +SPDX-License-Identifier: MIT +============================= end_copyright_notice ===========================*/ #include "llvm/ADT/StringRef.h" #include "llvm/GenXIntrinsics/GenXIntrinsics.h" diff --git a/License.md b/License.md deleted file mode 100644 index 4e66ab4c..00000000 --- a/License.md +++ /dev/null @@ -1,21 +0,0 @@ -MIT License - -Copyright (c) 2020 Intel Corporation - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in all -copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -SOFTWARE. diff --git a/Readme.md b/Readme.md index 9289b331..3fc0b9f1 100644 --- a/Readme.md +++ b/Readme.md @@ -1,3 +1,29 @@ + + # VC Intrinsics ## Introduction From 19e6ddafc545bc96ceaacbf7c81cacbff59a39b6 Mon Sep 17 00:00:00 2001 From: Aleksander Us Date: Tue, 15 Jun 2021 15:18:10 +0000 Subject: [PATCH 13/81] Wrap getName function Use getNameNoUnnamedTypes for LLVM tot to avoid buildbreak. --- .../include/llvmVCWrapper/IR/Intrinsics.h | 47 +++++++++++++++++++ .../lib/GenXIntrinsics/GenXIntrinsics.cpp | 3 +- 2 files changed, 49 insertions(+), 1 deletion(-) create mode 100644 GenXIntrinsics/include/llvmVCWrapper/IR/Intrinsics.h diff --git a/GenXIntrinsics/include/llvmVCWrapper/IR/Intrinsics.h b/GenXIntrinsics/include/llvmVCWrapper/IR/Intrinsics.h new file mode 100644 index 00000000..57db0663 --- /dev/null +++ b/GenXIntrinsics/include/llvmVCWrapper/IR/Intrinsics.h @@ -0,0 +1,47 @@ +/*========================== begin_copyright_notice ============================ + +Copyright (C) 2021-2021 Intel Corporation + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +the rights to use, copy, modify, merge, publish, distribute, sublicense, +and/or sell copies of the Software, and to permit persons to whom the +Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +IN THE SOFTWARE. + +SPDX-License-Identifier: MIT +============================= end_copyright_notice ===========================*/ + +#ifndef VCINTR_IR_INTRINSICS_H +#define VCINTR_IR_INTRINSICS_H + +#include + +namespace VCINTR { + +namespace Intrinsic { +inline std::string getName(llvm::Intrinsic::ID Id, + llvm::ArrayRef Tys) { +#if VC_INTR_LLVM_VERSION_MAJOR >= 13 + return llvm::Intrinsic::getNameNoUnnamedTypes(Id, Tys); +#else + return llvm::Intrinsic::getName(Id, Tys); +#endif +} + +} // namespace Intrinsic +} // namespace VCINTR + +#endif // VCINTR_IR_INTRINSICS_H diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp index 5a82441d..1108111a 100755 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp @@ -50,6 +50,7 @@ See LICENSE.TXT for details. #include #include "llvmVCWrapper/IR/DerivedTypes.h" +#include "llvmVCWrapper/IR/Intrinsics.h" #include @@ -681,6 +682,6 @@ std::string GenXIntrinsic::getAnyName(unsigned id, ArrayRef Tys) { } else if (isGenXIntrinsic(id)) return getGenXName((GenXIntrinsic::ID)id, Tys); else - return Intrinsic::getName((Intrinsic::ID)id, Tys); + return VCINTR::Intrinsic::getName((Intrinsic::ID)id, Tys); } From 3303f8ded01736d9b85512a8c6cbf7fe34c16cc2 Mon Sep 17 00:00:00 2001 From: y Date: Mon, 7 Jun 2021 13:19:08 +0000 Subject: [PATCH 14/81] made Intrinsics parameters named --- .../GenXIntrinsics/Intrinsic_definitions.py | 664 +++++++++--------- .../include/llvm/GenXIntrinsics/Intrinsics.py | 41 +- 2 files changed, 354 insertions(+), 351 deletions(-) diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py index a3afe361..f0bc441d 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py @@ -43,7 +43,7 @@ #IntrinsicsProperties = ["None", "NoMem", "ReadArgMem", "ReadMem", "ReadWriteArgMem", "NoReturn", "NoDuplicate", "Convergent"] #IntrinsicsProperties may be specified as a comma separated list(e.g., "Convergent,NoMem") # -# EX. "blah": [{return_type}, [arg1_type, arg2_type.....], Property] +# EX. "blah": {"result" : {return_type}, "arguments" : [arg1_type, arg2_type.....], "attributes" : Property } # # The "any" type can be followed by a default type if a type is not explicitly specified : Ex. "any:int" # @@ -58,8 +58,8 @@ ##-------------------------------------------------------------------- ## Start and end markers of the genx intrinsic enum values. This relies on ## tablegen outputting the intrinsics in sorted by name order. - "aaaabegin" : ["anyvector",[],"None"], - "zzzzend" : ["anyvector",[],"None"], + "aaaabegin" : { "result" : "anyvector", "arguments" : [], "attributes" : "None"}, + "zzzzend" : { "result" : "anyvector", "arguments" : [], "attributes" : "None"}, ### ``llvm.genx.alloca.`` : CMC internal, no VISA ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -70,7 +70,7 @@ ### ### * Return value: offset in stack surface ### - "alloca" : ["anyint",["any"],"None"], + "alloca" : { "result" : "anyint", "arguments" : ["any"], "attributes" : "None"}, ### ``llvm.genx.faddr.`` : take an address of the function provided ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -82,7 +82,7 @@ ### ### * Return value: i64 address ready to be consumed by an indirect call ### - "faddr" : ["long", ["any"], "NoMem"], + "faddr" : { "result" : "long", "arguments" : ["any"], "attributes" : "NoMem"}, ## -------------------------------- ### Region/element access intrinsics @@ -128,8 +128,8 @@ ### cross a multiple of parent width boundary. This is used by the backend ### to determine whether the region can be collapsed into another region. ### - "rdregioni" : ["anyint",["anyvector","int","int","int","anyint","int"],"NoMem"], - "rdregionf" : ["anyfloat",["anyvector","int","int","int","anyint","int"],"NoMem"], + "rdregioni" : { "result" : "anyint", "arguments" : ["anyvector","int","int","int","anyint","int"], "attributes" : "NoMem"}, + "rdregionf" : { "result" : "anyfloat", "arguments" : ["anyvector","int","int","int","anyint","int"], "attributes" : "NoMem"}, ### ``llvm.genx.wrregion*`` : write a region, direct or single-indirect ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -185,8 +185,8 @@ ### cross a multiple of parent width boundary. This is used by the backend ### to determine whether the region can be collapsed into another region. ### - "wrregioni" : ["anyvector",[0,"anyint","int","int","int","anyint","int","anyint"],"NoMem"], - "wrregionf" : ["anyvector",[0,"anyfloat","int","int","int","anyint","int","anyint"],"NoMem"], + "wrregioni" : { "result" : "anyvector", "arguments" : [0,"anyint","int","int","int","anyint","int","anyint"], "attributes" : "NoMem"}, + "wrregionf" : { "result" : "anyvector", "arguments" : [0,"anyfloat","int","int","int","anyint","int","anyint"], "attributes" : "NoMem"}, ### ``llvm.genx.vstore..`` : store a vector value into memory ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -199,7 +199,7 @@ ### * arg0: the vector to read from ### * arg1: the memory to be accessed ### - "vstore" : ["void",["anyvector","anyptr"],"None"], + "vstore" : { "result" : "void", "arguments" : ["anyvector","anyptr"], "attributes" : "None"}, ### ``llvm.genx.vload..`` : load a vector value from memory ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -212,7 +212,7 @@ ### * arg0: the memory to be accessed (overloaded) ### * Return value: the vector value read ### - "vload" : ["anyvector",["anyptr"],"None"], + "vload" : { "result" : "anyvector", "arguments" : ["anyptr"], "attributes" : "None"}, ## ------------------------------ ### ALU type conversion intrinsics @@ -226,7 +226,7 @@ ### * Return value: converted value, any scalar or vector integer type ### (treated as signed) with same vector width as arg0 ### - "fptosi_sat" : ["anyint",["anyfloat"],"NoMem"], + "fptosi_sat" : { "result" : "anyint", "arguments" : ["anyfloat"], "attributes" : "NoMem"}, ### ``llvm.genx.fptoui.sat..`` : convert floating point to unsigned integer with saturate ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -236,7 +236,7 @@ ### * Return value: converted value, any scalar or vector integer type ### (treated as unsigned) with same vector width as arg0 ### - "fptoui_sat" : ["anyint",["anyfloat"],"NoMem"], + "fptoui_sat" : { "result" : "anyint", "arguments" : ["anyfloat"], "attributes" : "NoMem"}, ### ``llvm.genx.sat..`` : floating point saturate ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -254,7 +254,7 @@ ### Instead, any integer operation that supports saturation needs an ### intrinsic for the saturating variant. ### - "sat" : ["anyfloat",[0],"NoMem"], + "sat" : { "result" : "anyfloat", "arguments" : [0], "attributes" : "NoMem"}, ### ``llvm.genx.*trunc.sat..`` : integer truncation with saturation ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -268,10 +268,10 @@ ### * Return value: truncated value, any scalar or vector integer type ### with same vector width as arg0 ### - "sstrunc_sat" : ["anyint",["anyint"],"NoMem"], - "sutrunc_sat" : ["anyint",["anyint"],"NoMem"], - "ustrunc_sat" : ["anyint",["anyint"],"NoMem"], - "uutrunc_sat" : ["anyint",["anyint"],"NoMem"], + "sstrunc_sat" : { "result" : "anyint", "arguments" : ["anyint"], "attributes" : "NoMem"}, + "sutrunc_sat" : { "result" : "anyint", "arguments" : ["anyint"], "attributes" : "NoMem"}, + "ustrunc_sat" : { "result" : "anyint", "arguments" : ["anyint"], "attributes" : "NoMem"}, + "uutrunc_sat" : { "result" : "anyint", "arguments" : ["anyint"], "attributes" : "NoMem"}, ## ------------------- ### Modifier intrinsics @@ -289,8 +289,8 @@ ### ### * Return value: result, same type ### - "absf" : ["anyfloat",[0],"NoMem"], - "absi" : ["anyint",[0],"NoMem"], + "absf" : { "result" : "anyfloat", "arguments" : [0], "attributes" : "NoMem"}, + "absi" : { "result" : "anyint", "arguments" : [0], "attributes" : "NoMem"}, ## ---------------------------- ### Boolean reduction intrinsics @@ -303,7 +303,7 @@ ### ### * Return value: i1 result ### - "all" : ["bool",["anyint"],"NoMem"], + "all" : { "result" : "bool", "arguments" : ["anyint"], "attributes" : "NoMem"}, ### ``llvm.genx.any.`` : true if any input element is true ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -312,7 +312,7 @@ ### ### * Return value: i1 result ### - "any" : ["bool",["anyint"],"NoMem"], + "any" : { "result" : "bool", "arguments" : ["anyint"], "attributes" : "NoMem"}, ## ---------------------------- ### SIMD control flow intrinsics @@ -492,7 +492,7 @@ ### Note that SimdCond has the same sense as in the Gen goto instruction, but ### the opposite sense to that in a vISA forward goto instruction. ### - "simdcf_goto" : [["anyvector","anyvector","bool"],[0,1,1],"NoMem"], + "simdcf_goto" : { "result" : ["anyvector","anyvector","bool"], "arguments" : [0,1,1], "attributes" : "NoMem"}, ### ``llvm.genx.simdcf.join..`` : join instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -535,14 +535,14 @@ ### still disabled, then BranchCond is true and the conditional branch in which it ### is used branches to the next join point in sequence. ### - "simdcf_join" : [["anyvector","bool"],[0,"anyvector"],"None"], + "simdcf_join" : { "result" : ["anyvector","bool"], "arguments" : [0,"anyvector"], "attributes" : "None"}, ### ``llvm.genx.simdcf.savemask.`` : ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ### ### * arg0: OldEM (old execution mask): v32i1 (overloaded) ### * ret: temp i32 for saving the oldEM - "simdcf_savemask" : ["int",["anyvector"],"WriteMem,SideEffects"], + "simdcf_savemask" : { "result" : "int", "arguments" : ["anyvector"], "attributes" : "WriteMem,SideEffects"}, ### ``llvm.genx.simdcf.unmask.`` : ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -550,7 +550,7 @@ ### * arg0: temp i32 from savemask ### * arg1: i32 constant, should be all-one ### * ret: NewEM (updated execution mask, all-one): v32i1 - "simdcf_unmask" : ["anyvector",["int","int"],"WriteMem,SideEffects"], + "simdcf_unmask" : { "result" : "anyvector", "arguments" : ["int","int"], "attributes" : "WriteMem,SideEffects"}, ### ``llvm.genx.simdcf.remask.`` : ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -560,7 +560,7 @@ ### ### Return value: NewEM (updated execution mask): v32i1 ### - "simdcf_remask" : ["anyvector",[0,"int"],"WriteMem,SideEffects"], + "simdcf_remask" : { "result" : "anyvector", "arguments" : [0,"int"], "attributes" : "WriteMem,SideEffects"}, ### ``llvm.genx.simdcf.get.em`` : ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -578,7 +578,7 @@ ### EM is different in different locations even when the ### dominance of DF is not corrupted. ### - "simdcf_get_em" : ["anyvector",[0],"WriteMem,SideEffects"], + "simdcf_get_em" : { "result" : "anyvector", "arguments" : [0], "attributes" : "WriteMem,SideEffects"}, ### -------------- ### ALU intrinsics @@ -607,10 +607,10 @@ ### For an fp add, use the LLVM IR FAdd instruction, followed by ### llvm.genx.sat if saturation is required. ### - "ssadd_sat" : ["anyint",["anyint",1],"NoMem"], - "suadd_sat" : ["anyint",["anyint",1],"NoMem"], - "usadd_sat" : ["anyint",["anyint",1],"NoMem"], - "uuadd_sat" : ["anyint",["anyint",1],"NoMem"], + "ssadd_sat" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, + "suadd_sat" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, + "usadd_sat" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, + "uuadd_sat" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, ### asr ### ^^^ @@ -632,10 +632,10 @@ ### * Return value: result, any scalar/vector integer type (not i64) ### with same vector width ### - "ssavg" : ["anyint",["anyint",1],"NoMem"], - "suavg" : ["anyint",["anyint",1],"NoMem"], - "usavg" : ["anyint",["anyint",1],"NoMem"], - "uuavg" : ["anyint",["anyint",1],"NoMem"], + "ssavg" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, + "suavg" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, + "usavg" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, + "uuavg" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, ### ``llvm.genx.*avg.sat..`` : integer averaging with saturation ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -650,10 +650,10 @@ ### * Return value: result, any scalar/vector integer type (not i64) ### with same vector width ### - "ssavg_sat" : ["anyint",["anyint",1],"NoMem"], - "suavg_sat" : ["anyint",["anyint",1],"NoMem"], - "usavg_sat" : ["anyint",["anyint",1],"NoMem"], - "uuavg_sat" : ["anyint",["anyint",1],"NoMem"], + "ssavg_sat" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, + "suavg_sat" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, + "usavg_sat" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, + "uuavg_sat" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, ### ``llvm.genx.*bfe.`` : bitfield extract ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -666,8 +666,8 @@ ### ### * Return value: result, same type as arg0 ### - "sbfe" : ["anyint",[0,0,0],"NoMem"], - "ubfe" : ["anyint",[0,0,0],"NoMem"], + "sbfe" : { "result" : "anyint", "arguments" : [0,0,0], "attributes" : "NoMem"}, + "ubfe" : { "result" : "anyint", "arguments" : [0,0,0], "attributes" : "NoMem"}, ### ``llvm.genx.bfi.`` : bitfield insert ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -679,7 +679,7 @@ ### ### * Return value: result, same type as arg0 ### - "bfi" : ["anyint",[0,0,0,0],"NoMem"], + "bfi" : { "result" : "anyint", "arguments" : [0,0,0,0], "attributes" : "NoMem"}, ### ``llvm.genx.bfrev.`` : reverse bits ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -688,7 +688,7 @@ ### ### * Return value: result, same type as arg0 ### - "bfrev" : ["anyint",[0],"NoMem"], + "bfrev" : { "result" : "anyint", "arguments" : [0], "attributes" : "NoMem"}, ### ``llvm.genx.cbit..`` : count set bits ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -697,7 +697,7 @@ ### ### * Return value: result, int32 of same width as arg0 ### - "cbit" : ["anyint",["anyint"],"NoMem"], + "cbit" : { "result" : "anyint", "arguments" : ["anyint"], "attributes" : "NoMem"}, ### cmp ### ^^^ @@ -712,7 +712,7 @@ ### ### * Return value: result, same type ### - "cos" : ["anyfloat",[0],"NoMem"], + "cos" : { "result" : "anyfloat", "arguments" : [0], "attributes" : "NoMem"}, ### div ### ^^^ @@ -728,7 +728,7 @@ ### ### * Return value: result, same type ### - "ieee_div" : ["anyfloat",[0,0],"NoMem"], + "ieee_div" : { "result" : "anyfloat", "arguments" : [0,0], "attributes" : "NoMem"}, ### ``llvm.genx.dp2.`` : dp2 instruction (dot product on groups of 4 elements) ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -738,7 +738,7 @@ ### ### * Return value: result, same type ### - "dp2" : ["anyfloat",[0,0],"NoMem"], + "dp2" : { "result" : "anyfloat", "arguments" : [0,0], "attributes" : "NoMem"}, ### ``llvm.genx.dp3.`` : dp3 instruction (dot product on groups of 3 elements) ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -748,7 +748,7 @@ ### ### * Return value: result, same type ### - "dp3" : ["anyfloat",[0,0],"NoMem"], + "dp3" : { "result" : "anyfloat", "arguments" : [0,0], "attributes" : "NoMem"}, ### ``llvm.genx.dp4.`` : dp4 instruction (dot product on groups of 4 elements) ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -758,7 +758,7 @@ ### ### * Return value: result, same type ### - "dp4" : ["anyfloat",[0,0],"NoMem"], + "dp4" : { "result" : "anyfloat", "arguments" : [0,0], "attributes" : "NoMem"}, ### ``llvm.genx.dph.`` : dph instruction (dot product homogenous) ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -768,7 +768,7 @@ ### ### * Return value: result, same type ### - "dph" : ["anyfloat",[0,0],"NoMem"], + "dph" : { "result" : "anyfloat", "arguments" : [0,0], "attributes" : "NoMem"}, ### ``llvm.genx.exp.`` : base 2 exponent ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -777,7 +777,7 @@ ### ### * Return value: result, same type ### - "exp" : ["anyfloat",[0],"NoMem"], + "exp" : { "result" : "anyfloat", "arguments" : [0], "attributes" : "NoMem"}, ### ``llvm.genx.*fbh.`` : find bit high ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -788,8 +788,8 @@ ### ### * Return value: result, same type ### - "sfbh" : ["anyint",[0],"NoMem"], - "ufbh" : ["anyint",[0],"NoMem"], + "sfbh" : { "result" : "anyint", "arguments" : [0], "attributes" : "NoMem"}, + "ufbh" : { "result" : "anyint", "arguments" : [0], "attributes" : "NoMem"}, ### ``llvm.genx.fbl.`` : find bit low ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -798,7 +798,7 @@ ### ### * Return value: result, same type ### - "fbl" : ["anyint",[0],"NoMem"], + "fbl" : { "result" : "anyint", "arguments" : [0], "attributes" : "NoMem"}, ### ``llvm.genx.frc.`` : fractional part ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -807,7 +807,7 @@ ### ### * Return value: result, same type ### - "frc" : ["anyfloat",[0],"NoMem"], + "frc" : { "result" : "anyfloat", "arguments" : [0], "attributes" : "NoMem"}, ### ``llvm.genx.inv.`` : reciprocal ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -816,7 +816,7 @@ ### ### * Return value: result, same type ### - "inv" : ["anyfloat",[0],"NoMem"], + "inv" : { "result" : "anyfloat", "arguments" : [0], "attributes" : "NoMem"}, ### ``llvm.genx.line.`` : linear equation ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -826,7 +826,7 @@ ### ### * Return value: result, same type as arg1 ### - "line" : ["anyfloat",["float4",0],"NoMem"], + "line" : { "result" : "anyfloat", "arguments" : ["float4",0], "attributes" : "NoMem"}, ### ``llvm.genx.log.`` : base 2 logarithm ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -835,7 +835,7 @@ ### ### * Return value: result, same type ### - "log" : ["anyfloat",[0],"NoMem"], + "log" : { "result" : "anyfloat", "arguments" : [0], "attributes" : "NoMem"}, ### ``llvm.genx.lrp.`` : linear interpolation ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -846,7 +846,7 @@ ### ### * Return value: result, same type ### - "lrp" : ["anyfloat",[0,0,0],"NoMem"], + "lrp" : { "result" : "anyfloat", "arguments" : [0,0,0], "attributes" : "NoMem"}, ### ``llvm.genx.lzd.`` : leading zero detection ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -855,7 +855,7 @@ ### ### * Return value: result, same type ### - "lzd" : ["anyint",[0],"NoMem"], + "lzd" : { "result" : "anyint", "arguments" : [0], "attributes" : "NoMem"}, ### ``llvm.genx.*mad..`` : mad instruction, no saturation ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -873,10 +873,10 @@ ### * arg1: second input, same type as arg0 ### * arg2: third input, same type as result ### - "ssmad" : ["anyint",["anyint",1,0],"NoMem"], - "sumad" : ["anyint",["anyint",1,0],"NoMem"], - "usmad" : ["anyint",["anyint",1,0],"NoMem"], - "uumad" : ["anyint",["anyint",1,0],"NoMem"], + "ssmad" : { "result" : "anyint", "arguments" : ["anyint",1,0], "attributes" : "NoMem"}, + "sumad" : { "result" : "anyint", "arguments" : ["anyint",1,0], "attributes" : "NoMem"}, + "usmad" : { "result" : "anyint", "arguments" : ["anyint",1,0], "attributes" : "NoMem"}, + "uumad" : { "result" : "anyint", "arguments" : ["anyint",1,0], "attributes" : "NoMem"}, ### ``llvm.genx.*mad.sat..`` : mad instruction with saturation ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -894,10 +894,10 @@ ### * arg1: second input, same type as arg0 ### * arg2: third input, same type as result ### - "ssmad_sat" : ["anyint",["anyint",1,0],"NoMem"], - "sumad_sat" : ["anyint",["anyint",1,0],"NoMem"], - "usmad_sat" : ["anyint",["anyint",1,0],"NoMem"], - "uumad_sat" : ["anyint",["anyint",1,0],"NoMem"], + "ssmad_sat" : { "result" : "anyint", "arguments" : ["anyint",1,0], "attributes" : "NoMem"}, + "sumad_sat" : { "result" : "anyint", "arguments" : ["anyint",1,0], "attributes" : "NoMem"}, + "usmad_sat" : { "result" : "anyint", "arguments" : ["anyint",1,0], "attributes" : "NoMem"}, + "uumad_sat" : { "result" : "anyint", "arguments" : ["anyint",1,0], "attributes" : "NoMem"}, ### ``llvm.genx.*max..`` : max instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -916,9 +916,9 @@ ### by this non-saturating max followed by the applicable one of the ### saturating trunc intrinsics. ### - "smax" : ["anyint",["anyint",1],"NoMem"], - "umax" : ["anyint",["anyint",1],"NoMem"], - "fmax" : ["anyfloat",["anyfloat",1],"NoMem"], + "smax" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, + "umax" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, + "fmax" : { "result" : "anyfloat", "arguments" : ["anyfloat",1], "attributes" : "NoMem"}, ### ``llvm.genx.*min.`` : min instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -937,9 +937,9 @@ ### by this non-saturating min followed by the applicable one of the ### saturating trunc intrinsics. ### - "smin" : ["anyint",["anyint",1],"NoMem"], - "umin" : ["anyint",["anyint",1],"NoMem"], - "fmin" : ["anyfloat",["anyfloat",1],"NoMem"], + "smin" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, + "umin" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, + "fmin" : { "result" : "anyfloat", "arguments" : ["anyfloat",1], "attributes" : "NoMem"}, ### mod ### ^^^ @@ -967,10 +967,10 @@ ### * arg0: first input, any scalar/vector integer type (not i64) (overloaded) ### * arg1: second input, same type as arg0 ### - "ssmul" : ["anyint",["anyint",1],"NoMem"], - "sumul" : ["anyint",["anyint",1],"NoMem"], - "usmul" : ["anyint",["anyint",1],"NoMem"], - "uumul" : ["anyint",["anyint",1],"NoMem"], + "ssmul" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, + "sumul" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, + "usmul" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, + "uumul" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, ### ``llvm.genx.*mul.sat..`` : mul instruction with saturation ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -988,10 +988,10 @@ ### For an fp mul, use the LLVM IR FMul instruction, followed by ### llvm.genx.sat if saturation is required. ### - "ssmul_sat" : ["anyint",["anyint",1],"NoMem"], - "sumul_sat" : ["anyint",["anyint",1],"NoMem"], - "usmul_sat" : ["anyint",["anyint",1],"NoMem"], - "uumul_sat" : ["anyint",["anyint",1],"NoMem"], + "ssmul_sat" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, + "sumul_sat" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, + "usmul_sat" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, + "uumul_sat" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, ### ``llvm.genx.*mulh..`` : mulh instruction, no saturation ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1003,8 +1003,8 @@ ### ### * Return value: result, same type as arg0 ### - "smulh" : ["anyint",["anyint",1],"NoMem"], - "umulh" : ["anyint",["anyint",1],"NoMem"], + "smulh" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, + "umulh" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, ### not ### ^^^ @@ -1024,7 +1024,7 @@ ### ### * Return value: result, vector float with half as many elements as arg1 ### - "pln" : ["anyfloat",["float4","anyfloat"],"NoMem"], + "pln" : { "result" : "anyfloat", "arguments" : ["float4","anyfloat"], "attributes" : "NoMem"}, ### ``llvm.genx.pow.`` : power ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1034,7 +1034,7 @@ ### ### * Return value: result, same type ### - "pow" : ["anyfloat",[0,0],"NoMem"], + "pow" : { "result" : "anyfloat", "arguments" : [0,0], "attributes" : "NoMem"}, ### ``llvm.genx.rndd.`` : round down ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1043,7 +1043,7 @@ ### ### * Return value: result, same type ### - "rndd" : ["anyfloat",[0],"NoMem"], + "rndd" : { "result" : "anyfloat", "arguments" : [0], "attributes" : "NoMem"}, ### ``llvm.genx.rnde.`` : round to even ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1052,7 +1052,7 @@ ### ### * Return value: result, same type ### - "rnde" : ["anyfloat",[0],"NoMem"], + "rnde" : { "result" : "anyfloat", "arguments" : [0], "attributes" : "NoMem"}, ### ``llvm.genx.rndu.`` : round up ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1061,7 +1061,7 @@ ### ### * Return value: result, same type ### - "rndu" : ["anyfloat",[0],"NoMem"], + "rndu" : { "result" : "anyfloat", "arguments" : [0], "attributes" : "NoMem"}, ### ``llvm.genx.rndz.`` : round to zero ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1070,7 +1070,7 @@ ### ### * Return value: result, same type ### - "rndz" : ["anyfloat",[0],"NoMem"], + "rndz" : { "result" : "anyfloat", "arguments" : [0], "attributes" : "NoMem"}, ### ``llvm.genx.rsqrt.`` : reciprocal square root ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1079,7 +1079,7 @@ ### ### * Return value: result, same type ### - "rsqrt" : ["anyfloat",[0],"NoMem"], + "rsqrt" : { "result" : "anyfloat", "arguments" : [0], "attributes" : "NoMem"}, ### ``llvm.genx.*sad2..`` : two-wide sum of absolute differences ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1091,8 +1091,8 @@ ### ### * Return value: result, vector of i16 of same vector width ### - "ssad2" : ["anyint",["anyint",1],"NoMem"], - "usad2" : ["anyint",["anyint",1],"NoMem"], + "ssad2" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, + "usad2" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, ### ``llvm.genx.*sad2add..`` : two-wide sum of absolute differences and add ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1107,10 +1107,10 @@ ### ### * Return value: result, same type as arg2 ### - "sssad2add" : ["anyint",["anyint",1,0],"NoMem"], - "uusad2add" : ["anyint",["anyint",1,0],"NoMem"], - "ussad2add" : ["anyint",["anyint",1,0],"NoMem"], - "susad2add" : ["anyint",["anyint",1,0],"NoMem"], + "sssad2add" : { "result" : "anyint", "arguments" : ["anyint",1,0], "attributes" : "NoMem"}, + "uusad2add" : { "result" : "anyint", "arguments" : ["anyint",1,0], "attributes" : "NoMem"}, + "ussad2add" : { "result" : "anyint", "arguments" : ["anyint",1,0], "attributes" : "NoMem"}, + "susad2add" : { "result" : "anyint", "arguments" : ["anyint",1,0], "attributes" : "NoMem"}, ### ``llvm.genx.*sad2add.sat..`` : two-wide sum of absolute differences and add, saturated ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1125,10 +1125,10 @@ ### ### * Return value: result, same type as arg2 ### - "sssad2add_sat" : ["anyint",["anyint",1,0],"NoMem"], - "uusad2add_sat" : ["anyint",["anyint",1,0],"NoMem"], - "ussad2add_sat" : ["anyint",["anyint",1,0],"NoMem"], - "susad2add_sat" : ["anyint",["anyint",1,0],"NoMem"], + "sssad2add_sat" : { "result" : "anyint", "arguments" : ["anyint",1,0], "attributes" : "NoMem"}, + "uusad2add_sat" : { "result" : "anyint", "arguments" : ["anyint",1,0], "attributes" : "NoMem"}, + "ussad2add_sat" : { "result" : "anyint", "arguments" : ["anyint",1,0], "attributes" : "NoMem"}, + "susad2add_sat" : { "result" : "anyint", "arguments" : ["anyint",1,0], "attributes" : "NoMem"}, ### ``llvm.genx.*shl..`` : shl instruction, no saturation ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1143,10 +1143,10 @@ ### * Return value: result, any scalar or vector integer type with same ### vector width, even i64 ### - "ssshl" : ["anyint",["anyint",1],"NoMem"], - "sushl" : ["anyint",["anyint",1],"NoMem"], - "usshl" : ["anyint",["anyint",1],"NoMem"], - "uushl" : ["anyint",["anyint",1],"NoMem"], + "ssshl" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, + "sushl" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, + "usshl" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, + "uushl" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, ### ``llvm.genx.*shl.sat..`` : shl instruction with saturation ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1161,10 +1161,10 @@ ### * Return value: result, any scalar/vector integer type with same ### vector width, even i64 ### - "ssshl_sat" : ["anyint",["anyint",1],"NoMem"], - "sushl_sat" : ["anyint",["anyint",1],"NoMem"], - "usshl_sat" : ["anyint",["anyint",1],"NoMem"], - "uushl_sat" : ["anyint",["anyint",1],"NoMem"], + "ssshl_sat" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, + "sushl_sat" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, + "usshl_sat" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, + "uushl_sat" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, ### shr ### ^^^ @@ -1184,8 +1184,8 @@ ### * Return value: result, any scalar or vector integer type with same ### vector width (even i64) ### - "rol" : ["anyint",["anyint",1],"NoMem"], - "ror" : ["anyint",["anyint",1],"NoMem"], + "rol" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, + "ror" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, ### ``llvm.genx.sin.`` : reciprocal square root ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1194,7 +1194,7 @@ ### ### * Return value: result, same type ### - "sin" : ["anyfloat",[0],"NoMem"], + "sin" : { "result" : "anyfloat", "arguments" : [0], "attributes" : "NoMem"}, ### ``llvm.genx.sqrt.`` : reciprocal square root ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1203,7 +1203,7 @@ ### ### * Return value: result, same type ### - "sqrt" : ["anyfloat",[0],"NoMem"], + "sqrt" : { "result" : "anyfloat", "arguments" : [0], "attributes" : "NoMem"}, ### ``llvm.genx.ieee.sqrt.`` : reciprocal square root, IEEE variant ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1212,7 +1212,7 @@ ### ### * Return value: result, same type ### - "ieee_sqrt" : ["anyfloat",[0],"NoMem"], + "ieee_sqrt" : { "result" : "anyfloat", "arguments" : [0], "attributes" : "NoMem"}, ### ``llvm.genx.dpas...`` : dpas instruction (Dot Product Accumulate Systolic) ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1224,7 +1224,7 @@ ### ### * Return value: result, same type as arg0 ### - "dpas" : ["anyvector",[0,"anyvector","anyvector","int"],"NoMem"], + "dpas" : { "result" : "anyvector", "arguments" : [0,"anyvector","anyvector","int"], "attributes" : "NoMem"}, ### ``llvm.genx.dpas2....`` : dpas instruction (Dot Product Accumulate Systolic) ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1241,7 +1241,7 @@ ### ### * Return value: result ### - "dpas2" : ["anyvector",["anyvector","anyvector","anyvector","int","int", "int", "int", "int", "int"],"NoMem"], + "dpas2" : { "result" : "anyvector", "arguments" : ["anyvector","anyvector","anyvector","int","int", "int", "int", "int", "int"], "attributes" : "NoMem"}, ### ``llvm.genx.dpas.nosrc0...`` : dpas instruction (Dot Product Accumulate Systolic) with no src0 ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1252,7 +1252,7 @@ ### ### * Return value: result ### - "dpas_nosrc0" : ["anyvector",["anyvector","anyvector","int"],"NoMem"], + "dpas_nosrc0" : { "result" : "anyvector", "arguments" : ["anyvector","anyvector","int"], "attributes" : "NoMem"}, ### ``llvm.genx.dpasw...`` : dpasw instruction (Dot Product Accumulate Systolic) ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1264,7 +1264,7 @@ ### ### * Return value: result, same type as arg0 ### - "dpasw" : ["anyvector",[0,"anyvector","anyvector","int"],"NoMem"], + "dpasw" : { "result" : "anyvector", "arguments" : [0,"anyvector","anyvector","int"], "attributes" : "NoMem"}, ### ``llvm.genx.dpasw.nosrc0...`` : dpasw instruction (Dot Product Accumulate Systolic) with no src0 ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1275,7 +1275,7 @@ ### ### * Return value: result ### - "dpasw_nosrc0" : ["anyvector",["anyvector","anyvector","int"],"NoMem"], + "dpasw_nosrc0" : { "result" : "anyvector", "arguments" : ["anyvector","anyvector","int"], "attributes" : "NoMem"}, ### ``llvm.genx.*dp4a*....`` : dp4a instruction (Dot Product 4 Accumulate) ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1295,14 +1295,14 @@ ### ### * Return value: result, vector integer type ### - "ssdp4a" : ["anyvector",["anyvector","anyvector","anyvector"],"NoMem"], - "sudp4a" : ["anyvector",["anyvector","anyvector","anyvector"],"NoMem"], - "usdp4a" : ["anyvector",["anyvector","anyvector","anyvector"],"NoMem"], - "uudp4a" : ["anyvector",["anyvector","anyvector","anyvector"],"NoMem"], - "ssdp4a_sat" : ["anyvector",["anyvector","anyvector","anyvector"],"NoMem"], - "sudp4a_sat" : ["anyvector",["anyvector","anyvector","anyvector"],"NoMem"], - "usdp4a_sat" : ["anyvector",["anyvector","anyvector","anyvector"],"NoMem"], - "uudp4a_sat" : ["anyvector",["anyvector","anyvector","anyvector"],"NoMem"], + "ssdp4a" : { "result" : "anyvector", "arguments" : ["anyvector","anyvector","anyvector"], "attributes" : "NoMem"}, + "sudp4a" : { "result" : "anyvector", "arguments" : ["anyvector","anyvector","anyvector"], "attributes" : "NoMem"}, + "usdp4a" : { "result" : "anyvector", "arguments" : ["anyvector","anyvector","anyvector"], "attributes" : "NoMem"}, + "uudp4a" : { "result" : "anyvector", "arguments" : ["anyvector","anyvector","anyvector"], "attributes" : "NoMem"}, + "ssdp4a_sat" : { "result" : "anyvector", "arguments" : ["anyvector","anyvector","anyvector"], "attributes" : "NoMem"}, + "sudp4a_sat" : { "result" : "anyvector", "arguments" : ["anyvector","anyvector","anyvector"], "attributes" : "NoMem"}, + "usdp4a_sat" : { "result" : "anyvector", "arguments" : ["anyvector","anyvector","anyvector"], "attributes" : "NoMem"}, + "uudp4a_sat" : { "result" : "anyvector", "arguments" : ["anyvector","anyvector","anyvector"], "attributes" : "NoMem"}, ### addc ### ^^^^ @@ -1313,7 +1313,7 @@ ### ### * arg0: first input, i32 scalar/vector integer type ### * arg1: second input, same type as arg0 - "addc" : [["anyint", "anyint"], [0, 0], "NoMem"], + "addc" : { "result" : ["anyint", "anyint"], "arguments" : [0, 0], "attributes" : "NoMem"}, ### subb ### ^^^^ @@ -1324,7 +1324,7 @@ ### ### * arg0: first input, i32 scalar/vector integer type ### * arg1: second input, same type as arg0 - "subb" : [["anyint", "anyint"], [0, 0], "NoMem"], + "subb" : { "result" : ["anyint", "anyint"], "arguments" : [0, 0], "attributes" : "NoMem"}, ### add3 ### ^^^^ @@ -1336,7 +1336,7 @@ ### * arg0: first input, any scalar/vector integer type, i16/i32 (overloaded) ### * arg1: second input, same type as arg0 ### * arg2: third input, same type as arg0 - "add3" : ["anyint",["anyint",1,1],"NoMem"], + "add3" : { "result" : "anyint", "arguments" : ["anyint",1,1], "attributes" : "NoMem"}, ### ``llvm.genx.*add3.sat..`` : add3 instruction with saturation ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1352,10 +1352,10 @@ ### * Return value: result, any scalar or vector integer type with same ### vector width ### - "ssadd3_sat" : ["anyint",["anyint",1,1],"NoMem"], - "suadd3_sat" : ["anyint",["anyint",1,1],"NoMem"], - "usadd3_sat" : ["anyint",["anyint",1,1],"NoMem"], - "uuadd3_sat" : ["anyint",["anyint",1,1],"NoMem"], + "ssadd3_sat" : { "result" : "anyint", "arguments" : ["anyint",1,1], "attributes" : "NoMem"}, + "suadd3_sat" : { "result" : "anyint", "arguments" : ["anyint",1,1], "attributes" : "NoMem"}, + "usadd3_sat" : { "result" : "anyint", "arguments" : ["anyint",1,1], "attributes" : "NoMem"}, + "uuadd3_sat" : { "result" : "anyint", "arguments" : ["anyint",1,1], "attributes" : "NoMem"}, ### bfn ### ^^^ @@ -1368,7 +1368,7 @@ ### * arg1: second input, same type as arg0 ### * arg2: third input, same type as arg0 ### * arg3: fourth input, byte, constant - "bfn" : ["anyint",["anyint",1,1,"char"],"NoMem"], + "bfn" : { "result" : "anyint", "arguments" : ["anyint",1,1,"char"], "attributes" : "NoMem"}, ### xor ### ^^^ @@ -1386,8 +1386,8 @@ ### ### * Return value: i16 the value read ### - "thread_x" : ["short",[],"NoMem"], - "thread_y" : ["short",[],"NoMem"], + "thread_x" : { "result" : "short", "arguments" : [], "attributes" : "NoMem"}, + "thread_y" : { "result" : "short", "arguments" : [], "attributes" : "NoMem"}, ### ``llvm.genx.group.id.*`` : read group ID register ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1397,9 +1397,9 @@ ### ### * Return value: i32 the value read ### - "group_id_x" : ["int",[],"NoMem"], - "group_id_y" : ["int",[],"NoMem"], - "group_id_z" : ["int",[],"NoMem"], + "group_id_x" : { "result" : "int", "arguments" : [], "attributes" : "NoMem"}, + "group_id_y" : { "result" : "int", "arguments" : [], "attributes" : "NoMem"}, + "group_id_z" : { "result" : "int", "arguments" : [], "attributes" : "NoMem"}, ### ``llvm.genx.timestamp.`` : read vISA v11 (%timestamp) ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1408,7 +1408,7 @@ ### ### The vector width must be power of 2 and no larger than 4. ### - "timestamp" : ["anyint",[],"None"], + "timestamp" : { "result" : "anyint", "arguments" : [], "attributes" : "None"}, ### ``llvm.genx.r0.`` : read vISA v12 (%r0) ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1417,7 +1417,7 @@ ### ### The vector width must be power of 2 and no larger than 8. ### - "r0" : ["anyint",[],"ReadMem"], + "r0" : { "result" : "anyint", "arguments" : [], "attributes" : "ReadMem"}, ### ``llvm.genx.sr0.`` : read vISA v13 (%sr0) ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1427,7 +1427,7 @@ ### The vector width must be 4 ### ### - "sr0" : ["anyint",[],"ReadMem"], + "sr0" : { "result" : "anyint", "arguments" : [], "attributes" : "ReadMem"}, ### ``llvm.genx.set.sr0.2`` : write vISA v13(0, 2) (%sr0.2) ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1436,7 +1436,7 @@ ### ### * Return value: void ### - "set_sr0_2" : ["void",["int"],"None"], + "set_sr0_2" : { "result" : "void", "arguments" : ["int"], "attributes" : "None"}, ### ``llvm.genx.get.color`` : read color value of the thread origin ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1446,21 +1446,21 @@ ### This may not be the most appropriate way to access this value, ### but is a stop-gap solution. ### - "get_color" : ["short",[],"NoMem"], + "get_color" : { "result" : "short", "arguments" : [], "attributes" : "NoMem"}, ### ``llvm.genx.get.hwid`` : read hw_id value ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ### ### Return Value: i32 the value read ### - "get_hwid" : ["int",[],"NoMem"], + "get_hwid" : { "result" : "int", "arguments" : [], "attributes" : "NoMem"}, ### ``llvm.genx.ce0`` : read channel-enable register ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ### ### Return Value: i32 the value read ### - "ce0" : ["int",[],"ReadMem"], + "ce0" : { "result" : "int", "arguments" : [], "attributes" : "ReadMem"}, ### ``llvm.genx.set.pause`` : set the pause register (v11.4) ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1475,7 +1475,7 @@ ### ### We set this intrinsic to have side-effects (last field empty) to stop it being removed as it ### otherwise looks dead - "set_pause" : ["void",["short"],"None"], + "set_pause" : { "result" : "void", "arguments" : ["short"], "attributes" : "None"}, ### ``llvm.genx.dummy.mov`` : insert a dummy mov to v0 ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1492,7 +1492,7 @@ ### ### We set this intrinsic to have side-effects (last field empty) to stop it being removed as it ### otherwise looks dead and also to prevent any kind of code motion optimisation - "dummy_mov" : ["void",["short"],"None"], + "dummy_mov" : { "result" : "void", "arguments" : ["short"], "attributes" : "None"}, ### The following 2 predef.reg intrinsics aren't translated directly to read/writes of the reg, ### instead they're baled together with rd/wrregions and in fact indicate that those rdr/wrrs @@ -1507,7 +1507,7 @@ ### * Return value: value read ### ### - "read_predef_reg" : ["any",["int", "any"],"ReadMem"], + "read_predef_reg" : { "result" : "any", "arguments" : ["int", "any"], "attributes" : "ReadMem"}, ### ``llvm.write.predef.reg..`` : write value to predefined vISA reg ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1517,7 +1517,7 @@ ### ### * Return value: value written ### - "write_predef_reg" : ["any",["int", "any"],"WriteMem"], + "write_predef_reg" : { "result" : "any", "arguments" : ["int", "any"], "attributes" : "WriteMem"}, ## -------------------------- ### Shared function intrinsics @@ -1551,16 +1551,16 @@ ### Predicate, element offset, src, and the return value must all have the ### same vector width, which must be 1, 8 or 16. ### - "dword_atomic_add" : ["anyvector",["anyvector","int","anyint",0,0],"None"], - "dword_atomic_sub" : ["anyvector",["anyvector","int","anyint",0,0],"None"], - "dword_atomic_min" : ["anyvector",["anyvector","int","anyint",0,0],"None"], - "dword_atomic_max" : ["anyvector",["anyvector","int","anyint",0,0],"None"], - "dword_atomic_xchg" : ["anyvector",["anyvector","int","anyint",0,0],"None"], - "dword_atomic_and" : ["anyvector",["anyvector","int","anyint",0,0],"None"], - "dword_atomic_or" : ["anyvector",["anyvector","int","anyint",0,0],"None"], - "dword_atomic_xor" : ["anyvector",["anyvector","int","anyint",0,0],"None"], - "dword_atomic_imin" : ["anyvector",["anyvector","int","anyint",0,0],"None"], - "dword_atomic_imax" : ["anyvector",["anyvector","int","anyint",0,0],"None"], + "dword_atomic_add" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0,0], "attributes" : "None"}, + "dword_atomic_sub" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0,0], "attributes" : "None"}, + "dword_atomic_min" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0,0], "attributes" : "None"}, + "dword_atomic_max" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0,0], "attributes" : "None"}, + "dword_atomic_xchg" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0,0], "attributes" : "None"}, + "dword_atomic_and" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0,0], "attributes" : "None"}, + "dword_atomic_or" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0,0], "attributes" : "None"}, + "dword_atomic_xor" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0,0], "attributes" : "None"}, + "dword_atomic_imin" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0,0], "attributes" : "None"}, + "dword_atomic_imax" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0,0], "attributes" : "None"}, ### ``llvm.genx.dword.atomic2.*..`` : dword atomic with binary operator (variant with no oldval) ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1586,16 +1586,16 @@ ### Predicate, element offset, src, and the return value must all have the ### same vector width, which must be 1, 8 or 16. ### - "dword_atomic2_add" : ["anyvector",["anyvector","int","anyint",0],"None"], - "dword_atomic2_sub" : ["anyvector",["anyvector","int","anyint",0],"None"], - "dword_atomic2_min" : ["anyvector",["anyvector","int","anyint",0],"None"], - "dword_atomic2_max" : ["anyvector",["anyvector","int","anyint",0],"None"], - "dword_atomic2_xchg" : ["anyvector",["anyvector","int","anyint",0],"None"], - "dword_atomic2_and" : ["anyvector",["anyvector","int","anyint",0],"None"], - "dword_atomic2_or" : ["anyvector",["anyvector","int","anyint",0],"None"], - "dword_atomic2_xor" : ["anyvector",["anyvector","int","anyint",0],"None"], - "dword_atomic2_imin" : ["anyvector",["anyvector","int","anyint",0],"None"], - "dword_atomic2_imax" : ["anyvector",["anyvector","int","anyint",0],"None"], + "dword_atomic2_add" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0], "attributes" : "None"}, + "dword_atomic2_sub" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0], "attributes" : "None"}, + "dword_atomic2_min" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0], "attributes" : "None"}, + "dword_atomic2_max" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0], "attributes" : "None"}, + "dword_atomic2_xchg" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0], "attributes" : "None"}, + "dword_atomic2_and" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0], "attributes" : "None"}, + "dword_atomic2_or" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0], "attributes" : "None"}, + "dword_atomic2_xor" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0], "attributes" : "None"}, + "dword_atomic2_imin" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0], "attributes" : "None"}, + "dword_atomic2_imax" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0], "attributes" : "None"}, ### ``llvm.genx.dword.atomic.*...`` : dword atomic with fmin/fmax operation ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1614,8 +1614,8 @@ ### Predicate, element offset, src, and the return value must all have the ### same vector width, which must be 1, 8 or 16. ### - "dword_atomic_fmin" : ["anyvector",["anyvector","int","anyint",0,0],"None"], - "dword_atomic_fmax" : ["anyvector",["anyvector","int","anyint",0,0],"None"], + "dword_atomic_fmin" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0,0], "attributes" : "None"}, + "dword_atomic_fmax" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0,0], "attributes" : "None"}, ### ``llvm.genx.dword.atomic2.*...`` : dword atomic with fmin/fmax operation (variant with no oldval) ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1633,8 +1633,8 @@ ### Predicate, element offset, src, and the return value must all have the ### same vector width, which must be 1, 8 or 16. ### - "dword_atomic2_fmin" : ["anyvector",["anyvector","int","anyint",0],"None"], - "dword_atomic2_fmax" : ["anyvector",["anyvector","int","anyint",0],"None"], + "dword_atomic2_fmin" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0], "attributes" : "None"}, + "dword_atomic2_fmax" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0], "attributes" : "None"}, ### ``llvm.genx.dword.atomic.*..`` : dword atomic with inc/dec operation @@ -1653,8 +1653,8 @@ ### Predicate, element offset, src, and the return value must all have the ### same vector width, which must be 1, 8 or 16. ### - "dword_atomic_inc" : ["anyvector",["anyvector","int",0,0],"None"], - "dword_atomic_dec" : ["anyvector",["anyvector","int",0,0],"None"], + "dword_atomic_inc" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,0], "attributes" : "None"}, + "dword_atomic_dec" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,0], "attributes" : "None"}, ### ``llvm.genx.dword.atomic2.*..`` : dword atomic with inc/dec operation (variant with no oldval) ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1671,8 +1671,8 @@ ### Predicate, element offset, src, and the return value must all have the ### same vector width, which must be 1, 8 or 16. ### - "dword_atomic2_inc" : ["anyvector",["anyvector","int",0],"None"], - "dword_atomic2_dec" : ["anyvector",["anyvector","int",0],"None"], + "dword_atomic2_inc" : { "result" : "anyvector", "arguments" : ["anyvector","int",0], "attributes" : "None"}, + "dword_atomic2_dec" : { "result" : "anyvector", "arguments" : ["anyvector","int",0], "attributes" : "None"}, ### ``llvm.genx.dword.atomic.cmpxchg..`` : vISA DWORD_ATOMIC CMPXCHG instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1690,7 +1690,7 @@ ### Predicate, element offset, src, and the return value must all have the ### same vector width, which must be 1, 8 or 16. ### - "dword_atomic_cmpxchg" : ["anyvector",["anyvector","int",0,0,0,0],"None"], + "dword_atomic_cmpxchg" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,0,0,0], "attributes" : "None"}, ### ``llvm.genx.dword.atomic2.cmpxchg..`` : vISA DWORD_ATOMIC CMPXCHG instruction (variant with no oldval) ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1707,7 +1707,7 @@ ### Predicate, element offset, src, and the return value must all have the ### same vector width, which must be 1, 8 or 16. ### - "dword_atomic2_cmpxchg" : ["anyvector",["anyvector","int",0,0,0],"None"], + "dword_atomic2_cmpxchg" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,0,0], "attributes" : "None"}, ### ``llvm.genx.dword.atomic.fcmpwr...`` : vISA DWORD_ATOMIC FCMPWR instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1725,7 +1725,7 @@ ### Predicate, element offset, src, and the return value must all have the ### same vector width, which must be 1, 8 or 16. ### - "dword_atomic_fcmpwr" : ["anyvector",["anyvector","int","anyint",0,0,0],"None"], + "dword_atomic_fcmpwr" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0,0,0], "attributes" : "None"}, ### ``llvm.genx.dword.atomic2.fcmpwr...`` : vISA DWORD_ATOMIC FCMPWR instruction (variant with no oldval) ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1742,7 +1742,7 @@ ### Predicate, element offset, src, and the return value must all have the ### same vector width, which must be 1, 8 or 16. ### - "dword_atomic2_fcmpwr" : ["anyvector",["anyvector","int","anyint",0,0],"None"], + "dword_atomic2_fcmpwr" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0,0], "attributes" : "None"}, ### ``llvm.genx.typed.atomic.*...`` : atomic typed with binary operator ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1771,16 +1771,16 @@ ### Predicate, element offset, src, and the return value must all have the ### same vector width (which in reality must be 8) ### - "typed_atomic_add" : ["anyvector",["anyvector","int",0,"anyint",2,2,2],"None"], - "typed_atomic_sub" : ["anyvector",["anyvector","int",0,"anyint",2,2,2],"None"], - "typed_atomic_min" : ["anyvector",["anyvector","int",0,"anyint",2,2,2],"None"], - "typed_atomic_max" : ["anyvector",["anyvector","int",0,"anyint",2,2,2],"None"], - "typed_atomic_xchg" : ["anyvector",["anyvector","int",0,"anyint",2,2,2],"None"], - "typed_atomic_and" : ["anyvector",["anyvector","int",0,"anyint",2,2,2],"None"], - "typed_atomic_or" : ["anyvector",["anyvector","int",0,"anyint",2,2,2],"None"], - "typed_atomic_xor" : ["anyvector",["anyvector","int",0,"anyint",2,2,2],"None"], - "typed_atomic_imin" : ["anyvector",["anyvector","int",0,"anyint",2,2,2],"None"], - "typed_atomic_imax" : ["anyvector",["anyvector","int",0,"anyint",2,2,2],"None"], + "typed_atomic_add" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,"anyint",2,2,2], "attributes" : "None"}, + "typed_atomic_sub" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,"anyint",2,2,2], "attributes" : "None"}, + "typed_atomic_min" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,"anyint",2,2,2], "attributes" : "None"}, + "typed_atomic_max" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,"anyint",2,2,2], "attributes" : "None"}, + "typed_atomic_xchg" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,"anyint",2,2,2], "attributes" : "None"}, + "typed_atomic_and" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,"anyint",2,2,2], "attributes" : "None"}, + "typed_atomic_or" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,"anyint",2,2,2], "attributes" : "None"}, + "typed_atomic_xor" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,"anyint",2,2,2], "attributes" : "None"}, + "typed_atomic_imin" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,"anyint",2,2,2], "attributes" : "None"}, + "typed_atomic_imax" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,"anyint",2,2,2], "attributes" : "None"}, ### ``llvm.genx.typed.atomic.*...`` : atomic typed with fmin/fmax operation ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1801,8 +1801,8 @@ ### Predicate, element offset, src, and the return value must all have the ### same vector width (which in reality must be 8) ### - "typed_atomic_fmin" : ["anyvector",["anyvector","int",0,"anyint",2,2,2],"None"], - "typed_atomic_fmax" : ["anyvector",["anyvector","int",0,"anyint",2,2,2],"None"], + "typed_atomic_fmin" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,"anyint",2,2,2], "attributes" : "None"}, + "typed_atomic_fmax" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,"anyint",2,2,2], "attributes" : "None"}, ### ``llvm.genx.typed.atomic.*...`` : atomic typed with inc/dec operation ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1822,8 +1822,8 @@ ### Predicate, element offset, src, and the return value must all have the ### same vector width (which in reality must be 8) ### - "typed_atomic_inc" : ["anyvector",["anyvector","int","anyint",2,2,2],"None"], - "typed_atomic_dec" : ["anyvector",["anyvector","int","anyint",2,2,2],"None"], + "typed_atomic_inc" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",2,2,2], "attributes" : "None"}, + "typed_atomic_dec" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",2,2,2], "attributes" : "None"}, ### ``llvm.genx.typed.atomic.cmpxchg...`` : vISA TYPED_ATOMIC CMPXCHG instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1843,7 +1843,7 @@ ### Predicate, element offset, src, and the return value must all have the ### same vector width (which in reality must be 8) ### - "typed_atomic_cmpxchg" : ["anyvector",["anyvector","int",0,0,"anyint",2,2,2],"None"], + "typed_atomic_cmpxchg" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,0,"anyint",2,2,2], "attributes" : "None"}, ### ``llvm.genx.typed.atomic.fcmpwr...`` : vISA TYPED_ATOMIC FCMPWR instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1863,7 +1863,7 @@ ### Predicate, element offset, src, and the return value must all have the ### same vector width (which in reality must be 8) ### - "typed_atomic_fcmpwr" : ["anyvector",["anyvector","int",0,0,"anyint",2,2,2],"None"], + "typed_atomic_fcmpwr" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,0,"anyint",2,2,2], "attributes" : "None"}, ### ``llvm.genx.gather.private...`` : CMC internal, no VISA ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1881,7 +1881,7 @@ ### ### The element offset arg must have the same vector width. ### - "gather_private" : ["anyvector",["anyvector","anyptr","anyint",0],"ReadMem"], + "gather_private" : { "result" : "anyvector", "arguments" : ["anyvector","anyptr","anyint",0], "attributes" : "ReadMem"}, ### ``llvm.genx.gather.scaled...`` : vISA GATHER_SCALED instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1906,7 +1906,7 @@ ### F type. For 1 and 2 byte (1 x num blocks) reads the upper bytes have ### undefined values in the returned value. ### - "gather_scaled" : ["anyvector",["anyvector","int","short","int","int","anyint",0],"ReadMem"], + "gather_scaled" : { "result" : "anyvector", "arguments" : ["anyvector","int","short","int","int","anyint",0], "attributes" : "ReadMem"}, ### ``llvm.genx.gather.scaled2`` : vISA GATHER_SCALED instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1929,7 +1929,7 @@ ### For 1 and 2 byte (1 x num blocks) reads the upper bytes have ### undefined values in the returned value. ### - "gather_scaled2" : ["anyvector",["int","short","int","int","anyint"],"ReadMem"], + "gather_scaled2" : { "result" : "anyvector", "arguments" : ["int","short","int","int","anyint"], "attributes" : "ReadMem"}, ### ``llvm.genx.gather.masked.scaled2`` : vISA GATHER_SCALED instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1945,7 +1945,7 @@ ### ### * Return value: the data read ### - "gather_masked_scaled2" : ["anyvector",["int","short","int","int","anyint","anyvector"],"ReadMem"], + "gather_masked_scaled2" : { "result" : "anyvector", "arguments" : ["int","short","int","int","anyint","anyvector"], "attributes" : "ReadMem"}, ### ``llvm.genx.gather4.scaled...`` : vISA GATHER4_SCALED instruction @@ -1973,7 +1973,7 @@ ### times the number of channels to read per element. ### The element type of the return value must be i32 or float. ### - "gather4_scaled" : ["anyvector",["anyvector","int","short","int","int","anyint",0],"ReadMem"], + "gather4_scaled" : { "result" : "anyvector", "arguments" : ["anyvector","int","short","int","int","anyint",0], "attributes" : "ReadMem"}, ### ``llvm.genx.gather4.scaled2`` : vISA GATHER4_SCALED instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2001,7 +2001,7 @@ ### times the number of channels to read per element. ### The element type of the return value must be i32 or float. ### - "gather4_scaled2" : ["anyvector",["int","short","int","int","anyint"],"ReadMem"], + "gather4_scaled2" : { "result" : "anyvector", "arguments" : ["int","short","int","int","anyint"], "attributes" : "ReadMem"}, ### ``llvm.genx.gather4.masked.scaled2`` : vISA GATHER4_SCALED instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2016,7 +2016,7 @@ ### ### * Return value: the data read ### - "gather4_masked_scaled2" : ["anyvector",["int","short","int","int","anyint","anyvector"],"ReadMem"], + "gather4_masked_scaled2" : { "result" : "anyvector", "arguments" : ["int","short","int","int","anyint","anyvector"], "attributes" : "ReadMem"}, ### ``llvm.genx.gather4.typed...`` : vISA GATHER4_TYPED instruction @@ -2044,7 +2044,7 @@ ### times the number of channels to read per element. ### The element type of the return value must be i32 or float. ### - "gather4_typed" : ["anyvector",["int","anyvector","int","anyvector",2,2,0],"ReadMem"], + "gather4_typed" : { "result" : "anyvector", "arguments" : ["int","anyvector","int","anyvector",2,2,0], "attributes" : "ReadMem"}, ### ``llvm.genx.media.ld.`` : vISA MEDIA_LD instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2067,7 +2067,7 @@ ### The block width has a maximum of 32 (64 on BDW+). The maxmimum byte ### size of the return type is 256. ### - "media_ld" : ["anyvector",["int","int","int","int","int","int"],"ReadMem"], + "media_ld" : { "result" : "anyvector", "arguments" : ["int","int","int","int","int","int"], "attributes" : "ReadMem"}, ### ``llvm.genx.media.st.`` : vISA MEDIA_ST instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2089,7 +2089,7 @@ ### The block width has a maximum of 32 (64 on BDW+). The maxmimum byte ### size of the data to write is 256. ### - "media_st" : ["void",["int","int","int","int","int","int","anyvector"],"None"], + "media_st" : { "result" : "void", "arguments" : ["int","int","int","int","int","int","anyvector"], "attributes" : "None"}, ### ``llvm.genx.oword.ld*.`` : oword load instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2105,8 +2105,8 @@ ### ### The byte size of the return type must be 16, 32, 64, or 128. ### - "oword_ld" : ["anyvector",["int","int","int"],"ReadMem"], - "oword_ld_unaligned" : ["anyvector",["int","int","int"],"ReadMem"], + "oword_ld" : { "result" : "anyvector", "arguments" : ["int","int","int"], "attributes" : "ReadMem"}, + "oword_ld_unaligned" : { "result" : "anyvector", "arguments" : ["int","int","int"], "attributes" : "ReadMem"}, ### ``llvm.genx.oword.st.`` : vISA OWORD_ST instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2118,7 +2118,7 @@ ### ### The byte size of the data to write must be 16, 32, 64, or 128. ### - "oword_st" : ["void",["int","int","anyvector"],"None"], + "oword_st" : { "result" : "void", "arguments" : ["int","int","anyvector"], "attributes" : "None"}, ### ``llvm.genx.scatter.private....`` : CM internal, no VISA ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2132,7 +2132,7 @@ ### which must be 1, 8 or 16. ### The element offset arg must have the same vector width. ### - "scatter_private" : ["void",["anyvector","anyptr","anyint","anyvector"],"None"], + "scatter_private" : { "result" : "void", "arguments" : ["anyvector","anyptr","anyint","anyvector"], "attributes" : "None"}, ### ``llvm.genx.scatter.scaled...`` : vISA SCATTER_SCALED instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2154,7 +2154,7 @@ ### The data type to write must have UD, D or F type. For 1 and 2 byte (1 x num ### blocks) accesses the upper bytes will be ignored. ### - "scatter_scaled" : ["void",["anyvector","int","short","int","int","anyint","anyvector"],"None"], + "scatter_scaled" : { "result" : "void", "arguments" : ["anyvector","int","short","int","int","anyint","anyvector"], "attributes" : "None"}, ### ``llvm.genx.scatter4.scaled...`` : vISA SCATTER4_SCALED instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2180,7 +2180,7 @@ ### times the number of channels to write per element. ### The element type of the data to write must be i32 or float. ### - "scatter4_scaled" : ["void",["anyvector","int","short","int","int","anyint","anyvector"],"None"], + "scatter4_scaled" : { "result" : "void", "arguments" : ["anyvector","int","short","int","int","anyint","anyvector"], "attributes" : "None"}, ### ``llvm.genx.scatter4.typed...`` : vISA SCATTER4_TYPED instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2205,7 +2205,7 @@ ### times the number of channels to read per element. ### The element type of the source value must be i32 or float. ### - "scatter4_typed" : ["void",["int","anyvector","int","anyvector",1,1,"anyvector"],"None"], + "scatter4_typed" : { "result" : "void", "arguments" : ["int","anyvector","int","anyvector",1,1,"anyvector"], "attributes" : "None"}, ### ``llvm.genx.transpose.ld.`` : vISA TRANSPOSE_LD instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2223,7 +2223,7 @@ ### inferred from those values. ### The element type of the return value must be i32 or float. ### - "transpose_ld" : ["anyvector",["int","int","int","int"],"ReadMem"], + "transpose_ld" : { "result" : "anyvector", "arguments" : ["int","int","int","int"], "attributes" : "ReadMem"}, ### ``llvm.genx.untyped.atomic.*..`` : vISA UNTYPED_ATOMIC with binary operator ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2250,16 +2250,16 @@ ### Predicate, element offset, src, and the return value must all have the ##same vector / width, which must be 8 or 16. ### - "untyped_atomic_add" : ["anyvector",["anyvector","int","int",0,0,0],"None"], - "untyped_atomic_sub" : ["anyvector",["anyvector","int","int",0,0,0],"None"], - "untyped_atomic_min" : ["anyvector",["anyvector","int","int",0,0,0],"None"], - "untyped_atomic_max" : ["anyvector",["anyvector","int","int",0,0,0],"None"], - "untyped_atomic_xchg" : ["anyvector",["anyvector","int","int",0,0,0],"None"], - "untyped_atomic_and" : ["anyvector",["anyvector","int","int",0,0,0],"None"], - "untyped_atomic_or" : ["anyvector",["anyvector","int","int",0,0,0],"None"], - "untyped_atomic_xor" : ["anyvector",["anyvector","int","int",0,0,0],"None"], - "untyped_atomic_imin" : ["anyvector",["anyvector","int","int",0,0,0],"None"], - "untyped_atomic_imax" : ["anyvector",["anyvector","int","int",0,0,0],"None"], + "untyped_atomic_add" : { "result" : "anyvector", "arguments" : ["anyvector","int","int",0,0,0], "attributes" : "None"}, + "untyped_atomic_sub" : { "result" : "anyvector", "arguments" : ["anyvector","int","int",0,0,0], "attributes" : "None"}, + "untyped_atomic_min" : { "result" : "anyvector", "arguments" : ["anyvector","int","int",0,0,0], "attributes" : "None"}, + "untyped_atomic_max" : { "result" : "anyvector", "arguments" : ["anyvector","int","int",0,0,0], "attributes" : "None"}, + "untyped_atomic_xchg" : { "result" : "anyvector", "arguments" : ["anyvector","int","int",0,0,0], "attributes" : "None"}, + "untyped_atomic_and" : { "result" : "anyvector", "arguments" : ["anyvector","int","int",0,0,0], "attributes" : "None"}, + "untyped_atomic_or" : { "result" : "anyvector", "arguments" : ["anyvector","int","int",0,0,0], "attributes" : "None"}, + "untyped_atomic_xor" : { "result" : "anyvector", "arguments" : ["anyvector","int","int",0,0,0], "attributes" : "None"}, + "untyped_atomic_imin" : { "result" : "anyvector", "arguments" : ["anyvector","int","int",0,0,0], "attributes" : "None"}, + "untyped_atomic_imax" : { "result" : "anyvector", "arguments" : ["anyvector","int","int",0,0,0], "attributes" : "None"}, ### ``llvm.genx.untyped.atomic.*..`` : vISA UNTYPED_ATOMIC with inc/dec ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2277,8 +2277,8 @@ ### Predicate, element offset and the return value must have the same vector ### width, which must be 8 or 16. ### - "untyped_atomic_inc" : ["anyvector",["anyvector","int","int",0,0],"None"], - "untyped_atomic_dec" : ["anyvector",["anyvector","int","int",0,0],"None"], + "untyped_atomic_inc" : { "result" : "anyvector", "arguments" : ["anyvector","int","int",0,0], "attributes" : "None"}, + "untyped_atomic_dec" : { "result" : "anyvector", "arguments" : ["anyvector","int","int",0,0], "attributes" : "None"}, ### ``llvm.genx.untyped.atomic.cmpxchg..`` : vISA UNTYPED_ATOMIC CMPXCHG instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2296,7 +2296,7 @@ ### Predicate, element offset, src0, src1, and the return value must all have ### the same vector width, which must be 8 or 16. ### - "untyped_atomic_cmpxchg" : ["anyvector",["anyvector","int","int",0,0,0,0],"None"], + "untyped_atomic_cmpxchg" : { "result" : "anyvector", "arguments" : ["anyvector","int","int",0,0,0,0], "attributes" : "None"}, ### ``llvm.genx.svm.block.ld*..
`` : vISA SVM BLOCK_LD instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2313,8 +2313,8 @@ ### The data read must have a size that is a power of two from 16 to 128 ### bytes. ### - "svm_block_ld" : ["anyvector",["anyint"],"ReadMem"], - "svm_block_ld_unaligned" : ["anyvector",["anyint"],"ReadMem"], + "svm_block_ld" : { "result" : "anyvector", "arguments" : ["anyint"], "attributes" : "ReadMem"}, + "svm_block_ld_unaligned" : { "result" : "anyvector", "arguments" : ["anyint"], "attributes" : "ReadMem"}, ### ``llvm.genx.svm.block.st.
`` : vISA SVM BLOCK_ST instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2326,7 +2326,7 @@ ### The data to write must have a size that is a power of two from 16 to 128 ### bytes. ### - "svm_block_st" : ["void",["anyint","anyvector"],"None"], + "svm_block_st" : { "result" : "void", "arguments" : ["anyint","anyvector"], "attributes" : "None"}, ### ``llvm.genx.svm.gather...`` : vISA SVM GATHER instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2345,7 +2345,7 @@ ### The return value vector width is the address vector width times ### number of blocks (rounded up to 4 if block size is 1). ### - "svm_gather" : ["anyvector",["anyvector","int","anyint",0],"ReadMem"], + "svm_gather" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0], "attributes" : "ReadMem"}, ### ``llvm.genx.svm.gather4.scaled...`` : vISA SVM GATHER4_SCALED instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2372,7 +2372,7 @@ ### times the number of channels to read per element. ### The element type of the return value must be i32 or float. ### - "svm_gather4_scaled" : ["anyvector",["anyvector","int","short","long","anyint",0],"ReadMem"], + "svm_gather4_scaled" : { "result" : "anyvector", "arguments" : ["anyvector","int","short","long","anyint",0], "attributes" : "ReadMem"}, ### ``llvm.genx.svm.scatter...`` : vISA SVM SCATTER instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2389,7 +2389,7 @@ ### The data vector width is the address vector width times ### number of blocks (rounded up to 4 if block size is 1). ### - "svm_scatter" : ["void",["anyvector","int","anyint","anyvector"],"None"], + "svm_scatter" : { "result" : "void", "arguments" : ["anyvector","int","anyint","anyvector"], "attributes" : "None"}, ### ``llvm.genx.svm.scatter4.scaled...`` : vISA SVM SCATTER4_SCALED instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2414,7 +2414,7 @@ ### times the number of channels to read per element. ### The element type of the data to write arg must be i32 or float. ### - "svm_scatter4_scaled" : ["void",["anyvector","int","short","long","anyint","anyvector"],"None"], + "svm_scatter4_scaled" : { "result" : "void", "arguments" : ["anyvector","int","short","long","anyint","anyvector"], "attributes" : "None"}, ### ``llvm.genx.svm.atomic.*...`` : vISA SVM_ATOMIC with binary operator ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2439,16 +2439,16 @@ ### Predicate, element offset, src, and the return value must all have the ### same vector width, which must be 1, 2, 4, or 8. ### - "svm_atomic_add" : ["anyvector",["anyvector","anyint",0,0],"None"], - "svm_atomic_sub" : ["anyvector",["anyvector","anyint",0,0],"None"], - "svm_atomic_min" : ["anyvector",["anyvector","anyint",0,0],"None"], - "svm_atomic_max" : ["anyvector",["anyvector","anyint",0,0],"None"], - "svm_atomic_xchg" : ["anyvector",["anyvector","anyint",0,0],"None"], - "svm_atomic_and" : ["anyvector",["anyvector","anyint",0,0],"None"], - "svm_atomic_or" : ["anyvector",["anyvector","anyint",0,0],"None"], - "svm_atomic_xor" : ["anyvector",["anyvector","anyint",0,0],"None"], - "svm_atomic_imin" : ["anyvector",["anyvector","anyint",0,0],"None"], - "svm_atomic_imax" : ["anyvector",["anyvector","anyint",0,0],"None"], + "svm_atomic_add" : { "result" : "anyvector", "arguments" : ["anyvector","anyint",0,0], "attributes" : "None"}, + "svm_atomic_sub" : { "result" : "anyvector", "arguments" : ["anyvector","anyint",0,0], "attributes" : "None"}, + "svm_atomic_min" : { "result" : "anyvector", "arguments" : ["anyvector","anyint",0,0], "attributes" : "None"}, + "svm_atomic_max" : { "result" : "anyvector", "arguments" : ["anyvector","anyint",0,0], "attributes" : "None"}, + "svm_atomic_xchg" : { "result" : "anyvector", "arguments" : ["anyvector","anyint",0,0], "attributes" : "None"}, + "svm_atomic_and" : { "result" : "anyvector", "arguments" : ["anyvector","anyint",0,0], "attributes" : "None"}, + "svm_atomic_or" : { "result" : "anyvector", "arguments" : ["anyvector","anyint",0,0], "attributes" : "None"}, + "svm_atomic_xor" : { "result" : "anyvector", "arguments" : ["anyvector","anyint",0,0], "attributes" : "None"}, + "svm_atomic_imin" : { "result" : "anyvector", "arguments" : ["anyvector","anyint",0,0], "attributes" : "None"}, + "svm_atomic_imax" : { "result" : "anyvector", "arguments" : ["anyvector","anyint",0,0], "attributes" : "None"}, ### ``llvm.genx.svm.atomic.*...`` : vISA SVM_ATOMIC with inc/dec ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2464,8 +2464,8 @@ ### Predicate, element offset and the return value must have the same vector ### width, which must be 1, 2, 4 or 8. ### - "svm_atomic_inc" : ["anyvector",["anyvector","anyint",0],"None"], - "svm_atomic_dec" : ["anyvector",["anyvector","anyint",0],"None"], + "svm_atomic_inc" : { "result" : "anyvector", "arguments" : ["anyvector","anyint",0], "attributes" : "None"}, + "svm_atomic_dec" : { "result" : "anyvector", "arguments" : ["anyvector","anyint",0], "attributes" : "None"}, ### ``llvm.genx.svm.atomic.cmpxchg...`` : vISA SVM_ATOMIC CMPXCHG instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2481,7 +2481,7 @@ ### Predicate, element offset, src0, src1, and the return value must all have ### the same vector width, which must be 1, 2, 4 or 8. ### - "svm_atomic_cmpxchg" : ["anyvector",["anyvector","anyint",0,0,0],"None"], + "svm_atomic_cmpxchg" : { "result" : "anyvector", "arguments" : ["anyvector","anyint",0,0,0], "attributes" : "None"}, ### ``llvm.genx.svm.atomic.*...`` : vISA SVM_ATOMIC with binary operator ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2498,8 +2498,8 @@ ### Predicate, element offset, src, and the return value must all have the ### same vector width, which must be 1, 2, 4, or 8. ### - "svm_atomic_fmin" : ["anyvector",["anyvector","anyint",0,0],"None"], - "svm_atomic_fmax" : ["anyvector",["anyvector","anyint",0,0],"None"], + "svm_atomic_fmin" : { "result" : "anyvector", "arguments" : ["anyvector","anyint",0,0], "attributes" : "None"}, + "svm_atomic_fmax" : { "result" : "anyvector", "arguments" : ["anyvector","anyint",0,0], "attributes" : "None"}, ### ``llvm.genx.svm.atomic.fcmpwr...`` : vISA SVM_ATOMIC FCMPWR instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2515,7 +2515,7 @@ ### Predicate, element offset, src0, src1, and the return value must all have ### the same vector width, which must be 1, 2, 4 or 8. ### - "svm_atomic_fcmpwr" : ["anyvector",["anyvector","anyint",0,0,0],"None"], + "svm_atomic_fcmpwr" : { "result" : "anyvector", "arguments" : ["anyvector","anyint",0,0,0], "attributes" : "None"}, ### ``llvm.genx.load..`` : vISA LOAD (sampler load) instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2542,7 +2542,7 @@ ### ### The element type of the return value must be i32 or float. ### - "load" : ["anyvector",["int","int","anyint",1,1],"ReadMem"], + "load" : { "result" : "anyvector", "arguments" : ["int","int","anyint",1,1], "attributes" : "ReadMem"}, ### ``llvm.genx.sample..`` : vISA SAMPLE instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2570,7 +2570,7 @@ ### ### The element type of the return value must be i32 or float. ### - "sample" : ["anyvector",["int","int","int","anyfloat",1,1],"ReadMem"], + "sample" : { "result" : "anyvector", "arguments" : ["int","int","int","anyfloat",1,1], "attributes" : "ReadMem"}, ### ``llvm.genx.sample..unorm`` : vISA SAMPLE_UNORM instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2590,7 +2590,7 @@ ### The number of 0 bits in that lower 4 bits of the channel mask arg is the ### number of channels to read per element. ### - "sample_unorm" : ["anyvector",["int","int","int","float","float","float","float"],"ReadMem"], + "sample_unorm" : { "result" : "anyvector", "arguments" : ["int","int","int","float","float","float","float"], "attributes" : "ReadMem"}, ### ``llvm.genx.3d.sample......`` : vISA 3D_SAMPLE instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2605,7 +2605,7 @@ ### ### * Return value: the data read ### - "3d_sample" : ["anyvector",["int","anyvector","int","short","int","int","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector"],"ReadMem"], + "3d_sample" : { "result" : "anyvector", "arguments" : ["int","anyvector","int","short","int","int","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector"], "attributes" : "ReadMem"}, ### ``llvm.genx.3d.load......`` : vISA 3D_LOAD instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2619,7 +2619,7 @@ ### ### * Return value: the data read ### - "3d_load" : ["anyvector",["int","anyvector","int","short","int","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector"],"ReadMem"], + "3d_load" : { "result" : "anyvector", "arguments" : ["int","anyvector","int","short","int","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector"], "attributes" : "ReadMem"}, ### ``llvm.genx.avs.`` : vISA AVS instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2647,44 +2647,44 @@ ### ### SIMD Control Flow: channel enable is ignored. ### - "avs" : ["anyvector",["int","int","int","float","float","float","float","float","int","int","int","float","int","char"],"ReadMem"], + "avs" : { "result" : "anyvector", "arguments" : ["int","int","int","float","float","float","float","float","int","int","int","float","int","char"], "attributes" : "ReadMem"}, ### ``llvm.genx.barrier`` : vISA BARRIER instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ### - "barrier" : ["void",[],"Convergent"], + "barrier" : { "result" : "void", "arguments" : [], "attributes" : "Convergent"}, ### ``llvm.genx.sbarrier`` : vISA SBARRIER instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ### ### * arg0: i8 signal flag, constant ### - "sbarrier" : ["void",["char"],"Convergent"], + "sbarrier" : { "result" : "void", "arguments" : ["char"], "attributes" : "Convergent"}, ### ``llvm.genx.cache.flush`` : vISA CACHE_FLUSH instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ### - "cache_flush" : ["void",[],"None"], + "cache_flush" : { "result" : "void", "arguments" : [], "attributes" : "None"}, ### ``llvm.genx.fence`` : vISA FENCE instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ### ### * arg0: i8 mask, constant ### - "fence" : ["void",["char"],"None"], + "fence" : { "result" : "void", "arguments" : ["char"], "attributes" : "None"}, ### ``llvm.genx.wait`` : vISA WAIT instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ### ### * arg0: i8 thread mask ### - "wait" : ["void",["char"],"None"], + "wait" : { "result" : "void", "arguments" : ["char"], "attributes" : "None"}, ### ``llvm.genx.yield`` : vISA YIELD instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ### - "yield" : ["void",[],"None"], + "yield" : { "result" : "void", "arguments" : [], "attributes" : "None"}, ### ``llvm.genx.raw.send...`` : vISA RAW_SEND instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2717,7 +2717,7 @@ ### predicatable. For a predicatable message, it must be a vector of i1 with ### width determining the execution size. ### - "raw_send" : ["anyvector",["int","anyint","int","int","anyvector",0],"None"], + "raw_send" : { "result" : "anyvector", "arguments" : ["int","anyint","int","int","anyvector",0], "attributes" : "None"}, ### ``llvm.genx.raw.send.noresult..`` : vISA RAW_SEND instruction with no result ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2739,7 +2739,7 @@ ### predicatable. For a predicatable message, it must be a vector of i1 with ### width determining the execution size. ### - "raw_send_noresult" : ["void",["int","anyint","int","int","anyvector"],"None"], + "raw_send_noresult" : { "result" : "void", "arguments" : ["int","anyint","int","int","anyvector"], "attributes" : "None"}, ### ``llvm.genx.raw.sends....`` : vISA RAW_SENDS instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2775,7 +2775,7 @@ ### predicatable. For a predicatable message, it must be a vector of i1 with ### width determining the execution size. ### - "raw_sends" : ["anyvector",["int","anyint","char","int","int","anyvector","anyvector",0],"None"], + "raw_sends" : { "result" : "anyvector", "arguments" : ["int","anyint","char","int","int","anyvector","anyvector",0], "attributes" : "None"}, ### ``llvm.genx.raw.sends.noresult...`` : vISA RAW_SENDS instruction with no result ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2801,7 +2801,7 @@ ### predicatable. For a predicatable message, it must be a vector of i1 with ### width determining the execution size. ### - "raw_sends_noresult" : ["void",["int","anyint","char","int","int","anyvector","anyvector"],"None"], + "raw_sends_noresult" : { "result" : "void", "arguments" : ["int","anyint","char","int","int","anyvector","anyvector"], "attributes" : "None"}, ### ``llvm.genx.raw.send2...`` : vISA RAW_SEND instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2822,7 +2822,7 @@ ### ### This intrinsic supports full encoding of the vISA raw_send instruction. ### - "raw_send2" : ["anyvector",["char","char","anyvector","char","char","char","int","int","anyvector",0],"None"], + "raw_send2" : { "result" : "anyvector", "arguments" : ["char","char","anyvector","char","char","char","int","int","anyvector",0], "attributes" : "None"}, ### ``llvm.genx.raw.send2.noresult..`` : vISA RAW_SEND instruction with no result ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2841,7 +2841,7 @@ ### ### This intrinsic supports full encoding of the vISA raw_send instruction with no result. ### - "raw_send2_noresult" : ["void",["char","char","anyvector","char","char","int","int","anyvector"],"None"], + "raw_send2_noresult" : { "result" : "void", "arguments" : ["char","char","anyvector","char","char","int","int","anyvector"], "attributes" : "None"}, ### ``llvm.genx.raw.sends2....`` : vISA RAW_SENDS instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2863,7 +2863,7 @@ ### ### This intrinsic supports full encoding of the vISA raw_sends instruction. ### - "raw_sends2" : ["anyvector",["char","char","anyvector","char","char","char","char","int","int","anyvector","anyvector",0],"None"], + "raw_sends2" : { "result" : "anyvector", "arguments" : ["char","char","anyvector","char","char","char","char","int","int","anyvector","anyvector",0], "attributes" : "None"}, ### ``llvm.genx.raw.sends2.noresult...`` : vISA RAW_SENDS instruction with no result ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2882,7 +2882,7 @@ ### ### This intrinsic supports full encoding of the vISA raw_sends instruction with no result. ### - "raw_sends2_noresult" : ["void",["char","char","anyvector","char","char","char","int","int","anyvector","anyvector"],"None"], + "raw_sends2_noresult" : { "result" : "void", "arguments" : ["char","char","anyvector","char","char","char","int","int","anyvector","anyvector"], "attributes" : "None"}, ## --------------------------- ### Video Analytics Instrinsics @@ -2899,7 +2899,7 @@ ### ### * Return value: v64i16 or v16i16 matrix, depending on properties value ### - "va_convolve2d" : ["anyint",["int","int","float","float","int"],"ReadMem"], + "va_convolve2d" : { "result" : "anyint", "arguments" : ["int","int","float","float","int"], "attributes" : "ReadMem"}, ### ``llvm.genx.va.hdc.convolve2d`` vISA VA HDC 2d Convolve instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2913,7 +2913,7 @@ ### * arg6: i16 destination surface x-offset ### * arg7: i16 destination surface y-offset ### - "va_hdc_convolve2d" : ["void",["int","int","float","float","int","int","short","short"],"None"], + "va_hdc_convolve2d" : { "result" : "void", "arguments" : ["int","int","float","float","int","int","short","short"], "attributes" : "None"}, ### ``llvm.genx.va.erode.`` vISA VA Erode instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2926,7 +2926,7 @@ ### ### * Return value: vXi32 ### - "va_erode" : ["anyint",["int","int","float","float","int"],"ReadMem"], + "va_erode" : { "result" : "anyint", "arguments" : ["int","int","float","float","int"], "attributes" : "ReadMem"}, ### ``llvm.genx.va.hdc.erode`` vISA VA HDC Erode instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2939,7 +2939,7 @@ ### * arg5: i16 destination surface x-offset ### * arg6: i16 destination surface y-offset ### - "va_hdc_erode" : ["void",["int","int","float","float","int","short","short"],"None"], + "va_hdc_erode" : { "result" : "void", "arguments" : ["int","int","float","float","int","short","short"], "attributes" : "None"}, ### ``llvm.genx.va.dilate.`` vISA VA Dilate instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2952,7 +2952,7 @@ ### ### * Return value: vXi32 ### - "va_dilate" : ["anyint",["int","int","float","float","int"],"ReadMem"], + "va_dilate" : { "result" : "anyint", "arguments" : ["int","int","float","float","int"], "attributes" : "ReadMem"}, ### ``llvm.genx.va.hdc.dilate`` vISA VA HDC Dilate instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2965,7 +2965,7 @@ ### * arg5: i16 destination surface x-offset ### * arg6: i16 destination surface y-offset ### - "va_hdc_dilate" : ["void",["int","int","float","float","int","short","short"],"None"], + "va_hdc_dilate" : { "result" : "void", "arguments" : ["int","int","float","float","int","short","short"], "attributes" : "None"}, ### ``llvm.genx.va.minmax.`` vISA MinMax instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2977,7 +2977,7 @@ ### ### * Return: v32i8 or v16i16 depending on the surface format ### - "va_minmax" : ["anyint",["int","float","float","int"],"ReadMem"], + "va_minmax" : { "result" : "anyint", "arguments" : ["int","float","float","int"], "attributes" : "ReadMem"}, ### ``llvm.genx.va.minmax.filter.`` vISA MinMax Filter instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2992,7 +2992,7 @@ ### ### * Return: vXi8 or vXi16 depending on return data size and format ### - "va_minmax_filter" : ["anyint",["int","int","float","float","int","int","int"],"ReadMem"], + "va_minmax_filter" : { "result" : "anyint", "arguments" : ["int","int","float","float","int","int","int"], "attributes" : "ReadMem"}, ### ``llvm.genx.va.hdc.minmax.filter`` vISA HDC MinMax Filter instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3007,7 +3007,7 @@ ### * arg7: i16 destination surface x-offset ### * arg8: i16 destination surface y-offset ### - "va_hdc_minmax_filter" : ["void",["int","int","float","float","int","int","int","short","short"],"None"], + "va_hdc_minmax_filter" : { "result" : "void", "arguments" : ["int","int","float","float","int","int","int","short","short"], "attributes" : "None"}, ### ``llvm.genx.va.bool.centroid.`` vISA Boolean Centroid instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3020,7 +3020,7 @@ ### ### * Return: v16i8 or v16i16 depending on surface format ### - "va_bool_centroid" : ["anyint",["int","float","float","char","char"],"ReadMem"], + "va_bool_centroid" : { "result" : "anyint", "arguments" : ["int","float","float","char","char"], "attributes" : "ReadMem"}, ### ``llvm.genx.va.centroid.`` vISA Centroid instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3032,7 +3032,7 @@ ### ### * Return: v32i32 ### - "va_centroid" : ["anyint",["int","float","float","char"],"ReadMem"], + "va_centroid" : { "result" : "anyint", "arguments" : ["int","float","float","char"], "attributes" : "ReadMem"}, ### ``llvm.genx.va.1d.convolve.horizontal.`` vISA 1d convolve horizontal instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3045,7 +3045,7 @@ ### ### * Return: v16i16 or v64i16 depending on mode ### - "va_1d_convolve_horizontal" : ["anyint",["int","int","float","float","int"],"ReadMem"], + "va_1d_convolve_horizontal" : { "result" : "anyint", "arguments" : ["int","int","float","float","int"], "attributes" : "ReadMem"}, ### ``llvm.genx.va.hdc.1d.convolve.horizontal`` vISA HDC 1d convolve horizontal instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3059,7 +3059,7 @@ ### * arg6: i16 destination surface x-offset ### * arg7: i16 destination surface y-offset ### - "va_hdc_1d_convolve_horizontal" : ["void",["int","int","float","float","int","int","short","short"],"None"], + "va_hdc_1d_convolve_horizontal" : { "result" : "void", "arguments" : ["int","int","float","float","int","int","short","short"], "attributes" : "None"}, ### ``llvm.genx.va.1d.convolve.vertical.`` vISA 1d convolve vertical instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3072,7 +3072,7 @@ ### ### * Return: v16i16 or v64i16 depending on mode ### - "va_1d_convolve_vertical" : ["anyint",["int","int","float","float","int"],"ReadMem"], + "va_1d_convolve_vertical" : { "result" : "anyint", "arguments" : ["int","int","float","float","int"], "attributes" : "ReadMem"}, ### ``llvm.genx.va.hdc.1d.convolve.vertical`` vISA HDC 1d convolve vertical instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3086,7 +3086,7 @@ ### * arg6: i16 destination surface x-offset ### * arg7: i16 destination surface y-offset ### - "va_hdc_1d_convolve_vertical" : ["void",["int","int","float","float","int","int","short","short"],"None"], + "va_hdc_1d_convolve_vertical" : { "result" : "void", "arguments" : ["int","int","float","float","int","int","short","short"], "attributes" : "None"}, ### ``llvm.genx.va.1pixel.convolve..`` vISA 1 Pixel Convolve instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3100,7 +3100,7 @@ ### ### * Return: v64i16 or v16i16 depending on mode. ### - "va_1pixel_convolve" : ["anyint",["int","int","float","float","int","anyint"],"ReadMem"], + "va_1pixel_convolve" : { "result" : "anyint", "arguments" : ["int","int","float","float","int","anyint"], "attributes" : "ReadMem"}, ### ``llvm.genx.va.hdc.1pixel.convolve`` vISA HDC 1 Pixel Convolve instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3115,7 +3115,7 @@ ### * arg7: i16 destination surface x-offset ### * arg8: i16 destination surface y-offset ### - "va_hdc_1pixel_convolve" : ["void",["int","int","float","float","int","anyint","int","short","short"],"None"], + "va_hdc_1pixel_convolve" : { "result" : "void", "arguments" : ["int","int","float","float","int","anyint","int","short","short"], "attributes" : "None"}, ### ``llvm.genx.va.1pixel.convolve.1x1mode.`` vISA 1 Pixel Convolve (1x1 mode) instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3127,7 +3127,7 @@ ### ### * Return: v64i16 or v16i16 depending on mode. ### - "va_1pixel_convolve_1x1mode" : ["anyint",["int","int","float","float"],"ReadMem"], + "va_1pixel_convolve_1x1mode" : { "result" : "anyint", "arguments" : ["int","int","float","float"], "attributes" : "ReadMem"}, ### ``llvm.genx.va.lbp.creation.`` vISA LBP Creation instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3139,7 +3139,7 @@ ### ### * Return: v64i8 or v128i8 depending on mode ### - "va_lbp_creation" : ["anyint",["int","float","float","int"],"ReadMem"], + "va_lbp_creation" : { "result" : "anyint", "arguments" : ["int","float","float","int"], "attributes" : "ReadMem"}, ### ``llvm.genx.va.hdc.lbp.creation`` vISA HDC LBP Creation instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3152,7 +3152,7 @@ ### * arg5: i16 destination surface x-offset ### * arg6: i16 destination surface y-offset ### - "va_hdc_lbp_creation" : ["void",["int","float","float","int","int","short","short"],"None"], + "va_hdc_lbp_creation" : { "result" : "void", "arguments" : ["int","float","float","int","int","short","short"], "attributes" : "None"}, ### ``llvm.genx.va.lbp.correlation.`` vISA LBP Correlation instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3164,7 +3164,7 @@ ### ### * Return: v64i8 ### - "va_lbp_correlation" : ["anyint",["int","float","float","short"],"ReadMem"], + "va_lbp_correlation" : { "result" : "anyint", "arguments" : ["int","float","float","short"], "attributes" : "ReadMem"}, ### ``llvm.genx.va.hdc.lbp.correlation`` vISA HDC LBP Correlation instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3177,7 +3177,7 @@ ### * arg5: i16 destination surface x-offset ### * arg6: i16 destination surface y-offset ### - "va_hdc_lbp_correlation" : ["void",["int","float","float","short","int","short","short"],"None"], + "va_hdc_lbp_correlation" : { "result" : "void", "arguments" : ["int","float","float","short","int","short","short"], "attributes" : "None"}, ### ``llvm.genx.va.correlation.search.`` vISA Correlation Search instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3194,7 +3194,7 @@ ### ### * Return: vXi32 ### - "va_correlation_search" : ["anyint",["int","float","float","float","float","char","char","char","char"],"ReadMem"], + "va_correlation_search" : { "result" : "anyint", "arguments" : ["int","float","float","float","float","char","char","char","char"], "attributes" : "ReadMem"}, ### ``llvm.genx.va.flood.fill..`` vISA Flood Fill instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3207,7 +3207,7 @@ ### ### * Return: v8i16 ### - "va_flood_fill" : ["anyint",["char","anyint","short","short","short"],"ReadMem"], + "va_flood_fill" : { "result" : "anyint", "arguments" : ["char","anyint","short","short","short"], "attributes" : "ReadMem"}, ##-------------------------------------------------------------------- ### CM codegen internal intrinsics @@ -3225,7 +3225,7 @@ ### reduction functions (cm_sum etc) whose behavior is sensitive to the ### surrounding SIMD CF context. It is lowered by the CMSimdCFLowering pass. ### - "simdcf_predicate" : ["anyvector",[0,0],"None"], + "simdcf_predicate" : { "result" : "anyvector", "arguments" : [0,0], "attributes" : "None"}, ### llvm.genx.simdcf.any. : simd cf marker intrinsic. ### @@ -3239,7 +3239,7 @@ ### This is generated by clang codegen in the implementation of SIMD control ### flow, and lowered by the CMSimdCFLowering pass. ### - "simdcf_any" : ["bool",["anyvector"],"None"], + "simdcf_any" : { "result" : "bool", "arguments" : ["anyvector"], "attributes" : "None"}, ### ``llvm.genx.unmask.begin`` : simd-unmask region begin ### @@ -3250,7 +3250,7 @@ ### the old mask in a temp. ### this intrinsic will be replaced by genx.simdcf.unmask by SimdCFLowering ### - "unmask_begin" : ["int",[],"WriteMem,SideEffects"], + "unmask_begin" : { "result" : "int", "arguments" : [], "attributes" : "WriteMem,SideEffects"}, ### ``llvm.genx.unmask.end`` : simd-unmask region end ### @@ -3261,7 +3261,7 @@ ### region, set execution mask back using the temp value from unmask-begin. ### this intrinsic will be replaced by genx.simdcf.remask by SimdCFLowering ### - "unmask_end" : ["void",["int"],"WriteMem,SideEffects"], + "unmask_end" : { "result" : "void", "arguments" : ["int"], "attributes" : "WriteMem,SideEffects"}, ### ``llvm.genx.lane.id`` : implicit lane-id in the simd-fork statement ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3269,7 +3269,7 @@ ### ### * Return value: i32 ### - "lane_id" : ["int",[],"NoMem"], + "lane_id" : { "result" : "int", "arguments" : [], "attributes" : "NoMem"}, ### ``llvm.genx.local.*.`` : read local ID register ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3282,9 +3282,9 @@ ### ### This is generated by clang codegen and lowered by CMImpParam. ### - "local_id" : ["anyvector",[],"NoMem"], - "local_id16" : ["anyvector",[],"NoMem"], - "local_size" : ["anyvector",[],"NoMem"], + "local_id" : { "result" : "anyvector", "arguments" : [], "attributes" : "NoMem"}, + "local_id16" : { "result" : "anyvector", "arguments" : [], "attributes" : "NoMem"}, + "local_size" : { "result" : "anyvector", "arguments" : [], "attributes" : "NoMem"}, ### ``llvm.genx.group.or.local.size`` : read local or group size register ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3296,7 +3296,7 @@ ### This is generated by CMImpParam. This is to match OpenCL thread ### payload layout. ### - "group_or_local_size" : ["int8",[],"NoMem"], + "group_or_local_size" : { "result" : "int8", "arguments" : [], "attributes" : "NoMem"}, ### ``llvm.genx.local.id.*`` : read local ID register ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3309,9 +3309,9 @@ ### This is generated by CMImpParam. This is to match OpenCL thread ### payload layout. ### - "local_id_x" : ["short8",[],"NoMem"], - "local_id_y" : ["short8",[],"NoMem"], - "local_id_z" : ["short8",[],"NoMem"], + "local_id_x" : { "result" : "short8", "arguments" : [], "attributes" : "NoMem"}, + "local_id_y" : { "result" : "short8", "arguments" : [], "attributes" : "NoMem"}, + "local_id_z" : { "result" : "short8", "arguments" : [], "attributes" : "NoMem"}, ### ``llvm.genx.group.count.`` : read group count register ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3321,7 +3321,7 @@ ### ### This is generated by clang codegen and lowered by CMImpParam. ### - "group_count" : ["anyvector",[],"NoMem"], + "group_count" : { "result" : "anyvector", "arguments" : [], "attributes" : "NoMem"}, ### ``llvm.genx.get.scoreboard.bti`` : get scoreboard surface implicit ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3330,7 +3330,7 @@ ### ###This is generated by clang codegen and lowered by CMImpParam. ### - "get_scoreboard_bti" : ["int",[],"NoMem"], + "get_scoreboard_bti" : { "result" : "int", "arguments" : [], "attributes" : "NoMem"}, ### ``llvm.genx.get.scoreboard.deltas`` : get scoreboard deltas ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3339,7 +3339,7 @@ ### ### This is generated by clang codegen and lowered by CMImpParam. ### - "get_scoreboard_deltas" : ["char16",[],"NoMem"], + "get_scoreboard_deltas" : { "result" : "char16", "arguments" : [], "attributes" : "NoMem"}, ### ``llvm.genx.get.scoreboard.depcnt`` : get the maximal scoreboard dependency count ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3348,7 +3348,7 @@ ### ### This is generated by clang codegen and lowered by CMImpParam. ### - "get_scoreboard_depcnt" : ["int",[],"NoMem"], + "get_scoreboard_depcnt" : { "result" : "int", "arguments" : [], "attributes" : "NoMem"}, ### ``llvm.genx.predefined.surface`` : get predefined surface ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3357,7 +3357,7 @@ ### ### This is generated by clang codegen when predefined surface is accessed. ### - "predefined_surface" : ["int",["int"],"NoMem"], + "predefined_surface" : { "result" : "int", "arguments" : ["int"], "attributes" : "NoMem"}, ##-------------------------------------------------------------------- ### GenX backend internal intrinsics @@ -3379,8 +3379,8 @@ ### There are two variants simply because there is no way of saying here ### that an argument can have any scalar or vector type. ### - "constanti" : ["anyint",[0],"NoMem"], - "constantf" : ["anyfloat",[0],"NoMem"], + "constanti" : { "result" : "anyint", "arguments" : [0], "attributes" : "NoMem"}, + "constantf" : { "result" : "anyfloat", "arguments" : [0], "attributes" : "NoMem"}, ### llvm.genx.convert. : convert register category (non address) ### @@ -3398,7 +3398,7 @@ ### of a value of category other than general. Thus the input and output ### might be both the same category, but not both general. ### - "convert" : ["anyint",[0],"NoMem"], + "convert" : { "result" : "anyint", "arguments" : [0], "attributes" : "NoMem"}, ### llvm.genx.convert.addr. : convert to address register category ### @@ -3414,7 +3414,7 @@ ### stop the address conversion falling outside of the register into which it ### points to avoid going out of spec (bug 4395). ### - "convert_addr" : ["anyint",[0,"short"],"NoMem"], + "convert_addr" : { "result" : "anyint", "arguments" : [0,"short"], "attributes" : "NoMem"}, ### llvm.genx.constantpred. : load constant predicate (i1 or vector of i1) ### @@ -3426,7 +3426,7 @@ ### We could just use a bitcast, except that EarlyCSE follows ### GenXConstantMaterialization and it has a habit of putting the constant ### back in the wrregion. - "constantpred" : ["anyint",[0],"NoMem"], + "constantpred" : { "result" : "anyint", "arguments" : [0], "attributes" : "NoMem"}, ### llvm.genx.add.addr.. : add an offset onto an address register ### @@ -3439,7 +3439,7 @@ ### a region access, GenXCategoryConversion converts it into this intrinsic ### so that it will be considered an add to an address register. ### - "add_addr" : ["anyint",["anyint",0],"NoMem"], + "add_addr" : { "result" : "anyint", "arguments" : ["anyint",0], "attributes" : "NoMem"}, ### llvm.genx.rdpredregion.. : read region at specified offset from a predicate ### @@ -3452,7 +3452,7 @@ ### in the return type, and must be 4, 8 or 16. ### The offset must be a multiple of the number of elements. ### - "rdpredregion" : ["anyint",["anyint","int"],"NoMem"], + "rdpredregion" : { "result" : "anyint", "arguments" : ["anyint","int"], "attributes" : "NoMem"}, ### llvm.genx.wrpredregion.. : write region at specified offset into a predicate ### @@ -3466,7 +3466,7 @@ ### in the "subvector to write" arg, and must be 4, 8 or 16. ### The offset must be a multiple of the number of elements. ### - "wrpredregion" : ["anyint",[0,"anyint","int"],"NoMem"], + "wrpredregion" : { "result" : "anyint", "arguments" : [0,"anyint","int"], "attributes" : "NoMem"}, ### llvm.genx.wrpredpredregion.. : predicated write region at specified offset ### into a predicate @@ -3486,7 +3486,7 @@ ### intrinsic is valid only if the predicate is an EM value, and the subvector ### operand is the result of a cmp (which is then baled in). ### - "wrpredpredregion" : ["anyint",[0,"anyint","int",0],"NoMem"], + "wrpredpredregion" : { "result" : "anyint", "arguments" : [0,"anyint","int",0], "attributes" : "NoMem"}, ### ``llvm.genx.wrconstregion....`` : write a constant region ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3515,7 +3515,7 @@ ### The operands are the same as llvm.genx.wrregion so it can mostly be handled ### by the same code as llvm.genx.wrregion. ### - "wrconstregion" : ["anyvector",[0,"anyvector","int","int","int","anyint","int","anyint"],"NoMem"], + "wrconstregion" : { "result" : "anyvector", "arguments" : [0,"anyvector","int","int","int","anyint","int","anyint"], "attributes" : "NoMem"}, ### ``llvm.genx.output`` : Mark output arguments ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3526,7 +3526,7 @@ ### This intrinsic call only extends the live range of marked arguments and ### emits no code. ### - "output" : ["void",["vararg"],"None"], + "output" : { "result" : "void", "arguments" : ["vararg"], "attributes" : "None"}, ### ``llvm.genx.output.1.`` : Mark output argument ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3539,7 +3539,7 @@ ### This intrinsic call only extends the live range of marked argument and ### emits no code. ### - "output_1" : ["void",["any"],"None"], + "output_1" : { "result" : "void", "arguments" : ["any"], "attributes" : "None"}, ## ``llvm.genx.print.buffer`` : read stateless pointer to print buffer ## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3549,7 +3549,7 @@ ## ## this is generated by clang codegen and lowered by cmimpparam. ## - "print_buffer" : ["long",[],"None"], + "print_buffer" : { "result" : "long", "arguments" : [], "attributes" : "None"}, ## ``llvm.genx.print.format.index`` : add printf format string to collection ## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3559,7 +3559,7 @@ ## ## * Return value: the vector value read ## - "print_format_index" : ["int",["anyptr"],"NoMem"], + "print_format_index" : { "result" : "int", "arguments" : ["anyptr"], "attributes" : "NoMem"}, ## ``llvm.genx.address.convert`` : convert dataport address to integer ## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3573,7 +3573,7 @@ ## used across all memory instructions. This is needed to encode ## SPIRV with appropriate types for kernel arguments. ## - "address_convert" : ["anyint",["anyptr"],"NoMem"], + "address_convert" : { "result" : "anyint", "arguments" : ["anyptr"], "attributes" : "NoMem"}, ## ``llvm.genx.gaddr`` : take an address of a global variable ## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3585,7 +3585,7 @@ ## ## * Return value: i64/i32 (depending on data layout) value of pointer ## - "gaddr" : ["anyint", ["anyptr"], "NoMem"], + "gaddr" : { "result" : "anyint", "arguments" : ["anyptr"], "attributes" : "NoMem"}, ## ``llvm.genx.jump.table`` : CMC internal, no VISA ## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3599,5 +3599,5 @@ ## will be used by visa switchjmp as index. Return value and arg1-N are ## used to make ir semantically legal. ## - "jump_table" : ["anyptr", ["anyint", "vararg"], "NoMem"] + "jump_table" : { "result" : "anyptr", "arguments" : ["anyint", "vararg"], "attributes" : "NoMem"} } diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py index 94cbd7dc..a1c3417c 100755 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py @@ -298,16 +298,17 @@ def createOverloadTable(): f.write(",\n 0") isOverloadable = False genISA_Intrinsic = Intrinsics[ID_array[i]] - for j in range(3): - if isinstance(genISA_Intrinsic[j],list): - for z in range(len(genISA_Intrinsic[j])): - if isinstance(genISA_Intrinsic[j][z],int): + for key in genISA_Intrinsic: + val = genISA_Intrinsic[key] + if isinstance(val,list): + for z in range(len(val)): + if isinstance(val[z],int): continue - elif "any" in genISA_Intrinsic[j][z]: + elif "any" in val[z]: isOverloadable = True break else: - if "any" in genISA_Intrinsic[j]: + if "any" in val: isOverloadable = True break if isOverloadable: @@ -329,11 +330,12 @@ def createOverloadRetTable(): for i in range(len(ID_array)): genISA_Intrinsic = Intrinsics[ID_array[i]] isOverloadable = False - if "any" in genISA_Intrinsic[0]: + ret = genISA_Intrinsic["result"] + if "any" in ret: isOverloadable = True - elif isinstance(genISA_Intrinsic[0], list): - for j in range(len(genISA_Intrinsic[0])): - if "any" in genISA_Intrinsic[0][j]: + elif isinstance(ret, list): + for j in range(len(ret)): + if "any" in ret[j]: isOverloadable = True if isOverloadable: f.write("case GenXIntrinsic::genx_" + ID_array[i] + ":\n") @@ -353,15 +355,16 @@ def createOverloadArgsTable(): f.write("case GenXIntrinsic::genx_" + ID_array[i]+": ") argNums = [] genISA_Intrinsic = Intrinsics[ID_array[i]] - if isinstance(genISA_Intrinsic[1],list): - for z in range(len(genISA_Intrinsic[1])): - if isinstance(genISA_Intrinsic[1][z],int): + args = genISA_Intrinsic["arguments"] + if isinstance(args,list): + for z in range(len(args)): + if isinstance(args[z],int): continue - elif "any" in genISA_Intrinsic[1][z]: + elif "any" in args[z]: argNums.append(z) else: - if "any" in genISA_Intrinsic[1]: - append.append(0) + if "any" in args: + argNums.append(0) if not argNums: f.write("\n return false;\n") else: @@ -429,8 +432,8 @@ def createTypeTable(): # For the first part we will create the basic type table for i in range(len(ID_array)): genISA_Intrinsic = Intrinsics[ID_array[i]] # This is our array of types - dest = genISA_Intrinsic[0] - source_list = genISA_Intrinsic[1] + dest = genISA_Intrinsic['result'] + source_list = genISA_Intrinsic['arguments'] anyArgs_array = [] type_string = str() @@ -508,7 +511,7 @@ def createAttributeTable(): attribute_Array = [] for i in range(len(ID_array)): found = False - intrinsic_attribute = Intrinsics[ID_array[i]][2] #This is the location of that attribute + intrinsic_attribute = Intrinsics[ID_array[i]]['attributes'] #This is the location of that attribute for j in range(len(attribute_Array)): if intrinsic_attribute == attribute_Array[j]: found = True From 475fb7fb0054548758e3e306ad6deaa6177a9e05 Mon Sep 17 00:00:00 2001 From: y Date: Thu, 17 Jun 2021 11:15:54 +0000 Subject: [PATCH 15/81] made intrinsics definitions multilined --- .../GenXIntrinsics/Intrinsic_definitions.py | 1655 +++++++++++++---- 1 file changed, 1324 insertions(+), 331 deletions(-) diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py index f0bc441d..6aae3169 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py @@ -58,8 +58,14 @@ ##-------------------------------------------------------------------- ## Start and end markers of the genx intrinsic enum values. This relies on ## tablegen outputting the intrinsics in sorted by name order. - "aaaabegin" : { "result" : "anyvector", "arguments" : [], "attributes" : "None"}, - "zzzzend" : { "result" : "anyvector", "arguments" : [], "attributes" : "None"}, + "aaaabegin" : { "result" : "anyvector", + "arguments" : [], + "attributes" : "None" + }, + "zzzzend" : { "result" : "anyvector", + "arguments" : [], + "attributes" : "None" + }, ### ``llvm.genx.alloca.`` : CMC internal, no VISA ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -70,7 +76,10 @@ ### ### * Return value: offset in stack surface ### - "alloca" : { "result" : "anyint", "arguments" : ["any"], "attributes" : "None"}, + "alloca" : { "result" : "anyint", + "arguments" : ["any"], + "attributes" : "None" + }, ### ``llvm.genx.faddr.`` : take an address of the function provided ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -82,7 +91,10 @@ ### ### * Return value: i64 address ready to be consumed by an indirect call ### - "faddr" : { "result" : "long", "arguments" : ["any"], "attributes" : "NoMem"}, + "faddr" : { "result" : "long", + "arguments" : ["any"], + "attributes" : "NoMem" + }, ## -------------------------------- ### Region/element access intrinsics @@ -128,8 +140,14 @@ ### cross a multiple of parent width boundary. This is used by the backend ### to determine whether the region can be collapsed into another region. ### - "rdregioni" : { "result" : "anyint", "arguments" : ["anyvector","int","int","int","anyint","int"], "attributes" : "NoMem"}, - "rdregionf" : { "result" : "anyfloat", "arguments" : ["anyvector","int","int","int","anyint","int"], "attributes" : "NoMem"}, + "rdregioni" : { "result" : "anyint", + "arguments" : ["anyvector","int","int","int","anyint","int"], + "attributes" : "NoMem" + }, + "rdregionf" : { "result" : "anyfloat", + "arguments" : ["anyvector","int","int","int","anyint","int"], + "attributes" : "NoMem" + }, ### ``llvm.genx.wrregion*`` : write a region, direct or single-indirect ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -185,8 +203,14 @@ ### cross a multiple of parent width boundary. This is used by the backend ### to determine whether the region can be collapsed into another region. ### - "wrregioni" : { "result" : "anyvector", "arguments" : [0,"anyint","int","int","int","anyint","int","anyint"], "attributes" : "NoMem"}, - "wrregionf" : { "result" : "anyvector", "arguments" : [0,"anyfloat","int","int","int","anyint","int","anyint"], "attributes" : "NoMem"}, + "wrregioni" : { "result" : "anyvector", + "arguments" : [0,"anyint","int","int","int","anyint","int","anyint"], + "attributes" : "NoMem" + }, + "wrregionf" : { "result" : "anyvector", + "arguments" : [0,"anyfloat","int","int","int","anyint","int","anyint"], + "attributes" : "NoMem" + }, ### ``llvm.genx.vstore..`` : store a vector value into memory ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -199,7 +223,10 @@ ### * arg0: the vector to read from ### * arg1: the memory to be accessed ### - "vstore" : { "result" : "void", "arguments" : ["anyvector","anyptr"], "attributes" : "None"}, + "vstore" : { "result" : "void", + "arguments" : ["anyvector","anyptr"], + "attributes" : "None" + }, ### ``llvm.genx.vload..`` : load a vector value from memory ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -212,7 +239,10 @@ ### * arg0: the memory to be accessed (overloaded) ### * Return value: the vector value read ### - "vload" : { "result" : "anyvector", "arguments" : ["anyptr"], "attributes" : "None"}, + "vload" : { "result" : "anyvector", + "arguments" : ["anyptr"], + "attributes" : "None" + }, ## ------------------------------ ### ALU type conversion intrinsics @@ -226,7 +256,10 @@ ### * Return value: converted value, any scalar or vector integer type ### (treated as signed) with same vector width as arg0 ### - "fptosi_sat" : { "result" : "anyint", "arguments" : ["anyfloat"], "attributes" : "NoMem"}, + "fptosi_sat" : { "result" : "anyint", + "arguments" : ["anyfloat"], + "attributes" : "NoMem" + }, ### ``llvm.genx.fptoui.sat..`` : convert floating point to unsigned integer with saturate ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -236,7 +269,10 @@ ### * Return value: converted value, any scalar or vector integer type ### (treated as unsigned) with same vector width as arg0 ### - "fptoui_sat" : { "result" : "anyint", "arguments" : ["anyfloat"], "attributes" : "NoMem"}, + "fptoui_sat" : { "result" : "anyint", + "arguments" : ["anyfloat"], + "attributes" : "NoMem" + }, ### ``llvm.genx.sat..`` : floating point saturate ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -254,7 +290,10 @@ ### Instead, any integer operation that supports saturation needs an ### intrinsic for the saturating variant. ### - "sat" : { "result" : "anyfloat", "arguments" : [0], "attributes" : "NoMem"}, + "sat" : { "result" : "anyfloat", + "arguments" : [0], + "attributes" : "NoMem" + }, ### ``llvm.genx.*trunc.sat..`` : integer truncation with saturation ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -268,10 +307,22 @@ ### * Return value: truncated value, any scalar or vector integer type ### with same vector width as arg0 ### - "sstrunc_sat" : { "result" : "anyint", "arguments" : ["anyint"], "attributes" : "NoMem"}, - "sutrunc_sat" : { "result" : "anyint", "arguments" : ["anyint"], "attributes" : "NoMem"}, - "ustrunc_sat" : { "result" : "anyint", "arguments" : ["anyint"], "attributes" : "NoMem"}, - "uutrunc_sat" : { "result" : "anyint", "arguments" : ["anyint"], "attributes" : "NoMem"}, + "sstrunc_sat" : { "result" : "anyint", + "arguments" : ["anyint"], + "attributes" : "NoMem" + }, + "sutrunc_sat" : { "result" : "anyint", + "arguments" : ["anyint"], + "attributes" : "NoMem" + }, + "ustrunc_sat" : { "result" : "anyint", + "arguments" : ["anyint"], + "attributes" : "NoMem" + }, + "uutrunc_sat" : { "result" : "anyint", + "arguments" : ["anyint"], + "attributes" : "NoMem" + }, ## ------------------- ### Modifier intrinsics @@ -289,8 +340,14 @@ ### ### * Return value: result, same type ### - "absf" : { "result" : "anyfloat", "arguments" : [0], "attributes" : "NoMem"}, - "absi" : { "result" : "anyint", "arguments" : [0], "attributes" : "NoMem"}, + "absf" : { "result" : "anyfloat", + "arguments" : [0], + "attributes" : "NoMem" + }, + "absi" : { "result" : "anyint", + "arguments" : [0], + "attributes" : "NoMem" + }, ## ---------------------------- ### Boolean reduction intrinsics @@ -303,7 +360,10 @@ ### ### * Return value: i1 result ### - "all" : { "result" : "bool", "arguments" : ["anyint"], "attributes" : "NoMem"}, + "all" : { "result" : "bool", + "arguments" : ["anyint"], + "attributes" : "NoMem" + }, ### ``llvm.genx.any.`` : true if any input element is true ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -312,7 +372,10 @@ ### ### * Return value: i1 result ### - "any" : { "result" : "bool", "arguments" : ["anyint"], "attributes" : "NoMem"}, + "any" : { "result" : "bool", + "arguments" : ["anyint"], + "attributes" : "NoMem" + }, ## ---------------------------- ### SIMD control flow intrinsics @@ -492,7 +555,10 @@ ### Note that SimdCond has the same sense as in the Gen goto instruction, but ### the opposite sense to that in a vISA forward goto instruction. ### - "simdcf_goto" : { "result" : ["anyvector","anyvector","bool"], "arguments" : [0,1,1], "attributes" : "NoMem"}, + "simdcf_goto" : { "result" : ["anyvector","anyvector","bool"], + "arguments" : [0,1,1], + "attributes" : "NoMem" + }, ### ``llvm.genx.simdcf.join..`` : join instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -535,14 +601,20 @@ ### still disabled, then BranchCond is true and the conditional branch in which it ### is used branches to the next join point in sequence. ### - "simdcf_join" : { "result" : ["anyvector","bool"], "arguments" : [0,"anyvector"], "attributes" : "None"}, + "simdcf_join" : { "result" : ["anyvector","bool"], + "arguments" : [0,"anyvector"], + "attributes" : "None" + }, ### ``llvm.genx.simdcf.savemask.`` : ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ### ### * arg0: OldEM (old execution mask): v32i1 (overloaded) ### * ret: temp i32 for saving the oldEM - "simdcf_savemask" : { "result" : "int", "arguments" : ["anyvector"], "attributes" : "WriteMem,SideEffects"}, + "simdcf_savemask" : { "result" : "int", + "arguments" : ["anyvector"], + "attributes" : "WriteMem,SideEffects" + }, ### ``llvm.genx.simdcf.unmask.`` : ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -550,7 +622,10 @@ ### * arg0: temp i32 from savemask ### * arg1: i32 constant, should be all-one ### * ret: NewEM (updated execution mask, all-one): v32i1 - "simdcf_unmask" : { "result" : "anyvector", "arguments" : ["int","int"], "attributes" : "WriteMem,SideEffects"}, + "simdcf_unmask" : { "result" : "anyvector", + "arguments" : ["int","int"], + "attributes" : "WriteMem,SideEffects" + }, ### ``llvm.genx.simdcf.remask.`` : ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -560,7 +635,10 @@ ### ### Return value: NewEM (updated execution mask): v32i1 ### - "simdcf_remask" : { "result" : "anyvector", "arguments" : [0,"int"], "attributes" : "WriteMem,SideEffects"}, + "simdcf_remask" : { "result" : "anyvector", + "arguments" : [0,"int"], + "attributes" : "WriteMem,SideEffects" + }, ### ``llvm.genx.simdcf.get.em`` : ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -578,7 +656,10 @@ ### EM is different in different locations even when the ### dominance of DF is not corrupted. ### - "simdcf_get_em" : { "result" : "anyvector", "arguments" : [0], "attributes" : "WriteMem,SideEffects"}, + "simdcf_get_em" : { "result" : "anyvector", + "arguments" : [0], + "attributes" : "WriteMem,SideEffects" + }, ### -------------- ### ALU intrinsics @@ -607,10 +688,22 @@ ### For an fp add, use the LLVM IR FAdd instruction, followed by ### llvm.genx.sat if saturation is required. ### - "ssadd_sat" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, - "suadd_sat" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, - "usadd_sat" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, - "uuadd_sat" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, + "ssadd_sat" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "suadd_sat" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "usadd_sat" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "uuadd_sat" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, ### asr ### ^^^ @@ -632,10 +725,22 @@ ### * Return value: result, any scalar/vector integer type (not i64) ### with same vector width ### - "ssavg" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, - "suavg" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, - "usavg" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, - "uuavg" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, + "ssavg" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "suavg" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "usavg" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "uuavg" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, ### ``llvm.genx.*avg.sat..`` : integer averaging with saturation ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -650,10 +755,22 @@ ### * Return value: result, any scalar/vector integer type (not i64) ### with same vector width ### - "ssavg_sat" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, - "suavg_sat" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, - "usavg_sat" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, - "uuavg_sat" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, + "ssavg_sat" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "suavg_sat" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "usavg_sat" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "uuavg_sat" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, ### ``llvm.genx.*bfe.`` : bitfield extract ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -666,8 +783,14 @@ ### ### * Return value: result, same type as arg0 ### - "sbfe" : { "result" : "anyint", "arguments" : [0,0,0], "attributes" : "NoMem"}, - "ubfe" : { "result" : "anyint", "arguments" : [0,0,0], "attributes" : "NoMem"}, + "sbfe" : { "result" : "anyint", + "arguments" : [0,0,0], + "attributes" : "NoMem" + }, + "ubfe" : { "result" : "anyint", + "arguments" : [0,0,0], + "attributes" : "NoMem" + }, ### ``llvm.genx.bfi.`` : bitfield insert ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -679,7 +802,10 @@ ### ### * Return value: result, same type as arg0 ### - "bfi" : { "result" : "anyint", "arguments" : [0,0,0,0], "attributes" : "NoMem"}, + "bfi" : { "result" : "anyint", + "arguments" : [0,0,0,0], + "attributes" : "NoMem" + }, ### ``llvm.genx.bfrev.`` : reverse bits ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -688,7 +814,10 @@ ### ### * Return value: result, same type as arg0 ### - "bfrev" : { "result" : "anyint", "arguments" : [0], "attributes" : "NoMem"}, + "bfrev" : { "result" : "anyint", + "arguments" : [0], + "attributes" : "NoMem" + }, ### ``llvm.genx.cbit..`` : count set bits ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -697,7 +826,10 @@ ### ### * Return value: result, int32 of same width as arg0 ### - "cbit" : { "result" : "anyint", "arguments" : ["anyint"], "attributes" : "NoMem"}, + "cbit" : { "result" : "anyint", + "arguments" : ["anyint"], + "attributes" : "NoMem" + }, ### cmp ### ^^^ @@ -712,7 +844,10 @@ ### ### * Return value: result, same type ### - "cos" : { "result" : "anyfloat", "arguments" : [0], "attributes" : "NoMem"}, + "cos" : { "result" : "anyfloat", + "arguments" : [0], + "attributes" : "NoMem" + }, ### div ### ^^^ @@ -728,7 +863,10 @@ ### ### * Return value: result, same type ### - "ieee_div" : { "result" : "anyfloat", "arguments" : [0,0], "attributes" : "NoMem"}, + "ieee_div" : { "result" : "anyfloat", + "arguments" : [0,0], + "attributes" : "NoMem" + }, ### ``llvm.genx.dp2.`` : dp2 instruction (dot product on groups of 4 elements) ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -738,7 +876,10 @@ ### ### * Return value: result, same type ### - "dp2" : { "result" : "anyfloat", "arguments" : [0,0], "attributes" : "NoMem"}, + "dp2" : { "result" : "anyfloat", + "arguments" : [0,0], + "attributes" : "NoMem" + }, ### ``llvm.genx.dp3.`` : dp3 instruction (dot product on groups of 3 elements) ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -748,7 +889,10 @@ ### ### * Return value: result, same type ### - "dp3" : { "result" : "anyfloat", "arguments" : [0,0], "attributes" : "NoMem"}, + "dp3" : { "result" : "anyfloat", + "arguments" : [0,0], + "attributes" : "NoMem" + }, ### ``llvm.genx.dp4.`` : dp4 instruction (dot product on groups of 4 elements) ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -758,7 +902,10 @@ ### ### * Return value: result, same type ### - "dp4" : { "result" : "anyfloat", "arguments" : [0,0], "attributes" : "NoMem"}, + "dp4" : { "result" : "anyfloat", + "arguments" : [0,0], + "attributes" : "NoMem" + }, ### ``llvm.genx.dph.`` : dph instruction (dot product homogenous) ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -768,7 +915,10 @@ ### ### * Return value: result, same type ### - "dph" : { "result" : "anyfloat", "arguments" : [0,0], "attributes" : "NoMem"}, + "dph" : { "result" : "anyfloat", + "arguments" : [0,0], + "attributes" : "NoMem" + }, ### ``llvm.genx.exp.`` : base 2 exponent ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -777,7 +927,10 @@ ### ### * Return value: result, same type ### - "exp" : { "result" : "anyfloat", "arguments" : [0], "attributes" : "NoMem"}, + "exp" : { "result" : "anyfloat", + "arguments" : [0], + "attributes" : "NoMem" + }, ### ``llvm.genx.*fbh.`` : find bit high ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -788,8 +941,14 @@ ### ### * Return value: result, same type ### - "sfbh" : { "result" : "anyint", "arguments" : [0], "attributes" : "NoMem"}, - "ufbh" : { "result" : "anyint", "arguments" : [0], "attributes" : "NoMem"}, + "sfbh" : { "result" : "anyint", + "arguments" : [0], + "attributes" : "NoMem" + }, + "ufbh" : { "result" : "anyint", + "arguments" : [0], + "attributes" : "NoMem" + }, ### ``llvm.genx.fbl.`` : find bit low ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -798,7 +957,10 @@ ### ### * Return value: result, same type ### - "fbl" : { "result" : "anyint", "arguments" : [0], "attributes" : "NoMem"}, + "fbl" : { "result" : "anyint", + "arguments" : [0], + "attributes" : "NoMem" + }, ### ``llvm.genx.frc.`` : fractional part ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -807,7 +969,10 @@ ### ### * Return value: result, same type ### - "frc" : { "result" : "anyfloat", "arguments" : [0], "attributes" : "NoMem"}, + "frc" : { "result" : "anyfloat", + "arguments" : [0], + "attributes" : "NoMem" + }, ### ``llvm.genx.inv.`` : reciprocal ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -816,7 +981,10 @@ ### ### * Return value: result, same type ### - "inv" : { "result" : "anyfloat", "arguments" : [0], "attributes" : "NoMem"}, + "inv" : { "result" : "anyfloat", + "arguments" : [0], + "attributes" : "NoMem" + }, ### ``llvm.genx.line.`` : linear equation ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -826,7 +994,10 @@ ### ### * Return value: result, same type as arg1 ### - "line" : { "result" : "anyfloat", "arguments" : ["float4",0], "attributes" : "NoMem"}, + "line" : { "result" : "anyfloat", + "arguments" : ["float4",0], + "attributes" : "NoMem" + }, ### ``llvm.genx.log.`` : base 2 logarithm ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -835,7 +1006,10 @@ ### ### * Return value: result, same type ### - "log" : { "result" : "anyfloat", "arguments" : [0], "attributes" : "NoMem"}, + "log" : { "result" : "anyfloat", + "arguments" : [0], + "attributes" : "NoMem" + }, ### ``llvm.genx.lrp.`` : linear interpolation ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -846,7 +1020,10 @@ ### ### * Return value: result, same type ### - "lrp" : { "result" : "anyfloat", "arguments" : [0,0,0], "attributes" : "NoMem"}, + "lrp" : { "result" : "anyfloat", + "arguments" : [0,0,0], + "attributes" : "NoMem" + }, ### ``llvm.genx.lzd.`` : leading zero detection ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -855,7 +1032,10 @@ ### ### * Return value: result, same type ### - "lzd" : { "result" : "anyint", "arguments" : [0], "attributes" : "NoMem"}, + "lzd" : { "result" : "anyint", + "arguments" : [0], + "attributes" : "NoMem" + }, ### ``llvm.genx.*mad..`` : mad instruction, no saturation ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -873,10 +1053,22 @@ ### * arg1: second input, same type as arg0 ### * arg2: third input, same type as result ### - "ssmad" : { "result" : "anyint", "arguments" : ["anyint",1,0], "attributes" : "NoMem"}, - "sumad" : { "result" : "anyint", "arguments" : ["anyint",1,0], "attributes" : "NoMem"}, - "usmad" : { "result" : "anyint", "arguments" : ["anyint",1,0], "attributes" : "NoMem"}, - "uumad" : { "result" : "anyint", "arguments" : ["anyint",1,0], "attributes" : "NoMem"}, + "ssmad" : { "result" : "anyint", + "arguments" : ["anyint",1,0], + "attributes" : "NoMem" + }, + "sumad" : { "result" : "anyint", + "arguments" : ["anyint",1,0], + "attributes" : "NoMem" + }, + "usmad" : { "result" : "anyint", + "arguments" : ["anyint",1,0], + "attributes" : "NoMem" + }, + "uumad" : { "result" : "anyint", + "arguments" : ["anyint",1,0], + "attributes" : "NoMem" + }, ### ``llvm.genx.*mad.sat..`` : mad instruction with saturation ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -894,10 +1086,22 @@ ### * arg1: second input, same type as arg0 ### * arg2: third input, same type as result ### - "ssmad_sat" : { "result" : "anyint", "arguments" : ["anyint",1,0], "attributes" : "NoMem"}, - "sumad_sat" : { "result" : "anyint", "arguments" : ["anyint",1,0], "attributes" : "NoMem"}, - "usmad_sat" : { "result" : "anyint", "arguments" : ["anyint",1,0], "attributes" : "NoMem"}, - "uumad_sat" : { "result" : "anyint", "arguments" : ["anyint",1,0], "attributes" : "NoMem"}, + "ssmad_sat" : { "result" : "anyint", + "arguments" : ["anyint",1,0], + "attributes" : "NoMem" + }, + "sumad_sat" : { "result" : "anyint", + "arguments" : ["anyint",1,0], + "attributes" : "NoMem" + }, + "usmad_sat" : { "result" : "anyint", + "arguments" : ["anyint",1,0], + "attributes" : "NoMem" + }, + "uumad_sat" : { "result" : "anyint", + "arguments" : ["anyint",1,0], + "attributes" : "NoMem" + }, ### ``llvm.genx.*max..`` : max instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -916,9 +1120,18 @@ ### by this non-saturating max followed by the applicable one of the ### saturating trunc intrinsics. ### - "smax" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, - "umax" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, - "fmax" : { "result" : "anyfloat", "arguments" : ["anyfloat",1], "attributes" : "NoMem"}, + "smax" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "umax" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "fmax" : { "result" : "anyfloat", + "arguments" : ["anyfloat",1], + "attributes" : "NoMem" + }, ### ``llvm.genx.*min.`` : min instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -937,9 +1150,18 @@ ### by this non-saturating min followed by the applicable one of the ### saturating trunc intrinsics. ### - "smin" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, - "umin" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, - "fmin" : { "result" : "anyfloat", "arguments" : ["anyfloat",1], "attributes" : "NoMem"}, + "smin" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "umin" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "fmin" : { "result" : "anyfloat", + "arguments" : ["anyfloat",1], + "attributes" : "NoMem" + }, ### mod ### ^^^ @@ -967,10 +1189,22 @@ ### * arg0: first input, any scalar/vector integer type (not i64) (overloaded) ### * arg1: second input, same type as arg0 ### - "ssmul" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, - "sumul" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, - "usmul" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, - "uumul" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, + "ssmul" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "sumul" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "usmul" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "uumul" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, ### ``llvm.genx.*mul.sat..`` : mul instruction with saturation ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -988,10 +1222,22 @@ ### For an fp mul, use the LLVM IR FMul instruction, followed by ### llvm.genx.sat if saturation is required. ### - "ssmul_sat" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, - "sumul_sat" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, - "usmul_sat" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, - "uumul_sat" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, + "ssmul_sat" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "sumul_sat" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "usmul_sat" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "uumul_sat" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, ### ``llvm.genx.*mulh..`` : mulh instruction, no saturation ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1003,8 +1249,14 @@ ### ### * Return value: result, same type as arg0 ### - "smulh" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, - "umulh" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, + "smulh" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "umulh" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, ### not ### ^^^ @@ -1024,7 +1276,10 @@ ### ### * Return value: result, vector float with half as many elements as arg1 ### - "pln" : { "result" : "anyfloat", "arguments" : ["float4","anyfloat"], "attributes" : "NoMem"}, + "pln" : { "result" : "anyfloat", + "arguments" : ["float4","anyfloat"], + "attributes" : "NoMem" + }, ### ``llvm.genx.pow.`` : power ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1034,7 +1289,10 @@ ### ### * Return value: result, same type ### - "pow" : { "result" : "anyfloat", "arguments" : [0,0], "attributes" : "NoMem"}, + "pow" : { "result" : "anyfloat", + "arguments" : [0,0], + "attributes" : "NoMem" + }, ### ``llvm.genx.rndd.`` : round down ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1043,7 +1301,10 @@ ### ### * Return value: result, same type ### - "rndd" : { "result" : "anyfloat", "arguments" : [0], "attributes" : "NoMem"}, + "rndd" : { "result" : "anyfloat", + "arguments" : [0], + "attributes" : "NoMem" + }, ### ``llvm.genx.rnde.`` : round to even ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1052,7 +1313,10 @@ ### ### * Return value: result, same type ### - "rnde" : { "result" : "anyfloat", "arguments" : [0], "attributes" : "NoMem"}, + "rnde" : { "result" : "anyfloat", + "arguments" : [0], + "attributes" : "NoMem" + }, ### ``llvm.genx.rndu.`` : round up ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1061,7 +1325,10 @@ ### ### * Return value: result, same type ### - "rndu" : { "result" : "anyfloat", "arguments" : [0], "attributes" : "NoMem"}, + "rndu" : { "result" : "anyfloat", + "arguments" : [0], + "attributes" : "NoMem" + }, ### ``llvm.genx.rndz.`` : round to zero ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1070,7 +1337,10 @@ ### ### * Return value: result, same type ### - "rndz" : { "result" : "anyfloat", "arguments" : [0], "attributes" : "NoMem"}, + "rndz" : { "result" : "anyfloat", + "arguments" : [0], + "attributes" : "NoMem" + }, ### ``llvm.genx.rsqrt.`` : reciprocal square root ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1079,7 +1349,10 @@ ### ### * Return value: result, same type ### - "rsqrt" : { "result" : "anyfloat", "arguments" : [0], "attributes" : "NoMem"}, + "rsqrt" : { "result" : "anyfloat", + "arguments" : [0], + "attributes" : "NoMem" + }, ### ``llvm.genx.*sad2..`` : two-wide sum of absolute differences ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1091,8 +1364,14 @@ ### ### * Return value: result, vector of i16 of same vector width ### - "ssad2" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, - "usad2" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, + "ssad2" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "usad2" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, ### ``llvm.genx.*sad2add..`` : two-wide sum of absolute differences and add ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1107,10 +1386,22 @@ ### ### * Return value: result, same type as arg2 ### - "sssad2add" : { "result" : "anyint", "arguments" : ["anyint",1,0], "attributes" : "NoMem"}, - "uusad2add" : { "result" : "anyint", "arguments" : ["anyint",1,0], "attributes" : "NoMem"}, - "ussad2add" : { "result" : "anyint", "arguments" : ["anyint",1,0], "attributes" : "NoMem"}, - "susad2add" : { "result" : "anyint", "arguments" : ["anyint",1,0], "attributes" : "NoMem"}, + "sssad2add" : { "result" : "anyint", + "arguments" : ["anyint",1,0], + "attributes" : "NoMem" + }, + "uusad2add" : { "result" : "anyint", + "arguments" : ["anyint",1,0], + "attributes" : "NoMem" + }, + "ussad2add" : { "result" : "anyint", + "arguments" : ["anyint",1,0], + "attributes" : "NoMem" + }, + "susad2add" : { "result" : "anyint", + "arguments" : ["anyint",1,0], + "attributes" : "NoMem" + }, ### ``llvm.genx.*sad2add.sat..`` : two-wide sum of absolute differences and add, saturated ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1125,10 +1416,22 @@ ### ### * Return value: result, same type as arg2 ### - "sssad2add_sat" : { "result" : "anyint", "arguments" : ["anyint",1,0], "attributes" : "NoMem"}, - "uusad2add_sat" : { "result" : "anyint", "arguments" : ["anyint",1,0], "attributes" : "NoMem"}, - "ussad2add_sat" : { "result" : "anyint", "arguments" : ["anyint",1,0], "attributes" : "NoMem"}, - "susad2add_sat" : { "result" : "anyint", "arguments" : ["anyint",1,0], "attributes" : "NoMem"}, + "sssad2add_sat" : { "result" : "anyint", + "arguments" : ["anyint",1,0], + "attributes" : "NoMem" + }, + "uusad2add_sat" : { "result" : "anyint", + "arguments" : ["anyint",1,0], + "attributes" : "NoMem" + }, + "ussad2add_sat" : { "result" : "anyint", + "arguments" : ["anyint",1,0], + "attributes" : "NoMem" + }, + "susad2add_sat" : { "result" : "anyint", + "arguments" : ["anyint",1,0], + "attributes" : "NoMem" + }, ### ``llvm.genx.*shl..`` : shl instruction, no saturation ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1143,10 +1446,22 @@ ### * Return value: result, any scalar or vector integer type with same ### vector width, even i64 ### - "ssshl" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, - "sushl" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, - "usshl" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, - "uushl" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, + "ssshl" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "sushl" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "usshl" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "uushl" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, ### ``llvm.genx.*shl.sat..`` : shl instruction with saturation ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1161,10 +1476,22 @@ ### * Return value: result, any scalar/vector integer type with same ### vector width, even i64 ### - "ssshl_sat" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, - "sushl_sat" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, - "usshl_sat" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, - "uushl_sat" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, + "ssshl_sat" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "sushl_sat" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "usshl_sat" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "uushl_sat" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, ### shr ### ^^^ @@ -1184,8 +1511,14 @@ ### * Return value: result, any scalar or vector integer type with same ### vector width (even i64) ### - "rol" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, - "ror" : { "result" : "anyint", "arguments" : ["anyint",1], "attributes" : "NoMem"}, + "rol" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, + "ror" : { "result" : "anyint", + "arguments" : ["anyint",1], + "attributes" : "NoMem" + }, ### ``llvm.genx.sin.`` : reciprocal square root ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1194,7 +1527,10 @@ ### ### * Return value: result, same type ### - "sin" : { "result" : "anyfloat", "arguments" : [0], "attributes" : "NoMem"}, + "sin" : { "result" : "anyfloat", + "arguments" : [0], + "attributes" : "NoMem" + }, ### ``llvm.genx.sqrt.`` : reciprocal square root ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1203,7 +1539,10 @@ ### ### * Return value: result, same type ### - "sqrt" : { "result" : "anyfloat", "arguments" : [0], "attributes" : "NoMem"}, + "sqrt" : { "result" : "anyfloat", + "arguments" : [0], + "attributes" : "NoMem" + }, ### ``llvm.genx.ieee.sqrt.`` : reciprocal square root, IEEE variant ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1212,7 +1551,10 @@ ### ### * Return value: result, same type ### - "ieee_sqrt" : { "result" : "anyfloat", "arguments" : [0], "attributes" : "NoMem"}, + "ieee_sqrt" : { "result" : "anyfloat", + "arguments" : [0], + "attributes" : "NoMem" + }, ### ``llvm.genx.dpas...`` : dpas instruction (Dot Product Accumulate Systolic) ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1224,7 +1566,10 @@ ### ### * Return value: result, same type as arg0 ### - "dpas" : { "result" : "anyvector", "arguments" : [0,"anyvector","anyvector","int"], "attributes" : "NoMem"}, + "dpas" : { "result" : "anyvector", + "arguments" : [0,"anyvector","anyvector","int"], + "attributes" : "NoMem" + }, ### ``llvm.genx.dpas2....`` : dpas instruction (Dot Product Accumulate Systolic) ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1241,7 +1586,10 @@ ### ### * Return value: result ### - "dpas2" : { "result" : "anyvector", "arguments" : ["anyvector","anyvector","anyvector","int","int", "int", "int", "int", "int"], "attributes" : "NoMem"}, + "dpas2" : { "result" : "anyvector", + "arguments" : ["anyvector","anyvector","anyvector","int","int", "int", "int", "int", "int"], + "attributes" : "NoMem" + }, ### ``llvm.genx.dpas.nosrc0...`` : dpas instruction (Dot Product Accumulate Systolic) with no src0 ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1252,7 +1600,10 @@ ### ### * Return value: result ### - "dpas_nosrc0" : { "result" : "anyvector", "arguments" : ["anyvector","anyvector","int"], "attributes" : "NoMem"}, + "dpas_nosrc0" : { "result" : "anyvector", + "arguments" : ["anyvector","anyvector","int"], + "attributes" : "NoMem" + }, ### ``llvm.genx.dpasw...`` : dpasw instruction (Dot Product Accumulate Systolic) ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1264,7 +1615,10 @@ ### ### * Return value: result, same type as arg0 ### - "dpasw" : { "result" : "anyvector", "arguments" : [0,"anyvector","anyvector","int"], "attributes" : "NoMem"}, + "dpasw" : { "result" : "anyvector", + "arguments" : [0,"anyvector","anyvector","int"], + "attributes" : "NoMem" + }, ### ``llvm.genx.dpasw.nosrc0...`` : dpasw instruction (Dot Product Accumulate Systolic) with no src0 ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1275,7 +1629,10 @@ ### ### * Return value: result ### - "dpasw_nosrc0" : { "result" : "anyvector", "arguments" : ["anyvector","anyvector","int"], "attributes" : "NoMem"}, + "dpasw_nosrc0" : { "result" : "anyvector", + "arguments" : ["anyvector","anyvector","int"], + "attributes" : "NoMem" + }, ### ``llvm.genx.*dp4a*....`` : dp4a instruction (Dot Product 4 Accumulate) ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1295,14 +1652,38 @@ ### ### * Return value: result, vector integer type ### - "ssdp4a" : { "result" : "anyvector", "arguments" : ["anyvector","anyvector","anyvector"], "attributes" : "NoMem"}, - "sudp4a" : { "result" : "anyvector", "arguments" : ["anyvector","anyvector","anyvector"], "attributes" : "NoMem"}, - "usdp4a" : { "result" : "anyvector", "arguments" : ["anyvector","anyvector","anyvector"], "attributes" : "NoMem"}, - "uudp4a" : { "result" : "anyvector", "arguments" : ["anyvector","anyvector","anyvector"], "attributes" : "NoMem"}, - "ssdp4a_sat" : { "result" : "anyvector", "arguments" : ["anyvector","anyvector","anyvector"], "attributes" : "NoMem"}, - "sudp4a_sat" : { "result" : "anyvector", "arguments" : ["anyvector","anyvector","anyvector"], "attributes" : "NoMem"}, - "usdp4a_sat" : { "result" : "anyvector", "arguments" : ["anyvector","anyvector","anyvector"], "attributes" : "NoMem"}, - "uudp4a_sat" : { "result" : "anyvector", "arguments" : ["anyvector","anyvector","anyvector"], "attributes" : "NoMem"}, + "ssdp4a" : { "result" : "anyvector", + "arguments" : ["anyvector","anyvector","anyvector"], + "attributes" : "NoMem" + }, + "sudp4a" : { "result" : "anyvector", + "arguments" : ["anyvector","anyvector","anyvector"], + "attributes" : "NoMem" + }, + "usdp4a" : { "result" : "anyvector", + "arguments" : ["anyvector","anyvector","anyvector"], + "attributes" : "NoMem" + }, + "uudp4a" : { "result" : "anyvector", + "arguments" : ["anyvector","anyvector","anyvector"], + "attributes" : "NoMem" + }, + "ssdp4a_sat" : { "result" : "anyvector", + "arguments" : ["anyvector","anyvector","anyvector"], + "attributes" : "NoMem" + }, + "sudp4a_sat" : { "result" : "anyvector", + "arguments" : ["anyvector","anyvector","anyvector"], + "attributes" : "NoMem" + }, + "usdp4a_sat" : { "result" : "anyvector", + "arguments" : ["anyvector","anyvector","anyvector"], + "attributes" : "NoMem" + }, + "uudp4a_sat" : { "result" : "anyvector", + "arguments" : ["anyvector","anyvector","anyvector"], + "attributes" : "NoMem" + }, ### addc ### ^^^^ @@ -1313,7 +1694,10 @@ ### ### * arg0: first input, i32 scalar/vector integer type ### * arg1: second input, same type as arg0 - "addc" : { "result" : ["anyint", "anyint"], "arguments" : [0, 0], "attributes" : "NoMem"}, + "addc" : { "result" : ["anyint", "anyint"], + "arguments" : [0, 0], + "attributes" : "NoMem" + }, ### subb ### ^^^^ @@ -1324,7 +1708,10 @@ ### ### * arg0: first input, i32 scalar/vector integer type ### * arg1: second input, same type as arg0 - "subb" : { "result" : ["anyint", "anyint"], "arguments" : [0, 0], "attributes" : "NoMem"}, + "subb" : { "result" : ["anyint", "anyint"], + "arguments" : [0, 0], + "attributes" : "NoMem" + }, ### add3 ### ^^^^ @@ -1336,7 +1723,10 @@ ### * arg0: first input, any scalar/vector integer type, i16/i32 (overloaded) ### * arg1: second input, same type as arg0 ### * arg2: third input, same type as arg0 - "add3" : { "result" : "anyint", "arguments" : ["anyint",1,1], "attributes" : "NoMem"}, + "add3" : { "result" : "anyint", + "arguments" : ["anyint",1,1], + "attributes" : "NoMem" + }, ### ``llvm.genx.*add3.sat..`` : add3 instruction with saturation ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1352,10 +1742,22 @@ ### * Return value: result, any scalar or vector integer type with same ### vector width ### - "ssadd3_sat" : { "result" : "anyint", "arguments" : ["anyint",1,1], "attributes" : "NoMem"}, - "suadd3_sat" : { "result" : "anyint", "arguments" : ["anyint",1,1], "attributes" : "NoMem"}, - "usadd3_sat" : { "result" : "anyint", "arguments" : ["anyint",1,1], "attributes" : "NoMem"}, - "uuadd3_sat" : { "result" : "anyint", "arguments" : ["anyint",1,1], "attributes" : "NoMem"}, + "ssadd3_sat" : { "result" : "anyint", + "arguments" : ["anyint",1,1], + "attributes" : "NoMem" + }, + "suadd3_sat" : { "result" : "anyint", + "arguments" : ["anyint",1,1], + "attributes" : "NoMem" + }, + "usadd3_sat" : { "result" : "anyint", + "arguments" : ["anyint",1,1], + "attributes" : "NoMem" + }, + "uuadd3_sat" : { "result" : "anyint", + "arguments" : ["anyint",1,1], + "attributes" : "NoMem" + }, ### bfn ### ^^^ @@ -1368,7 +1770,10 @@ ### * arg1: second input, same type as arg0 ### * arg2: third input, same type as arg0 ### * arg3: fourth input, byte, constant - "bfn" : { "result" : "anyint", "arguments" : ["anyint",1,1,"char"], "attributes" : "NoMem"}, + "bfn" : { "result" : "anyint", + "arguments" : ["anyint",1,1,"char"], + "attributes" : "NoMem" + }, ### xor ### ^^^ @@ -1386,8 +1791,14 @@ ### ### * Return value: i16 the value read ### - "thread_x" : { "result" : "short", "arguments" : [], "attributes" : "NoMem"}, - "thread_y" : { "result" : "short", "arguments" : [], "attributes" : "NoMem"}, + "thread_x" : { "result" : "short", + "arguments" : [], + "attributes" : "NoMem" + }, + "thread_y" : { "result" : "short", + "arguments" : [], + "attributes" : "NoMem" + }, ### ``llvm.genx.group.id.*`` : read group ID register ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1397,9 +1808,18 @@ ### ### * Return value: i32 the value read ### - "group_id_x" : { "result" : "int", "arguments" : [], "attributes" : "NoMem"}, - "group_id_y" : { "result" : "int", "arguments" : [], "attributes" : "NoMem"}, - "group_id_z" : { "result" : "int", "arguments" : [], "attributes" : "NoMem"}, + "group_id_x" : { "result" : "int", + "arguments" : [], + "attributes" : "NoMem" + }, + "group_id_y" : { "result" : "int", + "arguments" : [], + "attributes" : "NoMem" + }, + "group_id_z" : { "result" : "int", + "arguments" : [], + "attributes" : "NoMem" + }, ### ``llvm.genx.timestamp.`` : read vISA v11 (%timestamp) ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1408,7 +1828,10 @@ ### ### The vector width must be power of 2 and no larger than 4. ### - "timestamp" : { "result" : "anyint", "arguments" : [], "attributes" : "None"}, + "timestamp" : { "result" : "anyint", + "arguments" : [], + "attributes" : "None" + }, ### ``llvm.genx.r0.`` : read vISA v12 (%r0) ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1417,7 +1840,10 @@ ### ### The vector width must be power of 2 and no larger than 8. ### - "r0" : { "result" : "anyint", "arguments" : [], "attributes" : "ReadMem"}, + "r0" : { "result" : "anyint", + "arguments" : [], + "attributes" : "ReadMem" + }, ### ``llvm.genx.sr0.`` : read vISA v13 (%sr0) ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1427,7 +1853,10 @@ ### The vector width must be 4 ### ### - "sr0" : { "result" : "anyint", "arguments" : [], "attributes" : "ReadMem"}, + "sr0" : { "result" : "anyint", + "arguments" : [], + "attributes" : "ReadMem" + }, ### ``llvm.genx.set.sr0.2`` : write vISA v13(0, 2) (%sr0.2) ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1436,7 +1865,10 @@ ### ### * Return value: void ### - "set_sr0_2" : { "result" : "void", "arguments" : ["int"], "attributes" : "None"}, + "set_sr0_2" : { "result" : "void", + "arguments" : ["int"], + "attributes" : "None" + }, ### ``llvm.genx.get.color`` : read color value of the thread origin ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1446,21 +1878,30 @@ ### This may not be the most appropriate way to access this value, ### but is a stop-gap solution. ### - "get_color" : { "result" : "short", "arguments" : [], "attributes" : "NoMem"}, + "get_color" : { "result" : "short", + "arguments" : [], + "attributes" : "NoMem" + }, ### ``llvm.genx.get.hwid`` : read hw_id value ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ### ### Return Value: i32 the value read ### - "get_hwid" : { "result" : "int", "arguments" : [], "attributes" : "NoMem"}, + "get_hwid" : { "result" : "int", + "arguments" : [], + "attributes" : "NoMem" + }, ### ``llvm.genx.ce0`` : read channel-enable register ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ### ### Return Value: i32 the value read ### - "ce0" : { "result" : "int", "arguments" : [], "attributes" : "ReadMem"}, + "ce0" : { "result" : "int", + "arguments" : [], + "attributes" : "ReadMem" + }, ### ``llvm.genx.set.pause`` : set the pause register (v11.4) ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1475,7 +1916,10 @@ ### ### We set this intrinsic to have side-effects (last field empty) to stop it being removed as it ### otherwise looks dead - "set_pause" : { "result" : "void", "arguments" : ["short"], "attributes" : "None"}, + "set_pause" : { "result" : "void", + "arguments" : ["short"], + "attributes" : "None" + }, ### ``llvm.genx.dummy.mov`` : insert a dummy mov to v0 ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1492,7 +1936,10 @@ ### ### We set this intrinsic to have side-effects (last field empty) to stop it being removed as it ### otherwise looks dead and also to prevent any kind of code motion optimisation - "dummy_mov" : { "result" : "void", "arguments" : ["short"], "attributes" : "None"}, + "dummy_mov" : { "result" : "void", + "arguments" : ["short"], + "attributes" : "None" + }, ### The following 2 predef.reg intrinsics aren't translated directly to read/writes of the reg, ### instead they're baled together with rd/wrregions and in fact indicate that those rdr/wrrs @@ -1507,7 +1954,10 @@ ### * Return value: value read ### ### - "read_predef_reg" : { "result" : "any", "arguments" : ["int", "any"], "attributes" : "ReadMem"}, + "read_predef_reg" : { "result" : "any", + "arguments" : ["int", "any"], + "attributes" : "ReadMem" + }, ### ``llvm.write.predef.reg..`` : write value to predefined vISA reg ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1517,7 +1967,10 @@ ### ### * Return value: value written ### - "write_predef_reg" : { "result" : "any", "arguments" : ["int", "any"], "attributes" : "WriteMem"}, + "write_predef_reg" : { "result" : "any", + "arguments" : ["int", "any"], + "attributes" : "WriteMem" + }, ## -------------------------- ### Shared function intrinsics @@ -1551,16 +2004,46 @@ ### Predicate, element offset, src, and the return value must all have the ### same vector width, which must be 1, 8 or 16. ### - "dword_atomic_add" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0,0], "attributes" : "None"}, - "dword_atomic_sub" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0,0], "attributes" : "None"}, - "dword_atomic_min" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0,0], "attributes" : "None"}, - "dword_atomic_max" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0,0], "attributes" : "None"}, - "dword_atomic_xchg" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0,0], "attributes" : "None"}, - "dword_atomic_and" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0,0], "attributes" : "None"}, - "dword_atomic_or" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0,0], "attributes" : "None"}, - "dword_atomic_xor" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0,0], "attributes" : "None"}, - "dword_atomic_imin" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0,0], "attributes" : "None"}, - "dword_atomic_imax" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0,0], "attributes" : "None"}, + "dword_atomic_add" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0,0], + "attributes" : "None", + }, + "dword_atomic_sub" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0,0], + "attributes" : "None", + }, + "dword_atomic_min" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0,0], + "attributes" : "None", + }, + "dword_atomic_max" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0,0], + "attributes" : "None", + }, + "dword_atomic_xchg" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0,0], + "attributes" : "None", + }, + "dword_atomic_and" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0,0], + "attributes" : "None", + }, + "dword_atomic_or" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0,0], + "attributes" : "None", + }, + "dword_atomic_xor" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0,0], + "attributes" : "None", + }, + "dword_atomic_imin" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0,0], + "attributes" : "None", + }, + "dword_atomic_imax" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0,0], + "attributes" : "None", + }, ### ``llvm.genx.dword.atomic2.*..`` : dword atomic with binary operator (variant with no oldval) ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1586,16 +2069,46 @@ ### Predicate, element offset, src, and the return value must all have the ### same vector width, which must be 1, 8 or 16. ### - "dword_atomic2_add" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0], "attributes" : "None"}, - "dword_atomic2_sub" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0], "attributes" : "None"}, - "dword_atomic2_min" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0], "attributes" : "None"}, - "dword_atomic2_max" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0], "attributes" : "None"}, - "dword_atomic2_xchg" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0], "attributes" : "None"}, - "dword_atomic2_and" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0], "attributes" : "None"}, - "dword_atomic2_or" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0], "attributes" : "None"}, - "dword_atomic2_xor" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0], "attributes" : "None"}, - "dword_atomic2_imin" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0], "attributes" : "None"}, - "dword_atomic2_imax" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0], "attributes" : "None"}, + "dword_atomic2_add" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0], + "attributes" : "None", + }, + "dword_atomic2_sub" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0], + "attributes" : "None", + }, + "dword_atomic2_min" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0], + "attributes" : "None", + }, + "dword_atomic2_max" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0], + "attributes" : "None", + }, + "dword_atomic2_xchg" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0], + "attributes" : "None", + }, + "dword_atomic2_and" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0], + "attributes" : "None", + }, + "dword_atomic2_or" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0], + "attributes" : "None", + }, + "dword_atomic2_xor" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0], + "attributes" : "None", + }, + "dword_atomic2_imin" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0], + "attributes" : "None", + }, + "dword_atomic2_imax" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0], + "attributes" : "None", + }, ### ``llvm.genx.dword.atomic.*...`` : dword atomic with fmin/fmax operation ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1614,8 +2127,14 @@ ### Predicate, element offset, src, and the return value must all have the ### same vector width, which must be 1, 8 or 16. ### - "dword_atomic_fmin" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0,0], "attributes" : "None"}, - "dword_atomic_fmax" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0,0], "attributes" : "None"}, + "dword_atomic_fmin" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0,0], + "attributes" : "None", + }, + "dword_atomic_fmax" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0,0], + "attributes" : "None", + }, ### ``llvm.genx.dword.atomic2.*...`` : dword atomic with fmin/fmax operation (variant with no oldval) ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1633,8 +2152,14 @@ ### Predicate, element offset, src, and the return value must all have the ### same vector width, which must be 1, 8 or 16. ### - "dword_atomic2_fmin" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0], "attributes" : "None"}, - "dword_atomic2_fmax" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0], "attributes" : "None"}, + "dword_atomic2_fmin" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0], + "attributes" : "None", + }, + "dword_atomic2_fmax" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0], + "attributes" : "None", + }, ### ``llvm.genx.dword.atomic.*..`` : dword atomic with inc/dec operation @@ -1653,8 +2178,14 @@ ### Predicate, element offset, src, and the return value must all have the ### same vector width, which must be 1, 8 or 16. ### - "dword_atomic_inc" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,0], "attributes" : "None"}, - "dword_atomic_dec" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,0], "attributes" : "None"}, + "dword_atomic_inc" : { "result" : "anyvector", + "arguments" : ["anyvector","int",0,0], + "attributes" : "None", + }, + "dword_atomic_dec" : { "result" : "anyvector", + "arguments" : ["anyvector","int",0,0], + "attributes" : "None", + }, ### ``llvm.genx.dword.atomic2.*..`` : dword atomic with inc/dec operation (variant with no oldval) ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1671,8 +2202,14 @@ ### Predicate, element offset, src, and the return value must all have the ### same vector width, which must be 1, 8 or 16. ### - "dword_atomic2_inc" : { "result" : "anyvector", "arguments" : ["anyvector","int",0], "attributes" : "None"}, - "dword_atomic2_dec" : { "result" : "anyvector", "arguments" : ["anyvector","int",0], "attributes" : "None"}, + "dword_atomic2_inc" : { "result" : "anyvector", + "arguments" : ["anyvector","int",0], + "attributes" : "None", + }, + "dword_atomic2_dec" : { "result" : "anyvector", + "arguments" : ["anyvector","int",0], + "attributes" : "None", + }, ### ``llvm.genx.dword.atomic.cmpxchg..`` : vISA DWORD_ATOMIC CMPXCHG instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1690,7 +2227,10 @@ ### Predicate, element offset, src, and the return value must all have the ### same vector width, which must be 1, 8 or 16. ### - "dword_atomic_cmpxchg" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,0,0,0], "attributes" : "None"}, + "dword_atomic_cmpxchg" : { "result" : "anyvector", + "arguments" : ["anyvector","int",0,0,0,0], + "attributes" : "None", + }, ### ``llvm.genx.dword.atomic2.cmpxchg..`` : vISA DWORD_ATOMIC CMPXCHG instruction (variant with no oldval) ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1707,7 +2247,10 @@ ### Predicate, element offset, src, and the return value must all have the ### same vector width, which must be 1, 8 or 16. ### - "dword_atomic2_cmpxchg" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,0,0], "attributes" : "None"}, + "dword_atomic2_cmpxchg" : { "result" : "anyvector", + "arguments" : ["anyvector","int",0,0,0], + "attributes" : "None", + }, ### ``llvm.genx.dword.atomic.fcmpwr...`` : vISA DWORD_ATOMIC FCMPWR instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1725,7 +2268,10 @@ ### Predicate, element offset, src, and the return value must all have the ### same vector width, which must be 1, 8 or 16. ### - "dword_atomic_fcmpwr" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0,0,0], "attributes" : "None"}, + "dword_atomic_fcmpwr" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0,0,0], + "attributes" : "None", + }, ### ``llvm.genx.dword.atomic2.fcmpwr...`` : vISA DWORD_ATOMIC FCMPWR instruction (variant with no oldval) ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1742,7 +2288,10 @@ ### Predicate, element offset, src, and the return value must all have the ### same vector width, which must be 1, 8 or 16. ### - "dword_atomic2_fcmpwr" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0,0], "attributes" : "None"}, + "dword_atomic2_fcmpwr" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0,0], + "attributes" : "None", + }, ### ``llvm.genx.typed.atomic.*...`` : atomic typed with binary operator ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1771,16 +2320,46 @@ ### Predicate, element offset, src, and the return value must all have the ### same vector width (which in reality must be 8) ### - "typed_atomic_add" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,"anyint",2,2,2], "attributes" : "None"}, - "typed_atomic_sub" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,"anyint",2,2,2], "attributes" : "None"}, - "typed_atomic_min" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,"anyint",2,2,2], "attributes" : "None"}, - "typed_atomic_max" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,"anyint",2,2,2], "attributes" : "None"}, - "typed_atomic_xchg" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,"anyint",2,2,2], "attributes" : "None"}, - "typed_atomic_and" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,"anyint",2,2,2], "attributes" : "None"}, - "typed_atomic_or" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,"anyint",2,2,2], "attributes" : "None"}, - "typed_atomic_xor" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,"anyint",2,2,2], "attributes" : "None"}, - "typed_atomic_imin" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,"anyint",2,2,2], "attributes" : "None"}, - "typed_atomic_imax" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,"anyint",2,2,2], "attributes" : "None"}, + "typed_atomic_add" : { "result" : "anyvector", + "arguments" : ["anyvector","int",0,"anyint",2,2,2], + "attributes" : "None" + }, + "typed_atomic_sub" : { "result" : "anyvector", + "arguments" : ["anyvector","int",0,"anyint",2,2,2], + "attributes" : "None" + }, + "typed_atomic_min" : { "result" : "anyvector", + "arguments" : ["anyvector","int",0,"anyint",2,2,2], + "attributes" : "None" + }, + "typed_atomic_max" : { "result" : "anyvector", + "arguments" : ["anyvector","int",0,"anyint",2,2,2], + "attributes" : "None" + }, + "typed_atomic_xchg" : { "result" : "anyvector", + "arguments" : ["anyvector","int",0,"anyint",2,2,2], + "attributes" : "None" + }, + "typed_atomic_and" : { "result" : "anyvector", + "arguments" : ["anyvector","int",0,"anyint",2,2,2], + "attributes" : "None" + }, + "typed_atomic_or" : { "result" : "anyvector", + "arguments" : ["anyvector","int",0,"anyint",2,2,2], + "attributes" : "None" + }, + "typed_atomic_xor" : { "result" : "anyvector", + "arguments" : ["anyvector","int",0,"anyint",2,2,2], + "attributes" : "None" + }, + "typed_atomic_imin" : { "result" : "anyvector", + "arguments" : ["anyvector","int",0,"anyint",2,2,2], + "attributes" : "None" + }, + "typed_atomic_imax" : { "result" : "anyvector", + "arguments" : ["anyvector","int",0,"anyint",2,2,2], + "attributes" : "None" + }, ### ``llvm.genx.typed.atomic.*...`` : atomic typed with fmin/fmax operation ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1801,8 +2380,14 @@ ### Predicate, element offset, src, and the return value must all have the ### same vector width (which in reality must be 8) ### - "typed_atomic_fmin" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,"anyint",2,2,2], "attributes" : "None"}, - "typed_atomic_fmax" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,"anyint",2,2,2], "attributes" : "None"}, + "typed_atomic_fmin" : { "result" : "anyvector", + "arguments" : ["anyvector","int",0,"anyint",2,2,2], + "attributes" : "None" + }, + "typed_atomic_fmax" : { "result" : "anyvector", + "arguments" : ["anyvector","int",0,"anyint",2,2,2], + "attributes" : "None" + }, ### ``llvm.genx.typed.atomic.*...`` : atomic typed with inc/dec operation ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1822,8 +2407,14 @@ ### Predicate, element offset, src, and the return value must all have the ### same vector width (which in reality must be 8) ### - "typed_atomic_inc" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",2,2,2], "attributes" : "None"}, - "typed_atomic_dec" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",2,2,2], "attributes" : "None"}, + "typed_atomic_inc" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",2,2,2], + "attributes" : "None" + }, + "typed_atomic_dec" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",2,2,2], + "attributes" : "None" + }, ### ``llvm.genx.typed.atomic.cmpxchg...`` : vISA TYPED_ATOMIC CMPXCHG instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1843,7 +2434,10 @@ ### Predicate, element offset, src, and the return value must all have the ### same vector width (which in reality must be 8) ### - "typed_atomic_cmpxchg" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,0,"anyint",2,2,2], "attributes" : "None"}, + "typed_atomic_cmpxchg" : { "result" : "anyvector", + "arguments" : ["anyvector","int",0,0,"anyint",2,2,2], + "attributes" : "None" + }, ### ``llvm.genx.typed.atomic.fcmpwr...`` : vISA TYPED_ATOMIC FCMPWR instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1863,7 +2457,10 @@ ### Predicate, element offset, src, and the return value must all have the ### same vector width (which in reality must be 8) ### - "typed_atomic_fcmpwr" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,0,"anyint",2,2,2], "attributes" : "None"}, + "typed_atomic_fcmpwr" : { "result" : "anyvector", + "arguments" : ["anyvector","int",0,0,"anyint",2,2,2], + "attributes" : "None" + }, ### ``llvm.genx.gather.private...`` : CMC internal, no VISA ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1881,7 +2478,10 @@ ### ### The element offset arg must have the same vector width. ### - "gather_private" : { "result" : "anyvector", "arguments" : ["anyvector","anyptr","anyint",0], "attributes" : "ReadMem"}, + "gather_private" : { "result" : "anyvector", + "arguments" : ["anyvector","anyptr","anyint",0], + "attributes" : "ReadMem" + }, ### ``llvm.genx.gather.scaled...`` : vISA GATHER_SCALED instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1906,7 +2506,10 @@ ### F type. For 1 and 2 byte (1 x num blocks) reads the upper bytes have ### undefined values in the returned value. ### - "gather_scaled" : { "result" : "anyvector", "arguments" : ["anyvector","int","short","int","int","anyint",0], "attributes" : "ReadMem"}, + "gather_scaled" : { "result" : "anyvector", + "arguments" : ["anyvector","int","short","int","int","anyint",0], + "attributes" : "ReadMem", + }, ### ``llvm.genx.gather.scaled2`` : vISA GATHER_SCALED instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1929,7 +2532,10 @@ ### For 1 and 2 byte (1 x num blocks) reads the upper bytes have ### undefined values in the returned value. ### - "gather_scaled2" : { "result" : "anyvector", "arguments" : ["int","short","int","int","anyint"], "attributes" : "ReadMem"}, + "gather_scaled2" : { "result" : "anyvector", + "arguments" : ["int","short","int","int","anyint"], + "attributes" : "ReadMem", + }, ### ``llvm.genx.gather.masked.scaled2`` : vISA GATHER_SCALED instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1945,7 +2551,10 @@ ### ### * Return value: the data read ### - "gather_masked_scaled2" : { "result" : "anyvector", "arguments" : ["int","short","int","int","anyint","anyvector"], "attributes" : "ReadMem"}, + "gather_masked_scaled2" : { "result" : "anyvector", + "arguments" : ["int","short","int","int","anyint","anyvector"], + "attributes" : "ReadMem", + }, ### ``llvm.genx.gather4.scaled...`` : vISA GATHER4_SCALED instruction @@ -1973,7 +2582,10 @@ ### times the number of channels to read per element. ### The element type of the return value must be i32 or float. ### - "gather4_scaled" : { "result" : "anyvector", "arguments" : ["anyvector","int","short","int","int","anyint",0], "attributes" : "ReadMem"}, + "gather4_scaled" : { "result" : "anyvector", + "arguments" : ["anyvector","int","short","int","int","anyint",0], + "attributes" : "ReadMem" , + }, ### ``llvm.genx.gather4.scaled2`` : vISA GATHER4_SCALED instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2001,7 +2613,10 @@ ### times the number of channels to read per element. ### The element type of the return value must be i32 or float. ### - "gather4_scaled2" : { "result" : "anyvector", "arguments" : ["int","short","int","int","anyint"], "attributes" : "ReadMem"}, + "gather4_scaled2" : { "result" : "anyvector", + "arguments" : ["int","short","int","int","anyint"], + "attributes" : "ReadMem", + }, ### ``llvm.genx.gather4.masked.scaled2`` : vISA GATHER4_SCALED instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2016,7 +2631,10 @@ ### ### * Return value: the data read ### - "gather4_masked_scaled2" : { "result" : "anyvector", "arguments" : ["int","short","int","int","anyint","anyvector"], "attributes" : "ReadMem"}, + "gather4_masked_scaled2" : { "result" : "anyvector", + "arguments" : ["int","short","int","int","anyint","anyvector"], + "attributes" : "ReadMem", + }, ### ``llvm.genx.gather4.typed...`` : vISA GATHER4_TYPED instruction @@ -2044,7 +2662,10 @@ ### times the number of channels to read per element. ### The element type of the return value must be i32 or float. ### - "gather4_typed" : { "result" : "anyvector", "arguments" : ["int","anyvector","int","anyvector",2,2,0], "attributes" : "ReadMem"}, + "gather4_typed" : { "result" : "anyvector", + "arguments" : ["int","anyvector","int","anyvector",2,2,0], + "attributes" : "ReadMem", + }, ### ``llvm.genx.media.ld.`` : vISA MEDIA_LD instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2067,7 +2688,10 @@ ### The block width has a maximum of 32 (64 on BDW+). The maxmimum byte ### size of the return type is 256. ### - "media_ld" : { "result" : "anyvector", "arguments" : ["int","int","int","int","int","int"], "attributes" : "ReadMem"}, + "media_ld" : { "result" : "anyvector", + "arguments" : ["int","int","int","int","int","int"], + "attributes" : "ReadMem", + }, ### ``llvm.genx.media.st.`` : vISA MEDIA_ST instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2089,7 +2713,10 @@ ### The block width has a maximum of 32 (64 on BDW+). The maxmimum byte ### size of the data to write is 256. ### - "media_st" : { "result" : "void", "arguments" : ["int","int","int","int","int","int","anyvector"], "attributes" : "None"}, + "media_st" : { "result" : "void", + "arguments" : ["int","int","int","int","int","int","anyvector"], + "attributes" : "None", + }, ### ``llvm.genx.oword.ld*.`` : oword load instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2105,8 +2732,14 @@ ### ### The byte size of the return type must be 16, 32, 64, or 128. ### - "oword_ld" : { "result" : "anyvector", "arguments" : ["int","int","int"], "attributes" : "ReadMem"}, - "oword_ld_unaligned" : { "result" : "anyvector", "arguments" : ["int","int","int"], "attributes" : "ReadMem"}, + "oword_ld" : { "result" : "anyvector", + "arguments" : ["int","int","int"], + "attributes" : "ReadMem", + }, + "oword_ld_unaligned" : { "result" : "anyvector", + "arguments" : ["int","int","int"], + "attributes" : "ReadMem", + }, ### ``llvm.genx.oword.st.`` : vISA OWORD_ST instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2118,7 +2751,10 @@ ### ### The byte size of the data to write must be 16, 32, 64, or 128. ### - "oword_st" : { "result" : "void", "arguments" : ["int","int","anyvector"], "attributes" : "None"}, + "oword_st" : { "result" : "void", + "arguments" : ["int","int","anyvector"], + "attributes" : "None", + }, ### ``llvm.genx.scatter.private....`` : CM internal, no VISA ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2132,7 +2768,10 @@ ### which must be 1, 8 or 16. ### The element offset arg must have the same vector width. ### - "scatter_private" : { "result" : "void", "arguments" : ["anyvector","anyptr","anyint","anyvector"], "attributes" : "None"}, + "scatter_private" : { "result" : "void", + "arguments" : ["anyvector","anyptr","anyint","anyvector"], + "attributes" : "None" + }, ### ``llvm.genx.scatter.scaled...`` : vISA SCATTER_SCALED instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2154,7 +2793,10 @@ ### The data type to write must have UD, D or F type. For 1 and 2 byte (1 x num ### blocks) accesses the upper bytes will be ignored. ### - "scatter_scaled" : { "result" : "void", "arguments" : ["anyvector","int","short","int","int","anyint","anyvector"], "attributes" : "None"}, + "scatter_scaled" : { "result" : "void", + "arguments" : ["anyvector","int","short","int","int","anyint","anyvector"], + "attributes" : "None", + }, ### ``llvm.genx.scatter4.scaled...`` : vISA SCATTER4_SCALED instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2180,7 +2822,10 @@ ### times the number of channels to write per element. ### The element type of the data to write must be i32 or float. ### - "scatter4_scaled" : { "result" : "void", "arguments" : ["anyvector","int","short","int","int","anyint","anyvector"], "attributes" : "None"}, + "scatter4_scaled" : { "result" : "void", + "arguments" : ["anyvector","int","short","int","int","anyint","anyvector"], + "attributes" : "None", + }, ### ``llvm.genx.scatter4.typed...`` : vISA SCATTER4_TYPED instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2205,7 +2850,10 @@ ### times the number of channels to read per element. ### The element type of the source value must be i32 or float. ### - "scatter4_typed" : { "result" : "void", "arguments" : ["int","anyvector","int","anyvector",1,1,"anyvector"], "attributes" : "None"}, + "scatter4_typed" : { "result" : "void", + "arguments" : ["int","anyvector","int","anyvector",1,1,"anyvector"], + "attributes" : "None", + }, ### ``llvm.genx.transpose.ld.`` : vISA TRANSPOSE_LD instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2223,7 +2871,10 @@ ### inferred from those values. ### The element type of the return value must be i32 or float. ### - "transpose_ld" : { "result" : "anyvector", "arguments" : ["int","int","int","int"], "attributes" : "ReadMem"}, + "transpose_ld" : { "result" : "anyvector", + "arguments" : ["int","int","int","int"], + "attributes" : "ReadMem" + }, ### ``llvm.genx.untyped.atomic.*..`` : vISA UNTYPED_ATOMIC with binary operator ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2250,16 +2901,46 @@ ### Predicate, element offset, src, and the return value must all have the ##same vector / width, which must be 8 or 16. ### - "untyped_atomic_add" : { "result" : "anyvector", "arguments" : ["anyvector","int","int",0,0,0], "attributes" : "None"}, - "untyped_atomic_sub" : { "result" : "anyvector", "arguments" : ["anyvector","int","int",0,0,0], "attributes" : "None"}, - "untyped_atomic_min" : { "result" : "anyvector", "arguments" : ["anyvector","int","int",0,0,0], "attributes" : "None"}, - "untyped_atomic_max" : { "result" : "anyvector", "arguments" : ["anyvector","int","int",0,0,0], "attributes" : "None"}, - "untyped_atomic_xchg" : { "result" : "anyvector", "arguments" : ["anyvector","int","int",0,0,0], "attributes" : "None"}, - "untyped_atomic_and" : { "result" : "anyvector", "arguments" : ["anyvector","int","int",0,0,0], "attributes" : "None"}, - "untyped_atomic_or" : { "result" : "anyvector", "arguments" : ["anyvector","int","int",0,0,0], "attributes" : "None"}, - "untyped_atomic_xor" : { "result" : "anyvector", "arguments" : ["anyvector","int","int",0,0,0], "attributes" : "None"}, - "untyped_atomic_imin" : { "result" : "anyvector", "arguments" : ["anyvector","int","int",0,0,0], "attributes" : "None"}, - "untyped_atomic_imax" : { "result" : "anyvector", "arguments" : ["anyvector","int","int",0,0,0], "attributes" : "None"}, + "untyped_atomic_add" : { "result" : "anyvector", + "arguments" : ["anyvector","int","int",0,0,0], + "attributes" : "None" + }, + "untyped_atomic_sub" : { "result" : "anyvector", + "arguments" : ["anyvector","int","int",0,0,0], + "attributes" : "None" + }, + "untyped_atomic_min" : { "result" : "anyvector", + "arguments" : ["anyvector","int","int",0,0,0], + "attributes" : "None" + }, + "untyped_atomic_max" : { "result" : "anyvector", + "arguments" : ["anyvector","int","int",0,0,0], + "attributes" : "None" + }, + "untyped_atomic_xchg" : { "result" : "anyvector", + "arguments" : ["anyvector","int","int",0,0,0], + "attributes" : "None" + }, + "untyped_atomic_and" : { "result" : "anyvector", + "arguments" : ["anyvector","int","int",0,0,0], + "attributes" : "None" + }, + "untyped_atomic_or" : { "result" : "anyvector", + "arguments" : ["anyvector","int","int",0,0,0], + "attributes" : "None" + }, + "untyped_atomic_xor" : { "result" : "anyvector", + "arguments" : ["anyvector","int","int",0,0,0], + "attributes" : "None" + }, + "untyped_atomic_imin" : { "result" : "anyvector", + "arguments" : ["anyvector","int","int",0,0,0], + "attributes" : "None" + }, + "untyped_atomic_imax" : { "result" : "anyvector", + "arguments" : ["anyvector","int","int",0,0,0], + "attributes" : "None" + }, ### ``llvm.genx.untyped.atomic.*..`` : vISA UNTYPED_ATOMIC with inc/dec ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2277,8 +2958,14 @@ ### Predicate, element offset and the return value must have the same vector ### width, which must be 8 or 16. ### - "untyped_atomic_inc" : { "result" : "anyvector", "arguments" : ["anyvector","int","int",0,0], "attributes" : "None"}, - "untyped_atomic_dec" : { "result" : "anyvector", "arguments" : ["anyvector","int","int",0,0], "attributes" : "None"}, + "untyped_atomic_inc" : { "result" : "anyvector", + "arguments" : ["anyvector","int","int",0,0], + "attributes" : "None" + }, + "untyped_atomic_dec" : { "result" : "anyvector", + "arguments" : ["anyvector","int","int",0,0], + "attributes" : "None" + }, ### ``llvm.genx.untyped.atomic.cmpxchg..`` : vISA UNTYPED_ATOMIC CMPXCHG instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2296,7 +2983,10 @@ ### Predicate, element offset, src0, src1, and the return value must all have ### the same vector width, which must be 8 or 16. ### - "untyped_atomic_cmpxchg" : { "result" : "anyvector", "arguments" : ["anyvector","int","int",0,0,0,0], "attributes" : "None"}, + "untyped_atomic_cmpxchg" : { "result" : "anyvector", + "arguments" : ["anyvector","int","int",0,0,0,0], + "attributes" : "None" + }, ### ``llvm.genx.svm.block.ld*..
`` : vISA SVM BLOCK_LD instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2313,8 +3003,14 @@ ### The data read must have a size that is a power of two from 16 to 128 ### bytes. ### - "svm_block_ld" : { "result" : "anyvector", "arguments" : ["anyint"], "attributes" : "ReadMem"}, - "svm_block_ld_unaligned" : { "result" : "anyvector", "arguments" : ["anyint"], "attributes" : "ReadMem"}, + "svm_block_ld" : { "result" : "anyvector", + "arguments" : ["anyint"], + "attributes" : "ReadMem" + }, + "svm_block_ld_unaligned" : { "result" : "anyvector", + "arguments" : ["anyint"], + "attributes" : "ReadMem" + }, ### ``llvm.genx.svm.block.st.
`` : vISA SVM BLOCK_ST instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2326,7 +3022,10 @@ ### The data to write must have a size that is a power of two from 16 to 128 ### bytes. ### - "svm_block_st" : { "result" : "void", "arguments" : ["anyint","anyvector"], "attributes" : "None"}, + "svm_block_st" : { "result" : "void", + "arguments" : ["anyint","anyvector"], + "attributes" : "None" + }, ### ``llvm.genx.svm.gather...`` : vISA SVM GATHER instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2345,7 +3044,10 @@ ### The return value vector width is the address vector width times ### number of blocks (rounded up to 4 if block size is 1). ### - "svm_gather" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0], "attributes" : "ReadMem"}, + "svm_gather" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0], + "attributes" : "ReadMem" + }, ### ``llvm.genx.svm.gather4.scaled...`` : vISA SVM GATHER4_SCALED instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2372,7 +3074,10 @@ ### times the number of channels to read per element. ### The element type of the return value must be i32 or float. ### - "svm_gather4_scaled" : { "result" : "anyvector", "arguments" : ["anyvector","int","short","long","anyint",0], "attributes" : "ReadMem"}, + "svm_gather4_scaled" : { "result" : "anyvector", + "arguments" : ["anyvector","int","short","long","anyint",0], + "attributes" : "ReadMem" + }, ### ``llvm.genx.svm.scatter...`` : vISA SVM SCATTER instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2389,7 +3094,10 @@ ### The data vector width is the address vector width times ### number of blocks (rounded up to 4 if block size is 1). ### - "svm_scatter" : { "result" : "void", "arguments" : ["anyvector","int","anyint","anyvector"], "attributes" : "None"}, + "svm_scatter" : { "result" : "void", + "arguments" : ["anyvector","int","anyint","anyvector"], + "attributes" : "None" + }, ### ``llvm.genx.svm.scatter4.scaled...`` : vISA SVM SCATTER4_SCALED instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2414,7 +3122,10 @@ ### times the number of channels to read per element. ### The element type of the data to write arg must be i32 or float. ### - "svm_scatter4_scaled" : { "result" : "void", "arguments" : ["anyvector","int","short","long","anyint","anyvector"], "attributes" : "None"}, + "svm_scatter4_scaled" : { "result" : "void", + "arguments" : ["anyvector","int","short","long","anyint","anyvector"], + "attributes" : "None" + }, ### ``llvm.genx.svm.atomic.*...`` : vISA SVM_ATOMIC with binary operator ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2439,16 +3150,46 @@ ### Predicate, element offset, src, and the return value must all have the ### same vector width, which must be 1, 2, 4, or 8. ### - "svm_atomic_add" : { "result" : "anyvector", "arguments" : ["anyvector","anyint",0,0], "attributes" : "None"}, - "svm_atomic_sub" : { "result" : "anyvector", "arguments" : ["anyvector","anyint",0,0], "attributes" : "None"}, - "svm_atomic_min" : { "result" : "anyvector", "arguments" : ["anyvector","anyint",0,0], "attributes" : "None"}, - "svm_atomic_max" : { "result" : "anyvector", "arguments" : ["anyvector","anyint",0,0], "attributes" : "None"}, - "svm_atomic_xchg" : { "result" : "anyvector", "arguments" : ["anyvector","anyint",0,0], "attributes" : "None"}, - "svm_atomic_and" : { "result" : "anyvector", "arguments" : ["anyvector","anyint",0,0], "attributes" : "None"}, - "svm_atomic_or" : { "result" : "anyvector", "arguments" : ["anyvector","anyint",0,0], "attributes" : "None"}, - "svm_atomic_xor" : { "result" : "anyvector", "arguments" : ["anyvector","anyint",0,0], "attributes" : "None"}, - "svm_atomic_imin" : { "result" : "anyvector", "arguments" : ["anyvector","anyint",0,0], "attributes" : "None"}, - "svm_atomic_imax" : { "result" : "anyvector", "arguments" : ["anyvector","anyint",0,0], "attributes" : "None"}, + "svm_atomic_add" : { "result" : "anyvector", + "arguments" : ["anyvector","anyint",0,0], + "attributes" : "None" + }, + "svm_atomic_sub" : { "result" : "anyvector", + "arguments" : ["anyvector","anyint",0,0], + "attributes" : "None" + }, + "svm_atomic_min" : { "result" : "anyvector", + "arguments" : ["anyvector","anyint",0,0], + "attributes" : "None" + }, + "svm_atomic_max" : { "result" : "anyvector", + "arguments" : ["anyvector","anyint",0,0], + "attributes" : "None" + }, + "svm_atomic_xchg" : { "result" : "anyvector", + "arguments" : ["anyvector","anyint",0,0], + "attributes" : "None" + }, + "svm_atomic_and" : { "result" : "anyvector", + "arguments" : ["anyvector","anyint",0,0], + "attributes" : "None" + }, + "svm_atomic_or" : { "result" : "anyvector", + "arguments" : ["anyvector","anyint",0,0], + "attributes" : "None" + }, + "svm_atomic_xor" : { "result" : "anyvector", + "arguments" : ["anyvector","anyint",0,0], + "attributes" : "None" + }, + "svm_atomic_imin" : { "result" : "anyvector", + "arguments" : ["anyvector","anyint",0,0], + "attributes" : "None" + }, + "svm_atomic_imax" : { "result" : "anyvector", + "arguments" : ["anyvector","anyint",0,0], + "attributes" : "None" + }, ### ``llvm.genx.svm.atomic.*...`` : vISA SVM_ATOMIC with inc/dec ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2464,8 +3205,14 @@ ### Predicate, element offset and the return value must have the same vector ### width, which must be 1, 2, 4 or 8. ### - "svm_atomic_inc" : { "result" : "anyvector", "arguments" : ["anyvector","anyint",0], "attributes" : "None"}, - "svm_atomic_dec" : { "result" : "anyvector", "arguments" : ["anyvector","anyint",0], "attributes" : "None"}, + "svm_atomic_inc" : { "result" : "anyvector", + "arguments" : ["anyvector","anyint",0], + "attributes" : "None" + }, + "svm_atomic_dec" : { "result" : "anyvector", + "arguments" : ["anyvector","anyint",0], + "attributes" : "None" + }, ### ``llvm.genx.svm.atomic.cmpxchg...`` : vISA SVM_ATOMIC CMPXCHG instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2481,7 +3228,10 @@ ### Predicate, element offset, src0, src1, and the return value must all have ### the same vector width, which must be 1, 2, 4 or 8. ### - "svm_atomic_cmpxchg" : { "result" : "anyvector", "arguments" : ["anyvector","anyint",0,0,0], "attributes" : "None"}, + "svm_atomic_cmpxchg" : { "result" : "anyvector", + "arguments" : ["anyvector","anyint",0,0,0], + "attributes" : "None" + }, ### ``llvm.genx.svm.atomic.*...`` : vISA SVM_ATOMIC with binary operator ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2498,8 +3248,14 @@ ### Predicate, element offset, src, and the return value must all have the ### same vector width, which must be 1, 2, 4, or 8. ### - "svm_atomic_fmin" : { "result" : "anyvector", "arguments" : ["anyvector","anyint",0,0], "attributes" : "None"}, - "svm_atomic_fmax" : { "result" : "anyvector", "arguments" : ["anyvector","anyint",0,0], "attributes" : "None"}, + "svm_atomic_fmin" : { "result" : "anyvector", + "arguments" : ["anyvector","anyint",0,0], + "attributes" : "None" + }, + "svm_atomic_fmax" : { "result" : "anyvector", + "arguments" : ["anyvector","anyint",0,0], + "attributes" : "None" + }, ### ``llvm.genx.svm.atomic.fcmpwr...`` : vISA SVM_ATOMIC FCMPWR instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2515,7 +3271,10 @@ ### Predicate, element offset, src0, src1, and the return value must all have ### the same vector width, which must be 1, 2, 4 or 8. ### - "svm_atomic_fcmpwr" : { "result" : "anyvector", "arguments" : ["anyvector","anyint",0,0,0], "attributes" : "None"}, + "svm_atomic_fcmpwr" : { "result" : "anyvector", + "arguments" : ["anyvector","anyint",0,0,0], + "attributes" : "None" + }, ### ``llvm.genx.load..`` : vISA LOAD (sampler load) instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2542,7 +3301,10 @@ ### ### The element type of the return value must be i32 or float. ### - "load" : { "result" : "anyvector", "arguments" : ["int","int","anyint",1,1], "attributes" : "ReadMem"}, + "load" : { "result" : "anyvector", + "arguments" : ["int","int","anyint",1,1], + "attributes" : "ReadMem" + }, ### ``llvm.genx.sample..`` : vISA SAMPLE instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2570,7 +3332,10 @@ ### ### The element type of the return value must be i32 or float. ### - "sample" : { "result" : "anyvector", "arguments" : ["int","int","int","anyfloat",1,1], "attributes" : "ReadMem"}, + "sample" : { "result" : "anyvector", + "arguments" : ["int","int","int","anyfloat",1,1], + "attributes" : "ReadMem" + }, ### ``llvm.genx.sample..unorm`` : vISA SAMPLE_UNORM instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2590,7 +3355,10 @@ ### The number of 0 bits in that lower 4 bits of the channel mask arg is the ### number of channels to read per element. ### - "sample_unorm" : { "result" : "anyvector", "arguments" : ["int","int","int","float","float","float","float"], "attributes" : "ReadMem"}, + "sample_unorm" : { "result" : "anyvector", + "arguments" : ["int","int","int","float","float","float","float"], + "attributes" : "ReadMem" + }, ### ``llvm.genx.3d.sample......`` : vISA 3D_SAMPLE instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2605,7 +3373,10 @@ ### ### * Return value: the data read ### - "3d_sample" : { "result" : "anyvector", "arguments" : ["int","anyvector","int","short","int","int","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector"], "attributes" : "ReadMem"}, + "3d_sample" : { "result" : "anyvector", + "arguments" : ["int","anyvector","int","short","int","int","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector"], + "attributes" : "ReadMem" + }, ### ``llvm.genx.3d.load......`` : vISA 3D_LOAD instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2619,7 +3390,10 @@ ### ### * Return value: the data read ### - "3d_load" : { "result" : "anyvector", "arguments" : ["int","anyvector","int","short","int","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector"], "attributes" : "ReadMem"}, + "3d_load" : { "result" : "anyvector", + "arguments" : ["int","anyvector","int","short","int","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector","anyvector"], + "attributes" : "ReadMem" + }, ### ``llvm.genx.avs.`` : vISA AVS instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2647,44 +3421,65 @@ ### ### SIMD Control Flow: channel enable is ignored. ### - "avs" : { "result" : "anyvector", "arguments" : ["int","int","int","float","float","float","float","float","int","int","int","float","int","char"], "attributes" : "ReadMem"}, + "avs" : { "result" : "anyvector", + "arguments" : ["int","int","int","float","float","float","float","float","int","int","int","float","int","char"], + "attributes" : "ReadMem" + }, ### ``llvm.genx.barrier`` : vISA BARRIER instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ### - "barrier" : { "result" : "void", "arguments" : [], "attributes" : "Convergent"}, + "barrier" : { "result" : "void", + "arguments" : [], + "attributes" : "Convergent" + }, ### ``llvm.genx.sbarrier`` : vISA SBARRIER instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ### ### * arg0: i8 signal flag, constant ### - "sbarrier" : { "result" : "void", "arguments" : ["char"], "attributes" : "Convergent"}, + "sbarrier" : { "result" : "void", + "arguments" : ["char"], + "attributes" : "Convergent" + }, ### ``llvm.genx.cache.flush`` : vISA CACHE_FLUSH instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ### - "cache_flush" : { "result" : "void", "arguments" : [], "attributes" : "None"}, + "cache_flush" : { "result" : "void", + "arguments" : [], + "attributes" : "None" + }, ### ``llvm.genx.fence`` : vISA FENCE instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ### ### * arg0: i8 mask, constant ### - "fence" : { "result" : "void", "arguments" : ["char"], "attributes" : "None"}, + "fence" : { "result" : "void", + "arguments" : ["char"], + "attributes" : "None" + }, ### ``llvm.genx.wait`` : vISA WAIT instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ### ### * arg0: i8 thread mask ### - "wait" : { "result" : "void", "arguments" : ["char"], "attributes" : "None"}, + "wait" : { "result" : "void", + "arguments" : ["char"], + "attributes" : "None" + }, ### ``llvm.genx.yield`` : vISA YIELD instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ### - "yield" : { "result" : "void", "arguments" : [], "attributes" : "None"}, + "yield" : { "result" : "void", + "arguments" : [], + "attributes" : "None" + }, ### ``llvm.genx.raw.send...`` : vISA RAW_SEND instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2717,7 +3512,10 @@ ### predicatable. For a predicatable message, it must be a vector of i1 with ### width determining the execution size. ### - "raw_send" : { "result" : "anyvector", "arguments" : ["int","anyint","int","int","anyvector",0], "attributes" : "None"}, + "raw_send" : { "result" : "anyvector", + "arguments" : ["int","anyint","int","int","anyvector",0], + "attributes" : "None" + }, ### ``llvm.genx.raw.send.noresult..`` : vISA RAW_SEND instruction with no result ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2739,7 +3537,10 @@ ### predicatable. For a predicatable message, it must be a vector of i1 with ### width determining the execution size. ### - "raw_send_noresult" : { "result" : "void", "arguments" : ["int","anyint","int","int","anyvector"], "attributes" : "None"}, + "raw_send_noresult" : { "result" : "void", + "arguments" : ["int","anyint","int","int","anyvector"], + "attributes" : "None" + }, ### ``llvm.genx.raw.sends....`` : vISA RAW_SENDS instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2775,7 +3576,10 @@ ### predicatable. For a predicatable message, it must be a vector of i1 with ### width determining the execution size. ### - "raw_sends" : { "result" : "anyvector", "arguments" : ["int","anyint","char","int","int","anyvector","anyvector",0], "attributes" : "None"}, + "raw_sends" : { "result" : "anyvector", + "arguments" : ["int","anyint","char","int","int","anyvector","anyvector",0], + "attributes" : "None" + }, ### ``llvm.genx.raw.sends.noresult...`` : vISA RAW_SENDS instruction with no result ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2801,7 +3605,10 @@ ### predicatable. For a predicatable message, it must be a vector of i1 with ### width determining the execution size. ### - "raw_sends_noresult" : { "result" : "void", "arguments" : ["int","anyint","char","int","int","anyvector","anyvector"], "attributes" : "None"}, + "raw_sends_noresult" : { "result" : "void", + "arguments" : ["int","anyint","char","int","int","anyvector","anyvector"], + "attributes" : "None" + }, ### ``llvm.genx.raw.send2...`` : vISA RAW_SEND instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2822,7 +3629,10 @@ ### ### This intrinsic supports full encoding of the vISA raw_send instruction. ### - "raw_send2" : { "result" : "anyvector", "arguments" : ["char","char","anyvector","char","char","char","int","int","anyvector",0], "attributes" : "None"}, + "raw_send2" : { "result" : "anyvector", + "arguments" : ["char","char","anyvector","char","char","char","int","int","anyvector",0], + "attributes" : "None" + }, ### ``llvm.genx.raw.send2.noresult..`` : vISA RAW_SEND instruction with no result ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2841,7 +3651,10 @@ ### ### This intrinsic supports full encoding of the vISA raw_send instruction with no result. ### - "raw_send2_noresult" : { "result" : "void", "arguments" : ["char","char","anyvector","char","char","int","int","anyvector"], "attributes" : "None"}, + "raw_send2_noresult" : { "result" : "void", + "arguments" : ["char","char","anyvector","char","char","int","int","anyvector"], + "attributes" : "None" + }, ### ``llvm.genx.raw.sends2....`` : vISA RAW_SENDS instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2863,7 +3676,10 @@ ### ### This intrinsic supports full encoding of the vISA raw_sends instruction. ### - "raw_sends2" : { "result" : "anyvector", "arguments" : ["char","char","anyvector","char","char","char","char","int","int","anyvector","anyvector",0], "attributes" : "None"}, + "raw_sends2" : { "result" : "anyvector", + "arguments" : ["char","char","anyvector","char","char","char","char","int","int","anyvector","anyvector",0], + "attributes" : "None" + }, ### ``llvm.genx.raw.sends2.noresult...`` : vISA RAW_SENDS instruction with no result ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2882,7 +3698,10 @@ ### ### This intrinsic supports full encoding of the vISA raw_sends instruction with no result. ### - "raw_sends2_noresult" : { "result" : "void", "arguments" : ["char","char","anyvector","char","char","char","int","int","anyvector","anyvector"], "attributes" : "None"}, + "raw_sends2_noresult" : { "result" : "void", + "arguments" : ["char","char","anyvector","char","char","char","int","int","anyvector","anyvector"], + "attributes" : "None" + }, ## --------------------------- ### Video Analytics Instrinsics @@ -2899,7 +3718,10 @@ ### ### * Return value: v64i16 or v16i16 matrix, depending on properties value ### - "va_convolve2d" : { "result" : "anyint", "arguments" : ["int","int","float","float","int"], "attributes" : "ReadMem"}, + "va_convolve2d" : { "result" : "anyint", + "arguments" : ["int","int","float","float","int"], + "attributes" : "ReadMem" + }, ### ``llvm.genx.va.hdc.convolve2d`` vISA VA HDC 2d Convolve instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2913,7 +3735,10 @@ ### * arg6: i16 destination surface x-offset ### * arg7: i16 destination surface y-offset ### - "va_hdc_convolve2d" : { "result" : "void", "arguments" : ["int","int","float","float","int","int","short","short"], "attributes" : "None"}, + "va_hdc_convolve2d" : { "result" : "void", + "arguments" : ["int","int","float","float","int","int","short","short"], + "attributes" : "None" + }, ### ``llvm.genx.va.erode.`` vISA VA Erode instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2926,7 +3751,10 @@ ### ### * Return value: vXi32 ### - "va_erode" : { "result" : "anyint", "arguments" : ["int","int","float","float","int"], "attributes" : "ReadMem"}, + "va_erode" : { "result" : "anyint", + "arguments" : ["int","int","float","float","int"], + "attributes" : "ReadMem" + }, ### ``llvm.genx.va.hdc.erode`` vISA VA HDC Erode instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2939,7 +3767,10 @@ ### * arg5: i16 destination surface x-offset ### * arg6: i16 destination surface y-offset ### - "va_hdc_erode" : { "result" : "void", "arguments" : ["int","int","float","float","int","short","short"], "attributes" : "None"}, + "va_hdc_erode" : { "result" : "void", + "arguments" : ["int","int","float","float","int","short","short"], + "attributes" : "None" + }, ### ``llvm.genx.va.dilate.`` vISA VA Dilate instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2952,7 +3783,10 @@ ### ### * Return value: vXi32 ### - "va_dilate" : { "result" : "anyint", "arguments" : ["int","int","float","float","int"], "attributes" : "ReadMem"}, + "va_dilate" : { "result" : "anyint", + "arguments" : ["int","int","float","float","int"], + "attributes" : "ReadMem" + }, ### ``llvm.genx.va.hdc.dilate`` vISA VA HDC Dilate instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2965,7 +3799,10 @@ ### * arg5: i16 destination surface x-offset ### * arg6: i16 destination surface y-offset ### - "va_hdc_dilate" : { "result" : "void", "arguments" : ["int","int","float","float","int","short","short"], "attributes" : "None"}, + "va_hdc_dilate" : { "result" : "void", + "arguments" : ["int","int","float","float","int","short","short"], + "attributes" : "None" + }, ### ``llvm.genx.va.minmax.`` vISA MinMax instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2977,7 +3814,10 @@ ### ### * Return: v32i8 or v16i16 depending on the surface format ### - "va_minmax" : { "result" : "anyint", "arguments" : ["int","float","float","int"], "attributes" : "ReadMem"}, + "va_minmax" : { "result" : "anyint", + "arguments" : ["int","float","float","int"], + "attributes" : "ReadMem" + }, ### ``llvm.genx.va.minmax.filter.`` vISA MinMax Filter instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2992,7 +3832,10 @@ ### ### * Return: vXi8 or vXi16 depending on return data size and format ### - "va_minmax_filter" : { "result" : "anyint", "arguments" : ["int","int","float","float","int","int","int"], "attributes" : "ReadMem"}, + "va_minmax_filter" : { "result" : "anyint", + "arguments" : ["int","int","float","float","int","int","int"], + "attributes" : "ReadMem" + }, ### ``llvm.genx.va.hdc.minmax.filter`` vISA HDC MinMax Filter instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3007,7 +3850,10 @@ ### * arg7: i16 destination surface x-offset ### * arg8: i16 destination surface y-offset ### - "va_hdc_minmax_filter" : { "result" : "void", "arguments" : ["int","int","float","float","int","int","int","short","short"], "attributes" : "None"}, + "va_hdc_minmax_filter" : { "result" : "void", + "arguments" : ["int","int","float","float","int","int","int","short","short"], + "attributes" : "None" + }, ### ``llvm.genx.va.bool.centroid.`` vISA Boolean Centroid instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3020,7 +3866,10 @@ ### ### * Return: v16i8 or v16i16 depending on surface format ### - "va_bool_centroid" : { "result" : "anyint", "arguments" : ["int","float","float","char","char"], "attributes" : "ReadMem"}, + "va_bool_centroid" : { "result" : "anyint", + "arguments" : ["int","float","float","char","char"], + "attributes" : "ReadMem" + }, ### ``llvm.genx.va.centroid.`` vISA Centroid instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3032,7 +3881,10 @@ ### ### * Return: v32i32 ### - "va_centroid" : { "result" : "anyint", "arguments" : ["int","float","float","char"], "attributes" : "ReadMem"}, + "va_centroid" : { "result" : "anyint", + "arguments" : ["int","float","float","char"], + "attributes" : "ReadMem" + }, ### ``llvm.genx.va.1d.convolve.horizontal.`` vISA 1d convolve horizontal instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3045,7 +3897,10 @@ ### ### * Return: v16i16 or v64i16 depending on mode ### - "va_1d_convolve_horizontal" : { "result" : "anyint", "arguments" : ["int","int","float","float","int"], "attributes" : "ReadMem"}, + "va_1d_convolve_horizontal" : { "result" : "anyint", + "arguments" : ["int","int","float","float","int"], + "attributes" : "ReadMem" + }, ### ``llvm.genx.va.hdc.1d.convolve.horizontal`` vISA HDC 1d convolve horizontal instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3059,7 +3914,10 @@ ### * arg6: i16 destination surface x-offset ### * arg7: i16 destination surface y-offset ### - "va_hdc_1d_convolve_horizontal" : { "result" : "void", "arguments" : ["int","int","float","float","int","int","short","short"], "attributes" : "None"}, + "va_hdc_1d_convolve_horizontal" : { "result" : "void", + "arguments" : ["int","int","float","float","int","int","short","short"], + "attributes" : "None" + }, ### ``llvm.genx.va.1d.convolve.vertical.`` vISA 1d convolve vertical instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3072,7 +3930,10 @@ ### ### * Return: v16i16 or v64i16 depending on mode ### - "va_1d_convolve_vertical" : { "result" : "anyint", "arguments" : ["int","int","float","float","int"], "attributes" : "ReadMem"}, + "va_1d_convolve_vertical" : { "result" : "anyint", + "arguments" : ["int","int","float","float","int"], + "attributes" : "ReadMem" + }, ### ``llvm.genx.va.hdc.1d.convolve.vertical`` vISA HDC 1d convolve vertical instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3086,7 +3947,10 @@ ### * arg6: i16 destination surface x-offset ### * arg7: i16 destination surface y-offset ### - "va_hdc_1d_convolve_vertical" : { "result" : "void", "arguments" : ["int","int","float","float","int","int","short","short"], "attributes" : "None"}, + "va_hdc_1d_convolve_vertical" : { "result" : "void", + "arguments" : ["int","int","float","float","int","int","short","short"], + "attributes" : "None" + }, ### ``llvm.genx.va.1pixel.convolve..`` vISA 1 Pixel Convolve instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3100,7 +3964,10 @@ ### ### * Return: v64i16 or v16i16 depending on mode. ### - "va_1pixel_convolve" : { "result" : "anyint", "arguments" : ["int","int","float","float","int","anyint"], "attributes" : "ReadMem"}, + "va_1pixel_convolve" : { "result" : "anyint", + "arguments" : ["int","int","float","float","int","anyint"], + "attributes" : "ReadMem" + }, ### ``llvm.genx.va.hdc.1pixel.convolve`` vISA HDC 1 Pixel Convolve instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3115,7 +3982,10 @@ ### * arg7: i16 destination surface x-offset ### * arg8: i16 destination surface y-offset ### - "va_hdc_1pixel_convolve" : { "result" : "void", "arguments" : ["int","int","float","float","int","anyint","int","short","short"], "attributes" : "None"}, + "va_hdc_1pixel_convolve" : { "result" : "void", + "arguments" : ["int","int","float","float","int","anyint","int","short","short"], + "attributes" : "None" + }, ### ``llvm.genx.va.1pixel.convolve.1x1mode.`` vISA 1 Pixel Convolve (1x1 mode) instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3127,7 +3997,10 @@ ### ### * Return: v64i16 or v16i16 depending on mode. ### - "va_1pixel_convolve_1x1mode" : { "result" : "anyint", "arguments" : ["int","int","float","float"], "attributes" : "ReadMem"}, + "va_1pixel_convolve_1x1mode" : { "result" : "anyint", + "arguments" : ["int","int","float","float"], + "attributes" : "ReadMem" + }, ### ``llvm.genx.va.lbp.creation.`` vISA LBP Creation instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3139,7 +4012,10 @@ ### ### * Return: v64i8 or v128i8 depending on mode ### - "va_lbp_creation" : { "result" : "anyint", "arguments" : ["int","float","float","int"], "attributes" : "ReadMem"}, + "va_lbp_creation" : { "result" : "anyint", + "arguments" : ["int","float","float","int"], + "attributes" : "ReadMem" + }, ### ``llvm.genx.va.hdc.lbp.creation`` vISA HDC LBP Creation instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3152,7 +4028,10 @@ ### * arg5: i16 destination surface x-offset ### * arg6: i16 destination surface y-offset ### - "va_hdc_lbp_creation" : { "result" : "void", "arguments" : ["int","float","float","int","int","short","short"], "attributes" : "None"}, + "va_hdc_lbp_creation" : { "result" : "void", + "arguments" : ["int","float","float","int","int","short","short"], + "attributes" : "None" + }, ### ``llvm.genx.va.lbp.correlation.`` vISA LBP Correlation instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3164,7 +4043,10 @@ ### ### * Return: v64i8 ### - "va_lbp_correlation" : { "result" : "anyint", "arguments" : ["int","float","float","short"], "attributes" : "ReadMem"}, + "va_lbp_correlation" : { "result" : "anyint", + "arguments" : ["int","float","float","short"], + "attributes" : "ReadMem" + }, ### ``llvm.genx.va.hdc.lbp.correlation`` vISA HDC LBP Correlation instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3177,7 +4059,10 @@ ### * arg5: i16 destination surface x-offset ### * arg6: i16 destination surface y-offset ### - "va_hdc_lbp_correlation" : { "result" : "void", "arguments" : ["int","float","float","short","int","short","short"], "attributes" : "None"}, + "va_hdc_lbp_correlation" : { "result" : "void", + "arguments" : ["int","float","float","short","int","short","short"], + "attributes" : "None" + }, ### ``llvm.genx.va.correlation.search.`` vISA Correlation Search instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3194,7 +4079,10 @@ ### ### * Return: vXi32 ### - "va_correlation_search" : { "result" : "anyint", "arguments" : ["int","float","float","float","float","char","char","char","char"], "attributes" : "ReadMem"}, + "va_correlation_search" : { "result" : "anyint", + "arguments" : ["int","float","float","float","float","char","char","char","char"], + "attributes" : "ReadMem" + }, ### ``llvm.genx.va.flood.fill..`` vISA Flood Fill instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3207,7 +4095,10 @@ ### ### * Return: v8i16 ### - "va_flood_fill" : { "result" : "anyint", "arguments" : ["char","anyint","short","short","short"], "attributes" : "ReadMem"}, + "va_flood_fill" : { "result" : "anyint", + "arguments" : ["char","anyint","short","short","short"], + "attributes" : "ReadMem" + }, ##-------------------------------------------------------------------- ### CM codegen internal intrinsics @@ -3225,7 +4116,10 @@ ### reduction functions (cm_sum etc) whose behavior is sensitive to the ### surrounding SIMD CF context. It is lowered by the CMSimdCFLowering pass. ### - "simdcf_predicate" : { "result" : "anyvector", "arguments" : [0,0], "attributes" : "None"}, + "simdcf_predicate" : { "result" : "anyvector", + "arguments" : [0,0], + "attributes" : "None" + }, ### llvm.genx.simdcf.any. : simd cf marker intrinsic. ### @@ -3239,7 +4133,10 @@ ### This is generated by clang codegen in the implementation of SIMD control ### flow, and lowered by the CMSimdCFLowering pass. ### - "simdcf_any" : { "result" : "bool", "arguments" : ["anyvector"], "attributes" : "None"}, + "simdcf_any" : { "result" : "bool", + "arguments" : ["anyvector"], + "attributes" : "None" + }, ### ``llvm.genx.unmask.begin`` : simd-unmask region begin ### @@ -3250,7 +4147,10 @@ ### the old mask in a temp. ### this intrinsic will be replaced by genx.simdcf.unmask by SimdCFLowering ### - "unmask_begin" : { "result" : "int", "arguments" : [], "attributes" : "WriteMem,SideEffects"}, + "unmask_begin" : { "result" : "int", + "arguments" : [], + "attributes" : "WriteMem,SideEffects" + }, ### ``llvm.genx.unmask.end`` : simd-unmask region end ### @@ -3261,7 +4161,10 @@ ### region, set execution mask back using the temp value from unmask-begin. ### this intrinsic will be replaced by genx.simdcf.remask by SimdCFLowering ### - "unmask_end" : { "result" : "void", "arguments" : ["int"], "attributes" : "WriteMem,SideEffects"}, + "unmask_end" : { "result" : "void", + "arguments" : ["int"], + "attributes" : "WriteMem,SideEffects" + }, ### ``llvm.genx.lane.id`` : implicit lane-id in the simd-fork statement ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3269,7 +4172,10 @@ ### ### * Return value: i32 ### - "lane_id" : { "result" : "int", "arguments" : [], "attributes" : "NoMem"}, + "lane_id" : { "result" : "int", + "arguments" : [], + "attributes" : "NoMem" + }, ### ``llvm.genx.local.*.`` : read local ID register ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3282,9 +4188,18 @@ ### ### This is generated by clang codegen and lowered by CMImpParam. ### - "local_id" : { "result" : "anyvector", "arguments" : [], "attributes" : "NoMem"}, - "local_id16" : { "result" : "anyvector", "arguments" : [], "attributes" : "NoMem"}, - "local_size" : { "result" : "anyvector", "arguments" : [], "attributes" : "NoMem"}, + "local_id" : { "result" : "anyvector", + "arguments" : [], + "attributes" : "NoMem" + }, + "local_id16" : { "result" : "anyvector", + "arguments" : [], + "attributes" : "NoMem" + }, + "local_size" : { "result" : "anyvector", + "arguments" : [], + "attributes" : "NoMem" + }, ### ``llvm.genx.group.or.local.size`` : read local or group size register ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3296,7 +4211,10 @@ ### This is generated by CMImpParam. This is to match OpenCL thread ### payload layout. ### - "group_or_local_size" : { "result" : "int8", "arguments" : [], "attributes" : "NoMem"}, + "group_or_local_size" : { "result" : "int8", + "arguments" : [], + "attributes" : "NoMem" + }, ### ``llvm.genx.local.id.*`` : read local ID register ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3309,9 +4227,18 @@ ### This is generated by CMImpParam. This is to match OpenCL thread ### payload layout. ### - "local_id_x" : { "result" : "short8", "arguments" : [], "attributes" : "NoMem"}, - "local_id_y" : { "result" : "short8", "arguments" : [], "attributes" : "NoMem"}, - "local_id_z" : { "result" : "short8", "arguments" : [], "attributes" : "NoMem"}, + "local_id_x" : { "result" : "short8", + "arguments" : [], + "attributes" : "NoMem" + }, + "local_id_y" : { "result" : "short8", + "arguments" : [], + "attributes" : "NoMem" + }, + "local_id_z" : { "result" : "short8", + "arguments" : [], + "attributes" : "NoMem" + }, ### ``llvm.genx.group.count.`` : read group count register ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3321,7 +4248,10 @@ ### ### This is generated by clang codegen and lowered by CMImpParam. ### - "group_count" : { "result" : "anyvector", "arguments" : [], "attributes" : "NoMem"}, + "group_count" : { "result" : "anyvector", + "arguments" : [], + "attributes" : "NoMem" + }, ### ``llvm.genx.get.scoreboard.bti`` : get scoreboard surface implicit ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3330,7 +4260,10 @@ ### ###This is generated by clang codegen and lowered by CMImpParam. ### - "get_scoreboard_bti" : { "result" : "int", "arguments" : [], "attributes" : "NoMem"}, + "get_scoreboard_bti" : { "result" : "int", + "arguments" : [], + "attributes" : "NoMem" + }, ### ``llvm.genx.get.scoreboard.deltas`` : get scoreboard deltas ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3339,7 +4272,10 @@ ### ### This is generated by clang codegen and lowered by CMImpParam. ### - "get_scoreboard_deltas" : { "result" : "char16", "arguments" : [], "attributes" : "NoMem"}, + "get_scoreboard_deltas" : { "result" : "char16", + "arguments" : [], + "attributes" : "NoMem" + }, ### ``llvm.genx.get.scoreboard.depcnt`` : get the maximal scoreboard dependency count ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3348,7 +4284,10 @@ ### ### This is generated by clang codegen and lowered by CMImpParam. ### - "get_scoreboard_depcnt" : { "result" : "int", "arguments" : [], "attributes" : "NoMem"}, + "get_scoreboard_depcnt" : { "result" : "int", + "arguments" : [], + "attributes" : "NoMem" + }, ### ``llvm.genx.predefined.surface`` : get predefined surface ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3357,7 +4296,10 @@ ### ### This is generated by clang codegen when predefined surface is accessed. ### - "predefined_surface" : { "result" : "int", "arguments" : ["int"], "attributes" : "NoMem"}, + "predefined_surface" : { "result" : "int", + "arguments" : ["int"], + "attributes" : "NoMem" + }, ##-------------------------------------------------------------------- ### GenX backend internal intrinsics @@ -3379,8 +4321,14 @@ ### There are two variants simply because there is no way of saying here ### that an argument can have any scalar or vector type. ### - "constanti" : { "result" : "anyint", "arguments" : [0], "attributes" : "NoMem"}, - "constantf" : { "result" : "anyfloat", "arguments" : [0], "attributes" : "NoMem"}, + "constanti" : { "result" : "anyint", + "arguments" : [0], + "attributes" : "NoMem" + }, + "constantf" : { "result" : "anyfloat", + "arguments" : [0], + "attributes" : "NoMem" + }, ### llvm.genx.convert. : convert register category (non address) ### @@ -3398,7 +4346,10 @@ ### of a value of category other than general. Thus the input and output ### might be both the same category, but not both general. ### - "convert" : { "result" : "anyint", "arguments" : [0], "attributes" : "NoMem"}, + "convert" : { "result" : "anyint", + "arguments" : [0], + "attributes" : "NoMem" + }, ### llvm.genx.convert.addr. : convert to address register category ### @@ -3414,7 +4365,10 @@ ### stop the address conversion falling outside of the register into which it ### points to avoid going out of spec (bug 4395). ### - "convert_addr" : { "result" : "anyint", "arguments" : [0,"short"], "attributes" : "NoMem"}, + "convert_addr" : { "result" : "anyint", + "arguments" : [0,"short"], + "attributes" : "NoMem" + }, ### llvm.genx.constantpred. : load constant predicate (i1 or vector of i1) ### @@ -3426,7 +4380,10 @@ ### We could just use a bitcast, except that EarlyCSE follows ### GenXConstantMaterialization and it has a habit of putting the constant ### back in the wrregion. - "constantpred" : { "result" : "anyint", "arguments" : [0], "attributes" : "NoMem"}, + "constantpred" : { "result" : "anyint", + "arguments" : [0], + "attributes" : "NoMem" + }, ### llvm.genx.add.addr.. : add an offset onto an address register ### @@ -3439,7 +4396,10 @@ ### a region access, GenXCategoryConversion converts it into this intrinsic ### so that it will be considered an add to an address register. ### - "add_addr" : { "result" : "anyint", "arguments" : ["anyint",0], "attributes" : "NoMem"}, + "add_addr" : { "result" : "anyint", + "arguments" : ["anyint",0], + "attributes" : "NoMem" + }, ### llvm.genx.rdpredregion.. : read region at specified offset from a predicate ### @@ -3452,7 +4412,10 @@ ### in the return type, and must be 4, 8 or 16. ### The offset must be a multiple of the number of elements. ### - "rdpredregion" : { "result" : "anyint", "arguments" : ["anyint","int"], "attributes" : "NoMem"}, + "rdpredregion" : { "result" : "anyint", + "arguments" : ["anyint","int"], + "attributes" : "NoMem" + }, ### llvm.genx.wrpredregion.. : write region at specified offset into a predicate ### @@ -3466,7 +4429,10 @@ ### in the "subvector to write" arg, and must be 4, 8 or 16. ### The offset must be a multiple of the number of elements. ### - "wrpredregion" : { "result" : "anyint", "arguments" : [0,"anyint","int"], "attributes" : "NoMem"}, + "wrpredregion" : { "result" : "anyint", + "arguments" : [0,"anyint","int"], + "attributes" : "NoMem" + }, ### llvm.genx.wrpredpredregion.. : predicated write region at specified offset ### into a predicate @@ -3486,7 +4452,10 @@ ### intrinsic is valid only if the predicate is an EM value, and the subvector ### operand is the result of a cmp (which is then baled in). ### - "wrpredpredregion" : { "result" : "anyint", "arguments" : [0,"anyint","int",0], "attributes" : "NoMem"}, + "wrpredpredregion" : { "result" : "anyint", + "arguments" : [0,"anyint","int",0], + "attributes" : "NoMem" + }, ### ``llvm.genx.wrconstregion....`` : write a constant region ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3515,7 +4484,10 @@ ### The operands are the same as llvm.genx.wrregion so it can mostly be handled ### by the same code as llvm.genx.wrregion. ### - "wrconstregion" : { "result" : "anyvector", "arguments" : [0,"anyvector","int","int","int","anyint","int","anyint"], "attributes" : "NoMem"}, + "wrconstregion" : { "result" : "anyvector", + "arguments" : [0,"anyvector","int","int","int","anyint","int","anyint"], + "attributes" : "NoMem" + }, ### ``llvm.genx.output`` : Mark output arguments ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3526,7 +4498,10 @@ ### This intrinsic call only extends the live range of marked arguments and ### emits no code. ### - "output" : { "result" : "void", "arguments" : ["vararg"], "attributes" : "None"}, + "output" : { "result" : "void", + "arguments" : ["vararg"], + "attributes" : "None" + }, ### ``llvm.genx.output.1.`` : Mark output argument ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3539,7 +4514,10 @@ ### This intrinsic call only extends the live range of marked argument and ### emits no code. ### - "output_1" : { "result" : "void", "arguments" : ["any"], "attributes" : "None"}, + "output_1" : { "result" : "void", + "arguments" : ["any"], + "attributes" : "None" + }, ## ``llvm.genx.print.buffer`` : read stateless pointer to print buffer ## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3549,7 +4527,10 @@ ## ## this is generated by clang codegen and lowered by cmimpparam. ## - "print_buffer" : { "result" : "long", "arguments" : [], "attributes" : "None"}, + "print_buffer" : { "result" : "long", + "arguments" : [], + "attributes" : "None" + }, ## ``llvm.genx.print.format.index`` : add printf format string to collection ## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3559,7 +4540,10 @@ ## ## * Return value: the vector value read ## - "print_format_index" : { "result" : "int", "arguments" : ["anyptr"], "attributes" : "NoMem"}, + "print_format_index" : { "result" : "int", + "arguments" : ["anyptr"], + "attributes" : "NoMem" + }, ## ``llvm.genx.address.convert`` : convert dataport address to integer ## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3573,7 +4557,10 @@ ## used across all memory instructions. This is needed to encode ## SPIRV with appropriate types for kernel arguments. ## - "address_convert" : { "result" : "anyint", "arguments" : ["anyptr"], "attributes" : "NoMem"}, + "address_convert" : { "result" : "anyint", + "arguments" : ["anyptr"], + "attributes" : "NoMem" + }, ## ``llvm.genx.gaddr`` : take an address of a global variable ## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3585,7 +4572,10 @@ ## ## * Return value: i64/i32 (depending on data layout) value of pointer ## - "gaddr" : { "result" : "anyint", "arguments" : ["anyptr"], "attributes" : "NoMem"}, + "gaddr" : { "result" : "anyint", + "arguments" : ["anyptr"], + "attributes" : "NoMem" + }, ## ``llvm.genx.jump.table`` : CMC internal, no VISA ## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3599,5 +4589,8 @@ ## will be used by visa switchjmp as index. Return value and arg1-N are ## used to make ir semantically legal. ## - "jump_table" : { "result" : "anyptr", "arguments" : ["anyint", "vararg"], "attributes" : "NoMem"} + "jump_table" : { "result" : "anyptr", + "arguments" : ["anyint", "vararg"], + "attributes" : "NoMem" + } } From efec192d98e6d8ad611025d2cefd7a31cbc1d44b Mon Sep 17 00:00:00 2001 From: y Date: Wed, 23 Jun 2021 12:09:32 +0000 Subject: [PATCH 16/81] Add new field to vc-intrinsics. Now every intrinsic has list of suported platforms. --- .../llvm/GenXIntrinsics/GenXIntrinsics.h | 4 + .../GenXIntrinsics/Intrinsic_definitions.py | 11 +++ .../include/llvm/GenXIntrinsics/Intrinsics.py | 81 ++++++++++++++++++- .../lib/GenXIntrinsics/GenXIntrinsics.cpp | 11 +++ 4 files changed, 105 insertions(+), 2 deletions(-) diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h index 9f877fc8..304df669 100755 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h @@ -247,6 +247,10 @@ static inline FunctionType *getAnyType(LLVMContext &Context, unsigned id, return Intrinsic::getType(Context, (Intrinsic::ID)id, Tys); } +/// GenXIntrinsic::isSupportedPlatform(CPU, ID) - Return true if GenxIntrinsic +// is supported by current platform +bool isSupportedPlatform(const std::string &CPU, unsigned id); + /// GenXIntrinsic::isOverloadedArg(ID, ArgNum) - Return true if ArgNum /// in intrinsic overloaded bool isOverloadedArg(unsigned IntrinID, unsigned ArgNum); diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py index 6aae3169..43d427b4 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py @@ -51,6 +51,17 @@ # 1 - LLVMMatchType<1> # {int} - LLVMMatchType<{int}> +#------------ Supported platforms ---------------------- +# Every intrinsic has optinal field "platforms" : "CPU" +# CPU can be any from "platforms" in Intrinsics.py or "ALL" +# when field is absent - ALL by default +# additional commands : +# "CPU" = "-SKL" - unsupported since SKL +# "CPU" = "KBL+" - supported from KBL +# "CPU" = "~ICLLP" - unsupported on ICLLP +# CPU can be list: +# ["CNL+", "KBL"] - supported on KBL and all started from CNL +# ["ALL", "~TGLLP"] - supported everyvere except TGLLP Imported_Intrinsics = \ { diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py index a1c3417c..4a553e81 100755 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py @@ -94,6 +94,10 @@ "SideEffects": set(["NoUnwind"]), } +# order does really matter +platform_list = ["HSW", "BDW", "CHV", "SKL","BXT", "KBL", + "GLK", "CNL", "ICL", "ICLLP", "TGLLP", "DG1"] + def getAttributeList(Attrs): """ Takes a list of attribute names, calculates the union, @@ -299,7 +303,7 @@ def createOverloadTable(): isOverloadable = False genISA_Intrinsic = Intrinsics[ID_array[i]] for key in genISA_Intrinsic: - val = genISA_Intrinsic[key] + val = genISA_Intrinsic[key] if isinstance(val,list): for z in range(len(val)): if isinstance(val[z],int): @@ -549,6 +553,78 @@ def createAttributeTable(): "#endif // GET_INTRINSIC_ATTRIBUTES\n\n") f.close() +def platformExprProcess(curr_line,platf_expr,platforms): + platf_expr = platf_expr.strip() + # simple case + platf_id = platforms.get(platf_expr) + if platf_id is not None: + curr_line[platf_id] = 1; + # "platform+" case: + elif platf_expr[-1] == "+": + platf_id = platforms.get(platf_expr[:-1]) + if platf_id is None: + raise NameError("Error in platf in " + str(Intrinsics[ID_array[i]])) + for j in range(platf_id,len(platforms)): + curr_line[j] = 1; + # "-platform" case: + elif platf_expr[0] == "-": + platf_id = platforms.get(platf_expr[1:]) + if platf_id is None: + raise NameError("Error in platf in " + str(Intrinsics[ID_array[i]])) + for j in range(platf_id): + curr_line[j] = 1; + # "~platform" case + elif platf_expr[0] == "~": + platf_id = platforms.get(platf_expr[1:]) + if platf_id is None: + raise NameError("Error in platf in " + str(Intrinsics[ID_array[i]])) + curr_line[j] = 0; + elif platf_expr == "ALL": + curr_line = [1]*len(platforms) + else: + raise NameError("Error in platf in " + str(Intrinsics[ID_array[i]])) + + return curr_line + +def override_platform_name(platform): + return platform + +def createPlatformTable(): + f = open(outputFile,"a") + # platforms dict "platform" : number + platforms = { platform_list[i] : i for i in range(len(platform_list)) } + + # by default all platfroms are supported + support_matrix = [ [1]*len(platforms) for i in range(len(ID_array))] + + # fill support matrix + for i in range(len(ID_array)): + platf_expr = Intrinsics[ID_array[i]].get('platforms') + if platf_expr is None: + continue + curr_line = [0]*len(platforms) + if not isinstance(platf_expr,list): + platf_expr = [platf_expr] + for expr in platf_expr: + curr_line = platformExprProcess(curr_line,expr,platforms) + # swope line + support_matrix[i] = curr_line + + f.write("// Add list of supported intrinsics for each platform.\n" + "#ifdef GET_INTRINSIC_PLATFORMS\n" + "static const std::map> SupportedIntrinsics {\n") + transformed_matrix = [list(x) for x in zip(*support_matrix)] + for pl,ar in zip(platforms,transformed_matrix): + dump_ar = str(ar).replace("[", "{" ,1).replace("]", "}" ,1) + name = override_platform_name(pl) + wrstring = "{MANGLE(\"" + str(name) + "\") , " + str(dump_ar) + " },\n" + f.write(wrstring) + f.write("};\n") + f.write("#endif // GET_INTRINSIC_PLATFORMS\n") + f.close() + + def emitSuffix(): f = open(outputFile,"a") f.write("#if defined(_MSC_VER) && defined(setjmp_undefined_for_msvc)\n" @@ -558,7 +634,7 @@ def emitSuffix(): "#endif\n\n") f.close() -#main functions in order +# main functions in order emitPrefix() createTargetData() generateEnums() @@ -569,4 +645,5 @@ def emitSuffix(): sortedIntrinsicsOnLenth() createTypeTable() createAttributeTable() +createPlatformTable() emitSuffix() diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp index 1108111a..5dd95c40 100755 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp @@ -480,6 +480,17 @@ bool isOverloaded(GenXIntrinsic::ID id) { static StringRef GenXIntrinsicMDName{ "genx_intrinsic_id" }; +bool GenXIntrinsic::isSupportedPlatform(const std::string &CPU, unsigned id) { +#define GET_INTRINSIC_PLATFORMS +#include "llvm/GenXIntrinsics/GenXIntrinsicDescription.gen" +#undef GET_INTRINSIC_PLATFORMS + assert(SupportedIntrinsics.find(CPU) != SupportedIntrinsics.end() && + "Unknown Platform"); + assert(GenXIntrinsic::isGenXIntrinsic(id) && + "this function should be used only for GenXIntrinsics"); + return SupportedIntrinsics.at( + CPU)[id - GenXIntrinsic::ID::not_genx_intrinsic - 1]; +} /// Table of per-target intrinsic name tables. #define GET_INTRINSIC_TARGET_DATA From b976b830ddc48cff0e74fe35b15d3ee93518e9b7 Mon Sep 17 00:00:00 2001 From: Ivan Tetyushkin Date: Wed, 23 Jun 2021 13:43:15 +0000 Subject: [PATCH 17/81] introduce bf_cvt intrinsic --- .../llvm/GenXIntrinsics/Intrinsic_definitions.py | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py index 43d427b4..ee27b0c4 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py @@ -1786,6 +1786,22 @@ "attributes" : "NoMem" }, +### bf_cvt +### ^^^^^^ +### +### ``llvm.genx.bf.cvt..`` : bf_cvt instruction +### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +### * ``llvm.genx.bf.cvt`` : +### +### * arg0: first input, any scalar/vector bf/float type (overloaded) +### +### * Return value: result, must be float if arg0 is half, or half if arg0 is float. +### + "bf_cvt" : { "result" : "anyfloat", + "arguments" : ["anyfloat"], + "attributes" : "NoMem" + }, + ### xor ### ^^^ ### Intrinsic not needed; use LLVM IR Xor instruction From 6d29de3fa906619ad11533a4617fb52c52e1cccf Mon Sep 17 00:00:00 2001 From: lgotszal Date: Thu, 1 Jul 2021 06:44:35 +0000 Subject: [PATCH 18/81] update comment format of rst copyright headers --- GenXIntrinsics/docs/GenXLangRef.rst | 3 +-- GenXIntrinsics/docs/LangRefIndex.rst | 3 +-- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/GenXIntrinsics/docs/GenXLangRef.rst b/GenXIntrinsics/docs/GenXLangRef.rst index 77290ac2..63ecbf06 100644 --- a/GenXIntrinsics/docs/GenXLangRef.rst +++ b/GenXIntrinsics/docs/GenXLangRef.rst @@ -1,5 +1,4 @@ -.. - ========================== begin_copyright_notice ============================ +.. ========================= begin_copyright_notice ============================ Copyright (C) 2015-2021 Intel Corporation diff --git a/GenXIntrinsics/docs/LangRefIndex.rst b/GenXIntrinsics/docs/LangRefIndex.rst index 4f9682c2..6627dcf3 100644 --- a/GenXIntrinsics/docs/LangRefIndex.rst +++ b/GenXIntrinsics/docs/LangRefIndex.rst @@ -1,5 +1,4 @@ -.. - ========================== begin_copyright_notice ============================ +.. ========================= begin_copyright_notice ============================ Copyright (C) 2019-2021 Intel Corporation From d9ffe1f9cbe45b296f098669173bcaeff12bfe99 Mon Sep 17 00:00:00 2001 From: Aleksander Us Date: Wed, 7 Jul 2021 14:09:12 +0000 Subject: [PATCH 19/81] Add intrinsics for bindless buffers support write_predef_surface is main intrinsic to initialize %bss. Other intrinsics are duplicates of original intrinsics with ability to work with %bss variable. --- .../GenXIntrinsics/Intrinsic_definitions.py | 304 +++++++++++++++++- 1 file changed, 303 insertions(+), 1 deletion(-) diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py index ee27b0c4..d9f9ba41 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py @@ -4619,5 +4619,307 @@ "jump_table" : { "result" : "anyptr", "arguments" : ["anyint", "vararg"], "attributes" : "NoMem" - } + }, + +## ``llvm.genx.write.predef.surface`` : write predefined surface variable +## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +## +## * arg0: ptr predefined surface variable +## * arg1: i32 value to write +## +## This corresponds to MOVS visa instruction and utilizes technique of using +## global variable in LLVM IR for predefined surfaces. +## + "write_predef_surface" : { "result": "void", + "arguments" : ["anyptr", "int"], + "attributes" : "WriteMem", + }, + +## Internal VC memory intrinsics. +## These versions are supposed to use predefined visa variables like %bss. +## Intrinsics are supposed to be internal to VC backend. + +## ``llvm.genx.dword.atomic2.*.predef.surface`` : dword atomic with binary operator with predefined surface +## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +## * ``llvm.genx.dword.atomic2.add.predef.surface`` : vISA DWORD_ATOMIC ADD instruction +## * ``llvm.genx.dword.atomic2.sub.predef.surface`` : vISA DWORD_ATOMIC SUB instruction +## * ``llvm.genx.dword.atomic2.min.predef.surface`` : vISA DWORD_ATOMIC MIN instruction +## * ``llvm.genx.dword.atomic2.max.predef.surface`` : vISA DWORD_ATOMIC MAX instruction +## * ``llvm.genx.dword.atomic2.xchg.predef.surface`` : vISA DWORD_ATOMIC XCHG instruction +## * ``llvm.genx.dword.atomic2.and.predef.surface`` : vISA DWORD_ATOMIC AND instruction +## * ``llvm.genx.dword.atomic2.or.predef.surface`` : vISA DWORD_ATOMIC OR instruction +## * ``llvm.genx.dword.atomic2.xor.predef.surface`` : vISA DWORD_ATOMIC XOR instruction +## * ``llvm.genx.dword.atomic2.imin.predef.surface`` : vISA DWORD_ATOMIC IMIN instruction +## * ``llvm.genx.dword.atomic2.imax.predef.surface`` : vISA DWORD_ATOMIC IMAX instruction +## +## * (Exec_size inferred from element offset type) +## * arg0: vXi1 predicate (overloaded) +## * arg1: ptr predefined surface (overloaded) +## * arg2: vXi32 element offset in bytes (overloaded) +## * arg3: vXi32 src +## +## * Return value: vXi32 the old value read +## +## Predicate, element offset, src, and the return value must all have the +## same vector width, which must be 1, 8 or 16. +## + "dword_atomic2_add_predef_surface" : { "result" : "anyvector", + "arguments" : ["anyvector","anyptr","anyint",0], + "attributes" : "None", + }, + "dword_atomic2_sub_predef_surface" : { "result" : "anyvector", + "arguments" : ["anyvector","anyptr","anyint",0], + "attributes" : "None", + }, + "dword_atomic2_min_predef_surface" : { "result" : "anyvector", + "arguments" : ["anyvector","anyptr","anyint",0], + "attributes" : "None", + }, + "dword_atomic2_max_predef_surface" : { "result" : "anyvector", + "arguments" : ["anyvector","anyptr","anyint",0], + "attributes" : "None", + }, + "dword_atomic2_xchg_predef_surface" : { "result" : "anyvector", + "arguments" : ["anyvector","anyptr","anyint",0], + "attributes" : "None", + }, + "dword_atomic2_and_predef_surface" : { "result" : "anyvector", + "arguments" : ["anyvector","anyptr","anyint",0], + "attributes" : "None", + }, + "dword_atomic2_or_predef_surface" : { "result" : "anyvector", + "arguments" : ["anyvector","anyptr","anyint",0], + "attributes" : "None", + }, + "dword_atomic2_xor_predef_surface" : { "result" : "anyvector", + "arguments" : ["anyvector","anyptr","anyint",0], + "attributes" : "None", + }, + "dword_atomic2_imin_predef_surface" : { "result" : "anyvector", + "arguments" : ["anyvector","anyptr","anyint",0], + "attributes" : "None", + }, + "dword_atomic2_imax_predef_surface" : { "result" : "anyvector", + "arguments" : ["anyvector","anyptr","anyint",0], + "attributes" : "None", + }, + +## ``llvm.genx.dword.atomic2.*.predef.surface`` : dword atomic with fmin/fmax operation with predefined surface +## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +## * ``llvm.genx.dword.atomic2.fmin.predef.surface`` : vISA DWORD_ATOMIC FMIN instruction +## * ``llvm.genx.dword.atomic2.fmax.predef.surface`` : vISA DWORD_ATOMIC FMAX instruction +## +## * (Exec_size inferred from element offset type) +## * arg0: vXi1 predicate (overloaded) +## * arg1: ptr predefined surface (overloaded) +## * arg2: vXi32 element offset in bytes (overloaded) +## * arg3: vXfloat src +## +## * Return value: vXfloat the old value read +## +## Predicate, element offset, src, and the return value must all have the +## same vector width, which must be 1, 8 or 16. +## + "dword_atomic2_fmin_predef_surface" : { "result" : "anyvector", + "arguments" : ["anyvector","anyptr","anyint",0], + "attributes" : "None", + }, + "dword_atomic2_fmax_predef_surface" : { "result" : "anyvector", + "arguments" : ["anyvector","anyptr","anyint",0], + "attributes" : "None", + }, + +## ``llvm.genx.dword.atomic2.*.predef.surface`` : dword atomic with inc/dec operation with predefined surface +## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +## * ``llvm.genx.dword.atomic2.inc.predef.surface`` : vISA DWORD_ATOMIC INC instruction +## * ``llvm.genx.dword.atomic2.dec.predef.surface`` : vISA DWORD_ATOMIC DEC instruction +## +## * (Exec_size inferred from element offset type) +## * arg0: vXi1 predicate (overloaded) +## * arg1: ptr predefined surface (overloaded) +## * arg2: vXi32 element offset in bytes (overloaded) +## +## * Return value: vXi32 the old value read +## +## Predicate, element offset, src, and the return value must all have the +## same vector width, which must be 1, 8 or 16. +## + "dword_atomic2_inc_predef_surface" : { "result" : "anyvector", + "arguments" : ["anyvector","anyptr","anyint"], + "attributes" : "None", + }, + "dword_atomic2_dec_predef_surface" : { "result" : "anyvector", + "arguments" : ["anyvector","anyptr","anyint"], + "attributes" : "None", + }, + +## ``llvm.genx.dword.atomic2.cmpxchg.predef.surface`` : vISA DWORD_ATOMIC CMPXCHG instruction with predefined surface +## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +## +## * (Exec_size inferred from element offset type) +## * arg0: vXi1 predicate (overloaded) +## * arg1: ptr predefined surface (overloaded) +## * arg2: vXi32 element offset in bytes (overloaded) +## * arg3: vXi32 src0 +## * arg4: vXi32 src1 +## +## * Return value: vXi32 the old value read +## +## Predicate, element offset, src, and the return value must all have the +## same vector width, which must be 1, 8 or 16. +## + "dword_atomic2_cmpxchg_predef_surface" : { "result" : "anyvector", + "arguments" : ["anyvector","anyptr","anyint",0,0], + "attributes" : "None", + }, + +## ``llvm.genx.dword.atomic2.fcmpwr.predef.surface`` : vISA DWORD_ATOMIC FCMPWR instruction with predefined surface +## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +## +## * (Exec_size inferred from element offset type) +## * arg0: vXi1 predicate (overloaded) +## * arg1: ptr predefined surface (overloaded) +## * arg2: vXi32 element offset in bytes (overloaded) +## * arg3: vXfloat src0 +## * arg4: vXfloat src1 +## +## * Return value: vXfloat the old value read +## +## Predicate, element offset, src, and the return value must all have the +## same vector width, which must be 1, 8 or 16. +## + "dword_atomic2_fcmpwr_predef_surface" : { "result" : "anyvector", + "arguments" : ["anyvector","anyptr","anyint",0,0], + "attributes" : "None", + }, + +## ``llvm.genx.gather.masked.scaled2.predef.surface`` : vISA GATHER_SCALED instruction with predefined surface +## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +## +## * (Exec_size inferred from element offset type) +## * arg0: i32 log2 num blocks, constant (0/1/2 for num blocks 1/2/4) +## * arg1: i16 scale, constant +## * arg2: ptr predefined surface (overloaded) +## * arg3: i32 global offset in bytes +## * arg4: vXi32 element offset in bytes (overloaded) +## * arg5: vXi1 predicate (overloaded) +## +## * Return value: vXi32/float the data read +## + "gather_masked_scaled2_predef_surface" : { "result" : "anyvector", + "arguments" : ["int","short","anyptr","int","anyint","anyvector"], + "attributes" : "ReadMem", + }, + +## ``llvm.genx.gather4.masked.scaled2.predef.surface`` : vISA GATHER4_SCALED instruction with predefined surface +## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +## +## * (Exec_size inferred from element offset type) +## * arg0: i32 channel mask, constant +## * arg1: i16 scale, constant +## * arg2: ptr predefined surface (overloaded) +## * arg3: i32 global offset in bytes +## * arg4: vXi32 element offset in bytes +## * arg5: vXi1 predicate (overloaded) +## +## * Return value: vXi32/float the data read +## + "gather4_masked_scaled2_predef_surface" : { "result" : "anyvector", + "arguments" : ["int","short","anyptr","int","anyint","anyvector"], + "attributes" : "ReadMem", + }, + +## ``llvm.genx.scatter.scaled.predef.surface`` : vISA SCATTER_SCALED instruction with predefined surface +## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +## +## * (Exec_size inferred from element offset type) +## * arg0: vXi1 predicate (overloaded) +## * arg1: i32 log2 num blocks, constant (0/1/2 for num blocks 1/2/4) +## * arg2: i16 scale, constant +## * arg3: ptr predefined surface (overloaded) +## * arg4: i32 global offset in bytes +## * arg5: vXi32 element offset (overloaded) +## * arg6: data to write (overloaded) +## +## The vector width of the element offset arg is the number of elements to +## write, which must be power of 2 and less than or equal to 32. +## +## The predicate arg must have the same vector width. +## +## The data type to write must have UD, D or F type. For 1 and 2 byte (1 x num +## blocks) accesses the upper bytes will be ignored. +## + "scatter_scaled_predef_surface" : { "result" : "void", + "arguments" : ["anyvector","int","short","anyptr","int","anyint","anyvector"], + "attributes" : "None", + }, + +## ``llvm.genx.scatter4.scaled.predef.surface`` : vISA SCATTER4_SCALED instruction with predefined surface +## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +## +## * (Exec_size inferred from element offset type) +## * arg0: vXi1 predicate (overloaded) +## * arg1: i32 channel mask, constant +## * arg2: i16 scale, constant +## * arg3: ptr predefined surface (overloaded) +## * arg4: i32 global offset in bytes +## * arg5: vXi32 element offset in bytes (overloaded) +## * arg6: data to write (overloaded) +## +## The vector width of the element offset arg is the number of elements to +## write, which must be 8 or 16. +## The predicate arg must have the same vector width. +## The instruction writes up to 4 channels per element, with the lowest 4 +## bits of the channel mask arg giving the mask of channels _not_ to read. +## The number of 0 bits in that lower 4 bits of the channel mask arg is the +## number of channels to write per element. +## The channels to write must be contiguous and starting at channel 0. +## The vector width of the data to write must be the number of elements +## times the number of channels to write per element. +## The element type of the data to write must be i32 or float. +## + "scatter4_scaled_predef_surface" : { "result" : "void", + "arguments" : ["anyvector","int","short","anyptr","int","anyint","anyvector"], + "attributes" : "None", + }, + +## ``llvm.genx.oword.ld*.predef.surface`` : oword load instruction with predefined surface +## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +## * ``llvm.genx.oword.ld.predef.surface`` : vISA OWORD_LD instruction +## * ``llvm.genx.oword.ld.unaligned.predef.surface`` : vISA OWORD_LD_UNALIGNED instruction +## +## * (log2 number of owords inferred from return type) +## * arg0: i32 is_modified, constant +## * arg1: ptr predefined surface variable (overloaded) +## * arg2: i32 offset (in owords for .ld / in bytes for .ld.unaligned) +## +## * Return value: vXiN the data read. +## +## The byte size of the return type must be 16, 32, 64, or 128. +## + "oword_ld_predef_surface" : { "result" : "anyvector", + "arguments" : ["int", "anyptr", "int"], + "attributes": "ReadMem", + }, + + "oword_ld_unaligned_predef_surface" : { "result" : "anyvector", + "arguments": ["int", "anyptr", "int"], + "attributes" : "ReadMem", + }, + +## ``llvm.genx.oword.st.predef.surface`` : vISA OWORD_ST instruction with predefined surface +## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +## +## * (log2 number of owords inferred from return type) +## * arg0: ptr predefined surface variable (overloaded) +## * arg1: i32 offset (in owords) +## * arg2: data to write (overloaded) +## +## The byte size of the data to write must be 16, 32, 64, or 128. +## + "oword_st_predef_surface" : { "result" : "void", + "arguments" : ["anyptr", "int", "anyvector"], + "attributes" : "None", + }, + } From f45e04c6aa293d04da97f902aa9aa766a525e017 Mon Sep 17 00:00:00 2001 From: Dmitriy Drozdov Date: Tue, 20 Jul 2021 15:15:02 +0000 Subject: [PATCH 20/81] Introduce new vc intrinsic to access timestamp register --- .../llvm/GenXIntrinsics/Intrinsic_definitions.py | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py index d9f9ba41..3976e6fa 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py @@ -1897,6 +1897,19 @@ "attributes" : "None" }, +### ``llvm.genx.tm0.`` : read vISA v6 (%tm0) +### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +### +### * Return value: vxi32 the value read +### +### The vector width must be 8 +### +### + "tm0" : { "result" : "anyint", + "arguments" : [], + "attributes" : "SideEffects" + }, + ### ``llvm.genx.get.color`` : read color value of the thread origin ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ### From 63cbfe0b0d68fa0c2d66b8a4a676c2bb3f01facf Mon Sep 17 00:00:00 2001 From: lgotszal Date: Tue, 6 Jul 2021 10:55:54 +0000 Subject: [PATCH 21/81] update MIT copyright headers --- CMakeLists.txt | 20 +------------------ GenXIntrinsics/CMakeLists.txt | 20 +------------------ GenXIntrinsics/cmake/utils.cmake | 20 +------------------ GenXIntrinsics/docs/GenXLangRef.rst | 20 +------------------ GenXIntrinsics/docs/LangRefIndex.rst | 20 +------------------ GenXIntrinsics/docs/Makefile.sphinx | 20 +------------------ GenXIntrinsics/docs/ReadMe.txt | 20 +------------------ GenXIntrinsics/docs/conf.py | 20 +------------------ GenXIntrinsics/include/llvm/CMakeLists.txt | 20 +------------------ .../llvm/GenXIntrinsics/CMakeLists.txt | 20 +------------------ .../GenXIntrinsics/ConfigureVersionFile.cmake | 20 +------------------ .../llvm/GenXIntrinsics/GenXIntrOpts.h | 20 +------------------ .../llvm/GenXIntrinsics/GenXIntrinsicInst.h | 20 +------------------ .../llvm/GenXIntrinsics/GenXIntrinsics.h | 20 +------------------ .../llvm/GenXIntrinsics/GenXMetadata.h | 20 +------------------ .../GenXIntrinsics/GenXSPIRVReaderAdaptor.h | 20 +------------------ .../GenXIntrinsics/GenXSPIRVWriterAdaptor.h | 20 +------------------ .../llvm/GenXIntrinsics/GenXSimdCFLowering.h | 20 +------------------ .../include/llvm/GenXIntrinsics/GenXVersion.h | 20 +------------------ .../GenXIntrinsics/Intrinsic_definitions.py | 20 +------------------ .../include/llvm/GenXIntrinsics/Intrinsics.py | 20 +------------------ .../include/llvmVCWrapper/IR/DerivedTypes.h | 20 +------------------ .../include/llvmVCWrapper/IR/Function.h | 20 +------------------ .../include/llvmVCWrapper/IR/GlobalValue.h | 20 +------------------ .../include/llvmVCWrapper/IR/InstrTypes.h | 20 +------------------ .../include/llvmVCWrapper/IR/Instructions.h | 20 +------------------ .../include/llvmVCWrapper/IR/Intrinsics.h | 20 +------------------ .../include/llvmVCWrapper/Support/Alignment.h | 20 +------------------ GenXIntrinsics/lib/CMakeLists.txt | 20 +------------------ .../lib/GenXIntrinsics/AdaptorsCommon.h | 20 +------------------ .../lib/GenXIntrinsics/CMakeLists.txt | 20 +------------------ .../lib/GenXIntrinsics/GenXIntrinsics.cpp | 20 +------------------ .../GenXIntrinsics/GenXRestoreIntrAttr.cpp | 20 +------------------ .../GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp | 20 +------------------ .../GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp | 20 +------------------ .../lib/GenXIntrinsics/GenXSimdCFLowering.cpp | 20 +------------------ .../GenXSingleElementVectorUtil.cpp | 20 +------------------ .../GenXSingleElementVectorUtil.h | 20 +------------------ .../lib/GenXIntrinsics/GenXVersion.cpp | 20 +------------------ .../test/Adaptors/annot_mess_writer.ll | 20 +------------------ .../Adaptors/annotated_args_mixed_reader.ll | 20 +------------------ .../Adaptors/annotated_args_no_conv_reader.ll | 20 +------------------ .../Adaptors/annotated_args_no_conv_writer.ll | 20 +------------------ .../test/Adaptors/annotated_args_reader.ll | 20 +------------------ .../test/Adaptors/annotated_args_writer.ll | 20 +------------------ .../test/Adaptors/combined_args_reader.ll | 20 +------------------ .../test/Adaptors/combined_args_writer.ll | 20 +------------------ .../test/Adaptors/empty_kernel_writer.ll | 20 +------------------ .../test/Adaptors/no_vcfunction_reader.ll | 20 +------------------ .../test/Adaptors/non_global_ptr_reader.ll | 20 +------------------ .../Adaptors/old_decorated_args_reader.ll | 20 +------------------ .../test/Adaptors/plain_args_reader.ll | 20 +------------------ .../test/Adaptors/plain_args_writer.ll | 20 +------------------ .../test/Adaptors/sev_signature_reader.ll | 20 +------------------ .../test/Adaptors/sev_signature_writer.ll | 20 +------------------ .../test/Adaptors/surface_access_reader.ll | 20 +------------------ .../test/Adaptors/surface_access_writer.ll | 20 +------------------ .../test/Adaptors/unknown_arg_reader.ll | 20 +------------------ .../test/Adaptors/unknown_arg_writer.ll | 20 +------------------ GenXIntrinsics/test/CMakeLists.txt | 20 +------------------ GenXIntrinsics/test/Plugin/CMakeLists.txt | 20 +------------------ GenXIntrinsics/test/Plugin/Plugin.cpp | 20 +------------------ .../SimdCFLowering/bitcast_between_wrrs.ll | 20 +------------------ .../SimdCFLowering/predicate_masked_gather.ll | 20 +------------------ .../test/SimdCFLowering/replicate_mask.ll | 20 +------------------ .../replicate_mask_masked_gather4.ll | 20 +------------------ .../update_mask_masked_gather4.ll | 20 +------------------ GenXIntrinsics/test/lit.cfg.py | 20 +------------------ GenXIntrinsics/test/lit.site.cfg.py.in | 20 +------------------ GenXIntrinsics/unittests/CMakeLists.txt | 20 +------------------ .../unittests/GenXIntrinsics/CMakeLists.txt | 20 +------------------ .../GenXIntrinsics/GenXIntrinsicsTest.cpp | 20 +------------------ Readme.md | 20 +------------------ 73 files changed, 73 insertions(+), 1387 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index bb35d667..675fe5b4 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -2,26 +2,8 @@ # # Copyright (C) 2019-2021 Intel Corporation # -# Permission is hereby granted, free of charge, to any person obtaining a copy -# of this software and associated documentation files (the "Software"), -# to deal in the Software without restriction, including without limitation -# the rights to use, copy, modify, merge, publish, distribute, sublicense, -# and/or sell copies of the Software, and to permit persons to whom the -# Software is furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice (including the next -# paragraph) shall be included in all copies or substantial portions of the -# Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -# IN THE SOFTWARE. -# # SPDX-License-Identifier: MIT +# #============================ end_copyright_notice ============================= cmake_minimum_required(VERSION 3.13.4) diff --git a/GenXIntrinsics/CMakeLists.txt b/GenXIntrinsics/CMakeLists.txt index 1bd9896a..b9f1daee 100644 --- a/GenXIntrinsics/CMakeLists.txt +++ b/GenXIntrinsics/CMakeLists.txt @@ -2,26 +2,8 @@ # # Copyright (C) 2019-2021 Intel Corporation # -# Permission is hereby granted, free of charge, to any person obtaining a copy -# of this software and associated documentation files (the "Software"), -# to deal in the Software without restriction, including without limitation -# the rights to use, copy, modify, merge, publish, distribute, sublicense, -# and/or sell copies of the Software, and to permit persons to whom the -# Software is furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice (including the next -# paragraph) shall be included in all copies or substantial portions of the -# Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -# IN THE SOFTWARE. -# # SPDX-License-Identifier: MIT +# #============================ end_copyright_notice ============================= cmake_minimum_required(VERSION 3.13.4) diff --git a/GenXIntrinsics/cmake/utils.cmake b/GenXIntrinsics/cmake/utils.cmake index 07debda3..2adb09df 100644 --- a/GenXIntrinsics/cmake/utils.cmake +++ b/GenXIntrinsics/cmake/utils.cmake @@ -2,26 +2,8 @@ # # Copyright (C) 2020-2021 Intel Corporation # -# Permission is hereby granted, free of charge, to any person obtaining a copy -# of this software and associated documentation files (the "Software"), -# to deal in the Software without restriction, including without limitation -# the rights to use, copy, modify, merge, publish, distribute, sublicense, -# and/or sell copies of the Software, and to permit persons to whom the -# Software is furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice (including the next -# paragraph) shall be included in all copies or substantial portions of the -# Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -# IN THE SOFTWARE. -# # SPDX-License-Identifier: MIT +# #============================ end_copyright_notice ============================= # Convenience function to get list of LLVM components for diff --git a/GenXIntrinsics/docs/GenXLangRef.rst b/GenXIntrinsics/docs/GenXLangRef.rst index 63ecbf06..99878e25 100644 --- a/GenXIntrinsics/docs/GenXLangRef.rst +++ b/GenXIntrinsics/docs/GenXLangRef.rst @@ -2,26 +2,8 @@ Copyright (C) 2015-2021 Intel Corporation - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice (including the next - paragraph) shall be included in all copies or substantial portions of the - Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - IN THE SOFTWARE. - SPDX-License-Identifier: MIT + =========================== end_copyright_notice ============================= ============================ diff --git a/GenXIntrinsics/docs/LangRefIndex.rst b/GenXIntrinsics/docs/LangRefIndex.rst index 6627dcf3..4154183e 100644 --- a/GenXIntrinsics/docs/LangRefIndex.rst +++ b/GenXIntrinsics/docs/LangRefIndex.rst @@ -2,26 +2,8 @@ Copyright (C) 2019-2021 Intel Corporation - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice (including the next - paragraph) shall be included in all copies or substantial portions of the - Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - IN THE SOFTWARE. - SPDX-License-Identifier: MIT + =========================== end_copyright_notice ============================= VC Intrinsics documentation (language reference) diff --git a/GenXIntrinsics/docs/Makefile.sphinx b/GenXIntrinsics/docs/Makefile.sphinx index 8e86fbcf..fbf43401 100644 --- a/GenXIntrinsics/docs/Makefile.sphinx +++ b/GenXIntrinsics/docs/Makefile.sphinx @@ -2,26 +2,8 @@ # # Copyright (C) 2019-2021 Intel Corporation # -# Permission is hereby granted, free of charge, to any person obtaining a copy -# of this software and associated documentation files (the "Software"), -# to deal in the Software without restriction, including without limitation -# the rights to use, copy, modify, merge, publish, distribute, sublicense, -# and/or sell copies of the Software, and to permit persons to whom the -# Software is furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice (including the next -# paragraph) shall be included in all copies or substantial portions of the -# Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -# IN THE SOFTWARE. -# # SPDX-License-Identifier: MIT +# #============================ end_copyright_notice ============================= # Minimal makefile for Sphinx documentation diff --git a/GenXIntrinsics/docs/ReadMe.txt b/GenXIntrinsics/docs/ReadMe.txt index 497212ab..06e9d93a 100644 --- a/GenXIntrinsics/docs/ReadMe.txt +++ b/GenXIntrinsics/docs/ReadMe.txt @@ -2,25 +2,7 @@ Copyright (C) 2021 Intel Corporation -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -the rights to use, copy, modify, merge, publish, distribute, sublicense, -and/or sell copies of the Software, and to permit persons to whom the -Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -IN THE SOFTWARE. - SPDX-License-Identifier: MIT + ============================= end_copyright_notice ==========================--> diff --git a/GenXIntrinsics/docs/conf.py b/GenXIntrinsics/docs/conf.py index 6f22f09f..03c33e4d 100644 --- a/GenXIntrinsics/docs/conf.py +++ b/GenXIntrinsics/docs/conf.py @@ -2,26 +2,8 @@ # # Copyright (C) 2019-2021 Intel Corporation # -# Permission is hereby granted, free of charge, to any person obtaining a copy -# of this software and associated documentation files (the "Software"), -# to deal in the Software without restriction, including without limitation -# the rights to use, copy, modify, merge, publish, distribute, sublicense, -# and/or sell copies of the Software, and to permit persons to whom the -# Software is furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice (including the next -# paragraph) shall be included in all copies or substantial portions of the -# Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -# IN THE SOFTWARE. -# # SPDX-License-Identifier: MIT +# #============================ end_copyright_notice ============================= # -*- coding: utf-8 -*- diff --git a/GenXIntrinsics/include/llvm/CMakeLists.txt b/GenXIntrinsics/include/llvm/CMakeLists.txt index 9d617432..0836db4e 100644 --- a/GenXIntrinsics/include/llvm/CMakeLists.txt +++ b/GenXIntrinsics/include/llvm/CMakeLists.txt @@ -2,26 +2,8 @@ # # Copyright (C) 2019-2021 Intel Corporation # -# Permission is hereby granted, free of charge, to any person obtaining a copy -# of this software and associated documentation files (the "Software"), -# to deal in the Software without restriction, including without limitation -# the rights to use, copy, modify, merge, publish, distribute, sublicense, -# and/or sell copies of the Software, and to permit persons to whom the -# Software is furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice (including the next -# paragraph) shall be included in all copies or substantial portions of the -# Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -# IN THE SOFTWARE. -# # SPDX-License-Identifier: MIT +# #============================ end_copyright_notice ============================= add_subdirectory(GenXIntrinsics) diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/CMakeLists.txt b/GenXIntrinsics/include/llvm/GenXIntrinsics/CMakeLists.txt index ec65369b..c46e47c4 100755 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/CMakeLists.txt +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/CMakeLists.txt @@ -2,26 +2,8 @@ # # Copyright (C) 2019-2021 Intel Corporation # -# Permission is hereby granted, free of charge, to any person obtaining a copy -# of this software and associated documentation files (the "Software"), -# to deal in the Software without restriction, including without limitation -# the rights to use, copy, modify, merge, publish, distribute, sublicense, -# and/or sell copies of the Software, and to permit persons to whom the -# Software is furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice (including the next -# paragraph) shall be included in all copies or substantial portions of the -# Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -# IN THE SOFTWARE. -# # SPDX-License-Identifier: MIT +# #============================ end_copyright_notice ============================= add_custom_command( diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/ConfigureVersionFile.cmake b/GenXIntrinsics/include/llvm/GenXIntrinsics/ConfigureVersionFile.cmake index 212490a9..e4b4256a 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/ConfigureVersionFile.cmake +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/ConfigureVersionFile.cmake @@ -2,26 +2,8 @@ # # Copyright (C) 2020-2021 Intel Corporation # -# Permission is hereby granted, free of charge, to any person obtaining a copy -# of this software and associated documentation files (the "Software"), -# to deal in the Software without restriction, including without limitation -# the rights to use, copy, modify, merge, publish, distribute, sublicense, -# and/or sell copies of the Software, and to permit persons to whom the -# Software is furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice (including the next -# paragraph) shall be included in all copies or substantial portions of the -# Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -# IN THE SOFTWARE. -# # SPDX-License-Identifier: MIT +# #============================ end_copyright_notice ============================= include(${VCS_SCRIPT}) diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrOpts.h b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrOpts.h index f8296a52..f5e644fb 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrOpts.h +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrOpts.h @@ -2,26 +2,8 @@ Copyright (C) 2020-2021 Intel Corporation -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -the rights to use, copy, modify, merge, publish, distribute, sublicense, -and/or sell copies of the Software, and to permit persons to whom the -Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -IN THE SOFTWARE. - SPDX-License-Identifier: MIT + ============================= end_copyright_notice ===========================*/ /*========================== begin_copyright_notice ============================ diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsicInst.h b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsicInst.h index 3d828568..ded7dd10 100755 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsicInst.h +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsicInst.h @@ -2,26 +2,8 @@ Copyright (C) 2019-2021 Intel Corporation -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -the rights to use, copy, modify, merge, publish, distribute, sublicense, -and/or sell copies of the Software, and to permit persons to whom the -Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -IN THE SOFTWARE. - SPDX-License-Identifier: MIT + ============================= end_copyright_notice ===========================*/ //===----------------------------------------------------------------------===// diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h index 304df669..b0e69d08 100755 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h @@ -2,26 +2,8 @@ Copyright (C) 2019-2021 Intel Corporation -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -the rights to use, copy, modify, merge, publish, distribute, sublicense, -and/or sell copies of the Software, and to permit persons to whom the -Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -IN THE SOFTWARE. - SPDX-License-Identifier: MIT + ============================= end_copyright_notice ===========================*/ //===----------------------------------------------------------------------===// diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXMetadata.h b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXMetadata.h index 122c8ed5..2ee5bb1c 100755 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXMetadata.h +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXMetadata.h @@ -2,26 +2,8 @@ Copyright (C) 2020-2021 Intel Corporation -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -the rights to use, copy, modify, merge, publish, distribute, sublicense, -and/or sell copies of the Software, and to permit persons to whom the -Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -IN THE SOFTWARE. - SPDX-License-Identifier: MIT + ============================= end_copyright_notice ===========================*/ //===----------------------------------------------------------------------===// diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSPIRVReaderAdaptor.h b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSPIRVReaderAdaptor.h index a21b0d9a..347a535f 100755 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSPIRVReaderAdaptor.h +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSPIRVReaderAdaptor.h @@ -2,26 +2,8 @@ Copyright (C) 2020-2021 Intel Corporation -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -the rights to use, copy, modify, merge, publish, distribute, sublicense, -and/or sell copies of the Software, and to permit persons to whom the -Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -IN THE SOFTWARE. - SPDX-License-Identifier: MIT + ============================= end_copyright_notice ===========================*/ /// diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSPIRVWriterAdaptor.h b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSPIRVWriterAdaptor.h index b877f76b..12e92f43 100755 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSPIRVWriterAdaptor.h +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSPIRVWriterAdaptor.h @@ -2,26 +2,8 @@ Copyright (C) 2020-2021 Intel Corporation -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -the rights to use, copy, modify, merge, publish, distribute, sublicense, -and/or sell copies of the Software, and to permit persons to whom the -Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -IN THE SOFTWARE. - SPDX-License-Identifier: MIT + ============================= end_copyright_notice ===========================*/ /// diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSimdCFLowering.h b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSimdCFLowering.h index a10de7e6..b5cffcb0 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSimdCFLowering.h +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSimdCFLowering.h @@ -2,26 +2,8 @@ Copyright (C) 2019-2021 Intel Corporation -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -the rights to use, copy, modify, merge, publish, distribute, sublicense, -and/or sell copies of the Software, and to permit persons to whom the -Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -IN THE SOFTWARE. - SPDX-License-Identifier: MIT + ============================= end_copyright_notice ===========================*/ // This is the worker class to lowers CM SIMD control flow into a form where diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXVersion.h b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXVersion.h index 6d8b136d..8241726e 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXVersion.h +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXVersion.h @@ -2,26 +2,8 @@ Copyright (C) 2020-2021 Intel Corporation -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -the rights to use, copy, modify, merge, publish, distribute, sublicense, -and/or sell copies of the Software, and to permit persons to whom the -Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -IN THE SOFTWARE. - SPDX-License-Identifier: MIT + ============================= end_copyright_notice ===========================*/ // This file declares interface functions used to aquire version info. diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py index 3976e6fa..be8139f7 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py @@ -2,26 +2,8 @@ # # Copyright (C) 2019-2021 Intel Corporation # -# Permission is hereby granted, free of charge, to any person obtaining a copy -# of this software and associated documentation files (the "Software"), -# to deal in the Software without restriction, including without limitation -# the rights to use, copy, modify, merge, publish, distribute, sublicense, -# and/or sell copies of the Software, and to permit persons to whom the -# Software is furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice (including the next -# paragraph) shall be included in all copies or substantial portions of the -# Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -# IN THE SOFTWARE. -# # SPDX-License-Identifier: MIT +# #============================ end_copyright_notice ============================= #===----------------------------------------------------------------------===// diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py index 4a553e81..90e6dabb 100755 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py @@ -4,26 +4,8 @@ # # Copyright (C) 2019-2021 Intel Corporation # -# Permission is hereby granted, free of charge, to any person obtaining a copy -# of this software and associated documentation files (the "Software"), -# to deal in the Software without restriction, including without limitation -# the rights to use, copy, modify, merge, publish, distribute, sublicense, -# and/or sell copies of the Software, and to permit persons to whom the -# Software is furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice (including the next -# paragraph) shall be included in all copies or substantial portions of the -# Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -# IN THE SOFTWARE. -# # SPDX-License-Identifier: MIT +# #============================ end_copyright_notice ============================= import os diff --git a/GenXIntrinsics/include/llvmVCWrapper/IR/DerivedTypes.h b/GenXIntrinsics/include/llvmVCWrapper/IR/DerivedTypes.h index 63e4b9b0..cfaef3f4 100644 --- a/GenXIntrinsics/include/llvmVCWrapper/IR/DerivedTypes.h +++ b/GenXIntrinsics/include/llvmVCWrapper/IR/DerivedTypes.h @@ -2,26 +2,8 @@ Copyright (C) 2020-2021 Intel Corporation -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -the rights to use, copy, modify, merge, publish, distribute, sublicense, -and/or sell copies of the Software, and to permit persons to whom the -Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -IN THE SOFTWARE. - SPDX-License-Identifier: MIT + ============================= end_copyright_notice ===========================*/ #ifndef VCINTR_IR_DERIVEDYPES_H diff --git a/GenXIntrinsics/include/llvmVCWrapper/IR/Function.h b/GenXIntrinsics/include/llvmVCWrapper/IR/Function.h index 076fe512..2898d4f8 100644 --- a/GenXIntrinsics/include/llvmVCWrapper/IR/Function.h +++ b/GenXIntrinsics/include/llvmVCWrapper/IR/Function.h @@ -2,26 +2,8 @@ Copyright (C) 2020-2021 Intel Corporation -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -the rights to use, copy, modify, merge, publish, distribute, sublicense, -and/or sell copies of the Software, and to permit persons to whom the -Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -IN THE SOFTWARE. - SPDX-License-Identifier: MIT + ============================= end_copyright_notice ===========================*/ #ifndef VCINTR_IR_FUNCTION_H diff --git a/GenXIntrinsics/include/llvmVCWrapper/IR/GlobalValue.h b/GenXIntrinsics/include/llvmVCWrapper/IR/GlobalValue.h index de2f016c..00d2f70b 100644 --- a/GenXIntrinsics/include/llvmVCWrapper/IR/GlobalValue.h +++ b/GenXIntrinsics/include/llvmVCWrapper/IR/GlobalValue.h @@ -2,26 +2,8 @@ Copyright (C) 2020-2021 Intel Corporation -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -the rights to use, copy, modify, merge, publish, distribute, sublicense, -and/or sell copies of the Software, and to permit persons to whom the -Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -IN THE SOFTWARE. - SPDX-License-Identifier: MIT + ============================= end_copyright_notice ===========================*/ #ifndef VCINTR_IR_GLOBALVALUE_H diff --git a/GenXIntrinsics/include/llvmVCWrapper/IR/InstrTypes.h b/GenXIntrinsics/include/llvmVCWrapper/IR/InstrTypes.h index cfcfa2c3..c8a6901b 100644 --- a/GenXIntrinsics/include/llvmVCWrapper/IR/InstrTypes.h +++ b/GenXIntrinsics/include/llvmVCWrapper/IR/InstrTypes.h @@ -2,26 +2,8 @@ Copyright (C) 2020-2021 Intel Corporation -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -the rights to use, copy, modify, merge, publish, distribute, sublicense, -and/or sell copies of the Software, and to permit persons to whom the -Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -IN THE SOFTWARE. - SPDX-License-Identifier: MIT + ============================= end_copyright_notice ===========================*/ #ifndef VCINTR_IR_INSTRTYPES_H diff --git a/GenXIntrinsics/include/llvmVCWrapper/IR/Instructions.h b/GenXIntrinsics/include/llvmVCWrapper/IR/Instructions.h index 144c24dd..2649f6f6 100755 --- a/GenXIntrinsics/include/llvmVCWrapper/IR/Instructions.h +++ b/GenXIntrinsics/include/llvmVCWrapper/IR/Instructions.h @@ -2,26 +2,8 @@ Copyright (C) 2020-2021 Intel Corporation -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -the rights to use, copy, modify, merge, publish, distribute, sublicense, -and/or sell copies of the Software, and to permit persons to whom the -Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -IN THE SOFTWARE. - SPDX-License-Identifier: MIT + ============================= end_copyright_notice ===========================*/ #ifndef VCINTR_IR_INSTRUCTIONS_H diff --git a/GenXIntrinsics/include/llvmVCWrapper/IR/Intrinsics.h b/GenXIntrinsics/include/llvmVCWrapper/IR/Intrinsics.h index 57db0663..039eda74 100644 --- a/GenXIntrinsics/include/llvmVCWrapper/IR/Intrinsics.h +++ b/GenXIntrinsics/include/llvmVCWrapper/IR/Intrinsics.h @@ -2,26 +2,8 @@ Copyright (C) 2021-2021 Intel Corporation -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -the rights to use, copy, modify, merge, publish, distribute, sublicense, -and/or sell copies of the Software, and to permit persons to whom the -Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -IN THE SOFTWARE. - SPDX-License-Identifier: MIT + ============================= end_copyright_notice ===========================*/ #ifndef VCINTR_IR_INTRINSICS_H diff --git a/GenXIntrinsics/include/llvmVCWrapper/Support/Alignment.h b/GenXIntrinsics/include/llvmVCWrapper/Support/Alignment.h index ddaa03c8..b7850fb0 100755 --- a/GenXIntrinsics/include/llvmVCWrapper/Support/Alignment.h +++ b/GenXIntrinsics/include/llvmVCWrapper/Support/Alignment.h @@ -2,26 +2,8 @@ Copyright (C) 2020-2021 Intel Corporation -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -the rights to use, copy, modify, merge, publish, distribute, sublicense, -and/or sell copies of the Software, and to permit persons to whom the -Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -IN THE SOFTWARE. - SPDX-License-Identifier: MIT + ============================= end_copyright_notice ===========================*/ #ifndef VCINTR_IR_ALIGNMENT_H diff --git a/GenXIntrinsics/lib/CMakeLists.txt b/GenXIntrinsics/lib/CMakeLists.txt index 9d617432..0836db4e 100644 --- a/GenXIntrinsics/lib/CMakeLists.txt +++ b/GenXIntrinsics/lib/CMakeLists.txt @@ -2,26 +2,8 @@ # # Copyright (C) 2019-2021 Intel Corporation # -# Permission is hereby granted, free of charge, to any person obtaining a copy -# of this software and associated documentation files (the "Software"), -# to deal in the Software without restriction, including without limitation -# the rights to use, copy, modify, merge, publish, distribute, sublicense, -# and/or sell copies of the Software, and to permit persons to whom the -# Software is furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice (including the next -# paragraph) shall be included in all copies or substantial portions of the -# Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -# IN THE SOFTWARE. -# # SPDX-License-Identifier: MIT +# #============================ end_copyright_notice ============================= add_subdirectory(GenXIntrinsics) diff --git a/GenXIntrinsics/lib/GenXIntrinsics/AdaptorsCommon.h b/GenXIntrinsics/lib/GenXIntrinsics/AdaptorsCommon.h index d88163c2..5033e91b 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/AdaptorsCommon.h +++ b/GenXIntrinsics/lib/GenXIntrinsics/AdaptorsCommon.h @@ -2,26 +2,8 @@ Copyright (C) 2020-2021 Intel Corporation -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -the rights to use, copy, modify, merge, publish, distribute, sublicense, -and/or sell copies of the Software, and to permit persons to whom the -Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -IN THE SOFTWARE. - SPDX-License-Identifier: MIT + ============================= end_copyright_notice ===========================*/ // This file defines common constants for writer/reader spirv adaptors. diff --git a/GenXIntrinsics/lib/GenXIntrinsics/CMakeLists.txt b/GenXIntrinsics/lib/GenXIntrinsics/CMakeLists.txt index e6dbd6ab..ea0c120d 100755 --- a/GenXIntrinsics/lib/GenXIntrinsics/CMakeLists.txt +++ b/GenXIntrinsics/lib/GenXIntrinsics/CMakeLists.txt @@ -2,26 +2,8 @@ # # Copyright (C) 2019-2021 Intel Corporation # -# Permission is hereby granted, free of charge, to any person obtaining a copy -# of this software and associated documentation files (the "Software"), -# to deal in the Software without restriction, including without limitation -# the rights to use, copy, modify, merge, publish, distribute, sublicense, -# and/or sell copies of the Software, and to permit persons to whom the -# Software is furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice (including the next -# paragraph) shall be included in all copies or substantial portions of the -# Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -# IN THE SOFTWARE. -# # SPDX-License-Identifier: MIT +# #============================ end_copyright_notice ============================= set(LLVM_COMPONENTS diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp index 5dd95c40..3a1fe24c 100755 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp @@ -2,26 +2,8 @@ Copyright (C) 2019-2021 Intel Corporation -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -the rights to use, copy, modify, merge, publish, distribute, sublicense, -and/or sell copies of the Software, and to permit persons to whom the -Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -IN THE SOFTWARE. - SPDX-License-Identifier: MIT + ============================= end_copyright_notice ===========================*/ /*========================== begin_copyright_notice ============================ diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXRestoreIntrAttr.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXRestoreIntrAttr.cpp index 9627ac5f..9a79b9ae 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXRestoreIntrAttr.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXRestoreIntrAttr.cpp @@ -2,26 +2,8 @@ Copyright (C) 2020-2021 Intel Corporation -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -the rights to use, copy, modify, merge, publish, distribute, sublicense, -and/or sell copies of the Software, and to permit persons to whom the -Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -IN THE SOFTWARE. - SPDX-License-Identifier: MIT + ============================= end_copyright_notice ===========================*/ /*========================== begin_copyright_notice ============================ diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp index 1224ce77..bd1a7a65 100755 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp @@ -2,26 +2,8 @@ Copyright (C) 2020-2021 Intel Corporation -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -the rights to use, copy, modify, merge, publish, distribute, sublicense, -and/or sell copies of the Software, and to permit persons to whom the -Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -IN THE SOFTWARE. - SPDX-License-Identifier: MIT + ============================= end_copyright_notice ===========================*/ // This pass converts metadata from SPIRV format to whichever used in backend. diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp index 8cbf1227..5132a17f 100755 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp @@ -2,26 +2,8 @@ Copyright (C) 2020-2021 Intel Corporation -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -the rights to use, copy, modify, merge, publish, distribute, sublicense, -and/or sell copies of the Software, and to permit persons to whom the -Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -IN THE SOFTWARE. - SPDX-License-Identifier: MIT + ============================= end_copyright_notice ===========================*/ // This pass converts metadata to SPIRV format from whichever used in frontend. diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSimdCFLowering.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSimdCFLowering.cpp index baa6ebf8..2aaf1554 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSimdCFLowering.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSimdCFLowering.cpp @@ -2,26 +2,8 @@ Copyright (C) 2015-2021 Intel Corporation -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -the rights to use, copy, modify, merge, publish, distribute, sublicense, -and/or sell copies of the Software, and to permit persons to whom the -Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -IN THE SOFTWARE. - SPDX-License-Identifier: MIT + ============================= end_copyright_notice ===========================*/ // Lower CM SIMD control flow diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp index 6232ee0b..ef659ec6 100755 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp @@ -2,26 +2,8 @@ Copyright (C) 2020-2021 Intel Corporation -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -the rights to use, copy, modify, merge, publish, distribute, sublicense, -and/or sell copies of the Software, and to permit persons to whom the -Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -IN THE SOFTWARE. - SPDX-License-Identifier: MIT + ============================= end_copyright_notice ===========================*/ // This file defines common functions for rewriting single element vectors diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.h b/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.h index ec5c9b0c..d7177578 100755 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.h +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.h @@ -2,26 +2,8 @@ Copyright (C) 2020-2021 Intel Corporation -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -the rights to use, copy, modify, merge, publish, distribute, sublicense, -and/or sell copies of the Software, and to permit persons to whom the -Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -IN THE SOFTWARE. - SPDX-License-Identifier: MIT + ============================= end_copyright_notice ===========================*/ // This file declares functions for rewriting single element vectors diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXVersion.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXVersion.cpp index d4f63c25..9375c691 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXVersion.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXVersion.cpp @@ -2,26 +2,8 @@ Copyright (C) 2020-2021 Intel Corporation -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -the rights to use, copy, modify, merge, publish, distribute, sublicense, -and/or sell copies of the Software, and to permit persons to whom the -Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -IN THE SOFTWARE. - SPDX-License-Identifier: MIT + ============================= end_copyright_notice ===========================*/ // This source file defines interface functions to retrive version info. diff --git a/GenXIntrinsics/test/Adaptors/annot_mess_writer.ll b/GenXIntrinsics/test/Adaptors/annot_mess_writer.ll index e5e3cd15..e708908a 100644 --- a/GenXIntrinsics/test/Adaptors/annot_mess_writer.ll +++ b/GenXIntrinsics/test/Adaptors/annot_mess_writer.ll @@ -2,26 +2,8 @@ ; ; Copyright (C) 2020-2021 Intel Corporation ; -; Permission is hereby granted, free of charge, to any person obtaining a copy -; of this software and associated documentation files (the "Software"), -; to deal in the Software without restriction, including without limitation -; the rights to use, copy, modify, merge, publish, distribute, sublicense, -; and/or sell copies of the Software, and to permit persons to whom the -; Software is furnished to do so, subject to the following conditions: -; -; The above copyright notice and this permission notice (including the next -; paragraph) shall be included in all copies or substantial portions of the -; Software. -; -; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -; FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -; IN THE SOFTWARE. -; ; SPDX-License-Identifier: MIT +; ;============================ end_copyright_notice ============================= ; Test messy annnotations translation in writer. First valid diff --git a/GenXIntrinsics/test/Adaptors/annotated_args_mixed_reader.ll b/GenXIntrinsics/test/Adaptors/annotated_args_mixed_reader.ll index daadd393..74fc4de4 100644 --- a/GenXIntrinsics/test/Adaptors/annotated_args_mixed_reader.ll +++ b/GenXIntrinsics/test/Adaptors/annotated_args_mixed_reader.ll @@ -2,26 +2,8 @@ ; ; Copyright (C) 2020-2021 Intel Corporation ; -; Permission is hereby granted, free of charge, to any person obtaining a copy -; of this software and associated documentation files (the "Software"), -; to deal in the Software without restriction, including without limitation -; the rights to use, copy, modify, merge, publish, distribute, sublicense, -; and/or sell copies of the Software, and to permit persons to whom the -; Software is furnished to do so, subject to the following conditions: -; -; The above copyright notice and this permission notice (including the next -; paragraph) shall be included in all copies or substantial portions of the -; Software. -; -; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -; FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -; IN THE SOFTWARE. -; ; SPDX-License-Identifier: MIT +; ;============================ end_copyright_notice ============================= ; XFAIL: llvm13 diff --git a/GenXIntrinsics/test/Adaptors/annotated_args_no_conv_reader.ll b/GenXIntrinsics/test/Adaptors/annotated_args_no_conv_reader.ll index ac01a656..8628646c 100644 --- a/GenXIntrinsics/test/Adaptors/annotated_args_no_conv_reader.ll +++ b/GenXIntrinsics/test/Adaptors/annotated_args_no_conv_reader.ll @@ -2,26 +2,8 @@ ; ; Copyright (C) 2020-2021 Intel Corporation ; -; Permission is hereby granted, free of charge, to any person obtaining a copy -; of this software and associated documentation files (the "Software"), -; to deal in the Software without restriction, including without limitation -; the rights to use, copy, modify, merge, publish, distribute, sublicense, -; and/or sell copies of the Software, and to permit persons to whom the -; Software is furnished to do so, subject to the following conditions: -; -; The above copyright notice and this permission notice (including the next -; paragraph) shall be included in all copies or substantial portions of the -; Software. -; -; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -; FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -; IN THE SOFTWARE. -; ; SPDX-License-Identifier: MIT +; ;============================ end_copyright_notice ============================= ; XFAIL: llvm13 diff --git a/GenXIntrinsics/test/Adaptors/annotated_args_no_conv_writer.ll b/GenXIntrinsics/test/Adaptors/annotated_args_no_conv_writer.ll index 020d8cde..baab71ca 100644 --- a/GenXIntrinsics/test/Adaptors/annotated_args_no_conv_writer.ll +++ b/GenXIntrinsics/test/Adaptors/annotated_args_no_conv_writer.ll @@ -2,26 +2,8 @@ ; ; Copyright (C) 2020-2021 Intel Corporation ; -; Permission is hereby granted, free of charge, to any person obtaining a copy -; of this software and associated documentation files (the "Software"), -; to deal in the Software without restriction, including without limitation -; the rights to use, copy, modify, merge, publish, distribute, sublicense, -; and/or sell copies of the Software, and to permit persons to whom the -; Software is furnished to do so, subject to the following conditions: -; -; The above copyright notice and this permission notice (including the next -; paragraph) shall be included in all copies or substantial portions of the -; Software. -; -; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -; FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -; IN THE SOFTWARE. -; ; SPDX-License-Identifier: MIT +; ;============================ end_copyright_notice ============================= ; Test that writer does not changes signature if correct diff --git a/GenXIntrinsics/test/Adaptors/annotated_args_reader.ll b/GenXIntrinsics/test/Adaptors/annotated_args_reader.ll index 90c1aa81..112046c1 100644 --- a/GenXIntrinsics/test/Adaptors/annotated_args_reader.ll +++ b/GenXIntrinsics/test/Adaptors/annotated_args_reader.ll @@ -2,26 +2,8 @@ ; ; Copyright (C) 2020-2021 Intel Corporation ; -; Permission is hereby granted, free of charge, to any person obtaining a copy -; of this software and associated documentation files (the "Software"), -; to deal in the Software without restriction, including without limitation -; the rights to use, copy, modify, merge, publish, distribute, sublicense, -; and/or sell copies of the Software, and to permit persons to whom the -; Software is furnished to do so, subject to the following conditions: -; -; The above copyright notice and this permission notice (including the next -; paragraph) shall be included in all copies or substantial portions of the -; Software. -; -; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -; FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -; IN THE SOFTWARE. -; ; SPDX-License-Identifier: MIT +; ;============================ end_copyright_notice ============================= ; XFAIL: llvm13 diff --git a/GenXIntrinsics/test/Adaptors/annotated_args_writer.ll b/GenXIntrinsics/test/Adaptors/annotated_args_writer.ll index 2b5852c4..3125f98e 100644 --- a/GenXIntrinsics/test/Adaptors/annotated_args_writer.ll +++ b/GenXIntrinsics/test/Adaptors/annotated_args_writer.ll @@ -2,26 +2,8 @@ ; ; Copyright (C) 2020-2021 Intel Corporation ; -; Permission is hereby granted, free of charge, to any person obtaining a copy -; of this software and associated documentation files (the "Software"), -; to deal in the Software without restriction, including without limitation -; the rights to use, copy, modify, merge, publish, distribute, sublicense, -; and/or sell copies of the Software, and to permit persons to whom the -; Software is furnished to do so, subject to the following conditions: -; -; The above copyright notice and this permission notice (including the next -; paragraph) shall be included in all copies or substantial portions of the -; Software. -; -; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -; FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -; IN THE SOFTWARE. -; ; SPDX-License-Identifier: MIT +; ;============================ end_copyright_notice ============================= ; Test kernel arguments translation from old style with metadata to diff --git a/GenXIntrinsics/test/Adaptors/combined_args_reader.ll b/GenXIntrinsics/test/Adaptors/combined_args_reader.ll index 775b5fab..ec243067 100644 --- a/GenXIntrinsics/test/Adaptors/combined_args_reader.ll +++ b/GenXIntrinsics/test/Adaptors/combined_args_reader.ll @@ -2,26 +2,8 @@ ; ; Copyright (C) 2020-2021 Intel Corporation ; -; Permission is hereby granted, free of charge, to any person obtaining a copy -; of this software and associated documentation files (the "Software"), -; to deal in the Software without restriction, including without limitation -; the rights to use, copy, modify, merge, publish, distribute, sublicense, -; and/or sell copies of the Software, and to permit persons to whom the -; Software is furnished to do so, subject to the following conditions: -; -; The above copyright notice and this permission notice (including the next -; paragraph) shall be included in all copies or substantial portions of the -; Software. -; -; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -; FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -; IN THE SOFTWARE. -; ; SPDX-License-Identifier: MIT +; ;============================ end_copyright_notice ============================= ; XFAIL: llvm13 diff --git a/GenXIntrinsics/test/Adaptors/combined_args_writer.ll b/GenXIntrinsics/test/Adaptors/combined_args_writer.ll index 06a6f05a..3be41ad4 100644 --- a/GenXIntrinsics/test/Adaptors/combined_args_writer.ll +++ b/GenXIntrinsics/test/Adaptors/combined_args_writer.ll @@ -2,26 +2,8 @@ ; ; Copyright (C) 2020-2021 Intel Corporation ; -; Permission is hereby granted, free of charge, to any person obtaining a copy -; of this software and associated documentation files (the "Software"), -; to deal in the Software without restriction, including without limitation -; the rights to use, copy, modify, merge, publish, distribute, sublicense, -; and/or sell copies of the Software, and to permit persons to whom the -; Software is furnished to do so, subject to the following conditions: -; -; The above copyright notice and this permission notice (including the next -; paragraph) shall be included in all copies or substantial portions of the -; Software. -; -; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -; FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -; IN THE SOFTWARE. -; ; SPDX-License-Identifier: MIT +; ;============================ end_copyright_notice ============================= ; Test combined writer translation: kernel has both annotated explicit diff --git a/GenXIntrinsics/test/Adaptors/empty_kernel_writer.ll b/GenXIntrinsics/test/Adaptors/empty_kernel_writer.ll index 0960a00d..2fb013d2 100644 --- a/GenXIntrinsics/test/Adaptors/empty_kernel_writer.ll +++ b/GenXIntrinsics/test/Adaptors/empty_kernel_writer.ll @@ -2,26 +2,8 @@ ; ; Copyright (C) 2020-2021 Intel Corporation ; -; Permission is hereby granted, free of charge, to any person obtaining a copy -; of this software and associated documentation files (the "Software"), -; to deal in the Software without restriction, including without limitation -; the rights to use, copy, modify, merge, publish, distribute, sublicense, -; and/or sell copies of the Software, and to permit persons to whom the -; Software is furnished to do so, subject to the following conditions: -; -; The above copyright notice and this permission notice (including the next -; paragraph) shall be included in all copies or substantial portions of the -; Software. -; -; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -; FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -; IN THE SOFTWARE. -; ; SPDX-License-Identifier: MIT +; ;============================ end_copyright_notice ============================= ; Test empty kernel metadata translation: old -> new. diff --git a/GenXIntrinsics/test/Adaptors/no_vcfunction_reader.ll b/GenXIntrinsics/test/Adaptors/no_vcfunction_reader.ll index a51cbd8a..9bbd8610 100644 --- a/GenXIntrinsics/test/Adaptors/no_vcfunction_reader.ll +++ b/GenXIntrinsics/test/Adaptors/no_vcfunction_reader.ll @@ -2,26 +2,8 @@ ; ; Copyright (C) 2020-2021 Intel Corporation ; -; Permission is hereby granted, free of charge, to any person obtaining a copy -; of this software and associated documentation files (the "Software"), -; to deal in the Software without restriction, including without limitation -; the rights to use, copy, modify, merge, publish, distribute, sublicense, -; and/or sell copies of the Software, and to permit persons to whom the -; Software is furnished to do so, subject to the following conditions: -; -; The above copyright notice and this permission notice (including the next -; paragraph) shall be included in all copies or substantial portions of the -; Software. -; -; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -; FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -; IN THE SOFTWARE. -; ; SPDX-License-Identifier: MIT +; ;============================ end_copyright_notice ============================= ; XFAIL: llvm13 diff --git a/GenXIntrinsics/test/Adaptors/non_global_ptr_reader.ll b/GenXIntrinsics/test/Adaptors/non_global_ptr_reader.ll index 8b25e179..9008715d 100644 --- a/GenXIntrinsics/test/Adaptors/non_global_ptr_reader.ll +++ b/GenXIntrinsics/test/Adaptors/non_global_ptr_reader.ll @@ -2,26 +2,8 @@ ; ; Copyright (C) 2020-2021 Intel Corporation ; -; Permission is hereby granted, free of charge, to any person obtaining a copy -; of this software and associated documentation files (the "Software"), -; to deal in the Software without restriction, including without limitation -; the rights to use, copy, modify, merge, publish, distribute, sublicense, -; and/or sell copies of the Software, and to permit persons to whom the -; Software is furnished to do so, subject to the following conditions: -; -; The above copyright notice and this permission notice (including the next -; paragraph) shall be included in all copies or substantial portions of the -; Software. -; -; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -; FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -; IN THE SOFTWARE. -; ; SPDX-License-Identifier: MIT +; ;============================ end_copyright_notice ============================= ; XFAIL: llvm13 diff --git a/GenXIntrinsics/test/Adaptors/old_decorated_args_reader.ll b/GenXIntrinsics/test/Adaptors/old_decorated_args_reader.ll index e997c9bc..ea6179d6 100644 --- a/GenXIntrinsics/test/Adaptors/old_decorated_args_reader.ll +++ b/GenXIntrinsics/test/Adaptors/old_decorated_args_reader.ll @@ -2,26 +2,8 @@ ; ; Copyright (C) 2020-2021 Intel Corporation ; -; Permission is hereby granted, free of charge, to any person obtaining a copy -; of this software and associated documentation files (the "Software"), -; to deal in the Software without restriction, including without limitation -; the rights to use, copy, modify, merge, publish, distribute, sublicense, -; and/or sell copies of the Software, and to permit persons to whom the -; Software is furnished to do so, subject to the following conditions: -; -; The above copyright notice and this permission notice (including the next -; paragraph) shall be included in all copies or substantial portions of the -; Software. -; -; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -; FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -; IN THE SOFTWARE. -; ; SPDX-License-Identifier: MIT +; ;============================ end_copyright_notice ============================= ; XFAIL: llvm13 diff --git a/GenXIntrinsics/test/Adaptors/plain_args_reader.ll b/GenXIntrinsics/test/Adaptors/plain_args_reader.ll index 0978f803..f7738490 100644 --- a/GenXIntrinsics/test/Adaptors/plain_args_reader.ll +++ b/GenXIntrinsics/test/Adaptors/plain_args_reader.ll @@ -2,26 +2,8 @@ ; ; Copyright (C) 2020-2021 Intel Corporation ; -; Permission is hereby granted, free of charge, to any person obtaining a copy -; of this software and associated documentation files (the "Software"), -; to deal in the Software without restriction, including without limitation -; the rights to use, copy, modify, merge, publish, distribute, sublicense, -; and/or sell copies of the Software, and to permit persons to whom the -; Software is furnished to do so, subject to the following conditions: -; -; The above copyright notice and this permission notice (including the next -; paragraph) shall be included in all copies or substantial portions of the -; Software. -; -; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -; FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -; IN THE SOFTWARE. -; ; SPDX-License-Identifier: MIT +; ;============================ end_copyright_notice ============================= ; XFAIL: llvm13 diff --git a/GenXIntrinsics/test/Adaptors/plain_args_writer.ll b/GenXIntrinsics/test/Adaptors/plain_args_writer.ll index 803f3bb9..b3f35231 100644 --- a/GenXIntrinsics/test/Adaptors/plain_args_writer.ll +++ b/GenXIntrinsics/test/Adaptors/plain_args_writer.ll @@ -2,26 +2,8 @@ ; ; Copyright (C) 2020-2021 Intel Corporation ; -; Permission is hereby granted, free of charge, to any person obtaining a copy -; of this software and associated documentation files (the "Software"), -; to deal in the Software without restriction, including without limitation -; the rights to use, copy, modify, merge, publish, distribute, sublicense, -; and/or sell copies of the Software, and to permit persons to whom the -; Software is furnished to do so, subject to the following conditions: -; -; The above copyright notice and this permission notice (including the next -; paragraph) shall be included in all copies or substantial portions of the -; Software. -; -; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -; FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -; IN THE SOFTWARE. -; ; SPDX-License-Identifier: MIT +; ;============================ end_copyright_notice ============================= ; Test kernel arguments translation from old style with metadata to diff --git a/GenXIntrinsics/test/Adaptors/sev_signature_reader.ll b/GenXIntrinsics/test/Adaptors/sev_signature_reader.ll index e1edf14b..b9923252 100644 --- a/GenXIntrinsics/test/Adaptors/sev_signature_reader.ll +++ b/GenXIntrinsics/test/Adaptors/sev_signature_reader.ll @@ -2,26 +2,8 @@ ; ; Copyright (C) 2020-2021 Intel Corporation ; -; Permission is hereby granted, free of charge, to any person obtaining a copy -; of this software and associated documentation files (the "Software"), -; to deal in the Software without restriction, including without limitation -; the rights to use, copy, modify, merge, publish, distribute, sublicense, -; and/or sell copies of the Software, and to permit persons to whom the -; Software is furnished to do so, subject to the following conditions: -; -; The above copyright notice and this permission notice (including the next -; paragraph) shall be included in all copies or substantial portions of the -; Software. -; -; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -; FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -; IN THE SOFTWARE. -; ; SPDX-License-Identifier: MIT +; ;============================ end_copyright_notice ============================= ; XFAIL: llvm13 diff --git a/GenXIntrinsics/test/Adaptors/sev_signature_writer.ll b/GenXIntrinsics/test/Adaptors/sev_signature_writer.ll index 4ee2eddc..12935184 100644 --- a/GenXIntrinsics/test/Adaptors/sev_signature_writer.ll +++ b/GenXIntrinsics/test/Adaptors/sev_signature_writer.ll @@ -2,26 +2,8 @@ ; ; Copyright (C) 2020-2021 Intel Corporation ; -; Permission is hereby granted, free of charge, to any person obtaining a copy -; of this software and associated documentation files (the "Software"), -; to deal in the Software without restriction, including without limitation -; the rights to use, copy, modify, merge, publish, distribute, sublicense, -; and/or sell copies of the Software, and to permit persons to whom the -; Software is furnished to do so, subject to the following conditions: -; -; The above copyright notice and this permission notice (including the next -; paragraph) shall be included in all copies or substantial portions of the -; Software. -; -; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -; FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -; IN THE SOFTWARE. -; ; SPDX-License-Identifier: MIT +; ;============================ end_copyright_notice ============================= ; Test simple signatures tranform diff --git a/GenXIntrinsics/test/Adaptors/surface_access_reader.ll b/GenXIntrinsics/test/Adaptors/surface_access_reader.ll index f703922e..8cbfb460 100644 --- a/GenXIntrinsics/test/Adaptors/surface_access_reader.ll +++ b/GenXIntrinsics/test/Adaptors/surface_access_reader.ll @@ -2,26 +2,8 @@ ; ; Copyright (C) 2020-2021 Intel Corporation ; -; Permission is hereby granted, free of charge, to any person obtaining a copy -; of this software and associated documentation files (the "Software"), -; to deal in the Software without restriction, including without limitation -; the rights to use, copy, modify, merge, publish, distribute, sublicense, -; and/or sell copies of the Software, and to permit persons to whom the -; Software is furnished to do so, subject to the following conditions: -; -; The above copyright notice and this permission notice (including the next -; paragraph) shall be included in all copies or substantial portions of the -; Software. -; -; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -; FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -; IN THE SOFTWARE. -; ; SPDX-License-Identifier: MIT +; ;============================ end_copyright_notice ============================= ; XFAIL: llvm13 diff --git a/GenXIntrinsics/test/Adaptors/surface_access_writer.ll b/GenXIntrinsics/test/Adaptors/surface_access_writer.ll index e431201a..609d445c 100644 --- a/GenXIntrinsics/test/Adaptors/surface_access_writer.ll +++ b/GenXIntrinsics/test/Adaptors/surface_access_writer.ll @@ -2,26 +2,8 @@ ; ; Copyright (C) 2020-2021 Intel Corporation ; -; Permission is hereby granted, free of charge, to any person obtaining a copy -; of this software and associated documentation files (the "Software"), -; to deal in the Software without restriction, including without limitation -; the rights to use, copy, modify, merge, publish, distribute, sublicense, -; and/or sell copies of the Software, and to permit persons to whom the -; Software is furnished to do so, subject to the following conditions: -; -; The above copyright notice and this permission notice (including the next -; paragraph) shall be included in all copies or substantial portions of the -; Software. -; -; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -; FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -; IN THE SOFTWARE. -; ; SPDX-License-Identifier: MIT +; ;============================ end_copyright_notice ============================= ; Test kernel surface argument translation from old style with diff --git a/GenXIntrinsics/test/Adaptors/unknown_arg_reader.ll b/GenXIntrinsics/test/Adaptors/unknown_arg_reader.ll index f74727c7..4058a6c6 100644 --- a/GenXIntrinsics/test/Adaptors/unknown_arg_reader.ll +++ b/GenXIntrinsics/test/Adaptors/unknown_arg_reader.ll @@ -2,26 +2,8 @@ ; ; Copyright (C) 2020-2021 Intel Corporation ; -; Permission is hereby granted, free of charge, to any person obtaining a copy -; of this software and associated documentation files (the "Software"), -; to deal in the Software without restriction, including without limitation -; the rights to use, copy, modify, merge, publish, distribute, sublicense, -; and/or sell copies of the Software, and to permit persons to whom the -; Software is furnished to do so, subject to the following conditions: -; -; The above copyright notice and this permission notice (including the next -; paragraph) shall be included in all copies or substantial portions of the -; Software. -; -; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -; FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -; IN THE SOFTWARE. -; ; SPDX-License-Identifier: MIT +; ;============================ end_copyright_notice ============================= ; XFAIL: llvm13 diff --git a/GenXIntrinsics/test/Adaptors/unknown_arg_writer.ll b/GenXIntrinsics/test/Adaptors/unknown_arg_writer.ll index 0f3bf1ba..085b69e9 100644 --- a/GenXIntrinsics/test/Adaptors/unknown_arg_writer.ll +++ b/GenXIntrinsics/test/Adaptors/unknown_arg_writer.ll @@ -2,26 +2,8 @@ ; ; Copyright (C) 2020-2021 Intel Corporation ; -; Permission is hereby granted, free of charge, to any person obtaining a copy -; of this software and associated documentation files (the "Software"), -; to deal in the Software without restriction, including without limitation -; the rights to use, copy, modify, merge, publish, distribute, sublicense, -; and/or sell copies of the Software, and to permit persons to whom the -; Software is furnished to do so, subject to the following conditions: -; -; The above copyright notice and this permission notice (including the next -; paragraph) shall be included in all copies or substantial portions of the -; Software. -; -; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -; FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -; IN THE SOFTWARE. -; ; SPDX-License-Identifier: MIT +; ;============================ end_copyright_notice ============================= ; Test writer translation of implicit argument. Implicit arguments diff --git a/GenXIntrinsics/test/CMakeLists.txt b/GenXIntrinsics/test/CMakeLists.txt index d8ef4a4c..62d22032 100644 --- a/GenXIntrinsics/test/CMakeLists.txt +++ b/GenXIntrinsics/test/CMakeLists.txt @@ -2,26 +2,8 @@ # # Copyright (C) 2020-2021 Intel Corporation # -# Permission is hereby granted, free of charge, to any person obtaining a copy -# of this software and associated documentation files (the "Software"), -# to deal in the Software without restriction, including without limitation -# the rights to use, copy, modify, merge, publish, distribute, sublicense, -# and/or sell copies of the Software, and to permit persons to whom the -# Software is furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice (including the next -# paragraph) shall be included in all copies or substantial portions of the -# Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -# IN THE SOFTWARE. -# # SPDX-License-Identifier: MIT +# #============================ end_copyright_notice ============================= if(BUILD_EXTERNAL) diff --git a/GenXIntrinsics/test/Plugin/CMakeLists.txt b/GenXIntrinsics/test/Plugin/CMakeLists.txt index 78136b63..a03393ce 100644 --- a/GenXIntrinsics/test/Plugin/CMakeLists.txt +++ b/GenXIntrinsics/test/Plugin/CMakeLists.txt @@ -2,26 +2,8 @@ # # Copyright (C) 2020-2021 Intel Corporation # -# Permission is hereby granted, free of charge, to any person obtaining a copy -# of this software and associated documentation files (the "Software"), -# to deal in the Software without restriction, including without limitation -# the rights to use, copy, modify, merge, publish, distribute, sublicense, -# and/or sell copies of the Software, and to permit persons to whom the -# Software is furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice (including the next -# paragraph) shall be included in all copies or substantial portions of the -# Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -# IN THE SOFTWARE. -# # SPDX-License-Identifier: MIT +# #============================ end_copyright_notice ============================= set(PLUGIN_SOURCES diff --git a/GenXIntrinsics/test/Plugin/Plugin.cpp b/GenXIntrinsics/test/Plugin/Plugin.cpp index c2e69f06..522d2ba6 100644 --- a/GenXIntrinsics/test/Plugin/Plugin.cpp +++ b/GenXIntrinsics/test/Plugin/Plugin.cpp @@ -2,26 +2,8 @@ Copyright (C) 2020-2021 Intel Corporation -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -the rights to use, copy, modify, merge, publish, distribute, sublicense, -and/or sell copies of the Software, and to permit persons to whom the -Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -IN THE SOFTWARE. - SPDX-License-Identifier: MIT + ============================= end_copyright_notice ===========================*/ #include "llvm/GenXIntrinsics/GenXSimdCFLowering.h" diff --git a/GenXIntrinsics/test/SimdCFLowering/bitcast_between_wrrs.ll b/GenXIntrinsics/test/SimdCFLowering/bitcast_between_wrrs.ll index ba47f077..2dd74cbc 100644 --- a/GenXIntrinsics/test/SimdCFLowering/bitcast_between_wrrs.ll +++ b/GenXIntrinsics/test/SimdCFLowering/bitcast_between_wrrs.ll @@ -2,26 +2,8 @@ ; ; Copyright (C) 2020-2021 Intel Corporation ; -; Permission is hereby granted, free of charge, to any person obtaining a copy -; of this software and associated documentation files (the "Software"), -; to deal in the Software without restriction, including without limitation -; the rights to use, copy, modify, merge, publish, distribute, sublicense, -; and/or sell copies of the Software, and to permit persons to whom the -; Software is furnished to do so, subject to the following conditions: -; -; The above copyright notice and this permission notice (including the next -; paragraph) shall be included in all copies or substantial portions of the -; Software. -; -; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -; FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -; IN THE SOFTWARE. -; ; SPDX-License-Identifier: MIT +; ;============================ end_copyright_notice ============================= ; XFAIL: llvm13 diff --git a/GenXIntrinsics/test/SimdCFLowering/predicate_masked_gather.ll b/GenXIntrinsics/test/SimdCFLowering/predicate_masked_gather.ll index 634279ee..c3b4e0be 100644 --- a/GenXIntrinsics/test/SimdCFLowering/predicate_masked_gather.ll +++ b/GenXIntrinsics/test/SimdCFLowering/predicate_masked_gather.ll @@ -2,26 +2,8 @@ ; ; Copyright (C) 2020-2021 Intel Corporation ; -; Permission is hereby granted, free of charge, to any person obtaining a copy -; of this software and associated documentation files (the "Software"), -; to deal in the Software without restriction, including without limitation -; the rights to use, copy, modify, merge, publish, distribute, sublicense, -; and/or sell copies of the Software, and to permit persons to whom the -; Software is furnished to do so, subject to the following conditions: -; -; The above copyright notice and this permission notice (including the next -; paragraph) shall be included in all copies or substantial portions of the -; Software. -; -; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -; FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -; IN THE SOFTWARE. -; ; SPDX-License-Identifier: MIT +; ;============================ end_copyright_notice ============================= ; XFAIL: llvm13 diff --git a/GenXIntrinsics/test/SimdCFLowering/replicate_mask.ll b/GenXIntrinsics/test/SimdCFLowering/replicate_mask.ll index 98ebac41..c6efd95f 100644 --- a/GenXIntrinsics/test/SimdCFLowering/replicate_mask.ll +++ b/GenXIntrinsics/test/SimdCFLowering/replicate_mask.ll @@ -2,26 +2,8 @@ ; ; Copyright (C) 2020-2021 Intel Corporation ; -; Permission is hereby granted, free of charge, to any person obtaining a copy -; of this software and associated documentation files (the "Software"), -; to deal in the Software without restriction, including without limitation -; the rights to use, copy, modify, merge, publish, distribute, sublicense, -; and/or sell copies of the Software, and to permit persons to whom the -; Software is furnished to do so, subject to the following conditions: -; -; The above copyright notice and this permission notice (including the next -; paragraph) shall be included in all copies or substantial portions of the -; Software. -; -; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -; FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -; IN THE SOFTWARE. -; ; SPDX-License-Identifier: MIT +; ;============================ end_copyright_notice ============================= ; XFAIL: llvm13 diff --git a/GenXIntrinsics/test/SimdCFLowering/replicate_mask_masked_gather4.ll b/GenXIntrinsics/test/SimdCFLowering/replicate_mask_masked_gather4.ll index 0266744c..5a05b289 100644 --- a/GenXIntrinsics/test/SimdCFLowering/replicate_mask_masked_gather4.ll +++ b/GenXIntrinsics/test/SimdCFLowering/replicate_mask_masked_gather4.ll @@ -2,26 +2,8 @@ ; ; Copyright (C) 2021 Intel Corporation ; -; Permission is hereby granted, free of charge, to any person obtaining a copy -; of this software and associated documentation files (the "Software"), -; to deal in the Software without restriction, including without limitation -; the rights to use, copy, modify, merge, publish, distribute, sublicense, -; and/or sell copies of the Software, and to permit persons to whom the -; Software is furnished to do so, subject to the following conditions: -; -; The above copyright notice and this permission notice (including the next -; paragraph) shall be included in all copies or substantial portions of the -; Software. -; -; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -; FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -; IN THE SOFTWARE. -; ; SPDX-License-Identifier: MIT +; ;============================ end_copyright_notice ============================= ; XFAIL: llvm13 diff --git a/GenXIntrinsics/test/SimdCFLowering/update_mask_masked_gather4.ll b/GenXIntrinsics/test/SimdCFLowering/update_mask_masked_gather4.ll index 14440284..eb1aae0e 100644 --- a/GenXIntrinsics/test/SimdCFLowering/update_mask_masked_gather4.ll +++ b/GenXIntrinsics/test/SimdCFLowering/update_mask_masked_gather4.ll @@ -2,26 +2,8 @@ ; ; Copyright (C) 2020-2021 Intel Corporation ; -; Permission is hereby granted, free of charge, to any person obtaining a copy -; of this software and associated documentation files (the "Software"), -; to deal in the Software without restriction, including without limitation -; the rights to use, copy, modify, merge, publish, distribute, sublicense, -; and/or sell copies of the Software, and to permit persons to whom the -; Software is furnished to do so, subject to the following conditions: -; -; The above copyright notice and this permission notice (including the next -; paragraph) shall be included in all copies or substantial portions of the -; Software. -; -; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -; FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -; IN THE SOFTWARE. -; ; SPDX-License-Identifier: MIT +; ;============================ end_copyright_notice ============================= ; XFAIL: llvm13 diff --git a/GenXIntrinsics/test/lit.cfg.py b/GenXIntrinsics/test/lit.cfg.py index 092a6aa2..51a1f2d6 100644 --- a/GenXIntrinsics/test/lit.cfg.py +++ b/GenXIntrinsics/test/lit.cfg.py @@ -2,26 +2,8 @@ # # Copyright (C) 2020-2021 Intel Corporation # -# Permission is hereby granted, free of charge, to any person obtaining a copy -# of this software and associated documentation files (the "Software"), -# to deal in the Software without restriction, including without limitation -# the rights to use, copy, modify, merge, publish, distribute, sublicense, -# and/or sell copies of the Software, and to permit persons to whom the -# Software is furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice (including the next -# paragraph) shall be included in all copies or substantial portions of the -# Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -# IN THE SOFTWARE. -# # SPDX-License-Identifier: MIT +# #============================ end_copyright_notice ============================= # -*- Python -*- diff --git a/GenXIntrinsics/test/lit.site.cfg.py.in b/GenXIntrinsics/test/lit.site.cfg.py.in index 1eb2237b..5ee435e7 100644 --- a/GenXIntrinsics/test/lit.site.cfg.py.in +++ b/GenXIntrinsics/test/lit.site.cfg.py.in @@ -2,26 +2,8 @@ # # Copyright (C) 2020-2021 Intel Corporation # -# Permission is hereby granted, free of charge, to any person obtaining a copy -# of this software and associated documentation files (the "Software"), -# to deal in the Software without restriction, including without limitation -# the rights to use, copy, modify, merge, publish, distribute, sublicense, -# and/or sell copies of the Software, and to permit persons to whom the -# Software is furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice (including the next -# paragraph) shall be included in all copies or substantial portions of the -# Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -# IN THE SOFTWARE. -# # SPDX-License-Identifier: MIT +# #============================ end_copyright_notice ============================= @LIT_SITE_CFG_IN_HEADER@ diff --git a/GenXIntrinsics/unittests/CMakeLists.txt b/GenXIntrinsics/unittests/CMakeLists.txt index c8751204..46393500 100644 --- a/GenXIntrinsics/unittests/CMakeLists.txt +++ b/GenXIntrinsics/unittests/CMakeLists.txt @@ -2,26 +2,8 @@ # # Copyright (C) 2019-2021 Intel Corporation # -# Permission is hereby granted, free of charge, to any person obtaining a copy -# of this software and associated documentation files (the "Software"), -# to deal in the Software without restriction, including without limitation -# the rights to use, copy, modify, merge, publish, distribute, sublicense, -# and/or sell copies of the Software, and to permit persons to whom the -# Software is furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice (including the next -# paragraph) shall be included in all copies or substantial portions of the -# Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -# IN THE SOFTWARE. -# # SPDX-License-Identifier: MIT +# #============================ end_copyright_notice ============================= add_custom_target(GenXIntrinsicsUnitTests) diff --git a/GenXIntrinsics/unittests/GenXIntrinsics/CMakeLists.txt b/GenXIntrinsics/unittests/GenXIntrinsics/CMakeLists.txt index 5afdde7d..8befa3c5 100644 --- a/GenXIntrinsics/unittests/GenXIntrinsics/CMakeLists.txt +++ b/GenXIntrinsics/unittests/GenXIntrinsics/CMakeLists.txt @@ -2,26 +2,8 @@ # # Copyright (C) 2019-2021 Intel Corporation # -# Permission is hereby granted, free of charge, to any person obtaining a copy -# of this software and associated documentation files (the "Software"), -# to deal in the Software without restriction, including without limitation -# the rights to use, copy, modify, merge, publish, distribute, sublicense, -# and/or sell copies of the Software, and to permit persons to whom the -# Software is furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice (including the next -# paragraph) shall be included in all copies or substantial portions of the -# Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -# IN THE SOFTWARE. -# # SPDX-License-Identifier: MIT +# #============================ end_copyright_notice ============================= set(LLVM_LINK_COMPONENTS diff --git a/GenXIntrinsics/unittests/GenXIntrinsics/GenXIntrinsicsTest.cpp b/GenXIntrinsics/unittests/GenXIntrinsics/GenXIntrinsicsTest.cpp index 78309dd4..01fef597 100644 --- a/GenXIntrinsics/unittests/GenXIntrinsics/GenXIntrinsicsTest.cpp +++ b/GenXIntrinsics/unittests/GenXIntrinsics/GenXIntrinsicsTest.cpp @@ -2,26 +2,8 @@ Copyright (C) 2019-2021 Intel Corporation -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -the rights to use, copy, modify, merge, publish, distribute, sublicense, -and/or sell copies of the Software, and to permit persons to whom the -Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -IN THE SOFTWARE. - SPDX-License-Identifier: MIT + ============================= end_copyright_notice ===========================*/ #include "llvm/ADT/StringRef.h" diff --git a/Readme.md b/Readme.md index 3fc0b9f1..fd9e186c 100644 --- a/Readme.md +++ b/Readme.md @@ -2,26 +2,8 @@ Copyright (C) 2020-2021 Intel Corporation -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -the rights to use, copy, modify, merge, publish, distribute, sublicense, -and/or sell copies of the Software, and to permit persons to whom the -Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -IN THE SOFTWARE. - SPDX-License-Identifier: MIT + ============================= end_copyright_notice ==========================--> # VC Intrinsics From 185f382cc9d564d34c3cb9452762e496f43d3fd7 Mon Sep 17 00:00:00 2001 From: lgotszal Date: Thu, 22 Jul 2021 07:43:26 +0000 Subject: [PATCH 22/81] update copyright headers update Python copyright to PEP8 style --- GenXIntrinsics/docs/conf.py | 4 ++-- .../include/llvm/GenXIntrinsics/Intrinsic_definitions.py | 4 ++-- GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py | 4 ++-- GenXIntrinsics/test/lit.cfg.py | 4 ++-- GenXIntrinsics/test/lit.site.cfg.py.in | 4 ++-- 5 files changed, 10 insertions(+), 10 deletions(-) diff --git a/GenXIntrinsics/docs/conf.py b/GenXIntrinsics/docs/conf.py index 03c33e4d..8201c69e 100644 --- a/GenXIntrinsics/docs/conf.py +++ b/GenXIntrinsics/docs/conf.py @@ -1,10 +1,10 @@ -#=========================== begin_copyright_notice ============================ +# ========================== begin_copyright_notice ============================ # # Copyright (C) 2019-2021 Intel Corporation # # SPDX-License-Identifier: MIT # -#============================ end_copyright_notice ============================= +# =========================== end_copyright_notice ============================= # -*- coding: utf-8 -*- # diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py index be8139f7..cd9255c1 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py @@ -1,10 +1,10 @@ -#=========================== begin_copyright_notice ============================ +# ========================== begin_copyright_notice ============================ # # Copyright (C) 2019-2021 Intel Corporation # # SPDX-License-Identifier: MIT # -#============================ end_copyright_notice ============================= +# =========================== end_copyright_notice ============================= #===----------------------------------------------------------------------===// # diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py index 90e6dabb..29e1592f 100755 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py @@ -1,12 +1,12 @@ #!/usr/bin/env python -#=========================== begin_copyright_notice ============================ +# ========================== begin_copyright_notice ============================ # # Copyright (C) 2019-2021 Intel Corporation # # SPDX-License-Identifier: MIT # -#============================ end_copyright_notice ============================= +# =========================== end_copyright_notice ============================= import os import sys diff --git a/GenXIntrinsics/test/lit.cfg.py b/GenXIntrinsics/test/lit.cfg.py index 51a1f2d6..2e3a4eae 100644 --- a/GenXIntrinsics/test/lit.cfg.py +++ b/GenXIntrinsics/test/lit.cfg.py @@ -1,10 +1,10 @@ -#=========================== begin_copyright_notice ============================ +# ========================== begin_copyright_notice ============================ # # Copyright (C) 2020-2021 Intel Corporation # # SPDX-License-Identifier: MIT # -#============================ end_copyright_notice ============================= +# =========================== end_copyright_notice ============================= # -*- Python -*- diff --git a/GenXIntrinsics/test/lit.site.cfg.py.in b/GenXIntrinsics/test/lit.site.cfg.py.in index 5ee435e7..588e895d 100644 --- a/GenXIntrinsics/test/lit.site.cfg.py.in +++ b/GenXIntrinsics/test/lit.site.cfg.py.in @@ -1,10 +1,10 @@ -#=========================== begin_copyright_notice ============================ +# ========================== begin_copyright_notice ============================ # # Copyright (C) 2020-2021 Intel Corporation # # SPDX-License-Identifier: MIT # -#============================ end_copyright_notice ============================= +# =========================== end_copyright_notice ============================= @LIT_SITE_CFG_IN_HEADER@ From 43b1af8933c75c045c7d5e659bf98eaa57811071 Mon Sep 17 00:00:00 2001 From: Nikita Rudenko Date: Tue, 27 Jul 2021 12:36:20 +0000 Subject: [PATCH 23/81] Fix typo in GenXIntrinsics/CMakeLists.txt --- GenXIntrinsics/CMakeLists.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/GenXIntrinsics/CMakeLists.txt b/GenXIntrinsics/CMakeLists.txt index b9f1daee..3c4f9c0f 100644 --- a/GenXIntrinsics/CMakeLists.txt +++ b/GenXIntrinsics/CMakeLists.txt @@ -22,8 +22,8 @@ include(cmake/utils.cmake) # Global config. add_compile_definitions(VC_INTR_LLVM_VERSION_MAJOR=${LLVM_VERSION_MAJOR}) -include_directories(${CMAKE_CURRENT_SOURCE_DIR}/GenXIntrinsics/include) -include_directories(${CMAKE_CURRENT_BINARY_DIR}/GenXIntrinsics/include) +include_directories(${CMAKE_CURRENT_SOURCE_DIR}/include) +include_directories(${CMAKE_CURRENT_BINARY_DIR}/include) set(GENX_INTRINSICS_DESCRIPTION "GenXIntrinsicDescription.gen") From 05d3f3d2b9ae59d32893976e0e76415fec1108b9 Mon Sep 17 00:00:00 2001 From: Nikita Rudenko Date: Thu, 24 Jun 2021 14:54:03 +0000 Subject: [PATCH 24/81] Add global variables support to GenXSingleElementVector pass --- .../llvm/GenXIntrinsics/GenXMetadata.h | 2 +- .../include/llvmVCWrapper/Support/Alignment.h | 2 +- .../GenXSingleElementVectorUtil.cpp | 147 +++++++++++++++--- .../test/Adaptors/sev_signature_reader.ll | 27 ++++ .../test/Adaptors/sev_signature_writer.ll | 26 ++++ 5 files changed, 181 insertions(+), 23 deletions(-) diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXMetadata.h b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXMetadata.h index 2ee5bb1c..58b4d483 100755 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXMetadata.h +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXMetadata.h @@ -38,6 +38,7 @@ namespace VCModuleMD { static constexpr const char VCGlobalVariable[] = "VCGlobalVariable"; static constexpr const char VCVolatile[] = "VCVolatile"; static constexpr const char VCByteOffset[] = "VCByteOffset"; +static constexpr const char VCSingleElementVector[] = "VCSingleElementVector"; } // namespace VCModuleMD namespace VCFunctionMD { @@ -51,7 +52,6 @@ static constexpr const char VCSLMSize[] = "VCSLMSize"; static constexpr const char VCArgumentKind[] = "VCArgumentKind"; static constexpr const char VCArgumentDesc[] = "VCArgumentDesc"; static constexpr const char VCSIMTCall[] = "VCSIMTCall"; -static constexpr const char VCSingleElementVector[] = "VCSingleElementVector"; } // namespace VCFunctionMD enum KernelMDOp { diff --git a/GenXIntrinsics/include/llvmVCWrapper/Support/Alignment.h b/GenXIntrinsics/include/llvmVCWrapper/Support/Alignment.h index b7850fb0..7ef5d2b4 100755 --- a/GenXIntrinsics/include/llvmVCWrapper/Support/Alignment.h +++ b/GenXIntrinsics/include/llvmVCWrapper/Support/Alignment.h @@ -26,7 +26,7 @@ template llvm::MaybeAlign getAlign(TValue *Val) { return llvm::MaybeAlign(Val->getAlignment()); } #else -template llvm::Align getAlign(TValue *Val) { +template auto getAlign(TValue *Val) { return Val->getAlign(); } #endif diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp index ef659ec6..1f664dd9 100755 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp @@ -52,6 +52,15 @@ static std::vector getFunctions(Module &M) { return Functions; } +// Globals with SEVs are deleted from module +// This util allows to continue iteration even after deletion +static std::vector getGlobalVariables(Module &M) { + auto Globals = std::vector{}; + std::transform(M.global_begin(), M.global_end(), std::back_inserter(Globals), + [](GlobalVariable &GV) { return &GV; }); + return Globals; +} + // Instructions with SEVs are deleted from module // This util allows to continue iteration even after deletion static std::vector getInstructions(Function &F) { @@ -192,16 +201,19 @@ static Value *createVectorToScalarValue(Value *Vector, Instruction *InsertBefore, size_t idx = 0) { assert(hasSingleElementVector(Vector->getType())); - if (isa(Vector->getType())) + if (isa(Vector)) + return UndefValue::get( + getTypeFreeFromSingleElementVector(Vector->getType())); + else if (isa(Vector->getType())) return new BitCastInst( - Vector, getTypeFreeFromSingleElementVector(Vector->getType()), "", - InsertBefore); + Vector, getTypeFreeFromSingleElementVector(Vector->getType()), + "sev.cast.", InsertBefore); else if (auto *Const = dyn_cast(Vector)) return Const->getAggregateElement(idx); else { auto *M = InsertBefore->getModule(); - return ExtractElementInst::Create(Vector, getVectorIndex(*M, idx), "", - InsertBefore); + return ExtractElementInst::Create(Vector, getVectorIndex(*M, idx), + "sev.cast.", InsertBefore); } } @@ -212,14 +224,19 @@ static Value *createVectorToScalarValue(Value *Vector, static Value *createVectorToScalarValue(Value *Vector, BasicBlock *BB, size_t idx = 0) { assert(hasSingleElementVector(Vector->getType())); - if (isa(Vector->getType())) + if (isa(Vector)) + return UndefValue::get( + getTypeFreeFromSingleElementVector(Vector->getType())); + else if (isa(Vector->getType())) return new BitCastInst( - Vector, getTypeFreeFromSingleElementVector(Vector->getType()), "", BB); + Vector, getTypeFreeFromSingleElementVector(Vector->getType()), + "sev.cast.", BB); else if (auto *Const = dyn_cast(Vector)) return Const->getAggregateElement(idx); else { auto *M = BB->getModule(); - return ExtractElementInst::Create(Vector, getVectorIndex(*M, idx), "", BB); + return ExtractElementInst::Create(Vector, getVectorIndex(*M, idx), + "sev.cast.", BB); } } @@ -229,19 +246,20 @@ static Value *createVectorToScalarValue(Value *Vector, BasicBlock *BB, // For non-constant vectors it returns InsertElementInst static Value *createScalarToVectorValue(Value *Scalar, Type *ReferenceType, Instruction *InsertBefore) { - if (isa(Scalar->getType())) { + if (isa(Scalar)) + return UndefValue::get(ReferenceType); + else if (isa(Scalar->getType())) { auto Inner = getInnerPointerVectorNesting(ReferenceType); return new BitCastInst( - Scalar, getTypeWithSingleElementVector(Scalar->getType(), Inner), "", - InsertBefore); - } else if (isa(Scalar)) - return UndefValue::get(ReferenceType); - else if (auto *Const = dyn_cast(Scalar)) + Scalar, getTypeWithSingleElementVector(Scalar->getType(), Inner), + "sev.cast.", InsertBefore); + } else if (auto *Const = dyn_cast(Scalar)) return ConstantInt::getSigned(ReferenceType, getConstantElement(Const)); else { auto *M = InsertBefore->getModule(); return InsertElementInst::Create(UndefValue::get(ReferenceType), Scalar, - getVectorIndex(*M, 0), "", InsertBefore); + getVectorIndex(*M, 0), "sev.cast.", + InsertBefore); } } @@ -441,11 +459,11 @@ static void manageSingleElementVectorAttribute(Function &NewF, Type *OldT, assert(!hasSingleElementVector(NewT)); auto InnerPtrs = std::to_string(getInnerPointerVectorNesting(OldT)); auto Attr = Attribute::get(NewF.getContext(), - VCFunctionMD::VCSingleElementVector, InnerPtrs); + VCModuleMD::VCSingleElementVector, InnerPtrs); NewF.addAttribute(AttrNo, Attr); } else if (hasSingleElementVector(NewT)) { assert(!hasSingleElementVector(OldT)); - NewF.removeAttribute(AttrNo, VCFunctionMD::VCSingleElementVector); + NewF.removeAttribute(AttrNo, VCModuleMD::VCSingleElementVector); } } @@ -474,10 +492,10 @@ static Type *getOriginalType(Function &F, size_t AttrNo) { auto *T = AttrNo == 0 ? FuncT->getReturnType() : FuncT->getParamType(AttrNo - 1); auto Attrs = F.getAttributes(); - if (!Attrs.hasAttribute(AttrNo, VCFunctionMD::VCSingleElementVector)) + if (!Attrs.hasAttribute(AttrNo, VCModuleMD::VCSingleElementVector)) return T; auto InnerPtrsStr = - Attrs.getAttribute(AttrNo, VCFunctionMD::VCSingleElementVector) + Attrs.getAttribute(AttrNo, VCModuleMD::VCSingleElementVector) .getValueAsString(); auto InnerPtrs = InnerPtrsStr.empty() ? 0 : std::stoull(InnerPtrsStr.str()); return getTypeWithSingleElementVector(T, InnerPtrs); @@ -723,6 +741,93 @@ class SingleElementVectorInstRewriter } }; +/// This section contains utils for rewriting global variables + +// For conversion in SEV-rich to SEV-free direction +// this function adds VCSingleElementVector attribute to global var +static void manageSingleElementVectorAttribute(GlobalVariable &GV, Type *OldT, + Type *NewT) { + if (hasSingleElementVector(OldT)) { + assert(!hasSingleElementVector(NewT)); + auto InnerPtrs = std::to_string(getInnerPointerVectorNesting(OldT)); + GV.addAttribute(VCModuleMD::VCSingleElementVector, InnerPtrs); + } +} + +static GlobalVariable &createAndTakeFrom(GlobalVariable &GV, PointerType *NewT, + Constant *Initializer) { + auto *NewGV = new GlobalVariable( + *GV.getParent(), NewT->getElementType(), GV.isConstant(), GV.getLinkage(), + Initializer, "sev.global.", &GV, GV.getThreadLocalMode(), + VCINTR::GlobalValue::getAddressSpace(GV), GV.isExternallyInitialized()); + auto DebugInfoVec = SmallVector{}; + GV.getDebugInfo(DebugInfoVec); + NewGV->takeName(&GV); + NewGV->setAttributes(GV.getAttributes()); + NewGV->copyMetadata(&GV, 0); + NewGV->setComdat(GV.getComdat()); + NewGV->setAlignment(VCINTR::Align::getAlign(&GV)); + for (auto *DebugInf : DebugInfoVec) + NewGV->addDebugInfo(DebugInf); + return *NewGV; +} + +static void rewriteGlobalVariable(GlobalVariable &GV) { + auto *T = cast(GV.getType()); + auto *NewT = cast(getTypeFreeFromSingleElementVector(T)); + if (NewT == T) + return; + auto *Initializer = static_cast(nullptr); + if (GV.hasInitializer()) + Initializer = cast(createVectorToScalarValue( + GV.getInitializer(), static_cast(nullptr))); + auto &&NewGV = createAndTakeFrom(GV, NewT, Initializer); + while (GV.use_begin() != GV.use_end()) { + auto &&Use = GV.use_begin(); + auto *Inst = cast(Use->getUser()); + auto *V = createScalarToVectorValue(&NewGV, T, Inst); + *Use = V; + } + manageSingleElementVectorAttribute(NewGV, T, NewT); + GV.eraseFromParent(); +} + +static void restoreGlobalVariable(GlobalVariable &GV) { + auto *T = cast(GV.getType()); + if (!GV.hasAttribute(VCModuleMD::VCSingleElementVector)) + return; + auto InnerPtrsStr = + GV.getAttribute(VCModuleMD::VCSingleElementVector).getValueAsString(); + auto InnerPtrs = InnerPtrsStr.empty() ? 0 : std::stoull(InnerPtrsStr.str()); + auto *NewT = cast(getTypeWithSingleElementVector(T, InnerPtrs)); + if (NewT == T) + return; + auto *Initializer = static_cast(nullptr); + if (GV.hasInitializer()) + Initializer = cast( + createScalarToVectorValue(GV.getInitializer(), NewT->getElementType(), + static_cast(nullptr))); + auto &&NewGV = createAndTakeFrom(GV, NewT, Initializer); + while (GV.use_begin() != GV.use_end()) { + auto &&Use = GV.use_begin(); + auto *Inst = cast(Use->getUser()); + auto *V = createVectorToScalarValue(&NewGV, Inst); + *Use = V; + } + manageSingleElementVectorAttribute(NewGV, T, NewT); + GV.eraseFromParent(); +} + +static void rewriteGlobalVariables(Module &M, bool IsScalarToVector = false) { + auto &&Globals = getGlobalVariables(M); + for (auto *GV : Globals) { + if (IsScalarToVector) + restoreGlobalVariable(*GV); + else + rewriteGlobalVariable(*GV); + } +} + /// This section contains utils for collapsing pairs of convertion instructions /// After rewriting all insructions in the module there are lots of pairs /// Extract-insert and bitcast-bitcast conversions left @@ -873,7 +978,7 @@ static void collapseInsertInstructions(Function &F, /// They either remove or restore Single Element Vectors in the module void rewriteSingleElementVectors(Module &M) { - // TODO: rewrite globals + rewriteGlobalVariables(M, /*IsScalarToVector=*/false); auto Functions = getFunctions(M); for (auto *F : Functions) @@ -893,7 +998,7 @@ void rewriteSingleElementVectors(Module &M) { } void restoreSingleElementVectors(Module &M) { - // TODO: rewrite globals + rewriteGlobalVariables(M, /*IsScalarToVector=*/true); auto Functions = getFunctions(M); for (auto *F : Functions) diff --git a/GenXIntrinsics/test/Adaptors/sev_signature_reader.ll b/GenXIntrinsics/test/Adaptors/sev_signature_reader.ll index b9923252..b3647506 100644 --- a/GenXIntrinsics/test/Adaptors/sev_signature_reader.ll +++ b/GenXIntrinsics/test/Adaptors/sev_signature_reader.ll @@ -11,9 +11,31 @@ ; RUN: opt -S -GenXSPIRVReaderAdaptor < %s | FileCheck %s +; CHECK: @global_var_0 = internal global <1 x i32> undef, align 4 +@global_var_0 = internal global i32 undef, align 4 #2 + +; CHECK: @global_var_1 = internal global <1 x i32**> undef, align 4 +@global_var_1 = internal global i32** undef, align 4 #3 + +; CHECK: @global_var_2 = external global <1 x i32**> +@global_var_2 = external global i32** #3 + +; CHECK: @global_var_3 = internal global i32** undef, align 4 +@global_var_3 = internal global i32** undef, align 4 + ; CHECK: <1 x i32> @some.func.1(<1 x i32> %a, <1 x i32> %b) define internal "VCSingleElementVector" i32 @some.func.1(i32 "VCSingleElementVector" %a, i32 "VCSingleElementVector" %b) local_unnamed_addr #0 { entry: + +; CHECK: call void @llvm.genx.some.intr.0(<1 x i32>* @global_var_0) + call void @llvm.genx.some.intr.0(i32* @global_var_0) + +; CHECK: call void @llvm.genx.some.intr.1(<1 x i32**>* @global_var_1) + call void @llvm.genx.some.intr.1(i32*** @global_var_1) + +; CHECK: call void @llvm.genx.some.intr.1(<1 x i32**>* @global_var_2) + call void @llvm.genx.some.intr.1(i32*** @global_var_2) + ret i32 %a } @@ -40,5 +62,10 @@ entry: ret void } +declare void @llvm.genx.some.intr.0(i32* "VCSingleElementVector") +declare void @llvm.genx.some.intr.1(i32*** "VCSingleElementVector"="2") + attributes #0 = { "VCFunction" } attributes #1 = { "VCFunction" "VCNamedBarrierCount"="0" "VCSLMSize"="0" } +attributes #2 = { "VCGlobalVariable" "VCSingleElementVector"="0" } +attributes #3 = { "VCGlobalVariable" "VCSingleElementVector"="2" } diff --git a/GenXIntrinsics/test/Adaptors/sev_signature_writer.ll b/GenXIntrinsics/test/Adaptors/sev_signature_writer.ll index 12935184..de5da211 100644 --- a/GenXIntrinsics/test/Adaptors/sev_signature_writer.ll +++ b/GenXIntrinsics/test/Adaptors/sev_signature_writer.ll @@ -10,9 +10,28 @@ ; RUN: opt -S -GenXSPIRVWriterAdaptor < %s | FileCheck %s +; CHECK: @global_var_0 = internal global i32 undef, align 4 +@global_var_0 = internal global <1 x i32> undef, align 4 #0 + +; CHECK: @global_var_1 = internal global i32** undef, align 4 +@global_var_1 = internal global <1 x i32**> undef, align 4 #0 + +; CHECK: @global_var_2 = external global i32** +@global_var_2 = external global <1 x i32**> #0 + ; CHECK: "VCSingleElementVector"="0" i32 @some.func.1(i32 "VCSingleElementVector"="0" %a, i32 "VCSingleElementVector"="0" %b) define dso_local <1 x i32> @some.func.1(<1 x i32> %a, <1 x i32> %b) local_unnamed_addr { entry: + +; CHECK: call void @llvm.genx.some.intr.0(i32* @global_var_0) + call void @llvm.genx.some.intr.0(<1 x i32>* @global_var_0) + +; CHECK: call void @llvm.genx.some.intr.1(i32*** @global_var_1) + call void @llvm.genx.some.intr.1(<1 x i32**>* @global_var_1) + +; CHECK: call void @llvm.genx.some.intr.1(i32*** @global_var_2) + call void @llvm.genx.some.intr.1(<1 x i32**>* @global_var_2) + ret <1 x i32> %a } @@ -42,6 +61,13 @@ entry: ret void } +declare void @llvm.genx.some.intr.0(<1 x i32>*) +declare void @llvm.genx.some.intr.1(<1 x i32**>*) + +; CHECK: "VCSingleElementVector"="0" +; CHECK: "VCSingleElementVector"="2" +attributes #0 = { "VCGlobalVariable" } + !genx.kernels = !{!0} !0 = !{void ()* @test, !"test", !1, i32 0, i32 0, !2, !3, i32 0} From 0bf761ef358d70b5a27292845f0def764aeb8a7f Mon Sep 17 00:00:00 2001 From: Dmitriy Drozdov Date: Thu, 29 Jul 2021 16:29:49 +0000 Subject: [PATCH 25/81] Mark lit tests as XFAIL for llvm 14 (tot) --- GenXIntrinsics/test/Adaptors/annotated_args_mixed_reader.ll | 2 +- GenXIntrinsics/test/Adaptors/annotated_args_no_conv_reader.ll | 2 +- GenXIntrinsics/test/Adaptors/annotated_args_reader.ll | 2 +- GenXIntrinsics/test/Adaptors/combined_args_reader.ll | 2 +- GenXIntrinsics/test/Adaptors/no_vcfunction_reader.ll | 2 +- GenXIntrinsics/test/Adaptors/non_global_ptr_reader.ll | 2 +- GenXIntrinsics/test/Adaptors/old_decorated_args_reader.ll | 2 +- GenXIntrinsics/test/Adaptors/plain_args_reader.ll | 2 +- GenXIntrinsics/test/Adaptors/sev_signature_reader.ll | 2 +- GenXIntrinsics/test/Adaptors/surface_access_reader.ll | 2 +- GenXIntrinsics/test/Adaptors/unknown_arg_reader.ll | 2 +- GenXIntrinsics/test/SimdCFLowering/bitcast_between_wrrs.ll | 2 +- GenXIntrinsics/test/SimdCFLowering/predicate_masked_gather.ll | 2 +- GenXIntrinsics/test/SimdCFLowering/replicate_mask.ll | 2 +- .../test/SimdCFLowering/replicate_mask_masked_gather4.ll | 2 +- .../test/SimdCFLowering/update_mask_masked_gather4.ll | 2 +- 16 files changed, 16 insertions(+), 16 deletions(-) diff --git a/GenXIntrinsics/test/Adaptors/annotated_args_mixed_reader.ll b/GenXIntrinsics/test/Adaptors/annotated_args_mixed_reader.ll index 74fc4de4..57d4aa6a 100644 --- a/GenXIntrinsics/test/Adaptors/annotated_args_mixed_reader.ll +++ b/GenXIntrinsics/test/Adaptors/annotated_args_mixed_reader.ll @@ -6,7 +6,7 @@ ; ;============================ end_copyright_notice ============================= -; XFAIL: llvm13 +; XFAIL: llvm13,llvm14 ; Test that reader can cope with mixed mode when some ; arguments use address convert and some do not. diff --git a/GenXIntrinsics/test/Adaptors/annotated_args_no_conv_reader.ll b/GenXIntrinsics/test/Adaptors/annotated_args_no_conv_reader.ll index 8628646c..5abfa391 100644 --- a/GenXIntrinsics/test/Adaptors/annotated_args_no_conv_reader.ll +++ b/GenXIntrinsics/test/Adaptors/annotated_args_no_conv_reader.ll @@ -6,7 +6,7 @@ ; ;============================ end_copyright_notice ============================= -; XFAIL: llvm13 +; XFAIL: llvm13,llvm14 ; Test that reader correctly restores metadata and does ; not change other things if there is no address conversion ; but correct SPIRV types in signature. diff --git a/GenXIntrinsics/test/Adaptors/annotated_args_reader.ll b/GenXIntrinsics/test/Adaptors/annotated_args_reader.ll index 112046c1..1638daea 100644 --- a/GenXIntrinsics/test/Adaptors/annotated_args_reader.ll +++ b/GenXIntrinsics/test/Adaptors/annotated_args_reader.ll @@ -6,7 +6,7 @@ ; ;============================ end_copyright_notice ============================= -; XFAIL: llvm13 +; XFAIL: llvm13,llvm14 ; Test kernel argument translation from new style with opaque types ; that SPIRV translator can understand to old style with ; metadata. Here annotations for OCL runtime are used. diff --git a/GenXIntrinsics/test/Adaptors/combined_args_reader.ll b/GenXIntrinsics/test/Adaptors/combined_args_reader.ll index ec243067..d48662a6 100644 --- a/GenXIntrinsics/test/Adaptors/combined_args_reader.ll +++ b/GenXIntrinsics/test/Adaptors/combined_args_reader.ll @@ -6,7 +6,7 @@ ; ;============================ end_copyright_notice ============================= -; XFAIL: llvm13 +; XFAIL: llvm13,llvm14 ; Test combined reader translation: kernel has both native SPIRV types ; and impicit arguments. Implicit arguments would not show in normal ; flow, though they appear in old cmc. diff --git a/GenXIntrinsics/test/Adaptors/no_vcfunction_reader.ll b/GenXIntrinsics/test/Adaptors/no_vcfunction_reader.ll index 9bbd8610..c447bb8e 100644 --- a/GenXIntrinsics/test/Adaptors/no_vcfunction_reader.ll +++ b/GenXIntrinsics/test/Adaptors/no_vcfunction_reader.ll @@ -6,7 +6,7 @@ ; ;============================ end_copyright_notice ============================= -; XFAIL: llvm13 +; XFAIL: llvm13,llvm14 ; Test that reader ignores signature rewriting for kernels ; that are not VCFunction. diff --git a/GenXIntrinsics/test/Adaptors/non_global_ptr_reader.ll b/GenXIntrinsics/test/Adaptors/non_global_ptr_reader.ll index 9008715d..a2e467db 100644 --- a/GenXIntrinsics/test/Adaptors/non_global_ptr_reader.ll +++ b/GenXIntrinsics/test/Adaptors/non_global_ptr_reader.ll @@ -6,7 +6,7 @@ ; ;============================ end_copyright_notice ============================= -; XFAIL: llvm13 +; XFAIL: llvm13,llvm14 ; Test that reader treats only global pointer as svmptr type ; and ignores other address spaces. diff --git a/GenXIntrinsics/test/Adaptors/old_decorated_args_reader.ll b/GenXIntrinsics/test/Adaptors/old_decorated_args_reader.ll index ea6179d6..141d7f2b 100644 --- a/GenXIntrinsics/test/Adaptors/old_decorated_args_reader.ll +++ b/GenXIntrinsics/test/Adaptors/old_decorated_args_reader.ll @@ -6,7 +6,7 @@ ; ;============================ end_copyright_notice ============================= -; XFAIL: llvm13 +; XFAIL: llvm13,llvm14 ; Test reader translation of old-style decorated arguments. ; Annotations for these are directly translated from attributes to ; kernel metadata without any checks. Required until full transition diff --git a/GenXIntrinsics/test/Adaptors/plain_args_reader.ll b/GenXIntrinsics/test/Adaptors/plain_args_reader.ll index f7738490..faf2e89a 100644 --- a/GenXIntrinsics/test/Adaptors/plain_args_reader.ll +++ b/GenXIntrinsics/test/Adaptors/plain_args_reader.ll @@ -6,7 +6,7 @@ ; ;============================ end_copyright_notice ============================= -; XFAIL: llvm13 +; XFAIL: llvm13,llvm14 ; Test kernel argument translation from new style with opaque types ; that SPIRV translator can understand to old style with ; metadata. Arguments without annotations are used here (CMRT like). diff --git a/GenXIntrinsics/test/Adaptors/sev_signature_reader.ll b/GenXIntrinsics/test/Adaptors/sev_signature_reader.ll index b3647506..63c43958 100644 --- a/GenXIntrinsics/test/Adaptors/sev_signature_reader.ll +++ b/GenXIntrinsics/test/Adaptors/sev_signature_reader.ll @@ -6,7 +6,7 @@ ; ;============================ end_copyright_notice ============================= -; XFAIL: llvm13 +; XFAIL: llvm13, llvm14 ; Test simple signatures tranform ; RUN: opt -S -GenXSPIRVReaderAdaptor < %s | FileCheck %s diff --git a/GenXIntrinsics/test/Adaptors/surface_access_reader.ll b/GenXIntrinsics/test/Adaptors/surface_access_reader.ll index 8cbfb460..75fe3051 100644 --- a/GenXIntrinsics/test/Adaptors/surface_access_reader.ll +++ b/GenXIntrinsics/test/Adaptors/surface_access_reader.ll @@ -6,7 +6,7 @@ ; ;============================ end_copyright_notice ============================= -; XFAIL: llvm13 +; XFAIL: llvm13,llvm14 ; Test kernel surface argument translation from new style with opaque ; types that SPIRV translator can understand to old style with ; metadata. This test checks access qualifiers translation. diff --git a/GenXIntrinsics/test/Adaptors/unknown_arg_reader.ll b/GenXIntrinsics/test/Adaptors/unknown_arg_reader.ll index 4058a6c6..d71fddf2 100644 --- a/GenXIntrinsics/test/Adaptors/unknown_arg_reader.ll +++ b/GenXIntrinsics/test/Adaptors/unknown_arg_reader.ll @@ -6,7 +6,7 @@ ; ;============================ end_copyright_notice ============================= -; XFAIL: llvm13 +; XFAIL: llvm13,llvm14 ; Test reader translation of implicit argument with argument kind ; decoration. diff --git a/GenXIntrinsics/test/SimdCFLowering/bitcast_between_wrrs.ll b/GenXIntrinsics/test/SimdCFLowering/bitcast_between_wrrs.ll index 2dd74cbc..e2372375 100644 --- a/GenXIntrinsics/test/SimdCFLowering/bitcast_between_wrrs.ll +++ b/GenXIntrinsics/test/SimdCFLowering/bitcast_between_wrrs.ll @@ -6,7 +6,7 @@ ; ;============================ end_copyright_notice ============================= -; XFAIL: llvm13 +; XFAIL: llvm13,llvm14 ; RUN: opt -S -cmsimdcflowering < %s | FileCheck %s @Rcp_T2 = internal global <64 x double> undef diff --git a/GenXIntrinsics/test/SimdCFLowering/predicate_masked_gather.ll b/GenXIntrinsics/test/SimdCFLowering/predicate_masked_gather.ll index c3b4e0be..f7220c6b 100644 --- a/GenXIntrinsics/test/SimdCFLowering/predicate_masked_gather.ll +++ b/GenXIntrinsics/test/SimdCFLowering/predicate_masked_gather.ll @@ -6,7 +6,7 @@ ; ;============================ end_copyright_notice ============================= -; XFAIL: llvm13 +; XFAIL: llvm13,llvm14 ; RUN: opt -S -cmsimdcflowering < %s | FileCheck %s ; CHECK: @EM = internal global <32 x i1> diff --git a/GenXIntrinsics/test/SimdCFLowering/replicate_mask.ll b/GenXIntrinsics/test/SimdCFLowering/replicate_mask.ll index c6efd95f..017c84f9 100644 --- a/GenXIntrinsics/test/SimdCFLowering/replicate_mask.ll +++ b/GenXIntrinsics/test/SimdCFLowering/replicate_mask.ll @@ -6,7 +6,7 @@ ; ;============================ end_copyright_notice ============================= -; XFAIL: llvm13 +; XFAIL: llvm13,llvm14 ; RUN: opt -S -cmsimdcflowering < %s | FileCheck %s @g1 = internal global <64 x i32> undef diff --git a/GenXIntrinsics/test/SimdCFLowering/replicate_mask_masked_gather4.ll b/GenXIntrinsics/test/SimdCFLowering/replicate_mask_masked_gather4.ll index 5a05b289..1babab42 100644 --- a/GenXIntrinsics/test/SimdCFLowering/replicate_mask_masked_gather4.ll +++ b/GenXIntrinsics/test/SimdCFLowering/replicate_mask_masked_gather4.ll @@ -6,7 +6,7 @@ ; ;============================ end_copyright_notice ============================= -; XFAIL: llvm13 +; XFAIL: llvm13,llvm14 ; RUN: opt -S -cmsimdcflowering < %s | FileCheck %s @Rcp_T2 = internal global <64 x i32> undef diff --git a/GenXIntrinsics/test/SimdCFLowering/update_mask_masked_gather4.ll b/GenXIntrinsics/test/SimdCFLowering/update_mask_masked_gather4.ll index eb1aae0e..3ab9102e 100644 --- a/GenXIntrinsics/test/SimdCFLowering/update_mask_masked_gather4.ll +++ b/GenXIntrinsics/test/SimdCFLowering/update_mask_masked_gather4.ll @@ -6,7 +6,7 @@ ; ;============================ end_copyright_notice ============================= -; XFAIL: llvm13 +; XFAIL: llvm13,llvm14 ; RUN: opt -S -cmsimdcflowering < %s | FileCheck %s @g1 = internal global <64 x i32> undef From 4e3870da11247096c1d2524e858bd2ae3df5175d Mon Sep 17 00:00:00 2001 From: Dmitriy Drozdov Date: Thu, 29 Jul 2021 09:47:33 +0000 Subject: [PATCH 26/81] Revert "Introduce new vc intrinsic to access timestamp register" --- .../llvm/GenXIntrinsics/Intrinsic_definitions.py | 13 ------------- 1 file changed, 13 deletions(-) diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py index cd9255c1..1d7fc4ba 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py @@ -1879,19 +1879,6 @@ "attributes" : "None" }, -### ``llvm.genx.tm0.`` : read vISA v6 (%tm0) -### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -### -### * Return value: vxi32 the value read -### -### The vector width must be 8 -### -### - "tm0" : { "result" : "anyint", - "arguments" : [], - "attributes" : "SideEffects" - }, - ### ``llvm.genx.get.color`` : read color value of the thread origin ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ### From 90113a56d0f0b67b268d55e685dc3c00dad9e3a0 Mon Sep 17 00:00:00 2001 From: Kirill Yansitov Date: Fri, 30 Jul 2021 21:26:25 +0000 Subject: [PATCH 27/81] add intrinsic to represent visa madw instr --- .../GenXIntrinsics/Intrinsic_definitions.py | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py index 1d7fc4ba..c9dd1a54 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py @@ -1096,6 +1096,35 @@ "attributes" : "NoMem" }, +### ``llvm.genx.*madw..`` : madw instruction, no saturation +### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +### * ``llvm.genx.smadw`` : result signed +### * ``llvm.genx.umadw`` : result unsigned +### +### result := arg0 * arg1 + arg2 +### +### * Return value: result, the full 64-bit of the results of multiplying two 32-bit +### integers and adding 32-bit integer(32b*32b+32b->64b). +### The low 32b of results are stored in the lower GRF and +### the high 32b of results are stored in the high GRF. +### +### Return width of intrinsic depends on args width: +### if args width <= GRF/sizeof(i32) then return width = 2*GRF/sizeof(i32) +### else return width = 2 * args width +### +### * arg0: first input, same element type as result +### * arg1: second input, same type as arg0 +### * arg2: third input, same type as arg0 +### + "umadw" : { "result" : "anyint", + "arguments" : ["anyint", 1, 1], + "attributes" : "NoMem" + }, + "smadw" : { "result" : "anyint", + "arguments" : ["anyint", 1, 1], + "attributes" : "NoMem" + }, + ### ``llvm.genx.*max..`` : max instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ### * ``llvm.genx.smax`` : result and operands signed From fd9bf4b3a91f853ed74a376df58123bb75f64449 Mon Sep 17 00:00:00 2001 From: Aleksander Us Date: Mon, 16 Aug 2021 13:28:05 +0000 Subject: [PATCH 28/81] Wrap AttributeList::hasFnAttr Fix intrinsics build after https://reviews.llvm.org/rG92ce6db9ee7666a347fccf0f72ba3225b199d6d1 --- .../include/llvmVCWrapper/IR/Attributes.h | 40 +++++++++++++++++++ .../GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp | 18 +++++---- .../GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp | 13 +++--- 3 files changed, 57 insertions(+), 14 deletions(-) create mode 100644 GenXIntrinsics/include/llvmVCWrapper/IR/Attributes.h diff --git a/GenXIntrinsics/include/llvmVCWrapper/IR/Attributes.h b/GenXIntrinsics/include/llvmVCWrapper/IR/Attributes.h new file mode 100644 index 00000000..eeae92fe --- /dev/null +++ b/GenXIntrinsics/include/llvmVCWrapper/IR/Attributes.h @@ -0,0 +1,40 @@ +/*========================== begin_copyright_notice ============================ + +Copyright (C) 2021 Intel Corporation + +SPDX-License-Identifier: MIT + +============================= end_copyright_notice ===========================*/ + +#ifndef VCINTR_IR_ATTRIBUTES_H +#define VCINTR_IR_ATTRIBUTES_H + +#include + +namespace VCINTR { + +namespace AttributeList { + +inline bool hasFnAttr(const llvm::AttributeList &AttrList, + llvm::Attribute::AttrKind Kind) { +#if VC_INTR_LLVM_VERSION_MAJOR >= 14 + return AttrList.hasFnAttr(Kind); +#else + return AttrList.hasFnAttribute(Kind); +#endif +} + +inline bool hasFnAttr(const llvm::AttributeList &AttrList, + llvm::StringRef Kind) { +#if VC_INTR_LLVM_VERSION_MAJOR >= 14 + return AttrList.hasFnAttr(Kind); +#else + return AttrList.hasFnAttribute(Kind); +#endif +} + +} // namespace AttributeList + +} // namespace VCINTR + +#endif // VCINTR_IR_ATTRIBUTES_H diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp index bd1a7a65..bc2e188e 100755 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp @@ -22,6 +22,7 @@ SPDX-License-Identifier: MIT #include "llvm/IR/Module.h" #include "llvm/Pass.h" +#include "llvmVCWrapper/IR/Attributes.h" #include "llvmVCWrapper/IR/Function.h" #include "llvmVCWrapper/IR/GlobalValue.h" @@ -377,7 +378,8 @@ static void rewriteKernelsTypes(Module &M) { // Skip things that are not VC kernels. if (F->getCallingConv() != CallingConv::SPIR_KERNEL) continue; - if (!F->getAttributes().hasFnAttribute(VCFunctionMD::VCFunction)) + if (!VCINTR::AttributeList::hasFnAttr(F->getAttributes(), + VCFunctionMD::VCFunction)) continue; rewriteKernelArguments(*F); } @@ -411,23 +413,23 @@ bool GenXSPIRVReaderAdaptor::runOnModule(Module &M) { bool GenXSPIRVReaderAdaptor::runOnFunction(Function &F) { auto Attrs = F.getAttributes(); - if (!Attrs.hasFnAttribute(VCFunctionMD::VCFunction)) + if (!VCINTR::AttributeList::hasFnAttr(Attrs, VCFunctionMD::VCFunction)) return true; - if (Attrs.hasFnAttribute(VCFunctionMD::VCStackCall)) { + if (VCINTR::AttributeList::hasFnAttr(Attrs, VCFunctionMD::VCStackCall)) { F.addFnAttr(FunctionMD::CMStackCall); F.addFnAttr(Attribute::NoInline); } - if (Attrs.hasFnAttribute(VCFunctionMD::VCCallable)){ + if (VCINTR::AttributeList::hasFnAttr(Attrs, VCFunctionMD::VCCallable)) { F.addFnAttr(FunctionMD::CMCallable); } - if (Attrs.hasFnAttribute(VCFunctionMD::VCFCEntry)) { + if (VCINTR::AttributeList::hasFnAttr(Attrs, VCFunctionMD::VCFCEntry)) { F.addFnAttr(FunctionMD::CMEntry); } - if (Attrs.hasFnAttribute(VCFunctionMD::VCSIMTCall)) { + if (VCINTR::AttributeList::hasFnAttr(Attrs, VCFunctionMD::VCSIMTCall)) { auto SIMTMode = StringRef(); SIMTMode = Attrs .getAttribute(AttributeList::FunctionIndex, @@ -437,7 +439,7 @@ bool GenXSPIRVReaderAdaptor::runOnFunction(Function &F) { } auto &&Context = F.getContext(); - if (Attrs.hasFnAttribute(VCFunctionMD::VCFloatControl)) { + if (VCINTR::AttributeList::hasFnAttr(Attrs, VCFunctionMD::VCFloatControl)) { auto FloatControl = unsigned(0); Attrs .getAttribute(AttributeList::FunctionIndex, @@ -475,7 +477,7 @@ bool GenXSPIRVReaderAdaptor::runOnFunction(Function &F) { llvm::Type *I32Ty = llvm::Type::getInt32Ty(Context); - if (Attrs.hasFnAttribute(VCFunctionMD::VCSLMSize)) { + if (VCINTR::AttributeList::hasFnAttr(Attrs, VCFunctionMD::VCSLMSize)) { Attrs.getAttribute(AttributeList::FunctionIndex, VCFunctionMD::VCSLMSize) .getValueAsString() .getAsInteger(0, SLMSize); diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp index 5132a17f..e6234b38 100755 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp @@ -24,6 +24,7 @@ SPDX-License-Identifier: MIT #include "llvm/Pass.h" #include "llvm/Support/Process.h" +#include "llvmVCWrapper/IR/Attributes.h" #include "llvmVCWrapper/IR/DerivedTypes.h" #include "llvmVCWrapper/IR/Function.h" #include "llvmVCWrapper/IR/GlobalValue.h" @@ -466,19 +467,19 @@ bool GenXSPIRVWriterAdaptorImpl::runOnFunction(Function &F) { F.addFnAttr(VCFunctionMD::VCFunction); auto Attrs = F.getAttributes(); - if (Attrs.hasFnAttribute(FunctionMD::CMStackCall)) { + if (VCINTR::AttributeList::hasFnAttr(Attrs, FunctionMD::CMStackCall)) { F.addFnAttr(VCFunctionMD::VCStackCall); } - if (Attrs.hasFnAttribute(FunctionMD::CMCallable)) { + if (VCINTR::AttributeList::hasFnAttr(Attrs, FunctionMD::CMCallable)) { F.addFnAttr(VCFunctionMD::VCCallable); } - if (Attrs.hasFnAttribute(FunctionMD::CMEntry)) { + if (VCINTR::AttributeList::hasFnAttr(Attrs, FunctionMD::CMEntry)) { F.addFnAttr(VCFunctionMD::VCFCEntry); } - if (Attrs.hasFnAttribute(FunctionMD::CMGenxSIMT)) { + if (VCINTR::AttributeList::hasFnAttr(Attrs, FunctionMD::CMGenxSIMT)) { auto SIMTMode = StringRef(); SIMTMode = Attrs.getAttribute(AttributeList::FunctionIndex, FunctionMD::CMGenxSIMT) @@ -487,7 +488,7 @@ bool GenXSPIRVWriterAdaptorImpl::runOnFunction(Function &F) { } auto &&Context = F.getContext(); - if (Attrs.hasFnAttribute(FunctionMD::CMFloatControl)) { + if (VCINTR::AttributeList::hasFnAttr(Attrs, FunctionMD::CMFloatControl)) { auto FloatControl = unsigned(0); Attrs.getAttribute(AttributeList::FunctionIndex, FunctionMD::CMFloatControl) .getValueAsString() @@ -502,7 +503,7 @@ bool GenXSPIRVWriterAdaptorImpl::runOnFunction(Function &F) { if (!KernelMDs) return true; - if (Attrs.hasFnAttribute(FunctionMD::OCLRuntime)) { + if (VCINTR::AttributeList::hasFnAttr(Attrs, FunctionMD::OCLRuntime)) { auto SIMDSize = unsigned(0); Attrs.getAttribute(AttributeList::FunctionIndex, FunctionMD::OCLRuntime) .getValueAsString() From 2bbb573f4030c3006031a585b2ab2b027fe0a507 Mon Sep 17 00:00:00 2001 From: Bargatin-Intel Date: Wed, 18 Aug 2021 13:42:58 +0300 Subject: [PATCH 29/81] Add missing header --- GenXIntrinsics/include/llvmVCWrapper/IR/DerivedTypes.h | 1 + 1 file changed, 1 insertion(+) diff --git a/GenXIntrinsics/include/llvmVCWrapper/IR/DerivedTypes.h b/GenXIntrinsics/include/llvmVCWrapper/IR/DerivedTypes.h index cfaef3f4..da5f4d4a 100644 --- a/GenXIntrinsics/include/llvmVCWrapper/IR/DerivedTypes.h +++ b/GenXIntrinsics/include/llvmVCWrapper/IR/DerivedTypes.h @@ -10,6 +10,7 @@ SPDX-License-Identifier: MIT #define VCINTR_IR_DERIVEDYPES_H #include +#include namespace VCINTR { // TODO: move this to namespace VectorType and rename to "get" From 6221091b0a6b97c9bd9147d03ad09fbe74b8d89f Mon Sep 17 00:00:00 2001 From: Dmitry Bushev Date: Thu, 19 Aug 2021 16:42:01 +0300 Subject: [PATCH 30/81] Fix llvm verifier assertion SPIRVAdaptor passes didn't properly handle the pointer attributes when rewiting types in kernel signature leading to module verification failure --- .../lib/GenXIntrinsics/AdaptorsCommon.cpp | 64 +++++++++++++++++++ .../lib/GenXIntrinsics/AdaptorsCommon.h | 15 +++++ .../lib/GenXIntrinsics/CMakeLists.txt | 1 + .../GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp | 2 + .../GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp | 2 + .../args_attributes_transform_reader.ll | 28 ++++++++ .../args_attributes_transform_writer.ll | 28 ++++++++ 7 files changed, 140 insertions(+) create mode 100644 GenXIntrinsics/lib/GenXIntrinsics/AdaptorsCommon.cpp create mode 100644 GenXIntrinsics/test/Adaptors/args_attributes_transform_reader.ll create mode 100644 GenXIntrinsics/test/Adaptors/args_attributes_transform_writer.ll diff --git a/GenXIntrinsics/lib/GenXIntrinsics/AdaptorsCommon.cpp b/GenXIntrinsics/lib/GenXIntrinsics/AdaptorsCommon.cpp new file mode 100644 index 00000000..2fbac4e6 --- /dev/null +++ b/GenXIntrinsics/lib/GenXIntrinsics/AdaptorsCommon.cpp @@ -0,0 +1,64 @@ +/*========================== begin_copyright_notice ============================ + +Copyright (C) 2021 Intel Corporation + +SPDX-License-Identifier: MIT + +============================= end_copyright_notice ===========================*/ + +#include "AdaptorsCommon.h" + +#include "llvm/IR/Function.h" +#include "llvm/IR/Instructions.h" +#include "llvm/IR/Type.h" + +namespace llvm { +namespace genx { +#if VC_INTR_LLVM_VERSION_MAJOR >= 9 + +static void legalizeAttribute(Argument &Arg, Type *NewType, + Attribute::AttrKind Kind) { + + if (!Arg.hasAttribute(Kind) || + Arg.getAttribute(Kind).getValueAsType() == NewType) + return; + + Arg.removeAttr(Kind); + Arg.addAttr(Attribute::get(Arg.getParent()->getContext(), Kind, NewType)); +} + +#endif + +void legalizeParamAttributes(Function *F) { + assert(F && "Valid function ptr must be passed"); + +#if VC_INTR_LLVM_VERSION_MAJOR >= 9 + for (auto &Arg : F->args()) { + auto *PTy = dyn_cast(Arg.getType()); + if (!PTy) + continue; + +#if VC_INTR_LLVM_VERSION_MAJOR >= 13 + if (PTy->isOpaque()) + continue; +#endif // VC_INTR_LLVM_VERSION_MAJOR >= 13 + + auto *ElemType = PTy->getElementType(); + + legalizeAttribute(Arg, ElemType, Attribute::ByVal); + +#if VC_INTR_LLVM_VERSION_MAJOR >= 11 + legalizeAttribute(Arg, ElemType, Attribute::Preallocated); +#if VC_INTR_LLVM_VERSION_MAJOR >= 12 + legalizeAttribute(Arg, ElemType, Attribute::ByRef); +#if VC_INTR_LLVM_VERSION_MAJOR >= 13 + legalizeAttribute(Arg, ElemType, Attribute::InAlloca); + legalizeAttribute(Arg, ElemType, Attribute::ElementType); +#endif // VC_INTR_LLVM_VERSION_MAJOR >= 13 +#endif // VC_INTR_LLVM_VERSION_MAJOR >= 12 +#endif // VC_INTR_LLVM_VERSION_MAJOR >= 11 + } +#endif // VC_INTR_LLVM_VERSION_MAJOR >= 9 +} +} // namespace genx +} // namespace llvm diff --git a/GenXIntrinsics/lib/GenXIntrinsics/AdaptorsCommon.h b/GenXIntrinsics/lib/GenXIntrinsics/AdaptorsCommon.h index 5033e91b..052fa434 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/AdaptorsCommon.h +++ b/GenXIntrinsics/lib/GenXIntrinsics/AdaptorsCommon.h @@ -9,6 +9,9 @@ SPDX-License-Identifier: MIT // This file defines common constants for writer/reader spirv adaptors. namespace llvm { + +class Function; + namespace genx { enum class ArgKind { @@ -131,5 +134,17 @@ inline unsigned getOpaqueTypeAddressSpace(SPIRVType Ty) { } } +// Overrides specific attributes of function parameters. +// +// Function arguments of PointerType can have specific +// attributes like ByVal, ByRef, Preallocated, InAlloca +// that contain Pointee Type of that pointer as parameter. +// SPIRV Adaptor passes may change Pointee type, so we must +// explicitly change this type in corresponding attributes +// in order to construct valid llvm-IR. +// +// (see more here: https://llvm.org/docs/LangRef.html#parameter-attributes) +void legalizeParamAttributes(Function* F); + } // namespace genx } // namespace llvm diff --git a/GenXIntrinsics/lib/GenXIntrinsics/CMakeLists.txt b/GenXIntrinsics/lib/GenXIntrinsics/CMakeLists.txt index ea0c120d..f3ee8fcf 100755 --- a/GenXIntrinsics/lib/GenXIntrinsics/CMakeLists.txt +++ b/GenXIntrinsics/lib/GenXIntrinsics/CMakeLists.txt @@ -22,6 +22,7 @@ if(BUILD_EXTERNAL) GenXSPIRVReaderAdaptor.cpp GenXSPIRVWriterAdaptor.cpp GenXVersion.cpp + AdaptorsCommon.cpp ) llvm_update_compile_flags(LLVMGenXIntrinsics) add_dependencies(LLVMGenXIntrinsics GenXIntrinsicsGen) diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp index bc2e188e..1043c08c 100755 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp @@ -322,6 +322,8 @@ transformKernelSignature(Function &F, const std::vector &Descs) { NewF->addParamAttr(i, Attr); } + legalizeParamAttributes(NewF); + return NewF; } diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp index e6234b38..e38d6149 100755 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp @@ -198,6 +198,8 @@ transformKernelSignature(Function &F, const std::vector &Descs) { NewF->removeParamAttr(i, VCFunctionMD::VCArgumentDesc); } + legalizeParamAttributes(NewF); + return NewF; } diff --git a/GenXIntrinsics/test/Adaptors/args_attributes_transform_reader.ll b/GenXIntrinsics/test/Adaptors/args_attributes_transform_reader.ll new file mode 100644 index 00000000..16797d96 --- /dev/null +++ b/GenXIntrinsics/test/Adaptors/args_attributes_transform_reader.ll @@ -0,0 +1,28 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2021 Intel Corporation +; +; SPDX-License-Identifier: MIT +; +;============================ end_copyright_notice ============================= + +; Test that adaptor correctly handles parameter attributes with types. + +; UNSUPPORTED: llvm7, llvm8 +; XFAIL: llvm13, llvm14 +; RUN: opt -S -GenXSPIRVReaderAdaptor < %s | FileCheck %s +; CHECK: @test +; CHECK-SAME: %foo +; CHECK-SAME: byval(%foo) +; CHECK-SAME: arg + +%foo = type { i32 } + +define spir_kernel void @test(i8 addrspace(1)* byval(i8) "VCArgumentIOKind"="0" %arg) #0 { + %1 = call %foo addrspace(1)* @llvm.genx.address.convert.p1foo.p1i8(i8 addrspace(1)* %arg) + ret void +} + +declare %foo addrspace(1)* @llvm.genx.address.convert.p1foo.p1i8(i8 addrspace(1)*) + +attributes #0 = { "VCFunction" } diff --git a/GenXIntrinsics/test/Adaptors/args_attributes_transform_writer.ll b/GenXIntrinsics/test/Adaptors/args_attributes_transform_writer.ll new file mode 100644 index 00000000..63ca886b --- /dev/null +++ b/GenXIntrinsics/test/Adaptors/args_attributes_transform_writer.ll @@ -0,0 +1,28 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2021 Intel Corporation +; +; SPDX-License-Identifier: MIT +; +;============================ end_copyright_notice ============================= + +; Test that adaptor correctly handles parameter attributes with types. + +; UNSUPPORTED: llvm7, llvm8 +; RUN: opt -S -GenXSPIRVWriterAdaptor < %s | FileCheck %s +; CHECK: @test +; CHECK-SAME: i8 +; CHECK-SAME: byval(i8) +; CHECK-SAME: arg + +%foo = type { i32 } + +define spir_kernel void @test(%foo addrspace(1)* byval(%foo) %arg) { + ret void +} + +!genx.kernels = !{!0} +!0 = !{void (%foo addrspace(1)*)* @test, !"test", !1, i32 0, i32 0, !2, !3, i32 0} +!1 = !{i32 0} +!2 = !{i32 0} +!3 = !{!"svmptr_t"} From a2f2f10dc61c8161c57cf33ed606c8e3ccf3a921 Mon Sep 17 00:00:00 2001 From: DenisBakhvalov <61807338+DenisBakhvalov@users.noreply.github.com> Date: Thu, 19 Aug 2021 15:58:05 -0700 Subject: [PATCH 31/81] Fix Cmake Error When building DPCPP compiler I saw the following error: CMake Error at /llvm/cmake/modules/LLVMProcessSources.cmake:114 (message): Found unknown source file AdaptorsCommon.cpp --- GenXIntrinsics/lib/GenXIntrinsics/CMakeLists.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/GenXIntrinsics/lib/GenXIntrinsics/CMakeLists.txt b/GenXIntrinsics/lib/GenXIntrinsics/CMakeLists.txt index f3ee8fcf..facbe189 100755 --- a/GenXIntrinsics/lib/GenXIntrinsics/CMakeLists.txt +++ b/GenXIntrinsics/lib/GenXIntrinsics/CMakeLists.txt @@ -49,6 +49,7 @@ else() GenXSPIRVReaderAdaptor.cpp GenXSPIRVWriterAdaptor.cpp GenXVersion.cpp + AdaptorsCommon.cpp ADDITIONAL_HEADER_DIRS ${GENX_INTRINSICS_MAIN_INCLUDE_DIR}/llvm/GenXIntrinsics From 006d176f31b4ebf5e2c2ad8befb8d0227112bb0a Mon Sep 17 00:00:00 2001 From: Aleksander Us Date: Fri, 20 Aug 2021 13:12:43 +0000 Subject: [PATCH 32/81] Remove odd specifiers from functions in headers Remove static from inline functions in headers. Remove inline from in-class static function definitions. Replace static with inline for functions in wrapper headers. --- .../llvm/GenXIntrinsics/GenXIntrinsicInst.h | 4 +- .../llvm/GenXIntrinsics/GenXIntrinsics.h | 98 +++++++++---------- .../include/llvmVCWrapper/IR/DerivedTypes.h | 14 +-- .../include/llvmVCWrapper/IR/Instructions.h | 4 +- 4 files changed, 60 insertions(+), 60 deletions(-) diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsicInst.h b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsicInst.h index ded7dd10..fb37eddd 100755 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsicInst.h +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsicInst.h @@ -50,13 +50,13 @@ class GenXIntrinsicInst : public CallInst { } // Methods for support type inquiry through isa, cast, and dyn_cast: - static inline bool classof(const CallInst *I) { + static bool classof(const CallInst *I) { if (const Function *CF = I->getCalledFunction()) { return CF->getName().startswith(GenXIntrinsic::getGenXIntrinsicPrefix()); } return false; } - static inline bool classof(const Value *V) { + static bool classof(const Value *V) { return isa(V) && classof(cast(V)); } }; diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h index b0e69d08..50efc3d7 100755 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h @@ -67,13 +67,13 @@ enum { }; } // namespace GenXRegion -static inline const char *getGenXIntrinsicPrefix() { return "llvm.genx."; } +inline const char *getGenXIntrinsicPrefix() { return "llvm.genx."; } ID getGenXIntrinsicID(const Function *F); /// Utility function to get the genx_intrinsic ID if V is a GenXIntrinsic call. /// V is allowed to be 0. -static inline ID getGenXIntrinsicID(const Value *V) { +inline ID getGenXIntrinsicID(const Value *V) { if (V) if (const CallInst *CI = dyn_cast(V)) if (Function *Callee = CI->getCalledFunction()) @@ -84,7 +84,7 @@ static inline ID getGenXIntrinsicID(const Value *V) { /// GenXIntrinsic::isGenXIntrinsic(ID) - Is GenX intrinsic /// NOTE that this is include not_genx_intrinsic /// BUT DOES NOT include not_any_intrinsic -static inline bool isGenXIntrinsic(unsigned ID) { +inline bool isGenXIntrinsic(unsigned ID) { return ID >= not_genx_intrinsic && ID < num_genx_intrinsics; } @@ -92,7 +92,7 @@ static inline bool isGenXIntrinsic(unsigned ID) { /// the function's name starts with "llvm.genx.". /// It's possible for this function to return true while getGenXIntrinsicID() /// returns GenXIntrinsic::not_genx_intrinsic! -static inline bool isGenXIntrinsic(const Function *CF) { +inline bool isGenXIntrinsic(const Function *CF) { return CF->getName().startswith(getGenXIntrinsicPrefix()); } @@ -100,7 +100,7 @@ static inline bool isGenXIntrinsic(const Function *CF) { /// the function's name starts with "llvm.genx.". /// It's possible for this function to return true while getGenXIntrinsicID() /// returns GenXIntrinsic::not_genx_intrinsic! -static inline bool isGenXIntrinsic(const Value *V) { +inline bool isGenXIntrinsic(const Value *V) { if (V) if (const CallInst *CI = dyn_cast(V)) if (Function *Callee = CI->getCalledFunction()) @@ -110,19 +110,19 @@ static inline bool isGenXIntrinsic(const Value *V) { /// GenXIntrinsic::isGenXNonTrivialIntrinsic(ID) - Is GenX intrinsic, /// which is not equal to not_genx_intrinsic or not_any_intrinsic -static inline bool isGenXNonTrivialIntrinsic(unsigned ID) { +inline bool isGenXNonTrivialIntrinsic(unsigned ID) { return ID > not_genx_intrinsic && ID < num_genx_intrinsics; } /// GenXIntrinsic::isGenXNonTrivialIntrinsic(CF) - Returns true if /// CF is genx intrinsic, not equal to not_any_intrinsic or not_genx_intrinsic -static inline bool isGenXNonTrivialIntrinsic(const Function *CF) { +inline bool isGenXNonTrivialIntrinsic(const Function *CF) { return isGenXNonTrivialIntrinsic(getGenXIntrinsicID(CF)); } /// GenXIntrinsic::isGenXNonTrivialIntrinsic(V) - Returns true if /// V is genx intrinsic, not equal to not_any_intrinsic or not_genx_intrinsic -static inline bool isGenXNonTrivialIntrinsic(const Value *V) { +inline bool isGenXNonTrivialIntrinsic(const Value *V) { return isGenXNonTrivialIntrinsic(getGenXIntrinsicID(V)); } @@ -161,7 +161,7 @@ void resetGenXAttributes(Function* F); /// GenXIntrinsic::getAnyIntrinsicID(F) - Return LLVM or GenX intrinsic ID /// If is not intrinsic returns not_any_intrinsic /// Note that Function::getIntrinsicID returns ONLY LLVM intrinsics -static inline unsigned getAnyIntrinsicID(const Function *F) { +inline unsigned getAnyIntrinsicID(const Function *F) { if (isGenXNonTrivialIntrinsic(F)) return getGenXIntrinsicID(F); else { @@ -177,7 +177,7 @@ static inline unsigned getAnyIntrinsicID(const Function *F) { /// Utility function to get the LLVM or GenX intrinsic ID if V is an intrinsic /// call. /// V is allowed to be 0. -static inline unsigned getAnyIntrinsicID(const Value *V) { +inline unsigned getAnyIntrinsicID(const Value *V) { if (V) if (const CallInst *CI = dyn_cast(V)) if (Function *Callee = CI->getCalledFunction()) @@ -187,7 +187,7 @@ static inline unsigned getAnyIntrinsicID(const Value *V) { /// GenXIntrinsic::isAnyIntrinsic(ID) - Is any intrinsic /// including not_any_intrinsic -static inline bool isAnyIntrinsic(unsigned id) { +inline bool isAnyIntrinsic(unsigned id) { assert(id != not_genx_intrinsic && id != Intrinsic::not_intrinsic && "Do not use this method with getGenXIntrinsicID or getIntrinsicID!"); return id < num_genx_intrinsics || id == not_any_intrinsic; @@ -195,7 +195,7 @@ static inline bool isAnyIntrinsic(unsigned id) { /// GenXIntrinsic::isAnyNonTrivialIntrinsic(id) - Is GenX or LLVM intrinsic, /// which is not equal to not_any_intrinsic -static inline bool isAnyNonTrivialIntrinsic(unsigned id) { +inline bool isAnyNonTrivialIntrinsic(unsigned id) { assert(id != not_genx_intrinsic && id != Intrinsic::not_intrinsic && "Do not use this method with getGenXIntrinsicID or getIntrinsicID!"); return id < num_genx_intrinsics && @@ -204,14 +204,14 @@ static inline bool isAnyNonTrivialIntrinsic(unsigned id) { /// GenXIntrinsic::isAnyNonTrivialIntrinsic(ID) - Is GenX or LLVM intrinsic, /// which is not equal to not_genx_intrinsic, not_any_intrinsic or not_intrinsic -static inline bool isAnyNonTrivialIntrinsic(const Function *CF) { +inline bool isAnyNonTrivialIntrinsic(const Function *CF) { return isAnyNonTrivialIntrinsic(getAnyIntrinsicID(CF)); } /// Utility function to check if V is LLVM or GenX intrinsic call, /// which is not not_intrinsic, not_genx_intrinsic or not_any_intrinsic /// V is allowed to be 0. -static inline bool isAnyNonTrivialIntrinsic(const Value *V) { +inline bool isAnyNonTrivialIntrinsic(const Value *V) { return isAnyNonTrivialIntrinsic(getAnyIntrinsicID(V)); } @@ -220,8 +220,8 @@ static inline bool isAnyNonTrivialIntrinsic(const Value *V) { std::string getAnyName(unsigned id, ArrayRef Tys = None); /// GenXIntrinsic::getAnyType(ID) - Return the function type for an intrinsic. -static inline FunctionType *getAnyType(LLVMContext &Context, unsigned id, - ArrayRef Tys = None) { +inline FunctionType *getAnyType(LLVMContext &Context, unsigned id, + ArrayRef Tys = None) { assert(isAnyNonTrivialIntrinsic(id)); if (isGenXIntrinsic(id)) return getGenXType(Context, (ID)id, Tys); @@ -248,8 +248,8 @@ bool isOverloadedRet(unsigned IntrinID); /// using iAny, fAny, vAny, or iPTRAny). For a declaration of an overloaded /// intrinsic, Tys must provide exactly one type for each overloaded type in /// the intrinsic. -static inline Function *getAnyDeclaration(Module *M, unsigned id, - ArrayRef Tys = None) { +inline Function *getAnyDeclaration(Module *M, unsigned id, + ArrayRef Tys = None) { assert(isAnyNonTrivialIntrinsic(id)); if (isGenXIntrinsic(id)) { return getGenXDeclaration(M, (ID)id, Tys); @@ -261,13 +261,13 @@ static inline Function *getAnyDeclaration(Module *M, unsigned id, /// GenXIntrinsic::getGenXMulIID(S1, S2) - returns GenXIntrinsic::ID for /// the enx_XXmul opertation, where XX is is defined by the input arguments /// which represent signs of the operands -static inline GenXIntrinsic::ID getGenXMulIID(bool LHSign, bool RHSign) { +inline GenXIntrinsic::ID getGenXMulIID(bool LHSign, bool RHSign) { return LHSign ? (RHSign ? GenXIntrinsic::genx_ssmul : GenXIntrinsic::genx_sumul) : (RHSign ? GenXIntrinsic::genx_usmul : GenXIntrinsic::genx_uumul); } -static inline bool isRdRegion(unsigned IntrinID) { +inline bool isRdRegion(unsigned IntrinID) { switch (IntrinID) { case GenXIntrinsic::genx_rdregioni: case GenXIntrinsic::genx_rdregionf: @@ -277,15 +277,15 @@ static inline bool isRdRegion(unsigned IntrinID) { } } -static inline bool isRdRegion(const Function *F) { +inline bool isRdRegion(const Function *F) { return isRdRegion(getGenXIntrinsicID(F)); } -static inline bool isRdRegion(const Value *V) { +inline bool isRdRegion(const Value *V) { return isRdRegion(getGenXIntrinsicID(V)); } -static inline bool isWrRegion(unsigned IntrinID) { +inline bool isWrRegion(unsigned IntrinID) { switch (IntrinID) { case GenXIntrinsic::genx_wrregioni: case GenXIntrinsic::genx_wrregionf: @@ -296,29 +296,29 @@ static inline bool isWrRegion(unsigned IntrinID) { } } -static inline bool isWrRegion(const Function *F) { +inline bool isWrRegion(const Function *F) { return isWrRegion(getGenXIntrinsicID(F)); } -static inline bool isWrRegion(const Value *V) { +inline bool isWrRegion(const Value *V) { return isWrRegion(getGenXIntrinsicID(V)); } -static inline bool isAbs(unsigned IntrinID) { +inline bool isAbs(unsigned IntrinID) { if (IntrinID == GenXIntrinsic::genx_absf || IntrinID == GenXIntrinsic::genx_absi) return true; return false; } -static inline bool isAbs(const Function *F) { +inline bool isAbs(const Function *F) { return isAbs(getGenXIntrinsicID(F)); } -static inline bool isAbs(const Value *V) { +inline bool isAbs(const Value *V) { return isAbs(getGenXIntrinsicID(V)); } -static inline bool isIntegerSat(unsigned IID) { +inline bool isIntegerSat(unsigned IID) { switch (IID) { case GenXIntrinsic::genx_sstrunc_sat: case GenXIntrinsic::genx_sutrunc_sat: @@ -330,84 +330,84 @@ static inline bool isIntegerSat(unsigned IID) { } } -static inline bool isIntegerSat(const Function *F) { +inline bool isIntegerSat(const Function *F) { return isIntegerSat(getGenXIntrinsicID(F)); } -static inline bool isIntegerSat(const Value *V) { +inline bool isIntegerSat(const Value *V) { return isIntegerSat(getGenXIntrinsicID(V)); } -static inline bool isVLoad(unsigned IntrinID) { +inline bool isVLoad(unsigned IntrinID) { return IntrinID == GenXIntrinsic::genx_vload; } -static inline bool isVLoad(const Function *F) { +inline bool isVLoad(const Function *F) { return isVLoad(getGenXIntrinsicID(F)); } -static inline bool isVLoad(const Value *V) { +inline bool isVLoad(const Value *V) { return isVLoad(getGenXIntrinsicID(V)); } -static inline bool isVStore(unsigned IntrinID) { +inline bool isVStore(unsigned IntrinID) { return IntrinID == GenXIntrinsic::genx_vstore; } -static inline bool isVStore(const Function *F) { +inline bool isVStore(const Function *F) { return isVStore(getGenXIntrinsicID(F)); } -static inline bool isVStore(const Value *V) { +inline bool isVStore(const Value *V) { return isVStore(getGenXIntrinsicID(V)); } -static inline bool isVLoadStore(unsigned IntrinID) { +inline bool isVLoadStore(unsigned IntrinID) { return isVLoad(IntrinID) || isVStore(IntrinID); } -static inline bool isVLoadStore(const Function *F) { +inline bool isVLoadStore(const Function *F) { return isVLoadStore(getGenXIntrinsicID(F)); } -static inline bool isVLoadStore(const Value *V) { +inline bool isVLoadStore(const Value *V) { return isVLoadStore(getGenXIntrinsicID(V)); } -static inline bool isReadPredefReg(unsigned IntrinID) { +inline bool isReadPredefReg(unsigned IntrinID) { return IntrinID == GenXIntrinsic::genx_read_predef_reg; } -static inline bool isReadPredefReg(const Function *F) { +inline bool isReadPredefReg(const Function *F) { return isReadPredefReg(getGenXIntrinsicID(F)); } -static inline bool isReadPredefReg(const Value *V) { +inline bool isReadPredefReg(const Value *V) { return isReadPredefReg(getGenXIntrinsicID(V)); } -static inline bool isWritePredefReg(unsigned IntrinID) { +inline bool isWritePredefReg(unsigned IntrinID) { return IntrinID == GenXIntrinsic::genx_write_predef_reg; } -static inline bool isWritePredefReg(const Function *F) { +inline bool isWritePredefReg(const Function *F) { return isWritePredefReg(getGenXIntrinsicID(F)); } -static inline bool isWritePredefReg(const Value *V) { +inline bool isWritePredefReg(const Value *V) { return isWritePredefReg(getGenXIntrinsicID(V)); } -static inline bool isReadWritePredefReg(unsigned IntrinID) { +inline bool isReadWritePredefReg(unsigned IntrinID) { return isWritePredefReg(IntrinID) || isReadPredefReg(IntrinID); } -static inline bool isReadWritePredefReg(const Value *V) { +inline bool isReadWritePredefReg(const Value *V) { return isWritePredefReg(getGenXIntrinsicID(V)) || isReadPredefReg(getGenXIntrinsicID(V)); } -static inline bool isReadWritePredefReg(const Function *F) { +inline bool isReadWritePredefReg(const Function *F) { return isWritePredefReg(getGenXIntrinsicID(F)) || isReadPredefReg(getGenXIntrinsicID(F)); } diff --git a/GenXIntrinsics/include/llvmVCWrapper/IR/DerivedTypes.h b/GenXIntrinsics/include/llvmVCWrapper/IR/DerivedTypes.h index da5f4d4a..e0982450 100644 --- a/GenXIntrinsics/include/llvmVCWrapper/IR/DerivedTypes.h +++ b/GenXIntrinsics/include/llvmVCWrapper/IR/DerivedTypes.h @@ -15,14 +15,14 @@ SPDX-License-Identifier: MIT namespace VCINTR { // TODO: move this to namespace VectorType and rename to "get" #if VC_INTR_LLVM_VERSION_MAJOR >= 9 - static inline llvm::VectorType *getVectorType(llvm::Type *ElementType, - llvm::ElementCount EC) { + inline llvm::VectorType *getVectorType(llvm::Type *ElementType, + llvm::ElementCount EC) { return llvm::VectorType::get(ElementType, EC); } #endif - static inline llvm::VectorType *getVectorType(llvm::Type *ElementType, - unsigned NumElements) { + inline llvm::VectorType *getVectorType(llvm::Type *ElementType, + unsigned NumElements) { #if VC_INTR_LLVM_VERSION_MAJOR >= 11 return llvm::VectorType::get(ElementType, NumElements, false /*Scalable*/); #else @@ -30,8 +30,8 @@ namespace VCINTR { #endif } - static inline llvm::StructType *getTypeByName(llvm::Module *M, - llvm::StringRef Name) { + inline llvm::StructType *getTypeByName(llvm::Module *M, + llvm::StringRef Name) { #if VC_INTR_LLVM_VERSION_MAJOR >= 12 return llvm::StructType::getTypeByName(M->getContext(), Name); #else @@ -41,7 +41,7 @@ namespace VCINTR { namespace VectorType { -static unsigned getNumElements(llvm::VectorType *VecType) { +inline unsigned getNumElements(llvm::VectorType *VecType) { using namespace llvm; #if VC_INTR_LLVM_VERSION_MAJOR <= 10 return VecType->getNumElements(); diff --git a/GenXIntrinsics/include/llvmVCWrapper/IR/Instructions.h b/GenXIntrinsics/include/llvmVCWrapper/IR/Instructions.h index 2649f6f6..c4871e30 100755 --- a/GenXIntrinsics/include/llvmVCWrapper/IR/Instructions.h +++ b/GenXIntrinsics/include/llvmVCWrapper/IR/Instructions.h @@ -19,7 +19,7 @@ auto static constexpr UndefMaskElem = -1; // LLVM <= 10 does not have ShuffleVectorInst ctor which accepts ArrayRef // This method returns mask with appropriate type for ShuffleVectorInst ctor #if VC_INTR_LLVM_VERSION_MAJOR <= 10 -static llvm::Constant *getShuffleMask(llvm::ArrayRef Mask, +inline llvm::Constant *getShuffleMask(llvm::ArrayRef Mask, llvm::LLVMContext &Context) { using namespace llvm; auto Indices = SmallVector{}; @@ -34,7 +34,7 @@ static llvm::Constant *getShuffleMask(llvm::ArrayRef Mask, return ConstantVector::get(Indices); } #else -static llvm::ArrayRef getShuffleMask(llvm::ArrayRef Mask, +inline llvm::ArrayRef getShuffleMask(llvm::ArrayRef Mask, llvm::LLVMContext &Context) { return Mask; } From b66c5bbd66dc4a556fc624122d835552b3516f14 Mon Sep 17 00:00:00 2001 From: Kirill Yansitov Date: Tue, 31 Aug 2021 16:22:22 +0000 Subject: [PATCH 33/81] Add intrinsics to represent cm_imul builtin This intrinsic doesn't produce vISA instr and must be lower in backend Small fixes in madw description to allow only width equal 2GRF/sizeof(i32) --- .../GenXIntrinsics/Intrinsic_definitions.py | 79 ++++++++++++------- 1 file changed, 50 insertions(+), 29 deletions(-) diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py index c9dd1a54..5fbf7a50 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py @@ -1096,35 +1096,6 @@ "attributes" : "NoMem" }, -### ``llvm.genx.*madw..`` : madw instruction, no saturation -### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -### * ``llvm.genx.smadw`` : result signed -### * ``llvm.genx.umadw`` : result unsigned -### -### result := arg0 * arg1 + arg2 -### -### * Return value: result, the full 64-bit of the results of multiplying two 32-bit -### integers and adding 32-bit integer(32b*32b+32b->64b). -### The low 32b of results are stored in the lower GRF and -### the high 32b of results are stored in the high GRF. -### -### Return width of intrinsic depends on args width: -### if args width <= GRF/sizeof(i32) then return width = 2*GRF/sizeof(i32) -### else return width = 2 * args width -### -### * arg0: first input, same element type as result -### * arg1: second input, same type as arg0 -### * arg2: third input, same type as arg0 -### - "umadw" : { "result" : "anyint", - "arguments" : ["anyint", 1, 1], - "attributes" : "NoMem" - }, - "smadw" : { "result" : "anyint", - "arguments" : ["anyint", 1, 1], - "attributes" : "NoMem" - }, - ### ``llvm.genx.*max..`` : max instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ### * ``llvm.genx.smax`` : result and operands signed @@ -1191,6 +1162,28 @@ ### cover vISA functionality ### +### imad +### ^^^^ +### +### ``llvm.genx.*imad.<{hi, lo}>.`` : imad instruction +### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +### * ``llvm.genx.simad`` : result and operands signed +### * ``llvm.genx.uimad`` : result and operands unsigned +### +### result := {hi, lo} = arg0 * arg1 +### +### * arg0: first input, i32 scalar/vector integer type +### * arg1: second input, same type as arg0 +### + "simad" : { "result" : ["anyint", "anyint"], + "arguments" : [0, 0], + "attributes" : "NoMem" + }, + "uimad" : { "result" : ["anyint", "anyint"], + "arguments" : [0, 0], + "attributes" : "NoMem" + }, + ### mul ### ^^^ ### Still need non-saaturating mul intrinsic as def-hoist/copy-prop in jitter @@ -4933,4 +4926,32 @@ "attributes" : "None", }, + +## ``llvm.genx.*madw..`` : madw instruction, no saturation +## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +## * ``llvm.genx.smadw`` : result signed +## * ``llvm.genx.umadw`` : result unsigned +## +## result := arg0 * arg1 + arg2 +## +## * Return value: result, the full 64-bit of the results of multiplying two 32-bit +## integers and adding 32-bit integer(32b*32b+32b->64b). +## The low 32b of results are stored in the lower GRF and +## the high 32b of results are stored in the high GRF. +## +## Return width must be 2*GRF/sizeof(i32) +## Args width must be no more than GRF/sizeof(i32) and must be a power of two +## +## * arg0: first input, same element type as result +## * arg1: second input, same type as arg0 +## * arg2: third input, same type as arg0 +## + "umadw" : { "result" : "anyint", + "arguments" : ["anyint", 1, 1], + "attributes" : "NoMem" + }, + "smadw" : { "result" : "anyint", + "arguments" : ["anyint", 1, 1], + "attributes" : "NoMem" + }, } From b1db3e55bac23670be4ffbd0da85a9fd0110f593 Mon Sep 17 00:00:00 2001 From: Aleksander Us Date: Fri, 3 Sep 2021 10:36:49 +0000 Subject: [PATCH 34/81] Wrap attribute at index methods Fix after https://reviews.llvm.org/D108614. --- .../include/llvmVCWrapper/IR/Attributes.h | 39 ++++++++++++++++++ .../include/llvmVCWrapper/IR/Function.h | 27 +++++++++++++ .../GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp | 40 +++++++++++-------- .../GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp | 24 ++++++----- .../GenXSingleElementVectorUtil.cpp | 15 ++++--- 5 files changed, 113 insertions(+), 32 deletions(-) diff --git a/GenXIntrinsics/include/llvmVCWrapper/IR/Attributes.h b/GenXIntrinsics/include/llvmVCWrapper/IR/Attributes.h index eeae92fe..8af2ef73 100644 --- a/GenXIntrinsics/include/llvmVCWrapper/IR/Attributes.h +++ b/GenXIntrinsics/include/llvmVCWrapper/IR/Attributes.h @@ -33,6 +33,45 @@ inline bool hasFnAttr(const llvm::AttributeList &AttrList, #endif } +inline bool hasAttributeAtIndex(const llvm::AttributeList &AttrList, + unsigned Index, + llvm::Attribute::AttrKind Kind) { +#if VC_INTR_LLVM_VERSION_MAJOR >= 14 + return AttrList.hasAttributeAtIndex(Index, Kind); +#else + return AttrList.hasAttribute(Index, Kind); +#endif +} + +inline bool hasAttributeAtIndex(const llvm::AttributeList &AttrList, + unsigned Index, llvm::StringRef Kind) { +#if VC_INTR_LLVM_VERSION_MAJOR >= 14 + return AttrList.hasAttributeAtIndex(Index, Kind); +#else + return AttrList.hasAttribute(Index, Kind); +#endif +} + +inline llvm::Attribute getAttributeAtIndex(const llvm::AttributeList &AttrList, + unsigned Index, + llvm::Attribute::AttrKind Kind) { +#if VC_INTR_LLVM_VERSION_MAJOR >= 14 + return AttrList.getAttributeAtIndex(Index, Kind); +#else + return AttrList.getAttribute(Index, Kind); +#endif +} + +inline llvm::Attribute getAttributeAtIndex(const llvm::AttributeList &AttrList, + unsigned Index, + llvm::StringRef Kind) { +#if VC_INTR_LLVM_VERSION_MAJOR >= 14 + return AttrList.getAttributeAtIndex(Index, Kind); +#else + return AttrList.getAttribute(Index, Kind); +#endif +} + } // namespace AttributeList } // namespace VCINTR diff --git a/GenXIntrinsics/include/llvmVCWrapper/IR/Function.h b/GenXIntrinsics/include/llvmVCWrapper/IR/Function.h index 2898d4f8..1120d2a2 100644 --- a/GenXIntrinsics/include/llvmVCWrapper/IR/Function.h +++ b/GenXIntrinsics/include/llvmVCWrapper/IR/Function.h @@ -28,6 +28,33 @@ inline llvm::Function *Create(llvm::FunctionType *FTy, #endif } +inline void addAttributeAtIndex(llvm::Function &F, unsigned Index, + llvm::Attribute Attr) { +#if VC_INTR_LLVM_VERSION_MAJOR >= 14 + F.addAttributeAtIndex(Index, Attr); +#else + F.addAttribute(Index, Attr); +#endif +} + +inline void removeAttributeAtIndex(llvm::Function &F, unsigned Index, + llvm::Attribute::AttrKind Kind) { +#if VC_INTR_LLVM_VERSION_MAJOR >= 14 + F.removeAttributeAtIndex(Index, Kind); +#else + F.removeAttribute(Index, Kind); +#endif +} + +inline void removeAttributeAtIndex(llvm::Function &F, unsigned Index, + llvm::StringRef Kind) { +#if VC_INTR_LLVM_VERSION_MAJOR >= 14 + F.removeAttributeAtIndex(Index, Kind); +#else + F.removeAttribute(Index, Kind); +#endif +} + } // namespace Function } // namespace VCINTR diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp index 1043c08c..312ded63 100755 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp @@ -433,25 +433,25 @@ bool GenXSPIRVReaderAdaptor::runOnFunction(Function &F) { if (VCINTR::AttributeList::hasFnAttr(Attrs, VCFunctionMD::VCSIMTCall)) { auto SIMTMode = StringRef(); - SIMTMode = Attrs - .getAttribute(AttributeList::FunctionIndex, - VCFunctionMD::VCSIMTCall) - .getValueAsString(); + SIMTMode = + VCINTR::AttributeList::getAttributeAtIndex( + Attrs, AttributeList::FunctionIndex, VCFunctionMD::VCSIMTCall) + .getValueAsString(); F.addFnAttr(FunctionMD::CMGenxSIMT, SIMTMode); } auto &&Context = F.getContext(); if (VCINTR::AttributeList::hasFnAttr(Attrs, VCFunctionMD::VCFloatControl)) { auto FloatControl = unsigned(0); - Attrs - .getAttribute(AttributeList::FunctionIndex, - VCFunctionMD::VCFloatControl) + VCINTR::AttributeList::getAttributeAtIndex( + Attrs, AttributeList::FunctionIndex, VCFunctionMD::VCFloatControl) .getValueAsString() .getAsInteger(0, FloatControl); auto Attr = Attribute::get(Context, FunctionMD::CMFloatControl, std::to_string(FloatControl)); - F.addAttribute(AttributeList::FunctionIndex, Attr); + VCINTR::Function::addAttributeAtIndex(F, AttributeList::FunctionIndex, + Attr); } if (auto *ReqdSubgroupSize = @@ -461,7 +461,8 @@ bool GenXSPIRVReaderAdaptor::runOnFunction(Function &F) { ->getZExtValue(); Attribute Attr = Attribute::get(Context, FunctionMD::OCLRuntime, std::to_string(SIMDSize)); - F.addAttribute(AttributeList::FunctionIndex, Attr); + VCINTR::Function::addAttributeAtIndex(F, AttributeList::FunctionIndex, + Attr); } if (!(F.getCallingConv() == CallingConv::SPIR_KERNEL)) @@ -480,7 +481,8 @@ bool GenXSPIRVReaderAdaptor::runOnFunction(Function &F) { llvm::Type *I32Ty = llvm::Type::getInt32Ty(Context); if (VCINTR::AttributeList::hasFnAttr(Attrs, VCFunctionMD::VCSLMSize)) { - Attrs.getAttribute(AttributeList::FunctionIndex, VCFunctionMD::VCSLMSize) + VCINTR::AttributeList::getAttributeAtIndex( + Attrs, AttributeList::FunctionIndex, VCFunctionMD::VCSLMSize) .getValueAsString() .getAsInteger(0, SLMSize); } @@ -490,18 +492,24 @@ bool GenXSPIRVReaderAdaptor::runOnFunction(Function &F) { auto ArgKind = unsigned(0); auto ArgIOKind = unsigned(0); auto ArgDesc = std::string(); - if (Attrs.hasAttribute(ArgNo + 1, VCFunctionMD::VCArgumentKind)) { - Attrs.getAttribute(ArgNo + 1, VCFunctionMD::VCArgumentKind) + if (VCINTR::AttributeList::hasAttributeAtIndex( + Attrs, ArgNo + 1, VCFunctionMD::VCArgumentKind)) { + VCINTR::AttributeList::getAttributeAtIndex(Attrs, ArgNo + 1, + VCFunctionMD::VCArgumentKind) .getValueAsString() .getAsInteger(0, ArgKind); } - if (Attrs.hasAttribute(ArgNo + 1, VCFunctionMD::VCArgumentIOKind)) { - Attrs.getAttribute(ArgNo + 1, VCFunctionMD::VCArgumentIOKind) + if (VCINTR::AttributeList::hasAttributeAtIndex( + Attrs, ArgNo + 1, VCFunctionMD::VCArgumentIOKind)) { + VCINTR::AttributeList::getAttributeAtIndex(Attrs, ArgNo + 1, + VCFunctionMD::VCArgumentIOKind) .getValueAsString() .getAsInteger(0, ArgIOKind); } - if (Attrs.hasAttribute(ArgNo + 1, VCFunctionMD::VCArgumentDesc)) { - ArgDesc = Attrs.getAttribute(ArgNo + 1, VCFunctionMD::VCArgumentDesc) + if (VCINTR::AttributeList::hasAttributeAtIndex( + Attrs, ArgNo + 1, VCFunctionMD::VCArgumentDesc)) { + ArgDesc = VCINTR::AttributeList::getAttributeAtIndex( + Attrs, ArgNo + 1, VCFunctionMD::VCArgumentDesc) .getValueAsString() .str(); } diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp index e38d6149..8ab2877c 100755 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp @@ -483,22 +483,24 @@ bool GenXSPIRVWriterAdaptorImpl::runOnFunction(Function &F) { if (VCINTR::AttributeList::hasFnAttr(Attrs, FunctionMD::CMGenxSIMT)) { auto SIMTMode = StringRef(); - SIMTMode = - Attrs.getAttribute(AttributeList::FunctionIndex, FunctionMD::CMGenxSIMT) - .getValueAsString(); + SIMTMode = VCINTR::AttributeList::getAttributeAtIndex( + Attrs, AttributeList::FunctionIndex, FunctionMD::CMGenxSIMT) + .getValueAsString(); F.addFnAttr(VCFunctionMD::VCSIMTCall, SIMTMode); } auto &&Context = F.getContext(); if (VCINTR::AttributeList::hasFnAttr(Attrs, FunctionMD::CMFloatControl)) { auto FloatControl = unsigned(0); - Attrs.getAttribute(AttributeList::FunctionIndex, FunctionMD::CMFloatControl) + VCINTR::AttributeList::getAttributeAtIndex( + Attrs, AttributeList::FunctionIndex, FunctionMD::CMFloatControl) .getValueAsString() .getAsInteger(0, FloatControl); auto Attr = Attribute::get(Context, VCFunctionMD::VCFloatControl, std::to_string(FloatControl)); - F.addAttribute(AttributeList::FunctionIndex, Attr); + VCINTR::Function::addAttributeAtIndex(F, AttributeList::FunctionIndex, + Attr); } auto *KernelMDs = F.getParent()->getNamedMetadata(FunctionMD::GenXKernels); @@ -507,7 +509,8 @@ bool GenXSPIRVWriterAdaptorImpl::runOnFunction(Function &F) { if (VCINTR::AttributeList::hasFnAttr(Attrs, FunctionMD::OCLRuntime)) { auto SIMDSize = unsigned(0); - Attrs.getAttribute(AttributeList::FunctionIndex, FunctionMD::OCLRuntime) + VCINTR::AttributeList::getAttributeAtIndex( + Attrs, AttributeList::FunctionIndex, FunctionMD::OCLRuntime) .getValueAsString() .getAsInteger(0, SIMDSize); auto SizeMD = ConstantAsMetadata::get( @@ -537,7 +540,7 @@ bool GenXSPIRVWriterAdaptorImpl::runOnFunction(Function &F) { auto ArgKind = V->getZExtValue(); auto Attr = Attribute::get(Context, VCFunctionMD::VCArgumentKind, std::to_string(ArgKind)); - F.addAttribute(ArgNo + 1, Attr); + VCINTR::Function::addAttributeAtIndex(F, ArgNo + 1, Attr); } } } @@ -550,7 +553,8 @@ bool GenXSPIRVWriterAdaptorImpl::runOnFunction(Function &F) { auto SLMSize = V->getZExtValue(); auto Attr = Attribute::get(Context, VCFunctionMD::VCSLMSize, std::to_string(SLMSize)); - F.addAttribute(AttributeList::FunctionIndex, Attr); + VCINTR::Function::addAttributeAtIndex(F, AttributeList::FunctionIndex, + Attr); } } @@ -564,7 +568,7 @@ bool GenXSPIRVWriterAdaptorImpl::runOnFunction(Function &F) { auto ArgKind = V->getZExtValue(); auto Attr = Attribute::get(Context, VCFunctionMD::VCArgumentIOKind, std::to_string(ArgKind)); - F.addAttribute(ArgNo + 1, Attr); + VCINTR::Function::addAttributeAtIndex(F, ArgNo + 1, Attr); } } } @@ -579,7 +583,7 @@ bool GenXSPIRVWriterAdaptorImpl::runOnFunction(Function &F) { auto &&Desc = MS->getString(); auto Attr = Attribute::get(Context, VCFunctionMD::VCArgumentDesc, Desc); - F.addAttribute(ArgNo + 1, Attr); + VCINTR::Function::addAttributeAtIndex(F, ArgNo + 1, Attr); } } } diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp index 1f664dd9..19c61383 100755 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp @@ -22,6 +22,7 @@ SPDX-License-Identifier: MIT #include "llvm/IR/Module.h" #include "llvm/Pass.h" +#include "llvmVCWrapper/IR/Attributes.h" #include "llvmVCWrapper/IR/DerivedTypes.h" #include "llvmVCWrapper/IR/Function.h" #include "llvmVCWrapper/IR/GlobalValue.h" @@ -460,10 +461,11 @@ static void manageSingleElementVectorAttribute(Function &NewF, Type *OldT, auto InnerPtrs = std::to_string(getInnerPointerVectorNesting(OldT)); auto Attr = Attribute::get(NewF.getContext(), VCModuleMD::VCSingleElementVector, InnerPtrs); - NewF.addAttribute(AttrNo, Attr); + VCINTR::Function::addAttributeAtIndex(NewF, AttrNo, Attr); } else if (hasSingleElementVector(NewT)) { assert(!hasSingleElementVector(OldT)); - NewF.removeAttribute(AttrNo, VCModuleMD::VCSingleElementVector); + VCINTR::Function::removeAttributeAtIndex(NewF, AttrNo, + VCModuleMD::VCSingleElementVector); } } @@ -492,11 +494,12 @@ static Type *getOriginalType(Function &F, size_t AttrNo) { auto *T = AttrNo == 0 ? FuncT->getReturnType() : FuncT->getParamType(AttrNo - 1); auto Attrs = F.getAttributes(); - if (!Attrs.hasAttribute(AttrNo, VCModuleMD::VCSingleElementVector)) + if (!VCINTR::AttributeList::hasAttributeAtIndex( + Attrs, AttrNo, VCModuleMD::VCSingleElementVector)) return T; - auto InnerPtrsStr = - Attrs.getAttribute(AttrNo, VCModuleMD::VCSingleElementVector) - .getValueAsString(); + auto InnerPtrsStr = VCINTR::AttributeList::getAttributeAtIndex( + Attrs, AttrNo, VCModuleMD::VCSingleElementVector) + .getValueAsString(); auto InnerPtrs = InnerPtrsStr.empty() ? 0 : std::stoull(InnerPtrsStr.str()); return getTypeWithSingleElementVector(T, InnerPtrs); } From e5ad7e02aa4aa21a3cd7b3e5d1f3ec9b95f58872 Mon Sep 17 00:00:00 2001 From: Aleksander Us Date: Tue, 7 Sep 2021 12:30:52 +0000 Subject: [PATCH 35/81] Add image array conversion in spirv adaptors --- .../lib/GenXIntrinsics/AdaptorsCommon.h | 8 ++++ .../GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp | 14 ++++++ .../GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp | 10 +++++ .../test/Adaptors/image_array_reader.ll | 43 +++++++++++++++++++ .../test/Adaptors/image_array_writer.ll | 36 ++++++++++++++++ 5 files changed, 111 insertions(+) create mode 100644 GenXIntrinsics/test/Adaptors/image_array_reader.ll create mode 100644 GenXIntrinsics/test/Adaptors/image_array_writer.ll diff --git a/GenXIntrinsics/lib/GenXIntrinsics/AdaptorsCommon.h b/GenXIntrinsics/lib/GenXIntrinsics/AdaptorsCommon.h index 052fa434..f864086e 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/AdaptorsCommon.h +++ b/GenXIntrinsics/lib/GenXIntrinsics/AdaptorsCommon.h @@ -29,8 +29,10 @@ static constexpr const char Buffer[] = "buffer_t"; static constexpr const char SVM[] = "svmptr_t"; static constexpr const char Sampler[] = "sampler_t"; static constexpr const char Image1d[] = "image1d_t"; +static constexpr const char Image1dArray[] = "image1d_array_t"; static constexpr const char Image1dBuffer[] = "image1d_buffer_t"; static constexpr const char Image2d[] = "image2d_t"; +static constexpr const char Image2dArray[] = "image2d_array_t"; static constexpr const char Image3d[] = "image3d_t"; } // namespace ArgDesc @@ -41,8 +43,10 @@ enum class SPIRVType { // Surfaces + corresponding desc. Buffer, Image1d, + Image1dArray, Image1dBuffer, Image2d, + Image2dArray, Image3d, // Sampler + sampler_t. Sampler, @@ -77,8 +81,10 @@ static constexpr const char TypePrefix[] = "opencl."; // Currently used image types. static constexpr const char Image[] = "image"; static constexpr const char Dim1d[] = "1d"; +static constexpr const char Dim1dArray[] = "1d_array"; static constexpr const char Dim1dBuffer[] = "1d_buffer"; static constexpr const char Dim2d[] = "2d"; +static constexpr const char Dim2dArray[] = "2d_array"; static constexpr const char Dim3d[] = "3d"; // Sampler type. static constexpr const char Sampler[] = "sampler"; @@ -124,8 +130,10 @@ inline unsigned getOpaqueTypeAddressSpace(SPIRVType Ty) { return SPIRVParams::SPIRVConstantAS; case SPIRVType::Buffer: case SPIRVType::Image1d: + case SPIRVType::Image1dArray: case SPIRVType::Image1dBuffer: case SPIRVType::Image2d: + case SPIRVType::Image2dArray: case SPIRVType::Image3d: return SPIRVParams::SPIRVGlobalAS; default: diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp index 312ded63..cc47e72c 100755 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp @@ -67,9 +67,15 @@ static std::pair parseImageDim(StringRef TyName) { if (TyName.consume_front(OCLTypes::Dim1dBuffer)) return {SPIRVType::Image1dBuffer, TyName}; + if (TyName.consume_front(OCLTypes::Dim1dArray)) + return {SPIRVType::Image1dArray, TyName}; + if (TyName.consume_front(OCLTypes::Dim1d)) return {SPIRVType::Image1d, TyName}; + if (TyName.consume_front(OCLTypes::Dim2dArray)) + return {SPIRVType::Image2dArray, TyName}; + if (TyName.consume_front(OCLTypes::Dim2d)) return {SPIRVType::Image2d, TyName}; @@ -221,8 +227,10 @@ static ArgKind mapSPIRVTypeToArgKind(SPIRVType Ty) { switch (Ty) { case SPIRVType::Buffer: case SPIRVType::Image1d: + case SPIRVType::Image1dArray: case SPIRVType::Image1dBuffer: case SPIRVType::Image2d: + case SPIRVType::Image2dArray: case SPIRVType::Image3d: return ArgKind::Surface; case SPIRVType::Sampler: @@ -245,12 +253,18 @@ static std::string mapSPIRVDescToArgDesc(SPIRVArgDesc SPIRVDesc) { case SPIRVType::Image1d: Desc += ArgDesc::Image1d; break; + case SPIRVType::Image1dArray: + Desc += ArgDesc::Image1dArray; + break; case SPIRVType::Image1dBuffer: Desc += ArgDesc::Image1dBuffer; break; case SPIRVType::Image2d: Desc += ArgDesc::Image2d; break; + case SPIRVType::Image2dArray: + Desc += ArgDesc::Image2dArray; + break; case SPIRVType::Image3d: Desc += ArgDesc::Image3d; break; diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp index 8ab2877c..3ddc39ad 100755 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp @@ -113,12 +113,18 @@ static Type *getImageType(SPIRVArgDesc Desc, Module *M) { case SPIRVType::Image1d: Name += OCLTypes::Dim1d; break; + case SPIRVType::Image1dArray: + Name += OCLTypes::Dim1dArray; + break; case SPIRVType::Image1dBuffer: Name += OCLTypes::Dim1dBuffer; break; case SPIRVType::Image2d: Name += OCLTypes::Dim2d; break; + case SPIRVType::Image2dArray: + Name += OCLTypes::Dim2dArray; + break; case SPIRVType::Image3d: Name += OCLTypes::Dim3d; break; @@ -240,8 +246,10 @@ static SPIRVArgDesc parseArgDesc(StringRef Desc) { Ty = StringSwitch>(Tok) .Case(ArgDesc::Buffer, SPIRVType::Buffer) .Case(ArgDesc::Image1d, SPIRVType::Image1d) + .Case(ArgDesc::Image1dArray, SPIRVType::Image1dArray) .Case(ArgDesc::Image1dBuffer, SPIRVType::Image1dBuffer) .Case(ArgDesc::Image2d, SPIRVType::Image2d) + .Case(ArgDesc::Image2dArray, SPIRVType::Image2dArray) .Case(ArgDesc::Image3d, SPIRVType::Image3d) .Case(ArgDesc::SVM, SPIRVType::Pointer) .Case(ArgDesc::Sampler, SPIRVType::Sampler) @@ -290,8 +298,10 @@ static SPIRVArgDesc analyzeSurfaceArg(StringRef Desc) { switch (SPVDesc.Ty) { case SPIRVType::Buffer: case SPIRVType::Image1d: + case SPIRVType::Image1dArray: case SPIRVType::Image1dBuffer: case SPIRVType::Image2d: + case SPIRVType::Image2dArray: case SPIRVType::Image3d: return SPVDesc; // CMRT does not require to annotate arguments. diff --git a/GenXIntrinsics/test/Adaptors/image_array_reader.ll b/GenXIntrinsics/test/Adaptors/image_array_reader.ll new file mode 100644 index 00000000..d49e6036 --- /dev/null +++ b/GenXIntrinsics/test/Adaptors/image_array_reader.ll @@ -0,0 +1,43 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2021 Intel Corporation +; +; SPDX-License-Identifier: MIT +; +;============================ end_copyright_notice ============================= + +; XFAIL: llvm13,llvm14 +; Test reader translation of image array arguments. + +; RUN: opt -S -GenXSPIRVReaderAdaptor < %s | FileCheck %s + +%opencl.image1d_array_ro_t = type opaque +%opencl.image2d_array_wo_t = type opaque + +define spir_kernel void @test(%opencl.image1d_array_ro_t addrspace(1)* %im1d, %opencl.image2d_array_wo_t addrspace(1)* %im2d) #0 { +; CHECK-LABEL: @test( + +; CHECK: i32 +; CHECK: [[IM1D:%[^,]+]], + +; CHECK: i32 +; CHECK: [[IM2D:%[^,]+]]) + +; CHECK-NEXT: entry: +; CHECK-NEXT: ret void +; +entry: + %0 = call i32 @llvm.genx.address.convert.i32.p1opencl.image1d_array_ro_t(%opencl.image1d_array_ro_t addrspace(1)* %im1d) + %1 = call i32 @llvm.genx.address.convert.i32.p1opencl.image2d_array_wo_t(%opencl.image2d_array_wo_t addrspace(1)* %im2d) + ret void +} + +declare i32 @llvm.genx.address.convert.i32.p1opencl.image1d_array_ro_t(%opencl.image1d_array_ro_t addrspace(1)*) +declare i32 @llvm.genx.address.convert.i32.p1opencl.image2d_array_wo_t(%opencl.image2d_array_wo_t addrspace(1)*) + +attributes #0 = { "VCFunction" } + +; CHECK: !genx.kernels = !{[[KERNEL:![0-9]+]]} +; CHECK: [[KERNEL]] = !{void (i32, i32)* @test, !"test", [[KINDS:![0-9]+]], i32 0, i32 0, !{{[0-9]+}}, [[DESCS:![0-9]+]], i32 0} +; CHECK-DAG: [[KINDS]] = !{i32 2, i32 2} +; CHECK-DAG: [[DESCS]] = !{!"image1d_array_t read_only", !"image2d_array_t write_only"} diff --git a/GenXIntrinsics/test/Adaptors/image_array_writer.ll b/GenXIntrinsics/test/Adaptors/image_array_writer.ll new file mode 100644 index 00000000..79f16761 --- /dev/null +++ b/GenXIntrinsics/test/Adaptors/image_array_writer.ll @@ -0,0 +1,36 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2021 Intel Corporation +; +; SPDX-License-Identifier: MIT +; +;============================ end_copyright_notice ============================= + +; Test writer translation of image array arguments. + +; RUN: opt -S -GenXSPIRVWriterAdaptor < %s | FileCheck %s + +define void @test(i32 %im1darr, i32 %im2darr) { +; CHECK-LABEL: @test( + +; CHECK: %opencl.image1d_array_ro_t addrspace(1)* +; CHECK: [[IM1D:%[^,]+]], + +; CHECK: %opencl.image2d_array_wo_t addrspace(1)* +; CHECK: [[IM2D:%[^)]+]]) + +; CHECK-NEXT: entry: +; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.genx.address.convert.i32.p1opencl.image1d_array_ro_t(%opencl.image1d_array_ro_t addrspace(1)* [[IM1D]]) +; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.genx.address.convert.i32.p1opencl.image2d_array_wo_t(%opencl.image2d_array_wo_t addrspace(1)* [[IM2D]]) +; CHECK-NEXT: ret void +; +entry: + ret void +} + +!genx.kernels = !{!0} + +!0 = !{void (i32, i32)* @test, !"test", !1, i32 0, i32 0, !2, !3, i32 0, i32 0} +!1 = !{i32 2, i32 2} +!2 = !{i32 0, i32 0} +!3 = !{!"image1d_array_t read_only", !"image2d_array_t write_only"} From 4e2a1cebbf5c47563d92785d04d8e0c614857a93 Mon Sep 17 00:00:00 2001 From: Anatoly Parshintsev Date: Wed, 8 Sep 2021 23:02:41 +0000 Subject: [PATCH 36/81] synchornize platform list --- GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py index 29e1592f..327e97ce 100755 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py @@ -76,9 +76,10 @@ "SideEffects": set(["NoUnwind"]), } -# order does really matter -platform_list = ["HSW", "BDW", "CHV", "SKL","BXT", "KBL", - "GLK", "CNL", "ICL", "ICLLP", "TGLLP", "DG1"] +# order does really matter. +# It is used to define ordering between the respected platforms +platform_list = ["HSW", "BDW", "CHV", "SKL", "BXT", "KBL", + "GLK", "CNL", "ICL", "ICLLP", "TGLLP", "DG1", "XEHP"] def getAttributeList(Attrs): """ From 7a46e7e3ea7eef37cc1a77043fd1bf6a3cab1d9e Mon Sep 17 00:00:00 2001 From: Parshintsev Anatoly Date: Fri, 10 Sep 2021 23:54:05 +0300 Subject: [PATCH 37/81] More robust procedure to query availability of an intrinsic on a particular platform --- GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp index 3a1fe24c..4958dd69 100755 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp @@ -470,8 +470,14 @@ bool GenXIntrinsic::isSupportedPlatform(const std::string &CPU, unsigned id) { "Unknown Platform"); assert(GenXIntrinsic::isGenXIntrinsic(id) && "this function should be used only for GenXIntrinsics"); - return SupportedIntrinsics.at( - CPU)[id - GenXIntrinsic::ID::not_genx_intrinsic - 1]; + auto PlatformInfoIt = SupportedIntrinsics.find(CPU); + if (PlatformInfoIt == SupportedIntrinsics.end()) + return false; + const auto &IntrinsicInfo = PlatformInfoIt->second; + size_t IntrinsicIdx = id - GenXIntrinsic::ID::not_genx_intrinsic - 1; + if (IntrinsicIdx < IntrinsicInfo.size()) + return IntrinsicInfo[IntrinsicIdx]; + return false; } /// Table of per-target intrinsic name tables. From 5647df399355098aa5e8fe2c5c6bab2442533224 Mon Sep 17 00:00:00 2001 From: Kirill Yansitov Date: Mon, 13 Sep 2021 12:29:38 +0000 Subject: [PATCH 38/81] Add 3rd argument for imad --- .../include/llvm/GenXIntrinsics/Intrinsic_definitions.py | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py index 5fbf7a50..53eacb01 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py @@ -1170,17 +1170,18 @@ ### * ``llvm.genx.simad`` : result and operands signed ### * ``llvm.genx.uimad`` : result and operands unsigned ### -### result := {hi, lo} = arg0 * arg1 +### result := {hi, lo} = arg0 * arg1 + arg2 ### ### * arg0: first input, i32 scalar/vector integer type ### * arg1: second input, same type as arg0 +### * arg2: third input, same type as arg0 ### "simad" : { "result" : ["anyint", "anyint"], - "arguments" : [0, 0], + "arguments" : [0, 0, 0], "attributes" : "NoMem" }, "uimad" : { "result" : ["anyint", "anyint"], - "arguments" : [0, 0], + "arguments" : [0, 0, 0], "attributes" : "NoMem" }, From 085fcacac61e4012db8c7a175c43d7aa23f1911a Mon Sep 17 00:00:00 2001 From: DmitryBushev Date: Tue, 7 Sep 2021 17:07:27 +0000 Subject: [PATCH 39/81] In case there no kernels in module, SPIRV adaptor passes would skip proccessing of all functions that is not right --- .../GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp | 9 +++---- .../test/Adaptors/no_kernels_module_reader.ll | 23 ++++++++++++++++++ .../test/Adaptors/no_kernels_module_writer.ll | 24 +++++++++++++++++++ 3 files changed, 52 insertions(+), 4 deletions(-) create mode 100644 GenXIntrinsics/test/Adaptors/no_kernels_module_reader.ll create mode 100644 GenXIntrinsics/test/Adaptors/no_kernels_module_writer.ll diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp index 3ddc39ad..533d821e 100755 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp @@ -457,12 +457,13 @@ bool GenXSPIRVWriterAdaptorImpl::run(Module &M) { } } - if (auto *MD = M.getNamedMetadata(FunctionMD::GenXKernels)) { - for (auto &&F : M) + + for (auto &&F : M) runOnFunction(F); - // Old metadata is not needed anymore at this point. + + // Old metadata is not needed anymore at this point. + if (auto *MD = M.getNamedMetadata(FunctionMD::GenXKernels)) M.eraseNamedMetadata(MD); - } if (RewriteTypes) rewriteKernelsTypes(M); diff --git a/GenXIntrinsics/test/Adaptors/no_kernels_module_reader.ll b/GenXIntrinsics/test/Adaptors/no_kernels_module_reader.ll new file mode 100644 index 00000000..090d4c91 --- /dev/null +++ b/GenXIntrinsics/test/Adaptors/no_kernels_module_reader.ll @@ -0,0 +1,23 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2021 Intel Corporation +; +; SPDX-License-Identifier: MIT +; +;============================ end_copyright_notice ============================= + +; XFAIL: llvm13,llvm14 +; Test general translation of attributes within module that has no kernels + +; RUN: opt -S -GenXSPIRVReaderAdaptor < %s | FileCheck %s + +; CHECK: @some_func +; CHECK-SAME: #[[ATTR_GROUP:[0-9]+]] +define <16 x float> @some_func(<16 x float> %x) local_unnamed_addr #0 { + ret <16 x float> %x +} + +; CHECK: attributes #[[ATTR_GROUP]] = { +; CHECK: "CMStackCall" +; CHECK: } +attributes #0 = { "VCStackCall" "VCFunction"} diff --git a/GenXIntrinsics/test/Adaptors/no_kernels_module_writer.ll b/GenXIntrinsics/test/Adaptors/no_kernels_module_writer.ll new file mode 100644 index 00000000..e5d7093e --- /dev/null +++ b/GenXIntrinsics/test/Adaptors/no_kernels_module_writer.ll @@ -0,0 +1,24 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2021 Intel Corporation +; +; SPDX-License-Identifier: MIT +; +;============================ end_copyright_notice ============================= + +; Test general translation of attributes within module that has no kernels + +; RUN: opt -S -GenXSPIRVWriterAdaptor < %s | FileCheck %s + +; CHECK: @some_func +; CHECK: #[[ATTR_GROUP:[0-9]+]] + +define <16 x float> @some_func(<16 x float> %x) local_unnamed_addr #0 { + ret <16 x float> %x +} + +; CHECK: attributes #[[ATTR_GROUP]] = { +; CHECK-DAG: "VCFunction" +; CHECK-DAG: "VCStackCall" +; CHECK: } +attributes #0 = { "CMStackCall" } From 5c8159af873c96110c1b354f8660c044ff6b35b0 Mon Sep 17 00:00:00 2001 From: Anatoly Parshintsev Date: Sun, 26 Sep 2021 06:19:09 +0000 Subject: [PATCH 40/81] Cleanup unnecessary/deprecated attributes from test --- GenXIntrinsics/test/Adaptors/sev_signature_reader.ll | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/GenXIntrinsics/test/Adaptors/sev_signature_reader.ll b/GenXIntrinsics/test/Adaptors/sev_signature_reader.ll index 63c43958..f282517a 100644 --- a/GenXIntrinsics/test/Adaptors/sev_signature_reader.ll +++ b/GenXIntrinsics/test/Adaptors/sev_signature_reader.ll @@ -66,6 +66,6 @@ declare void @llvm.genx.some.intr.0(i32* "VCSingleElementVector") declare void @llvm.genx.some.intr.1(i32*** "VCSingleElementVector"="2") attributes #0 = { "VCFunction" } -attributes #1 = { "VCFunction" "VCNamedBarrierCount"="0" "VCSLMSize"="0" } +attributes #1 = { "VCFunction" "VCSLMSize"="0" } attributes #2 = { "VCGlobalVariable" "VCSingleElementVector"="0" } attributes #3 = { "VCGlobalVariable" "VCSingleElementVector"="2" } From 465abdd6522b8e21b2c60ca2694bc8964a24c164 Mon Sep 17 00:00:00 2001 From: Aleksander Us Date: Thu, 23 Sep 2021 17:52:34 +0000 Subject: [PATCH 41/81] Add media block images to SPIRV adaptors Translate arguments annotated with "image2d_media_block_t" to special opaque type. New annotation is required to distinguish media block images and texture images. --- .../lib/GenXIntrinsics/AdaptorsCommon.h | 5 +++ .../GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp | 37 +++++++++++++------ .../GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp | 25 +++++++++---- .../test/Adaptors/media_block_reader.ll | 37 +++++++++++++++++++ .../test/Adaptors/media_block_writer.ll | 32 ++++++++++++++++ 5 files changed, 117 insertions(+), 19 deletions(-) create mode 100644 GenXIntrinsics/test/Adaptors/media_block_reader.ll create mode 100644 GenXIntrinsics/test/Adaptors/media_block_writer.ll diff --git a/GenXIntrinsics/lib/GenXIntrinsics/AdaptorsCommon.h b/GenXIntrinsics/lib/GenXIntrinsics/AdaptorsCommon.h index f864086e..0ddee515 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/AdaptorsCommon.h +++ b/GenXIntrinsics/lib/GenXIntrinsics/AdaptorsCommon.h @@ -33,6 +33,7 @@ static constexpr const char Image1dArray[] = "image1d_array_t"; static constexpr const char Image1dBuffer[] = "image1d_buffer_t"; static constexpr const char Image2d[] = "image2d_t"; static constexpr const char Image2dArray[] = "image2d_array_t"; +static constexpr const char Image2dMediaBlock[] = "image2d_media_block_t"; static constexpr const char Image3d[] = "image3d_t"; } // namespace ArgDesc @@ -47,6 +48,7 @@ enum class SPIRVType { Image1dBuffer, Image2d, Image2dArray, + Image2dMediaBlock, Image3d, // Sampler + sampler_t. Sampler, @@ -98,6 +100,8 @@ static constexpr const char TypePrefix[] = "intel."; // Stateful buffer type. static constexpr const char Buffer[] = "buffer"; +// Media block image. +static constexpr const char MediaBlockImage[] = "image2d_media_block"; } // namespace IntelTypes namespace CommonTypes { @@ -134,6 +138,7 @@ inline unsigned getOpaqueTypeAddressSpace(SPIRVType Ty) { case SPIRVType::Image1dBuffer: case SPIRVType::Image2d: case SPIRVType::Image2dArray: + case SPIRVType::Image2dMediaBlock: case SPIRVType::Image3d: return SPIRVParams::SPIRVGlobalAS; default: diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp index cc47e72c..0b893cca 100755 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp @@ -111,19 +111,26 @@ static SPIRVArgDesc parseImageType(StringRef TyName) { return {ImageType, AccType}; } -static Optional parseBufferType(StringRef TyName) { - if (!TyName.consume_front(IntelTypes::TypePrefix)) - return None; +static std::pair parseIntelMainType(StringRef TyName) { + if (TyName.consume_front(IntelTypes::Buffer)) + return {SPIRVType::Buffer, TyName}; + + if (TyName.consume_front(IntelTypes::MediaBlockImage)) + return {SPIRVType::Image2dMediaBlock, TyName}; + + llvm_unreachable("Unexpected intel extension type"); +} - if (!TyName.consume_front(IntelTypes::Buffer)) +static Optional parseIntelType(StringRef TyName) { + if (!TyName.consume_front(IntelTypes::TypePrefix)) return None; - // Now assume that buffer type is correct. + SPIRVType MainType; + std::tie(MainType, TyName) = parseIntelMainType(TyName); AccessType AccType; - StringRef Suffix; - std::tie(AccType, Suffix) = parseAccessQualifier(TyName); - assert(Suffix == CommonTypes::TypeSuffix && "Bad buffer type"); - return SPIRVArgDesc{SPIRVType::Buffer, AccType}; + std::tie(AccType, TyName) = parseAccessQualifier(TyName); + assert(TyName == CommonTypes::TypeSuffix && "Bad intel type"); + return SPIRVArgDesc{MainType, AccType}; } static Optional parseOCLType(StringRef TyName) { @@ -141,15 +148,17 @@ static Optional parseOCLType(StringRef TyName) { } // Parse opaque type name. -// Ty -> "opencl." OCLTy | "intel.buffer" Acc "_t" +// Ty -> "opencl." OCLTy | "intel." IntelTy // OCLTy -> "sampler_t" | ImageTy +// IntelTy -> MainIntelTy Acc "_t" +// MainIntelTy -> "buffer" | "image2d_media_block" // ImageTy -> "image" Dim Acc "_t" // Dim -> "1d" | "1d_buffer" | "2d" | "3d" // Acc -> "_ro" | "_wo" | "_rw" // Assume that "opencl." and "intel.buffer" types are well-formed. static Optional parseOpaqueType(StringRef TyName) { - if (auto MaybeBuffer = parseBufferType(TyName)) - return MaybeBuffer.getValue(); + if (auto MaybeIntelTy = parseIntelType(TyName)) + return MaybeIntelTy.getValue(); return parseOCLType(TyName); } @@ -231,6 +240,7 @@ static ArgKind mapSPIRVTypeToArgKind(SPIRVType Ty) { case SPIRVType::Image1dBuffer: case SPIRVType::Image2d: case SPIRVType::Image2dArray: + case SPIRVType::Image2dMediaBlock: case SPIRVType::Image3d: return ArgKind::Surface; case SPIRVType::Sampler: @@ -265,6 +275,9 @@ static std::string mapSPIRVDescToArgDesc(SPIRVArgDesc SPIRVDesc) { case SPIRVType::Image2dArray: Desc += ArgDesc::Image2dArray; break; + case SPIRVType::Image2dMediaBlock: + Desc += ArgDesc::Image2dMediaBlock; + break; case SPIRVType::Image3d: Desc += ArgDesc::Image3d; break; diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp index 533d821e..4e1bcfab 100755 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp @@ -137,15 +137,23 @@ static Type *getImageType(SPIRVArgDesc Desc, Module *M) { return getOpaquePtrType(M, Name, getOpaqueTypeAddressSpace(Desc.Ty)); } -// Get or create buffer type with given access qualifier. -static Type *getBufferType(AccessType Acc, Module *M) { +// Get or create vector compute extension type with given access qualifier. +static Type *getIntelExtType(SPIRVArgDesc Desc, Module *M) { std::string Name = IntelTypes::TypePrefix; - Name += IntelTypes::Buffer; + switch (Desc.Ty) { + case SPIRVType::Buffer: + Name += IntelTypes::Buffer; + break; + case SPIRVType::Image2dMediaBlock: + Name += IntelTypes::MediaBlockImage; + break; + default: + llvm_unreachable("Unexpected spirv type for intel extensions"); + } - addCommonTypesPostfix(Name, Acc); + addCommonTypesPostfix(Name, Desc.Acc); - return getOpaquePtrType(M, Name, - getOpaqueTypeAddressSpace(SPIRVType::Buffer)); + return getOpaquePtrType(M, Name, getOpaqueTypeAddressSpace(Desc.Ty)); } // Sampler and surface arguments require opaque types that will be @@ -155,7 +163,8 @@ static Type *getOpaqueType(SPIRVArgDesc Desc, Module *M) { case SPIRVType::Sampler: return getSamplerType(M); case SPIRVType::Buffer: - return getBufferType(Desc.Acc, M); + case SPIRVType::Image2dMediaBlock: + return getIntelExtType(Desc, M); default: return getImageType(Desc, M); } @@ -250,6 +259,7 @@ static SPIRVArgDesc parseArgDesc(StringRef Desc) { .Case(ArgDesc::Image1dBuffer, SPIRVType::Image1dBuffer) .Case(ArgDesc::Image2d, SPIRVType::Image2d) .Case(ArgDesc::Image2dArray, SPIRVType::Image2dArray) + .Case(ArgDesc::Image2dMediaBlock, SPIRVType::Image2dMediaBlock) .Case(ArgDesc::Image3d, SPIRVType::Image3d) .Case(ArgDesc::SVM, SPIRVType::Pointer) .Case(ArgDesc::Sampler, SPIRVType::Sampler) @@ -302,6 +312,7 @@ static SPIRVArgDesc analyzeSurfaceArg(StringRef Desc) { case SPIRVType::Image1dBuffer: case SPIRVType::Image2d: case SPIRVType::Image2dArray: + case SPIRVType::Image2dMediaBlock: case SPIRVType::Image3d: return SPVDesc; // CMRT does not require to annotate arguments. diff --git a/GenXIntrinsics/test/Adaptors/media_block_reader.ll b/GenXIntrinsics/test/Adaptors/media_block_reader.ll new file mode 100644 index 00000000..810627d0 --- /dev/null +++ b/GenXIntrinsics/test/Adaptors/media_block_reader.ll @@ -0,0 +1,37 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2021 Intel Corporation +; +; SPDX-License-Identifier: MIT +; +;============================ end_copyright_notice ============================= + +; XFAIL: llvm13,llvm14 +; Test reader translation of media block image arguments. + +; RUN: opt -S -GenXSPIRVReaderAdaptor < %s | FileCheck %s + +%intel.image2d_media_block_ro_t = type opaque + +define spir_kernel void @test(%intel.image2d_media_block_ro_t addrspace(1)* %image) #0 { +; CHECK-LABEL: @test( + +; CHECK: i32 +; CHECK [[IMAGE:%[^)]+]]) + +; CHECK-NEXT: entry: +; CHECK-NEXT: ret void +; +entry: + %0 = call i32 @llvm.genx.address.convert.i32.p1intel.image2d_media_block_ro_t(%intel.image2d_media_block_ro_t addrspace(1)* %image) + ret void +} + +declare i32 @llvm.genx.address.convert.i32.p1intel.image2d_media_block_ro_t(%intel.image2d_media_block_ro_t addrspace(1)*) + +attributes #0 = { "VCFunction" } + +; CHECK: !genx.kernels = !{[[KERNEL:![0-9]+]]} +; CHECK: [[KERNEL]] = !{void (i32)* @test, !"test", [[KINDS:![0-9]+]], i32 0, i32 0, !{{[0-9]+}}, [[DESCS:![0-9]+]], i32 0} +; CHECK-DAG: [[KINDS]] = !{i32 2} +; CHECK-DAG: [[DESCS]] = !{!"image2d_media_block_t read_only"} diff --git a/GenXIntrinsics/test/Adaptors/media_block_writer.ll b/GenXIntrinsics/test/Adaptors/media_block_writer.ll new file mode 100644 index 00000000..8238ee0b --- /dev/null +++ b/GenXIntrinsics/test/Adaptors/media_block_writer.ll @@ -0,0 +1,32 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2021 Intel Corporation +; +; SPDX-License-Identifier: MIT +; +;============================ end_copyright_notice ============================= + +; Test writer translation of media block images arguments. + +; RUN: opt -S -GenXSPIRVWriterAdaptor < %s | FileCheck %s + +define void @test(i32 %image) { +; CHECK-LABEL: @test( + +; CHECK: %intel.image2d_media_block_ro_t addrspace(1)* +; CHECK: [[IMAGE:%[^)]+]]) + +; CHECK-NEXT: entry: +; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.genx.address.convert.i32.p1intel.image2d_media_block_ro_t(%intel.image2d_media_block_ro_t addrspace(1)* [[IMAGE]]) +; CHECK-NEXT: ret void +; +entry: + ret void +} + +!genx.kernels = !{!0} + +!0 = !{void (i32)* @test, !"test", !1, i32 0, i32 0, !2, !3, i32 0, i32 0} +!1 = !{i32 2} +!2 = !{i32 0} +!3 = !{!"image2d_media_block_t read_only"} From 9aafb518a05be160beffd7812a0f169c10786d04 Mon Sep 17 00:00:00 2001 From: DmitryBushev Date: Tue, 28 Sep 2021 16:24:03 +0000 Subject: [PATCH 42/81] SPIRV-LLVM-Translator may convert native SPIRV types to 'SPIRV friendly IR' types defined in translator docs if dedicated option is passed. Adaptor should be able to read them as well as OCL types. --- .../lib/GenXIntrinsics/AdaptorsCommon.h | 10 ++ .../GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp | 107 +++++++++++++++++- .../Adaptors/spirv_friendly_types_reader.ll | 55 +++++++++ 3 files changed, 169 insertions(+), 3 deletions(-) create mode 100644 GenXIntrinsics/test/Adaptors/spirv_friendly_types_reader.ll diff --git a/GenXIntrinsics/lib/GenXIntrinsics/AdaptorsCommon.h b/GenXIntrinsics/lib/GenXIntrinsics/AdaptorsCommon.h index 0ddee515..413f4e41 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/AdaptorsCommon.h +++ b/GenXIntrinsics/lib/GenXIntrinsics/AdaptorsCommon.h @@ -92,6 +92,16 @@ static constexpr const char Dim3d[] = "3d"; static constexpr const char Sampler[] = "sampler"; } // namespace OCLTypes +// SPIRV friendly IR types. May be generated by SPIRV-LLVM-Translator. +namespace SPIRVIRTypes { + +static constexpr const char TypePrefix[] = "spirv."; + +enum Dim { Dim1D = 0, Dim2D = 1, Dim3D = 2, DimBuffer = 5 }; +static constexpr const char Image[] = "Image."; +static constexpr const char Sampler[] = "Sampler"; +} // namespace SPIRVIRTypes + // These are not really standardized names. // Just something for POC implementation. namespace IntelTypes { diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp index 0b893cca..089a5127 100755 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp @@ -121,6 +121,92 @@ static std::pair parseIntelMainType(StringRef TyName) { llvm_unreachable("Unexpected intel extension type"); } +template T consumeIntegerLiteral(StringRef TyName) { + int Literal; + + auto ProperlyConsumed = !TyName.consumeInteger(0, Literal); + assert(ProperlyConsumed && "Expected string to rpresent integer literal"); + (void)ProperlyConsumed; + + return static_cast(Literal); +} + +static SPIRVType evaluateImageTypeFromSPVIR(SPIRVIRTypes::Dim Dim, + bool Arrayed) { + SPIRVType ResultType; + if (!Arrayed) { + switch (Dim) { + case SPIRVIRTypes::Dim1D: + ResultType = SPIRVType::Image1d; + break; + case SPIRVIRTypes::Dim2D: + ResultType = SPIRVType::Image2d; + break; + case SPIRVIRTypes::Dim3D: + ResultType = SPIRVType::Image3d; + break; + case SPIRVIRTypes::DimBuffer: + ResultType = SPIRVType::Image1dBuffer; + break; + default: + llvm_unreachable("Bad Image Type"); + } + } else { + switch (Dim) { + case SPIRVIRTypes::Dim1D: + ResultType = SPIRVType::Image1dArray; + break; + case SPIRVIRTypes::Dim2D: + ResultType = SPIRVType::Image2dArray; + break; + default: + llvm_unreachable("Bad Image Type"); + } + } + + return ResultType; +} + +static StringRef skipUnderscores(StringRef StrRef, int Count) { + for (int i = 0; i < Count; ++i) { + StrRef = StrRef.drop_while([](char C) { return C != '_'; }); + StrRef = StrRef.drop_front(1); + } + + return StrRef; +} + +static SPIRVArgDesc parseSPIRVIRImageType(StringRef TyName) { + const bool Consumed = TyName.consume_front(SPIRVIRTypes::Image); + assert(Consumed && "Unexpected SPIRV friendly IR type"); + (void)Consumed; + + // SPIRV friendly Ir image type looks like this: + // spirv.Image._{Sampled T}_{Dim}_{Depth}_{Arrayed}_{MS}_{Fmt}_{Acc} + + // skip Samled Type. + TyName = skipUnderscores(TyName, 2); + + auto Dim = consumeIntegerLiteral(TyName); + + // Skip Depth. + TyName = skipUnderscores(TyName, 2); + + auto Arrayed = consumeIntegerLiteral(TyName); + + // Skip Multisampling and Format. + TyName = skipUnderscores(TyName, 4); + + AccessType AccessTy = AccessType::ReadOnly; + + if (!TyName.empty()) + AccessTy = consumeIntegerLiteral(TyName); + + auto ResultType = evaluateImageTypeFromSPVIR(Dim, Arrayed); + + return {ResultType, AccessTy}; +} + static Optional parseIntelType(StringRef TyName) { if (!TyName.consume_front(IntelTypes::TypePrefix)) return None; @@ -147,20 +233,35 @@ static Optional parseOCLType(StringRef TyName) { return parseImageType(TyName); } +static Optional parseSPIRVIRType(StringRef TyName) { + if (!TyName.consume_front(SPIRVIRTypes::TypePrefix)) + return None; + + if (TyName.consume_front(SPIRVIRTypes::Sampler)) + return {SPIRVType::Sampler}; + + return parseSPIRVIRImageType(TyName); +} // Parse opaque type name. -// Ty -> "opencl." OCLTy | "intel." IntelTy +// Ty -> "opencl." OCLTy | "spirv." SPVIRTy | "intel" IntelTy // OCLTy -> "sampler_t" | ImageTy // IntelTy -> MainIntelTy Acc "_t" // MainIntelTy -> "buffer" | "image2d_media_block" // ImageTy -> "image" Dim Acc "_t" // Dim -> "1d" | "1d_buffer" | "2d" | "3d" // Acc -> "_ro" | "_wo" | "_rw" -// Assume that "opencl." and "intel.buffer" types are well-formed. +// SPVIRTy -> "Sampler" | SPVImageTy +// SPVImageTy -> "Image." _..._{Dim}_..._{Arrayed}_..._{Acc} +// Dim, Arrayed, Acc - literal operands matching OpTypeImage operands in SPIRV +// Assume that "opencl." "spirv." and "intel.buffer" types are well-formed. static Optional parseOpaqueType(StringRef TyName) { if (auto MaybeIntelTy = parseIntelType(TyName)) return MaybeIntelTy.getValue(); - return parseOCLType(TyName); + if (auto MaybeOCL = parseOCLType(TyName)) + return MaybeOCL.getValue(); + + return parseSPIRVIRType(TyName); } static SPIRVArgDesc analyzeKernelArg(const Argument &Arg) { diff --git a/GenXIntrinsics/test/Adaptors/spirv_friendly_types_reader.ll b/GenXIntrinsics/test/Adaptors/spirv_friendly_types_reader.ll new file mode 100644 index 00000000..bd43cee6 --- /dev/null +++ b/GenXIntrinsics/test/Adaptors/spirv_friendly_types_reader.ll @@ -0,0 +1,55 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2021 Intel Corporation +; +; SPDX-License-Identifier: MIT +; +;============================ end_copyright_notice ============================= + +; XFAIL: llvm13,llvm14 +; Test reader translation of SPIRV friendly IR types + +; RUN: opt -S -GenXSPIRVReaderAdaptor < %s | FileCheck %s + +%spirv.Sampler = type opaque +%spirv.Image._void_0_0_1_0_0_0_0 = type opaque +%spirv.Image._void_1_0_1_0_0_0_1 = type opaque +%spirv.Image._void_2_0_0_0_0_0_2 = type opaque + +define spir_kernel void @test(%spirv.Sampler addrspace(2)* %smp, %spirv.Image._void_0_0_1_0_0_0_0 addrspace(1)* %im1d, %spirv.Image._void_1_0_1_0_0_0_1 addrspace(1)* %im2d, %spirv.Image._void_2_0_0_0_0_0_2 addrspace(1)* %im3d) #0 { +; CHECK-LABEL: @test( + +; CHECK: i32 +; CHECK: [[SMP:%[^,]+]], + +; CHECK: i32 +; CHECK: [[IM1D:%[^,]+]], + +; CHECK: i32 +; CHECK: [[IM2D:%[^,]+]], + +; CHECK: i32 +; CHECK: [[IM3D:%[^,]+]]) + +; CHECK-NEXT: entry: +; CHECK-NEXT: ret void +; +entry: + %0 = call i32 @llvm.genx.address.convert.i32.p2spirv.Sampler(%spirv.Sampler addrspace(2)* %smp) + %1 = call i32 @llvm.genx.address.convert.i32.p1spirv.Image._void_0_0_1_0_0_0_0(%spirv.Image._void_0_0_1_0_0_0_0 addrspace(1)* %im1d) + %2 = call i32 @llvm.genx.address.convert.i32.p1spirv.Image._void_1_0_1_0_0_0_1(%spirv.Image._void_1_0_1_0_0_0_1 addrspace(1)* %im2d) + %3 = call i32 @llvm.genx.address.convert.i32.p1spirv.Image._void_2_0_0_0_0_0_2(%spirv.Image._void_2_0_0_0_0_0_2 addrspace(1)* %im3d) + ret void +} + +declare i32 @llvm.genx.address.convert.i32.p2spirv.Sampler(%spirv.Sampler addrspace(2)*) +declare i32 @llvm.genx.address.convert.i32.p1spirv.Image._void_0_0_1_0_0_0_0(%spirv.Image._void_0_0_1_0_0_0_0 addrspace(1)*) +declare i32 @llvm.genx.address.convert.i32.p1spirv.Image._void_1_0_1_0_0_0_1(%spirv.Image._void_1_0_1_0_0_0_1 addrspace(1)*) +declare i32 @llvm.genx.address.convert.i32.p1spirv.Image._void_2_0_0_0_0_0_2(%spirv.Image._void_2_0_0_0_0_0_2 addrspace(1)*) + +attributes #0 = { "VCFunction" } + +; CHECK: !genx.kernels = !{[[KERNEL:![0-9]+]]} +; CHECK: [[KERNEL]] = !{void (i32, i32, i32, i32)* @test, !"test", [[KINDS:![0-9]+]], i32 0, i32 0, !{{[0-9]+}}, [[DESCS:![0-9]+]], i32 0} +; CHECK-DAG: [[KINDS]] = !{i32 1, i32 2, i32 2, i32 2} +; CHECK-DAG: [[DESCS]] = !{!"sampler_t", !"image1d_array_t read_only", !"image2d_array_t write_only", !"image3d_t read_write"} From 2140c91a241703d7d6c39d1b86e7684b2558d9d5 Mon Sep 17 00:00:00 2001 From: Anatoly Parshintsev Date: Fri, 1 Oct 2021 14:36:09 +0000 Subject: [PATCH 43/81] spirv reader adaptor should discard redundant attributes --- .../include/llvmVCWrapper/IR/Attributes.h | 33 +++++++++ .../GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp | 73 +++++++++++++++---- .../args_attributes_transform_reader.ll | 4 +- .../fun_attributes_transform_reader.ll | 67 +++++++++++++++++ .../test/Adaptors/non_global_ptr_reader.ll | 6 +- .../Adaptors/old_decorated_args_reader.ll | 11 +-- .../test/Adaptors/unknown_arg_reader.ll | 6 +- 7 files changed, 164 insertions(+), 36 deletions(-) create mode 100644 GenXIntrinsics/test/Adaptors/fun_attributes_transform_reader.ll diff --git a/GenXIntrinsics/include/llvmVCWrapper/IR/Attributes.h b/GenXIntrinsics/include/llvmVCWrapper/IR/Attributes.h index 8af2ef73..4902572d 100644 --- a/GenXIntrinsics/include/llvmVCWrapper/IR/Attributes.h +++ b/GenXIntrinsics/include/llvmVCWrapper/IR/Attributes.h @@ -72,6 +72,39 @@ inline llvm::Attribute getAttributeAtIndex(const llvm::AttributeList &AttrList, #endif } +inline llvm::AttributeList +removeAttributeAtIndex(llvm::LLVMContext &C, + const llvm::AttributeList &AttrList, unsigned Index, + llvm::Attribute::AttrKind Kind) { +#if VC_INTR_LLVM_VERSION_MAJOR >= 14 + return AttrList.removeAttributeAtIndex(C, Index, Kind); +#else + return AttrList.removeAttribute(C, Index, Kind); +#endif +} + +inline llvm::AttributeList +removeAttributeAtIndex(llvm::LLVMContext &C, + const llvm::AttributeList &AttrList, unsigned Index, + llvm::StringRef Kind) { +#if VC_INTR_LLVM_VERSION_MAJOR >= 14 + return AttrList.removeAttributeAtIndex(C, Index, Kind); +#else + return AttrList.removeAttribute(C, Index, Kind); +#endif +} + +inline llvm::AttributeList +removeAttributesAtIndex(llvm::LLVMContext &C, + const llvm::AttributeList &AttrList, unsigned Index, + const llvm::AttrBuilder &AttrsToRemove) { +#if VC_INTR_LLVM_VERSION_MAJOR >= 14 + return AttrList.removeAttributesAtIndex(C, Index, AttrsToRemove); +#else + return AttrList.removeAttributes(C, Index, AttrsToRemove); +#endif +} + } // namespace AttributeList } // namespace VCINTR diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp index 089a5127..3cc8f4c2 100755 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp @@ -43,6 +43,18 @@ class GenXSPIRVReaderAdaptor final : public ModulePass { private: bool runOnFunction(Function &F); + + bool processVCFunctionAttributes(Function &F); + bool processVCKernelAttributes(Function &F); + + void dropAttributeAtIndex(Function &F, unsigned Index, StringRef Kind) { + auto NewAttributes = VCINTR::AttributeList::removeAttributeAtIndex( + F.getContext(), F.getAttributes(), Index, Kind); + F.setAttributes(NewAttributes); + } + void dropFnAttribute(Function &F, StringRef Kind) { + dropAttributeAtIndex(F, AttributeList::FunctionIndex, Kind); + } }; } // namespace @@ -541,22 +553,27 @@ bool GenXSPIRVReaderAdaptor::runOnModule(Module &M) { return true; } -bool GenXSPIRVReaderAdaptor::runOnFunction(Function &F) { +bool GenXSPIRVReaderAdaptor::processVCFunctionAttributes(Function &F) { auto Attrs = F.getAttributes(); if (!VCINTR::AttributeList::hasFnAttr(Attrs, VCFunctionMD::VCFunction)) - return true; + return false; + + dropFnAttribute(F, VCFunctionMD::VCFunction); if (VCINTR::AttributeList::hasFnAttr(Attrs, VCFunctionMD::VCStackCall)) { F.addFnAttr(FunctionMD::CMStackCall); F.addFnAttr(Attribute::NoInline); + dropFnAttribute(F, VCFunctionMD::VCStackCall); } if (VCINTR::AttributeList::hasFnAttr(Attrs, VCFunctionMD::VCCallable)) { F.addFnAttr(FunctionMD::CMCallable); + dropFnAttribute(F, VCFunctionMD::VCCallable); } if (VCINTR::AttributeList::hasFnAttr(Attrs, VCFunctionMD::VCFCEntry)) { F.addFnAttr(FunctionMD::CMEntry); + dropFnAttribute(F, VCFunctionMD::VCFCEntry); } if (VCINTR::AttributeList::hasFnAttr(Attrs, VCFunctionMD::VCSIMTCall)) { @@ -566,6 +583,7 @@ bool GenXSPIRVReaderAdaptor::runOnFunction(Function &F) { Attrs, AttributeList::FunctionIndex, VCFunctionMD::VCSIMTCall) .getValueAsString(); F.addFnAttr(FunctionMD::CMGenxSIMT, SIMTMode); + dropFnAttribute(F, VCFunctionMD::VCSIMTCall); } auto &&Context = F.getContext(); @@ -580,6 +598,7 @@ bool GenXSPIRVReaderAdaptor::runOnFunction(Function &F) { std::to_string(FloatControl)); VCINTR::Function::addAttributeAtIndex(F, AttributeList::FunctionIndex, Attr); + dropFnAttribute(F, VCFunctionMD::VCFloatControl); } if (auto *ReqdSubgroupSize = @@ -592,12 +611,18 @@ bool GenXSPIRVReaderAdaptor::runOnFunction(Function &F) { VCINTR::Function::addAttributeAtIndex(F, AttributeList::FunctionIndex, Attr); } + return true; +} +bool GenXSPIRVReaderAdaptor::processVCKernelAttributes(Function &F) { if (!(F.getCallingConv() == CallingConv::SPIR_KERNEL)) - return true; + return false; + F.addFnAttr(FunctionMD::CMGenXMain); F.setDLLStorageClass(llvm::GlobalVariable::DLLExportStorageClass); + auto Attrs = F.getAttributes(); + auto *FunctionRef = ValueAsMetadata::get(&F); auto KernelName = F.getName(); auto ArgKinds = llvm::SmallVector(); @@ -606,40 +631,39 @@ bool GenXSPIRVReaderAdaptor::runOnFunction(Function &F) { auto ArgIOKinds = llvm::SmallVector(); auto ArgDescs = llvm::SmallVector(); + auto &&Context = F.getContext(); llvm::Type *I32Ty = llvm::Type::getInt32Ty(Context); - if (VCINTR::AttributeList::hasFnAttr(Attrs, VCFunctionMD::VCSLMSize)) { - VCINTR::AttributeList::getAttributeAtIndex( - Attrs, AttributeList::FunctionIndex, VCFunctionMD::VCSLMSize) - .getValueAsString() - .getAsInteger(0, SLMSize); - } - for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { auto ArgNo = I->getArgNo(); auto ArgKind = unsigned(0); auto ArgIOKind = unsigned(0); auto ArgDesc = std::string(); + auto AttrIndex = ArgNo + 1; + if (VCINTR::AttributeList::hasAttributeAtIndex( - Attrs, ArgNo + 1, VCFunctionMD::VCArgumentKind)) { - VCINTR::AttributeList::getAttributeAtIndex(Attrs, ArgNo + 1, + Attrs, AttrIndex, VCFunctionMD::VCArgumentKind)) { + VCINTR::AttributeList::getAttributeAtIndex(Attrs, AttrIndex, VCFunctionMD::VCArgumentKind) .getValueAsString() .getAsInteger(0, ArgKind); + dropAttributeAtIndex(F, AttrIndex, VCFunctionMD::VCArgumentKind); } if (VCINTR::AttributeList::hasAttributeAtIndex( - Attrs, ArgNo + 1, VCFunctionMD::VCArgumentIOKind)) { - VCINTR::AttributeList::getAttributeAtIndex(Attrs, ArgNo + 1, + Attrs, AttrIndex, VCFunctionMD::VCArgumentIOKind)) { + VCINTR::AttributeList::getAttributeAtIndex(Attrs, AttrIndex, VCFunctionMD::VCArgumentIOKind) .getValueAsString() .getAsInteger(0, ArgIOKind); + dropAttributeAtIndex(F, AttrIndex, VCFunctionMD::VCArgumentIOKind); } if (VCINTR::AttributeList::hasAttributeAtIndex( - Attrs, ArgNo + 1, VCFunctionMD::VCArgumentDesc)) { + Attrs, AttrIndex, VCFunctionMD::VCArgumentDesc)) { ArgDesc = VCINTR::AttributeList::getAttributeAtIndex( - Attrs, ArgNo + 1, VCFunctionMD::VCArgumentDesc) + Attrs, AttrIndex, VCFunctionMD::VCArgumentDesc) .getValueAsString() .str(); + dropAttributeAtIndex(F, AttrIndex, VCFunctionMD::VCArgumentDesc); } ArgKinds.push_back( llvm::ValueAsMetadata::get(llvm::ConstantInt::get(I32Ty, ArgKind))); @@ -648,6 +672,14 @@ bool GenXSPIRVReaderAdaptor::runOnFunction(Function &F) { ArgDescs.push_back(llvm::MDString::get(Context, ArgDesc)); } + if (VCINTR::AttributeList::hasFnAttr(Attrs, VCFunctionMD::VCSLMSize)) { + VCINTR::AttributeList::getAttributeAtIndex( + Attrs, AttributeList::FunctionIndex, VCFunctionMD::VCSLMSize) + .getValueAsString() + .getAsInteger(0, SLMSize); + dropFnAttribute(F, VCFunctionMD::VCSLMSize); + } + auto KernelMD = std::vector(); KernelMD.push_back(FunctionRef); KernelMD.push_back(llvm::MDString::get(Context, KernelName)); @@ -663,5 +695,14 @@ bool GenXSPIRVReaderAdaptor::runOnFunction(Function &F) { F.getParent()->getOrInsertNamedMetadata(FunctionMD::GenXKernels); llvm::MDNode *Node = MDNode::get(F.getContext(), KernelMD); KernelMDs->addOperand(Node); + + return true; +} + +bool GenXSPIRVReaderAdaptor::runOnFunction(Function &F) { + if (!processVCFunctionAttributes(F)) + return true; + + processVCKernelAttributes(F); return true; } diff --git a/GenXIntrinsics/test/Adaptors/args_attributes_transform_reader.ll b/GenXIntrinsics/test/Adaptors/args_attributes_transform_reader.ll index 16797d96..69146873 100644 --- a/GenXIntrinsics/test/Adaptors/args_attributes_transform_reader.ll +++ b/GenXIntrinsics/test/Adaptors/args_attributes_transform_reader.ll @@ -12,9 +12,7 @@ ; XFAIL: llvm13, llvm14 ; RUN: opt -S -GenXSPIRVReaderAdaptor < %s | FileCheck %s ; CHECK: @test -; CHECK-SAME: %foo -; CHECK-SAME: byval(%foo) -; CHECK-SAME: arg +; CHECK-SAME: (%foo addrspace(1)* byval(%foo) %arg) %foo = type { i32 } diff --git a/GenXIntrinsics/test/Adaptors/fun_attributes_transform_reader.ll b/GenXIntrinsics/test/Adaptors/fun_attributes_transform_reader.ll new file mode 100644 index 00000000..c31ac347 --- /dev/null +++ b/GenXIntrinsics/test/Adaptors/fun_attributes_transform_reader.ll @@ -0,0 +1,67 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2021 Intel Corporation +; +; SPDX-License-Identifier: MIT +; +;============================ end_copyright_notice ============================= + +; Test that adaptor correctly translates function attributes to VC-specific +; metadata (the processed attributes are expected to be discarded) + +; UNSUPPORTED: llvm7, llvm8 +; XFAIL: llvm13, llvm14 +; RUN: opt -S -GenXSPIRVReaderAdaptor < %s | FileCheck %s +; CHECK: @test_VCFunction() +; CHECK: @test_VCStackCall() +; CHECK-SAME: #[[FATR_STACK_CALL_ATTR_IDX:[0-9]+]] +; CHECK: @test_VCCallable() +; CHECK-SAME: #[[FATR_CALLABLE_ATTR_IDX:[0-9]+]] +; CHECK: @test_VCFCEntry() +; CHECK-SAME: #[[FATR_FC_ENTRY_IDX:[0-9]+]] +; CHECK: @test_VCSIMTCall() +; CHECK-SAME: #[[FATR_SIMT_CALL_IDX:[0-9]+]] +; CHECK: @test_VCFloatControl() +; CHECK-SAME: #[[FATR_FLOAT_CONTROL_IDX:[0-9]+]] +; CHECK: @test_VCSLMSize() +; CHECK-SAME: #[[FATR_SLM_SIZE_IDX:[0-9]+]] + +define void @test_VCFunction() #0 { + ret void +} +define void @test_VCStackCall() #1 { + ret void +} +define void @test_VCCallable() #2 { + ret void +} +define void @test_VCFCEntry() #3 { + ret void +} +define void @test_VCSIMTCall() #4 { + ret void +} +define void @test_VCFloatControl() #5 { + ret void +} +define spir_kernel void @test_VCSLMSize() #6 { + ret void +} + +; CHECK-DAG: attributes #[[FATR_STACK_CALL_ATTR_IDX]] = { noinline "CMStackCall" } +; CHECK-DAG: attributes #[[FATR_CALLABLE_ATTR_IDX]] = { "CMCallable" } +; CHECK-DAG: attributes #[[FATR_FC_ENTRY_IDX]] = { "CMEntry" } +; CHECK-DAG: attributes #[[FATR_SIMT_CALL_IDX]] = { "CMGenxSIMT" } +; CHECK-DAG: attributes #[[FATR_FLOAT_CONTROL_IDX]] = { "CMFloatControl"="0" } +; CHECK-DAG: attributes #[[FATR_SLM_SIZE_IDX]] = { "CMGenxMain" } + +; CHECK-DAG: !{void ()* @test_VCSLMSize, !"test_VCSLMSize", !{{[0-9]+}}, i32 100500, i32 0, !{{[0-9]+}}, !{{[0-9]+}}, i32 0} + +attributes #0 = { "VCFunction" } +attributes #1 = { "VCFunction" "VCStackCall" } +attributes #2 = { "VCFunction" "VCCallable" } +attributes #3 = { "VCFunction" "VCFCEntry" } +attributes #4 = { "VCFunction" "VCSIMTCall" } +attributes #5 = { "VCFunction" "VCFloatControl"="0" } +attributes #6 = { "VCFunction" "VCSLMSize"="100500" } + diff --git a/GenXIntrinsics/test/Adaptors/non_global_ptr_reader.ll b/GenXIntrinsics/test/Adaptors/non_global_ptr_reader.ll index a2e467db..ab383288 100644 --- a/GenXIntrinsics/test/Adaptors/non_global_ptr_reader.ll +++ b/GenXIntrinsics/test/Adaptors/non_global_ptr_reader.ll @@ -13,11 +13,9 @@ ; RUN: opt -S -GenXSPIRVReaderAdaptor < %s | FileCheck %s define spir_kernel void @test(i32* %ptr) #0 { -; CHECK-LABEL: @test( -; CHECK: i32* -; CHECK: "VCArgumentKind"="0" -; CHECK: [[PTR:%[^)]+]]) +; CHECK-LABEL: @test +; CHECK-SAME: (i32* [[PTR:%[^)]+]]) ; CHECK-NEXT: entry: ; CHECK-NEXT: ret void diff --git a/GenXIntrinsics/test/Adaptors/old_decorated_args_reader.ll b/GenXIntrinsics/test/Adaptors/old_decorated_args_reader.ll index 141d7f2b..f78ba283 100644 --- a/GenXIntrinsics/test/Adaptors/old_decorated_args_reader.ll +++ b/GenXIntrinsics/test/Adaptors/old_decorated_args_reader.ll @@ -15,16 +15,9 @@ ; RUN: opt -S -GenXSPIRVReaderAdaptor < %s | FileCheck %s define spir_kernel void @test(i32 "VCArgumentDesc"="image2d_t read_only" "VCArgumentKind"="2" %in, i32 "VCArgumentDesc"="image2d_t write_only" "VCArgumentKind"="2" %out, <3 x i32> "VCArgumentKind"="24" %__arg_llvm.genx.local.id) #0 { -; CHECK-LABEL: @test( +; CHECK-LABEL: @test -; CHECK: i32 -; CHECK: [[IN:%[^,]+]], - -; CHECK: i32 -; CHECK: [[OUT:%[^,]+]], - -; CHECK: <3 x i32> -; CHECK: [[LOCAL_ID:%[^)]+]]) +; CHECK-SAME: (i32 [[IN:%[^,]+]], i32 [[OUT:%[^,]+]], <3 x i32> [[LOCAL_ID:%[^)]+]]) ; CHECK-NEXT: entry: ; CHECK-NEXT: [[TMP0:%.*]] = extractelement <3 x i32> [[LOCAL_ID]], i32 0 diff --git a/GenXIntrinsics/test/Adaptors/unknown_arg_reader.ll b/GenXIntrinsics/test/Adaptors/unknown_arg_reader.ll index d71fddf2..3201686a 100644 --- a/GenXIntrinsics/test/Adaptors/unknown_arg_reader.ll +++ b/GenXIntrinsics/test/Adaptors/unknown_arg_reader.ll @@ -13,11 +13,9 @@ ; RUN: opt -S -GenXSPIRVReaderAdaptor < %s | FileCheck %s define spir_kernel void @test(<3 x i32> "VCArgumentKind"="24" %__arg_llvm.genx.local.id) #0 { -; CHECK-LABEL: @test( -; CHECK: <3 x i32> -; CHECK: "VCArgumentKind"="24" -; CHECK: [[LOCAL_ID:%[^)]+]]) +; CHECK-LABEL: @test +; CHECK-SAME: (<3 x i32> [[LOCAL_ID:%[^)]+]]) ; CHECK-NEXT: entry: ; CHECK-NEXT: ret void From 2cd5a7b013d09d21ad206708943faf0b575e0ece Mon Sep 17 00:00:00 2001 From: Anatoly Parshintsev Date: Thu, 7 Oct 2021 12:25:27 +0000 Subject: [PATCH 44/81] introduce new RKL platform --- GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py index 327e97ce..21f1b1ff 100755 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py @@ -79,7 +79,7 @@ # order does really matter. # It is used to define ordering between the respected platforms platform_list = ["HSW", "BDW", "CHV", "SKL", "BXT", "KBL", - "GLK", "CNL", "ICL", "ICLLP", "TGLLP", "DG1", "XEHP"] + "GLK", "CNL", "ICL", "ICLLP", "TGLLP", "RKL", "DG1", "XEHP"] def getAttributeList(Attrs): """ From 6a7e93d3d90638b6565d97cef96ffaf0f77d688c Mon Sep 17 00:00:00 2001 From: Aleksander Us Date: Mon, 18 Oct 2021 18:03:24 +0000 Subject: [PATCH 45/81] Wrap arg_size for call instructions Build fix after: https://reviews.llvm.org/rGb2ee408dde374d6a27a34746fd7c7b5bab97ea89 --- GenXIntrinsics/include/llvmVCWrapper/IR/InstrTypes.h | 10 ++++++++++ .../lib/GenXIntrinsics/GenXSimdCFLowering.cpp | 8 ++++---- 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/GenXIntrinsics/include/llvmVCWrapper/IR/InstrTypes.h b/GenXIntrinsics/include/llvmVCWrapper/IR/InstrTypes.h index c8a6901b..aa58235d 100644 --- a/GenXIntrinsics/include/llvmVCWrapper/IR/InstrTypes.h +++ b/GenXIntrinsics/include/llvmVCWrapper/IR/InstrTypes.h @@ -17,6 +17,16 @@ using llvm::TerminatorInst; #elif VC_INTR_LLVM_VERSION_MAJOR >= 8 using TerminatorInst = llvm::Instruction; #endif + +namespace CallBase { +template unsigned arg_size(const CBTy &CB) { +#if VC_INTR_LLVM_VERSION_MAJOR <= 7 + return CB.getNumArgOperands(); +#else + return CB.arg_size(); +#endif +} +} // namespace CallBase } // namespace VCINTR #endif // VCINTR_IR_INSTRTYPES_H diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSimdCFLowering.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSimdCFLowering.cpp index 2aaf1554..70c4aa8d 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSimdCFLowering.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSimdCFLowering.cpp @@ -1078,7 +1078,7 @@ void CMSimdCFLower::predicateInst(Instruction *Inst, unsigned SimdWidth) { return; } // An IntrNoMem intrinsic is an ALU intrinsic and can be ignored. - if (Callee->doesNotAccessMemory() || CI->getNumArgOperands() == 0) + if (Callee->doesNotAccessMemory() || VCINTR::CallBase::arg_size(*CI) == 0) return; // no predication for intrinsic marked as ISPC uniform, // for example, atomic and oword_store used in printf @@ -1086,7 +1086,7 @@ void CMSimdCFLower::predicateInst(Instruction *Inst, unsigned SimdWidth) { return; // Look for a predicate operand in operand 2, 1 or 0. - unsigned PredNum = CI->getNumArgOperands() - 1; + unsigned PredNum = VCINTR::CallBase::arg_size(*CI) - 1; for (;;) { if (auto VT = dyn_cast(CI->getArgOperand(PredNum)->getType())) { @@ -1446,7 +1446,7 @@ void CMSimdCFLower::predicateSend(CallInst *CI, unsigned IntrinsicID, break; } SmallVector Args; - for (unsigned i = 0, e = CI->getNumArgOperands(); i != e; ++i) + for (unsigned i = 0, e = VCINTR::CallBase::arg_size(*CI); i != e; ++i) if (i == PredOperandNum) Args.push_back(Pred); else @@ -1507,7 +1507,7 @@ CallInst *CMSimdCFLower::predicateWrRegion(CallInst *WrR, unsigned SimdWidth) { // First gather the args of the original wrregion. SmallVector Args; - for (unsigned i = 0, e = WrR->getNumArgOperands(); i != e; ++i) + for (unsigned i = 0, e = VCINTR::CallBase::arg_size(*WrR); i != e; ++i) Args.push_back(WrR->getArgOperand(i)); // Modify the predicate in Args. Value *Pred = Args[GenXIntrinsic::GenXRegion::PredicateOperandNum]; From d6d08b3b02af08ed4cd78029f5eee806ede657c7 Mon Sep 17 00:00:00 2001 From: Aleksander Us Date: Tue, 19 Oct 2021 13:00:16 +0000 Subject: [PATCH 46/81] Bump minimum supported LLVM version to 8 --- Readme.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Readme.md b/Readme.md index fd9e186c..cc385d7c 100644 --- a/Readme.md +++ b/Readme.md @@ -53,7 +53,7 @@ To build documentation: ## Building VC Intrinsics can be built in two major modes: in-tree and -external. All major LLVM versions starting from LLVM 7 are supported. +external. All major LLVM versions starting from LLVM 8 are supported. LLVM ToT can be used too, but there is no guarantee that it will always work (because of sudden breaking changes in LLVM C++ From ed60a79bc552c1fb81b1e9251ba0d235237635cd Mon Sep 17 00:00:00 2001 From: Stanislav Sidelnikov Date: Mon, 25 Oct 2021 11:19:30 +0000 Subject: [PATCH 47/81] Updating source files permissions Removed executuion bit in sources --- GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsicInst.h | 0 GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h | 0 GenXIntrinsics/include/llvm/GenXIntrinsics/GenXMetadata.h | 0 .../include/llvm/GenXIntrinsics/GenXSPIRVReaderAdaptor.h | 0 .../include/llvm/GenXIntrinsics/GenXSPIRVWriterAdaptor.h | 0 GenXIntrinsics/include/llvmVCWrapper/IR/Instructions.h | 0 GenXIntrinsics/include/llvmVCWrapper/Support/Alignment.h | 0 GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp | 0 GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp | 0 GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp | 0 GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp | 0 GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.h | 0 12 files changed, 0 insertions(+), 0 deletions(-) mode change 100755 => 100644 GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsicInst.h mode change 100755 => 100644 GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h mode change 100755 => 100644 GenXIntrinsics/include/llvm/GenXIntrinsics/GenXMetadata.h mode change 100755 => 100644 GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSPIRVReaderAdaptor.h mode change 100755 => 100644 GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSPIRVWriterAdaptor.h mode change 100755 => 100644 GenXIntrinsics/include/llvmVCWrapper/IR/Instructions.h mode change 100755 => 100644 GenXIntrinsics/include/llvmVCWrapper/Support/Alignment.h mode change 100755 => 100644 GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp mode change 100755 => 100644 GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp mode change 100755 => 100644 GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp mode change 100755 => 100644 GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp mode change 100755 => 100644 GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.h diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsicInst.h b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsicInst.h old mode 100755 new mode 100644 diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h old mode 100755 new mode 100644 diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXMetadata.h b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXMetadata.h old mode 100755 new mode 100644 diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSPIRVReaderAdaptor.h b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSPIRVReaderAdaptor.h old mode 100755 new mode 100644 diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSPIRVWriterAdaptor.h b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSPIRVWriterAdaptor.h old mode 100755 new mode 100644 diff --git a/GenXIntrinsics/include/llvmVCWrapper/IR/Instructions.h b/GenXIntrinsics/include/llvmVCWrapper/IR/Instructions.h old mode 100755 new mode 100644 diff --git a/GenXIntrinsics/include/llvmVCWrapper/Support/Alignment.h b/GenXIntrinsics/include/llvmVCWrapper/Support/Alignment.h old mode 100755 new mode 100644 diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp old mode 100755 new mode 100644 diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp old mode 100755 new mode 100644 diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp old mode 100755 new mode 100644 diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp old mode 100755 new mode 100644 diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.h b/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.h old mode 100755 new mode 100644 From c6e0c45edd7d8234ea271b0cbf11126dd5f3404b Mon Sep 17 00:00:00 2001 From: Aleksander Us Date: Wed, 27 Oct 2021 21:36:00 +0000 Subject: [PATCH 48/81] Normalize ifs in cmake code Normalize ifs in cmake code --- CMakeLists.txt | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 675fe5b4..a3e3f678 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -16,7 +16,7 @@ set(LLVM_GENX_INTRINSICS_ROOT_DIR ${CMAKE_CURRENT_SOURCE_DIR}) if(CMAKE_SOURCE_DIR STREQUAL CMAKE_CURRENT_SOURCE_DIR) get_filename_component(LLVM_CMAKE_PATH ${LLVM_DIR} ABSOLUTE BASE_DIR ${CMAKE_BINARY_DIR}) set(BUILD_EXTERNAL YES) - if (NOT DEFINED INSTALL_REQUIRED) + if(NOT DEFINED INSTALL_REQUIRED) set(INSTALL_REQUIRED YES) endif() project(LLVM_GenXIntrinsics @@ -46,20 +46,20 @@ else(CMAKE_SOURCE_DIR STREQUAL CMAKE_CURRENT_SOURCE_DIR) # LLVM_CMAKE_DIR is not set for non-standalone builds. Use LLVM_CMAKE_PATH # instead. (see clang/CMakeLists.txt) - if (NOT LLVM_CMAKE_DIR) + if(NOT LLVM_CMAKE_DIR) set(LLVM_CMAKE_DIR ${LLVM_CMAKE_PATH}) endif() endif(CMAKE_SOURCE_DIR STREQUAL CMAKE_CURRENT_SOURCE_DIR) include(FindPythonInterp) -if( NOT PYTHONINTERP_FOUND ) +if(NOT PYTHONINTERP_FOUND) message(FATAL_ERROR "Unable to find Python interpreter, required for builds and testing. Please install Python or specify the PYTHON_EXECUTABLE CMake variable.") endif() -if( "${PYTHON_VERSION_STRING}" VERSION_LESS 2.7 ) +if("${PYTHON_VERSION_STRING}" VERSION_LESS 2.7) message(FATAL_ERROR "Python 2.7 or newer is required") endif() From 4f460713c90662e20a56840d48466aeb18c9ef81 Mon Sep 17 00:00:00 2001 From: DmitryBushev Date: Tue, 12 Oct 2021 15:08:20 +0000 Subject: [PATCH 49/81] Fixed SPIRVWriterAdaptor pass not adding attribute on address convert intrinsic SPIRVWriterAdaptor pass may add llvm.genx.address_convert intrinsics. Doing so it must explicitly add VCFunction attribute to newly created intrinsics. --- .../GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp | 1 + .../Adaptors/addr_conv_attribute_writer.ll | 34 +++++++++++++++++++ 2 files changed, 35 insertions(+) create mode 100644 GenXIntrinsics/test/Adaptors/addr_conv_attribute_writer.ll diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp index 4e1bcfab..20ffa788 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp @@ -233,6 +233,7 @@ static Instruction *rewriteArgumentUses(Argument &OldArg, Argument &NewArg) { Module *M = OldArg.getParent()->getParent(); Function *ConvFn = GenXIntrinsic::getGenXDeclaration( M, GenXIntrinsic::genx_address_convert, {OldTy, NewTy}); + ConvFn->addFnAttr(VCFunctionMD::VCFunction); auto *Conv = CallInst::Create(ConvFn, {&NewArg}); OldArg.replaceAllUsesWith(Conv); return Conv; diff --git a/GenXIntrinsics/test/Adaptors/addr_conv_attribute_writer.ll b/GenXIntrinsics/test/Adaptors/addr_conv_attribute_writer.ll new file mode 100644 index 00000000..62b1ccb1 --- /dev/null +++ b/GenXIntrinsics/test/Adaptors/addr_conv_attribute_writer.ll @@ -0,0 +1,34 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2021-2021 Intel Corporation +; +; SPDX-License-Identifier: MIT +; +;============================ end_copyright_notice ============================= + +; Test @llvm.genx.address.convert intrinsic generation with proper attributes + +; RUN: opt -S -GenXSPIRVWriterAdaptor < %s | FileCheck %s + +define void @test(i32 %buf) { +; CHECK-LABEL: @test( +; CHECK: %intel.buffer_rw_t addrspace(1)* +; CHECK: [[BUF:%[^,]+]]) +; CHECK-NEXT: entry: +; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.genx.address.convert.i32.p1intel.buffer_rw_t(%intel.buffer_rw_t addrspace(1)* [[BUF]]) +; CHECK-NEXT: ret void +; +entry: + ret void +} + +; CHECK: declare !genx_intrinsic_id !{{[0-9]+}} i32 @llvm.genx.address.convert.i32.p1intel.buffer_rw_t(%intel.buffer_rw_t addrspace(1)*) #[[ATTRS:[0-9]+]] +!genx.kernels = !{!0} + +; CHECK: attributes #[[ATTRS]] +; CHECK-SAME: "VCFunction" + +!0 = !{void (i32)* @test, !"test", !1, i32 0, i32 0, !2, !3, i32 0, i32 0} +!1 = !{i32 2} +!2 = !{i32 0} +!3 = !{!"buffer_t"} From 8ee879314584e6630688b0a3b290d065dcabb383 Mon Sep 17 00:00:00 2001 From: Konstantin Vladimirov Date: Tue, 2 Nov 2021 10:08:40 +0000 Subject: [PATCH 50/81] Introducing VC intrinsics interface for DG2 and PVC platforms A number of new intrinsics introduced --- .../llvm/GenXIntrinsics/GenXIntrinsics.h | 332 +++++++++++++ .../llvm/GenXIntrinsics/GenXMetadata.h | 3 +- .../GenXIntrinsics/Intrinsic_definitions.py | 458 ++++++++++++++++++ .../include/llvm/GenXIntrinsics/Intrinsics.py | 3 +- .../lib/GenXIntrinsics/GenXIntrinsics.cpp | 93 ++++ .../GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp | 14 +- .../lib/GenXIntrinsics/GenXSimdCFLowering.cpp | 11 + 7 files changed, 910 insertions(+), 4 deletions(-) diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h index 50efc3d7..c018ba00 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h @@ -47,6 +47,49 @@ namespace GenXResult { }; } +// The number of elements to load per address (vector size) +// NOTE: taken from cmc/support +enum class LSCVectorSize : uint8_t { + N0 = 0, + N1 = 1, // 1 element + N2 = 2, // 2 element + N3 = 3, // 3 element + N4 = 4, // 4 element + N8 = 5, // 8 element + N16 = 6, // 16 element + N32 = 7, // 32 element + N64 = 8 // 64 element +}; + +enum class LSCDataSize : uint8_t { + Invalid, + D8, + D16, + D32, + D64, + D8U32, + D16U32, + D16U32H, +}; + +enum class LSCDataOrder : uint8_t { + Invalid, + NonTranspose, + Transpose +}; + +enum class LSCCategory : uint8_t { + Load, + Load2D, + Prefetch, + Prefetch2D, + Store, + Store2D, + Fence, + LegacyAtomic, + Atomic, + NotLSC +}; namespace GenXRegion { enum { @@ -412,6 +455,295 @@ inline bool isReadWritePredefReg(const Function *F) { isReadPredefReg(getGenXIntrinsicID(F)); } +inline LSCCategory getLSCCategory(unsigned IntrinID) { + switch(IntrinID) { + case GenXIntrinsic::genx_lsc_load_bti: + case GenXIntrinsic::genx_lsc_load_stateless: + case GenXIntrinsic::genx_lsc_load_slm: + case GenXIntrinsic::genx_lsc_load_bindless: + case GenXIntrinsic::genx_lsc_load_quad_bti: + case GenXIntrinsic::genx_lsc_load_quad_slm: + case GenXIntrinsic::genx_lsc_load_quad_stateless: + return LSCCategory::Load; + case GenXIntrinsic::genx_lsc_load2d_stateless: + return LSCCategory::Load2D; + case GenXIntrinsic::genx_lsc_prefetch_bti: + case GenXIntrinsic::genx_lsc_prefetch_stateless: + return LSCCategory::Prefetch; + case GenXIntrinsic::genx_lsc_prefetch2d_stateless: + return LSCCategory::Prefetch2D; + case GenXIntrinsic::genx_lsc_store_bti: + case GenXIntrinsic::genx_lsc_store_stateless: + case GenXIntrinsic::genx_lsc_store_slm: + case GenXIntrinsic::genx_lsc_store_bindless: + case GenXIntrinsic::genx_lsc_store_quad_bti: + case GenXIntrinsic::genx_lsc_store_quad_slm: + case GenXIntrinsic::genx_lsc_store_quad_stateless: + return LSCCategory::Store; + case GenXIntrinsic::genx_lsc_store2d_stateless: + return LSCCategory::Store2D; + case GenXIntrinsic::genx_lsc_fence: + return LSCCategory::Fence; + case GenXIntrinsic::genx_lsc_atomic_bti: + case GenXIntrinsic::genx_lsc_atomic_stateless: + case GenXIntrinsic::genx_lsc_atomic_slm: + case GenXIntrinsic::genx_lsc_atomic_bindless: + return LSCCategory::LegacyAtomic; + case GenXIntrinsic::genx_lsc_xatomic_bti: + case GenXIntrinsic::genx_lsc_xatomic_stateless: + case GenXIntrinsic::genx_lsc_xatomic_slm: + case GenXIntrinsic::genx_lsc_xatomic_bindless: + return LSCCategory::Atomic; + default: + return LSCCategory::NotLSC; + } +} + +inline LSCCategory getLSCCategory(const Value *V) { + return getLSCCategory(getGenXIntrinsicID(V)); +} + +inline LSCCategory getLSCCategory(const Function *F) { + return getLSCCategory(getGenXIntrinsicID(F)); +} + +inline bool isLSCLoad(unsigned IntrinID) { + return getLSCCategory(IntrinID) == LSCCategory::Load; +} + +inline bool isLSCLoad(const Value *V) { + return isLSCLoad(getGenXIntrinsicID(V)); +} + +inline bool isLSCLoad(const Function *F) { + return isLSCLoad(getGenXIntrinsicID(F)); +} + +inline bool isLSCLoad2D(unsigned IntrinID) { + return getLSCCategory(IntrinID) == LSCCategory::Load2D; +} + +inline bool isLSCLoad2D(const Value *V) { + return isLSCLoad2D(getGenXIntrinsicID(V)); +} + +inline bool isLSCLoad2D(const Function *F) { + return isLSCLoad2D(getGenXIntrinsicID(F)); +} + + +inline bool isLSCPrefetch(unsigned IntrinID) { + return getLSCCategory(IntrinID) == LSCCategory::Prefetch; +} + +inline bool isLSCPrefetch(const Value *V) { + return isLSCPrefetch(getGenXIntrinsicID(V)); +} + +inline bool isLSCPrefetch(const Function *F) { + return isLSCPrefetch(getGenXIntrinsicID(F)); +} + +inline bool isLSCPrefetch2D(unsigned IntrinID) { + return getLSCCategory(IntrinID) == LSCCategory::Prefetch2D; +} + +inline bool isLSCPrefetch2D(const Value *V) { + return isLSCPrefetch2D(getGenXIntrinsicID(V)); +} + +inline bool isLSCPrefetch2D(const Function *F) { + return isLSCPrefetch2D(getGenXIntrinsicID(F)); +} + +inline bool isLSCStore(unsigned IntrinID) { + return getLSCCategory(IntrinID) == LSCCategory::Store; +} + +inline bool isLSCStore(const Value *V) { + return isLSCStore(getGenXIntrinsicID(V)); +} + +inline bool isLSCStore(const Function *F) { + return isLSCStore(getGenXIntrinsicID(F)); +} + +inline bool isLSCStore2D(unsigned IntrinID) { + return getLSCCategory(IntrinID) == LSCCategory::Store2D; +} + +inline bool isLSCStore2D(const Value *V) { + return isLSCStore2D(getGenXIntrinsicID(V)); +} + +inline bool isLSCStore2D(const Function *F) { + return isLSCStore2D(getGenXIntrinsicID(F)); +} + + +inline bool isLSCFence(unsigned IntrinID) { + return getLSCCategory(IntrinID) == LSCCategory::Fence; +} + +inline bool isLSCFence(const Value *V) { + return isLSCFence(getGenXIntrinsicID(V)); +} + +inline bool isLSCFence(const Function *F) { + return isLSCFence(getGenXIntrinsicID(F)); +} + +inline bool isLSCLegacyAtomic(unsigned IntrinID) { + return getLSCCategory(IntrinID) == LSCCategory::LegacyAtomic; +} + +inline bool isLSCLegacyAtomic(const Value *V) { + return isLSCLegacyAtomic(getGenXIntrinsicID(V)); +} + +inline bool isLSCLegacyAtomic(const Function *F) { + return isLSCLegacyAtomic(getGenXIntrinsicID(F)); +} + +inline bool isLSCAtomic(unsigned IntrinID) { + return getLSCCategory(IntrinID) == LSCCategory::Atomic; +} + +inline bool isLSCAtomic(const Value *V) { + return isLSCAtomic(getGenXIntrinsicID(V)); +} + +inline bool isLSCAtomic(const Function *F) { + return isLSCAtomic(getGenXIntrinsicID(F)); +} + +inline bool isLSC(unsigned IntrinID) { + return getLSCCategory(IntrinID) != LSCCategory::NotLSC; +} + +inline bool isLSC(const Value *V) { + return isLSC(getGenXIntrinsicID(V)); +} + +inline bool isLSC(const Function *F) { + return isLSC(getGenXIntrinsicID(F)); +} + +inline bool isLSC2D(unsigned IntrinID) { + switch (getLSCCategory(IntrinID)) { + case LSCCategory::Load2D: + case LSCCategory::Prefetch2D: + case LSCCategory::Store2D: + return true; + case LSCCategory::Load: + case LSCCategory::Prefetch: + case LSCCategory::Store: + case LSCCategory::Fence: + case LSCCategory::LegacyAtomic: + case LSCCategory::Atomic: + case LSCCategory::NotLSC: + return false; + } + llvm_unreachable("Unknown LSC category"); +} + +inline bool isLSC2D(const Value *V) { + return isLSC2D(getGenXIntrinsicID(V)); +} + +inline bool isLSC2D(const Function *F) { + return isLSC2D(getGenXIntrinsicID(F)); +} + +inline unsigned getLSCNumVectorElements(LSCVectorSize VS) { + switch (VS) { + case LSCVectorSize::N0: + break; + case LSCVectorSize::N1: + return 1; + case LSCVectorSize::N2: + return 2; + case LSCVectorSize::N3: + return 3; + case LSCVectorSize::N4: + return 4; + case LSCVectorSize::N8: + return 8; + case LSCVectorSize::N16: + return 16; + case LSCVectorSize::N32: + return 32; + case LSCVectorSize::N64: + return 64; + } + llvm_unreachable("Unknown vector size"); +} + +LSCVectorSize getLSCVectorSize(const Instruction *I); + +inline unsigned getLSCNumVectorElements(const Instruction *I) { + return GenXIntrinsic::getLSCNumVectorElements(getLSCVectorSize(I)); +} + +inline unsigned getLSCDataBitsRegister(LSCDataSize DS) { + switch(DS) { + case LSCDataSize::Invalid: + break; + case LSCDataSize::D8: + return 8; + case LSCDataSize::D16: + return 16; + case LSCDataSize::D32: + case LSCDataSize::D8U32: + case LSCDataSize::D16U32: + case LSCDataSize::D16U32H: + return 32; + case LSCDataSize::D64: + return 64; + } + llvm_unreachable("Unknown data size"); +} + +inline unsigned getLSCDataBitsMemory(LSCDataSize DS) { + switch(DS) { + case LSCDataSize::Invalid: + break; + case LSCDataSize::D8: + case LSCDataSize::D8U32: + return 8; + case LSCDataSize::D16: + case LSCDataSize::D16U32: + case LSCDataSize::D16U32H: + return 16; + case LSCDataSize::D32: + return 32; + case LSCDataSize::D64: + return 64; + } + llvm_unreachable("Unknown data size"); +} + +LSCDataSize getLSCDataSize(const Instruction *I); + +inline unsigned getLSCDataBitsRegister(const Instruction *I) { + return getLSCDataBitsRegister(getLSCDataSize(I)); +} + +inline unsigned getLSCDataBitsMemory(const Instruction *I) { + return getLSCDataBitsMemory(getLSCDataSize(I)); +} + +LSCDataOrder getLSCDataOrder(const Instruction *I); + +inline bool isLSCNonTransposed(const Instruction *I) { + return getLSCDataOrder(I) == LSCDataOrder::NonTranspose; +} + +inline bool isLSCTransposed(const Instruction *I) { + return getLSCDataOrder(I) == LSCDataOrder::Transpose; +} + +unsigned getLSCWidth(const Instruction *I); } // namespace GenXIntrinsic diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXMetadata.h b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXMetadata.h index 58b4d483..55dd332c 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXMetadata.h +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXMetadata.h @@ -52,6 +52,7 @@ static constexpr const char VCSLMSize[] = "VCSLMSize"; static constexpr const char VCArgumentKind[] = "VCArgumentKind"; static constexpr const char VCArgumentDesc[] = "VCArgumentDesc"; static constexpr const char VCSIMTCall[] = "VCSIMTCall"; +static constexpr const char VCNamedBarrierCount[] = "VCNamedBarrierCount"; } // namespace VCFunctionMD enum KernelMDOp { @@ -63,7 +64,7 @@ enum KernelMDOp { ArgIOKinds, // Reference to metadata node containing kernel argument // input/output kinds ArgTypeDescs, // Kernel argument type descriptors - Reserved_0, + NBarrierCnt, // Named barrier count BarrierCnt // Barrier count }; diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py index 53eacb01..16588c1c 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py @@ -1791,6 +1791,21 @@ "attributes" : "NoMem" }, +### srnd +### ^^^ +### +### ``llvm.genx.srnd...`` : srnd instruction +### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +### * ``llvm.genx.srnd`` : +### +### * arg0: first input, any vector f32/hf16 type +### * arg1: second input, same type as arg0 +### * Return value: result, must be half if arg0 is f32, or ub if arg0 is half. + "srnd" : { "result" : "anyvector", + "arguments" : ["anyvector", "anyvector"], + "attributes" : "NoMem" + }, + ### bf_cvt ### ^^^^^^ ### @@ -1807,6 +1822,404 @@ "attributes" : "NoMem" }, +### tf32_cvt +### ^^^^^^ +### +### ``llvm.genx.tf32.cvt..`` : tf32_cvt instruction +### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +### * ``llvm.genx.tf32.cvt`` : +### +### * arg0: first input, vector float type fp32/hf16 +### +### * Return value: result, must be ud( Unsigned Doubleword) +### + "tf32_cvt" : { "result" : "anyvector", + "arguments" : ["anyvector"], + "attributes" : "NoMem" + }, + +### qf_cvt +### ^^^^^^ +### +### ``llvm.genx.qf.cvt..`` : qf_cvt instruction +### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +### * ``llvm.genx.qf.cvt`` : +### +### * arg0: first input, any scalar/vector i8/half type (overloaded) +### +### * Return value: result, must be i8 if arg0 is half, or half if arg0 is i8. +### + "qf_cvt" : { "result" : "anyvector", + "arguments" : ["anyvector"], + "attributes" : "NoMem" + }, + +### ``llvm.genx.lsc.load.*...`` : lsc_load instructions +### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +### +### * ``llvm.genx.lsc.load.slm`` : +### * ``llvm.genx.lsc.load.bti`` : +### * ``llvm.genx.lsc.load.stateless`` : +### * ``llvm.genx.lsc.prefetch.bti`` : +### * ``llvm.genx.lsc.prefetch.stateless`` : +### +### * Exec_size ignored unless operation is transposed (DataOrder == Tranpose) +### * arg0: {1,32}Xi1 predicate (overloaded) +### * arg1: i8 Subopcode, [MBZ] +### * arg2: i8 Caching behavior for L1, [MBC] +### * arg3: i8 Caching behavior for L3, [MBC] +### * arg4: i16 Address scale, [MBC] +### * arg5: i32 Immediate offset added to each address, [MBC] +### * arg6: i8 The dataum size, [MBC] +### * arg7: i8 Number of elements to load per address (vector size), [MBC] +### * arg8: i8 Indicates if the data is transposed during the transfer, [MBC] +### * arg9: i8 Channel mask for quad versions, [MBC] +### * arg10: {1,32}Xi{16,32,64} The vector register holding offsets (overloaded) +### for flat version Base Address + Offset[i] goes here +### * arg11: i32 surface to use for this operation. This can be an immediate or a register +### for flat and bindless version pass zero here +### +### * Return value: the value read or void for prefetch +### +### Cache mappings are: +### +### - 0 -> .df (default) +### - 1 -> .uc (uncached) +### - 2 -> .wb (writeback) +### - 3 -> .wt (writethrough) +### - 4 -> .st (streaming) +### - 5 -> .ri (read-invalidate) +### +### Only certain combinations of CachingL1 with CachingL3 are valid on hardware. +### +### +---------+-----+-----------------------------------------------------------------------+ +### | L1 | L3 | Notes | +### +---------+-----+-----------------------------------------------------------------------+ +### | .df | .df | default behavior on both L1 and L3 (L3 uses MOCS settings) | +### +---------+-----+-----------------------------------------------------------------------+ +### | .ri/.wb | .wb | read-invalidate on reads (e.g. last use) / writeback on Stores for L1 | +### +---------+-----+-----------------------------------------------------------------------+ +### | .uc | .uc | uncached (bypass) both L1 and L3 | +### +---------+-----+-----------------------------------------------------------------------+ +### | .uc | .wb | bypass L1 / writeback L3 | +### +---------+-----+-----------------------------------------------------------------------+ +### | .wt | .uc | writethrough L1 / bypass L3 | +### +---------+-----+-----------------------------------------------------------------------+ +### | .wt | .wb | writethrough L1 / writeback L3 | +### +---------+-----+-----------------------------------------------------------------------+ +### | .st | .uc | streaming L1 / bypass L3 | +### +---------+-----+-----------------------------------------------------------------------+ +### | .st | .wb | streaming L1 / writeback L3 | +### +---------+-----+-----------------------------------------------------------------------+ +### +### Immediate offset. The compiler may be able to fuse this add into the message, otherwise +### additional instructions are generated to honor the semantics. +### +### Dataum size mapping is +### +### - 1 = :u8 +### - 2 = :u16 +### - 3 = :u32 +### - 4 = :u64 +### - 5 = :u8u32 (load 8b, zero extend to 32b; store the opposite), +### - 6 = :u16u32 (load 8b, zero extend to 32b; store the opposite), +### - 7 = :u16u32h (load 16b into high 16 of each 32b; store the high 16) +### + "lsc_load_slm" : { "result" : "anyvector", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","any","int"], + "attributes" : "ReadMem" + }, + "lsc_load_stateless" : { "result" : "anyvector", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","any","int"], + "attributes" : "ReadMem" + }, + "lsc_load_bindless" : { "result" : "anyvector", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","any","int"], + "attributes" : "ReadMem" + }, + "lsc_load_bti" : { "result" : "anyvector", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","any","int"], + "attributes" : "ReadMem" + }, + "lsc_prefetch_slm" : { "result" : "void", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","any","int"], + "attributes" : "None" + }, + "lsc_prefetch_bti" : { "result" : "void", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","any","int"], + "attributes" : "None" + }, + "lsc_prefetch_stateless" : { "result" : "void", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","any","int"], + "attributes" : "None" + }, + "lsc_prefetch_bindless" : { "result" : "void", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","any","int"], + "attributes" : "None" + }, + "lsc_load_quad_slm" : { "result" : "anyvector", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","any","int"], + "attributes" : "ReadMem" + }, + "lsc_load_quad_stateless" : { "result" : "anyvector", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","any","int"], + "attributes" : "ReadMem" + }, + "lsc_load_quad_bindless" : { "result" : "anyvector", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","any","int"], + "attributes" : "ReadMem" + }, + "lsc_load_quad_bti" : { "result" : "anyvector", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","any","int"], + "attributes" : "ReadMem" + }, + +### ``llvm.genx.lsc.store.*...`` : lsc_store instructions +### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +### +### * ``llvm.genx.lsc.store.slm`` : +### * ``llvm.genx.lsc.store.bti`` : +### * ``llvm.genx.lsc.store.stateless`` : +### +### * Exec_size ignored unless operation is transposed (DataOrder == Tranpose) +### * arg0: {1,32}Xi1 predicate(overloaded) +### * arg1: i8 Subopcode, [MBZ] +### * arg2: i8 Caching behavior for L1, [MBC] +### * arg3: i8 Caching behavior for L3, [MBC] +### * arg4: i16 Address scale, [MBC] +### * arg5: {1,32}Xi32 Immediate offset added to each address, [MBC] +### * arg6: i8 The dataum size, [MBC] +### * arg7: i8 Number of elements to load per address (vector size), [MBC] +### * arg8: i8 Indicates if the data is transposed during the transfer, [MBC] +### * arg9: i8 Channel mask for quad version, [MBC] +### * arg10: {1,32}Xi{16,32,64} The vector register holding offsets (overloaded) +### for flat version Base Address + Offset[i] goes here +### * arg11: VXi{16,32,64} The data to write (overloaded) +### * arg12: i32 surface to use for this operation. This can be an immediate or a register +### for flat and bindless version pass zero here +### +### * Return value: void +### + "lsc_store_slm" : { "result" : "void", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","any","anyvector","int"], + "attributes" : "None" + }, + "lsc_store_stateless" : { "result" : "void", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","any","anyvector","int"], + "attributes" : "None" + }, + "lsc_store_bindless" : { "result" : "void", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","any","anyvector","int"], + "attributes" : "None" + }, + "lsc_store_bti" : { "result" : "void", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","any","anyvector","int"], + "attributes" : "None" + }, + "lsc_store_quad_slm" : { "result" : "void", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","any","anyvector","int"], + "attributes" : "None" + }, + "lsc_store_quad_stateless" : { "result" : "void", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","any","anyvector","int"], + "attributes" : "None" + }, + "lsc_store_quad_bindless" : { "result" : "void", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","any","anyvector","int"], + "attributes" : "None" + }, + "lsc_store_quad_bti" : { "result" : "void", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","any","anyvector","int"], + "attributes" : "None" + }, + +### ``llvm.genx.lsc.*2d.stateless.[return type]..
`` : 2d stateless load/prefecth instructions +### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +### +### * ``llvm.genx.lsc.load2d.stateless...
`` : +### * ``llvm.genx.lsc.prefetch2d.stateless..
`` : +### +### * Exec_size ignored unless operation is transposed (DataOrder == Tranpose) +### * arg0: {1,32}Xi1 predicate (overloaded) +### * arg1: i8 Caching behavior for L1, [MBC] +### * arg2: i8 Caching behavior for L3, [MBC] +### * arg3: i8 The dataum size, [MBC] +### * arg4: i8 Indicates if the data is transposed during the transfer, [MBC] +### * arg5: i8 number of blocks, [MBC] +### * arg6: i32 BlockWidth, [MBC] +### * arg7: i32 BlockHeight, [MBC] +### * arg8: i8 VNNI. This performs a VNNI transform during the access. +### * arg9: i32/i64 surface base address for this operation. +### * arg10: i32 surface width minus 1. +### * arg11: i32 surface height minus 1. +### * arg12: i32 surface pitch minus 1. +### * arg13: i32 Src0AddrX, the base X position of the 2D region to load or store. +### * arg14: i32 Src0AddrY, the base Y position of the 2D region to load or store. +### +### * Return value: the value read or void for prefetch +### + "lsc_load2d_stateless" : { "result" : "anyvector", + "arguments" : ["anyvector","char","char","char","char","char","short","short","char","anyint","int","int","int","int","int"], + "attributes" : "ReadMem" + }, + "lsc_prefetch2d_stateless" : { "result" : "void", + "arguments" : ["anyvector","char","char","char","char","char","short","short","char","anyint","int","int","int","int","int"], + "attributes" : "None" + }, + +## ``llvm.genx.lsc.store2d.stateless..
.`` : 2d stateless store +### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +### +### * Exec_size ignored unless operation is transposed (DataOrder == Tranpose) +### * arg0: {1,32}Xi1 predicate (overloaded) +### * arg1: i8 Caching behavior for L1, [MBC] +### * arg2: i8 Caching behavior for L3, [MBC] +### * arg3: i8 The dataum size, [MBC] +### * arg4: i8 Indicates if the data is transposed during the transfer, [MBC] +### * arg5: i8 number of blocks, [MBC] +### * arg7: i32 BlockWidth, [MBC] +### * arg6: i32 BlockHeight, [MBC] +### * arg8: i8 VNNI. This performs a VNNI transform during the access. +### * arg9: i32/i64 surface base address for this operation. +### * arg10: i32 surface width minus 1. +### * arg11: i32 surface height minus 1. +### * arg12: i32 surface pitch minus 1. +### * arg13: i32 Src0AddrX, the base X position of the 2D region to load or store. +### * arg14: i32 Src0AddrY, the base Y position of the 2D region to load or store. +### * arg15: data to write (overloaded) +### +### * Return value: void +### + "lsc_store2d_stateless" : { "result" : "void", + "arguments" : ["anyvector","char","char","char","char","char","short","short","char","anyint","int","int","int","int","int","anyvector"], + "attributes" : "None" + }, + + +### ``llvm.genx.lsc.atomic.*...`` : lsc_atomic instructions +### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +### +### !!! Those are legacy ones! Use xatomic version instead !!! +### +### * ``llvm.genx.lsc.atomic.bti`` : +### * ``llvm.genx.lsc.atomic.slm`` : +### * ``llvm.genx.lsc.atomic.slateless`` : +### +### * arg0: {1,32}Xi1 predicate (overloaded) +### * arg1: i8 Subopcode, [MBZ] +### * arg2: i8 Caching behavior for L1, [MBC] +### * arg3: i8 Caching behavior for L3, [MBC] +### * arg4: i16 Address scale, [MBC] +### * arg5: {1,32}Xi32 Immediate offset added to each address, [MBC] +### * arg6: i8 The dataum size, [MBC] +### * arg7: i8 Indicates if the data is transposed during the transfer, [MBC] +### * arg8: i8 Number of elements to load per address (vector size), [MBC] +### * arg9: i8 Channel mask, currently ignored, [MBC]. +### * arg10: i32/i64 surface base address for this operation. +### * arg11: {1,32}Xi{16,32,64} The vector register holding addresses. (overloaded) +### * arg12: i32 {1,32}Xi32 Src0 or undef (same vector size as predicate) +### * arg13: i32 {1,32}Xi32 Src1 or undef (same vector size as predicate) +### * arg14: i32 {1,32}Xi32 Old value of destination (same vector size as predicate), now always undef +### + "lsc_atomic_bti" : { "result" : "any", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","int","anyvector",0,0,0], + "attributes" : "None" + }, + "lsc_atomic_slm" : { "result" : "any", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","int","anyvector",0,0,0], + "attributes" : "None" + }, + "lsc_atomic_stateless" : { "result" : "any", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","int","anyvector",0,0,0], + "attributes" : "None" + }, + "lsc_atomic_bindless" : { "result" : "any", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","int","anyvector",0,0,0], + "attributes" : "None" + }, + +### ``llvm.genx.lsc.xatomic.*...`` : lsc_atomic instructions +### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +### +### * ``llvm.genx.lsc.xatomic.bti`` : +### * ``llvm.genx.lsc.xatomic.slm`` : +### * ``llvm.genx.lsc.xatomic.slateless`` : +### * ``llvm.genx.lsc.xatomic.bindless`` : +### +### * arg0: {1,32}Xi1 predicate (overloaded) +### * arg1: i8 Subopcode, [MBZ] +### * arg2: i8 Caching behavior for L1, [MBC] +### * arg3: i8 Caching behavior for L3, [MBC] +### * arg4: i16 Address scale, [MBC] +### * arg5: {1,32}Xi32 Immediate offset added to each address, [MBC] +### * arg6: i8 Data size, [MBC] +### * arg7: i8 Number of elements to load per address (vector size), [MBC] +### * arg8: i8 Indicates if the data is transposed during the transfer, [MBC] +### * arg9: i8 Channel mask, currently ignored, [MBC] +### * arg10: {1,32}Xi{16,32,64} The vector register holding offsets (overloaded) +### for flat version Base Address + Offset[i] goes here +### * arg11: i32 {1,32}Xi32 Src0 or undef (same vector size as predicate) +### * arg12: i32 {1,32}Xi32 Src1 or undef (same vector size as predicate) +### * arg13: i32 surface to use for this operation. This can be an immediate or a register +### for flat and bindless version pass zero here +### * arg14: i32 {1,32}Xi32 Old value of destination (same vector size as predicate), now always undef +### + "lsc_xatomic_bti" : { "result" : "any", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","anyvector",0,0,"int",0], + "attributes" : "None" + }, + "lsc_xatomic_slm" : { "result" : "any", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","anyvector",0,0,"int",0], + "attributes" : "None" + }, + "lsc_xatomic_stateless" : { "result" : "any", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","anyvector",0,0,"int",0], + "attributes" : "None" + }, + "lsc_xatomic_bindless" : { "result" : "any", + "arguments" : ["any","char","char","char","short","int","char","char","char","char","anyvector",0,0,"int",0], + "attributes" : "None" + }, + +### ``llvm.genx.lsc.fence.`` : lsc_fence instruction +### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +### +### * ``llvm.genx.lsc.fence`` : +### +### * Exec_size ignored unless operation is transposed (DataOrder == Tranpose) +### * arg0: {1,32}Xi1 predicate (overloaded) +### * arg1: i8 SFID +### * arg2: i8 Fence operation +### * arg3: i8 Fence operation scope +### +### [2] Mappings are: +### 0 -> .ugm (unified global memory) +### 1 -> .ugml (low-bandwith untyped global memory) +### 2 -> .tgm (typed global memory) +### 3 -> .slm (shared local memory) +### +### [3] Mappings are: +### 0 -> .none (no operation) +### 1 -> .evict (dirty lines evicted and invalidated from L1) +### 2 -> .invalidate (invalidate all clean lines) +### 3 -> .discard (direct and clean lines are discarded w/o eviction) +### 4 -> .clean (dirty lines are written to memory, but retained in cache in clean state) +### 5 -> .flushl3 (flush only L3) +### +### [4] Mappings are: +### 0 -> .group (flush out to the threadgroup's scope) +### 1 -> .local (flush out to the local scope) +### 2 -> .tile (tile, flush out to several DSSs) +### 3 -> .gpu (entire GPU, flush out to the GPUs LLC) +### 4 -> .gpus (all GPUs in the system, flush out to memory shared by all GPUs) +### 5 -> .system (the entire system memory space) +### 6 -> .sysacq (the entire system memory space with system-acquire semantics) +### + "lsc_fence" : { "result" : "void", + "arguments" : ["anyvector","char","char","char"], + "attributes" : "None" + }, + ### xor ### ^^^ ### Intrinsic not needed; use LLVM IR Xor instruction @@ -2167,6 +2580,14 @@ "arguments" : ["anyvector","int","anyint",0,0], "attributes" : "None", }, + "dword_atomic_fadd" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0,0], + "attributes" : "None", + }, + "dword_atomic_fsub" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0,0], + "attributes" : "None", + }, ### ``llvm.genx.dword.atomic2.*...`` : dword atomic with fmin/fmax operation (variant with no oldval) ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2192,6 +2613,14 @@ "arguments" : ["anyvector","int","anyint",0], "attributes" : "None", }, + "dword_atomic2_fadd" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0], + "attributes" : "None", + }, + "dword_atomic2_fsub" : { "result" : "anyvector", + "arguments" : ["anyvector","int","anyint",0], + "attributes" : "None", + }, ### ``llvm.genx.dword.atomic.*..`` : dword atomic with inc/dec operation @@ -2420,6 +2849,14 @@ "arguments" : ["anyvector","int",0,"anyint",2,2,2], "attributes" : "None" }, + "typed_atomic_fadd" : { "result" : "anyvector", + "arguments" : ["anyvector","int",0,"anyint",2,2,2], + "attributes" : "None" + }, + "typed_atomic_fsub" : { "result" : "anyvector", + "arguments" : ["anyvector","int",0,"anyint",2,2,2], + "attributes" : "None" + }, ### ``llvm.genx.typed.atomic.*...`` : atomic typed with inc/dec operation ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3476,6 +3913,17 @@ "attributes" : "Convergent" }, +### ``llvm.genx.nbarrier`` : vISA NBARRIER instruction +### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +### +### * arg0: i8 signal flag, constant +### * arg1: i8 barrier id +### * arg2: i8 number of threads +### + "nbarrier" : { "result" : "void", + "arguments" : ["char","char","char"], + "attributes" : "Convergent" + }, ### ``llvm.genx.cache.flush`` : vISA CACHE_FLUSH instruction ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -4713,6 +5161,8 @@ ## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ## * ``llvm.genx.dword.atomic2.fmin.predef.surface`` : vISA DWORD_ATOMIC FMIN instruction ## * ``llvm.genx.dword.atomic2.fmax.predef.surface`` : vISA DWORD_ATOMIC FMAX instruction +## * ``llvm.genx.dword.atomic2.fadd.predef.surface`` : vISA DWORD_ATOMIC FADD instruction +## * ``llvm.genx.dword.atomic2.fsub.predef.surface`` : vISA DWORD_ATOMIC FSUB instruction ## ## * (Exec_size inferred from element offset type) ## * arg0: vXi1 predicate (overloaded) @@ -4733,6 +5183,14 @@ "arguments" : ["anyvector","anyptr","anyint",0], "attributes" : "None", }, + "dword_atomic2_fadd_predef_surface" : { "result" : "anyvector", + "arguments" : ["anyvector","anyptr","anyint",0], + "attributes" : "None", + }, + "dword_atomic2_fsub_predef_surface" : { "result" : "anyvector", + "arguments" : ["anyvector","anyptr","anyint",0], + "attributes" : "None", + }, ## ``llvm.genx.dword.atomic2.*.predef.surface`` : dword atomic with inc/dec operation with predefined surface ## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py index 21f1b1ff..caef9ba8 100755 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py @@ -79,7 +79,8 @@ # order does really matter. # It is used to define ordering between the respected platforms platform_list = ["HSW", "BDW", "CHV", "SKL", "BXT", "KBL", - "GLK", "CNL", "ICL", "ICLLP", "TGLLP", "RKL", "DG1", "XEHP"] + "GLK", "CNL", "ICL", "ICLLP", "TGLLP", "RKL", "DG1", + "XEHP", "DG2", "PVC", "PVCXT"] def getAttributeList(Attrs): """ diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp index 4958dd69..71c4ada7 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp @@ -684,3 +684,96 @@ std::string GenXIntrinsic::getAnyName(unsigned id, ArrayRef Tys) { return VCINTR::Intrinsic::getName((Intrinsic::ID)id, Tys); } +GenXIntrinsic::LSCVectorSize GenXIntrinsic::getLSCVectorSize( + const Instruction *I) { + assert(isLSC(I)); + switch (getLSCCategory(I)) { + case LSCCategory::Load: + case LSCCategory::Prefetch: + case LSCCategory::Store: + case LSCCategory::Atomic: + return static_cast( + cast(I->getOperand(7))->getZExtValue()); + case LSCCategory::LegacyAtomic: + return static_cast( + cast(I->getOperand(8))->getZExtValue()); + case LSCCategory::Fence: + case LSCCategory::Load2D: + case LSCCategory::Prefetch2D: + case LSCCategory::Store2D: + case LSCCategory::NotLSC: + return LSCVectorSize::N0; + } + llvm_unreachable("Unknown LSC category"); +} + +GenXIntrinsic::LSCDataSize GenXIntrinsic::getLSCDataSize( + const Instruction *I) { + assert(isLSC(I)); + switch (getLSCCategory(I)) { + case LSCCategory::Load: + case LSCCategory::Prefetch: + case LSCCategory::Store: + case LSCCategory::LegacyAtomic: + case LSCCategory::Atomic: + return static_cast( + cast(I->getOperand(6))->getZExtValue()); + case LSCCategory::Load2D: + case LSCCategory::Prefetch2D: + case LSCCategory::Store2D: + return static_cast( + cast(I->getOperand(3))->getZExtValue()); + case LSCCategory::Fence: + case LSCCategory::NotLSC: + return LSCDataSize::Invalid; + } + llvm_unreachable("Unknown LSC category"); +} + +GenXIntrinsic::LSCDataOrder GenXIntrinsic::getLSCDataOrder( + const Instruction *I) { + assert(isLSC(I)); + switch (getLSCCategory(I)) { + case LSCCategory::Load: + case LSCCategory::Prefetch: + case LSCCategory::Store: + case LSCCategory::Atomic: + return static_cast( + cast(I->getOperand(8))->getZExtValue()); + case LSCCategory::LegacyAtomic: + return static_cast( + cast(I->getOperand(7))->getZExtValue()); + case LSCCategory::Load2D: + case LSCCategory::Prefetch2D: + case LSCCategory::Store2D: + return static_cast( + cast(I->getOperand(4))->getZExtValue()); + case LSCCategory::Fence: + case LSCCategory::NotLSC: + return LSCDataOrder::Invalid; + } + llvm_unreachable("Unknown LSC category"); +} + +unsigned GenXIntrinsic::getLSCWidth(const Instruction *I) { + assert(isLSC(I)); + switch(getLSCCategory(I)) { + case LSCCategory::Load: + case LSCCategory::Prefetch: + case LSCCategory::Store: + case LSCCategory::Fence: + case LSCCategory::LegacyAtomic: + case LSCCategory::Atomic: { + case LSCCategory::Prefetch2D: + if (auto VT = dyn_cast(I->getOperand(0)->getType())) + return VCINTR::VectorType::getNumElements(VT); + return 1; + } + case LSCCategory::Load2D: + case LSCCategory::Store2D: + case LSCCategory::NotLSC: + return 1; + } + llvm_unreachable("Unknown LSC category"); +} + diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp index 3cc8f4c2..d8c929f2 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp @@ -630,6 +630,7 @@ bool GenXSPIRVReaderAdaptor::processVCKernelAttributes(Function &F) { auto ArgOffset = unsigned(0); auto ArgIOKinds = llvm::SmallVector(); auto ArgDescs = llvm::SmallVector(); + auto NBarrierCnt = unsigned(0); auto &&Context = F.getContext(); llvm::Type *I32Ty = llvm::Type::getInt32Ty(Context); @@ -680,6 +681,15 @@ bool GenXSPIRVReaderAdaptor::processVCKernelAttributes(Function &F) { dropFnAttribute(F, VCFunctionMD::VCSLMSize); } + if (VCINTR::AttributeList::hasFnAttr(Attrs, + VCFunctionMD::VCNamedBarrierCount)) { + VCINTR::AttributeList::getAttributeAtIndex( + Attrs, AttributeList::FunctionIndex, VCFunctionMD::VCNamedBarrierCount) + .getValueAsString() + .getAsInteger(0, NBarrierCnt); + dropFnAttribute(F, VCFunctionMD::VCNamedBarrierCount); + } + auto KernelMD = std::vector(); KernelMD.push_back(FunctionRef); KernelMD.push_back(llvm::MDString::get(Context, KernelName)); @@ -689,8 +699,8 @@ bool GenXSPIRVReaderAdaptor::processVCKernelAttributes(Function &F) { ConstantAsMetadata::get(ConstantInt::get(I32Ty, ArgOffset))); KernelMD.push_back(llvm::MDNode::get(Context, ArgIOKinds)); KernelMD.push_back(llvm::MDNode::get(Context, ArgDescs)); - KernelMD.push_back(ConstantAsMetadata::get(ConstantInt::get(I32Ty, 0))); - + KernelMD.push_back( + ConstantAsMetadata::get(ConstantInt::get(I32Ty, NBarrierCnt))); NamedMDNode *KernelMDs = F.getParent()->getOrInsertNamedMetadata(FunctionMD::GenXKernels); llvm::MDNode *Node = MDNode::get(F.getContext(), KernelMD); diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSimdCFLowering.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSimdCFLowering.cpp index 70c4aa8d..64a84455 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSimdCFLowering.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSimdCFLowering.cpp @@ -1218,6 +1218,17 @@ unsigned CMSimdCFLower::deduceNumChannels(Instruction *SI) { NumChannels = ResultElems / AddrElems; break; } + case GenXIntrinsic::genx_lsc_load_slm: + case GenXIntrinsic::genx_lsc_load_stateless: + case GenXIntrinsic::genx_lsc_load_bindless: + case GenXIntrinsic::genx_lsc_load_bti: + case GenXIntrinsic::genx_lsc_prefetch_bti: + case GenXIntrinsic::genx_lsc_prefetch_stateless: + case GenXIntrinsic::genx_lsc_prefetch_bindless: + NumChannels = GenXIntrinsic::getLSCNumVectorElements( + static_cast( + cast(CI->getOperand(7))->getZExtValue())); + break; default: break; } From 381535d6c25c794adf164fae0d0cfdd6a18a09a5 Mon Sep 17 00:00:00 2001 From: Anton Sidorenko Date: Thu, 2 Dec 2021 11:22:37 +0000 Subject: [PATCH 51/81] Stack calls are not necessary to be noinline If the stack call must not be inlined, NoInline attribute should be added by the FE, but not by the SPIRV reader adapter. --- GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp | 1 - GenXIntrinsics/test/Adaptors/fun_attributes_transform_reader.ll | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp index d8c929f2..816c6322 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp @@ -562,7 +562,6 @@ bool GenXSPIRVReaderAdaptor::processVCFunctionAttributes(Function &F) { if (VCINTR::AttributeList::hasFnAttr(Attrs, VCFunctionMD::VCStackCall)) { F.addFnAttr(FunctionMD::CMStackCall); - F.addFnAttr(Attribute::NoInline); dropFnAttribute(F, VCFunctionMD::VCStackCall); } diff --git a/GenXIntrinsics/test/Adaptors/fun_attributes_transform_reader.ll b/GenXIntrinsics/test/Adaptors/fun_attributes_transform_reader.ll index c31ac347..1c0effb3 100644 --- a/GenXIntrinsics/test/Adaptors/fun_attributes_transform_reader.ll +++ b/GenXIntrinsics/test/Adaptors/fun_attributes_transform_reader.ll @@ -48,7 +48,7 @@ define spir_kernel void @test_VCSLMSize() #6 { ret void } -; CHECK-DAG: attributes #[[FATR_STACK_CALL_ATTR_IDX]] = { noinline "CMStackCall" } +; CHECK-DAG: attributes #[[FATR_STACK_CALL_ATTR_IDX]] = { "CMStackCall" } ; CHECK-DAG: attributes #[[FATR_CALLABLE_ATTR_IDX]] = { "CMCallable" } ; CHECK-DAG: attributes #[[FATR_FC_ENTRY_IDX]] = { "CMEntry" } ; CHECK-DAG: attributes #[[FATR_SIMT_CALL_IDX]] = { "CMGenxSIMT" } From d3cef33488b7d7a23dffe49aac42c2759b447dcf Mon Sep 17 00:00:00 2001 From: Dmitry Ryabtsev Date: Thu, 9 Dec 2021 15:49:28 +0000 Subject: [PATCH 52/81] Fix lack of includes in GenXMetadata.h GetOldStyleKernelMD implementation was moved out of the header. Proper forward declarations were added. --- .../llvm/GenXIntrinsics/GenXMetadata.h | 21 +++--------- .../lib/GenXIntrinsics/CMakeLists.txt | 2 ++ .../lib/GenXIntrinsics/GenXMetadata.cpp | 32 +++++++++++++++++++ 3 files changed, 39 insertions(+), 16 deletions(-) create mode 100644 GenXIntrinsics/lib/GenXIntrinsics/GenXMetadata.cpp diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXMetadata.h b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXMetadata.h index 55dd332c..e95512db 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXMetadata.h +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXMetadata.h @@ -17,6 +17,10 @@ SPDX-License-Identifier: MIT #define GENX_METADATA_H namespace llvm { + +class MDNode; +class Function; + namespace genx { namespace FunctionMD { @@ -68,22 +72,7 @@ enum KernelMDOp { BarrierCnt // Barrier count }; -inline MDNode *GetOldStyleKernelMD(Function const &F) { - auto *KernelMD = static_cast(nullptr); - auto *KernelMDs = F.getParent()->getNamedMetadata(FunctionMD::GenXKernels); - if (!KernelMDs) - return KernelMD; - - for (unsigned I = 0, E = KernelMDs->getNumOperands(); I < E; ++I) { - auto *Kernel = mdconst::dyn_extract( - KernelMDs->getOperand(I)->getOperand(KernelMDOp::FunctionRef)); - if (Kernel == &F) { - KernelMD = KernelMDs->getOperand(I); - break; - } - } - return KernelMD; -} +MDNode *GetOldStyleKernelMD(const Function &F); } // namespace genx } // namespace llvm diff --git a/GenXIntrinsics/lib/GenXIntrinsics/CMakeLists.txt b/GenXIntrinsics/lib/GenXIntrinsics/CMakeLists.txt index facbe189..32cddf7b 100755 --- a/GenXIntrinsics/lib/GenXIntrinsics/CMakeLists.txt +++ b/GenXIntrinsics/lib/GenXIntrinsics/CMakeLists.txt @@ -23,6 +23,7 @@ if(BUILD_EXTERNAL) GenXSPIRVWriterAdaptor.cpp GenXVersion.cpp AdaptorsCommon.cpp + GenXMetadata.cpp ) llvm_update_compile_flags(LLVMGenXIntrinsics) add_dependencies(LLVMGenXIntrinsics GenXIntrinsicsGen) @@ -50,6 +51,7 @@ else() GenXSPIRVWriterAdaptor.cpp GenXVersion.cpp AdaptorsCommon.cpp + GenXMetadata.cpp ADDITIONAL_HEADER_DIRS ${GENX_INTRINSICS_MAIN_INCLUDE_DIR}/llvm/GenXIntrinsics diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXMetadata.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXMetadata.cpp new file mode 100644 index 00000000..30b9d8c4 --- /dev/null +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXMetadata.cpp @@ -0,0 +1,32 @@ +/*========================== begin_copyright_notice ============================ + +Copyright (C) 2021 Intel Corporation + +SPDX-License-Identifier: MIT + +============================= end_copyright_notice ===========================*/ + +#include "llvm/GenXIntrinsics/GenXMetadata.h" + +#include +#include +#include + +using namespace llvm; + +MDNode *llvm::genx::GetOldStyleKernelMD(Function const &F) { + auto *KernelMD = static_cast(nullptr); + auto *KernelMDs = F.getParent()->getNamedMetadata(FunctionMD::GenXKernels); + if (!KernelMDs) + return KernelMD; + + for (unsigned I = 0, E = KernelMDs->getNumOperands(); I < E; ++I) { + auto *Kernel = mdconst::dyn_extract( + KernelMDs->getOperand(I)->getOperand(KernelMDOp::FunctionRef)); + if (Kernel == &F) { + KernelMD = KernelMDs->getOperand(I); + break; + } + } + return KernelMD; +} From 84308bec33fb1c15dd03c82f5c97145f3756add9 Mon Sep 17 00:00:00 2001 From: Aleksander Us Date: Fri, 29 Oct 2021 17:57:35 +0000 Subject: [PATCH 53/81] Provide cmake error when unsupported LLVM found Fail earlier on configuration stage. --- CMakeLists.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/CMakeLists.txt b/CMakeLists.txt index a3e3f678..19f38151 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -51,6 +51,10 @@ else(CMAKE_SOURCE_DIR STREQUAL CMAKE_CURRENT_SOURCE_DIR) endif() endif(CMAKE_SOURCE_DIR STREQUAL CMAKE_CURRENT_SOURCE_DIR) +if(LLVM_VERSION_MAJOR VERSION_LESS 8) + message(FATAL_ERROR "VC-intrinsics do not support ${LLVM_VERSION} LLVM version") +endif() + include(FindPythonInterp) if(NOT PYTHONINTERP_FOUND) message(FATAL_ERROR From 09ff7f80a6db1831de1ea5494a425184d490df1e Mon Sep 17 00:00:00 2001 From: Aleksander Us Date: Tue, 26 Oct 2021 14:13:13 +0000 Subject: [PATCH 54/81] Remove wrappers for LLVM 7 VC intrinsics no longer support LLVM 7. --- .../include/llvmVCWrapper/IR/Function.h | 13 -------- .../include/llvmVCWrapper/IR/GlobalValue.h | 30 ----------------- .../include/llvmVCWrapper/IR/InstrTypes.h | 32 ------------------- .../GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp | 4 +-- .../GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp | 4 +-- .../lib/GenXIntrinsics/GenXSimdCFLowering.cpp | 29 +++++++---------- .../GenXSingleElementVectorUtil.cpp | 9 ++---- .../args_attributes_transform_reader.ll | 2 +- .../args_attributes_transform_writer.ll | 2 +- .../fun_attributes_transform_reader.ll | 2 +- 10 files changed, 20 insertions(+), 107 deletions(-) delete mode 100644 GenXIntrinsics/include/llvmVCWrapper/IR/GlobalValue.h delete mode 100644 GenXIntrinsics/include/llvmVCWrapper/IR/InstrTypes.h diff --git a/GenXIntrinsics/include/llvmVCWrapper/IR/Function.h b/GenXIntrinsics/include/llvmVCWrapper/IR/Function.h index 1120d2a2..0180a931 100644 --- a/GenXIntrinsics/include/llvmVCWrapper/IR/Function.h +++ b/GenXIntrinsics/include/llvmVCWrapper/IR/Function.h @@ -15,19 +15,6 @@ namespace VCINTR { namespace Function { -inline llvm::Function *Create(llvm::FunctionType *FTy, - llvm::Function::LinkageTypes Linkage, - unsigned AddressSpace, const llvm::Twine &N = "", - llvm::Module *M = nullptr) { -#if VC_INTR_LLVM_VERSION_MAJOR <= 7 - // Let's stick to newer LLVM versions interface. - (void)AddressSpace; - return llvm::Function::Create(FTy, Linkage, N, M); -#else - return llvm::Function::Create(FTy, Linkage, AddressSpace, N, M); -#endif -} - inline void addAttributeAtIndex(llvm::Function &F, unsigned Index, llvm::Attribute Attr) { #if VC_INTR_LLVM_VERSION_MAJOR >= 14 diff --git a/GenXIntrinsics/include/llvmVCWrapper/IR/GlobalValue.h b/GenXIntrinsics/include/llvmVCWrapper/IR/GlobalValue.h deleted file mode 100644 index 00d2f70b..00000000 --- a/GenXIntrinsics/include/llvmVCWrapper/IR/GlobalValue.h +++ /dev/null @@ -1,30 +0,0 @@ -/*========================== begin_copyright_notice ============================ - -Copyright (C) 2020-2021 Intel Corporation - -SPDX-License-Identifier: MIT - -============================= end_copyright_notice ===========================*/ - -#ifndef VCINTR_IR_GLOBALVALUE_H -#define VCINTR_IR_GLOBALVALUE_H - -#include - -namespace VCINTR { - -namespace GlobalValue { - -inline unsigned getAddressSpace(const llvm::GlobalValue &GV) { -#if VC_INTR_LLVM_VERSION_MAJOR <= 7 - return GV.getType()->getAddressSpace(); -#else - return GV.getAddressSpace(); -#endif -} - -} // namespace GlobalValue - -} // namespace VCINTR - -#endif // VCINTR_IR_GLOBALVARIABLE_H diff --git a/GenXIntrinsics/include/llvmVCWrapper/IR/InstrTypes.h b/GenXIntrinsics/include/llvmVCWrapper/IR/InstrTypes.h deleted file mode 100644 index aa58235d..00000000 --- a/GenXIntrinsics/include/llvmVCWrapper/IR/InstrTypes.h +++ /dev/null @@ -1,32 +0,0 @@ -/*========================== begin_copyright_notice ============================ - -Copyright (C) 2020-2021 Intel Corporation - -SPDX-License-Identifier: MIT - -============================= end_copyright_notice ===========================*/ - -#ifndef VCINTR_IR_INSTRTYPES_H -#define VCINTR_IR_INSTRTYPES_H - -#include - -namespace VCINTR { -#if VC_INTR_LLVM_VERSION_MAJOR <= 7 -using llvm::TerminatorInst; -#elif VC_INTR_LLVM_VERSION_MAJOR >= 8 -using TerminatorInst = llvm::Instruction; -#endif - -namespace CallBase { -template unsigned arg_size(const CBTy &CB) { -#if VC_INTR_LLVM_VERSION_MAJOR <= 7 - return CB.getNumArgOperands(); -#else - return CB.arg_size(); -#endif -} -} // namespace CallBase -} // namespace VCINTR - -#endif // VCINTR_IR_INSTRTYPES_H diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp index 816c6322..87d57f0e 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp @@ -24,7 +24,6 @@ SPDX-License-Identifier: MIT #include "llvmVCWrapper/IR/Attributes.h" #include "llvmVCWrapper/IR/Function.h" -#include "llvmVCWrapper/IR/GlobalValue.h" using namespace llvm; using namespace genx; @@ -434,8 +433,7 @@ transformKernelSignature(Function &F, const std::vector &Descs) { [](Argument &Arg) { return getOriginalValue(Arg)->getType(); }); auto *NewFTy = FunctionType::get(F.getReturnType(), NewTypes, false); - auto *NewF = VCINTR::Function::Create( - NewFTy, F.getLinkage(), VCINTR::GlobalValue::getAddressSpace(F)); + auto *NewF = Function::Create(NewFTy, F.getLinkage(), F.getAddressSpace()); // Copy function info. LLVMContext &Ctx = F.getContext(); diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp index 20ffa788..c1705cbc 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp @@ -27,7 +27,6 @@ SPDX-License-Identifier: MIT #include "llvmVCWrapper/IR/Attributes.h" #include "llvmVCWrapper/IR/DerivedTypes.h" #include "llvmVCWrapper/IR/Function.h" -#include "llvmVCWrapper/IR/GlobalValue.h" using namespace llvm; using namespace genx; @@ -197,8 +196,7 @@ transformKernelSignature(Function &F, const std::vector &Descs) { assert(!F.isVarArg() && "Kernel cannot be vararg"); auto *NewFTy = FunctionType::get(F.getReturnType(), NewParams, false); - auto *NewF = VCINTR::Function::Create( - NewFTy, F.getLinkage(), VCINTR::GlobalValue::getAddressSpace(F)); + auto *NewF = Function::Create(NewFTy, F.getLinkage(), F.getAddressSpace()); NewF->copyAttributesFrom(&F); NewF->takeName(&F); NewF->copyMetadata(&F, 0); diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSimdCFLowering.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSimdCFLowering.cpp index 64a84455..947223a8 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSimdCFLowering.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSimdCFLowering.cpp @@ -151,21 +151,22 @@ SPDX-License-Identifier: MIT #define DEBUG_TYPE "cmsimdcflowering" +#include "llvm/GenXIntrinsics/GenXSimdCFLowering.h" #include "llvm/ADT/MapVector.h" #include "llvm/Analysis/PostDominators.h" +#include "llvm/GenXIntrinsics/GenXIntrOpts.h" #include "llvm/GenXIntrinsics/GenXIntrinsics.h" #include "llvm/GenXIntrinsics/GenXMetadata.h" -#include "llvm/GenXIntrinsics/GenXIntrOpts.h" -#include "llvm/GenXIntrinsics/GenXSimdCFLowering.h" #include "llvm/IR/Constants.h" #include "llvm/IR/DebugInfo.h" #include "llvm/IR/DiagnosticInfo.h" #include "llvm/IR/DiagnosticPrinter.h" +#include "llvm/IR/IRBuilder.h" #include "llvm/IR/Instructions.h" #include "llvm/IR/Intrinsics.h" -#include "llvm/IR/IRBuilder.h" #include "llvm/IR/LLVMContext.h" #include "llvm/IR/Module.h" +#include "llvm/IR/PatternMatch.h" #include "llvm/IR/ValueHandle.h" #include "llvm/Pass.h" #include "llvm/Support/Debug.h" @@ -173,13 +174,7 @@ SPDX-License-Identifier: MIT #include #include -#if VC_INTR_LLVM_VERSION_MAJOR >= 8 -#include -#endif - -#include "llvmVCWrapper/IR/GlobalValue.h" #include "llvmVCWrapper/IR/DerivedTypes.h" -#include "llvmVCWrapper/IR/InstrTypes.h" using namespace llvm; @@ -333,7 +328,7 @@ bool CMSimdCFLowering::doInitialization(Module &M) continue; // Transform all load store on volatile globals to vload/vstore to disable // optimizations on this global (no PHI will be produced.). - auto AS0 = VCINTR::GlobalValue::getAddressSpace(G); + auto AS0 = G.getAddressSpace(); std::vector WL; for (auto UI = G.user_begin(); UI != G.user_end();) { auto U = *UI++; @@ -778,7 +773,7 @@ void CMSimdCFLower::findAndSplitJoinPoints() } for (auto sji = Jumps.begin(), sje = Jumps.end(); sji != sje; ++sji) { assert((*sji)->isTerminator() && "Expected terminator inst"); - auto Br = cast(*sji); + auto *Br = *sji; unsigned SimdWidth = SimdBranches[Br->getParent()]; LLVM_DEBUG(dbgs() << *Br << "\n"); auto JP = Br->getSuccessor(0); @@ -835,7 +830,7 @@ void CMSimdCFLower::determineJIPs() for (auto NextBB = &F->front(), EndBB = &F->back(); NextBB;) { auto BB = NextBB; NextBB = BB == EndBB ? nullptr : BB->getNextNode(); - auto Term = cast(BB->getTerminator()); + auto *Term = BB->getTerminator(); for (unsigned si = 0, se = Term->getNumSuccessors(); si != se; ++si) { BasicBlock *Succ = Term->getSuccessor(si); if (Succ == NextBB) @@ -944,7 +939,7 @@ void CMSimdCFLower::determineJIP(BasicBlock *BB, if (NeedNextJoin && JoinPoints.count(JP)) break; // found join point // See if JP finishes with a branch to BB or before. - auto Term = cast(JP->getTerminator()); + auto *Term = JP->getTerminator(); for (unsigned si = 0, se = Term->getNumSuccessors(); si != se; ++si) { auto Succ = Term->getSuccessor(si); if ((*Numbers)[Succ] <= BBNum) { @@ -1078,7 +1073,7 @@ void CMSimdCFLower::predicateInst(Instruction *Inst, unsigned SimdWidth) { return; } // An IntrNoMem intrinsic is an ALU intrinsic and can be ignored. - if (Callee->doesNotAccessMemory() || VCINTR::CallBase::arg_size(*CI) == 0) + if (Callee->doesNotAccessMemory() || CI->arg_size() == 0) return; // no predication for intrinsic marked as ISPC uniform, // for example, atomic and oword_store used in printf @@ -1086,7 +1081,7 @@ void CMSimdCFLower::predicateInst(Instruction *Inst, unsigned SimdWidth) { return; // Look for a predicate operand in operand 2, 1 or 0. - unsigned PredNum = VCINTR::CallBase::arg_size(*CI) - 1; + unsigned PredNum = CI->arg_size() - 1; for (;;) { if (auto VT = dyn_cast(CI->getArgOperand(PredNum)->getType())) { @@ -1457,7 +1452,7 @@ void CMSimdCFLower::predicateSend(CallInst *CI, unsigned IntrinsicID, break; } SmallVector Args; - for (unsigned i = 0, e = VCINTR::CallBase::arg_size(*CI); i != e; ++i) + for (unsigned i = 0, e = CI->arg_size(); i != e; ++i) if (i == PredOperandNum) Args.push_back(Pred); else @@ -1518,7 +1513,7 @@ CallInst *CMSimdCFLower::predicateWrRegion(CallInst *WrR, unsigned SimdWidth) { // First gather the args of the original wrregion. SmallVector Args; - for (unsigned i = 0, e = VCINTR::CallBase::arg_size(*WrR); i != e; ++i) + for (unsigned i = 0, e = WrR->arg_size(); i != e; ++i) Args.push_back(WrR->getArgOperand(i)); // Modify the predicate in Args. Value *Pred = Args[GenXIntrinsic::GenXRegion::PredicateOperandNum]; diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp index 19c61383..5e635595 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp @@ -25,7 +25,6 @@ SPDX-License-Identifier: MIT #include "llvmVCWrapper/IR/Attributes.h" #include "llvmVCWrapper/IR/DerivedTypes.h" #include "llvmVCWrapper/IR/Function.h" -#include "llvmVCWrapper/IR/GlobalValue.h" #include "llvmVCWrapper/IR/Instructions.h" #include "llvmVCWrapper/Support/Alignment.h" @@ -532,8 +531,8 @@ static Function &getSingleElementVectorSignature(Function &F, if (NewFunctionType == F.getFunctionType()) return F; - auto &&NewF = *VCINTR::Function::Create( - NewFunctionType, F.getLinkage(), VCINTR::GlobalValue::getAddressSpace(F)); + auto &&NewF = + *Function::Create(NewFunctionType, F.getLinkage(), F.getAddressSpace()); assert(doesSignatureHaveSingleElementVector(F) || doesSignatureHaveSingleElementVector(NewF)); @@ -702,14 +701,12 @@ class SingleElementVectorInstRewriter OldInst.getOrdering(), OldInst.getSyncScopeID(), &OldInst); } -#if VC_INTR_LLVM_VERSION_MAJOR >= 8 Instruction *visitUnaryOperator(UnaryOperator &OldInst) { auto *NewT = static_cast(nullptr); auto NewVals = ValueCont{}; std::tie(NewT, NewVals) = getOperandsFreeFromSingleElementVector(OldInst); return UnaryOperator::Create(OldInst.getOpcode(), NewVals[0], "", &OldInst); } -#endif Instruction *visitVAArgInst(VAArgInst &OldInst) { auto *NewT = static_cast(nullptr); auto NewVals = ValueCont{}; @@ -762,7 +759,7 @@ static GlobalVariable &createAndTakeFrom(GlobalVariable &GV, PointerType *NewT, auto *NewGV = new GlobalVariable( *GV.getParent(), NewT->getElementType(), GV.isConstant(), GV.getLinkage(), Initializer, "sev.global.", &GV, GV.getThreadLocalMode(), - VCINTR::GlobalValue::getAddressSpace(GV), GV.isExternallyInitialized()); + GV.getAddressSpace(), GV.isExternallyInitialized()); auto DebugInfoVec = SmallVector{}; GV.getDebugInfo(DebugInfoVec); NewGV->takeName(&GV); diff --git a/GenXIntrinsics/test/Adaptors/args_attributes_transform_reader.ll b/GenXIntrinsics/test/Adaptors/args_attributes_transform_reader.ll index 69146873..14bfb4c4 100644 --- a/GenXIntrinsics/test/Adaptors/args_attributes_transform_reader.ll +++ b/GenXIntrinsics/test/Adaptors/args_attributes_transform_reader.ll @@ -8,7 +8,7 @@ ; Test that adaptor correctly handles parameter attributes with types. -; UNSUPPORTED: llvm7, llvm8 +; UNSUPPORTED: llvm8 ; XFAIL: llvm13, llvm14 ; RUN: opt -S -GenXSPIRVReaderAdaptor < %s | FileCheck %s ; CHECK: @test diff --git a/GenXIntrinsics/test/Adaptors/args_attributes_transform_writer.ll b/GenXIntrinsics/test/Adaptors/args_attributes_transform_writer.ll index 63ca886b..c0496773 100644 --- a/GenXIntrinsics/test/Adaptors/args_attributes_transform_writer.ll +++ b/GenXIntrinsics/test/Adaptors/args_attributes_transform_writer.ll @@ -8,7 +8,7 @@ ; Test that adaptor correctly handles parameter attributes with types. -; UNSUPPORTED: llvm7, llvm8 +; UNSUPPORTED: llvm8 ; RUN: opt -S -GenXSPIRVWriterAdaptor < %s | FileCheck %s ; CHECK: @test ; CHECK-SAME: i8 diff --git a/GenXIntrinsics/test/Adaptors/fun_attributes_transform_reader.ll b/GenXIntrinsics/test/Adaptors/fun_attributes_transform_reader.ll index 1c0effb3..b20455f6 100644 --- a/GenXIntrinsics/test/Adaptors/fun_attributes_transform_reader.ll +++ b/GenXIntrinsics/test/Adaptors/fun_attributes_transform_reader.ll @@ -9,7 +9,7 @@ ; Test that adaptor correctly translates function attributes to VC-specific ; metadata (the processed attributes are expected to be discarded) -; UNSUPPORTED: llvm7, llvm8 +; UNSUPPORTED: llvm8 ; XFAIL: llvm13, llvm14 ; RUN: opt -S -GenXSPIRVReaderAdaptor < %s | FileCheck %s ; CHECK: @test_VCFunction() From 753ad5002af5a5e467b3a0194a2b0e9a3243059e Mon Sep 17 00:00:00 2001 From: Aleksander Us Date: Thu, 7 Oct 2021 10:41:10 +0000 Subject: [PATCH 55/81] Remove legacy simd8 intrinsics VC always uses simd1 mode with separate intrinsics. --- .../GenXIntrinsics/Intrinsic_definitions.py | 39 ------------------- 1 file changed, 39 deletions(-) diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py index 16588c1c..451a04df 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py @@ -4681,45 +4681,6 @@ "attributes" : "NoMem" }, -### ``llvm.genx.group.or.local.size`` : read local or group size register -### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -### -### * Return value: v8i32 -### -### [GROUP_X, GROUP_Y, GROUP_Z, LOCAL_X, LOCAL_Y, LOCAL_Z, UNDEF, UNDEF] -### -### This is generated by CMImpParam. This is to match OpenCL thread -### payload layout. -### - "group_or_local_size" : { "result" : "int8", - "arguments" : [], - "attributes" : "NoMem" - }, - -### ``llvm.genx.local.id.*`` : read local ID register -### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -### * ``llvm.genx.local.id.x`` : read implicit arg local id x -### * ``llvm.genx.local.id.y`` : read implicit arg local id y -### * ``llvm.genx.local.id.z`` : read implicit arg local id z -### -### * Return value: v8i16 - SIMD8 dispatch but only the first componentis used. -### -### This is generated by CMImpParam. This is to match OpenCL thread -### payload layout. -### - "local_id_x" : { "result" : "short8", - "arguments" : [], - "attributes" : "NoMem" - }, - "local_id_y" : { "result" : "short8", - "arguments" : [], - "attributes" : "NoMem" - }, - "local_id_z" : { "result" : "short8", - "arguments" : [], - "attributes" : "NoMem" - }, - ### ``llvm.genx.group.count.`` : read group count register ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ### ``llvm.genx.group.count`` : read vISA v9 (%group_count_x) From 3a5f4b4608f0e18fcdc04d851568f3aab4651545 Mon Sep 17 00:00:00 2001 From: Aleksander Us Date: Tue, 11 Jan 2022 12:23:57 +0000 Subject: [PATCH 56/81] Fix buildfail on ToT caused by D116110 Remove unused wrapper to fix buildfail because of attribute removal API change. New class was added in D116110 and wrapping of this case is not trivial so removal of unneeded function is the easiest solution. --- GenXIntrinsics/include/llvmVCWrapper/IR/Attributes.h | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/GenXIntrinsics/include/llvmVCWrapper/IR/Attributes.h b/GenXIntrinsics/include/llvmVCWrapper/IR/Attributes.h index 4902572d..149336b0 100644 --- a/GenXIntrinsics/include/llvmVCWrapper/IR/Attributes.h +++ b/GenXIntrinsics/include/llvmVCWrapper/IR/Attributes.h @@ -94,17 +94,6 @@ removeAttributeAtIndex(llvm::LLVMContext &C, #endif } -inline llvm::AttributeList -removeAttributesAtIndex(llvm::LLVMContext &C, - const llvm::AttributeList &AttrList, unsigned Index, - const llvm::AttrBuilder &AttrsToRemove) { -#if VC_INTR_LLVM_VERSION_MAJOR >= 14 - return AttrList.removeAttributesAtIndex(C, Index, AttrsToRemove); -#else - return AttrList.removeAttributes(C, Index, AttrsToRemove); -#endif -} - } // namespace AttributeList } // namespace VCINTR From d2f78f24314cd5aad1f633042cf5ae49b0ecdb24 Mon Sep 17 00:00:00 2001 From: Sergey Semenov Date: Tue, 25 Jan 2022 17:59:19 +0000 Subject: [PATCH 57/81] Fix an issue with GenXIntrinsicDescription.gen includes Fix an issue where GenXIntrinsicDescription.gen is included without including map header. --- GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSimdCFLowering.h | 1 + GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp | 1 + 2 files changed, 2 insertions(+) diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSimdCFLowering.h b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSimdCFLowering.h index b5cffcb0..e71633e9 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSimdCFLowering.h +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSimdCFLowering.h @@ -17,6 +17,7 @@ SPDX-License-Identifier: MIT #include "llvm/IR/GlobalVariable.h" #include "llvm/IR/Instructions.h" #include +#include #include namespace llvm { diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp index 71c4ada7..906bcdf3 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp @@ -35,6 +35,7 @@ See LICENSE.TXT for details. #include "llvmVCWrapper/IR/Intrinsics.h" #include +#include using namespace llvm; From a7a3efa116ae165132508f3f9a975fccb196fede Mon Sep 17 00:00:00 2001 From: Anatoly Parshintsev Date: Wed, 26 Jan 2022 15:11:43 +0000 Subject: [PATCH 58/81] Fix potential null pointer dereference dyn_extract implies that nullptr can be returned, while in this case we need a more strict check. --- GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp index 87d57f0e..4d154c69 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp @@ -601,7 +601,7 @@ bool GenXSPIRVReaderAdaptor::processVCFunctionAttributes(Function &F) { if (auto *ReqdSubgroupSize = F.getMetadata(SPIRVParams::SPIRVSIMDSubgroupSize)) { auto SIMDSize = - mdconst::dyn_extract(ReqdSubgroupSize->getOperand(0)) + mdconst::extract(ReqdSubgroupSize->getOperand(0)) ->getZExtValue(); Attribute Attr = Attribute::get(Context, FunctionMD::OCLRuntime, std::to_string(SIMDSize)); From a3ca3a364a92ed966a337d9154f9f2d02b0efc5a Mon Sep 17 00:00:00 2001 From: Nikita Rudenko Date: Thu, 3 Feb 2022 14:10:33 +0000 Subject: [PATCH 59/81] Set some tests to XFAIL on latest LLVM 15 Set some tests to XFAIL on latest LLVM 15 --- GenXIntrinsics/lib/GenXIntrinsics/GenXRestoreIntrAttr.cpp | 4 ++-- GenXIntrinsics/lib/GenXIntrinsics/GenXSimdCFLowering.cpp | 4 ++-- GenXIntrinsics/test/Adaptors/annotated_args_mixed_reader.ll | 2 +- GenXIntrinsics/test/Adaptors/annotated_args_no_conv_reader.ll | 2 +- GenXIntrinsics/test/Adaptors/annotated_args_reader.ll | 2 +- .../test/Adaptors/args_attributes_transform_reader.ll | 2 +- GenXIntrinsics/test/Adaptors/combined_args_reader.ll | 2 +- .../test/Adaptors/fun_attributes_transform_reader.ll | 2 +- GenXIntrinsics/test/Adaptors/image_array_reader.ll | 2 +- GenXIntrinsics/test/Adaptors/media_block_reader.ll | 2 +- GenXIntrinsics/test/Adaptors/no_kernels_module_reader.ll | 2 +- GenXIntrinsics/test/Adaptors/no_vcfunction_reader.ll | 2 +- GenXIntrinsics/test/Adaptors/non_global_ptr_reader.ll | 2 +- GenXIntrinsics/test/Adaptors/old_decorated_args_reader.ll | 2 +- GenXIntrinsics/test/Adaptors/plain_args_reader.ll | 2 +- GenXIntrinsics/test/Adaptors/sev_signature_reader.ll | 2 +- GenXIntrinsics/test/Adaptors/spirv_friendly_types_reader.ll | 2 +- GenXIntrinsics/test/Adaptors/surface_access_reader.ll | 2 +- GenXIntrinsics/test/Adaptors/unknown_arg_reader.ll | 2 +- GenXIntrinsics/test/SimdCFLowering/bitcast_between_wrrs.ll | 2 +- GenXIntrinsics/test/SimdCFLowering/predicate_masked_gather.ll | 2 +- GenXIntrinsics/test/SimdCFLowering/replicate_mask.ll | 2 +- .../test/SimdCFLowering/replicate_mask_masked_gather4.ll | 2 +- .../test/SimdCFLowering/update_mask_masked_gather4.ll | 2 +- 24 files changed, 26 insertions(+), 26 deletions(-) diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXRestoreIntrAttr.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXRestoreIntrAttr.cpp index 9a79b9ae..dcd2d455 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXRestoreIntrAttr.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXRestoreIntrAttr.cpp @@ -27,13 +27,13 @@ See LICENSE.TXT for details. /// //===----------------------------------------------------------------------===// -#define DEBUG_TYPE "GENX_RESTOREINTRATTR" - #include "llvm/GenXIntrinsics/GenXIntrOpts.h" #include "llvm/GenXIntrinsics/GenXIntrinsics.h" #include "llvm/Support/Debug.h" #include "llvm/Pass.h" +#define DEBUG_TYPE "GENX_RESTOREINTRATTR" + using namespace llvm; namespace { diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSimdCFLowering.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSimdCFLowering.cpp index 947223a8..fe53aeae 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSimdCFLowering.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSimdCFLowering.cpp @@ -149,8 +149,6 @@ SPDX-License-Identifier: MIT /// //===----------------------------------------------------------------------===// -#define DEBUG_TYPE "cmsimdcflowering" - #include "llvm/GenXIntrinsics/GenXSimdCFLowering.h" #include "llvm/ADT/MapVector.h" #include "llvm/Analysis/PostDominators.h" @@ -176,6 +174,8 @@ SPDX-License-Identifier: MIT #include "llvmVCWrapper/IR/DerivedTypes.h" +#define DEBUG_TYPE "cmsimdcflowering" + using namespace llvm; namespace { diff --git a/GenXIntrinsics/test/Adaptors/annotated_args_mixed_reader.ll b/GenXIntrinsics/test/Adaptors/annotated_args_mixed_reader.ll index 57d4aa6a..84815aea 100644 --- a/GenXIntrinsics/test/Adaptors/annotated_args_mixed_reader.ll +++ b/GenXIntrinsics/test/Adaptors/annotated_args_mixed_reader.ll @@ -6,7 +6,7 @@ ; ;============================ end_copyright_notice ============================= -; XFAIL: llvm13,llvm14 +; XFAIL: llvm13, llvm14, llvm15 ; Test that reader can cope with mixed mode when some ; arguments use address convert and some do not. diff --git a/GenXIntrinsics/test/Adaptors/annotated_args_no_conv_reader.ll b/GenXIntrinsics/test/Adaptors/annotated_args_no_conv_reader.ll index 5abfa391..9a47be46 100644 --- a/GenXIntrinsics/test/Adaptors/annotated_args_no_conv_reader.ll +++ b/GenXIntrinsics/test/Adaptors/annotated_args_no_conv_reader.ll @@ -6,7 +6,7 @@ ; ;============================ end_copyright_notice ============================= -; XFAIL: llvm13,llvm14 +; XFAIL: llvm13, llvm14, llvm15 ; Test that reader correctly restores metadata and does ; not change other things if there is no address conversion ; but correct SPIRV types in signature. diff --git a/GenXIntrinsics/test/Adaptors/annotated_args_reader.ll b/GenXIntrinsics/test/Adaptors/annotated_args_reader.ll index 1638daea..db7c3a15 100644 --- a/GenXIntrinsics/test/Adaptors/annotated_args_reader.ll +++ b/GenXIntrinsics/test/Adaptors/annotated_args_reader.ll @@ -6,7 +6,7 @@ ; ;============================ end_copyright_notice ============================= -; XFAIL: llvm13,llvm14 +; XFAIL: llvm13, llvm14, llvm15 ; Test kernel argument translation from new style with opaque types ; that SPIRV translator can understand to old style with ; metadata. Here annotations for OCL runtime are used. diff --git a/GenXIntrinsics/test/Adaptors/args_attributes_transform_reader.ll b/GenXIntrinsics/test/Adaptors/args_attributes_transform_reader.ll index 14bfb4c4..5310a881 100644 --- a/GenXIntrinsics/test/Adaptors/args_attributes_transform_reader.ll +++ b/GenXIntrinsics/test/Adaptors/args_attributes_transform_reader.ll @@ -9,7 +9,7 @@ ; Test that adaptor correctly handles parameter attributes with types. ; UNSUPPORTED: llvm8 -; XFAIL: llvm13, llvm14 +; XFAIL: llvm13, llvm14, llvm15 ; RUN: opt -S -GenXSPIRVReaderAdaptor < %s | FileCheck %s ; CHECK: @test ; CHECK-SAME: (%foo addrspace(1)* byval(%foo) %arg) diff --git a/GenXIntrinsics/test/Adaptors/combined_args_reader.ll b/GenXIntrinsics/test/Adaptors/combined_args_reader.ll index d48662a6..fe1dc276 100644 --- a/GenXIntrinsics/test/Adaptors/combined_args_reader.ll +++ b/GenXIntrinsics/test/Adaptors/combined_args_reader.ll @@ -6,7 +6,7 @@ ; ;============================ end_copyright_notice ============================= -; XFAIL: llvm13,llvm14 +; XFAIL: llvm13, llvm14, llvm15 ; Test combined reader translation: kernel has both native SPIRV types ; and impicit arguments. Implicit arguments would not show in normal ; flow, though they appear in old cmc. diff --git a/GenXIntrinsics/test/Adaptors/fun_attributes_transform_reader.ll b/GenXIntrinsics/test/Adaptors/fun_attributes_transform_reader.ll index b20455f6..68b0f336 100644 --- a/GenXIntrinsics/test/Adaptors/fun_attributes_transform_reader.ll +++ b/GenXIntrinsics/test/Adaptors/fun_attributes_transform_reader.ll @@ -10,7 +10,7 @@ ; metadata (the processed attributes are expected to be discarded) ; UNSUPPORTED: llvm8 -; XFAIL: llvm13, llvm14 +; XFAIL: llvm13, llvm14, llvm15 ; RUN: opt -S -GenXSPIRVReaderAdaptor < %s | FileCheck %s ; CHECK: @test_VCFunction() ; CHECK: @test_VCStackCall() diff --git a/GenXIntrinsics/test/Adaptors/image_array_reader.ll b/GenXIntrinsics/test/Adaptors/image_array_reader.ll index d49e6036..28965a55 100644 --- a/GenXIntrinsics/test/Adaptors/image_array_reader.ll +++ b/GenXIntrinsics/test/Adaptors/image_array_reader.ll @@ -6,7 +6,7 @@ ; ;============================ end_copyright_notice ============================= -; XFAIL: llvm13,llvm14 +; XFAIL: llvm13, llvm14, llvm15 ; Test reader translation of image array arguments. ; RUN: opt -S -GenXSPIRVReaderAdaptor < %s | FileCheck %s diff --git a/GenXIntrinsics/test/Adaptors/media_block_reader.ll b/GenXIntrinsics/test/Adaptors/media_block_reader.ll index 810627d0..95d5ac76 100644 --- a/GenXIntrinsics/test/Adaptors/media_block_reader.ll +++ b/GenXIntrinsics/test/Adaptors/media_block_reader.ll @@ -6,7 +6,7 @@ ; ;============================ end_copyright_notice ============================= -; XFAIL: llvm13,llvm14 +; XFAIL: llvm13, llvm14, llvm15 ; Test reader translation of media block image arguments. ; RUN: opt -S -GenXSPIRVReaderAdaptor < %s | FileCheck %s diff --git a/GenXIntrinsics/test/Adaptors/no_kernels_module_reader.ll b/GenXIntrinsics/test/Adaptors/no_kernels_module_reader.ll index 090d4c91..8f7e4a8e 100644 --- a/GenXIntrinsics/test/Adaptors/no_kernels_module_reader.ll +++ b/GenXIntrinsics/test/Adaptors/no_kernels_module_reader.ll @@ -6,7 +6,7 @@ ; ;============================ end_copyright_notice ============================= -; XFAIL: llvm13,llvm14 +; XFAIL: llvm13, llvm14, llvm15 ; Test general translation of attributes within module that has no kernels ; RUN: opt -S -GenXSPIRVReaderAdaptor < %s | FileCheck %s diff --git a/GenXIntrinsics/test/Adaptors/no_vcfunction_reader.ll b/GenXIntrinsics/test/Adaptors/no_vcfunction_reader.ll index c447bb8e..74fa9fc3 100644 --- a/GenXIntrinsics/test/Adaptors/no_vcfunction_reader.ll +++ b/GenXIntrinsics/test/Adaptors/no_vcfunction_reader.ll @@ -6,7 +6,7 @@ ; ;============================ end_copyright_notice ============================= -; XFAIL: llvm13,llvm14 +; XFAIL: llvm13, llvm14, llvm15 ; Test that reader ignores signature rewriting for kernels ; that are not VCFunction. diff --git a/GenXIntrinsics/test/Adaptors/non_global_ptr_reader.ll b/GenXIntrinsics/test/Adaptors/non_global_ptr_reader.ll index ab383288..5f0704e5 100644 --- a/GenXIntrinsics/test/Adaptors/non_global_ptr_reader.ll +++ b/GenXIntrinsics/test/Adaptors/non_global_ptr_reader.ll @@ -6,7 +6,7 @@ ; ;============================ end_copyright_notice ============================= -; XFAIL: llvm13,llvm14 +; XFAIL: llvm13, llvm14, llvm15 ; Test that reader treats only global pointer as svmptr type ; and ignores other address spaces. diff --git a/GenXIntrinsics/test/Adaptors/old_decorated_args_reader.ll b/GenXIntrinsics/test/Adaptors/old_decorated_args_reader.ll index f78ba283..4eac7c5a 100644 --- a/GenXIntrinsics/test/Adaptors/old_decorated_args_reader.ll +++ b/GenXIntrinsics/test/Adaptors/old_decorated_args_reader.ll @@ -6,7 +6,7 @@ ; ;============================ end_copyright_notice ============================= -; XFAIL: llvm13,llvm14 +; XFAIL: llvm13, llvm14, llvm15 ; Test reader translation of old-style decorated arguments. ; Annotations for these are directly translated from attributes to ; kernel metadata without any checks. Required until full transition diff --git a/GenXIntrinsics/test/Adaptors/plain_args_reader.ll b/GenXIntrinsics/test/Adaptors/plain_args_reader.ll index faf2e89a..fca3883d 100644 --- a/GenXIntrinsics/test/Adaptors/plain_args_reader.ll +++ b/GenXIntrinsics/test/Adaptors/plain_args_reader.ll @@ -6,7 +6,7 @@ ; ;============================ end_copyright_notice ============================= -; XFAIL: llvm13,llvm14 +; XFAIL: llvm13, llvm14, llvm15 ; Test kernel argument translation from new style with opaque types ; that SPIRV translator can understand to old style with ; metadata. Arguments without annotations are used here (CMRT like). diff --git a/GenXIntrinsics/test/Adaptors/sev_signature_reader.ll b/GenXIntrinsics/test/Adaptors/sev_signature_reader.ll index f282517a..7a030732 100644 --- a/GenXIntrinsics/test/Adaptors/sev_signature_reader.ll +++ b/GenXIntrinsics/test/Adaptors/sev_signature_reader.ll @@ -6,7 +6,7 @@ ; ;============================ end_copyright_notice ============================= -; XFAIL: llvm13, llvm14 +; XFAIL: llvm13, llvm14, llvm15 ; Test simple signatures tranform ; RUN: opt -S -GenXSPIRVReaderAdaptor < %s | FileCheck %s diff --git a/GenXIntrinsics/test/Adaptors/spirv_friendly_types_reader.ll b/GenXIntrinsics/test/Adaptors/spirv_friendly_types_reader.ll index bd43cee6..76a50f0e 100644 --- a/GenXIntrinsics/test/Adaptors/spirv_friendly_types_reader.ll +++ b/GenXIntrinsics/test/Adaptors/spirv_friendly_types_reader.ll @@ -6,7 +6,7 @@ ; ;============================ end_copyright_notice ============================= -; XFAIL: llvm13,llvm14 +; XFAIL: llvm13, llvm14, llvm15 ; Test reader translation of SPIRV friendly IR types ; RUN: opt -S -GenXSPIRVReaderAdaptor < %s | FileCheck %s diff --git a/GenXIntrinsics/test/Adaptors/surface_access_reader.ll b/GenXIntrinsics/test/Adaptors/surface_access_reader.ll index 75fe3051..6fbf8d1d 100644 --- a/GenXIntrinsics/test/Adaptors/surface_access_reader.ll +++ b/GenXIntrinsics/test/Adaptors/surface_access_reader.ll @@ -6,7 +6,7 @@ ; ;============================ end_copyright_notice ============================= -; XFAIL: llvm13,llvm14 +; XFAIL: llvm13, llvm14, llvm15 ; Test kernel surface argument translation from new style with opaque ; types that SPIRV translator can understand to old style with ; metadata. This test checks access qualifiers translation. diff --git a/GenXIntrinsics/test/Adaptors/unknown_arg_reader.ll b/GenXIntrinsics/test/Adaptors/unknown_arg_reader.ll index 3201686a..b1e3b1e3 100644 --- a/GenXIntrinsics/test/Adaptors/unknown_arg_reader.ll +++ b/GenXIntrinsics/test/Adaptors/unknown_arg_reader.ll @@ -6,7 +6,7 @@ ; ;============================ end_copyright_notice ============================= -; XFAIL: llvm13,llvm14 +; XFAIL: llvm13, llvm14, llvm15 ; Test reader translation of implicit argument with argument kind ; decoration. diff --git a/GenXIntrinsics/test/SimdCFLowering/bitcast_between_wrrs.ll b/GenXIntrinsics/test/SimdCFLowering/bitcast_between_wrrs.ll index e2372375..109ca229 100644 --- a/GenXIntrinsics/test/SimdCFLowering/bitcast_between_wrrs.ll +++ b/GenXIntrinsics/test/SimdCFLowering/bitcast_between_wrrs.ll @@ -6,7 +6,7 @@ ; ;============================ end_copyright_notice ============================= -; XFAIL: llvm13,llvm14 +; XFAIL: llvm13, llvm14, llvm15 ; RUN: opt -S -cmsimdcflowering < %s | FileCheck %s @Rcp_T2 = internal global <64 x double> undef diff --git a/GenXIntrinsics/test/SimdCFLowering/predicate_masked_gather.ll b/GenXIntrinsics/test/SimdCFLowering/predicate_masked_gather.ll index f7220c6b..67f4cb43 100644 --- a/GenXIntrinsics/test/SimdCFLowering/predicate_masked_gather.ll +++ b/GenXIntrinsics/test/SimdCFLowering/predicate_masked_gather.ll @@ -6,7 +6,7 @@ ; ;============================ end_copyright_notice ============================= -; XFAIL: llvm13,llvm14 +; XFAIL: llvm13, llvm14, llvm15 ; RUN: opt -S -cmsimdcflowering < %s | FileCheck %s ; CHECK: @EM = internal global <32 x i1> diff --git a/GenXIntrinsics/test/SimdCFLowering/replicate_mask.ll b/GenXIntrinsics/test/SimdCFLowering/replicate_mask.ll index 017c84f9..594ca3ec 100644 --- a/GenXIntrinsics/test/SimdCFLowering/replicate_mask.ll +++ b/GenXIntrinsics/test/SimdCFLowering/replicate_mask.ll @@ -6,7 +6,7 @@ ; ;============================ end_copyright_notice ============================= -; XFAIL: llvm13,llvm14 +; XFAIL: llvm13, llvm14, llvm15 ; RUN: opt -S -cmsimdcflowering < %s | FileCheck %s @g1 = internal global <64 x i32> undef diff --git a/GenXIntrinsics/test/SimdCFLowering/replicate_mask_masked_gather4.ll b/GenXIntrinsics/test/SimdCFLowering/replicate_mask_masked_gather4.ll index 1babab42..86eabdfa 100644 --- a/GenXIntrinsics/test/SimdCFLowering/replicate_mask_masked_gather4.ll +++ b/GenXIntrinsics/test/SimdCFLowering/replicate_mask_masked_gather4.ll @@ -6,7 +6,7 @@ ; ;============================ end_copyright_notice ============================= -; XFAIL: llvm13,llvm14 +; XFAIL: llvm13, llvm14, llvm15 ; RUN: opt -S -cmsimdcflowering < %s | FileCheck %s @Rcp_T2 = internal global <64 x i32> undef diff --git a/GenXIntrinsics/test/SimdCFLowering/update_mask_masked_gather4.ll b/GenXIntrinsics/test/SimdCFLowering/update_mask_masked_gather4.ll index 3ab9102e..9e5d2ac1 100644 --- a/GenXIntrinsics/test/SimdCFLowering/update_mask_masked_gather4.ll +++ b/GenXIntrinsics/test/SimdCFLowering/update_mask_masked_gather4.ll @@ -6,7 +6,7 @@ ; ;============================ end_copyright_notice ============================= -; XFAIL: llvm13,llvm14 +; XFAIL: llvm13, llvm14, llvm15 ; RUN: opt -S -cmsimdcflowering < %s | FileCheck %s @g1 = internal global <64 x i32> undef From a9bb6d8040c43404c5fbe3694e59c503d179d19a Mon Sep 17 00:00:00 2001 From: Nikita Rudenko Date: Tue, 1 Feb 2022 14:57:43 +0000 Subject: [PATCH 60/81] Fix attributes are not forwarded for call inst with SEV GenXSingleElementVectorUtil did not forward metadata and attributes for call instructions with SEV. This commit fixes it. --- .../GenXSingleElementVectorUtil.cpp | 6 ++- .../test/Adaptors/sev_calling_conv_reader.ll | 37 +++++++++++++++++ .../test/Adaptors/sev_calling_conv_writer.ll | 40 +++++++++++++++++++ 3 files changed, 82 insertions(+), 1 deletion(-) create mode 100644 GenXIntrinsics/test/Adaptors/sev_calling_conv_reader.ll create mode 100644 GenXIntrinsics/test/Adaptors/sev_calling_conv_writer.ll diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp index 5e635595..db83b7be 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp @@ -387,7 +387,11 @@ static void replaceAllUsesWith(Function &OldF, Function &NewF) { } auto *NewCall = CallInst::Create(&NewF, NewParams, "", OldInst); - NewCall->setTailCall(OldInst->isTailCall()); + NewCall->setCallingConv(OldInst->getCallingConv()); + NewCall->setTailCallKind(OldInst->getTailCallKind()); + NewCall->copyIRFlags(OldInst); + NewCall->copyMetadata(*OldInst); + NewCall->setAttributes(OldInst->getAttributes()); replaceAllUsesWith(OldInst, NewCall); } } diff --git a/GenXIntrinsics/test/Adaptors/sev_calling_conv_reader.ll b/GenXIntrinsics/test/Adaptors/sev_calling_conv_reader.ll new file mode 100644 index 00000000..fe680683 --- /dev/null +++ b/GenXIntrinsics/test/Adaptors/sev_calling_conv_reader.ll @@ -0,0 +1,37 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2022 Intel Corporation +; +; SPDX-License-Identifier: MIT +; +;============================ end_copyright_notice ============================= + +; Test GenXSingleElementVectorUtil preserves calling convention +; (spir_func here) + +; XFAIL: llvm13, llvm14, llvm15 +; RUN: opt -S -GenXSPIRVReaderAdaptor < %s | FileCheck %s + + +; ModuleID = 'start.ll' +source_filename = "start.ll" +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024" +target triple = "spir64-unknown-unknown" + +; Function Attrs: noinline nounwind +; CHECK: define internal spir_func void @bar(<1 x i32>* %a) #0 { +define internal spir_func void @bar(i32* "VCSingleElementVector"="0" %a) #0 { + ret void +} + +; Function Attrs: noinline nounwind +define spir_kernel void @foo() #1 !intel_reqd_sub_group_size !0 { +; CHECK: call spir_func void @bar(<1 x i32>* undef) + call spir_func void @bar(i32* undef) + ret void +} + +attributes #0 = { noinline nounwind "VCFunction" } +attributes #1 = { noinline nounwind "VCFunction" "VCNamedBarrierCount"="0" "VCSLMSize"="0" } + +!0 = !{i32 1} diff --git a/GenXIntrinsics/test/Adaptors/sev_calling_conv_writer.ll b/GenXIntrinsics/test/Adaptors/sev_calling_conv_writer.ll new file mode 100644 index 00000000..e37edc18 --- /dev/null +++ b/GenXIntrinsics/test/Adaptors/sev_calling_conv_writer.ll @@ -0,0 +1,40 @@ +;=========================== begin_copyright_notice ============================ +; +; Copyright (C) 2022 Intel Corporation +; +; SPDX-License-Identifier: MIT +; +;============================ end_copyright_notice ============================= + +; Test GenXSingleElementVectorUtil preserves calling convention +; (spir_func here) + +; XFAIL: llvm13, llvm14 +; RUN: opt -S -GenXSPIRVWriterAdaptor < %s | FileCheck %s + +; ModuleID = 'sev_calling_conv_reader.ll' +source_filename = "start.ll" +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024" +target triple = "spir64-unknown-unknown" + +; Function Attrs: noinline nounwind +; CHECK: define internal spir_func void @bar(i32* "VCSingleElementVector"="0" %a) #0 +define internal spir_func void @bar(<1 x i32>* %a) #0 { + ret void +} + +; Function Attrs: noinline nounwind +define dllexport spir_kernel void @foo() #1 !intel_reqd_sub_group_size !2 { +; CHECK: call spir_func void @bar(i32* undef) + call spir_func void @bar(<1 x i32>* undef) + ret void +} + +attributes #0 = { noinline nounwind } +attributes #1 = { noinline nounwind "CMGenxMain" "oclrt"="1" } + +!genx.kernels = !{!0} + +!0 = !{void ()* @foo, !"foo", !1, i32 0, i32 0, !1, !1, i32 0} +!1 = !{} +!2 = !{i32 1} From 5066d947985dd0c5107765daec5f24f735f3259a Mon Sep 17 00:00:00 2001 From: y Date: Mon, 7 Feb 2022 23:12:24 +0300 Subject: [PATCH 61/81] add ADLP and ADLS platforms --- GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py index caef9ba8..3e084255 100755 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py @@ -80,7 +80,7 @@ # It is used to define ordering between the respected platforms platform_list = ["HSW", "BDW", "CHV", "SKL", "BXT", "KBL", "GLK", "CNL", "ICL", "ICLLP", "TGLLP", "RKL", "DG1", - "XEHP", "DG2", "PVC", "PVCXT"] + "ADLP", "ADLS", "XEHP", "DG2", "PVC", "PVCXT"] def getAttributeList(Attrs): """ From 91071ac9d072adebbe59bbbd6ad502ab5c781048 Mon Sep 17 00:00:00 2001 From: Yuly Tarasov Date: Tue, 8 Feb 2022 13:22:43 +0300 Subject: [PATCH 62/81] Add add3c intrinsic Add add3 with carry intrinsic --- .../include/llvm/GenXIntrinsics/GenXIntrinsics.h | 14 ++++++++------ .../llvm/GenXIntrinsics/Intrinsic_definitions.py | 15 +++++++++++++++ 2 files changed, 23 insertions(+), 6 deletions(-) diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h index c018ba00..e451ec35 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h @@ -39,12 +39,14 @@ enum ID : unsigned { }; namespace GenXResult { - enum ResultIndexes { - IdxAddc_Add = 1, - IdxAddc_Carry = 0, - IdxSubb_Sub = 1, - IdxSubb_Borrow = 0 - }; +enum ResultIndexes { + IdxAddc_Add = 1, + IdxAddc_Carry = 0, + IdxSubb_Sub = 1, + IdxSubb_Borrow = 0, + IdxAdd3c_Add = 1, + IdxAdd3c_Carry = 0 +}; } // The number of elements to load per address (vector size) diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py index 451a04df..087898cf 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py @@ -1775,6 +1775,21 @@ "attributes" : "NoMem" }, +### add3c +### ^^^^^ +### +### ``llvm.genx.add3c.<{carry, add3}>.`` : add3 with carry +### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +### * ``llvm.genx.add3c`` : +### +### * arg0: first input, i32 scalar/vector integer type +### * arg1: second input, same type as arg0 +### * arg2: third input, same type as arg0 + "add3c" : { "result" : ["anyint", "intvector"], + "arguments" : ["anyint",1,1,1], + "attributes" : "NoMem" + }, + ### bfn ### ^^^ ### From 9b2ae13a645538565c8a32993ca1791797221e55 Mon Sep 17 00:00:00 2001 From: Nikita Rudenko Date: Fri, 4 Feb 2022 17:04:42 +0000 Subject: [PATCH 63/81] Remove XFAIL from some tests Remove XFAIL from some tests --- GenXIntrinsics/test/Adaptors/sev_calling_conv_writer.ll | 1 - 1 file changed, 1 deletion(-) diff --git a/GenXIntrinsics/test/Adaptors/sev_calling_conv_writer.ll b/GenXIntrinsics/test/Adaptors/sev_calling_conv_writer.ll index e37edc18..14e5853f 100644 --- a/GenXIntrinsics/test/Adaptors/sev_calling_conv_writer.ll +++ b/GenXIntrinsics/test/Adaptors/sev_calling_conv_writer.ll @@ -9,7 +9,6 @@ ; Test GenXSingleElementVectorUtil preserves calling convention ; (spir_func here) -; XFAIL: llvm13, llvm14 ; RUN: opt -S -GenXSPIRVWriterAdaptor < %s | FileCheck %s ; ModuleID = 'sev_calling_conv_reader.ll' From 8b6e209fe1269a2c6470b36dfbaa0e051d2a100f Mon Sep 17 00:00:00 2001 From: Konstantin Vladimirov Date: Tue, 8 Feb 2022 10:47:03 +0000 Subject: [PATCH 64/81] introducing named barrier support in adaptor pass named barrier required for DPC++ and other customers --- .../lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp index c1705cbc..e0e895a9 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp @@ -610,6 +610,18 @@ bool GenXSPIRVWriterAdaptorImpl::runOnFunction(Function &F) { } } + if (KernelMD->getNumOperands() > KernelMDOp::NBarrierCnt) { + if (auto VM = dyn_cast( + KernelMD->getOperand(KernelMDOp::NBarrierCnt))) + if (auto V = dyn_cast(VM->getValue())) { + auto NBarrierCnt = V->getZExtValue(); + auto Attr = Attribute::get(Context, VCFunctionMD::VCNamedBarrierCount, + std::to_string(NBarrierCnt)); + VCINTR::Function::addAttributeAtIndex(F, AttributeList::FunctionIndex, + Attr); + } + } + return true; } From e45940b947892e724e6c4fb954c5464f9ae4aa66 Mon Sep 17 00:00:00 2001 From: Aleksander Us Date: Mon, 14 Feb 2022 14:58:22 +0000 Subject: [PATCH 65/81] Use getPointerElementType for pointee types PointerType::getElementType() was removed from LLVM. https://reviews.llvm.org/rGd593cf79458a59d37e75c886a4fc3ac6a02b484d --- .../lib/GenXIntrinsics/AdaptorsCommon.cpp | 2 +- .../lib/GenXIntrinsics/GenXIntrinsics.cpp | 2 +- .../GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp | 2 +- .../lib/GenXIntrinsics/GenXSimdCFLowering.cpp | 4 ++-- .../GenXSingleElementVectorUtil.cpp | 20 +++++++++---------- 5 files changed, 15 insertions(+), 15 deletions(-) diff --git a/GenXIntrinsics/lib/GenXIntrinsics/AdaptorsCommon.cpp b/GenXIntrinsics/lib/GenXIntrinsics/AdaptorsCommon.cpp index 2fbac4e6..536a2c5b 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/AdaptorsCommon.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/AdaptorsCommon.cpp @@ -43,7 +43,7 @@ void legalizeParamAttributes(Function *F) { continue; #endif // VC_INTR_LLVM_VERSION_MAJOR >= 13 - auto *ElemType = PTy->getElementType(); + auto *ElemType = PTy->getPointerElementType(); legalizeAttribute(Arg, ElemType, Attribute::ByVal); diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp index 906bcdf3..816d1705 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp @@ -412,7 +412,7 @@ static std::string getMangledTypeStr(Type* Ty) { std::string Result; if (PointerType* PTyp = dyn_cast(Ty)) { Result += "p" + llvm::utostr(PTyp->getAddressSpace()) + - getMangledTypeStr(PTyp->getElementType()); + getMangledTypeStr(PTyp->getPointerElementType()); } else if (ArrayType* ATyp = dyn_cast(Ty)) { Result += "a" + llvm::utostr(ATyp->getNumElements()) + getMangledTypeStr(ATyp->getElementType()); diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp index 4d154c69..00e59e62 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp @@ -294,7 +294,7 @@ static SPIRVArgDesc analyzeKernelArg(const Argument &Arg) { AddressSpace != SPIRVParams::SPIRVConstantAS) return {SPIRVType::Other}; - Type *PointeeTy = PointerTy->getElementType(); + Type *PointeeTy = PointerTy->getPointerElementType(); // Not a pointer to struct, cannot be sampler or image. if (!isa(PointeeTy)) return {SPIRVType::Pointer}; diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSimdCFLowering.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSimdCFLowering.cpp index fe53aeae..ba6748ab 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSimdCFLowering.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSimdCFLowering.cpp @@ -362,7 +362,7 @@ bool CMSimdCFLowering::doInitialization(Module &M) auto AS1 = LI->getPointerAddressSpace(); if (AS1 != AS0) { auto PtrTy = cast(Ptr->getType()); - PtrTy = PointerType::get(PtrTy->getElementType(), AS0); + PtrTy = PointerType::get(PtrTy->getPointerElementType(), AS0); Ptr = Builder.CreateAddrSpaceCast(Ptr, PtrTy); } Type* Tys[] = { LI->getType(), Ptr->getType() }; @@ -379,7 +379,7 @@ bool CMSimdCFLowering::doInitialization(Module &M) auto AS1 = SI->getPointerAddressSpace(); if (AS1 != AS0) { auto PtrTy = cast(Ptr->getType()); - PtrTy = PointerType::get(PtrTy->getElementType(), AS0); + PtrTy = PointerType::get(PtrTy->getPointerElementType(), AS0); Ptr = Builder.CreateAddrSpaceCast(Ptr, PtrTy); } Type* Tys[] = { SI->getValueOperand()->getType(), Ptr->getType() }; diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp index db83b7be..e8d74f6f 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp @@ -91,7 +91,7 @@ static size_t getPointerNesting(Type *T, Type **ReturnNested = nullptr) { auto NPtrs = size_t{0}; auto *NestedType = T; while (dyn_cast(NestedType)) { - NestedType = cast(NestedType)->getElementType(); + NestedType = cast(NestedType)->getPointerElementType(); ++NPtrs; } if (ReturnNested) @@ -137,8 +137,8 @@ static size_t getInnerPointerVectorNesting(Type *T) { static Type *getTypeFreeFromSingleElementVector(Type *T) { // Pointer types should be "undressed" first if (auto *Ptr = dyn_cast(T)) { - auto UT = getTypeFreeFromSingleElementVector(Ptr->getElementType()); - if (UT == Ptr->getElementType()) + auto UT = getTypeFreeFromSingleElementVector(Ptr->getPointerElementType()); + if (UT == Ptr->getPointerElementType()) return Ptr; return PointerType::get(UT, Ptr->getAddressSpace()); } else if (auto *VecTy = dyn_cast(T)) { @@ -165,8 +165,8 @@ static Type *getTypeWithSingleElementVector(Type *T, size_t InnerPointers = 0) { return VCINTR::getVectorType(T, 1); auto *Ptr = cast(T); - auto *UT = - getTypeWithSingleElementVector(Ptr->getElementType(), InnerPointers); + auto *UT = getTypeWithSingleElementVector(Ptr->getPointerElementType(), + InnerPointers); return PointerType::get(UT, Ptr->getAddressSpace()); } @@ -761,8 +761,8 @@ static void manageSingleElementVectorAttribute(GlobalVariable &GV, Type *OldT, static GlobalVariable &createAndTakeFrom(GlobalVariable &GV, PointerType *NewT, Constant *Initializer) { auto *NewGV = new GlobalVariable( - *GV.getParent(), NewT->getElementType(), GV.isConstant(), GV.getLinkage(), - Initializer, "sev.global.", &GV, GV.getThreadLocalMode(), + *GV.getParent(), NewT->getPointerElementType(), GV.isConstant(), + GV.getLinkage(), Initializer, "sev.global.", &GV, GV.getThreadLocalMode(), GV.getAddressSpace(), GV.isExternallyInitialized()); auto DebugInfoVec = SmallVector{}; GV.getDebugInfo(DebugInfoVec); @@ -808,9 +808,9 @@ static void restoreGlobalVariable(GlobalVariable &GV) { return; auto *Initializer = static_cast(nullptr); if (GV.hasInitializer()) - Initializer = cast( - createScalarToVectorValue(GV.getInitializer(), NewT->getElementType(), - static_cast(nullptr))); + Initializer = cast(createScalarToVectorValue( + GV.getInitializer(), NewT->getPointerElementType(), + static_cast(nullptr))); auto &&NewGV = createAndTakeFrom(GV, NewT, Initializer); while (GV.use_begin() != GV.use_end()) { auto &&Use = GV.use_begin(); From a7270625195501019507017aab17e50f5dac6466 Mon Sep 17 00:00:00 2001 From: Aleksander Us Date: Mon, 14 Feb 2022 13:00:26 +0000 Subject: [PATCH 66/81] Rename exported package Use VCIntrinsics naming scheme for exported package to solve two issues: 1. Exported package does not have LLVM prefix to express that this is not LLVM project code. 2. Exported package has explicit LLVM version in name so potential errors with LLVM versions mismatch can be caught earlier. Old LLVMGenXIntrinsics export is left for backward compatibility. It will be removed later. --- GenXIntrinsics/CMakeLists.txt | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/GenXIntrinsics/CMakeLists.txt b/GenXIntrinsics/CMakeLists.txt index 3c4f9c0f..689e7558 100644 --- a/GenXIntrinsics/CMakeLists.txt +++ b/GenXIntrinsics/CMakeLists.txt @@ -75,9 +75,16 @@ if(INSTALL_REQUIRED) INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} ) + # Legacy export. To remove when all clients switch to new name. install(EXPORT LLVMGenXIntrinsicsTargets FILE LLVMGenXIntrinsicsConfig.cmake DESTINATION ${CMAKE_INSTALL_LIBDIR}/cmake/LLVMGenXIntrinsics ) + + set(PACKAGE_NAME VCIntrinsics${LLVM_VERSION_MAJOR}) + install(EXPORT LLVMGenXIntrinsicsTargets + FILE ${PACKAGE_NAME}Config.cmake + DESTINATION ${CMAKE_INSTALL_LIBDIR}/cmake/${PACKAGE_NAME} + ) endif() # BUILD_EXTERNAL endif() # INSTALL_REQUIRED From 328694af367a35c2ef62b2e10b98e68f4af3897d Mon Sep 17 00:00:00 2001 From: Aleksander Us Date: Mon, 21 Feb 2022 08:00:12 +0000 Subject: [PATCH 67/81] Remove duplication of source list This was a source of build errors at least once. --- .../lib/GenXIntrinsics/CMakeLists.txt | 38 ++++++++----------- 1 file changed, 16 insertions(+), 22 deletions(-) diff --git a/GenXIntrinsics/lib/GenXIntrinsics/CMakeLists.txt b/GenXIntrinsics/lib/GenXIntrinsics/CMakeLists.txt index 32cddf7b..a7b33112 100755 --- a/GenXIntrinsics/lib/GenXIntrinsics/CMakeLists.txt +++ b/GenXIntrinsics/lib/GenXIntrinsics/CMakeLists.txt @@ -13,18 +13,20 @@ set(LLVM_COMPONENTS Analysis ) +set(SRC_LIST + GenXIntrinsics.cpp + GenXRestoreIntrAttr.cpp + GenXSimdCFLowering.cpp + GenXSingleElementVectorUtil.cpp + GenXSPIRVReaderAdaptor.cpp + GenXSPIRVWriterAdaptor.cpp + GenXVersion.cpp + AdaptorsCommon.cpp + GenXMetadata.cpp +) + if(BUILD_EXTERNAL) - add_library(LLVMGenXIntrinsics - GenXIntrinsics.cpp - GenXRestoreIntrAttr.cpp - GenXSimdCFLowering.cpp - GenXSingleElementVectorUtil.cpp - GenXSPIRVReaderAdaptor.cpp - GenXSPIRVWriterAdaptor.cpp - GenXVersion.cpp - AdaptorsCommon.cpp - GenXMetadata.cpp - ) + add_library(LLVMGenXIntrinsics ${SRC_LIST}) llvm_update_compile_flags(LLVMGenXIntrinsics) add_dependencies(LLVMGenXIntrinsics GenXIntrinsicsGen) @@ -43,18 +45,10 @@ else() ) add_llvm_library(LLVMGenXIntrinsics - GenXIntrinsics.cpp - GenXRestoreIntrAttr.cpp - GenXSimdCFLowering.cpp - GenXSingleElementVectorUtil.cpp - GenXSPIRVReaderAdaptor.cpp - GenXSPIRVWriterAdaptor.cpp - GenXVersion.cpp - AdaptorsCommon.cpp - GenXMetadata.cpp - ADDITIONAL_HEADER_DIRS - ${GENX_INTRINSICS_MAIN_INCLUDE_DIR}/llvm/GenXIntrinsics + ${SRC_LIST} + ADDITIONAL_HEADER_DIRS + ${GENX_INTRINSICS_MAIN_INCLUDE_DIR}/llvm/GenXIntrinsics DEPENDS GenXIntrinsicsGen intrinsics_gen From e9fa035ea255ee24e3b3ca0dcd00107dc0592378 Mon Sep 17 00:00:00 2001 From: Aleksander Us Date: Mon, 21 Feb 2022 14:57:58 +0000 Subject: [PATCH 68/81] Add interface includes for in-tree mode Unify handling of intrinsics interface includes in both modes. --- GenXIntrinsics/lib/GenXIntrinsics/CMakeLists.txt | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/GenXIntrinsics/lib/GenXIntrinsics/CMakeLists.txt b/GenXIntrinsics/lib/GenXIntrinsics/CMakeLists.txt index a7b33112..b89d1de2 100755 --- a/GenXIntrinsics/lib/GenXIntrinsics/CMakeLists.txt +++ b/GenXIntrinsics/lib/GenXIntrinsics/CMakeLists.txt @@ -32,12 +32,6 @@ if(BUILD_EXTERNAL) vc_get_llvm_targets(LLVM_LIBS ${LLVM_COMPONENTS}) target_link_libraries(LLVMGenXIntrinsics ${LLVM_LIBS}) - - target_include_directories(LLVMGenXIntrinsics PUBLIC - $ - $ - $ - ) else() # when we are building in LLVM infra, we need to conform set(LLVM_LINK_COMPONENTS @@ -54,3 +48,9 @@ else() intrinsics_gen ) endif() + +target_include_directories(LLVMGenXIntrinsics PUBLIC + $ + $ + $ + ) From 3b94702a3e5f627bed3593009a47237ebee50ca5 Mon Sep 17 00:00:00 2001 From: Anton Sidorenko Date: Mon, 21 Feb 2022 14:00:20 +0000 Subject: [PATCH 69/81] Correct/improve lsc messages documentation * add one missing caching behavior (.ca) * separate caching documentation for loads and stores --- .../GenXIntrinsics/Intrinsic_definitions.py | 55 +++++++++++++++---- 1 file changed, 44 insertions(+), 11 deletions(-) diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py index 087898cf..590a8d8c 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py @@ -1900,10 +1900,11 @@ ### ### - 0 -> .df (default) ### - 1 -> .uc (uncached) -### - 2 -> .wb (writeback) -### - 3 -> .wt (writethrough) -### - 4 -> .st (streaming) -### - 5 -> .ri (read-invalidate) +### - 2 -> .ca (cached) +### - 3 -> .wb (writeback) +### - 4 -> .wt (writethrough) +### - 5 -> .st (streaming) +### - 6 -> .ri (read-invalidate) ### ### Only certain combinations of CachingL1 with CachingL3 are valid on hardware. ### @@ -1912,19 +1913,19 @@ ### +---------+-----+-----------------------------------------------------------------------+ ### | .df | .df | default behavior on both L1 and L3 (L3 uses MOCS settings) | ### +---------+-----+-----------------------------------------------------------------------+ -### | .ri/.wb | .wb | read-invalidate on reads (e.g. last use) / writeback on Stores for L1 | -### +---------+-----+-----------------------------------------------------------------------+ ### | .uc | .uc | uncached (bypass) both L1 and L3 | ### +---------+-----+-----------------------------------------------------------------------+ -### | .uc | .wb | bypass L1 / writeback L3 | +### | .st | .uc | streaming L1 / bypass L3 | ### +---------+-----+-----------------------------------------------------------------------+ -### | .wt | .uc | writethrough L1 / bypass L3 | +### | .uc | .ca | bypass L1 / cache in L3 | ### +---------+-----+-----------------------------------------------------------------------+ -### | .wt | .wb | writethrough L1 / writeback L3 | +### | .ca | .uc | cache in L1 / bypass L3 | ### +---------+-----+-----------------------------------------------------------------------+ -### | .st | .uc | streaming L1 / bypass L3 | +### | .ca | .ca | cache in both L1 and L3 | ### +---------+-----+-----------------------------------------------------------------------+ -### | .st | .wb | streaming L1 / writeback L3 | +### | .st | .ca | streaming L1 / cache in L3 | +### +---------+-----+-----------------------------------------------------------------------+ +### | .ri | .ca | read-invalidate (e.g. last-use) on L1 loads / cache in L3 | ### +---------+-----+-----------------------------------------------------------------------+ ### ### Immediate offset. The compiler may be able to fuse this add into the message, otherwise @@ -2014,6 +2015,38 @@ ### for flat and bindless version pass zero here ### ### * Return value: void +### +### Cache mappings are: +### +### - 0 -> .df (default) +### - 1 -> .uc (uncached) +### - 2 -> .ca (cached) +### - 3 -> .wb (writeback) +### - 4 -> .wt (writethrough) +### - 5 -> .st (streaming) +### - 6 -> .ri (read-invalidate) +### +### Only certain combinations of CachingL1 with CachingL3 are valid on hardware. +### +### +---------+-----+-----------------------------------------------------------------------+ +### | L1 | L3 | Notes | +### +---------+-----+-----------------------------------------------------------------------+ +### | .df | .df | default behavior on both L1 and L3 (L3 uses MOCS settings) | +### +---------+-----+-----------------------------------------------------------------------+ +### | .uc | .uc | uncached (bypass) both L1 and L3 | +### +---------+-----+-----------------------------------------------------------------------+ +### | .st | .uc | streaming L1 / bypass L3 | +### +---------+-----+-----------------------------------------------------------------------+ +### | .uc | .wb | bypass L1/ writeback L3 | +### +---------+-----+-----------------------------------------------------------------------+ +### | .wt | .uc | writethrough L1 / bypass L3 | +### +---------+-----+-----------------------------------------------------------------------+ +### | .wt | .wb | writethrough L1 / writeback L3 | +### +---------+-----+-----------------------------------------------------------------------+ +### | .st | .wb | streaming L1 / writeback L3 | +### +---------+-----+-----------------------------------------------------------------------+ +### | .wb | .wb | writeback both L1 and L3 | +### +---------+-----+-----------------------------------------------------------------------+ ### "lsc_store_slm" : { "result" : "void", "arguments" : ["any","char","char","char","short","int","char","char","char","char","any","anyvector","int"], From 8db834532b07d306c54e61c6b77ac74a4a792f4d Mon Sep 17 00:00:00 2001 From: Igor Gorban Date: Fri, 25 Feb 2022 21:30:45 +0000 Subject: [PATCH 70/81] Fill debug values in created instructions Fill debug values in created instructions --- .../GenXSingleElementVectorUtil.cpp | 28 ++++++++++++------- 1 file changed, 18 insertions(+), 10 deletions(-) diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp index e8d74f6f..ec1b70d7 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp @@ -201,20 +201,24 @@ static Value *createVectorToScalarValue(Value *Vector, Instruction *InsertBefore, size_t idx = 0) { assert(hasSingleElementVector(Vector->getType())); + Instruction *Val = nullptr; if (isa(Vector)) return UndefValue::get( getTypeFreeFromSingleElementVector(Vector->getType())); else if (isa(Vector->getType())) - return new BitCastInst( - Vector, getTypeFreeFromSingleElementVector(Vector->getType()), - "sev.cast.", InsertBefore); + Val = new BitCastInst(Vector, + getTypeFreeFromSingleElementVector(Vector->getType()), + "sev.cast.", InsertBefore); else if (auto *Const = dyn_cast(Vector)) return Const->getAggregateElement(idx); else { auto *M = InsertBefore->getModule(); - return ExtractElementInst::Create(Vector, getVectorIndex(*M, idx), - "sev.cast.", InsertBefore); + Val = ExtractElementInst::Create(Vector, getVectorIndex(*M, idx), + "sev.cast.", InsertBefore); } + if (auto *InVector = dyn_cast(Vector)) + Val->setDebugLoc(InVector->getDebugLoc()); + return Val; } // This util accepts SEV-rich Value and returns new, SEV-free one @@ -224,20 +228,24 @@ static Value *createVectorToScalarValue(Value *Vector, static Value *createVectorToScalarValue(Value *Vector, BasicBlock *BB, size_t idx = 0) { assert(hasSingleElementVector(Vector->getType())); + Instruction *Val = nullptr; if (isa(Vector)) return UndefValue::get( getTypeFreeFromSingleElementVector(Vector->getType())); else if (isa(Vector->getType())) - return new BitCastInst( - Vector, getTypeFreeFromSingleElementVector(Vector->getType()), - "sev.cast.", BB); + Val = new BitCastInst(Vector, + getTypeFreeFromSingleElementVector(Vector->getType()), + "sev.cast.", BB); else if (auto *Const = dyn_cast(Vector)) return Const->getAggregateElement(idx); else { auto *M = BB->getModule(); - return ExtractElementInst::Create(Vector, getVectorIndex(*M, idx), - "sev.cast.", BB); + Val = ExtractElementInst::Create(Vector, getVectorIndex(*M, idx), + "sev.cast.", BB); } + if (auto *InVector = dyn_cast(Vector)) + Val->setDebugLoc(InVector->getDebugLoc()); + return Val; } // This util accepts Scalar Value and returns new SEV-rich Value From 99ac111c2604a47d865bd4d7996be8cfaf2af146 Mon Sep 17 00:00:00 2001 From: Anatoly Parshintsev Date: Wed, 16 Mar 2022 09:37:03 +0000 Subject: [PATCH 71/81] add PVCXT_A0 platfrom add PVCXT_A0 platform and refactor the list initialization to simplify maintenance --- .../include/llvm/GenXIntrinsics/Intrinsics.py | 25 ++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py index 3e084255..92fc783e 100755 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py @@ -78,9 +78,28 @@ # order does really matter. # It is used to define ordering between the respected platforms -platform_list = ["HSW", "BDW", "CHV", "SKL", "BXT", "KBL", - "GLK", "CNL", "ICL", "ICLLP", "TGLLP", "RKL", "DG1", - "ADLP", "ADLS", "XEHP", "DG2", "PVC", "PVCXT"] +platform_list = [ + "HSW", + "BDW", + "CHV", + "SKL", + "BXT", + "KBL", + "GLK", + "CNL", + "ICL", + "ICLLP", + "TGLLP", + "RKL", + "DG1", + "ADLP", + "ADLS", + "XEHP", + "DG2", + "PVC", + "PVCXT_A0", + "PVCXT", +] def getAttributeList(Attrs): """ From c97396d044a8b3eacf0fbad5395a4b7bbce583a8 Mon Sep 17 00:00:00 2001 From: Ilya Andreev Date: Wed, 30 Mar 2022 17:19:41 +0300 Subject: [PATCH 72/81] Extend GenXIntrinsics interface Add some functions to get LSC special argument indices. Add function to get encoded LSCVectorSize. --- .../llvm/GenXIntrinsics/GenXIntrinsics.h | 160 ++++++++++++++++++ .../lib/GenXIntrinsics/GenXIntrinsics.cpp | 95 +++-------- 2 files changed, 181 insertions(+), 74 deletions(-) diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h index e451ec35..cf5cdc37 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h @@ -657,6 +657,166 @@ inline bool isLSC2D(const Function *F) { return isLSC2D(getGenXIntrinsicID(F)); } + +// Dependency from visa_igc_common_header. +// Converts vector size into LSC-appropriate code. +inline LSCVectorSize getLSCVectorSize(unsigned N) { + switch (N) { + case 0: + return LSCVectorSize::N0; + case 1: + return LSCVectorSize::N1; + case 2: + return LSCVectorSize::N2; + case 3: + return LSCVectorSize::N3; + case 4: + return LSCVectorSize::N4; + case 8: + return LSCVectorSize::N8; + case 16: + return LSCVectorSize::N16; + case 32: + return LSCVectorSize::N32; + case 64: + return LSCVectorSize::N64; + } + llvm_unreachable("Unknown vector size"); +} +// Gets encoded vector size for LSC instruction. +inline uint8_t getEncodedLSCVectorSize(unsigned N) { + return static_cast(getLSCVectorSize(N)); +} + +// Functions in this namespace return argument index for LSC instruction. +namespace LSCArgIdx { +constexpr int Invalid = -1; +// Returns VectorSize index. +inline int getLSCVectorSize(LSCCategory Cat) { + switch (Cat) { + case LSCCategory::Load: + case LSCCategory::Prefetch: + case LSCCategory::Store: + case LSCCategory::Atomic: + return 7; + case LSCCategory::LegacyAtomic: + return 8; + case LSCCategory::Prefetch2D: + case LSCCategory::Load2D: + case LSCCategory::Store2D: + case LSCCategory::Fence: + case LSCCategory::NotLSC: + default: + llvm_unreachable("no such argument"); + return Invalid; + } +} +// Returns VectorSize index. +inline int getLSCVectorSize(unsigned IID) { + return LSCArgIdx::getLSCVectorSize(getLSCCategory(IID)); +} + +// Returns DataSize index. +inline int getLSCDataSize(LSCCategory Cat) { + switch (Cat) { + case LSCCategory::Load: + case LSCCategory::Prefetch: + case LSCCategory::Store: + case LSCCategory::LegacyAtomic: + case LSCCategory::Atomic: + return 6; + case LSCCategory::Load2D: + case LSCCategory::Prefetch2D: + case LSCCategory::Store2D: + return 3; + case LSCCategory::Fence: + case LSCCategory::NotLSC: + default: + llvm_unreachable("no such argument"); + return Invalid; + } +} +// Returns DataSize index. +inline int getLSCDataSize(unsigned IID) { + return LSCArgIdx::getLSCDataSize(getLSCCategory(IID)); +} + +// Returns immediate offset index. +inline int getLSCImmOffset(LSCCategory Cat) { + switch (Cat) { + case LSCCategory::Load: + case LSCCategory::Prefetch: + case LSCCategory::Store: + case LSCCategory::LegacyAtomic: + case LSCCategory::Atomic: + return 5; + case LSCCategory::Prefetch2D: + case LSCCategory::Load2D: + case LSCCategory::Store2D: + case LSCCategory::Fence: + case LSCCategory::NotLSC: + default: + llvm_unreachable("no such argument"); + return Invalid; + } +} +// Returns immediate offset index. +inline int getLSCImmOffset(unsigned IID) { + return LSCArgIdx::getLSCImmOffset(getLSCCategory(IID)); +} + +// Returns data order index. +inline int getLSCDataOrder(LSCCategory Cat) { + switch (Cat) { + case LSCCategory::Load: + case LSCCategory::Prefetch: + case LSCCategory::Store: + case LSCCategory::Atomic: + return 8; + case LSCCategory::LegacyAtomic: + return 7; + case LSCCategory::Load2D: + case LSCCategory::Prefetch2D: + case LSCCategory::Store2D: + return 4; + case LSCCategory::Fence: + case LSCCategory::NotLSC: + default: + llvm_unreachable("no such argument"); + return Invalid; + } +} +// Returns data order index. +inline int getLSCDataOrder(unsigned IID) { + return LSCArgIdx::getLSCDataOrder(getLSCCategory(IID)); +} + +// Returns width index. +inline int getLSCWidth(LSCCategory Cat) { + switch (Cat) { + case LSCCategory::Load: + case LSCCategory::Prefetch: + case LSCCategory::Store: + case LSCCategory::Fence: + case LSCCategory::LegacyAtomic: + case LSCCategory::Atomic: + case LSCCategory::Prefetch2D: + return 0; + case LSCCategory::Load2D: + case LSCCategory::Store2D: + case LSCCategory::NotLSC: + default: + llvm_unreachable("no such argument"); + return Invalid; + } +} +// Returns width index. +inline int getLSCWidth(unsigned IID) { + return LSCArgIdx::getLSCWidth(getLSCCategory(IID)); +} + +} // namespace LSCArgIdx + inline unsigned getLSCNumVectorElements(LSCVectorSize VS) { switch (VS) { case LSCVectorSize::N0: diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp index 816d1705..118a27e8 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp @@ -688,93 +688,40 @@ std::string GenXIntrinsic::getAnyName(unsigned id, ArrayRef Tys) { GenXIntrinsic::LSCVectorSize GenXIntrinsic::getLSCVectorSize( const Instruction *I) { assert(isLSC(I)); - switch (getLSCCategory(I)) { - case LSCCategory::Load: - case LSCCategory::Prefetch: - case LSCCategory::Store: - case LSCCategory::Atomic: - return static_cast( - cast(I->getOperand(7))->getZExtValue()); - case LSCCategory::LegacyAtomic: - return static_cast( - cast(I->getOperand(8))->getZExtValue()); - case LSCCategory::Fence: - case LSCCategory::Load2D: - case LSCCategory::Prefetch2D: - case LSCCategory::Store2D: - case LSCCategory::NotLSC: - return LSCVectorSize::N0; - } - llvm_unreachable("Unknown LSC category"); + const int VectorSizeIdx = LSCArgIdx::getLSCVectorSize(getLSCCategory(I)); + if (VectorSizeIdx == LSCArgIdx::Invalid) + return LSCVectorSize::N0; + return static_cast( + cast(I->getOperand(VectorSizeIdx))->getZExtValue()); } GenXIntrinsic::LSCDataSize GenXIntrinsic::getLSCDataSize( const Instruction *I) { assert(isLSC(I)); - switch (getLSCCategory(I)) { - case LSCCategory::Load: - case LSCCategory::Prefetch: - case LSCCategory::Store: - case LSCCategory::LegacyAtomic: - case LSCCategory::Atomic: - return static_cast( - cast(I->getOperand(6))->getZExtValue()); - case LSCCategory::Load2D: - case LSCCategory::Prefetch2D: - case LSCCategory::Store2D: - return static_cast( - cast(I->getOperand(3))->getZExtValue()); - case LSCCategory::Fence: - case LSCCategory::NotLSC: - return LSCDataSize::Invalid; - } - llvm_unreachable("Unknown LSC category"); + const int DataSizeIdx = LSCArgIdx::getLSCDataSize(getLSCCategory(I)); + if (DataSizeIdx == LSCArgIdx::Invalid) + return LSCDataSize::Invalid; + return static_cast( + cast(I->getOperand(DataSizeIdx))->getZExtValue()); } GenXIntrinsic::LSCDataOrder GenXIntrinsic::getLSCDataOrder( const Instruction *I) { assert(isLSC(I)); - switch (getLSCCategory(I)) { - case LSCCategory::Load: - case LSCCategory::Prefetch: - case LSCCategory::Store: - case LSCCategory::Atomic: - return static_cast( - cast(I->getOperand(8))->getZExtValue()); - case LSCCategory::LegacyAtomic: - return static_cast( - cast(I->getOperand(7))->getZExtValue()); - case LSCCategory::Load2D: - case LSCCategory::Prefetch2D: - case LSCCategory::Store2D: - return static_cast( - cast(I->getOperand(4))->getZExtValue()); - case LSCCategory::Fence: - case LSCCategory::NotLSC: - return LSCDataOrder::Invalid; - } - llvm_unreachable("Unknown LSC category"); + const int DataOrderIdx = LSCArgIdx::getLSCDataOrder(getLSCCategory(I)); + if (DataOrderIdx == LSCArgIdx::Invalid) + return LSCDataOrder::Invalid; + return static_cast( + cast(I->getOperand(DataOrderIdx))->getZExtValue()); } unsigned GenXIntrinsic::getLSCWidth(const Instruction *I) { assert(isLSC(I)); - switch(getLSCCategory(I)) { - case LSCCategory::Load: - case LSCCategory::Prefetch: - case LSCCategory::Store: - case LSCCategory::Fence: - case LSCCategory::LegacyAtomic: - case LSCCategory::Atomic: { - case LSCCategory::Prefetch2D: - if (auto VT = dyn_cast(I->getOperand(0)->getType())) - return VCINTR::VectorType::getNumElements(VT); - return 1; - } - case LSCCategory::Load2D: - case LSCCategory::Store2D: - case LSCCategory::NotLSC: - return 1; - } - llvm_unreachable("Unknown LSC category"); + const int WidthIdx = LSCArgIdx::getLSCWidth(getLSCCategory(I)); + if (WidthIdx == LSCArgIdx::Invalid) + return 1; + if (auto VT = dyn_cast(I->getOperand(WidthIdx)->getType())) + return VCINTR::VectorType::getNumElements(VT); + return 1; } From 7bcfff9051cabd44cf0691d4f3b7a3ef0cd9789e Mon Sep 17 00:00:00 2001 From: Kaiyu Chen Date: Fri, 22 Apr 2022 11:33:29 -0700 Subject: [PATCH 73/81] [ESIMD] Add slm_init intrinsic for variable slm size support. --- .../llvm/GenXIntrinsics/Intrinsic_definitions.py | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py index 590a8d8c..b354bf94 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py @@ -1869,6 +1869,16 @@ "attributes" : "NoMem" }, +### ``llvm.genx.slm.init`` : slm_init instruction +### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +### +### * arg0: slm size, i32 scalar integer type +### + "slm_init" : { "result" : "void", + "arguments" : ["int"], + "attributes" : "None" + }, + ### ``llvm.genx.lsc.load.*...`` : lsc_load instructions ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ### From 1e2562d87528e1870ea2ad7197e4cc0346192e22 Mon Sep 17 00:00:00 2001 From: Victor Mustya Date: Mon, 25 Apr 2022 20:34:16 +0000 Subject: [PATCH 74/81] Restore intrinsics order External intrinsics order is expected to be unchanged to keep SPIR-V compatibility. --- .../GenXIntrinsics/Intrinsic_definitions.py | 20 +++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py index b354bf94..6d09b35b 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py @@ -1869,16 +1869,6 @@ "attributes" : "NoMem" }, -### ``llvm.genx.slm.init`` : slm_init instruction -### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -### -### * arg0: slm size, i32 scalar integer type -### - "slm_init" : { "result" : "void", - "arguments" : ["int"], - "attributes" : "None" - }, - ### ``llvm.genx.lsc.load.*...`` : lsc_load instructions ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ### @@ -5432,4 +5422,14 @@ "arguments" : ["anyint", 1, 1], "attributes" : "NoMem" }, + +### ``llvm.genx.slm.init`` : slm_init instruction +### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +### +### * arg0: slm size, i32 scalar integer type +### + "slm_init" : { "result" : "void", + "arguments" : ["int"], + "attributes" : "None" + }, } From 561f4ff575a198b36a72fcb790e1997d7d6d6c91 Mon Sep 17 00:00:00 2001 From: Victor Mustya Date: Tue, 3 May 2022 17:56:40 +0000 Subject: [PATCH 75/81] Remove default switch labels for LSC-related functions Build might fail because of `-Werror -Wcovered-switch-default` options passed to gcc and clang --- GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h | 5 ----- 1 file changed, 5 deletions(-) diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h index cf5cdc37..e0d29161 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h @@ -706,7 +706,6 @@ inline int getLSCVectorSize(LSCCategory Cat) { case LSCCategory::Store2D: case LSCCategory::Fence: case LSCCategory::NotLSC: - default: llvm_unreachable("no such argument"); return Invalid; } @@ -731,7 +730,6 @@ inline int getLSCDataSize(LSCCategory Cat) { return 3; case LSCCategory::Fence: case LSCCategory::NotLSC: - default: llvm_unreachable("no such argument"); return Invalid; } @@ -755,7 +753,6 @@ inline int getLSCImmOffset(LSCCategory Cat) { case LSCCategory::Store2D: case LSCCategory::Fence: case LSCCategory::NotLSC: - default: llvm_unreachable("no such argument"); return Invalid; } @@ -781,7 +778,6 @@ inline int getLSCDataOrder(LSCCategory Cat) { return 4; case LSCCategory::Fence: case LSCCategory::NotLSC: - default: llvm_unreachable("no such argument"); return Invalid; } @@ -805,7 +801,6 @@ inline int getLSCWidth(LSCCategory Cat) { case LSCCategory::Load2D: case LSCCategory::Store2D: case LSCCategory::NotLSC: - default: llvm_unreachable("no such argument"); return Invalid; } From 1fad747bd864f302407935f692fc92a4c5755ee5 Mon Sep 17 00:00:00 2001 From: Victor Mustya Date: Tue, 10 May 2022 21:09:28 +0000 Subject: [PATCH 76/81] Fix LSC helpers Correctly handle LSC 2d stateless intrinsics --- GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h index e0d29161..70115d74 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h @@ -796,10 +796,10 @@ inline int getLSCWidth(LSCCategory Cat) { case LSCCategory::Fence: case LSCCategory::LegacyAtomic: case LSCCategory::Atomic: - case LSCCategory::Prefetch2D: - return 0; case LSCCategory::Load2D: + case LSCCategory::Prefetch2D: case LSCCategory::Store2D: + return 0; case LSCCategory::NotLSC: llvm_unreachable("no such argument"); return Invalid; From 4ce354da51f219bbdfa9c4cd5d8f640e92e38511 Mon Sep 17 00:00:00 2001 From: Victor Mustya Date: Wed, 11 May 2022 23:12:22 +0000 Subject: [PATCH 77/81] Fix for build as part of igc IGC build used to fail because of warnings/errors emitted by gcc --- GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h index 70115d74..48ab26cf 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h @@ -709,6 +709,7 @@ inline int getLSCVectorSize(LSCCategory Cat) { llvm_unreachable("no such argument"); return Invalid; } + return Invalid; } // Returns VectorSize index. inline int getLSCVectorSize(unsigned IID) { @@ -733,6 +734,7 @@ inline int getLSCDataSize(LSCCategory Cat) { llvm_unreachable("no such argument"); return Invalid; } + return Invalid; } // Returns DataSize index. inline int getLSCDataSize(unsigned IID) { @@ -756,6 +758,7 @@ inline int getLSCImmOffset(LSCCategory Cat) { llvm_unreachable("no such argument"); return Invalid; } + return Invalid; } // Returns immediate offset index. inline int getLSCImmOffset(unsigned IID) { @@ -781,6 +784,7 @@ inline int getLSCDataOrder(LSCCategory Cat) { llvm_unreachable("no such argument"); return Invalid; } + return Invalid; } // Returns data order index. inline int getLSCDataOrder(unsigned IID) { @@ -804,6 +808,7 @@ inline int getLSCWidth(LSCCategory Cat) { llvm_unreachable("no such argument"); return Invalid; } + return Invalid; } // Returns width index. inline int getLSCWidth(unsigned IID) { From abce9184b7a3a7fe1b02289b9285610d9dc45465 Mon Sep 17 00:00:00 2001 From: Haohai Wen Date: Fri, 10 Jun 2022 03:46:22 +0000 Subject: [PATCH 78/81] Format InstructionSimplify names N/A --- .../Analysis/InstructionSimplify.h | 49 +++++++++++++++++++ .../GenXSingleElementVectorUtil.cpp | 9 ++-- 2 files changed, 54 insertions(+), 4 deletions(-) create mode 100644 GenXIntrinsics/include/llvmVCWrapper/Analysis/InstructionSimplify.h diff --git a/GenXIntrinsics/include/llvmVCWrapper/Analysis/InstructionSimplify.h b/GenXIntrinsics/include/llvmVCWrapper/Analysis/InstructionSimplify.h new file mode 100644 index 00000000..9933fd38 --- /dev/null +++ b/GenXIntrinsics/include/llvmVCWrapper/Analysis/InstructionSimplify.h @@ -0,0 +1,49 @@ +/*========================== begin_copyright_notice ============================ + +Copyright (C) 2022 Intel Corporation + +SPDX-License-Identifier: MIT + +============================= end_copyright_notice ===========================*/ + +#ifndef VCINTR_ANALYSIS_INSTRUCTIONSIMPLIFY_H +#define VCINTR_ANALYSIS_INSTRUCTIONSIMPLIFY_H + +#include + +namespace VCINTR { + +inline llvm::Value *SimplifyInsertElementInst(llvm::Value *Vec, + llvm::Value *Elt, + llvm::Value *Idx, + const llvm::SimplifyQuery &Q) { +#if VC_INTR_LLVM_VERSION_MAJOR <= 14 + return llvm::SimplifyInsertElementInst(Vec, Elt, Idx, Q); +#else + return llvm::simplifyInsertElementInst(Vec, Elt, Idx, Q); +#endif +} + +inline llvm::Value *SimplifyExtractElementInst(llvm::Value *Vec, + llvm::Value *Idx, + const llvm::SimplifyQuery &Q) { +#if VC_INTR_LLVM_VERSION_MAJOR <= 14 + return llvm::SimplifyExtractElementInst(Vec, Idx, Q); +#else + return llvm::simplifyExtractElementInst(Vec, Idx, Q); +#endif +} + +inline llvm::Value *SimplifyCastInst(unsigned CastOpc, llvm::Value *Op, + llvm::Type *Ty, + const llvm::SimplifyQuery &Q) { +#if VC_INTR_LLVM_VERSION_MAJOR <= 14 + return llvm::SimplifyCastInst(CastOpc, Op, Ty, Q); +#else + return llvm::simplifyCastInst(CastOpc, Op, Ty, Q); +#endif +} + +} // namespace VCINTR + +#endif // VCINTR_ANALYSIS_INSTRUCTIONSIMPLIFY_H diff --git a/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp b/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp index ec1b70d7..fa3ef25c 100644 --- a/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp +++ b/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp @@ -22,6 +22,7 @@ SPDX-License-Identifier: MIT #include "llvm/IR/Module.h" #include "llvm/Pass.h" +#include "llvmVCWrapper/Analysis/InstructionSimplify.h" #include "llvmVCWrapper/IR/Attributes.h" #include "llvmVCWrapper/IR/DerivedTypes.h" #include "llvmVCWrapper/IR/Function.h" @@ -852,7 +853,7 @@ static void collapseBitcastInst(BitCastInst *BitCast, bool CollapseCannotFail) { } auto &&M = *BitCast->getModule(); auto &&Q = SimplifyQuery(M.getDataLayout()); - auto *ReplaceWith = SimplifyCastInst( + auto *ReplaceWith = VCINTR::SimplifyCastInst( BitCast->getOpcode(), BitCast->getOperand(0), BitCast->getType(), Q); if (!CollapseCannotFail && !ReplaceWith) return; @@ -893,8 +894,8 @@ static void collapseExtractInst(ExtractElementInst *Extract, } auto &&M = *Extract->getModule(); auto &&Q = SimplifyQuery(M.getDataLayout()); - auto *ReplaceWith = SimplifyExtractElementInst(Extract->getOperand(0), - Extract->getOperand(1), Q); + auto *ReplaceWith = VCINTR::SimplifyExtractElementInst( + Extract->getOperand(0), Extract->getOperand(1), Q); if (!CollapseCannotFail && !ReplaceWith) return; assert(ReplaceWith && "Oops... Cannot collapse ExtractElement instruction"); @@ -910,7 +911,7 @@ static void collapseInsertInst(InsertElementInst *Insert, } auto &&M = *Insert->getModule(); auto &&Q = SimplifyQuery(M.getDataLayout()); - auto *ReplaceWith = SimplifyInsertElementInst( + auto *ReplaceWith = VCINTR::SimplifyInsertElementInst( Insert->getOperand(0), Insert->getOperand(1), Insert->getOperand(2), Q); // SimplifyInsertElementInst provides too simple analysis From 984bb27baacce6ee5c716c2e64845f2a1928025b Mon Sep 17 00:00:00 2001 From: Victor Mustya Date: Fri, 17 Jun 2022 22:39:49 +0000 Subject: [PATCH 79/81] Support ADLN platform --- GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py | 1 + 1 file changed, 1 insertion(+) diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py index 92fc783e..68738dd5 100755 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py @@ -94,6 +94,7 @@ "DG1", "ADLP", "ADLS", + "ADLN", "XEHP", "DG2", "PVC", From c456ff05bd8e11458772acef20e59ef18aa7876d Mon Sep 17 00:00:00 2001 From: fineg74 <61437305+fineg74@users.noreply.github.com> Date: Wed, 6 Jul 2022 05:30:55 +0000 Subject: [PATCH 80/81] Add support for LLVM_LINK_LLVM_DYLIB option Toolchain build used to fail when LLVM_LINK_LLVM_DYLIB is enabled --- .../lib/GenXIntrinsics/CMakeLists.txt | 35 ++++++++++++++----- 1 file changed, 26 insertions(+), 9 deletions(-) diff --git a/GenXIntrinsics/lib/GenXIntrinsics/CMakeLists.txt b/GenXIntrinsics/lib/GenXIntrinsics/CMakeLists.txt index b89d1de2..9b48788f 100755 --- a/GenXIntrinsics/lib/GenXIntrinsics/CMakeLists.txt +++ b/GenXIntrinsics/lib/GenXIntrinsics/CMakeLists.txt @@ -38,15 +38,32 @@ else() ${LLVM_COMPONENTS} ) - add_llvm_library(LLVMGenXIntrinsics - ${SRC_LIST} - - ADDITIONAL_HEADER_DIRS - ${GENX_INTRINSICS_MAIN_INCLUDE_DIR}/llvm/GenXIntrinsics - DEPENDS - GenXIntrinsicsGen - intrinsics_gen - ) + if(LLVM_LINK_LLVM_DYLIB) + add_llvm_library(LLVMGenXIntrinsics STATIC DISABLE_LLVM_LINK_LLVM_DYLIB + ${SRC_LIST} + + ADDITIONAL_HEADER_DIRS + ${GENX_INTRINSICS_MAIN_INCLUDE_DIR}/llvm/GenXIntrinsics + DEPENDS + GenXIntrinsicsGen + intrinsics_gen + LLVMCodeGen + LLVMSupport + LLVMCore + LLVMAnalysis + LLVMSPIRVLib + ) + else() + add_llvm_library(LLVMGenXIntrinsics + ${SRC_LIST} + + ADDITIONAL_HEADER_DIRS + ${GENX_INTRINSICS_MAIN_INCLUDE_DIR}/llvm/GenXIntrinsics + DEPENDS + GenXIntrinsicsGen + intrinsics_gen + ) + endif() endif() target_include_directories(LLVMGenXIntrinsics PUBLIC From f67c21cbfa5e3b719de0d180f1a8a2adcf849de8 Mon Sep 17 00:00:00 2001 From: "Romanov, Vlad" Date: Wed, 31 Aug 2022 00:25:32 -0700 Subject: [PATCH 81/81] Make intrinsics module searching more robust Portable(or embedded) versions of python doesn't have the script directory in the module search path by default. So, adding expected module directory in the script itself allows the script to work correctly even with such versions of python. --- GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py | 1 + 1 file changed, 1 insertion(+) diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py index 68738dd5..c44ca94f 100755 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py @@ -117,6 +117,7 @@ def getAttributeList(Attrs): #Populate the dictionary with the appropriate Intrinsics if i != 0: if (".py" in parse[i]): + sys.path.append(os.path.split(parse[i])[0]) module = importlib.import_module(os.path.split(parse[i])[1].replace(".py","")) Intrinsics.update(module.Imported_Intrinsics)