Can't convert file with custom types in PORT declaration

[shawnanastasio]

When attempting to translate a VHDL entity whose PORT declaration contains a user defined type using the technique described here: https://stackoverflow.com/questions/16872950/can-custom-types-be-used-in-port-declaration, there is no way to inform vhd2vl of the custom types and translation fails.

Perhaps an extension that allows users to define packages and entities in the same file would provide a workaround for this?