Doesn't understand packages

[hacksterous]

I tried to define a record type in a package file, saved as core_types.vhd:

package core_types is
type CPU_ToRAM is record
memAWriteEnable : std_logic;
memBWrite : std_logic_vector(31 downto 0);
end record;
end package;

Then, in my main file, this package is used as:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.core_types.all;

entity core_flex is
generic (
IMPL_MULTIPLY : boolean -- Self explanatory
);
port (
clk : in std_logic;
reset : in std_logic;
from_rom : in CPU_ToRAM
);
end core_flex;

architecture behave of core_flex is

end behave;

I see an error:

ERROR (line 13): undefined type 'CPU_ToRAM'.