Add `CONVFUNC_1` support

[ApexGP]

See #31 (comment) .

Hi, @ldoolitt . I've managed to make a patch to deal with this issue. You can apply it and see how it goes.

By introducing wrap_sgn_expr(), now vhd2vl will parse conv_integer and to_integer with an $unsigned() or $signed identifier (disabled if implicit) like

assign u = $unsigned(s);
assign i = $signed(s);

If everything is going well, I'll create a PR.

[ApexGP]

Additionally, you can uncomment these two lines in fifo.vhd to verify its functionality:

-------- fifo.vhd#Line 66 to 75 --------
process (clk_WR)
begin
	if (rising_edge(clk_WR)) then
		if ((WR = '1') and (ifull = '0')) then
			ram_mem(to_integer(unsigned(add_WR(3 downto 0)))) <= D;  -- uncomment
		end if;
	end if;
end process;

	Q <= ram_mem(to_integer(unsigned(add_RD(3 downto 0))));  -- uncomment

[ldoolitt]

Looks OK, but limited.

1. Please squelch trailing whitespace in vhd2vl.y.
2. Please update translated_examples/dsp.v.
3. Yes, include that update to fifo.vhd (and the corresponding fifo.v).
4. I could easily confuse new code by saying e.g., u <= conv_integer(unsigned(s)+1); in conv_integer.vhd. The result is still valid Verilog, but the new feature doesn't appear. Not a regression, so maybe OK.

I don't have a good sense of what VHDL code "in the wild" typically does with conv_integer and std_ulogic_vector.

[ApexGP]

Understood, please see #36.&nbsp; 原始邮件 发件人：Larry Doolittle ***@***.***&gt; 发件时间：2026年2月10日 12:24 收件人：ldoolitt/vhd2vl ***@***.***&gt; 抄送：Yunfan Xu ***@***.***&gt;, Author ***@***.***&gt; 主题：Re: [ldoolitt/vhd2vl] Add `CONVFUNC_1` support (Issue #35) ldoolitt left a comment (ldoolitt/vhd2vl#35) Looks OK, but limited. Please squelch trailing whitespace in vhd2vl.y. Please update translated_examples/dsp.v. Yes, include that update to fifo.vhd (and the corresponding fifo.v). I could easily confuse new code by saying e.g., u <= conv_integer(unsigned(s)+1);&nbsp;in conv_integer.vhd. The result is still valid Verilog, but the new feature doesn't appear. Not a regression, so maybe OK. I don't have a good sense of what VHDL code "in the wild" typically does with conv_integer&nbsp;and std_ulogic_vector. — Reply to this email directly, view it on GitHub, or unsubscribe. You are receiving this because you authored the thread.

[ldoolitt]

fixed with commit a6ed1b4 from PR #36