From d11210d6d0a677bc229ba4f94ed8e506c8f3b262 Mon Sep 17 00:00:00 2001 From: Max Hsu Date: Fri, 20 Feb 2026 16:27:05 +0800 Subject: [PATCH 1/5] dt-bindings: net: macb: Add SiFive FU740-C000 support Add the SiFive FU740-C000 ethernet controller compatible string to the Cadence MACB binding documentation. The FU740 ethernet controller uses the same GEMGXL management block as the FU540, which is tightly coupled with the Cadence MACB IP. This follows the SiFive IP versioning scheme which requires SoC-specific compatible strings for proper hardware identification. Signed-off-by: Max Hsu Signed-off-by: Linux RISC-V bot --- Documentation/devicetree/bindings/net/cdns,macb.yaml | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/net/cdns,macb.yaml b/Documentation/devicetree/bindings/net/cdns,macb.yaml index cb14c35ba99693..b46dde1da17088 100644 --- a/Documentation/devicetree/bindings/net/cdns,macb.yaml +++ b/Documentation/devicetree/bindings/net/cdns,macb.yaml @@ -63,6 +63,7 @@ properties: - mobileye,eyeq5-gem # Mobileye EyeQ5 SoCs - raspberrypi,rp1-gem # Raspberry Pi RP1 gigabit ethernet interface - sifive,fu540-c000-gem # SiFive FU540-C000 SoC + - sifive,fu740-c000-gem # SiFive FU740-C000 SoC - items: - enum: @@ -74,7 +75,7 @@ properties: minItems: 1 items: - description: Basic register set - - description: GEMGXL Management block registers on SiFive FU540-C000 SoC + - description: GEMGXL Management block registers on SiFive FU540/FU740 SoCs interrupts: minItems: 1 @@ -181,7 +182,9 @@ allOf: properties: compatible: contains: - const: sifive,fu540-c000-gem + enum: + - sifive,fu540-c000-gem + - sifive,fu740-c000-gem then: properties: reg: From dcf39093d979d2f8335ba64d38da44769bc25106 Mon Sep 17 00:00:00 2001 From: Max Hsu Date: Fri, 20 Feb 2026 16:27:06 +0800 Subject: [PATCH 2/5] dt-bindings: interrupt-controller: Add SiFive FU740-C000 PLIC Add the SiFive FU740-C000 PLIC compatible string to the binding documentation. This follows the SiFive IP versioning scheme which requires SoC-specific compatible strings for proper hardware identification, even when the IP blocks are functionally identical. Signed-off-by: Max Hsu Signed-off-by: Linux RISC-V bot --- .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index e0267223887ec2..351d26ab19563a 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -63,6 +63,7 @@ properties: - eswin,eic7700-plic - microchip,pic64gx-plic - sifive,fu540-c000-plic + - sifive,fu740-c000-plic - spacemit,k1-plic - starfive,jh7100-plic - starfive,jh7110-plic From 9f0cc4fa144e0a1da1db808a86790e1bfdddb81a Mon Sep 17 00:00:00 2001 From: Max Hsu Date: Fri, 20 Feb 2026 16:27:07 +0800 Subject: [PATCH 3/5] net: macb: Add support for SiFive FU740-C000 Add a distinct configuration for the SiFive FU740-C000 ethernet controller to comply with the SiFive IP versioning guidelines. The FU740 ethernet controller uses the same management IP block as the FU540, which is tightly coupled with the Cadence MACB IP and manages boundary signals. To avoid code duplication while maintaining distinct SoC identification, this patch: - Renames sifive_fu540_macb_mgmt to sifive_macb_mgmt to reflect that it's shared between FU540 and FU740 - Adds a fu740_c000_config structure that reuses the FU540 initialization functions - Follows the established pattern in this driver where multiple SoC configs share the same init functions Signed-off-by: Max Hsu Signed-off-by: Linux RISC-V bot --- drivers/net/ethernet/cadence/macb_main.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c index 43cd013bb70e6b..10d049391a73f8 100644 --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c @@ -39,8 +39,8 @@ #include #include "macb.h" -/* This structure is only used for MACB on SiFive FU540 devices */ -struct sifive_fu540_macb_mgmt { +/* This structure is used for MACB on SiFive FU540/FU740 devices */ +struct sifive_macb_mgmt { void __iomem *reg; unsigned long rate; struct clk_hw hw; @@ -4650,7 +4650,7 @@ static const struct macb_usrio_config macb_default_usrio = { /* max number of receive buffers */ #define AT91ETHER_MAX_RX_DESCR 9 -static struct sifive_fu540_macb_mgmt *mgmt; +static struct sifive_macb_mgmt *mgmt; static int at91ether_alloc_coherent(struct macb *lp) { @@ -5236,6 +5236,16 @@ static const struct macb_config fu540_c000_config = { .usrio = &macb_default_usrio, }; +static const struct macb_config fu740_c000_config = { + .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO | + MACB_CAPS_GEM_HAS_PTP, + .dma_burst_length = 16, + .clk_init = fu540_c000_clk_init, + .init = fu540_c000_init, + .jumbo_max_len = 10240, + .usrio = &macb_default_usrio, +}; + static const struct macb_config at91sam9260_config = { .caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII, .clk_init = macb_clk_init, @@ -5411,6 +5421,7 @@ static const struct of_device_id macb_dt_ids[] = { { .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config}, /* deprecated */ { .compatible = "cdns,zynq-gem", .data = &zynq_config }, /* deprecated */ { .compatible = "sifive,fu540-c000-gem", .data = &fu540_c000_config }, + { .compatible = "sifive,fu740-c000-gem", .data = &fu740_c000_config }, { .compatible = "microchip,mpfs-macb", .data = &mpfs_config }, { .compatible = "microchip,sama7g5-gem", .data = &sama7g5_gem_config }, { .compatible = "microchip,sama7g5-emac", .data = &sama7g5_emac_config }, From ccb94c33a9f9fa6a63bdee784c7c1cbe915c805c Mon Sep 17 00:00:00 2001 From: Max Hsu Date: Fri, 20 Feb 2026 16:27:08 +0800 Subject: [PATCH 4/5] riscv: dts: sifive: fu740: Use correct ethernet compatible string Update the ethernet node compatible string from "sifive,fu540-c000-gem" to "sifive,fu740-c000-gem" to comply with the SiFive IP versioning scheme documented in sifive-blocks-ip-versioning.txt. The versioning scheme requires SoC-specific compatible strings even when IP blocks are functionally identical. Signed-off-by: Max Hsu Signed-off-by: Linux RISC-V bot --- arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi index 6150f3397bff92..15e11a03582aeb 100644 --- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi @@ -273,7 +273,7 @@ status = "disabled"; }; eth0: ethernet@10090000 { - compatible = "sifive,fu540-c000-gem"; + compatible = "sifive,fu740-c000-gem"; interrupt-parent = <&plic0>; interrupts = <55>; reg = <0x0 0x10090000 0x0 0x2000>, From 8c6216aae178fb7cf8d7885d2a3517b489b85538 Mon Sep 17 00:00:00 2001 From: Max Hsu Date: Fri, 20 Feb 2026 16:27:09 +0800 Subject: [PATCH 5/5] riscv: dts: sifive: fu740: Use correct PLIC compatible string Update the PLIC compatible string from "sifive,fu540-c000-plic" to "sifive,fu740-c000-plic" to comply with the SiFive IP versioning scheme documented in sifive-blocks-ip-versioning.txt. The versioning scheme requires SoC-specific compatible strings for proper hardware identification. Signed-off-by: Max Hsu Signed-off-by: Linux RISC-V bot --- arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi index 15e11a03582aeb..a44ccbf4822b9c 100644 --- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi @@ -182,7 +182,7 @@ plic0: interrupt-controller@c000000 { #interrupt-cells = <1>; #address-cells = <0>; - compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; + compatible = "sifive,fu740-c000-plic", "sifive,plic-1.0.0"; reg = <0x0 0xc000000 0x0 0x4000000>; riscv,ndev = <69>; interrupt-controller;