[top,rv_core_ibex] Add the Zc* parameter to topgen

SamuelRiedel · SamuelRiedel · commit 3097cd41c17e · 2025-12-23T18:30:35.000+01:00
diff --git a/hw/ip_templates/rv_core_ibex/data/rv_core_ibex.hjson.tpl b/hw/ip_templates/rv_core_ibex/data/rv_core_ibex.hjson.tpl
@@ -367,6 +367,14 @@
       expose:  "true"
     },
 
+    { name:    "RV32ZC"
+      type:    "ibex_pkg::rv32zc_e"
+      default: "ibex_pkg::RV32ZcaZcbZcmp"
+      desc:    "RV32ZC"
+      local:   "false"
+      expose:  "true"
+    },
+
     { name:    "RegFile"
       type:    "ibex_pkg::regfile_e"
       default: "ibex_pkg::RegFileFF"
diff --git a/hw/ip_templates/rv_core_ibex/rtl/rv_core_ibex.sv.tpl b/hw/ip_templates/rv_core_ibex/rtl/rv_core_ibex.sv.tpl
@@ -28,6 +28,7 @@ module ${module_instance_name}
   parameter bit                     RV32E               = 0,
   parameter ibex_pkg::rv32m_e       RV32M               = ibex_pkg::RV32MSingleCycle,
   parameter ibex_pkg::rv32b_e       RV32B               = ibex_pkg::RV32BOTEarlGrey,
+  parameter ibex_pkg::rv32zc_e      RV32ZC              = ibex_pkg::RV32ZcaZcbZcmp,
   parameter ibex_pkg::regfile_e     RegFile             = ibex_pkg::RegFileFF,
   parameter bit                     BranchTargetALU     = 1'b1,
   parameter bit                     WritebackStage      = 1'b1,
@@ -418,6 +419,7 @@ module ${module_instance_name}
     .RV32E                       ( RV32E                    ),
     .RV32M                       ( RV32M                    ),
     .RV32B                       ( RV32B                    ),
+    .RV32ZC                      ( RV32ZC                   ),
     .RegFile                     ( RegFile                  ),
     .BranchTargetALU             ( BranchTargetALU          ),
     .WritebackStage              ( WritebackStage           ),
diff --git a/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson b/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson
@@ -10179,6 +10179,7 @@
         RV32E: "0"
         RV32M: ibex_pkg::RV32MSingleCycle
         RV32B: ibex_pkg::RV32BOTEarlGrey
+        RV32ZC: ibex_pkg::RV32ZcaZcbZcmp
         RegFile: ibex_pkg::RegFileFF
         BranchTargetALU: "1"
         WritebackStage: "1"
@@ -10366,6 +10367,15 @@
           expose: "true"
           name_top: RvCoreIbexRV32B
         }
+        {
+          name: RV32ZC
+          desc: RV32ZC
+          type: ibex_pkg::rv32zc_e
+          default: ibex_pkg::RV32ZcaZcbZcmp
+          local: "false"
+          expose: "true"
+          name_top: RvCoreIbexRV32ZC
+        }
         {
           name: RegFile
           desc: Reg file
diff --git a/hw/top_darjeeling/data/top_darjeeling.hjson b/hw/top_darjeeling/data/top_darjeeling.hjson
@@ -1088,6 +1088,7 @@
                    RV32E: "0",
                    RV32M: "ibex_pkg::RV32MSingleCycle",
                    RV32B: "ibex_pkg::RV32BOTEarlGrey",
+                   RV32ZC: "ibex_pkg::RV32ZcaZcbZcmp",
                    RegFile: "ibex_pkg::RegFileFF",
                    BranchTargetALU: "1",
                    WritebackStage: "1",
diff --git a/hw/top_darjeeling/ip_autogen/rv_core_ibex/data/rv_core_ibex.hjson b/hw/top_darjeeling/ip_autogen/rv_core_ibex/data/rv_core_ibex.hjson
@@ -341,6 +341,14 @@
       expose:  "true"
     },
 
+    { name:    "RV32ZC"
+      type:    "ibex_pkg::rv32zc_e"
+      default: "ibex_pkg::RV32ZcaZcbZcmp"
+      desc:    "RV32ZC"
+      local:   "false"
+      expose:  "true"
+    },
+
     { name:    "RegFile"
       type:    "ibex_pkg::regfile_e"
       default: "ibex_pkg::RegFileFF"
diff --git a/hw/top_darjeeling/ip_autogen/rv_core_ibex/rtl/rv_core_ibex.sv b/hw/top_darjeeling/ip_autogen/rv_core_ibex/rtl/rv_core_ibex.sv
@@ -28,6 +28,7 @@ module rv_core_ibex
   parameter bit                     RV32E               = 0,
   parameter ibex_pkg::rv32m_e       RV32M               = ibex_pkg::RV32MSingleCycle,
   parameter ibex_pkg::rv32b_e       RV32B               = ibex_pkg::RV32BOTEarlGrey,
+  parameter ibex_pkg::rv32zc_e      RV32ZC              = ibex_pkg::RV32ZcaZcbZcmp,
   parameter ibex_pkg::regfile_e     RegFile             = ibex_pkg::RegFileFF,
   parameter bit                     BranchTargetALU     = 1'b1,
   parameter bit                     WritebackStage      = 1'b1,
@@ -405,6 +406,7 @@ module rv_core_ibex
     .RV32E                       ( RV32E                    ),
     .RV32M                       ( RV32M                    ),
     .RV32B                       ( RV32B                    ),
+    .RV32ZC                      ( RV32ZC                   ),
     .RegFile                     ( RegFile                  ),
     .BranchTargetALU             ( BranchTargetALU          ),
     .WritebackStage              ( WritebackStage           ),
diff --git a/hw/top_darjeeling/rtl/autogen/top_darjeeling.sv b/hw/top_darjeeling/rtl/autogen/top_darjeeling.sv
@@ -143,6 +143,7 @@ module top_darjeeling #(
   parameter bit RvCoreIbexRV32E = 0,
   parameter ibex_pkg::rv32m_e RvCoreIbexRV32M = ibex_pkg::RV32MSingleCycle,
   parameter ibex_pkg::rv32b_e RvCoreIbexRV32B = ibex_pkg::RV32BOTEarlGrey,
+  parameter ibex_pkg::rv32zc_e RvCoreIbexRV32ZC = ibex_pkg::RV32ZcaZcbZcmp,
   parameter ibex_pkg::regfile_e RvCoreIbexRegFile = ibex_pkg::RegFileFF,
   parameter bit RvCoreIbexBranchTargetALU = 1,
   parameter bit RvCoreIbexWritebackStage = 1,
@@ -2729,6 +2730,7 @@ module top_darjeeling #(
     .RV32E(RvCoreIbexRV32E),
     .RV32M(RvCoreIbexRV32M),
     .RV32B(RvCoreIbexRV32B),
+    .RV32ZC(RvCoreIbexRV32ZC),
     .RegFile(RvCoreIbexRegFile),
     .BranchTargetALU(RvCoreIbexBranchTargetALU),
     .WritebackStage(RvCoreIbexWritebackStage),
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -9110,6 +9110,7 @@
         RV32E: "0"
         RV32M: ibex_pkg::RV32MSingleCycle
         RV32B: ibex_pkg::RV32BOTEarlGrey
+        RV32ZC: ibex_pkg::RV32ZcaZcbZcmp
         RegFile: ibex_pkg::RegFileFF
         BranchTargetALU: "1"
         WritebackStage: "1"
@@ -9296,6 +9297,15 @@
           expose: "true"
           name_top: RvCoreIbexRV32B
         }
+        {
+          name: RV32ZC
+          desc: RV32ZC
+          type: ibex_pkg::rv32zc_e
+          default: ibex_pkg::RV32ZcaZcbZcmp
+          local: "false"
+          expose: "true"
+          name_top: RvCoreIbexRV32ZC
+        }
         {
           name: RegFile
           desc: Reg file
diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson
@@ -1028,6 +1028,7 @@
                    RV32E: "0",
                    RV32M: "ibex_pkg::RV32MSingleCycle",
                    RV32B: "ibex_pkg::RV32BOTEarlGrey",
+                   RV32ZC: "ibex_pkg::RV32ZcaZcbZcmp",
                    RegFile: "ibex_pkg::RegFileFF",
                    BranchTargetALU: "1",
                    WritebackStage: "1",
diff --git a/hw/top_earlgrey/ip_autogen/rv_core_ibex/data/rv_core_ibex.hjson b/hw/top_earlgrey/ip_autogen/rv_core_ibex/data/rv_core_ibex.hjson
@@ -341,6 +341,14 @@
       expose:  "true"
     },
 
+    { name:    "RV32ZC"
+      type:    "ibex_pkg::rv32zc_e"
+      default: "ibex_pkg::RV32ZcaZcbZcmp"
+      desc:    "RV32ZC"
+      local:   "false"
+      expose:  "true"
+    },
+
     { name:    "RegFile"
       type:    "ibex_pkg::regfile_e"
       default: "ibex_pkg::RegFileFF"
diff --git a/hw/top_earlgrey/ip_autogen/rv_core_ibex/rtl/rv_core_ibex.sv b/hw/top_earlgrey/ip_autogen/rv_core_ibex/rtl/rv_core_ibex.sv
@@ -28,6 +28,7 @@ module rv_core_ibex
   parameter bit                     RV32E               = 0,
   parameter ibex_pkg::rv32m_e       RV32M               = ibex_pkg::RV32MSingleCycle,
   parameter ibex_pkg::rv32b_e       RV32B               = ibex_pkg::RV32BOTEarlGrey,
+  parameter ibex_pkg::rv32zc_e      RV32ZC              = ibex_pkg::RV32ZcaZcbZcmp,
   parameter ibex_pkg::regfile_e     RegFile             = ibex_pkg::RegFileFF,
   parameter bit                     BranchTargetALU     = 1'b1,
   parameter bit                     WritebackStage      = 1'b1,
@@ -405,6 +406,7 @@ module rv_core_ibex
     .RV32E                       ( RV32E                    ),
     .RV32M                       ( RV32M                    ),
     .RV32B                       ( RV32B                    ),
+    .RV32ZC                      ( RV32ZC                   ),
     .RegFile                     ( RegFile                  ),
     .BranchTargetALU             ( BranchTargetALU          ),
     .WritebackStage              ( WritebackStage           ),
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -129,6 +129,7 @@ module top_earlgrey #(
   parameter bit RvCoreIbexRV32E = 0,
   parameter ibex_pkg::rv32m_e RvCoreIbexRV32M = ibex_pkg::RV32MSingleCycle,
   parameter ibex_pkg::rv32b_e RvCoreIbexRV32B = ibex_pkg::RV32BOTEarlGrey,
+  parameter ibex_pkg::rv32zc_e RvCoreIbexRV32ZC = ibex_pkg::RV32ZcaZcbZcmp,
   parameter ibex_pkg::regfile_e RvCoreIbexRegFile = ibex_pkg::RegFileFF,
   parameter bit RvCoreIbexBranchTargetALU = 1,
   parameter bit RvCoreIbexWritebackStage = 1,
@@ -2828,6 +2829,7 @@ module top_earlgrey #(
     .RV32E(RvCoreIbexRV32E),
     .RV32M(RvCoreIbexRV32M),
     .RV32B(RvCoreIbexRV32B),
+    .RV32ZC(RvCoreIbexRV32ZC),
     .RegFile(RvCoreIbexRegFile),
     .BranchTargetALU(RvCoreIbexBranchTargetALU),
     .WritebackStage(RvCoreIbexWritebackStage),
diff --git a/hw/top_englishbreakfast/data/autogen/top_englishbreakfast.gen.hjson b/hw/top_englishbreakfast/data/autogen/top_englishbreakfast.gen.hjson
@@ -4133,6 +4133,7 @@
         RV32E: "0"
         RV32M: ibex_pkg::RV32MSingleCycle
         RV32B: ibex_pkg::RV32BNone
+        RV32ZC: ibex_pkg::RV32ZcaZcbZcmp
         RegFile: ibex_pkg::RegFileFF
         BranchTargetALU: "1"
         WritebackStage: "1"
@@ -4306,6 +4307,15 @@
           expose: "true"
           name_top: RvCoreIbexRV32B
         }
+        {
+          name: RV32ZC
+          desc: RV32ZC
+          type: ibex_pkg::rv32zc_e
+          default: ibex_pkg::RV32ZcaZcbZcmp
+          local: "false"
+          expose: "true"
+          name_top: RvCoreIbexRV32ZC
+        }
         {
           name: RegFile
           desc: Reg file
diff --git a/hw/top_englishbreakfast/data/top_englishbreakfast.hjson b/hw/top_englishbreakfast/data/top_englishbreakfast.hjson
@@ -604,6 +604,7 @@
                    RV32E: "0",
                    RV32M: "ibex_pkg::RV32MSingleCycle",
                    RV32B: "ibex_pkg::RV32BNone",
+                   RV32ZC: "ibex_pkg::RV32ZcaZcbZcmp",
                    RegFile: "ibex_pkg::RegFileFF",
                    BranchTargetALU: "1",
                    WritebackStage: "1",
diff --git a/hw/top_englishbreakfast/ip_autogen/rv_core_ibex/data/rv_core_ibex.hjson b/hw/top_englishbreakfast/ip_autogen/rv_core_ibex/data/rv_core_ibex.hjson
@@ -341,6 +341,14 @@
       expose:  "true"
     },
 
+    { name:    "RV32ZC"
+      type:    "ibex_pkg::rv32zc_e"
+      default: "ibex_pkg::RV32ZcaZcbZcmp"
+      desc:    "RV32ZC"
+      local:   "false"
+      expose:  "true"
+    },
+
     { name:    "RegFile"
       type:    "ibex_pkg::regfile_e"
       default: "ibex_pkg::RegFileFF"
diff --git a/hw/top_englishbreakfast/ip_autogen/rv_core_ibex/rtl/rv_core_ibex.sv b/hw/top_englishbreakfast/ip_autogen/rv_core_ibex/rtl/rv_core_ibex.sv
@@ -28,6 +28,7 @@ module rv_core_ibex
   parameter bit                     RV32E               = 0,
   parameter ibex_pkg::rv32m_e       RV32M               = ibex_pkg::RV32MSingleCycle,
   parameter ibex_pkg::rv32b_e       RV32B               = ibex_pkg::RV32BOTEarlGrey,
+  parameter ibex_pkg::rv32zc_e      RV32ZC              = ibex_pkg::RV32ZcaZcbZcmp,
   parameter ibex_pkg::regfile_e     RegFile             = ibex_pkg::RegFileFF,
   parameter bit                     BranchTargetALU     = 1'b1,
   parameter bit                     WritebackStage      = 1'b1,
@@ -405,6 +406,7 @@ module rv_core_ibex
     .RV32E                       ( RV32E                    ),
     .RV32M                       ( RV32M                    ),
     .RV32B                       ( RV32B                    ),
+    .RV32ZC                      ( RV32ZC                   ),
     .RegFile                     ( RegFile                  ),
     .BranchTargetALU             ( BranchTargetALU          ),
     .WritebackStage              ( WritebackStage           ),
diff --git a/hw/top_englishbreakfast/rtl/autogen/top_englishbreakfast.sv b/hw/top_englishbreakfast/rtl/autogen/top_englishbreakfast.sv
@@ -65,6 +65,7 @@ module top_englishbreakfast #(
   parameter bit RvCoreIbexRV32E = 0,
   parameter ibex_pkg::rv32m_e RvCoreIbexRV32M = ibex_pkg::RV32MSingleCycle,
   parameter ibex_pkg::rv32b_e RvCoreIbexRV32B = ibex_pkg::RV32BNone,
+  parameter ibex_pkg::rv32zc_e RvCoreIbexRV32ZC = ibex_pkg::RV32ZcaZcbZcmp,
   parameter ibex_pkg::regfile_e RvCoreIbexRegFile = ibex_pkg::RegFileFF,
   parameter bit RvCoreIbexBranchTargetALU = 1,
   parameter bit RvCoreIbexWritebackStage = 1,
@@ -1296,6 +1297,7 @@ module top_englishbreakfast #(
     .RV32E(RvCoreIbexRV32E),
     .RV32M(RvCoreIbexRV32M),
     .RV32B(RvCoreIbexRV32B),
+    .RV32ZC(RvCoreIbexRV32ZC),
     .RegFile(RvCoreIbexRegFile),
     .BranchTargetALU(RvCoreIbexBranchTargetALU),
     .WritebackStage(RvCoreIbexWritebackStage),
