From 552766cba1d6e9d67650278ebfefaaa660bd4e96 Mon Sep 17 00:00:00 2001 From: Peter Feerick Date: Fri, 7 Feb 2025 01:06:44 +0000 Subject: [PATCH 01/54] chore: pin for 2.11 --- .github/workflows/build_fw.yml | 4 +- .github/workflows/linux_cpn.yml | 2 +- .github/workflows/nightly.yml | 2 +- .github/workflows/win_cpn-32.yml | 100 ------------------------------- .gitpod.yml | 2 +- 5 files changed, 5 insertions(+), 105 deletions(-) delete mode 100644 .github/workflows/win_cpn-32.yml diff --git a/.github/workflows/build_fw.yml b/.github/workflows/build_fw.yml index 5d52656aedb..78a739ad34d 100644 --- a/.github/workflows/build_fw.yml +++ b/.github/workflows/build_fw.yml @@ -56,7 +56,7 @@ jobs: - nb4p - st16 container: - image: ghcr.io/edgetx/edgetx-dev:latest + image: ghcr.io/edgetx/edgetx-dev:2.11 volumes: - ${{ github.workspace }}:/src steps: @@ -103,7 +103,7 @@ jobs: - nb4p - st16 container: - image: ghcr.io/edgetx/edgetx-dev:latest + image: ghcr.io/edgetx/edgetx-dev:2.11 volumes: - ${{ github.workspace }}:/src steps: diff --git a/.github/workflows/linux_cpn.yml b/.github/workflows/linux_cpn.yml index c282a5274ed..5d9b6eeed95 100644 --- a/.github/workflows/linux_cpn.yml +++ b/.github/workflows/linux_cpn.yml @@ -29,7 +29,7 @@ jobs: build: runs-on: ubuntu-latest container: - image: ghcr.io/edgetx/edgetx-dev:latest + image: ghcr.io/edgetx/edgetx-dev:2.11 volumes: - ${{ github.workspace }}:/src diff --git a/.github/workflows/nightly.yml b/.github/workflows/nightly.yml index 2c838b27f14..2d252abfc01 100644 --- a/.github/workflows/nightly.yml +++ b/.github/workflows/nightly.yml @@ -38,7 +38,7 @@ jobs: - st16 - tx15 container: - image: ghcr.io/edgetx/edgetx-dev:latest + image: ghcr.io/edgetx/edgetx-dev:2.11 volumes: - ${{ github.workspace }}:/src steps: diff --git a/.github/workflows/win_cpn-32.yml b/.github/workflows/win_cpn-32.yml deleted file mode 100644 index 1fb67e40199..00000000000 --- a/.github/workflows/win_cpn-32.yml +++ /dev/null @@ -1,100 +0,0 @@ -name: Windows Companion 32-bit - -on: - push: - branches: - - 'main' - tags: - - v* - paths: - - '.github/workflows/win_cpn-32.yml' - - 'companion/**' - - 'tools/build-companion.sh' - - workflow_dispatch: - -env: - # Customize the CMake build type here (Release, Debug, RelWithDebInfo, etc.) - BUILD_TYPE: Release - CMAKE_GENERATOR: "MSYS Makefiles" - QT_VERSION: "5.15.2" - MINGW_VERSION: "win32_mingw81" - MINGW_PATH: "mingw81_32" - -jobs: - build: - # The CMake configure and build commands are platform agnostic and should work equally - # well on Windows or Mac. You can convert this to a matrix build if you need - # cross-platform coverage. - # See: https://docs.github.com/en/free-pro-team@latest/actions/learn-github-actions/managing-complex-workflows#using-a-build-matrix - runs-on: windows-latest - defaults: - run: - shell: msys2 {0} - - steps: - - uses: msys2/setup-msys2@v2 - with: - msystem: MINGW32 - update: true - install: git make curl tar mingw-w64-i686-toolchain - - - name: Install Dependencies - run: | - pacman -S --noconfirm mingw-w64-i686-cmake \ - mingw-w64-i686-python-pip \ - mingw-w64-i686-python-pillow \ - mingw-w64-i686-libjpeg-turbo \ - mingw-w64-i686-zlib \ - mingw-w64-i686-libtiff \ - mingw-w64-i686-freetype \ - mingw-w64-i686-lcms2 \ - mingw-w64-i686-libwebp \ - mingw-w64-i686-openjpeg2 \ - mingw-w64-i686-libimagequant \ - mingw-w64-i686-libraqm \ - mingw-w64-i686-SDL2 \ - mingw-w64-i686-clang \ - mingw-w64-i686-nsis \ - mingw-w64-i686-openssl - SETUPTOOLS_USE_DISTUTILS=stdlib pip install lz4 - python -m pip install clang jinja2 lz4 - - - name: Download and unpack dfu-util - run: | - curl -LO https://dfu-util.sourceforge.net/releases/dfu-util-0.11-binaries.tar.xz && \ - tar -xf dfu-util-0.11-binaries.tar.xz - cp dfu-util-0.11-binaries/win32/dfu-util-static.exe /mingw32/bin/dfu-util.exe - cp dfu-util-0.11-binaries/win32/libusb-1.0.dll /mingw32/bin/libusb-1.0.dll - cp dfu-util-0.11-binaries/win32/libusb-1.0.dll.a /mingw32/bin/libusb-1.0.dll.a - - - name: Install Qt - uses: jurplel/install-qt-action@v3 - with: - cache: true - cache-key-prefix: 'install-qt-action-win32' - version: ${{ env.QT_VERSION }} - arch: ${{ env.MINGW_VERSION }} - - - name: Check out the repo - uses: actions/checkout@v4 - with: - submodules: recursive - - - name: Build - working-directory: ${{github.workspace}} - # Execute the build. You can specify a specific target with "--target " - run: | - mkdir output && \ - CMAKE_PREFIX_PATH=$RUNNER_WORKSPACE/Qt/$QT_VERSION/$MINGW_PATH \ - tools/build-companion.sh "$(pwd)" "$(pwd)/output/" - - name: Compose release filename - # https://stackoverflow.com/questions/58033366/how-to-get-current-branch-within-github-actions - run: echo "artifact_name=edgetx-cpn-win32-${GITHUB_REF##*/}" >> $GITHUB_ENV - - - name: Archive production artifacts - uses: actions/upload-artifact@v4 - with: - name: "${{ env.artifact_name }}" - path: ${{github.workspace}}/output - retention-days: 15 diff --git a/.gitpod.yml b/.gitpod.yml index ecb5b54cb9e..2ca361697af 100644 --- a/.gitpod.yml +++ b/.gitpod.yml @@ -1,4 +1,4 @@ -image: ghcr.io/edgetx/gitpod-workspace:latest +image: ghcr.io/edgetx/gitpod-workspace:2.11 tasks: - name: Prep build folder From 376ccbf1f5126baf9ceadbc014de0f0a3212e161 Mon Sep 17 00:00:00 2001 From: Peter Feerick Date: Fri, 7 Feb 2025 08:23:04 +0000 Subject: [PATCH 02/54] chore: run `companion_translations` --- companion/src/translations/companion_cs.ts | 16 ++++++++-------- companion/src/translations/companion_da.ts | 14 +++++++------- companion/src/translations/companion_de.ts | 16 ++++++++-------- companion/src/translations/companion_en.ts | 14 +++++++------- companion/src/translations/companion_es.ts | 16 ++++++++-------- companion/src/translations/companion_fi.ts | 16 ++++++++-------- companion/src/translations/companion_fr.ts | 16 ++++++++-------- companion/src/translations/companion_he.ts | 16 ++++++++-------- companion/src/translations/companion_it.ts | 16 ++++++++-------- companion/src/translations/companion_ja.ts | 14 +++++++------- companion/src/translations/companion_nl.ts | 16 ++++++++-------- companion/src/translations/companion_pl.ts | 16 ++++++++-------- companion/src/translations/companion_pt.ts | 16 ++++++++-------- companion/src/translations/companion_ru.ts | 16 ++++++++-------- companion/src/translations/companion_zh_CN.ts | 16 ++++++++-------- companion/src/translations/companion_zh_TW.ts | 16 ++++++++-------- 16 files changed, 125 insertions(+), 125 deletions(-) diff --git a/companion/src/translations/companion_cs.ts b/companion/src/translations/companion_cs.ts index b284c3cbc12..e5ea2b313b2 100644 --- a/companion/src/translations/companion_cs.ts +++ b/companion/src/translations/companion_cs.ts @@ -7304,42 +7304,42 @@ Sloupce pro nadmořskou výšku "GAlt" a pro rychlost "GSpd" - + Tabbed Windows Okna se záložkami - + Use tabs to arrange open windows. Pomocí záložek můžete uspořádat otevřená okna. - + Tile Windows Dlaždice - + Arrange open windows across all the available space. Uspořádá otevřená okna napříč celým volným prostorem. - + Cascade Windows Kaskádová okna - + Arrange all open windows in a stack. Uspořádá všechna otevřená okna do kaskády. - + Close All Windows Zavřít všechna okna - + Closes all open files (prompts to save if necessary. Zavře všechny otevřené soubory (v případě potřeby vás požádá o uložení). diff --git a/companion/src/translations/companion_da.ts b/companion/src/translations/companion_da.ts index 47a9600d46d..9b879c79ad4 100644 --- a/companion/src/translations/companion_da.ts +++ b/companion/src/translations/companion_da.ts @@ -7760,37 +7760,37 @@ Vil du fortsætte? Arrangeret med faner - + Use tabs to arrange open windows. Brug tab for at arrangere åbne vinduer. - + Tile Windows Arrangeret som fliser - + Arrange open windows across all the available space. Arrangeret med åbne vinduer fordelt over den mulige plads. - + Cascade Windows Arrangeret som kaskade vinduer - + Arrange all open windows in a stack. Arrangeret ved stabling af åbne vinduer. - + Close All Windows Luk alle vinduer - + Closes all open files (prompts to save if necessary. Luk alle åbne filer (du får mulighed for at gemme først). diff --git a/companion/src/translations/companion_de.ts b/companion/src/translations/companion_de.ts index 82a8b410c9c..4f18428b541 100644 --- a/companion/src/translations/companion_de.ts +++ b/companion/src/translations/companion_de.ts @@ -7341,42 +7341,42 @@ Do you wish to continue? - + Tabbed Windows - + Use tabs to arrange open windows. - + Tile Windows - + Arrange open windows across all the available space. - + Cascade Windows - + Arrange all open windows in a stack. - + Close All Windows - + Closes all open files (prompts to save if necessary. diff --git a/companion/src/translations/companion_en.ts b/companion/src/translations/companion_en.ts index 37cc56cd6e6..e120e96ab81 100644 --- a/companion/src/translations/companion_en.ts +++ b/companion/src/translations/companion_en.ts @@ -7309,7 +7309,7 @@ The columns for altitude "GAlt" and for speed "GSpd" are opt - + Tabbed Windows @@ -7454,12 +7454,12 @@ The columns for altitude "GAlt" and for speed "GSpd" are opt - + Cascade Windows - + Close All Windows @@ -7573,22 +7573,22 @@ The columns for altitude "GAlt" and for speed "GSpd" are opt - + Use tabs to arrange open windows. - + Arrange open windows across all the available space. - + Arrange all open windows in a stack. - + Closes all open files (prompts to save if necessary. diff --git a/companion/src/translations/companion_es.ts b/companion/src/translations/companion_es.ts index bd0c378318c..1ad252c88d6 100644 --- a/companion/src/translations/companion_es.ts +++ b/companion/src/translations/companion_es.ts @@ -7428,42 +7428,42 @@ Do you wish to continue? Carga los ajustes de %1 y del simulador desde un fichero de ajustes exportado previamente - + Use tabs to arrange open windows. Usa las pestañas para organizar las ventanas abiertas - + Tabbed Windows Ventanas con pestañas - + Tile Windows Ventanas en cascada - + Arrange open windows across all the available space. Organiza las ventanas en todo el espacio disponible - + Cascade Windows Ventanas en cascada - + Arrange all open windows in a stack. Organiza todas las ventanas abiertas en una cascada - + Close All Windows Cierra todas las ventanas - + Closes all open files (prompts to save if necessary. Cierra todos los archivos abiertos (pregunta guardar si es necesario) diff --git a/companion/src/translations/companion_fi.ts b/companion/src/translations/companion_fi.ts index fa136dd83e3..58e9fb02db6 100644 --- a/companion/src/translations/companion_fi.ts +++ b/companion/src/translations/companion_fi.ts @@ -7432,42 +7432,42 @@ Do you wish to continue? - + Tabbed Windows - + Use tabs to arrange open windows. - + Tile Windows - + Arrange open windows across all the available space. - + Cascade Windows - + Arrange all open windows in a stack. - + Close All Windows - + Closes all open files (prompts to save if necessary. diff --git a/companion/src/translations/companion_fr.ts b/companion/src/translations/companion_fr.ts index 45ac06630aa..c9de356d9d7 100644 --- a/companion/src/translations/companion_fr.ts +++ b/companion/src/translations/companion_fr.ts @@ -7592,42 +7592,42 @@ Do you wish to continue? Charger les paramètres %1 et les paramètres de Simulation depuis un fichier précédemment exporté. - + Tabbed Windows Fenêtres à onglets - + Use tabs to arrange open windows. Utilisez les onglets pour organiser les fenêtres ouvertes. - + Tile Windows Titre de la fenêtre - + Arrange open windows across all the available space. Disposez les fenêtres ouvertes sur tout l'espace disponible. - + Cascade Windows Fenêtres en cascade - + Arrange all open windows in a stack. Organisez toutes les fenêtres ouvertes dans une pile. - + Close All Windows Fermer toutes les fenêtres - + Closes all open files (prompts to save if necessary. Fermer tous les fichiers ouverts (proposer de sauvegarder si nécessaire). diff --git a/companion/src/translations/companion_he.ts b/companion/src/translations/companion_he.ts index 98272374b3c..9a34324f3f4 100644 --- a/companion/src/translations/companion_he.ts +++ b/companion/src/translations/companion_he.ts @@ -7320,42 +7320,42 @@ Do you wish to continue? - + Tabbed Windows - + Use tabs to arrange open windows. - + Tile Windows - + Arrange open windows across all the available space. - + Cascade Windows - + Arrange all open windows in a stack. - + Close All Windows - + Closes all open files (prompts to save if necessary. diff --git a/companion/src/translations/companion_it.ts b/companion/src/translations/companion_it.ts index 2fddbb90441..3ddc8d01dd6 100644 --- a/companion/src/translations/companion_it.ts +++ b/companion/src/translations/companion_it.ts @@ -7362,42 +7362,42 @@ Do you wish to continue? - + Tabbed Windows - + Use tabs to arrange open windows. - + Tile Windows - + Arrange open windows across all the available space. - + Cascade Windows - + Arrange all open windows in a stack. - + Close All Windows - + Closes all open files (prompts to save if necessary. diff --git a/companion/src/translations/companion_ja.ts b/companion/src/translations/companion_ja.ts index 762e420590e..99837591174 100644 --- a/companion/src/translations/companion_ja.ts +++ b/companion/src/translations/companion_ja.ts @@ -7439,7 +7439,7 @@ The columns for altitude "GAlt" and for speed "GSpd" are opt <p>以前の設定はこちらにバックアップされました:<br> %1 </p> - + Tabbed Windows タブ付きウィンドウ @@ -7584,12 +7584,12 @@ The columns for altitude "GAlt" and for speed "GSpd" are opt ウィンドウのタイトル - + Cascade Windows ウィンドウを重ねる - + Close All Windows すべてのウィンドウを閉じる @@ -7703,22 +7703,22 @@ The columns for altitude "GAlt" and for speed "GSpd" are opt 現在の送信機プロファイルを削除... - + Use tabs to arrange open windows. タブを使用し、開いているウィンドウを並べます。 - + Arrange open windows across all the available space. 開いているウィンドウを空いているスペース全体に配置します。 - + Arrange all open windows in a stack. 開いているウィンドウをスタックに並べます。 - + Closes all open files (prompts to save if necessary. 開いているファイルをすべて閉じます (必要に応じ保存を求められます)。 diff --git a/companion/src/translations/companion_nl.ts b/companion/src/translations/companion_nl.ts index 820b96c78aa..b609192ab8c 100644 --- a/companion/src/translations/companion_nl.ts +++ b/companion/src/translations/companion_nl.ts @@ -7305,42 +7305,42 @@ Do you wish to continue? - + Tabbed Windows - + Use tabs to arrange open windows. - + Tile Windows - + Arrange open windows across all the available space. - + Cascade Windows - + Arrange all open windows in a stack. - + Close All Windows - + Closes all open files (prompts to save if necessary. diff --git a/companion/src/translations/companion_pl.ts b/companion/src/translations/companion_pl.ts index a8d851b0783..765cc1a59a8 100644 --- a/companion/src/translations/companion_pl.ts +++ b/companion/src/translations/companion_pl.ts @@ -7255,42 +7255,42 @@ Do you wish to continue? Skasuj Aktualny Profil Radia... - + Tabbed Windows Zakładkowane okna - + Use tabs to arrange open windows. Użyj zakładek do ustawienia otwartych okien. - + Tile Windows Tytuł Okien - + Arrange open windows across all the available space. Ustaw otwarte okna na całej dostępnej przestrzeni. - + Cascade Windows Okna kaskadowo - + Arrange all open windows in a stack. Ustaw wszytkie otwarte okna na stosie. - + Close All Windows Zamknij wszytkie okna - + Closes all open files (prompts to save if necessary. Zamknij wszystkie otwarte pliki (zapytaj by zapisać jeśli trzeba). diff --git a/companion/src/translations/companion_pt.ts b/companion/src/translations/companion_pt.ts index f8088c10f46..53a64a0a667 100644 --- a/companion/src/translations/companion_pt.ts +++ b/companion/src/translations/companion_pt.ts @@ -7305,42 +7305,42 @@ Do you wish to continue? - + Tabbed Windows - + Use tabs to arrange open windows. - + Tile Windows - + Arrange open windows across all the available space. - + Cascade Windows - + Arrange all open windows in a stack. - + Close All Windows - + Closes all open files (prompts to save if necessary. diff --git a/companion/src/translations/companion_ru.ts b/companion/src/translations/companion_ru.ts index c67ea5cab41..957865d6823 100644 --- a/companion/src/translations/companion_ru.ts +++ b/companion/src/translations/companion_ru.ts @@ -7372,42 +7372,42 @@ Do you wish to continue? Чтение ранее экспортированных настроек %1 и симулятора из файла. - + Tabbed Windows В виде закладок - + Use tabs to arrange open windows. Использовать закладки для переключения между окнами. - + Tile Windows По горизонтали - + Arrange open windows across all the available space. Выравнивание открытых окон по горизонтали. - + Cascade Windows Каскадом - + Arrange all open windows in a stack. Выравнивание открытых окон каскадом. - + Close All Windows Закрыть все окна - + Closes all open files (prompts to save if necessary. Закрыть все окна (с запросом на сохранение изменений). diff --git a/companion/src/translations/companion_zh_CN.ts b/companion/src/translations/companion_zh_CN.ts index 163a262523e..15bd1e05ea7 100644 --- a/companion/src/translations/companion_zh_CN.ts +++ b/companion/src/translations/companion_zh_CN.ts @@ -7579,42 +7579,42 @@ Do you wish to continue? - + Tabbed Windows - + Use tabs to arrange open windows. - + Tile Windows - + Arrange open windows across all the available space. - + Cascade Windows - + Arrange all open windows in a stack. - + Close All Windows - + Closes all open files (prompts to save if necessary. diff --git a/companion/src/translations/companion_zh_TW.ts b/companion/src/translations/companion_zh_TW.ts index 7379e5e0bd5..69a0f978247 100644 --- a/companion/src/translations/companion_zh_TW.ts +++ b/companion/src/translations/companion_zh_TW.ts @@ -7579,42 +7579,42 @@ Do you wish to continue? - + Tabbed Windows - + Use tabs to arrange open windows. - + Tile Windows - + Arrange open windows across all the available space. - + Cascade Windows - + Arrange all open windows in a stack. - + Close All Windows - + Closes all open files (prompts to save if necessary. From 686cf1c438ce94db63635b963e0e8e7e3f0cd730 Mon Sep 17 00:00:00 2001 From: Peter Feerick Date: Mon, 10 Feb 2025 08:53:28 +0000 Subject: [PATCH 03/54] chore: codename Yes, and fixed the allignment of that brace! --- CMakeLists.txt | 2 +- radio/util/hw_defs/hal_keys.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 4bf1e6705cf..386f40eaad9 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -5,7 +5,7 @@ project(EdgeTX) set(VERSION_MAJOR "3") set(VERSION_MINOR "0") set(VERSION_REVISION "0") -set(CODENAME "dev") +set(CODENAME "Jolly Mon") string(TIMESTAMP BUILD_YEAR "%Y") if(MINGW OR WIN32) diff --git a/radio/util/hw_defs/hal_keys.py b/radio/util/hw_defs/hal_keys.py index 8a00b0a311a..e7439078dba 100644 --- a/radio/util/hw_defs/hal_keys.py +++ b/radio/util/hw_defs/hal_keys.py @@ -120,7 +120,7 @@ "RIGHT": { "label": "Right/MDL" } } }, - { + { "targets": {"commando8"}, "keys": { "EXIT": { "label": "BCK" }, From 7c1dc65808c2ebbd32bc1d22878a1d5d1a41bcc4 Mon Sep 17 00:00:00 2001 From: Peter Feerick Date: Mon, 17 Feb 2025 05:44:15 +0000 Subject: [PATCH 04/54] chore(ci): build for 2.11 --- .github/workflows/build_fw.yml | 2 +- .github/workflows/linux_cpn.yml | 4 ++-- .github/workflows/macosx_cpn.yml | 4 ++-- .github/workflows/win_cpn-64.yml | 4 ++-- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/.github/workflows/build_fw.yml b/.github/workflows/build_fw.yml index 78a739ad34d..3878cf1b338 100644 --- a/.github/workflows/build_fw.yml +++ b/.github/workflows/build_fw.yml @@ -3,7 +3,7 @@ name: Run tests and package firmware on: push: branches: - - 'main' + - '2.11' tags: - v* paths: diff --git a/.github/workflows/linux_cpn.yml b/.github/workflows/linux_cpn.yml index 5d9b6eeed95..a021cc17145 100644 --- a/.github/workflows/linux_cpn.yml +++ b/.github/workflows/linux_cpn.yml @@ -3,7 +3,7 @@ name: Linux Companion on: push: branches: - - 'main' + - '2.11' tags: - v* paths: @@ -13,7 +13,7 @@ on: pull_request: branches: - - 'main' + - '2.11' paths: - '.github/workflows/linux_cpn.yml' - 'companion/**' diff --git a/.github/workflows/macosx_cpn.yml b/.github/workflows/macosx_cpn.yml index cdee31fcdd7..3c5c23f094f 100644 --- a/.github/workflows/macosx_cpn.yml +++ b/.github/workflows/macosx_cpn.yml @@ -3,7 +3,7 @@ name: MacOSX Companion on: push: branches: - - 'main' + - '2.11' tags: - v* paths: @@ -13,7 +13,7 @@ on: pull_request: branches: - - 'main' + - '2.11' paths: - '.github/workflows/macosx_cpn.yml' - 'companion/**' diff --git a/.github/workflows/win_cpn-64.yml b/.github/workflows/win_cpn-64.yml index a73643d6aab..a30712f00f4 100644 --- a/.github/workflows/win_cpn-64.yml +++ b/.github/workflows/win_cpn-64.yml @@ -3,7 +3,7 @@ name: Windows Companion 64-bit on: push: branches: - - 'main' + - '2.11' tags: - v* paths: @@ -13,7 +13,7 @@ on: pull_request: branches: - - 'main' + - '2.11' paths: - '.github/workflows/win_cpn-64.yml' - 'companion/**' From c8604697c986b273042ba6932ea18a0f0aaf7030 Mon Sep 17 00:00:00 2001 From: Maxwell Schaefer Date: Tue, 25 Mar 2025 11:26:37 -0700 Subject: [PATCH 05/54] First building commit of Zorro Blue v2 --- radio/src/CMakeLists.txt | 8 +- radio/src/bitmaps/128x64/splash.png | Bin 452 -> 4825 bytes .../stm32h753_sdram/bootloader/layout.ld | 37 + .../linker/stm32h753_sdram/extra_sections.ld | 58 + .../linker/stm32h753_sdram/layout.ld | 39 + .../startup/startup_stm32h753xx.s | 753 + radio/src/buzzer.h | 2 + radio/src/datastructs.h | 9 + radio/src/gui/128x64/model_setup.cpp | 3 +- radio/src/storage/yaml/CMakeLists.txt | 2 + radio/src/storage/yaml/yaml_datastructs.cpp | 2 + .../common/arm/stm32/h7/CMakeLists.txt | 4 + .../common/arm/stm32/timers_driver.cpp | 2 + radio/src/targets/modalai/CMakeLists.txt | 184 + .../src/targets/modalai/backlight_driver.cpp | 185 + radio/src/targets/modalai/board.cpp | 243 + radio/src/targets/modalai/board.h | 270 + .../targets/modalai/bootloader/boot_menu.cpp | 162 + radio/src/targets/modalai/bsp_io.h | 21 + radio/src/targets/modalai/hal.h | 384 + radio/src/targets/modalai/lcd_driver_aspi.cpp | 296 + radio/src/targets/modalai/lcd_driver_spi.cpp | 379 + radio/src/targets/modalai/led_driver.cpp | 106 + .../targets/modalai/usb_charger_driver.cpp | 36 + radio/src/targets/modalai/usb_descriptor.h | 100 + .../src/targets/modalai/voxlpm_i2c_driver.cpp | 192 + radio/src/targets/modalai/voxlpm_i2c_driver.h | 12 + .../Device/ST/STM32H7xx/Include/stm32h753xx.h | 26867 ++++++++++++++++ radio/util/hw_defs/legacy_names.py | 3 +- 29 files changed, 30354 insertions(+), 5 deletions(-) create mode 100644 radio/src/boards/generic_stm32/linker/stm32h753_sdram/bootloader/layout.ld create mode 100644 radio/src/boards/generic_stm32/linker/stm32h753_sdram/extra_sections.ld create mode 100644 radio/src/boards/generic_stm32/linker/stm32h753_sdram/layout.ld create mode 100644 radio/src/boards/generic_stm32/startup/startup_stm32h753xx.s create mode 100644 radio/src/targets/modalai/CMakeLists.txt create mode 100644 radio/src/targets/modalai/backlight_driver.cpp create mode 100644 radio/src/targets/modalai/board.cpp create mode 100644 radio/src/targets/modalai/board.h create mode 100644 radio/src/targets/modalai/bootloader/boot_menu.cpp create mode 100644 radio/src/targets/modalai/bsp_io.h create mode 100644 radio/src/targets/modalai/hal.h create mode 100644 radio/src/targets/modalai/lcd_driver_aspi.cpp create mode 100644 radio/src/targets/modalai/lcd_driver_spi.cpp create mode 100644 radio/src/targets/modalai/led_driver.cpp create mode 100644 radio/src/targets/modalai/usb_charger_driver.cpp create mode 100644 radio/src/targets/modalai/usb_descriptor.h create mode 100644 radio/src/targets/modalai/voxlpm_i2c_driver.cpp create mode 100644 radio/src/targets/modalai/voxlpm_i2c_driver.h create mode 100644 radio/src/thirdparty/CMSIS/Device/ST/STM32H7xx/Include/stm32h753xx.h diff --git a/radio/src/CMakeLists.txt b/radio/src/CMakeLists.txt index f63a00225d9..deb514cad92 100644 --- a/radio/src/CMakeLists.txt +++ b/radio/src/CMakeLists.txt @@ -37,7 +37,7 @@ option(TEMPLATES "Model templates menu" OFF) option(TRACE_SIMPGMSPACE "Turn on traces in simpgmspace.cpp" ON) option(TRACE_LUA_INTERNALS "Turn on traces for Lua internals" OFF) option(TRACE_AUDIO "Traces audio enabled" OFF) -option(DEBUG_SEGGER_RTT "Debug output to Segger RTT" OFF) +option(DEBUG_SEGGER_RTT "Debug output to Segger RTT" ON) option(DEBUG_WINDOWS "Turn on windows traces" OFF) option(DEBUG_YAML "Turn on YAML traces" OFF) option(DEBUG_LABELS "Turn on Labels traces" OFF) @@ -50,11 +50,11 @@ option(FRSKY_RELEASE "Used to build FrSky released firmware" OFF) option(TBS_RELEASE "Used to build TBS released firmware" OFF) option(IMRC_RELEASE "Used to build IMRC released firmware" OFF) option(HARDWARE_TRAINER_MULTI "Allow multi trainer" OFF) -option(BOOTLOADER "Include Bootloader" ON) +option(BOOTLOADER "Include Bootloader" OFF) option(FWDRIVE "Attach also firmware drive with USB" OFF) option(DISABLE_MCUCHECK "Disable MCU check at start" OFF) option(LUA_MIXER "Enable LUA mixer/model scripts support" ON) -if(PCB STREQUAL X9D+ AND PCBREV STREQUAL 2019) +if((PCB STREQUAL X9D+ AND PCBREV STREQUAL 2019) OR PCB STREQUAL M207) option(USBJ_EX "Enable USB Joystick Extension" OFF) else() option(USBJ_EX "Enable USB Joystick Extension" ON) @@ -96,6 +96,8 @@ elseif(PCB STREQUAL STM32H7S78_DK) include(targets/stm32h7s78-dk/CMakeLists.txt) elseif(PCB STREQUAL X9E OR PCB STREQUAL X9D+ OR PCB STREQUAL X9D OR PCB STREQUAL X7 OR PCB STREQUAL X9LITE OR PCB STREQUAL X9LITES OR PCB STREQUAL XLITE OR PCB STREQUAL XLITES) include(targets/taranis/CMakeLists.txt) +elseif(PCB STREQUAL M207) + include(targets/modalai/CMakeLists.txt) else() message(FATAL_ERROR "Unknown PCB '${PCB}'") endif() diff --git a/radio/src/bitmaps/128x64/splash.png b/radio/src/bitmaps/128x64/splash.png index 04f9b242931e9ed742d94108a72f428ea6e79766..16551e4e05d105d8ed7ad77d0cd3c7cbc95ee178 100644 GIT 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bootloader code size */ +BOOTLOADER_SIZE = 0x10000; + +/* Required amount of stack for interrupt stack (Main stack) */ +MAIN_STACK_SIZE = 8192; + +/* Generate a link error if heap and stack don't fit into RAM */ +MIN_HEAP_SIZE = 4096k; /* required amount of heap */ + +/* Specify the memory areas */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K + ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K + DTCMRAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K + RAM_D1 (xrw) : ORIGIN = 0x24000000, LENGTH = 512K + RAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 288K + RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 64K + SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_SIZE +} + +REGION_ALIAS("REGION_TEXT_STORAGE", FLASH); +REGION_ALIAS("REGION_TEXT", ITCMRAM); +REGION_ALIAS("REGION_ISR_VECT", DTCMRAM); +REGION_ALIAS("REGION_DATA", DTCMRAM); +REGION_ALIAS("REGION_BSS", RAM_D1); +REGION_ALIAS("REGION_RAM", RAM_D1); diff --git a/radio/src/boards/generic_stm32/linker/stm32h753_sdram/extra_sections.ld b/radio/src/boards/generic_stm32/linker/stm32h753_sdram/extra_sections.ld new file mode 100644 index 00000000000..a6da2e2f105 --- /dev/null +++ b/radio/src/boards/generic_stm32/linker/stm32h753_sdram/extra_sections.ld @@ -0,0 +1,58 @@ + +/* Task stacks */ +.ccm (NOLOAD) : +{ + . = ALIGN(4); + _sccm = .; + *(.ccm) + . = ALIGN(4); + _eccm = .; +} > DTCMRAM + +/* Reserve stack space */ +.stack (NOLOAD) : +{ + . = ALIGN(4); + . = . + MAIN_STACK_SIZE; + . = ALIGN(4); +} > DTCMRAM + +/* Fast code */ +.iram : +{ + . = ALIGN(4); + _siram = .; + *(.iram) + . = ALIGN(4); + _eiram = .; +} > ITCMRAM AT> REGION_TEXT_STORAGE + +_stext_iram = LOADADDR(.iram); + +/* Extra DMA section */ +.dram (NOLOAD) : +{ + . = ALIGN(4); + _s_dram = .; + *(.dram) + . = ALIGN(4); + _e_dram = .; +} > RAM_D2 + +.sdram (NOLOAD) : +{ + . = ALIGN(4); + *(.sdram) + *(.sdram*) + *(.sdram_rodata) + *(.sdram_rodata*) + + . = ALIGN(4); + _esdram = .; + + /* Reserve heap space in RAM */ + . = . + MIN_HEAP_SIZE; + . = ALIGN(4); +} > SDRAM + +PROVIDE(_heap_start = _esdram); diff --git a/radio/src/boards/generic_stm32/linker/stm32h753_sdram/layout.ld b/radio/src/boards/generic_stm32/linker/stm32h753_sdram/layout.ld new file mode 100644 index 00000000000..7f94540169c --- /dev/null +++ b/radio/src/boards/generic_stm32/linker/stm32h753_sdram/layout.ld @@ -0,0 +1,39 @@ +/* SDRAM definitions */ +SDRAM_START = DEFINED(__sdram_start) ? __sdram_start : 0xC0000000; +SDRAM_SIZE = DEFINED(__sdram_size) ? __sdram_size : 8192K; + +/* Highest heap address */ +HEAP_ADDRESS = SDRAM_START + SDRAM_SIZE; + +/* Highest address of the user mode stack */ +STACK_ADDRESS = ORIGIN(DTCMRAM) + LENGTH(DTCMRAM); /* end of RAM */ + +/* Maximum bootloader code size */ +BOOTLOADER_SIZE = 0x10000; + +/* Required amount of stack for interrupt stack (Main stack) */ +MAIN_STACK_SIZE = 8192; + +/* Generate a link error if heap and stack don't fit into RAM */ +MIN_HEAP_SIZE = 4096k; /* required amount of heap */ + +/* Specify the memory areas */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K + ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K + DTCMRAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K + RAM_D1 (xrw) : ORIGIN = 0x24000000, LENGTH = 512K + RAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 288K + RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 64K + SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_SIZE + NORFLASH (rx) : ORIGIN = 0x90000000, LENGTH = 8M +} + +REGION_ALIAS("REGION_BOOTLOADER", FLASH); +REGION_ALIAS("REGION_TEXT_STORAGE", NORFLASH); +REGION_ALIAS("REGION_TEXT", SDRAM); +REGION_ALIAS("REGION_ISR_VECT", DTCMRAM); +REGION_ALIAS("REGION_DATA", DTCMRAM); +REGION_ALIAS("REGION_BSS", RAM_D1); +REGION_ALIAS("REGION_RAM", RAM_D1); diff --git a/radio/src/boards/generic_stm32/startup/startup_stm32h753xx.s b/radio/src/boards/generic_stm32/startup/startup_stm32h753xx.s new file mode 100644 index 00000000000..3dec8aeb219 --- /dev/null +++ b/radio/src/boards/generic_stm32/startup/startup_stm32h753xx.s @@ -0,0 +1,753 @@ +/** + ****************************************************************************** + * @file startup_stm32h753xx.s + * @author MCD Application Team + * @brief STM32H753xx Devices vector table for GCC based toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m7 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + + +g_pfnVectors: + .word _estack + .word Reset_Handler + + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */ + .word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */ + .word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */ + .word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */ + .word TIM1_UP_IRQHandler /* TIM1 Update interrupt */ + .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word 0 /* Reserved */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word FMC_IRQHandler /* FMC */ + .word SDMMC1_IRQHandler /* SDMMC1 */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word ETH_IRQHandler /* Ethernet */ + .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ + .word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt*/ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word DCMI_IRQHandler /* DCMI */ + .word CRYP_IRQHandler /* Crypto */ + .word HASH_RNG_IRQHandler /* Hash and Rng */ + .word FPU_IRQHandler /* FPU */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word SPI4_IRQHandler /* SPI4 */ + .word SPI5_IRQHandler /* SPI5 */ + .word SPI6_IRQHandler /* SPI6 */ + .word SAI1_IRQHandler /* SAI1 */ + .word LTDC_IRQHandler /* LTDC */ + .word LTDC_ER_IRQHandler /* LTDC error */ + .word DMA2D_IRQHandler /* DMA2D */ + .word SAI2_IRQHandler /* SAI2 */ + .word QUADSPI_IRQHandler /* QUADSPI */ + .word LPTIM1_IRQHandler /* LPTIM1 */ + .word CEC_IRQHandler /* HDMI_CEC */ + .word I2C4_EV_IRQHandler /* I2C4 Event */ + .word I2C4_ER_IRQHandler /* I2C4 Error */ + .word SPDIF_RX_IRQHandler /* SPDIF_RX */ + .word OTG_FS_EP1_OUT_IRQHandler /* USB OTG FS End Point 1 Out */ + .word OTG_FS_EP1_IN_IRQHandler /* USB OTG FS End Point 1 In */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */ + .word HRTIM1_Master_IRQHandler /* HRTIM Master Timer global Interrupt */ + .word HRTIM1_TIMA_IRQHandler /* HRTIM Timer A global Interrupt */ + .word HRTIM1_TIMB_IRQHandler /* HRTIM Timer B global Interrupt */ + .word HRTIM1_TIMC_IRQHandler /* HRTIM Timer C global Interrupt */ + .word HRTIM1_TIMD_IRQHandler /* HRTIM Timer D global Interrupt */ + .word HRTIM1_TIME_IRQHandler /* HRTIM Timer E global Interrupt */ + .word HRTIM1_FLT_IRQHandler /* HRTIM Fault global Interrupt */ + .word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */ + .word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */ + .word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */ + .word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */ + .word SAI3_IRQHandler /* SAI3 global Interrupt */ + .word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */ + .word TIM15_IRQHandler /* TIM15 global Interrupt */ + .word TIM16_IRQHandler /* TIM16 global Interrupt */ + .word TIM17_IRQHandler /* TIM17 global Interrupt */ + .word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */ + .word MDIOS_IRQHandler /* MDIOS global Interrupt */ + .word JPEG_IRQHandler /* JPEG global Interrupt */ + .word MDMA_IRQHandler /* MDMA global Interrupt */ + .word 0 /* Reserved */ + .word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */ + .word HSEM1_IRQHandler /* HSEM1 global Interrupt */ + .word 0 /* Reserved */ + .word ADC3_IRQHandler /* ADC3 global Interrupt */ + .word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */ + .word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */ + .word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */ + .word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */ + .word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */ + .word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */ + .word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */ + .word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */ + .word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */ + .word COMP1_IRQHandler /* COMP1 global Interrupt */ + .word LPTIM2_IRQHandler /* LP TIM2 global interrupt */ + .word LPTIM3_IRQHandler /* LP TIM3 global interrupt */ + .word LPTIM4_IRQHandler /* LP TIM4 global interrupt */ + .word LPTIM5_IRQHandler /* LP TIM5 global interrupt */ + .word LPUART1_IRQHandler /* LP UART1 interrupt */ + .word 0 /* Reserved */ + .word CRS_IRQHandler /* Clock Recovery Global Interrupt */ + .word ECC_IRQHandler /* ECC diagnostic Global Interrupt */ + .word SAI4_IRQHandler /* SAI4 global interrupt */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */ + + .size g_pfnVectors, .-g_pfnVectors + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_AVD_IRQHandler + .thumb_set PVD_AVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak FDCAN1_IT0_IRQHandler + .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler + + .weak FDCAN2_IT0_IRQHandler + .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler + + .weak FDCAN1_IT1_IRQHandler + .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler + + .weak FDCAN2_IT1_IRQHandler + .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak SDMMC1_IRQHandler + .thumb_set SDMMC1_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak FDCAN_CAL_IRQHandler + .thumb_set FDCAN_CAL_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_OUT_IRQHandler + .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_IN_IRQHandler + .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_HS_WKUP_IRQHandler + .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak DCMI_IRQHandler + .thumb_set DCMI_IRQHandler,Default_Handler + + .weak CRYP_IRQHandler + .thumb_set CRYP_IRQHandler,Default_Handler + + .weak HASH_RNG_IRQHandler + .thumb_set HASH_RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak SPI6_IRQHandler + .thumb_set SPI6_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak LTDC_IRQHandler + .thumb_set LTDC_IRQHandler,Default_Handler + + .weak LTDC_ER_IRQHandler + .thumb_set LTDC_ER_IRQHandler,Default_Handler + + .weak DMA2D_IRQHandler + .thumb_set DMA2D_IRQHandler,Default_Handler + + .weak SAI2_IRQHandler + .thumb_set SAI2_IRQHandler,Default_Handler + + .weak QUADSPI_IRQHandler + .thumb_set QUADSPI_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak I2C4_EV_IRQHandler + .thumb_set I2C4_EV_IRQHandler,Default_Handler + + .weak I2C4_ER_IRQHandler + .thumb_set I2C4_ER_IRQHandler,Default_Handler + + .weak SPDIF_RX_IRQHandler + .thumb_set SPDIF_RX_IRQHandler,Default_Handler + + .weak OTG_FS_EP1_OUT_IRQHandler + .thumb_set OTG_FS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_FS_EP1_IN_IRQHandler + .thumb_set OTG_FS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMAMUX1_OVR_IRQHandler + .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler + + .weak HRTIM1_Master_IRQHandler + .thumb_set HRTIM1_Master_IRQHandler,Default_Handler + + .weak HRTIM1_TIMA_IRQHandler + .thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler + + .weak HRTIM1_TIMB_IRQHandler + .thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler + + .weak HRTIM1_TIMC_IRQHandler + .thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler + + .weak HRTIM1_TIMD_IRQHandler + .thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler + + .weak HRTIM1_TIME_IRQHandler + .thumb_set HRTIM1_TIME_IRQHandler,Default_Handler + + .weak HRTIM1_FLT_IRQHandler + .thumb_set HRTIM1_FLT_IRQHandler,Default_Handler + + .weak DFSDM1_FLT0_IRQHandler + .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler + + .weak DFSDM1_FLT1_IRQHandler + .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler + + .weak DFSDM1_FLT2_IRQHandler + .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler + + .weak DFSDM1_FLT3_IRQHandler + .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler + + .weak SAI3_IRQHandler + .thumb_set SAI3_IRQHandler,Default_Handler + + .weak SWPMI1_IRQHandler + .thumb_set SWPMI1_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak MDIOS_WKUP_IRQHandler + .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler + + .weak MDIOS_IRQHandler + .thumb_set MDIOS_IRQHandler,Default_Handler + + .weak JPEG_IRQHandler + .thumb_set JPEG_IRQHandler,Default_Handler + + .weak MDMA_IRQHandler + .thumb_set MDMA_IRQHandler,Default_Handler + + .weak SDMMC2_IRQHandler + .thumb_set SDMMC2_IRQHandler,Default_Handler + + .weak HSEM1_IRQHandler + .thumb_set HSEM1_IRQHandler,Default_Handler + + .weak ADC3_IRQHandler + .thumb_set ADC3_IRQHandler,Default_Handler + + .weak DMAMUX2_OVR_IRQHandler + .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler + + .weak BDMA_Channel0_IRQHandler + .thumb_set BDMA_Channel0_IRQHandler,Default_Handler + + .weak BDMA_Channel1_IRQHandler + .thumb_set BDMA_Channel1_IRQHandler,Default_Handler + + .weak BDMA_Channel2_IRQHandler + .thumb_set BDMA_Channel2_IRQHandler,Default_Handler + + .weak BDMA_Channel3_IRQHandler + .thumb_set BDMA_Channel3_IRQHandler,Default_Handler + + .weak BDMA_Channel4_IRQHandler + .thumb_set BDMA_Channel4_IRQHandler,Default_Handler + + .weak BDMA_Channel5_IRQHandler + .thumb_set BDMA_Channel5_IRQHandler,Default_Handler + + .weak BDMA_Channel6_IRQHandler + .thumb_set BDMA_Channel6_IRQHandler,Default_Handler + + .weak BDMA_Channel7_IRQHandler + .thumb_set BDMA_Channel7_IRQHandler,Default_Handler + + .weak COMP1_IRQHandler + .thumb_set COMP1_IRQHandler,Default_Handler + + .weak LPTIM2_IRQHandler + .thumb_set LPTIM2_IRQHandler,Default_Handler + + .weak LPTIM3_IRQHandler + .thumb_set LPTIM3_IRQHandler,Default_Handler + + .weak LPTIM4_IRQHandler + .thumb_set LPTIM4_IRQHandler,Default_Handler + + .weak LPTIM5_IRQHandler + .thumb_set LPTIM5_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak CRS_IRQHandler + .thumb_set CRS_IRQHandler,Default_Handler + + .weak ECC_IRQHandler + .thumb_set ECC_IRQHandler,Default_Handler + + .weak SAI4_IRQHandler + .thumb_set SAI4_IRQHandler,Default_Handler + + .weak WAKEUP_PIN_IRQHandler + .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler + + diff --git a/radio/src/buzzer.h b/radio/src/buzzer.h index e5e66251f36..84a276b4c92 100644 --- a/radio/src/buzzer.h +++ b/radio/src/buzzer.h @@ -104,6 +104,8 @@ inline void beep(uint8_t) { } #define AUDIO_TRIM_END(f) #define AUDIO_PLAY(p) #define IS_AUDIO_BUSY() false + #define AUDIO_KEY_PRESS() + #define AUDIO_KEY_ERROR() #endif /* BUZZER */ #define AUDIO_RESET() diff --git a/radio/src/datastructs.h b/radio/src/datastructs.h index f85c8ee1212..7fb790da205 100644 --- a/radio/src/datastructs.h +++ b/radio/src/datastructs.h @@ -61,6 +61,13 @@ static inline void check_struct() CHKSIZE(FrSkyLineData, 4); CHKTYPE(TelemetryScreenData, 24); CHKSIZE(ModelHeader, 12); +#elif defined(PCBM207) + CHKSIZE(LimitData, 11); + CHKSIZE(TimerData, 12); + CHKSIZE(FrSkyBarData, 6); + CHKSIZE(FrSkyLineData, 4); + CHKTYPE(TelemetryScreenData, 24); + CHKSIZE(ModelHeader, 12); #elif defined(PCBTARANIS) CHKSIZE(LimitData, 13); CHKSIZE(TimerData, 17); @@ -100,6 +107,8 @@ static inline void check_struct() #if defined(RADIO_TPRO) || defined(RADIO_TPROV2) || defined(RADIO_BUMBLEBEE) CHKSIZE(ModelData, 6355); +#elif defined(RADIO_MODAL) + CHKSIZE(ModelData, 6329); #elif defined(RADIO_T14) || defined(RADIO_T12MAX) CHKSIZE(ModelData, 6329); #elif defined(RADIO_FAMILY_T20) diff --git a/radio/src/gui/128x64/model_setup.cpp b/radio/src/gui/128x64/model_setup.cpp index 49f40edefc4..0edce2bbf3f 100644 --- a/radio/src/gui/128x64/model_setup.cpp +++ b/radio/src/gui/128x64/model_setup.cpp @@ -825,7 +825,8 @@ void menuModelSetup(event_t event) EXTRA_MODULE_ROWS - TRAINER_ROWS, + TRAINER_ROWS + #warning removed ',' since none of these are currently used // View options 0, diff --git a/radio/src/storage/yaml/CMakeLists.txt b/radio/src/storage/yaml/CMakeLists.txt index 69c75cabb53..c68bb8aabb6 100644 --- a/radio/src/storage/yaml/CMakeLists.txt +++ b/radio/src/storage/yaml/CMakeLists.txt @@ -68,6 +68,8 @@ elseif((PCB STREQUAL X9D) OR (PCB STREQUAL X9D+)) else() set(YAML_GEN_OUTPUT storage/yaml/yaml_datastructs_x9d.cpp) endif() +elseif(PCB STREQUAL M207) + set(YAML_GEN_OUTPUT storage/yaml/yaml_datastructs_128x64.cpp) else() message(FATAL_ERROR "PCB '${PCB}' is not supported by YAML storage") endif() diff --git a/radio/src/storage/yaml/yaml_datastructs.cpp b/radio/src/storage/yaml/yaml_datastructs.cpp index 3bf47a0ee00..2034b70388a 100644 --- a/radio/src/storage/yaml/yaml_datastructs.cpp +++ b/radio/src/storage/yaml/yaml_datastructs.cpp @@ -36,6 +36,8 @@ #else #include "yaml_datastructs_x10.cpp" #endif +#elif defined(PCBM207) + #include "yaml_datastructs_128x64.cpp" #elif defined(PCBTX15) #include "yaml_datastructs_tx15.cpp" #elif defined(PCBPL18) diff --git a/radio/src/targets/common/arm/stm32/h7/CMakeLists.txt b/radio/src/targets/common/arm/stm32/h7/CMakeLists.txt index 8455b8335fc..2b0e950e532 100644 --- a/radio/src/targets/common/arm/stm32/h7/CMakeLists.txt +++ b/radio/src/targets/common/arm/stm32/h7/CMakeLists.txt @@ -132,6 +132,10 @@ elseif(CPU_TYPE_FULL STREQUAL STM32H7S7xx OR CPU_TYPE_FULL STREQUAL STM32H7R7xx) set(CMSIS_SRC ${CMSIS_SRC} targets/common/arm/stm32/h7/vectors_stm32h7s7xx.c ) +elseif(CPU_TYPE_FULL STREQUAL STM32H753II) + set(CMSIS_SRC ${CMSIS_SRC} + boards/generic_stm32/startup/startup_stm32h753xx.s + ) else() message(FATAL_ERROR "### ERROR ####: ${CPU_TYPE_FULL}") endif() diff --git a/radio/src/targets/common/arm/stm32/timers_driver.cpp b/radio/src/targets/common/arm/stm32/timers_driver.cpp index b3138bb7d0f..e8bdfebb484 100644 --- a/radio/src/targets/common/arm/stm32/timers_driver.cpp +++ b/radio/src/targets/common/arm/stm32/timers_driver.cpp @@ -28,6 +28,8 @@ static volatile uint32_t _ms_ticks; +__weak void per5ms() {} + static void _init_1ms_timer() { stm32_timer_enable_clock(MS_TIMER); diff --git a/radio/src/targets/modalai/CMakeLists.txt b/radio/src/targets/modalai/CMakeLists.txt new file mode 100644 index 00000000000..f038ab87a5c --- /dev/null +++ b/radio/src/targets/modalai/CMakeLists.txt @@ -0,0 +1,184 @@ +option(SHUTDOWN_CONFIRMATION "Shutdown confirmation" OFF) +option(PXX1 "PXX1 protocol support" ON) +option(PXX2 "PXX2 protocol support" OFF) +option(AFHDS3 "AFHDS3 TX Module" OFF) +option(GHOST "Ghost TX Module" ON) +option(INTERNAL_MODULE_PPM "Support for PPM internal module" OFF) +option(AUTOUPDATE "Auto update internal chips from SD" OFF) +option(BIND_KEY "Enable bind button" OFF) +option(BLUETOOTH "FrSky BT module support" OFF) + +set(USE_RTC_CLOCK YES) +set(HARDWARE_EXTERNAL_MODULE YES) +set(TARGET_DIR modalai) + +set(HSE_VALUE 16000000) +set(PPM_LIMITS_SYMETRICAL YES) + +add_definitions(-DPCBFRSKY -DPCBTARANIS -DPCBMODALAI) +add_definitions(-DMANUFACTURER_MODALAI) + +# Make malloc() thread-safe +add_definitions(-DTHREADSAFE_MALLOC) + +if(PCB STREQUAL M207) + set(PWR_BUTTON "PRESS" CACHE STRING "Pwr button type (PRESS/SWITCH)") + #set(HAPTIC YES) + set(GUI_DIR 128x64) + set(SDCARD YES) + set(STORAGE_MODELSLIST NO) + set(BITMAPS_DIR 128x64) + set(BITMAPS_TARGET 9x_bitmaps) + set(FONTS_TARGET 9x_fonts_1bit) + set(LCD_DRIVER lcd_driver_spi.cpp) + set(HARDWARE_EXTERNAL_MODULE NO) + set(INTERNAL_MODULE_CRSF YES) + add_definitions(-DHARDWARE_INTERNAL_MODULE) + add_definitions(-DINTERNAL_MODULE_CRSF) + set(STATUS_LEDS YES) + add_definitions(-DPCBM207 -DSOFTWARE_VOLUME) + add_definitions(-DPWR_BUTTON_${PWR_BUTTON}) + if(PCBREV STREQUAL MODAL_ZORRO) + set(DEFAULT_INTERNAL_MODULE CROSSFIRE CACHE STRING "Default internal module") + set(INTERNAL_MODULE_SERIAL YES) + set(MODULE_SIZE_SML YES) + set(FLAVOUR modal_zorro) + set(CPU_TYPE_FULL STM32H753II) + set(ROTARY_ENCODER YES) + # set(USB_CHARGER YES) + add_definitions(-DRADIO_MODAL) + # set(PXX2 ON) + # set(ENABLE_SERIAL_PASSTHROUGH ON CACHE BOOL "Enable serial passthrough") + #if (NOT BLUETOOTH) + # set(AUX_SERIAL ON) + #endif() + endif() +endif() + +message("CPU_TYPE_FULL = ${CPU_TYPE_FULL}") +if (CPU_TYPE_FULL STREQUAL STM32H753II) + set(CPU_TYPE STM32H7) + add_definitions(-DSTM32H753xx) + set(TARGET_LINKER_DIR stm32h753_sdram) +else() + message(FATAL_ERROR "Unknown CPU_TYPE_FULL" ) +endif() + + +#if(ENABLE_SERIAL_PASSTHROUGH) +# set(CLI ON "Enable CLI") +#endif() + +if(INTERNAL_MODULE_SERIAL) + + # defines default internal modules + set(INTERNAL_MODULES MULTI;CRSF CACHE STRING "Internal modules") + + add_definitions(-DINTERNAL_MODULE_SERIAL) + + endif() + +set(TARGET_SRC_DIR targets/${TARGET_DIR}) + +set(BOARD_COMMON_SRC + ${TARGET_SRC_DIR}/board.cpp + ${TARGET_SRC_DIR}/led_driver.cpp + ${TARGET_SRC_DIR}/backlight_driver.cpp + ${TARGET_SRC_DIR}/${LCD_DRIVER} + ${TARGET_SRC_DIR}/voxlpm_i2c_driver.cpp + targets/common/arm/stm32/abnormal_reboot.cpp + targets/common/arm/stm32/delays_driver.cpp + targets/common/arm/stm32/flash_driver.cpp + targets/common/arm/stm32/pwr_driver.cpp + targets/common/arm/stm32/rtc_driver.cpp + targets/common/arm/stm32/watchdog_driver.cpp +) + +if(ROTARY_ENCODER) + list(APPEND BOARD_COMMON_SRC + targets/common/arm/stm32/rotary_encoder_driver.cpp + ) +endif() + +if(BLUETOOTH) + list(APPEND BOARD_COMMON_SRC + targets/common/arm/stm32/bluetooth_driver.cpp + ) +endif() + +# Bootloader board library +add_library(board_bl OBJECT EXCLUDE_FROM_ALL + ${BOARD_COMMON_SRC} + ${TARGET_SRC_DIR}/bootloader/boot_menu.cpp +) +# add_dependencies(board_bl ${BITMAPS_TARGET}) +set(BOOTLOADER_SRC ${BOOTLOADER_SRC} $) + +# Firmware board library +add_library(board OBJECT EXCLUDE_FROM_ALL + ${BOARD_COMMON_SRC} + targets/common/arm/stm32/delays_driver.cpp + targets/common/arm/stm32/mixer_scheduler_driver.cpp + targets/common/arm/stm32/module_timer_driver.cpp + targets/common/arm/stm32/stm32_pulse_driver.cpp + targets/common/arm/stm32/stm32_softserial_driver.cpp + targets/common/arm/stm32/stm32_switch_driver.cpp + targets/common/arm/stm32/stm32_ws2812.cpp +) +set(FIRMWARE_SRC ${FIRMWARE_SRC} $) + +if(STATUS_LEDS) + target_sources(board PRIVATE ${TARGET_SRC_DIR}/led_driver.cpp) +endif() + +if(BIND_KEY) + add_definitions(-DBIND_KEY) + target_sources(board PRIVATE ${TARGET_SRC_DIR}/bind_button_driver.cpp) +endif() + +if(USB_CHARGE_LED) + add_definitions(-DUSB_CHARGE_LED) +endif() + +if(USB_CHARGER) + add_definitions(-DUSB_CHARGER) + target_sources(board PRIVATE ${TARGET_SRC_DIR}/usb_charger_driver.cpp) +endif() + +if(IMU) + target_sources(board PRIVATE targets/common/arm/stm32/lsm6ds_driver.cpp) +endif() + +if(AUTOUPDATE) + add_definitions(-DAUTOUPDATE) +endif() + +if(USE_RTC_CLOCK) + add_definitions(-DRTCLOCK) +endif() + +set(SRC ${SRC} + io/frsky_firmware_update.cpp + io/multi_firmware_update.cpp +) + +set(GUI_SRC ${GUI_SRC} + model_input_edit.cpp + model_mix_edit.cpp + model_display.cpp + radio_diagkeys.cpp + radio_diaganas.cpp + view_channels.cpp + view_telemetry.cpp + view_about.cpp + bmp.cpp +) + +# There has to be a better way... +# In C23 there is now support for #embed... +#set(FIRMWARE_SRC +# ${FIRMWARE_SRC} +# targets/common/arm/loadboot.cpp +# ) + +set(RADIO_DEPENDENCIES ${RADIO_DEPENDENCIES} ${BITMAPS_TARGET}) diff --git a/radio/src/targets/modalai/backlight_driver.cpp b/radio/src/targets/modalai/backlight_driver.cpp new file mode 100644 index 00000000000..c33f05ec614 --- /dev/null +++ b/radio/src/targets/modalai/backlight_driver.cpp @@ -0,0 +1,185 @@ +/* + * Copyright (C) EdgeTX + * + * Based on code named + * opentx - https://github.com/opentx/opentx + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "hal/gpio.h" +#include "stm32_gpio.h" +#include "stm32_timer.h" + +#include "board.h" + +#if !defined(BACKLIGHT_GPIO) && (!defined(BACKLIGHT_GPIO_1) || !defined(BACKLIGHT_GPIO_2)) + // no backlight + void backlightInit() {} + void backlightEnable(uint8_t level) {} + void backlightFullOn() {} + void backlightDisable() {} + uint8_t isBacklightEnabled() {return false;} +#elif defined(PCBX9E) +void backlightInit() +{ + gpio_init_af(BACKLIGHT_GPIO_1, BACKLIGHT_GPIO_AF, GPIO_PIN_SPEED_LOW); + gpio_init_af(BACKLIGHT_GPIO_2, BACKLIGHT_GPIO_AF, GPIO_PIN_SPEED_LOW); + stm32_timer_enable_clock(BACKLIGHT_TIMER); + BACKLIGHT_TIMER->ARR = 100; + BACKLIGHT_TIMER->PSC = BACKLIGHT_TIMER_FREQ / 50000 - 1; // 20us * 100 = 2ms => 500Hz + BACKLIGHT_TIMER->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2M_2; // PWM + BACKLIGHT_TIMER->CCER = TIM_CCER_CC1E | TIM_CCER_CC2E; + BACKLIGHT_TIMER->CCR2 = 0; + BACKLIGHT_TIMER->CCR1 = 100; + BACKLIGHT_TIMER->EGR = 0; + BACKLIGHT_TIMER->CR1 = TIM_CR1_CEN; // Counter enable +} + +void backlightEnable(uint8_t level, uint8_t color) +{ + BACKLIGHT_TIMER->CCR1 = ((100-level)*(20-color))/20; + BACKLIGHT_TIMER->CCR2 = ((100-level)*color)/20; +} + +void backlightFullOn() +{ + backlightEnable(0, 0); +} + +void backlightDisable() +{ + BACKLIGHT_TIMER->CCR1 = 0; + BACKLIGHT_TIMER->CCR2 = 0; +} + +uint8_t isBacklightEnabled() +{ + return (BACKLIGHT_TIMER->CCR1 != 0 || BACKLIGHT_TIMER->CCR2 != 0); +} +#elif defined(PCBX9DP) +void backlightInit() +{ + gpio_init_af(BACKLIGHT_GPIO_1, BACKLIGHT_GPIO_AF, GPIO_PIN_SPEED_LOW); + gpio_init_af(BACKLIGHT_GPIO_2, BACKLIGHT_GPIO_AF, GPIO_PIN_SPEED_LOW); + stm32_timer_enable_clock(BACKLIGHT_TIMER); + BACKLIGHT_TIMER->ARR = 100; + BACKLIGHT_TIMER->PSC = BACKLIGHT_TIMER_FREQ / 50000 - 1; // 20us * 100 = 2ms => 500Hz + BACKLIGHT_TIMER->CCMR1 = TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2M_2; // PWM + BACKLIGHT_TIMER->CCMR2 = TIM_CCMR2_OC4M_1 | TIM_CCMR2_OC4M_2; // PWM + BACKLIGHT_TIMER->CCER = TIM_CCER_CC4E | TIM_CCER_CC2E; + BACKLIGHT_TIMER->CCR2 = 0; + BACKLIGHT_TIMER->CCR4 = 0; + BACKLIGHT_TIMER->EGR = 0; + BACKLIGHT_TIMER->CR1 = TIM_CR1_CEN; // Counter enable +} + +void backlightEnable(uint8_t level, uint8_t color) +{ + BACKLIGHT_TIMER->CCR4 = ((100-level)*(20-color))/20; + BACKLIGHT_TIMER->CCR2 = ((100-level)*color)/20; +} + +void backlightFullOn() +{ + backlightEnable(0, 0); +} + +void backlightDisable() +{ + BACKLIGHT_TIMER->CCR4 = 0; + BACKLIGHT_TIMER->CCR2 = 0; +} + +uint8_t isBacklightEnabled() +{ + return (BACKLIGHT_TIMER->CCR4 != 0 || BACKLIGHT_TIMER->CCR2 != 0); +} +#elif defined(PCBX7) || defined(PCBXLITE) || defined(PCBX9LITE) || defined(PCBM207) +void backlightInit() +{ + gpio_init_af(BACKLIGHT_GPIO, BACKLIGHT_GPIO_AF, GPIO_PIN_SPEED_LOW); + stm32_timer_enable_clock(BACKLIGHT_TIMER); + +#if defined(BACKLIGHT_BDTR) // TODO perhaps it can be always done + BACKLIGHT_TIMER->BDTR = BACKLIGHT_BDTR; // Enable outputs +#endif + BACKLIGHT_TIMER->ARR = 100; + BACKLIGHT_TIMER->PSC = BACKLIGHT_TIMER_FREQ / 50000 - 1; // 20us * 100 = 2ms => 500Hz + #if defined(BACKLIGHT_CCMR1) + BACKLIGHT_TIMER->CCMR1 = BACKLIGHT_CCMR1; + #elif defined(BACKLIGHT_CCMR2) + BACKLIGHT_TIMER->CCMR2 = BACKLIGHT_CCMR2; + #endif + BACKLIGHT_TIMER->CCER = BACKLIGHT_CCER; + BACKLIGHT_COUNTER_REGISTER = 100; + BACKLIGHT_TIMER->EGR = 0; + BACKLIGHT_TIMER->CR1 = TIM_CR1_CEN; // Counter enable +} + +void backlightEnable(uint8_t level) +{ + BACKLIGHT_COUNTER_REGISTER = 100 - level; +} + +void backlightFullOn() +{ + backlightEnable(0); +} + +void backlightDisable() +{ + BACKLIGHT_COUNTER_REGISTER = 0; +} + +uint8_t isBacklightEnabled() +{ + return BACKLIGHT_COUNTER_REGISTER != 0; +} +#else +void backlightInit() +{ + gpio_init_af(BACKLIGHT_GPIO, BACKLIGHT_GPIO_AF, GPIO_PIN_SPEED_LOW); + stm32_timer_enable_clock(BACKLIGHT_TIMER); + + BACKLIGHT_TIMER->ARR = 100; + BACKLIGHT_TIMER->PSC = BACKLIGHT_TIMER_FREQ / 50000 - 1; // 20us * 100 = 2ms => 500Hz + BACKLIGHT_TIMER->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2; // PWM + BACKLIGHT_TIMER->CCER = TIM_CCER_CC1E; + BACKLIGHT_TIMER->CCR1 = 80; + BACKLIGHT_TIMER->EGR = 0; + BACKLIGHT_TIMER->CR1 = 1; +} + +void backlightEnable(uint8_t level) +{ + BACKLIGHT_TIMER->CCR1 = 100 - level; +} + +void backlightFullOn() +{ + backlightEnable(0); +} + +void backlightDisable() +{ + BACKLIGHT_TIMER->CCR1 = 0; +} + +uint8_t isBacklightEnabled() +{ + return BACKLIGHT_TIMER->CCR1 != 0; +} +#endif diff --git a/radio/src/targets/modalai/board.cpp b/radio/src/targets/modalai/board.cpp new file mode 100644 index 00000000000..9821d81c161 --- /dev/null +++ b/radio/src/targets/modalai/board.cpp @@ -0,0 +1,243 @@ +/* + * Copyright (C) EdgeTX + * + * Based on code named + * opentx - https://github.com/opentx/opentx + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "stm32_hal_ll.h" +#include "stm32_gpio.h" +#include "stm32_ws2812.h" + +#include "hal/switch_driver.h" +#include "hal/module_port.h" +#include "hal/abnormal_reboot.h" +#include "hal/usb_driver.h" +#include "hal/gpio.h" + +#include "board.h" +#include "boards/generic_stm32/module_ports.h" +#include "boards/generic_stm32/analog_inputs.h" +#include "boards/generic_stm32/rgb_leds.h" + +#include "debug.h" +#include "rtc.h" + +#include "timers_driver.h" +#include "dataconstants.h" + +#if defined(FLYSKY_GIMBAL) + #include "flysky_gimbal_driver.h" +#endif + +#if !defined(BOOT) + #include "edgetx.h" + #if defined(PXX1) + #include "pulses/pxx1.h" + #endif +#endif + +#if defined(BLUETOOTH) + #include "bluetooth_driver.h" +#endif + +HardwareOptions hardwareOptions; + +#if !defined(BOOT) + +#if defined(SEMIHOSTING) +extern "C" void initialise_monitor_handles(); +#endif + +#if defined(POWER_I2C) + #include "voxlpm_i2c_driver.h" +#endif + + +void boardInit() +{ +#if defined(SEMIHOSTING) + initialise_monitor_handles(); +#elif defined(DEBUG_SEGGER_RTT) + // SEGGER_RTT_Init(); + // SEGGER_RTT_ConfigUpBuffer(0, NULL, NULL, 0, SEGGER_RTT_MODE_NO_BLOCK_SKIP); +#endif + LL_APB4_GRP1_EnableClock(LL_APB4_GRP1_PERIPH_SYSCFG); + + SCB_EnableDCache(); + + RCC->D3CFGR = (0x5 << 4); + RCC->APB4ENR |= RCC_APB4ENR_SPI6EN; + + // Setup pll1 + // RCC->PLL1DIVR |= (0xA0000U & RCC_PLL1DIVR_Q1_Msk); // Set prescaler to 6 (~21 MHz after scaling) + // RCC->CR |= RCC_CR_PLL1ON; + // while (RCC->CR & RCC_CR_PLL1ON == 0) { } + + // Setup pll2 + // RCC->PLLCKSELR &= ~(0x10000 & RCC_PLLCKSELR_DIVM2); + // RCC->PLLCKSELR |= (0x10000 & RCC_PLLCKSELR_DIVM2); + //DIVN2 = 200 + //DIVP2 = 8 + // RCC->PLL2DIVR |= ((0x1000 & RCC_PLL2DIVR_P2) | (0xC8 & RCC_PLL2DIVR_N2)); + // RCC->CR |= RCC_CR_PLL2ON; + // while (RCC->CR & RCC_CR_PLL2ON == 0) { } + + // Select UART clock source as HSI: + // RCC->D2CCIP2R &= ~(0x18); + // RCC->D2CCIP2R |= 0x18; + +#if defined(POWER_I2C) + + voxl_pm_init(); + +#endif + + +#if defined(USB_CHARGE_LED) && !defined(DEBUG) + usbInit(); + // prime debounce state... + usbPlugged(); + + if (usbPlugged()) { + delaysInit(); +#if defined(AUDIO_MUTE_GPIO) + // Charging can make a buzzing noise + gpio_init(AUDIO_MUTE_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); + gpio_set(AUDIO_MUTE_GPIO); + #endif + while (usbPlugged()) { + delay_ms(1000); + } + pwrOff(); + } +#endif + + // void board_set_bor_level(); + // board_set_bor_level(); + + // Sets 'hardwareOption.pcbrev' as well + pwrInit(); + boardInitModulePorts(); + +#if defined(STATUS_LEDS) + ledInit(); + ledGreen(); +#endif + + keysInit(); + switchInit(); + +#if defined(ROTARY_ENCODER_NAVIGATION) + rotaryEncoderInit(); +#endif + + delaysInit(); + __enable_irq(); + + if (!adcInit(&_adc_driver)) + TRACE("adcInit failed"); + + lcdInit(); // delaysInit() must be called before + + timersInit(); + // usbInit(); + +#if defined(DEBUG) && defined(AUX_SERIAL) + serialSetMode(SP_AUX1, UART_MODE_DEBUG); // indicate AUX1 is used + serialInit(SP_AUX1, UART_MODE_DEBUG); // early AUX1 init +#endif + +#if defined(DEBUG) + // Freeze timers & watchdog when core is halted + // DBGMCU->APB1FZ = 0x00E009FF; + // DBGMCU->APB2FZ = 0x00070003; + // TODO: define these for the H7 +#endif + +#if defined(PWR_BUTTON_PRESS) // TODO: re-enable + if (WAS_RESET_BY_WATCHDOG_OR_SOFTWARE()) { + pwrOn(); + } +#endif + +#if defined(USB_CHARGER) + usbChargerInit(); +#endif + +#if defined(RTCLOCK) + rtcInit(); // RTC must be initialized before rambackupRestore() is called +#endif + + backlightInit(); + + gpio_set(GPIO_PIN(GPIOH, 2)); + +#if defined(GUI) + lcdSetContrast(true); +#endif +} +#endif + +void boardOff() +{ +#if defined(STATUS_LEDS) && !defined(BOOT) + ledOff(); +#endif + + BACKLIGHT_DISABLE(); + + +#if defined(PWR_BUTTON_PRESS) + while (pwrPressed()) { + WDG_RESET(); + } +#endif + +// #if defined(MANUFACTURER_RADIOMASTER) && defined(STM32F407xx) +// lcdInit(); +// #endif + + lcdOff(); + SysTick->CTRL = 0; // turn off systick + pwrOff(); + + // disable interrupts + __disable_irq(); + + while (1) { + WDG_RESET(); +#if defined(PWR_BUTTON_PRESS) + // X9E/X7 needs watchdog reset because CPU is still running while + // the power key is held pressed by the user. + // The power key should be released by now, but we must make sure + if (!pwrPressed()) { + // Put the CPU into sleep to reduce the consumption, + // it might help with the RTC reset issue + //PWR->CR |= PWR_CR_CWUF; + /* Select STANDBY mode */ + //PWR->CR |= PWR_CR_PDDS; + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + /* Request Wait For Event */ + __WFE(); + } +#endif + } + + // this function must not return! +} diff --git a/radio/src/targets/modalai/board.h b/radio/src/targets/modalai/board.h new file mode 100644 index 00000000000..b89e97e6f6d --- /dev/null +++ b/radio/src/targets/modalai/board.h @@ -0,0 +1,270 @@ +/* + * Copyright (C) EdgeTX + * + * Based on code named + * opentx - https://github.com/opentx/opentx + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#pragma once + +#include +#include "hal.h" +#include "hal/serial_port.h" +#include "hal/watchdog_driver.h" + +#include "definitions.h" +#include "edgetx_constants.h" +#include "board_common.h" + +#if defined(ROTARY_ENCODER_NAVIGATION) +// Rotary Encoder driver +void rotaryEncoderInit(); +void rotaryEncoderCheck(); +#endif + +#define FLASHSIZE 0x80000 // 512k +#define FLASH_PAGESIZE 256 +#define BOOTLOADER_SIZE 0x8000 +#define FIRMWARE_ADDRESS 0x08000000 +#define FIRMWARE_LEN(fsize) (fsize - BOOTLOADER_SIZE) +#define FIRMWARE_MAX_LEN (FLASHSIZE - BOOTLOADER_SIZE) +#define APP_START_ADDRESS (uint32_t)(FIRMWARE_ADDRESS + BOOTLOADER_SIZE) + +#define LUA_MEM_MAX (0) // max allowed memory usage for complete Lua (in bytes), 0 means unlimited + +#define BOOTLOADER_KEYS 0x42 + + +extern uint16_t sessionTimer; + +// Board driver +void boardInit(); +void boardOff(); + +// PCBREV driver +enum { + // X7 + PCBREV_X7_STD = 0, + PCBREV_X7_40 = 1, +}; + +// Pulses driver +//#define INTERNAL_MODULE_ON() gpio_set(INTMODULE_PWR_GPIO) +//#define INTERNAL_MODULE_OFF() gpio_clear(INTMODULE_PWR_GPIO) +#define INTERNAL_MODULE_ON() +#define INTERNAL_MODULE_OFF() + +#if (defined(INTERNAL_MODULE_PXX1) || defined(INTERNAL_MODULE_PXX2)) && (!defined(PCBX9LITE) || defined(PCBX9LITES)) + #define HARDWARE_INTERNAL_RAS +#endif + +//#define EXTERNAL_MODULE_ON() EXTERNAL_MODULE_PWR_ON() +//#define EXTERNAL_MODULE_OFF() EXTERNAL_MODULE_PWR_OFF() +#define EXTERNAL_MODULE_ON() +#define EXTERNAL_MODULE_OFF() + +// Trainer driver +#define SLAVE_MODE() (g_model.trainerData.mode == TRAINER_MODE_SLAVE) + +// Not supporting a trainer +#define TRAINER_CONNECTED() false + +#define NUM_FUNCTIONS_SWITCHES 0 + +PACK(typedef struct { + uint8_t pcbrev:2; +}) HardwareOptions; + +extern HardwareOptions hardwareOptions; + +// NI-MH 7.2V +// #define BATTERY_WARN 65 // 6.5V +// #define BATTERY_MIN 60 // 6.0V +// #define BATTERY_MAX 80 // 8.0V +#define BATTERY_WARN 0 // 6.5V +#define BATTERY_MIN 0 // 6.0V +#define BATTERY_MAX 80 // 8.0V + +#define BATT_SCALE 123 + +#if defined(__cplusplus) && !defined(SIMU) +extern "C" { +#endif + +// Power driver +#define SOFT_PWR_CTRL +#if defined(PWR_BUTTON_PRESS) +# define STARTUP_ANIMATION +#endif + +void pwrInit(); +uint32_t pwrCheck(); +void pwrOn(); +void pwrOff(); +bool pwrPressed(); +bool pwrOffPressed(); +void pwrResetHandler(); +#define pwrForcePressed() false + +// Backlight driver +#if defined(OLED_SCREEN) +#define BACKLIGHT_DISABLE() lcdSetRefVolt(0) +#define BACKLIGHT_FORCED_ON 255 +#else +#define BACKLIGHT_DISABLE() backlightDisable() +#define BACKLIGHT_FORCED_ON 101 +#endif + + +void backlightInit(); +void backlightDisable(); +void backlightFullOn(); +uint8_t isBacklightEnabled(); + +#if defined(PCBX9E) || defined(PCBX9DP) + void backlightEnable(uint8_t level, uint8_t color); + #define BACKLIGHT_ENABLE() \ + backlightEnable(currentBacklightBright, g_eeGeneral.backlightColor) +#elif defined(OLED_SCREEN) + #define BACKLIGHT_ENABLE() lcdSetRefVolt(currentBacklightBright) +#else + void backlightEnable(uint8_t level); + #define BACKLIGHT_ENABLE() backlightEnable(currentBacklightBright) +#endif + +#if defined(__cplusplus) && !defined(SIMU) +} +#endif + +// Debug driver +void debugPutc(const char c); + +// Audio driver +void audioInit() ; +void audioEnd() ; +void dacStart(); +void dacStop(); +void setSampleRate(uint32_t frequency); +#define VOLUME_LEVEL_MAX 23 +#define VOLUME_LEVEL_DEF 12 +#if !defined(SOFTWARE_VOLUME) +void setScaledVolume(uint8_t volume); +void setVolume(uint8_t volume); +int32_t getVolume(); +#endif +#if defined(AUDIO_SPEAKER_ENABLE_GPIO) +void initSpeakerEnable(); +void enableSpeaker(); +void disableSpeaker(); +#else +static inline void initSpeakerEnable() { } +static inline void enableSpeaker() { } +static inline void disableSpeaker() { } +#endif +#if defined(HEADPHONE_TRAINER_SWITCH_GPIO) +void initHeadphoneTrainerSwitch(); +void enableHeadphone(); +void enableTrainer(); +#else +static inline void initHeadphoneTrainerSwitch() { } +static inline void enableHeadphone() { } +static inline void enableTrainer() { } +#endif +#if defined(JACK_DETECT_GPIO) +void initJackDetect(); +bool isJackPlugged(); +#endif +void audioConsumeCurrentBuffer(); +#define audioDisableIrq() __disable_irq() +#define audioEnableIrq() __enable_irq() + +// Haptic driver +// void hapticInit(); +// void hapticOff(); +// #if defined(HAPTIC_PWM) +// void hapticOn(uint32_t pwmPercent); +// #else +// void hapticOn(); +// #endif + +#define DEBUG_BAUDRATE 115200 +#define LUA_DEFAULT_BAUDRATE 115200 + +const etx_serial_port_t* auxSerialGetPort(int port_nr); + +// USB Charger +#if defined(USB_CHARGER) +void usbChargerInit(); +bool usbChargerLed(); +#endif + +// LED driver +void ledInit(); +void ledOff(); +void ledRed(); +void ledGreen(); +void ledBlue(); + +// LCD driver +#define LCD_W 128 +#define LCD_H 64 +#define LCD_DEPTH 1 +#define IS_LCD_RESET_NEEDED() true +#define LCD_CONTRAST_MIN 10 +#define LCD_CONTRAST_MAX 30 +#define LCD_CONTRAST_DEFAULT 20 + +#define IS_LCD_RESET_NEEDED() true + +void lcdInit(); +void lcdInitFinish(); +void lcdOff(); + +// TODO lcdRefreshWait() stub in simpgmspace +#if defined(LCD_DMA) && !defined(SIMU) +void lcdRefreshWait(); +#else +#define lcdRefreshWait() +#endif +void lcdRefresh(bool wait=true); // TODO uint8_t wait to simplify this +void lcdSetRefVolt(unsigned char val); +#if LCD_W == 128 +void lcdSetInvert(bool invert); +#endif +#ifdef __cplusplus +void lcdSetContrast(bool useDefault = false); +#endif +void lcdFlushed(); + + +#if defined(CROSSFIRE) +#define TELEMETRY_FIFO_SIZE 128 +#else +#define TELEMETRY_FIFO_SIZE 64 +#endif + +#define INTMODULE_FIFO_SIZE 128 + + +#define BATTERY_DIVIDER 23711 // = 2047*128*BATT_SCALE/(100*(VREF*(160+499)/160)) + +#define VOLTAGE_DROP 45 + +#define NUM_TRIMS 4 + +#define NUM_TRIMS_KEYS (NUM_TRIMS * 2) + diff --git a/radio/src/targets/modalai/bootloader/boot_menu.cpp b/radio/src/targets/modalai/bootloader/boot_menu.cpp new file mode 100644 index 00000000000..6c4e97b5c51 --- /dev/null +++ b/radio/src/targets/modalai/bootloader/boot_menu.cpp @@ -0,0 +1,162 @@ +/* + * Copyright (C) EdgeTX + * + * Based on code named + * opentx - https://github.com/opentx/opentx + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + #include + + #include "board.h" + #include "lcd.h" + + #include "translations.h" + + #include "fw_version.h" + #include "translations.h" + #include "../../common/arm/stm32/bootloader/boot.h" + #include "bootloader/firmware_files.h" + + void bootloaderInitScreen() + { + lcdInit(); + lcdSetContrast(true); + + backlightInit(); + #if defined(LCD_BRIGHTNESS_DEFAULT) + backlightEnable(LCD_BRIGHTNESS_DEFAULT); + #else + backlightFullOn(); + #endif + } + + static void bootloaderDrawMsg(unsigned int x, const char *str, uint8_t line, bool inverted) + { + lcdDrawSizedText(x, (line + 2) * FH, str, DISPLAY_CHAR_WIDTH, inverted ? INVERS : 0); + } + + void bootloaderDrawFilename(const char *str, uint8_t line, bool selected) + { + bootloaderDrawMsg(INDENT_WIDTH, str, line, selected); + } + + bool checkFirmwareFlavor(const char * flavour) + { + if (strncmp(flavour,FLAVOUR, sizeof(FLAVOUR) - 1) != 0) + return false; + + char * tmp = (char *) flavour; + while (*tmp != 0) tmp++; + if ((tmp - flavour) != (sizeof(FLAVOUR) - 1)) + return false; + + return true; + } + + void bootloaderDrawScreen(BootloaderState st, int opt, const char *str) + { + lcdClear(); + lcdDrawText(LCD_W / 2, 0, BOOTLOADER_TITLE, CENTERED); + lcdInvertLine(0); + + if (st == ST_START) { + lcdDrawText(3*FW, 2*FH, TR_BL_WRITE_FW, opt == 0 ? INVERS : 0); + lcdDrawText(3*FW, 3*FH, TR_BL_EXIT, opt == 1 ? INVERS : 0); + + lcdDrawText(LCD_W / 2, 5 * FH + FH / 2, TR_BL_OR_PLUGIN_USB_CABLE, CENTERED); + + const char * vers = getFirmwareVersion(); + #if LCD_W < 212 + // Remove "edgetx-" from string + if (strncmp(vers, "edgetx-", 7) == 0) + vers += 7; + #endif + lcdDrawCenteredText(7 * FH, vers); + lcdInvertLine(7); + } + else if (st == ST_USB) { + lcdDrawCenteredText(4 * FH, TR_BL_USB_CONNECTED); + } + else if (st == ST_DIR_CHECK) { + if (opt == FR_NO_PATH) { + bootloaderDrawMsg(INDENT_WIDTH, TR_BL_DIR_MISSING, 1, false); + bootloaderDrawMsg(INDENT_WIDTH, getFirmwarePath(), 2, false); + } + else { + bootloaderDrawMsg(INDENT_WIDTH, TR_BL_DIR_EMPTY, 1, false); + } + } + else if (st == ST_FLASH_CHECK) { + if (opt == FC_ERROR) { + bootloaderDrawMsg(0, TR_BL_INVALID_FIRMWARE, 2, false); + } + else if (opt == FC_OK) { + bool flavorCheck = false; + VersionTag tag; + getFileFirmwareVersion(&tag); + #if LCD_W < 212 + // Remove "edgetx-" from string + flavorCheck = checkFirmwareFlavor(tag.flavour); + #else + flavorCheck = checkFirmwareFlavor(tag.flavour); + #endif + bootloaderDrawMsg(INDENT_WIDTH, tag.version, 0, false); + if (flavorCheck) + bootloaderDrawMsg(0, TR_BL_HOLD_ENTER_TO_START, 2, false); + else + bootloaderDrawMsg(0, TR_BL_INVALID_FIRMWARE, 2, false); + } + } + else if (st == ST_FLASHING) { + lcdDrawCenteredText(4 * FH, TR_BL_WRITING_FW); + + lcdDrawRect(3, 6 * FH + 4, (LCD_W - 8), 7); + lcdDrawSolidHorizontalLine(5, 6 * FH + 6, (LCD_W - 12) * opt / 100, FORCE); + lcdDrawSolidHorizontalLine(5, 6 * FH + 7, (LCD_W - 12) * opt / 100, FORCE); + lcdDrawSolidHorizontalLine(5, 6 * FH + 8, (LCD_W - 12) * opt / 100, FORCE); + } + else if (st == ST_FLASH_DONE) { + lcdDrawCenteredText(4 * FH, TR_BL_WRITING_COMPL); + } + } + + uint32_t bootloaderGetMenuItemCount(int baseCount) + { + return baseCount; + } + + bool bootloaderRadioMenu(uint32_t menuItem, event_t event) + { + return true; + } + + void blExit(void) + { + #if defined(RADIO_COMMANDO8) + lcdClear(); + lcdDrawText(2, 22, TR_BL_POWER_KEY); + lcdDrawText(2, 33, TR_BL_FLASH_EXIT); + lcdRefresh(); + lcdRefreshWait(); + while(1); + #else + lcdClear(); + lcdRefresh(); + lcdRefreshWait(); + #endif + } + \ No newline at end of file diff --git a/radio/src/targets/modalai/bsp_io.h b/radio/src/targets/modalai/bsp_io.h new file mode 100644 index 00000000000..b74cedd309c --- /dev/null +++ b/radio/src/targets/modalai/bsp_io.h @@ -0,0 +1,21 @@ +/* + * Copyright (C) EdgeTX + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#pragma once + +#include "hal/switch_driver.h" +#include "stm32_switch_driver.h" + +SwitchHwPos bsp_get_switch_position(const stm32_switch_t *sw, SwitchCategory cat, uint8_t idx) {return SWITCH_HW_MID;} diff --git a/radio/src/targets/modalai/hal.h b/radio/src/targets/modalai/hal.h new file mode 100644 index 00000000000..6e03540cd8e --- /dev/null +++ b/radio/src/targets/modalai/hal.h @@ -0,0 +1,384 @@ +/* + * Copyright (C) EdgeTX + * + * Based on code named + * opentx - https://github.com/opentx/opentx + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#pragma once + +#warning TODO: Verify/Set these numbers +#define CPU_FREQ 600000000 + +#define PERI1_FREQUENCY 150000000 +#define PERI2_FREQUENCY 150000000 +#define TIMER_MULT_APB1 2 +#define TIMER_MULT_APB2 2 + +#define TELEMETRY_EXTI_PRIO 0 // required for soft serial + +/* Timers Allocation: + * TIM5 = Backlight + * TIM7 = 2 MHz counter + * + * TIM12 = Mixer scheduler + * TIM14 = 5 ms counter + */ + +/* DMA Allocation: + DMA/Stream/Channel + 1/7/0? LCD + 1/0/0 ADC1 + 2/3/4 SDIO +*/ + +// Zorro Blue official hardware config + +// Keys + +#define KEYS_GPIO_REG_PAGEUP GPIOD +#define KEYS_GPIO_PIN_PAGEUP LL_GPIO_PIN_14 // PD.14 +#define KEYS_GPIO_REG_PAGEDN GPIOH +#define KEYS_GPIO_PIN_PAGEDN LL_GPIO_PIN_6 // PH.06 +#define KEYS_GPIO_REG_EXIT GPIOD +#define KEYS_GPIO_PIN_EXIT LL_GPIO_PIN_11 // PD.11 +#define KEYS_GPIO_REG_ENTER GPIOB +#define KEYS_GPIO_PIN_ENTER LL_GPIO_PIN_2 // PB.02 +#define KEYS_GPIO_REG_SYS GPIOD +#define KEYS_GPIO_PIN_SYS LL_GPIO_PIN_10 // PD.10 +#define KEYS_GPIO_REG_MDL GPIOG +#define KEYS_GPIO_PIN_MDL LL_GPIO_PIN_1 // PG.01 +#define KEYS_GPIO_REG_TELE GPIOG +#define KEYS_GPIO_PIN_TELE LL_GPIO_PIN_0 // PG.00 + +// Rotary Encoder + +#define ROTARY_ENCODER_NAVIGATION +#define ROTARY_ENCODER_GPIO GPIOC +#define ROTARY_ENCODER_GPIO_PIN_A LL_GPIO_PIN_1 // PC.01 +#define ROTARY_ENCODER_GPIO_PIN_B LL_GPIO_PIN_2 // PC.02 +#define ROTARY_ENCODER_POSITION() (((ROTARY_ENCODER_GPIO->IDR >> 8) & 0x02) + ((ROTARY_ENCODER_GPIO->IDR >> 12) & 0x01)) +#define ROTARY_ENCODER_EXTI_LINE1 LL_EXTI_LINE_12 +#define ROTARY_ENCODER_EXTI_LINE2 LL_EXTI_LINE_9 +#define ROTARY_ENCODER_EXTI_PORT LL_SYSCFG_EXTI_PORTC +#define ROTARY_ENCODER_EXTI_SYS_LINE1 LL_SYSCFG_EXTI_LINE1 +#define ROTARY_ENCODER_EXTI_SYS_LINE2 LL_SYSCFG_EXTI_LINE2 +// ROTARY_ENCODER_EXTI_LINE1 IRQ +#if !defined(USE_EXTI1_IRQ) + #define USE_EXTI1_IRQ + #define EXTI1_IRQ_Priority 5 +#endif +#if !defined(USE_EXTI2_IRQ) + #define USE_EXTI2_IRQ + #define EXTI2_IRQ_Priority 5 +#endif +#define ROTARY_ENCODER_INVERTED + +#define ROTARY_ENCODER_TIMER TIM5 +#define ROTARY_ENCODER_TIMER_IRQn TIM5_IRQn +#define ROTARY_ENCODER_TIMER_IRQHandler TIM5_IRQHandler + +// Trims +// #warning Disconnect all of these +// #define TRIMS_GPIO_REG_LHL GPIOH +// #define TRIMS_GPIO_PIN_LHL LL_GPIO_PIN_15 // PH.15 +// #define TRIMS_GPIO_REG_LHR GPIOH +// #define TRIMS_GPIO_PIN_LHR LL_GPIO_PIN_15 // PH.15 +// #define TRIMS_GPIO_REG_LVD GPIOH +// #define TRIMS_GPIO_PIN_LVD LL_GPIO_PIN_15 // PH.15 +// #define TRIMS_GPIO_REG_LVU GPIOH +// #define TRIMS_GPIO_PIN_LVU LL_GPIO_PIN_15 // PH.15 +// #define TRIMS_GPIO_REG_RVD GPIOH +// #define TRIMS_GPIO_PIN_RVD LL_GPIO_PIN_15 // PH.15 +// #define TRIMS_GPIO_REG_RHL GPIOH +// #define TRIMS_GPIO_PIN_RHL LL_GPIO_PIN_15 // PH.15 +// #define TRIMS_GPIO_REG_RVU GPIOH +// #define TRIMS_GPIO_PIN_RVU LL_GPIO_PIN_15 // PH.15 +// #define TRIMS_GPIO_REG_RHR GPIOH +// #define TRIMS_GPIO_PIN_RHR LL_GPIO_PIN_15 // PH.15 + +// Switches +// #define STORAGE_SWITCH_A +// #define HARDWARE_SWITCH_A +// #define SWITCHES_GPIO_REG_A GPIOG +// #define SWITCHES_GPIO_PIN_A LL_GPIO_PIN_2 // PG.02 + +#define STORAGE_SWITCH_B +#define HARDWARE_SWITCH_B +#define SWITCHES_GPIO_REG_B_L GPIOD +#define SWITCHES_GPIO_PIN_B_L LL_GPIO_PIN_12 // PD.12 +#define SWITCHES_GPIO_REG_B_H GPIOD +#define SWITCHES_GPIO_PIN_B_H LL_GPIO_PIN_13 // PD.13 + +#define STORAGE_SWITCH_C +#define HARDWARE_SWITCH_C +#define SWITCHES_GPIO_REG_C_L GPIOH +#define SWITCHES_GPIO_PIN_C_L LL_GPIO_PIN_11 // PH.11 +#define SWITCHES_GPIO_REG_C_H GPIOH +#define SWITCHES_GPIO_PIN_C_H LL_GPIO_PIN_12 // PH.12 + +// #define STORAGE_SWITCH_D +// #define HARDWARE_SWITCH_D +// #define SWITCHES_GPIO_REG_D GPIOG +// #define SWITCHES_GPIO_PIN_D LL_GPIO_PIN_3 // PG.3 + +#define STORAGE_SWITCH_E +#define HARDWARE_SWITCH_E +#define SWITCHES_GPIO_REG_E GPIOE +#define SWITCHES_GPIO_PIN_E LL_GPIO_PIN_12 // PE.12 + +#define STORAGE_SWITCH_F +#define HARDWARE_SWITCH_F +#define SWITCHES_GPIO_REG_F GPIOF +#define SWITCHES_GPIO_PIN_F LL_GPIO_PIN_10 // PF.10 + +#warning consider changing sample time (seems low) +#define ADC_SAMPTIME LL_ADC_SAMPLINGTIME_8CYCLES_5 +#define ADC_CHANNEL_RTC_BAT LL_ADC_CHANNEL_VBAT + +#define ADC_MAIN ADC1 +#define ADC_DMA DMA1 +#define ADC_DMA_CHANNEL LL_DMAMUX1_REQ_ADC1 +#define ADC_DMA_STREAM LL_DMA_STREAM_0 +#define ADC_DMA_STREAM_IRQ DMA1_Stream0_IRQn +#define ADC_DMA_STREAM_IRQHandler DMA1_Stream0_IRQHandler +#define HARDWARE_POT1 +#define HARDWARE_POT2 +#define ADC_GPIO_PIN_STICK_RV LL_GPIO_PIN_1 // PB.01 +#define ADC_GPIO_PIN_STICK_RH LL_GPIO_PIN_12 // PF.12 +#define ADC_GPIO_PIN_STICK_LV LL_GPIO_PIN_1 // PA.01 +#define ADC_GPIO_PIN_STICK_LH LL_GPIO_PIN_0 // PC.00 +#define ADC_CHANNEL_STICK_RV LL_ADC_CHANNEL_5 // ADC1_CH5 +#define ADC_CHANNEL_STICK_RH LL_ADC_CHANNEL_6 // ADC1_CH6 +#define ADC_CHANNEL_STICK_LV LL_ADC_CHANNEL_17 // ADC1_CH17 +#define ADC_CHANNEL_STICK_LH LL_ADC_CHANNEL_10 // ADC1_CH10 +#define ADC_CHANNEL_POT1 LL_ADC_CHANNEL_9 // ADC1_CH9 +#define ADC_CHANNEL_POT2 LL_ADC_CHANNEL_16 // ADC1_CH16 +#define ADC_GPIO_PIN_POT1 LL_GPIO_PIN_0 // PB.00 +#define ADC_GPIO_PIN_POT2 LL_GPIO_PIN_0 // PA.00 +// !#define ADC_GPIO_PIN_BATT LL_GPIO_PIN_0 // PC.00 // This pin is disconnected (hopefully that doesn't trigger anything) +#define ADC_GPIOA_PINS (ADC_GPIO_PIN_STICK_LV | ADC_GPIO_PIN_POT2) +#define ADC_GPIOB_PINS (ADC_GPIO_PIN_STICK_RV | ADC_GPIO_PIN_POT1) +#define ADC_GPIOC_PINS (ADC_GPIO_PIN_STICK_LH) +#define ADC_GPIOF_PINS (ADC_GPIO_PIN_STICK_RH) +// !#define ADC_CHANNEL_BATT LL_ADC_CHANNEL_10 +#define ADC_VREF_PREC2 330 +#warning verify adc direction +#define ADC_DIRECTION {-1, 1, 1, -1, -1, 1, 1, 1} + +// PWR and LED driver + +// #warning unsure what these do, TODO: Remove these buttons completely +// #define PWR_SWITCH_GPIO GPIO_PIN(GPIOC, 10) // PC.06 +// #define PWR_ON_GPIO GPIO_PIN(GPIOC, 11) // PC.07 + +#define USE_LEDS +#ifdef USE_LEDS +#warning remove these later +#define STATUS_LEDS +#define GPIO_LED_GPIO_ON gpio_clear +#define GPIO_LED_GPIO_OFF gpio_set +#define LED_GREEN_GPIO GPIO_PIN(GPIOI, 5) // PE.04 +#define LED_RED_GPIO GPIO_PIN(GPIOI, 6) // PE.03 +#define LED_BLUE_GPIO GPIO_PIN(GPIOI, 7) // PA.05 +#endif // USE_LEDS + +// Internal Module +#define INTMODULE_BOOTCMD_GPIO GPIO_PIN(GPIOI, 6) // PI.06 (Disconnected) +#define INTMODULE_PWR_GPIO GPIO_PIN(GPIOI, 7) // PI.07 (Disconnected) +#define INTMODULE_BOOTCMD_DEFAULT 0 // RESET +#define INTMODULE_TX_GPIO GPIO_PIN(GPIOC, 6) // PC.06 +#define INTMODULE_RX_GPIO GPIO_PIN(GPIOC, 7) // PC.07 +#define INTMODULE_USART USART6 +#define INTMODULE_USART_IRQHandler USART6_IRQHandler +#define INTMODULE_USART_IRQn USART6_IRQn +// #define INTMODULE_DMA DMA2 +// #define INTMODULE_DMA_STREAM LL_DMA_STREAM_7 +// #define INTMODULE_DMA_STREAM_IRQ DMA2_Stream7_IRQn +// #define INTMODULE_DMA_STREAM_IRQHandler DMA2_Stream7_IRQHandler +// #define INTMODULE_DMA_CHANNEL LL_DMA_CHANNEL_4 +// #define INTMODULE_RX_DMA DMA2 +// #define INTMODULE_RX_DMA_STREAM LL_DMA_STREAM_2 +// #define INTMODULE_RX_DMA_CHANNEL LL_DMA_CHANNEL_4 + +// Software IRQ (Prio 5 -> FreeRTOS compatible) +//#define TELEMETRY_RX_FRAME_EXTI_LINE LL_EXTI_LINE_4 +//#define USE_EXTI4_IRQ +//#define EXTI4_IRQ_Priority 5 + +// USB Charger +#if defined(USB_CHARGER) + #error should be off + #define USB_CHARGER_GPIO GPIO_PIN(GPIOB, 5) +#endif + +#warning can probably increase this +#define SPORT_MAX_BAUDRATE 400000 + +// USB +#define USB_GPIO_VBUS GPIO_PIN(GPIOA, 9) // PA.09 +#define USB_GPIO_DM GPIO_PIN(GPIOA, 11) // PA.11 +#define USB_GPIO_DP GPIO_PIN(GPIOA, 12) // PA.12 +#define USB_GPIO_AF GPIO_AF10 + +// BackLight +#warning Backlight settings (check bus and frequency) +#define BACKLIGHT_TIMER_FREQ (PERI1_FREQUENCY * TIMER_MULT_APB1) +#define BACKLIGHT_TIMER TIM5 +#define BACKLIGHT_GPIO GPIO_PIN(GPIOH, 10) // PH.10 +#define BACKLIGHT_GPIO_AF GPIO_AF2 // TIM5 CH1 +#define BACKLIGHT_CCMR1 TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 // Channel1, PWM +#define BACKLIGHT_CCER TIM_CCER_CC1E +#define BACKLIGHT_COUNTER_REGISTER BACKLIGHT_TIMER->CCR1 + +// LCD driver +#define LCD_MOSI_GPIO GPIO_PIN(GPIOE, 6) // PE.06 +#define LCD_CLK_GPIO GPIO_PIN(GPIOE, 2) // PE.02 +#define LCD_A0_GPIO GPIO_PIN(GPIOE, 4) // PE.04 +#define LCD_NCS_GPIO GPIO_PIN(GPIOE, 3) // PE.03 +#define LCD_RST_GPIO GPIO_PIN(GPIOE, 5) // PE.05 +#define LCD_DMA DMA1 +#define LCD_DMA_Stream DMA1_Stream7 +#define LCD_DMA_Stream_Num LL_DMA_STREAM_7 +#define LCD_DMA_Stream_IRQn DMA1_Stream7_IRQn +#define LCD_DMA_Stream_IRQHandler DMA1_Stream7_IRQHandler +#define LCD_DMA_FLAGS (DMA_HIFCR_CTCIF7 | DMA_HIFCR_CHTIF7 | DMA_HIFCR_CTEIF7 | DMA_HIFCR_CDMEIF7 | DMA_HIFCR_CFEIF7) +#define LCD_DMA_FLAG_INT DMA_HIFCR_CTCIF7 +#define LCD_SPI SPI4 +#define LCD_GPIO_AF GPIO_AF5 // For SPI4 +#define LCD_VERTICAL_INVERT +#define LCD_SPI_PRESCALER 0x20000000 + + +// TODO: M0207 has a SPI EEPROM +// I2C Bus 1: EEPROM and CAT5137 digital pot for volume control +// #define I2C_B1 I2C1 +// #define I2C_B1_GPIO_AF LL_GPIO_AF_4 + +// #warning remove eeprom +// #define I2C_B1_SCL_GPIO GPIO_PIN(GPIOB, 8) // PB.08 +// #define I2C_B1_SDA_GPIO GPIO_PIN(GPIOB, 9) // PB.09 + +// EEPROM +// #warning remove eeprom +// #define EEPROM_WP_GPIO GPIOD +// #define EEPROM_WP_GPIO_PIN LL_GPIO_PIN_10 // PD.10 + +// #define I2C_B1_CLK_RATE 400000 + + +// FC2 internal hardware + +//SD - SDIO +// #define SD_SDIO_DMA DMA2 +// #define SD_SDIO_DMA_STREAM DMA2_Stream3 +// #define SD_SDIO_DMA_CHANNEL LL_DMA_CHANNEL_4 +// #define SD_SDIO_DMA_IRQn DMA2_Stream3_IRQn +// #define SD_SDIO_DMA_IRQHANDLER DMA2_Stream3_IRQHandler +// #define SD_SDIO_DMAMUX DMAMUX1_Channel2 +// #define SD_SDIO_CLK_DIV(fq) ((48000000 / (fq)) - 2) +// #define SD_SDIO_INIT_CLK_DIV SD_SDIO_CLK_DIV(400000) +// #define SD_SDIO_TRANSFER_CLK_DIV SD_SDIO_CLK_DIV(24000000) +#define STORAGE_USE_SDIO +#define SD_SDIO_TRANSFER_CLK_DIV SDMMC_NSPEED_CLK_DIV + +// Define the pins just to be sure +#define SD_SDIO_PIN_D0 GPIO_PIN(GPIOC, 8) // PC.08 +#define SD_SDIO_AF_D0 GPIO_AF12 +#define SD_SDIO_PIN_D1 GPIO_PIN(GPIOC, 9) // PC.09 +#define SD_SDIO_AF_D1 GPIO_AF12 +#define SD_SDIO_PIN_D2 GPIO_PIN(GPIOC, 10) // PC.10 +#define SD_SDIO_AF_D2 GPIO_AF12 +#define SD_SDIO_PIN_D3 GPIO_PIN(GPIOC, 11) // PC.11 +#define SD_SDIO_AF_D3 GPIO_AF12 +#define SD_SDIO_PIN_CMD GPIO_PIN(GPIOD, 2) // PD.02 +#define SD_SDIO_AF_CMD GPIO_AF12 +#define SD_SDIO_PIN_CLK GPIO_PIN(GPIOC, 12) // PC.12 +#define SD_SDIO_AF_CLK GPIO_AF12 +// Use SDMMC1 +#define SD_SDIO SDMMC1 + +// Power monitoring + + +#define VOXLPM_INA231_ADDR_VBATT 0x44 << 1 +#define VOXLPM_INA231_ADDR_P5_12VDC 0x45 << 1 + +/* INA231 Registers addresses */ +#define INA231_REG_CONFIG 0x00 +#define INA231_REG_SHUNTVOLTAGE 0x01 +#define INA231_REG_BUSVOLTAGE 0x02 +#define INA231_REG_POWER 0x03 +#define INA231_REG_CURRENT 0x04 +#define INA231_REG_CALIBRATION 0x05 +#define INA231_REG_MASKENABLE 0x06 +#define INA231_REG_ALERTLIMIT 0x07 + +/* [0:2] Mode - Shunt and bus, 111, continuous (INA231A default) */ +#define INA231_CONFIG_MODE (0x07 << 0) +/* [5:3] Shunt Voltage Conversion Time, 100, 1.1ms (INA231A default) */ +#define INA231_CONFIG_SHUNT_CT (0x04 << 3) +/* [8:6] Shunt Voltage Conversion Time, 100, 1.1ms (INA231A default) */ +#define INA231_CONFIG_BUS_CT (0x04 << 6) +/* [11:9] Averaging Mode, 010, 16 */ +#define INA231_CONFIG_AVG (0x02 << 9) +/* [1] Reset bit */ +#define INA231_RST_BIT (0x01 << 15) +/* Configuration register settings */ +#define INA231_CONFIG (INA231_CONFIG_MODE+INA231_CONFIG_SHUNT_CT+INA231_CONFIG_BUS_CT+INA231_CONFIG_AVG) + +#define INA231_CONST 0.00512f /* is an internal fixed value used to ensure scaling is maintained properly */ +#define INA231_VBUSSCALE 0.00125f /* LSB of bus voltage is 1.25 mV */ +#define INA231_VSHUNTSCALE 0.0000025f /* LSB of shunt voltage is 2.5 uV */ + +/* From SCH-M00041 REVB */ +#define VOXLPM_INA231_VBAT_SHUNT 0.0005f /* VBAT shunt is 500 micro-ohm */ +#define VOXLPM_INA231_VREG_SHUNT 0.005f /* VREG output shunt is 5 milli-ohm */ +#define VOXLPM_INA231_VBAT_MAX_AMPS 90.0f /* 90.0 Amps max through VBAT sense resistor */ +#define VOXLPM_INA231_VREG_MAX_AMPS 6.0f /* 6.0 Amps max through VREG sense resistor */ + +/* ina231.pdf section 8.5 */ +#define VOXLPM_INA231_VBAT_I_LSB (VOXLPM_INA231_VBAT_MAX_AMPS/32768.0f) +#define VOXLPM_INA231_VREG_I_LSB (VOXLPM_INA231_VREG_MAX_AMPS/32768.0f) + +#define POWER_I2C I2C1 // Comment this out to disable I2C +#define POWER_I2C_PIN_SDA GPIO_PIN(GPIOB, 9) // PB.09 +#define POWER_I2C_SDA_AF GPIO_AF4 +#define POWER_I2C_PIN_SCL GPIO_PIN(GPIOB, 8) // PB.08 +#define POWER_I2C_SCL_AF GPIO_AF4 +#define POWER_I2C_TIMING_REGISTER 0x20707DBDU // 100KHz clock +#define POWER_I2C_SLAVE_ADDRESS VOXLPM_INA231_ADDR_VBATT // or 0x45 + + +// Audio +// #warning Disable audio and haptics +// #define HAPTIC_GPIO GPIO_PIN(GPIOC, 12) // PC.12 + +// To avoid change in modelsize, todo: remove me +#define STORAGE_BLUETOOTH + +// Millisecond timer +#define MS_TIMER TIM14 +#define MS_TIMER_IRQn TIM8_TRG_COM_TIM14_IRQn +#define MS_TIMER_IRQHandler TIM8_TRG_COM_TIM14_IRQHandler + +// Mixer scheduler timer +#warning check bus / freq +#define MIXER_SCHEDULER_TIMER TIM12 +#define MIXER_SCHEDULER_TIMER_FREQ (PERI1_FREQUENCY * TIMER_MULT_APB1) +#define MIXER_SCHEDULER_TIMER_IRQn TIM8_BRK_TIM12_IRQn +#define MIXER_SCHEDULER_TIMER_IRQHandler TIM8_BRK_TIM12_IRQHandler diff --git a/radio/src/targets/modalai/lcd_driver_aspi.cpp b/radio/src/targets/modalai/lcd_driver_aspi.cpp new file mode 100644 index 00000000000..521d38225c1 --- /dev/null +++ b/radio/src/targets/modalai/lcd_driver_aspi.cpp @@ -0,0 +1,296 @@ +/* + * Copyright (C) EdgeTX + * + * Based on code named + * opentx - https://github.com/opentx/opentx + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "hal/gpio.h" +#include "stm32_gpio.h" + +#include "board.h" +#include "lcd.h" + +#include "hal/abnormal_reboot.h" +#include "timers_driver.h" + +#if !defined(BOOT) +#include "myeeprom.h" +#include "debug.h" +#endif + +#define CONTRAST_OFS 5 +#define RESET_WAIT_DELAY_MS 1300 // Wait time after LCD reset before first command + +bool lcdInitFinished = false; +void lcdInitFinish(); + +#define LCD_NCS_HIGH() gpio_set(LCD_NCS_GPIO) +#define LCD_NCS_LOW() gpio_clear(LCD_NCS_GPIO) + +#define LCD_A0_HIGH() gpio_set(LCD_A0_GPIO) +#define LCD_A0_LOW() gpio_clear(LCD_A0_GPIO) + +#define LCD_RST_HIGH() gpio_set(LCD_RST_GPIO) +#define LCD_RST_LOW() gpio_clear(LCD_RST_GPIO) + +#define LCD_CLK_HIGH() gpio_set(LCD_CLK_GPIO) +#define LCD_CLK_LOW() gpio_clear(LCD_CLK_GPIO) + +#define LCD_MOSI_HIGH() gpio_set(LCD_MOSI_GPIO) +#define LCD_MOSI_LOW() gpio_clear(LCD_MOSI_GPIO) + +void lcdWriteCommand(uint8_t command) +{ + int i = 8; + LCD_A0_LOW(); + + LCD_CLK_HIGH(); + LCD_CLK_HIGH(); + LCD_NCS_LOW(); + + while (i--) { + LCD_CLK_LOW(); + + if (command & 0x80) + LCD_MOSI_HIGH(); + else + LCD_MOSI_LOW(); + + command <<= 1; + + LCD_CLK_LOW(); + LCD_CLK_LOW(); + + LCD_CLK_HIGH(); + LCD_CLK_HIGH(); + } + + LCD_NCS_HIGH(); + LCD_A0_HIGH(); +} + +void lcdWriteData(uint8_t data) +{ + int i = 8; + + LCD_CLK_HIGH(); + LCD_CLK_HIGH(); + LCD_A0_HIGH(); + LCD_NCS_LOW(); + + while (i--) { + LCD_CLK_LOW(); + if (data & 0x80) + LCD_MOSI_HIGH(); + else + LCD_MOSI_LOW(); + + data <<= 1; + + LCD_CLK_LOW(); + LCD_CLK_LOW(); + + LCD_CLK_HIGH(); + LCD_CLK_HIGH(); + } + + LCD_NCS_HIGH(); + LCD_A0_HIGH(); +} + +void lcdStart() +{ + lcdWriteCommand(0x2B); // Panel loading set, Internal VLCD. + delay_ms(20); + lcdWriteCommand(0x25); // Temperature compensation curve definition: 0x25 = -0.05%/oC + lcdWriteCommand(0xEA); // Set bias=1/10: Command table NO.27 + lcdWriteCommand(0x81); // Set Vop +#if defined(BOOT) + lcdWriteCommand(CONTRAST_OFS+25); +#else + lcdWriteCommand(CONTRAST_OFS+g_eeGeneral.contrast); +#endif + lcdWriteCommand(0xA6); // Inverse display off + lcdWriteCommand(0xD1); // Set RGB: Command table NO.21, D1=RGB + lcdWriteCommand(0xD5); // Set color mode 4K and 12bits: Command table NO.22 + lcdWriteCommand(0xA0); // Line rates, 25.2 Klps + lcdWriteCommand(0xC8); // Set N-LINE inversion + lcdWriteCommand(0x1D); // Disable NIV + lcdWriteCommand(0xF1); // Set CEN + lcdWriteCommand(0x3F); // 1/64 DUTY + lcdWriteCommand(0x84); // Disable Partial Display + lcdWriteCommand(0xC4); // MY=1, MX=0 + lcdWriteCommand(0x89); // WA=1, column (CA) increment (+1) first until CA reaches CA boundary, then RA will increment by (+1) + + lcdWriteCommand(0xF8); // Set Window Program Enable, inside modle + lcdWriteCommand(0xF4); // Start column address of RAM program window. + lcdWriteCommand(0x00); + lcdWriteCommand(0xF5); // Start row address of RAM program window. + lcdWriteCommand(0x60); + lcdWriteCommand(0xF6); // End column address of RAM program window. + lcdWriteCommand(0x47); + lcdWriteCommand(0xF7); // End row address of RAM program window. + lcdWriteCommand(0x9F); +} + +void lcdWriteAddress(uint8_t x, uint8_t y) +{ + lcdWriteCommand(x&0x0F); // Set Column Address LSB CA[3:0] + lcdWriteCommand((x>>4) | 0x10); // Set Column Address MSB CA[7:4] + + lcdWriteCommand((y&0x0F) | 0x60); // Set Row Address LSB RA [3:0] + lcdWriteCommand(((y>>4) & 0x0F) | 0x70); // Set Row Address MSB RA [7:4] +} + +#define LCD_WRITE_BIT(bit) \ + if (bit) \ + LCD_MOSI_HIGH(); \ + else \ + LCD_MOSI_LOW(); \ + LCD_CLK_LOW(); \ + LCD_CLK_LOW(); \ + LCD_CLK_LOW(); \ + LCD_CLK_HIGH(); \ + LCD_CLK_HIGH(); + +void lcdRefresh() +{ + if (!lcdInitFinished) { + lcdInitFinish(); + } + + for (uint8_t y=0; y>= 4; + LCD_WRITE_BIT(b & 0x08); + LCD_WRITE_BIT(b & 0x04); + LCD_WRITE_BIT(b & 0x02); + LCD_WRITE_BIT(b & 0x01); + } + + LCD_NCS_HIGH(); + LCD_A0_HIGH(); + + lcdWriteData(0); + } +} + +void lcdHardwareInit() +{ + gpio_init(LCD_MOSI_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); + gpio_init(LCD_CLK_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); + gpio_init(LCD_A0_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); + + gpio_init(LCD_NCS_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); + LCD_NCS_HIGH(); + + gpio_init(LCD_RST_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); +} + +/* + Proper method for turning of LCD module. It must be used, + otherwise we might damage LCD crystals in the long run! +*/ +void lcdOff() +{ + /* + LCD Sleep mode is also good for draining capacitors and enables us + to re-init LCD without any delay + */ + lcdWriteCommand(0xAE); // LCD sleep + delay_ms(3); // wait for caps to drain +} + +void lcdReset() +{ + LCD_RST_LOW(); + delay_ms(1); // only 3 us needed according to data-sheet, we use 1 ms + LCD_RST_HIGH(); +} + +/* + Starts LCD initialization routine. It should be called as + soon as possible after the reset because LCD takes a lot of + time to properly power-on. + + Make sure that delay_ms() is functional before calling this function! +*/ +void lcdInit() +{ + lcdHardwareInit(); + + if (!WAS_RESET_BY_WATCHDOG_OR_SOFTWARE()) { + lcdReset(); + } +} + +/* + Finishes LCD initialization. It is called auto-magically when first LCD command is + issued by the other parts of the code. +*/ +void lcdInitFinish() +{ + lcdInitFinished = true; + + /* + LCD needs longer time to initialize in low temperatures. The data-sheet + mentions a time of at least 150 ms. The delay of 1300 ms was obtained + experimentally. It was tested down to -10 deg Celsius. + + The longer initialization time seems to only be needed for regular Taranis, + the Taranis Plus (9XE) has been tested to work without any problems at -18 deg Celsius. + Therefore the delay for T+ is lower. + + If radio is reset by watchdog or boot-loader the wait is skipped, but the LCD + is initialized in any case. + + This initialization is needed in case the user moved power switch to OFF and + then immediately to ON position, because lcdOff() was called. In any case the LCD + initialization (without reset) is also recommended by the data sheet. + */ + + if (!WAS_RESET_BY_WATCHDOG_OR_SOFTWARE()) { + uint32_t end = timersGetMsTick() + RESET_WAIT_DELAY_MS; + while (timersGetMsTick() < end); + } + + lcdStart(); + lcdWriteCommand(0xAF); // dc2=1, IC into exit SLEEP MODE, dc3=1 gray=ON, dc4=1 Green Enhanc mode disabled + delay_ms(20); // Needed for internal DC-DC converter startup +} + +void lcdSetRefVolt(uint8_t val) +{ + if (!lcdInitFinished) { + lcdInitFinish(); + } + + lcdWriteCommand(0x81); // Set Vop + lcdWriteCommand(val+CONTRAST_OFS); // 0-255 +} diff --git a/radio/src/targets/modalai/lcd_driver_spi.cpp b/radio/src/targets/modalai/lcd_driver_spi.cpp new file mode 100644 index 00000000000..c388e4916f8 --- /dev/null +++ b/radio/src/targets/modalai/lcd_driver_spi.cpp @@ -0,0 +1,379 @@ +/* + * Copyright (C) EdgeTX + * + * Based on code named + * opentx - https://github.com/opentx/opentx + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + #include "hal/gpio.h" + #include "stm32_gpio.h" + #include "stm32_spi.h" + #include "stm32_dma.h" + + #include "board.h" + #include "debug.h" + #include "lcd.h" + + #include "hal/abnormal_reboot.h" + #include "timers_driver.h" + + #if !defined(BOOT) + #include "edgetx.h" + #endif + + #if defined(OLED_SCREEN) + #define LCD_CONTRAST_OFFSET 0 + #elif defined(RADIO_FAMILY_JUMPER_T12) || defined(MANUFACTURER_RADIOMASTER) || defined(RADIO_COMMANDO8) || defined(RADIO_TPRO) || defined(RADIO_T12MAX) || defined(RADIO_V12) || defined(RADIO_V14) + #define LCD_CONTRAST_OFFSET -10 + #else + #define LCD_CONTRAST_OFFSET 160 + #endif + #define RESET_WAIT_DELAY_MS 300 // Wait time after LCD reset before first command + #define WAIT_FOR_DMA_END() do { } while (lcd_busy) + + #define LCD_NCS_HIGH() gpio_set(LCD_NCS_GPIO) + #define LCD_NCS_LOW() gpio_clear(LCD_NCS_GPIO) + + #define LCD_A0_HIGH() gpio_set(LCD_A0_GPIO) + #define LCD_A0_LOW() gpio_clear(LCD_A0_GPIO) + + #define LCD_RST_HIGH() gpio_set(LCD_RST_GPIO) + #define LCD_RST_LOW() gpio_clear(LCD_RST_GPIO) + + bool lcdInitFinished = false; + void lcdInitFinish(); + + void lcdWriteCommand(uint8_t byte) + { + LCD_A0_LOW(); + LCD_NCS_LOW(); + while ((LCD_SPI->SR & SPI_SR_TXC) == 0) { + // Wait + } + //(void)LCD_SPI->RXDR; // Clear receive + *((volatile uint8_t *)&LCD_SPI->TXDR) = byte; // Must limit to 8-bit bus transaction + LCD_SPI->CR1 |= SPI_CR1_CSTART; + while ((LCD_SPI->SR & SPI_SR_TXC) == 0) { + // Wait + } + LCD_NCS_HIGH(); + } + + void lcdHardwareInit() + { + stm32_spi_enable_clock(LCD_SPI); + gpio_init_af(LCD_MOSI_GPIO, LCD_GPIO_AF, GPIO_PIN_SPEED_VERY_HIGH); + gpio_init_af(LCD_CLK_GPIO, LCD_GPIO_AF, GPIO_PIN_SPEED_VERY_HIGH); + gpio_init(LCD_NCS_GPIO, GPIO_OUT, GPIO_PIN_SPEED_MEDIUM); + gpio_init(LCD_RST_GPIO, GPIO_OUT, GPIO_PIN_SPEED_MEDIUM); + gpio_init(LCD_A0_GPIO, GPIO_OUT, GPIO_PIN_SPEED_HIGH); + + LCD_NCS_HIGH(); + + // APB1 clock / 2 = 133nS per clock + LCD_SPI->CR1 &= ~(SPI_CR1_SPE); + LCD_SPI->CR1 = 0; // Clear any mode error + LCD_SPI->CR1 = SPI_CR1_SSI | SPI_CR1_HDDIR; + LCD_SPI->CR2 = 0; + LCD_SPI->CFG1 = 0x00070007; + LCD_SPI->CFG1 |= LCD_SPI_PRESCALER; + LCD_SPI->CFG2 = SPI_CFG2_CPHA | SPI_CFG2_CPOL | SPI_CFG2_SSM | SPI_CFG2_MASTER | (0x3 << SPI_CFG2_COMM_Pos); + // LCD_SPI->CFG2 = SPI_CFG2_CPHA | SPI_CFG2_CPOL | SPI_CFG2_SSM | SPI_CFG2_MASTER; + LCD_SPI->CR1 |= SPI_CR1_SPE; + + stm32_dma_enable_clock(LCD_DMA); + LCD_DMA_Stream->CR &= ~DMA_SxCR_EN; // Disable DMA + LCD_DMA->HIFCR = LCD_DMA_FLAGS; // Write ones to clear bits + LCD_DMA_Stream->CR = DMA_SxCR_PL_0 | DMA_SxCR_MINC | DMA_SxCR_DIR_0; + LCD_DMA_Stream->PAR = (uint32_t)&LCD_SPI->TXDR; + LL_DMA_SetPeriphRequest(LCD_DMA, LCD_DMA_Stream_Num, LL_DMAMUX1_REQ_SPI4_TX); + #if LCD_W == 128 + LCD_DMA_Stream->NDTR = LCD_W; + #else + LCD_DMA_Stream->M0AR = (uint32_t)displayBuf; + LCD_DMA_Stream->NDTR = LCD_W*LCD_H/8*4; + #endif + LCD_DMA_Stream->FCR = DMA_SxFCR_DMDIS | DMA_SxFCR_FTH_0; + + NVIC_SetPriority(LCD_DMA_Stream_IRQn, 7); + NVIC_EnableIRQ(LCD_DMA_Stream_IRQn); + } + + void lcdStart() + { + #if defined(LCD_VERTICAL_INVERT) + // T12 and TX12 have the screen inverted. + #if defined(RADIO_V12) + lcdWriteCommand(0xe2); // (14) Soft reset + lcdWriteCommand(0xa0); // Set seg + lcdWriteCommand(0xc8); // Set com + lcdWriteCommand(0xf8); // Set booster + lcdWriteCommand(0x00); // 5x + lcdWriteCommand(0xa2); // Set bias=1/6 + lcdWriteCommand(0x26); // Set internal rb/ra=5.0 + lcdWriteCommand(0x2f); // All built-in power circuits on + lcdWriteCommand(0x81); // Set contrast + lcdWriteCommand(0x1F); // Set Vop + lcdWriteCommand(0xa6); // Set display mode + #else + lcdWriteCommand(0xe2); // (14) Soft reset + #if defined(LCD_HORIZONTAL_INVERT) + lcdWriteCommand(0xa1); // Set seg + #else + lcdWriteCommand(0xa0); // Set seg + #endif + lcdWriteCommand(0xc8); // Set com + lcdWriteCommand(0xf8); // Set booster + lcdWriteCommand(0x00); // 5x + lcdWriteCommand(0xa3); // Set bias=1/6 + lcdWriteCommand(0x22); // Set internal rb/ra=5.0 + lcdWriteCommand(0x2f); // All built-in power circuits on + lcdWriteCommand(0x24); // Power control set + lcdWriteCommand(0x81); // Set contrast + lcdWriteCommand(0x0A); // Set Vop + lcdWriteCommand(0xa6); // Set display mode + #endif + #else + #if defined(RADIO_V14) + lcdWriteCommand(0xe2); // (14) Soft reset + lcdWriteCommand(0xa1); // Set seg + lcdWriteCommand(0xc0); // Set com + lcdWriteCommand(0xf8); // Set booster + lcdWriteCommand(0x00); // 5x + lcdWriteCommand(0xa2); // Set bias=1/6 + lcdWriteCommand(0x26); // Set internal rb/ra=5.0 + lcdWriteCommand(0x2f); // All built-in power circuits on + lcdWriteCommand(0x81); // Set contrast + lcdWriteCommand(0x1F); // Set Vop + lcdWriteCommand(0xa6); // Set display mode + #else + lcdWriteCommand(0xe2); // (14) Soft reset + lcdWriteCommand(0xa1); // Set seg + lcdWriteCommand(0xc0); // Set com + lcdWriteCommand(0xf8); // Set booster + lcdWriteCommand(0x00); // 5x + lcdWriteCommand(0xa3); // Set bias=1/6 + lcdWriteCommand(0x22); // Set internal rb/ra=5.0 + lcdWriteCommand(0x2f); // All built-in power circuits on + lcdWriteCommand(0x81); // Set contrast + lcdWriteCommand(0x36); // Set Vop + lcdWriteCommand(0xa6); // Set display mode + #endif + #endif + #if defined(BOOT) + lcdSetRefVolt(LCD_CONTRAST_DEFAULT); + #else + lcdSetRefVolt(g_eeGeneral.contrast); + #endif + } + + volatile bool lcd_busy; + + void lcdRefreshWait() + { + WAIT_FOR_DMA_END(); + } + + void lcdRefresh(bool wait) + { + if (!lcdInitFinished) { + lcdInitFinish(); + } + + SCB_CleanDCache(); + + #if LCD_W == 128 + uint8_t * p = displayBuf; + #if defined(LCD_W_OFFSET) + lcdWriteCommand(LCD_W_OFFSET); + #endif + for (uint8_t y=0; y < 8; y++, p+=LCD_W) { + #if defined(SSD1309_LCD) + lcdPageSet(y); + lcdColumnSet(0); + #else + lcdWriteCommand(0x10); // Column addr 0 + lcdWriteCommand(0xB0 | y); // Page addr y + #if !defined(LCD_VERTICAL_INVERT) + lcdWriteCommand(0x04); + #endif + #endif + + LCD_NCS_LOW(); + LCD_A0_HIGH(); + + lcd_busy = true; + LCD_DMA_Stream->CR &= ~DMA_SxCR_EN; // Disable DMA + LCD_DMA->HIFCR = LCD_DMA_FLAGS; // Write ones to clear bits + LCD_DMA_Stream->M0AR = (uint32_t)p; + LCD_DMA_Stream->CR |= DMA_SxCR_EN | DMA_SxCR_TCIE; // Enable DMA & TC interrupts + LCD_SPI->CFG1 |= SPI_CFG1_TXDMAEN; + + WAIT_FOR_DMA_END(); + + LCD_NCS_HIGH(); + LCD_A0_HIGH(); + } + #else + // Wait if previous DMA transfer still active + WAIT_FOR_DMA_END(); + lcd_busy = true; + + lcdWriteAddress(0, 0); + + LCD_NCS_LOW(); + LCD_A0_HIGH(); + + LCD_DMA_Stream->CR &= ~DMA_SxCR_EN; // Disable DMA + LCD_DMA->HIFCR = LCD_DMA_FLAGS; // Write ones to clear bits + + LCD_DMA_Stream->CR |= DMA_SxCR_EN | DMA_SxCR_TCIE; // Enable DMA & TC interrupts + LCD_SPI->CR2 |= SPI_CR2_TXDMAEN; + #endif + } + + extern "C" void LCD_DMA_Stream_IRQHandler() + { + DEBUG_INTERRUPT(INT_LCD); + + LCD_DMA_Stream->CR &= ~DMA_SxCR_TCIE; // Stop interrupt + LCD_DMA->HIFCR |= LCD_DMA_FLAG_INT; // Clear interrupt flag + LCD_SPI->CFG1 &= ~SPI_CFG1_TXDMAEN; + LCD_DMA_Stream->CR &= ~DMA_SxCR_EN; // Disable DMA + + while ((LCD_SPI->SR & SPI_SR_TXC) == 0) { + /* Wait for SPI to finish sending data + The DMA TX End interrupt comes two bytes before the end of SPI transmission, + therefore we have to wait here. + */ + } + LCD_NCS_HIGH(); + lcd_busy = false; + } + + /* + Proper method for turning of LCD module. It must be used, + otherwise we might damage LCD crystals in the long run! + */ + void lcdOff() + { + WAIT_FOR_DMA_END(); + + /* + LCD Sleep mode is also good for draining capacitors and enables us + to re-init LCD without any delay + */ + lcdWriteCommand(0xAE); // LCD sleep + delay_ms(3); // Wait for caps to drain + } + + void lcdReset() + { + LCD_NCS_HIGH(); + LCD_RST_LOW(); +#if LCD_W == 128 + delay_ms(150); +#else + delay_ms(1); // Only 3 us needed according to data-sheet, we use 1 ms +#endif + LCD_RST_HIGH(); + } + + /* + Starts LCD initialization routine. It should be called as + soon as possible after the reset because LCD takes a lot of + time to properly power-on. + + Make sure that delay_ms() is functional before calling this function! + */ + void lcdInit() + { + lcdHardwareInit(); + + if (IS_LCD_RESET_NEEDED()) { + lcdReset(); + } + } + + /* + Finishes LCD initialization. It is called auto-magically when first LCD command is + issued by the other parts of the code. + */ + + #if defined(RADIO_X9DP2019) || defined(RADIO_X7ACCESS) + #define LCD_DELAY_NEEDED() true + #else + #define LCD_DELAY_NEEDED() (!WAS_RESET_BY_WATCHDOG_OR_SOFTWARE()) + #endif + + void lcdInitFinish() + { + lcdInitFinished = true; + + /* + LCD needs longer time to initialize in low temperatures. The data-sheet + mentions a time of at least 150 ms. The delay of 1300 ms was obtained + experimentally. It was tested down to -10 deg Celsius. + + The longer initialization time seems to only be needed for regular Taranis, + the Taranis Plus (9XE) has been tested to work without any problems at -18 deg Celsius. + Therefore the delay for T+ is lower. + + If radio is reset by watchdog or boot-loader the wait is skipped, but the LCD + is initialized in any case. + + This initialization is needed in case the user moved power switch to OFF and + then immediately to ON position, because lcdOff() was called. In any case the LCD + initialization (without reset) is also recommended by the data sheet. + */ + + if (LCD_DELAY_NEEDED()) { + uint32_t end = timersGetMsTick() + RESET_WAIT_DELAY_MS; + while (timersGetMsTick() < end); + } + + lcdStart(); + lcdWriteCommand(0xAF); // dc2=1, IC into exit SLEEP MODE, dc3=1 gray=ON, dc4=1 Green Enhanc mode disabled + delay_ms(20); // needed for internal DC-DC converter startup + } + + void lcdSetRefVolt(uint8_t val) + { + if (!lcdInitFinished) { + lcdInitFinish(); + } + + #if LCD_W != 128 + WAIT_FOR_DMA_END(); + #endif + + #if defined(RADIO_V12) || defined(RADIO_V14) + lcdWriteCommand(0x81); // Set Vop + lcdWriteCommand(val+LCD_CONTRAST_OFFSET+20);// 0-255 + #else + lcdWriteCommand(0x81); // Set Vop + lcdWriteCommand(val+LCD_CONTRAST_OFFSET); // 0-255 + #endif + } + + #if LCD_W == 128 + void lcdSetInvert(bool invert) + { + lcdWriteCommand(invert ? 0xA7 : 0xA6); + } + #endif + \ No newline at end of file diff --git a/radio/src/targets/modalai/led_driver.cpp b/radio/src/targets/modalai/led_driver.cpp new file mode 100644 index 00000000000..3a5ad9e275c --- /dev/null +++ b/radio/src/targets/modalai/led_driver.cpp @@ -0,0 +1,106 @@ +/* + * Copyright (C) EdgeTX + * + * Based on code named + * opentx - https://github.com/opentx/opentx + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "hal/gpio.h" +#include "stm32_gpio.h" + +#include "board.h" + +#if defined(FUNCTION_SWITCHES) +static const uint32_t fsLeds[] = {FSLED_GPIO_PIN_1, FSLED_GPIO_PIN_2, + FSLED_GPIO_PIN_3, FSLED_GPIO_PIN_4, + FSLED_GPIO_PIN_5, FSLED_GPIO_PIN_6}; +#endif + +void ledInit() +{ +#if defined(LED_GREEN_GPIO) + gpio_init(LED_GREEN_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); +#endif + +#if defined(LED_RED_GPIO) + gpio_init(LED_RED_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); +#endif + +#if defined(LED_BLUE_GPIO) + gpio_init(LED_BLUE_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); +#endif + +#if defined(FUNCTION_SWITCHES) + for (size_t i = 0; i < DIM(fsLeds); i++) { + gpio_init(fsLeds[i], GPIO_OUT, GPIO_PIN_SPEED_LOW); + } +#endif +} + +#if defined(FUNCTION_SWITCHES) +void fsLedOff(uint8_t index) +{ + gpio_clear(fsLeds[index]); +} + +void fsLedOn(uint8_t index) +{ + gpio_set(fsLeds[index]); +} + +bool getFSLedState(uint8_t index) +{ + return gpio_read(fsLeds[index]) ? true : false; +} +#endif + +void ledOff() +{ +#if defined(LED_RED_GPIO) + GPIO_LED_GPIO_OFF(LED_RED_GPIO); +#endif +#if defined(LED_BLUE_GPIO) + GPIO_LED_GPIO_OFF(LED_BLUE_GPIO); +#endif +#if defined(LED_GREEN_GPIO) + GPIO_LED_GPIO_OFF(LED_GREEN_GPIO); +#endif +} + +void ledRed() +{ + ledOff(); +#if defined(LED_RED_GPIO) + GPIO_LED_GPIO_ON(LED_RED_GPIO); +#endif +} + +void ledGreen() +{ + ledOff(); +#if defined(LED_GREEN_GPIO) + GPIO_LED_GPIO_ON(LED_GREEN_GPIO); +#endif +} + +void ledBlue() +{ + ledOff(); +#if defined(LED_BLUE_GPIO) + GPIO_LED_GPIO_ON(LED_BLUE_GPIO); +#endif +} diff --git a/radio/src/targets/modalai/usb_charger_driver.cpp b/radio/src/targets/modalai/usb_charger_driver.cpp new file mode 100644 index 00000000000..fd919d83b20 --- /dev/null +++ b/radio/src/targets/modalai/usb_charger_driver.cpp @@ -0,0 +1,36 @@ +/* + * Copyright (C) EdgeTX + * + * Based on code named + * opentx - https://github.com/opentx/opentx + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "hal/gpio.h" +#include "stm32_gpio.h" + +#include "board.h" +#include "hal/usb_driver.h" + +void usbChargerInit() +{ + gpio_init(USB_CHARGER_GPIO, GPIO_IN_PU, GPIO_PIN_SPEED_LOW); +} + +bool usbChargerLed() +{ + return (!gpio_read(USB_CHARGER_GPIO) && usbPlugged()); +} diff --git a/radio/src/targets/modalai/usb_descriptor.h b/radio/src/targets/modalai/usb_descriptor.h new file mode 100644 index 00000000000..8be765b2279 --- /dev/null +++ b/radio/src/targets/modalai/usb_descriptor.h @@ -0,0 +1,100 @@ +/* + * Copyright (C) EdgeTX + * + * Based on code named + * opentx - https://github.com/opentx/opentx + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#pragma once + +#if defined(RADIO_TX12) || defined(RADIO_TX12MK2) + #define USB_NAME "Radiomaster TX12" + #define USB_MANUFACTURER 'R', 'M', '_', 'T', 'X', ' ', ' ', ' ' /* 8 bytes */ + #define USB_PRODUCT 'R', 'M', ' ', 'T', 'X', '1', '2', ' ' /* 8 Bytes */ +#elif defined(RADIO_BOXER) + #define USB_NAME "Radiomaster Boxer" + #define USB_MANUFACTURER 'R', 'M', '_', 'T', 'X', ' ', ' ', ' ' /* 8 bytes */ + #define USB_PRODUCT 'R', 'M', ' ', 'B', 'o', 'x', 'e', 'r' /* 8 Bytes */ +#elif defined(RADIO_ZORRO) + #define USB_NAME "Radiomaster Zorro" + #define USB_MANUFACTURER 'R', 'M', '_', 'T', 'X', ' ', ' ', ' ' /* 8 bytes */ + #define USB_PRODUCT 'R', 'M', ' ', 'Z', 'o', 'r', 'r', 'o' /* 8 Bytes */ +#elif defined(RADIO_MT12) + #define USB_NAME "Radiomaster MT12" + #define USB_MANUFACTURER 'R', 'M', '_', 'T', 'X', ' ', ' ', ' ' /* 8 bytes */ + #define USB_PRODUCT 'R', 'M', ' ', 'M', 'T', '1', '2', ' ' /* 8 Bytes */ +#elif defined(RADIO_POCKET) + #define USB_NAME "Radiomaster Pocket" + #define USB_MANUFACTURER 'R', 'M', '_', 'T', 'X', ' ', ' ', ' ' /* 8 bytes */ + #define USB_PRODUCT 'R', 'M', 'P', 'o', 'c', 'k', 'e', 't' /* 8 Bytes */ +#elif defined(RADIO_T8) + #define USB_NAME "Radiomaster T8" + #define USB_MANUFACTURER 'R', 'M', '_', 'T', 'X', ' ', ' ', ' ' /* 8 bytes */ + #define USB_PRODUCT 'R', 'M', ' ', 'T', '8', ' ', ' ', ' ' /* 8 Bytes */ +#elif defined(RADIO_LR3PRO) + #define USB_NAME "BETAFPV LR3PRO" + #define USB_MANUFACTURER 'B', 'E', 'T', 'A', 'F', 'P', 'V', ' ' /* 8 bytes */ + #define USB_PRODUCT 'L', 'R', '3', 'P', 'R', 'O', ' ', ' ' /* 8 Bytes */ +#elif defined(RADIO_TLITE) + #define USB_NAME "Jumper TLite" + #define USB_MANUFACTURER 'J', 'U', 'M', 'P', 'E', 'R', ' ', ' ' /* 8 bytes */ + #define USB_PRODUCT 'T', '-', 'L', 'i', 't', 'e', ' ', ' ' /* 8 Bytes */ +#elif defined(RADIO_TPRO) + #define USB_NAME "Jumper TPro" + #define USB_MANUFACTURER 'J', 'U', 'M', 'P', 'E', 'R', ' ', ' ' /* 8 bytes */ + #define USB_PRODUCT 'T', '-', 'P', 'r', 'o', ' ', ' ', ' ' /* 8 Bytes */ +#elif defined(RADIO_TPROV2) + #define USB_NAME "Jumper TPro V2" + #define USB_MANUFACTURER 'J', 'U', 'M', 'P', 'E', 'R', ' ', ' ' /* 8 bytes */ + #define USB_PRODUCT 'T', '-', 'P', 'r', 'o', ' ', 'V', '2' /* 8 Bytes */ +#elif defined(RADIO_T12MAX) +#define USB_NAME "Jumper T12 MAX" + #define USB_MANUFACTURER 'J', 'U', 'M', 'P', 'E', 'R', ' ', ' ' /* 8 bytes */ + #define USB_PRODUCT 'T', '1', '2', ' ', 'M', 'A', 'X', ' ' /* 8 Bytes */ +#elif defined(RADIO_TPROS) + #define USB_NAME "Jumper T-Pro S" + #define USB_MANUFACTURER 'J', 'U', 'M', 'P', 'E', 'R', ' ', ' ' /* 8 bytes */ + #define USB_PRODUCT 'T', '-', 'P', 'r', 'o', ' ', 'S', ' ' /* 8 Bytes */ +#elif defined(RADIO_T14) + #define USB_NAME "Jumper T14" + #define USB_MANUFACTURER 'J', 'U', 'M', 'P', 'E', 'R', ' ', ' ' /* 8 bytes */ + #define USB_PRODUCT 'T', '1', '4', ' ', ' ', ' ', ' ', ' ' /* 8 Bytes */ +#elif defined(RADIO_T20) + #define USB_NAME "Jumper T20" + #define USB_MANUFACTURER 'J', 'U', 'M', 'P', 'E', 'R', ' ', ' ' /* 8 bytes */ + #define USB_PRODUCT 'T', '2', '0', ' ', ' ', ' ', ' ', ' ' /* 8 Bytes */ +#elif defined(RADIO_T20V2) + #define USB_NAME "Jumper T20 V2" + #define USB_MANUFACTURER 'J', 'U', 'M', 'P', 'E', 'R', ' ', ' ' /* 8 bytes */ + #define USB_PRODUCT 'T', '2', '0', 'V', '2', ' ', ' ', ' ' /* 8 Bytes */ +#elif defined(RADIO_COMMANDO8) + #define USB_NAME "iFlight Commando 8" + #define USB_MANUFACTURER 'i', 'F', 'l', 'i', 'g', 'h', 't', '-' /* 8 bytes */ + #define USB_PRODUCT 'C', 'o', 'm', 'm', 'a', 'n', 'd', 'o' /* 8 Bytes */ +#elif defined(RADIO_V12) + #define USB_NAME "HelloRadioSky V12" + #define USB_MANUFACTURER 'H', 'R', 'S', 'k', 'y', ' ', ' ', ' ' /* 8 bytes */ + #define USB_PRODUCT 'V', '1', '2', ' ', ' ', ' ', ' ', ' ' /* 8 Bytes */ +#elif defined(RADIO_V14) + #define USB_NAME "HelloRadioSky V14" + #define USB_MANUFACTURER 'H', 'R', 'S', 'k', 'y', ' ', ' ', ' ' /* 8 bytes */ + #define USB_PRODUCT 'V', '1', '4', ' ', ' ', ' ', ' ', ' ' /* 8 Bytes */ +#else + #define USB_NAME "FrSky Taranis" + #define USB_MANUFACTURER 'F', 'r', 'S', 'k', 'y', ' ', ' ', ' ' /* 8 bytes */ + #define USB_PRODUCT 'T', 'a', 'r', 'a', 'n', 'i', 's', ' ' /* 8 Bytes */ +#endif diff --git a/radio/src/targets/modalai/voxlpm_i2c_driver.cpp b/radio/src/targets/modalai/voxlpm_i2c_driver.cpp new file mode 100644 index 00000000000..f248114aa4d --- /dev/null +++ b/radio/src/targets/modalai/voxlpm_i2c_driver.cpp @@ -0,0 +1,192 @@ +#pragma once + +#include "voxlpm_i2c_driver.h" + +#include "stm32_hal_ll.h" +#include "stm32_gpio.h" +#include "stm32_ws2812.h" + +#include "board.h" +#include "boards/generic_stm32/module_ports.h" +#include "boards/generic_stm32/analog_inputs.h" +#include "boards/generic_stm32/rgb_leds.h" + + +#if defined(POWER_I2C) + +// static int count = 0; +static uint8_t current_reg = 0; + +static volatile uint32_t status = 0; +static volatile uint32_t cr1_stat = 0; +static volatile uint32_t cr2_stat = 0; + +void i2c_set_read_reg(uint8_t reg) +{ + uint8_t n_bytes = 1; + volatile uint8_t tx_buf[1] = {0}; + + tx_buf[0] = reg; + + POWER_I2C->CR1 |= I2C_CR1_PE; // Turn on the peripheral + + POWER_I2C->CR2 &= ~I2C_CR2_START; // Clear START + + while(POWER_I2C->CR2 & I2C_CR2_START) {}; + + POWER_I2C->ISR |= I2C_ISR_TXE; + POWER_I2C->ICR |= I2C_ICR_NACKCF; + POWER_I2C->ICR |= I2C_ICR_STOPCF; + + POWER_I2C->CR2 &= ~I2C_CR2_RD_WRN; // Set Write mode + + POWER_I2C->CR2 &= ~(I2C_CR2_NBYTES_Msk);; + POWER_I2C->CR2 |= (n_bytes << I2C_CR2_NBYTES_Pos);; // Set number of bytes to transfer + + POWER_I2C->CR2 |= I2C_CR2_START; // START + + for(volatile int i = 0; i < n_bytes; i++) // transmit each byte when register available + { + while(!(POWER_I2C->ISR & I2C_ISR_TXE)) { status = POWER_I2C->ISR; cr1_stat = POWER_I2C->CR1; cr2_stat = POWER_I2C->CR2; } + if(i < n_bytes) POWER_I2C->TXDR = tx_buf[i]; + } + + while(!(POWER_I2C->ISR & I2C_ISR_STOPF)) { status = POWER_I2C->ISR; cr1_stat = POWER_I2C->CR1; cr2_stat = POWER_I2C->CR2; } // Wait until transaction finished + + POWER_I2C->CR1 &= ~I2C_CR1_PE; // Turn off the peripheral + + current_reg = reg; +} + + + +void i2c_transmit(uint8_t reg, uint16_t val) +{ + uint8_t n_bytes = 3; + volatile uint8_t rx_buf[3] = {0}; + volatile uint8_t tx_buf[3] = {0}; + + tx_buf[0] = reg; + tx_buf[1] = (val >> 8) & 0xFF; // MSB first + tx_buf[2] = (val) & 0xFF; + + POWER_I2C->CR1 |= I2C_CR1_PE; // Turn on the peripheral + + POWER_I2C->CR2 &= ~I2C_CR2_START; // Clear START + + while(POWER_I2C->CR2 & I2C_CR2_START) {}; + + POWER_I2C->ISR |= I2C_ISR_TXE; + POWER_I2C->ICR |= I2C_ICR_NACKCF; + POWER_I2C->ICR |= I2C_ICR_STOPCF; + + POWER_I2C->CR2 &= ~I2C_CR2_RD_WRN; // Set Read mode + + POWER_I2C->CR2 &= ~(I2C_CR2_NBYTES_Msk); + POWER_I2C->CR2 |= (n_bytes << I2C_CR2_NBYTES_Pos); // Set number of bytes to transfer + + POWER_I2C->CR2 |= I2C_CR2_START; // START + + for(volatile int i = 0; i < n_bytes; i++) // transmit each byte when register available + { + while(!(POWER_I2C->ISR & I2C_ISR_TXE)) { status = POWER_I2C->ISR; cr1_stat = POWER_I2C->CR1; cr2_stat = POWER_I2C->CR2; } + if(i < n_bytes) POWER_I2C->TXDR = tx_buf[i]; + } + + while(!(POWER_I2C->ISR & I2C_ISR_STOPF)) { status = POWER_I2C->ISR; cr1_stat = POWER_I2C->CR1; cr2_stat = POWER_I2C->CR2; } // Wait until transaction finished + + POWER_I2C->CR1 &= ~I2C_CR1_PE; // Turn off the peripheral + + current_reg = reg; + return; +} + +uint16_t i2c_receive(uint8_t reg) +{ + // if(current_reg != reg); + // { + i2c_set_read_reg(reg); + // } + uint8_t n_bytes = 2; + volatile uint8_t rx_buf[3] = {0}; + + POWER_I2C->CR1 |= I2C_CR1_PE; // Turn on the peripheral + + POWER_I2C->CR2 &= ~I2C_CR2_START; // Clear START + + while(POWER_I2C->CR2 & I2C_CR2_START) {}; + + POWER_I2C->ISR |= I2C_ISR_TXE; + POWER_I2C->ICR |= I2C_ICR_NACKCF; + POWER_I2C->ICR |= I2C_ICR_STOPCF; + + POWER_I2C->CR2 |= I2C_CR2_RD_WRN; // Set Read mode + + POWER_I2C->CR2 &= ~(I2C_CR2_NBYTES_Msk); + POWER_I2C->CR2 |= (n_bytes << I2C_CR2_NBYTES_Pos); // Set number of bytes to transfer + + POWER_I2C->CR2 |= I2C_CR2_START; // START + + for(volatile int i = 0; i < n_bytes; i++) + { + while(!(POWER_I2C->ISR & I2C_ISR_RXNE)) { status = POWER_I2C->ISR; cr1_stat = POWER_I2C->CR1; cr2_stat = POWER_I2C->CR2; } // Wait for data + rx_buf[i] = POWER_I2C->RXDR; + } + + while(!(POWER_I2C->ISR & I2C_ISR_STOPF)) { status = POWER_I2C->ISR; cr1_stat = POWER_I2C->CR1; cr2_stat = POWER_I2C->CR2; } // Wait until transaction finished + + POWER_I2C->CR1 &= ~I2C_CR1_PE; // Turn off the peripheral + + uint16_t data_out = rx_buf[1]; // LSB + data_out |= rx_buf[0] << 8; + return data_out; +} + +void voxl_pm_init() +{ + gpio_init(POWER_I2C_PIN_SDA, GPIO_OD, GPIO_PIN_SPEED_HIGH); + gpio_init(POWER_I2C_PIN_SCL, GPIO_OD, GPIO_PIN_SPEED_HIGH); + + gpio_init_af(POWER_I2C_PIN_SDA, POWER_I2C_SDA_AF, GPIO_PIN_SPEED_HIGH); + gpio_init_af(POWER_I2C_PIN_SCL, POWER_I2C_SCL_AF, GPIO_PIN_SPEED_HIGH); + + // RCC->APB1LENR |= 0x800000; // Turn on I2C3 Peripheral Clock + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C3); + + POWER_I2C->TIMINGR = POWER_I2C_TIMING_REGISTER; // Set timing values + // POWER_I2C->CR1 |= I2C_CR1_ANFOFF; // Turn off analog filter + uint32_t dnf = 0x3U; + POWER_I2C->CR1 |= dnf << I2C_CR1_DNF_Pos; + + + POWER_I2C->CR2 |= I2C_CR2_RD_WRN; // Set Read mode + + POWER_I2C->CR2 |= I2C_CR2_AUTOEND; // Automatically send stop condition + + // Empty receive register + while(POWER_I2C->ISR & I2C_ISR_RXNE) + { + uint8_t data = POWER_I2C->RXDR; // Read one data byte out + } + + POWER_I2C->CR2 &= ~(I2C_CR2_SADD_Msk); // Clear slave address + POWER_I2C->CR2 |= (uint32_t) POWER_I2C_SLAVE_ADDRESS; // Set slave address + + POWER_I2C->CR2 &= ~I2C_CR2_START; // Clear START + + while(POWER_I2C->CR2 & I2C_CR2_START) {}; // Wait for start to be 0 + + i2c_transmit(INA231_REG_CONFIG, (INA231_CONFIG | 0x4000)); + + // while(i2c_receive(INA231_REG_CONFIG) != (INA231_CONFIG | 0x4000)) { count++; }; + return; +} + +uint16_t voxl_pm_get_voltage() +{ + uint16_t voltage = i2c_receive(INA231_REG_BUSVOLTAGE) * (INA231_VBUSSCALE * 100); + return voltage; +} + + +#endif \ No newline at end of file diff --git a/radio/src/targets/modalai/voxlpm_i2c_driver.h b/radio/src/targets/modalai/voxlpm_i2c_driver.h new file mode 100644 index 00000000000..c7131ead001 --- /dev/null +++ b/radio/src/targets/modalai/voxlpm_i2c_driver.h @@ -0,0 +1,12 @@ +#pragma once + +#include +#include "hal.h" + +#if defined(POWER_I2C) + +void voxl_pm_init(); + +uint16_t voxl_pm_get_voltage(); + +#endif \ No newline at end of file diff --git a/radio/src/thirdparty/CMSIS/Device/ST/STM32H7xx/Include/stm32h753xx.h b/radio/src/thirdparty/CMSIS/Device/ST/STM32H7xx/Include/stm32h753xx.h new file mode 100644 index 00000000000..40a4bb2e382 --- /dev/null +++ b/radio/src/thirdparty/CMSIS/Device/ST/STM32H7xx/Include/stm32h753xx.h @@ -0,0 +1,26867 @@ +/** + ****************************************************************************** + * @file stm32h753xx.h + * @author MCD Application Team + * @brief CMSIS STM32H753xx Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32h753xx + * @{ + */ + +#ifndef STM32H753xx_H +#define STM32H753xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32H7XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ +/****** Cortex-M Processor Exceptions Numbers *****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) */ + PVD_AVD_IRQn = 1, /*!< PVD/AVD through EXTI Line detection Interrupt */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC_IRQn = 18, /*!< ADC1 and ADC2 global Interrupts */ + FDCAN1_IT0_IRQn = 19, /*!< FDCAN1 Interrupt line 0 */ + FDCAN2_IT0_IRQn = 20, /*!< FDCAN2 Interrupt line 0 */ + FDCAN1_IT1_IRQn = 21, /*!< FDCAN1 Interrupt line 1 */ + FDCAN2_IT1_IRQn = 22, /*!< FDCAN2 Interrupt line 1 */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + ETH_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + FDCAN_CAL_IRQn = 63, /*!< FDCAN Calibration unit Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ + OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ + OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ + OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ + DCMI_IRQn = 78, /*!< DCMI global interrupt */ + CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */ + HASH_RNG_IRQn = 80, /*!< HASH and RNG global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + UART7_IRQn = 82, /*!< UART7 global interrupt */ + UART8_IRQn = 83, /*!< UART8 global interrupt */ + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ + SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ + SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ + LTDC_IRQn = 88, /*!< LTDC global Interrupt */ + LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */ + DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */ + SAI2_IRQn = 91, /*!< SAI2 global Interrupt */ + QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */ + LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */ + CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */ + I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */ + I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */ + SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */ + OTG_FS_EP1_OUT_IRQn = 98, /*!< USB OTG HS2 global interrupt */ + OTG_FS_EP1_IN_IRQn = 99, /*!< USB OTG HS2 End Point 1 Out global interrupt */ + OTG_FS_WKUP_IRQn = 100, /*!< USB OTG HS2 End Point 1 In global interrupt */ + OTG_FS_IRQn = 101, /*!< USB OTG HS2 Wakeup through EXTI interrupt */ + DMAMUX1_OVR_IRQn = 102, /*! + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ + __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */ + __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */ + __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x028 */ + uint32_t RESERVED2; /*!< Reserved, 0x02C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x044 */ + uint32_t RESERVED4; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */ + __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */ + __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */ + __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ + __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ +} ADC_TypeDef; + + +typedef struct +{ +__IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ +uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ +__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ +__IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ +__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + +} ADC_Common_TypeDef; + + +/** + * @brief VREFBUF + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + __IO uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + __IO uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + __IO uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + __IO uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t GFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t SIDFC; /*!< FDCAN Standard ID Filter Configuration register, Address offset: 0x084 */ + __IO uint32_t XIDFC; /*!< FDCAN Extended ID Filter Configuration register, Address offset: 0x088 */ + __IO uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x090 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x094 */ + __IO uint32_t NDAT1; /*!< FDCAN New Data 1 register, Address offset: 0x098 */ + __IO uint32_t NDAT2; /*!< FDCAN New Data 2 register, Address offset: 0x09C */ + __IO uint32_t RXF0C; /*!< FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0 */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8 */ + __IO uint32_t RXBC; /*!< FDCAN Rx Buffer Configuration register, Address offset: 0x0AC */ + __IO uint32_t RXF1C; /*!< FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8 */ + __IO uint32_t RXESC; /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXESC; /*!< FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, 0x0E8 - 0x0EC */ + __IO uint32_t TXEFC; /*!< FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0F4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8 */ + __IO uint32_t RESERVED7; /*!< Reserved, 0x0FC */ +} FDCAN_GlobalTypeDef; + +/** + * @brief TTFD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address offset: 0x100 */ + __IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address offset: 0x104 */ + __IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address offset: 0x108 */ + __IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address offset: 0x10C */ + __IO uint32_t TURCF; /*!< TUR Configuration register, Address offset: 0x110 */ + __IO uint32_t TTOCN; /*!< TT Operation Control register, Address offset: 0x114 */ + __IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address offset: 0x118 */ + __IO uint32_t TTTMK; /*!< TT Time Mark register, Address offset: 0x11C */ + __IO uint32_t TTIR; /*!< TT Interrupt register, Address offset: 0x120 */ + __IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address offset: 0x124 */ + __IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address offset: 0x128 */ + __IO uint32_t TTOST; /*!< TT Operation Status register, Address offset: 0x12C */ + __IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address offset: 0x130 */ + __IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address offset: 0x134 */ + __IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address offset: 0x138 */ + __IO uint32_t TTCPT; /*!< TT Capture Time register, Address offset: 0x13C */ + __IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address offset: 0x140 */ + __IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x2FC */ + __IO uint32_t TTTS; /*!< TT Trigger Select register, Address offset: 0x300 */ +} TTCAN_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */ + __IO uint32_t CCFG; /*!< Calibration Configuration register, Address offset: 0x04 */ + __IO uint32_t CSTAT; /*!< Calibration Status register, Address offset: 0x08 */ + __IO uint32_t CWD; /*!< Calibration Watchdog register, Address offset: 0x0C */ + __IO uint32_t IR; /*!< CCU Interrupt register, Address offset: 0x10 */ + __IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */ +} FDCAN_ClockCalibrationUnit_TypeDef; + + +/** + * @brief Consumer Electronics Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ +}CEC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ +} DAC_TypeDef; + +/** + * @brief DFSDM module registers + */ +typedef struct +{ + __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ + __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ + __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ + __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ + __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ + __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ + __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ + __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ + __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ + __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ + __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ + __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ + __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ + __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ + __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ +} DFSDM_Filter_TypeDef; + +/** + * @brief DFSDM channel configuration registers + */ +typedef struct +{ + __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ + __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ + __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and + short circuit detector register, Address offset: 0x08 */ + __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ + __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ +} DFSDM_Channel_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + uint32_t RESERVED4[11]; /*!< Reserved, Address offset: 0x08 */ + __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register, Address offset: 0x34 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x38 */ + __IO uint32_t APB1LFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x3C */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x40 */ + __IO uint32_t APB1HFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x44 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x48 */ + __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register, Address offset: 0x4C */ + uint32_t RESERVED8; /*!< Reserved, Address offset: 0x50 */ + __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register, Address offset: 0x54 */ +}DBGMCU_TypeDef; +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CM0AR; /*!< DMA channel x memory 0 address register */ + __IO uint32_t CM1AR; /*!< DMA channel x memory 1 address register */ +} BDMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} BDMA_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMA Request Generator Status Register */ + __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register */ +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief MDMA Controller + */ +typedef struct +{ + __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x00 */ +}MDMA_TypeDef; + +typedef struct +{ + __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */ + __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */ + __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */ + __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */ + __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */ + __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */ + __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */ + __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */ + __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */ + __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */ + __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */ + uint32_t RESERVED0; /*!< Reserved, 0x6C */ + __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */ + __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */ +}MDMA_Channel_TypeDef; + +/** + * @brief DMA2D Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ + __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ + __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ + __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ + __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ + __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ + __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ + __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ + __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ + __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ + __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ + __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ + __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ + __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ + __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ + __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ + __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ + __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ + __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ + __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ + uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */ + __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */ + __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */ +} DMA2D_TypeDef; + + +/** + * @brief Ethernet MAC + */ +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACECR; + __IO uint32_t MACPFR; + __IO uint32_t MACWTR; + __IO uint32_t MACHT0R; + __IO uint32_t MACHT1R; + uint32_t RESERVED1[14]; + __IO uint32_t MACVTR; + uint32_t RESERVED2; + __IO uint32_t MACVHTR; + uint32_t RESERVED3; + __IO uint32_t MACVIR; + __IO uint32_t MACIVIR; + uint32_t RESERVED4[2]; + __IO uint32_t MACTFCR; + uint32_t RESERVED5[7]; + __IO uint32_t MACRFCR; + uint32_t RESERVED6[7]; + __IO uint32_t MACISR; + __IO uint32_t MACIER; + __IO uint32_t MACRXTXSR; + uint32_t RESERVED7; + __IO uint32_t MACPCSR; + __IO uint32_t MACRWKPFR; + uint32_t RESERVED8[2]; + __IO uint32_t MACLCSR; + __IO uint32_t MACLTCR; + __IO uint32_t MACLETR; + __IO uint32_t MAC1USTCR; + uint32_t RESERVED9[12]; + __IO uint32_t MACVR; + __IO uint32_t MACDR; + uint32_t RESERVED10; + __IO uint32_t MACHWF0R; + __IO uint32_t MACHWF1R; + __IO uint32_t MACHWF2R; + uint32_t RESERVED11[54]; + __IO uint32_t MACMDIOAR; + __IO uint32_t MACMDIODR; + uint32_t RESERVED12[2]; + __IO uint32_t MACARPAR; + uint32_t RESERVED13[59]; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; + uint32_t RESERVED14[248]; + __IO uint32_t MMCCR; + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; + uint32_t RESERVED15[14]; + __IO uint32_t MMCTSCGPR; + __IO uint32_t MMCTMCGPR; + uint32_t RESERVED16[5]; + __IO uint32_t MMCTPCGR; + uint32_t RESERVED17[10]; + __IO uint32_t MMCRCRCEPR; + __IO uint32_t MMCRAEPR; + uint32_t RESERVED18[10]; + __IO uint32_t MMCRUPGR; + uint32_t RESERVED19[9]; + __IO uint32_t MMCTLPIMSTR; + __IO uint32_t MMCTLPITCR; + __IO uint32_t MMCRLPIMSTR; + __IO uint32_t MMCRLPITCR; + uint32_t RESERVED20[65]; + __IO uint32_t MACL3L4C0R; + __IO uint32_t MACL4A0R; + uint32_t RESERVED21[2]; + __IO uint32_t MACL3A0R0R; + __IO uint32_t MACL3A1R0R; + __IO uint32_t MACL3A2R0R; + __IO uint32_t MACL3A3R0R; + uint32_t RESERVED22[4]; + __IO uint32_t MACL3L4C1R; + __IO uint32_t MACL4A1R; + uint32_t RESERVED23[2]; + __IO uint32_t MACL3A0R1R; + __IO uint32_t MACL3A1R1R; + __IO uint32_t MACL3A2R1R; + __IO uint32_t MACL3A3R1R; + uint32_t RESERVED24[108]; + __IO uint32_t MACTSCR; + __IO uint32_t MACSSIR; + __IO uint32_t MACSTSR; + __IO uint32_t MACSTNR; + __IO uint32_t MACSTSUR; + __IO uint32_t MACSTNUR; + __IO uint32_t MACTSAR; + uint32_t RESERVED25; + __IO uint32_t MACTSSR; + uint32_t RESERVED26[3]; + __IO uint32_t MACTTSSNR; + __IO uint32_t MACTTSSSR; + uint32_t RESERVED27[2]; + __IO uint32_t MACACR; + uint32_t RESERVED28; + __IO uint32_t MACATSNR; + __IO uint32_t MACATSSR; + __IO uint32_t MACTSIACR; + __IO uint32_t MACTSEACR; + __IO uint32_t MACTSICNR; + __IO uint32_t MACTSECNR; + uint32_t RESERVED29[4]; + __IO uint32_t MACPPSCR; + uint32_t RESERVED30[3]; + __IO uint32_t MACPPSTTSR; + __IO uint32_t MACPPSTTNR; + __IO uint32_t MACPPSIR; + __IO uint32_t MACPPSWR; + uint32_t RESERVED31[12]; + __IO uint32_t MACPOCR; + __IO uint32_t MACSPI0R; + __IO uint32_t MACSPI1R; + __IO uint32_t MACSPI2R; + __IO uint32_t MACLMIR; + uint32_t RESERVED32[11]; + __IO uint32_t MTLOMR; + uint32_t RESERVED33[7]; + __IO uint32_t MTLISR; + uint32_t RESERVED34[55]; + __IO uint32_t MTLTQOMR; + __IO uint32_t MTLTQUR; + __IO uint32_t MTLTQDR; + uint32_t RESERVED35[8]; + __IO uint32_t MTLQICSR; + __IO uint32_t MTLRQOMR; + __IO uint32_t MTLRQMPOCR; + __IO uint32_t MTLRQDR; + uint32_t RESERVED36[177]; + __IO uint32_t DMAMR; + __IO uint32_t DMASBMR; + __IO uint32_t DMAISR; + __IO uint32_t DMADSR; + uint32_t RESERVED37[60]; + __IO uint32_t DMACCR; + __IO uint32_t DMACTCR; + __IO uint32_t DMACRCR; + uint32_t RESERVED38[2]; + __IO uint32_t DMACTDLAR; + uint32_t RESERVED39; + __IO uint32_t DMACRDLAR; + __IO uint32_t DMACTDTPR; + uint32_t RESERVED40; + __IO uint32_t DMACRDTPR; + __IO uint32_t DMACTDRLR; + __IO uint32_t DMACRDRLR; + __IO uint32_t DMACIER; + __IO uint32_t DMACRIWTR; +__IO uint32_t DMACSFCSR; + uint32_t RESERVED41; + __IO uint32_t DMACCATDR; + uint32_t RESERVED42; + __IO uint32_t DMACCARDR; + uint32_t RESERVED43; + __IO uint32_t DMACCATBR; + uint32_t RESERVED44; + __IO uint32_t DMACCARBR; + __IO uint32_t DMACSR; +uint32_t RESERVED45[2]; +__IO uint32_t DMACMFCR; +}ETH_TypeDef; +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ +__IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */ +__IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */ +__IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */ +__IO uint32_t D3PMR1; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR1) Address offset: 0x0C */ +__IO uint32_t D3PCR1L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR1L) Address offset: 0x10 */ +__IO uint32_t D3PCR1H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR1H) Address offset: 0x14 */ +uint32_t RESERVED1[2]; /*!< Reserved, 0x18 to 0x1C */ +__IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */ +__IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */ +__IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */ +__IO uint32_t D3PMR2; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR2) Address offset: 0x2C */ +__IO uint32_t D3PCR2L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR2L) Address offset: 0x30 */ +__IO uint32_t D3PCR2H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR2H) Address offset: 0x34 */ +uint32_t RESERVED2[2]; /*!< Reserved, 0x38 to 0x3C */ +__IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */ +__IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */ +__IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */ +__IO uint32_t D3PMR3; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR3) Address offset: 0x4C */ +__IO uint32_t D3PCR3L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR3L) Address offset: 0x50 */ +__IO uint32_t D3PCR3H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR3H) Address offset: 0x54 */ +uint32_t RESERVED3[10]; /*!< Reserved, 0x58 to 0x7C */ +__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x80 */ +__IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x84 */ +__IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x88 */ +uint32_t RESERVED4; /*!< Reserved, 0x8C */ +__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x90 */ +__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x94 */ +__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x98 */ +uint32_t RESERVED5; /*!< Reserved, 0x9C */ +__IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0xA0 */ +__IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0xA4 */ +__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0xA8 */ +}EXTI_TypeDef; + +/** + * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2 + * with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2. + * Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register: + * IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7) + * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4) + * Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only + */ + +typedef struct +{ +__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ +__IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */ +__IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x08 */ +uint32_t RESERVED1; /*!< Reserved, 0x0C */ +__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */ +__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */ +__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x18 */ +uint32_t RESERVED2; /*!< Reserved, 0x1C */ +__IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ +__IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */ +__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0x28 */ +}EXTI_Core_TypeDef; + + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t KEYR1; /*!< Flash Key Register for bank1, Address offset: 0x04 */ + __IO uint32_t OPTKEYR; /*!< Flash Option Key Register, Address offset: 0x08 */ + __IO uint32_t CR1; /*!< Flash Control Register for bank1, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< Flash Status Register for bank1, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< Flash Control Register for bank1, Address offset: 0x14 */ + __IO uint32_t OPTCR; /*!< Flash Option Control Register, Address offset: 0x18 */ + __IO uint32_t OPTSR_CUR; /*!< Flash Option Status Current Register, Address offset: 0x1C */ + __IO uint32_t OPTSR_PRG; /*!< Flash Option Status to Program Register, Address offset: 0x20 */ + __IO uint32_t OPTCCR; /*!< Flash Option Clear Control Register, Address offset: 0x24 */ + __IO uint32_t PRAR_CUR1; /*!< Flash Current Protection Address Register for bank1, Address offset: 0x28 */ + __IO uint32_t PRAR_PRG1; /*!< Flash Protection Address to Program Register for bank1, Address offset: 0x2C */ + __IO uint32_t SCAR_CUR1; /*!< Flash Current Secure Address Register for bank1, Address offset: 0x30 */ + __IO uint32_t SCAR_PRG1; /*!< Flash Secure Address to Program Register for bank1, Address offset: 0x34 */ + __IO uint32_t WPSN_CUR1; /*!< Flash Current Write Protection Register on bank1, Address offset: 0x38 */ + __IO uint32_t WPSN_PRG1; /*!< Flash Write Protection to Program Register on bank1, Address offset: 0x3C */ + __IO uint32_t BOOT_CUR; /*!< Flash Current Boot Address for Pelican Core Register, Address offset: 0x40 */ + __IO uint32_t BOOT_PRG; /*!< Flash Boot Address to Program for Pelican Core Register, Address offset: 0x44 */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x48 to 0x4C */ + __IO uint32_t CRCCR1; /*!< Flash CRC Control register For Bank1 Register , Address offset: 0x50 */ + __IO uint32_t CRCSADD1; /*!< Flash CRC Start Address Register for Bank1 , Address offset: 0x54 */ + __IO uint32_t CRCEADD1; /*!< Flash CRC End Address Register for Bank1 , Address offset: 0x58 */ + __IO uint32_t CRCDATA; /*!< Flash CRC Data Register for Bank1 , Address offset: 0x5C */ + __IO uint32_t ECC_FA1; /*!< Flash ECC Fail Address For Bank1 Register , Address offset: 0x60 */ + uint32_t RESERVED1[40]; /*!< Reserved, 0x64 to 0x100 */ + __IO uint32_t KEYR2; /*!< Flash Key Register for bank2, Address offset: 0x104 */ + uint32_t RESERVED2; /*!< Reserved, 0x108 */ + __IO uint32_t CR2; /*!< Flash Control Register for bank2, Address offset: 0x10C */ + __IO uint32_t SR2; /*!< Flash Status Register for bank2, Address offset: 0x110 */ + __IO uint32_t CCR2; /*!< Flash Status Register for bank2, Address offset: 0x114 */ + uint32_t RESERVED3[4]; /*!< Reserved, 0x118 to 0x124 */ + __IO uint32_t PRAR_CUR2; /*!< Flash Current Protection Address Register for bank2, Address offset: 0x128 */ + __IO uint32_t PRAR_PRG2; /*!< Flash Protection Address to Program Register for bank2, Address offset: 0x12C */ + __IO uint32_t SCAR_CUR2; /*!< Flash Current Secure Address Register for bank2, Address offset: 0x130 */ + __IO uint32_t SCAR_PRG2; /*!< Flash Secure Address Register for bank2, Address offset: 0x134 */ + __IO uint32_t WPSN_CUR2; /*!< Flash Current Write Protection Register on bank2, Address offset: 0x138 */ + __IO uint32_t WPSN_PRG2; /*!< Flash Write Protection to Program Register on bank2, Address offset: 0x13C */ + uint32_t RESERVED4[4]; /*!< Reserved, 0x140 to 0x14C */ + __IO uint32_t CRCCR2; /*!< Flash CRC Control register For Bank2 Register , Address offset: 0x150 */ + __IO uint32_t CRCSADD2; /*!< Flash CRC Start Address Register for Bank2 , Address offset: 0x154 */ + __IO uint32_t CRCEADD2; /*!< Flash CRC End Address Register for Bank2 , Address offset: 0x158 */ + __IO uint32_t CRCDATA2; /*!< Flash CRC Data Register for Bank2 , Address offset: 0x15C */ + __IO uint32_t ECC_FA2; /*!< Flash ECC Fail Address For Bank2 Register , Address offset: 0x160 */ +} FLASH_TypeDef; + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank2 + */ + +typedef struct +{ + __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ + __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ + __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ + __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ + uint32_t RESERVED0; /*!< Reserved, 0x70 */ + __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ +} FMC_Bank2_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + uint32_t RESERVED; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ +} FMC_Bank3_TypeDef; + +/** + * @brief Flexible Memory Controller Bank5 and 6 + */ + + +typedef struct +{ + __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ + __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ + __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ + __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */ + __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */ +} FMC_Bank5_6_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ +} GPIO_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t HSOTR; /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */ +} OPAMP_TypeDef; + +/** + * @brief System configuration controller + */ + +typedef struct +{ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x00 */ + __IO uint32_t PMCR; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + __IO uint32_t CFGR; /*!< SYSCFG configuration registers, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t CCCSR; /*!< SYSCFG compensation cell control/status register, Address offset: 0x20 */ + __IO uint32_t CCVR; /*!< SYSCFG compensation cell value register, Address offset: 0x24 */ + __IO uint32_t CCCR; /*!< SYSCFG compensation cell code register, Address offset: 0x28 */ + __IO uint32_t PWRCR; /*!< PWR control register, Address offset: 0x2C */ + uint32_t RESERVED3[61]; /*!< Reserved, 0x30-0x120 */ + __IO uint32_t PKGR; /*!< SYSCFG package register, Address offset: 0x124 */ + uint32_t RESERVED4[118]; /*!< Reserved, 0x128-0x2FC */ + __IO uint32_t UR0; /*!< SYSCFG user register 0, Address offset: 0x300 */ + __IO uint32_t UR1; /*!< SYSCFG user register 1, Address offset: 0x304 */ + __IO uint32_t UR2; /*!< SYSCFG user register 2, Address offset: 0x308 */ + __IO uint32_t UR3; /*!< SYSCFG user register 3, Address offset: 0x30C */ + __IO uint32_t UR4; /*!< SYSCFG user register 4, Address offset: 0x310 */ + __IO uint32_t UR5; /*!< SYSCFG user register 5, Address offset: 0x314 */ + __IO uint32_t UR6; /*!< SYSCFG user register 6, Address offset: 0x318 */ + __IO uint32_t UR7; /*!< SYSCFG user register 7, Address offset: 0x31C */ + __IO uint32_t UR8; /*!< SYSCFG user register 8, Address offset: 0x320 */ + __IO uint32_t UR9; /*!< SYSCFG user register 9, Address offset: 0x324 */ + __IO uint32_t UR10; /*!< SYSCFG user register 10, Address offset: 0x328 */ + __IO uint32_t UR11; /*!< SYSCFG user register 11, Address offset: 0x32C */ + __IO uint32_t UR12; /*!< SYSCFG user register 12, Address offset: 0x330 */ + __IO uint32_t UR13; /*!< SYSCFG user register 13, Address offset: 0x334 */ + __IO uint32_t UR14; /*!< SYSCFG user register 14, Address offset: 0x338 */ + __IO uint32_t UR15; /*!< SYSCFG user register 15, Address offset: 0x33C */ + __IO uint32_t UR16; /*!< SYSCFG user register 16, Address offset: 0x340 */ + __IO uint32_t UR17; /*!< SYSCFG user register 17, Address offset: 0x344 */ + +} SYSCFG_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + + +/** + * @brief JPEG Codec + */ +typedef struct +{ + __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */ + __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */ + __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */ + __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */ + __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */ + __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */ + __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */ + __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */ + uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */ + __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */ + __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */ + __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */ + uint32_t Reserved3c; /* Reserved Address offset: 3Ch */ + __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */ + __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */ + uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */ + __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */ + __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */ + __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */ + __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */ + __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */ + __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */ + __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */ + __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */ + uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */ + __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */ + __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */ + __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */ + __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */ + +} JPEG_TypeDef; + +/** + * @brief LCD-TFT Display Controller + */ + +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ + __IO uint32_t CSR1; /*!< PWR power control status register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */ + __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x0C */ + __IO uint32_t CPUCR; /*!< PWR CPU control register, Address offset: 0x10 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t D3CR; /*!< PWR D3 domain control register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t WKUPCR; /*!< PWR wakeup clear register, Address offset: 0x20 */ + __IO uint32_t WKUPFR; /*!< PWR wakeup flag register, Address offset: 0x24 */ + __IO uint32_t WKUPEPR; /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t HSICFGR; /*!< HSI Clock Calibration Register, Address offset: 0x04 */ + __IO uint32_t CRRCR; /*!< Clock Recovery RC Register, Address offset: 0x08 */ + __IO uint32_t CSICFGR; /*!< CSI Clock Calibration Register, Address offset: 0x0C */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t D1CFGR; /*!< RCC Domain 1 configuration register, Address offset: 0x18 */ + __IO uint32_t D2CFGR; /*!< RCC Domain 2 configuration register, Address offset: 0x1C */ + __IO uint32_t D3CFGR; /*!< RCC Domain 3 configuration register, Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t PLLCKSELR; /*!< RCC PLLs Clock Source Selection Register, Address offset: 0x28 */ + __IO uint32_t PLLCFGR; /*!< RCC PLLs Configuration Register, Address offset: 0x2C */ + __IO uint32_t PLL1DIVR; /*!< RCC PLL1 Dividers Configuration Register, Address offset: 0x30 */ + __IO uint32_t PLL1FRACR; /*!< RCC PLL1 Fractional Divider Configuration Register, Address offset: 0x34 */ + __IO uint32_t PLL2DIVR; /*!< RCC PLL2 Dividers Configuration Register, Address offset: 0x38 */ + __IO uint32_t PLL2FRACR; /*!< RCC PLL2 Fractional Divider Configuration Register, Address offset: 0x3C */ + __IO uint32_t PLL3DIVR; /*!< RCC PLL3 Dividers Configuration Register, Address offset: 0x40 */ + __IO uint32_t PLL3FRACR; /*!< RCC PLL3 Fractional Divider Configuration Register, Address offset: 0x44 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x48 */ + __IO uint32_t D1CCIPR; /*!< RCC Domain 1 Kernel Clock Configuration Register Address offset: 0x4C */ + __IO uint32_t D2CCIP1R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x50 */ + __IO uint32_t D2CCIP2R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x54 */ + __IO uint32_t D3CCIPR; /*!< RCC Domain 3 Kernel Clock Configuration Register Address offset: 0x58 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x5C */ + __IO uint32_t CIER; /*!< RCC Clock Source Interrupt Enable Register Address offset: 0x60 */ + __IO uint32_t CIFR; /*!< RCC Clock Source Interrupt Flag Register Address offset: 0x64 */ + __IO uint32_t CICR; /*!< RCC Clock Source Interrupt Clear Register Address offset: 0x68 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x6C */ + __IO uint32_t BDCR; /*!< RCC Vswitch Backup Domain Control Register, Address offset: 0x70 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x78 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x7C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x80 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x84 */ + __IO uint32_t AHB4RSTR; /*!< RCC AHB4 peripheral reset register, Address offset: 0x88 */ + __IO uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x8C */ + __IO uint32_t APB1LRSTR; /*!< RCC APB1 peripheral reset Low Word register, Address offset: 0x90 */ + __IO uint32_t APB1HRSTR; /*!< RCC APB1 peripheral reset High Word register, Address offset: 0x94 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x98 */ + __IO uint32_t APB4RSTR; /*!< RCC APB4 peripheral reset register, Address offset: 0x9C */ + __IO uint32_t GCR; /*!< RCC RCC Global Control Register, Address offset: 0xA0 */ + uint32_t RESERVED8; /*!< Reserved, Address offset: 0xA4 */ + __IO uint32_t D3AMR; /*!< RCC Domain 3 Autonomous Mode Register, Address offset: 0xA8 */ + uint32_t RESERVED11[9]; /*!< Reserved, 0xAC-0xCC Address offset: 0xAC */ + __IO uint32_t RSR; /*!< RCC Reset status register, Address offset: 0xD0 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0xD4 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0xD8 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0xDC */ + __IO uint32_t AHB4ENR; /*!< RCC AHB4 peripheral clock register, Address offset: 0xE0 */ + __IO uint32_t APB3ENR; /*!< RCC APB3 peripheral clock register, Address offset: 0xE4 */ + __IO uint32_t APB1LENR; /*!< RCC APB1 peripheral clock Low Word register, Address offset: 0xE8 */ + __IO uint32_t APB1HENR; /*!< RCC APB1 peripheral clock High Word register, Address offset: 0xEC */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock register, Address offset: 0xF0 */ + __IO uint32_t APB4ENR; /*!< RCC APB4 peripheral clock register, Address offset: 0xF4 */ + uint32_t RESERVED12; /*!< Reserved, Address offset: 0xF8 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral sleep clock register, Address offset: 0xFC */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral sleep clock register, Address offset: 0x100 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral sleep clock register, Address offset: 0x104 */ + __IO uint32_t AHB4LPENR; /*!< RCC AHB4 peripheral sleep clock register, Address offset: 0x108 */ + __IO uint32_t APB3LPENR; /*!< RCC APB3 peripheral sleep clock register, Address offset: 0x10C */ + __IO uint32_t APB1LLPENR; /*!< RCC APB1 peripheral sleep clock Low Word register, Address offset: 0x110 */ + __IO uint32_t APB1HLPENR; /*!< RCC APB1 peripheral sleep clock High Word register, Address offset: 0x114 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral sleep clock register, Address offset: 0x118 */ + __IO uint32_t APB4LPENR; /*!< RCC APB4 peripheral sleep clock register, Address offset: 0x11C */ + uint32_t RESERVED13[4]; /*!< Reserved, 0x120-0x12C Address offset: 0x120 */ + +} RCC_TypeDef; + + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ + __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ + __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */ + __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */ + __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */ + __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */ + __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */ + __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */ + __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */ + __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */ + __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */ + __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */ + __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */ + __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ +} RTC_TypeDef; + +/** + * @brief Serial Audio Interface + */ + +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED0[16]; /*!< Reserved, 0x04 - 0x43 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief SPDIF-RX Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */ + __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */ + __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */ + __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */ + __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1A */ +} SPDIFRX_TypeDef; + + +/** + * @brief Secure digital input/output Interface + */ + +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ + uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ + __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ + __IO uint32_t IDMABASE0; /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58 */ + __IO uint32_t IDMABASE1; /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C */ + uint32_t RESERVED1[8]; /*!< Reserved, 0x60-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ + uint32_t RESERVED2[222]; /*!< Reserved, 0x84-0x3F8 */ + __IO uint32_t IPVR; /*!< SDMMC data FIFO register, Address offset: 0x3FC */ +} SDMMC_TypeDef; + + +/** + * @brief Delay Block DLYB + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */ +} DLYB_TypeDef; + +/** + * @brief HW Semaphore HSEM + */ + +typedef struct +{ + __IO uint32_t R[32]; /*!< 2-step write lock and read back registers, Address offset: 00h-7Ch */ + __IO uint32_t RLR[32]; /*!< 1-step read lock registers, Address offset: 80h-FCh */ + __IO uint32_t C1IER; /*!< HSEM Interrupt enable register , Address offset: 100h */ + __IO uint32_t C1ICR; /*!< HSEM Interrupt clear register , Address offset: 104h */ + __IO uint32_t C1ISR; /*!< HSEM Interrupt Status register , Address offset: 108h */ + __IO uint32_t C1MISR; /*!< HSEM Interrupt Masked Status register , Address offset: 10Ch */ + uint32_t Reserved[12]; /* Reserved Address offset: 110h-13Ch */ + __IO uint32_t CR; /*!< HSEM Semaphore clear register , Address offset: 140h */ + __IO uint32_t KEYR; /*!< HSEM Semaphore clear key register , Address offset: 144h */ + +} HSEM_TypeDef; + +typedef struct +{ + __IO uint32_t IER; /*!< HSEM interrupt enable register , Address offset: 0h */ + __IO uint32_t ICR; /*!< HSEM interrupt clear register , Address offset: 4h */ + __IO uint32_t ISR; /*!< HSEM interrupt status register , Address offset: 8h */ + __IO uint32_t MISR; /*!< HSEM masked interrupt status register , Address offset: Ch */ +} HSEM_Common_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IO uint32_t IER; /*!< SPI/I2S Interrupt Enable register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< SPI/I2S Status register, Address offset: 0x14 */ + __IO uint32_t IFCR; /*!< SPI/I2S Interrupt/Status flags clear register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, 0x1C */ + __IO uint32_t TXDR; /*!< SPI/I2S Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */ + __IO uint32_t RXDR; /*!< SPI/I2S Receive data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */ + __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ + __IO uint32_t I2SCFGR; /*!< I2S Configuration register, Address offset: 0x50 */ + +} SPI_TypeDef; +/** + * @brief QUAD Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */ + __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */ + __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */ + __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */ + __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ + __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */ + __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ + __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */ + __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ +} QUADSPI_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + uint32_t RESERVED1; /*!< Reserved, 0x50 */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ +} TIM_TypeDef; + +/** + * @brief LPTIMIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved, 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register, Address offset: 0x24 */ +} LPTIM_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + __IO uint32_t SR; /*!< Comparator status register, Address offset: 0x00 */ + __IO uint32_t ICFR; /*!< Comparator interrupt clear flag register, Address offset: 0x04 */ + __IO uint32_t OR; /*!< Comparator option register, Address offset: 0x08 */ +} COMPOPT_TypeDef; + +typedef struct +{ + __IO uint32_t CFGR; /*!< Comparator configuration register , Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CFGR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ +} COMP_Common_TypeDef; +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief Single Wire Protocol Master Interface SPWMI + */ +typedef struct +{ + __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */ + __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */ + uint32_t RESERVED1; /*!< Reserved, 0x08 */ + __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */ + __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */ + __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */ + __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */ + __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */ + __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */ +} SWPMI_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + + +/** + * @brief RAM_ECC_Specific_Registers + */ +typedef struct +{ + __IO uint32_t CR; /*!< RAMECC monitor configuration register */ + __IO uint32_t SR; /*!< RAMECC monitor status register */ + __IO uint32_t FAR; /*!< RAMECC monitor failing address register */ + __IO uint32_t FDRL; /*!< RAMECC monitor failing data low register */ + __IO uint32_t FDRH; /*!< RAMECC monitor failing data high register */ + __IO uint32_t FECR; /*!< RAMECC monitor failing ECC error code register */ +} RAMECC_MonitorTypeDef; + +typedef struct +{ + __IO uint32_t IER; /*!< RAMECC interrupt enable register */ +} RAMECC_TypeDef; +/** + * @} + */ + + +/** + * @brief Crypto Processor + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */ + __IO uint32_t DIN; /*!< CRYP data input register, Address offset: 0x08 */ + __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */ + __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */ + __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */ + __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */ + __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */ + __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */ + __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */ + __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */ + __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */ + __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */ + __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */ + __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */ + __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */ + __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */ + __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */ + __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */ + __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */ + __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */ + __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */ + __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */ + __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */ + __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */ + __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */ + __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */ + __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */ + __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */ + __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */ + __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */ + __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */ + __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */ + __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */ + __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */ + __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */ +} CRYP_TypeDef; + +/** + * @brief HASH + */ + +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ + +typedef struct +{ + __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */ +} HASH_DIGEST_TypeDef; + + +/** + * @brief High resolution Timer (HRTIM) + */ +/* HRTIM master registers definition */ +typedef struct +{ + __IO uint32_t MCR; /*!< HRTIM Master Timer control register, Address offset: 0x00 */ + __IO uint32_t MISR; /*!< HRTIM Master Timer interrupt status register, Address offset: 0x04 */ + __IO uint32_t MICR; /*!< HRTIM Master Timer interrupt clear register, Address offset: 0x08 */ + __IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Address offset: 0x0C */ + __IO uint32_t MCNTR; /*!< HRTIM Master Timer counter register, Address offset: 0x10 */ + __IO uint32_t MPER; /*!< HRTIM Master Timer period register, Address offset: 0x14 */ + __IO uint32_t MREP; /*!< HRTIM Master Timer repetition register, Address offset: 0x18 */ + __IO uint32_t MCMP1R; /*!< HRTIM Master Timer compare 1 register, Address offset: 0x1C */ + uint32_t RESERVED0; /*!< Reserved, 0x20 */ + __IO uint32_t MCMP2R; /*!< HRTIM Master Timer compare 2 register, Address offset: 0x24 */ + __IO uint32_t MCMP3R; /*!< HRTIM Master Timer compare 3 register, Address offset: 0x28 */ + __IO uint32_t MCMP4R; /*!< HRTIM Master Timer compare 4 register, Address offset: 0x2C */ + uint32_t RESERVED1[20]; /*!< Reserved, 0x30..0x7C */ +}HRTIM_Master_TypeDef; + +/* HRTIM Timer A to E registers definition */ +typedef struct +{ + __IO uint32_t TIMxCR; /*!< HRTIM Timerx control register, Address offset: 0x00 */ + __IO uint32_t TIMxISR; /*!< HRTIM Timerx interrupt status register, Address offset: 0x04 */ + __IO uint32_t TIMxICR; /*!< HRTIM Timerx interrupt clear register, Address offset: 0x08 */ + __IO uint32_t TIMxDIER; /*!< HRTIM Timerx DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t CNTxR; /*!< HRTIM Timerx counter register, Address offset: 0x10 */ + __IO uint32_t PERxR; /*!< HRTIM Timerx period register, Address offset: 0x14 */ + __IO uint32_t REPxR; /*!< HRTIM Timerx repetition register, Address offset: 0x18 */ + __IO uint32_t CMP1xR; /*!< HRTIM Timerx compare 1 register, Address offset: 0x1C */ + __IO uint32_t CMP1CxR; /*!< HRTIM Timerx compare 1 compound register, Address offset: 0x20 */ + __IO uint32_t CMP2xR; /*!< HRTIM Timerx compare 2 register, Address offset: 0x24 */ + __IO uint32_t CMP3xR; /*!< HRTIM Timerx compare 3 register, Address offset: 0x28 */ + __IO uint32_t CMP4xR; /*!< HRTIM Timerx compare 4 register, Address offset: 0x2C */ + __IO uint32_t CPT1xR; /*!< HRTIM Timerx capture 1 register, Address offset: 0x30 */ + __IO uint32_t CPT2xR; /*!< HRTIM Timerx capture 2 register, Address offset: 0x34 */ + __IO uint32_t DTxR; /*!< HRTIM Timerx dead time register, Address offset: 0x38 */ + __IO uint32_t SETx1R; /*!< HRTIM Timerx output 1 set register, Address offset: 0x3C */ + __IO uint32_t RSTx1R; /*!< HRTIM Timerx output 1 reset register, Address offset: 0x40 */ + __IO uint32_t SETx2R; /*!< HRTIM Timerx output 2 set register, Address offset: 0x44 */ + __IO uint32_t RSTx2R; /*!< HRTIM Timerx output 2 reset register, Address offset: 0x48 */ + __IO uint32_t EEFxR1; /*!< HRTIM Timerx external event filtering 1 register, Address offset: 0x4C */ + __IO uint32_t EEFxR2; /*!< HRTIM Timerx external event filtering 2 register, Address offset: 0x50 */ + __IO uint32_t RSTxR; /*!< HRTIM Timerx Reset register, Address offset: 0x54 */ + __IO uint32_t CHPxR; /*!< HRTIM Timerx Chopper register, Address offset: 0x58 */ + __IO uint32_t CPT1xCR; /*!< HRTIM Timerx Capture 1 register, Address offset: 0x5C */ + __IO uint32_t CPT2xCR; /*!< HRTIM Timerx Capture 2 register, Address offset: 0x60 */ + __IO uint32_t OUTxR; /*!< HRTIM Timerx Output register, Address offset: 0x64 */ + __IO uint32_t FLTxR; /*!< HRTIM Timerx Fault register, Address offset: 0x68 */ + uint32_t RESERVED0[5]; /*!< Reserved, 0x6C..0x7C */ +}HRTIM_Timerx_TypeDef; + +/* HRTIM common register definition */ +typedef struct +{ + __IO uint32_t CR1; /*!< HRTIM control register1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< HRTIM control register2, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< HRTIM interrupt status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< HRTIM interrupt clear register, Address offset: 0x0C */ + __IO uint32_t IER; /*!< HRTIM interrupt enable register, Address offset: 0x10 */ + __IO uint32_t OENR; /*!< HRTIM Output enable register, Address offset: 0x14 */ + __IO uint32_t ODISR; /*!< HRTIM Output disable register, Address offset: 0x18 */ + __IO uint32_t ODSR; /*!< HRTIM Output disable status register, Address offset: 0x1C */ + __IO uint32_t BMCR; /*!< HRTIM Burst mode control register, Address offset: 0x20 */ + __IO uint32_t BMTRGR; /*!< HRTIM Burst mode trigger register, Address offset: 0x24 */ + __IO uint32_t BMCMPR; /*!< HRTIM Burst mode compare register, Address offset: 0x28 */ + __IO uint32_t BMPER; /*!< HRTIM Burst mode period register, Address offset: 0x2C */ + __IO uint32_t EECR1; /*!< HRTIM Timer external event control register1, Address offset: 0x30 */ + __IO uint32_t EECR2; /*!< HRTIM Timer external event control register2, Address offset: 0x34 */ + __IO uint32_t EECR3; /*!< HRTIM Timer external event control register3, Address offset: 0x38 */ + __IO uint32_t ADC1R; /*!< HRTIM ADC Trigger 1 register, Address offset: 0x3C */ + __IO uint32_t ADC2R; /*!< HRTIM ADC Trigger 2 register, Address offset: 0x40 */ + __IO uint32_t ADC3R; /*!< HRTIM ADC Trigger 3 register, Address offset: 0x44 */ + __IO uint32_t ADC4R; /*!< HRTIM ADC Trigger 4 register, Address offset: 0x48 */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x4C */ + __IO uint32_t FLTINR1; /*!< HRTIM Fault input register1, Address offset: 0x50 */ + __IO uint32_t FLTINR2; /*!< HRTIM Fault input register2, Address offset: 0x54 */ + __IO uint32_t BDMUPR; /*!< HRTIM Burst DMA Master Timer update register, Address offset: 0x58 */ + __IO uint32_t BDTAUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x5C */ + __IO uint32_t BDTBUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x60 */ + __IO uint32_t BDTCUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x64 */ + __IO uint32_t BDTDUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x68 */ + __IO uint32_t BDTEUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x6C */ + __IO uint32_t BDMADR; /*!< HRTIM Burst DMA Master Data register, Address offset: 0x70 */ +}HRTIM_Common_TypeDef; + +/* HRTIM register definition */ +typedef struct { + HRTIM_Master_TypeDef sMasterRegs; + HRTIM_Timerx_TypeDef sTimerxRegs[5]; + uint32_t RESERVED0[32]; + HRTIM_Common_TypeDef sCommonRegs; +}HRTIM_TypeDef; +/** + * @brief RNG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + +/** + * @brief MDIOS + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t WRFR; + __IO uint32_t CWRFR; + __IO uint32_t RDFR; + __IO uint32_t CRDFR; + __IO uint32_t SR; + __IO uint32_t CLRFR; + uint32_t RESERVED[57]; + __IO uint32_t DINR0; + __IO uint32_t DINR1; + __IO uint32_t DINR2; + __IO uint32_t DINR3; + __IO uint32_t DINR4; + __IO uint32_t DINR5; + __IO uint32_t DINR6; + __IO uint32_t DINR7; + __IO uint32_t DINR8; + __IO uint32_t DINR9; + __IO uint32_t DINR10; + __IO uint32_t DINR11; + __IO uint32_t DINR12; + __IO uint32_t DINR13; + __IO uint32_t DINR14; + __IO uint32_t DINR15; + __IO uint32_t DINR16; + __IO uint32_t DINR17; + __IO uint32_t DINR18; + __IO uint32_t DINR19; + __IO uint32_t DINR20; + __IO uint32_t DINR21; + __IO uint32_t DINR22; + __IO uint32_t DINR23; + __IO uint32_t DINR24; + __IO uint32_t DINR25; + __IO uint32_t DINR26; + __IO uint32_t DINR27; + __IO uint32_t DINR28; + __IO uint32_t DINR29; + __IO uint32_t DINR30; + __IO uint32_t DINR31; + __IO uint32_t DOUTR0; + __IO uint32_t DOUTR1; + __IO uint32_t DOUTR2; + __IO uint32_t DOUTR3; + __IO uint32_t DOUTR4; + __IO uint32_t DOUTR5; + __IO uint32_t DOUTR6; + __IO uint32_t DOUTR7; + __IO uint32_t DOUTR8; + __IO uint32_t DOUTR9; + __IO uint32_t DOUTR10; + __IO uint32_t DOUTR11; + __IO uint32_t DOUTR12; + __IO uint32_t DOUTR13; + __IO uint32_t DOUTR14; + __IO uint32_t DOUTR15; + __IO uint32_t DOUTR16; + __IO uint32_t DOUTR17; + __IO uint32_t DOUTR18; + __IO uint32_t DOUTR19; + __IO uint32_t DOUTR20; + __IO uint32_t DOUTR21; + __IO uint32_t DOUTR22; + __IO uint32_t DOUTR23; + __IO uint32_t DOUTR24; + __IO uint32_t DOUTR25; + __IO uint32_t DOUTR26; + __IO uint32_t DOUTR27; + __IO uint32_t DOUTR28; + __IO uint32_t DOUTR29; + __IO uint32_t DOUTR30; + __IO uint32_t DOUTR31; +} MDIOS_TypeDef; + + +/** + * @brief USB_OTG_Core_Registers + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */ + uint32_t Reserved30[2]; /*!< Reserved 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */ + __IO uint32_t CID; /*!< User ID Register 03Ch */ + __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/ + __IO uint32_t GHWCFG1; /* User HW config1 044h*/ + __IO uint32_t GHWCFG2; /* User HW config2 048h*/ + __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */ + uint32_t Reserved6; /*!< Reserved 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register 054h */ + __IO uint32_t GPWRDN; /*!< Power Down Register 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */ + uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */ +} USB_OTG_GlobalTypeDef; + + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register 800h */ + __IO uint32_t DCTL; /*!< dev Control Register 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */ + uint32_t Reserved0C; /*!< Reserved 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */ + uint32_t Reserved20; /*!< Reserved 820h */ + uint32_t Reserved9; /*!< Reserved 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */ + uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ +} USB_OTG_DeviceTypeDef; + + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ + uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */ + uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */ +} USB_OTG_OUTEndpointTypeDef; + + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */ + uint32_t Reserved40C; /*!< Reserved 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */ + uint32_t Reserved[2]; /*!< Reserved */ +} USB_OTG_HostChannelTypeDef; +/** + * @} + */ + + +/** + * @brief Global Programmer View + */ + +typedef struct +{ + uint32_t RESERVED0[2036]; /*!< Reserved, Address offset: 0x00-0x1FCC */ + __IO uint32_t AXI_PERIPH_ID_4; /*!< AXI interconnect - peripheral ID4 register, Address offset: 0x1FD0 */ + uint32_t AXI_PERIPH_ID_5; /*!< Reserved, Address offset: 0x1FD4 */ + uint32_t AXI_PERIPH_ID_6; /*!< Reserved, Address offset: 0x1FD8 */ + uint32_t AXI_PERIPH_ID_7; /*!< Reserved, Address offset: 0x1FDC */ + __IO uint32_t AXI_PERIPH_ID_0; /*!< AXI interconnect - peripheral ID0 register, Address offset: 0x1FE0 */ + __IO uint32_t AXI_PERIPH_ID_1; /*!< AXI interconnect - peripheral ID1 register, Address offset: 0x1FE4 */ + __IO uint32_t AXI_PERIPH_ID_2; /*!< AXI interconnect - peripheral ID2 register, Address offset: 0x1FE8 */ + __IO uint32_t AXI_PERIPH_ID_3; /*!< AXI interconnect - peripheral ID3 register, Address offset: 0x1FEC */ + __IO uint32_t AXI_COMP_ID_0; /*!< AXI interconnect - component ID0 register, Address offset: 0x1FF0 */ + __IO uint32_t AXI_COMP_ID_1; /*!< AXI interconnect - component ID1 register, Address offset: 0x1FF4 */ + __IO uint32_t AXI_COMP_ID_2; /*!< AXI interconnect - component ID2 register, Address offset: 0x1FF8 */ + __IO uint32_t AXI_COMP_ID_3; /*!< AXI interconnect - component ID3 register, Address offset: 0x1FFC */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x2000-0x2004 */ + __IO uint32_t AXI_TARG1_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 1 bus matrix issuing functionality register, Address offset: 0x2008 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x200C-0x2020 */ + __IO uint32_t AXI_TARG1_FN_MOD2; /*!< AXI interconnect - TARG 1 bus matrix functionality 2 register, Address offset: 0x2024 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x2028 */ + __IO uint32_t AXI_TARG1_FN_MOD_LB; /*!< AXI interconnect - TARG 1 long burst functionality modification register, Address offset: 0x202C */ + uint32_t RESERVED4[54]; /*!< Reserved, Address offset: 0x2030-0x2104 */ + __IO uint32_t AXI_TARG1_FN_MOD; /*!< AXI interconnect - TARG 1 issuing functionality modification register, Address offset: 0x2108 */ + uint32_t RESERVED5[959]; /*!< Reserved, Address offset: 0x210C-0x3004 */ + __IO uint32_t AXI_TARG2_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 2 bus matrix issuing functionality register, Address offset: 0x3008 */ + uint32_t RESERVED6[6]; /*!< Reserved, Address offset: 0x300C-0x3020 */ + __IO uint32_t AXI_TARG2_FN_MOD2; /*!< AXI interconnect - TARG 2 bus matrix functionality 2 register, Address offset: 0x3024 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x3028 */ + __IO uint32_t AXI_TARG2_FN_MOD_LB; /*!< AXI interconnect - TARG 2 long burst functionality modification register, Address offset: 0x302C */ + uint32_t RESERVED8[54]; /*!< Reserved, Address offset: 0x3030-0x3104 */ + __IO uint32_t AXI_TARG2_FN_MOD; /*!< AXI interconnect - TARG 2 issuing functionality modification register, Address offset: 0x3108 */ + uint32_t RESERVED9[959]; /*!< Reserved, Address offset: 0x310C-0x4004 */ + __IO uint32_t AXI_TARG3_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 3 bus matrix issuing functionality register, Address offset: 0x4008 */ + uint32_t RESERVED10[1023]; /*!< Reserved, Address offset: 0x400C-0x5004 */ + __IO uint32_t AXI_TARG4_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 4 bus matrix issuing functionality register, Address offset: 0x5008 */ + uint32_t RESERVED11[1023]; /*!< Reserved, Address offset: 0x500C-0x6004 */ + __IO uint32_t AXI_TARG5_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 5 bus matrix issuing functionality register, Address offset: 0x6008 */ + uint32_t RESERVED12[1023]; /*!< Reserved, Address offset: 0x600C-0x7004 */ + __IO uint32_t AXI_TARG6_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 6 bus matrix issuing functionality register, Address offset: 0x7008 */ + uint32_t RESERVED13[1023]; /*!< Reserved, Address offset: 0x700C-0x8004 */ + __IO uint32_t AXI_TARG7_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 7 bus matrix issuing functionality register, Address offset: 0x8008 */ + uint32_t RESERVED14[6]; /*!< Reserved, Address offset: 0x800C-0x8020 */ + __IO uint32_t AXI_TARG7_FN_MOD2; /*!< AXI interconnect - TARG 7 bus matrix functionality 2 register, Address offset: 0x8024 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x8028 */ + __IO uint32_t AXI_TARG7_FN_MOD_LB; /*!< AXI interconnect - TARG 7 long burst functionality modification register, Address offset: 0x802C */ + uint32_t RESERVED16[54]; /*!< Reserved, Address offset: 0x8030-0x8104 */ + __IO uint32_t AXI_TARG7_FN_MOD; /*!< AXI interconnect - TARG 7 issuing functionality modification register, Address offset: 0x8108 */ + uint32_t RESERVED17[59334]; /*!< Reserved, Address offset: 0x810C-0x42020 */ + __IO uint32_t AXI_INI1_FN_MOD2; /*!< AXI interconnect - INI 1 functionality modification 2 register, Address offset: 0x42024 */ + __IO uint32_t AXI_INI1_FN_MOD_AHB; /*!< AXI interconnect - INI 1 AHB functionality modification register, Address offset: 0x42028 */ + uint32_t RESERVED18[53]; /*!< Reserved, Address offset: 0x4202C-0x420FC */ + __IO uint32_t AXI_INI1_READ_QOS; /*!< AXI interconnect - INI 1 read QoS register, Address offset: 0x42100 */ + __IO uint32_t AXI_INI1_WRITE_QOS; /*!< AXI interconnect - INI 1 write QoS register, Address offset: 0x42104 */ + __IO uint32_t AXI_INI1_FN_MOD; /*!< AXI interconnect - INI 1 issuing functionality modification register, Address offset: 0x42108 */ + uint32_t RESERVED19[1021]; /*!< Reserved, Address offset: 0x4210C-0x430FC */ + __IO uint32_t AXI_INI2_READ_QOS; /*!< AXI interconnect - INI 2 read QoS register, Address offset: 0x43100 */ + __IO uint32_t AXI_INI2_WRITE_QOS; /*!< AXI interconnect - INI 2 write QoS register, Address offset: 0x43104 */ + __IO uint32_t AXI_INI2_FN_MOD; /*!< AXI interconnect - INI 2 issuing functionality modification register, Address offset: 0x43108 */ + uint32_t RESERVED20[966]; /*!< Reserved, Address offset: 0x4310C-0x44020 */ + __IO uint32_t AXI_INI3_FN_MOD2; /*!< AXI interconnect - INI 3 functionality modification 2 register, Address offset: 0x44024 */ + __IO uint32_t AXI_INI3_FN_MOD_AHB; /*!< AXI interconnect - INI 3 AHB functionality modification register, Address offset: 0x44028 */ + uint32_t RESERVED21[53]; /*!< Reserved, Address offset: 0x4402C-0x440FC */ + __IO uint32_t AXI_INI3_READ_QOS; /*!< AXI interconnect - INI 3 read QoS register, Address offset: 0x44100 */ + __IO uint32_t AXI_INI3_WRITE_QOS; /*!< AXI interconnect - INI 3 write QoS register, Address offset: 0x44104 */ + __IO uint32_t AXI_INI3_FN_MOD; /*!< AXI interconnect - INI 3 issuing functionality modification register, Address offset: 0x44108 */ + uint32_t RESERVED22[1021]; /*!< Reserved, Address offset: 0x4410C-0x450FC */ + __IO uint32_t AXI_INI4_READ_QOS; /*!< AXI interconnect - INI 4 read QoS register, Address offset: 0x45100 */ + __IO uint32_t AXI_INI4_WRITE_QOS; /*!< AXI interconnect - INI 4 write QoS register, Address offset: 0x45104 */ + __IO uint32_t AXI_INI4_FN_MOD; /*!< AXI interconnect - INI 4 issuing functionality modification register, Address offset: 0x45108 */ + uint32_t RESERVED23[1021]; /*!< Reserved, Address offset: 0x4510C-0x460FC */ + __IO uint32_t AXI_INI5_READ_QOS; /*!< AXI interconnect - INI 5 read QoS register, Address offset: 0x46100 */ + __IO uint32_t AXI_INI5_WRITE_QOS; /*!< AXI interconnect - INI 5 write QoS register, Address offset: 0x46104 */ + __IO uint32_t AXI_INI5_FN_MOD; /*!< AXI interconnect - INI 5 issuing functionality modification register, Address offset: 0x46108 */ + uint32_t RESERVED24[1021]; /*!< Reserved, Address offset: 0x4610C-0x470FC */ + __IO uint32_t AXI_INI6_READ_QOS; /*!< AXI interconnect - INI 6 read QoS register, Address offset: 0x47100 */ + __IO uint32_t AXI_INI6_WRITE_QOS; /*!< AXI interconnect - INI 6 write QoS register, Address offset: 0x47104 */ + __IO uint32_t AXI_INI6_FN_MOD; /*!< AXI interconnect - INI 6 issuing functionality modification register, Address offset: 0x47108 */ + +} GPV_TypeDef; + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define D1_ITCMRAM_BASE (0x00000000UL) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM */ +#define D1_ITCMICP_BASE (0x00100000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over ITCM */ +#define D1_DTCMRAM_BASE (0x20000000UL) /*!< Base address of : 128KB system data RAM accessible over DTCM */ +#define D1_AXIFLASH_BASE (0x08000000UL) /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI */ +#define D1_AXIICP_BASE (0x1FF00000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over AXI */ +#define D1_AXISRAM_BASE (0x24000000UL) /*!< Base address of : (up to 512KB) system data RAM accessible over over AXI */ + +#define D2_AXISRAM_BASE (0x10000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI */ +#define D2_AHBSRAM_BASE (0x30000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI->AHB Bridge */ + +#define D3_BKPSRAM_BASE (0x38800000UL) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge */ +#define D3_SRAM_BASE (0x38000000UL) /*!< Base address of : Backup SRAM(64 KB) over AXI->AHB Bridge */ + +#define PERIPH_BASE (0x40000000UL) /*!< Base address of : AHB/APB Peripherals */ +#define QSPI_BASE (0x90000000UL) /*!< Base address of : QSPI memories accessible over AXI */ + +#define FLASH_BANK1_BASE (0x08000000UL) /*!< Base address of : (up to 1 MB) Flash Bank1 accessible over AXI */ +#define FLASH_BANK2_BASE (0x08100000UL) /*!< Base address of : (up to 1 MB) Flash Bank2 accessible over AXI */ +#define FLASH_END (0x081FFFFFUL) /*!< FLASH end address */ + +/* Legacy define */ +#define FLASH_BASE FLASH_BANK1_BASE + +/*!< Device electronic signature memory map */ +#define UID_BASE (0x1FF1E800UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FF1E880UL) /*!< FLASH Size register base address */ + + +/*!< Peripheral memory map */ +#define D2_APB1PERIPH_BASE PERIPH_BASE +#define D2_APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define D2_AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define D2_AHB2PERIPH_BASE (PERIPH_BASE + 0x08020000UL) + +#define D1_APB1PERIPH_BASE (PERIPH_BASE + 0x10000000UL) +#define D1_AHB1PERIPH_BASE (PERIPH_BASE + 0x12000000UL) + +#define D3_APB1PERIPH_BASE (PERIPH_BASE + 0x18000000UL) +#define D3_AHB1PERIPH_BASE (PERIPH_BASE + 0x18020000UL) + +/*!< Legacy Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) + + +/*!< D1_AHB1PERIPH peripherals */ + +#define MDMA_BASE (D1_AHB1PERIPH_BASE + 0x0000UL) +#define DMA2D_BASE (D1_AHB1PERIPH_BASE + 0x1000UL) +#define JPGDEC_BASE (D1_AHB1PERIPH_BASE + 0x3000UL) +#define FLASH_R_BASE (D1_AHB1PERIPH_BASE + 0x2000UL) +#define FMC_R_BASE (D1_AHB1PERIPH_BASE + 0x4000UL) +#define QSPI_R_BASE (D1_AHB1PERIPH_BASE + 0x5000UL) +#define DLYB_QSPI_BASE (D1_AHB1PERIPH_BASE + 0x6000UL) +#define SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x7000UL) +#define DLYB_SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x8000UL) +#define RAMECC1_BASE (D1_AHB1PERIPH_BASE + 0x9000UL) + +/*!< D2_AHB1PERIPH peripherals */ + +#define DMA1_BASE (D2_AHB1PERIPH_BASE + 0x0000UL) +#define DMA2_BASE (D2_AHB1PERIPH_BASE + 0x0400UL) +#define DMAMUX1_BASE (D2_AHB1PERIPH_BASE + 0x0800UL) +#define ADC1_BASE (D2_AHB1PERIPH_BASE + 0x2000UL) +#define ADC2_BASE (D2_AHB1PERIPH_BASE + 0x2100UL) +#define ADC12_COMMON_BASE (D2_AHB1PERIPH_BASE + 0x2300UL) +#define ETH_BASE (D2_AHB1PERIPH_BASE + 0x8000UL) +#define ETH_MAC_BASE (ETH_BASE) + +/*!< USB registers base address */ +#define USB1_OTG_HS_PERIPH_BASE (0x40040000UL) +#define USB2_OTG_FS_PERIPH_BASE (0x40080000UL) +#define USB_OTG_GLOBAL_BASE (0x000UL) +#define USB_OTG_DEVICE_BASE (0x800UL) +#define USB_OTG_IN_ENDPOINT_BASE (0x900UL) +#define USB_OTG_OUT_ENDPOINT_BASE (0xB00UL) +#define USB_OTG_EP_REG_SIZE (0x20UL) +#define USB_OTG_HOST_BASE (0x400UL) +#define USB_OTG_HOST_PORT_BASE (0x440UL) +#define USB_OTG_HOST_CHANNEL_BASE (0x500UL) +#define USB_OTG_HOST_CHANNEL_SIZE (0x20UL) +#define USB_OTG_PCGCCTL_BASE (0xE00UL) +#define USB_OTG_FIFO_BASE (0x1000UL) +#define USB_OTG_FIFO_SIZE (0x1000UL) + +/*!< D2_AHB2PERIPH peripherals */ + +#define DCMI_BASE (D2_AHB2PERIPH_BASE + 0x0000UL) +#define CRYP_BASE (D2_AHB2PERIPH_BASE + 0x1000UL) +#define HASH_BASE (D2_AHB2PERIPH_BASE + 0x1400UL) +#define HASH_DIGEST_BASE (D2_AHB2PERIPH_BASE + 0x1710UL) +#define RNG_BASE (D2_AHB2PERIPH_BASE + 0x1800UL) +#define SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2400UL) +#define DLYB_SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2800UL) +#define RAMECC2_BASE (D2_AHB2PERIPH_BASE + 0x3000UL) + +/*!< D3_AHB1PERIPH peripherals */ +#define GPIOA_BASE (D3_AHB1PERIPH_BASE + 0x0000UL) +#define GPIOB_BASE (D3_AHB1PERIPH_BASE + 0x0400UL) +#define GPIOC_BASE (D3_AHB1PERIPH_BASE + 0x0800UL) +#define GPIOD_BASE (D3_AHB1PERIPH_BASE + 0x0C00UL) +#define GPIOE_BASE (D3_AHB1PERIPH_BASE + 0x1000UL) +#define GPIOF_BASE (D3_AHB1PERIPH_BASE + 0x1400UL) +#define GPIOG_BASE (D3_AHB1PERIPH_BASE + 0x1800UL) +#define GPIOH_BASE (D3_AHB1PERIPH_BASE + 0x1C00UL) +#define GPIOI_BASE (D3_AHB1PERIPH_BASE + 0x2000UL) +#define GPIOJ_BASE (D3_AHB1PERIPH_BASE + 0x2400UL) +#define GPIOK_BASE (D3_AHB1PERIPH_BASE + 0x2800UL) +#define RCC_BASE (D3_AHB1PERIPH_BASE + 0x4400UL) +#define PWR_BASE (D3_AHB1PERIPH_BASE + 0x4800UL) +#define CRC_BASE (D3_AHB1PERIPH_BASE + 0x4C00UL) +#define BDMA_BASE (D3_AHB1PERIPH_BASE + 0x5400UL) +#define DMAMUX2_BASE (D3_AHB1PERIPH_BASE + 0x5800UL) +#define ADC3_BASE (D3_AHB1PERIPH_BASE + 0x6000UL) +#define ADC3_COMMON_BASE (D3_AHB1PERIPH_BASE + 0x6300UL) +#define HSEM_BASE (D3_AHB1PERIPH_BASE + 0x6400UL) +#define RAMECC3_BASE (D3_AHB1PERIPH_BASE + 0x7000UL) + +/*!< D1_APB1PERIPH peripherals */ +#define LTDC_BASE (D1_APB1PERIPH_BASE + 0x1000UL) +#define LTDC_Layer1_BASE (LTDC_BASE + 0x84UL) +#define LTDC_Layer2_BASE (LTDC_BASE + 0x104UL) +#define WWDG1_BASE (D1_APB1PERIPH_BASE + 0x3000UL) + +/*!< D2_APB1PERIPH peripherals */ +#define TIM2_BASE (D2_APB1PERIPH_BASE + 0x0000UL) +#define TIM3_BASE (D2_APB1PERIPH_BASE + 0x0400UL) +#define TIM4_BASE (D2_APB1PERIPH_BASE + 0x0800UL) +#define TIM5_BASE (D2_APB1PERIPH_BASE + 0x0C00UL) +#define TIM6_BASE (D2_APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (D2_APB1PERIPH_BASE + 0x1400UL) +#define TIM12_BASE (D2_APB1PERIPH_BASE + 0x1800UL) +#define TIM13_BASE (D2_APB1PERIPH_BASE + 0x1C00UL) +#define TIM14_BASE (D2_APB1PERIPH_BASE + 0x2000UL) +#define LPTIM1_BASE (D2_APB1PERIPH_BASE + 0x2400UL) + + +#define SPI2_BASE (D2_APB1PERIPH_BASE + 0x3800UL) +#define SPI3_BASE (D2_APB1PERIPH_BASE + 0x3C00UL) +#define SPDIFRX_BASE (D2_APB1PERIPH_BASE + 0x4000UL) +#define USART2_BASE (D2_APB1PERIPH_BASE + 0x4400UL) +#define USART3_BASE (D2_APB1PERIPH_BASE + 0x4800UL) +#define UART4_BASE (D2_APB1PERIPH_BASE + 0x4C00UL) +#define UART5_BASE (D2_APB1PERIPH_BASE + 0x5000UL) +#define I2C1_BASE (D2_APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (D2_APB1PERIPH_BASE + 0x5800UL) +#define I2C3_BASE (D2_APB1PERIPH_BASE + 0x5C00UL) +#define CEC_BASE (D2_APB1PERIPH_BASE + 0x6C00UL) +#define DAC1_BASE (D2_APB1PERIPH_BASE + 0x7400UL) +#define UART7_BASE (D2_APB1PERIPH_BASE + 0x7800UL) +#define UART8_BASE (D2_APB1PERIPH_BASE + 0x7C00UL) +#define CRS_BASE (D2_APB1PERIPH_BASE + 0x8400UL) +#define SWPMI1_BASE (D2_APB1PERIPH_BASE + 0x8800UL) +#define OPAMP_BASE (D2_APB1PERIPH_BASE + 0x9000UL) +#define OPAMP1_BASE (D2_APB1PERIPH_BASE + 0x9000UL) +#define OPAMP2_BASE (D2_APB1PERIPH_BASE + 0x9010UL) +#define MDIOS_BASE (D2_APB1PERIPH_BASE + 0x9400UL) +#define FDCAN1_BASE (D2_APB1PERIPH_BASE + 0xA000UL) +#define FDCAN2_BASE (D2_APB1PERIPH_BASE + 0xA400UL) +#define FDCAN_CCU_BASE (D2_APB1PERIPH_BASE + 0xA800UL) +#define SRAMCAN_BASE (D2_APB1PERIPH_BASE + 0xAC00UL) + +/*!< D2_APB2PERIPH peripherals */ + +#define TIM1_BASE (D2_APB2PERIPH_BASE + 0x0000UL) +#define TIM8_BASE (D2_APB2PERIPH_BASE + 0x0400UL) +#define USART1_BASE (D2_APB2PERIPH_BASE + 0x1000UL) +#define USART6_BASE (D2_APB2PERIPH_BASE + 0x1400UL) +#define SPI1_BASE (D2_APB2PERIPH_BASE + 0x3000UL) +#define SPI4_BASE (D2_APB2PERIPH_BASE + 0x3400UL) +#define TIM15_BASE (D2_APB2PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (D2_APB2PERIPH_BASE + 0x4400UL) +#define TIM17_BASE (D2_APB2PERIPH_BASE + 0x4800UL) +#define SPI5_BASE (D2_APB2PERIPH_BASE + 0x5000UL) +#define SAI1_BASE (D2_APB2PERIPH_BASE + 0x5800UL) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL) +#define SAI2_BASE (D2_APB2PERIPH_BASE + 0x5C00UL) +#define SAI2_Block_A_BASE (SAI2_BASE + 0x004UL) +#define SAI2_Block_B_BASE (SAI2_BASE + 0x024UL) +#define SAI3_BASE (D2_APB2PERIPH_BASE + 0x6000UL) +#define SAI3_Block_A_BASE (SAI3_BASE + 0x004UL) +#define SAI3_Block_B_BASE (SAI3_BASE + 0x024UL) +#define DFSDM1_BASE (D2_APB2PERIPH_BASE + 0x7000UL) +#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00UL) +#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20UL) +#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40UL) +#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60UL) +#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80UL) +#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0UL) +#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0UL) +#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0UL) +#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100UL) +#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180UL) +#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200UL) +#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280UL) +#define HRTIM1_BASE (D2_APB2PERIPH_BASE + 0x7400UL) +#define HRTIM1_TIMA_BASE (HRTIM1_BASE + 0x00000080UL) +#define HRTIM1_TIMB_BASE (HRTIM1_BASE + 0x00000100UL) +#define HRTIM1_TIMC_BASE (HRTIM1_BASE + 0x00000180UL) +#define HRTIM1_TIMD_BASE (HRTIM1_BASE + 0x00000200UL) +#define HRTIM1_TIME_BASE (HRTIM1_BASE + 0x00000280UL) +#define HRTIM1_COMMON_BASE (HRTIM1_BASE + 0x00000380UL) + + +/*!< D3_APB1PERIPH peripherals */ +#define EXTI_BASE (D3_APB1PERIPH_BASE + 0x0000UL) +#define EXTI_D1_BASE (EXTI_BASE + 0x0080UL) +#define EXTI_D2_BASE (EXTI_BASE + 0x00C0UL) +#define SYSCFG_BASE (D3_APB1PERIPH_BASE + 0x0400UL) +#define LPUART1_BASE (D3_APB1PERIPH_BASE + 0x0C00UL) +#define SPI6_BASE (D3_APB1PERIPH_BASE + 0x1400UL) +#define I2C4_BASE (D3_APB1PERIPH_BASE + 0x1C00UL) +#define LPTIM2_BASE (D3_APB1PERIPH_BASE + 0x2400UL) +#define LPTIM3_BASE (D3_APB1PERIPH_BASE + 0x2800UL) +#define LPTIM4_BASE (D3_APB1PERIPH_BASE + 0x2C00UL) +#define LPTIM5_BASE (D3_APB1PERIPH_BASE + 0x3000UL) +#define COMP12_BASE (D3_APB1PERIPH_BASE + 0x3800UL) +#define COMP1_BASE (COMP12_BASE + 0x0CUL) +#define COMP2_BASE (COMP12_BASE + 0x10UL) +#define VREFBUF_BASE (D3_APB1PERIPH_BASE + 0x3C00UL) +#define RTC_BASE (D3_APB1PERIPH_BASE + 0x4000UL) +#define IWDG1_BASE (D3_APB1PERIPH_BASE + 0x4800UL) + + +#define SAI4_BASE (D3_APB1PERIPH_BASE + 0x5400UL) +#define SAI4_Block_A_BASE (SAI4_BASE + 0x004UL) +#define SAI4_Block_B_BASE (SAI4_BASE + 0x024UL) + + + + +#define BDMA_Channel0_BASE (BDMA_BASE + 0x0008UL) +#define BDMA_Channel1_BASE (BDMA_BASE + 0x001CUL) +#define BDMA_Channel2_BASE (BDMA_BASE + 0x0030UL) +#define BDMA_Channel3_BASE (BDMA_BASE + 0x0044UL) +#define BDMA_Channel4_BASE (BDMA_BASE + 0x0058UL) +#define BDMA_Channel5_BASE (BDMA_BASE + 0x006CUL) +#define BDMA_Channel6_BASE (BDMA_BASE + 0x0080UL) +#define BDMA_Channel7_BASE (BDMA_BASE + 0x0094UL) + +#define DMAMUX2_Channel0_BASE (DMAMUX2_BASE) +#define DMAMUX2_Channel1_BASE (DMAMUX2_BASE + 0x0004UL) +#define DMAMUX2_Channel2_BASE (DMAMUX2_BASE + 0x0008UL) +#define DMAMUX2_Channel3_BASE (DMAMUX2_BASE + 0x000CUL) +#define DMAMUX2_Channel4_BASE (DMAMUX2_BASE + 0x0010UL) +#define DMAMUX2_Channel5_BASE (DMAMUX2_BASE + 0x0014UL) +#define DMAMUX2_Channel6_BASE (DMAMUX2_BASE + 0x0018UL) +#define DMAMUX2_Channel7_BASE (DMAMUX2_BASE + 0x001CUL) + +#define DMAMUX2_RequestGenerator0_BASE (DMAMUX2_BASE + 0x0100UL) +#define DMAMUX2_RequestGenerator1_BASE (DMAMUX2_BASE + 0x0104UL) +#define DMAMUX2_RequestGenerator2_BASE (DMAMUX2_BASE + 0x0108UL) +#define DMAMUX2_RequestGenerator3_BASE (DMAMUX2_BASE + 0x010CUL) +#define DMAMUX2_RequestGenerator4_BASE (DMAMUX2_BASE + 0x0110UL) +#define DMAMUX2_RequestGenerator5_BASE (DMAMUX2_BASE + 0x0114UL) +#define DMAMUX2_RequestGenerator6_BASE (DMAMUX2_BASE + 0x0118UL) +#define DMAMUX2_RequestGenerator7_BASE (DMAMUX2_BASE + 0x011CUL) + +#define DMAMUX2_ChannelStatus_BASE (DMAMUX2_BASE + 0x0080UL) +#define DMAMUX2_RequestGenStatus_BASE (DMAMUX2_BASE + 0x0140UL) + +#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL) +#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL) +#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL) +#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL) +#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL) +#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL) +#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL) +#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL) + +#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL) +#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL) +#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL) +#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL) +#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL) +#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL) +#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL) +#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL) + +#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) +#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL) +#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL) +#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL) +#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL) +#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL) +#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL) +#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL) +#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL) +#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL) +#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL) +#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL) +#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL) +#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL) +#define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL) +#define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL) + +#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL) +#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL) +#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL) +#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL) +#define DMAMUX1_RequestGenerator4_BASE (DMAMUX1_BASE + 0x0110UL) +#define DMAMUX1_RequestGenerator5_BASE (DMAMUX1_BASE + 0x0114UL) +#define DMAMUX1_RequestGenerator6_BASE (DMAMUX1_BASE + 0x0118UL) +#define DMAMUX1_RequestGenerator7_BASE (DMAMUX1_BASE + 0x011CUL) + +#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL) +#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL) + +/*!< FMC Banks registers base address */ +#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL) +#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL) +#define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060UL) +#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL) +#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0x5C001000UL) + +#define MDMA_Channel0_BASE (MDMA_BASE + 0x00000040UL) +#define MDMA_Channel1_BASE (MDMA_BASE + 0x00000080UL) +#define MDMA_Channel2_BASE (MDMA_BASE + 0x000000C0UL) +#define MDMA_Channel3_BASE (MDMA_BASE + 0x00000100UL) +#define MDMA_Channel4_BASE (MDMA_BASE + 0x00000140UL) +#define MDMA_Channel5_BASE (MDMA_BASE + 0x00000180UL) +#define MDMA_Channel6_BASE (MDMA_BASE + 0x000001C0UL) +#define MDMA_Channel7_BASE (MDMA_BASE + 0x00000200UL) +#define MDMA_Channel8_BASE (MDMA_BASE + 0x00000240UL) +#define MDMA_Channel9_BASE (MDMA_BASE + 0x00000280UL) +#define MDMA_Channel10_BASE (MDMA_BASE + 0x000002C0UL) +#define MDMA_Channel11_BASE (MDMA_BASE + 0x00000300UL) +#define MDMA_Channel12_BASE (MDMA_BASE + 0x00000340UL) +#define MDMA_Channel13_BASE (MDMA_BASE + 0x00000380UL) +#define MDMA_Channel14_BASE (MDMA_BASE + 0x000003C0UL) +#define MDMA_Channel15_BASE (MDMA_BASE + 0x00000400UL) + +#define RAMECC1_Monitor1_BASE (RAMECC1_BASE + 0x20UL) +#define RAMECC1_Monitor2_BASE (RAMECC1_BASE + 0x40UL) +#define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x60UL) +#define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0x80UL) +#define RAMECC1_Monitor5_BASE (RAMECC1_BASE + 0xA0UL) + +#define RAMECC2_Monitor1_BASE (RAMECC2_BASE + 0x20UL) +#define RAMECC2_Monitor2_BASE (RAMECC2_BASE + 0x40UL) +#define RAMECC2_Monitor3_BASE (RAMECC2_BASE + 0x60UL) +#define RAMECC2_Monitor4_BASE (RAMECC2_BASE + 0x80UL) +#define RAMECC2_Monitor5_BASE (RAMECC2_BASE + 0xA0UL) + +#define RAMECC3_Monitor1_BASE (RAMECC3_BASE + 0x20UL) +#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL) + + + +#define GPV_BASE (PERIPH_BASE + 0x11000000UL) /*!< GPV_BASE (PERIPH_BASE + 0x11000000UL) */ + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM13 ((TIM_TypeDef *) TIM13_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG1 ((WWDG_TypeDef *) WWDG1_BASE) + + +#define IWDG1 ((IWDG_TypeDef *) IWDG1_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define SPI4 ((SPI_TypeDef *) SPI4_BASE) +#define SPI5 ((SPI_TypeDef *) SPI5_BASE) +#define SPI6 ((SPI_TypeDef *) SPI6_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define USART6 ((USART_TypeDef *) USART6_BASE) +#define UART7 ((USART_TypeDef *) UART7_BASE) +#define UART8 ((USART_TypeDef *) UART8_BASE) +#define CRS ((CRS_TypeDef *) CRS_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define I2C4 ((I2C_TypeDef *) I2C4_BASE) +#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE) +#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE) +#define FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE) +#define CEC ((CEC_TypeDef *) CEC_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC1 ((DAC_TypeDef *) DAC1_BASE) +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE) +#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE) +#define LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE) +#define LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE) +#define LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE) + +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define COMP12 ((COMPOPT_TypeDef *) COMP12_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define COMP2 ((COMP_TypeDef *) COMP2_BASE) +#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE) +#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) +#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE) +#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE) + + +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE) +#define EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE) +#define HRTIM1_TIMA ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMA_BASE) +#define HRTIM1_TIMB ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMB_BASE) +#define HRTIM1_TIMC ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMC_BASE) +#define HRTIM1_TIMD ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMD_BASE) +#define HRTIM1_TIME ((HRTIM_Timerx_TypeDef *) HRTIM1_TIME_BASE) +#define HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE) +#define SAI1 ((SAI_TypeDef *) SAI1_BASE) +#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) +#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) +#define SAI2 ((SAI_TypeDef *) SAI2_BASE) +#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE) +#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE) +#define SAI3 ((SAI_TypeDef *) SAI3_BASE) +#define SAI3_Block_A ((SAI_Block_TypeDef *)SAI3_Block_A_BASE) +#define SAI3_Block_B ((SAI_Block_TypeDef *)SAI3_Block_B_BASE) +#define SAI4 ((SAI_TypeDef *) SAI4_BASE) +#define SAI4_Block_A ((SAI_Block_TypeDef *)SAI4_Block_A_BASE) +#define SAI4_Block_B ((SAI_Block_TypeDef *)SAI4_Block_B_BASE) + +#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE) +#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE) +#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE) +#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE) +#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE) +#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE) +#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE) +#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE) +#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE) +#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE) +#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE) +#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE) +#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE) +#define DMA2D ((DMA2D_TypeDef *) DMA2D_BASE) +#define DCMI ((DCMI_TypeDef *) DCMI_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) + +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) +#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE) +#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE) + +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define ADC3_COMMON ((ADC_Common_TypeDef *) ADC3_COMMON_BASE) +#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE) + +#define CRYP ((CRYP_TypeDef *) CRYP_BASE) +#define HASH ((HASH_TypeDef *) HASH_BASE) +#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE) +#define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE) + +#define BDMA ((BDMA_TypeDef *) BDMA_BASE) +#define BDMA_Channel0 ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE) +#define BDMA_Channel1 ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE) +#define BDMA_Channel2 ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE) +#define BDMA_Channel3 ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE) +#define BDMA_Channel4 ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE) +#define BDMA_Channel5 ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE) +#define BDMA_Channel6 ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE) +#define BDMA_Channel7 ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE) + +#define RAMECC1 ((RAMECC_TypeDef *)RAMECC1_BASE) +#define RAMECC1_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE) +#define RAMECC1_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE) +#define RAMECC1_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE) +#define RAMECC1_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE) +#define RAMECC1_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE) + +#define RAMECC2 ((RAMECC_TypeDef *)RAMECC2_BASE) +#define RAMECC2_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE) +#define RAMECC2_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE) +#define RAMECC2_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE) +#define RAMECC2_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor4_BASE) +#define RAMECC2_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor5_BASE) + +#define RAMECC3 ((RAMECC_TypeDef *)RAMECC3_BASE) +#define RAMECC3_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE) +#define RAMECC3_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE) + +#define DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE) +#define DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE) +#define DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE) +#define DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE) +#define DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE) +#define DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE) +#define DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE) +#define DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE) +#define DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE) + + +#define DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE) +#define DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE) +#define DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE) +#define DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE) +#define DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE) +#define DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE) +#define DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE) +#define DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE) + +#define DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE) +#define DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE) + +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) +#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) +#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) +#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) +#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) +#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) +#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) +#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) + +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) +#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) +#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) +#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) +#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) +#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) +#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) +#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) + + +#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) +#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) +#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) +#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) +#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) +#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) +#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) +#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) +#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE) +#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE) +#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE) +#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE) +#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE) +#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE) +#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE) +#define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE) +#define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE) + +#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) +#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) +#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) +#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) +#define DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE) +#define DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE) +#define DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE) +#define DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE) + +#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) +#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) + + +#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) +#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) +#define FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE) +#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) +#define FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE) + + +#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE) +#define DLYB_QUADSPI ((DLYB_TypeDef *) DLYB_QSPI_BASE) +#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE) +#define DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +#define JPEG ((JPEG_TypeDef *) JPGDEC_BASE) +#define HSEM ((HSEM_TypeDef *) HSEM_BASE) +#define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL)) + +#define LTDC ((LTDC_TypeDef *)LTDC_BASE) +#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) +#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE) + +#define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE) + +#define ETH ((ETH_TypeDef *)ETH_BASE) +#define MDMA ((MDMA_TypeDef *)MDMA_BASE) +#define MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE) +#define MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE) +#define MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE) +#define MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE) +#define MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE) +#define MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE) +#define MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE) +#define MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE) +#define MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE) +#define MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE) +#define MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE) +#define MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE) +#define MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE) +#define MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE) +#define MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE) +#define MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE) + + +#define USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE) +#define USB2_OTG_FS ((USB_OTG_GlobalTypeDef *) USB2_OTG_FS_PERIPH_BASE) + +/* Legacy defines */ +#define USB_OTG_HS USB1_OTG_HS +#define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE +#define USB_OTG_FS USB2_OTG_FS +#define USB_OTG_FS_PERIPH_BASE USB2_OTG_FS_PERIPH_BASE + +#define GPV ((GPV_TypeDef *) GPV_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************************* ADC VERSION ********************************/ +#define ADC_VER_V5_X +/******************** Bit definition for ADC_ISR register ********************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */ + +/******************** Bit definition for ADC_IER register ********************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready (ADRDY) interrupt source */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC End of Sampling interrupt source */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC End of Regular Conversion interrupt source */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC overrun interrupt source */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC End of Injected Conversion interrupt source */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC Analog watchdog 1 interrupt source */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC Analog watchdog 2 interrupt source */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC Analog watchdog 3 interrupt source */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC Injected Context Queue Overflow interrupt source */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */ +#define ADC_CR_BOOST_Pos (8U) +#define ADC_CR_BOOST_Msk (0x3UL << ADC_CR_BOOST_Pos) /*!< 0x00000300 */ +#define ADC_CR_BOOST ADC_CR_BOOST_Msk /*!< ADC Boost Mode configuration */ +#define ADC_CR_BOOST_0 (0x1UL << ADC_CR_BOOST_Pos) /*!< 0x00000100 */ +#define ADC_CR_BOOST_1 (0x2UL << ADC_CR_BOOST_Pos) /*!< 0x00000200 */ +#define ADC_CR_ADCALLIN_Pos (16U) +#define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */ +#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */ +#define ADC_CR_LINCALRDYW1_Pos (22U) +#define ADC_CR_LINCALRDYW1_Msk (0x1UL << ADC_CR_LINCALRDYW1_Pos) /*!< 0x00400000 */ +#define ADC_CR_LINCALRDYW1 ADC_CR_LINCALRDYW1_Msk /*!< ADC Linearity calibration ready Word 1 */ +#define ADC_CR_LINCALRDYW2_Pos (23U) +#define ADC_CR_LINCALRDYW2_Msk (0x1UL << ADC_CR_LINCALRDYW2_Pos) /*!< 0x00800000 */ +#define ADC_CR_LINCALRDYW2 ADC_CR_LINCALRDYW2_Msk /*!< ADC Linearity calibration ready Word 2 */ +#define ADC_CR_LINCALRDYW3_Pos (24U) +#define ADC_CR_LINCALRDYW3_Msk (0x1UL << ADC_CR_LINCALRDYW3_Pos) /*!< 0x01000000 */ +#define ADC_CR_LINCALRDYW3 ADC_CR_LINCALRDYW3_Msk /*!< ADC Linearity calibration ready Word 3 */ +#define ADC_CR_LINCALRDYW4_Pos (25U) +#define ADC_CR_LINCALRDYW4_Msk (0x1UL << ADC_CR_LINCALRDYW4_Pos) /*!< 0x02000000 */ +#define ADC_CR_LINCALRDYW4 ADC_CR_LINCALRDYW4_Msk /*!< ADC Linearity calibration ready Word 4 */ +#define ADC_CR_LINCALRDYW5_Pos (26U) +#define ADC_CR_LINCALRDYW5_Msk (0x1UL << ADC_CR_LINCALRDYW5_Pos) /*!< 0x04000000 */ +#define ADC_CR_LINCALRDYW5 ADC_CR_LINCALRDYW5_Msk /*!< ADC Linearity calibration ready Word 5 */ +#define ADC_CR_LINCALRDYW6_Pos (27U) +#define ADC_CR_LINCALRDYW6_Msk (0x1UL << ADC_CR_LINCALRDYW6_Pos) /*!< 0x08000000 */ +#define ADC_CR_LINCALRDYW6 ADC_CR_LINCALRDYW6_Msk /*!< ADC Linearity calibration ready Word 6 */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC Differential Mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */ + +/******************** Bit definition for ADC_CFGR register ********************/ +#define ADC_CFGR_DMNGT_Pos (0U) +#define ADC_CFGR_DMNGT_Msk (0x3UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000003 */ +#define ADC_CFGR_DMNGT ADC_CFGR_DMNGT_Msk /*!< ADC Data Management configuration */ +#define ADC_CFGR_DMNGT_0 (0x1UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMNGT_1 (0x2UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000002 */ + +#define ADC_CFGR_RES_Pos (2U) +#define ADC_CFGR_RES_Msk (0x7UL << ADC_CFGR_RES_Pos) /*!< 0x0000001C */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC Data resolution */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_2 (0x4UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_EXTSEL_Pos (5U) +#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ +#define ADC_CFGR_EXTSEL_0 (0x01UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_EXTSEL_1 (0x02UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_2 (0x04UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_3 (0x08UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC overrun mode */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC Delayed conversion mode */ + +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC JSQR Queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC Automatic injected group conversion */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC Injected queue disable */ + +/******************** Bit definition for ADC_CFGR2 register ********************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ + +#define ADC_CFGR2_RSHIFT1_Pos (11U) +#define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */ +#define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */ +#define ADC_CFGR2_RSHIFT2_Pos (12U) +#define ADC_CFGR2_RSHIFT2_Msk (0x1UL << ADC_CFGR2_RSHIFT2_Pos) /*!< 0x00001000 */ +#define ADC_CFGR2_RSHIFT2 ADC_CFGR2_RSHIFT2_Msk /*!< ADC Right-shift data after Offset 2 correction */ +#define ADC_CFGR2_RSHIFT3_Pos (13U) +#define ADC_CFGR2_RSHIFT3_Msk (0x1UL << ADC_CFGR2_RSHIFT3_Pos) /*!< 0x00002000 */ +#define ADC_CFGR2_RSHIFT3 ADC_CFGR2_RSHIFT3_Msk /*!< ADC Right-shift data after Offset 3 correction */ +#define ADC_CFGR2_RSHIFT4_Pos (14U) +#define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */ +#define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */ + +#define ADC_CFGR2_OVSR_Pos (16U) +#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ + +#define ADC_CFGR2_LSHIFT_Pos (28U) +#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ +#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */ +#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ +#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_SMPR1 register ********************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_SMPR2 register ********************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR2_SMP19_Pos (27U) +#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ +#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */ +#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ +#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ +#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_PCSEL register ********************/ +#define ADC_PCSEL_PCSEL_Pos (0U) +#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */ +#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ +#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ +#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ +#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ +#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ +#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ +#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ +#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ +#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ +#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ +#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ +#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ +#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ +#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ +#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */ +#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */ +#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */ +#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */ +#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */ +#define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/ +#define ADC_LTR_LT_Pos (0U) +#define ADC_LTR_LT_Msk (0x3FFFFFFUL << ADC_LTR_LT_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */ + +/***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/ +#define ADC_HTR_HT_Pos (0U) +#define ADC_HTR_HT_Msk (0x3FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */ + + +/******************** Bit definition for ADC_SQR1 register ********************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ********************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ********************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ********************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ + +/******************** Bit definition for ADC_JSQR register ********************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */ +#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ + +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ********************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */ +#define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ +#define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */ +#define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */ +#define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */ +#define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */ +#define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */ +#define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */ +#define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */ +#define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */ +#define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */ +#define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */ +#define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */ +#define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */ +#define ADC_OFR1_OFFSET1_24 (0x1000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSET1_25 (0x2000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_SSATE_Pos (31U) +#define ADC_OFR1_SSATE_Msk (0x1UL << ADC_OFR1_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_SSATE ADC_OFR1_SSATE_Msk /*!< ADC Signed saturation Enable */ + + +/******************** Bit definition for ADC_OFR2 register ********************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */ +#define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ +#define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */ +#define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */ +#define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */ +#define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */ +#define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */ +#define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */ +#define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */ +#define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */ +#define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */ +#define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */ +#define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */ +#define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */ +#define ADC_OFR2_OFFSET2_24 (0x1000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSET2_25 (0x2000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_SSATE_Pos (31U) +#define ADC_OFR2_SSATE_Msk (0x1UL << ADC_OFR2_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_SSATE ADC_OFR2_SSATE_Msk /*!< ADC Signed saturation Enable */ + + +/******************** Bit definition for ADC_OFR3 register ********************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */ +#define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ +#define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */ +#define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */ +#define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */ +#define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */ +#define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */ +#define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */ +#define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */ +#define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */ +#define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */ +#define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */ +#define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */ +#define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */ +#define ADC_OFR3_OFFSET3_24 (0x1000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSET3_25 (0x2000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_SSATE_Pos (31U) +#define ADC_OFR3_SSATE_Msk (0x1UL << ADC_OFR3_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_SSATE ADC_OFR3_SSATE_Msk /*!< ADC Signed saturation Enable */ + + +/******************** Bit definition for ADC_OFR4 register ********************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */ +#define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ +#define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */ +#define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */ +#define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */ +#define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */ +#define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */ +#define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */ +#define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */ +#define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */ +#define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */ +#define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */ +#define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */ +#define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */ +#define ADC_OFR4_OFFSET4_24 (0x1000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSET4_25 (0x2000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_SSATE_Pos (31U) +#define ADC_OFR4_SSATE_Msk (0x1UL << ADC_OFR4_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_SSATE ADC_OFR4_SSATE_Msk /*!< ADC Signed saturation Enable */ + + +/******************** Bit definition for ADC_JDR1 register ********************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR2 register ********************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR3 register ********************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR4 register ********************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD2CR register ********************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x000FFFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_AWD3CR register ********************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_DIFSEL register ********************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_CALFACT register ********************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factors in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x001UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x002UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x004UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x008UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x010UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x020UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x040UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT_CALFACT_S_7 (0x080UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */ +#define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x001UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x002UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x004UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x008UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x010UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x020UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x040UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT_CALFACT_D_7 (0x080UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */ +#define ADC_CALFACT_CALFACT_D_8 (0x100UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_CALFACT_D_9 (0x200UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */ +#define ADC_CALFACT_CALFACT_D_10 (0x400UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */ + +/******************** Bit definition for ADC_CALFACT2 register ********************/ +#define ADC_CALFACT2_LINCALFACT_Pos (0U) +#define ADC_CALFACT2_LINCALFACT_Msk (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */ +#define ADC_CALFACT2_LINCALFACT ADC_CALFACT2_LINCALFACT_Msk /*!< ADC Linearity calibration factors */ +#define ADC_CALFACT2_LINCALFACT_0 (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT2_LINCALFACT_1 (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT2_LINCALFACT_2 (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT2_LINCALFACT_3 (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT2_LINCALFACT_4 (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT2_LINCALFACT_5 (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT2_LINCALFACT_6 (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT2_LINCALFACT_7 (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */ +#define ADC_CALFACT2_LINCALFACT_8 (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT2_LINCALFACT_9 (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT2_LINCALFACT_10 (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT2_LINCALFACT_11 (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */ +#define ADC_CALFACT2_LINCALFACT_12 (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */ +#define ADC_CALFACT2_LINCALFACT_13 (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */ +#define ADC_CALFACT2_LINCALFACT_14 (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */ +#define ADC_CALFACT2_LINCALFACT_15 (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */ +#define ADC_CALFACT2_LINCALFACT_16 (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT2_LINCALFACT_17 (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT2_LINCALFACT_18 (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT2_LINCALFACT_19 (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT2_LINCALFACT_20 (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT2_LINCALFACT_21 (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT2_LINCALFACT_22 (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT2_LINCALFACT_23 (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */ +#define ADC_CALFACT2_LINCALFACT_24 (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT2_LINCALFACT_25 (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */ +#define ADC_CALFACT2_LINCALFACT_26 (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */ +#define ADC_CALFACT2_LINCALFACT_27 (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000000 */ +#define ADC_CALFACT2_LINCALFACT_28 (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */ +#define ADC_CALFACT2_LINCALFACT_29 (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register ********************/ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ + +/******************** Bit definition for ADC_CCR register ********************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< Dual ADC mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + + +#define ADC_CCR_DAMDF_Pos (14U) +#define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< Dual ADC mode Data format */ +#define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */ +#define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC clock mode */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + +/******************** Bit definition for ADC_CDR2 register ******************/ +#define ADC_CDR2_RDATA_ALT_Pos (0U) +#define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< Regular data of the master/slave alternated ADCs */ + + +/******************************************************************************/ +/* */ +/* VREFBUF */ +/* */ +/******************************************************************************/ +/******************* Bit definition for VREFBUF_CSR register ****************/ +#define VREFBUF_CSR_ENVR_Pos (0U) +#define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */ +#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!> 1) /* 1 MB */ +#define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */ +#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */ +#define FLASH_NB_32BITWORD_IN_FLASHWORD 8U /* 256 bits */ +#define DUAL_BANK /* Dual-bank Flash */ + +/******************* Bits definition for FLASH_ACR register **********************/ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F: bit4 is kept only for legacy purpose */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */ +#define FLASH_ACR_LATENCY_0WS (0x00000000UL) +#define FLASH_ACR_LATENCY_1WS (0x00000001UL) +#define FLASH_ACR_LATENCY_2WS (0x00000002UL) +#define FLASH_ACR_LATENCY_3WS (0x00000003UL) +#define FLASH_ACR_LATENCY_4WS (0x00000004UL) +#define FLASH_ACR_LATENCY_5WS (0x00000005UL) +#define FLASH_ACR_LATENCY_6WS (0x00000006UL) +#define FLASH_ACR_LATENCY_7WS (0x00000007UL) + +#define FLASH_ACR_WRHIGHFREQ_Pos (4U) +#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ +#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ +#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ +#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ + +/* Legacy FLASH Latency defines */ +#define FLASH_ACR_LATENCY_8WS (0x00000008UL) +#define FLASH_ACR_LATENCY_9WS (0x00000009UL) +#define FLASH_ACR_LATENCY_10WS (0x0000000AUL) +#define FLASH_ACR_LATENCY_11WS (0x0000000BUL) +#define FLASH_ACR_LATENCY_12WS (0x0000000CUL) +#define FLASH_ACR_LATENCY_13WS (0x0000000DUL) +#define FLASH_ACR_LATENCY_14WS (0x0000000EUL) +#define FLASH_ACR_LATENCY_15WS (0x0000000FUL) +/******************* Bits definition for FLASH_CR register ***********************/ +#define FLASH_CR_LOCK_Pos (0U) +#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Configuration lock bit */ +#define FLASH_CR_PG_Pos (1U) +#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000002 */ +#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Internal buffer control bit */ +#define FLASH_CR_SER_Pos (2U) +#define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos) /*!< 0x00000004 */ +#define FLASH_CR_SER FLASH_CR_SER_Msk /*!< Sector erase request */ +#define FLASH_CR_BER_Pos (3U) +#define FLASH_CR_BER_Msk (0x1UL << FLASH_CR_BER_Pos) /*!< 0x00000008 */ +#define FLASH_CR_BER FLASH_CR_BER_Msk /*!< Bank erase request */ +#define FLASH_CR_PSIZE_Pos (4U) +#define FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000030 */ +#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk /*!< Program size */ +#define FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000010 */ +#define FLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000020 */ +#define FLASH_CR_FW_Pos (6U) +#define FLASH_CR_FW_Msk (0x1UL << FLASH_CR_FW_Pos) /*!< 0x00000040 */ +#define FLASH_CR_FW FLASH_CR_FW_Msk /*!< Write forcing control bit */ +#define FLASH_CR_START_Pos (7U) +#define FLASH_CR_START_Msk (0x1UL << FLASH_CR_START_Pos) /*!< 0x00000080 */ +#define FLASH_CR_START FLASH_CR_START_Msk /*!< Erase start control bit */ +#define FLASH_CR_SNB_Pos (8U) +#define FLASH_CR_SNB_Msk (0x7UL << FLASH_CR_SNB_Pos) /*!< 0x00000700 */ +#define FLASH_CR_SNB FLASH_CR_SNB_Msk /*!< Sector erase selection number */ +#define FLASH_CR_SNB_0 (0x1UL << FLASH_CR_SNB_Pos) /*!< 0x00000100 */ +#define FLASH_CR_SNB_1 (0x2UL << FLASH_CR_SNB_Pos) /*!< 0x00000200 */ +#define FLASH_CR_SNB_2 (0x4UL << FLASH_CR_SNB_Pos) /*!< 0x00000400 */ +#define FLASH_CR_CRC_EN_Pos (15U) +#define FLASH_CR_CRC_EN_Msk (0x1UL << FLASH_CR_CRC_EN_Pos) /*!< 0x00008000 */ +#define FLASH_CR_CRC_EN FLASH_CR_CRC_EN_Msk /*!< CRC control bit */ +#define FLASH_CR_EOPIE_Pos (16U) +#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x00010000 */ +#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End-of-program interrupt control bit */ +#define FLASH_CR_WRPERRIE_Pos (17U) +#define FLASH_CR_WRPERRIE_Msk (0x1UL << FLASH_CR_WRPERRIE_Pos) /*!< 0x00020000 */ +#define FLASH_CR_WRPERRIE FLASH_CR_WRPERRIE_Msk /*!< Write protection error interrupt enable bit */ +#define FLASH_CR_PGSERRIE_Pos (18U) +#define FLASH_CR_PGSERRIE_Msk (0x1UL << FLASH_CR_PGSERRIE_Pos) /*!< 0x00040000 */ +#define FLASH_CR_PGSERRIE FLASH_CR_PGSERRIE_Msk /*!< Programming sequence error interrupt enable bit */ +#define FLASH_CR_STRBERRIE_Pos (19U) +#define FLASH_CR_STRBERRIE_Msk (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */ +#define FLASH_CR_STRBERRIE FLASH_CR_STRBERRIE_Msk /*!< Strobe error interrupt enable bit */ +#define FLASH_CR_INCERRIE_Pos (21U) +#define FLASH_CR_INCERRIE_Msk (0x1UL << FLASH_CR_INCERRIE_Pos) /*!< 0x00200000 */ +#define FLASH_CR_INCERRIE FLASH_CR_INCERRIE_Msk /*!< Inconsistency error interrupt enable bit */ +#define FLASH_CR_OPERRIE_Pos (22U) +#define FLASH_CR_OPERRIE_Msk (0x1UL << FLASH_CR_OPERRIE_Pos) /*!< 0x00400000 */ +#define FLASH_CR_OPERRIE FLASH_CR_OPERRIE_Msk /*!< Write/erase error interrupt enable bit */ +#define FLASH_CR_RDPERRIE_Pos (23U) +#define FLASH_CR_RDPERRIE_Msk (0x1UL << FLASH_CR_RDPERRIE_Pos) /*!< 0x00800000 */ +#define FLASH_CR_RDPERRIE FLASH_CR_RDPERRIE_Msk /*!< Read protection error interrupt enable bit */ +#define FLASH_CR_RDSERRIE_Pos (24U) +#define FLASH_CR_RDSERRIE_Msk (0x1UL << FLASH_CR_RDSERRIE_Pos) /*!< 0x01000000 */ +#define FLASH_CR_RDSERRIE FLASH_CR_RDSERRIE_Msk /*!< Secure error interrupt enable bit */ +#define FLASH_CR_SNECCERRIE_Pos (25U) +#define FLASH_CR_SNECCERRIE_Msk (0x1UL << FLASH_CR_SNECCERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_CR_SNECCERRIE FLASH_CR_SNECCERRIE_Msk /*!< ECC single correction error interrupt enable bit */ +#define FLASH_CR_DBECCERRIE_Pos (26U) +#define FLASH_CR_DBECCERRIE_Msk (0x1UL << FLASH_CR_DBECCERRIE_Pos) /*!< 0x04000000 */ +#define FLASH_CR_DBECCERRIE FLASH_CR_DBECCERRIE_Msk /*!< ECC double detection error interrupt enable bit */ +#define FLASH_CR_CRCENDIE_Pos (27U) +#define FLASH_CR_CRCENDIE_Msk (0x1UL << FLASH_CR_CRCENDIE_Pos) /*!< 0x08000000 */ +#define FLASH_CR_CRCENDIE FLASH_CR_CRCENDIE_Msk /*!< CRC end of calculation interrupt enable bit */ +#define FLASH_CR_CRCRDERRIE_Pos (28U) +#define FLASH_CR_CRCRDERRIE_Msk (0x1UL << FLASH_CR_CRCRDERRIE_Pos) /*!< 0x10000000 */ +#define FLASH_CR_CRCRDERRIE FLASH_CR_CRCRDERRIE_Msk /*!< CRC read error interrupt enable bit */ + +/******************* Bits definition for FLASH_SR register ***********************/ +#define FLASH_SR_BSY_Pos (0U) +#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ +#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy flag */ +#define FLASH_SR_WBNE_Pos (1U) +#define FLASH_SR_WBNE_Msk (0x1UL << FLASH_SR_WBNE_Pos) /*!< 0x00000002 */ +#define FLASH_SR_WBNE FLASH_SR_WBNE_Msk /*!< Write buffer not empty flag */ +#define FLASH_SR_QW_Pos (2U) +#define FLASH_SR_QW_Msk (0x1UL << FLASH_SR_QW_Pos) /*!< 0x00000004 */ +#define FLASH_SR_QW FLASH_SR_QW_Msk /*!< Wait queue flag */ +#define FLASH_SR_CRC_BUSY_Pos (3U) +#define FLASH_SR_CRC_BUSY_Msk (0x1UL << FLASH_SR_CRC_BUSY_Pos) /*!< 0x00000008 */ +#define FLASH_SR_CRC_BUSY FLASH_SR_CRC_BUSY_Msk /*!< CRC busy flag */ +#define FLASH_SR_EOP_Pos (16U) +#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00010000 */ +#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End-of-program flag */ +#define FLASH_SR_WRPERR_Pos (17U) +#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00020000 */ +#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error flag */ +#define FLASH_SR_PGSERR_Pos (18U) +#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00040000 */ +#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk /*!< Programming sequence error flag */ +#define FLASH_SR_STRBERR_Pos (19U) +#define FLASH_SR_STRBERR_Msk (0x1UL << FLASH_SR_STRBERR_Pos) /*!< 0x00080000 */ +#define FLASH_SR_STRBERR FLASH_SR_STRBERR_Msk /*!< Strobe error flag */ +#define FLASH_SR_INCERR_Pos (21U) +#define FLASH_SR_INCERR_Msk (0x1UL << FLASH_SR_INCERR_Pos) /*!< 0x00200000 */ +#define FLASH_SR_INCERR FLASH_SR_INCERR_Msk /*!< Inconsistency error flag */ +#define FLASH_SR_OPERR_Pos (22U) +#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00400000 */ +#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk /*!< Write/erase error flag */ +#define FLASH_SR_RDPERR_Pos (23U) +#define FLASH_SR_RDPERR_Msk (0x1UL << FLASH_SR_RDPERR_Pos) /*!< 0x00800000 */ +#define FLASH_SR_RDPERR FLASH_SR_RDPERR_Msk /*!< Read protection error flag */ +#define FLASH_SR_RDSERR_Pos (24U) +#define FLASH_SR_RDSERR_Msk (0x1UL << FLASH_SR_RDSERR_Pos) /*!< 0x01000000 */ +#define FLASH_SR_RDSERR FLASH_SR_RDSERR_Msk /*!< Secure error flag */ +#define FLASH_SR_SNECCERR_Pos (25U) +#define FLASH_SR_SNECCERR_Msk (0x1UL << FLASH_SR_SNECCERR_Pos) /*!< 0x02000000 */ +#define FLASH_SR_SNECCERR FLASH_SR_SNECCERR_Msk /*!< Single correction error flag */ +#define FLASH_SR_DBECCERR_Pos (26U) +#define FLASH_SR_DBECCERR_Msk (0x1UL << FLASH_SR_DBECCERR_Pos) /*!< 0x04000000 */ +#define FLASH_SR_DBECCERR FLASH_SR_DBECCERR_Msk /*!< ECC double detection error flag */ +#define FLASH_SR_CRCEND_Pos (27U) +#define FLASH_SR_CRCEND_Msk (0x1UL << FLASH_SR_CRCEND_Pos) /*!< 0x08000000 */ +#define FLASH_SR_CRCEND FLASH_SR_CRCEND_Msk /*!< CRC end of calculation flag */ +#define FLASH_SR_CRCRDERR_Pos (28U) +#define FLASH_SR_CRCRDERR_Msk (0x1UL << FLASH_SR_CRCRDERR_Pos) /*!< 0x10000000 */ +#define FLASH_SR_CRCRDERR FLASH_SR_CRCRDERR_Msk /*!< CRC read error flag */ + +/******************* Bits definition for FLASH_CCR register *******************/ +#define FLASH_CCR_CLR_EOP_Pos (16U) +#define FLASH_CCR_CLR_EOP_Msk (0x1UL << FLASH_CCR_CLR_EOP_Pos) /*!< 0x00010000 */ +#define FLASH_CCR_CLR_EOP FLASH_CCR_CLR_EOP_Msk /*!< EOP flag clear bit */ +#define FLASH_CCR_CLR_WRPERR_Pos (17U) +#define FLASH_CCR_CLR_WRPERR_Msk (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */ +#define FLASH_CCR_CLR_WRPERR FLASH_CCR_CLR_WRPERR_Msk /*!< WRPERR flag clear bit */ +#define FLASH_CCR_CLR_PGSERR_Pos (18U) +#define FLASH_CCR_CLR_PGSERR_Msk (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */ +#define FLASH_CCR_CLR_PGSERR FLASH_CCR_CLR_PGSERR_Msk /*!< PGSERR flag clear bit */ +#define FLASH_CCR_CLR_STRBERR_Pos (19U) +#define FLASH_CCR_CLR_STRBERR_Msk (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */ +#define FLASH_CCR_CLR_STRBERR FLASH_CCR_CLR_STRBERR_Msk /*!< STRBERR flag clear bit */ +#define FLASH_CCR_CLR_INCERR_Pos (21U) +#define FLASH_CCR_CLR_INCERR_Msk (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00200000 */ +#define FLASH_CCR_CLR_INCERR FLASH_CCR_CLR_INCERR_Msk /*!< INCERR flag clear bit */ +#define FLASH_CCR_CLR_OPERR_Pos (22U) +#define FLASH_CCR_CLR_OPERR_Msk (0x1UL << FLASH_CCR_CLR_OPERR_Pos) /*!< 0x00400000 */ +#define FLASH_CCR_CLR_OPERR FLASH_CCR_CLR_OPERR_Msk /*!< OPERR flag clear bit */ +#define FLASH_CCR_CLR_RDPERR_Pos (23U) +#define FLASH_CCR_CLR_RDPERR_Msk (0x1UL << FLASH_CCR_CLR_RDPERR_Pos) /*!< 0x00800000 */ +#define FLASH_CCR_CLR_RDPERR FLASH_CCR_CLR_RDPERR_Msk /*!< RDPERR flag clear bit */ +#define FLASH_CCR_CLR_RDSERR_Pos (24U) +#define FLASH_CCR_CLR_RDSERR_Msk (0x1UL << FLASH_CCR_CLR_RDSERR_Pos) /*!< 0x01000000 */ +#define FLASH_CCR_CLR_RDSERR FLASH_CCR_CLR_RDSERR_Msk /*!< RDSERR flag clear bit */ +#define FLASH_CCR_CLR_SNECCERR_Pos (25U) +#define FLASH_CCR_CLR_SNECCERR_Msk (0x1UL << FLASH_CCR_CLR_SNECCERR_Pos) /*!< 0x02000000 */ +#define FLASH_CCR_CLR_SNECCERR FLASH_CCR_CLR_SNECCERR_Msk /*!< SNECCERR flag clear bit */ +#define FLASH_CCR_CLR_DBECCERR_Pos (26U) +#define FLASH_CCR_CLR_DBECCERR_Msk (0x1UL << FLASH_CCR_CLR_DBECCERR_Pos) /*!< 0x04000000 */ +#define FLASH_CCR_CLR_DBECCERR FLASH_CCR_CLR_DBECCERR_Msk /*!< DBECCERR flag clear bit */ +#define FLASH_CCR_CLR_CRCEND_Pos (27U) +#define FLASH_CCR_CLR_CRCEND_Msk (0x1UL << FLASH_CCR_CLR_CRCEND_Pos) /*!< 0x08000000 */ +#define FLASH_CCR_CLR_CRCEND FLASH_CCR_CLR_CRCEND_Msk /*!< CRCEND flag clear bit */ +#define FLASH_CCR_CLR_CRCRDERR_Pos (28U) +#define FLASH_CCR_CLR_CRCRDERR_Msk (0x1UL << FLASH_CCR_CLR_CRCRDERR_Pos) /*!< 0x10000000 */ +#define FLASH_CCR_CLR_CRCRDERR FLASH_CCR_CLR_CRCRDERR_Msk /*!< CRCRDERR flag clear bit */ + +/******************* Bits definition for FLASH_OPTCR register *******************/ +#define FLASH_OPTCR_OPTLOCK_Pos (0U) +#define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */ +#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk /*!< FLASH_OPTCR lock option configuration bit */ +#define FLASH_OPTCR_OPTSTART_Pos (1U) +#define FLASH_OPTCR_OPTSTART_Msk (0x1UL << FLASH_OPTCR_OPTSTART_Pos) /*!< 0x00000002 */ +#define FLASH_OPTCR_OPTSTART FLASH_OPTCR_OPTSTART_Msk /*!< Option byte start change option configuration bit */ +#define FLASH_OPTCR_MER_Pos (4U) +#define FLASH_OPTCR_MER_Msk (0x1UL << FLASH_OPTCR_MER_Pos) /*!< 0x00000010 */ +#define FLASH_OPTCR_MER FLASH_OPTCR_MER_Msk /*!< Mass erase request */ +#define FLASH_OPTCR_OPTCHANGEERRIE_Pos (30U) +#define FLASH_OPTCR_OPTCHANGEERRIE_Msk (0x1UL << FLASH_OPTCR_OPTCHANGEERRIE_Pos) /*!< 0x40000000 */ +#define FLASH_OPTCR_OPTCHANGEERRIE FLASH_OPTCR_OPTCHANGEERRIE_Msk /*!< Option byte change error interrupt enable bit */ +#define FLASH_OPTCR_SWAP_BANK_Pos (31U) +#define FLASH_OPTCR_SWAP_BANK_Msk (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */ +#define FLASH_OPTCR_SWAP_BANK FLASH_OPTCR_SWAP_BANK_Msk /*!< Bank swapping option configuration bit */ + +/******************* Bits definition for FLASH_OPTSR register ***************/ +#define FLASH_OPTSR_OPT_BUSY_Pos (0U) +#define FLASH_OPTSR_OPT_BUSY_Msk (0x1UL << FLASH_OPTSR_OPT_BUSY_Pos) /*!< 0x00000001 */ +#define FLASH_OPTSR_OPT_BUSY FLASH_OPTSR_OPT_BUSY_Msk /*!< Option byte change ongoing flag */ +#define FLASH_OPTSR_BOR_LEV_Pos (2U) +#define FLASH_OPTSR_BOR_LEV_Msk (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x0000000C */ +#define FLASH_OPTSR_BOR_LEV FLASH_OPTSR_BOR_LEV_Msk /*!< Brownout level option status bit */ +#define FLASH_OPTSR_BOR_LEV_0 (0x1UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000004 */ +#define FLASH_OPTSR_BOR_LEV_1 (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000008 */ +#define FLASH_OPTSR_IWDG1_SW_Pos (4U) +#define FLASH_OPTSR_IWDG1_SW_Msk (0x1UL << FLASH_OPTSR_IWDG1_SW_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR_IWDG1_SW FLASH_OPTSR_IWDG1_SW_Msk /*!< IWDG1 control mode option status bit */ +#define FLASH_OPTSR_NRST_STOP_D1_Pos (6U) +#define FLASH_OPTSR_NRST_STOP_D1_Msk (0x1UL << FLASH_OPTSR_NRST_STOP_D1_Pos) /*!< 0x00000040 */ +#define FLASH_OPTSR_NRST_STOP_D1 FLASH_OPTSR_NRST_STOP_D1_Msk /*!< D1 domain DStop entry reset option status bit */ +#define FLASH_OPTSR_NRST_STBY_D1_Pos (7U) +#define FLASH_OPTSR_NRST_STBY_D1_Msk (0x1UL << FLASH_OPTSR_NRST_STBY_D1_Pos) /*!< 0x00000080 */ +#define FLASH_OPTSR_NRST_STBY_D1 FLASH_OPTSR_NRST_STBY_D1_Msk /*!< D1 domain DStandby entry reset option status bit */ +#define FLASH_OPTSR_RDP_Pos (8U) +#define FLASH_OPTSR_RDP_Msk (0xFFUL << FLASH_OPTSR_RDP_Pos) /*!< 0x0000FF00 */ +#define FLASH_OPTSR_RDP FLASH_OPTSR_RDP_Msk /*!< Readout protection level option status byte */ +#define FLASH_OPTSR_FZ_IWDG_STOP_Pos (17U) +#define FLASH_OPTSR_FZ_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_FZ_IWDG_STOP_Pos) /*!< 0x00020000 */ +#define FLASH_OPTSR_FZ_IWDG_STOP FLASH_OPTSR_FZ_IWDG_STOP_Msk /*!< IWDG Stop mode freeze option status bit */ +#define FLASH_OPTSR_FZ_IWDG_SDBY_Pos (18U) +#define FLASH_OPTSR_FZ_IWDG_SDBY_Msk (0x1UL << FLASH_OPTSR_FZ_IWDG_SDBY_Pos) /*!< 0x00040000 */ +#define FLASH_OPTSR_FZ_IWDG_SDBY FLASH_OPTSR_FZ_IWDG_SDBY_Msk /*!< IWDG Standby mode freeze option status bit */ +#define FLASH_OPTSR_ST_RAM_SIZE_Pos (19U) +#define FLASH_OPTSR_ST_RAM_SIZE_Msk (0x3UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00180000 */ +#define FLASH_OPTSR_ST_RAM_SIZE FLASH_OPTSR_ST_RAM_SIZE_Msk /*!< ST RAM size option status */ +#define FLASH_OPTSR_ST_RAM_SIZE_0 (0x1UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00080000 */ +#define FLASH_OPTSR_ST_RAM_SIZE_1 (0x2UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00100000 */ +#define FLASH_OPTSR_SECURITY_Pos (21U) +#define FLASH_OPTSR_SECURITY_Msk (0x1UL << FLASH_OPTSR_SECURITY_Pos) /*!< 0x00200000 */ +#define FLASH_OPTSR_SECURITY FLASH_OPTSR_SECURITY_Msk /*!< Security enable option status bit */ +#define FLASH_OPTSR_IO_HSLV_Pos (29U) +#define FLASH_OPTSR_IO_HSLV_Msk (0x1UL << FLASH_OPTSR_IO_HSLV_Pos) /*!< 0x20000000 */ +#define FLASH_OPTSR_IO_HSLV FLASH_OPTSR_IO_HSLV_Msk /*!< I/O high-speed at low-voltage status bit */ +#define FLASH_OPTSR_OPTCHANGEERR_Pos (30U) +#define FLASH_OPTSR_OPTCHANGEERR_Msk (0x1UL << FLASH_OPTSR_OPTCHANGEERR_Pos) /*!< 0x40000000 */ +#define FLASH_OPTSR_OPTCHANGEERR FLASH_OPTSR_OPTCHANGEERR_Msk /*!< Option byte change error flag */ +#define FLASH_OPTSR_SWAP_BANK_OPT_Pos (31U) +#define FLASH_OPTSR_SWAP_BANK_OPT_Msk (0x1UL << FLASH_OPTSR_SWAP_BANK_OPT_Pos) /*!< 0x80000000 */ +#define FLASH_OPTSR_SWAP_BANK_OPT FLASH_OPTSR_SWAP_BANK_OPT_Msk /*!< Bank swapping option status bit */ + +/******************* Bits definition for FLASH_OPTCCR register *******************/ +#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos (30U) +#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk (0x1UL << FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos) /*!< 0x40000000 */ +#define FLASH_OPTCCR_CLR_OPTCHANGEERR FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk /*!< OPTCHANGEERR reset bit */ + +/******************* Bits definition for FLASH_PRAR register *********************/ +#define FLASH_PRAR_PROT_AREA_START_Pos (0U) +#define FLASH_PRAR_PROT_AREA_START_Msk (0xFFFUL << FLASH_PRAR_PROT_AREA_START_Pos) /*!< 0x00000FFF */ +#define FLASH_PRAR_PROT_AREA_START FLASH_PRAR_PROT_AREA_START_Msk /*!< PCROP area start status bits */ +#define FLASH_PRAR_PROT_AREA_END_Pos (16U) +#define FLASH_PRAR_PROT_AREA_END_Msk (0xFFFUL << FLASH_PRAR_PROT_AREA_END_Pos) /*!< 0x0FFF0000 */ +#define FLASH_PRAR_PROT_AREA_END FLASH_PRAR_PROT_AREA_END_Msk /*!< PCROP area end status bits */ +#define FLASH_PRAR_DMEP_Pos (31U) +#define FLASH_PRAR_DMEP_Msk (0x1UL << FLASH_PRAR_DMEP_Pos) /*!< 0x80000000 */ +#define FLASH_PRAR_DMEP FLASH_PRAR_DMEP_Msk /*!< PCROP protected erase enable option status bit */ + +/******************* Bits definition for FLASH_SCAR register *********************/ +#define FLASH_SCAR_SEC_AREA_START_Pos (0U) +#define FLASH_SCAR_SEC_AREA_START_Msk (0xFFFUL << FLASH_SCAR_SEC_AREA_START_Pos) /*!< 0x00000FFF */ +#define FLASH_SCAR_SEC_AREA_START FLASH_SCAR_SEC_AREA_START_Msk /*!< Secure-only area start status bits */ +#define FLASH_SCAR_SEC_AREA_END_Pos (16U) +#define FLASH_SCAR_SEC_AREA_END_Msk (0xFFFUL << FLASH_SCAR_SEC_AREA_END_Pos) /*!< 0x0FFF0000 */ +#define FLASH_SCAR_SEC_AREA_END FLASH_SCAR_SEC_AREA_END_Msk /*!< Secure-only area end status bits */ +#define FLASH_SCAR_DMES_Pos (31U) +#define FLASH_SCAR_DMES_Msk (0x1UL << FLASH_SCAR_DMES_Pos) /*!< 0x80000000 */ +#define FLASH_SCAR_DMES FLASH_SCAR_DMES_Msk /*!< Secure access protected erase enable option status bit */ + +/******************* Bits definition for FLASH_WPSN register *********************/ +#define FLASH_WPSN_WRPSN_Pos (0U) +#define FLASH_WPSN_WRPSN_Msk (0xFFUL << FLASH_WPSN_WRPSN_Pos) /*!< 0x000000FF */ +#define FLASH_WPSN_WRPSN FLASH_WPSN_WRPSN_Msk /*!< Sector write protection option status byte */ + +/******************* Bits definition for FLASH_BOOT_CUR register ****************/ +#define FLASH_BOOT_ADD0_Pos (0U) +#define FLASH_BOOT_ADD0_Msk (0xFFFFUL << FLASH_BOOT_ADD0_Pos) /*!< 0x0000FFFF */ +#define FLASH_BOOT_ADD0 FLASH_BOOT_ADD0_Msk /*!< Arm Cortex-M7 boot address 0 */ +#define FLASH_BOOT_ADD1_Pos (16U) +#define FLASH_BOOT_ADD1_Msk (0xFFFFUL << FLASH_BOOT_ADD1_Pos) /*!< 0xFFFF0000 */ +#define FLASH_BOOT_ADD1 FLASH_BOOT_ADD1_Msk /*!< Arm Cortex-M7 boot address 1 */ + + +/******************* Bits definition for FLASH_CRCCR register ********************/ +#define FLASH_CRCCR_CRC_SECT_Pos (0U) +#define FLASH_CRCCR_CRC_SECT_Msk (0x7UL << FLASH_CRCCR_CRC_SECT_Pos) /*!< 0x00000007 */ +#define FLASH_CRCCR_CRC_SECT FLASH_CRCCR_CRC_SECT_Msk /*!< CRC sector number */ +#define FLASH_CRCCR_CRC_BY_SECT_Pos (8U) +#define FLASH_CRCCR_CRC_BY_SECT_Msk (0x1UL << FLASH_CRCCR_CRC_BY_SECT_Pos) /*!< 0x00000100 */ +#define FLASH_CRCCR_CRC_BY_SECT FLASH_CRCCR_CRC_BY_SECT_Msk /*!< CRC sector mode select bit */ +#define FLASH_CRCCR_ADD_SECT_Pos (9U) +#define FLASH_CRCCR_ADD_SECT_Msk (0x1UL << FLASH_CRCCR_ADD_SECT_Pos) /*!< 0x00000200 */ +#define FLASH_CRCCR_ADD_SECT FLASH_CRCCR_ADD_SECT_Msk /*!< CRC sector select bit */ +#define FLASH_CRCCR_CLEAN_SECT_Pos (10U) +#define FLASH_CRCCR_CLEAN_SECT_Msk (0x1UL << FLASH_CRCCR_CLEAN_SECT_Pos) /*!< 0x00000400 */ +#define FLASH_CRCCR_CLEAN_SECT FLASH_CRCCR_CLEAN_SECT_Msk /*!< CRC sector list clear bit */ +#define FLASH_CRCCR_START_CRC_Pos (16U) +#define FLASH_CRCCR_START_CRC_Msk (0x1UL << FLASH_CRCCR_START_CRC_Pos) /*!< 0x00010000 */ +#define FLASH_CRCCR_START_CRC FLASH_CRCCR_START_CRC_Msk /*!< CRC start bit */ +#define FLASH_CRCCR_CLEAN_CRC_Pos (17U) +#define FLASH_CRCCR_CLEAN_CRC_Msk (0x1UL << FLASH_CRCCR_CLEAN_CRC_Pos) /*!< 0x00020000 */ +#define FLASH_CRCCR_CLEAN_CRC FLASH_CRCCR_CLEAN_CRC_Msk /*!< CRC clear bit */ +#define FLASH_CRCCR_CRC_BURST_Pos (20U) +#define FLASH_CRCCR_CRC_BURST_Msk (0x3UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00300000 */ +#define FLASH_CRCCR_CRC_BURST FLASH_CRCCR_CRC_BURST_Msk /*!< CRC burst size */ +#define FLASH_CRCCR_CRC_BURST_0 (0x1UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00100000 */ +#define FLASH_CRCCR_CRC_BURST_1 (0x2UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00200000 */ +#define FLASH_CRCCR_ALL_BANK_Pos (22U) +#define FLASH_CRCCR_ALL_BANK_Msk (0x1UL << FLASH_CRCCR_ALL_BANK_Pos) /*!< 0x00400000 */ +#define FLASH_CRCCR_ALL_BANK FLASH_CRCCR_ALL_BANK_Msk /*!< CRC select bit */ + +/******************* Bits definition for FLASH_CRCSADD register ****************/ +#define FLASH_CRCSADD_CRC_START_ADDR_Pos (0U) +#define FLASH_CRCSADD_CRC_START_ADDR_Msk (0xFFFFFFFFUL << FLASH_CRCSADD_CRC_START_ADDR_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_CRCSADD_CRC_START_ADDR FLASH_CRCSADD_CRC_START_ADDR_Msk /*!< CRC start address */ + +/******************* Bits definition for FLASH_CRCEADD register ****************/ +#define FLASH_CRCEADD_CRC_END_ADDR_Pos (0U) +#define FLASH_CRCEADD_CRC_END_ADDR_Msk (0xFFFFFFFFUL << FLASH_CRCEADD_CRC_END_ADDR_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_CRCEADD_CRC_END_ADDR FLASH_CRCEADD_CRC_END_ADDR_Msk /*!< CRC end address */ + +/******************* Bits definition for FLASH_CRCDATA register ***************/ +#define FLASH_CRCDATA_CRC_DATA_Pos (0U) +#define FLASH_CRCDATA_CRC_DATA_Msk (0xFFFFFFFFUL << FLASH_CRCDATA_CRC_DATA_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_CRCDATA_CRC_DATA FLASH_CRCDATA_CRC_DATA_Msk /*!< CRC result */ + +/******************* Bits definition for FLASH_ECC_FA register *******************/ +#define FLASH_ECC_FA_FAIL_ECC_ADDR_Pos (0U) +#define FLASH_ECC_FA_FAIL_ECC_ADDR_Msk (0x7FFFUL << FLASH_ECC_FA_FAIL_ECC_ADDR_Pos) /*!< 0x00007FFF */ +#define FLASH_ECC_FA_FAIL_ECC_ADDR FLASH_ECC_FA_FAIL_ECC_ADDR_Msk /*!< ECC error address */ + +/******************************************************************************/ +/* */ +/* Flexible Memory Controller */ +/* */ +/******************************************************************************/ +/****************** Bit definition for FMC_BCR1 register *******************/ +#define FMC_BCR1_CCLKEN_Pos (20U) +#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ +#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*! Date: Tue, 25 Mar 2025 11:47:54 -0700 Subject: [PATCH 06/54] Removed SDRAM from h7 linker script --- .../bootloader/layout.ld | 11 +++-------- .../extra_sections.ld | 18 +----------------- .../{stm32h753_sdram => stm32h753}/layout.ld | 16 +++++----------- radio/src/targets/modalai/CMakeLists.txt | 2 +- 4 files changed, 10 insertions(+), 37 deletions(-) rename radio/src/boards/generic_stm32/linker/{stm32h753_sdram => stm32h753}/bootloader/layout.ld (72%) rename radio/src/boards/generic_stm32/linker/{stm32h753_sdram => stm32h753}/extra_sections.ld (67%) rename radio/src/boards/generic_stm32/linker/{stm32h753_sdram => stm32h753}/layout.ld (63%) diff --git a/radio/src/boards/generic_stm32/linker/stm32h753_sdram/bootloader/layout.ld b/radio/src/boards/generic_stm32/linker/stm32h753/bootloader/layout.ld similarity index 72% rename from radio/src/boards/generic_stm32/linker/stm32h753_sdram/bootloader/layout.ld rename to radio/src/boards/generic_stm32/linker/stm32h753/bootloader/layout.ld index a2205176354..8de0437b8dc 100644 --- a/radio/src/boards/generic_stm32/linker/stm32h753_sdram/bootloader/layout.ld +++ b/radio/src/boards/generic_stm32/linker/stm32h753/bootloader/layout.ld @@ -1,9 +1,5 @@ -/* SDRAM definitions */ -SDRAM_START = DEFINED(__sdram_start) ? __sdram_start : 0xC0000000; -SDRAM_SIZE = DEFINED(__sdram_size) ? __sdram_size : 8192K; - /* Highest heap address */ -HEAP_ADDRESS = SDRAM_START + SDRAM_SIZE; +HEAP_ADDRESS = ORIGIN(RAM_D2) + LENGTH(RAM_D2) - 16; /* Highest address of the user mode stack */ STACK_ADDRESS = ORIGIN(DTCMRAM) + LENGTH(DTCMRAM) - 16; /* end of RAM */ @@ -15,18 +11,17 @@ BOOTLOADER_SIZE = 0x10000; MAIN_STACK_SIZE = 8192; /* Generate a link error if heap and stack don't fit into RAM */ -MIN_HEAP_SIZE = 4096k; /* required amount of heap */ +MIN_HEAP_SIZE = 0; /* required amount of heap */ /* Specify the memory areas */ MEMORY { - FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 2048K ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K DTCMRAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K RAM_D1 (xrw) : ORIGIN = 0x24000000, LENGTH = 512K RAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 288K RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 64K - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_SIZE } REGION_ALIAS("REGION_TEXT_STORAGE", FLASH); diff --git a/radio/src/boards/generic_stm32/linker/stm32h753_sdram/extra_sections.ld b/radio/src/boards/generic_stm32/linker/stm32h753/extra_sections.ld similarity index 67% rename from radio/src/boards/generic_stm32/linker/stm32h753_sdram/extra_sections.ld rename to radio/src/boards/generic_stm32/linker/stm32h753/extra_sections.ld index a6da2e2f105..165ebac1719 100644 --- a/radio/src/boards/generic_stm32/linker/stm32h753_sdram/extra_sections.ld +++ b/radio/src/boards/generic_stm32/linker/stm32h753/extra_sections.ld @@ -39,20 +39,4 @@ _stext_iram = LOADADDR(.iram); _e_dram = .; } > RAM_D2 -.sdram (NOLOAD) : -{ - . = ALIGN(4); - *(.sdram) - *(.sdram*) - *(.sdram_rodata) - *(.sdram_rodata*) - - . = ALIGN(4); - _esdram = .; - - /* Reserve heap space in RAM */ - . = . + MIN_HEAP_SIZE; - . = ALIGN(4); -} > SDRAM - -PROVIDE(_heap_start = _esdram); +PROVIDE(_heap_start = _e_dram); diff --git a/radio/src/boards/generic_stm32/linker/stm32h753_sdram/layout.ld b/radio/src/boards/generic_stm32/linker/stm32h753/layout.ld similarity index 63% rename from radio/src/boards/generic_stm32/linker/stm32h753_sdram/layout.ld rename to radio/src/boards/generic_stm32/linker/stm32h753/layout.ld index 7f94540169c..bef4dff7810 100644 --- a/radio/src/boards/generic_stm32/linker/stm32h753_sdram/layout.ld +++ b/radio/src/boards/generic_stm32/linker/stm32h753/layout.ld @@ -1,9 +1,5 @@ -/* SDRAM definitions */ -SDRAM_START = DEFINED(__sdram_start) ? __sdram_start : 0xC0000000; -SDRAM_SIZE = DEFINED(__sdram_size) ? __sdram_size : 8192K; - /* Highest heap address */ -HEAP_ADDRESS = SDRAM_START + SDRAM_SIZE; +HEAP_ADDRESS = ORIGIN(RAM_D2) + LENGTH(RAM_D2) - 16; /* Highest address of the user mode stack */ STACK_ADDRESS = ORIGIN(DTCMRAM) + LENGTH(DTCMRAM); /* end of RAM */ @@ -15,24 +11,22 @@ BOOTLOADER_SIZE = 0x10000; MAIN_STACK_SIZE = 8192; /* Generate a link error if heap and stack don't fit into RAM */ -MIN_HEAP_SIZE = 4096k; /* required amount of heap */ +MIN_HEAP_SIZE = 128K; /* required amount of heap */ /* Specify the memory areas */ MEMORY { - FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 2048K ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K DTCMRAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K RAM_D1 (xrw) : ORIGIN = 0x24000000, LENGTH = 512K RAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 288K RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 64K - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_SIZE - NORFLASH (rx) : ORIGIN = 0x90000000, LENGTH = 8M } REGION_ALIAS("REGION_BOOTLOADER", FLASH); -REGION_ALIAS("REGION_TEXT_STORAGE", NORFLASH); -REGION_ALIAS("REGION_TEXT", SDRAM); +REGION_ALIAS("REGION_TEXT_STORAGE", FLASH); +REGION_ALIAS("REGION_TEXT", FLASH); REGION_ALIAS("REGION_ISR_VECT", DTCMRAM); REGION_ALIAS("REGION_DATA", DTCMRAM); REGION_ALIAS("REGION_BSS", RAM_D1); diff --git a/radio/src/targets/modalai/CMakeLists.txt b/radio/src/targets/modalai/CMakeLists.txt index f038ab87a5c..a586a3012bf 100644 --- a/radio/src/targets/modalai/CMakeLists.txt +++ b/radio/src/targets/modalai/CMakeLists.txt @@ -59,7 +59,7 @@ message("CPU_TYPE_FULL = ${CPU_TYPE_FULL}") if (CPU_TYPE_FULL STREQUAL STM32H753II) set(CPU_TYPE STM32H7) add_definitions(-DSTM32H753xx) - set(TARGET_LINKER_DIR stm32h753_sdram) + set(TARGET_LINKER_DIR stm32h753) else() message(FATAL_ERROR "Unknown CPU_TYPE_FULL" ) endif() From 4a2ce3eb0f819166ca297788696cc4dd7b7da703 Mon Sep 17 00:00:00 2001 From: Maxwell Schaefer Date: Tue, 25 Mar 2025 13:03:05 -0700 Subject: [PATCH 07/54] Ported setup code from H7RS, now running TODO: fix clock setup --- radio/src/edgetx.cpp | 2 +- .../common/arm/stm32/abnormal_reboot.cpp | 3 +- .../common/arm/stm32/h7/system_stm32h7xx.c | 3 + radio/src/targets/modalai/CMakeLists.txt | 4 +- radio/src/targets/modalai/board.cpp | 33 ++-- radio/src/targets/modalai/hal.h | 12 +- radio/src/targets/modalai/system_clock.cpp | 149 ++++++++++++++ radio/src/targets/modalai/system_clock.h | 23 +++ radio/src/targets/modalai/system_init.cpp | 185 ++++++++++++++++++ radio/src/targets/modalai/usb_descriptor.h | 80 +------- 10 files changed, 393 insertions(+), 101 deletions(-) create mode 100644 radio/src/targets/modalai/system_clock.cpp create mode 100644 radio/src/targets/modalai/system_clock.h create mode 100644 radio/src/targets/modalai/system_init.cpp diff --git a/radio/src/edgetx.cpp b/radio/src/edgetx.cpp index a89a2ab09ce..c1084081231 100644 --- a/radio/src/edgetx.cpp +++ b/radio/src/edgetx.cpp @@ -143,7 +143,7 @@ void checkValidMCU(void) #define TARGET_IDCODE 0x419 #elif defined(STM32F413xx) #define TARGET_IDCODE 0x463 -#elif defined(STM32H750xx) || defined(STM32H747xx) +#elif defined(STM32H750xx) || defined(STM32H747xx) || defined(STM32H753xx) #define TARGET_IDCODE 0x450 #elif defined(STM32H7RS) #define TARGET_IDCODE 0x485 diff --git a/radio/src/targets/common/arm/stm32/abnormal_reboot.cpp b/radio/src/targets/common/arm/stm32/abnormal_reboot.cpp index ad1cbd0ddae..54dc2bf8244 100644 --- a/radio/src/targets/common/arm/stm32/abnormal_reboot.cpp +++ b/radio/src/targets/common/arm/stm32/abnormal_reboot.cpp @@ -23,7 +23,8 @@ #include "stm32_hal_ll.h" -#define __REBOOT_DATA __attribute__((section(".rebootdata"), aligned(4))) +// #define __REBOOT_DATA __attribute__((section(".rebootdata"), aligned(4))) +#define __REBOOT_DATA __attribute__((aligned(4))) // This variable is define at a fixed memory location // and is used in bootloader and firmware to pass diff --git a/radio/src/targets/common/arm/stm32/h7/system_stm32h7xx.c b/radio/src/targets/common/arm/stm32/h7/system_stm32h7xx.c index bc618f01244..0504011dfec 100644 --- a/radio/src/targets/common/arm/stm32/h7/system_stm32h7xx.c +++ b/radio/src/targets/common/arm/stm32/h7/system_stm32h7xx.c @@ -303,6 +303,9 @@ BOOTSTRAP void SystemInit (void) /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */ +#else + extern uint32_t g_pfnVectors ; + SCB->VTOR = (uint32_t) &g_pfnVectors ; /* Vector Table Relocation in Internal FLASH */ #endif /* USER_VECT_TAB_ADDRESS */ #endif /*DUAL_CORE && CORE_CM4*/ diff --git a/radio/src/targets/modalai/CMakeLists.txt b/radio/src/targets/modalai/CMakeLists.txt index a586a3012bf..574dd50bfa8 100644 --- a/radio/src/targets/modalai/CMakeLists.txt +++ b/radio/src/targets/modalai/CMakeLists.txt @@ -8,7 +8,7 @@ option(AUTOUPDATE "Auto update internal chips from SD" OFF) option(BIND_KEY "Enable bind button" OFF) option(BLUETOOTH "FrSky BT module support" OFF) -set(USE_RTC_CLOCK YES) +set(USE_RTC_CLOCK NO) set(HARDWARE_EXTERNAL_MODULE YES) set(TARGET_DIR modalai) @@ -82,6 +82,8 @@ set(TARGET_SRC_DIR targets/${TARGET_DIR}) set(BOARD_COMMON_SRC ${TARGET_SRC_DIR}/board.cpp + ${TARGET_SRC_DIR}/system_init.cpp + ${TARGET_SRC_DIR}/system_clock.cpp ${TARGET_SRC_DIR}/led_driver.cpp ${TARGET_SRC_DIR}/backlight_driver.cpp ${TARGET_SRC_DIR}/${LCD_DRIVER} diff --git a/radio/src/targets/modalai/board.cpp b/radio/src/targets/modalai/board.cpp index 9821d81c161..8ebb144f088 100644 --- a/radio/src/targets/modalai/board.cpp +++ b/radio/src/targets/modalai/board.cpp @@ -78,28 +78,28 @@ void boardInit() #endif LL_APB4_GRP1_EnableClock(LL_APB4_GRP1_PERIPH_SYSCFG); - SCB_EnableDCache(); + // SCB_EnableDCache(); RCC->D3CFGR = (0x5 << 4); RCC->APB4ENR |= RCC_APB4ENR_SPI6EN; // Setup pll1 - // RCC->PLL1DIVR |= (0xA0000U & RCC_PLL1DIVR_Q1_Msk); // Set prescaler to 6 (~21 MHz after scaling) - // RCC->CR |= RCC_CR_PLL1ON; - // while (RCC->CR & RCC_CR_PLL1ON == 0) { } + RCC->PLL1DIVR |= (0xA0000U & RCC_PLL1DIVR_Q1_Msk); // Set prescaler to 6 (~21 MHz after scaling) + RCC->CR |= RCC_CR_PLL1ON; + while (RCC->CR & RCC_CR_PLL1ON == 0) { } // Setup pll2 - // RCC->PLLCKSELR &= ~(0x10000 & RCC_PLLCKSELR_DIVM2); - // RCC->PLLCKSELR |= (0x10000 & RCC_PLLCKSELR_DIVM2); - //DIVN2 = 200 - //DIVP2 = 8 - // RCC->PLL2DIVR |= ((0x1000 & RCC_PLL2DIVR_P2) | (0xC8 & RCC_PLL2DIVR_N2)); - // RCC->CR |= RCC_CR_PLL2ON; - // while (RCC->CR & RCC_CR_PLL2ON == 0) { } + RCC->PLLCKSELR &= ~(0x10000 & RCC_PLLCKSELR_DIVM2); + RCC->PLLCKSELR |= (0x10000 & RCC_PLLCKSELR_DIVM2); + // DIVN2 = 200 + // DIVP2 = 8 + RCC->PLL2DIVR |= ((0x1000 & RCC_PLL2DIVR_P2) | (0xC8 & RCC_PLL2DIVR_N2)); + RCC->CR |= RCC_CR_PLL2ON; + while (RCC->CR & RCC_CR_PLL2ON == 0) { } // Select UART clock source as HSI: - // RCC->D2CCIP2R &= ~(0x18); - // RCC->D2CCIP2R |= 0x18; + RCC->D2CCIP2R &= ~(0x18); + RCC->D2CCIP2R |= 0x18; #if defined(POWER_I2C) @@ -170,9 +170,9 @@ void boardInit() #endif #if defined(PWR_BUTTON_PRESS) // TODO: re-enable - if (WAS_RESET_BY_WATCHDOG_OR_SOFTWARE()) { - pwrOn(); - } + // if (WAS_RESET_BY_WATCHDOG_OR_SOFTWARE()) { + // pwrOn(); + // } #endif #if defined(USB_CHARGER) @@ -180,6 +180,7 @@ void boardInit() #endif #if defined(RTCLOCK) + #error RTC rtcInit(); // RTC must be initialized before rambackupRestore() is called #endif diff --git a/radio/src/targets/modalai/hal.h b/radio/src/targets/modalai/hal.h index 6e03540cd8e..570097560c2 100644 --- a/radio/src/targets/modalai/hal.h +++ b/radio/src/targets/modalai/hal.h @@ -183,8 +183,8 @@ // PWR and LED driver // #warning unsure what these do, TODO: Remove these buttons completely -// #define PWR_SWITCH_GPIO GPIO_PIN(GPIOC, 10) // PC.06 -// #define PWR_ON_GPIO GPIO_PIN(GPIOC, 11) // PC.07 +#define PWR_SWITCH_GPIO GPIO_PIN(GPIOA, 5) // PC.06 +#define PWR_ON_GPIO GPIO_PIN(GPIOA, 6) // PC.07 #define USE_LEDS #ifdef USE_LEDS @@ -192,9 +192,9 @@ #define STATUS_LEDS #define GPIO_LED_GPIO_ON gpio_clear #define GPIO_LED_GPIO_OFF gpio_set -#define LED_GREEN_GPIO GPIO_PIN(GPIOI, 5) // PE.04 -#define LED_RED_GPIO GPIO_PIN(GPIOI, 6) // PE.03 -#define LED_BLUE_GPIO GPIO_PIN(GPIOI, 7) // PA.05 +#define LED_GREEN_GPIO GPIO_PIN(GPIOI, 7) // PI.07 +#define LED_RED_GPIO GPIO_PIN(GPIOI, 6) // PI.06 +#define LED_BLUE_GPIO GPIO_PIN(GPIOI, 5) // PI.05 #endif // USE_LEDS // Internal Module @@ -355,7 +355,7 @@ #define VOXLPM_INA231_VBAT_I_LSB (VOXLPM_INA231_VBAT_MAX_AMPS/32768.0f) #define VOXLPM_INA231_VREG_I_LSB (VOXLPM_INA231_VREG_MAX_AMPS/32768.0f) -#define POWER_I2C I2C1 // Comment this out to disable I2C +// #define POWER_I2C I2C1 // Comment this out to disable I2C #define POWER_I2C_PIN_SDA GPIO_PIN(GPIOB, 9) // PB.09 #define POWER_I2C_SDA_AF GPIO_AF4 #define POWER_I2C_PIN_SCL GPIO_PIN(GPIOB, 8) // PB.08 diff --git a/radio/src/targets/modalai/system_clock.cpp b/radio/src/targets/modalai/system_clock.cpp new file mode 100644 index 00000000000..87506638bfe --- /dev/null +++ b/radio/src/targets/modalai/system_clock.cpp @@ -0,0 +1,149 @@ +/* + * Copyright (C) EdgeTX + * + * Based on code named + * opentx - https://github.com/opentx/opentx + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "stm32h7xx_ll_pwr.h" +#include "stm32h7xx_ll_rcc.h" +#include "stm32h7xx_ll_system.h" +#include "stm32h7xx_ll_bus.h" + +#define BOOTSTRAP __attribute__((section(".bootstrap"))) + +/** + * @brief System Clock Configuration + * The system Clock is configured as follow : + * System Clock source = PLL1 (HSE BYPASS) + * SYSCLK(Hz) = 400000000 (CPU Clock) + * HCLK(Hz) = 200000000 (Cortex-M4 CPU, Bus matrix Clocks) + * AHB Prescaler = 2 + * D1 APB3 Prescaler = 2 (APB3 Clock 100MHz) + * D2 APB1 Prescaler = 2 (APB1 Clock 100MHz) + * D2 APB2 Prescaler = 2 (APB2 Clock 100MHz) + * D3 APB4 Prescaler = 2 (APB4 Clock 100MHz) + * HSE Frequency(Hz) = 25000000 + * PLL_M = 5 + * PLL_N = 160 + * PLL_P = 2 + * PLL_Q = 4 + * PLL_R = 2 + * VDD(V) = 3.3 + * Flash Latency(WS) = 4 + * @param None + * @retval None + */ +extern "C" BOOTSTRAP +void SystemClock_Config() +{ +// /* Power Configuration */ +// LL_PWR_ConfigSupply(LL_PWR_DIRECT_SMPS_SUPPLY); +// while (LL_PWR_IsActiveFlag_ACTVOSRDY() == 0) { +// } +// LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE0); +// while (LL_PWR_IsActiveFlag_VOSRDY() == 0) { +// } + +// /* Enable HSE oscillator */ +// LL_RCC_HSE_Enable(); +// while (LL_RCC_HSE_IsReady() != 1) { +// } + +// /* Set FLASH latency */ +// LL_FLASH_SetLatency(LL_FLASH_LATENCY_6); + +// /* Main PLL configuration and activation */ +// LL_RCC_PLL_SetSource(LL_RCC_PLLSOURCE_HSE); +// LL_RCC_PLL1P_Enable(); +// // LL_RCC_PLL1Q_Enable(); +// // LL_RCC_PLL1R_Enable(); +// LL_RCC_PLL1FRACN_Disable(); +// LL_RCC_PLL1_SetVCOInputRange(LL_RCC_PLLINPUTRANGE_2_4); +// LL_RCC_PLL1_SetVCOOutputRange(LL_RCC_PLLVCORANGE_WIDE); +// LL_RCC_PLL1_SetM(2); +// LL_RCC_PLL1_SetN(50); +// LL_RCC_PLL1_SetP(1); +// // LL_RCC_PLL1_SetQ(2); +// // LL_RCC_PLL1_SetR(2); +// // LL_RCC_PLL1_SetS(2); +// LL_RCC_PLL1_Enable(); +// while (LL_RCC_PLL1_IsReady() != 1) { +// } + +// /* Set Sys & AHB & APB1 & APB2 & APB4 prescaler */ +// LL_RCC_SetSysPrescaler(LL_RCC_SYSCLK_DIV_1); +// LL_RCC_SetAHBPrescaler(LL_RCC_AHB_DIV_2); +// LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_2); +// LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_2); +// LL_RCC_SetAPB4Prescaler(LL_RCC_APB4_DIV_2); + +// /* Set PLL1 as System Clock Source */ +// LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL1); +// while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL1) { +// } + +// /* PLL2 configuration and activation */ +// LL_RCC_PLL2S_Enable(); +// LL_RCC_PLL2Q_Enable(); +// LL_RCC_PLL2FRACN_Disable(); +// LL_RCC_PLL2_SetVCOInputRange(LL_RCC_PLLINPUTRANGE_2_4); +// LL_RCC_PLL2_SetVCOOutputRange(LL_RCC_PLLVCORANGE_WIDE); +// LL_RCC_PLL2_SetM(2); +// LL_RCC_PLL2_SetN(64); +// LL_RCC_PLL2_SetP(2); // disabled +// LL_RCC_PLL2_SetQ(47); // 16.340 MHz +// LL_RCC_PLL2_SetR(2); // disabled +// LL_RCC_PLL2_SetS(4); // 192 MHz +// LL_RCC_PLL2_Enable(); +// while (LL_RCC_PLL2_IsReady() != 1) { +// } + +// /* PLL2 configuration and activation */ +// LL_RCC_PLL3R_Enable(); +// LL_RCC_PLL3FRACN_Disable(); +// LL_RCC_PLL3_SetVCOInputRange(LL_RCC_PLLINPUTRANGE_4_8); +// LL_RCC_PLL3_SetVCOOutputRange(LL_RCC_PLLVCORANGE_WIDE); +// LL_RCC_PLL3_SetM(2); +// LL_RCC_PLL3_SetN(50); +// LL_RCC_PLL3_SetP(2); +// LL_RCC_PLL3_SetQ(2); +// LL_RCC_PLL3_SetR(24); +// LL_RCC_PLL3_Enable(); +// while (LL_RCC_PLL3_IsReady() != 1) { +// } + +// #if defined(USE_USB_HS) +// LL_RCC_SetUSBPHYCClockSource(LL_RCC_USBPHYC_CLKSOURCE_HSE); +// LL_RCC_SetUSBREFClockSource(LL_RCC_USBREF_CLKSOURCE_24M); +// #else +// LL_RCC_HSI48_Enable(); +// while (LL_RCC_HSI48_IsReady() != 1) { +// } +// LL_RCC_SetOTGFSClockSource(LL_RCC_OTGFS_CLKSOURCE_HSI48); +// #endif + +// // 192 MHz +// LL_RCC_SetXSPIClockSource(LL_RCC_XSPI1_CLKSOURCE_PLL2S); +// LL_RCC_SetXSPIClockSource(LL_RCC_XSPI2_CLKSOURCE_PLL2S); + +// // 16.340 MHz +// LL_RCC_SetSPIClockSource(LL_RCC_SPI6_CLKSOURCE_PLL2Q); + +// // Only required if using Async ADC clock ??? +// LL_RCC_SetADCClockSource(LL_RCC_ADC_CLKSOURCE_CLKP); +} diff --git a/radio/src/targets/modalai/system_clock.h b/radio/src/targets/modalai/system_clock.h new file mode 100644 index 00000000000..758d63c32a0 --- /dev/null +++ b/radio/src/targets/modalai/system_clock.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) EdgeTX + * + * Based on code named + * opentx - https://github.com/opentx/opentx + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +extern "C" void SystemClock_Config(); + diff --git a/radio/src/targets/modalai/system_init.cpp b/radio/src/targets/modalai/system_init.cpp new file mode 100644 index 00000000000..a0e6ef34f8f --- /dev/null +++ b/radio/src/targets/modalai/system_init.cpp @@ -0,0 +1,185 @@ +#include +#include "stm32_cmsis.h" +#include "system_clock.h" + +#include "stm32_hal.h" + +#define NAKED __attribute__((naked)) +#define BOOTSTRAP __attribute__((section(".bootstrap"))) + +// Linker script symbols +extern uint32_t _sisr_vector; +extern uint32_t _dram_addr; +extern uint32_t PSRAM_START; +extern uint32_t NORFLASH_START; + +extern "C" NAKED BOOTSTRAP +void Reset_Handler() +{ + asm inline ( + "ldr sp, =_estack \n" + ); + +#if defined(BOOT) + asm inline ( + "bl SystemClock_Config \n" + "bl CPU_CACHE_Enable \n" + ); +#endif + + // Copy code into normal RAM + asm inline ( + "ldr r0, =_stext \n" + "ldr r1, =_etext \n" + "ldr r2, =_text_load \n" + "bl naked_copy \n" + ); + +#if defined(BOOT) + asm inline ( + "bl SystemInit \n" + "bl MPU_Init \n" + ); +#endif + + // Copy / setup ISR vector + asm inline ( + "ldr r0, =_sisr_vector \n" + "ldr r1, =_eisr_vector \n" + "ldr r2, =_isr_load \n" + "bl naked_copy \n" + "bl set_vtor \n" + ); + + // Copy code into fast RAM + asm inline ( + "ldr r0, =_siram \n" + "ldr r1, =_eiram \n" + "ldr r2, =_stext_iram \n" + "bl naked_copy \n" + ); + + // Copy initialized data segment + asm inline ( + "ldr r0, =_sdata \n" + "ldr r1, =_edata \n" + "ldr r2, =_sidata \n" + "bl naked_copy \n" + ); + + // Zero fill bss segment + asm inline ( + "ldr r2, =_sbss \n" + "ldr r4, =_ebss \n" + "movs r3, 0 \n" + "b LoopFillZerobss \n" + + "FillZerobss: \n" + "str r3, [r2] \n" + "adds r2, r2, 4 \n" + + "LoopFillZerobss: \n" + "cmp r2, r4 \n" + "bcc FillZerobss \n" + ); + + asm inline ( + "bl clean_dcache \n" + // Call static constructors + "bl __libc_init_array \n" + "bl SystemCoreClockUpdate \n" + // Call the application's entry point + "bl main \n" + "bx lr \n" + ); +} + +extern "C" BOOTSTRAP void set_vtor() { + SCB->VTOR = (intptr_t)&_sisr_vector; +} + +extern "C" NAKED BOOTSTRAP void naked_copy() { + // r0: destination start + // r1: destination end + // r2: source start + asm inline ( + "cmp r0, r2 \n" + "beq SkipCopy \n" + "movs r3, 0 \n" + "b LoopCopyInit \n" + + "CopyInit: \n" + "ldr r4, [r2, r3] \n" + "str r4, [r0, r3] \n" + "adds r3, r3, #4 \n" + + "LoopCopyInit: \n" + "adds r4, r0, r3 \n" + "cmp r4, r1 \n" + "bcc CopyInit \n" + "SkipCopy: \n" + "bx lr \n" + ); +} + +extern "C" BOOTSTRAP +void CPU_CACHE_Enable() +{ + /* Enable I-Cache */ + SCB_EnableICache(); + + /* Enable D-Cache */ + SCB_EnableDCache(); +} + +extern "C" __attribute__((used)) +void MPU_Init() +{ + MPU_Region_InitTypeDef MPU_InitStruct = {0}; + + /* Disables the MPU */ + HAL_MPU_Disable(); + + /* + * Region 0: overwrite default setting to prevent speculative + * read to unavailable memories. + * Range: 0x60000000 to 0xE0000000 + * + * Set as strongly ordered, code execution disabled + */ + MPU_InitStruct.Enable = MPU_REGION_ENABLE; + MPU_InitStruct.Number = MPU_REGION_NUMBER0; + MPU_InitStruct.BaseAddress = 0; + MPU_InitStruct.Size = MPU_REGION_SIZE_4GB; + MPU_InitStruct.SubRegionDisable = 0x87; + MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0; + MPU_InitStruct.AccessPermission = MPU_REGION_NO_ACCESS; + MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE; + MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE; + MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE; + MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE; + HAL_MPU_ConfigRegion(&MPU_InitStruct); + + /* Region 3: DMA memory range */ + MPU_InitStruct.Enable = MPU_REGION_ENABLE; + MPU_InitStruct.Number = MPU_REGION_NUMBER4; + MPU_InitStruct.BaseAddress = (uint32_t)&_dram_addr; + MPU_InitStruct.Size = MPU_REGION_SIZE_64KB; // actually 72KB + MPU_InitStruct.SubRegionDisable = 0x0; + MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1; + MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS; + MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE; + MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE; + MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE; + MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE; + HAL_MPU_ConfigRegion(&MPU_InitStruct); + + HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT); + + /* Enable bus fault exception */ + SCB->SHCSR |= SCB_SHCSR_BUSFAULTENA_Msk; +} + +extern "C" void clean_dcache() { + SCB_CleanDCache(); +} diff --git a/radio/src/targets/modalai/usb_descriptor.h b/radio/src/targets/modalai/usb_descriptor.h index 8be765b2279..eb13116def3 100644 --- a/radio/src/targets/modalai/usb_descriptor.h +++ b/radio/src/targets/modalai/usb_descriptor.h @@ -21,80 +21,8 @@ #pragma once -#if defined(RADIO_TX12) || defined(RADIO_TX12MK2) - #define USB_NAME "Radiomaster TX12" - #define USB_MANUFACTURER 'R', 'M', '_', 'T', 'X', ' ', ' ', ' ' /* 8 bytes */ - #define USB_PRODUCT 'R', 'M', ' ', 'T', 'X', '1', '2', ' ' /* 8 Bytes */ -#elif defined(RADIO_BOXER) - #define USB_NAME "Radiomaster Boxer" - #define USB_MANUFACTURER 'R', 'M', '_', 'T', 'X', ' ', ' ', ' ' /* 8 bytes */ - #define USB_PRODUCT 'R', 'M', ' ', 'B', 'o', 'x', 'e', 'r' /* 8 Bytes */ -#elif defined(RADIO_ZORRO) - #define USB_NAME "Radiomaster Zorro" - #define USB_MANUFACTURER 'R', 'M', '_', 'T', 'X', ' ', ' ', ' ' /* 8 bytes */ - #define USB_PRODUCT 'R', 'M', ' ', 'Z', 'o', 'r', 'r', 'o' /* 8 Bytes */ -#elif defined(RADIO_MT12) - #define USB_NAME "Radiomaster MT12" - #define USB_MANUFACTURER 'R', 'M', '_', 'T', 'X', ' ', ' ', ' ' /* 8 bytes */ - #define USB_PRODUCT 'R', 'M', ' ', 'M', 'T', '1', '2', ' ' /* 8 Bytes */ -#elif defined(RADIO_POCKET) - #define USB_NAME "Radiomaster Pocket" - #define USB_MANUFACTURER 'R', 'M', '_', 'T', 'X', ' ', ' ', ' ' /* 8 bytes */ - #define USB_PRODUCT 'R', 'M', 'P', 'o', 'c', 'k', 'e', 't' /* 8 Bytes */ -#elif defined(RADIO_T8) - #define USB_NAME "Radiomaster T8" - #define USB_MANUFACTURER 'R', 'M', '_', 'T', 'X', ' ', ' ', ' ' /* 8 bytes */ - #define USB_PRODUCT 'R', 'M', ' ', 'T', '8', ' ', ' ', ' ' /* 8 Bytes */ -#elif defined(RADIO_LR3PRO) - #define USB_NAME "BETAFPV LR3PRO" - #define USB_MANUFACTURER 'B', 'E', 'T', 'A', 'F', 'P', 'V', ' ' /* 8 bytes */ - #define USB_PRODUCT 'L', 'R', '3', 'P', 'R', 'O', ' ', ' ' /* 8 Bytes */ -#elif defined(RADIO_TLITE) - #define USB_NAME "Jumper TLite" - #define USB_MANUFACTURER 'J', 'U', 'M', 'P', 'E', 'R', ' ', ' ' /* 8 bytes */ - #define USB_PRODUCT 'T', '-', 'L', 'i', 't', 'e', ' ', ' ' /* 8 Bytes */ -#elif defined(RADIO_TPRO) - #define USB_NAME "Jumper TPro" - #define USB_MANUFACTURER 'J', 'U', 'M', 'P', 'E', 'R', ' ', ' ' /* 8 bytes */ - #define USB_PRODUCT 'T', '-', 'P', 'r', 'o', ' ', ' ', ' ' /* 8 Bytes */ -#elif defined(RADIO_TPROV2) - #define USB_NAME "Jumper TPro V2" - #define USB_MANUFACTURER 'J', 'U', 'M', 'P', 'E', 'R', ' ', ' ' /* 8 bytes */ - #define USB_PRODUCT 'T', '-', 'P', 'r', 'o', ' ', 'V', '2' /* 8 Bytes */ -#elif defined(RADIO_T12MAX) -#define USB_NAME "Jumper T12 MAX" - #define USB_MANUFACTURER 'J', 'U', 'M', 'P', 'E', 'R', ' ', ' ' /* 8 bytes */ - #define USB_PRODUCT 'T', '1', '2', ' ', 'M', 'A', 'X', ' ' /* 8 Bytes */ -#elif defined(RADIO_TPROS) - #define USB_NAME "Jumper T-Pro S" - #define USB_MANUFACTURER 'J', 'U', 'M', 'P', 'E', 'R', ' ', ' ' /* 8 bytes */ - #define USB_PRODUCT 'T', '-', 'P', 'r', 'o', ' ', 'S', ' ' /* 8 Bytes */ -#elif defined(RADIO_T14) - #define USB_NAME "Jumper T14" - #define USB_MANUFACTURER 'J', 'U', 'M', 'P', 'E', 'R', ' ', ' ' /* 8 bytes */ - #define USB_PRODUCT 'T', '1', '4', ' ', ' ', ' ', ' ', ' ' /* 8 Bytes */ -#elif defined(RADIO_T20) - #define USB_NAME "Jumper T20" - #define USB_MANUFACTURER 'J', 'U', 'M', 'P', 'E', 'R', ' ', ' ' /* 8 bytes */ - #define USB_PRODUCT 'T', '2', '0', ' ', ' ', ' ', ' ', ' ' /* 8 Bytes */ -#elif defined(RADIO_T20V2) - #define USB_NAME "Jumper T20 V2" - #define USB_MANUFACTURER 'J', 'U', 'M', 'P', 'E', 'R', ' ', ' ' /* 8 bytes */ - #define USB_PRODUCT 'T', '2', '0', 'V', '2', ' ', ' ', ' ' /* 8 Bytes */ -#elif defined(RADIO_COMMANDO8) - #define USB_NAME "iFlight Commando 8" - #define USB_MANUFACTURER 'i', 'F', 'l', 'i', 'g', 'h', 't', '-' /* 8 bytes */ - #define USB_PRODUCT 'C', 'o', 'm', 'm', 'a', 'n', 'd', 'o' /* 8 Bytes */ -#elif defined(RADIO_V12) - #define USB_NAME "HelloRadioSky V12" - #define USB_MANUFACTURER 'H', 'R', 'S', 'k', 'y', ' ', ' ', ' ' /* 8 bytes */ - #define USB_PRODUCT 'V', '1', '2', ' ', ' ', ' ', ' ', ' ' /* 8 Bytes */ -#elif defined(RADIO_V14) - #define USB_NAME "HelloRadioSky V14" - #define USB_MANUFACTURER 'H', 'R', 'S', 'k', 'y', ' ', ' ', ' ' /* 8 bytes */ - #define USB_PRODUCT 'V', '1', '4', ' ', ' ', ' ', ' ', ' ' /* 8 Bytes */ -#else - #define USB_NAME "FrSky Taranis" - #define USB_MANUFACTURER 'F', 'r', 'S', 'k', 'y', ' ', ' ', ' ' /* 8 bytes */ - #define USB_PRODUCT 'T', 'a', 'r', 'a', 'n', 'i', 's', ' ' /* 8 Bytes */ +#if defined(RADIO_MODAL) + #define USB_NAME "ModalAI Zorro Blue" + #define USB_MANUFACTURER 'M', 'o', 'd', 'a', 'l', 'A', 'I', ' ' /* 8 bytes */ + #define USB_PRODUCT 'B', 'l', 'u', 'e', ' ', 'Z', ' ', ' ' /* 8 Bytes */ #endif From c594b430c38fefbad22cf40154c04a174259c1a0 Mon Sep 17 00:00:00 2001 From: Maxwell Schaefer Date: Tue, 25 Mar 2025 13:46:59 -0700 Subject: [PATCH 08/54] Added bootloader support --- radio/src/CMakeLists.txt | 2 +- radio/src/targets/modalai/CMakeLists.txt | 8 +++---- radio/src/targets/modalai/system_init.cpp | 26 +++++++++++------------ 3 files changed, 18 insertions(+), 18 deletions(-) diff --git a/radio/src/CMakeLists.txt b/radio/src/CMakeLists.txt index deb514cad92..b363e823e41 100644 --- a/radio/src/CMakeLists.txt +++ b/radio/src/CMakeLists.txt @@ -50,7 +50,7 @@ option(FRSKY_RELEASE "Used to build FrSky released firmware" OFF) option(TBS_RELEASE "Used to build TBS released firmware" OFF) option(IMRC_RELEASE "Used to build IMRC released firmware" OFF) option(HARDWARE_TRAINER_MULTI "Allow multi trainer" OFF) -option(BOOTLOADER "Include Bootloader" OFF) +option(BOOTLOADER "Include Bootloader" ON) option(FWDRIVE "Attach also firmware drive with USB" OFF) option(DISABLE_MCUCHECK "Disable MCU check at start" OFF) option(LUA_MIXER "Enable LUA mixer/model scripts support" ON) diff --git a/radio/src/targets/modalai/CMakeLists.txt b/radio/src/targets/modalai/CMakeLists.txt index 574dd50bfa8..8e14419db8a 100644 --- a/radio/src/targets/modalai/CMakeLists.txt +++ b/radio/src/targets/modalai/CMakeLists.txt @@ -178,9 +178,9 @@ set(GUI_SRC ${GUI_SRC} # There has to be a better way... # In C23 there is now support for #embed... -#set(FIRMWARE_SRC -# ${FIRMWARE_SRC} -# targets/common/arm/loadboot.cpp -# ) +set(FIRMWARE_SRC + ${FIRMWARE_SRC} + targets/common/arm/loadboot.cpp +) set(RADIO_DEPENDENCIES ${RADIO_DEPENDENCIES} ${BITMAPS_TARGET}) diff --git a/radio/src/targets/modalai/system_init.cpp b/radio/src/targets/modalai/system_init.cpp index a0e6ef34f8f..1c00ecde61a 100644 --- a/radio/src/targets/modalai/system_init.cpp +++ b/radio/src/targets/modalai/system_init.cpp @@ -160,19 +160,19 @@ void MPU_Init() MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE; HAL_MPU_ConfigRegion(&MPU_InitStruct); - /* Region 3: DMA memory range */ - MPU_InitStruct.Enable = MPU_REGION_ENABLE; - MPU_InitStruct.Number = MPU_REGION_NUMBER4; - MPU_InitStruct.BaseAddress = (uint32_t)&_dram_addr; - MPU_InitStruct.Size = MPU_REGION_SIZE_64KB; // actually 72KB - MPU_InitStruct.SubRegionDisable = 0x0; - MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1; - MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS; - MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE; - MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE; - MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE; - MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE; - HAL_MPU_ConfigRegion(&MPU_InitStruct); + // /* Region 3: DMA memory range */ + // MPU_InitStruct.Enable = MPU_REGION_ENABLE; + // MPU_InitStruct.Number = MPU_REGION_NUMBER4; + // MPU_InitStruct.BaseAddress = (uint32_t)&_dram_addr; + // MPU_InitStruct.Size = MPU_REGION_SIZE_64KB; // actually 72KB + // MPU_InitStruct.SubRegionDisable = 0x0; + // MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1; + // MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS; + // MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE; + // MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE; + // MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE; + // MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE; + // HAL_MPU_ConfigRegion(&MPU_InitStruct); HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT); From beaa1deeeae1a2967048e2b616fed27d98f716f0 Mon Sep 17 00:00:00 2001 From: Maxwell Schaefer Date: Wed, 26 Mar 2025 11:35:57 -0700 Subject: [PATCH 09/54] Defined clock configuration, based on H7RS clock config --- radio/src/targets/modalai/CMakeLists.txt | 2 +- radio/src/targets/modalai/board.cpp | 7 +- radio/src/targets/modalai/hal.h | 19 +- radio/src/targets/modalai/system_clock.cpp | 211 +++++++++++---------- 4 files changed, 123 insertions(+), 116 deletions(-) diff --git a/radio/src/targets/modalai/CMakeLists.txt b/radio/src/targets/modalai/CMakeLists.txt index 8e14419db8a..dba9daefa78 100644 --- a/radio/src/targets/modalai/CMakeLists.txt +++ b/radio/src/targets/modalai/CMakeLists.txt @@ -8,7 +8,7 @@ option(AUTOUPDATE "Auto update internal chips from SD" OFF) option(BIND_KEY "Enable bind button" OFF) option(BLUETOOTH "FrSky BT module support" OFF) -set(USE_RTC_CLOCK NO) +set(USE_RTC_CLOCK YES) set(HARDWARE_EXTERNAL_MODULE YES) set(TARGET_DIR modalai) diff --git a/radio/src/targets/modalai/board.cpp b/radio/src/targets/modalai/board.cpp index 8ebb144f088..ef10b2ccc06 100644 --- a/radio/src/targets/modalai/board.cpp +++ b/radio/src/targets/modalai/board.cpp @@ -170,9 +170,9 @@ void boardInit() #endif #if defined(PWR_BUTTON_PRESS) // TODO: re-enable - // if (WAS_RESET_BY_WATCHDOG_OR_SOFTWARE()) { - // pwrOn(); - // } + if (WAS_RESET_BY_WATCHDOG_OR_SOFTWARE()) { + pwrOn(); + } #endif #if defined(USB_CHARGER) @@ -180,7 +180,6 @@ void boardInit() #endif #if defined(RTCLOCK) - #error RTC rtcInit(); // RTC must be initialized before rambackupRestore() is called #endif diff --git a/radio/src/targets/modalai/hal.h b/radio/src/targets/modalai/hal.h index 570097560c2..f65772cbc27 100644 --- a/radio/src/targets/modalai/hal.h +++ b/radio/src/targets/modalai/hal.h @@ -21,11 +21,10 @@ #pragma once -#warning TODO: Verify/Set these numbers -#define CPU_FREQ 600000000 +#define CPU_FREQ 400000000 -#define PERI1_FREQUENCY 150000000 -#define PERI2_FREQUENCY 150000000 +#define PERI1_FREQUENCY 100000000 +#define PERI2_FREQUENCY 100000000 #define TIMER_MULT_APB1 2 #define TIMER_MULT_APB2 2 @@ -50,10 +49,10 @@ // Keys -#define KEYS_GPIO_REG_PAGEUP GPIOD -#define KEYS_GPIO_PIN_PAGEUP LL_GPIO_PIN_14 // PD.14 -#define KEYS_GPIO_REG_PAGEDN GPIOH -#define KEYS_GPIO_PIN_PAGEDN LL_GPIO_PIN_6 // PH.06 +#define KEYS_GPIO_REG_PAGEUP GPIOH +#define KEYS_GPIO_PIN_PAGEUP LL_GPIO_PIN_6 // PH.06 +#define KEYS_GPIO_REG_PAGEDN GPIOD +#define KEYS_GPIO_PIN_PAGEDN LL_GPIO_PIN_14 // PD.14 #define KEYS_GPIO_REG_EXIT GPIOD #define KEYS_GPIO_PIN_EXIT LL_GPIO_PIN_11 // PD.11 #define KEYS_GPIO_REG_ENTER GPIOB @@ -71,7 +70,7 @@ #define ROTARY_ENCODER_GPIO GPIOC #define ROTARY_ENCODER_GPIO_PIN_A LL_GPIO_PIN_1 // PC.01 #define ROTARY_ENCODER_GPIO_PIN_B LL_GPIO_PIN_2 // PC.02 -#define ROTARY_ENCODER_POSITION() (((ROTARY_ENCODER_GPIO->IDR >> 8) & 0x02) + ((ROTARY_ENCODER_GPIO->IDR >> 12) & 0x01)) +#define ROTARY_ENCODER_POSITION() (((ROTARY_ENCODER_GPIO->IDR >> 1) & 0x02) + ((ROTARY_ENCODER_GPIO->IDR >> 1) & 0x01)) #define ROTARY_ENCODER_EXTI_LINE1 LL_EXTI_LINE_12 #define ROTARY_ENCODER_EXTI_LINE2 LL_EXTI_LINE_9 #define ROTARY_ENCODER_EXTI_PORT LL_SYSCFG_EXTI_PORTC @@ -149,6 +148,7 @@ #warning consider changing sample time (seems low) #define ADC_SAMPTIME LL_ADC_SAMPLINGTIME_8CYCLES_5 #define ADC_CHANNEL_RTC_BAT LL_ADC_CHANNEL_VBAT +#define ADC_VREF_PREC2 330 #define ADC_MAIN ADC1 #define ADC_DMA DMA1 @@ -176,7 +176,6 @@ #define ADC_GPIOC_PINS (ADC_GPIO_PIN_STICK_LH) #define ADC_GPIOF_PINS (ADC_GPIO_PIN_STICK_RH) // !#define ADC_CHANNEL_BATT LL_ADC_CHANNEL_10 -#define ADC_VREF_PREC2 330 #warning verify adc direction #define ADC_DIRECTION {-1, 1, 1, -1, -1, 1, 1, 1} diff --git a/radio/src/targets/modalai/system_clock.cpp b/radio/src/targets/modalai/system_clock.cpp index 87506638bfe..f5d5b1efae0 100644 --- a/radio/src/targets/modalai/system_clock.cpp +++ b/radio/src/targets/modalai/system_clock.cpp @@ -19,10 +19,12 @@ * GNU General Public License for more details. */ -#include "stm32h7xx_ll_pwr.h" -#include "stm32h7xx_ll_rcc.h" +#include "stm32h7xx_hal_rcc.h" +#include "stm32h7xx_hal_pwr.h" +#include "stm32h7xx_hal_pwr_ex.h" +#include "stm32h7xx_hal_flash_ex.h" #include "stm32h7xx_ll_system.h" -#include "stm32h7xx_ll_bus.h" +#include "stm32h7xx_ll_rcc.h" #define BOOTSTRAP __attribute__((section(".bootstrap"))) @@ -37,9 +39,9 @@ * D2 APB1 Prescaler = 2 (APB1 Clock 100MHz) * D2 APB2 Prescaler = 2 (APB2 Clock 100MHz) * D3 APB4 Prescaler = 2 (APB4 Clock 100MHz) - * HSE Frequency(Hz) = 25000000 - * PLL_M = 5 - * PLL_N = 160 + * HSE Frequency(Hz) = 16000000 + * PLL_M = 2 + * PLL_N = 100 * PLL_P = 2 * PLL_Q = 4 * PLL_R = 2 @@ -51,99 +53,106 @@ extern "C" BOOTSTRAP void SystemClock_Config() { -// /* Power Configuration */ -// LL_PWR_ConfigSupply(LL_PWR_DIRECT_SMPS_SUPPLY); -// while (LL_PWR_IsActiveFlag_ACTVOSRDY() == 0) { -// } -// LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE0); -// while (LL_PWR_IsActiveFlag_VOSRDY() == 0) { -// } - -// /* Enable HSE oscillator */ -// LL_RCC_HSE_Enable(); -// while (LL_RCC_HSE_IsReady() != 1) { -// } - -// /* Set FLASH latency */ -// LL_FLASH_SetLatency(LL_FLASH_LATENCY_6); - -// /* Main PLL configuration and activation */ -// LL_RCC_PLL_SetSource(LL_RCC_PLLSOURCE_HSE); -// LL_RCC_PLL1P_Enable(); -// // LL_RCC_PLL1Q_Enable(); -// // LL_RCC_PLL1R_Enable(); -// LL_RCC_PLL1FRACN_Disable(); -// LL_RCC_PLL1_SetVCOInputRange(LL_RCC_PLLINPUTRANGE_2_4); -// LL_RCC_PLL1_SetVCOOutputRange(LL_RCC_PLLVCORANGE_WIDE); -// LL_RCC_PLL1_SetM(2); -// LL_RCC_PLL1_SetN(50); -// LL_RCC_PLL1_SetP(1); -// // LL_RCC_PLL1_SetQ(2); -// // LL_RCC_PLL1_SetR(2); -// // LL_RCC_PLL1_SetS(2); -// LL_RCC_PLL1_Enable(); -// while (LL_RCC_PLL1_IsReady() != 1) { -// } - -// /* Set Sys & AHB & APB1 & APB2 & APB4 prescaler */ -// LL_RCC_SetSysPrescaler(LL_RCC_SYSCLK_DIV_1); -// LL_RCC_SetAHBPrescaler(LL_RCC_AHB_DIV_2); -// LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_2); -// LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_2); -// LL_RCC_SetAPB4Prescaler(LL_RCC_APB4_DIV_2); - -// /* Set PLL1 as System Clock Source */ -// LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL1); -// while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL1) { -// } - -// /* PLL2 configuration and activation */ -// LL_RCC_PLL2S_Enable(); -// LL_RCC_PLL2Q_Enable(); -// LL_RCC_PLL2FRACN_Disable(); -// LL_RCC_PLL2_SetVCOInputRange(LL_RCC_PLLINPUTRANGE_2_4); -// LL_RCC_PLL2_SetVCOOutputRange(LL_RCC_PLLVCORANGE_WIDE); -// LL_RCC_PLL2_SetM(2); -// LL_RCC_PLL2_SetN(64); -// LL_RCC_PLL2_SetP(2); // disabled -// LL_RCC_PLL2_SetQ(47); // 16.340 MHz -// LL_RCC_PLL2_SetR(2); // disabled -// LL_RCC_PLL2_SetS(4); // 192 MHz -// LL_RCC_PLL2_Enable(); -// while (LL_RCC_PLL2_IsReady() != 1) { -// } - -// /* PLL2 configuration and activation */ -// LL_RCC_PLL3R_Enable(); -// LL_RCC_PLL3FRACN_Disable(); -// LL_RCC_PLL3_SetVCOInputRange(LL_RCC_PLLINPUTRANGE_4_8); -// LL_RCC_PLL3_SetVCOOutputRange(LL_RCC_PLLVCORANGE_WIDE); -// LL_RCC_PLL3_SetM(2); -// LL_RCC_PLL3_SetN(50); -// LL_RCC_PLL3_SetP(2); -// LL_RCC_PLL3_SetQ(2); -// LL_RCC_PLL3_SetR(24); -// LL_RCC_PLL3_Enable(); -// while (LL_RCC_PLL3_IsReady() != 1) { -// } - -// #if defined(USE_USB_HS) -// LL_RCC_SetUSBPHYCClockSource(LL_RCC_USBPHYC_CLKSOURCE_HSE); -// LL_RCC_SetUSBREFClockSource(LL_RCC_USBREF_CLKSOURCE_24M); -// #else -// LL_RCC_HSI48_Enable(); -// while (LL_RCC_HSI48_IsReady() != 1) { -// } -// LL_RCC_SetOTGFSClockSource(LL_RCC_OTGFS_CLKSOURCE_HSI48); -// #endif - -// // 192 MHz -// LL_RCC_SetXSPIClockSource(LL_RCC_XSPI1_CLKSOURCE_PLL2S); -// LL_RCC_SetXSPIClockSource(LL_RCC_XSPI2_CLKSOURCE_PLL2S); - -// // 16.340 MHz -// LL_RCC_SetSPIClockSource(LL_RCC_SPI6_CLKSOURCE_PLL2Q); - -// // Only required if using Async ADC clock ??? -// LL_RCC_SetADCClockSource(LL_RCC_ADC_CLKSOURCE_CLKP); + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + + /** Supply configuration update enable + */ + HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); + + /** Configure the main internal regulator output voltage + */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 2; + RCC_OscInitStruct.PLL.PLLN = 100; + RCC_OscInitStruct.PLL.PLLP = 2; + RCC_OscInitStruct.PLL.PLLQ = 4; + RCC_OscInitStruct.PLL.PLLR = 2; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_3; + RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; + RCC_OscInitStruct.PLL.PLLFRACN = 0; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + while(1) {}; + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 + |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; + RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; + RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) + { + while(1) {}; + } + + /** Enables the Clock Security System + */ + HAL_RCC_EnableCSS(); + + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SPI4; + PeriphClkInitStruct.PLL2.PLL2M = 4; + PeriphClkInitStruct.PLL2.PLL2N = 128; + PeriphClkInitStruct.PLL2.PLL2P = 2; + PeriphClkInitStruct.PLL2.PLL2Q = 32; + PeriphClkInitStruct.PLL2.PLL2R = 20; + PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_2; + PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE; + PeriphClkInitStruct.PLL2.PLL2FRACN = 0; + PeriphClkInitStruct.Spi45ClockSelection = RCC_SPI45CLKSOURCE_PLL2; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + while(1) {}; + } + +// PeriphClkInitStruct.PLL3.PLL3M = 4; +// PeriphClkInitStruct.PLL3.PLL3N = 128; +// PeriphClkInitStruct.PLL3.PLL3P = 2; +// PeriphClkInitStruct.PLL3.PLL3Q = 8; +// PeriphClkInitStruct.PLL3.PLL3R = 20; +// PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3VCIRANGE_2; +// PeriphClkInitStruct.PLL3.PLL3FRACN = 0; +// if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) +// { +// while(1) {}; +// } + + /** Enables the Clock Security System + */ + HAL_RCC_EnableCSS(); + + LL_RCC_PLL2_Enable(); + while (LL_RCC_PLL2_IsReady() != 1) { + } + + LL_RCC_PLL3_Enable(); + while (LL_RCC_PLL3_IsReady() != 1) { + } + + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + while(1) {}; + } } From 75f609764a6f4571d6fb6bf6ea04cdf8c5dcd0d6 Mon Sep 17 00:00:00 2001 From: Maxwell Schaefer Date: Thu, 27 Mar 2025 15:16:58 -0700 Subject: [PATCH 10/54] Added battery voltage monitoring over i2c --- radio/src/CMakeLists.txt | 7 +- .../linker/stm32h753/bootloader/layout.ld | 2 +- radio/src/hal/adc_driver.cpp | 47 ++++++++++ .../common/arm/stm32/h7/CMakeLists.txt | 2 +- .../common/arm/stm32/stm32h7xx_hal_conf.h | 2 +- radio/src/targets/modalai/board.cpp | 25 +----- radio/src/targets/modalai/hal.h | 69 +++++--------- radio/src/targets/modalai/lcd_driver_spi.cpp | 84 ++++++++--------- radio/src/targets/modalai/system_clock.cpp | 90 +++++++++---------- radio/src/targets/modalai/system_init.cpp | 20 +++-- .../src/targets/modalai/voxlpm_i2c_driver.cpp | 3 +- 11 files changed, 172 insertions(+), 179 deletions(-) diff --git a/radio/src/CMakeLists.txt b/radio/src/CMakeLists.txt index b363e823e41..82396f55ddf 100644 --- a/radio/src/CMakeLists.txt +++ b/radio/src/CMakeLists.txt @@ -12,7 +12,7 @@ set_property(CACHE TRANSLATIONS PROPERTY STRINGS ${RADIO_LANGUAGES}) set(DEFAULT_MODE "" CACHE STRING "Default sticks mode") set(POPUP_LEVEL 2 CACHE STRING "Popup level") -option(HELI "Heli menu" ON) +option(HELI "Heli menu" OFF) option(FLIGHT_MODES "Flight Modes" ON) option(CURVES "Curves" ON) option(GVARS "Global variables" ON) @@ -28,6 +28,9 @@ option(SEMIHOSTING "Enable debugger semihosting" OFF) option(JITTER_MEASURE "Enable ADC jitter measurement" OFF) option(WATCHDOG "Enable hardware Watchdog" ON) option(ASTERISK "Enable asterisk icon (test only firmware)" OFF) +if(SDL2_FOUND) + option(SIMU_AUDIO "Enable simulator audio." ON) +endif() option(LUA "Enable LUA support" ON) option(SIMU_DISKIO "Enable disk IO simulation in simulator. Simulator will use FatFs module and simulated IO layer that uses \"./sdcard.image\" file as image of SD card. This file must contain whole SD card from first to last sector" OFF) option(SIMU_LUA_COMPILER "Pre-compile and save Lua scripts in simulator." ON) @@ -550,7 +553,7 @@ find_program(BASH bash set(OPT "s" CACHE STRING "Optimization mode (0/1/2/s)") set(COMMON_FLAGS "-mcpu=${MCU} -mthumb -fomit-frame-pointer -fverbose-asm -Wa,-ahlms=firmware.lst") -set(COMMON_FLAGS "${COMMON_FLAGS} -gdwarf-2 -fno-exceptions -fdata-sections -ffunction-sections") +set(COMMON_FLAGS "${COMMON_FLAGS} -ggdb -fno-exceptions -fdata-sections -ffunction-sections") set(COMMON_FLAGS "${COMMON_FLAGS} -DHSE_VALUE=${HSE_VALUE}") set(COMMON_FLAGS "${COMMON_FLAGS} -O${OPT} ${FPU_FLAGS}") set(COMMON_FLAGS "${COMMON_FLAGS} ${WARNING_FLAGS}") diff --git a/radio/src/boards/generic_stm32/linker/stm32h753/bootloader/layout.ld b/radio/src/boards/generic_stm32/linker/stm32h753/bootloader/layout.ld index 8de0437b8dc..e1c519ec395 100644 --- a/radio/src/boards/generic_stm32/linker/stm32h753/bootloader/layout.ld +++ b/radio/src/boards/generic_stm32/linker/stm32h753/bootloader/layout.ld @@ -25,7 +25,7 @@ MEMORY } REGION_ALIAS("REGION_TEXT_STORAGE", FLASH); -REGION_ALIAS("REGION_TEXT", ITCMRAM); +REGION_ALIAS("REGION_TEXT", FLASH); REGION_ALIAS("REGION_ISR_VECT", DTCMRAM); REGION_ALIAS("REGION_DATA", DTCMRAM); REGION_ALIAS("REGION_BSS", RAM_D1); diff --git a/radio/src/hal/adc_driver.cpp b/radio/src/hal/adc_driver.cpp index 7cf26e888c0..2c0daab40e7 100644 --- a/radio/src/hal/adc_driver.cpp +++ b/radio/src/hal/adc_driver.cpp @@ -32,6 +32,12 @@ const etx_hal_adc_inputs_t* _hal_adc_inputs = nullptr; static uint16_t adcValues[MAX_ANALOG_INPUTS] __DMA_NO_CACHE; +#if defined(RADIO_MODAL) +#include "voxlpm_i2c_driver.h" +#elif defined(CSD203_SENSOR) + extern uint16_t getCSD203BatteryVoltage(void); +#endif + bool adcInit(const etx_hal_adc_driver_t* driver) { // Init buffer, provides non random values before mixer task starts @@ -299,6 +305,47 @@ JitterMeter avgJitter[MAX_ANALOG_INPUTS]; tmr10ms_t jitterResetTime = 0; #endif +uint16_t getBatteryVoltage() +{ +#if defined(RADIO_MODAL) +#if defined(POWER_I2C) + return voxl_pm_get_voltage(); +#else + return 500; +#endif +#elif defined(CSD203_SENSOR) && !defined(SIMU) + return getCSD203BatteryVoltage() / 10; +#else + // using filtered ADC value on purpose + if (adcGetMaxInputs(ADC_INPUT_VBAT) < 1) return 0; + int32_t instant_vbat = anaIn(adcGetInputOffset(ADC_INPUT_VBAT)); + + // TODO: remove BATT_SCALE / BATTERY_DIVIDER defines +#if defined(VBAT_MOSFET_DROP) + // 1000 is used as multiplier for both numerator and denominator to allow to stay in integer domain + return (uint16_t)((instant_vbat * ADC_VREF_PREC2 * ((((1000 + g_eeGeneral.txVoltageCalibration)) * (VBAT_DIV_R2 + VBAT_DIV_R1)) / VBAT_DIV_R1)) / (2*RESX*1000)) + VBAT_MOSFET_DROP; +#elif defined(BATT_SCALE) + instant_vbat = + (instant_vbat * BATT_SCALE * (128 + g_eeGeneral.txVoltageCalibration)) / + BATTERY_DIVIDER; + // add voltage drop because of the diode TODO check if this is needed, but + // removal will break existing calibrations! + instant_vbat += VOLTAGE_DROP; + return (uint16_t)instant_vbat; +#elif defined(VOLTAGE_DROP) + instant_vbat = ((instant_vbat * (1000 + g_eeGeneral.txVoltageCalibration)) / + BATTERY_DIVIDER); + // add voltage drop because of the diode + // removal will break existing calibrations! + instant_vbat += VOLTAGE_DROP; + return (uint16_t)instant_vbat; +#else + return (uint16_t)((instant_vbat * (1000 + g_eeGeneral.txVoltageCalibration)) / + BATTERY_DIVIDER); +#endif +#endif +} + static uint32_t apply_low_pass_filter(uint32_t v, uint32_t v_prev, bool is_main_input) { diff --git a/radio/src/targets/common/arm/stm32/h7/CMakeLists.txt b/radio/src/targets/common/arm/stm32/h7/CMakeLists.txt index 2b0e950e532..863877ca033 100644 --- a/radio/src/targets/common/arm/stm32/h7/CMakeLists.txt +++ b/radio/src/targets/common/arm/stm32/h7/CMakeLists.txt @@ -1,6 +1,6 @@ set(CPU_FAMILY STM32) set(MCU cortex-m7) -set(FPU_FLAGS "-mfloat-abi=hard -mfpu=fpv4-sp-d16") +set(FPU_FLAGS "-mfpu=fpv4-sp-d16 -mfloat-abi=hard") # CMSIS library set(CMSIS_DIR ${THIRDPARTY_DIR}/CMSIS) diff --git a/radio/src/targets/common/arm/stm32/stm32h7xx_hal_conf.h b/radio/src/targets/common/arm/stm32/stm32h7xx_hal_conf.h index d2649803165..01af4e73d6d 100644 --- a/radio/src/targets/common/arm/stm32/stm32h7xx_hal_conf.h +++ b/radio/src/targets/common/arm/stm32/stm32h7xx_hal_conf.h @@ -94,7 +94,7 @@ #define HAL_SPI_MODULE_ENABLED // #define HAL_SRAM_MODULE_ENABLED // #define HAL_SWPMI_MODULE_ENABLED -// #define HAL_TIM_MODULE_ENABLED +//#define HAL_TIM_MODULE_ENABLED // #define HAL_UART_MODULE_ENABLED // #define HAL_USART_MODULE_ENABLED // #define HAL_WWDG_MODULE_ENABLED diff --git a/radio/src/targets/modalai/board.cpp b/radio/src/targets/modalai/board.cpp index ef10b2ccc06..926267ac1b3 100644 --- a/radio/src/targets/modalai/board.cpp +++ b/radio/src/targets/modalai/board.cpp @@ -80,31 +80,8 @@ void boardInit() // SCB_EnableDCache(); - RCC->D3CFGR = (0x5 << 4); - RCC->APB4ENR |= RCC_APB4ENR_SPI6EN; - - // Setup pll1 - RCC->PLL1DIVR |= (0xA0000U & RCC_PLL1DIVR_Q1_Msk); // Set prescaler to 6 (~21 MHz after scaling) - RCC->CR |= RCC_CR_PLL1ON; - while (RCC->CR & RCC_CR_PLL1ON == 0) { } - - // Setup pll2 - RCC->PLLCKSELR &= ~(0x10000 & RCC_PLLCKSELR_DIVM2); - RCC->PLLCKSELR |= (0x10000 & RCC_PLLCKSELR_DIVM2); - // DIVN2 = 200 - // DIVP2 = 8 - RCC->PLL2DIVR |= ((0x1000 & RCC_PLL2DIVR_P2) | (0xC8 & RCC_PLL2DIVR_N2)); - RCC->CR |= RCC_CR_PLL2ON; - while (RCC->CR & RCC_CR_PLL2ON == 0) { } - - // Select UART clock source as HSI: - RCC->D2CCIP2R &= ~(0x18); - RCC->D2CCIP2R |= 0x18; - #if defined(POWER_I2C) - voxl_pm_init(); - #endif @@ -155,7 +132,7 @@ void boardInit() lcdInit(); // delaysInit() must be called before timersInit(); - // usbInit(); + usbInit(); #if defined(DEBUG) && defined(AUX_SERIAL) serialSetMode(SP_AUX1, UART_MODE_DEBUG); // indicate AUX1 is used diff --git a/radio/src/targets/modalai/hal.h b/radio/src/targets/modalai/hal.h index f65772cbc27..3f404c7d060 100644 --- a/radio/src/targets/modalai/hal.h +++ b/radio/src/targets/modalai/hal.h @@ -31,11 +31,12 @@ #define TELEMETRY_EXTI_PRIO 0 // required for soft serial /* Timers Allocation: + * TIM7 = Rotary Encoder + * * TIM5 = Backlight - * TIM7 = 2 MHz counter * * TIM12 = Mixer scheduler - * TIM14 = 5 ms counter + * TIM14 = 5 ms counter (unused) */ /* DMA Allocation: @@ -71,8 +72,8 @@ #define ROTARY_ENCODER_GPIO_PIN_A LL_GPIO_PIN_1 // PC.01 #define ROTARY_ENCODER_GPIO_PIN_B LL_GPIO_PIN_2 // PC.02 #define ROTARY_ENCODER_POSITION() (((ROTARY_ENCODER_GPIO->IDR >> 1) & 0x02) + ((ROTARY_ENCODER_GPIO->IDR >> 1) & 0x01)) -#define ROTARY_ENCODER_EXTI_LINE1 LL_EXTI_LINE_12 -#define ROTARY_ENCODER_EXTI_LINE2 LL_EXTI_LINE_9 +#define ROTARY_ENCODER_EXTI_LINE1 LL_EXTI_LINE_1 +#define ROTARY_ENCODER_EXTI_LINE2 LL_EXTI_LINE_2 #define ROTARY_ENCODER_EXTI_PORT LL_SYSCFG_EXTI_PORTC #define ROTARY_ENCODER_EXTI_SYS_LINE1 LL_SYSCFG_EXTI_LINE1 #define ROTARY_ENCODER_EXTI_SYS_LINE2 LL_SYSCFG_EXTI_LINE2 @@ -87,34 +88,12 @@ #endif #define ROTARY_ENCODER_INVERTED -#define ROTARY_ENCODER_TIMER TIM5 -#define ROTARY_ENCODER_TIMER_IRQn TIM5_IRQn -#define ROTARY_ENCODER_TIMER_IRQHandler TIM5_IRQHandler - -// Trims -// #warning Disconnect all of these -// #define TRIMS_GPIO_REG_LHL GPIOH -// #define TRIMS_GPIO_PIN_LHL LL_GPIO_PIN_15 // PH.15 -// #define TRIMS_GPIO_REG_LHR GPIOH -// #define TRIMS_GPIO_PIN_LHR LL_GPIO_PIN_15 // PH.15 -// #define TRIMS_GPIO_REG_LVD GPIOH -// #define TRIMS_GPIO_PIN_LVD LL_GPIO_PIN_15 // PH.15 -// #define TRIMS_GPIO_REG_LVU GPIOH -// #define TRIMS_GPIO_PIN_LVU LL_GPIO_PIN_15 // PH.15 -// #define TRIMS_GPIO_REG_RVD GPIOH -// #define TRIMS_GPIO_PIN_RVD LL_GPIO_PIN_15 // PH.15 -// #define TRIMS_GPIO_REG_RHL GPIOH -// #define TRIMS_GPIO_PIN_RHL LL_GPIO_PIN_15 // PH.15 -// #define TRIMS_GPIO_REG_RVU GPIOH -// #define TRIMS_GPIO_PIN_RVU LL_GPIO_PIN_15 // PH.15 -// #define TRIMS_GPIO_REG_RHR GPIOH -// #define TRIMS_GPIO_PIN_RHR LL_GPIO_PIN_15 // PH.15 +#define ROTARY_ENCODER_TIMER TIM7 +#define ROTARY_ENCODER_TIMER_IRQn TIM7_IRQn +#define ROTARY_ENCODER_TIMER_IRQHandler TIM7_IRQHandler + // Switches -// #define STORAGE_SWITCH_A -// #define HARDWARE_SWITCH_A -// #define SWITCHES_GPIO_REG_A GPIOG -// #define SWITCHES_GPIO_PIN_A LL_GPIO_PIN_2 // PG.02 #define STORAGE_SWITCH_B #define HARDWARE_SWITCH_B @@ -130,11 +109,6 @@ #define SWITCHES_GPIO_REG_C_H GPIOH #define SWITCHES_GPIO_PIN_C_H LL_GPIO_PIN_12 // PH.12 -// #define STORAGE_SWITCH_D -// #define HARDWARE_SWITCH_D -// #define SWITCHES_GPIO_REG_D GPIOG -// #define SWITCHES_GPIO_PIN_D LL_GPIO_PIN_3 // PG.3 - #define STORAGE_SWITCH_E #define HARDWARE_SWITCH_E #define SWITCHES_GPIO_REG_E GPIOE @@ -145,7 +119,8 @@ #define SWITCHES_GPIO_REG_F GPIOF #define SWITCHES_GPIO_PIN_F LL_GPIO_PIN_10 // PF.10 -#warning consider changing sample time (seems low) +// Sticks and pots + #define ADC_SAMPTIME LL_ADC_SAMPLINGTIME_8CYCLES_5 #define ADC_CHANNEL_RTC_BAT LL_ADC_CHANNEL_VBAT #define ADC_VREF_PREC2 330 @@ -176,7 +151,6 @@ #define ADC_GPIOC_PINS (ADC_GPIO_PIN_STICK_LH) #define ADC_GPIOF_PINS (ADC_GPIO_PIN_STICK_RH) // !#define ADC_CHANNEL_BATT LL_ADC_CHANNEL_10 -#warning verify adc direction #define ADC_DIRECTION {-1, 1, 1, -1, -1, 1, 1, 1} // PWR and LED driver @@ -187,7 +161,6 @@ #define USE_LEDS #ifdef USE_LEDS -#warning remove these later #define STATUS_LEDS #define GPIO_LED_GPIO_ON gpio_clear #define GPIO_LED_GPIO_OFF gpio_set @@ -197,14 +170,14 @@ #endif // USE_LEDS // Internal Module -#define INTMODULE_BOOTCMD_GPIO GPIO_PIN(GPIOI, 6) // PI.06 (Disconnected) -#define INTMODULE_PWR_GPIO GPIO_PIN(GPIOI, 7) // PI.07 (Disconnected) +#define INTMODULE_BOOTCMD_GPIO GPIO_PIN(GPIOE, 13) // PE.13 (Disconnected) +#define INTMODULE_PWR_GPIO GPIO_PIN(GPIOG, 8) // PG.08 (Disconnected) #define INTMODULE_BOOTCMD_DEFAULT 0 // RESET -#define INTMODULE_TX_GPIO GPIO_PIN(GPIOC, 6) // PC.06 -#define INTMODULE_RX_GPIO GPIO_PIN(GPIOC, 7) // PC.07 -#define INTMODULE_USART USART6 -#define INTMODULE_USART_IRQHandler USART6_IRQHandler -#define INTMODULE_USART_IRQn USART6_IRQn +#define INTMODULE_TX_GPIO GPIO_PIN(GPIOB, 13) // PB.13 +#define INTMODULE_RX_GPIO GPIO_PIN(GPIOB, 12) // PB.12 +#define INTMODULE_USART UART5 +#define INTMODULE_USART_IRQHandler UART5_IRQHandler +#define INTMODULE_USART_IRQn UART5_IRQn // #define INTMODULE_DMA DMA2 // #define INTMODULE_DMA_STREAM LL_DMA_STREAM_7 // #define INTMODULE_DMA_STREAM_IRQ DMA2_Stream7_IRQn @@ -225,7 +198,7 @@ #define USB_CHARGER_GPIO GPIO_PIN(GPIOB, 5) #endif -#warning can probably increase this +// TODO: increase #define SPORT_MAX_BAUDRATE 400000 // USB @@ -235,7 +208,6 @@ #define USB_GPIO_AF GPIO_AF10 // BackLight -#warning Backlight settings (check bus and frequency) #define BACKLIGHT_TIMER_FREQ (PERI1_FREQUENCY * TIMER_MULT_APB1) #define BACKLIGHT_TIMER TIM5 #define BACKLIGHT_GPIO GPIO_PIN(GPIOH, 10) // PH.10 @@ -354,7 +326,7 @@ #define VOXLPM_INA231_VBAT_I_LSB (VOXLPM_INA231_VBAT_MAX_AMPS/32768.0f) #define VOXLPM_INA231_VREG_I_LSB (VOXLPM_INA231_VREG_MAX_AMPS/32768.0f) -// #define POWER_I2C I2C1 // Comment this out to disable I2C +#define POWER_I2C I2C1 // Comment this out to disable I2C #define POWER_I2C_PIN_SDA GPIO_PIN(GPIOB, 9) // PB.09 #define POWER_I2C_SDA_AF GPIO_AF4 #define POWER_I2C_PIN_SCL GPIO_PIN(GPIOB, 8) // PB.08 @@ -376,7 +348,6 @@ #define MS_TIMER_IRQHandler TIM8_TRG_COM_TIM14_IRQHandler // Mixer scheduler timer -#warning check bus / freq #define MIXER_SCHEDULER_TIMER TIM12 #define MIXER_SCHEDULER_TIMER_FREQ (PERI1_FREQUENCY * TIMER_MULT_APB1) #define MIXER_SCHEDULER_TIMER_IRQn TIM8_BRK_TIM12_IRQn diff --git a/radio/src/targets/modalai/lcd_driver_spi.cpp b/radio/src/targets/modalai/lcd_driver_spi.cpp index c388e4916f8..425515294ba 100644 --- a/radio/src/targets/modalai/lcd_driver_spi.cpp +++ b/radio/src/targets/modalai/lcd_driver_spi.cpp @@ -31,50 +31,44 @@ #include "hal/abnormal_reboot.h" #include "timers_driver.h" - #if !defined(BOOT) - #include "edgetx.h" - #endif - - #if defined(OLED_SCREEN) - #define LCD_CONTRAST_OFFSET 0 - #elif defined(RADIO_FAMILY_JUMPER_T12) || defined(MANUFACTURER_RADIOMASTER) || defined(RADIO_COMMANDO8) || defined(RADIO_TPRO) || defined(RADIO_T12MAX) || defined(RADIO_V12) || defined(RADIO_V14) - #define LCD_CONTRAST_OFFSET -10 - #else - #define LCD_CONTRAST_OFFSET 160 - #endif - #define RESET_WAIT_DELAY_MS 300 // Wait time after LCD reset before first command - #define WAIT_FOR_DMA_END() do { } while (lcd_busy) - - #define LCD_NCS_HIGH() gpio_set(LCD_NCS_GPIO) - #define LCD_NCS_LOW() gpio_clear(LCD_NCS_GPIO) - - #define LCD_A0_HIGH() gpio_set(LCD_A0_GPIO) - #define LCD_A0_LOW() gpio_clear(LCD_A0_GPIO) - - #define LCD_RST_HIGH() gpio_set(LCD_RST_GPIO) - #define LCD_RST_LOW() gpio_clear(LCD_RST_GPIO) +#if !defined(BOOT) + #include "edgetx.h" +#endif - bool lcdInitFinished = false; - void lcdInitFinish(); +#define LCD_CONTRAST_OFFSET -10 +#define RESET_WAIT_DELAY_MS 300 // Wait time after LCD reset before first command +#define WAIT_FOR_DMA_END() do { } while (lcd_busy) + +#define LCD_NCS_HIGH() gpio_set(LCD_NCS_GPIO) +#define LCD_NCS_LOW() gpio_clear(LCD_NCS_GPIO) + +#define LCD_A0_HIGH() gpio_set(LCD_A0_GPIO) +#define LCD_A0_LOW() gpio_clear(LCD_A0_GPIO) + +#define LCD_RST_HIGH() gpio_set(LCD_RST_GPIO) +#define LCD_RST_LOW() gpio_clear(LCD_RST_GPIO) + +bool lcdInitFinished = false; +void lcdInitFinish(); - void lcdWriteCommand(uint8_t byte) - { - LCD_A0_LOW(); - LCD_NCS_LOW(); - while ((LCD_SPI->SR & SPI_SR_TXC) == 0) { - // Wait - } - //(void)LCD_SPI->RXDR; // Clear receive - *((volatile uint8_t *)&LCD_SPI->TXDR) = byte; // Must limit to 8-bit bus transaction - LCD_SPI->CR1 |= SPI_CR1_CSTART; - while ((LCD_SPI->SR & SPI_SR_TXC) == 0) { - // Wait - } - LCD_NCS_HIGH(); - } +void lcdWriteCommand(uint8_t byte) +{ + LCD_A0_LOW(); + LCD_NCS_LOW(); + while ((LCD_SPI->SR & SPI_SR_TXC) == 0) { + // Wait + } + //(void)LCD_SPI->RXDR; // Clear receive + *((volatile uint8_t *)&LCD_SPI->TXDR) = byte; // Must limit to 8-bit bus transaction + LCD_SPI->CR1 |= SPI_CR1_CSTART; + while ((LCD_SPI->SR & SPI_SR_TXC) == 0) { + // Wait + } + LCD_NCS_HIGH(); +} - void lcdHardwareInit() - { +void lcdHardwareInit() +{ stm32_spi_enable_clock(LCD_SPI); gpio_init_af(LCD_MOSI_GPIO, LCD_GPIO_AF, GPIO_PIN_SPEED_VERY_HIGH); gpio_init_af(LCD_CLK_GPIO, LCD_GPIO_AF, GPIO_PIN_SPEED_VERY_HIGH); @@ -101,17 +95,17 @@ LCD_DMA_Stream->CR = DMA_SxCR_PL_0 | DMA_SxCR_MINC | DMA_SxCR_DIR_0; LCD_DMA_Stream->PAR = (uint32_t)&LCD_SPI->TXDR; LL_DMA_SetPeriphRequest(LCD_DMA, LCD_DMA_Stream_Num, LL_DMAMUX1_REQ_SPI4_TX); - #if LCD_W == 128 +#if LCD_W == 128 LCD_DMA_Stream->NDTR = LCD_W; - #else +#else LCD_DMA_Stream->M0AR = (uint32_t)displayBuf; LCD_DMA_Stream->NDTR = LCD_W*LCD_H/8*4; - #endif +#endif LCD_DMA_Stream->FCR = DMA_SxFCR_DMDIS | DMA_SxFCR_FTH_0; NVIC_SetPriority(LCD_DMA_Stream_IRQn, 7); NVIC_EnableIRQ(LCD_DMA_Stream_IRQn); - } +} void lcdStart() { diff --git a/radio/src/targets/modalai/system_clock.cpp b/radio/src/targets/modalai/system_clock.cpp index f5d5b1efae0..b719ab55b38 100644 --- a/radio/src/targets/modalai/system_clock.cpp +++ b/radio/src/targets/modalai/system_clock.cpp @@ -19,6 +19,7 @@ * GNU General Public License for more details. */ +#include "stm32h7xx_hal.h" #include "stm32h7xx_hal_rcc.h" #include "stm32h7xx_hal_pwr.h" #include "stm32h7xx_hal_pwr_ex.h" @@ -54,7 +55,6 @@ extern "C" BOOTSTRAP void SystemClock_Config() { RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; /** Supply configuration update enable */ @@ -87,55 +87,46 @@ void SystemClock_Config() while(1) {}; } - /** Initializes the CPU, AHB and APB buses clocks - */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK - |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 - |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; - RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; - RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; - RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; - RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; - - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) - { - while(1) {}; + /* Set Sys & AHB & APB1 & APB2 & APB4 prescaler */ + LL_RCC_SetSysPrescaler(LL_RCC_SYSCLK_DIV_1); + LL_RCC_SetAHBPrescaler(LL_RCC_AHB_DIV_2); + LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_2); + LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_2); + LL_RCC_SetAPB3Prescaler(LL_RCC_APB3_DIV_2); + LL_RCC_SetAPB4Prescaler(LL_RCC_APB4_DIV_2); + + /* Set PLL1 as System Clock Source */ + LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL1); + while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL1) { } - /** Enables the Clock Security System - */ - HAL_RCC_EnableCSS(); - - RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SPI4; - PeriphClkInitStruct.PLL2.PLL2M = 4; - PeriphClkInitStruct.PLL2.PLL2N = 128; - PeriphClkInitStruct.PLL2.PLL2P = 2; - PeriphClkInitStruct.PLL2.PLL2Q = 32; - PeriphClkInitStruct.PLL2.PLL2R = 20; - PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_2; - PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE; - PeriphClkInitStruct.PLL2.PLL2FRACN = 0; - PeriphClkInitStruct.Spi45ClockSelection = RCC_SPI45CLKSOURCE_PLL2; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) - { - while(1) {}; + /* PLL2 configuration and activation */ + LL_RCC_PLL2R_Enable(); + LL_RCC_PLL2Q_Enable(); + LL_RCC_PLL2FRACN_Disable(); + LL_RCC_PLL2_SetVCOInputRange(LL_RCC_PLLINPUTRANGE_4_8); + LL_RCC_PLL2_SetVCOOutputRange(LL_RCC_PLLVCORANGE_WIDE); + LL_RCC_PLL2_SetM(4); + LL_RCC_PLL2_SetN(128); + LL_RCC_PLL2_SetP(2); + LL_RCC_PLL2_SetQ(8); + LL_RCC_PLL2_SetR(20); + LL_RCC_PLL2_Enable(); + while (LL_RCC_PLL2_IsReady() != 1) { } -// PeriphClkInitStruct.PLL3.PLL3M = 4; -// PeriphClkInitStruct.PLL3.PLL3N = 128; -// PeriphClkInitStruct.PLL3.PLL3P = 2; -// PeriphClkInitStruct.PLL3.PLL3Q = 8; -// PeriphClkInitStruct.PLL3.PLL3R = 20; -// PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3VCIRANGE_2; -// PeriphClkInitStruct.PLL3.PLL3FRACN = 0; -// if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) -// { -// while(1) {}; -// } + LL_RCC_PLL3R_Enable(); + LL_RCC_PLL3FRACN_Disable(); + LL_RCC_PLL3_SetVCOInputRange(LL_RCC_PLLINPUTRANGE_4_8); + LL_RCC_PLL3_SetVCOOutputRange(LL_RCC_PLLVCORANGE_WIDE); + LL_RCC_PLL3_SetM(4); + LL_RCC_PLL3_SetN(128); + LL_RCC_PLL3_SetP(2); + LL_RCC_PLL3_SetQ(8); + LL_RCC_PLL3_SetR(20); + LL_RCC_PLL3_Enable(); + while (LL_RCC_PLL3_IsReady() != 1) { + } /** Enables the Clock Security System */ @@ -149,10 +140,17 @@ void SystemClock_Config() while (LL_RCC_PLL3_IsReady() != 1) { } + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { while(1) {}; } + + // HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK_DIV8); + + // Only required if using Async ADC clock ??? + LL_RCC_SetADCClockSource(LL_RCC_ADC_CLKSOURCE_CLKP); + LL_RCC_SetSPIClockSource(LL_RCC_SPI45_CLKSOURCE_PCLK2); } diff --git a/radio/src/targets/modalai/system_init.cpp b/radio/src/targets/modalai/system_init.cpp index 1c00ecde61a..0a135333676 100644 --- a/radio/src/targets/modalai/system_init.cpp +++ b/radio/src/targets/modalai/system_init.cpp @@ -20,13 +20,7 @@ void Reset_Handler() "ldr sp, =_estack \n" ); -#if defined(BOOT) - asm inline ( - "bl SystemClock_Config \n" - "bl CPU_CACHE_Enable \n" - ); -#endif - + // TODO: Clock config should be first so this will go faster // Copy code into normal RAM asm inline ( "ldr r0, =_stext \n" @@ -35,12 +29,12 @@ void Reset_Handler() "bl naked_copy \n" ); -#if defined(BOOT) +// #if defined(BOOT) asm inline ( "bl SystemInit \n" "bl MPU_Init \n" ); -#endif +// #endif // Copy / setup ISR vector asm inline ( @@ -51,6 +45,14 @@ void Reset_Handler() "bl set_vtor \n" ); +#warning Clock/Cache config should stay in the bootloader only +// #if defined(BOOT) + asm inline ( + "bl SystemClock_Config \n" + "bl CPU_CACHE_Enable \n" + ); +// #endif + // Copy code into fast RAM asm inline ( "ldr r0, =_siram \n" diff --git a/radio/src/targets/modalai/voxlpm_i2c_driver.cpp b/radio/src/targets/modalai/voxlpm_i2c_driver.cpp index f248114aa4d..e1a48c64fe7 100644 --- a/radio/src/targets/modalai/voxlpm_i2c_driver.cpp +++ b/radio/src/targets/modalai/voxlpm_i2c_driver.cpp @@ -11,6 +11,7 @@ #include "boards/generic_stm32/analog_inputs.h" #include "boards/generic_stm32/rgb_leds.h" +// TODO: Make this more portable using the edgetx stm32_i2c libs #if defined(POWER_I2C) @@ -151,7 +152,7 @@ void voxl_pm_init() gpio_init_af(POWER_I2C_PIN_SCL, POWER_I2C_SCL_AF, GPIO_PIN_SPEED_HIGH); // RCC->APB1LENR |= 0x800000; // Turn on I2C3 Peripheral Clock - LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C3); + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C1); POWER_I2C->TIMINGR = POWER_I2C_TIMING_REGISTER; // Set timing values // POWER_I2C->CR1 |= I2C_CR1_ANFOFF; // Turn off analog filter From e575f239637fb0bb4ea3e7546ed184a463ca8d7b Mon Sep 17 00:00:00 2001 From: Maxwell Schaefer Date: Fri, 28 Mar 2025 15:41:48 -0700 Subject: [PATCH 11/54] Fixed bootloader and USB --- radio/src/bootloader/boot.cpp | 7 +++++++ .../targets/common/arm/stm32/usb_driver.cpp | 2 +- .../src/targets/common/arm/stm32/usbd_conf.c | 2 +- radio/src/targets/modalai/board.cpp | 20 +++++++++++++++++++ radio/src/targets/modalai/board.h | 8 +------- radio/src/targets/modalai/system_clock.cpp | 9 +++------ 6 files changed, 33 insertions(+), 15 deletions(-) diff --git a/radio/src/bootloader/boot.cpp b/radio/src/bootloader/boot.cpp index 805977d64d1..318834c4364 100644 --- a/radio/src/bootloader/boot.cpp +++ b/radio/src/bootloader/boot.cpp @@ -29,6 +29,7 @@ #include "debug.h" #include "timers_driver.h" +#include "fw_desc.h" #if defined(BLUETOOTH) #include "bluetooth_driver.h" @@ -61,8 +62,14 @@ typedef void (*fctptr_t)(void); static __attribute__((noreturn)) void jumpTo(uint32_t addr) { __disable_irq(); +#if defined(STM32H7) + firmware_description_t *fw_desc = (firmware_description_t*)APP_START_ADDRESS; + fctptr_t reset_handler = (fctptr_t) fw_desc->reset_handler; + __set_MSP((uint32_t) fw_desc->stack_address); +#else __set_MSP(*(uint32_t*)addr); fctptr_t reset_handler = (fctptr_t)*(uint32_t*)(addr + 4); +#endif reset_handler(); while(1){} } diff --git a/radio/src/targets/common/arm/stm32/usb_driver.cpp b/radio/src/targets/common/arm/stm32/usb_driver.cpp index 38d5c82719e..05679b9e621 100644 --- a/radio/src/targets/common/arm/stm32/usb_driver.cpp +++ b/radio/src/targets/common/arm/stm32/usb_driver.cpp @@ -121,7 +121,7 @@ extern "C" void OTG_FS_IRQHandler() } #endif -void usbInit() +void usbInit() { #if defined(STM32H7) HAL_PWREx_EnableUSBVoltageDetector(); diff --git a/radio/src/targets/common/arm/stm32/usbd_conf.c b/radio/src/targets/common/arm/stm32/usbd_conf.c index d080555297f..145b0dcfed2 100644 --- a/radio/src/targets/common/arm/stm32/usbd_conf.c +++ b/radio/src/targets/common/arm/stm32/usbd_conf.c @@ -45,7 +45,7 @@ /* USER CODE END PV */ PCD_HandleTypeDef hpcd_USB_OTG; -void Error_Handler(void){} +void Error_Handler(void) { } /* External functions --------------------------------------------------------*/ diff --git a/radio/src/targets/modalai/board.cpp b/radio/src/targets/modalai/board.cpp index 926267ac1b3..73b67b908c7 100644 --- a/radio/src/targets/modalai/board.cpp +++ b/radio/src/targets/modalai/board.cpp @@ -67,6 +67,24 @@ extern "C" void initialise_monitor_handles(); #include "voxlpm_i2c_driver.h" #endif +bool boardBLStartCondition() +{ +// gpio_init(BL_KEY, GPIO_IN, 0); +// return gpio_read(BL_KEY); + return false; +} + +void boardBLPreJump() +{ +} + +void boardBLInit() +{ + // TODO: register SD card or internal flash for DFU + // It may be prefered to only update via SD card firmware files + // usbRegisterDFUMedia((void*)extflash_dfu_media); +} + void boardInit() { @@ -172,6 +190,8 @@ void boardInit() void boardOff() { + // Since we have no software off switch, we should never reach this point + #if defined(STATUS_LEDS) && !defined(BOOT) ledOff(); #endif diff --git a/radio/src/targets/modalai/board.h b/radio/src/targets/modalai/board.h index b89e97e6f6d..c75dc9d5144 100644 --- a/radio/src/targets/modalai/board.h +++ b/radio/src/targets/modalai/board.h @@ -38,7 +38,7 @@ void rotaryEncoderCheck(); #define FLASHSIZE 0x80000 // 512k #define FLASH_PAGESIZE 256 -#define BOOTLOADER_SIZE 0x8000 +#define BOOTLOADER_SIZE 0x10000 #define FIRMWARE_ADDRESS 0x08000000 #define FIRMWARE_LEN(fsize) (fsize - BOOTLOADER_SIZE) #define FIRMWARE_MAX_LEN (FLASHSIZE - BOOTLOADER_SIZE) @@ -46,8 +46,6 @@ void rotaryEncoderCheck(); #define LUA_MEM_MAX (0) // max allowed memory usage for complete Lua (in bytes), 0 means unlimited -#define BOOTLOADER_KEYS 0x42 - extern uint16_t sessionTimer; @@ -106,10 +104,6 @@ extern "C" { #endif // Power driver -#define SOFT_PWR_CTRL -#if defined(PWR_BUTTON_PRESS) -# define STARTUP_ANIMATION -#endif void pwrInit(); uint32_t pwrCheck(); diff --git a/radio/src/targets/modalai/system_clock.cpp b/radio/src/targets/modalai/system_clock.cpp index b719ab55b38..c52d590f18c 100644 --- a/radio/src/targets/modalai/system_clock.cpp +++ b/radio/src/targets/modalai/system_clock.cpp @@ -140,13 +140,10 @@ void SystemClock_Config() while (LL_RCC_PLL3_IsReady() != 1) { } - RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; - PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) - { - while(1) {}; + LL_RCC_HSI48_Enable(); + while (LL_RCC_HSI48_IsReady() != 1) { } + LL_RCC_SetUSBClockSource(LL_RCC_USB_CLKSOURCE_HSI48); // HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK_DIV8); From 724b58eed89f5a1979418f7a4add82378a9c066b Mon Sep 17 00:00:00 2001 From: Maxwell Schaefer Date: Fri, 28 Mar 2025 15:44:00 -0700 Subject: [PATCH 12/54] gitignore binaries --- .gitignore | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.gitignore b/.gitignore index 6f195bb0431..242239e9e82 100644 --- a/.gitignore +++ b/.gitignore @@ -17,3 +17,5 @@ compile_commands.json /.idea /.vs CMakeUserPresets.json +.bin +.elf From 143a87f76051e7f9cd827f007ddd2bcfdd2bd695 Mon Sep 17 00:00:00 2001 From: Maxwell Schaefer Date: Fri, 28 Mar 2025 15:44:37 -0700 Subject: [PATCH 13/54] Fixed gitignore changes --- .gitignore | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.gitignore b/.gitignore index 242239e9e82..d737939f7b3 100644 --- a/.gitignore +++ b/.gitignore @@ -19,3 +19,5 @@ compile_commands.json CMakeUserPresets.json .bin .elf +**.bin +**.elf From c1c36b5cbc1f053e94b291be9d1ac56553d49cd5 Mon Sep 17 00:00:00 2001 From: Maxwell Schaefer Date: Mon, 31 Mar 2025 11:05:28 -0700 Subject: [PATCH 14/54] Fixed bootloader initialization --- radio/src/targets/modalai/CMakeLists.txt | 3 ++- radio/src/targets/modalai/board.cpp | 15 +++++++------- radio/src/targets/modalai/hal.h | 26 +++++++++++++----------- 3 files changed, 24 insertions(+), 20 deletions(-) diff --git a/radio/src/targets/modalai/CMakeLists.txt b/radio/src/targets/modalai/CMakeLists.txt index dba9daefa78..7fd87f0681a 100644 --- a/radio/src/targets/modalai/CMakeLists.txt +++ b/radio/src/targets/modalai/CMakeLists.txt @@ -111,9 +111,10 @@ endif() # Bootloader board library add_library(board_bl OBJECT EXCLUDE_FROM_ALL ${BOARD_COMMON_SRC} + ${TARGET_SRC_DIR}/system_clock.cpp ${TARGET_SRC_DIR}/bootloader/boot_menu.cpp ) -# add_dependencies(board_bl ${BITMAPS_TARGET}) +add_dependencies(board_bl ${BITMAPS_TARGET}) set(BOOTLOADER_SRC ${BOOTLOADER_SRC} $) # Firmware board library diff --git a/radio/src/targets/modalai/board.cpp b/radio/src/targets/modalai/board.cpp index 73b67b908c7..3f094d9ad37 100644 --- a/radio/src/targets/modalai/board.cpp +++ b/radio/src/targets/modalai/board.cpp @@ -22,6 +22,8 @@ #include "stm32_hal_ll.h" #include "stm32_gpio.h" #include "stm32_ws2812.h" +#include "bootloader/boot.h" +#include "stm32_gpio.h" #include "hal/switch_driver.h" #include "hal/module_port.h" @@ -57,8 +59,6 @@ HardwareOptions hardwareOptions; -#if !defined(BOOT) - #if defined(SEMIHOSTING) extern "C" void initialise_monitor_handles(); #endif @@ -67,11 +67,13 @@ extern "C" void initialise_monitor_handles(); #include "voxlpm_i2c_driver.h" #endif +// SYS key (D.10) +#define BL_KEY GPIO_PIN(GPIOD, 10) + bool boardBLStartCondition() { -// gpio_init(BL_KEY, GPIO_IN, 0); -// return gpio_read(BL_KEY); - return false; + gpio_init(BL_KEY, GPIO_IN_PU, GPIO_PIN_SPEED_LOW); + return !gpio_read(BL_KEY); } void boardBLPreJump() @@ -114,7 +116,7 @@ void boardInit() // Charging can make a buzzing noise gpio_init(AUDIO_MUTE_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); gpio_set(AUDIO_MUTE_GPIO); - #endif +#endif while (usbPlugged()) { delay_ms(1000); } @@ -186,7 +188,6 @@ void boardInit() lcdSetContrast(true); #endif } -#endif void boardOff() { diff --git a/radio/src/targets/modalai/hal.h b/radio/src/targets/modalai/hal.h index 3f404c7d060..fb84244bf48 100644 --- a/radio/src/targets/modalai/hal.h +++ b/radio/src/targets/modalai/hal.h @@ -133,23 +133,23 @@ #define ADC_DMA_STREAM_IRQHandler DMA1_Stream0_IRQHandler #define HARDWARE_POT1 #define HARDWARE_POT2 -#define ADC_GPIO_PIN_STICK_RV LL_GPIO_PIN_1 // PB.01 -#define ADC_GPIO_PIN_STICK_RH LL_GPIO_PIN_12 // PF.12 -#define ADC_GPIO_PIN_STICK_LV LL_GPIO_PIN_1 // PA.01 -#define ADC_GPIO_PIN_STICK_LH LL_GPIO_PIN_0 // PC.00 -#define ADC_CHANNEL_STICK_RV LL_ADC_CHANNEL_5 // ADC1_CH5 -#define ADC_CHANNEL_STICK_RH LL_ADC_CHANNEL_6 // ADC1_CH6 -#define ADC_CHANNEL_STICK_LV LL_ADC_CHANNEL_17 // ADC1_CH17 -#define ADC_CHANNEL_STICK_LH LL_ADC_CHANNEL_10 // ADC1_CH10 +#define ADC_GPIO_PIN_STICK_LV LL_GPIO_PIN_1 // PB.01 +#define ADC_GPIO_PIN_STICK_LH LL_GPIO_PIN_12 // PF.12 +#define ADC_GPIO_PIN_STICK_RV LL_GPIO_PIN_1 // PA.01 +#define ADC_GPIO_PIN_STICK_RH LL_GPIO_PIN_0 // PC.00 +#define ADC_CHANNEL_STICK_LV LL_ADC_CHANNEL_5 // ADC1_CH5 +#define ADC_CHANNEL_STICK_LH LL_ADC_CHANNEL_6 // ADC1_CH6 +#define ADC_CHANNEL_STICK_RV LL_ADC_CHANNEL_17 // ADC1_CH17 +#define ADC_CHANNEL_STICK_RH LL_ADC_CHANNEL_10 // ADC1_CH10 #define ADC_CHANNEL_POT1 LL_ADC_CHANNEL_9 // ADC1_CH9 #define ADC_CHANNEL_POT2 LL_ADC_CHANNEL_16 // ADC1_CH16 #define ADC_GPIO_PIN_POT1 LL_GPIO_PIN_0 // PB.00 #define ADC_GPIO_PIN_POT2 LL_GPIO_PIN_0 // PA.00 // !#define ADC_GPIO_PIN_BATT LL_GPIO_PIN_0 // PC.00 // This pin is disconnected (hopefully that doesn't trigger anything) -#define ADC_GPIOA_PINS (ADC_GPIO_PIN_STICK_LV | ADC_GPIO_PIN_POT2) -#define ADC_GPIOB_PINS (ADC_GPIO_PIN_STICK_RV | ADC_GPIO_PIN_POT1) -#define ADC_GPIOC_PINS (ADC_GPIO_PIN_STICK_LH) -#define ADC_GPIOF_PINS (ADC_GPIO_PIN_STICK_RH) +#define ADC_GPIOA_PINS (ADC_GPIO_PIN_STICK_RV | ADC_GPIO_PIN_POT2) +#define ADC_GPIOB_PINS (ADC_GPIO_PIN_STICK_LV | ADC_GPIO_PIN_POT1) +#define ADC_GPIOC_PINS (ADC_GPIO_PIN_STICK_RH) +#define ADC_GPIOF_PINS (ADC_GPIO_PIN_STICK_LH) // !#define ADC_CHANNEL_BATT LL_ADC_CHANNEL_10 #define ADC_DIRECTION {-1, 1, 1, -1, -1, 1, 1, 1} @@ -187,6 +187,8 @@ // #define INTMODULE_RX_DMA_STREAM LL_DMA_STREAM_2 // #define INTMODULE_RX_DMA_CHANNEL LL_DMA_CHANNEL_4 +// TODO: Add extmodule when pins are decided on + // Software IRQ (Prio 5 -> FreeRTOS compatible) //#define TELEMETRY_RX_FRAME_EXTI_LINE LL_EXTI_LINE_4 //#define USE_EXTI4_IRQ From 1a7736d8b438f583e4091e77758dc13b9429ba91 Mon Sep 17 00:00:00 2001 From: Maxwell Schaefer Date: Mon, 31 Mar 2025 15:35:54 -0700 Subject: [PATCH 15/54] Fixed bootloader flashing and switched intmodule UART to UART8 --- radio/src/edgetx.cpp | 4 ++++ .../targets/common/arm/stm32/flash_driver.cpp | 3 +++ radio/src/targets/modalai/hal.h | 16 +++++++++++----- 3 files changed, 18 insertions(+), 5 deletions(-) diff --git a/radio/src/edgetx.cpp b/radio/src/edgetx.cpp index c1084081231..00407a993f5 100644 --- a/radio/src/edgetx.cpp +++ b/radio/src/edgetx.cpp @@ -386,6 +386,10 @@ void generalDefault() setDefaultOwnerId(); #endif +#if defined(MANUFACTURER_MODALAI) + g_eeGeneral.disableRtcWarning = 1; +#endif + #if defined(RADIOMASTER_RTF_RELEASE) // Those settings are for headless radio g_eeGeneral.USBMode = USB_JOYSTICK_MODE; diff --git a/radio/src/targets/common/arm/stm32/flash_driver.cpp b/radio/src/targets/common/arm/stm32/flash_driver.cpp index cc41ad11ed9..f6f214a1c7f 100644 --- a/radio/src/targets/common/arm/stm32/flash_driver.cpp +++ b/radio/src/targets/common/arm/stm32/flash_driver.cpp @@ -249,6 +249,8 @@ uint32_t isFirmwareStart(const uint8_t * buffer) if ((block[0] & 0xFFFF0000) != 0x20020000) { return 0; } +// The following is board specific code! (so is the above line but our layout conforms with that) +#ifndef PCBMODALAI // First ISR pointer in FLASH if ((block[1] & 0xF0000000) != 0x90000000) { return 0; @@ -257,6 +259,7 @@ uint32_t isFirmwareStart(const uint8_t * buffer) if ((block[2] & 0xF0000000) != 0xC0000000) { return 0; } +#endif #else // Stack pointer in RAM if ((block[0] & 0xFFFC0000) != 0x20000000) { diff --git a/radio/src/targets/modalai/hal.h b/radio/src/targets/modalai/hal.h index fb84244bf48..1b4587660fb 100644 --- a/radio/src/targets/modalai/hal.h +++ b/radio/src/targets/modalai/hal.h @@ -173,11 +173,17 @@ #define INTMODULE_BOOTCMD_GPIO GPIO_PIN(GPIOE, 13) // PE.13 (Disconnected) #define INTMODULE_PWR_GPIO GPIO_PIN(GPIOG, 8) // PG.08 (Disconnected) #define INTMODULE_BOOTCMD_DEFAULT 0 // RESET -#define INTMODULE_TX_GPIO GPIO_PIN(GPIOB, 13) // PB.13 -#define INTMODULE_RX_GPIO GPIO_PIN(GPIOB, 12) // PB.12 -#define INTMODULE_USART UART5 -#define INTMODULE_USART_IRQHandler UART5_IRQHandler -#define INTMODULE_USART_IRQn UART5_IRQn +// Alternate pin assignment depending on the side of M0207 we use +//#define INTMODULE_TX_GPIO GPIO_PIN(GPIOB, 13) // PB.13 +//#define INTMODULE_RX_GPIO GPIO_PIN(GPIOB, 12) // PB.12 +//#define INTMODULE_USART UART5 +//#define INTMODULE_USART_IRQHandler UART5_IRQHandler +//#define INTMODULE_USART_IRQn UART5_IRQn +#define INTMODULE_TX_GPIO GPIO_PIN(GPIOE, 1) // PE.01 +#define INTMODULE_RX_GPIO GPIO_PIN(GPIOE, 0) // PE.00 +#define INTMODULE_USART UART8 +#define INTMODULE_USART_IRQHandler UART8_IRQHandler +#define INTMODULE_USART_IRQn UART8_IRQn // #define INTMODULE_DMA DMA2 // #define INTMODULE_DMA_STREAM LL_DMA_STREAM_7 // #define INTMODULE_DMA_STREAM_IRQ DMA2_Stream7_IRQn From 6871be603ff63640f0b438d98123bf1822f44a64 Mon Sep 17 00:00:00 2001 From: Maxwell Schaefer Date: Mon, 31 Mar 2025 15:42:09 -0700 Subject: [PATCH 16/54] Removed unnecessary warning --- radio/src/targets/modalai/system_init.cpp | 1 - 1 file changed, 1 deletion(-) diff --git a/radio/src/targets/modalai/system_init.cpp b/radio/src/targets/modalai/system_init.cpp index 0a135333676..0e7f005c012 100644 --- a/radio/src/targets/modalai/system_init.cpp +++ b/radio/src/targets/modalai/system_init.cpp @@ -45,7 +45,6 @@ void Reset_Handler() "bl set_vtor \n" ); -#warning Clock/Cache config should stay in the bootloader only // #if defined(BOOT) asm inline ( "bl SystemClock_Config \n" From fec826d419750c333bf0cc6dd94773952c87214b Mon Sep 17 00:00:00 2001 From: Maxwell Schaefer Date: Mon, 31 Mar 2025 12:31:28 -0700 Subject: [PATCH 17/54] Cleaned up system init --- radio/src/targets/modalai/board.cpp | 4 ++-- radio/src/targets/modalai/system_init.cpp | 18 +++++++++--------- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/radio/src/targets/modalai/board.cpp b/radio/src/targets/modalai/board.cpp index 3f094d9ad37..0e0bb55b03a 100644 --- a/radio/src/targets/modalai/board.cpp +++ b/radio/src/targets/modalai/board.cpp @@ -82,9 +82,9 @@ void boardBLPreJump() void boardBLInit() { - // TODO: register SD card or internal flash for DFU + // TODO: register SD card or internal flash for DFU // It may be prefered to only update via SD card firmware files - // usbRegisterDFUMedia((void*)extflash_dfu_media); + // usbRegisterDFUMedia((void*)extflash_dfu_media); } diff --git a/radio/src/targets/modalai/system_init.cpp b/radio/src/targets/modalai/system_init.cpp index 0e7f005c012..7d7d4498d3f 100644 --- a/radio/src/targets/modalai/system_init.cpp +++ b/radio/src/targets/modalai/system_init.cpp @@ -20,6 +20,13 @@ void Reset_Handler() "ldr sp, =_estack \n" ); +#if defined(BOOT) + asm inline ( + "bl SystemClock_Config \n" + "bl CPU_CACHE_Enable \n" + ); +#endif + // TODO: Clock config should be first so this will go faster // Copy code into normal RAM asm inline ( @@ -29,12 +36,12 @@ void Reset_Handler() "bl naked_copy \n" ); -// #if defined(BOOT) +#if defined(BOOT) asm inline ( "bl SystemInit \n" "bl MPU_Init \n" ); -// #endif +#endif // Copy / setup ISR vector asm inline ( @@ -45,13 +52,6 @@ void Reset_Handler() "bl set_vtor \n" ); -// #if defined(BOOT) - asm inline ( - "bl SystemClock_Config \n" - "bl CPU_CACHE_Enable \n" - ); -// #endif - // Copy code into fast RAM asm inline ( "ldr r0, =_siram \n" From 1a07f1190161c1f1ad4702ec09cc413250c40b21 Mon Sep 17 00:00:00 2001 From: Maxwell Schaefer Date: Tue, 1 Apr 2025 13:24:30 -0700 Subject: [PATCH 18/54] Switched connectors J7 and J8 --- radio/src/targets/modalai/board.cpp | 2 +- radio/src/targets/modalai/hal.h | 116 ++++++++++++++-------------- 2 files changed, 59 insertions(+), 59 deletions(-) diff --git a/radio/src/targets/modalai/board.cpp b/radio/src/targets/modalai/board.cpp index 0e0bb55b03a..95077eabc24 100644 --- a/radio/src/targets/modalai/board.cpp +++ b/radio/src/targets/modalai/board.cpp @@ -68,7 +68,7 @@ extern "C" void initialise_monitor_handles(); #endif // SYS key (D.10) -#define BL_KEY GPIO_PIN(GPIOD, 10) +#define BL_KEY GPIO_PIN(GPIOF, 9) bool boardBLStartCondition() { diff --git a/radio/src/targets/modalai/hal.h b/radio/src/targets/modalai/hal.h index 1b4587660fb..d271e8273c1 100644 --- a/radio/src/targets/modalai/hal.h +++ b/radio/src/targets/modalai/hal.h @@ -50,41 +50,41 @@ // Keys -#define KEYS_GPIO_REG_PAGEUP GPIOH -#define KEYS_GPIO_PIN_PAGEUP LL_GPIO_PIN_6 // PH.06 -#define KEYS_GPIO_REG_PAGEDN GPIOD -#define KEYS_GPIO_PIN_PAGEDN LL_GPIO_PIN_14 // PD.14 -#define KEYS_GPIO_REG_EXIT GPIOD -#define KEYS_GPIO_PIN_EXIT LL_GPIO_PIN_11 // PD.11 -#define KEYS_GPIO_REG_ENTER GPIOB -#define KEYS_GPIO_PIN_ENTER LL_GPIO_PIN_2 // PB.02 -#define KEYS_GPIO_REG_SYS GPIOD -#define KEYS_GPIO_PIN_SYS LL_GPIO_PIN_10 // PD.10 -#define KEYS_GPIO_REG_MDL GPIOG -#define KEYS_GPIO_PIN_MDL LL_GPIO_PIN_1 // PG.01 -#define KEYS_GPIO_REG_TELE GPIOG -#define KEYS_GPIO_PIN_TELE LL_GPIO_PIN_0 // PG.00 +#define KEYS_GPIO_REG_PAGEUP GPIOG +#define KEYS_GPIO_PIN_PAGEUP LL_GPIO_PIN_1 // PG.01 +#define KEYS_GPIO_REG_PAGEDN GPIOG +#define KEYS_GPIO_PIN_PAGEDN LL_GPIO_PIN_0 // PG.00 +#define KEYS_GPIO_REG_EXIT GPIOF +#define KEYS_GPIO_PIN_EXIT LL_GPIO_PIN_13 // PF.13 +#define KEYS_GPIO_REG_ENTER GPIOH +#define KEYS_GPIO_PIN_ENTER LL_GPIO_PIN_9 // PH.09 +#define KEYS_GPIO_REG_SYS GPIOF +#define KEYS_GPIO_PIN_SYS LL_GPIO_PIN_9 // PF.09 +#define KEYS_GPIO_REG_MDL GPIOH +#define KEYS_GPIO_PIN_MDL LL_GPIO_PIN_6 // PH.06 +#define KEYS_GPIO_REG_TELE GPIOD +#define KEYS_GPIO_PIN_TELE LL_GPIO_PIN_14 // PD.14 // Rotary Encoder #define ROTARY_ENCODER_NAVIGATION -#define ROTARY_ENCODER_GPIO GPIOC -#define ROTARY_ENCODER_GPIO_PIN_A LL_GPIO_PIN_1 // PC.01 -#define ROTARY_ENCODER_GPIO_PIN_B LL_GPIO_PIN_2 // PC.02 -#define ROTARY_ENCODER_POSITION() (((ROTARY_ENCODER_GPIO->IDR >> 1) & 0x02) + ((ROTARY_ENCODER_GPIO->IDR >> 1) & 0x01)) -#define ROTARY_ENCODER_EXTI_LINE1 LL_EXTI_LINE_1 -#define ROTARY_ENCODER_EXTI_LINE2 LL_EXTI_LINE_2 -#define ROTARY_ENCODER_EXTI_PORT LL_SYSCFG_EXTI_PORTC -#define ROTARY_ENCODER_EXTI_SYS_LINE1 LL_SYSCFG_EXTI_LINE1 -#define ROTARY_ENCODER_EXTI_SYS_LINE2 LL_SYSCFG_EXTI_LINE2 +#define ROTARY_ENCODER_GPIO GPIOF +#define ROTARY_ENCODER_GPIO_PIN_A LL_GPIO_PIN_11 // PC.01 +#define ROTARY_ENCODER_GPIO_PIN_B LL_GPIO_PIN_8 // PC.02 +#define ROTARY_ENCODER_POSITION() (((ROTARY_ENCODER_GPIO->IDR >> 7) & 0x02) + ((ROTARY_ENCODER_GPIO->IDR >> 11) & 0x01)) +#define ROTARY_ENCODER_EXTI_LINE1 LL_EXTI_LINE_11 +#define ROTARY_ENCODER_EXTI_LINE2 LL_EXTI_LINE_8 +#define ROTARY_ENCODER_EXTI_PORT LL_SYSCFG_EXTI_PORTF +#define ROTARY_ENCODER_EXTI_SYS_LINE1 LL_SYSCFG_EXTI_LINE11 +#define ROTARY_ENCODER_EXTI_SYS_LINE2 LL_SYSCFG_EXTI_LINE8 // ROTARY_ENCODER_EXTI_LINE1 IRQ -#if !defined(USE_EXTI1_IRQ) - #define USE_EXTI1_IRQ - #define EXTI1_IRQ_Priority 5 +#if !defined(USE_EXTI9_5_IRQ) + #define USE_EXTI9_5_IRQ + #define EXTI9_5_IRQ_Priority 5 #endif -#if !defined(USE_EXTI2_IRQ) - #define USE_EXTI2_IRQ - #define EXTI2_IRQ_Priority 5 +#if !defined(USE_EXTI15_10_IRQ) + #define USE_EXTI15_10_IRQ + #define EXTI15_10_IRQ_Priority 5 #endif #define ROTARY_ENCODER_INVERTED @@ -97,27 +97,27 @@ #define STORAGE_SWITCH_B #define HARDWARE_SWITCH_B -#define SWITCHES_GPIO_REG_B_L GPIOD -#define SWITCHES_GPIO_PIN_B_L LL_GPIO_PIN_12 // PD.12 -#define SWITCHES_GPIO_REG_B_H GPIOD -#define SWITCHES_GPIO_PIN_B_H LL_GPIO_PIN_13 // PD.13 +#define SWITCHES_GPIO_REG_B_L GPIOH +#define SWITCHES_GPIO_PIN_B_L LL_GPIO_PIN_11 // PH.11 +#define SWITCHES_GPIO_REG_B_H GPIOH +#define SWITCHES_GPIO_PIN_B_H LL_GPIO_PIN_12 // PH.12 #define STORAGE_SWITCH_C #define HARDWARE_SWITCH_C -#define SWITCHES_GPIO_REG_C_L GPIOH -#define SWITCHES_GPIO_PIN_C_L LL_GPIO_PIN_11 // PH.11 -#define SWITCHES_GPIO_REG_C_H GPIOH -#define SWITCHES_GPIO_PIN_C_H LL_GPIO_PIN_12 // PH.12 +#define SWITCHES_GPIO_REG_C_L GPIOD +#define SWITCHES_GPIO_PIN_C_L LL_GPIO_PIN_12 // PD.12 +#define SWITCHES_GPIO_REG_C_H GPIOD +#define SWITCHES_GPIO_PIN_C_H LL_GPIO_PIN_13 // PD.13 #define STORAGE_SWITCH_E #define HARDWARE_SWITCH_E -#define SWITCHES_GPIO_REG_E GPIOE -#define SWITCHES_GPIO_PIN_E LL_GPIO_PIN_12 // PE.12 +#define SWITCHES_GPIO_REG_E GPIOF +#define SWITCHES_GPIO_PIN_E LL_GPIO_PIN_10 // PF.10 #define STORAGE_SWITCH_F #define HARDWARE_SWITCH_F -#define SWITCHES_GPIO_REG_F GPIOF -#define SWITCHES_GPIO_PIN_F LL_GPIO_PIN_10 // PF.10 +#define SWITCHES_GPIO_REG_F GPIOE +#define SWITCHES_GPIO_PIN_F LL_GPIO_PIN_12 // PE.12 // Sticks and pots @@ -133,23 +133,23 @@ #define ADC_DMA_STREAM_IRQHandler DMA1_Stream0_IRQHandler #define HARDWARE_POT1 #define HARDWARE_POT2 -#define ADC_GPIO_PIN_STICK_LV LL_GPIO_PIN_1 // PB.01 -#define ADC_GPIO_PIN_STICK_LH LL_GPIO_PIN_12 // PF.12 -#define ADC_GPIO_PIN_STICK_RV LL_GPIO_PIN_1 // PA.01 -#define ADC_GPIO_PIN_STICK_RH LL_GPIO_PIN_0 // PC.00 -#define ADC_CHANNEL_STICK_LV LL_ADC_CHANNEL_5 // ADC1_CH5 -#define ADC_CHANNEL_STICK_LH LL_ADC_CHANNEL_6 // ADC1_CH6 -#define ADC_CHANNEL_STICK_RV LL_ADC_CHANNEL_17 // ADC1_CH17 -#define ADC_CHANNEL_STICK_RH LL_ADC_CHANNEL_10 // ADC1_CH10 -#define ADC_CHANNEL_POT1 LL_ADC_CHANNEL_9 // ADC1_CH9 -#define ADC_CHANNEL_POT2 LL_ADC_CHANNEL_16 // ADC1_CH16 -#define ADC_GPIO_PIN_POT1 LL_GPIO_PIN_0 // PB.00 -#define ADC_GPIO_PIN_POT2 LL_GPIO_PIN_0 // PA.00 +#define ADC_GPIO_PIN_STICK_RV LL_GPIO_PIN_1 // PB.01 +#define ADC_GPIO_PIN_STICK_RH LL_GPIO_PIN_12 // PF.12 +#define ADC_GPIO_PIN_STICK_LV LL_GPIO_PIN_1 // PA.01 +#define ADC_GPIO_PIN_STICK_LH LL_GPIO_PIN_0 // PC.00 +#define ADC_CHANNEL_STICK_RV LL_ADC_CHANNEL_5 // ADC1_CH5 +#define ADC_CHANNEL_STICK_RH LL_ADC_CHANNEL_6 // ADC1_CH6 +#define ADC_CHANNEL_STICK_LV LL_ADC_CHANNEL_17 // ADC1_CH17 +#define ADC_CHANNEL_STICK_LH LL_ADC_CHANNEL_10 // ADC1_CH10 +#define ADC_CHANNEL_POT2 LL_ADC_CHANNEL_9 // ADC1_CH9 +#define ADC_CHANNEL_POT1 LL_ADC_CHANNEL_16 // ADC1_CH16 +#define ADC_GPIO_PIN_POT2 LL_GPIO_PIN_0 // PB.00 +#define ADC_GPIO_PIN_POT1 LL_GPIO_PIN_0 // PA.00 // !#define ADC_GPIO_PIN_BATT LL_GPIO_PIN_0 // PC.00 // This pin is disconnected (hopefully that doesn't trigger anything) -#define ADC_GPIOA_PINS (ADC_GPIO_PIN_STICK_RV | ADC_GPIO_PIN_POT2) -#define ADC_GPIOB_PINS (ADC_GPIO_PIN_STICK_LV | ADC_GPIO_PIN_POT1) -#define ADC_GPIOC_PINS (ADC_GPIO_PIN_STICK_RH) -#define ADC_GPIOF_PINS (ADC_GPIO_PIN_STICK_LH) +#define ADC_GPIOA_PINS (ADC_GPIO_PIN_STICK_LV | ADC_GPIO_PIN_POT1) +#define ADC_GPIOB_PINS (ADC_GPIO_PIN_STICK_RV | ADC_GPIO_PIN_POT2) +#define ADC_GPIOC_PINS (ADC_GPIO_PIN_STICK_LH) +#define ADC_GPIOF_PINS (ADC_GPIO_PIN_STICK_RH) // !#define ADC_CHANNEL_BATT LL_ADC_CHANNEL_10 #define ADC_DIRECTION {-1, 1, 1, -1, -1, 1, 1, 1} @@ -240,7 +240,7 @@ #define LCD_SPI SPI4 #define LCD_GPIO_AF GPIO_AF5 // For SPI4 #define LCD_VERTICAL_INVERT -#define LCD_SPI_PRESCALER 0x20000000 +#define LCD_SPI_PRESCALER 0x10000000 // TODO: M0207 has a SPI EEPROM From 636a9cc3dd48e82cee9df986ff87e7326f5620fa Mon Sep 17 00:00:00 2001 From: Maxwell Schaefer Date: Tue, 1 Apr 2025 18:11:44 -0700 Subject: [PATCH 19/54] Added a fix for battery voltage min/max being incorrect --- radio/src/targets/modalai/board.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/radio/src/targets/modalai/board.h b/radio/src/targets/modalai/board.h index c75dc9d5144..4f423e7e9ee 100644 --- a/radio/src/targets/modalai/board.h +++ b/radio/src/targets/modalai/board.h @@ -93,8 +93,8 @@ extern HardwareOptions hardwareOptions; // #define BATTERY_WARN 65 // 6.5V // #define BATTERY_MIN 60 // 6.0V // #define BATTERY_MAX 80 // 8.0V -#define BATTERY_WARN 0 // 6.5V -#define BATTERY_MIN 0 // 6.0V +#define BATTERY_WARN 65 // 6.5V +#define BATTERY_MIN 60 // 6.0V #define BATTERY_MAX 80 // 8.0V #define BATT_SCALE 123 From a870bda0c3dd586375f1e285b9fef33d58f879b8 Mon Sep 17 00:00:00 2001 From: Maxwell Schaefer Date: Fri, 18 Apr 2025 12:06:10 -0700 Subject: [PATCH 20/54] Updated to new Zorro pinout Also changed references to /usr/env/python to /usr/env/python3 so builds work outside of docker better --- radio/src/edgetx.cpp | 2 + radio/src/targets/modalai/board.cpp | 4 +- radio/src/targets/modalai/hal.h | 74 +++++++++++++++------------ radio/src/tasks.cpp | 1 - radio/src/thirdparty/FreeRTOS | 2 +- radio/src/thirdparty/stb | 2 +- radio/src/translations/translation.py | 2 +- radio/util/addtr.py | 2 +- radio/util/bin2lbm.py | 2 +- radio/util/build-firmware.py | 2 +- radio/util/capitalize.py | 2 +- radio/util/crossfire-parse.py | 2 +- radio/util/encode-bitmap.py | 2 +- radio/util/fat12.py | 2 +- radio/util/font2png.py | 2 +- radio/util/fwoptions.py | 2 +- radio/util/lua_trace2plot.py | 2 +- radio/util/parse.py | 2 +- radio/util/sport-parse.py | 2 +- radio/util/taranisicons.py | 2 +- tools/add-issue-links.py | 2 +- tools/build-font-bitmap.py | 2 +- tools/build-frsk.py | 2 +- tools/charset.py | 2 +- tools/copyright.py | 2 +- tools/encode-font.py | 2 +- tools/encode-translation.py | 2 +- tools/include-guard.py | 2 +- 28 files changed, 70 insertions(+), 59 deletions(-) diff --git a/radio/src/edgetx.cpp b/radio/src/edgetx.cpp index 00407a993f5..e7b4507b08a 100644 --- a/radio/src/edgetx.cpp +++ b/radio/src/edgetx.cpp @@ -1556,6 +1556,8 @@ void edgeTxInit() #endif #endif + mixerTaskInit(); + #if defined(GUI) if (calibration_needed) { cancelSplash(); diff --git a/radio/src/targets/modalai/board.cpp b/radio/src/targets/modalai/board.cpp index 95077eabc24..82bd9114c34 100644 --- a/radio/src/targets/modalai/board.cpp +++ b/radio/src/targets/modalai/board.cpp @@ -67,8 +67,8 @@ extern "C" void initialise_monitor_handles(); #include "voxlpm_i2c_driver.h" #endif -// SYS key (D.10) -#define BL_KEY GPIO_PIN(GPIOF, 9) +// SYS key (B.02) +#define BL_KEY GPIO_PIN(GPIOB, 2) bool boardBLStartCondition() { diff --git a/radio/src/targets/modalai/hal.h b/radio/src/targets/modalai/hal.h index d271e8273c1..6eda2ec860e 100644 --- a/radio/src/targets/modalai/hal.h +++ b/radio/src/targets/modalai/hal.h @@ -50,38 +50,34 @@ // Keys -#define KEYS_GPIO_REG_PAGEUP GPIOG -#define KEYS_GPIO_PIN_PAGEUP LL_GPIO_PIN_1 // PG.01 +#define KEYS_GPIO_REG_PAGEUP GPIOF +#define KEYS_GPIO_PIN_PAGEUP LL_GPIO_PIN_13 // PF.13 #define KEYS_GPIO_REG_PAGEDN GPIOG #define KEYS_GPIO_PIN_PAGEDN LL_GPIO_PIN_0 // PG.00 -#define KEYS_GPIO_REG_EXIT GPIOF -#define KEYS_GPIO_PIN_EXIT LL_GPIO_PIN_13 // PF.13 -#define KEYS_GPIO_REG_ENTER GPIOH -#define KEYS_GPIO_PIN_ENTER LL_GPIO_PIN_9 // PH.09 -#define KEYS_GPIO_REG_SYS GPIOF -#define KEYS_GPIO_PIN_SYS LL_GPIO_PIN_9 // PF.09 +#define KEYS_GPIO_REG_EXIT GPIOG +#define KEYS_GPIO_PIN_EXIT LL_GPIO_PIN_1 // PG.01 +#define KEYS_GPIO_REG_ENTER GPIOD +#define KEYS_GPIO_PIN_ENTER LL_GPIO_PIN_14 // PD.14 +#define KEYS_GPIO_REG_SYS GPIOB +#define KEYS_GPIO_PIN_SYS LL_GPIO_PIN_2 // PB.02 #define KEYS_GPIO_REG_MDL GPIOH #define KEYS_GPIO_PIN_MDL LL_GPIO_PIN_6 // PH.06 -#define KEYS_GPIO_REG_TELE GPIOD -#define KEYS_GPIO_PIN_TELE LL_GPIO_PIN_14 // PD.14 +#define KEYS_GPIO_REG_TELE GPIOH +#define KEYS_GPIO_PIN_TELE LL_GPIO_PIN_9 // PH.09 // Rotary Encoder #define ROTARY_ENCODER_NAVIGATION -#define ROTARY_ENCODER_GPIO GPIOF -#define ROTARY_ENCODER_GPIO_PIN_A LL_GPIO_PIN_11 // PC.01 -#define ROTARY_ENCODER_GPIO_PIN_B LL_GPIO_PIN_8 // PC.02 -#define ROTARY_ENCODER_POSITION() (((ROTARY_ENCODER_GPIO->IDR >> 7) & 0x02) + ((ROTARY_ENCODER_GPIO->IDR >> 11) & 0x01)) +#define ROTARY_ENCODER_GPIO GPIOD +#define ROTARY_ENCODER_GPIO_PIN_A LL_GPIO_PIN_11 // PD.11 +#define ROTARY_ENCODER_GPIO_PIN_B LL_GPIO_PIN_10 // PD.10 +#define ROTARY_ENCODER_POSITION() (((ROTARY_ENCODER_GPIO->IDR >> 10) & 0x02) + ((ROTARY_ENCODER_GPIO->IDR >> 10) & 0x01)) #define ROTARY_ENCODER_EXTI_LINE1 LL_EXTI_LINE_11 -#define ROTARY_ENCODER_EXTI_LINE2 LL_EXTI_LINE_8 -#define ROTARY_ENCODER_EXTI_PORT LL_SYSCFG_EXTI_PORTF +#define ROTARY_ENCODER_EXTI_LINE2 LL_EXTI_LINE_10 +#define ROTARY_ENCODER_EXTI_PORT LL_SYSCFG_EXTI_PORTD #define ROTARY_ENCODER_EXTI_SYS_LINE1 LL_SYSCFG_EXTI_LINE11 -#define ROTARY_ENCODER_EXTI_SYS_LINE2 LL_SYSCFG_EXTI_LINE8 +#define ROTARY_ENCODER_EXTI_SYS_LINE2 LL_SYSCFG_EXTI_LINE10 // ROTARY_ENCODER_EXTI_LINE1 IRQ -#if !defined(USE_EXTI9_5_IRQ) - #define USE_EXTI9_5_IRQ - #define EXTI9_5_IRQ_Priority 5 -#endif #if !defined(USE_EXTI15_10_IRQ) #define USE_EXTI15_10_IRQ #define EXTI15_10_IRQ_Priority 5 @@ -95,6 +91,13 @@ // Switches +#define STORAGE_SWITCH_A +#define HARDWARE_SWITCH_A +#define SWITCHES_GPIO_REG_A_L GPIOA +#define SWITCHES_GPIO_PIN_A_L LL_GPIO_PIN_1 // PA.01 +#define SWITCHES_GPIO_REG_A_H GPIOC +#define SWITCHES_GPIO_PIN_A_H LL_GPIO_PIN_4 // PC.04 + #define STORAGE_SWITCH_B #define HARDWARE_SWITCH_B #define SWITCHES_GPIO_REG_B_L GPIOH @@ -105,14 +108,21 @@ #define STORAGE_SWITCH_C #define HARDWARE_SWITCH_C #define SWITCHES_GPIO_REG_C_L GPIOD -#define SWITCHES_GPIO_PIN_C_L LL_GPIO_PIN_12 // PD.12 +#define SWITCHES_GPIO_PIN_C_L LL_GPIO_PIN_12 // PD.12 #define SWITCHES_GPIO_REG_C_H GPIOD #define SWITCHES_GPIO_PIN_C_H LL_GPIO_PIN_13 // PD.13 +#define STORAGE_SWITCH_D +#define HARDWARE_SWITCH_D +#define SWITCHES_GPIO_REG_D_L GPIOB +#define SWITCHES_GPIO_PIN_D_L LL_GPIO_PIN_1 // PB.01 +#define SWITCHES_GPIO_REG_D_H GPIOE +#define SWITCHES_GPIO_PIN_D_H LL_GPIO_PIN_10 // PE.10 + #define STORAGE_SWITCH_E #define HARDWARE_SWITCH_E #define SWITCHES_GPIO_REG_E GPIOF -#define SWITCHES_GPIO_PIN_E LL_GPIO_PIN_10 // PF.10 +#define SWITCHES_GPIO_PIN_E LL_GPIO_PIN_10 // PF.10 #define STORAGE_SWITCH_F #define HARDWARE_SWITCH_F @@ -133,25 +143,25 @@ #define ADC_DMA_STREAM_IRQHandler DMA1_Stream0_IRQHandler #define HARDWARE_POT1 #define HARDWARE_POT2 -#define ADC_GPIO_PIN_STICK_RV LL_GPIO_PIN_1 // PB.01 +#define ADC_GPIO_PIN_STICK_RV LL_GPIO_PIN_11 // PF.11 #define ADC_GPIO_PIN_STICK_RH LL_GPIO_PIN_12 // PF.12 -#define ADC_GPIO_PIN_STICK_LV LL_GPIO_PIN_1 // PA.01 +#define ADC_GPIO_PIN_STICK_LV LL_GPIO_PIN_1 // PC.01 #define ADC_GPIO_PIN_STICK_LH LL_GPIO_PIN_0 // PC.00 -#define ADC_CHANNEL_STICK_RV LL_ADC_CHANNEL_5 // ADC1_CH5 +#define ADC_CHANNEL_STICK_RV LL_ADC_CHANNEL_2 // ADC1_CH2 #define ADC_CHANNEL_STICK_RH LL_ADC_CHANNEL_6 // ADC1_CH6 -#define ADC_CHANNEL_STICK_LV LL_ADC_CHANNEL_17 // ADC1_CH17 +#define ADC_CHANNEL_STICK_LV LL_ADC_CHANNEL_11 // ADC1_CH11 #define ADC_CHANNEL_STICK_LH LL_ADC_CHANNEL_10 // ADC1_CH10 #define ADC_CHANNEL_POT2 LL_ADC_CHANNEL_9 // ADC1_CH9 #define ADC_CHANNEL_POT1 LL_ADC_CHANNEL_16 // ADC1_CH16 #define ADC_GPIO_PIN_POT2 LL_GPIO_PIN_0 // PB.00 #define ADC_GPIO_PIN_POT1 LL_GPIO_PIN_0 // PA.00 // !#define ADC_GPIO_PIN_BATT LL_GPIO_PIN_0 // PC.00 // This pin is disconnected (hopefully that doesn't trigger anything) -#define ADC_GPIOA_PINS (ADC_GPIO_PIN_STICK_LV | ADC_GPIO_PIN_POT1) -#define ADC_GPIOB_PINS (ADC_GPIO_PIN_STICK_RV | ADC_GPIO_PIN_POT2) -#define ADC_GPIOC_PINS (ADC_GPIO_PIN_STICK_LH) -#define ADC_GPIOF_PINS (ADC_GPIO_PIN_STICK_RH) +#define ADC_GPIOA_PINS (ADC_GPIO_PIN_POT1) +#define ADC_GPIOB_PINS (ADC_GPIO_PIN_POT2) +#define ADC_GPIOC_PINS (ADC_GPIO_PIN_STICK_LH | ADC_GPIO_PIN_STICK_LV) +#define ADC_GPIOF_PINS (ADC_GPIO_PIN_STICK_RH | ADC_GPIO_PIN_STICK_RV) // !#define ADC_CHANNEL_BATT LL_ADC_CHANNEL_10 -#define ADC_DIRECTION {-1, 1, 1, -1, -1, 1, 1, 1} +#define ADC_DIRECTION {-1, 1, 1, -1, 1, -1, 1, 1} // PWR and LED driver diff --git a/radio/src/tasks.cpp b/radio/src/tasks.cpp index e21a1dd6ab2..a695a2bd2ad 100644 --- a/radio/src/tasks.cpp +++ b/radio/src/tasks.cpp @@ -61,7 +61,6 @@ static void menusTask() edgeTxInit(); - mixerTaskInit(); #if defined(PWR_BUTTON_PRESS) while (task_running()) { diff --git a/radio/src/thirdparty/FreeRTOS b/radio/src/thirdparty/FreeRTOS index dbf70559b27..a4b28e35103 160000 --- a/radio/src/thirdparty/FreeRTOS +++ b/radio/src/thirdparty/FreeRTOS @@ -1 +1 @@ -Subproject commit dbf70559b27d39c1fdb68dfb9a32140b6a6777a0 +Subproject commit a4b28e35103d699edf074dfff4835921b481b301 diff --git a/radio/src/thirdparty/stb b/radio/src/thirdparty/stb index 5c205738c19..f4a71b13373 160000 --- a/radio/src/thirdparty/stb +++ b/radio/src/thirdparty/stb @@ -1 +1 @@ -Subproject commit 5c205738c191bcb0abc65c4febfa9bd25ff35234 +Subproject commit f4a71b13373436a2866c5d68f8f80ac6f0bc1ffe diff --git a/radio/src/translations/translation.py b/radio/src/translations/translation.py index 12cd6b26033..ba4bac43207 100755 --- a/radio/src/translations/translation.py +++ b/radio/src/translations/translation.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python +#!/usr/bin/env python3 import os import glob diff --git a/radio/util/addtr.py b/radio/util/addtr.py index 5b91a49c957..6d510784495 100755 --- a/radio/util/addtr.py +++ b/radio/util/addtr.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python +#!/usr/bin/env python3 from __future__ import print_function diff --git a/radio/util/bin2lbm.py b/radio/util/bin2lbm.py index caba6e3da4e..55e5e34814e 100755 --- a/radio/util/bin2lbm.py +++ b/radio/util/bin2lbm.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python +#!/usr/bin/env python3 from __future__ import division import sys diff --git a/radio/util/build-firmware.py b/radio/util/build-firmware.py index 3b6f0c0fed2..c713eab2536 100755 --- a/radio/util/build-firmware.py +++ b/radio/util/build-firmware.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python +#!/usr/bin/env python3 from __future__ import print_function import os diff --git a/radio/util/capitalize.py b/radio/util/capitalize.py index ac087168d84..a3efa610a46 100755 --- a/radio/util/capitalize.py +++ b/radio/util/capitalize.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python +#!/usr/bin/env python3 import glob import os diff --git a/radio/util/crossfire-parse.py b/radio/util/crossfire-parse.py index cc3fb97d60a..203b94084be 100755 --- a/radio/util/crossfire-parse.py +++ b/radio/util/crossfire-parse.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python +#!/usr/bin/env python3 # -*- coding: utf-8 -*- # This program parses CRSF capture data diff --git a/radio/util/encode-bitmap.py b/radio/util/encode-bitmap.py index bd2c7be904e..d103fc0d420 100755 --- a/radio/util/encode-bitmap.py +++ b/radio/util/encode-bitmap.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python +#!/usr/bin/env python3 import argparse from PIL import Image diff --git a/radio/util/fat12.py b/radio/util/fat12.py index 16c07d3a654..442aaad6f45 100755 --- a/radio/util/fat12.py +++ b/radio/util/fat12.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python +#!/usr/bin/env python3 from __future__ import division, print_function diff --git a/radio/util/font2png.py b/radio/util/font2png.py index cc0528ae6ca..a404b725cac 100644 --- a/radio/util/font2png.py +++ b/radio/util/font2png.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python +#!/usr/bin/env python3 # -*- coding: utf-8 -*- import sys, os diff --git a/radio/util/fwoptions.py b/radio/util/fwoptions.py index 304cc0ef0b6..06a2f123bb8 100755 --- a/radio/util/fwoptions.py +++ b/radio/util/fwoptions.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python +#!/usr/bin/env python3 languages = ( "en", diff --git a/radio/util/lua_trace2plot.py b/radio/util/lua_trace2plot.py index 2327a047555..cfa76e05ade 100755 --- a/radio/util/lua_trace2plot.py +++ b/radio/util/lua_trace2plot.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python +#!/usr/bin/env python3 # -*- coding: utf-8 -*- """ diff --git a/radio/util/parse.py b/radio/util/parse.py index b267fe3de55..0e175f6b802 100755 --- a/radio/util/parse.py +++ b/radio/util/parse.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python +#!/usr/bin/env python3 from __future__ import print_function diff --git a/radio/util/sport-parse.py b/radio/util/sport-parse.py index 0f2eaac4be6..88627cb808c 100755 --- a/radio/util/sport-parse.py +++ b/radio/util/sport-parse.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python +#!/usr/bin/env python3 # -*- coding: utf-8 -*- # This program parses sport.log files diff --git a/radio/util/taranisicons.py b/radio/util/taranisicons.py index d96abccada2..805361e9013 100755 --- a/radio/util/taranisicons.py +++ b/radio/util/taranisicons.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python +#!/usr/bin/env python3 # -*- coding: utf-8 -*- try: from PyQt5 import Qt, QtGui diff --git a/tools/add-issue-links.py b/tools/add-issue-links.py index 582809885ba..75084f0fef5 100755 --- a/tools/add-issue-links.py +++ b/tools/add-issue-links.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python +#!/usr/bin/env python3 # -*- coding: utf-8 -*- from __future__ import print_function diff --git a/tools/build-font-bitmap.py b/tools/build-font-bitmap.py index 8196b159ae6..72cbdd87042 100755 --- a/tools/build-font-bitmap.py +++ b/tools/build-font-bitmap.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python +#!/usr/bin/env python3 # -*- coding: utf-8 -*- import argparse diff --git a/tools/build-frsk.py b/tools/build-frsk.py index 1d80800fbf1..21b540352ce 100755 --- a/tools/build-frsk.py +++ b/tools/build-frsk.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python +#!/usr/bin/env python3 import argparse import os diff --git a/tools/charset.py b/tools/charset.py index cba3415fdc6..2e879a0776a 100644 --- a/tools/charset.py +++ b/tools/charset.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python +#!/usr/bin/env python3 # -*- coding: utf-8 -*- # used ? Δ~\n\t diff --git a/tools/copyright.py b/tools/copyright.py index 8c1853c6349..8d973411ad0 100644 --- a/tools/copyright.py +++ b/tools/copyright.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python +#!/usr/bin/env python3 from __future__ import print_function diff --git a/tools/encode-font.py b/tools/encode-font.py index aeed8a0682a..9d7c569ee9e 100755 --- a/tools/encode-font.py +++ b/tools/encode-font.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python +#!/usr/bin/env python3 import sys import argparse diff --git a/tools/encode-translation.py b/tools/encode-translation.py index 39eab1f0824..7848cd49903 100755 --- a/tools/encode-translation.py +++ b/tools/encode-translation.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python +#!/usr/bin/env python3 # -*- coding: utf-8 -*- import argparse diff --git a/tools/include-guard.py b/tools/include-guard.py index 5a60f6b2705..d69b38ea76d 100644 --- a/tools/include-guard.py +++ b/tools/include-guard.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python +#!/usr/bin/env python3 from __future__ import print_function From b15b3053fb9418bd8694f01f04787563c801003e Mon Sep 17 00:00:00 2001 From: benjinne Date: Tue, 10 Jun 2025 09:23:46 -0700 Subject: [PATCH 21/54] zorro-blue enable usb passthrough to flash internal module --- radio/src/targets/modalai/CMakeLists.txt | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/radio/src/targets/modalai/CMakeLists.txt b/radio/src/targets/modalai/CMakeLists.txt index 7fd87f0681a..2ea0223c96f 100644 --- a/radio/src/targets/modalai/CMakeLists.txt +++ b/radio/src/targets/modalai/CMakeLists.txt @@ -48,7 +48,7 @@ if(PCB STREQUAL M207) # set(USB_CHARGER YES) add_definitions(-DRADIO_MODAL) # set(PXX2 ON) - # set(ENABLE_SERIAL_PASSTHROUGH ON CACHE BOOL "Enable serial passthrough") + set(ENABLE_SERIAL_PASSTHROUGH ON CACHE BOOL "Enable serial passthrough") #if (NOT BLUETOOTH) # set(AUX_SERIAL ON) #endif() @@ -65,9 +65,9 @@ else() endif() -#if(ENABLE_SERIAL_PASSTHROUGH) -# set(CLI ON "Enable CLI") -#endif() +if(ENABLE_SERIAL_PASSTHROUGH) + set(CLI ON "Enable CLI") +endif() if(INTERNAL_MODULE_SERIAL) From ad88b511ce1df4994b8b9b18fb1952e7b1b0bbfa Mon Sep 17 00:00:00 2001 From: benjinne Date: Tue, 10 Jun 2025 09:24:02 -0700 Subject: [PATCH 22/54] zorro-blue disable rtc module --- radio/src/targets/modalai/CMakeLists.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/radio/src/targets/modalai/CMakeLists.txt b/radio/src/targets/modalai/CMakeLists.txt index 2ea0223c96f..e963cb3fbe5 100644 --- a/radio/src/targets/modalai/CMakeLists.txt +++ b/radio/src/targets/modalai/CMakeLists.txt @@ -8,7 +8,8 @@ option(AUTOUPDATE "Auto update internal chips from SD" OFF) option(BIND_KEY "Enable bind button" OFF) option(BLUETOOTH "FrSky BT module support" OFF) -set(USE_RTC_CLOCK YES) +set(USE_RTC_CLOCK NO) +set(RTC_BACKUP_RAM NO) set(HARDWARE_EXTERNAL_MODULE YES) set(TARGET_DIR modalai) From fe3e6181365cc4be9552b17ea1b7568cbc66a471 Mon Sep 17 00:00:00 2001 From: benjinne Date: Tue, 10 Jun 2025 09:25:12 -0700 Subject: [PATCH 23/54] zorro-blue add flag to allow removing bootloader --- radio/src/targets/modalai/CMakeLists.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/radio/src/targets/modalai/CMakeLists.txt b/radio/src/targets/modalai/CMakeLists.txt index e963cb3fbe5..b06802a9187 100644 --- a/radio/src/targets/modalai/CMakeLists.txt +++ b/radio/src/targets/modalai/CMakeLists.txt @@ -184,5 +184,11 @@ set(FIRMWARE_SRC ${FIRMWARE_SRC} targets/common/arm/loadboot.cpp ) +if(BOOTLOADER) + set(FIRMWARE_SRC + ${FIRMWARE_SRC} + targets/common/arm/loadboot.cpp + ) +endif() set(RADIO_DEPENDENCIES ${RADIO_DEPENDENCIES} ${BITMAPS_TARGET}) From 3110aec57a2e8f7ef179878ca5ef0648f0ba5f8d Mon Sep 17 00:00:00 2001 From: benjinne Date: Mon, 28 Jul 2025 11:36:50 -0700 Subject: [PATCH 24/54] modal_zorro add to switch_config --- radio/util/hw_defs/switch_config.py | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/radio/util/hw_defs/switch_config.py b/radio/util/hw_defs/switch_config.py index f12011f9145..a5c620cf16b 100644 --- a/radio/util/hw_defs/switch_config.py +++ b/radio/util/hw_defs/switch_config.py @@ -598,6 +598,18 @@ "SF": {"default": "2POS", "display": [1, 2]}, "SH": {"default": "TOGGLE", "display": [1, 3]}, }, + "modal_zorro": { + # left side + "SB": {"default": "3POS", "display": [0, 0]}, + "SA": {"default": "TOGGLE", "display": [0, 1]}, + "SE": {"default": "2POS", "display": [0, 2]}, + "SG": {"default": "TOGGLE", "display": [0, 3]}, + # right side + "SC": {"default": "3POS", "display": [1, 0]}, + "SD": {"default": "TOGGLE", "display": [1, 1]}, + "SF": {"default": "2POS", "display": [1, 2]}, + "SH": {"default": "TOGGLE", "display": [1, 3]}, + }, "pocket": { # left side "SA": { "default": "2POS", "display": [ 0, 0 ] }, From e2587201fb2c08ca4fd8ded8523e8f2036ee6fdb Mon Sep 17 00:00:00 2001 From: benjinne Date: Fri, 8 Aug 2025 08:59:54 -0700 Subject: [PATCH 25/54] modalai h7 increase flash-size --- radio/src/targets/modalai/board.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/radio/src/targets/modalai/board.h b/radio/src/targets/modalai/board.h index 4f423e7e9ee..230f90909db 100644 --- a/radio/src/targets/modalai/board.h +++ b/radio/src/targets/modalai/board.h @@ -36,7 +36,7 @@ void rotaryEncoderInit(); void rotaryEncoderCheck(); #endif -#define FLASHSIZE 0x80000 // 512k +#define FLASHSIZE 0x200000 #define FLASH_PAGESIZE 256 #define BOOTLOADER_SIZE 0x10000 #define FIRMWARE_ADDRESS 0x08000000 From 015fc4ce8b1db1e18aa9e3a2cdfe93092bb3ba42 Mon Sep 17 00:00:00 2001 From: benjinne Date: Fri, 8 Aug 2025 09:00:19 -0700 Subject: [PATCH 26/54] modalai cmakelists cleanup --- radio/src/targets/modalai/CMakeLists.txt | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) diff --git a/radio/src/targets/modalai/CMakeLists.txt b/radio/src/targets/modalai/CMakeLists.txt index b06802a9187..0d6ac57687d 100644 --- a/radio/src/targets/modalai/CMakeLists.txt +++ b/radio/src/targets/modalai/CMakeLists.txt @@ -1,5 +1,5 @@ option(SHUTDOWN_CONFIRMATION "Shutdown confirmation" OFF) -option(PXX1 "PXX1 protocol support" ON) +option(PXX1 "PXX1 protocol support" OFF) option(PXX2 "PXX2 protocol support" OFF) option(AFHDS3 "AFHDS3 TX Module" OFF) option(GHOST "Ghost TX Module" ON) @@ -10,7 +10,6 @@ option(BLUETOOTH "FrSky BT module support" OFF) set(USE_RTC_CLOCK NO) set(RTC_BACKUP_RAM NO) -set(HARDWARE_EXTERNAL_MODULE YES) set(TARGET_DIR modalai) set(HSE_VALUE 16000000) @@ -46,13 +45,14 @@ if(PCB STREQUAL M207) set(FLAVOUR modal_zorro) set(CPU_TYPE_FULL STM32H753II) set(ROTARY_ENCODER YES) - # set(USB_CHARGER YES) - add_definitions(-DRADIO_MODAL) - # set(PXX2 ON) - set(ENABLE_SERIAL_PASSTHROUGH ON CACHE BOOL "Enable serial passthrough") + set(USB_CHARGER NO) + set(IMU NO) + set(BLUETOOTH NO) #if (NOT BLUETOOTH) # set(AUX_SERIAL ON) #endif() + add_definitions(-DRADIO_MODAL) + set(ENABLE_SERIAL_PASSTHROUGH ON CACHE BOOL "Enable serial passthrough") endif() endif() @@ -184,11 +184,5 @@ set(FIRMWARE_SRC ${FIRMWARE_SRC} targets/common/arm/loadboot.cpp ) -if(BOOTLOADER) - set(FIRMWARE_SRC - ${FIRMWARE_SRC} - targets/common/arm/loadboot.cpp - ) -endif() set(RADIO_DEPENDENCIES ${RADIO_DEPENDENCIES} ${BITMAPS_TARGET}) From b02f2156e3c9504cb879558728ed66bb46ddeb11 Mon Sep 17 00:00:00 2001 From: benjinne Date: Mon, 11 Aug 2025 15:38:17 -0700 Subject: [PATCH 27/54] zorro-blue bootloader fix attempt --- .../startup/startup_stm32h753xx.s | 753 ------------------ .../common/arm/stm32/h7/CMakeLists.txt | 2 +- .../common/arm/stm32/h7/vectors_stm32h753xx.c | 318 ++++++++ .../targets/common/arm/stm32/system_init.c | 4 +- radio/src/targets/modalai/CMakeLists.txt | 13 +- .../targets/modalai/bootloader/boot_menu.cpp | 162 ---- .../{system_clock.cpp => system_clock.c} | 3 +- radio/src/targets/modalai/system_clock.h | 2 +- radio/src/targets/modalai/system_init.cpp | 186 ----- 9 files changed, 326 insertions(+), 1117 deletions(-) delete mode 100644 radio/src/boards/generic_stm32/startup/startup_stm32h753xx.s create mode 100644 radio/src/targets/common/arm/stm32/h7/vectors_stm32h753xx.c delete mode 100644 radio/src/targets/modalai/bootloader/boot_menu.cpp rename radio/src/targets/modalai/{system_clock.cpp => system_clock.c} (99%) delete mode 100644 radio/src/targets/modalai/system_init.cpp diff --git a/radio/src/boards/generic_stm32/startup/startup_stm32h753xx.s b/radio/src/boards/generic_stm32/startup/startup_stm32h753xx.s deleted file mode 100644 index 3dec8aeb219..00000000000 --- a/radio/src/boards/generic_stm32/startup/startup_stm32h753xx.s +++ /dev/null @@ -1,753 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32h753xx.s - * @author MCD Application Team - * @brief STM32H753xx Devices vector table for GCC based toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m7 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss -/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ - -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - ldr sp, =_estack /* set stack pointer */ - -/* Call the clock system initialization function.*/ - bl SystemInit - -/* Copy the data segment initializers from flash to SRAM */ - ldr r0, =_sdata - ldr r1, =_edata - ldr r2, =_sidata - movs r3, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r4, [r2, r3] - str r4, [r0, r3] - adds r3, r3, #4 - -LoopCopyDataInit: - adds r4, r0, r3 - cmp r4, r1 - bcc CopyDataInit -/* Zero fill the bss segment. */ - ldr r2, =_sbss - ldr r4, =_ebss - movs r3, #0 - b LoopFillZerobss - -FillZerobss: - str r3, [r2] - adds r2, r2, #4 - -LoopFillZerobss: - cmp r2, r4 - bcc FillZerobss - -/* Call static constructors */ - bl __libc_init_array -/* Call the application's entry point.*/ - bl main - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * @param None - * @retval None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -*******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - - -g_pfnVectors: - .word _estack - .word Reset_Handler - - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - - /* External Interrupts */ - .word WWDG_IRQHandler /* Window WatchDog */ - .word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */ - .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ - .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ - .word FLASH_IRQHandler /* FLASH */ - .word RCC_IRQHandler /* RCC */ - .word EXTI0_IRQHandler /* EXTI Line0 */ - .word EXTI1_IRQHandler /* EXTI Line1 */ - .word EXTI2_IRQHandler /* EXTI Line2 */ - .word EXTI3_IRQHandler /* EXTI Line3 */ - .word EXTI4_IRQHandler /* EXTI Line4 */ - .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ - .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ - .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ - .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ - .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ - .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ - .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ - .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ - .word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */ - .word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */ - .word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */ - .word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */ - .word EXTI9_5_IRQHandler /* External Line[9:5]s */ - .word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */ - .word TIM1_UP_IRQHandler /* TIM1 Update interrupt */ - .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */ - .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ - .word TIM2_IRQHandler /* TIM2 */ - .word TIM3_IRQHandler /* TIM3 */ - .word TIM4_IRQHandler /* TIM4 */ - .word I2C1_EV_IRQHandler /* I2C1 Event */ - .word I2C1_ER_IRQHandler /* I2C1 Error */ - .word I2C2_EV_IRQHandler /* I2C2 Event */ - .word I2C2_ER_IRQHandler /* I2C2 Error */ - .word SPI1_IRQHandler /* SPI1 */ - .word SPI2_IRQHandler /* SPI2 */ - .word USART1_IRQHandler /* USART1 */ - .word USART2_IRQHandler /* USART2 */ - .word USART3_IRQHandler /* USART3 */ - .word EXTI15_10_IRQHandler /* External Line[15:10]s */ - .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ - .word 0 /* Reserved */ - .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ - .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ - .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ - .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ - .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ - .word FMC_IRQHandler /* FMC */ - .word SDMMC1_IRQHandler /* SDMMC1 */ - .word TIM5_IRQHandler /* TIM5 */ - .word SPI3_IRQHandler /* SPI3 */ - .word UART4_IRQHandler /* UART4 */ - .word UART5_IRQHandler /* UART5 */ - .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ - .word TIM7_IRQHandler /* TIM7 */ - .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ - .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ - .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ - .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ - .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ - .word ETH_IRQHandler /* Ethernet */ - .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ - .word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt*/ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ - .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ - .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ - .word USART6_IRQHandler /* USART6 */ - .word I2C3_EV_IRQHandler /* I2C3 event */ - .word I2C3_ER_IRQHandler /* I2C3 error */ - .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ - .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ - .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ - .word OTG_HS_IRQHandler /* USB OTG HS */ - .word DCMI_IRQHandler /* DCMI */ - .word CRYP_IRQHandler /* Crypto */ - .word HASH_RNG_IRQHandler /* Hash and Rng */ - .word FPU_IRQHandler /* FPU */ - .word UART7_IRQHandler /* UART7 */ - .word UART8_IRQHandler /* UART8 */ - .word SPI4_IRQHandler /* SPI4 */ - .word SPI5_IRQHandler /* SPI5 */ - .word SPI6_IRQHandler /* SPI6 */ - .word SAI1_IRQHandler /* SAI1 */ - .word LTDC_IRQHandler /* LTDC */ - .word LTDC_ER_IRQHandler /* LTDC error */ - .word DMA2D_IRQHandler /* DMA2D */ - .word SAI2_IRQHandler /* SAI2 */ - .word QUADSPI_IRQHandler /* QUADSPI */ - .word LPTIM1_IRQHandler /* LPTIM1 */ - .word CEC_IRQHandler /* HDMI_CEC */ - .word I2C4_EV_IRQHandler /* I2C4 Event */ - .word I2C4_ER_IRQHandler /* I2C4 Error */ - .word SPDIF_RX_IRQHandler /* SPDIF_RX */ - .word OTG_FS_EP1_OUT_IRQHandler /* USB OTG FS End Point 1 Out */ - .word OTG_FS_EP1_IN_IRQHandler /* USB OTG FS End Point 1 In */ - .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI */ - .word OTG_FS_IRQHandler /* USB OTG FS */ - .word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */ - .word HRTIM1_Master_IRQHandler /* HRTIM Master Timer global Interrupt */ - .word HRTIM1_TIMA_IRQHandler /* HRTIM Timer A global Interrupt */ - .word HRTIM1_TIMB_IRQHandler /* HRTIM Timer B global Interrupt */ - .word HRTIM1_TIMC_IRQHandler /* HRTIM Timer C global Interrupt */ - .word HRTIM1_TIMD_IRQHandler /* HRTIM Timer D global Interrupt */ - .word HRTIM1_TIME_IRQHandler /* HRTIM Timer E global Interrupt */ - .word HRTIM1_FLT_IRQHandler /* HRTIM Fault global Interrupt */ - .word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */ - .word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */ - .word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */ - .word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */ - .word SAI3_IRQHandler /* SAI3 global Interrupt */ - .word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */ - .word TIM15_IRQHandler /* TIM15 global Interrupt */ - .word TIM16_IRQHandler /* TIM16 global Interrupt */ - .word TIM17_IRQHandler /* TIM17 global Interrupt */ - .word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */ - .word MDIOS_IRQHandler /* MDIOS global Interrupt */ - .word JPEG_IRQHandler /* JPEG global Interrupt */ - .word MDMA_IRQHandler /* MDMA global Interrupt */ - .word 0 /* Reserved */ - .word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */ - .word HSEM1_IRQHandler /* HSEM1 global Interrupt */ - .word 0 /* Reserved */ - .word ADC3_IRQHandler /* ADC3 global Interrupt */ - .word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */ - .word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */ - .word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */ - .word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */ - .word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */ - .word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */ - .word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */ - .word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */ - .word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */ - .word COMP1_IRQHandler /* COMP1 global Interrupt */ - .word LPTIM2_IRQHandler /* LP TIM2 global interrupt */ - .word LPTIM3_IRQHandler /* LP TIM3 global interrupt */ - .word LPTIM4_IRQHandler /* LP TIM4 global interrupt */ - .word LPTIM5_IRQHandler /* LP TIM5 global interrupt */ - .word LPUART1_IRQHandler /* LP UART1 interrupt */ - .word 0 /* Reserved */ - .word CRS_IRQHandler /* Clock Recovery Global Interrupt */ - .word ECC_IRQHandler /* ECC diagnostic Global Interrupt */ - .word SAI4_IRQHandler /* SAI4 global interrupt */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */ - - .size g_pfnVectors, .-g_pfnVectors - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_AVD_IRQHandler - .thumb_set PVD_AVD_IRQHandler,Default_Handler - - .weak TAMP_STAMP_IRQHandler - .thumb_set TAMP_STAMP_IRQHandler,Default_Handler - - .weak RTC_WKUP_IRQHandler - .thumb_set RTC_WKUP_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Stream0_IRQHandler - .thumb_set DMA1_Stream0_IRQHandler,Default_Handler - - .weak DMA1_Stream1_IRQHandler - .thumb_set DMA1_Stream1_IRQHandler,Default_Handler - - .weak DMA1_Stream2_IRQHandler - .thumb_set DMA1_Stream2_IRQHandler,Default_Handler - - .weak DMA1_Stream3_IRQHandler - .thumb_set DMA1_Stream3_IRQHandler,Default_Handler - - .weak DMA1_Stream4_IRQHandler - .thumb_set DMA1_Stream4_IRQHandler,Default_Handler - - .weak DMA1_Stream5_IRQHandler - .thumb_set DMA1_Stream5_IRQHandler,Default_Handler - - .weak DMA1_Stream6_IRQHandler - .thumb_set DMA1_Stream6_IRQHandler,Default_Handler - - .weak ADC_IRQHandler - .thumb_set ADC_IRQHandler,Default_Handler - - .weak FDCAN1_IT0_IRQHandler - .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler - - .weak FDCAN2_IT0_IRQHandler - .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler - - .weak FDCAN1_IT1_IRQHandler - .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler - - .weak FDCAN2_IT1_IRQHandler - .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM1_BRK_IRQHandler - .thumb_set TIM1_BRK_IRQHandler,Default_Handler - - .weak TIM1_UP_IRQHandler - .thumb_set TIM1_UP_IRQHandler,Default_Handler - - .weak TIM1_TRG_COM_IRQHandler - .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTC_Alarm_IRQHandler - .thumb_set RTC_Alarm_IRQHandler,Default_Handler - - .weak TIM8_BRK_TIM12_IRQHandler - .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler - - .weak TIM8_UP_TIM13_IRQHandler - .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler - - .weak TIM8_TRG_COM_TIM14_IRQHandler - .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler - - .weak TIM8_CC_IRQHandler - .thumb_set TIM8_CC_IRQHandler,Default_Handler - - .weak DMA1_Stream7_IRQHandler - .thumb_set DMA1_Stream7_IRQHandler,Default_Handler - - .weak FMC_IRQHandler - .thumb_set FMC_IRQHandler,Default_Handler - - .weak SDMMC1_IRQHandler - .thumb_set SDMMC1_IRQHandler,Default_Handler - - .weak TIM5_IRQHandler - .thumb_set TIM5_IRQHandler,Default_Handler - - .weak SPI3_IRQHandler - .thumb_set SPI3_IRQHandler,Default_Handler - - .weak UART4_IRQHandler - .thumb_set UART4_IRQHandler,Default_Handler - - .weak UART5_IRQHandler - .thumb_set UART5_IRQHandler,Default_Handler - - .weak TIM6_DAC_IRQHandler - .thumb_set TIM6_DAC_IRQHandler,Default_Handler - - .weak TIM7_IRQHandler - .thumb_set TIM7_IRQHandler,Default_Handler - - .weak DMA2_Stream0_IRQHandler - .thumb_set DMA2_Stream0_IRQHandler,Default_Handler - - .weak DMA2_Stream1_IRQHandler - .thumb_set DMA2_Stream1_IRQHandler,Default_Handler - - .weak DMA2_Stream2_IRQHandler - .thumb_set DMA2_Stream2_IRQHandler,Default_Handler - - .weak DMA2_Stream3_IRQHandler - .thumb_set DMA2_Stream3_IRQHandler,Default_Handler - - .weak DMA2_Stream4_IRQHandler - .thumb_set DMA2_Stream4_IRQHandler,Default_Handler - - .weak ETH_IRQHandler - .thumb_set ETH_IRQHandler,Default_Handler - - .weak ETH_WKUP_IRQHandler - .thumb_set ETH_WKUP_IRQHandler,Default_Handler - - .weak FDCAN_CAL_IRQHandler - .thumb_set FDCAN_CAL_IRQHandler,Default_Handler - - .weak DMA2_Stream5_IRQHandler - .thumb_set DMA2_Stream5_IRQHandler,Default_Handler - - .weak DMA2_Stream6_IRQHandler - .thumb_set DMA2_Stream6_IRQHandler,Default_Handler - - .weak DMA2_Stream7_IRQHandler - .thumb_set DMA2_Stream7_IRQHandler,Default_Handler - - .weak USART6_IRQHandler - .thumb_set USART6_IRQHandler,Default_Handler - - .weak I2C3_EV_IRQHandler - .thumb_set I2C3_EV_IRQHandler,Default_Handler - - .weak I2C3_ER_IRQHandler - .thumb_set I2C3_ER_IRQHandler,Default_Handler - - .weak OTG_HS_EP1_OUT_IRQHandler - .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler - - .weak OTG_HS_EP1_IN_IRQHandler - .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler - - .weak OTG_HS_WKUP_IRQHandler - .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler - - .weak OTG_HS_IRQHandler - .thumb_set OTG_HS_IRQHandler,Default_Handler - - .weak DCMI_IRQHandler - .thumb_set DCMI_IRQHandler,Default_Handler - - .weak CRYP_IRQHandler - .thumb_set CRYP_IRQHandler,Default_Handler - - .weak HASH_RNG_IRQHandler - .thumb_set HASH_RNG_IRQHandler,Default_Handler - - .weak FPU_IRQHandler - .thumb_set FPU_IRQHandler,Default_Handler - - .weak UART7_IRQHandler - .thumb_set UART7_IRQHandler,Default_Handler - - .weak UART8_IRQHandler - .thumb_set UART8_IRQHandler,Default_Handler - - .weak SPI4_IRQHandler - .thumb_set SPI4_IRQHandler,Default_Handler - - .weak SPI5_IRQHandler - .thumb_set SPI5_IRQHandler,Default_Handler - - .weak SPI6_IRQHandler - .thumb_set SPI6_IRQHandler,Default_Handler - - .weak SAI1_IRQHandler - .thumb_set SAI1_IRQHandler,Default_Handler - - .weak LTDC_IRQHandler - .thumb_set LTDC_IRQHandler,Default_Handler - - .weak LTDC_ER_IRQHandler - .thumb_set LTDC_ER_IRQHandler,Default_Handler - - .weak DMA2D_IRQHandler - .thumb_set DMA2D_IRQHandler,Default_Handler - - .weak SAI2_IRQHandler - .thumb_set SAI2_IRQHandler,Default_Handler - - .weak QUADSPI_IRQHandler - .thumb_set QUADSPI_IRQHandler,Default_Handler - - .weak LPTIM1_IRQHandler - .thumb_set LPTIM1_IRQHandler,Default_Handler - - .weak CEC_IRQHandler - .thumb_set CEC_IRQHandler,Default_Handler - - .weak I2C4_EV_IRQHandler - .thumb_set I2C4_EV_IRQHandler,Default_Handler - - .weak I2C4_ER_IRQHandler - .thumb_set I2C4_ER_IRQHandler,Default_Handler - - .weak SPDIF_RX_IRQHandler - .thumb_set SPDIF_RX_IRQHandler,Default_Handler - - .weak OTG_FS_EP1_OUT_IRQHandler - .thumb_set OTG_FS_EP1_OUT_IRQHandler,Default_Handler - - .weak OTG_FS_EP1_IN_IRQHandler - .thumb_set OTG_FS_EP1_IN_IRQHandler,Default_Handler - - .weak OTG_FS_WKUP_IRQHandler - .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler - - .weak OTG_FS_IRQHandler - .thumb_set OTG_FS_IRQHandler,Default_Handler - - .weak DMAMUX1_OVR_IRQHandler - .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler - - .weak HRTIM1_Master_IRQHandler - .thumb_set HRTIM1_Master_IRQHandler,Default_Handler - - .weak HRTIM1_TIMA_IRQHandler - .thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler - - .weak HRTIM1_TIMB_IRQHandler - .thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler - - .weak HRTIM1_TIMC_IRQHandler - .thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler - - .weak HRTIM1_TIMD_IRQHandler - .thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler - - .weak HRTIM1_TIME_IRQHandler - .thumb_set HRTIM1_TIME_IRQHandler,Default_Handler - - .weak HRTIM1_FLT_IRQHandler - .thumb_set HRTIM1_FLT_IRQHandler,Default_Handler - - .weak DFSDM1_FLT0_IRQHandler - .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler - - .weak DFSDM1_FLT1_IRQHandler - .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler - - .weak DFSDM1_FLT2_IRQHandler - .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler - - .weak DFSDM1_FLT3_IRQHandler - .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler - - .weak SAI3_IRQHandler - .thumb_set SAI3_IRQHandler,Default_Handler - - .weak SWPMI1_IRQHandler - .thumb_set SWPMI1_IRQHandler,Default_Handler - - .weak TIM15_IRQHandler - .thumb_set TIM15_IRQHandler,Default_Handler - - .weak TIM16_IRQHandler - .thumb_set TIM16_IRQHandler,Default_Handler - - .weak TIM17_IRQHandler - .thumb_set TIM17_IRQHandler,Default_Handler - - .weak MDIOS_WKUP_IRQHandler - .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler - - .weak MDIOS_IRQHandler - .thumb_set MDIOS_IRQHandler,Default_Handler - - .weak JPEG_IRQHandler - .thumb_set JPEG_IRQHandler,Default_Handler - - .weak MDMA_IRQHandler - .thumb_set MDMA_IRQHandler,Default_Handler - - .weak SDMMC2_IRQHandler - .thumb_set SDMMC2_IRQHandler,Default_Handler - - .weak HSEM1_IRQHandler - .thumb_set HSEM1_IRQHandler,Default_Handler - - .weak ADC3_IRQHandler - .thumb_set ADC3_IRQHandler,Default_Handler - - .weak DMAMUX2_OVR_IRQHandler - .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler - - .weak BDMA_Channel0_IRQHandler - .thumb_set BDMA_Channel0_IRQHandler,Default_Handler - - .weak BDMA_Channel1_IRQHandler - .thumb_set BDMA_Channel1_IRQHandler,Default_Handler - - .weak BDMA_Channel2_IRQHandler - .thumb_set BDMA_Channel2_IRQHandler,Default_Handler - - .weak BDMA_Channel3_IRQHandler - .thumb_set BDMA_Channel3_IRQHandler,Default_Handler - - .weak BDMA_Channel4_IRQHandler - .thumb_set BDMA_Channel4_IRQHandler,Default_Handler - - .weak BDMA_Channel5_IRQHandler - .thumb_set BDMA_Channel5_IRQHandler,Default_Handler - - .weak BDMA_Channel6_IRQHandler - .thumb_set BDMA_Channel6_IRQHandler,Default_Handler - - .weak BDMA_Channel7_IRQHandler - .thumb_set BDMA_Channel7_IRQHandler,Default_Handler - - .weak COMP1_IRQHandler - .thumb_set COMP1_IRQHandler,Default_Handler - - .weak LPTIM2_IRQHandler - .thumb_set LPTIM2_IRQHandler,Default_Handler - - .weak LPTIM3_IRQHandler - .thumb_set LPTIM3_IRQHandler,Default_Handler - - .weak LPTIM4_IRQHandler - .thumb_set LPTIM4_IRQHandler,Default_Handler - - .weak LPTIM5_IRQHandler - .thumb_set LPTIM5_IRQHandler,Default_Handler - - .weak LPUART1_IRQHandler - .thumb_set LPUART1_IRQHandler,Default_Handler - - .weak CRS_IRQHandler - .thumb_set CRS_IRQHandler,Default_Handler - - .weak ECC_IRQHandler - .thumb_set ECC_IRQHandler,Default_Handler - - .weak SAI4_IRQHandler - .thumb_set SAI4_IRQHandler,Default_Handler - - .weak WAKEUP_PIN_IRQHandler - .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler - - diff --git a/radio/src/targets/common/arm/stm32/h7/CMakeLists.txt b/radio/src/targets/common/arm/stm32/h7/CMakeLists.txt index 863877ca033..4f8dff6fe30 100644 --- a/radio/src/targets/common/arm/stm32/h7/CMakeLists.txt +++ b/radio/src/targets/common/arm/stm32/h7/CMakeLists.txt @@ -134,7 +134,7 @@ elseif(CPU_TYPE_FULL STREQUAL STM32H7S7xx OR CPU_TYPE_FULL STREQUAL STM32H7R7xx) ) elseif(CPU_TYPE_FULL STREQUAL STM32H753II) set(CMSIS_SRC ${CMSIS_SRC} - boards/generic_stm32/startup/startup_stm32h753xx.s + targets/common/arm/stm32/h7/vectors_stm32h753xx.c ) else() message(FATAL_ERROR "### ERROR ####: ${CPU_TYPE_FULL}") diff --git a/radio/src/targets/common/arm/stm32/h7/vectors_stm32h753xx.c b/radio/src/targets/common/arm/stm32/h7/vectors_stm32h753xx.c new file mode 100644 index 00000000000..ef91f27a33f --- /dev/null +++ b/radio/src/targets/common/arm/stm32/h7/vectors_stm32h753xx.c @@ -0,0 +1,318 @@ + +#include "stm32h753xx.h" +#include "cortex_m_isr.h" + +void Default_Handler() { default_isr_handler(); } + +/* stm32h753xx specific interrupt vectors */ +WEAK_DEFAULT void Reset_Handler(); +WEAK_DEFAULT void NMI_Handler(); +WEAK_DEFAULT void HardFault_Handler(); +WEAK_DEFAULT void MemManage_Handler(); +WEAK_DEFAULT void BusFault_Handler(); +WEAK_DEFAULT void UsageFault_Handler(); +WEAK_DEFAULT void SVC_Handler(); +WEAK_DEFAULT void DebugMon_Handler(); +WEAK_DEFAULT void PendSV_Handler(); +WEAK_DEFAULT void SysTick_Handler(); +WEAK_DEFAULT void WWDG_IRQHandler(); +WEAK_DEFAULT void PVD_AVD_IRQHandler(); +WEAK_DEFAULT void TAMP_STAMP_IRQHandler(); +WEAK_DEFAULT void RTC_WKUP_IRQHandler(); +WEAK_DEFAULT void FLASH_IRQHandler(); +WEAK_DEFAULT void RCC_IRQHandler(); +WEAK_DEFAULT void EXTI0_IRQHandler(); +WEAK_DEFAULT void EXTI1_IRQHandler(); +WEAK_DEFAULT void EXTI2_IRQHandler(); +WEAK_DEFAULT void EXTI3_IRQHandler(); +WEAK_DEFAULT void EXTI4_IRQHandler(); +WEAK_DEFAULT void DMA1_Stream0_IRQHandler(); +WEAK_DEFAULT void DMA1_Stream1_IRQHandler(); +WEAK_DEFAULT void DMA1_Stream2_IRQHandler(); +WEAK_DEFAULT void DMA1_Stream3_IRQHandler(); +WEAK_DEFAULT void DMA1_Stream4_IRQHandler(); +WEAK_DEFAULT void DMA1_Stream5_IRQHandler(); +WEAK_DEFAULT void DMA1_Stream6_IRQHandler(); +WEAK_DEFAULT void ADC_IRQHandler(); +WEAK_DEFAULT void FDCAN1_IT0_IRQHandler(); +WEAK_DEFAULT void FDCAN2_IT0_IRQHandler(); +WEAK_DEFAULT void FDCAN1_IT1_IRQHandler(); +WEAK_DEFAULT void FDCAN2_IT1_IRQHandler(); +WEAK_DEFAULT void EXTI9_5_IRQHandler(); +WEAK_DEFAULT void TIM1_BRK_IRQHandler(); +WEAK_DEFAULT void TIM1_UP_IRQHandler(); +WEAK_DEFAULT void TIM1_TRG_COM_IRQHandler(); +WEAK_DEFAULT void TIM1_CC_IRQHandler(); +WEAK_DEFAULT void TIM2_IRQHandler(); +WEAK_DEFAULT void TIM3_IRQHandler(); +WEAK_DEFAULT void TIM4_IRQHandler(); +WEAK_DEFAULT void I2C1_EV_IRQHandler(); +WEAK_DEFAULT void I2C1_ER_IRQHandler(); +WEAK_DEFAULT void I2C2_EV_IRQHandler(); +WEAK_DEFAULT void I2C2_ER_IRQHandler(); +WEAK_DEFAULT void SPI1_IRQHandler(); +WEAK_DEFAULT void SPI2_IRQHandler(); +WEAK_DEFAULT void USART1_IRQHandler(); +WEAK_DEFAULT void USART2_IRQHandler(); +WEAK_DEFAULT void USART3_IRQHandler(); +WEAK_DEFAULT void EXTI15_10_IRQHandler(); +WEAK_DEFAULT void RTC_Alarm_IRQHandler(); +WEAK_DEFAULT void TIM8_BRK_TIM12_IRQHandler(); +WEAK_DEFAULT void TIM8_UP_TIM13_IRQHandler(); +WEAK_DEFAULT void TIM8_TRG_COM_TIM14_IRQHandler(); +WEAK_DEFAULT void TIM8_CC_IRQHandler(); +WEAK_DEFAULT void DMA1_Stream7_IRQHandler(); +WEAK_DEFAULT void FMC_IRQHandler(); +WEAK_DEFAULT void SDMMC1_IRQHandler(); +WEAK_DEFAULT void TIM5_IRQHandler(); +WEAK_DEFAULT void SPI3_IRQHandler(); +WEAK_DEFAULT void UART4_IRQHandler(); +WEAK_DEFAULT void UART5_IRQHandler(); +WEAK_DEFAULT void TIM6_DAC_IRQHandler(); +WEAK_DEFAULT void TIM7_IRQHandler(); +WEAK_DEFAULT void DMA2_Stream0_IRQHandler(); +WEAK_DEFAULT void DMA2_Stream1_IRQHandler(); +WEAK_DEFAULT void DMA2_Stream2_IRQHandler(); +WEAK_DEFAULT void DMA2_Stream3_IRQHandler(); +WEAK_DEFAULT void DMA2_Stream4_IRQHandler(); +WEAK_DEFAULT void ETH_IRQHandler(); +WEAK_DEFAULT void ETH_WKUP_IRQHandler(); +WEAK_DEFAULT void FDCAN_CAL_IRQHandler(); +WEAK_DEFAULT void DMA2_Stream5_IRQHandler(); +WEAK_DEFAULT void DMA2_Stream6_IRQHandler(); +WEAK_DEFAULT void DMA2_Stream7_IRQHandler(); +WEAK_DEFAULT void USART6_IRQHandler(); +WEAK_DEFAULT void I2C3_EV_IRQHandler(); +WEAK_DEFAULT void I2C3_ER_IRQHandler(); +WEAK_DEFAULT void OTG_HS_EP1_OUT_IRQHandler(); +WEAK_DEFAULT void OTG_HS_EP1_IN_IRQHandler(); +WEAK_DEFAULT void OTG_HS_WKUP_IRQHandler(); +WEAK_DEFAULT void OTG_HS_IRQHandler(); +WEAK_DEFAULT void DCMI_IRQHandler(); +WEAK_DEFAULT void CRYP_IRQHandler(); +WEAK_DEFAULT void HASH_RNG_IRQHandler(); +WEAK_DEFAULT void FPU_IRQHandler(); +WEAK_DEFAULT void UART7_IRQHandler(); +WEAK_DEFAULT void UART8_IRQHandler(); +WEAK_DEFAULT void SPI4_IRQHandler(); +WEAK_DEFAULT void SPI5_IRQHandler(); +WEAK_DEFAULT void SPI6_IRQHandler(); +WEAK_DEFAULT void SAI1_IRQHandler(); +WEAK_DEFAULT void LTDC_IRQHandler(); +WEAK_DEFAULT void LTDC_ER_IRQHandler(); +WEAK_DEFAULT void DMA2D_IRQHandler(); +WEAK_DEFAULT void SAI2_IRQHandler(); +WEAK_DEFAULT void QUADSPI_IRQHandler(); +WEAK_DEFAULT void LPTIM1_IRQHandler(); +WEAK_DEFAULT void CEC_IRQHandler(); +WEAK_DEFAULT void I2C4_EV_IRQHandler(); +WEAK_DEFAULT void I2C4_ER_IRQHandler(); +WEAK_DEFAULT void SPDIF_RX_IRQHandler(); +WEAK_DEFAULT void OTG_FS_EP1_OUT_IRQHandler(); +WEAK_DEFAULT void OTG_FS_EP1_IN_IRQHandler(); +WEAK_DEFAULT void OTG_FS_WKUP_IRQHandler(); +WEAK_DEFAULT void OTG_FS_IRQHandler(); +WEAK_DEFAULT void DMAMUX1_OVR_IRQHandler(); +WEAK_DEFAULT void HRTIM1_Master_IRQHandler(); +WEAK_DEFAULT void HRTIM1_TIMA_IRQHandler(); +WEAK_DEFAULT void HRTIM1_TIMB_IRQHandler(); +WEAK_DEFAULT void HRTIM1_TIMC_IRQHandler(); +WEAK_DEFAULT void HRTIM1_TIMD_IRQHandler(); +WEAK_DEFAULT void HRTIM1_TIME_IRQHandler(); +WEAK_DEFAULT void HRTIM1_FLT_IRQHandler(); +WEAK_DEFAULT void DFSDM1_FLT0_IRQHandler(); +WEAK_DEFAULT void DFSDM1_FLT1_IRQHandler(); +WEAK_DEFAULT void DFSDM1_FLT2_IRQHandler(); +WEAK_DEFAULT void DFSDM1_FLT3_IRQHandler(); +WEAK_DEFAULT void SAI3_IRQHandler(); +WEAK_DEFAULT void SWPMI1_IRQHandler(); +WEAK_DEFAULT void TIM15_IRQHandler(); +WEAK_DEFAULT void TIM16_IRQHandler(); +WEAK_DEFAULT void TIM17_IRQHandler(); +WEAK_DEFAULT void MDIOS_WKUP_IRQHandler(); +WEAK_DEFAULT void MDIOS_IRQHandler(); +WEAK_DEFAULT void JPEG_IRQHandler(); +WEAK_DEFAULT void MDMA_IRQHandler(); +WEAK_DEFAULT void SDMMC2_IRQHandler(); +WEAK_DEFAULT void HSEM1_IRQHandler(); +WEAK_DEFAULT void ADC3_IRQHandler(); +WEAK_DEFAULT void DMAMUX2_OVR_IRQHandler(); +WEAK_DEFAULT void BDMA_Channel0_IRQHandler(); +WEAK_DEFAULT void BDMA_Channel1_IRQHandler(); +WEAK_DEFAULT void BDMA_Channel2_IRQHandler(); +WEAK_DEFAULT void BDMA_Channel3_IRQHandler(); +WEAK_DEFAULT void BDMA_Channel4_IRQHandler(); +WEAK_DEFAULT void BDMA_Channel5_IRQHandler(); +WEAK_DEFAULT void BDMA_Channel6_IRQHandler(); +WEAK_DEFAULT void BDMA_Channel7_IRQHandler(); +WEAK_DEFAULT void COMP_IRQHandler(); +WEAK_DEFAULT void LPTIM2_IRQHandler(); +WEAK_DEFAULT void LPTIM3_IRQHandler(); +WEAK_DEFAULT void LPTIM4_IRQHandler(); +WEAK_DEFAULT void LPTIM5_IRQHandler(); +WEAK_DEFAULT void LPUART1_IRQHandler(); +WEAK_DEFAULT void CRS_IRQHandler(); +WEAK_DEFAULT void ECC_IRQHandler(); +WEAK_DEFAULT void SAI4_IRQHandler(); +WEAK_DEFAULT void WAKEUP_PIN_IRQHandler(); + +/* CPU specific interrupt vector table */ +const isr_t g_pnfVectors[] ISR_VECTOR = { + [0] = (isr_t)&_estack, + [1 ] = Reset_Handler, + [2 ] = NMI_Handler, + [3 ] = HardFault_Handler, + [4 ] = MemManage_Handler, + [5 ] = BusFault_Handler, + [6 ] = UsageFault_Handler, + [7 ] = 0, + [8 ] = 0, + [9 ] = 0, + [10 ] = 0, + [11 ] = SVC_Handler, + [12 ] = DebugMon_Handler, + [13 ] = 0, + [14 ] = PendSV_Handler, + [15 ] = SysTick_Handler, + [WWDG_IRQn + 16 ] = WWDG_IRQHandler, + [PVD_AVD_IRQn + 16 ] = PVD_AVD_IRQHandler, + [TAMP_STAMP_IRQn + 16 ] = TAMP_STAMP_IRQHandler, + [RTC_WKUP_IRQn + 16 ] = RTC_WKUP_IRQHandler, + [FLASH_IRQn + 16 ] = FLASH_IRQHandler, + [RCC_IRQn + 16 ] = RCC_IRQHandler, + [EXTI0_IRQn + 16 ] = EXTI0_IRQHandler, + [EXTI1_IRQn + 16 ] = EXTI1_IRQHandler, + [EXTI2_IRQn + 16 ] = EXTI2_IRQHandler, + [EXTI3_IRQn + 16 ] = EXTI3_IRQHandler, + [EXTI4_IRQn + 16 ] = EXTI4_IRQHandler, + [DMA1_Stream0_IRQn + 16 ] = DMA1_Stream0_IRQHandler, + [DMA1_Stream1_IRQn + 16 ] = DMA1_Stream1_IRQHandler, + [DMA1_Stream2_IRQn + 16 ] = DMA1_Stream2_IRQHandler, + [DMA1_Stream3_IRQn + 16 ] = DMA1_Stream3_IRQHandler, + [DMA1_Stream4_IRQn + 16 ] = DMA1_Stream4_IRQHandler, + [DMA1_Stream5_IRQn + 16 ] = DMA1_Stream5_IRQHandler, + [DMA1_Stream6_IRQn + 16 ] = DMA1_Stream6_IRQHandler, + [ADC_IRQn + 16 ] = ADC_IRQHandler, + [FDCAN1_IT0_IRQn + 16 ] = FDCAN1_IT0_IRQHandler, + [FDCAN2_IT0_IRQn + 16 ] = FDCAN2_IT0_IRQHandler, + [FDCAN1_IT1_IRQn + 16 ] = FDCAN1_IT1_IRQHandler, + [FDCAN2_IT1_IRQn + 16 ] = FDCAN2_IT1_IRQHandler, + [EXTI9_5_IRQn + 16 ] = EXTI9_5_IRQHandler, + [TIM1_BRK_IRQn + 16 ] = TIM1_BRK_IRQHandler, + [TIM1_UP_IRQn + 16 ] = TIM1_UP_IRQHandler, + [TIM1_TRG_COM_IRQn + 16 ] = TIM1_TRG_COM_IRQHandler, + [TIM1_CC_IRQn + 16 ] = TIM1_CC_IRQHandler, + [TIM2_IRQn + 16 ] = TIM2_IRQHandler, + [TIM3_IRQn + 16 ] = TIM3_IRQHandler, + [TIM4_IRQn + 16 ] = TIM4_IRQHandler, + [I2C1_EV_IRQn + 16 ] = I2C1_EV_IRQHandler, + [I2C1_ER_IRQn + 16 ] = I2C1_ER_IRQHandler, + [I2C2_EV_IRQn + 16 ] = I2C2_EV_IRQHandler, + [I2C2_ER_IRQn + 16 ] = I2C2_ER_IRQHandler, + [SPI1_IRQn + 16 ] = SPI1_IRQHandler, + [SPI2_IRQn + 16 ] = SPI2_IRQHandler, + [USART1_IRQn + 16 ] = USART1_IRQHandler, + [USART2_IRQn + 16 ] = USART2_IRQHandler, + [USART3_IRQn + 16 ] = USART3_IRQHandler, + [EXTI15_10_IRQn + 16 ] = EXTI15_10_IRQHandler, + [RTC_Alarm_IRQn + 16 ] = RTC_Alarm_IRQHandler, + [TIM8_BRK_TIM12_IRQn + 16 ] = TIM8_BRK_TIM12_IRQHandler, + [TIM8_UP_TIM13_IRQn + 16 ] = TIM8_UP_TIM13_IRQHandler, + [TIM8_TRG_COM_TIM14_IRQn + 16 ] = TIM8_TRG_COM_TIM14_IRQHandler, + [TIM8_CC_IRQn + 16 ] = TIM8_CC_IRQHandler, + [DMA1_Stream7_IRQn + 16 ] = DMA1_Stream7_IRQHandler, + [FMC_IRQn + 16 ] = FMC_IRQHandler, + [SDMMC1_IRQn + 16 ] = SDMMC1_IRQHandler, + [TIM5_IRQn + 16 ] = TIM5_IRQHandler, + [SPI3_IRQn + 16 ] = SPI3_IRQHandler, + [UART4_IRQn + 16 ] = UART4_IRQHandler, + [UART5_IRQn + 16 ] = UART5_IRQHandler, + [TIM6_DAC_IRQn + 16 ] = TIM6_DAC_IRQHandler, + [TIM7_IRQn + 16 ] = TIM7_IRQHandler, + [DMA2_Stream0_IRQn + 16 ] = DMA2_Stream0_IRQHandler, + [DMA2_Stream1_IRQn + 16 ] = DMA2_Stream1_IRQHandler, + [DMA2_Stream2_IRQn + 16 ] = DMA2_Stream2_IRQHandler, + [DMA2_Stream3_IRQn + 16 ] = DMA2_Stream3_IRQHandler, + [DMA2_Stream4_IRQn + 16 ] = DMA2_Stream4_IRQHandler, + [ETH_IRQn + 16 ] = ETH_IRQHandler, + [ETH_WKUP_IRQn + 16 ] = ETH_WKUP_IRQHandler, + [FDCAN_CAL_IRQn + 16 ] = FDCAN_CAL_IRQHandler, + [DMA2_Stream5_IRQn + 16 ] = DMA2_Stream5_IRQHandler, + [DMA2_Stream6_IRQn + 16 ] = DMA2_Stream6_IRQHandler, + [DMA2_Stream7_IRQn + 16 ] = DMA2_Stream7_IRQHandler, + [USART6_IRQn + 16 ] = USART6_IRQHandler, + [I2C3_EV_IRQn + 16 ] = I2C3_EV_IRQHandler, + [I2C3_ER_IRQn + 16 ] = I2C3_ER_IRQHandler, + [OTG_HS_EP1_OUT_IRQn + 16 ] = OTG_HS_EP1_OUT_IRQHandler, + [OTG_HS_EP1_IN_IRQn + 16 ] = OTG_HS_EP1_IN_IRQHandler, + [OTG_HS_WKUP_IRQn + 16 ] = OTG_HS_WKUP_IRQHandler, + [OTG_HS_IRQn + 16 ] = OTG_HS_IRQHandler, + [DCMI_IRQn + 16 ] = DCMI_IRQHandler, + [CRYP_IRQn + 16 ] = CRYP_IRQHandler, + [HASH_RNG_IRQn + 16 ] = HASH_RNG_IRQHandler, + [FPU_IRQn + 16 ] = FPU_IRQHandler, + [UART7_IRQn + 16 ] = UART7_IRQHandler, + [UART8_IRQn + 16 ] = UART8_IRQHandler, + [SPI4_IRQn + 16 ] = SPI4_IRQHandler, + [SPI5_IRQn + 16 ] = SPI5_IRQHandler, + [SPI6_IRQn + 16 ] = SPI6_IRQHandler, + [SAI1_IRQn + 16 ] = SAI1_IRQHandler, + [LTDC_IRQn + 16 ] = LTDC_IRQHandler, + [LTDC_ER_IRQn + 16 ] = LTDC_ER_IRQHandler, + [DMA2D_IRQn + 16 ] = DMA2D_IRQHandler, + [SAI2_IRQn + 16 ] = SAI2_IRQHandler, + [QUADSPI_IRQn + 16 ] = QUADSPI_IRQHandler, + [LPTIM1_IRQn + 16 ] = LPTIM1_IRQHandler, + [CEC_IRQn + 16 ] = CEC_IRQHandler, + [I2C4_EV_IRQn + 16 ] = I2C4_EV_IRQHandler, + [I2C4_ER_IRQn + 16 ] = I2C4_ER_IRQHandler, + [SPDIF_RX_IRQn + 16 ] = SPDIF_RX_IRQHandler, + [OTG_FS_EP1_OUT_IRQn + 16 ] = OTG_FS_EP1_OUT_IRQHandler, + [OTG_FS_EP1_IN_IRQn + 16 ] = OTG_FS_EP1_IN_IRQHandler, + [OTG_FS_WKUP_IRQn + 16 ] = OTG_FS_WKUP_IRQHandler, + [OTG_FS_IRQn + 16 ] = OTG_FS_IRQHandler, + [DMAMUX1_OVR_IRQn + 16 ] = DMAMUX1_OVR_IRQHandler, + [HRTIM1_Master_IRQn + 16 ] = HRTIM1_Master_IRQHandler, + [HRTIM1_TIMA_IRQn + 16 ] = HRTIM1_TIMA_IRQHandler, + [HRTIM1_TIMB_IRQn + 16 ] = HRTIM1_TIMB_IRQHandler, + [HRTIM1_TIMC_IRQn + 16 ] = HRTIM1_TIMC_IRQHandler, + [HRTIM1_TIMD_IRQn + 16 ] = HRTIM1_TIMD_IRQHandler, + [HRTIM1_TIME_IRQn + 16 ] = HRTIM1_TIME_IRQHandler, + [HRTIM1_FLT_IRQn + 16 ] = HRTIM1_FLT_IRQHandler, + [DFSDM1_FLT0_IRQn + 16 ] = DFSDM1_FLT0_IRQHandler, + [DFSDM1_FLT1_IRQn + 16 ] = DFSDM1_FLT1_IRQHandler, + [DFSDM1_FLT2_IRQn + 16 ] = DFSDM1_FLT2_IRQHandler, + [DFSDM1_FLT3_IRQn + 16 ] = DFSDM1_FLT3_IRQHandler, + [SAI3_IRQn + 16 ] = SAI3_IRQHandler, + [SWPMI1_IRQn + 16 ] = SWPMI1_IRQHandler, + [TIM15_IRQn + 16 ] = TIM15_IRQHandler, + [TIM16_IRQn + 16 ] = TIM16_IRQHandler, + [TIM17_IRQn + 16 ] = TIM17_IRQHandler, + [MDIOS_WKUP_IRQn + 16 ] = MDIOS_WKUP_IRQHandler, + [MDIOS_IRQn + 16 ] = MDIOS_IRQHandler, + [JPEG_IRQn + 16 ] = JPEG_IRQHandler, + [MDMA_IRQn + 16 ] = MDMA_IRQHandler, + [SDMMC2_IRQn + 16 ] = SDMMC2_IRQHandler, + [HSEM1_IRQn + 16 ] = HSEM1_IRQHandler, + [ADC3_IRQn + 16 ] = ADC3_IRQHandler, + [DMAMUX2_OVR_IRQn + 16 ] = DMAMUX2_OVR_IRQHandler, + [BDMA_Channel0_IRQn + 16 ] = BDMA_Channel0_IRQHandler, + [BDMA_Channel1_IRQn + 16 ] = BDMA_Channel1_IRQHandler, + [BDMA_Channel2_IRQn + 16 ] = BDMA_Channel2_IRQHandler, + [BDMA_Channel3_IRQn + 16 ] = BDMA_Channel3_IRQHandler, + [BDMA_Channel4_IRQn + 16 ] = BDMA_Channel4_IRQHandler, + [BDMA_Channel5_IRQn + 16 ] = BDMA_Channel5_IRQHandler, + [BDMA_Channel6_IRQn + 16 ] = BDMA_Channel6_IRQHandler, + [BDMA_Channel7_IRQn + 16 ] = BDMA_Channel7_IRQHandler, + [COMP_IRQn + 16 ] = COMP_IRQHandler, + [LPTIM2_IRQn + 16 ] = LPTIM2_IRQHandler, + [LPTIM3_IRQn + 16 ] = LPTIM3_IRQHandler, + [LPTIM4_IRQn + 16 ] = LPTIM4_IRQHandler, + [LPTIM5_IRQn + 16 ] = LPTIM5_IRQHandler, + [LPUART1_IRQn + 16 ] = LPUART1_IRQHandler, + [CRS_IRQn + 16 ] = CRS_IRQHandler, + [ECC_IRQn + 16 ] = ECC_IRQHandler, + [SAI4_IRQn + 16 ] = SAI4_IRQHandler, + [WAKEUP_PIN_IRQn + 16 ] = WAKEUP_PIN_IRQHandler, +}; + diff --git a/radio/src/targets/common/arm/stm32/system_init.c b/radio/src/targets/common/arm/stm32/system_init.c index 358a90e2bf2..596de25e1a7 100644 --- a/radio/src/targets/common/arm/stm32/system_init.c +++ b/radio/src/targets/common/arm/stm32/system_init.c @@ -31,7 +31,9 @@ #endif #if (defined (USE_CACHE) && defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)) -#define REQUIRE_MPU_CONFIG + #ifndef RADIO_MODAL + #define REQUIRE_MPU_CONFIG + #endif #endif #if defined(ITCM_BASE) /* H7RS */ || defined(D1_ITCMRAM_BASE) /* H7 */ diff --git a/radio/src/targets/modalai/CMakeLists.txt b/radio/src/targets/modalai/CMakeLists.txt index 0d6ac57687d..64b1d580edc 100644 --- a/radio/src/targets/modalai/CMakeLists.txt +++ b/radio/src/targets/modalai/CMakeLists.txt @@ -83,8 +83,6 @@ set(TARGET_SRC_DIR targets/${TARGET_DIR}) set(BOARD_COMMON_SRC ${TARGET_SRC_DIR}/board.cpp - ${TARGET_SRC_DIR}/system_init.cpp - ${TARGET_SRC_DIR}/system_clock.cpp ${TARGET_SRC_DIR}/led_driver.cpp ${TARGET_SRC_DIR}/backlight_driver.cpp ${TARGET_SRC_DIR}/${LCD_DRIVER} @@ -112,8 +110,8 @@ endif() # Bootloader board library add_library(board_bl OBJECT EXCLUDE_FROM_ALL ${BOARD_COMMON_SRC} - ${TARGET_SRC_DIR}/system_clock.cpp - ${TARGET_SRC_DIR}/bootloader/boot_menu.cpp + ${TARGET_SRC_DIR}/system_clock.c + ${RADIO_SRC_DIR}/gui/common/stdlcd/boot_menu.cpp ) add_dependencies(board_bl ${BITMAPS_TARGET}) set(BOOTLOADER_SRC ${BOOTLOADER_SRC} $) @@ -178,11 +176,4 @@ set(GUI_SRC ${GUI_SRC} bmp.cpp ) -# There has to be a better way... -# In C23 there is now support for #embed... -set(FIRMWARE_SRC - ${FIRMWARE_SRC} - targets/common/arm/loadboot.cpp -) - set(RADIO_DEPENDENCIES ${RADIO_DEPENDENCIES} ${BITMAPS_TARGET}) diff --git a/radio/src/targets/modalai/bootloader/boot_menu.cpp b/radio/src/targets/modalai/bootloader/boot_menu.cpp deleted file mode 100644 index 6c4e97b5c51..00000000000 --- a/radio/src/targets/modalai/bootloader/boot_menu.cpp +++ /dev/null @@ -1,162 +0,0 @@ -/* - * Copyright (C) EdgeTX - * - * Based on code named - * opentx - https://github.com/opentx/opentx - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - #include - - #include "board.h" - #include "lcd.h" - - #include "translations.h" - - #include "fw_version.h" - #include "translations.h" - #include "../../common/arm/stm32/bootloader/boot.h" - #include "bootloader/firmware_files.h" - - void bootloaderInitScreen() - { - lcdInit(); - lcdSetContrast(true); - - backlightInit(); - #if defined(LCD_BRIGHTNESS_DEFAULT) - backlightEnable(LCD_BRIGHTNESS_DEFAULT); - #else - backlightFullOn(); - #endif - } - - static void bootloaderDrawMsg(unsigned int x, const char *str, uint8_t line, bool inverted) - { - lcdDrawSizedText(x, (line + 2) * FH, str, DISPLAY_CHAR_WIDTH, inverted ? INVERS : 0); - } - - void bootloaderDrawFilename(const char *str, uint8_t line, bool selected) - { - bootloaderDrawMsg(INDENT_WIDTH, str, line, selected); - } - - bool checkFirmwareFlavor(const char * flavour) - { - if (strncmp(flavour,FLAVOUR, sizeof(FLAVOUR) - 1) != 0) - return false; - - char * tmp = (char *) flavour; - while (*tmp != 0) tmp++; - if ((tmp - flavour) != (sizeof(FLAVOUR) - 1)) - return false; - - return true; - } - - void bootloaderDrawScreen(BootloaderState st, int opt, const char *str) - { - lcdClear(); - lcdDrawText(LCD_W / 2, 0, BOOTLOADER_TITLE, CENTERED); - lcdInvertLine(0); - - if (st == ST_START) { - lcdDrawText(3*FW, 2*FH, TR_BL_WRITE_FW, opt == 0 ? INVERS : 0); - lcdDrawText(3*FW, 3*FH, TR_BL_EXIT, opt == 1 ? INVERS : 0); - - lcdDrawText(LCD_W / 2, 5 * FH + FH / 2, TR_BL_OR_PLUGIN_USB_CABLE, CENTERED); - - const char * vers = getFirmwareVersion(); - #if LCD_W < 212 - // Remove "edgetx-" from string - if (strncmp(vers, "edgetx-", 7) == 0) - vers += 7; - #endif - lcdDrawCenteredText(7 * FH, vers); - lcdInvertLine(7); - } - else if (st == ST_USB) { - lcdDrawCenteredText(4 * FH, TR_BL_USB_CONNECTED); - } - else if (st == ST_DIR_CHECK) { - if (opt == FR_NO_PATH) { - bootloaderDrawMsg(INDENT_WIDTH, TR_BL_DIR_MISSING, 1, false); - bootloaderDrawMsg(INDENT_WIDTH, getFirmwarePath(), 2, false); - } - else { - bootloaderDrawMsg(INDENT_WIDTH, TR_BL_DIR_EMPTY, 1, false); - } - } - else if (st == ST_FLASH_CHECK) { - if (opt == FC_ERROR) { - bootloaderDrawMsg(0, TR_BL_INVALID_FIRMWARE, 2, false); - } - else if (opt == FC_OK) { - bool flavorCheck = false; - VersionTag tag; - getFileFirmwareVersion(&tag); - #if LCD_W < 212 - // Remove "edgetx-" from string - flavorCheck = checkFirmwareFlavor(tag.flavour); - #else - flavorCheck = checkFirmwareFlavor(tag.flavour); - #endif - bootloaderDrawMsg(INDENT_WIDTH, tag.version, 0, false); - if (flavorCheck) - bootloaderDrawMsg(0, TR_BL_HOLD_ENTER_TO_START, 2, false); - else - bootloaderDrawMsg(0, TR_BL_INVALID_FIRMWARE, 2, false); - } - } - else if (st == ST_FLASHING) { - lcdDrawCenteredText(4 * FH, TR_BL_WRITING_FW); - - lcdDrawRect(3, 6 * FH + 4, (LCD_W - 8), 7); - lcdDrawSolidHorizontalLine(5, 6 * FH + 6, (LCD_W - 12) * opt / 100, FORCE); - lcdDrawSolidHorizontalLine(5, 6 * FH + 7, (LCD_W - 12) * opt / 100, FORCE); - lcdDrawSolidHorizontalLine(5, 6 * FH + 8, (LCD_W - 12) * opt / 100, FORCE); - } - else if (st == ST_FLASH_DONE) { - lcdDrawCenteredText(4 * FH, TR_BL_WRITING_COMPL); - } - } - - uint32_t bootloaderGetMenuItemCount(int baseCount) - { - return baseCount; - } - - bool bootloaderRadioMenu(uint32_t menuItem, event_t event) - { - return true; - } - - void blExit(void) - { - #if defined(RADIO_COMMANDO8) - lcdClear(); - lcdDrawText(2, 22, TR_BL_POWER_KEY); - lcdDrawText(2, 33, TR_BL_FLASH_EXIT); - lcdRefresh(); - lcdRefreshWait(); - while(1); - #else - lcdClear(); - lcdRefresh(); - lcdRefreshWait(); - #endif - } - \ No newline at end of file diff --git a/radio/src/targets/modalai/system_clock.cpp b/radio/src/targets/modalai/system_clock.c similarity index 99% rename from radio/src/targets/modalai/system_clock.cpp rename to radio/src/targets/modalai/system_clock.c index c52d590f18c..0639f099ae5 100644 --- a/radio/src/targets/modalai/system_clock.cpp +++ b/radio/src/targets/modalai/system_clock.c @@ -51,8 +51,7 @@ * @param None * @retval None */ -extern "C" BOOTSTRAP -void SystemClock_Config() +BOOTSTRAP void SystemClock_Config() { RCC_OscInitTypeDef RCC_OscInitStruct = {0}; diff --git a/radio/src/targets/modalai/system_clock.h b/radio/src/targets/modalai/system_clock.h index 758d63c32a0..10b69a11885 100644 --- a/radio/src/targets/modalai/system_clock.h +++ b/radio/src/targets/modalai/system_clock.h @@ -19,5 +19,5 @@ * GNU General Public License for more details. */ -extern "C" void SystemClock_Config(); +void SystemClock_Config(); diff --git a/radio/src/targets/modalai/system_init.cpp b/radio/src/targets/modalai/system_init.cpp deleted file mode 100644 index 7d7d4498d3f..00000000000 --- a/radio/src/targets/modalai/system_init.cpp +++ /dev/null @@ -1,186 +0,0 @@ -#include -#include "stm32_cmsis.h" -#include "system_clock.h" - -#include "stm32_hal.h" - -#define NAKED __attribute__((naked)) -#define BOOTSTRAP __attribute__((section(".bootstrap"))) - -// Linker script symbols -extern uint32_t _sisr_vector; -extern uint32_t _dram_addr; -extern uint32_t PSRAM_START; -extern uint32_t NORFLASH_START; - -extern "C" NAKED BOOTSTRAP -void Reset_Handler() -{ - asm inline ( - "ldr sp, =_estack \n" - ); - -#if defined(BOOT) - asm inline ( - "bl SystemClock_Config \n" - "bl CPU_CACHE_Enable \n" - ); -#endif - - // TODO: Clock config should be first so this will go faster - // Copy code into normal RAM - asm inline ( - "ldr r0, =_stext \n" - "ldr r1, =_etext \n" - "ldr r2, =_text_load \n" - "bl naked_copy \n" - ); - -#if defined(BOOT) - asm inline ( - "bl SystemInit \n" - "bl MPU_Init \n" - ); -#endif - - // Copy / setup ISR vector - asm inline ( - "ldr r0, =_sisr_vector \n" - "ldr r1, =_eisr_vector \n" - "ldr r2, =_isr_load \n" - "bl naked_copy \n" - "bl set_vtor \n" - ); - - // Copy code into fast RAM - asm inline ( - "ldr r0, =_siram \n" - "ldr r1, =_eiram \n" - "ldr r2, =_stext_iram \n" - "bl naked_copy \n" - ); - - // Copy initialized data segment - asm inline ( - "ldr r0, =_sdata \n" - "ldr r1, =_edata \n" - "ldr r2, =_sidata \n" - "bl naked_copy \n" - ); - - // Zero fill bss segment - asm inline ( - "ldr r2, =_sbss \n" - "ldr r4, =_ebss \n" - "movs r3, 0 \n" - "b LoopFillZerobss \n" - - "FillZerobss: \n" - "str r3, [r2] \n" - "adds r2, r2, 4 \n" - - "LoopFillZerobss: \n" - "cmp r2, r4 \n" - "bcc FillZerobss \n" - ); - - asm inline ( - "bl clean_dcache \n" - // Call static constructors - "bl __libc_init_array \n" - "bl SystemCoreClockUpdate \n" - // Call the application's entry point - "bl main \n" - "bx lr \n" - ); -} - -extern "C" BOOTSTRAP void set_vtor() { - SCB->VTOR = (intptr_t)&_sisr_vector; -} - -extern "C" NAKED BOOTSTRAP void naked_copy() { - // r0: destination start - // r1: destination end - // r2: source start - asm inline ( - "cmp r0, r2 \n" - "beq SkipCopy \n" - "movs r3, 0 \n" - "b LoopCopyInit \n" - - "CopyInit: \n" - "ldr r4, [r2, r3] \n" - "str r4, [r0, r3] \n" - "adds r3, r3, #4 \n" - - "LoopCopyInit: \n" - "adds r4, r0, r3 \n" - "cmp r4, r1 \n" - "bcc CopyInit \n" - "SkipCopy: \n" - "bx lr \n" - ); -} - -extern "C" BOOTSTRAP -void CPU_CACHE_Enable() -{ - /* Enable I-Cache */ - SCB_EnableICache(); - - /* Enable D-Cache */ - SCB_EnableDCache(); -} - -extern "C" __attribute__((used)) -void MPU_Init() -{ - MPU_Region_InitTypeDef MPU_InitStruct = {0}; - - /* Disables the MPU */ - HAL_MPU_Disable(); - - /* - * Region 0: overwrite default setting to prevent speculative - * read to unavailable memories. - * Range: 0x60000000 to 0xE0000000 - * - * Set as strongly ordered, code execution disabled - */ - MPU_InitStruct.Enable = MPU_REGION_ENABLE; - MPU_InitStruct.Number = MPU_REGION_NUMBER0; - MPU_InitStruct.BaseAddress = 0; - MPU_InitStruct.Size = MPU_REGION_SIZE_4GB; - MPU_InitStruct.SubRegionDisable = 0x87; - MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0; - MPU_InitStruct.AccessPermission = MPU_REGION_NO_ACCESS; - MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE; - MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE; - MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE; - MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE; - HAL_MPU_ConfigRegion(&MPU_InitStruct); - - // /* Region 3: DMA memory range */ - // MPU_InitStruct.Enable = MPU_REGION_ENABLE; - // MPU_InitStruct.Number = MPU_REGION_NUMBER4; - // MPU_InitStruct.BaseAddress = (uint32_t)&_dram_addr; - // MPU_InitStruct.Size = MPU_REGION_SIZE_64KB; // actually 72KB - // MPU_InitStruct.SubRegionDisable = 0x0; - // MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1; - // MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS; - // MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE; - // MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE; - // MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE; - // MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE; - // HAL_MPU_ConfigRegion(&MPU_InitStruct); - - HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT); - - /* Enable bus fault exception */ - SCB->SHCSR |= SCB_SHCSR_BUSFAULTENA_Msk; -} - -extern "C" void clean_dcache() { - SCB_CleanDCache(); -} From 4201b72ee4d33d1961a497aafc63a12b0158a62e Mon Sep 17 00:00:00 2001 From: benjinne Date: Mon, 11 Aug 2025 18:52:59 -0700 Subject: [PATCH 28/54] zorro-blue system_init don't include extram since this h7 board doesn't have it --- radio/src/targets/common/arm/stm32/system_init.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/radio/src/targets/common/arm/stm32/system_init.c b/radio/src/targets/common/arm/stm32/system_init.c index 596de25e1a7..af622a7413e 100644 --- a/radio/src/targets/common/arm/stm32/system_init.c +++ b/radio/src/targets/common/arm/stm32/system_init.c @@ -31,9 +31,7 @@ #endif #if (defined (USE_CACHE) && defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)) - #ifndef RADIO_MODAL - #define REQUIRE_MPU_CONFIG - #endif + #define REQUIRE_MPU_CONFIG #endif #if defined(ITCM_BASE) /* H7RS */ || defined(D1_ITCMRAM_BASE) /* H7 */ @@ -203,11 +201,13 @@ BOOTSTRAP void CPU_CACHE_Enable() #if defined(BOOT) && defined(REQUIRE_MPU_CONFIG) // Linker script symbols +#ifndef RADIO_MODAL // no extram on modalAI h7 extern uint32_t _dram_addr; extern uint32_t EXTRAM_START; extern uint32_t EXTRAM_SIZE; extern uint32_t NORFLASH_START; extern uint32_t NORFLASH_SIZE; +#endif __STATIC_FORCEINLINE uint32_t mpu_region_size(uint32_t size) { @@ -240,7 +240,7 @@ void MPU_Config() MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE; MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE; HAL_MPU_ConfigRegion(&MPU_InitStruct); - +#ifndef RADIO_MODAL // no extram on modalAI h7 /* Region 2: QSPI memory range, bank1 */ MPU_InitStruct.Enable = MPU_REGION_ENABLE; MPU_InitStruct.Number = MPU_REGION_NUMBER2; @@ -282,6 +282,7 @@ void MPU_Config() MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE; MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE; HAL_MPU_ConfigRegion(&MPU_InitStruct); + #endif HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT); From 0d8729392860c9335c10e85c24dbd8b7d097f1b1 Mon Sep 17 00:00:00 2001 From: benjinne Date: Mon, 11 Aug 2025 18:53:10 -0700 Subject: [PATCH 29/54] zorro-blue re-add bootloader to firmware --- radio/src/targets/modalai/CMakeLists.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/radio/src/targets/modalai/CMakeLists.txt b/radio/src/targets/modalai/CMakeLists.txt index 64b1d580edc..57ba07d0630 100644 --- a/radio/src/targets/modalai/CMakeLists.txt +++ b/radio/src/targets/modalai/CMakeLists.txt @@ -176,4 +176,9 @@ set(GUI_SRC ${GUI_SRC} bmp.cpp ) +set(FIRMWARE_SRC + ${FIRMWARE_SRC} + bootloader/loadboot.cpp +) + set(RADIO_DEPENDENCIES ${RADIO_DEPENDENCIES} ${BITMAPS_TARGET}) From 37e7932a21409f4550b64854f216dec35547b630 Mon Sep 17 00:00:00 2001 From: benjinne Date: Mon, 11 Aug 2025 19:11:11 -0700 Subject: [PATCH 30/54] zorro-blue revert bootloader debug --- radio/src/bootloader/boot.cpp | 7 ------- 1 file changed, 7 deletions(-) diff --git a/radio/src/bootloader/boot.cpp b/radio/src/bootloader/boot.cpp index 318834c4364..805977d64d1 100644 --- a/radio/src/bootloader/boot.cpp +++ b/radio/src/bootloader/boot.cpp @@ -29,7 +29,6 @@ #include "debug.h" #include "timers_driver.h" -#include "fw_desc.h" #if defined(BLUETOOTH) #include "bluetooth_driver.h" @@ -62,14 +61,8 @@ typedef void (*fctptr_t)(void); static __attribute__((noreturn)) void jumpTo(uint32_t addr) { __disable_irq(); -#if defined(STM32H7) - firmware_description_t *fw_desc = (firmware_description_t*)APP_START_ADDRESS; - fctptr_t reset_handler = (fctptr_t) fw_desc->reset_handler; - __set_MSP((uint32_t) fw_desc->stack_address); -#else __set_MSP(*(uint32_t*)addr); fctptr_t reset_handler = (fctptr_t)*(uint32_t*)(addr + 4); -#endif reset_handler(); while(1){} } From 91ae6f440244d8f853c6fb4450af8e55ec55f6f7 Mon Sep 17 00:00:00 2001 From: benjinne Date: Mon, 11 Aug 2025 21:30:45 -0700 Subject: [PATCH 31/54] zorro-blue revert unrelated changes back to main --- .github/workflows/build_fw.yml | 6 +- .github/workflows/linux_cpn.yml | 6 +- .github/workflows/macosx_cpn.yml | 4 +- .github/workflows/nightly.yml | 2 +- .github/workflows/win_cpn-32.yml | 100 ++++++++++++++++++ .github/workflows/win_cpn-64.yml | 4 +- .gitpod.yml | 2 +- companion/src/translations/companion_cs.ts | 16 +-- companion/src/translations/companion_da.ts | 14 +-- companion/src/translations/companion_de.ts | 16 +-- companion/src/translations/companion_en.ts | 14 +-- companion/src/translations/companion_es.ts | 16 +-- companion/src/translations/companion_fi.ts | 16 +-- companion/src/translations/companion_fr.ts | 16 +-- companion/src/translations/companion_he.ts | 16 +-- companion/src/translations/companion_it.ts | 16 +-- companion/src/translations/companion_ja.ts | 14 +-- companion/src/translations/companion_nl.ts | 16 +-- companion/src/translations/companion_pl.ts | 16 +-- companion/src/translations/companion_pt.ts | 16 +-- companion/src/translations/companion_ru.ts | 16 +-- companion/src/translations/companion_zh_CN.ts | 16 +-- companion/src/translations/companion_zh_TW.ts | 16 +-- 23 files changed, 237 insertions(+), 137 deletions(-) create mode 100644 .github/workflows/win_cpn-32.yml diff --git a/.github/workflows/build_fw.yml b/.github/workflows/build_fw.yml index 3878cf1b338..5d52656aedb 100644 --- a/.github/workflows/build_fw.yml +++ b/.github/workflows/build_fw.yml @@ -3,7 +3,7 @@ name: Run tests and package firmware on: push: branches: - - '2.11' + - 'main' tags: - v* paths: @@ -56,7 +56,7 @@ jobs: - nb4p - st16 container: - image: ghcr.io/edgetx/edgetx-dev:2.11 + image: ghcr.io/edgetx/edgetx-dev:latest volumes: - ${{ github.workspace }}:/src steps: @@ -103,7 +103,7 @@ jobs: - nb4p - st16 container: - image: ghcr.io/edgetx/edgetx-dev:2.11 + image: ghcr.io/edgetx/edgetx-dev:latest volumes: - ${{ github.workspace }}:/src steps: diff --git a/.github/workflows/linux_cpn.yml b/.github/workflows/linux_cpn.yml index a021cc17145..c282a5274ed 100644 --- a/.github/workflows/linux_cpn.yml +++ b/.github/workflows/linux_cpn.yml @@ -3,7 +3,7 @@ name: Linux Companion on: push: branches: - - '2.11' + - 'main' tags: - v* paths: @@ -13,7 +13,7 @@ on: pull_request: branches: - - '2.11' + - 'main' paths: - '.github/workflows/linux_cpn.yml' - 'companion/**' @@ -29,7 +29,7 @@ jobs: build: runs-on: ubuntu-latest container: - image: ghcr.io/edgetx/edgetx-dev:2.11 + image: ghcr.io/edgetx/edgetx-dev:latest volumes: - ${{ github.workspace }}:/src diff --git a/.github/workflows/macosx_cpn.yml b/.github/workflows/macosx_cpn.yml index 3c5c23f094f..cdee31fcdd7 100644 --- a/.github/workflows/macosx_cpn.yml +++ b/.github/workflows/macosx_cpn.yml @@ -3,7 +3,7 @@ name: MacOSX Companion on: push: branches: - - '2.11' + - 'main' tags: - v* paths: @@ -13,7 +13,7 @@ on: pull_request: branches: - - '2.11' + - 'main' paths: - '.github/workflows/macosx_cpn.yml' - 'companion/**' diff --git a/.github/workflows/nightly.yml b/.github/workflows/nightly.yml index 2d252abfc01..2c838b27f14 100644 --- a/.github/workflows/nightly.yml +++ b/.github/workflows/nightly.yml @@ -38,7 +38,7 @@ jobs: - st16 - tx15 container: - image: ghcr.io/edgetx/edgetx-dev:2.11 + image: ghcr.io/edgetx/edgetx-dev:latest volumes: - ${{ github.workspace }}:/src steps: diff --git a/.github/workflows/win_cpn-32.yml b/.github/workflows/win_cpn-32.yml new file mode 100644 index 00000000000..1fb67e40199 --- /dev/null +++ b/.github/workflows/win_cpn-32.yml @@ -0,0 +1,100 @@ +name: Windows Companion 32-bit + +on: + push: + branches: + - 'main' + tags: + - v* + paths: + - '.github/workflows/win_cpn-32.yml' + - 'companion/**' + - 'tools/build-companion.sh' + + workflow_dispatch: + +env: + # Customize the CMake build type here (Release, Debug, RelWithDebInfo, etc.) + BUILD_TYPE: Release + CMAKE_GENERATOR: "MSYS Makefiles" + QT_VERSION: "5.15.2" + MINGW_VERSION: "win32_mingw81" + MINGW_PATH: "mingw81_32" + +jobs: + build: + # The CMake configure and build commands are platform agnostic and should work equally + # well on Windows or Mac. You can convert this to a matrix build if you need + # cross-platform coverage. + # See: https://docs.github.com/en/free-pro-team@latest/actions/learn-github-actions/managing-complex-workflows#using-a-build-matrix + runs-on: windows-latest + defaults: + run: + shell: msys2 {0} + + steps: + - uses: msys2/setup-msys2@v2 + with: + msystem: MINGW32 + update: true + install: git make curl tar mingw-w64-i686-toolchain + + - name: Install Dependencies + run: | + pacman -S --noconfirm mingw-w64-i686-cmake \ + mingw-w64-i686-python-pip \ + mingw-w64-i686-python-pillow \ + mingw-w64-i686-libjpeg-turbo \ + mingw-w64-i686-zlib \ + mingw-w64-i686-libtiff \ + mingw-w64-i686-freetype \ + mingw-w64-i686-lcms2 \ + mingw-w64-i686-libwebp \ + mingw-w64-i686-openjpeg2 \ + mingw-w64-i686-libimagequant \ + mingw-w64-i686-libraqm \ + mingw-w64-i686-SDL2 \ + mingw-w64-i686-clang \ + mingw-w64-i686-nsis \ + mingw-w64-i686-openssl + SETUPTOOLS_USE_DISTUTILS=stdlib pip install lz4 + python -m pip install clang jinja2 lz4 + + - name: Download and unpack dfu-util + run: | + curl -LO https://dfu-util.sourceforge.net/releases/dfu-util-0.11-binaries.tar.xz && \ + tar -xf dfu-util-0.11-binaries.tar.xz + cp dfu-util-0.11-binaries/win32/dfu-util-static.exe /mingw32/bin/dfu-util.exe + cp dfu-util-0.11-binaries/win32/libusb-1.0.dll /mingw32/bin/libusb-1.0.dll + cp dfu-util-0.11-binaries/win32/libusb-1.0.dll.a /mingw32/bin/libusb-1.0.dll.a + + - name: Install Qt + uses: jurplel/install-qt-action@v3 + with: + cache: true + cache-key-prefix: 'install-qt-action-win32' + version: ${{ env.QT_VERSION }} + arch: ${{ env.MINGW_VERSION }} + + - name: Check out the repo + uses: actions/checkout@v4 + with: + submodules: recursive + + - name: Build + working-directory: ${{github.workspace}} + # Execute the build. You can specify a specific target with "--target " + run: | + mkdir output && \ + CMAKE_PREFIX_PATH=$RUNNER_WORKSPACE/Qt/$QT_VERSION/$MINGW_PATH \ + tools/build-companion.sh "$(pwd)" "$(pwd)/output/" + - name: Compose release filename + # https://stackoverflow.com/questions/58033366/how-to-get-current-branch-within-github-actions + run: echo "artifact_name=edgetx-cpn-win32-${GITHUB_REF##*/}" >> $GITHUB_ENV + + - name: Archive production artifacts + uses: actions/upload-artifact@v4 + with: + name: "${{ env.artifact_name }}" + path: ${{github.workspace}}/output + retention-days: 15 diff --git a/.github/workflows/win_cpn-64.yml b/.github/workflows/win_cpn-64.yml index a30712f00f4..a73643d6aab 100644 --- a/.github/workflows/win_cpn-64.yml +++ b/.github/workflows/win_cpn-64.yml @@ -3,7 +3,7 @@ name: Windows Companion 64-bit on: push: branches: - - '2.11' + - 'main' tags: - v* paths: @@ -13,7 +13,7 @@ on: pull_request: branches: - - '2.11' + - 'main' paths: - '.github/workflows/win_cpn-64.yml' - 'companion/**' diff --git a/.gitpod.yml b/.gitpod.yml index 2ca361697af..ecb5b54cb9e 100644 --- a/.gitpod.yml +++ b/.gitpod.yml @@ -1,4 +1,4 @@ -image: ghcr.io/edgetx/gitpod-workspace:2.11 +image: ghcr.io/edgetx/gitpod-workspace:latest tasks: - name: Prep build folder diff --git a/companion/src/translations/companion_cs.ts b/companion/src/translations/companion_cs.ts index e5ea2b313b2..b284c3cbc12 100644 --- a/companion/src/translations/companion_cs.ts +++ b/companion/src/translations/companion_cs.ts @@ -7304,42 +7304,42 @@ Sloupce pro nadmořskou výšku "GAlt" a pro rychlost "GSpd" - + Tabbed Windows Okna se záložkami - + Use tabs to arrange open windows. Pomocí záložek můžete uspořádat otevřená okna. - + Tile Windows Dlaždice - + Arrange open windows across all the available space. Uspořádá otevřená okna napříč celým volným prostorem. - + Cascade Windows Kaskádová okna - + Arrange all open windows in a stack. Uspořádá všechna otevřená okna do kaskády. - + Close All Windows Zavřít všechna okna - + Closes all open files (prompts to save if necessary. Zavře všechny otevřené soubory (v případě potřeby vás požádá o uložení). diff --git a/companion/src/translations/companion_da.ts b/companion/src/translations/companion_da.ts index 9b879c79ad4..47a9600d46d 100644 --- a/companion/src/translations/companion_da.ts +++ b/companion/src/translations/companion_da.ts @@ -7760,37 +7760,37 @@ Vil du fortsætte? Arrangeret med faner - + Use tabs to arrange open windows. Brug tab for at arrangere åbne vinduer. - + Tile Windows Arrangeret som fliser - + Arrange open windows across all the available space. Arrangeret med åbne vinduer fordelt over den mulige plads. - + Cascade Windows Arrangeret som kaskade vinduer - + Arrange all open windows in a stack. Arrangeret ved stabling af åbne vinduer. - + Close All Windows Luk alle vinduer - + Closes all open files (prompts to save if necessary. Luk alle åbne filer (du får mulighed for at gemme først). diff --git a/companion/src/translations/companion_de.ts b/companion/src/translations/companion_de.ts index 4f18428b541..82a8b410c9c 100644 --- a/companion/src/translations/companion_de.ts +++ b/companion/src/translations/companion_de.ts @@ -7341,42 +7341,42 @@ Do you wish to continue? - + Tabbed Windows - + Use tabs to arrange open windows. - + Tile Windows - + Arrange open windows across all the available space. - + Cascade Windows - + Arrange all open windows in a stack. - + Close All Windows - + Closes all open files (prompts to save if necessary. diff --git a/companion/src/translations/companion_en.ts b/companion/src/translations/companion_en.ts index e120e96ab81..37cc56cd6e6 100644 --- a/companion/src/translations/companion_en.ts +++ b/companion/src/translations/companion_en.ts @@ -7309,7 +7309,7 @@ The columns for altitude "GAlt" and for speed "GSpd" are opt - + Tabbed Windows @@ -7454,12 +7454,12 @@ The columns for altitude "GAlt" and for speed "GSpd" are opt - + Cascade Windows - + Close All Windows @@ -7573,22 +7573,22 @@ The columns for altitude "GAlt" and for speed "GSpd" are opt - + Use tabs to arrange open windows. - + Arrange open windows across all the available space. - + Arrange all open windows in a stack. - + Closes all open files (prompts to save if necessary. diff --git a/companion/src/translations/companion_es.ts b/companion/src/translations/companion_es.ts index 1ad252c88d6..bd0c378318c 100644 --- a/companion/src/translations/companion_es.ts +++ b/companion/src/translations/companion_es.ts @@ -7428,42 +7428,42 @@ Do you wish to continue? Carga los ajustes de %1 y del simulador desde un fichero de ajustes exportado previamente - + Use tabs to arrange open windows. Usa las pestañas para organizar las ventanas abiertas - + Tabbed Windows Ventanas con pestañas - + Tile Windows Ventanas en cascada - + Arrange open windows across all the available space. Organiza las ventanas en todo el espacio disponible - + Cascade Windows Ventanas en cascada - + Arrange all open windows in a stack. Organiza todas las ventanas abiertas en una cascada - + Close All Windows Cierra todas las ventanas - + Closes all open files (prompts to save if necessary. Cierra todos los archivos abiertos (pregunta guardar si es necesario) diff --git a/companion/src/translations/companion_fi.ts b/companion/src/translations/companion_fi.ts index 58e9fb02db6..fa136dd83e3 100644 --- a/companion/src/translations/companion_fi.ts +++ b/companion/src/translations/companion_fi.ts @@ -7432,42 +7432,42 @@ Do you wish to continue? - + Tabbed Windows - + Use tabs to arrange open windows. - + Tile Windows - + Arrange open windows across all the available space. - + Cascade Windows - + Arrange all open windows in a stack. - + Close All Windows - + Closes all open files (prompts to save if necessary. diff --git a/companion/src/translations/companion_fr.ts b/companion/src/translations/companion_fr.ts index c9de356d9d7..45ac06630aa 100644 --- a/companion/src/translations/companion_fr.ts +++ b/companion/src/translations/companion_fr.ts @@ -7592,42 +7592,42 @@ Do you wish to continue? Charger les paramètres %1 et les paramètres de Simulation depuis un fichier précédemment exporté. - + Tabbed Windows Fenêtres à onglets - + Use tabs to arrange open windows. Utilisez les onglets pour organiser les fenêtres ouvertes. - + Tile Windows Titre de la fenêtre - + Arrange open windows across all the available space. Disposez les fenêtres ouvertes sur tout l'espace disponible. - + Cascade Windows Fenêtres en cascade - + Arrange all open windows in a stack. Organisez toutes les fenêtres ouvertes dans une pile. - + Close All Windows Fermer toutes les fenêtres - + Closes all open files (prompts to save if necessary. Fermer tous les fichiers ouverts (proposer de sauvegarder si nécessaire). diff --git a/companion/src/translations/companion_he.ts b/companion/src/translations/companion_he.ts index 9a34324f3f4..98272374b3c 100644 --- a/companion/src/translations/companion_he.ts +++ b/companion/src/translations/companion_he.ts @@ -7320,42 +7320,42 @@ Do you wish to continue? - + Tabbed Windows - + Use tabs to arrange open windows. - + Tile Windows - + Arrange open windows across all the available space. - + Cascade Windows - + Arrange all open windows in a stack. - + Close All Windows - + Closes all open files (prompts to save if necessary. diff --git a/companion/src/translations/companion_it.ts b/companion/src/translations/companion_it.ts index 3ddc8d01dd6..2fddbb90441 100644 --- a/companion/src/translations/companion_it.ts +++ b/companion/src/translations/companion_it.ts @@ -7362,42 +7362,42 @@ Do you wish to continue? - + Tabbed Windows - + Use tabs to arrange open windows. - + Tile Windows - + Arrange open windows across all the available space. - + Cascade Windows - + Arrange all open windows in a stack. - + Close All Windows - + Closes all open files (prompts to save if necessary. diff --git a/companion/src/translations/companion_ja.ts b/companion/src/translations/companion_ja.ts index 99837591174..762e420590e 100644 --- a/companion/src/translations/companion_ja.ts +++ b/companion/src/translations/companion_ja.ts @@ -7439,7 +7439,7 @@ The columns for altitude "GAlt" and for speed "GSpd" are opt <p>以前の設定はこちらにバックアップされました:<br> %1 </p> - + Tabbed Windows タブ付きウィンドウ @@ -7584,12 +7584,12 @@ The columns for altitude "GAlt" and for speed "GSpd" are opt ウィンドウのタイトル - + Cascade Windows ウィンドウを重ねる - + Close All Windows すべてのウィンドウを閉じる @@ -7703,22 +7703,22 @@ The columns for altitude "GAlt" and for speed "GSpd" are opt 現在の送信機プロファイルを削除... - + Use tabs to arrange open windows. タブを使用し、開いているウィンドウを並べます。 - + Arrange open windows across all the available space. 開いているウィンドウを空いているスペース全体に配置します。 - + Arrange all open windows in a stack. 開いているウィンドウをスタックに並べます。 - + Closes all open files (prompts to save if necessary. 開いているファイルをすべて閉じます (必要に応じ保存を求められます)。 diff --git a/companion/src/translations/companion_nl.ts b/companion/src/translations/companion_nl.ts index b609192ab8c..820b96c78aa 100644 --- a/companion/src/translations/companion_nl.ts +++ b/companion/src/translations/companion_nl.ts @@ -7305,42 +7305,42 @@ Do you wish to continue? - + Tabbed Windows - + Use tabs to arrange open windows. - + Tile Windows - + Arrange open windows across all the available space. - + Cascade Windows - + Arrange all open windows in a stack. - + Close All Windows - + Closes all open files (prompts to save if necessary. diff --git a/companion/src/translations/companion_pl.ts b/companion/src/translations/companion_pl.ts index 765cc1a59a8..a8d851b0783 100644 --- a/companion/src/translations/companion_pl.ts +++ b/companion/src/translations/companion_pl.ts @@ -7255,42 +7255,42 @@ Do you wish to continue? Skasuj Aktualny Profil Radia... - + Tabbed Windows Zakładkowane okna - + Use tabs to arrange open windows. Użyj zakładek do ustawienia otwartych okien. - + Tile Windows Tytuł Okien - + Arrange open windows across all the available space. Ustaw otwarte okna na całej dostępnej przestrzeni. - + Cascade Windows Okna kaskadowo - + Arrange all open windows in a stack. Ustaw wszytkie otwarte okna na stosie. - + Close All Windows Zamknij wszytkie okna - + Closes all open files (prompts to save if necessary. Zamknij wszystkie otwarte pliki (zapytaj by zapisać jeśli trzeba). diff --git a/companion/src/translations/companion_pt.ts b/companion/src/translations/companion_pt.ts index 53a64a0a667..f8088c10f46 100644 --- a/companion/src/translations/companion_pt.ts +++ b/companion/src/translations/companion_pt.ts @@ -7305,42 +7305,42 @@ Do you wish to continue? - + Tabbed Windows - + Use tabs to arrange open windows. - + Tile Windows - + Arrange open windows across all the available space. - + Cascade Windows - + Arrange all open windows in a stack. - + Close All Windows - + Closes all open files (prompts to save if necessary. diff --git a/companion/src/translations/companion_ru.ts b/companion/src/translations/companion_ru.ts index 957865d6823..c67ea5cab41 100644 --- a/companion/src/translations/companion_ru.ts +++ b/companion/src/translations/companion_ru.ts @@ -7372,42 +7372,42 @@ Do you wish to continue? Чтение ранее экспортированных настроек %1 и симулятора из файла. - + Tabbed Windows В виде закладок - + Use tabs to arrange open windows. Использовать закладки для переключения между окнами. - + Tile Windows По горизонтали - + Arrange open windows across all the available space. Выравнивание открытых окон по горизонтали. - + Cascade Windows Каскадом - + Arrange all open windows in a stack. Выравнивание открытых окон каскадом. - + Close All Windows Закрыть все окна - + Closes all open files (prompts to save if necessary. Закрыть все окна (с запросом на сохранение изменений). diff --git a/companion/src/translations/companion_zh_CN.ts b/companion/src/translations/companion_zh_CN.ts index 15bd1e05ea7..163a262523e 100644 --- a/companion/src/translations/companion_zh_CN.ts +++ b/companion/src/translations/companion_zh_CN.ts @@ -7579,42 +7579,42 @@ Do you wish to continue? - + Tabbed Windows - + Use tabs to arrange open windows. - + Tile Windows - + Arrange open windows across all the available space. - + Cascade Windows - + Arrange all open windows in a stack. - + Close All Windows - + Closes all open files (prompts to save if necessary. diff --git a/companion/src/translations/companion_zh_TW.ts b/companion/src/translations/companion_zh_TW.ts index 69a0f978247..7379e5e0bd5 100644 --- a/companion/src/translations/companion_zh_TW.ts +++ b/companion/src/translations/companion_zh_TW.ts @@ -7579,42 +7579,42 @@ Do you wish to continue? - + Tabbed Windows - + Use tabs to arrange open windows. - + Tile Windows - + Arrange open windows across all the available space. - + Cascade Windows - + Arrange all open windows in a stack. - + Close All Windows - + Closes all open files (prompts to save if necessary. From e0d480d172f912673eb4e6f511cc5747caf388ef Mon Sep 17 00:00:00 2001 From: benjinne Date: Tue, 12 Aug 2025 07:34:03 -0700 Subject: [PATCH 32/54] zorro-blue fix bootloader not responding by removing empty per5ms in bootloader code --- radio/src/targets/common/arm/stm32/timers_driver.cpp | 2 -- radio/src/targets/modalai/board.cpp | 9 +++++++++ 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/radio/src/targets/common/arm/stm32/timers_driver.cpp b/radio/src/targets/common/arm/stm32/timers_driver.cpp index e8bdfebb484..b3138bb7d0f 100644 --- a/radio/src/targets/common/arm/stm32/timers_driver.cpp +++ b/radio/src/targets/common/arm/stm32/timers_driver.cpp @@ -28,8 +28,6 @@ static volatile uint32_t _ms_ticks; -__weak void per5ms() {} - static void _init_1ms_timer() { stm32_timer_enable_clock(MS_TIMER); diff --git a/radio/src/targets/modalai/board.cpp b/radio/src/targets/modalai/board.cpp index 82bd9114c34..a55e69961ed 100644 --- a/radio/src/targets/modalai/board.cpp +++ b/radio/src/targets/modalai/board.cpp @@ -87,6 +87,10 @@ void boardBLInit() // usbRegisterDFUMedia((void*)extflash_dfu_media); } +void boardBLEarlyInit() +{ +} + void boardInit() { @@ -239,3 +243,8 @@ void boardOff() // this function must not return! } + +#if !defined(BOOT) +void per5ms() {} +#endif + From 5741d48d13863ef4c422445b9688ea1c0c04bc3d Mon Sep 17 00:00:00 2001 From: benjinne Date: Tue, 12 Aug 2025 07:48:30 -0700 Subject: [PATCH 33/54] zorro-blue cleanup --- radio/src/targets/common/arm/stm32/stm32h7xx_hal_conf.h | 2 +- radio/src/targets/common/arm/stm32/system_init.c | 2 +- radio/src/targets/common/arm/stm32/usb_driver.cpp | 2 +- radio/src/targets/common/arm/stm32/usbd_conf.c | 2 +- radio/src/thirdparty/FreeRTOS | 2 +- radio/src/thirdparty/stb | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/radio/src/targets/common/arm/stm32/stm32h7xx_hal_conf.h b/radio/src/targets/common/arm/stm32/stm32h7xx_hal_conf.h index 01af4e73d6d..d2649803165 100644 --- a/radio/src/targets/common/arm/stm32/stm32h7xx_hal_conf.h +++ b/radio/src/targets/common/arm/stm32/stm32h7xx_hal_conf.h @@ -94,7 +94,7 @@ #define HAL_SPI_MODULE_ENABLED // #define HAL_SRAM_MODULE_ENABLED // #define HAL_SWPMI_MODULE_ENABLED -//#define HAL_TIM_MODULE_ENABLED +// #define HAL_TIM_MODULE_ENABLED // #define HAL_UART_MODULE_ENABLED // #define HAL_USART_MODULE_ENABLED // #define HAL_WWDG_MODULE_ENABLED diff --git a/radio/src/targets/common/arm/stm32/system_init.c b/radio/src/targets/common/arm/stm32/system_init.c index af622a7413e..a5e44ce5218 100644 --- a/radio/src/targets/common/arm/stm32/system_init.c +++ b/radio/src/targets/common/arm/stm32/system_init.c @@ -31,7 +31,7 @@ #endif #if (defined (USE_CACHE) && defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)) - #define REQUIRE_MPU_CONFIG +#define REQUIRE_MPU_CONFIG #endif #if defined(ITCM_BASE) /* H7RS */ || defined(D1_ITCMRAM_BASE) /* H7 */ diff --git a/radio/src/targets/common/arm/stm32/usb_driver.cpp b/radio/src/targets/common/arm/stm32/usb_driver.cpp index 05679b9e621..38d5c82719e 100644 --- a/radio/src/targets/common/arm/stm32/usb_driver.cpp +++ b/radio/src/targets/common/arm/stm32/usb_driver.cpp @@ -121,7 +121,7 @@ extern "C" void OTG_FS_IRQHandler() } #endif -void usbInit() +void usbInit() { #if defined(STM32H7) HAL_PWREx_EnableUSBVoltageDetector(); diff --git a/radio/src/targets/common/arm/stm32/usbd_conf.c b/radio/src/targets/common/arm/stm32/usbd_conf.c index 145b0dcfed2..d080555297f 100644 --- a/radio/src/targets/common/arm/stm32/usbd_conf.c +++ b/radio/src/targets/common/arm/stm32/usbd_conf.c @@ -45,7 +45,7 @@ /* USER CODE END PV */ PCD_HandleTypeDef hpcd_USB_OTG; -void Error_Handler(void) { } +void Error_Handler(void){} /* External functions --------------------------------------------------------*/ diff --git a/radio/src/thirdparty/FreeRTOS b/radio/src/thirdparty/FreeRTOS index a4b28e35103..dbf70559b27 160000 --- a/radio/src/thirdparty/FreeRTOS +++ b/radio/src/thirdparty/FreeRTOS @@ -1 +1 @@ -Subproject commit a4b28e35103d699edf074dfff4835921b481b301 +Subproject commit dbf70559b27d39c1fdb68dfb9a32140b6a6777a0 diff --git a/radio/src/thirdparty/stb b/radio/src/thirdparty/stb index f4a71b13373..5c205738c19 160000 --- a/radio/src/thirdparty/stb +++ b/radio/src/thirdparty/stb @@ -1 +1 @@ -Subproject commit f4a71b13373436a2866c5d68f8f80ac6f0bc1ffe +Subproject commit 5c205738c191bcb0abc65c4febfa9bd25ff35234 From c70e80bee05b09f7b2b7b12a4d8800495a8db5d8 Mon Sep 17 00:00:00 2001 From: benjinne Date: Fri, 22 Aug 2025 10:15:17 -0700 Subject: [PATCH 34/54] rever FPU_FLAGS order --- radio/src/targets/common/arm/stm32/h7/CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/radio/src/targets/common/arm/stm32/h7/CMakeLists.txt b/radio/src/targets/common/arm/stm32/h7/CMakeLists.txt index 4f8dff6fe30..407e57c93bd 100644 --- a/radio/src/targets/common/arm/stm32/h7/CMakeLists.txt +++ b/radio/src/targets/common/arm/stm32/h7/CMakeLists.txt @@ -1,6 +1,6 @@ set(CPU_FAMILY STM32) set(MCU cortex-m7) -set(FPU_FLAGS "-mfpu=fpv4-sp-d16 -mfloat-abi=hard") +set(FPU_FLAGS "-mfloat-abi=hard -mfpu=fpv4-sp-d16") # CMSIS library set(CMSIS_DIR ${THIRDPARTY_DIR}/CMSIS) From 3f6b66f4241f8f5dcf9896aa7f895b8a36efae20 Mon Sep 17 00:00:00 2001 From: benjinne Date: Fri, 22 Aug 2025 10:19:47 -0700 Subject: [PATCH 35/54] standardize system_clock.c not use clock hal library since it's run before system_init copies code to ram --- radio/src/targets/modalai/system_clock.c | 85 +++++++++--------------- 1 file changed, 33 insertions(+), 52 deletions(-) diff --git a/radio/src/targets/modalai/system_clock.c b/radio/src/targets/modalai/system_clock.c index 0639f099ae5..6234a31a435 100644 --- a/radio/src/targets/modalai/system_clock.c +++ b/radio/src/targets/modalai/system_clock.c @@ -19,13 +19,10 @@ * GNU General Public License for more details. */ -#include "stm32h7xx_hal.h" -#include "stm32h7xx_hal_rcc.h" -#include "stm32h7xx_hal_pwr.h" -#include "stm32h7xx_hal_pwr_ex.h" -#include "stm32h7xx_hal_flash_ex.h" -#include "stm32h7xx_ll_system.h" +#include "stm32h7xx_ll_pwr.h" #include "stm32h7xx_ll_rcc.h" +#include "stm32h7xx_ll_system.h" +#include "stm32h7xx_ll_bus.h" #define BOOTSTRAP __attribute__((section(".bootstrap"))) @@ -51,39 +48,37 @@ * @param None * @retval None */ -BOOTSTRAP void SystemClock_Config() +BOOTSTRAP void SystemClock_Config(void) { - RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - - /** Supply configuration update enable - */ - HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); - - /** Configure the main internal regulator output voltage - */ - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + /* Power Configuration */ + LL_PWR_ConfigSupply(LL_PWR_LDO_SUPPLY); + LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1); + while (LL_PWR_IsActiveFlag_VOS() == 0) { + } - while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} + /* Enable HSE oscillator */ + LL_RCC_HSE_Enable(); + while (LL_RCC_HSE_IsReady() != 1) { + } - /** Initializes the RCC Oscillators according to the specified parameters - * in the RCC_OscInitTypeDef structure. - */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSEState = RCC_HSE_ON; - RCC_OscInitStruct.LSIState = RCC_LSI_ON; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = 2; - RCC_OscInitStruct.PLL.PLLN = 100; - RCC_OscInitStruct.PLL.PLLP = 2; - RCC_OscInitStruct.PLL.PLLQ = 4; - RCC_OscInitStruct.PLL.PLLR = 2; - RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_3; - RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; - RCC_OscInitStruct.PLL.PLLFRACN = 0; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) - { - while(1) {}; + /* Set FLASH latency */ + LL_FLASH_SetLatency(LL_FLASH_LATENCY_5); + + /* Main PLL configuration and activation */ + LL_RCC_PLL_SetSource(LL_RCC_PLLSOURCE_HSE); + LL_RCC_PLL1P_Enable(); + LL_RCC_PLL1Q_Enable(); + LL_RCC_PLL1R_Enable(); + LL_RCC_PLL1FRACN_Disable(); + LL_RCC_PLL1_SetVCOInputRange(LL_RCC_PLLINPUTRANGE_8_16); + LL_RCC_PLL1_SetVCOOutputRange(LL_RCC_PLLVCORANGE_WIDE); + LL_RCC_PLL1_SetM(2); + LL_RCC_PLL1_SetN(100); + LL_RCC_PLL1_SetP(2); + LL_RCC_PLL1_SetQ(4); + LL_RCC_PLL1_SetR(2); + LL_RCC_PLL1_Enable(); + while (LL_RCC_PLL1_IsReady() != 1) { } /* Set Sys & AHB & APB1 & APB2 & APB4 prescaler */ @@ -114,6 +109,7 @@ BOOTSTRAP void SystemClock_Config() while (LL_RCC_PLL2_IsReady() != 1) { } + /* PLL3 configuration and activation */ LL_RCC_PLL3R_Enable(); LL_RCC_PLL3FRACN_Disable(); LL_RCC_PLL3_SetVCOInputRange(LL_RCC_PLLINPUTRANGE_4_8); @@ -127,26 +123,11 @@ BOOTSTRAP void SystemClock_Config() while (LL_RCC_PLL3_IsReady() != 1) { } - /** Enables the Clock Security System - */ - HAL_RCC_EnableCSS(); - - LL_RCC_PLL2_Enable(); - while (LL_RCC_PLL2_IsReady() != 1) { - } - - LL_RCC_PLL3_Enable(); - while (LL_RCC_PLL3_IsReady() != 1) { - } - + /* USB/ADC/SPI clock sources */ LL_RCC_HSI48_Enable(); while (LL_RCC_HSI48_IsReady() != 1) { } LL_RCC_SetUSBClockSource(LL_RCC_USB_CLKSOURCE_HSI48); - - // HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK_DIV8); - - // Only required if using Async ADC clock ??? LL_RCC_SetADCClockSource(LL_RCC_ADC_CLKSOURCE_CLKP); LL_RCC_SetSPIClockSource(LL_RCC_SPI45_CLKSOURCE_PCLK2); } From 9869ef688b03ce7a329743b32c0154efe910b316 Mon Sep 17 00:00:00 2001 From: benjinne Date: Fri, 22 Aug 2025 10:50:13 -0700 Subject: [PATCH 36/54] remove setting f_pfnVectors since it's not set upstream and SCB->VTOR is already set in system_init --- radio/src/targets/common/arm/stm32/h7/system_stm32h7xx.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/radio/src/targets/common/arm/stm32/h7/system_stm32h7xx.c b/radio/src/targets/common/arm/stm32/h7/system_stm32h7xx.c index 0504011dfec..bc618f01244 100644 --- a/radio/src/targets/common/arm/stm32/h7/system_stm32h7xx.c +++ b/radio/src/targets/common/arm/stm32/h7/system_stm32h7xx.c @@ -303,9 +303,6 @@ BOOTSTRAP void SystemInit (void) /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */ -#else - extern uint32_t g_pfnVectors ; - SCB->VTOR = (uint32_t) &g_pfnVectors ; /* Vector Table Relocation in Internal FLASH */ #endif /* USER_VECT_TAB_ADDRESS */ #endif /*DUAL_CORE && CORE_CM4*/ From a7dc6590c7293529527e4f90081e6ddd613e4770 Mon Sep 17 00:00:00 2001 From: benjinne Date: Fri, 22 Aug 2025 10:51:15 -0700 Subject: [PATCH 37/54] h753 add disck_cache and _dram_addr to better match other h7 boards --- .../generic_stm32/linker/stm32h753/extra_sections.ld | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/radio/src/boards/generic_stm32/linker/stm32h753/extra_sections.ld b/radio/src/boards/generic_stm32/linker/stm32h753/extra_sections.ld index 165ebac1719..47a7483f1ac 100644 --- a/radio/src/boards/generic_stm32/linker/stm32h753/extra_sections.ld +++ b/radio/src/boards/generic_stm32/linker/stm32h753/extra_sections.ld @@ -29,6 +29,13 @@ _stext_iram = LOADADDR(.iram); +/* Disk cache buffers */ +.disk_cache (NOLOAD) : +{ + . = ALIGN(4); + *(.disk_cache) +} > RAM_D1 + /* Extra DMA section */ .dram (NOLOAD) : { @@ -39,4 +46,6 @@ _stext_iram = LOADADDR(.iram); _e_dram = .; } > RAM_D2 +_dram_addr = ADDR(.dram); + PROVIDE(_heap_start = _e_dram); From b5d639b51ede6037bef84f9b05b6866c6be50063 Mon Sep 17 00:00:00 2001 From: benjinne Date: Fri, 22 Aug 2025 10:58:11 -0700 Subject: [PATCH 38/54] h753 make bootloader run from ITCMRAM to improve avoid flash conflict when updating firmwre --- .../generic_stm32/linker/stm32h753/bootloader/layout.ld | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/radio/src/boards/generic_stm32/linker/stm32h753/bootloader/layout.ld b/radio/src/boards/generic_stm32/linker/stm32h753/bootloader/layout.ld index e1c519ec395..967ba0ddf96 100644 --- a/radio/src/boards/generic_stm32/linker/stm32h753/bootloader/layout.ld +++ b/radio/src/boards/generic_stm32/linker/stm32h753/bootloader/layout.ld @@ -25,8 +25,8 @@ MEMORY } REGION_ALIAS("REGION_TEXT_STORAGE", FLASH); -REGION_ALIAS("REGION_TEXT", FLASH); +REGION_ALIAS("REGION_TEXT", ITCMRAM); /* Todo: setting this to ITCMRAM this should fix bootloader instruction cache?*/ REGION_ALIAS("REGION_ISR_VECT", DTCMRAM); REGION_ALIAS("REGION_DATA", DTCMRAM); REGION_ALIAS("REGION_BSS", RAM_D1); -REGION_ALIAS("REGION_RAM", RAM_D1); +REGION_ALIAS("REGION_RAM", RAM_D1); /* used for DMA, capable regions: D1,D2*/ From 1205ee14d17590d4f6905e2fff35ef376d2f645f Mon Sep 17 00:00:00 2001 From: benjinne Date: Fri, 22 Aug 2025 10:58:47 -0700 Subject: [PATCH 39/54] h753 make firmware run from RAM_D1 (doesn't fit in ITCMRAM) to improve avoid flash conflict when updating bootloader --- radio/src/boards/generic_stm32/linker/stm32h753/layout.ld | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/radio/src/boards/generic_stm32/linker/stm32h753/layout.ld b/radio/src/boards/generic_stm32/linker/stm32h753/layout.ld index bef4dff7810..ed2618cd3e2 100644 --- a/radio/src/boards/generic_stm32/linker/stm32h753/layout.ld +++ b/radio/src/boards/generic_stm32/linker/stm32h753/layout.ld @@ -26,8 +26,8 @@ MEMORY REGION_ALIAS("REGION_BOOTLOADER", FLASH); REGION_ALIAS("REGION_TEXT_STORAGE", FLASH); -REGION_ALIAS("REGION_TEXT", FLASH); +REGION_ALIAS("REGION_TEXT", RAM_D1); REGION_ALIAS("REGION_ISR_VECT", DTCMRAM); REGION_ALIAS("REGION_DATA", DTCMRAM); REGION_ALIAS("REGION_BSS", RAM_D1); -REGION_ALIAS("REGION_RAM", RAM_D1); +REGION_ALIAS("REGION_RAM", RAM_D1); /* used for DMA, capable regions: D1,D2*/ From 3c4e0d4369b09a107a68081c84fc8ede0b79b884 Mon Sep 17 00:00:00 2001 From: benjinne Date: Fri, 22 Aug 2025 11:01:47 -0700 Subject: [PATCH 40/54] system_init add _dram_addr and mpu protection for dram --- radio/src/targets/common/arm/stm32/system_init.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/radio/src/targets/common/arm/stm32/system_init.c b/radio/src/targets/common/arm/stm32/system_init.c index a5e44ce5218..99c7d489d90 100644 --- a/radio/src/targets/common/arm/stm32/system_init.c +++ b/radio/src/targets/common/arm/stm32/system_init.c @@ -201,8 +201,8 @@ BOOTSTRAP void CPU_CACHE_Enable() #if defined(BOOT) && defined(REQUIRE_MPU_CONFIG) // Linker script symbols -#ifndef RADIO_MODAL // no extram on modalAI h7 extern uint32_t _dram_addr; +#ifndef RADIO_MODAL // no extram on modalAI h7 extern uint32_t EXTRAM_START; extern uint32_t EXTRAM_SIZE; extern uint32_t NORFLASH_START; @@ -268,7 +268,10 @@ void MPU_Config() MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE; MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE; HAL_MPU_ConfigRegion(&MPU_InitStruct); +#endif // RADIO_MODAL +// todo does disabling cache on dedicated DMA buffers help resolve firmware flashing issue? + /* Region 4: dedicated DMA buffers (cache disabled) */ MPU_InitStruct.Enable = MPU_REGION_ENABLE; MPU_InitStruct.Number = MPU_REGION_NUMBER4; @@ -282,8 +285,6 @@ void MPU_Config() MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE; MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE; HAL_MPU_ConfigRegion(&MPU_InitStruct); - #endif - HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT); From 8e718a618b256c67027be2793f46939a638ae0a6 Mon Sep 17 00:00:00 2001 From: benjinne Date: Fri, 22 Aug 2025 11:04:45 -0700 Subject: [PATCH 41/54] modalai cpp remove setting clock and begin with enable_irq --- radio/src/targets/modalai/board.cpp | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/radio/src/targets/modalai/board.cpp b/radio/src/targets/modalai/board.cpp index a55e69961ed..fea790992c2 100644 --- a/radio/src/targets/modalai/board.cpp +++ b/radio/src/targets/modalai/board.cpp @@ -94,21 +94,20 @@ void boardBLEarlyInit() void boardInit() { + +__enable_irq(); + #if defined(SEMIHOSTING) initialise_monitor_handles(); #elif defined(DEBUG_SEGGER_RTT) // SEGGER_RTT_Init(); // SEGGER_RTT_ConfigUpBuffer(0, NULL, NULL, 0, SEGGER_RTT_MODE_NO_BLOCK_SKIP); #endif - LL_APB4_GRP1_EnableClock(LL_APB4_GRP1_PERIPH_SYSCFG); - - // SCB_EnableDCache(); #if defined(POWER_I2C) voxl_pm_init(); #endif - #if defined(USB_CHARGE_LED) && !defined(DEBUG) usbInit(); // prime debounce state... @@ -148,7 +147,6 @@ void boardInit() #endif delaysInit(); - __enable_irq(); if (!adcInit(&_adc_driver)) TRACE("adcInit failed"); From f86edfc877e8d25d9c08c74d7f30331bc6e0ac61 Mon Sep 17 00:00:00 2001 From: benjinne Date: Fri, 22 Aug 2025 13:11:48 -0700 Subject: [PATCH 42/54] remove Jolly Mon codename since it's outdated --- CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 386f40eaad9..4bf1e6705cf 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -5,7 +5,7 @@ project(EdgeTX) set(VERSION_MAJOR "3") set(VERSION_MINOR "0") set(VERSION_REVISION "0") -set(CODENAME "Jolly Mon") +set(CODENAME "dev") string(TIMESTAMP BUILD_YEAR "%Y") if(MINGW OR WIN32) From 0e172ae86f0b137a8253c998de38b8229899bb61 Mon Sep 17 00:00:00 2001 From: benjinne Date: Fri, 22 Aug 2025 13:12:16 -0700 Subject: [PATCH 43/54] modalai remove setting GPIOH 2 --- radio/src/targets/modalai/board.cpp | 2 -- 1 file changed, 2 deletions(-) diff --git a/radio/src/targets/modalai/board.cpp b/radio/src/targets/modalai/board.cpp index fea790992c2..e7175ac56fd 100644 --- a/radio/src/targets/modalai/board.cpp +++ b/radio/src/targets/modalai/board.cpp @@ -184,8 +184,6 @@ __enable_irq(); backlightInit(); - gpio_set(GPIO_PIN(GPIOH, 2)); - #if defined(GUI) lcdSetContrast(true); #endif From cc6f564cbbaac072b57295a8fcb8f6e93f323093 Mon Sep 17 00:00:00 2001 From: benjinne Date: Fri, 22 Aug 2025 13:12:47 -0700 Subject: [PATCH 44/54] hal_keys.py reset bracket to main --- radio/util/hw_defs/hal_keys.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/radio/util/hw_defs/hal_keys.py b/radio/util/hw_defs/hal_keys.py index e7439078dba..8a00b0a311a 100644 --- a/radio/util/hw_defs/hal_keys.py +++ b/radio/util/hw_defs/hal_keys.py @@ -120,7 +120,7 @@ "RIGHT": { "label": "Right/MDL" } } }, - { + { "targets": {"commando8"}, "keys": { "EXIT": { "label": "BCK" }, From 32786067f224a5501556f5227f7d2ddfc60e5047 Mon Sep 17 00:00:00 2001 From: benjinne Date: Fri, 22 Aug 2025 16:18:20 -0700 Subject: [PATCH 45/54] modalai target move to switch definitions instead of press --- radio/src/targets/modalai/CMakeLists.txt | 2 +- radio/src/targets/modalai/board.h | 1 + radio/src/targets/modalai/hal.h | 6 ++++-- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/radio/src/targets/modalai/CMakeLists.txt b/radio/src/targets/modalai/CMakeLists.txt index 57ba07d0630..51a12329063 100644 --- a/radio/src/targets/modalai/CMakeLists.txt +++ b/radio/src/targets/modalai/CMakeLists.txt @@ -22,7 +22,7 @@ add_definitions(-DMANUFACTURER_MODALAI) add_definitions(-DTHREADSAFE_MALLOC) if(PCB STREQUAL M207) - set(PWR_BUTTON "PRESS" CACHE STRING "Pwr button type (PRESS/SWITCH)") + set(PWR_BUTTON "SWITCH" CACHE STRING "Pwr button type (PRESS/SWITCH)") #set(HAPTIC YES) set(GUI_DIR 128x64) set(SDCARD YES) diff --git a/radio/src/targets/modalai/board.h b/radio/src/targets/modalai/board.h index 230f90909db..93d4396ed38 100644 --- a/radio/src/targets/modalai/board.h +++ b/radio/src/targets/modalai/board.h @@ -104,6 +104,7 @@ extern "C" { #endif // Power driver +#define SOFT_PWR_CTRL void pwrInit(); uint32_t pwrCheck(); diff --git a/radio/src/targets/modalai/hal.h b/radio/src/targets/modalai/hal.h index 6eda2ec860e..b7ab549936f 100644 --- a/radio/src/targets/modalai/hal.h +++ b/radio/src/targets/modalai/hal.h @@ -166,8 +166,10 @@ // PWR and LED driver // #warning unsure what these do, TODO: Remove these buttons completely -#define PWR_SWITCH_GPIO GPIO_PIN(GPIOA, 5) // PC.06 -#define PWR_ON_GPIO GPIO_PIN(GPIOA, 6) // PC.07 +// don't define PWR_SWITCH_GPIO to not check on boot +// #define PWR_SWITCH_GPIO GPIO_PIN(GPIOA, 5) // PA.06 +// don't need to set PWR_ON_GPIO since there's no hardware latch connected like on most button controllers +// #define PWR_ON_GPIO GPIO_PIN(GPIOA, 6) // PA.07 #define USE_LEDS #ifdef USE_LEDS From de3b944f902dbb59a9a90f5f205358cd782c9baa Mon Sep 17 00:00:00 2001 From: benjinne Date: Fri, 22 Aug 2025 16:19:04 -0700 Subject: [PATCH 46/54] move mixerTask back to menusTask and add WDG_RESET --- radio/src/edgetx.cpp | 1 - radio/src/tasks.cpp | 3 +++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/radio/src/edgetx.cpp b/radio/src/edgetx.cpp index e7b4507b08a..3ed0f83febc 100644 --- a/radio/src/edgetx.cpp +++ b/radio/src/edgetx.cpp @@ -1556,7 +1556,6 @@ void edgeTxInit() #endif #endif - mixerTaskInit(); #if defined(GUI) if (calibration_needed) { diff --git a/radio/src/tasks.cpp b/radio/src/tasks.cpp index a695a2bd2ad..1baf7efaafb 100644 --- a/radio/src/tasks.cpp +++ b/radio/src/tasks.cpp @@ -61,6 +61,9 @@ static void menusTask() edgeTxInit(); + //WDG_RESET needed because MODAL_ZORRO watchdog triggers before mixer resets it + WDG_RESET(); + mixerTaskInit(); #if defined(PWR_BUTTON_PRESS) while (task_running()) { From 0366cdb66d1f1f7f88e68e89bfb65aa08398b908 Mon Sep 17 00:00:00 2001 From: benjinne Date: Fri, 22 Aug 2025 17:10:24 -0700 Subject: [PATCH 47/54] modalai align bootloader with sector size to ensure bootloader firmware updates are successful every time --- .../boards/generic_stm32/linker/stm32h753/bootloader/layout.ld | 2 +- radio/src/boards/generic_stm32/linker/stm32h753/layout.ld | 2 +- radio/src/targets/modalai/board.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/radio/src/boards/generic_stm32/linker/stm32h753/bootloader/layout.ld b/radio/src/boards/generic_stm32/linker/stm32h753/bootloader/layout.ld index 967ba0ddf96..10e14b11da3 100644 --- a/radio/src/boards/generic_stm32/linker/stm32h753/bootloader/layout.ld +++ b/radio/src/boards/generic_stm32/linker/stm32h753/bootloader/layout.ld @@ -5,7 +5,7 @@ HEAP_ADDRESS = ORIGIN(RAM_D2) + LENGTH(RAM_D2) - 16; STACK_ADDRESS = ORIGIN(DTCMRAM) + LENGTH(DTCMRAM) - 16; /* end of RAM */ /* Maximum bootloader code size */ -BOOTLOADER_SIZE = 0x10000; +BOOTLOADER_SIZE = 0x20000; /* Align to 128KB sector boundary on STM32H753 */ /* Required amount of stack for interrupt stack (Main stack) */ MAIN_STACK_SIZE = 8192; diff --git a/radio/src/boards/generic_stm32/linker/stm32h753/layout.ld b/radio/src/boards/generic_stm32/linker/stm32h753/layout.ld index ed2618cd3e2..32df3fc2199 100644 --- a/radio/src/boards/generic_stm32/linker/stm32h753/layout.ld +++ b/radio/src/boards/generic_stm32/linker/stm32h753/layout.ld @@ -5,7 +5,7 @@ HEAP_ADDRESS = ORIGIN(RAM_D2) + LENGTH(RAM_D2) - 16; STACK_ADDRESS = ORIGIN(DTCMRAM) + LENGTH(DTCMRAM); /* end of RAM */ /* Maximum bootloader code size */ -BOOTLOADER_SIZE = 0x10000; +BOOTLOADER_SIZE = 0x20000; /* Align to 128KB sector boundary on STM32H753 */ /* Required amount of stack for interrupt stack (Main stack) */ MAIN_STACK_SIZE = 8192; diff --git a/radio/src/targets/modalai/board.h b/radio/src/targets/modalai/board.h index 93d4396ed38..0d90c8400e4 100644 --- a/radio/src/targets/modalai/board.h +++ b/radio/src/targets/modalai/board.h @@ -38,7 +38,7 @@ void rotaryEncoderCheck(); #define FLASHSIZE 0x200000 #define FLASH_PAGESIZE 256 -#define BOOTLOADER_SIZE 0x10000 +#define BOOTLOADER_SIZE 0x20000 #define FIRMWARE_ADDRESS 0x08000000 #define FIRMWARE_LEN(fsize) (fsize - BOOTLOADER_SIZE) #define FIRMWARE_MAX_LEN (FLASHSIZE - BOOTLOADER_SIZE) From de7918064c1066ae6c34a8aaa4ffe1b621055239 Mon Sep 17 00:00:00 2001 From: benjinne Date: Mon, 25 Aug 2025 11:31:44 -0700 Subject: [PATCH 48/54] ModalAI reduce slow settings save time from 5s to 1s. fixed settings not getting save when restarting controller too quickly --- radio/src/storage/storage.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/radio/src/storage/storage.h b/radio/src/storage/storage.h index e7c4d33b7d3..40a8c9f9c6b 100644 --- a/radio/src/storage/storage.h +++ b/radio/src/storage/storage.h @@ -23,7 +23,7 @@ #include "edgetx_types.h" -#if defined(SIMU) +#if defined(SIMU) || defined(PCBMODALAI) #define WRITE_DELAY_10MS 100 #elif defined(RTC_BACKUP_RAM) #define WRITE_DELAY_10MS 1500 /* 15s */ From c0ee87cb570cb7eb3123e1c1762e7c59bf011795 Mon Sep 17 00:00:00 2001 From: benjinne Date: Mon, 25 Aug 2025 13:54:56 -0700 Subject: [PATCH 49/54] modalai fix model joystick settings --- radio/src/CMakeLists.txt | 2 +- radio/src/gui/128x64/model_setup.cpp | 5 ++--- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/radio/src/CMakeLists.txt b/radio/src/CMakeLists.txt index 82396f55ddf..dadfe06091f 100644 --- a/radio/src/CMakeLists.txt +++ b/radio/src/CMakeLists.txt @@ -57,7 +57,7 @@ option(BOOTLOADER "Include Bootloader" ON) option(FWDRIVE "Attach also firmware drive with USB" OFF) option(DISABLE_MCUCHECK "Disable MCU check at start" OFF) option(LUA_MIXER "Enable LUA mixer/model scripts support" ON) -if((PCB STREQUAL X9D+ AND PCBREV STREQUAL 2019) OR PCB STREQUAL M207) +if(PCB STREQUAL X9D+ AND PCBREV STREQUAL 2019) option(USBJ_EX "Enable USB Joystick Extension" OFF) else() option(USBJ_EX "Enable USB Joystick Extension" ON) diff --git a/radio/src/gui/128x64/model_setup.cpp b/radio/src/gui/128x64/model_setup.cpp index 0edce2bbf3f..0a1824baef8 100644 --- a/radio/src/gui/128x64/model_setup.cpp +++ b/radio/src/gui/128x64/model_setup.cpp @@ -425,7 +425,7 @@ void onModelAntennaSwitchConfirm(const char * result) #define TRAINER_BLUETOOTH_ROW (g_model.trainerData.mode == TRAINER_MODE_MASTER_BLUETOOTH ? TRAINER_BLUETOOTH_M_ROW : (g_model.trainerData.mode == TRAINER_MODE_SLAVE_BLUETOOTH ? TRAINER_BLUETOOTH_S_ROW : HIDDEN_ROW)) #define TRAINER_PPM_PARAMS_ROW (g_model.trainerData.mode == TRAINER_MODE_SLAVE ? (uint8_t)2 : HIDDEN_ROW) #define TRAINER_ROWS LABEL(Trainer), 0, IF_BT_TRAINER_ON(TRAINER_BLUETOOTH_ROW), TRAINER_CHANNELS_ROW, TRAINER_PPM_PARAMS_ROW -#elif defined(PCBX7) || defined(PCBX9LITE) +#elif defined(PCBX7) || defined(PCBX9LITE) || defined(PCBMODALAI) #if defined(BLUETOOTH) #define TRAINER_BLUETOOTH_ROW (g_model.trainerData.mode == TRAINER_MODE_MASTER_BLUETOOTH ? TRAINER_BLUETOOTH_M_ROW : (g_model.trainerData.mode == TRAINER_MODE_SLAVE_BLUETOOTH ? TRAINER_BLUETOOTH_S_ROW : HIDDEN_ROW)), #else @@ -825,8 +825,7 @@ void menuModelSetup(event_t event) EXTRA_MODULE_ROWS - TRAINER_ROWS - #warning removed ',' since none of these are currently used + TRAINER_ROWS, // View options 0, From d64a15444a6292b7a05e3ffeda8c7ae5f99fd680 Mon Sep 17 00:00:00 2001 From: benjinne Date: Tue, 2 Sep 2025 10:51:30 -0700 Subject: [PATCH 50/54] RADIO_MODAL disable MPU for dram region since it breaks advanced usb_joystick hid memcpy --- radio/src/targets/common/arm/stm32/system_init.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/radio/src/targets/common/arm/stm32/system_init.c b/radio/src/targets/common/arm/stm32/system_init.c index 99c7d489d90..4cc5d08b214 100644 --- a/radio/src/targets/common/arm/stm32/system_init.c +++ b/radio/src/targets/common/arm/stm32/system_init.c @@ -268,11 +268,9 @@ void MPU_Config() MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE; MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE; HAL_MPU_ConfigRegion(&MPU_InitStruct); -#endif // RADIO_MODAL - -// todo does disabling cache on dedicated DMA buffers help resolve firmware flashing issue? /* Region 4: dedicated DMA buffers (cache disabled) */ + // RADIO_MODAL, breaks advanced usb_joystick with unaligned memcpy functions MPU_InitStruct.Enable = MPU_REGION_ENABLE; MPU_InitStruct.Number = MPU_REGION_NUMBER4; MPU_InitStruct.BaseAddress = (uint32_t)&_dram_addr; @@ -285,7 +283,8 @@ void MPU_Config() MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE; MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE; HAL_MPU_ConfigRegion(&MPU_InitStruct); - + #endif // RADIO_MODAL + HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT); /* Enable bus fault exception */ From 8e7d4028d2b7ec8a48b1868a8bcc83afb3c6ca85 Mon Sep 17 00:00:00 2001 From: benjinne Date: Tue, 2 Sep 2025 10:51:56 -0700 Subject: [PATCH 51/54] undo abnormal_reboot section removal --- radio/src/targets/common/arm/stm32/abnormal_reboot.cpp | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/radio/src/targets/common/arm/stm32/abnormal_reboot.cpp b/radio/src/targets/common/arm/stm32/abnormal_reboot.cpp index 54dc2bf8244..ad1cbd0ddae 100644 --- a/radio/src/targets/common/arm/stm32/abnormal_reboot.cpp +++ b/radio/src/targets/common/arm/stm32/abnormal_reboot.cpp @@ -23,8 +23,7 @@ #include "stm32_hal_ll.h" -// #define __REBOOT_DATA __attribute__((section(".rebootdata"), aligned(4))) -#define __REBOOT_DATA __attribute__((aligned(4))) +#define __REBOOT_DATA __attribute__((section(".rebootdata"), aligned(4))) // This variable is define at a fixed memory location // and is used in bootloader and firmware to pass From d239e86802d14913d90b49d18e0146f0197f80bf Mon Sep 17 00:00:00 2001 From: benjinne Date: Tue, 16 Sep 2025 11:55:27 -0700 Subject: [PATCH 52/54] Move heap to RAM_D3 to fix joystick hid descriptor memcpy unaligned access issue due to RAM_D2 being NOT_CACHEABLE due to MPU. Also enable MPU on RAM_D2 to fix analog sticks/pots calibration issues. --- .../generic_stm32/linker/stm32h753/bootloader/layout.ld | 4 ++-- .../boards/generic_stm32/linker/stm32h753/extra_sections.ld | 2 +- radio/src/boards/generic_stm32/linker/stm32h753/layout.ld | 6 +++--- radio/src/targets/common/arm/stm32/system_init.c | 5 +++-- 4 files changed, 9 insertions(+), 8 deletions(-) diff --git a/radio/src/boards/generic_stm32/linker/stm32h753/bootloader/layout.ld b/radio/src/boards/generic_stm32/linker/stm32h753/bootloader/layout.ld index 10e14b11da3..0bbcaa05c69 100644 --- a/radio/src/boards/generic_stm32/linker/stm32h753/bootloader/layout.ld +++ b/radio/src/boards/generic_stm32/linker/stm32h753/bootloader/layout.ld @@ -1,5 +1,5 @@ /* Highest heap address */ -HEAP_ADDRESS = ORIGIN(RAM_D2) + LENGTH(RAM_D2) - 16; +HEAP_ADDRESS = ORIGIN(RAM_D3) + LENGTH(RAM_D3) - 16; /* Highest address of the user mode stack */ STACK_ADDRESS = ORIGIN(DTCMRAM) + LENGTH(DTCMRAM) - 16; /* end of RAM */ @@ -29,4 +29,4 @@ REGION_ALIAS("REGION_TEXT", ITCMRAM); /* Todo: setting this to ITCMRAM t REGION_ALIAS("REGION_ISR_VECT", DTCMRAM); REGION_ALIAS("REGION_DATA", DTCMRAM); REGION_ALIAS("REGION_BSS", RAM_D1); -REGION_ALIAS("REGION_RAM", RAM_D1); /* used for DMA, capable regions: D1,D2*/ +REGION_ALIAS("REGION_RAM", RAM_D1); diff --git a/radio/src/boards/generic_stm32/linker/stm32h753/extra_sections.ld b/radio/src/boards/generic_stm32/linker/stm32h753/extra_sections.ld index 47a7483f1ac..bbcd308bfb0 100644 --- a/radio/src/boards/generic_stm32/linker/stm32h753/extra_sections.ld +++ b/radio/src/boards/generic_stm32/linker/stm32h753/extra_sections.ld @@ -48,4 +48,4 @@ _stext_iram = LOADADDR(.iram); _dram_addr = ADDR(.dram); -PROVIDE(_heap_start = _e_dram); +PROVIDE(_heap_start = ORIGIN(RAM_D3)); \ No newline at end of file diff --git a/radio/src/boards/generic_stm32/linker/stm32h753/layout.ld b/radio/src/boards/generic_stm32/linker/stm32h753/layout.ld index 32df3fc2199..cc2f7c8c41d 100644 --- a/radio/src/boards/generic_stm32/linker/stm32h753/layout.ld +++ b/radio/src/boards/generic_stm32/linker/stm32h753/layout.ld @@ -1,5 +1,5 @@ /* Highest heap address */ -HEAP_ADDRESS = ORIGIN(RAM_D2) + LENGTH(RAM_D2) - 16; +HEAP_ADDRESS = ORIGIN(RAM_D3) + LENGTH(RAM_D3) - 16; /* Highest address of the user mode stack */ STACK_ADDRESS = ORIGIN(DTCMRAM) + LENGTH(DTCMRAM); /* end of RAM */ @@ -11,7 +11,7 @@ BOOTLOADER_SIZE = 0x20000; /* Align to 128KB sector boundary on STM32H753 */ MAIN_STACK_SIZE = 8192; /* Generate a link error if heap and stack don't fit into RAM */ -MIN_HEAP_SIZE = 128K; /* required amount of heap */ +MIN_HEAP_SIZE = 0; /* required amount of heap */ /* Specify the memory areas */ MEMORY @@ -30,4 +30,4 @@ REGION_ALIAS("REGION_TEXT", RAM_D1); REGION_ALIAS("REGION_ISR_VECT", DTCMRAM); REGION_ALIAS("REGION_DATA", DTCMRAM); REGION_ALIAS("REGION_BSS", RAM_D1); -REGION_ALIAS("REGION_RAM", RAM_D1); /* used for DMA, capable regions: D1,D2*/ +REGION_ALIAS("REGION_RAM", RAM_D1); \ No newline at end of file diff --git a/radio/src/targets/common/arm/stm32/system_init.c b/radio/src/targets/common/arm/stm32/system_init.c index 4cc5d08b214..43f3995ece6 100644 --- a/radio/src/targets/common/arm/stm32/system_init.c +++ b/radio/src/targets/common/arm/stm32/system_init.c @@ -269,12 +269,14 @@ void MPU_Config() MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE; HAL_MPU_ConfigRegion(&MPU_InitStruct); + #endif // RADIO_MODAL + /* Region 4: dedicated DMA buffers (cache disabled) */ // RADIO_MODAL, breaks advanced usb_joystick with unaligned memcpy functions MPU_InitStruct.Enable = MPU_REGION_ENABLE; MPU_InitStruct.Number = MPU_REGION_NUMBER4; MPU_InitStruct.BaseAddress = (uint32_t)&_dram_addr; - MPU_InitStruct.Size = MPU_REGION_SIZE_64KB; // FIXME + MPU_InitStruct.Size = MPU_REGION_SIZE_512KB; // FIXME MPU_InitStruct.SubRegionDisable = 0x0; MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1; MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS; @@ -283,7 +285,6 @@ void MPU_Config() MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE; MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE; HAL_MPU_ConfigRegion(&MPU_InitStruct); - #endif // RADIO_MODAL HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT); From a22cc662576d151adbf970d34c2cd9a4268f4283 Mon Sep 17 00:00:00 2001 From: benjinne Date: Thu, 16 Oct 2025 12:54:46 -0700 Subject: [PATCH 53/54] modalai hide values/bars and logical switches --- radio/src/dataconstants.h | 6 ++++++ radio/src/gui/128x64/view_main.cpp | 5 +++++ 2 files changed, 11 insertions(+) diff --git a/radio/src/dataconstants.h b/radio/src/dataconstants.h index 79a74072335..de4eca04063 100644 --- a/radio/src/dataconstants.h +++ b/radio/src/dataconstants.h @@ -159,6 +159,12 @@ enum MainViews { VIEW_SWITCHES, VIEW_COUNT }; +#elif defined(PCBMODALAI) +enum MainViews { + VIEW_INPUTS, + VIEW_CHAN_MONITOR, + VIEW_COUNT +}; #else enum MainViews { VIEW_OUTPUTS_VALUES, diff --git a/radio/src/gui/128x64/view_main.cpp b/radio/src/gui/128x64/view_main.cpp index d3d24d043e3..424cc0cf91f 100644 --- a/radio/src/gui/128x64/view_main.cpp +++ b/radio/src/gui/128x64/view_main.cpp @@ -456,6 +456,7 @@ void menuMainView(event_t event) menuChannelsViewCommon(event); break; + #ifndef PCBMODALAI case VIEW_OUTPUTS_VALUES: case VIEW_OUTPUTS_BARS: // scroll bar @@ -510,8 +511,12 @@ void menuMainView(event_t event) case VIEW_TIMER2: drawTimerWithMode(87, 5 * FH, 1, RIGHT | DBLSIZE); break; + #endif case VIEW_INPUTS: + #ifdef PCBMODALAI + view = VIEW_INPUTS; // hide logical switches + #endif if (view == VIEW_INPUTS) { // Sticks + Pots doMainScreenGraphics(); From 5f5ab68c256f7ebf02b15e4c36f747519e3f8809 Mon Sep 17 00:00:00 2001 From: benjinne Date: Thu, 16 Oct 2025 13:05:01 -0700 Subject: [PATCH 54/54] modalai always boot to telemetry screen --- radio/src/edgetx.cpp | 4 ++++ radio/src/targets/modalai/CMakeLists.txt | 3 +++ 2 files changed, 7 insertions(+) diff --git a/radio/src/edgetx.cpp b/radio/src/edgetx.cpp index 3ed0f83febc..1ccb9184c60 100644 --- a/radio/src/edgetx.cpp +++ b/radio/src/edgetx.cpp @@ -1389,7 +1389,11 @@ void edgeTxInit() ViewMain::instance(); #elif defined(GUI) // TODO add a function for this (duplicated) +#if defined(PCBMODALAI) && defined(DEFAULT_VIEW_TELEMETRY) + menuHandlers[0] = menuViewTelemetry; +#else menuHandlers[0] = menuMainView; +#endif menuHandlers[1] = menuModelSelect; #endif diff --git a/radio/src/targets/modalai/CMakeLists.txt b/radio/src/targets/modalai/CMakeLists.txt index 51a12329063..07484a13417 100644 --- a/radio/src/targets/modalai/CMakeLists.txt +++ b/radio/src/targets/modalai/CMakeLists.txt @@ -21,6 +21,9 @@ add_definitions(-DMANUFACTURER_MODALAI) # Make malloc() thread-safe add_definitions(-DTHREADSAFE_MALLOC) +# Default to telemetry view on boot +add_definitions(-DDEFAULT_VIEW_TELEMETRY) + if(PCB STREQUAL M207) set(PWR_BUTTON "SWITCH" CACHE STRING "Pwr button type (PRESS/SWITCH)") #set(HAPTIC YES)