diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index aa0718740df8..7c94443204ff 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -2509,6 +2509,7 @@ Documentation Infrastructure: - dts/bindings/wifi/nordic,nrf7000-spi.yaml - dts/bindings/wifi/nordic,nrf7001-qspi.yaml - dts/bindings/wifi/nordic,nrf7001-spi.yaml + - dts/bindings/wifi/nordic,nrf7120-wifi.yaml - boards/shields/nrf7002ek/ labels: - "area: Wi-Fi" diff --git a/boards/nordic/nrf7120dk/Kconfig.defconfig b/boards/nordic/nrf7120dk/Kconfig.defconfig new file mode 100644 index 000000000000..cfd142f10b5e --- /dev/null +++ b/boards/nordic/nrf7120dk/Kconfig.defconfig @@ -0,0 +1,36 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config HW_STACK_PROTECTION + default ARCH_HAS_STACK_PROTECTION + +if BOARD_NRF7120DK_NRF7120_CPUAPP + +config HAS_BT_CTLR + default BT + +config ROM_START_OFFSET + default 0x800 if BOOTLOADER_MCUBOOT + +endif # BOARD_NRF7120DK_NRF7120_CPUAPP + +if BOARD_NRF7120DK_NRF7120_CPUAPP_NS + +config BOARD_NRF7120DK + select USE_DT_CODE_PARTITION + +config HAS_BT_CTLR + default BT + +# By default, if we build for a Non-Secure version of the board, +# enable building with TF-M as the Secure Execution Environment. +config BUILD_WITH_TFM + default y + +# By default, if we build with TF-M, instruct build system to +# flash the combined TF-M (Secure) & Zephyr (Non Secure) image +config TFM_FLASH_MERGED_BINARY + default y + depends on BUILD_WITH_TFM + +endif # BOARD_NRF7120DK_NRF7120_CPUAPP_NS diff --git a/boards/nordic/nrf7120dk/Kconfig.nrf7120dk b/boards/nordic/nrf7120dk/Kconfig.nrf7120dk new file mode 100644 index 000000000000..37223f60bcd4 --- /dev/null +++ b/boards/nordic/nrf7120dk/Kconfig.nrf7120dk @@ -0,0 +1,7 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 +config BOARD_NRF7120DK + select SOC_NRF7120_ENGA_CPUAPP if BOARD_NRF7120DK_NRF7120_CPUAPP || \ + BOARD_NRF7120DK_NRF7120_CPUAPP_NS + select SOC_NRF7120_ENGA_CPUFLPR if BOARD_NRF7120DK_NRF7120_CPUFLPR || \ + BOARD_NRF7120DK_NRF7120_CPUFLPR_XIP diff --git a/boards/nordic/nrf7120dk/board.cmake b/boards/nordic/nrf7120dk/board.cmake new file mode 100644 index 000000000000..2d88640f297b --- /dev/null +++ b/boards/nordic/nrf7120dk/board.cmake @@ -0,0 +1,20 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_SOC_NRF7120_ENGA_CPUAPP) + board_runner_args(jlink "--device=cortex-m33" "--speed=4000") +elseif(CONFIG_SOC_NRF7120_ENGA_CPUFLPR) + board_runner_args(jlink "--speed=4000") +endif() + +if(BOARD_NRF7120DK_NRF7120_CPUAPP_NS) + set(TFM_PUBLIC_KEY_FORMAT "full") +endif() + +if(CONFIG_TFM_FLASH_MERGED_BINARY) + set_property(TARGET runners_yaml_props_target PROPERTY hex_file tfm_merged.hex) +endif() + +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) +include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/nordic/nrf7120dk/board.yml b/boards/nordic/nrf7120dk/board.yml new file mode 100644 index 000000000000..1923e74fea8f --- /dev/null +++ b/boards/nordic/nrf7120dk/board.yml @@ -0,0 +1,10 @@ +board: + name: nrf7120dk + vendor: nordic + socs: + - name: nrf7120 + variants: + - name: xip + cpucluster: cpuflpr + - name: ns + cpucluster: cpuapp diff --git a/boards/nordic/nrf7120dk/doc/index.rst b/boards/nordic/nrf7120dk/doc/index.rst new file mode 100644 index 000000000000..e43805f8857a --- /dev/null +++ b/boards/nordic/nrf7120dk/doc/index.rst @@ -0,0 +1,103 @@ +.. zephyr:board:: nrf7120dk + +Overview +******** + +The nRF7120 Development Kit hardware provides support for the Nordic Semiconductor +nRF7120 Arm Cortex-M33 CPU and the following devices: + +* :abbr:`SAADC (Successive Approximation Analog to Digital Converter)` +* CLOCK +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`TWIM (I2C-compatible two-wire interface master with EasyDMA)` +* MEMCONF +* :abbr:`MPU (Memory Protection Unit)` +* MRAM +* MSPI +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* :abbr:`GRTC (Global real-time counter)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UARTE (Universal asynchronous receiver-transmitter)` +* :abbr:`WDT (Watchdog Timer)` + +Hardware +******** + +nRF7120 DK has two crystal oscillators: + +* High-frequency 64 MHz crystal oscillator (HFXO) +* Low-frequency 32.768 kHz crystal oscillator (LFXO) + +The crystal oscillators can be configured to use either +internal or external capacitors. + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Applications for the ``nrf7120dk/nrf7120/cpuapp`` board target can be +built, flashed, and debugged in the usual way. See +:ref:`build_an_application` and :ref:`application_run` for more details on +building and running. + +Applications for the ``nrf7120dk/nrf7120/cpuflpr`` board target need +to be built using sysbuild to include the ``vpr_launcher`` image for the application core. + +Enter the following command to compile ``hello_world`` for the FLPR core: + +.. code-block:: console + + west build -p -b nrf7120dk/nrf7120/cpuflpr --sysbuild + + +Flashing +======== + +As an example, this section shows how to build and flash the :zephyr:code-sample:`hello_world` +application. + +.. warning:: + + When programming the device, you might get an error similar to the following message:: + + ERROR: The operation attempted is unavailable due to readback protection in + ERROR: your device. Please use --recover to unlock the device. + + This error occurs when readback protection is enabled. + To disable the readback protection, you must *recover* your device. + + Enter the following command to recover the core:: + + west flash --recover + + The ``--recover`` command erases the flash memory and then writes a small binary into + the recovered flash memory. + This binary prevents the readback protection from enabling itself again after a pin + reset or power cycle. + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. + +To build and program the sample to the nRF7120 DK, complete the following steps: + +First, connect the nRF7120 DK to you computer using the IMCU USB port on the DK. +Next, build the sample by running the following command: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nrf7120dk/nrf7120/cpuapp + :goals: build flash + +Testing the LEDs and buttons in the nRF7120 DK +************************************************ + +Test the nRF7120 DK with a :zephyr:code-sample:`blinky` sample. diff --git a/boards/nordic/nrf7120dk/nrf7120_cpuapp_common.dtsi b/boards/nordic/nrf7120dk/nrf7120_cpuapp_common.dtsi new file mode 100644 index 000000000000..7f2ae3f38843 --- /dev/null +++ b/boards/nordic/nrf7120dk/nrf7120_cpuapp_common.dtsi @@ -0,0 +1,168 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* This file is common to the secure and non-secure domain */ + +#include "arm/nordic/nrf7120_enga_cpuapp.dtsi" +#include "nrf7120dk_nrf7120-common.dtsi" + +/ { + chosen { + zephyr,console = &uart30; + zephyr,shell-uart = &uart30; + zephyr,uart-mcumgr = &uart30; + zephyr,bt-mon-uart = &uart30; + zephyr,bt-c2h-uart = &uart30; + zephyr,flash = &cpuapp_mram; + zephyr,ieee802154 = &ieee802154; + zephyr,wifi = &wlan0; + }; + + /* TODO: Fine tune the sizes */ + ipc_shm_area_cpuapp_cpuuma: memory@200C0000 { + compatible = "mmio-sram"; + reg = <0x200C0000 0x2000>; + ranges = <0x0 0x200C0000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + status = "okay"; + + ipc_shm_cpuapp_cpuuma_0: memory@0 { + reg = <0x0 DT_SIZE_K(2)>; + }; + + ipc_shm_cpuuma_cpuapp_0: memory@800 { + reg = <0x800 DT_SIZE_K(2)>; + }; + + ipc_shm_cpuapp_cpuuma_1: memory@1000 { + reg = <0x1000 DT_SIZE_K(2)>; + }; + + ipc_shm_cpuuma_cpuapp_1: memory@1800 { + reg = <0x1800 DT_SIZE_K(2)>; + }; + }; + + ipc { + ipc0: ipc0 { + compatible = "zephyr,ipc-icmsg"; + tx-region = <&ipc_shm_cpuapp_cpuuma_0>; + rx-region = <&ipc_shm_cpuuma_cpuapp_0>; + mboxes = <&wifi_bellboard 2>, + <&cpuapp_bellboard 0>; + mbox-names = "tx", "rx"; + status = "okay"; + }; + + ipc1: ipc1 { + compatible = "zephyr,ipc-icmsg"; + tx-region = <&ipc_shm_cpuapp_cpuuma_1>; + rx-region = <&ipc_shm_cpuuma_cpuapp_1>; + mboxes = <&wifi_bellboard 3>, + <&cpuapp_bellboard 1>; + mbox-names = "tx", "rx"; + status = "okay"; + }; + }; +}; + +&cpuapp_sram { + status = "okay"; +}; + +&grtc { + owned-channels = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>; + /* Channels 7-11 reserved for Zero Latency IRQs, 3-4 for FLPR */ + child-owned-channels = <3 4 7 8 9 10 11>; + status = "okay"; +}; + +&uart30 { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&gpiote20 { + status = "okay"; +}; + +&gpiote30 { + status = "okay"; +}; + +&radio { + status = "okay"; +}; + +&ieee802154 { + status = "okay"; +}; + +&temp { + status = "okay"; +}; + +&clock { + status = "okay"; +}; + +&spi00 { + status = "okay"; + cs-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&spi00_default>; + pinctrl-1 = <&spi00_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&adc { + status = "okay"; +}; + +&pwr_antswc { + status = "okay"; +}; + +&wifi { + status = "okay"; +}; + +&audio_auxpll { + nordic,frequency = ; + status = "okay"; +}; + +&cpuapp_bellboard { + status = "okay"; +}; + +&wifi_bellboard { + status = "okay"; +}; + +&qspi00 { + status = "okay"; + op-mode = "MSPI_OP_MODE_CONTROLLER"; +}; diff --git a/boards/nordic/nrf7120dk/nrf7120dk_nrf7120-common.dtsi b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120-common.dtsi new file mode 100644 index 000000000000..50a219c56a0d --- /dev/null +++ b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120-common.dtsi @@ -0,0 +1,126 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "nrf7120dk_nrf7120-pinctrl.dtsi" + +/ { + leds { + compatible = "gpio-leds"; + + led0: led_0 { + gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>; + label = "Green LED 0"; + }; + + led1: led_1 { + gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + label = "Green LED 1"; + }; + + led2: led_2 { + gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; + label = "Green LED 2"; + }; + + led3: led_3 { + gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; + label = "Green LED 3"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + /* + * PWM signal can be exposed on GPIO pin only within same domain. + * There is only one domain which contains both PWM and GPIO: + * PWM20/21/22 and GPIO Port P1. + * Only LEDs connected to P1 can work with PWM, for example LED1. + */ + + pwm_led1: pwm_led_1 { + pwms = <&pwm20 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + }; + }; + + buttons { + compatible = "gpio-keys"; + + button0: button_0 { + gpios = <&gpio1 13 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 0"; + zephyr,code = ; + }; + + button1: button_1 { + gpios = <&gpio1 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 1"; + zephyr,code = ; + }; + + button2: button_2 { + gpios = <&gpio1 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 2"; + zephyr,code = ; + }; + + button3: button_3 { + gpios = <&gpio0 4 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 3"; + zephyr,code = ; + }; + }; + + aliases { + led0 = &led0; + led1 = &led1; + led2 = &led2; + led3 = &led3; + pwm-led0 = &pwm_led1; + sw0 = &button0; + sw1 = &button1; + sw2 = &button2; + sw3 = &button3; + watchdog0 = &wdt31; + }; +}; + +&uart00 { + current-speed = <115200>; + pinctrl-0 = <&uart00_default>; + pinctrl-1 = <&uart00_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&uart20 { + current-speed = <115200>; + pinctrl-0 = <&uart20_default>; + pinctrl-1 = <&uart20_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&uart30 { + current-speed = <115200>; + pinctrl-0 = <&uart30_default>; + pinctrl-1 = <&uart30_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&pwm20 { + status = "okay"; + pinctrl-0 = <&pwm20_default>; + pinctrl-1 = <&pwm20_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&nfct { + status = "okay"; +}; + +&qspi00 { + pinctrl-0 = <&qspi00_default>; + pinctrl-1 = <&qspi00_sleep>; + pinctrl-names = "default", "sleep"; +}; diff --git a/boards/nordic/nrf7120dk/nrf7120dk_nrf7120-pinctrl.dtsi b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120-pinctrl.dtsi new file mode 100644 index 000000000000..6538af10f840 --- /dev/null +++ b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120-pinctrl.dtsi @@ -0,0 +1,129 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + /omit-if-no-ref/ uart20_default: uart20_default { + group1 { + psels = , + ; + }; + + group2 { + psels = , + ; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ uart20_sleep: uart20_sleep { + group1 { + psels = , + , + , + ; + low-power-enable; + }; + }; + + /omit-if-no-ref/ uart30_default: uart30_default { + group1 { + psels = , + ; + }; + + group2 { + psels = , + ; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ uart30_sleep: uart30_sleep { + group1 { + psels = , + , + , + ; + low-power-enable; + }; + }; + + /omit-if-no-ref/ spi00_default: spi00_default { + group1 { + psels = , + , + ; + }; + }; + + /omit-if-no-ref/ spi00_sleep: spi00_sleep { + group1 { + psels = , + , + ; + low-power-enable; + }; + }; + + /omit-if-no-ref/ pwm20_default: pwm20_default { + group1 { + psels = ; + }; + }; + + /omit-if-no-ref/ pwm20_sleep: pwm20_sleep { + group1 { + psels = ; + low-power-enable; + }; + }; + + /omit-if-no-ref/ uart00_default: uart00_default { + group1 { + psels = , + ; + }; + + group2 { + psels = , + ; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ uart00_sleep: uart00_sleep { + group1 { + psels = , + , + , + ; + low-power-enable; + }; + }; + + /omit-if-no-ref/ qspi00_default: qspi00_default { + group1 { + psels = , + , + , + , + , + ; + nordic,drive-mode = ; + }; + }; + + /omit-if-no-ref/ qspi00_sleep: qspi00_sleep { + group1 { + low-power-enable; + psels = , + , + , + , + , + ; + }; + }; +}; diff --git a/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuapp.dts b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuapp.dts new file mode 100644 index 000000000000..e8ed5ce1abd9 --- /dev/null +++ b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuapp.dts @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include "nrf7120_cpuapp_common.dtsi" + +/ { + compatible = "nordic,nrf7120dk_nrf7120-cpuapp"; + model = "Nordic nRF7120 DK nRF7120 Application MCU"; + + chosen { + zephyr,sram = &cpuapp_sram; + }; +}; + +#include diff --git a/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuapp.yaml b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuapp.yaml new file mode 100644 index 000000000000..93b8db953b4d --- /dev/null +++ b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuapp.yaml @@ -0,0 +1,24 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +identifier: nrf7120dk/nrf7120/cpuapp +name: nRF7120-DK-nRF7120-Application +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +sysbuild: true +ram: 512 +flash: 960 +supported: + - adc + - counter + - gpio + - i2c + - pwm + - spi + - watchdog + - i2s + - wifi diff --git a/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuapp_defconfig b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuapp_defconfig new file mode 100644 index 000000000000..8ff96446de24 --- /dev/null +++ b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuapp_defconfig @@ -0,0 +1,25 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# MPU-based null-pointer dereferencing detection cannot +# be applied as the (0x0 - 0x400) is unmapped for this target. +CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y + +# Start SYSCOUNTER on driver init +CONFIG_NRF_GRTC_START_SYSCOUNTER=y diff --git a/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuapp_ns.dts b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuapp_ns.dts new file mode 100644 index 000000000000..56f2104393d4 --- /dev/null +++ b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuapp_ns.dts @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#define USE_NON_SECURE_ADDRESS_MAP 1 + +#include "nrf7120_cpuapp_common.dtsi" + +/ { + compatible = "nordic,nrf7120dk_nrf7120-cpuapp"; + model = "Nordic nRF7120 DK nRF7120 Application MCU"; + + chosen { + zephyr,code-partition = &slot0_ns_partition; + zephyr,sram = &cpuapp_sram; + }; +}; + +&uart30 { + /* Disable so that TF-M can use this UART */ + status = "disabled"; +}; + +#include diff --git a/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuapp_ns.yaml b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuapp_ns.yaml new file mode 100644 index 000000000000..b8153da141af --- /dev/null +++ b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuapp_ns.yaml @@ -0,0 +1,22 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +identifier: nrf7120dk/nrf7120/cpuapp/ns +name: nRF7120-DK-nRF7120-Application-Non-Secure +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 896 +flash: 4088 +supported: + - adc + - gpio + - i2c + - spi + - counter + - watchdog + - adc + - i2s diff --git a/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuapp_ns_defconfig b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuapp_ns_defconfig new file mode 100644 index 000000000000..771440c64940 --- /dev/null +++ b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuapp_ns_defconfig @@ -0,0 +1,37 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# This Board implies building Non-Secure firmware +CONFIG_TRUSTED_EXECUTION_NONSECURE=y + +# Use devicetree code partition for TF-M +CONFIG_USE_DT_CODE_PARTITION=y + +# Don't enable the cache in the non-secure image as it is a +# secure-only peripheral on 71x series +CONFIG_CACHE_MANAGEMENT=n +CONFIG_EXTERNAL_CACHE=n + +CONFIG_UART_CONSOLE=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y + +# Enable GPIO +CONFIG_GPIO=y + +# Start SYSCOUNTER on driver init +CONFIG_NRF_GRTC_START_SYSCOUNTER=y + +# Disable TFM BL2 since it is not supported +CONFIG_TFM_BL2=n diff --git a/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuflpr.dts b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuflpr.dts new file mode 100644 index 000000000000..c10a66d64052 --- /dev/null +++ b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuflpr.dts @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include "nordic/nrf7120_enga_cpuflpr.dtsi" +#include "nrf7120dk_nrf7120-common.dtsi" + +/ { + model = "Nordic nRF7120 DK nRF7120 FLPR MCU"; + compatible = "nordic,nrf7120dk_nrf7120-cpuflpr"; + + chosen { + zephyr,console = &uart00; + zephyr,shell-uart = &uart00; + zephyr,code-partition = &cpuflpr_code_partition; + zephyr,flash = &cpuflpr_mram; + zephyr,sram = &cpuflpr_sram; + }; +}; + +&cpuflpr_sram { + status = "okay"; + reg = <0x200e0000 DT_SIZE_K(124)>; + ranges = <0x0 0x200e0000 0x1f000>; +}; + +&cpuflpr_mram { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + cpuflpr_code_partition: partition@0 { + label = "image-0"; + reg = <0 DT_SIZE_K(116)>; + }; + }; +}; + +&grtc { + owned-channels = <3 4>; + status = "okay"; +}; + +&uart00 { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&gpiote20 { + status = "okay"; +}; + +&gpiote30 { + status = "okay"; +}; diff --git a/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuflpr.yaml b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuflpr.yaml new file mode 100644 index 000000000000..53125d8ff031 --- /dev/null +++ b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuflpr.yaml @@ -0,0 +1,18 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +identifier: nrf7120dk/nrf7120/cpuflpr +name: nRF7120-DK-nRF7120-Fast-Lightweight-Peripheral-Processor +type: mcu +arch: riscv +toolchain: + - zephyr +sysbuild: true +ram: 124 +flash: 116 +supported: + - counter + - gpio + - i2c + - spi + - watchdog diff --git a/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuflpr_defconfig b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuflpr_defconfig new file mode 100644 index 000000000000..90cf13bdee5e --- /dev/null +++ b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuflpr_defconfig @@ -0,0 +1,17 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable GPIO +CONFIG_GPIO=y + +CONFIG_USE_DT_CODE_PARTITION=y + +# Execute from SRAM +CONFIG_XIP=n diff --git a/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuflpr_xip.dts b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuflpr_xip.dts new file mode 100644 index 000000000000..8c0b6285416e --- /dev/null +++ b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuflpr_xip.dts @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "nrf7120dk_nrf7120_cpuflpr.dts" diff --git a/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuflpr_xip.yaml b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuflpr_xip.yaml new file mode 100644 index 000000000000..73b927a2f09e --- /dev/null +++ b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuflpr_xip.yaml @@ -0,0 +1,18 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +identifier: nrf7120dk/nrf7120/cpuflpr/xip +name: nRF7120-DK-nRF7120-Fast-Lightweight-Peripheral-Processor (MRAM XIP) +type: mcu +arch: riscv +toolchain: + - zephyr +sysbuild: true +ram: 124 +flash: 116 +supported: + - counter + - gpio + - i2c + - spi + - watchdog diff --git a/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuflpr_xip_defconfig b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuflpr_xip_defconfig new file mode 100644 index 000000000000..f0b4a7dc2802 --- /dev/null +++ b/boards/nordic/nrf7120dk/nrf7120dk_nrf7120_cpuflpr_xip_defconfig @@ -0,0 +1,15 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable GPIO +CONFIG_GPIO=y + +# Execute from MRAM +CONFIG_XIP=y diff --git a/drivers/wifi/nrf_wifi/Kconfig.nrfwifi b/drivers/wifi/nrf_wifi/Kconfig.nrfwifi index be0ea854b2e2..e17db4f85735 100644 --- a/drivers/wifi/nrf_wifi/Kconfig.nrfwifi +++ b/drivers/wifi/nrf_wifi/Kconfig.nrfwifi @@ -6,7 +6,7 @@ # # TODO: Use DTS generated Kconfig once the board support is added -DT_COMPAT_NORDIC_WIFI71 := nordic,nrf7120 +DT_COMPAT_NORDIC_WIFI71 := nordic,nrf7120-wifi menuconfig WIFI_NRF70 bool "nRF70 driver" diff --git a/dts/arm/nordic/nrf7120_enga_cpuapp.dtsi b/dts/arm/nordic/nrf7120_enga_cpuapp.dtsi new file mode 100644 index 000000000000..24b3ae2aea87 --- /dev/null +++ b/dts/arm/nordic/nrf7120_enga_cpuapp.dtsi @@ -0,0 +1,145 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +cpu: &cpuapp {}; + +systick: &cpuapp_systick {}; + +nvic: &cpuapp_nvic {}; + +/delete-node/ &cpuflpr; +/delete-node/ &cpuflpr_clic; + +/ { + chosen { + zephyr,entropy = &psa_rng; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&cpuapp_nvic>; + ranges; + }; + + psa_rng: psa-rng { + compatible = "zephyr,psa-crypto-rng"; + status = "okay"; + }; +}; + +&cpuflpr_vpr { + cpuapp_vevif_rx: mailbox@1 { + compatible = "nordic,nrf-vevif-event-rx"; + reg = <0x0 0x1000>; + status = "disabled"; + interrupts = <76 NRF_DEFAULT_IRQ_PRIORITY>; + #mbox-cells = <1>; + nordic,events = <1>; + nordic,events-mask = <0x00100000>; + }; + + cpuapp_vevif_tx: mailbox@0 { + compatible = "nordic,nrf-vevif-task-tx"; + reg = <0x0 0x1000>; + #mbox-cells = <1>; + nordic,tasks = <7>; + nordic,tasks-mask = <0x007f0000>; + status = "disabled"; + }; +}; + +&cpuapp_ppb { + compatible = "simple-bus"; + ranges; +}; + +&grtc { +#ifdef USE_NON_SECURE_ADDRESS_MAP + interrupts = <227 NRF_DEFAULT_IRQ_PRIORITY>, +#else + interrupts = <228 NRF_DEFAULT_IRQ_PRIORITY>, +#endif + /* Reserved for Zero Latency IRQs */ + <229 NRF_DEFAULT_IRQ_PRIORITY>; +}; + +&gpiote20 { +#ifdef USE_NON_SECURE_ADDRESS_MAP + interrupts = <218 NRF_DEFAULT_IRQ_PRIORITY>; +#else + interrupts = <219 NRF_DEFAULT_IRQ_PRIORITY>; +#endif +}; + +&gpiote30 { +#ifdef USE_NON_SECURE_ADDRESS_MAP + interrupts = <268 NRF_DEFAULT_IRQ_PRIORITY>; +#else + interrupts = <269 NRF_DEFAULT_IRQ_PRIORITY>; +#endif +}; + +&dppic00 { + status = "okay"; +}; + +&dppic10 { + status = "okay"; +}; + +&dppic20 { + status = "okay"; +}; + +&dppic30 { + status = "okay"; +}; + +&ppib00 { + status = "okay"; +}; + +&ppib01 { + status = "okay"; +}; + +&ppib10 { + status = "okay"; +}; + +&ppib11 { + status = "okay"; +}; + +&ppib20 { + status = "okay"; +}; + +&ppib21 { + status = "okay"; +}; + +&ppib22 { + status = "okay"; +}; + +&ppib30 { + status = "okay"; +}; + +&wifi_bellboard { + compatible = "nordic,nrf-bellboard-tx"; +}; + +&cpuapp_bellboard { + compatible = "nordic,nrf-bellboard-rx"; + interrupts = <120 NRF_DEFAULT_IRQ_PRIORITY>, + <121 NRF_DEFAULT_IRQ_PRIORITY>; + interrupt-names = "irq0", "irq1"; + nordic,interrupt-mapping = <0x0000000f 0>, <0x0000000f 1>; +}; diff --git a/dts/bindings/arm/nordic,nrf-pwr-antswc.yaml b/dts/bindings/arm/nordic,nrf-pwr-antswc.yaml new file mode 100644 index 000000000000..c38ed631b28e --- /dev/null +++ b/dts/bindings/arm/nordic,nrf-pwr-antswc.yaml @@ -0,0 +1,20 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +description: | + + Nordic nRF family pwr-antswc (Powering Antenna Switch) + + Uses pwr-gpios to control the 1.8V supply for the antenna switch. This + pin is SoC specific and cannot be modified at a board level. + Relevant configuration is implemented in SOC_EARLY_INIT_HOOK. + +compatible: "nordic,nrf-pwr-antswc" + +include: base.yaml + +properties: + pwr-gpios: + type: phandle-array + description: | + GPIO specifier that controls power to the antenna switch controller. diff --git a/dts/bindings/clock/nordic,nrf71-lfxo.yaml b/dts/bindings/clock/nordic,nrf71-lfxo.yaml new file mode 100644 index 000000000000..94a7814f29c8 --- /dev/null +++ b/dts/bindings/clock/nordic,nrf71-lfxo.yaml @@ -0,0 +1,56 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +description: Nordic nRF low-frequency crystal oscillator (nRF71 series) + +compatible: "nordic,nrf71-lfxo" + +include: fixed-clock.yaml + +properties: + clock-frequency: + const: 32768 + + load-capacitors: + type: string + enum: + - "internal" + - "external" + description: | + Type of load capacitors connected to the crystal. If not specified, + adjustments may still happen when the device trimming happens during + system initialization. + + load-capacitance-femtofarad: + type: int + enum: + - 0 + - 1000 + - 2000 + - 3000 + - 4000 + - 5000 + - 6000 + - 7000 + - 8000 + - 9000 + - 10000 + - 11000 + - 12000 + - 13000 + - 14000 + - 15000 + - 16000 + - 17000 + - 18000 + - 19000 + - 20000 + - 21000 + - 22000 + - 23000 + - 24000 + - 25000 + + description: | + Load capacitance in femtofarads. This property is only used when + load-capacitors is set to "internal". diff --git a/dts/bindings/wifi/nordic,nrf7120-wifi.yaml b/dts/bindings/wifi/nordic,nrf7120-wifi.yaml new file mode 100644 index 000000000000..77822dd6a1a6 --- /dev/null +++ b/dts/bindings/wifi/nordic,nrf7120-wifi.yaml @@ -0,0 +1,12 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +description: > + This is a representation of the Wi-Fi parts of the nRF71 Series Wi-Fi and + Bluetooth chip SoC. + +compatible: nordic,nrf7120-wifi + +include: + - "wifi-tx-power-2g.yaml" + - "wifi-tx-power-5g.yaml" diff --git a/dts/vendor/nordic/nrf7120_cpuapp_ns_partition.dtsi b/dts/vendor/nordic/nrf7120_cpuapp_ns_partition.dtsi new file mode 100644 index 000000000000..e114134499c4 --- /dev/null +++ b/dts/vendor/nordic/nrf7120_cpuapp_ns_partition.dtsi @@ -0,0 +1,62 @@ +/* + * Copyright 2024 Embeint Inc + * + * SPDX-License-Identifier: Apache-2.0 + * + * Default memory partitioning for nRF7120 application CPU. + */ + +&cpuapp_mram { + /* + * Default NVM layout on NRF7120 Application MCU without BL2: + * This layout matches (by necessity) that in the TF-M repository: + * + * 0x0000_0000 Secure image primary (512 KB) + * 0x0008_0000 Protected Storage Area (16 KB) + * 0x0008_4000 Internal Trusted Storage Area (16 KB) + * 0x0008_8000 OTP / NV counters area (8 KB) + * 0x0008_A000 Non-secure image primary (844 KB) + * 0x0015_D000 Non-secure storage, used when built with NRF_NS_STORAGE=ON, + * otherwise unused (32 KB) + */ + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* This static layout needs to be the same with the upstream TF-M layout in the + * header flash_layout.h of the relevant platform. Any updates in the layout + * needs to happen both in the flash_layout.h and in this file at the same time. + */ + + slot0_partition: partition@0 { + label = "image-0"; + reg = <0x0000000 DT_SIZE_K(512)>; + }; + + tfm_ps_partition: partition@80000 { + label = "tfm-ps"; + reg = <0x00080000 DT_SIZE_K(16)>; + }; + + tfm_its_partition: partition@84000 { + label = "tfm-its"; + reg = <0x00084000 DT_SIZE_K(16)>; + }; + + tfm_otp_partition: partition@88000 { + label = "tfm-otp"; + reg = <0x00088000 DT_SIZE_K(8)>; + }; + + slot0_ns_partition: partition@8A000 { + label = "image-0-nonsecure"; + reg = <0x0008A000 DT_SIZE_K(844)>; + }; + + storage_partition: partition@15D000 { + label = "storage"; + reg = <0x00015D000 DT_SIZE_K(32)>; + }; + }; +}; diff --git a/dts/vendor/nordic/nrf7120_cpuapp_partition.dtsi b/dts/vendor/nordic/nrf7120_cpuapp_partition.dtsi new file mode 100644 index 000000000000..75ce9cb6845d --- /dev/null +++ b/dts/vendor/nordic/nrf7120_cpuapp_partition.dtsi @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + * + * Default memory partitioning for nRF7120 application CPU. + */ + +&cpuapp_mram { + reg = <0x0 DT_SIZE_K(4084)>; +}; + +/* These partition sizes assume no FLPR area in RRAM */ +&cpuapp_mram { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 DT_SIZE_K(64)>; + }; + + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 DT_SIZE_K(1992)>; + }; + + slot1_partition: partition@202000 { + label = "image-1"; + reg = <0x00202000 DT_SIZE_K(1992)>; + }; + + storage_partition: partition@3f4000 { + label = "storage"; + reg = <0x003f4000 DT_SIZE_K(36)>; + }; + }; +}; diff --git a/dts/vendor/nordic/nrf7120_enga.dtsi b/dts/vendor/nordic/nrf7120_enga.dtsi new file mode 100644 index 000000000000..a90f0fa79f09 --- /dev/null +++ b/dts/vendor/nordic/nrf7120_enga.dtsi @@ -0,0 +1,964 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +/delete-node/ &sw_pwm; + +/ { + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpuapp: cpu@0 { + compatible = "arm,cortex-m33f"; + reg = <0>; + device_type = "cpu"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <1>; + + itm: itm@e0000000 { + compatible = "arm,armv8m-itm"; + reg = <0xe0000000 0x1000>; + swo-ref-frequency = ; + }; + }; + + cpuflpr: cpu@1 { + compatible = "nordic,vpr"; + reg = <1>; + device_type = "cpu"; + clock-frequency = ; + riscv,isa = "rv32emc"; + nordic,bus-width = <32>; + }; + }; + + clocks { + pclk: pclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = ; + }; + + pclk32m: pclk32m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = ; + }; + + lfxo: lfxo { + compatible = "nordic,nrf71-lfxo"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + hfxo64m: hfxo64m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = ; + }; + + hfpll: hfpll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = ; + }; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + nordic_reserved: memory@200fe000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mmio-sram"; + reg = <0x200fe000 0x1000>; + ranges = <0x0 0x200fe000 0x1000>; + }; + + nrf_kmu_cracen_exchange_area: memory@200ff000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0x200ff000 0x1000>; + compatible = "zephyr,memory-region", "mmio-sram"; + zephyr,memory-region = "NRF_KMU_CRACEN_EXCHANGE"; + }; + + nrf_mpc_region: memory@50041000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "nordic,nrf-mpc"; + reg = <0x50041000 0x1000>; + override-num = <14>; + override-granularity = <4096>; + }; + }; + + pwr_antswc: pwr_antswc { + compatible = "nordic,nrf-pwr-antswc"; + // This is hardwired to P0.09 in nRF7120 + pwr-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + + ficr: ficr@ffc000 { + compatible = "nordic,nrf-ficr"; + reg = <0xffc000 0x1000>; + #nordic,ficr-cells = <1>; + }; + +#ifdef USE_NON_SECURE_ADDRESS_MAP + /* Intentionally empty because uicr is hardware fixed to Secure */ +#else + uicr: uicr@ffd000 { + compatible = "nordic,nrf-uicr"; + reg = <0xffd000 0x1000>; + status = "disabled"; + }; +#endif + + cpuapp_sram: memory@20000000 { + compatible = "mmio-sram"; + reg = <0x20000000 DT_SIZE_K(512)>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x20000000 0x80000>; + }; + + ram01_sram: memory@20080000 { + compatible = "mmio-sram"; + reg = <0x20080000 DT_SIZE_K(256)>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x20080000 0x40000>; + }; + + ram02_sram: memory@200c0000 { + compatible = "mmio-sram"; + reg = <0x200c0000 DT_SIZE_K(128)>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x200c0000 0x20000>; + }; + + cpuflpr_sram: memory@200e0000 { + compatible = "mmio-sram"; + reg = <0x200e0000 DT_SIZE_K(124)>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x200e0000 0x1f000>; + }; + +#ifdef USE_NON_SECURE_ADDRESS_MAP + global_peripherals: peripheral@40000000 { + reg = <0x40000000 0x10000000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x40000000 0x10000000>; +#else + global_peripherals: peripheral@50000000 { + reg = <0x50000000 0x10000000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x50000000 0x10000000>; + #include "nrf7120_enga_secure_peripherals.dtsi" +#endif + + dppic00: dppic@42000 { + compatible = "nordic,nrf-dppic"; + reg = <0x42000 0x1000>; + status = "disabled"; + }; + + ppib00: ppib@44000 { + compatible = "nordic,nrf-ppib"; + reg = <0x44000 0x1000>; + status = "disabled"; + }; + + ppib01: ppib@45000 { + compatible = "nordic,nrf-ppib"; + reg = <0x45000 0x1000>; + status = "disabled"; + }; + + ccm00: ccm@4a000 { + compatible = "nordic,nrf-ccm"; + reg = <0x4a000 0x1000>; + interrupts = <74 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + }; + + ecb00: ecb@4b000 { + compatible = "nordic,nrf-ecb"; + reg = <0x4b000 0x1000>; + interrupts = <75 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + }; + + cpuflpr_vpr: vpr@4c000 { + compatible = "nordic,nrf-vpr-coprocessor"; + reg = <0x4c000 0x1000>; + ranges = <0x0 0x4c000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + enable-secure; + enable-dma-secure; + + cpuflpr_clic: interrupt-controller@f0000000 { + compatible = "nordic,nrf-clic"; + reg = <0xf0000000 0x1780>; + interrupt-controller; + #interrupt-cells = <2>; + #address-cells = <1>; + status = "disabled"; + }; + }; + + spi00: spi@4d000 { + compatible = "nordic,nrf-spim"; + reg = <0x4d000 0x1000>; + interrupts = <77 NRF_DEFAULT_IRQ_PRIORITY>; + #address-cells = <1>; + #size-cells = <0>; + max-frequency = ; + easydma-maxcnt-bits = <16>; + rx-delay-supported; + rx-delay = <1>; + status = "disabled"; + }; + + uart00: uart@4d000 { + compatible = "nordic,nrf-uarte"; + reg = <0x4d000 0x1000>; + interrupts = <77 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + endtx-stoptx-supported; + frame-timeout-supported; + }; + + gpio2: gpio@50400 { + compatible = "nordic,nrf-gpio"; + reg = <0x50400 0x200>; + gpio-controller; + #gpio-cells = <2>; + port = <2>; + ngpios = <12>; + status = "disabled"; + }; + + ctrlap: ctrlap@52000 { + compatible = "nordic,nrf-ctrlapperi"; + reg = <0x52000 0x1000>; + interrupts = <82 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + }; + + timer00: timer@55000 { + compatible = "nordic,nrf-timer"; + reg = <0x55000 0x1000>; + interrupts = <85 NRF_DEFAULT_IRQ_PRIORITY>; + clocks = <&hfpll>; + cc-num = <6>; + max-bit-width = <32>; + prescaler = <0>; + status = "disabled"; + }; + + egu00: egu@58000 { + compatible = "nordic,nrf-egu"; + reg = <0x58000 0x1000>; + interrupts = <88 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + }; + + qspi00: qspi@5b000 { + compatible = "nordic,nrf-qspi-v2", "snps,designware-ssi"; + interrupts = <91 NRF_DEFAULT_IRQ_PRIORITY>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x5b000 0x900 0x5b900 0x700>; + reg-names = "wrapper", "core"; + clock-frequency = ; + fifo-depth = <16>; + packet-data-limit = <65536>; + dma-transmit-data-level = <8>; + dma-receive-data-level = <8>; + status = "disabled"; + }; + + qspi01: qspi@5c000 { + compatible = "nordic,nrf-qspi-v2", "snps,designware-ssi"; + interrupts = <92 NRF_DEFAULT_IRQ_PRIORITY>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x5c000 0x900 0x5c900 0x700>; + reg-names = "wrapper", "core"; + clock-frequency = ; + fifo-depth = <16>; + packet-data-limit = <65536>; + dma-transmit-data-level = <8>; + dma-receive-data-level = <8>; + status = "disabled"; + }; + + spi01: spi@5d000 { + compatible = "nordic,nrf-spim"; + reg = <0x5d000 0x1000>; + interrupts = <93 NRF_DEFAULT_IRQ_PRIORITY>; + #address-cells = <1>; + #size-cells = <0>; + max-frequency = ; + easydma-maxcnt-bits = <16>; + rx-delay-supported; + rx-delay = <1>; + status = "disabled"; + }; + + dppic10: dppic@82000 { + compatible = "nordic,nrf-dppic"; + reg = <0x82000 0x1000>; + status = "disabled"; + }; + + ppib10: ppib@83000 { + compatible = "nordic,nrf-ppib"; + reg = <0x83000 0x1000>; + status = "disabled"; + }; + + ppib11: ppib@84000 { + compatible = "nordic,nrf-ppib"; + reg = <0x84000 0x1000>; + status = "disabled"; + }; + + timer10: timer@85000 { + compatible = "nordic,nrf-timer"; + reg = <0x85000 0x1000>; + interrupts = <133 NRF_DEFAULT_IRQ_PRIORITY>; + clocks = <&pclk32m>; + cc-num = <8>; + max-bit-width = <32>; + prescaler = <0>; + status = "disabled"; + }; + + egu10: egu@87000 { + compatible = "nordic,nrf-egu"; + reg = <0x87000 0x1000>; + interrupts = <135 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + }; + + radio: radio@8a000 { + compatible = "nordic,nrf-radio"; + reg = <0x8a000 0x2000>; + interrupts = <138 NRF_DEFAULT_IRQ_PRIORITY>; + dfe-supported; + ieee802154-supported; + ble-2mbps-supported; + ble-coded-phy-supported; + status = "disabled"; + + ieee802154: ieee802154 { + compatible = "nordic,nrf-ieee802154"; + status = "disabled"; + }; + + bt_hci_sdc: bt_hci_sdc { + compatible = "nordic,bt-hci-sdc"; + status = "disabled"; + }; + + bt_hci_controller: bt_hci_controller { + compatible = "zephyr,bt-hci-ll-sw-split"; + status = "disabled"; + }; + }; + + ipct10: ipct@8d000 { + compatible = "nordic,nrf-ipct-global"; + reg = <0x8d000 0x1000>; + interrupts = <141 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + }; + + dppic20: dppic@c2000 { + compatible = "nordic,nrf-dppic"; + reg = <0xc2000 0x1000>; + status = "disabled"; + }; + + ppib20: ppib@c3000 { + compatible = "nordic,nrf-ppib"; + reg = <0xc3000 0x1000>; + status = "disabled"; + }; + + ppib21: ppib@c4000 { + compatible = "nordic,nrf-ppib"; + reg = <0xc4000 0x1000>; + status = "disabled"; + }; + + ppib22: ppib@c5000 { + compatible = "nordic,nrf-ppib"; + reg = <0xc5000 0x1000>; + status = "disabled"; + }; + + spi20: spi@c6000 { + compatible = "nordic,nrf-spim"; + reg = <0xc6000 0x1000>; + interrupts = <198 NRF_DEFAULT_IRQ_PRIORITY>; + #address-cells = <1>; + #size-cells = <0>; + max-frequency = ; + easydma-maxcnt-bits = <16>; + rx-delay-supported; + rx-delay = <1>; + status = "disabled"; + }; + + i2c20: i2c@c6000 { + compatible = "nordic,nrf-twim"; + reg = <0xc6000 0x1000>; + interrupts = <198 NRF_DEFAULT_IRQ_PRIORITY>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = ; + easydma-maxcnt-bits = <16>; + status = "disabled"; + }; + + uart20: uart@c6000 { + compatible = "nordic,nrf-uarte"; + reg = <0xc6000 0x1000>; + interrupts = <198 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + endtx-stoptx-supported; + frame-timeout-supported; + }; + + spi21: spi@c7000 { + compatible = "nordic,nrf-spim"; + reg = <0xc7000 0x1000>; + interrupts = <199 NRF_DEFAULT_IRQ_PRIORITY>; + #address-cells = <1>; + #size-cells = <0>; + max-frequency = ; + easydma-maxcnt-bits = <16>; + rx-delay-supported; + rx-delay = <1>; + status = "disabled"; + }; + + i2c21: i2c@c7000 { + compatible = "nordic,nrf-twim"; + reg = <0xc7000 0x1000>; + interrupts = <199 NRF_DEFAULT_IRQ_PRIORITY>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = ; + easydma-maxcnt-bits = <16>; + status = "disabled"; + }; + + uart21: uart@c7000 { + compatible = "nordic,nrf-uarte"; + reg = <0xc7000 0x1000>; + interrupts = <199 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + endtx-stoptx-supported; + frame-timeout-supported; + }; + + spi22: spi@c8000 { + compatible = "nordic,nrf-spim"; + reg = <0xc8000 0x1000>; + interrupts = <200 NRF_DEFAULT_IRQ_PRIORITY>; + #address-cells = <1>; + #size-cells = <0>; + max-frequency = ; + easydma-maxcnt-bits = <16>; + rx-delay-supported; + rx-delay = <1>; + status = "disabled"; + }; + + i2c22: i2c@c8000 { + compatible = "nordic,nrf-twim"; + reg = <0xc8000 0x1000>; + interrupts = <200 NRF_DEFAULT_IRQ_PRIORITY>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = ; + easydma-maxcnt-bits = <16>; + status = "disabled"; + }; + + uart22: uart@c8000 { + compatible = "nordic,nrf-uarte"; + reg = <0xc8000 0x1000>; + interrupts = <200 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + endtx-stoptx-supported; + frame-timeout-supported; + }; + + egu20: egu@c9000 { + compatible = "nordic,nrf-egu"; + reg = <0xc9000 0x1000>; + interrupts = <201 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + }; + + timer20: timer@ca000 { + compatible = "nordic,nrf-timer"; + reg = <0xca000 0x1000>; + interrupts = <202 NRF_DEFAULT_IRQ_PRIORITY>; + cc-num = <6>; + max-bit-width = <32>; + prescaler = <0>; + status = "disabled"; + }; + + timer21: timer@cb000 { + compatible = "nordic,nrf-timer"; + reg = <0xcb000 0x1000>; + interrupts = <203 NRF_DEFAULT_IRQ_PRIORITY>; + cc-num = <6>; + max-bit-width = <32>; + prescaler = <0>; + status = "disabled"; + }; + + timer22: timer@cc000 { + compatible = "nordic,nrf-timer"; + reg = <0xcc000 0x1000>; + interrupts = <204 NRF_DEFAULT_IRQ_PRIORITY>; + cc-num = <6>; + max-bit-width = <32>; + prescaler = <0>; + status = "disabled"; + }; + + timer23: timer@cd000 { + compatible = "nordic,nrf-timer"; + reg = <0xcd000 0x1000>; + interrupts = <205 NRF_DEFAULT_IRQ_PRIORITY>; + cc-num = <6>; + max-bit-width = <32>; + prescaler = <0>; + status = "disabled"; + }; + + timer24: timer@ce000 { + compatible = "nordic,nrf-timer"; + reg = <0xce000 0x1000>; + interrupts = <206 NRF_DEFAULT_IRQ_PRIORITY>; + cc-num = <6>; + max-bit-width = <32>; + prescaler = <0>; + status = "disabled"; + }; + + pdm20: pdm@d0000 { + compatible = "nordic,nrf-pdm"; + reg = <0xd0000 0x1000>; + interrupts = <208 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + }; + + pdm21: pdm@d1000 { + compatible = "nordic,nrf-pdm"; + reg = <0xd1000 0x1000>; + interrupts = <209 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + }; + + pwm20: pwm@d2000 { + compatible = "nordic,nrf-pwm"; + reg = <0xd2000 0x1000>; + interrupts = <210 NRF_DEFAULT_IRQ_PRIORITY>; + #pwm-cells = <3>; + status = "disabled"; + idleout-supported; + }; + + pwm21: pwm@d3000 { + compatible = "nordic,nrf-pwm"; + reg = <0xd3000 0x1000>; + interrupts = <211 NRF_DEFAULT_IRQ_PRIORITY>; + #pwm-cells = <3>; + status = "disabled"; + idleout-supported; + }; + + pwm22: pwm@d4000 { + compatible = "nordic,nrf-pwm"; + reg = <0xd4000 0x1000>; + interrupts = <212 NRF_DEFAULT_IRQ_PRIORITY>; + #pwm-cells = <3>; + status = "disabled"; + idleout-supported; + }; + + adc: adc@d5000 { + compatible = "nordic,nrf-saadc"; + reg = <0xd5000 0x1000>; + interrupts = <213 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + #io-channel-cells = <1>; + }; + + nfct: nfct@d6000 { + compatible = "nordic,nrf-nfct"; + reg = <0xd6000 0x1000>; + interrupts = <214 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + }; + + temp: temp@d7000 { + compatible = "nordic,nrf-temp"; + reg = <0xd7000 0x1000>; + interrupts = <215 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + }; + + gpio1: gpio@d8200 { + compatible = "nordic,nrf-gpio"; + reg = <0xd8200 0x200>; + gpio-controller; + #gpio-cells = <2>; + port = <1>; + ngpios = <16>; + gpiote-instance = <&gpiote20>; + status = "disabled"; + }; + + gpio3: gpio@d8600 { + compatible = "nordic,nrf-gpio"; + reg = <0xd8600 0x200>; + gpio-controller; + #gpio-cells = <2>; + port = <3>; + ngpios = <12>; + gpiote-instance = <&gpiote20>; + status = "disabled"; + }; + + gpio4: gpio@d8800 { + compatible = "nordic,nrf-gpio"; + reg = <0xd8800 0x200>; + gpio-controller; + #gpio-cells = <2>; + port = <4>; + ngpios = <12>; + status = "disabled"; + }; + + gpiote20: gpiote@da000 { + compatible = "nordic,nrf-gpiote"; + reg = <0xda000 0x1000>; + instance = <20>; + status = "disabled"; + }; + + qdec20: qdec@e0000 { + compatible = "nordic,nrf-qdec"; + reg = <0xe0000 0x1000>; + interrupts = <224 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + }; + + qdec21: qdec@e1000 { + compatible = "nordic,nrf-qdec"; + reg = <0xe1000 0x1000>; + interrupts = <225 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + }; + + grtc: grtc@e2000 { + compatible = "nordic,nrf-grtc"; + reg = <0xe2000 0x1000>; + cc-num = <16>; + clocks = <&lfxo>, <&pclk>; + clock-names = "lfclock", "hfclock"; + status = "disabled"; + }; + + tdm: tdm@e8000 { + compatible = "nordic,nrf-tdm"; + easydma-maxcnt-bits = <15>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xe8000 0x1000>; + interrupts = <232 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + clocks = <&pclk32m>; + }; + + spi23: spi@ed000 { + compatible = "nordic,nrf-spim"; + reg = <0xed000 0x1000>; + interrupts = <237 NRF_DEFAULT_IRQ_PRIORITY>; + #address-cells = <1>; + #size-cells = <0>; + max-frequency = ; + easydma-maxcnt-bits = <16>; + rx-delay-supported; + rx-delay = <1>; + status = "disabled"; + }; + + i2c23: i2c@ed000 { + compatible = "nordic,nrf-twim"; + reg = <0xed000 0x1000>; + interrupts = <237 NRF_DEFAULT_IRQ_PRIORITY>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = ; + easydma-maxcnt-bits = <16>; + status = "disabled"; + }; + + uart23: uart@ed000 { + compatible = "nordic,nrf-uarte"; + reg = <0xed000 0x1000>; + interrupts = <237 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + endtx-stoptx-supported; + frame-timeout-supported; + }; + + spi24: spi@ee000 { + compatible = "nordic,nrf-spim"; + reg = <0xee000 0x1000>; + interrupts = <238 NRF_DEFAULT_IRQ_PRIORITY>; + #address-cells = <1>; + #size-cells = <0>; + max-frequency = ; + easydma-maxcnt-bits = <16>; + rx-delay-supported; + rx-delay = <1>; + status = "disabled"; + }; + + i2c24: i2c@ee000 { + compatible = "nordic,nrf-twim"; + reg = <0xee000 0x1000>; + interrupts = <238 NRF_DEFAULT_IRQ_PRIORITY>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = ; + easydma-maxcnt-bits = <16>; + status = "disabled"; + }; + + uart24: uart@ee000 { + compatible = "nordic,nrf-uarte"; + reg = <0xee000 0x1000>; + interrupts = <238 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + endtx-stoptx-supported; + frame-timeout-supported; + }; + + dppic30: dppic@102000 { + compatible = "nordic,nrf-dppic"; + reg = <0x102000 0x1000>; + status = "disabled"; + }; + + ppib30: ppib@103000 { + compatible = "nordic,nrf-ppib"; + reg = <0x103000 0x1000>; + status = "disabled"; + }; + + spi30: spi@104000 { + compatible = "nordic,nrf-spim"; + reg = <0x104000 0x1000>; + interrupts = <260 NRF_DEFAULT_IRQ_PRIORITY>; + #address-cells = <1>; + #size-cells = <0>; + max-frequency = ; + easydma-maxcnt-bits = <16>; + rx-delay-supported; + rx-delay = <1>; + status = "disabled"; + }; + + i2c30: i2c@104000 { + compatible = "nordic,nrf-twim"; + reg = <0x104000 0x1000>; + interrupts = <260 NRF_DEFAULT_IRQ_PRIORITY>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = ; + easydma-maxcnt-bits = <16>; + status = "disabled"; + }; + + uart30: uart@104000 { + compatible = "nordic,nrf-uarte"; + reg = <0x104000 0x1000>; + interrupts = <260 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + endtx-stoptx-supported; + frame-timeout-supported; + }; + + comp: comp@106000 { + compatible = "nordic,nrf-comp"; + reg = <0x106000 0x1000>; + interrupts = <262 NRF_DEFAULT_IRQ_PRIORITY>; + #io-channels-cells = <1>; + status = "disabled"; + }; + + wdt31: wdt@109000 { + compatible = "nordic,nrf-wdt"; + reg = <0x109000 0x1000>; + interrupts = <265 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + }; + + gpio0: gpio@10a000 { + compatible = "nordic,nrf-gpio"; + reg = <0x10a000 0x200>; + gpio-controller; + #gpio-cells = <2>; + port = <0>; + ngpios = <13>; + gpiote-instance = <&gpiote30>; + status = "disabled"; + }; + + gpiote30: gpiote@10c000 { + compatible = "nordic,nrf-gpiote"; + reg = <0x10c000 0x1000>; + instance = <30>; + status = "disabled"; + }; + + clock: clock@10e000 { + compatible = "nordic,nrf-clock"; + reg = <0x10e000 0x1000>; + interrupts = <270 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + }; + + audio_auxpll: auxpll@130000 { + compatible = "nordic,nrf-auxpll"; + reg = <0x130000 0x1000>; + interrupts = <304 NRF_DEFAULT_IRQ_PRIORITY>; + clocks = <&pclk32m>; + #clock-cells = <0>; + /* + * Temporarily reading FICR addr 0 as FICR offsets + * not defined yet + */ + nordic,ficrs = <&ficr 0>; + nordic,out-div = ; + nordic,out-drive = <0>; + nordic,current-tune = <9>; + nordic,sdm-disable; + nordic,range = "mid"; + status = "disabled"; + }; + + cpuapp_ppb: cpuapp-ppb-bus { + #address-cells = <1>; + #size-cells = <1>; + + cpuapp_systick: timer@e000e010 { + compatible = "arm,armv8m-systick"; + reg = <0xe000e010 0x10>; + status = "disabled"; + }; + + cpuapp_nvic: interrupt-controller@e000e100 { + #address-cells = <1>; + compatible = "arm,v8m-nvic"; + reg = <0xe000e100 0xc00>; + arm,num-irq-priority-bits = <3>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + }; + + wifi_bellboard: mailbox@40074000 { + reg = <0x40074000 0x1000>; + status = "disabled"; + #mbox-cells = <1>; + }; + + cpuapp_bellboard: mailbox@40078000 { + reg = <0x40078000 0x1000>; + status = "disabled"; + #mbox-cells = <1>; + }; + + mram_controller: mram-controller@5004e000 { + compatible = "nordic,nrf-mramc"; + reg = <0x5004e000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + interrupts = <78 NRF_DEFAULT_IRQ_PRIORITY>; + + cpuapp_mram: mram@0 { + compatible = "soc-nv-flash"; + reg = <0 DT_SIZE_K(3968)>; + erase-block-size = <4096>; + write-block-size = <4>; + }; + + cpuflpr_mram: mram@3e0000 { + compatible = "soc-nv-flash"; + reg = <0x3e0000 DT_SIZE_K(116)>; + erase-block-size = <4096>; + write-block-size = <4>; + }; + }; + }; + + wifi: wifi { + compatible = "nordic,nrf7120-wifi"; + status = "disabled"; + + wifi-max-tx-pwr-2g-dsss = <21>; + wifi-max-tx-pwr-2g-mcs0 = <16>; + wifi-max-tx-pwr-2g-mcs7 = <16>; + wifi-max-tx-pwr-5g-low-mcs0 = <13>; + wifi-max-tx-pwr-5g-low-mcs7 = <13>; + wifi-max-tx-pwr-5g-mid-mcs0 = <13>; + wifi-max-tx-pwr-5g-mid-mcs7 = <13>; + wifi-max-tx-pwr-5g-high-mcs0 = <12>; + wifi-max-tx-pwr-5g-high-mcs7 = <12>; + + wlan0: wlan0 { + compatible = "nordic,wlan"; + }; + }; +}; diff --git a/dts/vendor/nordic/nrf7120_enga_secure_peripherals.dtsi b/dts/vendor/nordic/nrf7120_enga_secure_peripherals.dtsi new file mode 100644 index 000000000000..58c6abe21099 --- /dev/null +++ b/dts/vendor/nordic/nrf7120_enga_secure_peripherals.dtsi @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * This file contains peripherals that are secure only in nRF7120 + */ + +spu00: spu@40000 { + compatible = "nordic,nrf-spu"; + reg = <0x40000 0x1000>; + interrupts = <64 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; +}; + +kmu: kmu@49000 { + compatible = "nordic,nrf-kmu"; + reg = <0x49000 0x1000>; + status = "disabled"; +}; + +spu10: spu@80000 { + compatible = "nordic,nrf-spu"; + reg = <0x80000 0x1000>; + interrupts = <128 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; +}; + +spu20: spu@c0000 { + compatible = "nordic,nrf-spu"; + reg = <0xc0000 0x1000>; + interrupts = <192 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; +}; + +spu30: spu@100000 { + compatible = "nordic,nrf-spu"; + reg = <0x100000 0x1000>; + interrupts = <256 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; +}; + +wdt30: wdt@108000 { + compatible = "nordic,nrf-wdt"; + reg = <0x108000 0x1000>; + interrupts = <264 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; +}; diff --git a/modules/hal_nordic/nrfx/CMakeLists.txt b/modules/hal_nordic/nrfx/CMakeLists.txt index 0ebc92918a3a..53537ca0ee6e 100644 --- a/modules/hal_nordic/nrfx/CMakeLists.txt +++ b/modules/hal_nordic/nrfx/CMakeLists.txt @@ -73,6 +73,11 @@ zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54LM20A_ENGA_CPUAPP NRF_APPLICATI zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54LM20A_ENGA_CPUFLPR NRF_FLPR) zephyr_compile_definitions_ifdef(CONFIG_SOC_COMPATIBLE_NRF54LM20A NRF54LM20A_ENGA_XXAA) zephyr_compile_definitions_ifdef(CONFIG_SOC_COMPATIBLE_NRF54LM20A_CPUAPP NRF_APPLICATION) +zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF7120_ENGA NRF7120_ENGA_XXAA) +zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF7120_ENGA_CPUAPP NRF_APPLICATION) +zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF7120_ENGA_CPUFLPR NRF_FLPR) +zephyr_compile_definitions_ifdef(CONFIG_SOC_COMPATIBLE_NRF7120_ENGA NRF7120_ENGA_XXAA) +zephyr_compile_definitions_ifdef(CONFIG_SOC_COMPATIBLE_NRF7120_ENGA_CPUAPP NRF_APPLICATION) zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF9120 NRF9120_XXAA) zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF9160 NRF9160_XXAA) @@ -120,6 +125,7 @@ zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_NRF54HX ${MDK_DIR}/system_nrf54h. if(CONFIG_SOC_SERIES_NRF54LX OR CONFIG_SOC_SERIES_BSIM_NRF54LX) zephyr_library_sources(${MDK_DIR}/system_nrf54l.c) endif() +zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_NRF71X ${MDK_DIR}/system_nrf7120_enga.c) zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_NRF91X ${MDK_DIR}/system_nrf91.c) zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_NRF92X ${MDK_DIR}/system_nrf92.c) @@ -225,6 +231,12 @@ if(CONFIG_SOC_NRF54L_CPUAPP_COMMON) zephyr_compile_definitions("NRF_CONFIG_CPU_FREQ_MHZ=${clock_frequency_mhz}") endif() +if(CONFIG_SOC_NRF7120_ENGA_CPUAPP) + dt_prop(clock_frequency PATH "/cpus/cpu@0" PROPERTY "clock-frequency") + math(EXPR clock_frequency_mhz "${clock_frequency} / 1000000") + zephyr_compile_definitions("NRF_CONFIG_CPU_FREQ_MHZ=${clock_frequency_mhz}") +endif() + zephyr_compile_definitions_ifdef(CONFIG_NRF_SKIP_CLOCK_CONFIG NRF_SKIP_CLOCK_CONFIGURATION) zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54LX_DISABLE_FICR_TRIMCNF NRF_DISABLE_FICR_TRIMCNF) zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54LX_SKIP_GLITCHDETECTOR_DISABLE NRF_SKIP_GLITCHDETECTOR_DISABLE) @@ -264,6 +276,8 @@ mdk_svd_ifdef(CONFIG_SOC_NRF54L15_CPUAPP nrf54l15_application.svd) mdk_svd_ifdef(CONFIG_SOC_NRF54L15_CPUFLPR nrf54l15_flpr.svd) mdk_svd_ifdef(CONFIG_SOC_NRF54LM20A_ENGA_CPUAPP nrf54lm20a_enga_application.svd) mdk_svd_ifdef(CONFIG_SOC_NRF54LM20A_ENGA_CPUFLPR nrf54lm20a_enga_flpr.svd) +mdk_svd_ifdef(CONFIG_SOC_NRF7120_ENGA_CPUAPP nrf7120_enga_application.svd) +mdk_svd_ifdef(CONFIG_SOC_NRF7120_ENGA_CPUFLPR nrf7120_enga_flpr.svd) mdk_svd_ifdef(CONFIG_SOC_NRF9120 nrf9120.svd) mdk_svd_ifdef(CONFIG_SOC_NRF9160 nrf9160.svd) mdk_svd_ifdef(CONFIG_SOC_NRF9230_ENGB_CPUAPP nrf9230_engb_application.svd) diff --git a/modules/nrf_wifi/bus/Kconfig b/modules/nrf_wifi/bus/Kconfig index 430cf3ba9ffd..b319b4ad569c 100644 --- a/modules/nrf_wifi/bus/Kconfig +++ b/modules/nrf_wifi/bus/Kconfig @@ -10,7 +10,7 @@ DT_COMPAT_NORDIC_NRF7001_QSPI := nordic,nrf7001-qspi DT_COMPAT_NORDIC_NRF7001_SPI := nordic,nrf7001-spi DT_COMPAT_NORDIC_NRF7000_QSPI := nordic,nrf7000-qspi DT_COMPAT_NORDIC_NRF7000_SPI := nordic,nrf7000-spi -DT_COMPAT_NORDIC_WIFI71 := nordic,nrf7120 +DT_COMPAT_NORDIC_WIFI71 := nordic,nrf7120-wifi menuconfig NRF70_BUSLIB bool "NRF70 Bus Library" diff --git a/modules/trusted-firmware-m/Kconfig.tfm b/modules/trusted-firmware-m/Kconfig.tfm index 36a734ad8b3e..da55ea0f7c09 100644 --- a/modules/trusted-firmware-m/Kconfig.tfm +++ b/modules/trusted-firmware-m/Kconfig.tfm @@ -29,6 +29,7 @@ config TFM_BOARD default "$(ZEPHYR_BASE)/modules/trusted-firmware-m/nordic/nrf54l15_cpuapp" if SOC_NRF54L15_CPUAPP default "$(ZEPHYR_BASE)/modules/trusted-firmware-m/nordic/nrf54l10_cpuapp" if SOC_NRF54L10_CPUAPP default "$(ZEPHYR_BASE)/modules/trusted-firmware-m/nordic/nrf54lm20a_cpuapp" if SOC_NRF54LM20A_ENGA_CPUAPP + default "$(ZEPHYR_BASE)/modules/trusted-firmware-m/nordic/nrf7120_cpuapp" if SOC_NRF7120_ENGA_CPUAPP help The board name used for building TFM. Building with TFM requires that TFM has been ported to the given board/SoC. diff --git a/modules/trusted-firmware-m/nordic/include/tfm_peripherals_config.h b/modules/trusted-firmware-m/nordic/include/tfm_peripherals_config.h index 2b50abc57ae1..4e74f537c7d6 100644 --- a/modules/trusted-firmware-m/nordic/include/tfm_peripherals_config.h +++ b/modules/trusted-firmware-m/nordic/include/tfm_peripherals_config.h @@ -37,6 +37,8 @@ extern "C" { #include #elif defined(NRF54L_SERIES) #include +#elif defined(NRF71_SERIES) + #include #else #error "Unknown device." #endif diff --git a/modules/trusted-firmware-m/nordic/nrf7120_cpuapp/CMakeLists.txt b/modules/trusted-firmware-m/nordic/nrf7120_cpuapp/CMakeLists.txt new file mode 100644 index 000000000000..a33d98b24575 --- /dev/null +++ b/modules/trusted-firmware-m/nordic/nrf7120_cpuapp/CMakeLists.txt @@ -0,0 +1,28 @@ +# +# Copyright (c) 2025, Nordic Semiconductor ASA. +# +# SPDX-License-Identifier: Apache-2.0 +# + +set(NRF_BOARD_SELECTED True) + +add_subdirectory(${Trusted\ Firmware\ M_SOURCE_DIR}/platform/ext/target/nordic_nrf/common/nrf7120 nrf7120) + +add_subdirectory(.. common) + +# Add board-specific services/include to include path for common/core code +target_include_directories(platform_s + PUBLIC + ${Trusted\ Firmware\ M_SOURCE_DIR}/platform/ext/target/nordic_nrf/nrf7120dk_nrf7120_cpuapp/services/include +) + +install(FILES ${CMAKE_CURRENT_LIST_DIR}/ns/cpuarch_ns.cmake + DESTINATION ${INSTALL_PLATFORM_NS_DIR} + RENAME cpuarch.cmake) + +install(FILES config.cmake + DESTINATION ${INSTALL_PLATFORM_NS_DIR}) + +install(DIRECTORY ${Trusted\ Firmware\ M_SOURCE_DIR}/platform/ext/target/nordic_nrf/nrf7120dk_nrf7120_cpuapp/tests + DESTINATION ${INSTALL_PLATFORM_NS_DIR} +) diff --git a/modules/trusted-firmware-m/nordic/nrf7120_cpuapp/config.cmake b/modules/trusted-firmware-m/nordic/nrf7120_cpuapp/config.cmake new file mode 100644 index 000000000000..43792218bfec --- /dev/null +++ b/modules/trusted-firmware-m/nordic/nrf7120_cpuapp/config.cmake @@ -0,0 +1,10 @@ +# +# Copyright (c) 2025, Nordic Semiconductor ASA. +# +# SPDX-License-Identifier: Apache-2.0 +# + +set(NRF_SOC_VARIANT nrf7120 CACHE STRING "nRF SoC Variant") + +include(${PLATFORM_PATH}/common/nrf7120/config.cmake) + diff --git a/modules/trusted-firmware-m/nordic/nrf7120_cpuapp/cpuarch.cmake b/modules/trusted-firmware-m/nordic/nrf7120_cpuapp/cpuarch.cmake new file mode 100644 index 000000000000..cb4f343c81fe --- /dev/null +++ b/modules/trusted-firmware-m/nordic/nrf7120_cpuapp/cpuarch.cmake @@ -0,0 +1,10 @@ +# +# Copyright (c) 2025, Nordic Semiconductor ASA. +# +# SPDX-License-Identifier: Apache-2.0 +# + +set(PLATFORM_PATH platform/ext/target/nordic_nrf) + +include(${PLATFORM_PATH}/common/nrf7120/cpuarch.cmake) + diff --git a/modules/trusted-firmware-m/nordic/nrf7120_cpuapp/ns/cpuarch_ns.cmake b/modules/trusted-firmware-m/nordic/nrf7120_cpuapp/ns/cpuarch_ns.cmake new file mode 100644 index 000000000000..d8713b887302 --- /dev/null +++ b/modules/trusted-firmware-m/nordic/nrf7120_cpuapp/ns/cpuarch_ns.cmake @@ -0,0 +1,11 @@ +# +# Copyright (c) 2025, Nordic Semiconductor ASA. +# +# SPDX-License-Identifier: Apache-2.0 +# + +set(PLATFORM_DIR ${CMAKE_CURRENT_LIST_DIR}) +set(PLATFORM_PATH ${CMAKE_CURRENT_LIST_DIR}) + +include(${CMAKE_CURRENT_LIST_DIR}/common/nrf7120/cpuarch.cmake) + diff --git a/soc/nordic/Kconfig b/soc/nordic/Kconfig index df4bba2e1ce1..b40280aa9271 100644 --- a/soc/nordic/Kconfig +++ b/soc/nordic/Kconfig @@ -43,6 +43,12 @@ config SOC_COMPATIBLE_NRF54LM20A config SOC_COMPATIBLE_NRF54LM20A_CPUAPP bool +config SOC_COMPATIBLE_NRF7120 + bool + +config SOC_COMPATIBLE_NRF7120_CPUAPP + bool + config SOC_FAMILY_NORDIC_NRF select SOC_COMPATIBLE_NRF select SOC_RESET_HOOK diff --git a/soc/nordic/Kconfig.soc b/soc/nordic/Kconfig.soc index 6851c25becf1..b6ccdf631532 100644 --- a/soc/nordic/Kconfig.soc +++ b/soc/nordic/Kconfig.soc @@ -13,6 +13,7 @@ config SOC_SERIES default "nrf53" if SOC_SERIES_NRF53X default "nrf54h" if SOC_SERIES_NRF54HX default "nrf54l" if SOC_SERIES_NRF54LX + default "nrf71" if SOC_SERIES_NRF71X default "nrf91" if SOC_SERIES_NRF91X default "nrf92" if SOC_SERIES_NRF92X @@ -51,6 +52,12 @@ config SOC_SERIES_NRF54LX help Nordic Semiconductor nRF54L series MCU +config SOC_SERIES_NRF71X + bool + select SOC_FAMILY_NORDIC_NRF + help + Nordic Semiconductor nRF71 series MCU + config SOC_SERIES_NRF91X bool select SOC_FAMILY_NORDIC_NRF diff --git a/soc/nordic/nrf71/CMakeLists.txt b/soc/nordic/nrf71/CMakeLists.txt new file mode 100644 index 000000000000..b7e66a6ff30f --- /dev/null +++ b/soc/nordic/nrf71/CMakeLists.txt @@ -0,0 +1,10 @@ +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library_sources(soc.c) + +zephyr_include_directories(.) + +# Ensure that image size aligns with 16 bytes so that MRAMC finalizes all writes +# for the image correctly +zephyr_linker_sources(SECTIONS SORT_KEY zzz_place_align_at_end align.ld) diff --git a/soc/nordic/nrf71/Kconfig b/soc/nordic/nrf71/Kconfig new file mode 100644 index 000000000000..de219db6a638 --- /dev/null +++ b/soc/nordic/nrf71/Kconfig @@ -0,0 +1,27 @@ +# Nordic Semiconductor nRF71 MCU line + +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_NRF71X + select HAS_NRFX + select HAS_NORDIC_DRIVERS + select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE + select SOC_EARLY_INIT_HOOK + select SOC_RESET_HOOK + select NRF_PLATFORM_LUMOS + +config SOC_NRF7120_ENGA_CPUAPP + select ARM + select ARMV8_M_DSP + select CPU_CORTEX_M33 + select CPU_HAS_ARM_MPU + select CPU_HAS_ICACHE + select CPU_HAS_ARM_SAU + select CPU_HAS_FPU + select HAS_HW_NRF_RADIO_IEEE802154 + select HAS_POWEROFF + select HAS_SWO + +config SOC_NRF7120_ENGA_CPUFLPR + select RISCV_CORE_NORDIC_VPR diff --git a/soc/nordic/nrf71/Kconfig.defconfig b/soc/nordic/nrf71/Kconfig.defconfig new file mode 100644 index 000000000000..3fab30db5203 --- /dev/null +++ b/soc/nordic/nrf71/Kconfig.defconfig @@ -0,0 +1,45 @@ +# Nordic Semiconductor nRF71 MCU line + +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_NRF71X + +rsource "Kconfig.defconfig.nrf71*" + +if ARM + +config CORTEX_M_SYSTICK + default !NRF_GRTC_TIMER + +config CACHE_NRF_CACHE + default y if EXTERNAL_CACHE + +config CACHE_MANAGEMENT + default y + +choice CACHE_TYPE + default EXTERNAL_CACHE +endchoice + +endif # ARM + +if RISCV + +DT_CHOSEN_Z_SRAM = zephyr,sram +DT_CHOSEN_Z_CODE = zephyr,code-partition + +config BUILD_OUTPUT_ADJUST_LMA + depends on !XIP + default "$(dt_chosen_partition_addr_hex,$(DT_CHOSEN_Z_CODE)) - \ + $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_SRAM))" + +endif # RISCV + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_nodelabel_int_prop,grtc,clock-frequency) if NRF_GRTC_TIMER + +config MSPI_DW_DDR + default n + +endif # SOC_SERIES_NRF71X diff --git a/soc/nordic/nrf71/Kconfig.defconfig.nrf7120_enga_cpuapp b/soc/nordic/nrf71/Kconfig.defconfig.nrf7120_enga_cpuapp new file mode 100644 index 000000000000..c3d02aa5e6bf --- /dev/null +++ b/soc/nordic/nrf71/Kconfig.defconfig.nrf7120_enga_cpuapp @@ -0,0 +1,11 @@ +# Nordic Semiconductor nRF7120 MCU + +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if SOC_NRF7120_ENGA_CPUAPP + +config NUM_IRQS + default 293 + +endif # SOC_NRF7120_ENGA_CPUAPP diff --git a/soc/nordic/nrf71/Kconfig.defconfig.nrf7120_enga_cpuflpr b/soc/nordic/nrf71/Kconfig.defconfig.nrf7120_enga_cpuflpr new file mode 100644 index 000000000000..e1686995f66b --- /dev/null +++ b/soc/nordic/nrf71/Kconfig.defconfig.nrf7120_enga_cpuflpr @@ -0,0 +1,15 @@ +# Nordic Semiconductor nRF7120 MCU + +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if SOC_NRF7120_ENGA_CPUFLPR + +config NUM_IRQS + default 293 + +# As FLPR has limited memory most of tests does not fit with asserts enabled. +config ASSERT + default n + +endif # SOC_NRF7120_ENGA_CPUFLPR diff --git a/soc/nordic/nrf71/Kconfig.soc b/soc/nordic/nrf71/Kconfig.soc new file mode 100644 index 000000000000..259080326b9c --- /dev/null +++ b/soc/nordic/nrf71/Kconfig.soc @@ -0,0 +1,31 @@ +# Nordic Semiconductor nRF71 MCU line + +# Copyright (c) 2025 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config SOC_NRF7120 + bool + select SOC_SERIES_NRF71X + help + NRF7120 + +config SOC_NRF7120_ENGA + bool + select SOC_NRF7120 + help + NRF7120 ENGA + +config SOC_NRF7120_ENGA_CPUAPP + bool + select SOC_NRF7120_ENGA + help + NRF7120 ENGA CPUAPP + +config SOC_NRF7120_ENGA_CPUFLPR + bool + select SOC_NRF7120_ENGA + help + NRF7120 ENGA CPUFLPR + +config SOC + default "nrf7120" if SOC_NRF7120 diff --git a/soc/nordic/nrf71/align.ld b/soc/nordic/nrf71/align.ld new file mode 100644 index 000000000000..4fa606c1d658 --- /dev/null +++ b/soc/nordic/nrf71/align.ld @@ -0,0 +1,10 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA. + * SPDX-License-Identifier: Apache-2.0 + */ + +SECTION_PROLOGUE(.align16,,) +{ + . = (ALIGN(16) > 0 ? ALIGN(16) : 16) - 1; + BYTE(0); +} GROUP_LINK_IN(ROMABLE_REGION) diff --git a/soc/nordic/nrf71/soc.c b/soc/nordic/nrf71/soc.c new file mode 100644 index 000000000000..6d20f038429c --- /dev/null +++ b/soc/nordic/nrf71/soc.c @@ -0,0 +1,212 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief System/hardware module for Nordic Semiconductor nRF71 family processor + * + * This module provides routines to initialize and support board-level hardware + * for the Nordic Semiconductor nRF71 family processor. + */ + +#ifdef __NRF_TFM__ +#include +#endif + +#include +#include +#include +#include + +#ifndef __NRF_TFM__ +#include +#endif + +#if defined(NRF_APPLICATION) +#include +#include +#endif + +#include +#include + +#include +#include +#include + +LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL); + +#define LFXO_NODE DT_NODELABEL(lfxo) + +#if !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) +/* Copied from TF-M native driver */ +struct mpc_region_override { + nrf_mpc_override_config_t config; + nrf_owner_t owner_id; + uintptr_t start_address; + uintptr_t endaddr; + uint32_t perm; + uint32_t permmask; + size_t index; +}; + +static void mpc_configure_override(NRF_MPC_Type *mpc, struct mpc_region_override *override) +{ + nrf_mpc_override_startaddr_set(mpc, override->index, override->start_address); + nrf_mpc_override_endaddr_set(mpc, override->index, override->endaddr); + nrf_mpc_override_perm_set(mpc, override->index, override->perm); + nrf_mpc_override_permmask_set(mpc, override->index, override->permmask); +#if defined(NRF_MPC_HAS_OVERRIDE_OWNERID) && NRF_MPC_HAS_OVERRIDE_OWNERID + nrf_mpc_override_ownerid_set(mpc, override->index, override->owner_id); +#endif + nrf_mpc_override_config_set(mpc, override->index, &override->config); +} + +/* + * Configure the override struct with reasonable defaults. This includes: + * + * Use a slave number of 0 to avoid redirecting bus transactions from + * one slave to another. + * + * Lock the override to prevent the code that follows from tampering + * with the configuration. + * + * Enable the override so it takes effect. + * + * Indicate that secdom is not enabled as this driver is not used on + * platforms with secdom. + */ +static void init_mpc_region_override(struct mpc_region_override *override) +{ + *override = (struct mpc_region_override){ + .config = + (nrf_mpc_override_config_t){ + .slave_number = 0, + .lock = true, + .enable = true, + .secdom_enable = false, + .secure_mask = false, + }, + /* 0-NS R,W,X =1 */ + .perm = 0x7, + .permmask = 0xF, + .owner_id = 0, + }; +} + +/** + * Return the SPU instance that can be used to configure the + * peripheral at the given base address. + */ +static inline NRF_SPU_Type *spu_instance_from_peripheral_addr(uint32_t peripheral_addr) +{ + /* See the SPU chapter in the IPS for how this is calculated */ + + uint32_t apb_bus_number = peripheral_addr & 0x00FC0000; + + return (NRF_SPU_Type *)(0x50000000 | apb_bus_number); +} + +/* End of TF-M native driver */ + +void wifi_mpc_configuration(void) +{ + struct mpc_region_override override; + uint32_t index = 0; + + /* Make RAM_00/01/02 (AMBIX00 + AMBIX03) accessible to the Wi-Fi domain*/ + init_mpc_region_override(&override); + override.start_address = 0x20000000; + override.endaddr = 0x200E0000; + override.index = index++; + mpc_configure_override(NRF_MPC00, &override); + + /* MRAM MPC overrides for wifi */ + init_mpc_region_override(&override); + override.start_address = 0x00000000; + override.endaddr = 0x01000000; + override.index = index++; + mpc_configure_override(NRF_MPC00, &override); + + /* Make RAM_02 (AMBIX03) accessible to the Wi-Fi domain for IPC */ + init_mpc_region_override(&override); + override.start_address = 0x200C0000; + override.endaddr = 0x200E0000; + override.index = 0; + mpc_configure_override(NRF_MPC03, &override); +} + +void grtc_configuration(void) +{ + /* Split security configuration to let Wi-Fi access GRTC */ + nrf_spu_feature_secattr_set(NRF_SPU20, NRF_SPU_FEATURE_GRTC_CC, 15, 0, 0); + nrf_spu_feature_secattr_set(NRF_SPU20, NRF_SPU_FEATURE_GRTC_CC, 14, 0, 0); + nrf_spu_feature_secattr_set(NRF_SPU20, NRF_SPU_FEATURE_GRTC_INTERRUPT, 4, 0, 0); + nrf_spu_feature_secattr_set(NRF_SPU20, NRF_SPU_FEATURE_GRTC_INTERRUPT, 5, 0, 0); + nrf_spu_feature_secattr_set(NRF_SPU20, NRF_SPU_FEATURE_GRTC_SYSCOUNTER, 0, 0, 0); +} +#endif /* CONFIG_TRUSTED_EXECUTION_NONSECURE */ + +#if !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) || defined(__NRF_TFM__) +void wifi_setup(void) +{ +#if !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) + /* Skip for tf-m, configuration exist in target_cfg_71.c */ + wifi_mpc_configuration(); + + grtc_configuration(); + +#endif + + /* Kickstart the LMAC processor */ + NRF_WIFICORE_LRCCONF_LRC0->POWERON = + (LRCCONF_POWERON_MAIN_AlwaysOn << LRCCONF_POWERON_MAIN_Pos); + NRF_WIFICORE_LMAC_VPR->INITPC = NRF_WICR->RESERVED[0]; + NRF_WIFICORE_LMAC_VPR->CPURUN = (VPR_CPURUN_EN_Running << VPR_CPURUN_EN_Pos); +} +#endif + +void soc_early_init_hook(void) +{ +#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_pwr_antswc) + *(volatile uint32_t *)PWR_ANTSWC_REG |= PWR_ANTSWC_ENABLE; +#endif + /* Update the SystemCoreClock global variable with current core clock + * retrieved from hardware state. + */ +#if !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) || defined(__NRF_TFM__) + /* Currently not supported for non-secure */ + SystemCoreClockUpdate(); + wifi_setup(); + + /* Configure LFXO capacitive load if internal load capacitors are used */ +#if DT_ENUM_HAS_VALUE(LFXO_NODE, load_capacitors, internal) + nrf_lfxo_cload_set(NRF_LFXO, + (uint8_t)(DT_PROP(LFXO_NODE, load_capacitance_femtofarad) / 1000)); +#endif +#endif + +#ifdef __NRF_TFM__ + /* TF-M enables the instruction cache from target_cfg_71.c, so we + * don't need to enable it here. + */ +#else + /* Enable ICACHE */ + sys_cache_instr_enable(); +#endif +} + +void arch_busy_wait(uint32_t time_us) +{ + nrfx_coredep_delay_us(time_us); +} + +#ifdef CONFIG_SOC_RESET_HOOK +void soc_reset_hook(void) +{ + SystemInit(); +} +#endif diff --git a/soc/nordic/nrf71/soc.h b/soc/nordic/nrf71/soc.h new file mode 100644 index 000000000000..28ff81c8265e --- /dev/null +++ b/soc/nordic/nrf71/soc.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file SoC configuration macros for the Nordic Semiconductor NRF71 family processors. + */ + +#ifndef _NORDICSEMI_NRF71_SOC_H_ +#define _NORDICSEMI_NRF71_SOC_H_ + +#include + +#define FLASH_PAGE_ERASE_MAX_TIME_US 42000UL +#define FLASH_PAGE_MAX_CNT 381UL + +#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_pwr_antswc) + +#if defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) +#define PWR_ANTSWC_REG (0x4010F780UL) +#else /* CONFIG_TRUSTED_EXECUTION_NONSECURE */ +#define PWR_ANTSWC_REG (0x5010F780UL) +#endif /* CONFIG_TRUSTED_EXECUTION_NONSECURE */ + +#define PWR_ANTSWC_ENABLE (0x3UL) +#endif /* DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_pwr_antswc) */ + +#endif /* _NORDICSEMI_NRF71_SOC_H_ */ diff --git a/soc/nordic/soc.yml b/soc/nordic/soc.yml index c6f33f5866b0..aab70b717b11 100644 --- a/soc/nordic/soc.yml +++ b/soc/nordic/soc.yml @@ -45,6 +45,12 @@ family: - name: cpurad - name: cpuppr - name: cpuflpr + - name: nrf71 + socs: + - name: nrf7120 + cpuclusters: + - name: cpuapp + - name: cpuflpr - name: nrf91 socs: - name: nrf9131 @@ -248,6 +254,10 @@ runners: - nrf54h20/cpurad - nrf54h20/cpuppr - nrf54h20/cpuflpr + - qualifiers: + - nrf7120/cpuapp + - nrf7120/cpuapp/ns + - nrf7120/cpuflpr - qualifiers: - nrf9280/cpuapp - nrf9280/cpurad diff --git a/west.yml b/west.yml index 26335c8499e0..140fc3e5a3ff 100644 --- a/west.yml +++ b/west.yml @@ -364,7 +364,7 @@ manifest: groups: - tee - name: trusted-firmware-m - revision: c2f9edc77f72838e7d6f5f9c0b95e4318ddfced1 + revision: pull/165/head path: modules/tee/tf-m/trusted-firmware-m groups: - tee