diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index 2018a6ed356b..f689445af543 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -5803,20 +5803,6 @@ West: labels: - "area: Debugging" -"West project: sof": - status: maintained - maintainers: - - kv2019i - collaborators: - - andyross - - nashif - - lyakh - - lgirdwood - files: - - modules/Kconfig.sof - labels: - - "area: Audio" - "West project: tf-m-tests": status: maintained maintainers: diff --git a/boards/adi/max32658evkit/Kconfig.defconfig b/boards/adi/max32658evkit/Kconfig.defconfig new file mode 100644 index 000000000000..8235ba516f2b --- /dev/null +++ b/boards/adi/max32658evkit/Kconfig.defconfig @@ -0,0 +1,48 @@ +# Copyright (c) 2024-2025 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MAX32658EVKIT + +# Code Partition: +# +# For the secure version of the board the firmware is linked at the beginning +# of the flash, or into the code-partition defined in DT if it is intended to +# be loaded by MCUboot. If the secure firmware is to be combined with a non- +# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always +# be restricted to the size of its code partition. +# +# For the non-secure version of the board, the firmware +# must be linked into the code-partition (non-secure) defined in DT, regardless. +# Apply this configuration below by setting the Kconfig symbols used by +# the linker according to the information extracted from DT partitions. + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +if BOARD_MAX32658EVKIT_MAX32658_NS + +config FLASH_LOAD_OFFSET + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +# MAX32658 has one UART interface, +# It can be used either on TFM or Zephyr +# Enabling debug (TFM_SPM_LOG_LEVEL || TFM_PARTITION_LOG_LEVEL) will transfer it to the TFM side +# Disabling TFM debug will transfer it to the Zephyr side. + +choice TFM_SPM_LOG_LEVEL + default TFM_SPM_LOG_LEVEL_SILENCE +endchoice + +choice TFM_PARTITION_LOG_LEVEL + default TFM_PARTITION_LOG_LEVEL_SILENCE +endchoice + +endif # BOARD_MAX32658EVKIT_MAX32658_NS + +config I3C + default y if ADXL367 + +endif # BOARD_MAX32658EVKIT diff --git a/boards/adi/max32658evkit/Kconfig.max32658evkit b/boards/adi/max32658evkit/Kconfig.max32658evkit new file mode 100644 index 000000000000..d7b695e47587 --- /dev/null +++ b/boards/adi/max32658evkit/Kconfig.max32658evkit @@ -0,0 +1,6 @@ +# Copyright (c) 2024-2025 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MAX32658EVKIT + select SOC_MAX32658 if BOARD_MAX32658EVKIT_MAX32658 || \ + BOARD_MAX32658EVKIT_MAX32658_NS diff --git a/boards/adi/max32658evkit/board.cmake b/boards/adi/max32658evkit/board.cmake new file mode 100644 index 000000000000..32e6669b7018 --- /dev/null +++ b/boards/adi/max32658evkit/board.cmake @@ -0,0 +1,12 @@ +# Copyright (c) 2024-2025 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_BOARD_MAX32658EVKIT_MAX32658_NS) + set_property(TARGET runners_yaml_props_target PROPERTY hex_file tfm_merged.hex) +endif() + +board_runner_args(jlink "--device=MAX32658" "--reset-after-load") + +include(${ZEPHYR_BASE}/boards/common/openocd-adi-max32.boards.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/adi/max32658evkit/board.yml b/boards/adi/max32658evkit/board.yml new file mode 100644 index 000000000000..07a2bd79226d --- /dev/null +++ b/boards/adi/max32658evkit/board.yml @@ -0,0 +1,10 @@ +# Copyright (c) 2024-2025 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board: + name: max32658evkit + vendor: adi + socs: + - name: max32658 + variants: + - name: "ns" diff --git a/boards/adi/max32658evkit/doc/img/max32658evkit.webp b/boards/adi/max32658evkit/doc/img/max32658evkit.webp new file mode 100644 index 000000000000..7bbf5b668eef Binary files /dev/null and b/boards/adi/max32658evkit/doc/img/max32658evkit.webp differ diff --git a/boards/adi/max32658evkit/doc/index.rst b/boards/adi/max32658evkit/doc/index.rst new file mode 100644 index 000000000000..cd0999bac46b --- /dev/null +++ b/boards/adi/max32658evkit/doc/index.rst @@ -0,0 +1,571 @@ +.. zephyr:board:: max32658evkit + +Overview +******** + +The MAX32658 microcontroller (MCU) is an advanced system-on-chip (SoC) +featuring an Arm® Cortex®-M33 core with single-precision floating point unit (FPU) +with digital signal processing (DSP) instructions, large flash and SRAM memories, +and the latest generation Bluetooth® 5.4 Low Energy (LE) radio. +The nano-power modes increase battery life substantially. + +The MAX32658 is qualified to operate at a temperature range of -20°C to +85°C. +Bluetooth 5.4 LE radio supports Mesh, long-range (coded), and high-throughput modes. +A cryptographic toolbox (CTB) provides advanced root of trust security features, +including an Advanced Encryption Standard (AES) Engine, TRNG, and secure boot. +TrustZone is also included in the M33 Core. +Many high-speed interfaces are supported on the device, including multiple SPI, UART, +and I3C/I2C serial interfaces. +All interfaces support efficient DMA-driven transfers between peripheral and memory. + +The Zephyr port is running on the MAX32658 MCU. + +Hardware +******** + +- MAX32658 MCU: + + - Arm Cortex-M33 CPU with TrustZone® and FPU + - Single 1.8V Supply + - 50MHz Low Power Oscillator + - External Crystal Support + + - 32MHz required for BLE + + - 1MB Internal Flash with ECC + - 256kB Internal SRAM + - 8kB Cache + - 32.768kHz RTC external crystal + + - Typical Electrical Characteristics + + - ACTIVE: 50μA/MHz Arm Cortex-M33 Running Coremark (50MHz) + + - Bluetooth 5.4 LE Radio + + - Rx Sensitivity: -96dBm; Tx Power: +4.5dBm + - 15mW Tx Power at 0dBm at 1.5Vin + - 14mW Rx Power at 1.5Vin + - Single-Ended Antenna Connection (50Ω) + - Supports 802.15.4, and LE Audio + - High-Throughput (2Mbps) Mode + - Long-Range (125kbps and 500kbps) Modes + + - Optimal Peripheral Mix Provides Platform Scalability + + - 2 DMA Controllers (Secure and non-Secure) + - One SPI Controller/Peripheral + - One I2C/I3C + - 1 Low-Power UART (LPUART) + - Six 32-Bit Low Power Timers with PWM + - 14 Configurable GPIO with Internal Pullup/Pulldown Resistors + + - Cryptographic Tool Box (CTB) for IP/Data Security + + - True Random Number Generator (TRNG) + - AES-128/192/256 + - Unique ID + + - Secure Boot ROM + + +Supported Features +================== + +.. zephyr:board-supported-hw:: + + +Connections and IOs +=================== + ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| Name | Name | Settings | Description | ++===========+===============+===============+==================================================================================================+ +| JP1 | F5 EN | | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects the 1.8V LDO output used to power supply input F5. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects the 1.8V LDO output used from power supply input F5. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP2 | VDD18 EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects system power to the MAX32658 by connecting VDD18 to VSYS_OUT. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects system power from the MAX32658 by disconnecting VDD18 from VSYS_OUT. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP3 | VLDO EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects LDO output to VSYS_IN. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects LDO output from VSYS_IN. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP4 | E5 EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects the 1.8V LDO output used to power supply input E5. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects the 1.8V LDO output used from power supply input E5. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP5 | VTREF EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects a reference voltage to the OBD circuit. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects a reference voltage from the OBD circuit. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP6 | OBD VBUS EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Enables the OBD by connecting OBD_VBUS to VBUS. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disables the OBD by disconnecting OBD_VBUS from VBUS. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| J7 | VSYS EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects system power to all peripherals by connecting VSYS to VSYS_OUT. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects system power to all peripherals by disconnecting VSYS from VSYS_OUT. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP7 | ACC VS EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Enables the accelerometer by connecting its supply voltage pin VS to VSYS. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disables the accelerometer by disconnecting its supply voltage pin VS from VSYS. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP8 | ACC VDD EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Enables the accelerometer by connecting its VDDIO pin to VSYS. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disables the accelerometer by disconnecting its VDDIO pin from VSYS. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP9 | ACC I2C EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Accelerometer SDA Pin is connected to MAX32658 I2C0_SDA. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Accelerometer SDA Pin is disconnected from MAX32658 I2C0_SDA. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP10 | ACC I2C EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Accelerometer SCL Pin is connected to MAX32658 I2C0_SCL. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Accelerometer SCL Pin is disconnected from MAX32658 I2C0_SCL. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP11 | BYP MAG SW | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Bypass Magnetic Switch. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Enables magnetic switch. The output of the switch is controlled by the AFE pin. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP12 | LOCK RSTN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | AFE Lock Pin is connected to MAX32658 RSTN pin. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | AFE Lock Pin is disconnected from MAX32658 RSTN pin. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP13 | LATCH CTRL | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects the AFE (LOCK) to the magnetic switch (OUTPUT LATCH CONTROL). | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 2-3 | | | Connects the AFE (WAKE) to the magnetic switch (OUTPUT LATCH CONTROL). | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP14 | AFE EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Enables the AFE (VBAT) by connecting it to VSYS. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disables the AFE (VBAT) by disconnecting it from VSYS. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP15 | AFE SPI EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | AFE CSB is connected to MAX32658 SPI0_CS0. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 3-4 | | | AFE SDI is connected to MAX32658 SPI0_MOSI. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 5-6 | | | AFE SCLK is connected to MAX32658 SPI0_SCK. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 7-8 | | | AFE SDO is connected to MAX32658 SPI0_MISO. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 9-10 | | | AFE INTB is connected to MAX32658 P0.7. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 11-12 | | | AFE GPIO2 is connected to MAX32658 P0.8. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open All | | | Disconnect SPI Interface from MAX32658. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP16 | I2C PU EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Enable SCL PU resistor. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disable SCL PU resistor. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP17 | I2C PU EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Enable SDA PU resistor. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disable SDA PU resistor. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP18 | OBD SWD EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 3-4 | | | OBD SWDIO is connected to the MAX32658 SWDIO. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 5-6 | | | OBD SWCLK is connected to the MAX32658 SWCLK. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 7-8 | | | OBD JTAG TDO Enable Jumper (It's not used on MAX32658). | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 9-10 | | | OBD JTAG TDI Enable Jumper (It's not used on MAX32658). | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 11-12 | | | OBD RSTN is connected to the MAX32658 RSTN. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 13-14 | | | OBD JTAG TRST Enable Jumper (It's not used on MAX32658). | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open All | | | Disable OBD SWD Connection from MAX32658. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP19 | OBD VCOM EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 3-4 | | | OBD VCOM TXD is connected VCOM EN RX Jumper. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 5-6 | | | OBD VCOM RXD is connected VCOM EN TX Jumper. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 7-8 | | | OBD VCOM CTS Enable Jumper (It's not used on MAX32658). | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 9-10 | | | OBD VCOM RTS Enable Jumper (It's not used on MAX32658). | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disable OBD VCOM connection from MAX32658. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP20 | VCOM EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects OBD VCOM RXD to the MAX32658 UART0A_TX. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects OBD VCOM RXD from the MAX32658 UART0A_TX. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP21 | VCOM EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects OBD VCOM TXD to the MAX32658 UART0A_RX. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects OBD VCOM TXD from the MAX32658 UART0A_RX. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP22 | EXT SWD EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects EXT SWD Connector Data Signals to the MAX32658 SWDIO pin. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects EXT SWD Connector Data Signals from the MAX32658 SWDIO pin. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP23 | EXT SWD EN | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Connects EXT SWD Connector Clock Signals to the MAX32658 SWDCLK pin. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | Open | | | Disconnects EXT SWD Connector Clock Signals from the MAX32658 SWDCLK pin. | | +| | | +-----------+ | +----------------------------------------------------------------------------------+ | +| | | | | ++-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ + + +Zephyr board options +******************** + +The MAX32658 microcontroller (MCU) is an advanced system-on-chip (SoC) +featuring an ARM Cortex-M33 architecture that provides Trustzone technology +which allow define secure and non-secure application. +Zephyr provides support for building for both Secure (S) and Non-Secure (NS) firmware. + +The BOARD options are summarized below: + ++-------------------------------+-------------------------------------------+ +| BOARD | Description | ++===============================+===========================================+ +| max32658evkit/max32658 | For building Trust Zone Disabled firmware | ++-------------------------------+-------------------------------------------+ +| max32658evkit/max32658/ns | Building with TF-M (includes NS+S images) | ++-------------------------------+-------------------------------------------+ + + +BOARD: max32658evkit/max32658 +============================= + +Build the zephyr app for ``max32658evkit/max32658`` board target will generate secure firmware +for zephyr. In this configuration 960KB of flash is used to store the code and 64KB +is used for storage section. In this mode tf-m is off and secure mode flag is on +(:kconfig:option:`CONFIG_TRUSTED_EXECUTION_SECURE` to ``y`` and +:kconfig:option:`CONFIG_BUILD_WITH_TFM` to ``n``) + ++----------+------------------+---------------------------------+ +| Name | Address[Size] | Comment | ++==========+==================+=================================+ +| slot0 | 0x1000000[960k] | Secure zephyr image | ++----------+------------------+---------------------------------+ +| storage | 0x10f0000[64k] | File system, persistent storage | ++----------+------------------+---------------------------------+ + +Here are the instructions to build zephyr with a secure configuration, +using :zephyr:code-sample:`blinky` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky/ + :board: max32658evkit/max32658 + :goals: build + + +BOARD: max32658evkit/max32658/ns +================================ + +The ``max32658evkit/max32658/ns`` board target is used to build the secure firmware +image using TF-M (:kconfig:option:`CONFIG_BUILD_WITH_TFM` to ``y``) and +the non-secure firmware image using Zephyr +(:kconfig:option:`CONFIG_TRUSTED_EXECUTION_NONSECURE` to ``y``). + +Here are the instructions to build zephyr with a non-secure configuration, +using :zephyr:code-sample:`blinky` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky/ + :board: max32658evkit/max32658/ns + :goals: build + +The above command will: + * Build a bootloader image (MCUboot) + * Build a TF-M (secure) firmware image + * Build Zephyr application as non-secure firmware image + * Merge them as ``tfm_merged.hex`` which contain all images. + + +Note: + +Zephyr build TF-M with :kconfig:option:`CONFIG_TFM_PROFILE_TYPE_NOT_SET` mode +that meet most use case configuration especially for BLE related applications. +if TF-M small profile meet your application requirement you can set TF-M profile as small +:kconfig:option:`CONFIG_TFM_PROFILE_TYPE_SMALL` to ``y`` to decrease TF-M RAM and flash use. + + +Memory mappings +--------------- + +MAX32658 1MB flash and 256KB RAM split to define section for MCUBoot, +TF-M (S), Zephyr (NS) and storage that used for secure services and configurations. +Default layout of MAX32658 is listed in below table. + ++----------+------------------+---------------------------------+ +| Name | Address[Size] | Comment | ++==========+==================+=================================+ +| boot | 0x1000000[64K] | MCU Bootloader | ++----------+------------------+---------------------------------+ +| slot0 | 0x1010000[320k] | Secure image slot0 (TF-M) | ++----------+------------------+---------------------------------+ +| slot0_ns | 0x1060000[576k] | Non-secure image slot0 (Zephyr) | ++----------+------------------+---------------------------------+ +| slot1 | 0x10F0000[0k] | Updates slot0 image | ++----------+------------------+---------------------------------+ +| slot1_ns | 0x10F0000[0k] | Updates slot0_ns image | ++----------+------------------+---------------------------------+ +| storage | 0x10f0000[64k] | Persistent storage | ++----------+------------------+---------------------------------+ + + ++----------------+------------------+-------------------+ +| RAM | Address[Size] | Comment | ++================+==================+===================+ +| secure_ram | 0x20000000[64k] | Secure memory | ++----------------+------------------+-------------------+ +| non_secure_ram | 0x20010000[192k] | Non-Secure memory | ++----------------+------------------+-------------------+ + + +Flash memory layout are defines both on zephyr board file and `Trusted Firmware M`_ (TF-M) project +these definition shall be match. Zephyr defines it in +:zephyr_file:`boards/adi/max32658evkit/max32658evkit_max32658_common.dtsi` +file under flash section. TF-M project define them in +../modules/tee/tf-m/trusted-firmware-m/platform/ext/target/adi/max32657/partition/flash_layout.h file.` +If you would like to update flash region for your application you shall update related section in +these files. + +Additionally if firmware update feature requires slot1 and slot1_ns section need to be +defined. On default the section size set as 0 due to firmware update not requires on default. + + +Peripherals and Memory Ownership +-------------------------------- + +The ARM Security Extensions model allows system developers to partition device hardware and +software resources, so that they exist in either the Secure world for the security subsystem, +or the Normal world for everything else. Correct system design can ensure that no Secure world +assets can be accessed from the Normal world. A Secure design places all sensitive resources +in the Secure world, and ideally has robust software running that can protect assets against +a wide range of possible software attacks (`1`_). + +MPC (Memory Protection Controller) and PPC (Peripheral Protection Controller) are allow to +protect memory and peripheral. Incase of need peripheral and flash ownership can be updated in +../modules/tee/tf-m/trusted-firmware-m/platform/ext/target/adi/max32657/s_ns_access.cmake` +file by updating cmake flags to ON/OFF. + +As an example for below configuration TRNG, SRAM_0 and SRAM_1 is not going to be accessible +by non-secure. All others is going to be accessible by NS world. + +.. code-block:: + + set(ADI_NS_PRPH_GCR ON CACHE BOOL "") + set(ADI_NS_PRPH_SIR ON CACHE BOOL "") + set(ADI_NS_PRPH_FCR ON CACHE BOOL "") + set(ADI_NS_PRPH_WDT ON CACHE BOOL "") + set(ADI_NS_PRPH_AES OFF CACHE BOOL "") + set(ADI_NS_PRPH_AESKEY OFF CACHE BOOL "") + set(ADI_NS_PRPH_CRC ON CACHE BOOL "") + set(ADI_NS_PRPH_GPIO0 ON CACHE BOOL "") + set(ADI_NS_PRPH_TIMER0 ON CACHE BOOL "") + set(ADI_NS_PRPH_TIMER1 ON CACHE BOOL "") + set(ADI_NS_PRPH_TIMER2 ON CACHE BOOL "") + set(ADI_NS_PRPH_TIMER3 ON CACHE BOOL "") + set(ADI_NS_PRPH_TIMER4 ON CACHE BOOL "") + set(ADI_NS_PRPH_TIMER5 ON CACHE BOOL "") + set(ADI_NS_PRPH_I3C ON CACHE BOOL "") + set(ADI_NS_PRPH_UART ON CACHE BOOL "") + set(ADI_NS_PRPH_SPI ON CACHE BOOL "") + set(ADI_NS_PRPH_TRNG OFF CACHE BOOL "") + set(ADI_NS_PRPH_BTLE_DBB ON CACHE BOOL "") + set(ADI_NS_PRPH_BTLE_RFFE ON CACHE BOOL "") + set(ADI_NS_PRPH_RSTZ ON CACHE BOOL "") + set(ADI_NS_PRPH_BOOST ON CACHE BOOL "") + set(ADI_NS_PRPH_BBSIR ON CACHE BOOL "") + set(ADI_NS_PRPH_BBFCR ON CACHE BOOL "") + set(ADI_NS_PRPH_RTC ON CACHE BOOL "") + set(ADI_NS_PRPH_WUT0 ON CACHE BOOL "") + set(ADI_NS_PRPH_WUT1 ON CACHE BOOL "") + set(ADI_NS_PRPH_PWR ON CACHE BOOL "") + set(ADI_NS_PRPH_MCR ON CACHE BOOL "") + + # SRAMs + set(ADI_NS_SRAM_0 OFF CACHE BOOL "Size: 32KB") + set(ADI_NS_SRAM_1 OFF CACHE BOOL "Size: 32KB") + set(ADI_NS_SRAM_2 ON CACHE BOOL "Size: 64KB") + set(ADI_NS_SRAM_3 ON CACHE BOOL "Size: 64KB") + set(ADI_NS_SRAM_4 ON CACHE BOOL "Size: 64KB") + + # Ramfuncs section size + set(ADI_S_RAM_CODE_SIZE "0x800" CACHE STRING "Default: 2KB") + + # Flash: BL2, TFM and Zephyr are contiguous sections. + set(ADI_FLASH_AREA_BL2_SIZE "0x10000" CACHE STRING "Default: 64KB") + set(ADI_FLASH_S_PARTITION_SIZE "0x50000" CACHE STRING "Default: 320KB") + set(ADI_FLASH_NS_PARTITION_SIZE "0x90000" CACHE STRING "Default: 576KB") + set(ADI_FLASH_PS_AREA_SIZE "0x4000" CACHE STRING "Default: 16KB") + set(ADI_FLASH_ITS_AREA_SIZE "0x4000" CACHE STRING "Default: 16KB") + + # + # Allow user set S-NS resources ownership by overlay file + # + if(EXISTS "${CMAKE_BINARY_DIR}/../../s_ns_access_overlay.cmake") + include(${CMAKE_BINARY_DIR}/../../s_ns_access_overlay.cmake) + endif() + + +As an alternative method (which recommended) user can configurate ownership peripheral by +an cmake overlay file too without touching TF-M source files. For this path +create ``s_ns_access_overlay.cmake`` file under your project root folder and put peripheral/memory +you would like to be accessible by secure world. + +As an example if below configuration files been put in the ``s_ns_access_overlay.cmake`` file +TRNG, SRAM_0 and SRAM_1 will be accessible by secure world only. + +.. code-block:: + + set(ADI_NS_PRPH_TRNG OFF CACHE BOOL "") + set(ADI_NS_SRAM_0 OFF CACHE BOOL "Size: 32KB") + set(ADI_NS_SRAM_1 OFF CACHE BOOL "Size: 32KB") + + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Flashing +======== + +Here is an example for the :zephyr:code-sample:`hello_world` application. This example uses the +:ref:`jlink-debug-host-tools` as default. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: max32658evkit/max32658 + :goals: flash + +Open a serial terminal, reset the board (press the RESET button), and you should +see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS build v4.1.0 ***** + Hello World! max32658evkit/max32658 + +Building and flashing secure/non-secure with Arm |reg| TrustZone |reg| +---------------------------------------------------------------------- +The TF-M integration samples can be run using the +``max32658evkit/max32658/ns`` board target. To run we need to manually flash +the resulting image (``tfm_merged.hex``) with a J-Link as follows +(reset and erase are for recovering a locked core): + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: max32658evkit/max32658/ns + :goals: build + +.. code-block:: console + + west flash --hex-file build/zephyr/tfm_merged.hex + +.. code-block:: console + + [INF] Starting bootloader + [WRN] This device was provisioned with dummy keys. This device is NOT SECURE + [INF] PSA Crypto init done, sig_type: RSA-3072 + [WRN] Cannot upgrade: slots have non-compatible sectors + [WRN] Cannot upgrade: slots have non-compatible sectors + [INF] Bootloader chainload address offset: 0x10000 + [INF] Jumping to the first image slot + ***** Booting Zephyr OS build v4.2.0 ***** + Hello World! max32658evkit/max32658/ns + + +Debugging +========= + +Here is an example for the :zephyr:code-sample:`hello_world` application. This example uses the +:ref:`jlink-debug-host-tools` as default. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: max32658evkit/max32658 + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS build v4.2.0 ***** + Hello World! max32658evkit/max32658 + +References +********** + +.. _1: + https://developer.arm.com/documentation/100935/0100/The-TrustZone-hardware-architecture- + +.. _Trusted Firmware M: + https://tf-m-user-guide.trustedfirmware.org/building/tfm_build_instruction.html diff --git a/boards/adi/max32658evkit/max32658evkit_max32658.dts b/boards/adi/max32658evkit/max32658evkit_max32658.dts new file mode 100644 index 000000000000..20b52890f76b --- /dev/null +++ b/boards/adi/max32658evkit/max32658evkit_max32658.dts @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2024-2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "max32658evkit_max32658_common.dtsi" + +/ { + chosen { + zephyr,sram = &secure_ram; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + secure_ram: partition@30000000 { + label = "secure-memory"; + reg = <0x30000000 DT_SIZE_K(256)>; + }; + }; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + slot0_partition: partition@0 { + label = "image-0"; + reg = <0x0 DT_SIZE_K(960)>; + read-only; + }; + + storage_partition: partition@f0000 { + label = "storage"; + reg = <0xf0000 DT_SIZE_K(64)>; + }; + }; +}; + +&trng { + status = "okay"; +}; diff --git a/boards/adi/max32658evkit/max32658evkit_max32658.yaml b/boards/adi/max32658evkit/max32658evkit_max32658.yaml new file mode 100644 index 000000000000..f4e7fdac7f8f --- /dev/null +++ b/boards/adi/max32658evkit/max32658evkit_max32658.yaml @@ -0,0 +1,21 @@ +identifier: max32658evkit/max32658 +name: max32658evkit-max32658 +vendor: adi +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +supported: + - serial + - gpio + - trng + - watchdog + - dma + - counter + - pwm + - rtc_counter + - spi + - i3c +ram: 256 +flash: 960 diff --git a/boards/adi/max32658evkit/max32658evkit_max32658_common.dtsi b/boards/adi/max32658evkit/max32658evkit_max32658_common.dtsi new file mode 100644 index 000000000000..9b65c7bffab6 --- /dev/null +++ b/boards/adi/max32658evkit/max32658evkit_max32658_common.dtsi @@ -0,0 +1,108 @@ +/* + * Copyright (c) 2024-2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +/ { + model = "Analog Devices MAX32658EVKIT"; + compatible = "adi,max32658evkit"; + + chosen { + zephyr,console = &uart0; + zephyr,cortex-m-idle-timer = &counter_wut1; + zephyr,shell-uart = &uart0; + }; + + leds { + compatible = "gpio-leds"; + + led1: led_1 { + gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; + label = "Green LED"; + }; + }; + + buttons { + compatible = "gpio-keys"; + + pb1: pb1 { + gpios = <&gpio0 12 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW2"; + zephyr,code = ; + }; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + accel0 = &adxl367; + led0 = &led1; + sw0 = &pb1; + watchdog0 = &wdt0; + }; +}; + +&uart0 { + pinctrl-0 = <&uart0_tx_p0_9 &uart0_rx_p0_5>; + pinctrl-names = "default"; + current-speed = <115200>; + data-bits = <8>; + parity = "none"; + status = "okay"; +}; + +&clk_ipo { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + pinctrl-0 = <&spi0_mosi_p0_2 &spi0_miso_p0_4 &spi0_sck_p0_6 &spi0_ss0_p0_3>; + pinctrl-names = "default"; +}; + +&rtc_counter { + status = "okay"; + clock-source = ; +}; + +&i3c0 { + status = "okay"; + pinctrl-0 = <&i3c_scl_p0_0 &i3c_sda_p0_1>; + pinctrl-names = "default"; + i2c-scl-hz = ; + i3c-scl-hz = ; + i3c-od-scl-hz = ; + + adxl367: adxl367@530000000000000000 { + compatible = "adi,adxl367"; + reg = <0x53 0x00 0x00>; + status = "okay"; + }; +}; + +&wut0 { + clock-source = ; +}; + +&wut1 { + status = "okay"; + clock-source = ; + wakeup-source; + counter_wut1: counter { + status = "okay"; + }; +}; diff --git a/boards/adi/max32658evkit/max32658evkit_max32658_defconfig b/boards/adi/max32658evkit/max32658evkit_max32658_defconfig new file mode 100644 index 000000000000..25ef03ee5131 --- /dev/null +++ b/boards/adi/max32658evkit/max32658evkit_max32658_defconfig @@ -0,0 +1,16 @@ +# Copyright (c) 2024-2025 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# Enable GPIO +CONFIG_GPIO=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable UART +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# It is secure fw, enable flags +CONFIG_TRUSTED_EXECUTION_SECURE=y diff --git a/boards/adi/max32658evkit/max32658evkit_max32658_ns.dts b/boards/adi/max32658evkit/max32658evkit_max32658_ns.dts new file mode 100644 index 000000000000..0cc9f0880480 --- /dev/null +++ b/boards/adi/max32658evkit/max32658evkit_max32658_ns.dts @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2024-2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "max32658evkit_max32658_common.dtsi" + +/ { + chosen { + zephyr,sram = &non_secure_ram; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_ns_partition; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* RAM split used by TFM */ + secure_ram: partition@20000000 { + label = "secure-memory"; + reg = <0x20000000 DT_SIZE_K(64)>; + }; + + non_secure_ram: partition@20010000 { + label = "non-secure-memory"; + reg = <0x20010000 DT_SIZE_K(192)>; + }; + }; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x0 DT_SIZE_K(64)>; + read-only; + }; + + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x10000 DT_SIZE_K(320)>; + }; + + slot0_ns_partition: partition@60000 { + label = "image-0-nonsecure"; + reg = <0x60000 DT_SIZE_K(576)>; + }; + + /* + * slot1_partition: partition@f0000 { + * label = "image-1"; + * reg = <0xf0000 DT_SIZE_K(0)>; + * }; + * slot1_ns_partition: partition@f0000 { + * label = "image-1-nonsecure"; + * reg = <0xf0000 DT_SIZE_K(0)>; + * }; + */ + + storage_partition: partition@f0000 { + label = "storage"; + reg = <0xf0000 DT_SIZE_K(64)>; + }; + }; +}; diff --git a/boards/adi/max32658evkit/max32658evkit_max32658_ns.yaml b/boards/adi/max32658evkit/max32658evkit_max32658_ns.yaml new file mode 100644 index 000000000000..9868c5bb8a71 --- /dev/null +++ b/boards/adi/max32658evkit/max32658evkit_max32658_ns.yaml @@ -0,0 +1,20 @@ +identifier: max32658evkit/max32658/ns +name: max32658evkit-max32658-Non-Secure +vendor: adi +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +supported: + - serial + - gpio + - watchdog + - dma + - counter + - pwm + - rtc_counter + - spi + - i3c +ram: 192 +flash: 576 diff --git a/boards/adi/max32658evkit/max32658evkit_max32658_ns_defconfig b/boards/adi/max32658evkit/max32658evkit_max32658_ns_defconfig new file mode 100644 index 000000000000..d808f79c5459 --- /dev/null +++ b/boards/adi/max32658evkit/max32658evkit_max32658_ns_defconfig @@ -0,0 +1,19 @@ +# Copyright (c) 2024-2025 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# Enable GPIO +CONFIG_GPIO=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable UART +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# It is non-secure fw, enable flags +CONFIG_TRUSTED_EXECUTION_NONSECURE=y + +# Set TFM and Zephyr sign key +CONFIG_TFM_MCUBOOT_SIGNATURE_TYPE="RSA-3072" diff --git a/boards/arm/mps4/board.cmake b/boards/arm/mps4/board.cmake index 9c4d4a0ef337..56090124532a 100644 --- a/boards/arm/mps4/board.cmake +++ b/boards/arm/mps4/board.cmake @@ -33,7 +33,16 @@ if(CONFIG_ARM_PAC OR CONFIG_ARM_BTI) endif() if(CONFIG_BUILD_WITH_TFM) - set(ARMFVP_FLAGS ${ARMFVP_FLAGS} -a ${APPLICATION_BINARY_DIR}/zephyr/tfm_merged.hex) + # Workaround: Use binary (.bin) format images until TF-M supports generating them in hex (.hex) + # format. The image load addresses are referred from the TF-M official documentation at: + # https://trustedfirmware-m.readthedocs.io/en/latest/platform/arm/mps4/corstone320/README.html + set(ARMFVP_FLAGS ${ARMFVP_FLAGS} + --data ${APPLICATION_BINARY_DIR}/tfm/bin/bl1_1.bin@0x11000000 + --data ${APPLICATION_BINARY_DIR}/tfm/bin/cm_provisioning_bundle.bin@0x12024000 + --data ${APPLICATION_BINARY_DIR}/tfm/bin/dm_provisioning_bundle.bin@0x1202aa00 + --data ${APPLICATION_BINARY_DIR}/tfm/bin/bl2_signed.bin@0x12031400 + -a ${APPLICATION_BINARY_DIR}/zephyr/tfm_merged.hex + ) endif() # FVP Parameters diff --git a/boards/arm/mps4/mps4_corstone315_fvp_ns.yaml b/boards/arm/mps4/mps4_corstone315_fvp_ns.yaml index 01bee24100a2..c04889d7f6f4 100644 --- a/boards/arm/mps4/mps4_corstone315_fvp_ns.yaml +++ b/boards/arm/mps4/mps4_corstone315_fvp_ns.yaml @@ -7,6 +7,9 @@ type: mcu arch: arm ram: 1024 flash: 512 +simulation: + - name: armfvp + exec: FVP_Corstone_SSE-315 toolchain: - gnuarmemb - zephyr diff --git a/boards/arm/mps4/mps4_corstone320_fvp_ns.yaml b/boards/arm/mps4/mps4_corstone320_fvp_ns.yaml index 45ee954a3370..51bfb990e5f6 100644 --- a/boards/arm/mps4/mps4_corstone320_fvp_ns.yaml +++ b/boards/arm/mps4/mps4_corstone320_fvp_ns.yaml @@ -7,6 +7,9 @@ type: mcu arch: arm ram: 1024 flash: 512 +simulation: + - name: armfvp + exec: FVP_Corstone_SSE-320 toolchain: - gnuarmemb - zephyr diff --git a/boards/st/stm32wba65i_dk1/Kconfig.defconfig b/boards/st/stm32wba65i_dk1/Kconfig.defconfig new file mode 100644 index 000000000000..620565526e58 --- /dev/null +++ b/boards/st/stm32wba65i_dk1/Kconfig.defconfig @@ -0,0 +1,13 @@ +# STM32WBA65I Discovery kit board configuration + +# Copyright (c) 2025 STMicroelectronics + +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_STM32WBA65I_DK1 + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_STM32WBA65I_DK1 diff --git a/boards/st/stm32wba65i_dk1/Kconfig.stm32wba65i_dk1 b/boards/st/stm32wba65i_dk1/Kconfig.stm32wba65i_dk1 new file mode 100644 index 000000000000..9fcfc52471d8 --- /dev/null +++ b/boards/st/stm32wba65i_dk1/Kconfig.stm32wba65i_dk1 @@ -0,0 +1,5 @@ +# Copyright (c) 2025 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32WBA65I_DK1 + select SOC_STM32WBA65XX diff --git a/boards/st/stm32wba65i_dk1/arduino_r3_connector.dtsi b/boards/st/stm32wba65i_dk1/arduino_r3_connector.dtsi new file mode 100644 index 000000000000..999cb7600ea3 --- /dev/null +++ b/boards/st/stm32wba65i_dk1/arduino_r3_connector.dtsi @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2025 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + arduino_header: connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; +}; + +arduino_i2c: &i2c1 {}; +arduino_spi: &spi1 {}; diff --git a/boards/st/stm32wba65i_dk1/board.cmake b/boards/st/stm32wba65i_dk1/board.cmake new file mode 100644 index 000000000000..45abc466464f --- /dev/null +++ b/boards/st/stm32wba65i_dk1/board.cmake @@ -0,0 +1,7 @@ +# Copyright (c) 2025 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") + +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake) diff --git a/boards/st/stm32wba65i_dk1/board.yml b/boards/st/stm32wba65i_dk1/board.yml new file mode 100644 index 000000000000..521ca2c3169e --- /dev/null +++ b/boards/st/stm32wba65i_dk1/board.yml @@ -0,0 +1,6 @@ +board: + name: stm32wba65i_dk1 + full_name: STM32WBA65I Discovery kit + vendor: st + socs: + - name: stm32wba65xx diff --git a/boards/st/stm32wba65i_dk1/doc/img/stm32wba65i-dk1.webp b/boards/st/stm32wba65i_dk1/doc/img/stm32wba65i-dk1.webp new file mode 100644 index 000000000000..4cae2e31f470 Binary files /dev/null and b/boards/st/stm32wba65i_dk1/doc/img/stm32wba65i-dk1.webp differ diff --git a/boards/st/stm32wba65i_dk1/doc/index.rst b/boards/st/stm32wba65i_dk1/doc/index.rst new file mode 100644 index 000000000000..fab127b66318 --- /dev/null +++ b/boards/st/stm32wba65i_dk1/doc/index.rst @@ -0,0 +1,232 @@ +.. zephyr:board:: stm32wba65i_dk1 + +Overview +******** + +STM32WBA65I-DK1 is a Bluetooth |reg| Low Energy, 802.15.4 and Zigbee |reg| +wireless and ultra-low-power board embedding a powerful and ultra-low-power +radio compliant with the Bluetooth |reg| Low Energy SIG specification v5.4 +with IEEE 802.15.4-2015 and Zigbee |reg| specifications. + +The ARDUINO |reg| Uno V3 connectivity support and the ST morpho headers allow +the easy expansion of the functionality of the STM32 Discovery kit open +development platform with a wide choice of specialized shields. + +- Ultra-low-power wireless STM32WBA65RI microcontroller based on the Arm |reg| + Cortex |reg| ‑M33 core with TrustZone |reg|, MPU, DSP, and FPU, that operates + at a frequency of up to 100 MHz, featuring 2 Mbyte of flash memory and 512 + Kbytes of SRAM in a VFQFPN68 package + +- MCU RF board (MB2130): + + - 2.4 GHz RF transceiver supporting Bluetooth |reg| specification v5.4 + - Arm |reg| Cortex |reg| M33 CPU with TrustZone |reg|, MPU, DSP, and FPU + - Integrated PCB antenna + +- Three user LEDs (incl. one default not connected) +- One reset push-buttons +- One Joystick + +- Board connectors: + + - 2 USB Type-C + - ARDUINO |reg| Uno V3 expansion connector + - ST morpho headers for full access to all STM32 I/Os + +- Flexible power-supply options: ST-LINK USB VBUS or external sources +- On-board STLINK-V3MODS debugger/programmer with USB re-enumeration capability: + mass storage, Virtual COM port, and debug port + +Hardware +******** + +The STM32WBA65xx multiprotocol wireless and ultralow power devices embed a +powerful and ultralow power radio compliant with the Bluetooth |reg| SIG Low +Energy specification 5.4. + +- Includes ST state-of-the-art patented technology + +- Ultra low power radio: + + - 2.4 GHz radio + - RF transceiver supporting Bluetooth |reg| Low Energy 5.4 specification + IEEE 802.15.4-2015 PHY and MAC, supporting Thread, Matter and Zigbee |reg| + - Proprietary protocols + - RX sensitivity: -96 dBm (Bluetooth |reg| Low Energy at 1 Mbps) + and -100 dBm (IEEE 802.15.4 at 250 kbps) + - Programmable output power, up to +10 dBm with 1 dB steps + - Support for external PA + - Integrated balun to reduce BOM + - Suitable for systems requiring compliance with radio frequency regulations + ETSI EN 300 328, EN 300 440, FCC CFR47 Part 15 and ARIB STD-T66 + +- Ultra low power platform with FlexPowerControl: + + - 1.71 to 3.6 V power supply + - - 40 °C to 85 °C temperature range + - Autonomous peripherals with DMA, functional down to Stop 1 mode + - 120 nA Standby mode (16 wake-up pins) + - 1.68 |micro| A Standby mode with 64 KB SRAM with RTC + - 5.58 |micro| A Stop 2 mode with 64 KB SRAM with RTC + - 28.75 |micro| A/MHz Run mode at 3.3 V + - Radio: Rx 4.26 mA / Tx at 0 dBm 5.94 mA + +- ART Accelerator |trade|: 8-Kbyte instruction cache allowing 0-wait-state execution + from flash memory (frequency up to 100 MHz, 150 DMIPS) +- Power management: embedded regulator LDO and SMPS step-down converter +- Supporting switch on-the-fly and voltage scaling + +- Benchmarks: + + - 1.5 DMIPS/MHz (Drystone 2.1) + - 410 CoreMark |reg| (4.10 CoreMark/MHz) + +- Clock sources: + + - 32 MHz crystal oscillator + - 32 kHz crystal oscillator (LSE) + - Internal low-power 32 kHz (±5%) RC + - Internal 16 MHz factory trimmed RC (±1%) + - PLL for system clock and ADC + +- Memories: + + - 2 MB flash memory with ECC, including 256 Kbytes with 100 cycles + - 512 KB SRAM, including 64 KB with parity check + - 512-byte (32 rows) OTP + +- Rich analog peripherals (independent supply): + + - 12-bit ADC 2.5 Msps with hardware oversampling + +- Communication peripherals: + + - Four UARTs (ISO 7816, IrDA, modem) + - Three SPIs + - Four I2C Fm+ (1 Mbit/s), SMBus/PMBus |reg| + +- System peripherals: + + - Touch sensing controller, up to 24 sensors, supporting touch key, linear, + rotary touch sensors + - One 16-bit, advanced motor control timer + - Three 16-bit timers + - Two 32-bit timer + - Two low-power 16-bit timers (available in Stop mode) + - Two Systick timers + - RTC with hardware calendar and calibration + - Two watchdogs + - 8-channel DMA controller, functional in Stop mode + +- Security and cryptography: + + - Arm |reg| TrustZone |reg| and securable I/Os, memories, and peripherals + - Flexible life cycle scheme with RDP and password protected debug + - Root of trust thanks to unique boot entry and secure hide protection area (HDP) + - SFI (secure firmware installation) thanks to embedded RSS (root secure services) + - Secure data storage with root hardware unique key (RHUK) + - Secure firmware upgrade support with TF-M + - Two AES co-processors, including one with DPA resistance + - Public key accelerator, DPA resistant + - HASH hardware accelerator + - True random number generator, NIST SP800-90B compliant + - 96-bit unique ID + - Active tampers + - CRC calculation unit + +- Up to 86 I/Os (most of them 5 V-tolerant) with interrupt capability + +- Development support: + + - Serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| + +- ECOPACK2 compliant package + +More information about STM32WBA series can be found here: + +- `STM32WBA Series on www.st.com`_ + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Connections and IOs +=================== + +STM32WBA65I-DK1 board has 4 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +.. rst-class:: rst-columns + +- USART_1 TX/RX : PB12/PA8 +- I2C_1_SCL : PB2 +- I2C_1_SDA : PB1 +- LD6 : PD8 +- SPI_1_NSS : PA12 (arduino_spi) +- SPI_1_SCK : PB4 (arduino_spi) +- SPI_1_MISO : PB3 (arduino_spi) +- SPI_1_MOSI : PA15 (arduino_spi) + +System Clock +------------ + +STM32WBA65I-DK1 System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by HSE+PLL clock at 100MHz. + +Serial Port +----------- + +STM32WBA65I-DK1 board has 3 U(S)ARTs. The Zephyr console output is assigned to USART1. +Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +STM32WBA65I-DK1 board includes an ST-LINK/V3 embedded debug tool interface. +It could be used for flash and debug using STM32Cube ecosystem tools. + +Flashing +======== + +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Flashing an application to a STM32WBA65I-DK1 +-------------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm32wba65i_dk1 + :goals: build flash + +You will see the LED blinking every second. + +Debugging +========= + +Debugging using OpenOCD +----------------------- + +You can debug an application in the usual way using OpenOCD. Here is an example for the +:zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm32wba65i_dk1 + :maybe-skip-config: + :goals: debug + +.. _STM32WBA Series on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32wba-series.html + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/stm32wba65i_dk1/stm32wba65i_dk1.dts b/boards/st/stm32wba65i_dk1/stm32wba65i_dk1.dts new file mode 100644 index 000000000000..48e70a3e121e --- /dev/null +++ b/boards/st/stm32wba65i_dk1/stm32wba65i_dk1.dts @@ -0,0 +1,187 @@ +/* + * Copyright (c) 2025 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include "arduino_r3_connector.dtsi" +#include + +/ { + model = "STMicroelectronics STM32WBA65I Discovery kit board"; + compatible = "st,stm32wba65i-dk1"; + + #address-cells = <1>; + #size-cells = <1>; + + chosen { + zephyr,bt-c2h-uart = &usart1; + zephyr,console = &usart1; + zephyr,shell-uart = &usart1; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + leds: leds { + compatible = "gpio-leds"; + + green_led_1: led_0 { + gpios = <&gpiod 8 GPIO_ACTIVE_LOW>; + label = "User LD6"; + }; + + red_led_2: led_1 { + gpios = <&gpiod 9 GPIO_ACTIVE_LOW>; + label = "User LD5"; + }; + + blue_led_3: led_2 { + /* Not functional w/o a 0Ohm resistor on MB2143 R42 */ + gpios = <&gpiob 10 GPIO_ACTIVE_LOW>; + label = "User LD3"; + }; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&adc4 6>; + keyup-threshold-mv = <3300>; + + select_key { + press-thresholds-mv = <0>; + zephyr,code = ; + }; + + left_key { + press-thresholds-mv = <670>; + zephyr,code = ; + }; + + down_key { + press-thresholds-mv = <1320>; + zephyr,code = ; + }; + + up_key { + press-thresholds-mv = <2010>; + zephyr,code = ; + }; + + right_key { + press-thresholds-mv = <2650>; + zephyr,code = ; + }; + }; + + aliases { + led0 = &green_led_1; + led1 = &red_led_2; + }; +}; + +&clk_lsi { + status = "okay"; +}; + +&clk_lse { + status = "okay"; +}; + +&clk_hse { + hse-div2; + status = "okay"; +}; + +&clk_hsi { + status = "okay"; +}; + +&rcc { + clocks = <&clk_hse>; + clock-frequency = ; + ahb-prescaler = <1>; + ahb5-prescaler = <2>; + apb1-prescaler = <1>; + apb2-prescaler = <2>; + apb7-prescaler = <1>; +}; + +&iwdg { + status = "okay"; +}; + +&rtc { + status = "okay"; + clocks = <&rcc STM32_CLOCK(APB7, 21)>, + <&rcc STM32_SRC_LSE RTC_SEL(1)>; + prescaler = <32768>; +}; + +&usart1 { + clocks = <&rcc STM32_CLOCK(APB2, 14)>, + <&rcc STM32_SRC_HSI16 USART1_SEL(2)>; + pinctrl-0 = <&usart1_tx_pb12 &usart1_rx_pa8>; + pinctrl-1 = <&analog_pb12 &analog_pa8>; + pinctrl-names = "default", "sleep"; + current-speed = <115200>; + status = "okay"; +}; + +&spi1 { + pinctrl-0 = <&spi1_nss_pa12 &spi1_sck_pb4 + &spi1_miso_pb3 &spi1_mosi_pa15>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_scl_pb2 &i2c1_sda_pb1>; + pinctrl-names = "default"; + status = "okay"; + clock-frequency = ; +}; + +&adc4 { + pinctrl-0 = <&adc4_in6_pa3>; + pinctrl-names = "default"; + st,adc-clock-source = "ASYNC"; + st,adc-prescaler = <4>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + channel@6 { + reg = <0x6>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + zephyr,vref-mv = <3300>; + }; +}; + +stm32_lp_tick_source: &lptim1 { + clocks = <&rcc STM32_CLOCK(APB7, 11)>, + <&rcc STM32_SRC_LSE LPTIM1_SEL(3)>; + status = "okay"; +}; + +&rng { + status = "okay"; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + storage_partition: partition@1c0000 { + label = "storage"; + reg = <0x001c0000 DT_SIZE_K(256)>; + }; + }; +}; diff --git a/boards/st/stm32wba65i_dk1/stm32wba65i_dk1.yaml b/boards/st/stm32wba65i_dk1/stm32wba65i_dk1.yaml new file mode 100644 index 000000000000..b77e57240f1a --- /dev/null +++ b/boards/st/stm32wba65i_dk1/stm32wba65i_dk1.yaml @@ -0,0 +1,10 @@ +identifier: stm32wba65i_dk1/stm32wba65xx +name: ST STM32WBA65I Discovery kit +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +ram: 512 +flash: 2048 +vendor: st diff --git a/boards/st/stm32wba65i_dk1/stm32wba65i_dk1_defconfig b/boards/st/stm32wba65i_dk1/stm32wba65i_dk1_defconfig new file mode 100644 index 000000000000..5e650e6826cb --- /dev/null +++ b/boards/st/stm32wba65i_dk1/stm32wba65i_dk1_defconfig @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2025 STMicroelectronics + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable GPIO +CONFIG_GPIO=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable the internal SMPS regulator +CONFIG_POWER_SUPPLY_DIRECT_SMPS=y + +# Enable ADC for joystick +CONFIG_ADC=y diff --git a/boards/st/stm32wba65i_dk1/support/openocd.cfg b/boards/st/stm32wba65i_dk1/support/openocd.cfg new file mode 100644 index 000000000000..0745453a16a5 --- /dev/null +++ b/boards/st/stm32wba65i_dk1/support/openocd.cfg @@ -0,0 +1,26 @@ +# Note: Using OpenOCD using stm32wba65i_dk1 requires using openocd fork. +# See board documentation for more information + +source [find interface/stlink-dap.cfg] + +set WORKAREASIZE 0x8000 + +transport select "dapdirect_swd" + +# Enable debug when in low power modes +set ENABLE_LOW_POWER 1 + +# Stop Watchdog counters when halt +set STOP_WATCHDOG 1 + +# STlink Debug clock frequency +set CLOCK_FREQ 8000 + +# Reset configuration +# use hardware reset, connect under reset +# connect_assert_srst needed if low power mode application running (WFI...) +reset_config srst_only srst_nogate + +source [find target/stm32wbax.cfg] + +gdb_memory_map disable diff --git a/doc/releases/migration-guide-4.4.rst b/doc/releases/migration-guide-4.4.rst index 762082635b1c..6919f84e875c 100644 --- a/doc/releases/migration-guide-4.4.rst +++ b/doc/releases/migration-guide-4.4.rst @@ -57,5 +57,12 @@ Other subsystems Modules ******* +Trusted Firmware-M +================== + +* The ``SECURE_UART1`` TF-M define is now controlled by Zephyr's + :kconfig:option:`CONFIG_TFM_SECURE_UART`. This option will override any platform values previously + specified in the TF-M repository. + Architectures ************* diff --git a/include/zephyr/ipc/backends/intel_adsp_host_ipc.h b/include/zephyr/ipc/backends/intel_adsp_host_ipc.h new file mode 100644 index 000000000000..74938e53c86f --- /dev/null +++ b/include/zephyr/ipc/backends/intel_adsp_host_ipc.h @@ -0,0 +1,213 @@ +/* + * Copyright (c) 2022, 2025 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_IPC_BACKEND_INTEL_ADSP_IPC_H +#define ZEPHYR_INCLUDE_IPC_BACKEND_INTEL_ADSP_IPC_H + +#include +#include +#include +#include + +#include + +/** Enum on IPC send length argument to indicate IPC message type. */ +enum intel_adsp_send_len { + /** Normal IPC message. */ + INTEL_ADSP_IPC_SEND_MSG, + + /** Synchronous IPC message. */ + INTEL_ADSP_IPC_SEND_MSG_SYNC, + + /** Emergency IPC message. */ + INTEL_ADSP_IPC_SEND_MSG_EMERGENCY, + + /** Send a DONE message. */ + INTEL_ADSP_IPC_SEND_DONE, + + /** Query backend to see if IPC is complete. */ + INTEL_ADSP_IPC_SEND_IS_COMPLETE, +}; + +/** Enum on callback return values. */ +enum intel_adsp_cb_ret { + /** Callback return to indicate no issue. Must be 0. */ + INTEL_ADSP_IPC_CB_RET_OKAY = 0, + + /** Callback return to signal needing external completion. */ + INTEL_ADSP_IPC_CB_RET_EXT_COMPLETE, +}; + +/** Enum on callback length argument to indicate which triggers the callback. */ +enum intel_adsp_cb_len { + /** Callback length to indicate this is an IPC message. */ + INTEL_ADSP_IPC_CB_MSG, + + /** Callback length to indicate this is a DONE message. */ + INTEL_ADSP_IPC_CB_DONE, +}; + +/** Struct for IPC message descriptor. */ +struct intel_adsp_ipc_msg { + /** Header specific to platform. */ + uint32_t data; + + /** Extension specific to platform. */ + uint32_t ext_data; + + /** Timeout for sending synchronuous message. */ + k_timeout_t timeout; +}; + +#ifdef CONFIG_INTEL_ADSP_IPC_OLD_INTERFACE + +/** + * @brief Intel ADSP IPC Message Handler Callback. + * + * This function, once registered via intel_adsp_ipc_set_message_handler(), + * is invoked in interrupt context to service messages sent from the + * foreign/connected IPC context. The message contents of the TDR and + * TDD registers are provided in the data/ext_data argument. + * + * The function should return true if processing of the message is + * complete and return notification to the other side (via the TDA + * register) is desired immediately. Returning false means that no + * return "DONE" interrupt will occur until intel_adsp_ipc_complete() is + * called on this device at some point in the future. + * + * @note Further messages on the link will not be transmitted or + * received while an in-progress message remains incomplete! + * + * @param dev IPC device. + * @param arg Registered argument from intel_adsp_ipc_set_message_handler(). + * @param data Message data from other side (low bits of TDR register). + * @param ext_dat Extended message data (TDD register). + * @return true if the message is completely handled. + */ +typedef bool (*intel_adsp_ipc_handler_t)(const struct device *dev, void *arg, uint32_t data, + uint32_t ext_data); + +/** + * @brief Intel ADSP IPC Message Complete Callback. + * + * This function, once registered via intel_adsp_ipc_set_done_handler(), is + * invoked in interrupt context when a "DONE" return interrupt is + * received from the other side of the connection (indicating that a + * previously sent message is finished processing). + * + * @note On Intel ADSP hardware the DONE interrupt is transmitted + * synchronously with the interrupt being cleared on the remote + * device. It is not possible to delay processing. This callback + * will still occur, but protocols which rely on notification of + * asynchronous command processing will need modification. + * + * @param dev IPC device. + * @param arg Registered argument from intel_adsp_ipc_set_done_handler(). + * @return True if IPC completion will be done externally, otherwise false. + * @note Returning True will cause this API to skip writing IPC registers + * signalling IPC message completion and those actions should be done by + * external code manually. Returning false from the handler will perform + * writing to IPC registers signalling message completion normally by this API. + */ +typedef bool (*intel_adsp_ipc_done_t)(const struct device *dev, void *arg); + +#endif /* CONFIG_INTEL_ADSP_IPC_OLD_INTERFACE */ + +#ifdef CONFIG_PM_DEVICE +typedef int (*intel_adsp_ipc_resume_handler_t)(const struct device *dev, void *arg); + +typedef int (*intel_adsp_ipc_suspend_handler_t)(const struct device *dev, void *arg); +#endif /* CONFIG_PM_DEVICE */ + +/** + * Intel Audio DSP IPC service backend config struct. + */ +struct intel_adsp_ipc_config { + /** Pointer to hardware register block. */ + volatile struct intel_adsp_ipc *regs; +}; + +/** + * Intel Audio DSP IPC service backend data struct. + */ +struct intel_adsp_ipc_data { + /** Semaphore used to wait for remote acknowledgment of sent message. */ + struct k_sem sem; + + /** General driver lock. */ + struct k_spinlock lock; + + /** Pending TX acknowlegement. */ + bool tx_ack_pending; + + /** Pointer to endpoint configuration. */ + const struct ipc_ept_cfg *ept_cfg; + +#ifdef CONFIG_INTEL_ADSP_IPC_OLD_INTERFACE + /** Callback for message handler. */ + intel_adsp_ipc_handler_t handle_message; + + /** Argument for message handler callback. */ + void *handler_arg; + + /** Callback for done notification. */ + intel_adsp_ipc_done_t done_notify; + + /** Argument for done notification callback. */ + void *done_arg; +#endif /* CONFIG_INTEL_ADSP_IPC_OLD_INTERFACE */ + +#ifdef CONFIG_PM_DEVICE + /** Pointer to resume handler. */ + intel_adsp_ipc_resume_handler_t resume_fn; + + /** Argument for resume handler. */ + void *resume_fn_args; + + /** Pointer to suspend handler. */ + intel_adsp_ipc_suspend_handler_t suspend_fn; + + /** Argument for suspend handler. */ + void *suspend_fn_args; +#endif /* CONFIG_PM_DEVICE */ +}; + +/** + * Endpoint private data struct. + */ +struct intel_adsp_ipc_ept_priv_data { + /** Callback return value (enum intel_adsp_cb_ret). */ + int cb_ret; + + /** Pointer to additional private data. */ + void *priv; +}; + +#ifdef CONFIG_PM_DEVICE + +/** + * @brief Registers resume callback handler used to resume Device from suspended state. + * + * @param dev IPC device. + * @param fn Callback function. + * @param arg Value to pass as the "arg" parameter to the function. + */ +void intel_adsp_ipc_set_resume_handler(const struct device *dev, intel_adsp_ipc_resume_handler_t fn, + void *arg); + +/** + * @brief Registers suspend callback handler used to suspend active Device. + * + * @param dev IPC device. + * @param fn Callback function. + * @param arg Value to pass as the "arg" parameter to the function. + */ +void intel_adsp_ipc_set_suspend_handler(const struct device *dev, + intel_adsp_ipc_suspend_handler_t fn, void *arg); + +#endif /* CONFIG_PM_DEVICE */ + +#endif /* ZEPHYR_INCLUDE_IPC_BACKEND_INTEL_ADSP_IPC_H */ diff --git a/modules/Kconfig b/modules/Kconfig index b66955981fa0..cd29dc3ccc88 100644 --- a/modules/Kconfig +++ b/modules/Kconfig @@ -36,7 +36,6 @@ source "modules/Kconfig.picolibc" source "modules/Kconfig.renesas" source "modules/Kconfig.rust" source "modules/Kconfig.simplelink" -source "modules/Kconfig.sof" source "modules/Kconfig.stm32" source "modules/Kconfig.syst" source "modules/Kconfig.telink" diff --git a/modules/Kconfig.sof b/modules/Kconfig.sof deleted file mode 100644 index 4a0b94186606..000000000000 --- a/modules/Kconfig.sof +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2020 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config ZEPHYR_SOF_MODULE - bool - -config SOF - bool "Sound Open Firmware (SOF)" - depends on ZEPHYR_SOF_MODULE - help - Build Sound Open Firmware (SOF) support. diff --git a/modules/trusted-firmware-m/CMakeLists.txt b/modules/trusted-firmware-m/CMakeLists.txt index 0add755cdc67..0fc884cf79fa 100644 --- a/modules/trusted-firmware-m/CMakeLists.txt +++ b/modules/trusted-firmware-m/CMakeLists.txt @@ -67,6 +67,8 @@ if (CONFIG_BUILD_WITH_TFM) list(APPEND TFM_CMAKE_ARGS -DMCUBOOT_KEY_${SUFFIX}=${CONFIG_TFM_KEY_FILE_${SUFFIX}}) endforeach() + # Supply path to MCUboot for TF-M build + list(APPEND TFM_CMAKE_ARGS -DMCUBOOT_PATH=${ZEPHYR_MCUBOOT_MODULE_DIR}) else() list(APPEND TFM_CMAKE_ARGS -DBL2=FALSE) endif() @@ -154,6 +156,12 @@ if (CONFIG_BUILD_WITH_TFM) list(APPEND TFM_CMAKE_ARGS -DTFM_SPM_LOG_LEVEL=${TFM_SPM_LOG_LEVEL}) endif() + if(CONFIG_TFM_SECURE_UART) + list(APPEND TFM_CMAKE_ARGS -DSECURE_UART1=1) + else() + list(APPEND TFM_CMAKE_ARGS -DSECURE_UART1=0) + endif() + # Enable TFM partitions as specified in Kconfig foreach(partition ${TFM_VALID_PARTITIONS}) if (CONFIG_${partition}) @@ -183,7 +191,7 @@ if (CONFIG_BUILD_WITH_TFM) set(TFM_S_ELF_FILE ${TFM_BINARY_DIR}/bin/tfm_s.elf) set(TFM_S_BIN_FILE ${TFM_BINARY_DIR}/bin/tfm_s.bin) set(TFM_S_HEX_FILE ${TFM_BINARY_DIR}/bin/tfm_s.hex) - set(TFM_NS_BIN_FILE ${TFM_BINARY_DIR}/bin/tfm_ns.bin) + set(TFM_NS_BIN_FILE ${CMAKE_BINARY_DIR}/tfm_ns/bin/tfm_ns.bin) set(TFM_NS_HEX_FILE ${CMAKE_BINARY_DIR}/tfm_ns/bin/tfm_ns.hex) set(TFM_S_SIGNED_BIN_FILE ${TFM_BINARY_DIR}/bin/tfm_s_signed.bin) set(TFM_NS_SIGNED_BIN_FILE ${TFM_BINARY_DIR}/bin/tfm_ns_signed.bin) @@ -251,16 +259,11 @@ if (CONFIG_BUILD_WITH_TFM) list(APPEND TFM_CMAKE_ARGS -DTFM_PLATFORM_NXP_HAL_FILE_PATH=${TFM_PLATFORM_NXP_HAL_FILE_PATH}) endif() - if(CONFIG_BOARD_MAX32657EVKIT_MAX32657_NS) + if(CONFIG_BOARD_MAX32657EVKIT_MAX32657_NS OR CONFIG_BOARD_MAX32658EVKIT_MAX32658_NS) # Supply path to hal_adi for TF-M build list(APPEND TFM_CMAKE_ARGS -DHAL_ADI_PATH=${ZEPHYR_ADI_MODULE_DIR}) endif() - if(CONFIG_TFM_BL2 AND CONFIG_TFM_MCUBOOT_PATH_LOCAL) - # Supply path to MCUboot for TF-M build - list(APPEND TFM_CMAKE_ARGS -DMCUBOOT_PATH=${ZEPHYR_MCUBOOT_MODULE_DIR}) - endif() - if(CONFIG_TFM_MCUBOOT_DATA_SHARING) list(APPEND TFM_CMAKE_ARGS -DMCUBOOT_DATA_SHARING=ON) endif() @@ -277,8 +280,14 @@ if (CONFIG_BUILD_WITH_TFM) list(APPEND TFM_CMAKE_ARGS -DTFM_TESTS_REVISION_CHECKS=OFF) - if(CONFIG_TFM_ETHOS_DRIVER_PATH_LOCAL) - list(APPEND TFM_CMAKE_ARGS -DETHOS_DRIVER_PATH=${CONFIG_TFM_ETHOS_DRIVER_PATH_LOCAL}) + if(CONFIG_SOC_SERIES_MPS3 OR CONFIG_SOC_SERIES_MPS4) + list(APPEND TFM_CMAKE_ARGS -DETHOS_DRIVER_PATH=${ZEPHYR_HAL_ETHOS_U_MODULE_DIR}) + endif() + + if(CONFIG_TFM_STM32_FLASH_LAYOUT_BEGIN_OFFSET) + list(APPEND TFM_CMAKE_ARGS + -DSTM32_FLASH_LAYOUT_BEGIN_OFFSET=${CONFIG_TFM_STM32_FLASH_LAYOUT_BEGIN_OFFSET} + ) endif() file(MAKE_DIRECTORY ${TFM_BINARY_DIR}) @@ -316,8 +325,8 @@ if (CONFIG_BUILD_WITH_TFM) # number of parallel jobs to 1. set(PARALLEL_JOBS -j 1) else() - # Leave PARALLEL_JOBS unset and use the default number of - # threads. Which is num_cores+2 on Ninja and MAKEFLAGS with Make. + # Leave PARALLEL_JOBS unset and use the default number of + # threads. Which is num_cores+2 on Ninja and MAKEFLAGS with Make. endif() set(tfm_image_info MAP "name: tfm, source-dir: ${ZEPHYR_TRUSTED_FIRMWARE_M_MODULE_DIR}") @@ -448,115 +457,247 @@ if (CONFIG_BUILD_WITH_TFM) set(HEX_ADDR_ARGS_NS "--hex-addr=${TFM_HEX_BASE_ADDRESS_NS}") endif() - function(tfm_sign OUT_ARG SUFFIX PAD INPUT_FILE OUTPUT_FILE) - if(PAD) + if(CONFIG_TFM_BL2) + set(image_alignment 1) + set(flash_write_block_size 1) + set(flash_erase_block_size 1) + + dt_chosen(chosen_flash PROPERTY "zephyr,flash") + if(DEFINED chosen_flash AND chosen_flash) + dt_prop(flash_write_block_size PATH ${chosen_flash} PROPERTY write-block-size) + dt_prop(flash_erase_block_size PATH ${chosen_flash} PROPERTY erase-block-size) + else() + message(WARNING + "The 'zephyr,flash' chosen property is not defined! + Using flash_write_block_size and flash_erase_block_size default values + that may differ from TF-M board definitions resulting in invalid signatures." + ) + endif() + + # The alignment is determined by the minimal amount of bytes necessary to + # be written in the flash sector. Ex., assuming that the sector erase + # operation is 1KiB and, on that sector, the minimum amount of bytes that + # must be written is 8 bytes then the alignment is 8. + # + # Current MCUboot maximum alignment is 32 bytes. + if(flash_write_block_size GREATER 0) + if(flash_write_block_size GREATER 32) + message(WARNING + "imgtool max alignment is 32 and current value is ${flash_write_block_size}. + Keep default image alignment of 1." + ) + else() + set(image_alignment ${flash_write_block_size}) + endif() + endif() + + # Calculate the maximum number of sectors necessary to store the image. + dt_nodelabel(s_partition_node NODELABEL "slot0_partition" REQUIRED) + dt_nodelabel(ns_partition_node NODELABEL "slot0_ns_partition" REQUIRED) + dt_reg_size(s_partition_size PATH ${s_partition_node}) + dt_reg_size(ns_partition_size PATH ${ns_partition_node}) + math(EXPR S_MAX_SECTORS "${s_partition_size} / ${flash_erase_block_size}") + math(EXPR NS_MAX_SECTORS "${ns_partition_size} / ${flash_erase_block_size}") + if(CONFIG_TFM_MCUBOOT_IMAGE_NUMBER STREQUAL "1") + math(EXPR S_NS_MAX_SECTORS "${S_MAX_SECTORS} + ${NS_MAX_SECTORS}") + else() + if(${S_MAX_SECTORS} GREATER ${NS_MAX_SECTORS}) + set(S_NS_MAX_SECTORS ${S_MAX_SECTORS}) + else() + set(S_NS_MAX_SECTORS ${NS_MAX_SECTORS}) + endif() + endif() + endif() + + function(tfm_sign OUT_ARG) + set(options HEADER TRAILER CONFIRM) + set(oneValueArgs SUFFIX MAX_SECTORS INPUT_FILE OUTPUT_FILE) + set(multiValueArgs "") + + cmake_parse_arguments( + TFM_SIGN_ARG + "${options}" + "${oneValueArgs}" + "${multiValueArgs}" + ${ARGN} + ) + + if(NOT DEFINED TFM_SIGN_ARG_SUFFIX OR + NOT DEFINED TFM_SIGN_ARG_INPUT_FILE OR + NOT DEFINED TFM_SIGN_ARG_OUTPUT_FILE) + message(FATAL_ERROR "SUFFIX, INPUT_FILE and OUTPUT_FILE are required arguments") + endif() + + set(pad_args "") + if(TFM_SIGN_ARG_HEADER AND TFM_SIGN_ARG_TRAILER) set(pad_args --pad --pad-header) + elseif(TFM_SIGN_ARG_HEADER) + set(pad_args --pad-header) + elseif(TFM_SIGN_ARG_TRAILER) + set(pad_args --pad) endif() + + set(confirm "") + if(TFM_SIGN_ARG_CONFIRM) + set(confirm --confirm) + endif() + # Secure + Non-secure images are signed the same way as a secure only # build, but with a different layout file. - set(layout_file ${PREPROCESSED_FILE_${SUFFIX}}) - if(SUFFIX STREQUAL "S_NS") - set(SUFFIX "S") + set(layout_file ${PREPROCESSED_FILE_${TFM_SIGN_ARG_SUFFIX}}) + if(TFM_SIGN_ARG_SUFFIX STREQUAL "S_NS") + set(TFM_SIGN_ARG_SUFFIX "S") endif() - set (${OUT_ARG} + + set(${OUT_ARG} # Add the MCUBoot script to the path so that if there is a version of imgtool in there then # it gets used over the system imgtool. Used so that imgtool from upstream # mcuboot is preferred over system imgtool ${CMAKE_COMMAND} -E env PYTHONPATH=${ZEPHYR_MCUBOOT_MODULE_DIR}/scripts ${PYTHON_EXECUTABLE} ${TFM_MCUBOOT_DIR}/scripts/wrapper/wrapper.py --layout ${layout_file} - -k ${CONFIG_TFM_KEY_FILE_${SUFFIX}} + -k ${CONFIG_TFM_KEY_FILE_${TFM_SIGN_ARG_SUFFIX}} --public-key-format ${TFM_PUBLIC_KEY_FORMAT} - --align 1 - -v ${CONFIG_TFM_IMAGE_VERSION_${SUFFIX}} + --align ${image_alignment} + --max-sectors ${TFM_SIGN_ARG_MAX_SECTORS} + -v ${CONFIG_TFM_IMAGE_VERSION_${TFM_SIGN_ARG_SUFFIX}} ${pad_args} - ${HEX_ADDR_ARGS_${SUFFIX}} - ${ADD_${SUFFIX}_IMAGE_MIN_VER} + ${confirm} + ${HEX_ADDR_ARGS_${TFM_SIGN_ARG_SUFFIX}} + ${ADD_${TFM_SIGN_ARG_SUFFIX}_IMAGE_MIN_VER} -s ${CONFIG_TFM_IMAGE_SECURITY_COUNTER} --measured-boot-record -H ${CONFIG_ROM_START_OFFSET} - ${INPUT_FILE} - ${OUTPUT_FILE} + ${TFM_SIGN_ARG_INPUT_FILE} + ${TFM_SIGN_ARG_OUTPUT_FILE} PARENT_SCOPE) endfunction() - set(MERGED_FILE ${CMAKE_BINARY_DIR}/zephyr/tfm_merged.hex) - set(S_NS_FILE ${CMAKE_BINARY_DIR}/zephyr/tfm_s_zephyr_ns.hex) - set(S_NS_SIGNED_FILE ${CMAKE_BINARY_DIR}/zephyr/tfm_s_zephyr_ns_signed.hex) - set(NS_SIGNED_FILE ${CMAKE_BINARY_DIR}/zephyr/zephyr_ns_signed.hex) - set(S_SIGNED_FILE ${CMAKE_BINARY_DIR}/zephyr/tfm_s_signed.hex) + set(MERGED_HEX_FILE ${CMAKE_BINARY_DIR}/zephyr/tfm_merged.hex) + set(MERGED_BIN_FILE ${CMAKE_BINARY_DIR}/zephyr/tfm_merged.bin) + set(S_NS_SIGNED_CONFIRMED_HEX_FILE ${CMAKE_BINARY_DIR}/zephyr/tfm_s_zephyr_ns_confirmed_signed.hex) + set(S_NS_HEX_FILE ${CMAKE_BINARY_DIR}/zephyr/tfm_s_zephyr_ns.hex) + set(S_NS_SIGNED_HEX_FILE ${CMAKE_BINARY_DIR}/zephyr/tfm_s_zephyr_ns_signed.hex) + set(S_NS_SIGNED_BIN_FILE ${CMAKE_BINARY_DIR}/zephyr/tfm_s_zephyr_ns_signed.bin) + set(NS_SIGNED_HEX_FILE ${CMAKE_BINARY_DIR}/zephyr/zephyr_ns_signed.hex) + set(S_SIGNED_HEX_FILE ${CMAKE_BINARY_DIR}/zephyr/tfm_s_signed.hex) + set(NS_SIGNED_BIN_FILE ${CMAKE_BINARY_DIR}/zephyr/zephyr_ns_signed.bin) + set(S_SIGNED_BIN_FILE ${CMAKE_BINARY_DIR}/zephyr/tfm_s_signed.bin) if (CONFIG_TFM_USE_NS_APP) # Use the TF-M NS binary as the Non-Secure application firmware image - set(NS_APP_FILE $) + set(NS_HEX_APP_FILE $) + set(NS_BIN_APP_FILE $) else() # Use the Zephyr binary as the Non-Secure application firmware image - set(NS_APP_FILE ${CMAKE_BINARY_DIR}/zephyr/${KERNEL_HEX_NAME}) + set(NS_HEX_APP_FILE ${CMAKE_BINARY_DIR}/zephyr/${KERNEL_HEX_NAME}) + set(NS_BIN_APP_FILE ${CMAKE_BINARY_DIR}/zephyr/${KERNEL_BIN_NAME}) endif() if (NOT CONFIG_TFM_BL2) # Merge tfm_s and zephyr (NS) image to a single binary. set_property(GLOBAL APPEND PROPERTY extra_post_build_commands COMMAND ${PYTHON_EXECUTABLE} ${ZEPHYR_BASE}/scripts/build/mergehex.py - -o ${MERGED_FILE} + -o ${MERGED_HEX_FILE} $ - ${NS_APP_FILE} + ${NS_HEX_APP_FILE} ) set_property(GLOBAL APPEND PROPERTY extra_post_build_byproducts - ${MERGED_FILE} + ${MERGED_HEX_FILE} ) elseif(CONFIG_TFM_MCUBOOT_IMAGE_NUMBER STREQUAL "1") - tfm_sign(sign_cmd S_NS TRUE ${S_NS_FILE} ${S_NS_SIGNED_FILE}) + tfm_sign(sign_cmd_s_ns_confirm_hex SUFFIX "S_NS" + HEADER TRAILER CONFIRM MAX_SECTORS ${S_NS_MAX_SECTORS} + INPUT_FILE ${S_NS_HEX_FILE} OUTPUT_FILE ${S_NS_SIGNED_CONFIRMED_HEX_FILE}) + tfm_sign(sign_cmd_s_ns_hex SUFFIX "S_NS" + HEADER MAX_SECTORS ${S_NS_MAX_SECTORS} + INPUT_FILE ${S_NS_HEX_FILE} OUTPUT_FILE ${S_NS_SIGNED_HEX_FILE}) set_property(GLOBAL APPEND PROPERTY extra_post_build_commands COMMAND ${PYTHON_EXECUTABLE} ${ZEPHYR_BASE}/scripts/build/mergehex.py - -o ${S_NS_FILE} + -o ${S_NS_HEX_FILE} $ - ${NS_APP_FILE} + ${NS_HEX_APP_FILE} - COMMAND ${sign_cmd} + COMMAND ${sign_cmd_s_ns_confirm_hex} COMMAND ${PYTHON_EXECUTABLE} ${ZEPHYR_BASE}/scripts/build/mergehex.py - -o ${MERGED_FILE} + -o ${MERGED_HEX_FILE} $<$:$> $<$>:$> - ${S_NS_SIGNED_FILE} + ${S_NS_SIGNED_CONFIRMED_HEX_FILE} + + COMMAND ${CMAKE_OBJCOPY} --input-target=ihex --output-target=binary ${MERGED_HEX_FILE} ${MERGED_BIN_FILE} + ) + + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND ${sign_cmd_s_ns_hex} + + COMMAND ${CMAKE_OBJCOPY} --input-target=ihex --output-target=binary ${S_NS_SIGNED_HEX_FILE} ${S_NS_SIGNED_BIN_FILE} ) set_property(GLOBAL APPEND PROPERTY extra_post_build_byproducts - ${S_NS_FILE} - ${S_NS_SIGNED_FILE} - ${MERGED_FILE} + ${S_NS_SIGNED_CONFIRMED_HEX_FILE} + ${S_NS_HEX_FILE} + ${S_NS_SIGNED_HEX_FILE} + ${S_NS_SIGNED_BIN_FILE} + ${MERGED_HEX_FILE} + ${MERGED_BIN_FILE} ) else() if (CONFIG_TFM_USE_NS_APP) - tfm_sign(sign_cmd_ns NS TRUE ${NS_APP_FILE} ${NS_SIGNED_FILE}) + tfm_sign(sign_cmd_ns_hex SUFFIX "NS" + HEADER TRAILER CONFIRM MAX_SECTORS ${S_NS_MAX_SECTORS} + INPUT_FILE ${NS_HEX_APP_FILE} + OUTPUT_FILE ${NS_SIGNED_HEX_FILE}) + tfm_sign(sign_cmd_ns_bin SUFFIX "NS" + HEADER TRAILER MAX_SECTORS ${S_NS_MAX_SECTORS} + INPUT_FILE ${NS_BIN_APP_FILE} + OUTPUT_FILE ${NS_SIGNED_BIN_FILE}) else() - tfm_sign(sign_cmd_ns NS FALSE ${NS_APP_FILE} ${NS_SIGNED_FILE}) + tfm_sign(sign_cmd_ns_hex SUFFIX "NS" + TRAILER CONFIRM MAX_SECTORS ${S_NS_MAX_SECTORS} + INPUT_FILE ${NS_HEX_APP_FILE} + OUTPUT_FILE ${NS_SIGNED_HEX_FILE}) + tfm_sign(sign_cmd_ns_bin SUFFIX "NS" + MAX_SECTORS ${S_NS_MAX_SECTORS} + INPUT_FILE ${NS_BIN_APP_FILE} + OUTPUT_FILE ${NS_SIGNED_BIN_FILE}) endif() - tfm_sign(sign_cmd_s S TRUE $ ${S_SIGNED_FILE}) + tfm_sign(sign_cmd_s_hex SUFFIX "S" + HEADER TRAILER CONFIRM MAX_SECTORS ${S_NS_MAX_SECTORS} + INPUT_FILE $ + OUTPUT_FILE ${S_SIGNED_HEX_FILE}) + tfm_sign(sign_cmd_s_bin SUFFIX "S" + HEADER TRAILER MAX_SECTORS ${S_NS_MAX_SECTORS} + INPUT_FILE $ + OUTPUT_FILE ${S_SIGNED_BIN_FILE}) #Create and sign for concatenated binary image, should align with the TF-M BL2 set_property(GLOBAL APPEND PROPERTY extra_post_build_commands - COMMAND ${sign_cmd_ns} - COMMAND ${sign_cmd_s} + COMMAND ${sign_cmd_ns_hex} + COMMAND ${sign_cmd_ns_bin} + COMMAND ${sign_cmd_s_hex} + COMMAND ${sign_cmd_s_bin} COMMAND ${PYTHON_EXECUTABLE} ${ZEPHYR_BASE}/scripts/build/mergehex.py - -o ${MERGED_FILE} + -o ${MERGED_HEX_FILE} $<$:$> $<$>:$> - ${S_SIGNED_FILE} - ${NS_SIGNED_FILE} + ${S_SIGNED_HEX_FILE} + ${NS_SIGNED_HEX_FILE} ) set_property(GLOBAL APPEND PROPERTY extra_post_build_byproducts - ${S_SIGNED_FILE} - ${NS_SIGNED_FILE} - ${MERGED_FILE} + ${S_SIGNED_HEX_FILE} + ${S_SIGNED_BIN_FILE} + ${NS_SIGNED_HEX_FILE} + ${NS_SIGNED_BIN_FILE} + ${MERGED_HEX_FILE} ) endif() diff --git a/modules/trusted-firmware-m/Kconfig.tfm b/modules/trusted-firmware-m/Kconfig.tfm index 36a734ad8b3e..6a8140b23d5a 100644 --- a/modules/trusted-firmware-m/Kconfig.tfm +++ b/modules/trusted-firmware-m/Kconfig.tfm @@ -10,19 +10,22 @@ config ZEPHYR_TRUSTED_FIRMWARE_M_MODULE config TFM_BOARD string - default "nxp/lpcxpresso55s69" if BOARD_LPCXPRESSO55S69_LPC55S69_CPU0_NS + default "adi/max32657" if BOARD_MAX32657EVKIT_MAX32657_NS || BOARD_MAX32658EVKIT_MAX32658_NS default "arm/mps2/an521" if BOARD_MPS2_AN521_CPU0_NS - default "arm/mps3/corstone300/fvp" if BOARD_MPS3_CORSTONE300_FVP_NS + default "arm/mps3/corstone300/fvp" if BOARD_MPS3_CORSTONE300_FVP_NS default "arm/mps3/corstone300/an547" if BOARD_MPS3_CORSTONE300_AN547_NS default "arm/mps3/corstone300/an552" if BOARD_MPS3_CORSTONE300_AN552_NS default "arm/mps3/corstone310/an555" if BOARD_MPS3_CORSTONE310_AN555_NS - default "arm/mps3/corstone310/fvp" if BOARD_MPS3_CORSTONE310_FVP_NS + default "arm/mps3/corstone310/fvp" if BOARD_MPS3_CORSTONE310_FVP_NS + default "arm/mps4/corstone315" if BOARD_MPS4_CORSTONE315_FVP_NS + default "arm/mps4/corstone320" if BOARD_MPS4_CORSTONE320_FVP_NS + default "arm/musca_b1" if BOARD_V2M_MUSCA_B1 + default "arm/musca_s1" if BOARD_V2M_MUSCA_S1 + default "nxp/lpcxpresso55s69" if BOARD_LPCXPRESSO55S69_LPC55S69_CPU0_NS default "stm/b_u585i_iot02a" if BOARD_B_U585I_IOT02A default "stm/nucleo_l552ze_q" if BOARD_NUCLEO_L552ZE_Q default "stm/stm32l562e_dk" if BOARD_STM32L562E_DK - default "arm/musca_b1" if BOARD_V2M_MUSCA_B1 - default "arm/musca_s1" if BOARD_V2M_MUSCA_S1 - default "adi/max32657" if BOARD_MAX32657EVKIT_MAX32657_NS + default "stm/stm32wba65i_dk" if BOARD_NUCLEO_WBA65RI || BOARD_STM32WBA65I_DK1 default "$(ZEPHYR_BASE)/modules/trusted-firmware-m/nordic/nrf9160" if SOC_NRF9160 default "$(ZEPHYR_BASE)/modules/trusted-firmware-m/nordic/nrf9120" if SOC_NRF9120 default "$(ZEPHYR_BASE)/modules/trusted-firmware-m/nordic/nrf5340_cpuapp" if SOC_NRF5340_CPUAPP @@ -307,43 +310,6 @@ config TFM_MCUBOOT_IMAGE_NUMBER updated in one atomic operation. When this is 2, they are split and can be updated independently if dependency requirements are met. -choice TFM_MCUBOOT_PATH - prompt "Path to MCUboot or DOWNLOAD to fetch automatically" - default TFM_MCUBOOT_PATH_LOCAL - help - Path to MCUboot for TF-M builds. The default option - is to use Zephyr's MCUboot module. As an alternative, - users may switch to the 'download' version; in that - case MCUboot will be fetched by the TF-M build during - build time. The default option ensures that Zephyr builds - with TF-M do not fetch external trees. - -config TFM_MCUBOOT_PATH_LOCAL - bool "TF-M to use Zephyr's MCUboot" - help - TF-M builds with BL2 will use the Zephyr's MCUboot version, - which is present in the MCUboot module. - -config TFM_MCUBOOT_PATH_DOWNLOAD - bool "TF-M to automatically download MCUboot during build" - help - TF-M builds with BL2 will let the TF-M build to automatically - fetch and check-out the MCUboot version to use in the build. - -endchoice - -config TFM_ETHOS_DRIVER_PATH_LOCAL - string "Path to a locally available Ethos-U driver or an empty string" - depends on SOC_SERIES_MPS3 || SOC_SERIES_MPS4 - default "$(ZEPHYR_HAL_ETHOS_U_MODULE_DIR)" - help - Path to a locally available Ethos-U driver to be used for TF-M builds or - an empty string to allow TF-M to automatically fetch the Ethos-U - driver from an external repository at build time. - By default Zephyr's Ethos-U driver will be used. It is present in - the hal_ethos_u module. - Alternatively, applications can point to their own paths for Ethos-U driver. - config TFM_QCBOR_PATH string prompt "Path to QCBOR or DOWNLOAD to fetch automatically" @@ -509,6 +475,15 @@ config TFM_SPM_LOG_LEVEL_SILENCE bool "Off" endchoice +config TFM_SECURE_UART + bool "TF-M configure UART instance as secure peripheral" + default y if SOC_FAMILY_NORDIC_NRF && !TFM_LOG_LEVEL_SILENCE + help + Configure the UART instance as a secure peripheral for TF-M logging. + This makes the UART instance unavailable to the non-secure application. + When this option is selected the device tree node for the UART instance + needs to be disabled for the non-secure application. + config TFM_EXCEPTION_INFO_DUMP bool "TF-M exception info dump" default y @@ -516,4 +491,14 @@ config TFM_EXCEPTION_INFO_DUMP On fatal errors in the secure firmware, capture info about the exception. Print the info if the SPM log level is sufficient. +config TFM_STM32_FLASH_LAYOUT_BEGIN_OFFSET + int "Offset gap at beginning of flash layout" + depends on SOC_FAMILY_STM32 + default 0 + help + Set an offset at the beginning of the STM32 platform flash + layout above which TF-M resources location start. The platform uses + this gap for platform specific reason, as for example when a + bootloader that is external to TF-M is used. + endif # BUILD_WITH_TFM diff --git a/scripts/west_commands/sign.py b/scripts/west_commands/sign.py index c6fa273138e5..c90361a1447b 100644 --- a/scripts/west_commands/sign.py +++ b/scripts/west_commands/sign.py @@ -585,8 +585,8 @@ def sign(self, command, build_dir, build_conf, formats): # Non-SOF build does not have extended manifest data for # rimage to process, which might result in rimage error. # So skip it when not doing SOF builds. - is_sof_build = build_conf.getboolean('CONFIG_SOF') - if not is_sof_build: + rimage_schema = build_conf.get('CONFIG_RIMAGE_SIGNING_SCHEMA', None) + if rimage_schema is None: no_manifest = True self.generate_uuid_registry() diff --git a/soc/adi/max32/Kconfig.soc b/soc/adi/max32/Kconfig.soc index e4b2347ca021..7bd66bf2cc70 100644 --- a/soc/adi/max32/Kconfig.soc +++ b/soc/adi/max32/Kconfig.soc @@ -33,6 +33,10 @@ config SOC_MAX32657 bool select SOC_FAMILY_MAX32_M33 +config SOC_MAX32658 + bool + select SOC_MAX32657 + config SOC_MAX32660 bool select SOC_FAMILY_MAX32_M4 @@ -97,6 +101,7 @@ config SOC default "max32650" if SOC_MAX32650 default "max32655" if SOC_MAX32655 default "max32657" if SOC_MAX32657 + default "max32658" if SOC_MAX32658 default "max32660" if SOC_MAX32660 default "max32662" if SOC_MAX32662 default "max32666" if SOC_MAX32666 diff --git a/soc/adi/max32/soc.yml b/soc/adi/max32/soc.yml index 1a4b7c2568d3..270c8c28dfb3 100644 --- a/soc/adi/max32/soc.yml +++ b/soc/adi/max32/soc.yml @@ -9,6 +9,7 @@ family: cpuclusters: - name: m4 - name: max32657 + - name: max32658 - name: max32660 - name: max32662 - name: max32666 diff --git a/soc/intel/intel_adsp/Kconfig b/soc/intel/intel_adsp/Kconfig index 27a8e838b67b..7523f167fad2 100644 --- a/soc/intel/intel_adsp/Kconfig +++ b/soc/intel/intel_adsp/Kconfig @@ -11,6 +11,7 @@ config SOC_FAMILY_INTEL_ADSP select ARCH_HAS_USERSPACE if XTENSA_MMU imply XTENSA_MMU_DOUBLE_MAP select CPU_CACHE_INCOHERENT + select IPC_SERVICE if DT_HAS_INTEL_ADSP_HOST_IPC_ENABLED if SOC_FAMILY_INTEL_ADSP @@ -32,16 +33,20 @@ config INTEL_ADSP_SIM_NO_SECONDARY_CORE_FLOW endif # INTEL_ADSP_SIM -DT_COMPAT_INTEL_ADSP_HOST_IPC := intel,adsp-host-ipc -DT_COMPAT_INTEL_ADSP_IDC := intel,adsp-idc - config INTEL_ADSP_IPC bool "Driver for the host IPC interrupt delivery" - default $(dt_compat_enabled,$(DT_COMPAT_INTEL_ADSP_HOST_IPC)) if !SOF - default $(dt_compat_enabled,$(DT_COMPAT_INTEL_ADSP_IDC)) if !SOF + select DEPRECATED + help + Deprecated config for IPC. Will be removed in the future. + +config INTEL_ADSP_IPC_OLD_INTERFACE + bool "Expose old interface for the IPC" + depends on IPC_SERVICE_BACKEND_INTEL_ADSP_HOST_IPC + default y + select INTEL_ADSP_IPC help - Driver for the host IPC interrupt delivery mechanism. - Currently SOF has its own driver for this hardware. + Expose the old IPC interface (intel_adsp_ipc_* functions) to + maintain backward compatibility. config MEMORY_WIN_0_SIZE int "Size of memory window 0" diff --git a/soc/intel/intel_adsp/Kconfig.defconfig b/soc/intel/intel_adsp/Kconfig.defconfig index 1d8312e7fb6c..f69bc31cd8c7 100644 --- a/soc/intel/intel_adsp/Kconfig.defconfig +++ b/soc/intel/intel_adsp/Kconfig.defconfig @@ -8,11 +8,6 @@ if SOC_FAMILY_INTEL_ADSP rsource "*/Kconfig.defconfig.series" # A workaround for HWMv2 to recover SOF arch/xtensa defaults overridden by arch/host. -if SOF -config CORE_COUNT - int - default MP_MAX_NUM_CPUS -endif config XTENSA_RPO_CACHE def_bool y diff --git a/soc/intel/intel_adsp/common/CMakeLists.txt b/soc/intel/intel_adsp/common/CMakeLists.txt index a39e9ea98e77..9e49bd26eabe 100644 --- a/soc/intel/intel_adsp/common/CMakeLists.txt +++ b/soc/intel/intel_adsp/common/CMakeLists.txt @@ -9,7 +9,7 @@ zephyr_library_named(intel_adsp_common) zephyr_include_directories(include) zephyr_library_include_directories(${ZEPHYR_BASE}/drivers) -zephyr_library_sources_ifdef(CONFIG_INTEL_ADSP_IPC ipc.c) +zephyr_library_sources_ifdef(CONFIG_INTEL_ADSP_IPC_OLD_INTERFACE ipc.c) zephyr_library_sources_ifdef(CONFIG_GDBSTUB gdbstub_backend_sram.c diff --git a/soc/intel/intel_adsp/common/include/intel_adsp_ipc.h b/soc/intel/intel_adsp/common/include/intel_adsp_ipc.h index 1f283466a735..30a8f81360e2 100644 --- a/soc/intel/intel_adsp/common/include/intel_adsp_ipc.h +++ b/soc/intel/intel_adsp/common/include/intel_adsp_ipc.h @@ -9,69 +9,9 @@ #include #include -struct intel_adsp_ipc_config { - volatile struct intel_adsp_ipc *regs; -}; +#include -/** - * @brief Intel ADSP IPC Message Handler Callback. - * - * This function, once registered via intel_adsp_ipc_set_message_handler(), - * is invoked in interrupt context to service messages sent from the - * foreign/connected IPC context. The message contents of the TDR and - * TDD registers are provided in the data/ext_data argument. - * - * The function should return true if processing of the message is - * complete and return notification to the other side (via the TDA - * register) is desired immediately. Returning false means that no - * return "DONE" interrupt will occur until intel_adsp_ipc_complete() is - * called on this device at some point in the future. - * - * @note Further messages on the link will not be transmitted or - * received while an in-progress message remains incomplete! - * - * @param dev IPC device. - * @param arg Registered argument from intel_adsp_ipc_set_message_handler(). - * @param data Message data from other side (low bits of TDR register). - * @param ext_dat Extended message data (TDD register). - * @return true if the message is completely handled. - */ -typedef bool (*intel_adsp_ipc_handler_t)(const struct device *dev, void *arg, - uint32_t data, uint32_t ext_data); - -/** - * @brief Intel ADSP IPC Message Complete Callback. - * - * This function, once registered via intel_adsp_ipc_set_done_handler(), is - * invoked in interrupt context when a "DONE" return interrupt is - * received from the other side of the connection (indicating that a - * previously sent message is finished processing). - * - * @note On Intel ADSP hardware the DONE interrupt is transmitted - * synchronously with the interrupt being cleared on the remote - * device. It is not possible to delay processing. This callback - * will still occur, but protocols which rely on notification of - * asynchronous command processing will need modification. - * - * @param dev IPC device. - * @param arg Registered argument from intel_adsp_ipc_set_done_handler(). - * @return True if IPC completion will be done externally, otherwise false. - * @note Returning True will cause this API to skip writing IPC registers - * signalling IPC message completion and those actions should be done by - * external code manually. Returning false from the handler will perform - * writing to IPC registers signalling message completion normally by this API. - */ -typedef bool (*intel_adsp_ipc_done_t)(const struct device *dev, void *arg); - -struct intel_adsp_ipc_data { - struct k_sem sem; - struct k_spinlock lock; - intel_adsp_ipc_handler_t handle_message; - void *handler_arg; - intel_adsp_ipc_done_t done_notify; - void *done_arg; - bool tx_ack_pending; -}; +#if defined(CONFIG_INTEL_ADSP_IPC_OLD_INTERFACE) || defined(__DOXYGEN__) /** * @brief Register message callback handler. @@ -98,34 +38,27 @@ void intel_adsp_ipc_set_message_handler(const struct device *dev, void intel_adsp_ipc_set_done_handler(const struct device *dev, intel_adsp_ipc_done_t fn, void *arg); -/** @brief Initialize Intel ADSP IPC device. - * - * Initialize the device. Must be called before any API calls or - * interrupts can be serviced. - * - * @param dev IPC device. - * @return Zero on success, negative codes for error. - */ -int intel_adsp_ipc_init(const struct device *dev); - -/** @brief Complete an in-progress message. +/** + * @brief Complete an in-progress message. * * Notify the other side that the current in-progress message is * complete. This is a noop if no message is in progress. * * @note Further messages on the link will not be transmitted or - * received while an in-progress message remains incomplete! + * received while an in-progress message remains incomplete! * * @param dev IPC device. */ void intel_adsp_ipc_complete(const struct device *dev); -/** @brief Message-in-progress predicate. +/** + * @brief Message-in-progress predicate. * * Returns false if a message has been received but not yet completed * via intel_adsp_ipc_complete(), true otherwise. * * @param dev IPC device. + * * @return True if no message is in progress. */ bool intel_adsp_ipc_is_complete(const struct device *dev); @@ -175,38 +108,6 @@ int intel_adsp_ipc_send_message_sync(const struct device *dev, void intel_adsp_ipc_send_message_emergency(const struct device *dev, uint32_t data, uint32_t ext_data); -#ifdef CONFIG_PM_DEVICE - -typedef int (*intel_adsp_ipc_resume_handler_t)(const struct device *dev, void *arg); - -typedef int (*intel_adsp_ipc_suspend_handler_t)(const struct device *dev, void *arg); - -/** - * @brief Registers resume callback handler used to resume Device from suspended state. - * - * @param dev IPC device. - * @param fn Callback function. - * @param arg Value to pass as the "arg" parameter to the function. - */ -void intel_adsp_ipc_set_resume_handler(const struct device *dev, - intel_adsp_ipc_resume_handler_t fn, void *arg); - -/** - * @brief Registers suspend callback handler used to suspend active Device. - * - * @param dev IPC device. - * @param fn Callback function. - * @param arg Value to pass as the "arg" parameter to the function. - */ -void intel_adsp_ipc_set_suspend_handler(const struct device *dev, - intel_adsp_ipc_suspend_handler_t fn, void *arg); - -struct ipc_control_driver_api { - intel_adsp_ipc_resume_handler_t resume_fn; - void *resume_fn_args; - intel_adsp_ipc_suspend_handler_t suspend_fn; - void *suspend_fn_args; -}; +#endif /* CONFIG_INTEL_ADSP_IPC_OLD_INTERFACE */ -#endif /* CONFIG_PM_DEVICE */ #endif /* ZEPHYR_INCLUDE_INTEL_ADSP_IPC_H */ diff --git a/soc/intel/intel_adsp/common/ipc.c b/soc/intel/intel_adsp/common/ipc.c index bceee1b7c2a2..aff2c2f70ee6 100644 --- a/soc/intel/intel_adsp/common/ipc.c +++ b/soc/intel/intel_adsp/common/ipc.c @@ -1,20 +1,23 @@ -/* Copyright (c) 2022 Intel Corporation +/* + * Copyright (c) 2022, 2025 Intel Corporation + * * SPDX-License-Identifier: Apache-2.0 */ - #include -#include -#include -#include -#include -#include -#include -#include -#include #include -void intel_adsp_ipc_set_message_handler(const struct device *dev, - intel_adsp_ipc_handler_t fn, void *arg) +#include +#include + +#include +#include + +static struct ipc_ept intel_adsp_ipc_ept; +static struct intel_adsp_ipc_ept_priv_data intel_adsp_ipc_priv_data; +static struct ipc_ept_cfg intel_adsp_ipc_ept_cfg; + +void intel_adsp_ipc_set_message_handler(const struct device *dev, intel_adsp_ipc_handler_t fn, + void *arg) { struct intel_adsp_ipc_data *devdata = dev->data; k_spinlock_key_t key = k_spin_lock(&devdata->lock); @@ -24,8 +27,7 @@ void intel_adsp_ipc_set_message_handler(const struct device *dev, k_spin_unlock(&devdata->lock, key); } -void intel_adsp_ipc_set_done_handler(const struct device *dev, - intel_adsp_ipc_done_t fn, void *arg) +void intel_adsp_ipc_set_done_handler(const struct device *dev, intel_adsp_ipc_done_t fn, void *arg) { struct intel_adsp_ipc_data *devdata = dev->data; k_spinlock_key_t key = k_spin_lock(&devdata->lock); @@ -35,314 +37,121 @@ void intel_adsp_ipc_set_done_handler(const struct device *dev, k_spin_unlock(&devdata->lock, key); } -static void intel_adsp_ipc_isr(const void *devarg) +static void intel_adsp_ipc_receive_cb(const void *data, size_t len, void *priv) { - const struct device *dev = devarg; - const struct intel_adsp_ipc_config *config = dev->config; + const struct device *dev = INTEL_ADSP_IPC_HOST_DEV; struct intel_adsp_ipc_data *devdata = dev->data; + struct intel_adsp_ipc_ept_priv_data *priv_data = + (struct intel_adsp_ipc_ept_priv_data *)priv; + bool done = true; - volatile struct intel_adsp_ipc *regs = config->regs; - k_spinlock_key_t key = k_spin_lock(&devdata->lock); - - if (regs->tdr & INTEL_ADSP_IPC_BUSY) { - bool done = true; + if (len == INTEL_ADSP_IPC_CB_MSG) { + const struct intel_adsp_ipc_msg *msg = (const struct intel_adsp_ipc_msg *)data; if (devdata->handle_message != NULL) { - uint32_t msg = regs->tdr & ~INTEL_ADSP_IPC_BUSY; - uint32_t ext = regs->tdd; - - done = devdata->handle_message(dev, devdata->handler_arg, msg, ext); + done = devdata->handle_message(dev, devdata->handler_arg, msg->data, + msg->ext_data); } - regs->tdr = INTEL_ADSP_IPC_BUSY; if (done) { -#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE - regs->tda = INTEL_ADSP_IPC_ACE1X_TDA_DONE; -#else - regs->tda = INTEL_ADSP_IPC_DONE; -#endif + priv_data->cb_ret = INTEL_ADSP_IPC_CB_RET_OKAY; + } else { + priv_data->cb_ret = -EBADMSG; } - } - - /* Same signal, but on different bits in 1.5 */ - bool done = (regs->ida & INTEL_ADSP_IPC_DONE); - - if (done) { + } else if (len == INTEL_ADSP_IPC_CB_DONE) { bool external_completion = false; if (devdata->done_notify != NULL) { external_completion = devdata->done_notify(dev, devdata->done_arg); } - devdata->tx_ack_pending = false; - /* Allow the system to enter the runtime idle state after the IPC acknowledgment - * is received. - */ - pm_policy_state_lock_put(PM_STATE_RUNTIME_IDLE, PM_ALL_SUBSTATES); - k_sem_give(&devdata->sem); - - /* IPC completion registers will be set externally */ + if (external_completion) { - k_spin_unlock(&devdata->lock, key); - return; + priv_data->cb_ret = INTEL_ADSP_IPC_CB_RET_EXT_COMPLETE; + } else { + priv_data->cb_ret = INTEL_ADSP_IPC_CB_RET_OKAY; } - - regs->ida = INTEL_ADSP_IPC_DONE; } - - k_spin_unlock(&devdata->lock, key); -} - -int intel_adsp_ipc_init(const struct device *dev) -{ - pm_device_busy_set(dev); - struct intel_adsp_ipc_data *devdata = dev->data; - const struct intel_adsp_ipc_config *config = dev->config; - - memset(devdata, 0, sizeof(*devdata)); - - k_sem_init(&devdata->sem, 0, 1); - - /* ACK any latched interrupts (including TDA to clear IDA on - * the other side!), then enable. - */ - config->regs->tdr = INTEL_ADSP_IPC_BUSY; - config->regs->ida = INTEL_ADSP_IPC_DONE; -#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE - config->regs->tda = INTEL_ADSP_IPC_ACE1X_TDA_DONE; -#else - config->regs->tda = INTEL_ADSP_IPC_DONE; -#endif - config->regs->ctl |= (INTEL_ADSP_IPC_CTL_IDIE | INTEL_ADSP_IPC_CTL_TBIE); - pm_device_busy_clear(dev); - - return 0; } void intel_adsp_ipc_complete(const struct device *dev) { - const struct intel_adsp_ipc_config *config = dev->config; + int ret; -#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE - config->regs->tda = INTEL_ADSP_IPC_ACE1X_TDA_DONE; -#else - config->regs->tda = INTEL_ADSP_IPC_DONE; -#endif + ret = ipc_service_send(&intel_adsp_ipc_ept, NULL, INTEL_ADSP_IPC_SEND_DONE); + + ARG_UNUSED(ret); } bool intel_adsp_ipc_is_complete(const struct device *dev) { - const struct intel_adsp_ipc_config *config = dev->config; - const struct intel_adsp_ipc_data *devdata = dev->data; - bool not_busy = (config->regs->idr & INTEL_ADSP_IPC_BUSY) == 0; + int ret; + + ret = ipc_service_send(&intel_adsp_ipc_ept, NULL, INTEL_ADSP_IPC_SEND_IS_COMPLETE); - return not_busy && !devdata->tx_ack_pending; + return ret == 0; } -int intel_adsp_ipc_send_message(const struct device *dev, - uint32_t data, uint32_t ext_data) +int intel_adsp_ipc_send_message(const struct device *dev, uint32_t data, uint32_t ext_data) { -#ifdef CONFIG_PM_DEVICE - enum pm_device_state current_state; + struct intel_adsp_ipc_msg msg = {.data = data, .ext_data = ext_data}; + int ret; - if (pm_device_state_get(INTEL_ADSP_IPC_HOST_DEV, ¤t_state) != 0 || - current_state != PM_DEVICE_STATE_ACTIVE) { - return -ESHUTDOWN; - } -#endif + ret = ipc_service_send(&intel_adsp_ipc_ept, &msg, INTEL_ADSP_IPC_SEND_MSG); - pm_device_busy_set(dev); - const struct intel_adsp_ipc_config *config = dev->config; - struct intel_adsp_ipc_data *devdata = dev->data; - k_spinlock_key_t key = k_spin_lock(&devdata->lock); - - if ((config->regs->idr & INTEL_ADSP_IPC_BUSY) != 0 || devdata->tx_ack_pending) { - k_spin_unlock(&devdata->lock, key); - return -EBUSY; + if (ret < 0) { + return ret; } - k_sem_reset(&devdata->sem); - /* Prevent entering runtime idle state until IPC acknowledgment is received. */ - pm_policy_state_lock_get(PM_STATE_RUNTIME_IDLE, PM_ALL_SUBSTATES); - devdata->tx_ack_pending = true; - config->regs->idd = ext_data; - config->regs->idr = data | INTEL_ADSP_IPC_BUSY; - k_spin_unlock(&devdata->lock, key); - pm_device_busy_clear(dev); return 0; } -int intel_adsp_ipc_send_message_sync(const struct device *dev, - uint32_t data, uint32_t ext_data, - k_timeout_t timeout) +int intel_adsp_ipc_send_message_sync(const struct device *dev, uint32_t data, uint32_t ext_data, + k_timeout_t timeout) { - struct intel_adsp_ipc_data *devdata = dev->data; + struct intel_adsp_ipc_msg msg = { + .data = data, + .ext_data = ext_data, + .timeout = timeout, + }; + int ret; - int ret = intel_adsp_ipc_send_message(dev, data, ext_data); + ret = ipc_service_send(&intel_adsp_ipc_ept, &msg, INTEL_ADSP_IPC_SEND_MSG_SYNC); - if (!ret) { - k_sem_take(&devdata->sem, timeout); + if (ret < 0) { + return ret; } - return ret; + + return 0; } void intel_adsp_ipc_send_message_emergency(const struct device *dev, uint32_t data, uint32_t ext_data) { - const struct intel_adsp_ipc_config * const config = dev->config; - - volatile struct intel_adsp_ipc * const regs = config->regs; - bool done; - - /* check if host is processing message. */ - while (regs->idr & INTEL_ADSP_IPC_BUSY) { - k_busy_wait(1); - } - - /* check if host has pending acknowledge msg - * Same signal, but on different bits in 1.5 - */ - done = regs->ida & INTEL_ADSP_IPC_DONE; - if (done) { - /* IPC completion */ - regs->ida = INTEL_ADSP_IPC_DONE; - } - - regs->idd = ext_data; - regs->idr = data | INTEL_ADSP_IPC_BUSY; -} - -#if DT_NODE_EXISTS(INTEL_ADSP_IPC_HOST_DTNODE) - -#if defined(CONFIG_SOC_SERIES_INTEL_ADSP_ACE) -static inline void ace_ipc_intc_unmask(void) -{ - ACE_DINT[0].ie[ACE_INTL_HIPC] = BIT(0); -} -#else -static inline void ace_ipc_intc_unmask(void) {} -#endif - -static int dt_init(const struct device *dev) -{ - IRQ_CONNECT(DT_IRQN(INTEL_ADSP_IPC_HOST_DTNODE), 0, intel_adsp_ipc_isr, - INTEL_ADSP_IPC_HOST_DEV, 0); - irq_enable(DT_IRQN(INTEL_ADSP_IPC_HOST_DTNODE)); - - ace_ipc_intc_unmask(); - - return intel_adsp_ipc_init(dev); -} - -#ifdef CONFIG_PM_DEVICE - -void intel_adsp_ipc_set_resume_handler(const struct device *dev, - intel_adsp_ipc_resume_handler_t fn, void *arg) -{ - struct ipc_control_driver_api *api = - (struct ipc_control_driver_api *)dev->api; - struct intel_adsp_ipc_data *devdata = dev->data; - k_spinlock_key_t key = k_spin_lock(&devdata->lock); + struct intel_adsp_ipc_msg msg = {.data = data, .ext_data = ext_data}; + int ret; - api->resume_fn = fn; - api->resume_fn_args = arg; + ret = ipc_service_send(&intel_adsp_ipc_ept, &msg, INTEL_ADSP_IPC_SEND_MSG_EMERGENCY); - k_spin_unlock(&devdata->lock, key); + ARG_UNUSED(ret); } -void intel_adsp_ipc_set_suspend_handler(const struct device *dev, - intel_adsp_ipc_suspend_handler_t fn, void *arg) -{ - struct ipc_control_driver_api *api = - (struct ipc_control_driver_api *)dev->api; - struct intel_adsp_ipc_data *devdata = dev->data; - k_spinlock_key_t key = k_spin_lock(&devdata->lock); - - api->suspend_fn = fn; - api->suspend_fn_args = arg; - - k_spin_unlock(&devdata->lock, key); -} +static struct ipc_ept_cfg intel_adsp_ipc_ept_cfg = { + .name = "intel_adsp_ipc_ept", + .cb = { + .received = intel_adsp_ipc_receive_cb, + }, + .priv = (void *)&intel_adsp_ipc_priv_data, +}; -/** - * @brief Manages IPC driver power state change. - * - * @param dev IPC device. - * @param action Power state to be changed to. - * @return int Returns 0 on success or optionaly error code from the - * registered ipc_power_control_api callbacks. - * - * @note PM lock is taken at the start of each power transition to prevent concurrent calls - * to @ref pm_device_action_run function. - * If IPC Device performs hardware operation and device is busy (what should not happen) - * function returns failure. It is API user responsibility to make sure we are not entering - * device power transition while device is busy. - */ -static int ipc_pm_action(const struct device *dev, enum pm_device_action action) +static int intel_adsp_ipc_old_init(void) { - if (pm_device_is_busy(INTEL_ADSP_IPC_HOST_DEV)) { - return -EBUSY; - } - - const struct ipc_control_driver_api *api = - (const struct ipc_control_driver_api *)dev->api; + int ret; + const struct device *ipc_dev = INTEL_ADSP_IPC_HOST_DEV; - int ret = 0; - - switch (action) { - case PM_DEVICE_ACTION_SUSPEND: - if (api->suspend_fn) { - ret = api->suspend_fn(dev, api->suspend_fn_args); - if (!ret) { - irq_disable(DT_IRQN(INTEL_ADSP_IPC_HOST_DTNODE)); - } - } - break; - case PM_DEVICE_ACTION_RESUME: - irq_enable(DT_IRQN(INTEL_ADSP_IPC_HOST_DTNODE)); - if (!irq_is_enabled(DT_IRQN(INTEL_ADSP_IPC_HOST_DTNODE))) { - ret = -EINTR; - break; - } - ace_ipc_intc_unmask(); - ret = intel_adsp_ipc_init(dev); - if (ret) { - break; - } - if (api->resume_fn) { - ret = api->resume_fn(dev, api->resume_fn_args); - } - break; - default: - /* Return as default value when given PM action is not supported */ - return -ENOTSUP; - } + ret = ipc_service_register_endpoint(ipc_dev, &intel_adsp_ipc_ept, &intel_adsp_ipc_ept_cfg); return ret; } -/** - * @brief Callback functions to be executed by Zephyr application - * during IPC device suspend and resume. - */ -static struct ipc_control_driver_api ipc_power_control_api = { - .resume_fn = NULL, - .resume_fn_args = NULL, - .suspend_fn = NULL, - .suspend_fn_args = NULL -}; - -PM_DEVICE_DT_DEFINE(INTEL_ADSP_IPC_HOST_DTNODE, ipc_pm_action); - -#endif /* CONFIG_PM_DEVICE */ - -static const struct intel_adsp_ipc_config ipc_host_config = { - .regs = (void *)INTEL_ADSP_IPC_REG_ADDRESS, -}; - -static struct intel_adsp_ipc_data ipc_host_data; - -DEVICE_DT_DEFINE(INTEL_ADSP_IPC_HOST_DTNODE, dt_init, PM_DEVICE_DT_GET(INTEL_ADSP_IPC_HOST_DTNODE), - &ipc_host_data, &ipc_host_config, PRE_KERNEL_2, 0, COND_CODE_1(CONFIG_PM_DEVICE, - (&ipc_power_control_api), (NULL))); - -#endif /* DT_NODE_EXISTS(INTEL_ADSP_IPC_HOST_DTNODE) */ +/* Backend is at PRE_KERNEL_2:0, so we need to init after that. */ +SYS_INIT(intel_adsp_ipc_old_init, PRE_KERNEL_2, 1); diff --git a/submanifests/optional.yaml b/submanifests/optional.yaml index 57ad7affdd1c..a97aded1f717 100644 --- a/submanifests/optional.yaml +++ b/submanifests/optional.yaml @@ -22,24 +22,6 @@ manifest: remote: upstream groups: - optional - - name: psa-arch-tests - revision: 2cadb02a72eacda7042505dcbdd492371e8ce024 - path: modules/tee/tf-m/psa-arch-tests - remote: upstream - groups: - - optional - - name: sof - revision: ba8de7551f88a4f8d4533791274fa85b37ec332e - path: modules/audio/sof - remote: upstream - groups: - - optional - - name: tf-m-tests - revision: a90702bcb8fadb6f70daf0ffbb13888dfe63fc99 - path: modules/tee/tf-m/tf-m-tests - remote: upstream - groups: - - optional - name: tflite-micro revision: 8d404de73acf7687831e16d88e86e4f73cfddf8e path: optional/modules/lib/tflite-micro diff --git a/subsys/ipc/ipc_service/backends/CMakeLists.txt b/subsys/ipc/ipc_service/backends/CMakeLists.txt index d6ca8fb76c33..37c62b88e000 100644 --- a/subsys/ipc/ipc_service/backends/CMakeLists.txt +++ b/subsys/ipc/ipc_service/backends/CMakeLists.txt @@ -4,4 +4,5 @@ zephyr_sources_ifdef(CONFIG_IPC_SERVICE_BACKEND_ICMSG ipc_icmsg.c) zephyr_sources_ifdef(CONFIG_IPC_SERVICE_BACKEND_ICMSG_ME_INITIATOR ipc_icmsg_me_initiator.c) zephyr_sources_ifdef(CONFIG_IPC_SERVICE_BACKEND_ICMSG_ME_FOLLOWER ipc_icmsg_me_follower.c) zephyr_sources_ifdef(CONFIG_IPC_SERVICE_BACKEND_ICBMSG ipc_icbmsg.c) +zephyr_sources_ifdef(CONFIG_IPC_SERVICE_BACKEND_INTEL_ADSP_HOST_IPC ipc_intel_adsp_host_ipc.c) zephyr_sources_ifdef(CONFIG_IPC_SERVICE_BACKEND_RPMSG ipc_rpmsg_static_vrings.c) diff --git a/subsys/ipc/ipc_service/backends/Kconfig b/subsys/ipc/ipc_service/backends/Kconfig index bb8b444898f9..5677c609d410 100644 --- a/subsys/ipc/ipc_service/backends/Kconfig +++ b/subsys/ipc/ipc_service/backends/Kconfig @@ -50,4 +50,5 @@ config IPC_SERVICE_BACKEND_ICMSG_ME_FOLLOWER rsource "Kconfig.icmsg_me" rsource "Kconfig.icbmsg" +rsource "Kconfig.intel_adsp" rsource "Kconfig.rpmsg" diff --git a/subsys/ipc/ipc_service/backends/Kconfig.intel_adsp b/subsys/ipc/ipc_service/backends/Kconfig.intel_adsp new file mode 100644 index 000000000000..47a884310d7a --- /dev/null +++ b/subsys/ipc/ipc_service/backends/Kconfig.intel_adsp @@ -0,0 +1,11 @@ +# +# Copyright (c) 2025 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 +# + +config IPC_SERVICE_BACKEND_INTEL_ADSP_HOST_IPC + bool "Backend for the Intel Audio DSP Host IPC" + default DT_HAS_INTEL_ADSP_HOST_IPC_ENABLED + help + IPC Service Backend for Intel Audio DSP Host IPC. diff --git a/subsys/ipc/ipc_service/backends/ipc_intel_adsp_host_ipc.c b/subsys/ipc/ipc_service/backends/ipc_intel_adsp_host_ipc.c new file mode 100644 index 000000000000..274e13c9ea6d --- /dev/null +++ b/subsys/ipc/ipc_service/backends/ipc_intel_adsp_host_ipc.c @@ -0,0 +1,464 @@ +/* + * Copyright (c) 2022, 2025 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * + * @brief IPC service backend for Intel Audio DSP host IPC + * + * @note When declaring struct ipt_ept_cfg, the field priv must point to + * a struct intel_adsp_ipc_ept_priv_data. This is used for passing + * callback returns. + * + * @note For sending message and the received callback, the data and len + * arguments are not used to represent a byte array. Instead, + * the data argument points to the descriptor of data to be sent + * (of struct intel_adsp_ipc_msg). The len argument represents + * the type of message to be sent (enum intel_adsp_send_len) and + * the type of callback (enum intel_adsp_cb_len). + */ + +#define DT_DRV_COMPAT intel_adsp_host_ipc + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +static inline void ace_ipc_intc_mask(void) +{ +#if defined(CONFIG_SOC_SERIES_INTEL_ADSP_ACE) + ACE_DINT[0].ie[ACE_INTL_HIPC] = ACE_DINT[0].ie[ACE_INTL_HIPC] & ~BIT(0); +#endif +} + +static inline void ace_ipc_intc_unmask(void) +{ +#if defined(CONFIG_SOC_SERIES_INTEL_ADSP_ACE) + ACE_DINT[0].ie[ACE_INTL_HIPC] = BIT(0); +#endif +} + +static void intel_adsp_ipc_isr(const void *devarg) +{ + const struct device *dev = devarg; + const struct intel_adsp_ipc_config *config = dev->config; + struct intel_adsp_ipc_data *devdata = dev->data; + const struct ipc_ept_cfg *ept_cfg = devdata->ept_cfg; + + struct intel_adsp_ipc_ept_priv_data *priv_data = + (struct intel_adsp_ipc_ept_priv_data *)ept_cfg->priv; + + volatile struct intel_adsp_ipc *regs = config->regs; + k_spinlock_key_t key = k_spin_lock(&devdata->lock); + + if (regs->tdr & INTEL_ADSP_IPC_BUSY) { + bool done = true; + + if (ept_cfg->cb.received != NULL) { + struct intel_adsp_ipc_msg cb_msg = { + .data = regs->tdr & ~INTEL_ADSP_IPC_BUSY, + .ext_data = regs->tdd, + }; + + ept_cfg->cb.received(&cb_msg, INTEL_ADSP_IPC_CB_MSG, ept_cfg->priv); + + done = (priv_data->cb_ret == INTEL_ADSP_IPC_CB_RET_OKAY); + } + + regs->tdr = INTEL_ADSP_IPC_BUSY; + if (done) { +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE + regs->tda = INTEL_ADSP_IPC_ACE1X_TDA_DONE; +#else + regs->tda = INTEL_ADSP_IPC_DONE; +#endif + } + } + + /* Same signal, but on different bits in 1.5 */ + bool done = (regs->ida & INTEL_ADSP_IPC_DONE); + + if (done) { + bool external_completion = false; + + if (ept_cfg->cb.received != NULL) { + ept_cfg->cb.received(NULL, INTEL_ADSP_IPC_CB_DONE, ept_cfg->priv); + + if (priv_data->cb_ret == INTEL_ADSP_IPC_CB_RET_EXT_COMPLETE) { + external_completion = true; + } + } + + devdata->tx_ack_pending = false; + + /* + * Allow the system to enter the runtime idle state after the IPC acknowledgment + * is received. + */ + pm_policy_state_lock_put(PM_STATE_RUNTIME_IDLE, PM_ALL_SUBSTATES); + k_sem_give(&devdata->sem); + + /* IPC completion registers will be set externally. */ + if (external_completion) { + k_spin_unlock(&devdata->lock, key); + return; + } + + regs->ida = INTEL_ADSP_IPC_DONE; + } + + k_spin_unlock(&devdata->lock, key); +} + +int intel_adsp_ipc_init(const struct device *dev) +{ + pm_device_busy_set(dev); + struct intel_adsp_ipc_data *devdata = dev->data; + const struct intel_adsp_ipc_config *config = dev->config; + + k_sem_init(&devdata->sem, 0, 1); + + /* ACK any latched interrupts (including TDA to clear IDA on + * the other side!), then enable. + */ + config->regs->tdr = INTEL_ADSP_IPC_BUSY; + config->regs->ida = INTEL_ADSP_IPC_DONE; +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE + config->regs->tda = INTEL_ADSP_IPC_ACE1X_TDA_DONE; +#else + config->regs->tda = INTEL_ADSP_IPC_DONE; +#endif + config->regs->ctl |= (INTEL_ADSP_IPC_CTL_IDIE | INTEL_ADSP_IPC_CTL_TBIE); + pm_device_busy_clear(dev); + + return 0; +} + +static int intel_adsp_ipc_register_ept(const struct device *instance, void **token, + const struct ipc_ept_cfg *cfg) +{ + struct intel_adsp_ipc_data *data = instance->data; + + data->ept_cfg = cfg; + + irq_enable(DT_IRQN(INTEL_ADSP_IPC_HOST_DTNODE)); + ace_ipc_intc_unmask(); + + return 0; +} + +static int intel_adsp_ipc_deregister_ept(const struct device *instance, void *token) +{ + struct intel_adsp_ipc_data *data = instance->data; + + data->ept_cfg = NULL; + + ace_ipc_intc_mask(); + irq_disable(DT_IRQN(INTEL_ADSP_IPC_HOST_DTNODE)); + + return 0; +} + +static void ipc_complete(const struct device *dev) +{ + const struct intel_adsp_ipc_config *config = dev->config; + +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE + config->regs->tda = INTEL_ADSP_IPC_ACE1X_TDA_DONE; +#else + config->regs->tda = INTEL_ADSP_IPC_DONE; +#endif +} + +static bool ipc_is_complete(const struct device *dev) +{ + const struct intel_adsp_ipc_config *config = dev->config; + const struct intel_adsp_ipc_data *devdata = dev->data; + bool not_busy = (config->regs->idr & INTEL_ADSP_IPC_BUSY) == 0; + + return not_busy && !devdata->tx_ack_pending; +} + +static int ipc_send_message(const struct device *dev, uint32_t data, uint32_t ext_data) +{ +#ifdef CONFIG_PM_DEVICE + enum pm_device_state current_state; + + if (pm_device_state_get(INTEL_ADSP_IPC_HOST_DEV, ¤t_state) != 0 || + current_state != PM_DEVICE_STATE_ACTIVE) { + return -ESHUTDOWN; + } +#endif + + pm_device_busy_set(dev); + const struct intel_adsp_ipc_config *config = dev->config; + struct intel_adsp_ipc_data *devdata = dev->data; + k_spinlock_key_t key = k_spin_lock(&devdata->lock); + + if ((config->regs->idr & INTEL_ADSP_IPC_BUSY) != 0 || devdata->tx_ack_pending) { + k_spin_unlock(&devdata->lock, key); + return -EBUSY; + } + + k_sem_reset(&devdata->sem); + + /* Prevent entering runtime idle state until IPC acknowledgment is received. */ + pm_policy_state_lock_get(PM_STATE_RUNTIME_IDLE, PM_ALL_SUBSTATES); + + devdata->tx_ack_pending = true; + + config->regs->idd = ext_data; + config->regs->idr = data | INTEL_ADSP_IPC_BUSY; + + k_spin_unlock(&devdata->lock, key); + + pm_device_busy_clear(dev); + + return 0; +} + +static int ipc_send_message_sync(const struct device *dev, uint32_t data, uint32_t ext_data, + k_timeout_t timeout) +{ + struct intel_adsp_ipc_data *devdata = dev->data; + + int ret = ipc_send_message(dev, data, ext_data); + + if (ret == 0) { + k_sem_take(&devdata->sem, timeout); + } + + return ret; +} + +static int ipc_send_message_emergency(const struct device *dev, uint32_t data, uint32_t ext_data) +{ + const struct intel_adsp_ipc_config *const config = dev->config; + + volatile struct intel_adsp_ipc *const regs = config->regs; + bool done; + + /* check if host is processing message. */ + while (regs->idr & INTEL_ADSP_IPC_BUSY) { + k_busy_wait(1); + } + + /* check if host has pending acknowledge msg + * Same signal, but on different bits in 1.5 + */ + done = regs->ida & INTEL_ADSP_IPC_DONE; + if (done) { + /* IPC completion */ + regs->ida = INTEL_ADSP_IPC_DONE; + } + + regs->idd = ext_data; + regs->idr = data | INTEL_ADSP_IPC_BUSY; + + return 0; +} + +/** + * @brief Send an IPC message. + * + * This implements the inner working of ipc_service_send(). + * + * @note Arguments @a data and @a len are not used to point to a byte buffer of data + * to be sent. Instead, @a data must point to a descriptor of data to be sent, + * struct intel_adsp_ipc_msg. And @a len indicates what type of message to send + * as described in enum intel_adsp_send_len. + * + * Return values for various message types: + * - For INTEL_ADSP_IPC_SEND_MSG_*, returns 0 when message is sent. Negative errno if + * errors. + * - For INTEL_ADSP_IPC_SEND_DONE, always returns 0 for sending DONE message. + * - For INTEL_ADSP_IPC_SEND_IS_COMPLETE, returns 0 if host has processed the message. + * -EAGAIN if not. + * + * @param[in] dev Pointer to device struct. + * @param[in] token Backend-specific token. + * @param[in] data Descriptor of IPC message to be sent (as struct intel_adsp_ipc_msg). + * @param[in] len Type of message to be sent (described in enum intel_adsp_send_len). + * + * @return 0 if message is sent successfully or query returns okay. + * Negative errno otherwise. + */ +static int intel_adsp_ipc_send(const struct device *dev, void *token, const void *data, size_t len) +{ + int ret; + + const struct intel_adsp_ipc_msg *msg = (const struct intel_adsp_ipc_msg *)data; + + switch (len) { + case INTEL_ADSP_IPC_SEND_MSG: { + ret = ipc_send_message(dev, msg->data, msg->ext_data); + + break; + } + case INTEL_ADSP_IPC_SEND_MSG_SYNC: { + ret = ipc_send_message_sync(dev, msg->data, msg->ext_data, msg->timeout); + + break; + } + case INTEL_ADSP_IPC_SEND_MSG_EMERGENCY: { + ret = ipc_send_message_emergency(dev, msg->data, msg->ext_data); + + break; + } + case INTEL_ADSP_IPC_SEND_DONE: { + ipc_complete(dev); + + ret = 0; + + break; + } + case INTEL_ADSP_IPC_SEND_IS_COMPLETE: { + bool completed = ipc_is_complete(dev); + + if (completed) { + ret = 0; + } else { + ret = -EAGAIN; + } + + break; + } + default: + ret = -EBADMSG; + + break; + } + + return ret; +} + +static int intel_adsp_ipc_dt_init(const struct device *dev) +{ + struct intel_adsp_ipc_data *devdata = dev->data; + + memset(devdata, 0, sizeof(*devdata)); + + IRQ_CONNECT(DT_IRQN(INTEL_ADSP_IPC_HOST_DTNODE), 0, intel_adsp_ipc_isr, + INTEL_ADSP_IPC_HOST_DEV, 0); + + return intel_adsp_ipc_init(dev); +} + +#ifdef CONFIG_PM_DEVICE + +void intel_adsp_ipc_set_resume_handler(const struct device *dev, intel_adsp_ipc_resume_handler_t fn, + void *arg) +{ + struct intel_adsp_ipc_data *devdata = dev->data; + k_spinlock_key_t key = k_spin_lock(&devdata->lock); + + devdata->resume_fn = fn; + devdata->resume_fn_args = arg; + + k_spin_unlock(&devdata->lock, key); +} + +void intel_adsp_ipc_set_suspend_handler(const struct device *dev, + intel_adsp_ipc_suspend_handler_t fn, void *arg) +{ + struct intel_adsp_ipc_data *devdata = dev->data; + k_spinlock_key_t key = k_spin_lock(&devdata->lock); + + devdata->suspend_fn = fn; + devdata->suspend_fn_args = arg; + + k_spin_unlock(&devdata->lock, key); +} + +/** + * @brief Manages IPC driver power state change. + * + * @param dev IPC device. + * @param action Power state to be changed to. + * + * @return int Returns 0 on success or optionaly error code from the + * registered ipc_power_control_api callbacks. + * + * @note PM lock is taken at the start of each power transition to prevent concurrent calls + * to @ref pm_device_action_run function. + * If IPC Device performs hardware operation and device is busy (what should not happen) + * function returns failure. It is API user responsibility to make sure we are not entering + * device power transition while device is busy. + */ +static int ipc_pm_action(const struct device *dev, enum pm_device_action action) +{ + if (pm_device_is_busy(INTEL_ADSP_IPC_HOST_DEV)) { + return -EBUSY; + } + + struct intel_adsp_ipc_data *devdata = dev->data; + + int ret = 0; + + switch (action) { + case PM_DEVICE_ACTION_SUSPEND: + if (devdata->suspend_fn) { + ret = devdata->suspend_fn(dev, devdata->suspend_fn_args); + if (!ret) { + irq_disable(DT_IRQN(INTEL_ADSP_IPC_HOST_DTNODE)); + } + } + break; + case PM_DEVICE_ACTION_RESUME: + irq_enable(DT_IRQN(INTEL_ADSP_IPC_HOST_DTNODE)); + if (!irq_is_enabled(DT_IRQN(INTEL_ADSP_IPC_HOST_DTNODE))) { + ret = -EINTR; + break; + } + ace_ipc_intc_unmask(); + ret = intel_adsp_ipc_init(dev); + if (ret) { + break; + } + if (devdata->resume_fn) { + ret = devdata->resume_fn(dev, devdata->resume_fn_args); + } + break; + default: + /* Return as default value when given PM action is not supported */ + return -ENOTSUP; + } + + return ret; +} + +PM_DEVICE_DT_DEFINE(INTEL_ADSP_IPC_HOST_DTNODE, ipc_pm_action); + +#endif /* CONFIG_PM_DEVICE */ + +static const struct intel_adsp_ipc_config ipc_host_config = { + .regs = (void *)INTEL_ADSP_IPC_REG_ADDRESS, +}; + +static struct intel_adsp_ipc_data ipc_host_data; + +const static struct ipc_service_backend intel_adsp_ipc_backend_api = { + .send = intel_adsp_ipc_send, + .register_endpoint = intel_adsp_ipc_register_ept, + .deregister_endpoint = intel_adsp_ipc_deregister_ept, +}; + +DEVICE_DT_DEFINE(INTEL_ADSP_IPC_HOST_DTNODE, intel_adsp_ipc_dt_init, + PM_DEVICE_DT_GET(INTEL_ADSP_IPC_HOST_DTNODE), &ipc_host_data, &ipc_host_config, + PRE_KERNEL_2, 0, &intel_adsp_ipc_backend_api); diff --git a/west.yml b/west.yml index b9a1a35b79e9..417337854e95 100644 --- a/west.yml +++ b/west.yml @@ -24,7 +24,7 @@ manifest: - name: babblesim url-base: https://github.com/BabbleSim - group-filter: [-babblesim, -optional] + group-filter: [-babblesim, -optional, -testing] # # Please add items below based on alphabetical order @@ -352,19 +352,30 @@ manifest: - debug - name: picolibc path: modules/lib/picolibc - revision: 560946f26db075c296beea5b39d99e6de43c9010 + revision: ca8b6ebba5226a75545e57a140443168a26ba664 + - name: psa-arch-tests + revision: 941cd8436a2e0f1da9d8584b83a403930826899d + path: modules/tee/tf-m/psa-arch-tests + groups: + - testing + - tee - name: segger revision: cf56b1d9c80f81a26e2ac5727c9cf177116a4692 path: modules/debug/segger groups: - debug + - name: tf-m-tests + revision: cde5b6ed540d3ff5a09564fded6b39b0a70ad3bf + path: modules/tee/tf-m/tf-m-tests + groups: + - testing - name: trusted-firmware-a revision: 713ffbf96c5bcbdeab757423f10f73eb304eff07 path: modules/tee/tf-a/trusted-firmware-a groups: - tee - name: trusted-firmware-m - revision: c2f9edc77f72838e7d6f5f9c0b95e4318ddfced1 + revision: e295109067f71e1c8db76d02396baa050687b1df path: modules/tee/tf-m/trusted-firmware-m groups: - tee