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AmanieuAmanieu
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Merge pull request #1978 from adamgemmell/dev/adagem01/f16-cvt-feature
Remove fp16 target feature from some intrinsics
2 parents b192e28 + 48260eb commit a813561

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4 files changed

+218
-142
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4 files changed

+218
-142
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‎crates/core_arch/src/aarch64/neon/generated.rs‎

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -7217,8 +7217,8 @@ pub fn vcvtq_f64_u64(a: uint64x2_t) -> float64x2_t {
72177217
#[doc = "Floating-point convert to lower precision"]
72187218
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f16_f32)"]
72197219
#[inline]
7220+
#[target_feature(enable = "neon")]
72207221
#[cfg_attr(test, assert_instr(fcvtn2))]
7221-
#[target_feature(enable = "neon,fp16")]
72227222
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
72237223
#[cfg(not(target_arch = "arm64ec"))]
72247224
pub fn vcvt_high_f16_f32(a: float16x4_t, b: float32x4_t) -> float16x8_t {
@@ -7227,8 +7227,8 @@ pub fn vcvt_high_f16_f32(a: float16x4_t, b: float32x4_t) -> float16x8_t {
72277227
#[doc = "Floating-point convert to higher precision"]
72287228
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f32_f16)"]
72297229
#[inline]
7230+
#[target_feature(enable = "neon")]
72307231
#[cfg_attr(test, assert_instr(fcvtl2))]
7231-
#[target_feature(enable = "neon,fp16")]
72327232
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
72337233
#[cfg(not(target_arch = "arm64ec"))]
72347234
pub fn vcvt_high_f32_f16(a: float16x8_t) -> float32x4_t {
@@ -9487,7 +9487,7 @@ pub fn vdivq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
94879487
#[target_feature(enable = "neon,fp16")]
94889488
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
94899489
#[cfg(not(target_arch = "arm64ec"))]
9490-
#[cfg_attr(test, assert_instr(nop))]
9490+
#[cfg_attr(test, assert_instr(fdiv))]
94919491
pub fn vdivh_f16(a: f16, b: f16) -> f16 {
94929492
a / b
94939493
}
@@ -14829,7 +14829,7 @@ pub fn vmuld_lane_f64<const LANE: i32>(a: f64, b: float64x1_t) -> f64 {
1482914829
#[target_feature(enable = "neon,fp16")]
1483014830
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
1483114831
#[cfg(not(target_arch = "arm64ec"))]
14832-
#[cfg_attr(test, assert_instr(nop))]
14832+
#[cfg_attr(test, assert_instr(fmul))]
1483314833
pub fn vmulh_f16(a: f16, b: f16) -> f16 {
1483414834
a * b
1483514835
}
@@ -21492,7 +21492,7 @@ pub fn vrecpxh_f16(a: f16) -> f16 {
2149221492
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_f16)"]
2149321493
#[inline]
2149421494
#[cfg(target_endian = "little")]
21495-
#[target_feature(enable = "neon,fp16")]
21495+
#[target_feature(enable = "neon")]
2149621496
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
2149721497
#[cfg(not(target_arch = "arm64ec"))]
2149821498
#[cfg_attr(test, assert_instr(nop))]
@@ -21503,7 +21503,7 @@ pub fn vreinterpret_f64_f16(a: float16x4_t) -> float64x1_t {
2150321503
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_f16)"]
2150421504
#[inline]
2150521505
#[cfg(target_endian = "big")]
21506-
#[target_feature(enable = "neon,fp16")]
21506+
#[target_feature(enable = "neon")]
2150721507
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
2150821508
#[cfg(not(target_arch = "arm64ec"))]
2150921509
#[cfg_attr(test, assert_instr(nop))]
@@ -21515,7 +21515,7 @@ pub fn vreinterpret_f64_f16(a: float16x4_t) -> float64x1_t {
2151521515
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_f16)"]
2151621516
#[inline]
2151721517
#[cfg(target_endian = "little")]
21518-
#[target_feature(enable = "neon,fp16")]
21518+
#[target_feature(enable = "neon")]
2151921519
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
2152021520
#[cfg(not(target_arch = "arm64ec"))]
2152121521
#[cfg_attr(test, assert_instr(nop))]
@@ -21526,7 +21526,7 @@ pub fn vreinterpretq_f64_f16(a: float16x8_t) -> float64x2_t {
2152621526
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_f16)"]
2152721527
#[inline]
2152821528
#[cfg(target_endian = "big")]
21529-
#[target_feature(enable = "neon,fp16")]
21529+
#[target_feature(enable = "neon")]
2153021530
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
2153121531
#[cfg(not(target_arch = "arm64ec"))]
2153221532
#[cfg_attr(test, assert_instr(nop))]
@@ -21541,7 +21541,7 @@ pub fn vreinterpretq_f64_f16(a: float16x8_t) -> float64x2_t {
2154121541
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f64)"]
2154221542
#[inline]
2154321543
#[cfg(target_endian = "little")]
21544-
#[target_feature(enable = "neon,fp16")]
21544+
#[target_feature(enable = "neon")]
2154521545
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
2154621546
#[cfg(not(target_arch = "arm64ec"))]
2154721547
#[cfg_attr(test, assert_instr(nop))]
@@ -21552,7 +21552,7 @@ pub fn vreinterpret_f16_f64(a: float64x1_t) -> float16x4_t {
2155221552
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f64)"]
2155321553
#[inline]
2155421554
#[cfg(target_endian = "big")]
21555-
#[target_feature(enable = "neon,fp16")]
21555+
#[target_feature(enable = "neon")]
2155621556
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
2155721557
#[cfg(not(target_arch = "arm64ec"))]
2155821558
#[cfg_attr(test, assert_instr(nop))]
@@ -21566,7 +21566,7 @@ pub fn vreinterpret_f16_f64(a: float64x1_t) -> float16x4_t {
2156621566
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f64)"]
2156721567
#[inline]
2156821568
#[cfg(target_endian = "little")]
21569-
#[target_feature(enable = "neon,fp16")]
21569+
#[target_feature(enable = "neon")]
2157021570
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
2157121571
#[cfg(not(target_arch = "arm64ec"))]
2157221572
#[cfg_attr(test, assert_instr(nop))]
@@ -21577,7 +21577,7 @@ pub fn vreinterpretq_f16_f64(a: float64x2_t) -> float16x8_t {
2157721577
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f64)"]
2157821578
#[inline]
2157921579
#[cfg(target_endian = "big")]
21580-
#[target_feature(enable = "neon,fp16")]
21580+
#[target_feature(enable = "neon")]
2158121581
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
2158221582
#[cfg(not(target_arch = "arm64ec"))]
2158321583
#[cfg_attr(test, assert_instr(nop))]
@@ -26719,7 +26719,7 @@ pub fn vsubq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
2671926719
#[inline]
2672026720
#[target_feature(enable = "neon")]
2672126721
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26722-
#[cfg_attr(test, assert_instr(nop))]
26722+
#[cfg_attr(test, assert_instr(sub))]
2672326723
pub fn vsubd_s64(a: i64, b: i64) -> i64 {
2672426724
a.wrapping_sub(b)
2672526725
}
@@ -26728,7 +26728,7 @@ pub fn vsubd_s64(a: i64, b: i64) -> i64 {
2672826728
#[inline]
2672926729
#[target_feature(enable = "neon")]
2673026730
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26731-
#[cfg_attr(test, assert_instr(nop))]
26731+
#[cfg_attr(test, assert_instr(sub))]
2673226732
pub fn vsubd_u64(a: u64, b: u64) -> u64 {
2673326733
a.wrapping_sub(b)
2673426734
}
@@ -26738,7 +26738,7 @@ pub fn vsubd_u64(a: u64, b: u64) -> u64 {
2673826738
#[target_feature(enable = "neon,fp16")]
2673926739
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
2674026740
#[cfg(not(target_arch = "arm64ec"))]
26741-
#[cfg_attr(test, assert_instr(nop))]
26741+
#[cfg_attr(test, assert_instr(fsub))]
2674226742
pub fn vsubh_f16(a: f16, b: f16) -> f16 {
2674326743
a - b
2674426744
}

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