diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 9e339de3..00319f47 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -10,6 +10,10 @@ on: # Manual Dispatch workflow_dispatch: +concurrency: + group: lambdalib-${{ github.workflow }}-${{ github.event.pull_request.number || github.ref }} + cancel-in-progress: true + jobs: lint_python: name: Lint Python Code @@ -23,9 +27,24 @@ jobs: . .venv/bin/activate pip install --upgrade pip - pip install .[dev] + pip install .[lint] flake8 --statistics . + check_spelling: + name: Check code spelling + runs-on: ubuntu-latest + steps: + - name: Check out Git repository + uses: actions/checkout@v6 + - name: Check spelling with codespell + run: | + python3 -m venv .venv + . .venv/bin/activate + + pip install --upgrade pip + pip install .[lint] + codespell . + python_ci: name: Run Python Only runs-on: ubuntu-latest @@ -38,13 +57,13 @@ jobs: . .venv/bin/activate pip install --upgrade pip - pip install .[dev] + pip install .[test] # change running directory mkdir testrun cd testrun - pytest $GITHUB_WORKSPACE -m "not eda" + pytest $GITHUB_WORKSPACE -n logical -m "not eda" lint_verilog: name: Lint Verilog Code @@ -89,7 +108,7 @@ jobs: . .venv/bin/activate pip install --upgrade pip - pip install -e .[dev] + pip install -e .[test] # change running directory mkdir testrun diff --git a/lambdalib/analoglib/la_pll/rtl/la_pll.v b/lambdalib/analoglib/la_pll/rtl/la_pll.v index 26f4270c..8cbdf7d6 100644 --- a/lambdalib/analoglib/la_pll/rtl/la_pll.v +++ b/lambdalib/analoglib/la_pll/rtl/la_pll.v @@ -5,7 +5,7 @@ * * NOTE: The generic interface was derived by reviewing a number of * publicly open source PLLs and FPGA IP datasheets and via llm - * promting. + * prompting. * * This is a synthesizable zeroth order PLL model that only * supports one operating mode: clkout=clkref. @@ -19,7 +19,7 @@ module la_pll #(parameter PROP = "", // cell property parameter NIN = 1, // number of input reference clocks parameter NOUT = 1, // number of output clocks - parameter DIVINW = 8, // iunpyt divider width + parameter DIVINW = 8, // input divider width parameter DIVFBW = 8, // feedback divider width parameter DIVOUTW = 8, // output divider width parameter PHASEW = 8, // phase shift adjust width @@ -38,7 +38,7 @@ module la_pll #(parameter PROP = "", // cell property // standard controls input reset, // active high async reset input en, // pll enable - input bypass, // pll bypasses + input bypass, // pll bypass input [NIN-1:0] clksel, // one hot clock selector input [DIVINW-1:0] divin, // reference divider input [DIVFBW-1:0] divfb, // feedback divider diff --git a/lambdalib/fpgalib/la_clb4p0/rtl/la_clb4p0.v b/lambdalib/fpgalib/la_clb4p0/rtl/la_clb4p0.v index b997f3a2..38c4850b 100644 --- a/lambdalib/fpgalib/la_clb4p0/rtl/la_clb4p0.v +++ b/lambdalib/fpgalib/la_clb4p0/rtl/la_clb4p0.v @@ -81,7 +81,7 @@ module la_clb4p0 if (N>1) assign fbmux[i][j] = fb[i][cfgfb[(i*K+j)*$clog2(N)+:$clog2(N)]]; else - assign fbmux[i][j] = fb[i][0]; //TODO: suport N=1 + assign fbmux[i][j] = fb[i][0]; //TODO: support N=1 end // select between feedback and primary inputs diff --git a/pyproject.toml b/pyproject.toml index 77a01eeb..34bcd886 100644 --- a/pyproject.toml +++ b/pyproject.toml @@ -28,8 +28,7 @@ version = {attr = "lambdalib.__version__"} [project.optional-dependencies] # Dev dependencies. -dev = [ - "flake8 == 7.3.0", +test = [ "pytest == 8.4.2", "pytest-xdist==3.8.0", "pytest-timeout == 2.4.0", @@ -37,6 +36,11 @@ dev = [ "cocotb-bus == 0.3.0" ] +lint = [ + "flake8 == 7.3.0", + "codespell == 2.4.1" +] + [tool.pytest.ini_options] markers = [ "eda: this test requires EDA tools installed to run.", @@ -48,3 +52,8 @@ testpaths = [ "tests" ] timeout = "60" + +[tool.codespell] +count = true +quiet-level = 3 +ignore-words-list = 'inout,inouts,nin,te,dout'