Add RISC-V Support for Memory Benchmarking

[smzahraee]

Hi there,

I recently used tinymembench to evaluate memory performance and noticed that the tool does not include any RISC-V-specific assembly code or optimizations. While the benchmark runs, the memory performance results on RISC-V architectures are significantly suboptimal, likely due to the lack of architecture-specific tuning.

Given the growing adoption of RISC-V in various domains, it would be highly beneficial to add RISC-V support to tinymembench.
This could include:

• RISC-V-specific assembly optimizations: Adding hand-tuned assembly code for critical memory operations to ensure accurate benchmarking on RISC-V hardware.

• Instruction set utilization: Leveraging RISC-V-specific instructions (e.g., vector extensions or atomic operations) to improve the accuracy and relevance of the benchmark.

• Cross-architecture compatibility: Ensuring the benchmark can dynamically detect and adapt to RISC-V architectures for seamless testing.

Supporting RISC-V would make tinymembench a more versatile and inclusive tool for the broader community, especially as RISC-V continues to gain traction.

Can we prioritize this enhancement? I’d happily assist with testing or provide additional insights if needed.

Thanks for your consideration!