From 40ccbab628848984e889feca4fc91f9bca65fefb Mon Sep 17 00:00:00 2001 From: Yuuki Takano Date: Thu, 21 Aug 2025 14:49:27 +0900 Subject: [PATCH 1/2] fix(igc): print Rx/Tx registers Signed-off-by: Yuuki Takano --- awkernel_drivers/src/pcie/intel/igc.rs | 28 ++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/awkernel_drivers/src/pcie/intel/igc.rs b/awkernel_drivers/src/pcie/intel/igc.rs index 2a15579bf..273995d45 100644 --- a/awkernel_drivers/src/pcie/intel/igc.rs +++ b/awkernel_drivers/src/pcie/intel/igc.rs @@ -704,6 +704,34 @@ impl IgcInner { msg = format!("{msg}{msix_msg}"); } + let rctl = read_reg(&self.info, igc_regs::IGC_RCTL).unwrap_or(0); + msg = format!("{msg}RCTL: 0x{rctl:#08x}\r\n"); + + for i in 0..self.queue_info.que.len() { + let qctl = read_reg(&self.info, igc_regs::IGC_RXDCTL(i)).unwrap_or(0); + msg = format!("{msg}RXDCTL{i}: 0x{qctl:#08x}\r\n"); + + let rdh = read_reg(&self.info, igc_regs::IGC_RDH(i)).unwrap_or(0); + msg = format!("{msg}RDH{i}: 0x{rdh:#08x}\r\n"); + + let rdt = read_reg(&self.info, igc_regs::IGC_RDT(i)).unwrap_or(0); + msg = format!("{msg}RDT{i}: 0x{rdt:#08x}\r\n"); + } + + let tctl = read_reg(&self.info, igc_regs::IGC_TCTL).unwrap_or(0); + msg = format!("{msg}TCTL: 0x{tctl:#08x}\r\n"); + + for i in 0..self.queue_info.que.len() { + let qctl = read_reg(&self.info, igc_regs::IGC_TXDCTL(i)).unwrap_or(0); + msg = format!("{msg}TXDCTL{i}: 0x{qctl:#08x}\r\n"); + + let txd = read_reg(&self.info, igc_regs::IGC_TDH(i)).unwrap_or(0); + msg = format!("{msg}TDH{i}: 0x{txd:#08x}\r\n"); + + let tdt = read_reg(&self.info, igc_regs::IGC_TDT(i)).unwrap_or(0); + msg = format!("{msg}TDT{i}: 0x{tdt:#08x}\r\n"); + } + log::debug!("igc: dump:\r\n{msg}"); } From 4fa0b6770cb76be1b01971bfa94ed488bf205046 Mon Sep 17 00:00:00 2001 From: Yuuki Takano Date: Thu, 21 Aug 2025 19:02:58 +0900 Subject: [PATCH 2/2] dump RDLEN etc. Signed-off-by: Yuuki Takano --- awkernel_drivers/src/pcie/intel/igc.rs | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/awkernel_drivers/src/pcie/intel/igc.rs b/awkernel_drivers/src/pcie/intel/igc.rs index 273995d45..b91be7df4 100644 --- a/awkernel_drivers/src/pcie/intel/igc.rs +++ b/awkernel_drivers/src/pcie/intel/igc.rs @@ -716,6 +716,15 @@ impl IgcInner { let rdt = read_reg(&self.info, igc_regs::IGC_RDT(i)).unwrap_or(0); msg = format!("{msg}RDT{i}: 0x{rdt:#08x}\r\n"); + + let rdlen = read_reg(&self.info, igc_regs::IGC_RDLEN(i)).unwrap_or(0); + msg = format!("{msg}RDLEN{i}: 0x{rdlen:#08x}\r\n"); + + let rdbah = read_reg(&self.info, igc_regs::IGC_RDBAH(i)).unwrap_or(0); + msg = format!("{msg}RDBAH{i}: 0x{rdbah:#08x}\r\n"); + + let rdbal = read_reg(&self.info, igc_regs::IGC_RDBAL(i)).unwrap_or(0); + msg = format!("{msg}RDBAL{i}: 0x{rdbal:#08x}\r\n"); } let tctl = read_reg(&self.info, igc_regs::IGC_TCTL).unwrap_or(0); @@ -730,6 +739,15 @@ impl IgcInner { let tdt = read_reg(&self.info, igc_regs::IGC_TDT(i)).unwrap_or(0); msg = format!("{msg}TDT{i}: 0x{tdt:#08x}\r\n"); + + let tdlen = read_reg(&self.info, igc_regs::IGC_TDLEN(i)).unwrap_or(0); + msg = format!("{msg}TDLEN{i}: 0x{tdlen:#08x}\r\n"); + + let tdbah = read_reg(&self.info, igc_regs::IGC_TDBAH(i)).unwrap_or(0); + msg = format!("{msg}TDBAH{i}: 0x{tdbah:#08x}\r\n"); + + let tdbal = read_reg(&self.info, igc_regs::IGC_TDBAL(i)).unwrap_or(0); + msg = format!("{msg}TDBAL{i}: 0x{tdbal:#08x}\r\n"); } log::debug!("igc: dump:\r\n{msg}");