Build bitstream error

[zhuzhurrx]

When I run the command bash soc/script/buildbitstream.sh, I always encounted with an error about scale file source like this:

[localhost] out: cd /home/abc/cxz/RoSE/soc/sim/firesim/sim && java -cp /home/abc/cxz/RoSE/soc/sim/firesim/sim/generated-src/firesim-main.jar midas.stage.GoldenGateMain  -i /home/abc/cxz/RoSE/soc/sim/firesim/sim/generated-src/xilinx_alveo_u250/xilinx_alveo_u250-firesim-FireSim-DDR3FRFCFSLLC4MB_WithDefaultFireSimBridges_WithFireSimConfigTweaks_chipyard.config.RoseTLRocketConfig-BaseXilinxAlveoU250Config/firesim.firesim.FireSim.DDR3FRFCFSLLC4MB_WithDefaultFireSimBridges_WithFireSimConfigTweaks_chipyard.config.RoseTLRocketConfig.fir -td /home/abc/cxz/RoSE/soc/sim/firesim/sim/generated-src/xilinx_alveo_u250/xilinx_alveo_u250-firesim-FireSim-DDR3FRFCFSLLC4MB_WithDefaultFireSimBridges_WithFireSimConfigTweaks_chipyard.config.RoseTLRocketConfig-BaseXilinxAlveoU250Config -faf /home/abc/cxz/RoSE/soc/sim/firesim/sim/generated-src/xilinx_alveo_u250/xilinx_alveo_u250-firesim-FireSim-DDR3FRFCFSLLC4MB_WithDefaultFireSimBridges_WithFireSimConfigTweaks_chipyard.config.RoseTLRocketConfig-BaseXilinxAlveoU250Config/firesim.firesim.FireSim.DDR3FRFCFSLLC4MB_WithDefaultFireSimBridges_WithFireSimConfigTweaks_chipyard.config.RoseTLRocketConfig.anno.json -ggcp firesim.firesim -ggcs BaseXilinxAlveoU250Config --output-filename-base FireSim-generated --no-dedup
[localhost] out: Picked up JAVA_TOOL_OPTIONS: -Xmx16G -Xss8M -Djava.io.tmpdir=/home/abc/cxz/RoSE/soc/sim/firesim/sim/.java_tmp
[localhost] out: Exception in thread "main" firrtl.passes.PassExceptions:
[localhost] out: firrtl.passes.CheckInitialization$RefNotInitializedException:  @[home/abc/cxz/RoSE/soc/sim/firesim/target-design/chipyard/generators/chipyard/src/main/scala/harness/HasHarnessInstantiators.scala 87:40] : [module FireSim]  Reference chiptop0 is not fully initialized.
[localhost] out:    : chiptop0.roseAdapter.bits.rx[0].valid <= VOID
[localhost] out: firrtl.passes.CheckInitialization$RefNotInitializedException:  @[home/abc/cxz/RoSE/soc/sim/firesim/target-design/chipyard/generators/chipyard/src/main/scala/harness/HasHarnessInstantiators.scala 87:40] : [module FireSim]  Reference chiptop0 is not fully initialized.
[localhost] out:    : chiptop0.roseAdapter.bits.rx[0].bits <= VOID
[localhost] out: firrtl.passes.CheckInitialization$RefNotInitializedException:  @[home/abc/cxz/RoSE/soc/sim/firesim/target-design/chipyard/generators/chipyard/src/main/scala/harness/HasHarnessInstantiators.scala 87:40] : [module FireSim]  Reference chiptop0 is not fully initialized.
[localhost] out:    : chiptop0.roseAdapter.bits.rx[1].valid <= VOID
[localhost] out: firrtl.passes.CheckInitialization$RefNotInitializedException:  @[home/abc/cxz/RoSE/soc/sim/firesim/target-design/chipyard/generators/chipyard/src/main/scala/harness/HasHarnessInstantiators.scala 87:40] : [module FireSim]  Reference chiptop0 is not fully initialized.
[localhost] out:    : chiptop0.roseAdapter.bits.rx[2].bits <= VOID
[localhost] out: firrtl.passes.CheckInitialization$RefNotInitializedException:  @[home/abc/cxz/RoSE/soc/sim/firesim/target-design/chipyard/generators/chipyard/src/main/scala/harness/HasHarnessInstantiators.scala 87:40] : [module FireSim]  Reference chiptop0 is not fully initialized.
[localhost] out:    : chiptop0.roseAdapter.bits.tx.ready <= VOID
[localhost] out: firrtl.passes.CheckInitialization$RefNotInitializedException:  @[home/abc/cxz/RoSE/soc/sim/firesim/target-design/chipyard/generators/chipyard/src/main/scala/harness/HasHarnessInstantiators.scala 87:40] : [module FireSim]  Reference chiptop0 is not fully initialized.
[localhost] out:    : chiptop0.roseAdapter.bits.rx[2].valid <= VOID
[localhost] out: firrtl.passes.CheckInitialization$RefNotInitializedException:  @[home/abc/cxz/RoSE/soc/sim/firesim/target-design/chipyard/generators/chipyard/src/main/scala/harness/HasHarnessInstantiators.scala 87:40] : [module FireSim]  Reference chiptop0 is not fully initialized.
[localhost] out:    : chiptop0.roseAdapter.bits.rx[1].bits <= VOID
[localhost] out: firrtl.passes.PassException: 7 errors detected!
[localhost] out: make: *** [make/goldengate.mk:31: /home/abc/cxz/RoSE/soc/sim/firesim/sim/generated-src/xilinx_alveo_u250/xilinx_alveo_u250-firesim-FireSim-DDR3FRFCFSLLC4MB_WithDefaultFireSimBridges_WithFireSimConfigTweaks_chipyard.config.RoseTLRocketConfig-BaseXilinxAlveoU250Config/FireSim-generated.sv.intermediate] Error 1
[localhost] out:
Fatal error: run() received nonzero return code 2 while executing!

It seems like that the compiling process of RoSE scala code has something wrong. My Linux system is Ubuntu 20.04. My sbt version is 1.8.2. What can I do to deal with this problem? Looking forward to your kind help.