From 660100d072570e34cde1373235b2b867194b1970 Mon Sep 17 00:00:00 2001 From: Daniele Lacamera Date: Wed, 24 Dec 2025 10:59:01 +0100 Subject: [PATCH] STM32H5: Fixed GTZC1 base address These are used in hal_prepare_boot() for setting peripheral as non-secure. The base address for those registers were 0x4000 too high. Fixed according to RM0841 Chapter 2 Table 5, page 120. --- hal/stm32h5.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hal/stm32h5.h b/hal/stm32h5.h index c6f9478eb7..26a602663b 100644 --- a/hal/stm32h5.h +++ b/hal/stm32h5.h @@ -237,9 +237,9 @@ #define FLASH_NS_SR (*(volatile uint32_t *)(FLASH_NS_BASE + 0x20)) #define FLASH_NS_CR (*(volatile uint32_t *)(FLASH_NS_BASE + 0x28)) -#define TZSC_SECCFGR1 *((volatile uint32_t *)(0x50036410)) +#define TZSC_SECCFGR1 *((volatile uint32_t *)(0x50032410)) #define TZSC_SECCFGR1_USART3SEC (1 << 14) /* USART3 */ -#define TZSC_SECCFGR2 *((volatile uint32_t *)(0x50036414)) +#define TZSC_SECCFGR2 *((volatile uint32_t *)(0x50032414)) #define TZSC_SECCFGR2_LPUART1SEC (1 << 25) /* LPUART1 */ /* Mapping FLASH_SECCR for bank swapping */