diff --git a/lib/stm32wb0/BLE_TransparentMode/Core/Inc/app_conf.h b/lib/stm32wb0/BLE_TransparentMode/Core/Inc/app_conf.h index 16fb361be..93d3ba997 100644 --- a/lib/stm32wb0/BLE_TransparentMode/Core/Inc/app_conf.h +++ b/lib/stm32wb0/BLE_TransparentMode/Core/Inc/app_conf.h @@ -61,10 +61,11 @@ #ifndef __ZEPHYR__ /* It is handled by CMakeLists.txt */ #define CFG_BLE_NUM_RADIO_TASKS (CFG_NUM_RADIO_TASKS) -#endif +#endif /* __ZEPHYR__ */ /** - * Maximum number of Attributes that can be stored in the GATT database. + * Maximum number of attributes that can be stored in the GATT database in addition to the attributes number already defined for the GATT and GAP services + * (BLE_STACK_NUM_GATT_MANDATORY_ATTRIBUTES value on STM32_BLE middleware, ble_stack.h header file). */ #define CFG_BLE_NUM_GATT_ATTRIBUTES (60) @@ -108,7 +109,7 @@ */ #ifndef __ZEPHYR__ #define CFG_BLE_NUM_EATT_CHANNELS (6) -#endif +#endif /* __ZEPHYR__ */ /** * Maximum number of channels in LE Credit Based Flow Control mode [0-255]. @@ -129,7 +130,7 @@ #ifndef __ZEPHYR__ /* It is handled by CMakeLists.txt */ #define CFG_BLE_NUM_ADV_SETS (2) -#endif +#endif /* __ZEPHYR__ */ /** * Maximum number of Periodic Advertising with Responses subevents. @@ -147,7 +148,8 @@ */ #ifndef __ZEPHYR__ #define CFG_BLE_NUM_AUX_SCAN_SLOTS (4) -#endif +#endif /* __ZEPHYR__ */ + /** * Maximum number of slots for synchronizing to a periodic advertising train, * if Periodic Advertising and Synchronizing Feature is enabled. @@ -155,7 +157,7 @@ #ifndef __ZEPHYR__ /* It is handled by CMakeLists.txt */ #define CFG_BLE_NUM_SYNC_SLOTS (2) -#endif +#endif /* __ZEPHYR__ */ /** * Two's logarithm of Filter Accept, Resolving and Advertiser list size. @@ -205,6 +207,12 @@ #define CFG_BLE_NUM_CIS_MAX (2U) #endif /* __ZEPHYR__ */ +/** +* Maximum number of simultaneous Link Layer procedures that can be managed, in addition to the minimum required by the stack. +* The minimum number guarantees one LL procedure initiated by the peer for each link, one LL procedure automatically initiated by the Controller and one LL procedure initiated by the Host. +*/ +#define CFG_BLE_EXTRA_LL_PROCEDURE_CONTEXTS (0) + /** * Size of the internal FIFO used for critical controller events produced by the * ISR (e.g. rx data packets). @@ -223,6 +231,16 @@ */ #define CFG_BLE_USER_FIFO_SIZE (1024) +/** + * If 1, Peripheral Preferred Connection Parameters Characteristic is added in GAP service. + */ +#define CFG_BLE_GAP_PERIPH_PREF_CONN_PARAM_CHARACTERISTIC (1) + +/** + * If 1, Encrypted Key Material Characteristic is added in GAP service. + */ +#define CFG_BLE_GAP_ENCRYPTED_KEY_MATERIAL_CHARACTERISTIC (0) + /** * Number of allocated memory blocks used for packet allocation. * The use of BLE_STACK_MBLOCKS_CALC macro is suggested to calculate the minimum @@ -255,6 +273,7 @@ CFG_BLE_NUM_BRC_BIS_MAX,\ CFG_BLE_NUM_CIG_MAX,\ CFG_BLE_NUM_CIS_MAX,\ + CFG_BLE_EXTRA_LL_PROCEDURE_CONTEXTS,\ CFG_BLE_ISR0_FIFO_SIZE,\ CFG_BLE_ISR1_FIFO_SIZE,\ CFG_BLE_USER_FIFO_SIZE)) @@ -266,6 +285,11 @@ /****************************************************************************** * Initialization parameters used in Network Processor mode ******************************************************************************/ +/** + * Network mode (used in gap_profile.c) + */ +#define CFG_BLE_NETWORK_PROC_MODE (1) + /** * Size of buffer used for ATT queued writes */ @@ -287,6 +311,11 @@ */ #define CFG_BLE_GATT_ADV_NWK_BUFFER_SIZE (CFG_BLE_GATT_NWK_BUFFER_SIZE + CFG_BLE_ADV_NWK_BUFFER_SIZE + CFG_BLE_ATT_QUEUED_WRITE_SIZE) +/** +* Maximum number of characteristics that can be subscribed to check for security level. +*/ +#define CFG_BLE_GATT_CLT_NUM_CHARAC_SUBSCRIPTIONS_MAX (5) + /****************************************************************************** * BLE Stack modularity options ******************************************************************************/ @@ -308,7 +337,7 @@ #define CFG_BLE_CONTROLLER_BIS_ENABLED (1U) #define CFG_BLE_CONNECTION_SUBRATING_ENABLED (1U) #define CFG_BLE_CONTROLLER_CIS_ENABLED (1U) -#endif +#endif /* __ZEPHYR__ */ /****************************************************************************** * Low Power @@ -317,12 +346,17 @@ * low power mode. It means that all what can have an impact on the consumptions * are powered down.(For instance LED, Access to Debugger, Etc.) * + * When CFG_LPM_SUPPORTED and CFG_FULL_LOW_EMULATED are both set to 1, the system is configured to + * emulate the Deepstop mode without losing the debugger connection and breakpoints nor watchpoints. + * ******************************************************************************/ #define CFG_FULL_LOW_POWER (0) #define CFG_LPM_SUPPORTED (1) +#define CFG_LPM_EMULATED (0) + /** * Low Power configuration */ diff --git a/lib/stm32wb0/BLE_TransparentMode/Core/Src/stm32wb0x_hal_msp.c b/lib/stm32wb0/BLE_TransparentMode/Core/Src/stm32wb0x_hal_msp.c index c304eefb4..c3966774c 100644 --- a/lib/stm32wb0/BLE_TransparentMode/Core/Src/stm32wb0x_hal_msp.c +++ b/lib/stm32wb0/BLE_TransparentMode/Core/Src/stm32wb0x_hal_msp.c @@ -76,6 +76,8 @@ void HAL_MspInit(void) /* USER CODE END MspInit 0 */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ @@ -84,69 +86,70 @@ void HAL_MspInit(void) } /** -* @brief PKA MSP Initialization -* This function configures the hardware resources used in this example -* @param hpka: PKA handle pointer -* @retval None -*/ + * @brief PKA MSP Initialization + * This function configures the hardware resources used in this example + * @param hpka: PKA handle pointer + * @retval None + */ void HAL_PKA_MspInit(PKA_HandleTypeDef* hpka) { if(hpka->Instance==PKA) { - /* USER CODE BEGIN PKA_MspInit 0 */ + /* USER CODE BEGIN PKA_MspInit 0 */ - /* USER CODE END PKA_MspInit 0 */ + /* USER CODE END PKA_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_PKA_CLK_ENABLE(); /* PKA interrupt Init */ HAL_NVIC_SetPriority(PKA_IRQn, 1, 0); HAL_NVIC_EnableIRQ(PKA_IRQn); - /* USER CODE BEGIN PKA_MspInit 1 */ + /* USER CODE BEGIN PKA_MspInit 1 */ + + /* USER CODE END PKA_MspInit 1 */ - /* USER CODE END PKA_MspInit 1 */ } } /** -* @brief PKA MSP De-Initialization -* This function freeze the hardware resources used in this example -* @param hpka: PKA handle pointer -* @retval None -*/ + * @brief PKA MSP De-Initialization + * This function freeze the hardware resources used in this example + * @param hpka: PKA handle pointer + * @retval None + */ void HAL_PKA_MspDeInit(PKA_HandleTypeDef* hpka) { if(hpka->Instance==PKA) { - /* USER CODE BEGIN PKA_MspDeInit 0 */ + /* USER CODE BEGIN PKA_MspDeInit 0 */ - /* USER CODE END PKA_MspDeInit 0 */ + /* USER CODE END PKA_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_PKA_CLK_DISABLE(); /* PKA interrupt DeInit */ HAL_NVIC_DisableIRQ(PKA_IRQn); - /* USER CODE BEGIN PKA_MspDeInit 1 */ + /* USER CODE BEGIN PKA_MspDeInit 1 */ - /* USER CODE END PKA_MspDeInit 1 */ + /* USER CODE END PKA_MspDeInit 1 */ } } /** -* @brief RADIO MSP Initialization -* This function configures the hardware resources used in this example -* @param hradio: RADIO handle pointer -* @retval None -*/ + * @brief RADIO MSP Initialization + * This function configures the hardware resources used in this example + * @param hradio: RADIO handle pointer + * @retval None + */ void HAL_RADIO_MspInit(RADIO_HandleTypeDef* hradio) { RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; if(hradio->Instance==RADIO) { - /* USER CODE BEGIN RADIO_MspInit 0 */ + /* USER CODE BEGIN RADIO_MspInit 0 */ - /* USER CODE END RADIO_MspInit 0 */ + /* USER CODE END RADIO_MspInit 0 */ /** Initializes the peripherals clock */ @@ -173,26 +176,29 @@ void HAL_RADIO_MspInit(RADIO_HandleTypeDef* hradio) HAL_NVIC_EnableIRQ(RADIO_TXRX_IRQn); HAL_NVIC_SetPriority(RADIO_TXRX_SEQ_IRQn, 0, 0); HAL_NVIC_EnableIRQ(RADIO_TXRX_SEQ_IRQn); - /* USER CODE BEGIN RADIO_MspInit 1 */ + HAL_NVIC_SetPriority(RADIO_RRM_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(RADIO_RRM_IRQn); + /* USER CODE BEGIN RADIO_MspInit 1 */ + + /* USER CODE END RADIO_MspInit 1 */ - /* USER CODE END RADIO_MspInit 1 */ } } /** -* @brief RADIO MSP De-Initialization -* This function freeze the hardware resources used in this example -* @param hradio: RADIO handle pointer -* @retval None -*/ + * @brief RADIO MSP De-Initialization + * This function freeze the hardware resources used in this example + * @param hradio: RADIO handle pointer + * @retval None + */ void HAL_RADIO_MspDeInit(RADIO_HandleTypeDef* hradio) { if(hradio->Instance==RADIO) { - /* USER CODE BEGIN RADIO_MspDeInit 0 */ + /* USER CODE BEGIN RADIO_MspDeInit 0 */ - /* USER CODE END RADIO_MspDeInit 0 */ + /* USER CODE END RADIO_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_RADIO_CLK_DISABLE(); __HAL_RCC_RADIO_FORCE_RESET(); @@ -201,28 +207,29 @@ void HAL_RADIO_MspDeInit(RADIO_HandleTypeDef* hradio) /* RADIO interrupt DeInit */ HAL_NVIC_DisableIRQ(RADIO_TXRX_IRQn); HAL_NVIC_DisableIRQ(RADIO_TXRX_SEQ_IRQn); - /* USER CODE BEGIN RADIO_MspDeInit 1 */ + HAL_NVIC_DisableIRQ(RADIO_RRM_IRQn); + /* USER CODE BEGIN RADIO_MspDeInit 1 */ - /* USER CODE END RADIO_MspDeInit 1 */ + /* USER CODE END RADIO_MspDeInit 1 */ } } /** -* @brief UART MSP Initialization -* This function configures the hardware resources used in this example -* @param huart: UART handle pointer -* @retval None -*/ + * @brief UART MSP Initialization + * This function configures the hardware resources used in this example + * @param huart: UART handle pointer + * @retval None + */ #ifndef __ZEPHYR__ void HAL_UART_MspInit(UART_HandleTypeDef* huart) { GPIO_InitTypeDef GPIO_InitStruct = {0}; if(huart->Instance==USART1) { - /* USER CODE BEGIN USART1_MspInit 0 */ + /* USER CODE BEGIN USART1_MspInit 0 */ - /* USER CODE END USART1_MspInit 0 */ + /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); @@ -246,6 +253,14 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) GPIO_InitStruct.Alternate = GPIO_AF2_USART1; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + HAL_PWREx_DisableGPIOPullUp(PWR_GPIO_B, PWR_GPIO_BIT_0); + + HAL_PWREx_DisableGPIOPullUp(PWR_GPIO_A, PWR_GPIO_BIT_1); + + HAL_PWREx_DisableGPIOPullDown(PWR_GPIO_B, PWR_GPIO_BIT_0); + + HAL_PWREx_DisableGPIOPullDown(PWR_GPIO_A, PWR_GPIO_BIT_1); + /* USART1 DMA Init */ /* USART1_TX Init */ hdma_usart1_tx.Instance = DMA1_Channel1; @@ -284,26 +299,27 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USART1 interrupt Init */ HAL_NVIC_SetPriority(USART1_IRQn, 2, 0); HAL_NVIC_EnableIRQ(USART1_IRQn); - /* USER CODE BEGIN USART1_MspInit 1 */ + /* USER CODE BEGIN USART1_MspInit 1 */ + + /* USER CODE END USART1_MspInit 1 */ - /* USER CODE END USART1_MspInit 1 */ } } /** -* @brief UART MSP De-Initialization -* This function freeze the hardware resources used in this example -* @param huart: UART handle pointer -* @retval None -*/ + * @brief UART MSP De-Initialization + * This function freeze the hardware resources used in this example + * @param huart: UART handle pointer + * @retval None + */ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) { if(huart->Instance==USART1) { - /* USER CODE BEGIN USART1_MspDeInit 0 */ + /* USER CODE BEGIN USART1_MspDeInit 0 */ - /* USER CODE END USART1_MspDeInit 0 */ + /* USER CODE END USART1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART1_CLK_DISABLE(); @@ -321,9 +337,9 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USART1 interrupt DeInit */ HAL_NVIC_DisableIRQ(USART1_IRQn); - /* USER CODE BEGIN USART1_MspDeInit 1 */ + /* USER CODE BEGIN USART1_MspDeInit 1 */ - /* USER CODE END USART1_MspDeInit 1 */ + /* USER CODE END USART1_MspDeInit 1 */ } } diff --git a/lib/stm32wb0/BLE_TransparentMode/STM32_BLE/App/aci_adv_nwk.c b/lib/stm32wb0/BLE_TransparentMode/STM32_BLE/App/aci_adv_nwk.c index 903ffd282..a7049700b 100644 --- a/lib/stm32wb0/BLE_TransparentMode/STM32_BLE/App/aci_adv_nwk.c +++ b/lib/stm32wb0/BLE_TransparentMode/STM32_BLE/App/aci_adv_nwk.c @@ -212,6 +212,11 @@ tBleStatus hci_le_set_periodic_advertising_subevent_data(uint8_t Advertising_Han return BLE_ERROR_UNKNOWN_ADVERTISING_IDENTIFIER; } + if ((Num_Subevents == 0) || (Num_Subevents > 0x0F)) + { + return BLE_ERROR_INVALID_HCI_CMD_PARAMS; + } + if(pawr_buff_subevent_num_available() < Num_Subevents) { /* This happens is host has given more data than what requested by the Controller. */ diff --git a/lib/stm32wb0/BLE_TransparentMode/STM32_BLE/App/aci_gatt_nwk.h b/lib/stm32wb0/BLE_TransparentMode/STM32_BLE/App/aci_gatt_nwk.h index 2a6e5a409..86f58d036 100644 --- a/lib/stm32wb0/BLE_TransparentMode/STM32_BLE/App/aci_gatt_nwk.h +++ b/lib/stm32wb0/BLE_TransparentMode/STM32_BLE/App/aci_gatt_nwk.h @@ -506,6 +506,23 @@ tBleStatus aci_gatt_clt_write_char_reliable_nwk(uint16_t Connection_Handle, uint16_t Attribute_Val_Length, uint8_t Attribute_Val[]); +/** + * @brief Add a subscription security level setting. + * Any received Notification, Indication or Multiple Notification that not meet this + * requirement will be discarded automatically. + * @param Conn_Handle Connection handle that identifies the connection. + * Values: + * - 0x0000 ... 0x0EFF + * - 0xFFFF is a special value that identify the default setting + * @param Char_Handle Handle of the Characteristic + * Values: + * - 0x0001 ... 0xFFFF + * - 0xFFFF is a special value that identify the default setting + */ +tBleStatus aci_gatt_clt_add_subscription_security_level_nwk(uint16_t Conn_Handle, + uint16_t Char_Handle, + uint8_t Sec_Level); + /** * @brief * @param Conn_Handle Connection handle to be used to identify the connection with the peer device. diff --git a/lib/stm32wb0/BLE_TransparentMode/STM32_BLE/App/app_ble.h b/lib/stm32wb0/BLE_TransparentMode/STM32_BLE/App/app_ble.h index 11bc02f0c..323acd359 100644 --- a/lib/stm32wb0/BLE_TransparentMode/STM32_BLE/App/app_ble.h +++ b/lib/stm32wb0/BLE_TransparentMode/STM32_BLE/App/app_ble.h @@ -104,9 +104,9 @@ typedef enum #define CONN_SUP_TIMEOUT_MS(x) ((uint16_t)((x)/10.0f)) #define CONN_CE_LENGTH_MS(x) ((uint16_t)((x)/0.625f)) -/* STM32WB09 Transparent Mode/DTM version (Bluetooth LE stack v4.0) */ +/* Transparent Mode/DTM version (Bluetooth LE stack v4.x) */ #define DTM_FW_VERSION_MAJOR 1 -#define DTM_FW_VERSION_MINOR 0 +#define DTM_FW_VERSION_MINOR 2 #define DTM_FW_VERSION_PATCH 0 #define UART_INTERFACE @@ -125,6 +125,7 @@ typedef enum void ModulesInit(void); void BLE_Init(void); void APP_BLE_Init(void); + /* USER CODE BEGIN EF */ /* USER CODE END EF */ diff --git a/lib/stm32wb0/BLE_TransparentMode/STM32_BLE/App/dtm_cmd_db.c b/lib/stm32wb0/BLE_TransparentMode/STM32_BLE/App/dtm_cmd_db.c index 33dffa50f..9f1badd32 100644 --- a/lib/stm32wb0/BLE_TransparentMode/STM32_BLE/App/dtm_cmd_db.c +++ b/lib/stm32wb0/BLE_TransparentMode/STM32_BLE/App/dtm_cmd_db.c @@ -3,7 +3,7 @@ ****************************************************************************** * @file DTM_cmd_db.c * @author AMS - RF Application team - * @date 24 October 2023 + * @date 17 June 2025 * @brief Autogenerated files, do not edit!! ****************************************************************************** * @attention @@ -2849,6 +2849,16 @@ typedef PACKED(struct) aci_gatt_clt_read_multiple_var_len_char_value_rp0_s { uint8_t Status; } aci_gatt_clt_read_multiple_var_len_char_value_rp0; +typedef PACKED(struct) aci_gatt_clt_add_subscription_security_level_nwk_cp0_s { + uint16_t Conn_Handle; + uint16_t Char_Value_Handle; + uint8_t Sec_Level; +} aci_gatt_clt_add_subscription_security_level_nwk_cp0; + +typedef PACKED(struct) aci_gatt_clt_add_subscription_security_level_nwk_rp0_s { + uint8_t Status; +} aci_gatt_clt_add_subscription_security_level_nwk_rp0; + typedef PACKED(struct) aci_l2cap_connection_parameter_update_req_cp0_s { uint16_t Connection_Handle; uint16_t Connection_Interval_Min; @@ -2905,6 +2915,18 @@ typedef PACKED(struct) aci_l2cap_cos_connection_resp_rp0_s { uint16_t CID[(HCI_MAX_PAYLOAD_SIZE - 2)/sizeof(uint16_t)]; } aci_l2cap_cos_connection_resp_rp0; +typedef PACKED(struct) aci_l2cap_cos_flow_control_credits_ind_cp0_s { + uint16_t Connection_Handle; + uint16_t CID; + uint16_t RX_Credits; + uint8_t CFC_Policy; +} aci_l2cap_cos_flow_control_credits_ind_cp0; + +typedef PACKED(struct) aci_l2cap_cos_flow_control_credits_ind_rp0_s { + uint8_t Status; + uint16_t RX_Credit_Balance; +} aci_l2cap_cos_flow_control_credits_ind_rp0; + typedef PACKED(struct) aci_l2cap_cos_disconnect_req_cp0_s { uint16_t Connection_Handle; uint16_t CID; @@ -3190,6 +3212,7 @@ uint16_t aci_hal_tone_stop_process(uint8_t *buffer_in, uint16_t buffer_in_length uint16_t aci_hal_get_link_status_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); uint16_t aci_hal_set_radio_activity_mask_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); uint16_t aci_hal_set_le_power_control_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t aci_hal_updater_start_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); uint16_t aci_hal_transmitter_test_packets_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); uint16_t aci_hal_transmitter_test_packets_v2_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); uint16_t aci_hal_write_radio_reg_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); @@ -3274,10 +3297,12 @@ uint16_t aci_gatt_srv_write_multiple_instance_handle_value_process(uint8_t *buff uint16_t aci_gatt_srv_read_multiple_instance_handle_value_nwk_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); uint16_t aci_gatt_srv_multi_notify_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); uint16_t aci_gatt_clt_read_multiple_var_len_char_value_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t aci_gatt_clt_add_subscription_security_level_nwk_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); uint16_t aci_l2cap_connection_parameter_update_req_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); uint16_t aci_l2cap_connection_parameter_update_resp_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); uint16_t aci_l2cap_cos_connection_req_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); uint16_t aci_l2cap_cos_connection_resp_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t aci_l2cap_cos_flow_control_credits_ind_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); uint16_t aci_l2cap_cos_disconnect_req_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); uint16_t aci_l2cap_cos_sdu_data_transmit_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); uint16_t aci_l2cap_cos_reconfigure_req_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); @@ -3908,6 +3933,10 @@ const hci_command_table_type hci_command_table[] = { /* aci_hal_set_le_power_control */ {0xfc1c, aci_hal_set_le_power_control_process}, #endif +#if (!defined(ACI_HAL_UPDATER_START_ENABLED) || ACI_HAL_UPDATER_START_ENABLED) && !ACI_HAL_UPDATER_START_FORCE_DISABLED + /* aci_hal_updater_start */ + {0xfc20, aci_hal_updater_start_process}, +#endif #if (!defined(ACI_HAL_TRANSMITTER_TEST_PACKETS_ENABLED) || ACI_HAL_TRANSMITTER_TEST_PACKETS_ENABLED) && !ACI_HAL_TRANSMITTER_TEST_PACKETS_FORCE_DISABLED /* aci_hal_transmitter_test_packets */ {0xfc2b, aci_hal_transmitter_test_packets_process}, @@ -4247,6 +4276,10 @@ const hci_command_table_type hci_command_table[] = { /* aci_gatt_clt_read_multiple_var_len_char_value */ {0xfd39, aci_gatt_clt_read_multiple_var_len_char_value_process}, #endif +#if (!defined(ACI_GATT_CLT_ADD_SUBSCRIPTION_SECURITY_LEVEL_NWK_ENABLED) || ACI_GATT_CLT_ADD_SUBSCRIPTION_SECURITY_LEVEL_NWK_ENABLED) && !ACI_GATT_CLT_ADD_SUBSCRIPTION_SECURITY_LEVEL_NWK_FORCE_DISABLED + /* aci_gatt_clt_add_subscription_security_level_nwk */ + {0xfd3a, aci_gatt_clt_add_subscription_security_level_nwk_process}, +#endif #if (!defined(ACI_L2CAP_CONNECTION_PARAMETER_UPDATE_REQ_ENABLED) || ACI_L2CAP_CONNECTION_PARAMETER_UPDATE_REQ_ENABLED) && !ACI_L2CAP_CONNECTION_PARAMETER_UPDATE_REQ_FORCE_DISABLED /* aci_l2cap_connection_parameter_update_req */ {0xfd81, aci_l2cap_connection_parameter_update_req_process}, @@ -4263,6 +4296,10 @@ const hci_command_table_type hci_command_table[] = { /* aci_l2cap_cos_connection_resp */ {0xfd84, aci_l2cap_cos_connection_resp_process}, #endif +#if (!defined(ACI_L2CAP_COS_FLOW_CONTROL_CREDITS_IND_ENABLED) || ACI_L2CAP_COS_FLOW_CONTROL_CREDITS_IND_ENABLED) && !ACI_L2CAP_COS_FLOW_CONTROL_CREDITS_IND_FORCE_DISABLED + /* aci_l2cap_cos_flow_control_credits_ind */ + {0xfd85, aci_l2cap_cos_flow_control_credits_ind_process}, +#endif #if (!defined(ACI_L2CAP_COS_DISCONNECT_REQ_ENABLED) || ACI_L2CAP_COS_DISCONNECT_REQ_ENABLED) && !ACI_L2CAP_COS_DISCONNECT_REQ_FORCE_DISABLED /* aci_l2cap_cos_disconnect_req */ {0xfd86, aci_l2cap_cos_disconnect_req_process}, @@ -10113,6 +10150,16 @@ uint16_t aci_hal_get_fw_build_number_process(uint8_t *buffer_in, uint16_t buffer } #endif +#if (!defined(ACI_HAL_UPDATER_START_ENABLED) || ACI_HAL_UPDATER_START_ENABLED) && !ACI_HAL_UPDATER_START_DISABLED +tBleStatus aci_hal_updater_start(void) +{ + // For ACI_HAL_UPDATER_START, set flag to issue a updater start + RAM_VR.BlueFlag = BLUE_FLAG_RAM_RESET; + TL_ResetReqCallback(); + return BLE_STATUS_SUCCESS; +} +#endif + #if (!defined(ACI_HAL_GET_FIRMWARE_DETAILS_ENABLED) || ACI_HAL_GET_FIRMWARE_DETAILS_ENABLED) && !ACI_HAL_GET_FIRMWARE_DETAILS_FORCE_DISABLED /* tBleStatus aci_hal_get_firmware_details(uint8_t *DTM_version_major, uint8_t *DTM_version_minor, @@ -10600,6 +10647,37 @@ uint16_t aci_hal_set_le_power_control_process(uint8_t *buffer_in, uint16_t buffe } #endif +#if (!defined(ACI_HAL_UPDATER_START_ENABLED) || ACI_HAL_UPDATER_START_ENABLED) && !ACI_HAL_UPDATER_START_FORCE_DISABLED +/* tBleStatus aci_hal_updater_start(void); + */ +/* Command len: 0 */ +/* Response len: 1 */ +uint16_t aci_hal_updater_start_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + + int output_size = 1; + /* Output params */ + uint8_t *status = (uint8_t *) (buffer_out + 6); + + *status = BLE_ERROR_INVALID_HCI_CMD_PARAMS; + if (buffer_out_max_length < (1 + 6)) { return 0; } + if(buffer_in_length != 0) + { + goto fail; + } + + *status = aci_hal_updater_start(); +fail: + buffer_out[0] = 0x04; + buffer_out[1] = 0x0E; + buffer_out[2] = output_size + 3; + buffer_out[3] = 0x01; + buffer_out[4] = 0x20; + buffer_out[5] = 0xfc; + return (output_size + 6); +} +#endif + #if (!defined(ACI_HAL_TRANSMITTER_TEST_PACKETS_ENABLED) || ACI_HAL_TRANSMITTER_TEST_PACKETS_ENABLED) && !ACI_HAL_TRANSMITTER_TEST_PACKETS_FORCE_DISABLED /* tBleStatus aci_hal_transmitter_test_packets(uint8_t TX_Frequency, uint8_t Length_Of_Test_Data, @@ -10661,7 +10739,7 @@ uint16_t aci_hal_transmitter_test_packets_v2_process(uint8_t *buffer_in, uint16_ int output_size = 1; /* Output params */ - uint8_t *status = (uint8_t *) (buffer_out + 6); + uint8_t *status = (uint8_t *) (buffer_out + 3); *status = BLE_ERROR_INVALID_HCI_CMD_PARAMS; if (buffer_out_max_length < (1 + 6)) { return 0; } @@ -10681,11 +10759,11 @@ uint16_t aci_hal_transmitter_test_packets_v2_process(uint8_t *buffer_in, uint16_ cp0->Antenna_IDs /* cp0->Switching_Pattern_Length * (sizeof(uint8_t)) */); fail: buffer_out[0] = 0x04; - buffer_out[1] = 0x0E; + buffer_out[1] = 0x0F; buffer_out[2] = output_size + 3; - buffer_out[3] = 0x01; - buffer_out[4] = 0x2c; - buffer_out[5] = 0xfc; + buffer_out[4] = 0x01; + buffer_out[5] = 0x2c; + buffer_out[6] = 0xfc; return (output_size + 6); } #endif @@ -14080,6 +14158,43 @@ uint16_t aci_gatt_clt_read_multiple_var_len_char_value_process(uint8_t *buffer_i } #endif +#if (!defined(ACI_GATT_CLT_ADD_SUBSCRIPTION_SECURITY_LEVEL_NWK_ENABLED) || ACI_GATT_CLT_ADD_SUBSCRIPTION_SECURITY_LEVEL_NWK_ENABLED) && !ACI_GATT_CLT_ADD_SUBSCRIPTION_SECURITY_LEVEL_NWK_FORCE_DISABLED +/* tBleStatus aci_gatt_clt_add_subscription_security_level_nwk(uint16_t Conn_Handle, + uint16_t Char_Value_Handle, + uint8_t Sec_Level); + */ +/* Command len: 2 + 2 + 1 */ +/* Response len: 1 */ +uint16_t aci_gatt_clt_add_subscription_security_level_nwk_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + /* Input params */ + aci_gatt_clt_add_subscription_security_level_nwk_cp0 *cp0 = (aci_gatt_clt_add_subscription_security_level_nwk_cp0 *)(buffer_in + (0)); + + int output_size = 1; + /* Output params */ + uint8_t *status = (uint8_t *) (buffer_out + 6); + + *status = BLE_ERROR_INVALID_HCI_CMD_PARAMS; + if (buffer_out_max_length < (1 + 6)) { return 0; } + if(buffer_in_length != 2 + 2 + 1) + { + goto fail; + } + + *status = aci_gatt_clt_add_subscription_security_level_nwk(cp0->Conn_Handle /* 2 */, + cp0->Char_Value_Handle /* 2 */, + cp0->Sec_Level /* 1 */); +fail: + buffer_out[0] = 0x04; + buffer_out[1] = 0x0E; + buffer_out[2] = output_size + 3; + buffer_out[3] = 0x01; + buffer_out[4] = 0x3a; + buffer_out[5] = 0xfd; + return (output_size + 6); +} +#endif + #if (!defined(ACI_L2CAP_CONNECTION_PARAMETER_UPDATE_REQ_ENABLED) || ACI_L2CAP_CONNECTION_PARAMETER_UPDATE_REQ_ENABLED) && !ACI_L2CAP_CONNECTION_PARAMETER_UPDATE_REQ_FORCE_DISABLED /* tBleStatus aci_l2cap_connection_parameter_update_req(uint16_t Connection_Handle, uint16_t Connection_Interval_Min, @@ -14266,6 +14381,49 @@ uint16_t aci_l2cap_cos_connection_resp_process(uint8_t *buffer_in, uint16_t buff } #endif +#if (!defined(ACI_L2CAP_COS_FLOW_CONTROL_CREDITS_IND_ENABLED) || ACI_L2CAP_COS_FLOW_CONTROL_CREDITS_IND_ENABLED) && !ACI_L2CAP_COS_FLOW_CONTROL_CREDITS_IND_FORCE_DISABLED +/* tBleStatus aci_l2cap_cos_flow_control_credits_ind(uint16_t Connection_Handle, + uint16_t CID, + uint16_t RX_Credits, + uint8_t CFC_Policy, + uint16_t *RX_Credit_Balance); + */ +/* Command len: 2 + 2 + 2 + 1 */ +/* Response len: 1 + 2 */ +uint16_t aci_l2cap_cos_flow_control_credits_ind_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + /* Input params */ + aci_l2cap_cos_flow_control_credits_ind_cp0 *cp0 = (aci_l2cap_cos_flow_control_credits_ind_cp0 *)(buffer_in + (0)); + + int output_size = 1 + 2; + /* Output params */ + aci_l2cap_cos_flow_control_credits_ind_rp0 *rp0 = (aci_l2cap_cos_flow_control_credits_ind_rp0 *) (buffer_out + 6); + uint16_t RX_Credit_Balance = 0; + + rp0->Status = BLE_ERROR_INVALID_HCI_CMD_PARAMS; + if (buffer_out_max_length < (1 + 2 + 6)) { return 0; } + if(buffer_in_length != 2 + 2 + 2 + 1) + { + goto fail; + } + + rp0->Status = aci_l2cap_cos_flow_control_credits_ind(cp0->Connection_Handle /* 2 */, + cp0->CID /* 2 */, + cp0->RX_Credits /* 2 */, + cp0->CFC_Policy /* 1 */, + &RX_Credit_Balance); +fail: + rp0->RX_Credit_Balance = RX_Credit_Balance; + buffer_out[0] = 0x04; + buffer_out[1] = 0x0E; + buffer_out[2] = output_size + 3; + buffer_out[3] = 0x01; + buffer_out[4] = 0x85; + buffer_out[5] = 0xfd; + return (output_size + 6); +} +#endif + #if (!defined(ACI_L2CAP_COS_DISCONNECT_REQ_ENABLED) || ACI_L2CAP_COS_DISCONNECT_REQ_ENABLED) && !ACI_L2CAP_COS_DISCONNECT_REQ_FORCE_DISABLED /* tBleStatus aci_l2cap_cos_disconnect_req(uint16_t Connection_Handle, uint16_t CID); diff --git a/lib/stm32wb0/BLE_TransparentMode/STM32_BLE/App/dtm_cmd_db.h b/lib/stm32wb0/BLE_TransparentMode/STM32_BLE/App/dtm_cmd_db.h index 4bd5b302f..2a09cce67 100644 --- a/lib/stm32wb0/BLE_TransparentMode/STM32_BLE/App/dtm_cmd_db.h +++ b/lib/stm32wb0/BLE_TransparentMode/STM32_BLE/App/dtm_cmd_db.h @@ -39,6 +39,7 @@ tBleStatus aci_hal_transmitter_test_packets(uint8_t TX_Frequency,uint8_t Length_ tBleStatus aci_hal_transmitter_test_packets_v2(uint8_t TX_Channel,uint8_t Test_Data_Length,uint8_t Packet_Payload,uint16_t Number_Of_Packets,uint8_t PHY,uint8_t CTE_Length,uint8_t CTE_Type,uint8_t Switching_Pattern_Length, uint8_t Antenna_IDs[]); tBleStatus aci_hal_write_radio_reg(uint32_t Start_Address, uint8_t Num_Bytes, uint8_t Data[]); tBleStatus aci_hal_read_radio_reg(uint32_t Start_Address, uint8_t Num_Bytes, uint8_t *Data_Length, uint8_t Data[]); +tBleStatus aci_hal_updater_start(void); tBleStatus hci_le_read_maximum_advertising_data_length(uint16_t *Maximum_Advertising_Data_Length); tBleStatus aci_test_tx_notification_start(uint16_t Connection_Handle, uint16_t Service_Handle, uint16_t Char_Handle, uint16_t Value_Length); tBleStatus aci_test_tx_write_command_start(uint16_t Connection_Handle, uint16_t Attr_Handle, uint16_t Value_Length); diff --git a/lib/stm32wb0/BLE_TransparentMode/STM32_BLE/App/dtm_cmd_en.h b/lib/stm32wb0/BLE_TransparentMode/STM32_BLE/App/dtm_cmd_en.h index 96df1bdb7..beb7bd528 100644 --- a/lib/stm32wb0/BLE_TransparentMode/STM32_BLE/App/dtm_cmd_en.h +++ b/lib/stm32wb0/BLE_TransparentMode/STM32_BLE/App/dtm_cmd_en.h @@ -79,7 +79,7 @@ (CONNECTION_ENABLED) #ifndef __ZEPHYR__ #define ACI_HAL_TRANSMITTER_TEST_PACKETS_V2_ENABLED\ - (CONTROLLER_CTE_ENABLED) + (CONTROLLER_CTE_ENABLED) #endif /* __ZEPHYR__ */ #define ACI_TEST_TX_NOTIFICATION_START_ENABLED\ (CONNECTION_ENABLED) @@ -92,6 +92,8 @@ #define ACI_TEST_REPORT_ENABLED\ (CONNECTION_ENABLED) +#define ACI_HAL_UPDATER_START_FORCE_DISABLED 1 + #if CONFIG_NO_HCI_COMMANDS /* Macros to force exclusion of some unnecessary HCI/ACI commands from DTM */ #define HCI_DISCONNECT_FORCE_DISABLED 1 diff --git a/lib/stm32wb0/BLE_TransparentMode/STM32_BLE/App/dtm_cmd_stack_en.h b/lib/stm32wb0/BLE_TransparentMode/STM32_BLE/App/dtm_cmd_stack_en.h index d4700307c..657df9e3b 100644 --- a/lib/stm32wb0/BLE_TransparentMode/STM32_BLE/App/dtm_cmd_stack_en.h +++ b/lib/stm32wb0/BLE_TransparentMode/STM32_BLE/App/dtm_cmd_stack_en.h @@ -98,6 +98,8 @@ (CONNECTION_ENABLED) #define ACI_GAP_TERMINATE_PROC_ENABLED\ (CONTROLLER_SCAN_ENABLED) +#define ACI_GATT_CLT_ADD_SUBSCRIPTION_SECURITY_LEVEL_ENABLED\ + (CONNECTION_ENABLED) #define ACI_GATT_CLT_CONFIRM_INDICATION_ENABLED\ (CONNECTION_ENABLED) #define ACI_GATT_CLT_DISC_ALL_CHAR_DESC_ENABLED\ @@ -226,8 +228,7 @@ (CONNECTION_ENABLED) #define HCI_LE_ACCEPT_CIS_REQUEST_ENABLED\ (CONNECTION_ENABLED &\ - CONTROLLER_CIS_ENABLED &\ - CONTROLLER_ISO_ENABLED) + CONTROLLER_CIS_ENABLED) #define HCI_LE_ADD_DEVICE_TO_PERIODIC_ADVERTISER_LIST_ENABLED\ (CONTROLLER_SCAN_ENABLED &\ CONTROLLER_EXT_ADV_SCAN_ENABLED &\ @@ -238,14 +239,12 @@ (CONTROLLER_SCAN_ENABLED &\ CONTROLLER_EXT_ADV_SCAN_ENABLED &\ CONTROLLER_PERIODIC_ADV_ENABLED &\ - CONTROLLER_BIS_ENABLED &\ - CONTROLLER_ISO_ENABLED) + CONTROLLER_BIS_ENABLED) #define HCI_LE_BIG_TERMINATE_SYNC_ENABLED\ (CONTROLLER_SCAN_ENABLED &\ CONTROLLER_EXT_ADV_SCAN_ENABLED &\ CONTROLLER_PERIODIC_ADV_ENABLED &\ - CONTROLLER_BIS_ENABLED &\ - CONTROLLER_ISO_ENABLED) + CONTROLLER_BIS_ENABLED) #define HCI_LE_CLEAR_ADVERTISING_SETS_ENABLED\ (CONTROLLER_EXT_ADV_SCAN_ENABLED) #define HCI_LE_CLEAR_PERIODIC_ADVERTISER_LIST_ENABLED\ @@ -261,25 +260,35 @@ (CONTROLLER_CTE_ENABLED &\ CONNECTION_ENABLED) #define HCI_LE_CONNECTION_UPDATE_ENABLED\ - (CONNECTION_ENABLED) + (\ + (CONNECTION_ENABLED == 1)\ + &&\ + (\ + (CONTROLLER_SCAN_ENABLED == 1)\ + ||\ + (\ + (CONTROLLER_EXT_ADV_SCAN_ENABLED == 1) &&\ + (CONTROLLER_PERIODIC_ADV_ENABLED == 1) &&\ + (CONNECTION_ENABLED == 1) &&\ + (CONTROLLER_PERIODIC_ADV_WR_ENABLED == 1)\ + )\ + )\ + ) #define HCI_LE_CREATE_BIG_ENABLED\ (CONTROLLER_EXT_ADV_SCAN_ENABLED &\ CONTROLLER_PERIODIC_ADV_ENABLED &\ - CONTROLLER_BIS_ENABLED &\ - CONTROLLER_ISO_ENABLED) + CONTROLLER_BIS_ENABLED) #define HCI_LE_CREATE_BIG_TEST_ENABLED\ (CONTROLLER_EXT_ADV_SCAN_ENABLED &\ CONTROLLER_PERIODIC_ADV_ENABLED &\ - CONTROLLER_BIS_ENABLED &\ - CONTROLLER_ISO_ENABLED) + CONTROLLER_BIS_ENABLED) #define HCI_LE_CREATE_CIS_ENABLED\ (\ (CONNECTION_ENABLED == 1)\ &&\ (\ (CONNECTION_ENABLED == 1) &&\ - (CONTROLLER_CIS_ENABLED == 1) &&\ - (CONTROLLER_ISO_ENABLED == 1)\ + (CONTROLLER_CIS_ENABLED == 1)\ )\ &&\ (\ @@ -328,13 +337,57 @@ #define HCI_LE_GENERATE_DHKEY_ENABLED\ (CONNECTION_ENABLED) #define HCI_LE_ISO_READ_TEST_COUNTERS_ENABLED\ - (CONTROLLER_ISO_ENABLED) + (\ + (\ + (CONNECTION_ENABLED == 1) &&\ + (CONTROLLER_CIS_ENABLED == 1)\ + )\ + ||\ + (\ + (CONTROLLER_EXT_ADV_SCAN_ENABLED == 1) &&\ + (CONTROLLER_PERIODIC_ADV_ENABLED == 1) &&\ + (CONTROLLER_BIS_ENABLED == 1)\ + )\ + ) #define HCI_LE_ISO_RECEIVE_TEST_ENABLED\ - (CONTROLLER_ISO_ENABLED) + (\ + (\ + (CONNECTION_ENABLED == 1) &&\ + (CONTROLLER_CIS_ENABLED == 1)\ + )\ + ||\ + (\ + (CONTROLLER_EXT_ADV_SCAN_ENABLED == 1) &&\ + (CONTROLLER_PERIODIC_ADV_ENABLED == 1) &&\ + (CONTROLLER_BIS_ENABLED == 1)\ + )\ + ) #define HCI_LE_ISO_TEST_END_ENABLED\ - (CONTROLLER_ISO_ENABLED) + (\ + (\ + (CONNECTION_ENABLED == 1) &&\ + (CONTROLLER_CIS_ENABLED == 1)\ + )\ + ||\ + (\ + (CONTROLLER_EXT_ADV_SCAN_ENABLED == 1) &&\ + (CONTROLLER_PERIODIC_ADV_ENABLED == 1) &&\ + (CONTROLLER_BIS_ENABLED == 1)\ + )\ + ) #define HCI_LE_ISO_TRANSMIT_TEST_ENABLED\ - (CONTROLLER_ISO_ENABLED) + (\ + (\ + (CONNECTION_ENABLED == 1) &&\ + (CONTROLLER_CIS_ENABLED == 1)\ + )\ + ||\ + (\ + (CONTROLLER_EXT_ADV_SCAN_ENABLED == 1) &&\ + (CONTROLLER_PERIODIC_ADV_ENABLED == 1) &&\ + (CONTROLLER_BIS_ENABLED == 1)\ + )\ + ) #define HCI_LE_LONG_TERM_KEY_REQUEST_NEGATIVE_REPLY_ENABLED\ (CONNECTION_ENABLED) #define HCI_LE_LONG_TERM_KEY_REQUEST_REPLY_ENABLED\ @@ -363,13 +416,46 @@ #define HCI_LE_READ_ANTENNA_INFORMATION_ENABLED\ (CONTROLLER_CTE_ENABLED) #define HCI_LE_READ_BUFFER_SIZE_V2_ENABLED\ - (CONTROLLER_ISO_ENABLED) + (\ + (\ + (CONNECTION_ENABLED == 1) &&\ + (CONTROLLER_CIS_ENABLED == 1)\ + )\ + ||\ + (\ + (CONTROLLER_EXT_ADV_SCAN_ENABLED == 1) &&\ + (CONTROLLER_PERIODIC_ADV_ENABLED == 1) &&\ + (CONTROLLER_BIS_ENABLED == 1)\ + )\ + ) #define HCI_LE_READ_CHANNEL_MAP_ENABLED\ (CONNECTION_ENABLED) #define HCI_LE_READ_ISO_LINK_QUALITY_ENABLED\ - (CONTROLLER_ISO_ENABLED) + (\ + (\ + (CONNECTION_ENABLED == 1) &&\ + (CONTROLLER_CIS_ENABLED == 1)\ + )\ + ||\ + (\ + (CONTROLLER_EXT_ADV_SCAN_ENABLED == 1) &&\ + (CONTROLLER_PERIODIC_ADV_ENABLED == 1) &&\ + (CONTROLLER_BIS_ENABLED == 1)\ + )\ + ) #define HCI_LE_READ_ISO_TX_SYNC_ENABLED\ - (CONTROLLER_ISO_ENABLED) + (\ + (\ + (CONNECTION_ENABLED == 1) &&\ + (CONTROLLER_CIS_ENABLED == 1)\ + )\ + ||\ + (\ + (CONTROLLER_EXT_ADV_SCAN_ENABLED == 1) &&\ + (CONTROLLER_PERIODIC_ADV_ENABLED == 1) &&\ + (CONTROLLER_BIS_ENABLED == 1)\ + )\ + ) #define HCI_LE_READ_LOCAL_P256_PUBLIC_KEY_ENABLED\ (CONNECTION_ENABLED) #define HCI_LE_READ_LOCAL_RESOLVABLE_ADDRESS_ENABLED\ @@ -404,8 +490,7 @@ (CONTROLLER_CTE_ENABLED) #define HCI_LE_REJECT_CIS_REQUEST_ENABLED\ (CONNECTION_ENABLED &\ - CONTROLLER_CIS_ENABLED &\ - CONTROLLER_ISO_ENABLED) + CONTROLLER_CIS_ENABLED) #define HCI_LE_REMOVE_ADVERTISING_SET_ENABLED\ (CONTROLLER_EXT_ADV_SCAN_ENABLED) #define HCI_LE_REMOVE_CIG_ENABLED\ @@ -414,8 +499,7 @@ &&\ (\ (CONNECTION_ENABLED == 1) &&\ - (CONTROLLER_CIS_ENABLED == 1) &&\ - (CONTROLLER_ISO_ENABLED == 1)\ + (CONTROLLER_CIS_ENABLED == 1)\ )\ &&\ (\ @@ -436,11 +520,21 @@ #define HCI_LE_REMOVE_DEVICE_FROM_RESOLVING_LIST_ENABLED\ (CONTROLLER_PRIVACY_ENABLED) #define HCI_LE_REMOVE_ISO_DATA_PATH_ENABLED\ - (CONTROLLER_ISO_ENABLED) + (\ + (\ + (CONNECTION_ENABLED == 1) &&\ + (CONTROLLER_CIS_ENABLED == 1)\ + )\ + ||\ + (\ + (CONTROLLER_EXT_ADV_SCAN_ENABLED == 1) &&\ + (CONTROLLER_PERIODIC_ADV_ENABLED == 1) &&\ + (CONTROLLER_BIS_ENABLED == 1)\ + )\ + ) #define HCI_LE_REQUEST_PEER_SCA_ENABLED\ (CONNECTION_ENABLED &\ - CONTROLLER_CIS_ENABLED &\ - CONTROLLER_ISO_ENABLED) + CONTROLLER_CIS_ENABLED) #define HCI_LE_SET_ADDRESS_RESOLUTION_ENABLE_ENABLED\ (CONTROLLER_PRIVACY_ENABLED) #define HCI_LE_SET_ADVERTISING_SET_RANDOM_ADDRESS_ENABLED\ @@ -451,8 +545,7 @@ &&\ (\ (CONNECTION_ENABLED == 1) &&\ - (CONTROLLER_CIS_ENABLED == 1) &&\ - (CONTROLLER_ISO_ENABLED == 1)\ + (CONTROLLER_CIS_ENABLED == 1)\ )\ &&\ (\ @@ -472,8 +565,7 @@ &&\ (\ (CONNECTION_ENABLED == 1) &&\ - (CONTROLLER_CIS_ENABLED == 1) &&\ - (CONTROLLER_ISO_ENABLED == 1)\ + (CONTROLLER_CIS_ENABLED == 1)\ )\ &&\ (\ @@ -596,15 +688,25 @@ (CONTROLLER_POWER_CONTROL_ENABLED &\ CONNECTION_ENABLED) #define HCI_LE_SETUP_ISO_DATA_PATH_ENABLED\ - (CONTROLLER_ISO_ENABLED) + (\ + (\ + (CONNECTION_ENABLED == 1) &&\ + (CONTROLLER_CIS_ENABLED == 1)\ + )\ + ||\ + (\ + (CONTROLLER_EXT_ADV_SCAN_ENABLED == 1) &&\ + (CONTROLLER_PERIODIC_ADV_ENABLED == 1) &&\ + (CONTROLLER_BIS_ENABLED == 1)\ + )\ + ) #define HCI_LE_SUBRATE_REQUEST_ENABLED\ (CONNECTION_ENABLED &\ CONNECTION_SUBRATING_ENABLED) #define HCI_LE_TERMINATE_BIG_ENABLED\ (CONTROLLER_EXT_ADV_SCAN_ENABLED &\ CONTROLLER_PERIODIC_ADV_ENABLED &\ - CONTROLLER_BIS_ENABLED &\ - CONTROLLER_ISO_ENABLED) + CONTROLLER_BIS_ENABLED) #define HCI_LE_TRANSMITTER_TEST_V2_ENABLED\ (CONTROLLER_2M_CODED_PHY_ENABLED) #define HCI_LE_TRANSMITTER_TEST_V3_ENABLED\ @@ -622,8 +724,7 @@ (CONNECTION_ENABLED) #define HCI_READ_CONNECTION_ACCEPT_TIMEOUT_ENABLED\ (CONNECTION_ENABLED &\ - CONTROLLER_CIS_ENABLED &\ - CONTROLLER_ISO_ENABLED) + CONTROLLER_CIS_ENABLED) #define HCI_READ_REMOTE_VERSION_INFORMATION_ENABLED\ (CONNECTION_ENABLED) #define HCI_READ_RSSI_ENABLED\ @@ -631,7 +732,18 @@ #define HCI_READ_TRANSMIT_POWER_LEVEL_ENABLED\ (CONNECTION_ENABLED) #define HCI_TX_ISO_DATA_ENABLED\ - (CONTROLLER_ISO_ENABLED) + (\ + (\ + (CONNECTION_ENABLED == 1) &&\ + (CONTROLLER_CIS_ENABLED == 1)\ + )\ + ||\ + (\ + (CONTROLLER_EXT_ADV_SCAN_ENABLED == 1) &&\ + (CONTROLLER_PERIODIC_ADV_ENABLED == 1) &&\ + (CONTROLLER_BIS_ENABLED == 1)\ + )\ + ) #define HCI_WRITE_AFH_CHANNEL_ASSESSMENT_MODE_ENABLED\ (CONNECTION_ENABLED &\ CONTROLLER_CHAN_CLASS_ENABLED) @@ -639,7 +751,6 @@ (CONNECTION_ENABLED) #define HCI_WRITE_CONNECTION_ACCEPT_TIMEOUT_ENABLED\ (CONNECTION_ENABLED &\ - CONTROLLER_CIS_ENABLED &\ - CONTROLLER_ISO_ENABLED) + CONTROLLER_CIS_ENABLED) #endif /* _DTM_CMD_STACK_EN_H_ */ diff --git a/lib/stm32wb0/BLE_TransparentMode/STM32_BLE/App/dtm_cmds.c b/lib/stm32wb0/BLE_TransparentMode/STM32_BLE/App/dtm_cmds.c index 4d5224d7b..2e4f6273f 100644 --- a/lib/stm32wb0/BLE_TransparentMode/STM32_BLE/App/dtm_cmds.c +++ b/lib/stm32wb0/BLE_TransparentMode/STM32_BLE/App/dtm_cmds.c @@ -20,6 +20,7 @@ #include "stm32wb0x.h" #include "ble_stack.h" +#include "dtm_cmds.h" #include "dtm_cmd_db.h" #include "transport_layer.h" #include "adv_buff_alloc.h" @@ -66,6 +67,7 @@ */ #define CONNECTION_BIT ((uint32_t)0x00000800) /*!< Bit 11 selected */ #define CONTROLLER_ONLY_BIT ((uint32_t)0x00001000) /*!< Bit 12 selected */ +#define DTM_DEBUG_BIT ((uint32_t)0x00002000) /*!< Bit 13 selected */ #define CONTROLLER_CHAN_CLASS_BIT ((uint32_t)0x00010000) /*!< Bit 16 selected */ #define CONTROLLER_BIS_BIT ((uint32_t)0x00020000) /*!< Bit 17 selected */ #define CONNECTION_SUBRATING_BIT ((uint32_t)0x00080000) /*!< Bit 19 selected */ @@ -100,6 +102,7 @@ ((uint32_t)(CONTROLLER_POWER_CONTROL_ENABLED * CONTROLLER_POWER_CONTROL_BIT)) | \ ((uint32_t)(CONNECTION_ENABLED * CONNECTION_BIT)) | \ ((uint32_t)(BLESTACK_CONTROLLER_ONLY * CONTROLLER_ONLY_BIT)) | \ + ((uint32_t)(DTM_DEBUG_ENABLED * DTM_DEBUG_BIT)) | \ ((uint32_t)(CONTROLLER_CHAN_CLASS_ENABLED * CONTROLLER_CHAN_CLASS_BIT)) | \ ((uint32_t)(CONTROLLER_BIS_ENABLED * CONTROLLER_BIS_BIT)) | \ ((uint32_t)(CONNECTION_SUBRATING_ENABLED * CONNECTION_SUBRATING_BIT)) | \ @@ -107,6 +110,10 @@ ((uint32_t)(CONTROLLER_PERIODIC_ADV_WR_ENABLED * CONTROLLER_PERIODIC_ADV_WR_BIT)) \ ) +/* irq_count used for the aci_hal_transmitter_test_packets() command implementation */ +uint16_t irq_count = 0; +uint16_t num_packets = 0; + tBleStatus aci_hal_get_firmware_details(uint8_t *DTM_version_major, uint8_t *DTM_version_minor, uint8_t *DTM_version_patch, @@ -189,7 +196,6 @@ tBleStatus aci_hal_transmitter_test_packets(uint8_t TX_Frequency, uint16_t Number_Of_Packets, uint8_t PHY) { - extern uint16_t num_packets; tBleStatus status; if(Number_Of_Packets == 0) @@ -213,7 +219,12 @@ tBleStatus aci_hal_transmitter_test_packets(uint8_t TX_Frequency, if(status == 0x00) { - num_packets = Number_Of_Packets; + num_packets = Number_Of_Packets - 1; /* Request to stop one packet before the end */ + + if(num_packets == 0) + { + DTM_CMDS_TxTestStopRequest(); + } } return status; @@ -245,7 +256,6 @@ tBleStatus aci_hal_transmitter_test_packets_v2(uint8_t TX_Channel, uint8_t Switching_Pattern_Length, uint8_t Antenna_IDs[]) { - extern uint16_t num_packets; tBleStatus status; if(Number_Of_Packets == 0) @@ -264,13 +274,50 @@ tBleStatus aci_hal_transmitter_test_packets_v2(uint8_t TX_Channel, if(status == 0x00) { - num_packets = Number_Of_Packets; + num_packets = Number_Of_Packets - 1; /* Request to stop one packet before the end */ + + if(num_packets == 0) + { + DTM_CMDS_TxTestStopRequest(); + } } return status; } #endif +/* It must be called at the end of a TX */ +void DTM_CMDS_TxEnd(void) +{ + if(irq_count != num_packets) + { + irq_count++; + + if(irq_count == num_packets) + { + DTM_CMDS_TxTestStopRequest(); + } + } +} + +/* Check if the desired number of packets has been sent and possibly send the + aci_hal_le_test_end_event. */ +void DTM_CMDS_TxTestStop(void) +{ + uint32_t Number_Of_TX_Packets = 0; + uint16_t Number_Of_RX_Packets; + + /* Reached number of tx test packets */ + hci_le_test_end(&Number_Of_RX_Packets); + aci_hal_le_tx_test_packet_number(&Number_Of_TX_Packets); + aci_hal_le_test_end_event(Number_Of_TX_Packets); + + ATOMIC_SECTION_BEGIN(); + irq_count = 0; + num_packets = 0; + ATOMIC_SECTION_END(); +} + #if (CONNECTION_ENABLED == 1) && (BLESTACK_CONTROLLER_ONLY==0) tBleStatus aci_test_tx_notification_start(uint16_t Connection_Handle, uint16_t Service_Handle, uint16_t Char_Handle, uint16_t Value_Length) diff --git a/lib/stm32wb0/BLE_TransparentMode/STM32_BLE/App/dtm_cmds.h b/lib/stm32wb0/BLE_TransparentMode/STM32_BLE/App/dtm_cmds.h new file mode 100644 index 000000000..ca49b6dbe --- /dev/null +++ b/lib/stm32wb0/BLE_TransparentMode/STM32_BLE/App/dtm_cmds.h @@ -0,0 +1,31 @@ +/* USER CODE BEGIN Header */ + +/** + ****************************************************************************** + * @file dtm_cmds.h + * @author GPM WBL Application Team + * @brief Header file for module implementing come ACI commands outside of BLE Stack + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +#ifndef DTM_CMDS_H +#define DTM_CMDS_H + +void DTM_CMDS_TxEnd(void); + +void DTM_CMDS_TxTestStopRequest(void); + +void DTM_CMDS_TxTestStop(void); + +#endif /* DTM_CMDS_H */ diff --git a/lib/stm32wb0/BLE_TransparentMode/STM32_BLE/App/transport_layer.c b/lib/stm32wb0/BLE_TransparentMode/STM32_BLE/App/transport_layer.c index 5b5e06652..180f3ff75 100644 --- a/lib/stm32wb0/BLE_TransparentMode/STM32_BLE/App/transport_layer.c +++ b/lib/stm32wb0/BLE_TransparentMode/STM32_BLE/App/transport_layer.c @@ -30,6 +30,7 @@ #include "hci_parser.h" #include "dtm_preprocess_events.h" #include "app_common.h" +#include "dtm_cmds.h" /* Private typedef -----------------------------------------------------------*/\ @@ -81,6 +82,8 @@ static uint8_t DMA_RX_Buffer[DMA_RX_BUFFER_SIZE]; static event_lost_register_t event_lost_register; static uint8_t dma_state = DMA_IDLE; +bool tx_test_stop_request = false; + #ifdef DEBUG_DTM DebugLabel debug_buf[DEBUG_ARRAY_LEN] = {EMPTY,}; uint32_t debug_cnt = 0; @@ -213,10 +216,12 @@ static void transport_layer_send_data(uint8_t *data, uint16_t data_length) } } -static void transport_layer_DMA_RX_Data(uint16_t dma_counter) +static void transport_layer_DMA_RX_Data(UART_HandleTypeDef *huart) { static uint16_t rx_index = 0; + uint16_t dma_counter = DMA_RX_BUFFER_SIZE - __HAL_DMA_GET_COUNTER(huart->hdmarx); + if(rx_index != dma_counter) { if(dma_counter > rx_index) @@ -250,6 +255,12 @@ void transport_layer_tick(void) uint16_t len; uint16_t size = 0; + if(tx_test_stop_request) + { + tx_test_stop_request = false; + DTM_CMDS_TxTestStop(); + } + /* Event queue */ if ((fifo_size(&event_fifo) > 0) && (dma_state == DMA_IDLE)) { uint8_t *ptr; @@ -307,6 +318,7 @@ void transport_layer_tick(void) else { fifo_roll_back(&command_fifo, size); + TL_ProcessReqCallback(); } #else DEBUG_NOTES(COMMAND_PROCESSED); @@ -385,7 +397,7 @@ void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) { - transport_layer_DMA_RX_Data(Size); + transport_layer_DMA_RX_Data(huart); } __weak void TL_ProcessReqCallback(void){} @@ -469,3 +481,11 @@ void BLE_STACK_Event(hci_pckt *hci_pckt, uint16_t length) } } +#ifndef __ZEPHYR__ +/* Handle request to stop TX test for aci_hal_transmitter_test_packets */ +void DTM_CMDS_TxTestStopRequest(void) +{ + tx_test_stop_request = true; + TL_ProcessReqCallback(); +} +#endif /* __ZEPHYR__ */ diff --git a/lib/stm32wb0/BLE_TransparentMode/STM32_BLE/Target/bleplat_cntr.c b/lib/stm32wb0/BLE_TransparentMode/STM32_BLE/Target/bleplat_cntr.c index 6ca286c8b..098add778 100644 --- a/lib/stm32wb0/BLE_TransparentMode/STM32_BLE/Target/bleplat_cntr.c +++ b/lib/stm32wb0/BLE_TransparentMode/STM32_BLE/Target/bleplat_cntr.c @@ -40,11 +40,6 @@ * @{ */ -#define ATOMIC_SECTION_BEGIN() uint32_t uwPRIMASK_Bit = __get_PRIMASK(); \ -__disable_irq(); \ - /* Must be called in the same or in a lower scope of ATOMIC_SECTION_BEGIN */ -#define ATOMIC_SECTION_END() __set_PRIMASK(uwPRIMASK_Bit) - #define MAX_PA_LEVEL 31 #define HP_PA_LEVEL 32 /* Fake PA level that can be reached in high power mode. */ @@ -56,6 +51,8 @@ __disable_irq(); \ #define LL_PHY_CODED 0x04U #endif +#if defined (STM32WB06) || defined (STM32WB07) + #define ANY_HW_ERROR_INTERRUPT_Msk ( \ BLUE_STATUSREG_ADDPOINTERROR_Msk | \ BLUE_STATUSREG_RXOVERFLOWERROR_Msk | \ @@ -67,31 +64,41 @@ __disable_irq(); \ BLUE_STATUSREG_ALLTABLEREADYERROR_Msk | \ BLUE_STATUSREG_TXDATAREADYERROR_Msk | \ BLUE_STATUSREG_NOACTIVELERROR_Msk | \ + BLUE_STATUSREG_INITDELAYERROR_Msk | \ BLUE_STATUSREG_SEMATIMEOUTERROR_Msk | \ BLUE_STATUSREG_ACTIVE2ERROR_Msk | \ BLUE_STATUSREG_CONFIGERROR_Msk \ ) -#define WAKEUPINITDELAY_MT (64U) -#define TIMER12_INIT_DELAY_CAL (63U) -#define TIMER2_INIT_DELAY_NO_CAL (9U) -#define RCV_LEN_MARGIN_US (16U) -#define TX_DELAY_START (16U) -#define TX_DELAY_END (16U) +#define RADIO_FSM_RX_DELAY_CAL (116U) +#define RADIO_FSM_RX_DELAY_NO_CAL (56U) +#define RADIO_FSM_TX_DELAY_CAL (118U) +#define RADIO_FSM_TX_DELAY_NO_CAL (58U) + +#elif defined (STM32WB05) || defined (STM32WB09) + +#define ANY_HW_ERROR_INTERRUPT_Msk ( \ + BLUE_STATUSREG_ADDPOINTERROR_Msk | \ + BLUE_STATUSREG_RXOVERFLOWERROR_Msk | \ + BLUE_STATUSREG_TXERROR_0_Msk | \ + BLUE_STATUSREG_TXERROR_1_Msk | \ + BLUE_STATUSREG_TXERROR_2_Msk | \ + BLUE_STATUSREG_TXERROR_3_Msk | \ + BLUE_STATUSREG_TXERROR_4_Msk | \ + BLUE_STATUSREG_ALLTABLEREADYERROR_Msk | \ + BLUE_STATUSREG_TXDATAREADYERROR_Msk | \ + BLUE_STATUSREG_NOACTIVELERROR_Msk | \ + BLUE_STATUSREG_SEMATIMEOUTERROR_Msk | \ + BLUE_STATUSREG_ACTIVE2ERROR_Msk | \ + BLUE_STATUSREG_CONFIGERROR_Msk \ + ) #define RADIO_FSM_RX_DELAY_CAL (90U) #define RADIO_FSM_RX_DELAY_NO_CAL (50U) #define RADIO_FSM_TX_DELAY_CAL (92U) #define RADIO_FSM_TX_DELAY_NO_CAL (52U) -#define RECEIVE_CAL_DELAY_CHECK (RADIO_FSM_RX_DELAY_CAL) -#define RECEIVE_NO_CAL_DELAY_CHECK (RADIO_FSM_RX_DELAY_NO_CAL) -#define TRANSMIT_CAL_DELAY_CHECK (RADIO_FSM_TX_DELAY_CAL - 2U) -#define TRANSMIT_NO_CAL_DELAY_CHECK (RADIO_FSM_TX_DELAY_NO_CAL - 2U) - -#define CONFIG_END_DURATION (20U) -#define TX_DATA_READY_CHECK (5U) -#define TX_READY_TIMEOUT (4U) +#endif #ifndef LL_PHY_CODED #define LL_PHY_CODED 0x04U @@ -110,8 +117,6 @@ __disable_irq(); \ #define PHY_CODED_S2 (0x6U) #define PHY_CODED_S8 (0x4U) -#define BIT_TX_SKIP (0x0UL) - /** * @} */ @@ -163,107 +168,151 @@ BLEPLAT_CNTR_ResultStatus BLEPLAT_CNTR_Deinit(void) return BLEPLAT_CNTR_SUCCESS; } -/* Moved from the Stack library to the application environment - * - */ /* Calculate the Timeout to be programmed on Timer2 to obtain a give T_IFS - * when the next packet is a transmit one -*/ -uint32_t BLEPLAT_CNTR_GetTimer2TimeoutForIfs(uint32_t T_Ifs, BLEPLAT_CNTR_Transaction Transaction, uint8_t Cal_Enabled) + when the next packet is a transmit one */ +uint32_t BLEPLAT_CNTR_GetTimer2TimeoutForIfs(uint32_t T_Ifs, BLEPLAT_CNTR_Transaction Transaction, uint8_t Rx_Phy, uint8_t Tx_Phy, uint8_t Cal_Enabled) { - uint32_t Timeout = T_Ifs; - uint32_t Tx_Delay_Comp; - uint32_t Init_Delay=0; + uint32_t Timeout = T_Ifs; + uint32_t Tx_Delay_Comp; + uint32_t Init_Delay = 0; + + if(Transaction == BLEPLAT_CNTR_RxTx) + { + /* The correction values below have been determined by T_IFS measurements in + connection, initiating and active scanning */ +#if defined(STM32WB06) || defined(STM32WB07) + + const int32_t Adjust_Value = 4; + +#elif defined (STM32WB05) || defined (STM32WB09) + + int32_t Adjust_Value; - if(Transaction == BLEPLAT_CNTR_RxTx) + if((Rx_Phy == PHY_1MBPS) && + (Tx_Phy == PHY_1MBPS)) { - /* The correction values below have been determined by sniffer - * T_IFS measurements in connection, initiating and active - * scanning - */ -#ifdef STM32WB05 - const int32_t Adjust_Value = 4; -#else - const int32_t Adjust_Value = 6; -#endif - Tx_Delay_Comp = (TX_DELAY_START>>3) + Adjust_Value; + Adjust_Value = 4; } - else if(Transaction == BLEPLAT_CNTR_TxRx) + else if((Rx_Phy == PHY_1MBPS) && + (Tx_Phy == PHY_2MBPS)) { - /* The correction values below have been set to correspond to the hardcoded - * values used in prrevious versions of the stack. - * They could be optimized after careful analysis of timing margins and - * AGC behavior. - */ -#ifdef STM32WB05 - const int32_t Adjust_Value = 4; -#else - const int32_t Adjust_Value = 4; -#endif - Tx_Delay_Comp = (TX_DELAY_END>>3) + Adjust_Value; + Adjust_Value = 3; } - else if(Transaction == BLEPLAT_CNTR_TxTx) + else if((Rx_Phy == PHY_1MBPS) && + ((Tx_Phy == PHY_CODED_S2) || (Tx_Phy == PHY_CODED_S8))) { - /* The correction values below have been determined by sniffer - * T_IFS measurements in extended advertising (AUX_CHAIN_IND) - */ -#ifdef STM32WB05 - const int32_t Adjust_Value = 1; -#else - const int32_t Adjust_Value = 2; -#endif - Tx_Delay_Comp = ((TX_DELAY_START + TX_DELAY_END)>>3) + Adjust_Value; + Adjust_Value = 4; + } + else if((Rx_Phy == PHY_2MBPS) && + ((Tx_Phy == PHY_1MBPS) || (Tx_Phy == PHY_CODED_S2) || (Tx_Phy == PHY_CODED_S8))) + { + Adjust_Value = 6; + } + else if((Rx_Phy == PHY_2MBPS) && + (Tx_Phy == PHY_2MBPS)) + { + Adjust_Value = 4; + } + else if(((Rx_Phy == PHY_CODED_S2) || (Rx_Phy == PHY_CODED_S8)) && + (Tx_Phy == PHY_1MBPS)) + { + Adjust_Value = 5; + } + else if(((Rx_Phy == PHY_CODED_S2) || (Rx_Phy == PHY_CODED_S8)) && + (Tx_Phy == PHY_2MBPS)) + { + Adjust_Value = 4; + } + else if(((Rx_Phy == PHY_CODED_S2) || (Rx_Phy == PHY_CODED_S8)) && + ((Tx_Phy == PHY_CODED_S2) || (Tx_Phy == PHY_CODED_S8))) + { + Adjust_Value = 5; } else { - Tx_Delay_Comp = 0; + Adjust_Value = 6; } +#endif + + Tx_Delay_Comp = (RADIO_TXDELAY_START>>3) + Adjust_Value; + } + else if(Transaction == BLEPLAT_CNTR_TxRx) + { + /* The correction values below have been set to correspond to the hardcoded + values used in previous versions of the stack. + They could be optimized after careful analysis of timing margins and + AGC behavior. */ + const int32_t Adjust_Value = 4; + + Tx_Delay_Comp = (RADIO_TXDELAY_END>>3) + Adjust_Value; + } + else if(Transaction == BLEPLAT_CNTR_TxTx) + { + /* The correction values below have been determined by sniffer + * T_IFS measurements in extended advertising (AUX_CHAIN_IND) + */ +#if defined(STM32WB06) || defined(STM32WB07) + + const int32_t Adjust_Value = 1; + +#elif defined (STM32WB05) || defined (STM32WB09) + + const int32_t Adjust_Value = 2; + +#endif - if((Transaction == BLEPLAT_CNTR_RxTx) || (Transaction == BLEPLAT_CNTR_TxTx)) + Tx_Delay_Comp = ((RADIO_TXDELAY_START + RADIO_TXDELAY_END)>>3) + Adjust_Value; + } + else + { + Tx_Delay_Comp = 0; + } + + if((Transaction == BLEPLAT_CNTR_RxTx) || (Transaction == BLEPLAT_CNTR_TxTx)) + { + if(Cal_Enabled == TRUE) { - if(Cal_Enabled == TRUE) - { - Init_Delay = TIMER12_INIT_DELAY_CAL + RADIO_FSM_TX_DELAY_CAL; - } - else - { - Init_Delay = TIMER2_INIT_DELAY_NO_CAL + RADIO_FSM_TX_DELAY_NO_CAL; - } + Init_Delay = RADIO_INITDELAY_TIMER12_CAL + RADIO_FSM_TX_DELAY_CAL; } - else if((Transaction == BLEPLAT_CNTR_TxRx) || (Transaction == BLEPLAT_CNTR_RxRx)) + else { - /* The calculation below is based on the following sequence: + Init_Delay = RADIO_INITDELAY_TIMER2_NOCAL + RADIO_FSM_TX_DELAY_NO_CAL; + } + } + else if((Transaction == BLEPLAT_CNTR_TxRx) || (Transaction == BLEPLAT_CNTR_RxRx)) + { + /* The calculation below is based on the following sequence: * - When Timer2 expires the sequencer performs the 1st initialization step and sends - * a take_req to the radio - * - When TIMER12_INIT_DELAY_CAL or TIMER2_INIT_DELAY_NO_CAL expire the sequencer sends - * a tx_rx_req to the radio - * - When the radio FSM reaches the RX state (after RADIO_FSM_RX_DELAY_CAL or - * RADIO_FSM_RX_DELAY_NO_CAL) the demodulator is turned on - * - * The sum of Timer2 timeout + TIMER(1)2_INIT_DELAY(_NO)_CAL + RADIO_FSM_RX_DELAY(_NO)_CAL - * must be equal to the T IFS. - * - * The current calculation of Timer2 for TX-RX events is slightly conservative - * since it soes not consider the delay from digital modulator to antenna and from - * antenna to digital demodulator. As a consequence the demodulator is turned on - * a few microseconds earlier than stricty needed. - */ - if(Cal_Enabled == TRUE) - { - Init_Delay = TIMER12_INIT_DELAY_CAL + RADIO_FSM_RX_DELAY_CAL; - } - else - { - Init_Delay = TIMER2_INIT_DELAY_NO_CAL + RADIO_FSM_RX_DELAY_NO_CAL; - } + * a take_req to the radio + * - When RADIO_INITDELAY_TIMER12_CAL or RADIO_INITDELAY_TIMER2_NOCAL expire the sequencer sends + * a tx_rx_req to the radio + * - When the radio FSM reaches the RX state (after RADIO_FSM_RX_DELAY_CAL or + * RADIO_FSM_RX_DELAY_NO_CAL) the demodulator is turned on + * + * The sum of Timer2 timeout + TIMER(1)2_INIT_DELAY(_NO)_CAL + RADIO_FSM_RX_DELAY(_NO)_CAL + * must be equal to the T IFS. + * + * The current calculation of Timer2 for TX-RX events is slightly conservative + * since it soes not consider the delay from digital modulator to antenna and from + * antenna to digital demodulator. As a consequence the demodulator is turned on + * a few microseconds earlier than stricty needed. + */ + if(Cal_Enabled == TRUE) + { + Init_Delay = RADIO_INITDELAY_TIMER12_CAL + RADIO_FSM_RX_DELAY_CAL; } else { + Init_Delay = RADIO_INITDELAY_TIMER2_NOCAL + RADIO_FSM_RX_DELAY_NO_CAL; } + } + else + { + } - Timeout -= (Init_Delay + Tx_Delay_Comp); + Timeout -= (Init_Delay + Tx_Delay_Comp); - return Timeout; + return Timeout; } void BLEPLAT_CNTR_ClearInterrupt(uint32_t x) @@ -1197,6 +1246,11 @@ uint8_t BLEPLAT_CNTR_DemodDelaySt(uint8_t RxPHY) return (uint8_t)((LL_PHY_CODED == RxPHY) ? 0x9DU : 0x12U); } +uint32_t BLEPLAT_CNTR_IsEnabledTimer1(void) +{ + return LL_RADIO_TIMER_IsEnabledTimer1(BLUE); +} + /** * @} */ diff --git a/lib/stm32wb0/CMakeLists.txt b/lib/stm32wb0/CMakeLists.txt index 5e23eed06..24f320951 100644 --- a/lib/stm32wb0/CMakeLists.txt +++ b/lib/stm32wb0/CMakeLists.txt @@ -5,19 +5,19 @@ zephyr_library() if(CONFIG_STM32WB0_RADIO_TIMER) - zephyr_include_directories(BLE_TransparentMode/System/Modules) - zephyr_library_sources(BLE_TransparentMode/System/Modules/blue_unit_conversion.s) + zephyr_include_directories(Common/BLE/Modules) + zephyr_library_sources(Common/BLE/Modules/blue_unit_conversion.s) endif() if(CONFIG_BT_STM32WB0) # Set the correct directory zephyr_include_directories(STM32_BLE) zephyr_include_directories(STM32_BLE/stack/include) -zephyr_include_directories(BLE_TransparentMode/System/Modules/PKAMGR/Inc) -zephyr_include_directories(BLE_TransparentMode/System/Interfaces) -zephyr_include_directories(BLE_TransparentMode/System/Modules/RADIO_utils/Inc) -zephyr_include_directories(BLE_TransparentMode/System/Config/Debug_GPIO) -zephyr_include_directories(BLE_TransparentMode/System/Modules/RTDebug) +zephyr_include_directories(Common/BLE/Modules/PKAMGR/Inc) +zephyr_include_directories(Common/BLE/Interfaces) +zephyr_include_directories(Common/BLE/Modules/RADIO_utils/Inc) +zephyr_include_directories(Common/BLE/Config/Debug_GPIO) +zephyr_include_directories(Common/BLE/Modules/RTDebug) zephyr_include_directories(BLE_TransparentMode/Core/Inc) zephyr_include_directories(BLE_TransparentMode/STM32_BLE/App) @@ -25,9 +25,9 @@ target_link_directories(app PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/../../zephyr/blob target_link_libraries(app PUBLIC -l:stm32wb0x_ble_stack_controller_only.a) function(min OUT_VAR) - list(SORT ARGN COMPARE NATURAL ORDER ASCENDING) - list(GET ARGN 0 MIN_ELEMENT) - set(${OUT_VAR} ${MIN_ELEMENT} PARENT_SCOPE) + list(SORT ARGN COMPARE NATURAL ORDER ASCENDING) + list(GET ARGN 0 MIN_ELEMENT) + set(${OUT_VAR} ${MIN_ELEMENT} PARENT_SCOPE) endfunction() ########### Begining of modularity selection ########### @@ -50,42 +50,42 @@ set(CFG_BLE_CONNECTION_SUBRATING_ENABLED "0") set(CFG_BLE_CONTROLLER_CIS_ENABLED "0") zephyr_compile_definitions( - -DBLESTACK_CONTROLLER_ONLY=1 - -DACI_HAL_GET_FIRMWARE_DETAILS_ENABLED=0 - -DACI_HAL_GET_FIRMWARE_DETAILS_V2_ENABLED=0 - -DACI_HAL_UPDATER_START_ENABLED=0 - -DACI_HAL_TRANSMITTER_TEST_PACKETS_ENABLED=0 - -DACI_HAL_TRANSMITTER_TEST_PACKETS_V2_ENABLED=0 - -DACI_HAL_WRITE_RADIO_REG_ENABLED=0 - -DACI_HAL_READ_RADIO_REG_ENABLED=0 + -DBLESTACK_CONTROLLER_ONLY=1 + -DACI_HAL_GET_FIRMWARE_DETAILS_ENABLED=0 + -DACI_HAL_GET_FIRMWARE_DETAILS_V2_ENABLED=0 + -DACI_HAL_UPDATER_START_ENABLED=0 + -DACI_HAL_TRANSMITTER_TEST_PACKETS_ENABLED=0 + -DACI_HAL_TRANSMITTER_TEST_PACKETS_V2_ENABLED=0 + -DACI_HAL_WRITE_RADIO_REG_ENABLED=0 + -DACI_HAL_READ_RADIO_REG_ENABLED=0 ) if(CONFIG_BT_OBSERVER) - set(CFG_BLE_CONTROLLER_SCAN_ENABLED "1") + set(CFG_BLE_CONTROLLER_SCAN_ENABLED "1") endif() if(CONFIG_BT_PRIVACY) - set(CFG_BLE_CONTROLLER_PRIVACY_ENABLED "1") + set(CFG_BLE_CONTROLLER_PRIVACY_ENABLED "1") endif() if(CONFIG_BT_SMP) - set(CFG_BLE_SECURE_CONNECTIONS_ENABLED "1") + set(CFG_BLE_SECURE_CONNECTIONS_ENABLED "1") endif() if(CONFIG_BT_CTLR_DATA_LENGTH GREATER 27) - set(CFG_BLE_CONTROLLER_DATA_LENGTH_EXTENSION_ENABLED "1") + set(CFG_BLE_CONTROLLER_DATA_LENGTH_EXTENSION_ENABLED "1") endif() if(CONFIG_BT_EXT_ADV) - set(CFG_BLE_CONTROLLER_EXT_ADV_SCAN_ENABLED "1") + set(CFG_BLE_CONTROLLER_EXT_ADV_SCAN_ENABLED "1") endif() if(CONFIG_BT_L2CAP_ECRED) - set(CFG_BLE_L2CAP_COS_ENABLED "1") + set(CFG_BLE_L2CAP_COS_ENABLED "1") endif() if(CONFIG_BT_PER_ADV OR CONFIG_BT_PER_ADV_SYNC) - set(CFG_BLE_CONTROLLER_PERIODIC_ADV_ENABLED "1") + set(CFG_BLE_CONTROLLER_PERIODIC_ADV_ENABLED "1") endif() if(CONFIG_BT_PER_ADV_RSP) @@ -93,23 +93,23 @@ if(CONFIG_BT_PER_ADV_RSP) endif() if(CONFIG_BT_DF) - set(CFG_BLE_CONTROLLER_CTE_ENABLED "1") + set(CFG_BLE_CONTROLLER_CTE_ENABLED "1") endif() if(CONFIG_BT_TRANSMIT_POWER_CONTROL) - set(CFG_BLE_CONTROLLER_POWER_CONTROL_ENABLED "1") + set(CFG_BLE_CONTROLLER_POWER_CONTROL_ENABLED "1") endif() if(CONFIG_BT_CONN) - set(CFG_BLE_CONNECTION_ENABLED "1") + set(CFG_BLE_CONNECTION_ENABLED "1") endif() if(CONFIG_BT_ISO_BROADCAST) - set(CFG_BLE_CONTROLLER_BIS_ENABLED "1") + set(CFG_BLE_CONTROLLER_BIS_ENABLED "1") endif() if(CONFIG_BT_ISO_UNICAST) - set(CFG_BLE_CONTROLLER_CIS_ENABLED "1") + set(CFG_BLE_CONTROLLER_CIS_ENABLED "1") endif() message(STATUS "BLE Stack modularity configuration:") @@ -131,22 +131,22 @@ message(STATUS "CONNECTION_SUBRATING_ENABLED=${CFG_BLE_CONNECTION_SUBRATING_ENAB message(STATUS "CONTROLLER_CIS_ENABLED=${CFG_BLE_CONTROLLER_CIS_ENABLED}") zephyr_compile_definitions( - -DCFG_BLE_CONTROLLER_SCAN_ENABLED=${CFG_BLE_CONTROLLER_SCAN_ENABLED} - -DCFG_BLE_CONTROLLER_PRIVACY_ENABLED=${CFG_BLE_CONTROLLER_PRIVACY_ENABLED} - -DCFG_BLE_SECURE_CONNECTIONS_ENABLED=${CFG_BLE_SECURE_CONNECTIONS_ENABLED} - -DCFG_BLE_CONTROLLER_DATA_LENGTH_EXTENSION_ENABLED=${CFG_BLE_CONTROLLER_DATA_LENGTH_EXTENSION_ENABLED} - -DCFG_BLE_CONTROLLER_2M_CODED_PHY_ENABLED=${CFG_BLE_CONTROLLER_2M_CODED_PHY_ENABLED} - -DCFG_BLE_CONTROLLER_EXT_ADV_SCAN_ENABLED=${CFG_BLE_CONTROLLER_EXT_ADV_SCAN_ENABLED} - -DCFG_BLE_L2CAP_COS_ENABLED=${CFG_BLE_L2CAP_COS_ENABLED} - -DCFG_BLE_CONTROLLER_PERIODIC_ADV_ENABLED=${CFG_BLE_CONTROLLER_PERIODIC_ADV_ENABLED} - -DCFG_BLE_CONTROLLER_PERIODIC_ADV_WR_ENABLED=${CFG_BLE_CONTROLLER_PERIODIC_ADV_WR_ENABLED} - -DCFG_BLE_CONTROLLER_CTE_ENABLED=${CFG_BLE_CONTROLLER_CTE_ENABLED} - -DCFG_BLE_CONTROLLER_POWER_CONTROL_ENABLED=${CFG_BLE_CONTROLLER_POWER_CONTROL_ENABLED} - -DCFG_BLE_CONNECTION_ENABLED=${CFG_BLE_CONNECTION_ENABLED} - -DCFG_BLE_CONTROLLER_CHAN_CLASS_ENABLED=${CFG_BLE_CONTROLLER_CHAN_CLASS_ENABLED} - -DCFG_BLE_CONTROLLER_BIS_ENABLED=${CFG_BLE_CONTROLLER_BIS_ENABLED} - -DCFG_BLE_CONNECTION_SUBRATING_ENABLED=${CFG_BLE_CONNECTION_SUBRATING_ENABLED} - -DCFG_BLE_CONTROLLER_CIS_ENABLED=${CFG_BLE_CONTROLLER_CIS_ENABLED} + -DCFG_BLE_CONTROLLER_SCAN_ENABLED=${CFG_BLE_CONTROLLER_SCAN_ENABLED} + -DCFG_BLE_CONTROLLER_PRIVACY_ENABLED=${CFG_BLE_CONTROLLER_PRIVACY_ENABLED} + -DCFG_BLE_SECURE_CONNECTIONS_ENABLED=${CFG_BLE_SECURE_CONNECTIONS_ENABLED} + -DCFG_BLE_CONTROLLER_DATA_LENGTH_EXTENSION_ENABLED=${CFG_BLE_CONTROLLER_DATA_LENGTH_EXTENSION_ENABLED} + -DCFG_BLE_CONTROLLER_2M_CODED_PHY_ENABLED=${CFG_BLE_CONTROLLER_2M_CODED_PHY_ENABLED} + -DCFG_BLE_CONTROLLER_EXT_ADV_SCAN_ENABLED=${CFG_BLE_CONTROLLER_EXT_ADV_SCAN_ENABLED} + -DCFG_BLE_L2CAP_COS_ENABLED=${CFG_BLE_L2CAP_COS_ENABLED} + -DCFG_BLE_CONTROLLER_PERIODIC_ADV_ENABLED=${CFG_BLE_CONTROLLER_PERIODIC_ADV_ENABLED} + -DCFG_BLE_CONTROLLER_PERIODIC_ADV_WR_ENABLED=${CFG_BLE_CONTROLLER_PERIODIC_ADV_WR_ENABLED} + -DCFG_BLE_CONTROLLER_CTE_ENABLED=${CFG_BLE_CONTROLLER_CTE_ENABLED} + -DCFG_BLE_CONTROLLER_POWER_CONTROL_ENABLED=${CFG_BLE_CONTROLLER_POWER_CONTROL_ENABLED} + -DCFG_BLE_CONNECTION_ENABLED=${CFG_BLE_CONNECTION_ENABLED} + -DCFG_BLE_CONTROLLER_CHAN_CLASS_ENABLED=${CFG_BLE_CONTROLLER_CHAN_CLASS_ENABLED} + -DCFG_BLE_CONTROLLER_BIS_ENABLED=${CFG_BLE_CONTROLLER_BIS_ENABLED} + -DCFG_BLE_CONNECTION_SUBRATING_ENABLED=${CFG_BLE_CONNECTION_SUBRATING_ENABLED} + -DCFG_BLE_CONTROLLER_CIS_ENABLED=${CFG_BLE_CONTROLLER_CIS_ENABLED} ) ########### End of modularity selection ########### @@ -165,66 +165,66 @@ set(CFG_BLE_NUM_AUX_SCAN_SLOTS "4") set(bt_max_conn "0") if(CONFIG_BT_PER_ADV_SYNC_MAX) - set(CFG_BLE_NUM_SYNC_SLOTS "${CONFIG_BT_PER_ADV_SYNC_MAX}") + set(CFG_BLE_NUM_SYNC_SLOTS "${CONFIG_BT_PER_ADV_SYNC_MAX}") endif() if(CONFIG_BT_EXT_ADV_MAX_ADV_SET) - set(CFG_BLE_NUM_ADV_SETS "${CONFIG_BT_EXT_ADV_MAX_ADV_SET}") + set(CFG_BLE_NUM_ADV_SETS "${CONFIG_BT_EXT_ADV_MAX_ADV_SET}") endif() if (CONFIG_BT_MAX_CONN) - #Maximum number of simultaneous connections - set(bt_max_conn "${CONFIG_BT_MAX_CONN}") + #Maximum number of simultaneous connections + set(bt_max_conn "${CONFIG_BT_MAX_CONN}") endif() if (CONFIG_BT_EATT_MAX) - # Maximum number of Enhanced ATT bearers - set(CFG_BLE_NUM_EATT_CHANNELS "${CONFIG_BT_EATT_MAX}") + # Maximum number of Enhanced ATT bearers + set(CFG_BLE_NUM_EATT_CHANNELS "${CONFIG_BT_EATT_MAX}") endif() if (CONFIG_BT_ISO_MAX_BIG) - # Maximum number of Broadcast Isochronous Groups (BIGs) to support - # A BIG can be used for either transmitting or receiving, but not at the same time. - if (CONFIG_BT_ISO_BROADCASTER) - set(CFG_BLE_NUM_BRC_BIG_MAX "${CONFIG_BT_ISO_MAX_BIG}") - endif() - if (CONFIG_BT_ISO_SYNC_RECEIVER) - set(CFG_BLE_NUM_SYNC_BIG_MAX "${CONFIG_BT_ISO_MAX_BIG}") - endif() + # Maximum number of Broadcast Isochronous Groups (BIGs) to support + # A BIG can be used for either transmitting or receiving, but not at the same time. + if (CONFIG_BT_ISO_BROADCASTER) + set(CFG_BLE_NUM_BRC_BIG_MAX "${CONFIG_BT_ISO_MAX_BIG}") + endif() + if (CONFIG_BT_ISO_SYNC_RECEIVER) + set(CFG_BLE_NUM_SYNC_BIG_MAX "${CONFIG_BT_ISO_MAX_BIG}") + endif() endif() if (CONFIG_BT_ISO_MAX_CHAN) - # Maximum number of simultaneous Bluetooth isochronous channels supported. - if (CONFIG_BT_ISO_BROADCASTER) - set(CFG_BLE_NUM_BRC_BIS_MAX "${CONFIG_BT_ISO_MAX_BIG}") - endif() - if (CONFIG_BT_ISO_SYNC_RECEIVER) - set(CFG_BLE_NUM_SYNC_BIS_MAX "${CONFIG_BT_ISO_MAX_BIG}") - endif() + # Maximum number of simultaneous Bluetooth isochronous channels supported. + if (CONFIG_BT_ISO_BROADCASTER) + set(CFG_BLE_NUM_BRC_BIS_MAX "${CONFIG_BT_ISO_MAX_BIG}") + endif() + if (CONFIG_BT_ISO_SYNC_RECEIVER) + set(CFG_BLE_NUM_SYNC_BIS_MAX "${CONFIG_BT_ISO_MAX_BIG}") + endif() endif() if (CONFIG_BT_ISO_MAX_CIG) - # Maximum number of CIGs that are supported by the host. - # A CIG can be used for either transmitting or receiving. - set(CFG_BLE_NUM_CIG_MAX "${CONFIG_BT_ISO_MAX_CIG}") + # Maximum number of CIGs that are supported by the host. + # A CIG can be used for either transmitting or receiving. + set(CFG_BLE_NUM_CIG_MAX "${CONFIG_BT_ISO_MAX_CIG}") endif() if (CONFIG_BT_ISO_MAX_CHAN) - # Maximum number of simultaneous Bluetooth isochronous channels supported. - set(CFG_BLE_NUM_CIS_MAX "${CONFIG_BT_ISO_MAX_CHAN}") + # Maximum number of simultaneous Bluetooth isochronous channels supported. + set(CFG_BLE_NUM_CIS_MAX "${CONFIG_BT_ISO_MAX_CHAN}") endif() zephyr_compile_definitions( - -DCFG_BLE_NUM_SYNC_SLOTS=${CFG_BLE_NUM_SYNC_SLOTS} - -DCFG_BLE_NUM_ADV_SETS=${CFG_BLE_NUM_ADV_SETS} - -DCFG_BLE_NUM_EATT_CHANNELS=${CFG_BLE_NUM_EATT_CHANNELS} - -DCFG_BLE_NUM_BRC_BIG_MAX=${CFG_BLE_NUM_BRC_BIG_MAX} - -DCFG_BLE_NUM_SYNC_BIG_MAX=${CFG_BLE_NUM_SYNC_BIG_MAX} - -DCFG_BLE_NUM_SYNC_BIS_MAX=${CFG_BLE_NUM_SYNC_BIS_MAX} - -DCFG_BLE_NUM_BRC_BIS_MAX=${CFG_BLE_NUM_BRC_BIS_MAX} - -DCFG_BLE_NUM_CIG_MAX=${CFG_BLE_NUM_CIG_MAX} - -DCFG_BLE_NUM_CIS_MAX=${CFG_BLE_NUM_CIS_MAX} - -DCFG_BLE_NUM_AUX_SCAN_SLOTS=${CFG_BLE_NUM_AUX_SCAN_SLOTS} + -DCFG_BLE_NUM_SYNC_SLOTS=${CFG_BLE_NUM_SYNC_SLOTS} + -DCFG_BLE_NUM_ADV_SETS=${CFG_BLE_NUM_ADV_SETS} + -DCFG_BLE_NUM_EATT_CHANNELS=${CFG_BLE_NUM_EATT_CHANNELS} + -DCFG_BLE_NUM_BRC_BIG_MAX=${CFG_BLE_NUM_BRC_BIG_MAX} + -DCFG_BLE_NUM_SYNC_BIG_MAX=${CFG_BLE_NUM_SYNC_BIG_MAX} + -DCFG_BLE_NUM_SYNC_BIS_MAX=${CFG_BLE_NUM_SYNC_BIS_MAX} + -DCFG_BLE_NUM_BRC_BIS_MAX=${CFG_BLE_NUM_BRC_BIS_MAX} + -DCFG_BLE_NUM_CIG_MAX=${CFG_BLE_NUM_CIG_MAX} + -DCFG_BLE_NUM_CIS_MAX=${CFG_BLE_NUM_CIS_MAX} + -DCFG_BLE_NUM_AUX_SCAN_SLOTS=${CFG_BLE_NUM_AUX_SCAN_SLOTS} ) ########### End of numeric value section ########### @@ -232,50 +232,50 @@ zephyr_compile_definitions( set(tasks "1") if(${CFG_BLE_CONTROLLER_EXT_ADV_SCAN_ENABLED}) - MATH(EXPR tasks "2 * ${CFG_BLE_NUM_ADV_SETS}") - if(${CFG_BLE_CONTROLLER_PERIODIC_ADV_ENABLED}) - MATH(EXPR tasks "${tasks} + ${CFG_BLE_NUM_ADV_SETS}") - if(${CFG_BLE_CONTROLLER_PERIODIC_ADV_WR_ENABLED} AND ${CFG_BLE_CONNECTION_ENABLED}) - MATH(EXPR tasks "${tasks} + 2 * ${CFG_BLE_NUM_ADV_SETS}") - endif() - if(${CFG_BLE_CONTROLLER_BIS_ENABLED}) - #radio_tasks += min(NUM_ADV_SETS_CONF, MAX_NUM_BRC_BIG) - min(temp ${CFG_BLE_NUM_ADV_SETS} ${CFG_BLE_NUM_BRC_BIG_MAX}) - MATH(EXPR tasks "${tasks} + ${temp}") - endif() - endif() + MATH(EXPR tasks "2 * ${CFG_BLE_NUM_ADV_SETS}") + if(${CFG_BLE_CONTROLLER_PERIODIC_ADV_ENABLED}) + MATH(EXPR tasks "${tasks} + ${CFG_BLE_NUM_ADV_SETS}") + if(${CFG_BLE_CONTROLLER_PERIODIC_ADV_WR_ENABLED} AND ${CFG_BLE_CONNECTION_ENABLED}) + MATH(EXPR tasks "${tasks} + 2 * ${CFG_BLE_NUM_ADV_SETS}") + endif() + if(${CFG_BLE_CONTROLLER_BIS_ENABLED}) + #radio_tasks += min(NUM_ADV_SETS_CONF, MAX_NUM_BRC_BIG) + min(temp ${CFG_BLE_NUM_ADV_SETS} ${CFG_BLE_NUM_BRC_BIG_MAX}) + MATH(EXPR tasks "${tasks} + ${temp}") + endif() + endif() endif() if(${CFG_BLE_CONTROLLER_CIS_ENABLED} AND ${CFG_BLE_CONNECTION_ENABLED}) - MATH(EXPR tasks "${tasks} + ${CFG_BLE_NUM_CIG_MAX}") + MATH(EXPR tasks "${tasks} + ${CFG_BLE_NUM_CIG_MAX}") endif() if(${CFG_BLE_CONTROLLER_SCAN_ENABLED}) - MATH(EXPR tasks "${tasks} + 1") - if(${CFG_BLE_CONTROLLER_EXT_ADV_SCAN_ENABLED}) - MATH(EXPR tasks "${tasks} + ${CFG_BLE_NUM_AUX_SCAN_SLOTS}") - if (${CFG_BLE_CONTROLLER_2M_CODED_PHY_ENABLED}) - MATH(EXPR tasks "${tasks} + 1") - endif() - if(${CFG_BLE_CONTROLLER_PERIODIC_ADV_ENABLED}) - # radio_tasks += min(NUM_AUX_SCAN_SLOTS_CONF, NUM_SYNC_SLOTS_CONF) - min(temp ${CFG_BLE_NUM_AUX_SCAN_SLOTS} ${CFG_BLE_NUM_SYNC_SLOTS}) - MATH(EXPR tasks "${tasks} + ${temp}") - if(${CFG_BLE_CONTROLLER_PERIODIC_ADV_WR_ENABLED} AND ${CFG_BLE_CONNECTION_ENABLED}) - # radio_tasks += 2 * min(NUM_AUX_SCAN_SLOTS_CONF, NUM_SYNC_SLOTS_CONF) - min(temp ${CFG_BLE_NUM_AUX_SCAN_SLOTS} ${CFG_BLE_NUM_SYNC_SLOTS}) - MATH(EXPR tasks "${tasks} + 2*${temp}") - endif() - if(${CFG_BLE_CONTROLLER_BIS_ENABLED}) - #radio_tasks += min(NUM_AUX_SCAN_SLOTS_CONF, MAX_NUM_SYNC_BIG) - min(temp ${CFG_BLE_NUM_AUX_SCAN_SLOTS} ${CFG_BLE_NUM_SYNC_BIG_MAX}) - MATH(EXPR tasks "${tasks} +${temp}") - endif() - endif() - endif() # ${CFG_BLE_CONTROLLER_EXT_ADV_SCAN_ENABLED} - if(${CFG_BLE_CONTROLLER_CIS_ENABLED} AND ${CFG_BLE_CONNECTION_ENABLED}) - MATH(EXPR tasks "${tasks} + ${CFG_BLE_NUM_CIG_MAX}") - endif() + MATH(EXPR tasks "${tasks} + 1") + if(${CFG_BLE_CONTROLLER_EXT_ADV_SCAN_ENABLED}) + MATH(EXPR tasks "${tasks} + ${CFG_BLE_NUM_AUX_SCAN_SLOTS}") + if (${CFG_BLE_CONTROLLER_2M_CODED_PHY_ENABLED}) + MATH(EXPR tasks "${tasks} + 1") + endif() + if(${CFG_BLE_CONTROLLER_PERIODIC_ADV_ENABLED}) + # radio_tasks += min(NUM_AUX_SCAN_SLOTS_CONF, NUM_SYNC_SLOTS_CONF) + min(temp ${CFG_BLE_NUM_AUX_SCAN_SLOTS} ${CFG_BLE_NUM_SYNC_SLOTS}) + MATH(EXPR tasks "${tasks} + ${temp}") + if(${CFG_BLE_CONTROLLER_PERIODIC_ADV_WR_ENABLED} AND ${CFG_BLE_CONNECTION_ENABLED}) + # radio_tasks += 2 * min(NUM_AUX_SCAN_SLOTS_CONF, NUM_SYNC_SLOTS_CONF) + min(temp ${CFG_BLE_NUM_AUX_SCAN_SLOTS} ${CFG_BLE_NUM_SYNC_SLOTS}) + MATH(EXPR tasks "${tasks} + 2*${temp}") + endif() + if(${CFG_BLE_CONTROLLER_BIS_ENABLED}) + #radio_tasks += min(NUM_AUX_SCAN_SLOTS_CONF, MAX_NUM_SYNC_BIG) + min(temp ${CFG_BLE_NUM_AUX_SCAN_SLOTS} ${CFG_BLE_NUM_SYNC_BIG_MAX}) + MATH(EXPR tasks "${tasks} +${temp}") + endif() + endif() + endif() # ${CFG_BLE_CONTROLLER_EXT_ADV_SCAN_ENABLED} + if(${CFG_BLE_CONTROLLER_CIS_ENABLED} AND ${CFG_BLE_CONNECTION_ENABLED}) + MATH(EXPR tasks "${tasks} + ${CFG_BLE_NUM_CIG_MAX}") + endif() endif() message(STATUS "Number of computed radio tasks: ${tasks}") @@ -291,17 +291,17 @@ set_source_files_properties(BLE_TransparentMode/STM32_BLE/App/dtm_cmd_db.c PROPE set_source_files_properties(STM32_BLE/stack/config/ble_stack_user_cfg.c PROPERTIES COMPILE_FLAGS -Wno-array-parameter) zephyr_library_sources(BLE_TransparentMode/STM32_BLE/Target/bleplat_cntr.c) zephyr_library_sources(BLE_TransparentMode/STM32_BLE/Target/bleplat.c) -zephyr_library_sources(BLE_TransparentMode/System/Modules/PKAMGR/Src/pka_manager.c) -zephyr_library_sources(BLE_TransparentMode/System/Interfaces/hw_aes.c) -zephyr_library_sources(BLE_TransparentMode/System/Interfaces/hw_pka.c) -zephyr_library_sources(BLE_TransparentMode/System/Interfaces/hw_rng.c) -zephyr_library_sources(BLE_TransparentMode/System/Modules/osal_memcpy.s) +zephyr_library_sources(Common/BLE/Modules/PKAMGR/Src/pka_manager.c) +zephyr_library_sources(Common/BLE/Interfaces/hw_aes.c) +zephyr_library_sources(Common/BLE/Interfaces/hw_pka.c) +zephyr_library_sources(Common/BLE/Interfaces/hw_rng.c) +zephyr_library_sources(Common/BLE/Modules/osal_memcpy.s) zephyr_library_sources(BLE_TransparentMode/STM32_BLE/App/adv_buff_alloc_tiny.c) zephyr_library_sources(BLE_TransparentMode/STM32_BLE/App/transport_layer.c) zephyr_library_sources(BLE_TransparentMode/STM32_BLE/App/dtm_preprocess_events.c) zephyr_library_sources(BLE_TransparentMode/STM32_BLE/App/adv_buff_alloc.c) -zephyr_library_sources(BLE_TransparentMode/System/Modules/RADIO_utils/Src/RADIO_utils.c) -zephyr_library_sources(BLE_TransparentMode/System/Modules/miscutil.c) +zephyr_library_sources(Common/BLE/Modules/RADIO_utils/Src/RADIO_utils.c) +zephyr_library_sources(Common/BLE/Modules/miscutil.c) zephyr_library_sources(BLE_TransparentMode/STM32_BLE/App/pawr_buff_alloc.c) zephyr_library_sources(STM32_BLE/stack/config/ble_stack_user_cfg.c) zephyr_library_sources(BLE_TransparentMode/STM32_BLE/App/dtm_cmds.c) diff --git a/lib/stm32wb0/BLE_TransparentMode/System/Interfaces/hw_aes.c b/lib/stm32wb0/Common/BLE/Interfaces/hw_aes.c similarity index 100% rename from lib/stm32wb0/BLE_TransparentMode/System/Interfaces/hw_aes.c rename to lib/stm32wb0/Common/BLE/Interfaces/hw_aes.c diff --git a/lib/stm32wb0/BLE_TransparentMode/System/Interfaces/hw_aes.h b/lib/stm32wb0/Common/BLE/Interfaces/hw_aes.h similarity index 100% rename from lib/stm32wb0/BLE_TransparentMode/System/Interfaces/hw_aes.h rename to lib/stm32wb0/Common/BLE/Interfaces/hw_aes.h diff --git a/lib/stm32wb0/BLE_TransparentMode/System/Interfaces/hw_pka.c b/lib/stm32wb0/Common/BLE/Interfaces/hw_pka.c similarity index 99% rename from lib/stm32wb0/BLE_TransparentMode/System/Interfaces/hw_pka.c rename to lib/stm32wb0/Common/BLE/Interfaces/hw_pka.c index 70737556e..085288345 100644 --- a/lib/stm32wb0/BLE_TransparentMode/System/Interfaces/hw_pka.c +++ b/lib/stm32wb0/Common/BLE/Interfaces/hw_pka.c @@ -948,7 +948,7 @@ void HW_PKA_P256_StartPointCheck( const uint32_t* x, const uint32_t* y ) /* Set the point coordinate y */ HW_PKA_WriteOperand( PKA_POINT_CHECK_IN_INITIAL_POINT_Y, 8, y ); /* Set the Montgomery parameter */ - HW_PKA_WriteOperand( PKA_ECC_SCALAR_MUL_IN_MONTGOMERY_PARAM, 8, HW_PKA_P256_r2 ); + HW_PKA_WriteOperand( PKA_POINT_CHECK_IN_MONTGOMERY, 8, HW_PKA_P256_r2 ); /* Set the coefficient |b| */ HW_PKA_WriteOperand( PKA_POINT_CHECK_IN_B_COEFF, 8, HW_PKA_P256_b ); #endif /* STM32WB09 */ diff --git a/lib/stm32wb0/BLE_TransparentMode/System/Interfaces/hw_pka.h b/lib/stm32wb0/Common/BLE/Interfaces/hw_pka.h similarity index 100% rename from lib/stm32wb0/BLE_TransparentMode/System/Interfaces/hw_pka.h rename to lib/stm32wb0/Common/BLE/Interfaces/hw_pka.h diff --git a/lib/stm32wb0/BLE_TransparentMode/System/Interfaces/hw_rng.c b/lib/stm32wb0/Common/BLE/Interfaces/hw_rng.c similarity index 100% rename from lib/stm32wb0/BLE_TransparentMode/System/Interfaces/hw_rng.c rename to lib/stm32wb0/Common/BLE/Interfaces/hw_rng.c diff --git a/lib/stm32wb0/BLE_TransparentMode/System/Interfaces/hw_rng.h b/lib/stm32wb0/Common/BLE/Interfaces/hw_rng.h similarity index 100% rename from lib/stm32wb0/BLE_TransparentMode/System/Interfaces/hw_rng.h rename to lib/stm32wb0/Common/BLE/Interfaces/hw_rng.h diff --git a/lib/stm32wb0/BLE_TransparentMode/System/Modules/PKAMGR/Inc/pka_manager.h b/lib/stm32wb0/Common/BLE/Modules/PKAMGR/Inc/pka_manager.h similarity index 100% rename from lib/stm32wb0/BLE_TransparentMode/System/Modules/PKAMGR/Inc/pka_manager.h rename to lib/stm32wb0/Common/BLE/Modules/PKAMGR/Inc/pka_manager.h diff --git a/lib/stm32wb0/BLE_TransparentMode/System/Modules/PKAMGR/Src/pka_manager.c b/lib/stm32wb0/Common/BLE/Modules/PKAMGR/Src/pka_manager.c similarity index 100% rename from lib/stm32wb0/BLE_TransparentMode/System/Modules/PKAMGR/Src/pka_manager.c rename to lib/stm32wb0/Common/BLE/Modules/PKAMGR/Src/pka_manager.c diff --git a/lib/stm32wb0/BLE_TransparentMode/System/Modules/RADIO_utils/Inc/RADIO_utils.h b/lib/stm32wb0/Common/BLE/Modules/RADIO_utils/Inc/RADIO_utils.h similarity index 100% rename from lib/stm32wb0/BLE_TransparentMode/System/Modules/RADIO_utils/Inc/RADIO_utils.h rename to lib/stm32wb0/Common/BLE/Modules/RADIO_utils/Inc/RADIO_utils.h diff --git a/lib/stm32wb0/BLE_TransparentMode/System/Modules/RADIO_utils/Src/RADIO_utils.c b/lib/stm32wb0/Common/BLE/Modules/RADIO_utils/Src/RADIO_utils.c similarity index 96% rename from lib/stm32wb0/BLE_TransparentMode/System/Modules/RADIO_utils/Src/RADIO_utils.c rename to lib/stm32wb0/Common/BLE/Modules/RADIO_utils/Src/RADIO_utils.c index 4f09cc043..c5f424670 100644 --- a/lib/stm32wb0/BLE_TransparentMode/System/Modules/RADIO_utils/Src/RADIO_utils.c +++ b/lib/stm32wb0/Common/BLE/Modules/RADIO_utils/Src/RADIO_utils.c @@ -67,25 +67,25 @@ /* Expected TX output power (dBm) for each PA level when SMPS voltage is 1.4V */ static const int8_t normal_pa_level_table[TX_POWER_LEVELS] = { - -54, -21, -20, -19, -17, -16, -15, -14, - -13, -12, -11, -10, -9, -8, -7, -6, - -6, -4, -3, -3, -2, -2, -1, -1, - 0, 0, 1, 2, 3, 4, 5, 6 + -60, -23, -22, -21, -20, -18, -17, -16, + -15, -14, -13, -13, -12, -11, -10, -9, + -8, -7, -6, -5, -4, -3, -3, -2, + -1, 0, 2, 3, 4, 5, 5, 6 }; #if defined(STM32WB09) static const int8_t high_power_pa_level_table[HP_TX_POWER_LEVELS] = { - -54, -21, -20, -19, -17, -16, -15, -14, - -13, -12, -11, -10, -9, -8, -7, -6, - -6, -4, -3, -3, -2, -2, -1, -1, - 0, 0, 1, 2, 3, 4, 5, 6, - 8 + -60, -24, -23, -22, -21, -19, -18, -17, + -16, -15, -14, -13, -12, -11, -10, -9, + -8, -7, -6, -5, -4, -4, -3, -2, + -1, 0, 1, 2, 3, 4, 5, 6, + 7 }; #else /* Expected TX output power (dBm) for each PA level when SMPS voltage is 1.9V (high power mode). */ static const int8_t high_power_pa_level_table[HP_TX_POWER_LEVELS] = { - -54, -19, -18, -17, -16, -15, -14, -13, + -60, -19, -18, -17, -16, -15, -14, -13, -12, -11, -10, -9, -8, -7, -6, -5, -4, -3, -3, -2, -1, 0, 1, 2, 3, 8, 8, 8, 8, 8, 8, 8 @@ -344,7 +344,7 @@ int8_t RADIO_UpdateAvgRSSI(int8_t avg_rssi, int8_t rssi, uint8_t rssi_filter_coe void RADIO_AntIdxRemap(uint8_t AntPattLen, uint8_t *pAntRamTable, const uint8_t* pAntPatt) { -#if defined(STM32WB07) || defined(STM32WB06) || defined(STM32WB09) +#if defined(STM32WB05) || defined(STM32WB09) for (uint8_t i=0; i 0U) ? \ - (12U + 4U) \ - : 0U) - -#define BLE_STACK_BIG_SIZE(NUM_BRC_BIG, NUM_BRC_BIS, NUM_SYNC_BIG, NUM_SYNC_BIS) ((((NUM_BRC_BIG) + (NUM_SYNC_BIG)) > 0U) ? \ - (248U * (NUM_BRC_BIG) + \ - 8U * (NUM_BRC_BIG) * (NUM_BRC_BIS) + \ - 296U * (NUM_SYNC_BIG) + \ - 20U * (NUM_SYNC_BIS) * (NUM_SYNC_BIG)) \ - : 0U) - -#define BLE_STACK_CIG_SIZE(NUM_CIG, NUM_CIS) (((NUM_CIG) > 0U) ? \ - (16U + 56U + \ - 168U * (NUM_CIG) + \ - 192U * (NUM_CIS)) \ - : 0U) +#define BLE_STACK_ISO_CMN(NUM_ISO_GROUPS) (((NUM_ISO_GROUPS) > 0U) ? \ + (12U + 56U * (NUM_ISO_GROUPS)) \ + : 0U) +#define BLE_STACK_BIG_SIZE(BIS_EN, SYNC_EN, NUM_BRC_BIG, NUM_BRC_BIS, NUM_SYNC_BIG, NUM_SYNC_BIS) \ + (((BIS_EN) > 0U) ? \ + ((244U + 8U * (NUM_BRC_BIS)) * (NUM_BRC_BIG) + \ + (((SYNC_EN) > 0U) ? \ + ((280U + 20U * (NUM_SYNC_BIS)) * (NUM_SYNC_BIG)) \ + : 0U)) \ + : 0U) + +#define BLE_STACK_CIG_SIZE(CONN_SUPP_EN, NUM_CIG, NUM_CIS) ((((NUM_CIG) > 0U) && ((CONN_SUPP_EN) != 0U)) ? \ + (56U + \ + 128U * (NUM_CIG) + \ + 180U * (NUM_CIS)) \ + : 0U) #define BLE_STACK_ISOAL_SIZE(NUM_TX_STREAMS, NUM_RX_STREAMS) ((((NUM_TX_STREAMS) + (NUM_RX_STREAMS)) > 0U) ? \ - (20U + \ - 12U * ((NUM_TX_STREAMS) + (NUM_RX_STREAMS)) + \ - 52U * (NUM_TX_STREAMS) + \ - 28U * (NUM_RX_STREAMS)) \ + (24U + \ + 60U * (NUM_TX_STREAMS) + \ + 40U * (NUM_RX_STREAMS)) \ : 0U) -#define BLE_STACK_ISO_SIZE(NUM_BRC_BIG, NUM_BRC_BIS, NUM_SYNC_BIG, NUM_SYNC_BIS, NUM_CIG, NUM_CIS) \ - (BLE_STACK_ISO_CMN_SIZE(NUM_BRC_BIG, NUM_SYNC_BIG, NUM_CIG) + \ - BLE_STACK_BIG_SIZE(NUM_BRC_BIG, NUM_BRC_BIS, NUM_SYNC_BIG, NUM_SYNC_BIS) + \ - BLE_STACK_CIG_SIZE(NUM_CIG, NUM_CIS) + \ +#define BLE_STACK_ISO_SIZE(EXT_ADV_SCN_EN, PER_ADV_SCN_EN, SCN_EN, CONN_SUPP_EN, NUM_BRC_BIG, NUM_BRC_BIS, NUM_SYNC_BIG, NUM_SYNC_BIS, NUM_CIG, NUM_CIS) \ + (BLE_STACK_ISO_CMN((NUM_BRC_BIG) + (NUM_SYNC_BIG) + (NUM_CIG)) + \ + BLE_STACK_BIG_SIZE(((EXT_ADV_SCN_EN) + (PER_ADV_SCN_EN)), SCN_EN, NUM_BRC_BIG, NUM_BRC_BIS, NUM_SYNC_BIG, NUM_SYNC_BIS) + \ + BLE_STACK_CIG_SIZE(CONN_SUPP_EN, NUM_CIG, NUM_CIS) + \ BLE_STACK_ISOAL_SIZE((NUM_BRC_BIG) * (NUM_BRC_BIS) + (NUM_CIS), \ (NUM_SYNC_BIG) * (NUM_SYNC_BIS) + (NUM_CIS))) @@ -196,16 +185,18 @@ * - a part, that may be considered "fixed", i.e., independent from the above * mentioned parameters. */ -# define BLE_STACK_FIXED_BUFFER_SIZE_BYTES (970U) +# define BLE_STACK_FIXED_BUFFER_SIZE_BYTES (1058U) /** * Amount of memory needed by each radio link */ -# define COEFF_CONN_SUPP_EN (840U + BLE_STACK_GATT_ATTRIBUTE_SIZE * BLE_STACK_NUM_GATT_MANDATORY_ATTRIBUTES) -# define COEFF_NUM_OF_LINKS_0 (48U) -# define COEFF_NUM_OF_LINKS_1 (656U) +# define COEFF_CONN_SUPP_EN (980U + BLE_STACK_GATT_ATTRIBUTE_SIZE * BLE_STACK_NUM_GATT_MANDATORY_ATTRIBUTES) +# define COEFF_NUM_OF_LINKS_0 (8U) +# define COEFF_NUM_OF_LINKS_1 (664U) # define BLE_STACK_LINKS_SIZE(CONN_SUPP_EN, NUM_OF_LINKS) \ - (((CONN_SUPP_EN) == 1U) || ((NUM_OF_LINKS) > 0U) ? COEFF_CONN_SUPP_EN * (CONN_SUPP_EN) + COEFF_NUM_OF_LINKS_0 * (NUM_OF_LINKS) + COEFF_NUM_OF_LINKS_1 * (CONN_SUPP_EN) * (NUM_OF_LINKS) : 0U) + (((CONN_SUPP_EN) == 1U) || ((NUM_OF_LINKS) > 0U) ? COEFF_CONN_SUPP_EN * (CONN_SUPP_EN) + \ + COEFF_NUM_OF_LINKS_0 * (NUM_OF_LINKS) + \ + COEFF_NUM_OF_LINKS_1 * (CONN_SUPP_EN) * (NUM_OF_LINKS) : 0U) /** * Amount of memory needed for mem. blocks allocated for connections @@ -223,7 +214,7 @@ * subtracted from the total */ # define BLE_STACK_CONTROLLER_EXT_ADV_SIZE(ENABLED, NUM_ADV_SET, NUM_AUX_EVENT, NUM_OF_LINKS) \ - (((ENABLED) == 1U) ? -276U + 368U * (NUM_ADV_SET) + 0U * (NUM_AUX_EVENT) + 0U * (NUM_OF_LINKS) : 0U) + (((ENABLED) == 1U) ? -304U + 396U * (NUM_ADV_SET) + 0U * (NUM_AUX_EVENT) + 0U * (NUM_OF_LINKS) : 0U) /** * Amount of memory needed for the Filter Accept List and, if connections are supported, also for connection ID list @@ -245,10 +236,10 @@ * Amount of memory needed to support periodic advertising and synchronizing feature */ # define BLE_STACK_CONTROLLER_PERIODIC_ADV_WR_SIZE(PER_ADV_WR_EN, CONN_SUPP_EN, NUM_ADV_SET, NUM_SUBEVENTS_PAWR, MAX_SUBEVENT_DATA_COUNT_PAWR) \ - ((((PER_ADV_WR_EN) == 1U) && ((CONN_SUPP_EN) == 1U)) ? (132U + 8U * (NUM_SUBEVENTS_PAWR) + 16U * (MAX_SUBEVENT_DATA_COUNT_PAWR)) * (NUM_ADV_SET) : 0U) + ((((PER_ADV_WR_EN) == 1U) && ((CONN_SUPP_EN) == 1U)) ? (228U + 12U * (NUM_SUBEVENTS_PAWR) + 16U * (MAX_SUBEVENT_DATA_COUNT_PAWR)) * (NUM_ADV_SET) : 0U) # define BLE_STACK_CONTROLLER_PERIODIC_ADV_SIZE(PER_ADV_EN, PER_ADV_WR_EN, CONN_SUPP_EN, NUM_LINKS, NUM_ADV_SET, NUM_SUBEVENTS_PAWR, MAX_SUBEVENT_DATA_COUNT_PAWR) \ - (((PER_ADV_EN) == 1U) ? (156U * (NUM_ADV_SET) + 32U * (NUM_LINKS) + \ + (((PER_ADV_EN) == 1U) ? (204U * (NUM_ADV_SET) + 32U * (NUM_LINKS) + \ BLE_STACK_CONTROLLER_PERIODIC_ADV_WR_SIZE(PER_ADV_WR_EN, CONN_SUPP_EN, NUM_ADV_SET, NUM_SUBEVENTS_PAWR, MAX_SUBEVENT_DATA_COUNT_PAWR)) : \ 0U) @@ -257,25 +248,25 @@ */ # define BLE_STACK_BASE_SIZE(CONN_SUPP_EN) (((CONN_SUPP_EN) == 1U) ? 32U : 20U) -# define BLE_STACK_PAST_SIZE(CONN_SUPP_EN, NUM_OF_LINKS) (((CONN_SUPP_EN) == 1U) ? 24U * (NUM_OF_LINKS) : 0U) +# define BLE_STACK_PAST_SIZE(CONN_SUPP_EN, NUM_OF_LINKS) (((CONN_SUPP_EN) == 1U) ? 8U * (NUM_OF_LINKS) : 0U) # define BLE_STACK_PER_SYNC_SIZE(PER_ADV_EN, CONN_SUPP_EN, NUM_SYNC_SLOTS, NUM_OF_LINKS, ADV_LIST_LIZE)\ - (((PER_ADV_EN) == 1U) ? BLE_STACK_BASE_SIZE(CONN_SUPP_EN) + 144U * (NUM_SYNC_SLOTS) + 8U * (1U << (ADV_LIST_LIZE)) + BLE_STACK_PAST_SIZE(CONN_SUPP_EN, NUM_OF_LINKS) : 0U) + (((PER_ADV_EN) == 1U) ? BLE_STACK_BASE_SIZE(CONN_SUPP_EN) + 192U * (NUM_SYNC_SLOTS) + 8U * (1U << (ADV_LIST_LIZE)) + BLE_STACK_PAST_SIZE(CONN_SUPP_EN, NUM_OF_LINKS) : 0U) # define BLE_STACK_PER_SYNC_WR_SIZE(PER_ADV_EN, PER_ADV_WR_EN, CONN_SUPP_EN, NUM_SYNC_SLOTS, NUM_SYNC_SUBEVENTS)\ - (((PER_ADV_WR_EN & PER_ADV_EN & CONN_SUPP_EN) == 1U) ? 176U * (NUM_SYNC_SLOTS) + ALIGN_32(NUM_SYNC_SUBEVENTS) : 0U) + (((PER_ADV_WR_EN & PER_ADV_EN & CONN_SUPP_EN) == 1U) ? 224U * (NUM_SYNC_SLOTS) + ALIGN_32(NUM_SYNC_SUBEVENTS) : 0U) # define BLE_STACK_CONTROLLER_SCAN_SIZE(SCAN_EN, EXT_ADV_EN, PER_ADV_EN, PER_ADV_WR_EN, CONN_SUPP_EN, NUM_AUX_EVENT,\ NUM_SYNC_SLOTS, NUM_OF_LINKS, ADV_LIST_LIZE, NUM_SYNC_SUBEVENTS) \ - (((SCAN_EN) == 1U) ? 320U + (192U + 48U * (NUM_AUX_EVENT) + \ - BLE_STACK_PER_SYNC_SIZE(PER_ADV_EN, CONN_SUPP_EN, NUM_SYNC_SLOTS, NUM_OF_LINKS, ADV_LIST_LIZE) + \ - BLE_STACK_PER_SYNC_WR_SIZE(PER_ADV_EN, PER_ADV_WR_EN, CONN_SUPP_EN, NUM_SYNC_SLOTS, NUM_SYNC_SUBEVENTS)) * (EXT_ADV_EN) : 0U) + (((SCAN_EN) == 1U) ? 564U + (((EXT_ADV_EN) == 1U ) ? (192U + 96U * (NUM_AUX_EVENT) + \ + BLE_STACK_PER_SYNC_SIZE(PER_ADV_EN, CONN_SUPP_EN, NUM_SYNC_SLOTS, NUM_OF_LINKS, ADV_LIST_LIZE) + \ + BLE_STACK_PER_SYNC_WR_SIZE(PER_ADV_EN, PER_ADV_WR_EN, CONN_SUPP_EN, NUM_SYNC_SLOTS, NUM_SYNC_SUBEVENTS)) : 0U) : 0U) /** * Amount of memory needed to support controller privacy feature */ -# define BLE_STACK_CONTROLLER_PRIV_SIZE(ENABLED, FILTER_ACCEPT_LIST_SIZE_LOG2) (((ENABLED) == 1U) ? 104U + 80U * (1U << (FILTER_ACCEPT_LIST_SIZE_LOG2)) : 0U) +# define BLE_STACK_CONTROLLER_PRIV_SIZE(ENABLED, FILTER_ACCEPT_LIST_SIZE_LOG2) (((ENABLED) == 1U) ? 112U + 80U * (1U << (FILTER_ACCEPT_LIST_SIZE_LOG2)) : 0U) /** * Amount of memory needed to support CTE feature @@ -302,7 +293,7 @@ /** * Amount of memory needed to support PCL feature */ -# define BLE_STACK_PCL_NUM_OF_LINKS(NUM_OF_LINKS) (32U * (NUM_OF_LINKS)) +# define BLE_STACK_PCL_NUM_OF_LINKS(NUM_OF_LINKS) (36U * (NUM_OF_LINKS)) # define BLE_STACK_PCL_SIZE(CONN_SUPP_EN, PCL_EN, NUM_OF_LINKS) (((CONN_SUPP_EN) == 1U) && ((PCL_EN) == 1U) ? 20U + BLE_STACK_PCL_NUM_OF_LINKS(NUM_OF_LINKS) : 0U) /** @@ -311,6 +302,16 @@ # define BLE_STACK_CHC_NUM_OF_LINKS(NUM_OF_LINKS) (28U * (NUM_OF_LINKS)) # define BLE_STACK_CHC_SIZE(CONN_SUPP_EN, CHC_EN, NUM_OF_LINKS) (((CONN_SUPP_EN) == 1U) && ((CHC_EN) == 1U) ? BLE_STACK_CHC_NUM_OF_LINKS(NUM_OF_LINKS) : 0U) +/** + * Amount of memory needed for Link Layer extra Control Procedure contexts + */ +# define BLE_STACK_EXTRA_LL_PROCEDURE_CONTEXTS_SIZE(CONN_SUPP_EN, EXTRA_LL_PROCEDURE_CONTEXTS) (((CONN_SUPP_EN) == 1U) ? (72U * (EXTRA_LL_PROCEDURE_CONTEXTS)) : 0U) + +/** +* Amount of memory needed to support the logging feature +*/ +#define BLE_STACK_LOG_SIZE(BLE_STACK_LOG_EN) (((BLE_STACK_LOG_EN) == 1U) ? 2540U : 0U) + /** * Amount of memory needed by FIFOs */ @@ -329,16 +330,18 @@ #else // (BLESTACK_CONTROLLER_ONLY == 1) -# define BLE_STACK_FIXED_BUFFER_SIZE_BYTES (828U) +# define BLE_STACK_FIXED_BUFFER_SIZE_BYTES (908U) /** * Amount of memory needed by each radio link */ -# define COEFF_CONN_SUPP_EN (180U) -# define COEFF_NUM_OF_LINKS_0 (48U) // [DB] NOTE: scheduler's tasks -# define COEFF_NUM_OF_LINKS_1 (484U) +# define COEFF_CONN_SUPP_EN (312U) +# define COEFF_NUM_OF_LINKS_0 (8U) // [DB] NOTE: scheduler's tasks +# define COEFF_NUM_OF_LINKS_1 (488U) # define BLE_STACK_LINKS_SIZE(CONN_SUPP_EN, NUM_OF_LINKS) \ - (((CONN_SUPP_EN) == 1U) || ((NUM_OF_LINKS) > 0U) ? COEFF_CONN_SUPP_EN * (CONN_SUPP_EN) + COEFF_NUM_OF_LINKS_0 * (NUM_OF_LINKS) + COEFF_NUM_OF_LINKS_1 * (CONN_SUPP_EN) * (NUM_OF_LINKS) : 0U) + (((CONN_SUPP_EN) == 1U) || ((NUM_OF_LINKS) > 0U) ? COEFF_CONN_SUPP_EN * (CONN_SUPP_EN) + \ + COEFF_NUM_OF_LINKS_0 * (NUM_OF_LINKS) + \ + COEFF_NUM_OF_LINKS_1 * (CONN_SUPP_EN) * (NUM_OF_LINKS) : 0U) /** * Amount of memory needed for mem. blocks allocated for connections @@ -356,7 +359,7 @@ * subtracted from the total */ # define BLE_STACK_CONTROLLER_EXT_ADV_SIZE(ENABLED, NUM_ADV_SET, NUM_AUX_EVENT, NUM_OF_LINKS) \ - (((ENABLED) == 1U) ? -256U + 348U * (NUM_ADV_SET) + 0U * (NUM_AUX_EVENT) + 0U * (NUM_OF_LINKS) : 0U) + (((ENABLED) == 1U) ? -284U + 376U * (NUM_ADV_SET) + 0U * (NUM_AUX_EVENT) + 0U * (NUM_OF_LINKS) : 0U) /** * Amount of memory needed for the Filter Accept List and, if connections are supported, also for connection ID list @@ -378,10 +381,10 @@ * Amount of memory needed to support periodic advertising and synchronizing feature */ # define BLE_STACK_CONTROLLER_PERIODIC_ADV_WR_SIZE(PER_ADV_WR_EN, CONN_SUPP_EN, NUM_ADV_SET, NUM_SUBEVENTS_PAWR, MAX_SUBEVENT_DATA_COUNT_PAWR) \ - ((((PER_ADV_WR_EN) == 1U) && ((CONN_SUPP_EN) == 1U)) ? (132U + 8U * (NUM_SUBEVENTS_PAWR) + 16U * (MAX_SUBEVENT_DATA_COUNT_PAWR)) * (NUM_ADV_SET) : 0U) + ((((PER_ADV_WR_EN) == 1U) && ((CONN_SUPP_EN) == 1U)) ? (132U + 96U + 12U * (NUM_SUBEVENTS_PAWR) + 16U * (MAX_SUBEVENT_DATA_COUNT_PAWR)) * (NUM_ADV_SET) : 0U) # define BLE_STACK_CONTROLLER_PERIODIC_ADV_SIZE(PER_ADV_EN, PER_ADV_WR_EN, CONN_SUPP_EN, NUM_LINKS, NUM_ADV_SET, NUM_SUBEVENTS_PAWR, MAX_SUBEVENT_DATA_COUNT_PAWR) \ - (((PER_ADV_EN) == 1U) ? (156U * (NUM_ADV_SET) + 32U * (NUM_LINKS) + \ + (((PER_ADV_EN) == 1U) ? (204U * (NUM_ADV_SET) + 32U * (NUM_LINKS) + \ BLE_STACK_CONTROLLER_PERIODIC_ADV_WR_SIZE(PER_ADV_WR_EN, CONN_SUPP_EN, NUM_ADV_SET, NUM_SUBEVENTS_PAWR, MAX_SUBEVENT_DATA_COUNT_PAWR)) : \ 0U) @@ -390,24 +393,24 @@ */ # define BLE_STACK_BASE_SIZE(CONN_SUPP_EN) (((CONN_SUPP_EN) == 1U) ? 32U : 20U) -# define BLE_STACK_PAST_SIZE(CONN_SUPP_EN, NUM_OF_LINKS) (((CONN_SUPP_EN) == 1U) ? 24U * (NUM_OF_LINKS) : 0U) +# define BLE_STACK_PAST_SIZE(CONN_SUPP_EN, NUM_OF_LINKS) (((CONN_SUPP_EN) == 1U) ? 8U * (NUM_OF_LINKS) : 0U) # define BLE_STACK_PER_SYNC_SIZE(PER_ADV_EN, CONN_SUPP_EN, NUM_SYNC_SLOTS, NUM_OF_LINKS, ADV_LIST_LIZE)\ - (((PER_ADV_EN) == 1U) ? BLE_STACK_BASE_SIZE(CONN_SUPP_EN) + 144U * (NUM_SYNC_SLOTS) + 8U * (1U << (ADV_LIST_LIZE)) + BLE_STACK_PAST_SIZE(CONN_SUPP_EN, NUM_OF_LINKS) : 0U) + (((PER_ADV_EN) == 1U) ? BLE_STACK_BASE_SIZE(CONN_SUPP_EN) + 192U * (NUM_SYNC_SLOTS) + 8U * (1U << (ADV_LIST_LIZE)) + BLE_STACK_PAST_SIZE(CONN_SUPP_EN, NUM_OF_LINKS) : 0U) # define BLE_STACK_PER_SYNC_WR_SIZE(PER_ADV_EN, PER_ADV_WR_EN, CONN_SUPP_EN, NUM_SYNC_SLOTS, NUM_SYNC_SUBEVENTS)\ - (((PER_ADV_WR_EN & PER_ADV_EN & CONN_SUPP_EN) == 1U) ? 176U * (NUM_SYNC_SLOTS) + ALIGN_32(NUM_SYNC_SUBEVENTS) : 0U) + (((PER_ADV_WR_EN & PER_ADV_EN & CONN_SUPP_EN) == 1U) ? 224U * (NUM_SYNC_SLOTS) + ALIGN_32(NUM_SYNC_SUBEVENTS) : 0U) # define BLE_STACK_CONTROLLER_SCAN_SIZE(SCAN_EN, EXT_ADV_EN, PER_ADV_EN, PER_ADV_WR_EN, CONN_SUPP_EN, NUM_AUX_EVENT,\ NUM_SYNC_SLOTS, NUM_OF_LINKS, ADV_LIST_LIZE, NUM_SYNC_SUBEVENTS) \ - (((SCAN_EN) == 1U) ? 320U + (164U + 48U * (NUM_AUX_EVENT) + \ + (((SCAN_EN) == 1U) ? 564U + (((EXT_ADV_EN) == 1U ) ? (164U + 96U * (NUM_AUX_EVENT) + \ BLE_STACK_PER_SYNC_SIZE(PER_ADV_EN, CONN_SUPP_EN, NUM_SYNC_SLOTS, NUM_OF_LINKS, ADV_LIST_LIZE) + \ - BLE_STACK_PER_SYNC_WR_SIZE(PER_ADV_EN, PER_ADV_WR_EN, CONN_SUPP_EN, NUM_SYNC_SLOTS, NUM_SYNC_SUBEVENTS)) * (EXT_ADV_EN) : 0U) + BLE_STACK_PER_SYNC_WR_SIZE(PER_ADV_EN, PER_ADV_WR_EN, CONN_SUPP_EN, NUM_SYNC_SLOTS, NUM_SYNC_SUBEVENTS)) : 0U) : 0U) /** * Amount of memory needed to support controller privacy feature */ -# define BLE_STACK_CONTROLLER_PRIV_SIZE(ENABLED, FILTER_ACCEPT_LIST_SIZE_LOG2) (((ENABLED) == 1U) ? 104U + 80U * (1U << (FILTER_ACCEPT_LIST_SIZE_LOG2)) : 0U) +# define BLE_STACK_CONTROLLER_PRIV_SIZE(ENABLED, FILTER_ACCEPT_LIST_SIZE_LOG2) (((ENABLED) == 1U) ? 112U + 80U * (1U << (FILTER_ACCEPT_LIST_SIZE_LOG2)) : 0U) /** * Amount of memory needed to support CTE feature @@ -435,7 +438,7 @@ /** * Amount of memory needed to support PCL feature */ -# define BLE_STACK_PCL_NUM_OF_LINKS(NUM_OF_LINKS) (32U * (NUM_OF_LINKS)) +# define BLE_STACK_PCL_NUM_OF_LINKS(NUM_OF_LINKS) (36U * (NUM_OF_LINKS)) # define BLE_STACK_PCL_SIZE(CONN_SUPP_EN, PCL_EN, NUM_OF_LINKS) (((CONN_SUPP_EN) == 1U) && ((PCL_EN) == 1U) ? 20U + BLE_STACK_PCL_NUM_OF_LINKS(NUM_OF_LINKS) : 0U) /** @@ -444,6 +447,16 @@ # define BLE_STACK_CHC_NUM_OF_LINKS(NUM_OF_LINKS) (28U * (NUM_OF_LINKS)) # define BLE_STACK_CHC_SIZE(CONN_SUPP_EN, CHC_EN, NUM_OF_LINKS) (((CONN_SUPP_EN) == 1U) && ((CHC_EN) == 1U) ? BLE_STACK_CHC_NUM_OF_LINKS(NUM_OF_LINKS) : 0U) +/** + * Amount of memory needed for extra Link Layer Control Procedure contexts + */ +# define BLE_STACK_EXTRA_LL_PROCEDURE_CONTEXTS_SIZE(CONN_SUPP_EN, EXTRA_LL_PROCEDURE_CONTEXTS) (((CONN_SUPP_EN) == 1U) ? (72U * (EXTRA_LL_PROCEDURE_CONTEXTS)) : 0U) + +/** +* Amount of memory needed to support the logging feature +*/ +#define BLE_STACK_LOG_SIZE(BLE_STACK_LOG_EN) (((BLE_STACK_LOG_EN) == 1U) ? 2540U : 0U) + /** * Amount of memory needed by FIFOs */ @@ -496,7 +509,8 @@ * @param BLE_STACK_NUM_BRC_BIS: Number of BIG Broadcaster streams per group to support. * @param BLE_STACK_NUM_CIG: Number of CIG groups to support. * @param BLE_STACK_NUM_CIS: Number of CIS streams to support. - * @param BLE_STACK_CIS_EN: Enable or disable the Connected Isochronous Streams feature. Valid values are 0 or 1. + * @param BLE_STACK_EXTRA_LL_PROCEDURE_CONTEXTS: Number of extra Control Procedure contexts. + * @param BLE_STACK_LOG_EN: Enable or disable log buffer allocation in stack. Valid values are 0 or 1. * @param ISR0_FIFO_SIZE: Size of the internal FIFO used for critical controller events produced by the ISR (e.g. rx data packets) * @param ISR1_FIFO_SIZE: Size of the internal FIFO used for non-critical controller events produced by the ISR (e.g. advertising or IQ sampling reports) * @param USER_FIFO_SIZE: Size of the internal FIFO used for controller and host events produced outside the ISR @@ -535,6 +549,8 @@ BLE_STACK_NUM_BRC_BIS,\ BLE_STACK_NUM_CIG,\ BLE_STACK_NUM_CIS,\ + BLE_STACK_EXTRA_LL_PROCEDURE_CONTEXTS,\ + BLE_STACK_LOG_EN,\ ISR0_FIFO_SIZE,\ ISR1_FIFO_SIZE,\ USER_FIFO_SIZE)\ @@ -568,9 +584,12 @@ BLE_STACK_CTE_EN, BLE_STACK_NUM_LINKS, NUM_CTE_ANT_IDS, NUM_CTE_IQSAMPLES) + \ BLE_STACK_PCL_SIZE(BLE_STACK_CONN_SUPP_EN, BLE_STACK_PCL_EN, BLE_STACK_NUM_LINKS) + \ BLE_STACK_CHC_SIZE(BLE_STACK_CONN_SUPP_EN, BLE_STACK_CHC_EN, BLE_STACK_NUM_LINKS) + \ - BLE_STACK_ISO_SIZE(BLE_STACK_NUM_BRC_BIG, BLE_STACK_NUM_BRC_BIS, \ + BLE_STACK_ISO_SIZE(BLE_STACK_EXT_ADV_SCAN_EN, CONTROLLER_PERIODIC_ADV_EN, BLE_STACK_SCAN_EN, BLE_STACK_CONN_SUPP_EN, \ + BLE_STACK_NUM_BRC_BIG, BLE_STACK_NUM_BRC_BIS, \ BLE_STACK_NUM_SYNC_BIG, BLE_STACK_NUM_SYNC_BIS, \ BLE_STACK_NUM_CIG, BLE_STACK_NUM_CIS) + \ + BLE_STACK_EXTRA_LL_PROCEDURE_CONTEXTS_SIZE(BLE_STACK_CONN_SUPP_EN, BLE_STACK_EXTRA_LL_PROCEDURE_CONTEXTS) + \ + BLE_STACK_LOG_SIZE(BLE_STACK_LOG_EN) + \ BLE_STACK_FIFO_SIZE(ISR0_FIFO_SIZE, ISR1_FIFO_SIZE, USER_FIFO_SIZE) \ ) @@ -595,6 +614,13 @@ on the available device RAM) * @param NUM_SYNC_SLOTS: Number of radio tasks to allocate for synchronizing to periodic advertisements. * @param BLE_STACK_NUM_CTE_ANT_IDS: Maximum antenna switching pattern length . * @param BLE_STACK_NUM_IQSAMPLES: Maximum number of IQ-Samples in the buffer. + * @param BLE_STACK_NUM_SYNC_BIG: Number of BIG Synchronous groups to support. + * @param BLE_STACK_NUM_BRC_BIG: Number of BIG Broadcaster groups to support. + * @param BLE_STACK_NUM_SYNC_BIS: Number of BIG Synchronous streams per group to support. + * @param BLE_STACK_NUM_BRC_BIS: Number of BIG Broadcaster streams per group to support. + * @param BLE_STACK_NUM_CIG: Number of CIG groups to support. + * @param BLE_STACK_NUM_CIS: Number of CIS streams to support. + * @param BLE_STACK_EXTRA_LL_PROCEDURE_CONTEXTS: Number of extra Control Procedure contexts. * @param ISR0_FIFO_SIZE: Size of the internal FIFO used for critical controller events produced by the ISR (e.g. rx data packets). * @param ISR1_FIFO_SIZE: Size of the internal FIFO used for non-critical controller events produced by the ISR (e.g. advertising or IQ sampling reports). * @param USER_FIFO_SIZE: Size of the internal FIFO used for controller and host events produced outside the ISR. @@ -620,6 +646,7 @@ on the available device RAM) BLE_STACK_NUM_BRC_BIS,\ BLE_STACK_NUM_CIG,\ BLE_STACK_NUM_CIS,\ + BLE_STACK_EXTRA_LL_PROCEDURE_CONTEXTS,\ ISR0_FIFO_SIZE,\ ISR1_FIFO_SIZE,\ USER_FIFO_SIZE)\ @@ -658,6 +685,8 @@ on the available device RAM) BLE_STACK_NUM_BRC_BIS,\ BLE_STACK_NUM_CIG,\ BLE_STACK_NUM_CIS,\ + BLE_STACK_EXTRA_LL_PROCEDURE_CONTEXTS,\ + DTM_DEBUG_ENABLED,\ ISR0_FIFO_SIZE,\ ISR1_FIFO_SIZE,\ USER_FIFO_SIZE\ @@ -694,6 +723,7 @@ typedef struct { uint8_t NumOfBrcBIS; /**< Maximum number of ISO Broadcaster streams. */ uint8_t NumOfCIG; /**< Maximum number of Connected Isochronous Groups. */ uint8_t NumOfCIS; /**< Maximum number of Connected Isochronous Streams. */ + uint8_t ExtraLLProcedureContexts; /**< Number of extra Link Layer Control Procedure contexts */ uint16_t isr0_fifo_size; /**< Size of the internal FIFO used for critical controller events produced by the ISR (e.g. rx data packets)*/ uint16_t isr1_fifo_size; /**< Size of the internal FIFO used for non-critical controller events produced by the ISR (e.g. advertising or IQ sampling reports)*/ uint16_t user_fifo_size; /**< Size of the internal FIFO used for controller and host events produced outside the ISR */ @@ -703,11 +733,8 @@ typedef struct { /** * @brief This function executes the processing of all Host Stack layers. * - * The BLE Stack Tick function has to be executed regularly to process incoming Link Layer packets and to process Host Layers procedures. All - * stack callbacks are called by this function. - * - * If Low Speed Ring Oscillator is used instead of the LS Crystal oscillator this function performs also the LS RO calibration and hence must - * be called at least once at every system wake-up in order to keep the 500 ppm accuracy (at least 500 ppm accuracy is mandatory if acting as a Central). + * The BLE Stack Tick function has to be executed to process incoming Link Layer packets and to process Host Layers procedures. All + * stack callbacks are called by this function. This function should be executed after every call to the BLE_STACK_ProcessRequest(). * * No BLE stack function must be called while the BLE_STACK_Tick is running. For example, if a BLE stack function may be called inside an * interrupt routine, that interrupt must be disabled during the execution of BLE_STACK_Tick(). Example (if a stack function may be called inside @@ -717,12 +744,22 @@ typedef struct { * BLE_STACK_Tick(); * NVIC_EnableIRQ(UART_IRQn); * @endcode - - * @note The API name and parameters are subject to change in future releases. - * @return None + * + * @note Do not call BLE_STACK_Tick() directly from BLE_STACK_ProcessRequest(). */ void BLE_STACK_Tick(void); +/** + * @brief This function executes the processing of all Host Stack layers without calling BLE_STACK_Event() . + * + * This version of the BLE Stack Tick function is useful in case the classic BLE_STACK_Tick() cannot be called for long time. + * In fact it is possible to call this BLE_STACK_TickNoEvents() from an interrupt context (e.g. from the Systick ISR) while being sure + * that BLE_STACK_Event() will not be called by this function. + * + * @note Do not call BLE_STACK_TickNoEvents() while other BLE Stack functions are being executed. + */ +void BLE_STACK_TickNoEvents(void); + /** * @brief The BLE Stack initialization routine * @@ -741,11 +778,9 @@ tBleStatus BLE_STACK_Init(const BLE_STACK_InitTypeDef *BLE_STACK_InitStruct); * * @param hci_pckt: The user event received from the BLE stack * @param length: Length of the event - * @retval None */ void BLE_STACK_Event(hci_pckt *hci_pckt, uint16_t length); - /** * @brief Returns the BLE Stack matching sleep mode * @@ -757,6 +792,16 @@ void BLE_STACK_Event(hci_pckt *hci_pckt, uint16_t length); */ uint8_t BLE_STACK_SleepCheck(void); +/** + * + * @brief Radio Resource Manager (RRM) ISR routine. + * + * This is the base function called for any RRM ISR. + * + * @param[in] RRMStatus Value of RRM Status register + */ +void BLE_STACK_RRMHandler(uint32_t RRMStatus); + /** * * @brief Radio ISR routine. @@ -764,8 +809,6 @@ uint8_t BLE_STACK_SleepCheck(void); * This is the base function called for any radio ISR. * * @param[in] BlueInterrupt value of the radio interrupt register - * - * @return None */ void BLE_STACK_RadioHandler(uint32_t BlueInterrupt); @@ -785,6 +828,14 @@ Information provided includes type of radio activity and absolute time in system */ uint8_t BLE_STACK_ReadNextRadioActivity(uint32_t *NextStateSysTime); +/** + * @brief This function is called whenever an execution of BLE_STACK_Tick() is requested. + * + * It may be called from an interrupt context, so it should return as quickly as possible. + * The BLE_STACK_Tick() must not be called directly by this API. + */ +void BLE_STACK_ProcessRequest(void); + /* Statistics per link */ typedef struct llc_conn_per_statistic_s { diff --git a/lib/stm32wb0/STM32_BLE/stack/include/ble_stack_user_cfg.h b/lib/stm32wb0/STM32_BLE/stack/include/ble_stack_user_cfg.h index 17020d1fa..c556f862e 100644 --- a/lib/stm32wb0/STM32_BLE/stack/include/ble_stack_user_cfg.h +++ b/lib/stm32wb0/STM32_BLE/stack/include/ble_stack_user_cfg.h @@ -1,4 +1,5 @@ + /** ****************************************************************************** * @file ble_stack_user_cfg.h @@ -13,7 +14,7 @@ * -- LE 2M/Coded PHY * -- Extended Advertising * -- Periodic Advertising and Synchronizer - * -- Periodic Advertising with Responses + * -- Periodic Advertising with Responses * -- L2CAP Connection Oriented Channels * -- Constant Tone Extension * -- Power Control & Path Loss Monitoring @@ -59,10 +60,6 @@ #define CONTROLLER_CIS_ENABLED CFG_BLE_CONTROLLER_CIS_ENABLED -/** - * @} - */ - /* --------------------- Derived defines --------------------- */ #if (CONTROLLER_BIS_ENABLED == 1U) || (CONTROLLER_CIS_ENABLED == 1U) # define CONTROLLER_ISO_ENABLED (1U) /* ISO Support: ENABLED */ @@ -70,6 +67,10 @@ # define CONTROLLER_ISO_ENABLED (0U) /* ISO Support: DISABLED */ #endif +#if !defined(DTM_DEBUG_ENABLED) +# define DTM_DEBUG_ENABLED (0U) /* Logging: DISABLED */ +#endif + /* --------------------- Defines used by function prototypes -------------------- */ #if !defined(LLC_MAX_NUM_DATA_CHAN) @@ -222,18 +223,18 @@ void GAP_central_connection_complete_handler(uint8_t status, uint16_t connectionHandle); uint8_t GAP_parse_connectable_advertising_report_ucfg(uint8_t* adv_buf, - uint8_t extended); + uint8_t extended); uint8_t GAP_parse_connectable_advertising_report_ucfg_weak(uint8_t* adv_buf, - uint8_t extended); + uint8_t extended); uint8_t GAP_parse_connectable_advertising_report(uint8_t* adv_buf, - uint8_t extended); + uint8_t extended); uint8_t GAP_parse_advertising_report_ucfg(uint8_t* adv_buf, - uint8_t extended); + uint8_t extended); uint8_t GAP_parse_advertising_report_ucfg_weak(uint8_t* adv_buf, - uint8_t extended); + uint8_t extended); uint8_t GAP_parse_advertising_report(uint8_t* adv_buf, - uint8_t extended); + uint8_t extended); void GAP_DiscProcTimeoutcb_ucfg(uint8_t timer_id); void GAP_DiscProcTimeoutcb_ucfg_weak(uint8_t timer_id); @@ -279,9 +280,9 @@ tBleStatus GAP_set_controller_random_address_ucfg(uint8_t random_address[6]); tBleStatus GAP_set_controller_random_address_ucfg_weak(uint8_t random_address[6]); tBleStatus GAP_set_controller_random_address_extended(uint8_t random_address[6]); -tBleStatus GAP_init_advertising_sets_ucfg(uint8_t own_address_type); -tBleStatus GAP_init_advertising_sets_ucfg_weak(uint8_t own_address_type); -tBleStatus GAP_init_advertising_sets(uint8_t own_address_type); +tBleStatus GAP_init_advertising_sets_ucfg(void); +tBleStatus GAP_init_advertising_sets_ucfg_weak(void); +tBleStatus GAP_init_advertising_sets(void); tBleStatus GAP_suspend_resume_active_advertising_sets_ucfg(uint8_t resume); tBleStatus GAP_suspend_resume_active_advertising_sets_ucfg_weak(uint8_t resume); @@ -305,14 +306,6 @@ tBleStatus hci_acl_data_ind_event_int_cb_ucfg_weak(void* header_p, tBleStatus hci_acl_data_ind_event_int_cb(void* header_p, uint8_t* buff_p); -uint32_t chc_csr_ucfg(void); -uint32_t chc_csr_ucfg_weak(void); -uint32_t chc_csr(void); - -void Controller_Process_Q_ucfg(uint16_t task_idx); -void Controller_Process_Q_ucfg_weak(uint16_t task_idx); -void Controller_Process_Q(uint16_t task_idx); - void LLC_offline_control_procedures_processing_ucfg(uint16_t task_idx); void LLC_offline_control_procedures_processing_ucfg_weak(uint16_t task_idx); void LLC_offline_control_procedures_processing(uint16_t task_idx); @@ -459,6 +452,10 @@ tBleStatus MBM_init_ucfg(void); tBleStatus MBM_init_ucfg_weak(void); tBleStatus MBM_init(void); +tBleStatus smp_debug_trudy__set_config_ucfg(uint32_t config); +tBleStatus smp_debug_trudy__set_config_ucfg_weak(uint32_t config); +tBleStatus smp_debug_trudy__set_config(uint32_t config); + uint32_t secure_connections_csr_ucfg(void); uint32_t secure_connections_csr_ucfg_weak(void); uint32_t secure_connections_csr(void); @@ -481,6 +478,105 @@ void smp_sap_hci_le_generate_dhkey_complete_evt_hndl_ucfg_weak(uint8_t status, void smp_sap_hci_le_generate_dhkey_complete_evt_hndl(uint8_t status, uint8_t dhkey[32]); +uint8_t ble_stack_log_verbosity_set_ucfg(void* p); +uint8_t ble_stack_log_verbosity_set_ucfg_weak(void* p); +uint8_t ble_stack_log_verbosity_set(void* p); + +void ble_stack_log_verbosity_get_ucfg(void* verb_p); +void ble_stack_log_verbosity_get_ucfg_weak(void* verb_p); +void ble_stack_log_verbosity_get(void* verb_p); + +void ble_stack_log_init_ucfg(void); +void ble_stack_log_init_ucfg_weak(void); +void ble_stack_log_init(void); + +void ble_stack_log_notify_stu_ucfg(uint8_t lvl, + uint8_t cid, + uint16_t mid, + uint8_t uid, + uint8_t fmt, + uint8_t len, + uint8_t* buf_p, + uint8_t isr); +void ble_stack_log_notify_stu_ucfg_weak(uint8_t lvl, + uint8_t cid, + uint16_t mid, + uint8_t uid, + uint8_t fmt, + uint8_t len, + uint8_t* buf_p, + uint8_t isr); +void ble_stack_log_notify_stu(uint8_t lvl, + uint8_t cid, + uint16_t mid, + uint8_t uid, + uint8_t fmt, + uint8_t len, + uint8_t* buf_p, + uint8_t isr); + +void ble_stack_log_notify_us_deferred_ucfg(uint8_t lvl, + uint8_t cid, + uint16_t mid, + uint8_t uid, + uint8_t add_info_present, + uint32_t add_info); +void ble_stack_log_notify_us_deferred_ucfg_weak(uint8_t lvl, + uint8_t cid, + uint16_t mid, + uint8_t uid, + uint8_t add_info_present, + uint32_t add_info); +void ble_stack_log_notify_us_deferred(uint8_t lvl, + uint8_t cid, + uint16_t mid, + uint8_t uid, + uint8_t add_info_present, + uint32_t add_info); + +void ble_stack_log_notify_us_flush_ucfg(void); +void ble_stack_log_notify_us_flush_ucfg_weak(void); +void ble_stack_log_notify_us_flush(void); + +uint32_t ble_stack_log_csr_ucfg(void); +uint32_t ble_stack_log_csr_ucfg_weak(void); +uint32_t ble_stack_log_csr(void); + +int llc_isr_tim_mon_reset_stat_params_ucfg(uint8_t* params_p); +int llc_isr_tim_mon_reset_stat_params_ucfg_weak(uint8_t* params_p); +int llc_isr_tim_mon_reset_stat_params(uint8_t* params_p); + +void llc_isr_tim_mon_stat_abs_ucfg(uint8_t mod_id, + uint8_t var_id, + uint8_t checkp); +void llc_isr_tim_mon_stat_abs_ucfg_weak(uint8_t mod_id, + uint8_t var_id, + uint8_t checkp); +void llc_isr_tim_mon_stat_abs(uint8_t mod_id, + uint8_t var_id, + uint8_t checkp); + +void llc_isr_tim_mon_stat_rel_ucfg(uint8_t mod_id, + uint8_t var_id, + uint8_t checkp); +void llc_isr_tim_mon_stat_rel_ucfg_weak(uint8_t mod_id, + uint8_t var_id, + uint8_t checkp); +void llc_isr_tim_mon_stat_rel(uint8_t mod_id, + uint8_t var_id, + uint8_t checkp); + +void llc_isr_tim_mon_stat_check_ucfg(uint8_t mod_id, + uint8_t var_id); +void llc_isr_tim_mon_stat_check_ucfg_weak(uint8_t mod_id, + uint8_t var_id); +void llc_isr_tim_mon_stat_check(uint8_t mod_id, + uint8_t var_id); + +void llc_isr_tim_mon_stat_notify_ucfg(void); +void llc_isr_tim_mon_stat_notify_ucfg_weak(void); +void llc_isr_tim_mon_stat_notify(void); + uint32_t l2c_cos_csr_ucfg(void); uint32_t l2c_cos_csr_ucfg_weak(void); uint32_t l2c_cos_csr(void); @@ -536,6 +632,32 @@ void llc_conn_check_subrate_and_set_params_ucfg_weak(void* cntxt_p, void llc_conn_check_subrate_and_set_params(void* cntxt_p, void* params_p); +void llc_conn_mem_allocate_ucfg(uint8_t phy_upd_en, + uint8_t cte_en, + uint8_t pcl_en, + uint8_t cns_en, + uint8_t chc_en, + uint8_t padv_en); +void llc_conn_mem_allocate_ucfg_weak(uint8_t phy_upd_en, + uint8_t cte_en, + uint8_t pcl_en, + uint8_t cns_en, + uint8_t chc_en, + uint8_t padv_en); +void llc_conn_mem_allocate(uint8_t phy_upd_en, + uint8_t cte_en, + uint8_t pcl_en, + uint8_t cns_en, + uint8_t chc_en, + uint8_t padv_en); + +void llc_conn_list_replace_rpa_addresses_ucfg(void* peer_id_addr_p, + uint32_t peer_irk[4]); +void llc_conn_list_replace_rpa_addresses_ucfg_weak(void* peer_id_addr_p, + uint32_t peer_irk[4]); +void llc_conn_list_replace_rpa_addresses(void* peer_id_addr_p, + uint32_t peer_irk[4]); + uint32_t llc_conn_calc_skip_ucfg(void* cntxt_p, uint16_t event_counter, uint16_t latency); @@ -550,9 +672,13 @@ tBleStatus llc_conn_multi_link_connection_ucfg(uint8_t enable); tBleStatus llc_conn_multi_link_connection_ucfg_weak(uint8_t enable); tBleStatus llc_conn_multi_link_connection(uint8_t enable); -void llc_conn_peripheral_latency_cancellation_tsk_ucfg(uint16_t task_idx); -void llc_conn_peripheral_latency_cancellation_tsk_ucfg_weak(uint16_t task_idx); -void llc_conn_peripheral_latency_cancellation_tsk(uint16_t task_idx); +void llc_conn_peripheral_roll_back_params_tsk_ucfg(uint16_t task_idx); +void llc_conn_peripheral_roll_back_params_tsk_ucfg_weak(uint16_t task_idx); +void llc_conn_peripheral_roll_back_params_tsk(uint16_t task_idx); + +void llc_cpe_tsk_ucfg(uint16_t task_idx); +void llc_cpe_tsk_ucfg_weak(uint16_t task_idx); +void llc_cpe_tsk(uint16_t task_idx); uint8_t llc_check_sreq_or_creq_tx_addr_ucfg(void* tx_addr7_p, uint8_t pdu_type, @@ -750,21 +876,21 @@ tBleStatus llc_big_cmn_get_iso_params(uint8_t direction, uint16_t conn_handle, void* param_p); -uint32_t llc_cig_cen_get_cis_offset_from_acl_us_ucfg(void* ctx_p, +uint16_t llc_cig_cen_get_cis_offset_from_acl_us_ucfg(void* ctx_p, void* cis_p, uint8_t conn_idx, - uint16_t* event_count_p, - uint32_t* cig_anchor_st_p); -uint32_t llc_cig_cen_get_cis_offset_from_acl_us_ucfg_weak(void* ctx_p, + uint32_t* cis_min_offset_us_p, + uint32_t* cis_max_offset_us_p); +uint16_t llc_cig_cen_get_cis_offset_from_acl_us_ucfg_weak(void* ctx_p, void* cis_p, uint8_t conn_idx, - uint16_t* event_count_p, - uint32_t* cig_anchor_st_p); -uint32_t llc_cig_cen_get_cis_offset_from_acl_us(void* ctx_p, + uint32_t* cis_min_offset_us_p, + uint32_t* cis_max_offset_us_p); +uint16_t llc_cig_cen_get_cis_offset_from_acl_us(void* ctx_p, void* cis_p, uint8_t conn_idx, - uint16_t* event_count_p, - uint32_t* cig_anchor_st_p); + uint32_t* cis_min_offset_us_p, + uint32_t* cis_max_offset_us_p); uint32_t llc_cig_cen_get_sdu_synchronization_us_ucfg(uint16_t conn_handle, uint8_t framed, @@ -833,6 +959,28 @@ uint32_t llc_cig_cmn_get_own_cig_event_time(void* ctx_p, uint16_t conn_handle, uint16_t num_enq_packet); +void llc_cig_cmn_get_cis_anchor_range_ucfg(void* cig_p, + void* cis_p, + uint8_t conn_idx, + uint16_t event_offset, + uint16_t* acl_event_counter_p, + uint32_t* cis_min_offset_us_p, + uint32_t* cis_max_offset_us_p); +void llc_cig_cmn_get_cis_anchor_range_ucfg_weak(void* cig_p, + void* cis_p, + uint8_t conn_idx, + uint16_t event_offset, + uint16_t* acl_event_counter_p, + uint32_t* cis_min_offset_us_p, + uint32_t* cis_max_offset_us_p); +void llc_cig_cmn_get_cis_anchor_range(void* cig_p, + void* cis_p, + uint8_t conn_idx, + uint16_t event_offset, + uint16_t* acl_event_counter_p, + uint32_t* cis_min_offset_us_p, + uint32_t* cis_max_offset_us_p); + tBleStatus llc_cig_cmn_enqueue_pdu_to_tx_ucfg(void* ctx_p, uint32_t iso_interval_idx, uint16_t conn_handle, @@ -860,13 +1008,13 @@ void llc_cig_cmn_start_cis_ucfg_weak(uint8_t conn_idx, void llc_cig_cmn_start_cis(uint8_t conn_idx, uint16_t instant); -uint8_t llc_cig_cmn_is_active_cis_on_acl_ucfg(uint16_t acl_conn_handle); -uint8_t llc_cig_cmn_is_active_cis_on_acl_ucfg_weak(uint16_t acl_conn_handle); -uint8_t llc_cig_cmn_is_active_cis_on_acl(uint16_t acl_conn_handle); +uint8_t llc_cig_cmn_is_active_cis_on_acl_ucfg(uint8_t acl_conn_idx); +uint8_t llc_cig_cmn_is_active_cis_on_acl_ucfg_weak(uint8_t acl_conn_idx); +uint8_t llc_cig_cmn_is_active_cis_on_acl(uint8_t acl_conn_idx); -void llc_cig_cmn_terminate_cises_on_acl_ucfg(uint16_t acl_conn_handle); -void llc_cig_cmn_terminate_cises_on_acl_ucfg_weak(uint16_t acl_conn_handle); -void llc_cig_cmn_terminate_cises_on_acl(uint16_t acl_conn_handle); +void llc_cig_cmn_terminate_cises_on_acl_ucfg(uint8_t conn_idx); +void llc_cig_cmn_terminate_cises_on_acl_ucfg_weak(uint8_t conn_idx); +void llc_cig_cmn_terminate_cises_on_acl(uint8_t conn_idx); void llc_cig_cmn_cis_established_event_gen_ucfg(void* cig_p, void* cis_p, @@ -878,6 +1026,23 @@ void llc_cig_cmn_cis_established_event_gen(void* cig_p, void* cis_p, uint8_t status); +tBleStatus llc_cig_cmn_check_params_ucfg(uint8_t cig_id, + void* cig_p, + void* cis_p); +tBleStatus llc_cig_cmn_check_params_ucfg_weak(uint8_t cig_id, + void* cig_p, + void* cis_p); +tBleStatus llc_cig_cmn_check_params(uint8_t cig_id, + void* cig_p, + void* cis_p); + +tBleStatus llc_cig_cmn_check_iso_params_ucfg(void* cig_p, + void* cis_p); +tBleStatus llc_cig_cmn_check_iso_params_ucfg_weak(void* cig_p, + void* cis_p); +tBleStatus llc_cig_cmn_check_iso_params(void* cig_p, + void* cis_p); + tBleStatus llc_cig_cmn_get_iso_params_ucfg(uint8_t direction, uint16_t conn_handle, void* param_p); @@ -913,6 +1078,25 @@ tBleStatus llc_cig_cmn_read_iso_link_quality(uint16_t conn_handle, uint32_t* rx_unreceived_packets_p, uint32_t* duplicate_packets_p); +tBleStatus llc_cig_cmn_validate_cis_params_from_acl_ucfg(void* ctx_p, + void* cis_p, + uint8_t conn_idx, + uint16_t event_counter, + uint32_t cis_min_offset_us, + uint32_t cis_max_offset_us); +tBleStatus llc_cig_cmn_validate_cis_params_from_acl_ucfg_weak(void* ctx_p, + void* cis_p, + uint8_t conn_idx, + uint16_t event_counter, + uint32_t cis_min_offset_us, + uint32_t cis_max_offset_us); +tBleStatus llc_cig_cmn_validate_cis_params_from_acl(void* ctx_p, + void* cis_p, + uint8_t conn_idx, + uint16_t event_counter, + uint32_t cis_min_offset_us, + uint32_t cis_max_offset_us); + void llc_iso_cmn_mem_alloc_ucfg(void); void llc_iso_cmn_mem_alloc_ucfg_weak(void); void llc_iso_cmn_mem_alloc(void); @@ -956,11 +1140,11 @@ uint8_t llc_padv_check_if_syncinfo_is_included_and_start_periodic_advertising_uc uint8_t llc_padv_check_if_syncinfo_is_included_and_start_periodic_advertising(void* context_p); uint8_t llc_padv_update_sync_info_ucfg(void* padv_per_p, - uint32_t aux_adv_ind_anchor); + uint32_t aux_adv_ind_anchor); uint8_t llc_padv_update_sync_info_ucfg_weak(void* padv_per_p, - uint32_t aux_adv_ind_anchor); + uint32_t aux_adv_ind_anchor); uint8_t llc_padv_update_sync_info(void* padv_per_p, - uint32_t aux_adv_ind_anchor); + uint32_t aux_adv_ind_anchor); void llc_padv_prepare_periodic_advertising_payload_ucfg(void* padv_per_p, uint8_t extended_header_flags, @@ -977,11 +1161,11 @@ uint32_t llc_padv_periodic_adv_sync_csr_ucfg_weak(void); uint32_t llc_padv_periodic_adv_sync_csr(void); uint8_t llc_padv_wr_create_connection_cancel_ucfg(void* _padv_per_p, - uint8_t advertising_handle); + uint8_t advertising_handle); uint8_t llc_padv_wr_create_connection_cancel_ucfg_weak(void* _padv_per_p, - uint8_t advertising_handle); + uint8_t advertising_handle); uint8_t llc_padv_wr_create_connection_cancel(void* _padv_per_p, - uint8_t advertising_handle); + uint8_t advertising_handle); void llc_padv_wr_set_start_parameters_ucfg(void* set_padv_wr_start_parameters_p); void llc_padv_wr_set_start_parameters_ucfg_weak(void* set_padv_wr_start_parameters_p); @@ -992,11 +1176,11 @@ tBleStatus llc_padv_wr_set_periodic_advertising_subevent_data_ucfg_weak(void* se tBleStatus llc_padv_wr_set_periodic_advertising_subevent_data(void* set_padv_wr_data_p); uint8_t llc_padv_wr_set_ctrdata_ucfg(void* padv_per_p, - uint8_t* ctrdata_p); + uint8_t* ctrdata_p); uint8_t llc_padv_wr_set_ctrdata_ucfg_weak(void* padv_per_p, - uint8_t* ctrdata_p); + uint8_t* ctrdata_p); uint8_t llc_padv_wr_set_ctrdata(void* padv_per_p, - uint8_t* ctrdata_p); + uint8_t* ctrdata_p); void llc_padv_wr_set_acad_ucfg(void* padv_per_p, uint8_t* ext_hdr_p); @@ -1017,6 +1201,50 @@ void llc_padv_wr_disable_ext_ucfg(void* _padv_per_p); void llc_padv_wr_disable_ext_ucfg_weak(void* _padv_per_p); void llc_padv_wr_disable_ext(void* _padv_per_p); +void llc_past_mem_allocate_ucfg(uint8_t scan_en, + uint8_t ext_en, + uint8_t pscan_en, + uint8_t conn_en); +void llc_past_mem_allocate_ucfg_weak(uint8_t scan_en, + uint8_t ext_en, + uint8_t pscan_en, + uint8_t conn_en); +void llc_past_mem_allocate(uint8_t scan_en, + uint8_t ext_en, + uint8_t pscan_en, + uint8_t conn_en); + +void llc_past_init_ucfg(uint8_t conn_idx); +void llc_past_init_ucfg_weak(uint8_t conn_idx); +void llc_past_init(uint8_t conn_idx); + +void llc_past_by_scanner_ucfg(void* params, + uint32_t conn_anchor, + uint32_t conn_interval, + uint16_t conn_event_count, + uint8_t* pdu_p); +void llc_past_by_scanner_ucfg_weak(void* params, + uint32_t conn_anchor, + uint32_t conn_interval, + uint16_t conn_event_count, + uint8_t* pdu_p); +void llc_past_by_scanner(void* params, + uint32_t conn_anchor, + uint32_t conn_interval, + uint16_t conn_event_count, + uint8_t* pdu_p); + +void llc_past_peer_init_ucfg(uint8_t* pdu_p, + uint8_t conn_idx); +void llc_past_peer_init_ucfg_weak(uint8_t* pdu_p, + uint8_t conn_idx); +void llc_past_peer_init(uint8_t* pdu_p, + uint8_t conn_idx); + +void llc_past_register_cpf_ucfg(void); +void llc_past_register_cpf_ucfg_weak(void); +void llc_past_register_cpf(void); + void llc_priv_generate_peer_rpa_from_peer_id_ucfg(void* peer_p, uint8_t in_isr); void llc_priv_generate_peer_rpa_from_peer_id_ucfg_weak(void* peer_p, @@ -1024,6 +1252,36 @@ void llc_priv_generate_peer_rpa_from_peer_id_ucfg_weak(void* peer_p, void llc_priv_generate_peer_rpa_from_peer_id(void* peer_p, uint8_t in_isr); +uint8_t llc_check_creq_rx_addr_ucfg(uint8_t* rx_addr7_p, + uint8_t* tx_addr7_p, + uint8_t* local_addr7_p, + uint8_t* rl_index_p); +uint8_t llc_check_creq_rx_addr_ucfg_weak(uint8_t* rx_addr7_p, + uint8_t* tx_addr7_p, + uint8_t* local_addr7_p, + uint8_t* rl_index_p); +uint8_t llc_check_creq_rx_addr(uint8_t* rx_addr7_p, + uint8_t* tx_addr7_p, + uint8_t* local_addr7_p, + uint8_t* rl_index_p); + +uint8_t llc_priv_generate_rpa_from_rl_index_ucfg(uint8_t rl_index, + uint8_t local_rpa, + uint8_t in_isr, + void* addr8_rpa_p); +uint8_t llc_priv_generate_rpa_from_rl_index_ucfg_weak(uint8_t rl_index, + uint8_t local_rpa, + uint8_t in_isr, + void* addr8_rpa_p); +uint8_t llc_priv_generate_rpa_from_rl_index(uint8_t rl_index, + uint8_t local_rpa, + uint8_t in_isr, + void* addr8_rpa_p); + +void llc_priv_get_id_addr_from_rpa_ucfg(void* addr_p); +void llc_priv_get_id_addr_from_rpa_ucfg_weak(void* addr_p); +void llc_priv_get_id_addr_from_rpa(void* addr_p); + void llc_priv_init_ucfg(uint8_t first_call); void llc_priv_init_ucfg_weak(uint8_t first_call); void llc_priv_init(uint8_t first_call); @@ -1066,14 +1324,18 @@ void llc_priv_init_random_part_of_one_local_rpa_ucfg(void* peer_id_p); void llc_priv_init_random_part_of_one_local_rpa_ucfg_weak(void* peer_id_p); void llc_priv_init_random_part_of_one_local_rpa(void* peer_id_p); +void llc_priv_enable_rpa_change_at_timeout_ucfg(uint8_t enable); +void llc_priv_enable_rpa_change_at_timeout_ucfg_weak(uint8_t enable); +void llc_priv_enable_rpa_change_at_timeout(uint8_t enable); + +uint8_t llc_priv_is_rpa_change_at_timeout_enabled_ucfg(void); +uint8_t llc_priv_is_rpa_change_at_timeout_enabled_ucfg_weak(void); +uint8_t llc_priv_is_rpa_change_at_timeout_enabled(void); + void llc_pscan_cancel_slot_cte_ucfg(void* cntxt_per_p); void llc_pscan_cancel_slot_cte_ucfg_weak(void* cntxt_per_p); void llc_pscan_cancel_slot_cte(void* cntxt_per_p); -uint8_t llc_pscan_isr_ucfg(void* cntxt_per_p); -uint8_t llc_pscan_isr_ucfg_weak(void* cntxt_per_p); -uint8_t llc_pscan_isr(void* cntxt_per_p); - void llc_pscan_init_ucfg(void); void llc_pscan_init_ucfg_weak(void); void llc_pscan_init(void); @@ -1116,10 +1378,6 @@ void llc_pscan_synchronizing_ucfg(void* params_p); void llc_pscan_synchronizing_ucfg_weak(void* params_p); void llc_pscan_synchronizing(void* params_p); -void llc_pscan_wrong_cte_type_ucfg(void* cntxt_p); -void llc_pscan_wrong_cte_type_ucfg_weak(void* cntxt_p); -void llc_pscan_wrong_cte_type(void* cntxt_p); - void llc_pscan_wr_init_ucfg(void); void llc_pscan_wr_init_ucfg_weak(void); void llc_pscan_wr_init(void); @@ -1152,14 +1410,14 @@ void llc_pscan_wr_config_tx_blue_sm(void* params_p, uint8_t pawr_feat); uint8_t llc_pscan_wr_get_pawr_info_ucfg(uint8_t acad_size, - uint8_t* acad_p, - uint8_t* pawr_info_p); + uint8_t* acad_p, + uint8_t* pawr_info_p); uint8_t llc_pscan_wr_get_pawr_info_ucfg_weak(uint8_t acad_size, - uint8_t* acad_p, - uint8_t* pawr_info_p); + uint8_t* acad_p, + uint8_t* pawr_info_p); uint8_t llc_pscan_wr_get_pawr_info(uint8_t acad_size, - uint8_t* acad_p, - uint8_t* pawr_info_p); + uint8_t* acad_p, + uint8_t* pawr_info_p); uint8_t llc_pscan_wr_check_pawr_active_ucfg(uint8_t conn_idx); uint8_t llc_pscan_wr_check_pawr_active_ucfg_weak(uint8_t conn_idx); @@ -1187,6 +1445,10 @@ void llc_pscan_wr_set_scheduler_params_ucfg(void* params_p); void llc_pscan_wr_set_scheduler_params_ucfg_weak(void* params_p); void llc_pscan_wr_set_scheduler_params(void* params_p); +void llc_sca_upd_register_cpf_ucfg(void); +void llc_sca_upd_register_cpf_ucfg_weak(void); +void llc_sca_upd_register_cpf(void); + void llc_scan_conn_ind_sent_ucfg(void* ptr, uint8_t idx); void llc_scan_conn_ind_sent_ucfg_weak(void* ptr, @@ -1194,19 +1456,19 @@ void llc_scan_conn_ind_sent_ucfg_weak(void* ptr, void llc_scan_conn_ind_sent(void* ptr, uint8_t idx); -uint8_t llc_scan_process_ext_adv_ucfg(void* scan_p, +void llc_scan_process_ext_adv_ucfg(void* scan_p, void* params_p, uint32_t direct_addr[2], uint8_t idx, uint8_t advertiser_addr_flag, uint8_t* send_report_p); -uint8_t llc_scan_process_ext_adv_ucfg_weak(void* scan_p, +void llc_scan_process_ext_adv_ucfg_weak(void* scan_p, void* params_p, uint32_t direct_addr[2], uint8_t idx, uint8_t advertiser_addr_flag, uint8_t* send_report_p); -uint8_t llc_scan_process_ext_adv(void* scan_p, +void llc_scan_process_ext_adv(void* scan_p, void* params_p, uint32_t direct_addr[2], uint8_t idx, @@ -1279,10 +1541,6 @@ void llc_scan_disable_ucfg(void* scan_p); void llc_scan_disable_ucfg_weak(void* scan_p); void llc_scan_disable(void* scan_p); -uint8_t llc_subrate_get_active_sr_req_proc_ucfg(uint8_t conn_idx); -uint8_t llc_subrate_get_active_sr_req_proc_ucfg_weak(uint8_t conn_idx); -uint8_t llc_subrate_get_active_sr_req_proc(uint8_t conn_idx); - void llc_subrate_new_sr_base_event_ucfg(uint16_t sr_factor, uint16_t* sr_base_event_p); void llc_subrate_new_sr_base_event_ucfg_weak(uint16_t sr_factor, @@ -1298,6 +1556,10 @@ uint8_t llc_subrate_offline_processing_ucfg(void* cntxt_p); uint8_t llc_subrate_offline_processing_ucfg_weak(void* cntxt_p); uint8_t llc_subrate_offline_processing(void* cntxt_p); +void llc_subrate_register_cpf_ucfg(void); +void llc_subrate_register_cpf_ucfg_weak(void); +void llc_subrate_register_cpf(void); + void llc_mngm_csa2_select_subevent_channel_ucfg(uint8_t subevent_counter, uint8_t* subevent_index_p, uint16_t prn_s, @@ -1323,58 +1585,6 @@ void llc_mngm_csa2_select_subevent_channel(uint8_t subevent_counter, void* _csa2_table_p, uint8_t* channel_index_p); -void LL_cpe_init_length_update_ucfg(void); -void LL_cpe_init_length_update_ucfg_weak(void); -void LL_cpe_init_length_update(void); - -void LL_cpe_init_phy_update_ucfg(void); -void LL_cpe_init_phy_update_ucfg_weak(void); -void LL_cpe_init_phy_update(void); - -void LL_cpe_init_cte_ucfg(void); -void LL_cpe_init_cte_ucfg_weak(void); -void LL_cpe_init_cte(void); - -void LL_cpe_init_past_ucfg(void); -void LL_cpe_init_past_ucfg_weak(void); -void LL_cpe_init_past(void); - -void LL_cpe_init_pcl_ucfg(void); -void LL_cpe_init_pcl_ucfg_weak(void); -void LL_cpe_init_pcl(void); - -void LL_cpe_init_conn_update_ucfg(void); -void LL_cpe_init_conn_update_ucfg_weak(void); -void LL_cpe_init_conn_update(void); - -void LL_cpe_init_chmap_update_ucfg(void); -void LL_cpe_init_chmap_update_ucfg_weak(void); -void LL_cpe_init_chmap_update(void); - -void LL_cpe_init_chc_enable_ucfg(void); -void LL_cpe_init_chc_enable_ucfg_weak(void); -void LL_cpe_init_chc_enable(void); - -void LL_cpe_init_chc_reporting_ucfg(void); -void LL_cpe_init_chc_reporting_ucfg_weak(void); -void LL_cpe_init_chc_reporting(void); - -void LL_cpe_init_subrate_ucfg(void); -void LL_cpe_init_subrate_ucfg_weak(void); -void LL_cpe_init_subrate(void); - -void LL_cpe_init_sca_upd_ucfg(void); -void LL_cpe_init_sca_upd_ucfg_weak(void); -void LL_cpe_init_sca_upd(void); - -void LL_cpe_init_cis_ucfg(void); -void LL_cpe_init_cis_ucfg_weak(void); -void LL_cpe_init_cis(void); - -void LL_cpe_init_ucfg(void); -void LL_cpe_init_ucfg_weak(void); -void LL_cpe_init(void); - void LLC_channel_map_copy_to_cpf_context_ucfg(void* cntxt_p, uint8_t conn_idx); void LLC_channel_map_copy_to_cpf_context_ucfg_weak(void* cntxt_p, @@ -1398,10 +1608,29 @@ uint8_t LLC_chc_reporting_offline_processing_ucfg(uint8_t conn_idx); uint8_t LLC_chc_reporting_offline_processing_ucfg_weak(uint8_t conn_idx); uint8_t LLC_chc_reporting_offline_processing(uint8_t conn_idx); +uint32_t chc_csr_ucfg(void); +uint32_t chc_csr_ucfg_weak(void); +uint32_t chc_csr(void); + +void llc_chan_class_register_cpf_ucfg(void); +void llc_chan_class_register_cpf_ucfg_weak(void); +void llc_chan_class_register_cpf(void); + +void llc_chc_notify_all_conn_links_ucfg(uint8_t* chmap_p, + uint8_t* local_chclass_p); +void llc_chc_notify_all_conn_links_ucfg_weak(uint8_t* chmap_p, + uint8_t* local_chclass_p); +void llc_chc_notify_all_conn_links(uint8_t* chmap_p, + uint8_t* local_chclass_p); + void LL_cpf_cis_processing_ucfg(uint16_t task_idx); void LL_cpf_cis_processing_ucfg_weak(uint16_t task_idx); void LL_cpf_cis_processing(uint16_t task_idx); +void llc_cis_register_cpf_ucfg(void); +void llc_cis_register_cpf_ucfg_weak(void); +void llc_cis_register_cpf(void); + void LL_conn_upd_max_tx_time_coded_ucfg(void* params); void LL_conn_upd_max_tx_time_coded_ucfg_weak(void* params); void LL_conn_upd_max_tx_time_coded(void* params); @@ -1410,6 +1639,10 @@ void LL_conn_upd_data_length_change_event_ucfg(void* params); void LL_conn_upd_data_length_change_event_ucfg_weak(void* params); void LL_conn_upd_data_length_change_event(void* params); +void llc_cte_register_cpf_ucfg(void); +void llc_cte_register_cpf_ucfg_weak(void); +void llc_cte_register_cpf(void); + void llc_conn_init_cte_ctxt_ucfg(uint8_t conn_idx); void llc_conn_init_cte_ctxt_ucfg_weak(uint8_t conn_idx); void llc_conn_init_cte_ctxt(uint8_t conn_idx); @@ -1425,6 +1658,13 @@ void LLC_connection_cte_response_pause_resume_ucfg_weak(uint8_t conn_idx, void LLC_connection_cte_response_pause_resume(uint8_t conn_idx, uint8_t tx_phy); +void LLC_connection_cte_request_disable_ucfg(uint8_t conn_idx, + uint8_t taskslot_no); +void LLC_connection_cte_request_disable_ucfg_weak(uint8_t conn_idx, + uint8_t taskslot_no); +void LLC_connection_cte_request_disable(uint8_t conn_idx, + uint8_t taskslot_no); + void LLC_connection_cte_response_disable_ucfg(uint8_t conn_idx, uint8_t taskslot_no); void LLC_connection_cte_response_disable_ucfg_weak(uint8_t conn_idx, @@ -1439,60 +1679,14 @@ void llc_cte_process_rx_cte_ucfg_weak(void* params, void llc_cte_process_rx_cte(void* params, uint8_t cte_type); +void llc_len_upd_register_cpf_ucfg(void); +void llc_len_upd_register_cpf_ucfg_weak(void); +void llc_len_upd_register_cpf(void); + void LLC_authenticated_payload_timeout_processing_ucfg(uint16_t task_idx); void LLC_authenticated_payload_timeout_processing_ucfg_weak(uint16_t task_idx); void LLC_authenticated_payload_timeout_processing(uint16_t task_idx); -void llc_past_mem_allocate_ucfg(uint8_t scan_en, - uint8_t ext_en, - uint8_t pscan_en, - uint8_t conn_en); -void llc_past_mem_allocate_ucfg_weak(uint8_t scan_en, - uint8_t ext_en, - uint8_t pscan_en, - uint8_t conn_en); -void llc_past_mem_allocate(uint8_t scan_en, - uint8_t ext_en, - uint8_t pscan_en, - uint8_t conn_en); - -void LL_past_load_txctrl_packet_from_scanner_ucfg(void* params, - uint8_t* pdu_p, - uint32_t instant_anchor, - uint32_t connect_interval, - uint16_t connect_event_count, - uint16_t connect_event_cnt); -void LL_past_load_txctrl_packet_from_scanner_ucfg_weak(void* params, - uint8_t* pdu_p, - uint32_t instant_anchor, - uint32_t connect_interval, - uint16_t connect_event_count, - uint16_t connect_event_cnt); -void LL_past_load_txctrl_packet_from_scanner(void* params, - uint8_t* pdu_p, - uint32_t instant_anchor, - uint32_t connect_interval, - uint16_t connect_event_count, - uint16_t connect_event_cnt); - -void LL_periodicscan_deploy_scanner_from_past_ucfg(void* params, - uint8_t conn_idx, - uint8_t pawr_feat); -void LL_periodicscan_deploy_scanner_from_past_ucfg_weak(void* params, - uint8_t conn_idx, - uint8_t pawr_feat); -void LL_periodicscan_deploy_scanner_from_past(void* params, - uint8_t conn_idx, - uint8_t pawr_feat); - -void LL_past_initialize_connect_context_ucfg(uint8_t conn_idx); -void LL_past_initialize_connect_context_ucfg_weak(uint8_t conn_idx); -void LL_past_initialize_connect_context(uint8_t conn_idx); - -void LL_past_default_params_ucfg(uint8_t conn_idx); -void LL_past_default_params_ucfg_weak(uint8_t conn_idx); -void LL_past_default_params(uint8_t conn_idx); - void llc_conn_init_pcl_ctxt_ucfg(uint8_t conn_idx); void llc_conn_init_pcl_ctxt_ucfg_weak(uint8_t conn_idx); void llc_conn_init_pcl_ctxt(uint8_t conn_idx); @@ -1537,6 +1731,10 @@ uint8_t LLC_pcl_offline_processing_ucfg(uint8_t conn_idx); uint8_t LLC_pcl_offline_processing_ucfg_weak(uint8_t conn_idx); uint8_t LLC_pcl_offline_processing(uint8_t conn_idx); +void llc_pcl_register_cpf_ucfg(void); +void llc_pcl_register_cpf_ucfg_weak(void); +void llc_pcl_register_cpf(void); + tBleStatus LL_Read_RSSI_ucfg(int8_t* rssiVal, uint16_t connHandle); tBleStatus LL_Read_RSSI_ucfg_weak(int8_t* rssiVal, @@ -1556,13 +1754,20 @@ uint8_t LL_phy_upd_pending_ucfg(uint8_t conn_idx); uint8_t LL_phy_upd_pending_ucfg_weak(uint8_t conn_idx); uint8_t LL_phy_upd_pending(uint8_t conn_idx); +void llc_phy_upd_register_cpf_ucfg(void); +void llc_phy_upd_register_cpf_ucfg_weak(void); +void llc_phy_upd_register_cpf(void); + tBleStatus LL_phy_update_init_ucfg(void); tBleStatus LL_phy_update_init_ucfg_weak(void); tBleStatus LL_phy_update_init(void); -tBleStatus LL_phy_update_init_per_st_data_ucfg(uint8_t conn_idx); -tBleStatus LL_phy_update_init_per_st_data_ucfg_weak(uint8_t conn_idx); -tBleStatus LL_phy_update_init_per_st_data(uint8_t conn_idx); +tBleStatus LL_phy_update_init_per_st_data_ucfg(uint8_t conn_idx, + uint8_t hw_phy); +tBleStatus LL_phy_update_init_per_st_data_ucfg_weak(uint8_t conn_idx, + uint8_t hw_phy); +tBleStatus LL_phy_update_init_per_st_data(uint8_t conn_idx, + uint8_t hw_phy); void LL_phy_upd_evt_pending_check_isr_ucfg(uint8_t conn_idx); void LL_phy_upd_evt_pending_check_isr_ucfg_weak(uint8_t conn_idx); @@ -1589,14 +1794,14 @@ void LLC_connless_process_rx_cte(uint8_t iq_samples_ready, uint8_t channel); uint8_t LLC_check_iq_samples_ready_ucfg(uint8_t* iq_samples_number, - uint8_t* channel, - uint8_t taskslot_no); + uint8_t* channel, + uint8_t taskslot_no); uint8_t LLC_check_iq_samples_ready_ucfg_weak(uint8_t* iq_samples_number, - uint8_t* channel, - uint8_t taskslot_no); + uint8_t* channel, + uint8_t taskslot_no); uint8_t LLC_check_iq_samples_ready(uint8_t* iq_samples_number, - uint8_t* channel, - uint8_t taskslot_no); + uint8_t* channel, + uint8_t taskslot_no); void llc_cte_init_ucfg(void); void llc_cte_init_ucfg_weak(void); @@ -1619,9 +1824,12 @@ void llc_cte_timer_error_ucfg(void); void llc_cte_timer_error_ucfg_weak(void); void llc_cte_timer_error(void); -void llc_cte_timer_start_ucfg(void* params); -void llc_cte_timer_start_ucfg_weak(void* params); -void llc_cte_timer_start(void* params); +void llc_cte_timer_start_ucfg(void* params, + uint32_t radio_task_anchor); +void llc_cte_timer_start_ucfg_weak(void* params, + uint32_t radio_task_anchor); +void llc_cte_timer_start(void* params, + uint32_t radio_task_anchor); uint8_t llc_cte_timer_stop_ucfg(void); uint8_t llc_cte_timer_stop_ucfg_weak(void); @@ -1635,15 +1843,15 @@ void LLC_test_set_cte_ucfg(void* params); void LLC_test_set_cte_ucfg_weak(void* params); void LLC_test_set_cte(void* params); -void ADV_ISR_connect_request_received_ucfg(void* pointer, - uint8_t* packet, - void* PeerIDAddress_p); -void ADV_ISR_connect_request_received_ucfg_weak(void* pointer, - uint8_t* packet, - void* PeerIDAddress_p); -void ADV_ISR_connect_request_received(void* pointer, - uint8_t* packet, - void* PeerIDAddress_p); +uint8_t ADV_ISR_connect_request_received_ucfg(void* pointer, + uint8_t* packet, + void* PeerIDAddress_p); +uint8_t ADV_ISR_connect_request_received_ucfg_weak(void* pointer, + uint8_t* packet, + void* PeerIDAddress_p); +uint8_t ADV_ISR_connect_request_received(void* pointer, + uint8_t* packet, + void* PeerIDAddress_p); void LL_eadv_EauxIsr_connect_response_sent_ucfg(void* pointer); void LL_eadv_EauxIsr_connect_response_sent_ucfg_weak(void* pointer); @@ -1667,9 +1875,12 @@ tBleStatus llc_eadv_max_supported_data_check_ucfg_weak(uint16_t data_length, tBleStatus llc_eadv_max_supported_data_check(uint16_t data_length, void* pointer); -void LL_eadv_start_extended_ucfg(void* pointer); -void LL_eadv_start_extended_ucfg_weak(void* pointer); -void LL_eadv_start_extended(void* pointer); +tBleStatus LL_eadv_start_extended_ucfg(void* pointer, + uint32_t anchor_stu); +tBleStatus LL_eadv_start_extended_ucfg_weak(void* pointer, + uint32_t anchor_stu); +tBleStatus LL_eadv_start_extended(void* pointer, + uint32_t anchor_stu); uint8_t ext_adv_scan_enabled_ucfg(void); uint8_t ext_adv_scan_enabled_ucfg_weak(void); @@ -1683,12 +1894,9 @@ tBleStatus LL_Remove_Advertising_Set_ucfg(uint16_t Advertising_Handle); tBleStatus LL_Remove_Advertising_Set_ucfg_weak(uint16_t Advertising_Handle); tBleStatus LL_Remove_Advertising_Set(uint16_t Advertising_Handle); -uint8_t Data_Len_Update_Offline_Processing_ucfg(void* params, - uint32_t ctrl_flds); -uint8_t Data_Len_Update_Offline_Processing_ucfg_weak(void* params, - uint32_t ctrl_flds); -uint8_t Data_Len_Update_Offline_Processing(void* params, - uint32_t ctrl_flds); +uint8_t Data_Len_Update_Offline_Processing_ucfg(void* params); +uint8_t Data_Len_Update_Offline_Processing_ucfg_weak(void* params); +uint8_t Data_Len_Update_Offline_Processing(void* params); tBleStatus ll_write_supported_data_ucfg(uint16_t Supported_Max_Tx_Octets, uint16_t Supported_Max_Tx_Time, @@ -1737,10 +1945,6 @@ void LL_init(uint8_t dataLenExt, uint8_t Cns, uint8_t Chc); -tBleStatus smp_debug_trudy__set_config_ucfg(uint32_t config); -tBleStatus smp_debug_trudy__set_config_ucfg_weak(uint32_t config); -tBleStatus smp_debug_trudy__set_config(uint32_t config); - tBleStatus smp_start_encryption_ucfg(void* params); tBleStatus smp_start_encryption_ucfg_weak(void* params); tBleStatus smp_start_encryption(void* params); @@ -2135,6 +2339,8 @@ tBleStatus aci_gatt_clt_execute_write_req_api(uint16_t Connection_Handle, tBleStatus aci_gatt_clt_confirm_indication_api(uint16_t Connection_Handle, uint16_t CID); +tBleStatus aci_gatt_clt_add_subscription_security_level_api(ble_gatt_clt_sec_level_st* sec_level_p); + tBleStatus aci_hal_peripheral_latency_enable_api(uint16_t Connection_Handle, uint8_t Enable); @@ -2466,25 +2672,6 @@ tBleStatus hci_le_remove_advertising_set_api(uint8_t Advertising_Handle); tBleStatus hci_le_clear_advertising_sets_api(void); -tBleStatus hci_le_set_default_periodic_advertising_sync_transfer_parameters_api(uint8_t Mode, - uint16_t Skip, - uint16_t Sync_Timeout, - uint8_t CTE_Type); - -tBleStatus hci_le_set_periodic_advertising_sync_transfer_parameters_api(uint16_t Connection_Handle, - uint8_t Mode, - uint16_t Skip, - uint16_t Sync_Timeout, - uint8_t CTE_Type); - -tBleStatus hci_le_periodic_advertising_set_info_transfer_api(uint16_t Connection_Handle, - uint16_t Service_Data, - uint8_t Advertising_Handle); - -tBleStatus hci_le_periodic_advertising_sync_transfer_api(uint16_t Connection_Handle, - uint16_t Service_Data, - uint16_t Sync_Handle); - tBleStatus hci_le_iso_transmit_test_api(uint16_t Connection_Handle, uint8_t Payload_Type); @@ -2565,6 +2752,25 @@ tBleStatus hci_le_set_periodic_advertising_parameters_v2_api(uint8_t Advertising uint8_t Response_Slot_Spacing, uint8_t Num_Response_Slots); +tBleStatus hci_le_periodic_advertising_set_info_transfer_api(uint16_t Connection_Handle, + uint16_t Service_Data, + uint8_t Advertising_Handle); + +tBleStatus hci_le_periodic_advertising_sync_transfer_api(uint16_t Connection_Handle, + uint16_t Service_Data, + uint16_t Sync_Handle); + +tBleStatus hci_le_set_default_periodic_advertising_sync_transfer_parameters_api(uint8_t Mode, + uint16_t Skip, + uint16_t Sync_Timeout, + uint8_t CTE_Type); + +tBleStatus hci_le_set_periodic_advertising_sync_transfer_parameters_api(uint16_t Connection_Handle, + uint8_t Mode, + uint16_t Skip, + uint16_t Sync_Timeout, + uint8_t CTE_Type); + tBleStatus hci_le_enhanced_read_transmit_power_level_api(uint16_t Connection_Handle, uint8_t PHY, int8_t* Current_TX_Power_Level, diff --git a/lib/stm32wb0/STM32_BLE/stack/include/ble_status.h b/lib/stm32wb0/STM32_BLE/stack/include/ble_status.h index fb2f4bf78..61790a81e 100644 --- a/lib/stm32wb0/STM32_BLE/stack/include/ble_status.h +++ b/lib/stm32wb0/STM32_BLE/stack/include/ble_status.h @@ -226,10 +226,10 @@ typedef uint8_t tBleStatus; */ /** - * @brief The remote device in in the Blacklist and the pairing operation it requested - * cannot be performed. + * @brief The remote device is in the reject list due to repeated pairing attempts + * and the procedure cannot be started. */ -#define BLE_STATUS_DEV_IN_BLACKLIST ((tBleStatus)(0xB0)) +#define BLE_STATUS_REPEATED_ATTEMPTS ((tBleStatus)(0xB0)) /** * @brief CSRK not found during validation of an incoming signed packet @@ -309,7 +309,7 @@ typedef uint8_t tBleStatus; #define BLE_STATUS_INVALID_SCAN_CONFIGURATION ((tBleStatus)(0xD1)) /** - * @brief The configuration set by the aci_gap_set_connect_configuration command + * @brief The configuration set by the aci_gap_set_connection_configuration command * is not coherent with the GAP procedure that is requested to be started */ #define BLE_STATUS_INVALID_CONNECT_CONFIGURATION ((tBleStatus)(0xD2)) diff --git a/lib/stm32wb0/STM32_BLE/stack/include/bleplat.h b/lib/stm32wb0/STM32_BLE/stack/include/bleplat.h index 81c636012..6c91c30bb 100644 --- a/lib/stm32wb0/STM32_BLE/stack/include/bleplat.h +++ b/lib/stm32wb0/STM32_BLE/stack/include/bleplat.h @@ -122,11 +122,10 @@ int BLEPLAT_MemCmp(void *S1, void *S2, unsigned int Size); * This function returns the device ID, version and revision numbers. * To be called by the BLE Stack for ensuring platform independence. * - * @param[out] device_id Device ID (6 = STM32WB09) - * @param[out] major_cut Device cut version/major number - * @param[out] minor_cut Device cut revision/minor number + * @param[out] pDeviceId Device ID (6 = STM32WB09) + * @param[out] pMajorCut Device cut version/major number + * @param[out] pMinorCut Device cut revision/minor number * - * @retval None */ void BLEPLAT_GetPartInfo(uint8_t *pDeviceId, uint8_t *pMajorCut, uint8_t *pMinorCut); @@ -194,7 +193,7 @@ void BLEPLAT_RngGetRandom32(uint32_t* Num); /** * @brief Convert TX output power in dBm to the related Power Amplifier level - * @param TX_dBm Desired TX output power. + * @param TxDBm Desired TX output power. * * @retval PA level that has to be set in the radio register to have a TX * output power lower than or equal to the desired output power @@ -203,7 +202,7 @@ uint8_t BLEPLAT_DBmToPALevel(int8_t TxDBm); /** * @brief Convert TX output power in dBm to the related Power Amplifier level - * @param TX_dBm Desired TX output power. + * @param TxDBm Desired TX output power. * * @retval PA level that has to be set in the radio register to have a TX * output power greater than or equal to the desired output power @@ -212,7 +211,7 @@ uint8_t BLEPLAT_DBmToPALevelGe(int8_t TxDBm); /** * @brief Convert Power Amplifier level to TX output power in dBm - * @param PA_Level Level setting for the Power Amplifier + * @param PaLevel Level setting for the Power Amplifier * * @retval Output power in dBm, corresponding to the given PA level. If PA * level is invalid, returned value is 127. @@ -221,19 +220,17 @@ int8_t BLEPLAT_PALevelToDBm(uint8_t PaLevel); /** * @brief Return minimum and maximum supported TX power. - * @param[out] Min_Tx_Power Minimum supported TX power in dBm. - * @param[out] Max_Tx_Power Maximum supported TX power in dBm. + * @param[out] MinTxPower Minimum supported TX power in dBm. + * @param[out] MaxTxPower Maximum supported TX power in dBm. * - * @retval None */ void BLEPLAT_ReadTransmitPower(int8_t *MinTxPower, int8_t *MaxTxPower); /** * @brief Configure the radio in order to increase output power level. * @note This function should be called only by the BLE stack. - * @param enable Enable or disable the ability to reach maximum TX power. + * @param Enable Enable or disable the ability to reach maximum TX power. * Set to 1 to enable high power mode. Set ot 0 to disable. - * @retval None */ void BLEPLAT_SetHighPower(uint8_t Enable); @@ -245,17 +242,17 @@ void BLEPLAT_SetHighPower(uint8_t Enable); int8_t BLEPLAT_CalculateRSSI(void); /** - * @brief Return the next value of the average of RSSI values - * given the current RSSI average value and the next RSSI value. + * @brief This function must return the average of RSSI values + * given the past RSSI average value and the next RSSI value. * All values are signed and expressed in dBm. * An Exponential Moving Average algorithm is applied. - * @param avg_rssi Current RSSI average value. - * Set to 127 to return the 'rssi' value. - * @param rssi Next RSSI value - * @param rssi_filter_coeff Coefficient used for the filtering of + * @param AvgRssi Past RSSI average value. + * It is 127 if no average is available yet (i.e. first sample). + * @param Rssi Current RSSI value + * @param RssiFilterCoeff Coefficient used for the filtering of * the RSSI samples and the calculation of * the average RSSI. - * @retval Next RSSI average value + * @retval RSSI average value */ int8_t BLEPLAT_UpdateAvgRSSI(int8_t AvgRssi, int8_t Rssi, uint8_t RssiFilterCoeff); diff --git a/lib/stm32wb0/STM32_BLE/stack/include/bleplat_cntr.h b/lib/stm32wb0/STM32_BLE/stack/include/bleplat_cntr.h index b780259a4..5baa9f3d0 100644 --- a/lib/stm32wb0/STM32_BLE/stack/include/bleplat_cntr.h +++ b/lib/stm32wb0/STM32_BLE/stack/include/bleplat_cntr.h @@ -239,8 +239,8 @@ void BLEPLAT_CNTR_SmToggleSn(uint8_t smNo); void BLEPLAT_CNTR_StartEncrypt(void); uint32_t BLEPLAT_CNTR_TimeDiff(uint32_t x, uint32_t y); uint8_t BLEPLAT_CNTR_DemodDelaySt(uint8_t RxPHY); -uint32_t BLEPLAT_CNTR_GetTimer2TimeoutForIfs(uint32_t T_Ifs, BLEPLAT_CNTR_Transaction Transaction, uint8_t Cal_Enabled); - +uint32_t BLEPLAT_CNTR_GetTimer2TimeoutForIfs(uint32_t T_Ifs, BLEPLAT_CNTR_Transaction Transaction, uint8_t Rx_Phy, uint8_t Tx_Phy, uint8_t Cal_Enabled); +uint32_t BLEPLAT_CNTR_IsEnabledTimer1(void); /** * @} diff --git a/scripts/ble_library.py b/scripts/ble_library.py index 6dc8f8b76..39d7090f9 100644 --- a/scripts/ble_library.py +++ b/scripts/ble_library.py @@ -145,6 +145,81 @@ ], } +wb0_ble_transparent_mode_app_path = "Projects/NUCLEO-WB09KE/Applications/BLE/" \ + + "BLE_TransparentMode" + +file_list_wb0 = { + "STM32_BLE": [ + "Middlewares/ST/STM32_BLE/ble.h", + "Middlewares/ST/STM32_BLE/stack/config/ble_stack_user_cfg.c", + "Middlewares/ST/STM32_BLE/stack/include/ble_api.h", + "Middlewares/ST/STM32_BLE/stack/include/ble_const.h", + "Middlewares/ST/STM32_BLE/stack/include/ble_events.h", + "Middlewares/ST/STM32_BLE/stack/include/ble_gatt.h", + "Middlewares/ST/STM32_BLE/stack/include/bleplat_cntr.h", + "Middlewares/ST/STM32_BLE/stack/include/bleplat.h", + "Middlewares/ST/STM32_BLE/stack/include/ble_stack.h", + "Middlewares/ST/STM32_BLE/stack/include/ble_stack_user_cfg.h", + "Middlewares/ST/STM32_BLE/stack/include/ble_status.h", + "Middlewares/ST/STM32_BLE/stack/include/ble_types.h", + "Middlewares/ST/STM32_BLE/stack/include/uuid.h", + ], + "BLE_TransparentMode": [ + wb0_ble_transparent_mode_app_path + "/Core/Inc/app_common.h", + wb0_ble_transparent_mode_app_path + "/Core/Inc/app_conf.h", + wb0_ble_transparent_mode_app_path + "/Core/Src/stm32wb0x_hal_msp.c", + wb0_ble_transparent_mode_app_path + "/STM32_BLE/App/aci_adv_nwk.c", + wb0_ble_transparent_mode_app_path + "/STM32_BLE/App/aci_adv_nwk.h", + wb0_ble_transparent_mode_app_path + "/STM32_BLE/App/aci_gatt_nwk.h", + wb0_ble_transparent_mode_app_path + "/STM32_BLE/App/aci_l2cap_nwk.h", + wb0_ble_transparent_mode_app_path + "/STM32_BLE/App/adv_buff_alloc.c", + wb0_ble_transparent_mode_app_path + "/STM32_BLE/App/adv_buff_alloc.h", + wb0_ble_transparent_mode_app_path + "/STM32_BLE/App/adv_buff_alloc_tiny.c", + wb0_ble_transparent_mode_app_path + "/STM32_BLE/App/adv_buff_alloc_tiny.h", + wb0_ble_transparent_mode_app_path + "/STM32_BLE/App/app_ble.h", + wb0_ble_transparent_mode_app_path + "/STM32_BLE/App/ble_conf.h", + wb0_ble_transparent_mode_app_path + "/STM32_BLE/App/dm_alloc.c", + wb0_ble_transparent_mode_app_path + "/STM32_BLE/App/dm_alloc.h", + wb0_ble_transparent_mode_app_path + "/STM32_BLE/App/dtm_burst.h", + wb0_ble_transparent_mode_app_path + "/STM32_BLE/App/dtm_cmd_db.c", + wb0_ble_transparent_mode_app_path + "/STM32_BLE/App/dtm_cmd_db.h", + wb0_ble_transparent_mode_app_path + "/STM32_BLE/App/dtm_cmd_en.h", + wb0_ble_transparent_mode_app_path + "/STM32_BLE/App/dtm_cmds.c", + wb0_ble_transparent_mode_app_path + "/STM32_BLE/App/dtm_cmds.h", + wb0_ble_transparent_mode_app_path + "/STM32_BLE/App/dtm_cmd_stack_en.h", + wb0_ble_transparent_mode_app_path + "/STM32_BLE/App/dtm_preprocess_events.c", + wb0_ble_transparent_mode_app_path + "/STM32_BLE/App/dtm_preprocess_events.h", + wb0_ble_transparent_mode_app_path + "/STM32_BLE/App/fifo.h", + wb0_ble_transparent_mode_app_path + "/STM32_BLE/App/hci_parser.h", + wb0_ble_transparent_mode_app_path + "/STM32_BLE/App/pawr_buff_alloc.c", + wb0_ble_transparent_mode_app_path + "/STM32_BLE/App/pawr_buff_alloc.h", + wb0_ble_transparent_mode_app_path + "/STM32_BLE/App/transport_layer.c", + wb0_ble_transparent_mode_app_path + "/STM32_BLE/App/transport_layer.h", + wb0_ble_transparent_mode_app_path + "/STM32_BLE/Target/bleplat.c", + wb0_ble_transparent_mode_app_path + "/STM32_BLE/Target/bleplat_cntr.c", + ], + "Common": [ + "Projects/Common/BLE/Interfaces/hw_aes.c", + "Projects/Common/BLE/Interfaces/hw_aes.h", + "Projects/Common/BLE/Interfaces/hw_pka.c", + "Projects/Common/BLE/Interfaces/hw_pka.h", + "Projects/Common/BLE/Interfaces/hw_rng.c", + "Projects/Common/BLE/Interfaces/hw_rng.h", + "Projects/Common/BLE/Modules/asm.h", + "Projects/Common/BLE/Modules/blue_unit_conversion.s", + "Projects/Common/BLE/Modules/compiler.h", + "Projects/Common/BLE/Modules/crash_handler.h", + "Projects/Common/BLE/Modules/miscutil.c", + "Projects/Common/BLE/Modules/miscutil.h", + "Projects/Common/BLE/Modules/osal.h", + "Projects/Common/BLE/Modules/osal_memcpy.s", + "Projects/Common/BLE/Modules/PKAMGR/Inc/pka_manager.h", + "Projects/Common/BLE/Modules/PKAMGR/Src/pka_manager.c", + "Projects/Common/BLE/Modules/RADIO_utils/Inc/RADIO_utils.h", + "Projects/Common/BLE/Modules/RADIO_utils/Src/RADIO_utils.c", + ], +} + def os_cmd(cmd, cwd=None, shell=False): """Execute a command with subprocess.check_call() @@ -193,15 +268,25 @@ def copy_ble_lib_files(src_repo_path, dest_lib_path, stm32_serie): logging.error("Abort") sys.exit() - elif stm32_serie == "stm32wba": + elif stm32_serie in ["stm32wba", "stm32wb0"]: + + if stm32_serie == "stm32wba": + target_file_list = file_list_wba + elif stm32_serie == "stm32wb0": + target_file_list = file_list_wb0 + else: + logging.error(f"File : Unexpected series {stm32_serie}") + logging.error("Abort") + sys.exit() + # Remove existing *.c and *.h files for root, _, files in os.walk(dest_lib_path): for file in files: if file.endswith(".c") or file.endswith(".h"): os.remove(os.path.join(root, file)) - for dir_name in file_list_wba: - for file in file_list_wba[dir_name]: + for dir_name in target_file_list: + for file in target_file_list[dir_name]: # Src file path to be copied src_file_path = Path(src_repo_path / file) if src_file_path.exists(): diff --git a/scripts/serie_update.py b/scripts/serie_update.py index 06dbbdeb9..c4110b825 100644 --- a/scripts/serie_update.py +++ b/scripts/serie_update.py @@ -56,7 +56,7 @@ def __init__( """Class Stm32SerieUpdate constructor Args: - stm32_serie: stm32 serie ex:stm32f3xx + stm32_serie: stm32 series name (without 'x' suffixes), e.g. 'stm32f3' stm32cube_repo_path: directory path where to fetch github repo noclean: boolean to clean or not github repo after update done version_update: string to force a specified version to be updated @@ -76,9 +76,17 @@ def __init__( # Set serie variables self.stm32_serie = stm32_serie - self.stm32_seriexx = stm32_serie + "xx" # ex:stm32f3xx + + # STM32WB0 uses a single 'x' suffix in HAL/LL resources + if self.stm32_serie == 'stm32wb0': + x_suffix = 'x' + else: + x_suffix = 'xx' + + self.stm32_seriexx = stm32_serie + x_suffix + self.stm32_serie_upper = stm32_serie.upper() # ex:STM32F3 - self.stm32_seriexx_upper = self.stm32_serie_upper + "xx" # ex:STM32F3xx + self.stm32_seriexx_upper = self.stm32_serie_upper + x_suffix # ex:STM32F3xx self.serie = self.stm32_serie_upper[5:] self.noclean = noclean self.version_update = version_update @@ -273,13 +281,20 @@ def extract_source(self): temp_cmsis_soc_path = self.stm32cube_temp_serie / "soc" Path.mkdir(temp_cmsis_soc_path, parents=True) + # STM32WB0 uses a specifc CMSIS device driver path + # with a single uppercase X suffix. + if self.stm32_serie == 'stm32wb0': + cmsis_device_dir = 'STM32WB0X' + else: + cmsis_device_dir = self.stm32_seriexx_upper + stm32cube_cmsis_include_path = ( self.stm32cube_serie_path / "Drivers" / "CMSIS" / "Device" / "ST" - / self.stm32_seriexx_upper + / cmsis_device_dir / "Include" ) shutil.rmtree(temp_cmsis_soc_path, onerror=common_utils.remove_readonly) @@ -291,7 +306,7 @@ def extract_source(self): / "CMSIS" / "Device" / "ST" - / self.stm32_seriexx_upper + / cmsis_device_dir / "Source" / "Templates" ) @@ -764,24 +779,11 @@ def update_stm32_hal_serie(self): self.apply_zephyr_patch() self.merge_commit() - # 8) In case of stm32wb, update ble library - if self.stm32_serie == "stm32wb": - ble_library.update( - self.stm32cube_serie_path, - Path(self.zephyr_hal_stm32_path / "lib" / "stm32wb"), - self.stm32cube_temp, - self.current_version, - self.version_update, - self.update_commit, - self.stm32_serie - ) - self.merge_commit(lib=True) - - # 9) In case of stm32wba, update hci library - elif self.stm32_serie == "stm32wba": + # 8) In case of stm32wb/wba/wb0, update library + if self.stm32_serie in ["stm32wb", "stm32wba", "stm32wb0"]: ble_library.update( self.stm32cube_serie_path, - Path(self.zephyr_hal_stm32_path / "lib" / "stm32wba"), + Path(self.zephyr_hal_stm32_path / "lib" / self.stm32_serie), self.stm32cube_temp, self.current_version, self.version_update, @@ -790,6 +792,6 @@ def update_stm32_hal_serie(self): ) self.merge_commit(lib=True) - # 10) clean + # 9) clean self.clean_files() logging.info("%s", f"Done {self.stm32_serie}\n") diff --git a/scripts/update_stm32_package.py b/scripts/update_stm32_package.py index 5a1ec5c6b..a7a5f715e 100644 --- a/scripts/update_stm32_package.py +++ b/scripts/update_stm32_package.py @@ -78,9 +78,16 @@ def update_cubes(): "%s", f"*************** updating module {stmyyxx.name} *****************", ) + + # STM32WB0 uses a single 'x' suffix in HAL/LL resources + if stmyyxx.name == 'stm32wb0x': + serie_name = stmyyxx.name[:-1] + else: + serie_name = stmyyxx.name[:-2] + # Force the commit for each serie update_serie = serie_update.Stm32SerieUpdate( - stmyyxx.name[:-2], + serie_name, repo_path, noclean=args.noclean, debug=args.debug, diff --git a/stm32cube/common_ll/README.rst b/stm32cube/common_ll/README.rst index 2622c1e77..32e8b1b1c 100644 --- a/stm32cube/common_ll/README.rst +++ b/stm32cube/common_ll/README.rst @@ -33,7 +33,7 @@ stm32n6xx 1.2.0 stm32u0xx 1.3.0 stm32u3xx 1.2.0 stm32u5xx 1.8.0 -stm32wb0x 1.0.0 +stm32wb0x 1.4.0 stm32wbaxx 1.7.0 stm32wbxx 1.23.0 stm32wlxx 1.3.1 diff --git a/stm32cube/stm32wb0x/README b/stm32cube/stm32wb0x/README index 2f6eefb1f..a79f65752 100644 --- a/stm32cube/stm32wb0x/README +++ b/stm32cube/stm32wb0x/README @@ -6,7 +6,7 @@ Origin: http://www.st.com/en/embedded-software/stm32cubewb0.html Status: - version v1.0.0 + version v1.4.0 Purpose: STMicroelectronics official MCU package for STM32WB0 series. @@ -23,7 +23,7 @@ URL: https://github.com/STMicroelectronics/STM32CubeWB0 Commit: - 61d80e00cdb6136a58a33b95d2137e3bc9baa28e + feb9b9624b10a3af4e5dccb390a01b0cc4d71771 Maintained-by: External @@ -44,7 +44,9 @@ Patch List: -Added stm32cube/stm32wb0x/drivers/include/stm32_assert.h -Removed unused stm32cube/stm32wb0x/drivers/include/stm32_assert_template.h - *Added patches to enable compilation with Zephyr + *Added patches to enable compilation with Zephyr. + See commit e8043b4d124e ("stm32cube: stm32wb0x: add compatibility patches") + from pull request https://github.com/zephyrproject-rtos/hal_stm32/pull/230. -exclude stm32cube/stm32wb0x/soc/system_stm32wb0.c from build . Missing definitions moved to 'zephyr/soc/st/stm32/stm32wb0xx/soc.c' . SystemCoreClock (CMSIS global variable) @@ -61,4 +63,4 @@ Patch List: . Remove definition of __blue_RAM variable . Moved to 'zephyr/soc/st/stm32/stm32wb0xx/soc.c' - See Release_Notes.html from STM32Cube for more details. + See release_note.html from STM32Cube diff --git a/stm32cube/stm32wb0x/drivers/include/Legacy/stm32_hal_legacy.h b/stm32cube/stm32wb0x/drivers/include/Legacy/stm32_hal_legacy.h index 9f367692d..3729be054 100644 --- a/stm32cube/stm32wb0x/drivers/include/Legacy/stm32_hal_legacy.h +++ b/stm32cube/stm32wb0x/drivers/include/Legacy/stm32_hal_legacy.h @@ -361,7 +361,10 @@ extern "C" { #if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \ defined(STM32L4S7xx) || defined(STM32L4S9xx) #define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI -#endif +#elif defined(STM32L4P5xx) || defined(STM32L4Q5xx) +#define DMA_REQUEST_PSSI DMA_REQUEST_DCMI_PSSI +#define LL_DMAMUX_REQ_PSSI LL_DMAMUX_REQ_DCMI_PSSI +#endif /* STM32L4R5xx || STM32L4R9xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #endif /* STM32L4 */ @@ -472,9 +475,9 @@ extern "C" { #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD -#if 0 /** PATCH: do not define PAGESIZE (for POSIX compatibility) */ - #define PAGESIZE FLASH_PAGE_SIZE -#endif /* ENDOF PATCH */ +#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) && !defined(STM32H5) +/* #define PAGESIZE FLASH_PAGE_SIZE */ +#endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 && STM32H5 */ #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD @@ -538,6 +541,10 @@ extern "C" { #define FLASH_FLAG_WDW FLASH_FLAG_WBNE #define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL #endif /* STM32H7 */ +#if defined(STM32H7RS) +#define FLASH_OPTKEY1 FLASH_OPT_KEY1 +#define FLASH_OPTKEY2 FLASH_OPT_KEY2 +#endif /* STM32H7RS */ #if defined(STM32U5) #define OB_USER_nRST_STOP OB_USER_NRST_STOP #define OB_USER_nRST_STDBY OB_USER_NRST_STDBY @@ -560,6 +567,9 @@ extern "C" { #define OB_nBOOT0_RESET OB_NBOOT0_RESET #define OB_nBOOT0_SET OB_NBOOT0_SET #endif /* STM32U0 */ +#if defined(STM32H5) +#define FLASH_ECC_AREA_EDATA FLASH_ECC_AREA_EDATA_BANK1 +#endif /* STM32H5 */ /** * @} @@ -603,6 +613,15 @@ extern "C" { #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD #endif /* STM32G4 */ +#if defined(STM32U5) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOAnalogBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOAnalogBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection HAL_SYSCFG_EnableIOAnalogVoltageSelection +#define HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection HAL_SYSCFG_DisableIOAnalogVoltageSelection + +#endif /* STM32U5 */ + #if defined(STM32H5) #define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC #define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC @@ -877,6 +896,10 @@ extern "C" { #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE +#if defined(STM32F3) || defined(STM32G4) || defined(STM32H7) +#define HRTIMInterruptResquests HRTIMInterruptRequests +#endif /* STM32F3 || STM32G4 || STM32H7 */ + #if defined(STM32G4) #define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig #define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable @@ -1014,8 +1037,8 @@ extern "C" { #define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) #define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) #define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) - #endif /* STM32F3 */ + /** * @} */ @@ -1266,10 +1289,10 @@ extern "C" { #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 -#if defined(STM32H5) || defined(STM32H7RS) +#if defined(STM32H5) || defined(STM32H7RS) || defined(STM32N6) #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE #define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM -#endif /* STM32H5 || STM32H7RS */ +#endif /* STM32H5 || STM32H7RS || STM32N6 */ #if defined(STM32WBA) #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE @@ -1281,27 +1304,27 @@ extern "C" { #define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL #endif /* STM32WBA */ -#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) #define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE #define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL -#endif /* STM32H5 || STM32WBA || STM32H7RS */ +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ -#if defined(STM32F7) +#if defined(STM32F7) || defined(STM32WB) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK -#endif /* STM32F7 */ +#endif /* STM32F7 || STM32WB */ #if defined(STM32H7) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_X #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT #endif /* STM32H7 */ -#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) +#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) || defined(STM32WB) #define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 #define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 #define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 #define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP -#endif /* STM32F7 || STM32H7 || STM32L0 */ +#endif /* STM32F7 || STM32H7 || STM32L0 || STM32WB */ /** * @} @@ -1468,7 +1491,7 @@ extern "C" { #define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 #endif -#if defined(STM32U5) +#if defined(STM32U5) || defined(STM32MP2) #define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS #define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK #endif @@ -2016,12 +2039,12 @@ extern "C" { /** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose * @{ */ -#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) #define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey #define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock #define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock #define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets -#endif /* STM32H5 || STM32WBA || STM32H7RS */ +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ /** * @} @@ -2129,6 +2152,13 @@ extern "C" { #define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER #define CMP_PD_BitNumber CMP_PD_BIT_NUMBER +#if defined(STM32H7RS) || defined(STM32N6) +#define FMC_SWAPBMAP_DISABLE FMC_SWAPBANK_MODE0 +#define FMC_SWAPBMAP_SDRAM_SRAM FMC_SWAPBANK_MODE1 +#define HAL_SetFMCMemorySwappingConfig HAL_FMC_SetBankSwapConfig +#define HAL_GetFMCMemorySwappingConfig HAL_FMC_GetBankSwapConfig +#endif /* STM32H7RS || STM32N6 */ + /** * @} */ @@ -3681,7 +3711,7 @@ extern "C" { #define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK #endif -#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) || defined(STM32C0) || defined(STM32H7RS) || defined(STM32U0) +#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || defined(STM32U0) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK @@ -3930,7 +3960,7 @@ extern "C" { /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0) +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32N6) || defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -4224,6 +4254,33 @@ extern "C" { #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo +#if defined(STM32U5) +#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSVLD +#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINTMSK +#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPC +#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_PSRST +#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_GONAKEFF +#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUPINT +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM +#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_CHNUM +#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1RSMOK +#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFSIZ +#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MCNT +#define USB_OTG_HCCHAR_MC_0 USB_OTG_HCCHAR_MCNT_0 +#define USB_OTG_HCCHAR_MC_1 USB_OTG_HCCHAR_MCNT_1 +#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERRM +#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPNG +#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OUTPKTERRM +#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM +#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MCNT +#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM +#define USB_OTG_DOEPCTL_DPID USB_OTG_DOEPCTL_DPID_EONUM +#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_RXDPID +#define USB_OTG_DOEPTSIZ_STUPCNT_0 USB_OTG_DOEPTSIZ_RXDPID_0 +#define USB_OTG_DOEPTSIZ_STUPCNT_1 USB_OTG_DOEPTSIZ_RXDPID_1 +#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STPPCLK +#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATEHCLK +#endif /** * @} */ diff --git a/stm32cube/stm32wb0x/drivers/include/stm32wb0x_hal.h b/stm32cube/stm32wb0x/drivers/include/stm32wb0x_hal.h index b86ae976e..cfa9ae892 100644 --- a/stm32cube/stm32wb0x/drivers/include/stm32wb0x_hal.h +++ b/stm32cube/stm32wb0x/drivers/include/stm32wb0x_hal.h @@ -48,7 +48,7 @@ extern "C" { * @brief HAL Driver version number */ #define __STM32WB0x_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32WB0x_HAL_VERSION_SUB1 (0x00U) /*!< [23:16] sub1 version */ +#define __STM32WB0x_HAL_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */ #define __STM32WB0x_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32WB0x_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32WB0x_HAL_VERSION ((__STM32WB0x_HAL_VERSION_MAIN << 24U)\ diff --git a/stm32cube/stm32wb0x/drivers/include/stm32wb0x_hal_adc.h b/stm32cube/stm32wb0x/drivers/include/stm32wb0x_hal_adc.h index 920a97cb2..e73d2beb4 100644 --- a/stm32cube/stm32wb0x/drivers/include/stm32wb0x_hal_adc.h +++ b/stm32cube/stm32wb0x/drivers/include/stm32wb0x_hal_adc.h @@ -365,10 +365,14 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @{ */ -#define ADC_SAMPLING_AT_START (LL_ADC_SAMPLING_AT_START) /*!< Sampling only at conversion start (default) */ -#define ADC_SAMPLING_AT_END (LL_ADC_SAMPLING_AT_END) /*!< Sampling sampling phase starts after end of - conversion, and stops upon trigger event - (Also known as Bulb sampling mode). */ +#define ADC_SAMPLING_AT_START (LL_ADC_SAMPLING_AT_START) /*!< Sampling phase starts only at conversion start and + sampling time is 125ns regardless of the sampling + period (default). */ +#define ADC_SAMPLING_AT_END (LL_ADC_SAMPLING_AT_END) /*!< Sampling phase starts after end of + conversion, and stops upon trigger event (Also known + as Bulb sampling mode). + Sampling time is a function of the sampling period + (Sample rate). */ /** * @} diff --git a/stm32cube/stm32wb0x/drivers/include/stm32wb0x_hal_i2s.h b/stm32cube/stm32wb0x/drivers/include/stm32wb0x_hal_i2s.h index 08efcbe32..4486e2cc7 100644 --- a/stm32cube/stm32wb0x/drivers/include/stm32wb0x_hal_i2s.h +++ b/stm32cube/stm32wb0x/drivers/include/stm32wb0x_hal_i2s.h @@ -451,8 +451,8 @@ void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s); * @{ */ /* Peripheral Control and State functions ************************************/ -HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s); -uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s); +HAL_I2S_StateTypeDef HAL_I2S_GetState(const I2S_HandleTypeDef *hi2s); +uint32_t HAL_I2S_GetError(const I2S_HandleTypeDef *hi2s); /** * @} */ diff --git a/stm32cube/stm32wb0x/drivers/include/stm32wb0x_hal_radio.h b/stm32cube/stm32wb0x/drivers/include/stm32wb0x_hal_radio.h index c48a4353a..e1bed9337 100644 --- a/stm32cube/stm32wb0x/drivers/include/stm32wb0x_hal_radio.h +++ b/stm32cube/stm32wb0x/drivers/include/stm32wb0x_hal_radio.h @@ -96,6 +96,20 @@ typedef struct #endif /* USE_RADIO_PROPRIETARY_DRIVER */ +/** + * @} + */ + +/** @defgroup RADIO_TIMER_Exported_Constants Radio Timer Exported Constants + * @{ + */ + +#define RADIO_INITDELAY_WAKEUP (64U) +#define RADIO_INITDELAY_TIMER12_CAL (63U) +#define RADIO_INITDELAY_TIMER2_NOCAL (9U) + +#define RADIO_TXDELAY_START (16U) +#define RADIO_TXDELAY_END (24U) /** * @} */ @@ -109,10 +123,14 @@ void HAL_RADIO_Init(RADIO_HandleTypeDef *hradio); void HAL_RADIO_TXRX_IRQHandler(void); +void HAL_RADIO_RRM_IRQHandler(void); + void HAL_RADIO_TXRX_SEQ_IRQHandler(void); void HAL_RADIO_TxRxCallback(uint32_t flags); +void HAL_RADIO_RRMCallback(uint32_t ble_irq_status); + void HAL_RADIO_TxRxSeqCallback(void); int8_t HAL_RADIO_ReadRSSI(void); diff --git a/stm32cube/stm32wb0x/drivers/include/stm32wb0x_hal_radio_timer.h b/stm32cube/stm32wb0x/drivers/include/stm32wb0x_hal_radio_timer.h index 8d835a724..40d83e6f2 100644 --- a/stm32cube/stm32wb0x/drivers/include/stm32wb0x_hal_radio_timer.h +++ b/stm32cube/stm32wb0x/drivers/include/stm32wb0x_hal_radio_timer.h @@ -173,7 +173,7 @@ RADIO_TIMER_Status HAL_RADIO_TIMER_GetRadioTimerStatus(uint64_t *time); * @param event_type: Specify if it is a TX (1) or RX (0) event. * @param cal_req: Specify if PLL calibration is requested (1) or not (0). * @retval 0 if radio activity has been scheduled successfully. - * @retval 1 if radio activity has been rejected (it is too close or in the past). + * @retval 1 if radio activity has been rejected. */ uint32_t HAL_RADIO_TIMER_SetRadioTimerValue(uint32_t time, uint8_t event_type, uint8_t cal_req); diff --git a/stm32cube/stm32wb0x/drivers/include/stm32wb0x_hal_smartcard.h b/stm32cube/stm32wb0x/drivers/include/stm32wb0x_hal_smartcard.h index 366ee70d0..d8beeee4a 100644 --- a/stm32cube/stm32wb0x/drivers/include/stm32wb0x_hal_smartcard.h +++ b/stm32cube/stm32wb0x/drivers/include/stm32wb0x_hal_smartcard.h @@ -713,13 +713,13 @@ typedef void (*pSMARTCARD_CallbackTypeDef)(SMARTCARD_HandleTypeDef *hsmartcard) */ #define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ SMARTCARD_CR_POS) == 1U)?\ - ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\ + ((__HANDLE__)->Instance->CR1 &= ~ (1UL <<\ ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ SMARTCARD_CR_POS) == 2U)?\ - ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\ + ((__HANDLE__)->Instance->CR2 &= ~ (1UL <<\ ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\ + ((__HANDLE__)->Instance->CR3 &= ~ (1UL <<\ ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) /** @brief Check whether the specified SmartCard interrupt has occurred or not. diff --git a/stm32cube/stm32wb0x/drivers/include/stm32wb0x_hal_spi.h b/stm32cube/stm32wb0x/drivers/include/stm32wb0x_hal_spi.h index a7319a72c..7e8cd1c4f 100644 --- a/stm32cube/stm32wb0x/drivers/include/stm32wb0x_hal_spi.h +++ b/stm32cube/stm32wb0x/drivers/include/stm32wb0x_hal_spi.h @@ -118,7 +118,7 @@ typedef struct __SPI_HandleTypeDef SPI_InitTypeDef Init; /*!< SPI communication parameters */ - uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ + const uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ uint16_t TxXferSize; /*!< SPI Tx Transfer size */ @@ -426,11 +426,12 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @retval None */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) -#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_SPI_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) +#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) \ + do{ \ + (__HANDLE__)->State = HAL_SPI_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) #else #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ @@ -533,7 +534,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to __IO uint32_t tmpreg_fre = 0x00U; \ tmpreg_fre = (__HANDLE__)->Instance->SR; \ UNUSED(tmpreg_fre); \ - }while(0U) + } while(0U) /** @brief Enable the SPI peripheral. * @param __HANDLE__ specifies the SPI Handle. @@ -577,8 +578,11 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ -#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\ - SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U) +#define SPI_RESET_CRC(__HANDLE__) \ + do{ \ + CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \ + SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \ + } while(0U) /** @brief Check whether the specified SPI flag is set or not. * @param __SR__ copy of SPI SR register. @@ -596,7 +600,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @retval SET or RESET. */ #define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \ - ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) + ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) /** @brief Check whether the specified SPI Interrupt is set or not. * @param __CR2__ copy of SPI CR2 register. @@ -608,7 +612,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @retval SET or RESET. */ #define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \ - (__INTERRUPT__)) ? SET : RESET) + (__INTERRUPT__)) ? SET : RESET) /** @brief Checks if SPI Mode parameter is in allowed range. * @param __MODE__ specifies the SPI Mode. @@ -746,7 +750,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to */ #define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && \ ((__POLYNOMIAL__) <= 0xFFFFU) && \ - (((__POLYNOMIAL__)&0x1U) != 0U)) + (((__POLYNOMIAL__)&0x1U) != 0U)) /** @brief Checks if DMA handle is valid. * @param __HANDLE__ specifies a DMA Handle. @@ -789,17 +793,17 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca * @{ */ /* I/O operation functions ***************************************************/ -HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, - uint32_t Timeout); -HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); @@ -825,8 +829,8 @@ void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi); * @{ */ /* Peripheral State and Error functions ***************************************/ -HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi); -uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); +HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi); +uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi); /** * @} */ diff --git a/stm32cube/stm32wb0x/drivers/include/stm32wb0x_hal_uart.h b/stm32cube/stm32wb0x/drivers/include/stm32wb0x_hal_uart.h index 532730db5..4370a23f6 100644 --- a/stm32cube/stm32wb0x/drivers/include/stm32wb0x_hal_uart.h +++ b/stm32cube/stm32wb0x/drivers/include/stm32wb0x_hal_uart.h @@ -47,12 +47,10 @@ typedef struct { uint32_t BaudRate; /*!< This member configures the UART communication baud rate. The baud rate register is computed using the following formula: - LPUART: - ======= + @note For LPUART : Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate))) - where lpuart_ker_ck_pres is the UART input clock divided by a prescaler - UART: - ===== + where lpuart_ker_ck_pres is the UART input clock divided by a prescaler. + @note For UART : - If oversampling is 16 or in LIN mode, Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate))) - If oversampling is 8, @@ -297,7 +295,11 @@ typedef enum HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, /*!< UART Abort Complete Callback ID */ HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< UART Abort Transmit Complete Callback ID */ HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< UART Abort Receive Complete Callback ID */ +#if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUFIE) HAL_UART_WAKEUP_CB_ID = 0x08U, /*!< UART Wakeup Callback ID */ +#endif /* USART_CR3_WUFIE */ +#endif /* USART_CR1_UESM */ HAL_UART_RX_FIFO_FULL_CB_ID = 0x09U, /*!< UART Rx Fifo Full Callback ID */ HAL_UART_TX_FIFO_EMPTY_CB_ID = 0x0AU, /*!< UART Tx Fifo Empty Callback ID */ @@ -1283,7 +1285,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) /** @defgroup UART_Private_Macros UART Private Macros * @{ */ -/** @brief Get UART clok division factor from clock prescaler value. +/** @brief Get UART clock division factor from clock prescaler value. * @param __CLOCKPRESCALER__ UART prescaler value. * @retval UART clock division factor */ @@ -1298,8 +1300,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) ? 16U : \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) ? 32U : \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) ? 64U : \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256) ? 256U : 1U) + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : 256U) /** @brief BRR division operation to set BRR register with LPUART. * @param __PCLK__ LPUART clock. diff --git a/stm32cube/stm32wb0x/drivers/include/stm32wb0x_hal_uart_ex.h b/stm32cube/stm32wb0x/drivers/include/stm32wb0x_hal_uart_ex.h index fd21e34dc..6b1425fbf 100644 --- a/stm32cube/stm32wb0x/drivers/include/stm32wb0x_hal_uart_ex.h +++ b/stm32cube/stm32wb0x/drivers/include/stm32wb0x_hal_uart_ex.h @@ -151,8 +151,10 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, */ #if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUFIE) void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart); +#endif /* USART_CR3_WUFIE */ #endif /* USART_CR1_UESM */ void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart); void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart); diff --git a/stm32cube/stm32wb0x/drivers/include/stm32wb0x_hal_usart.h b/stm32cube/stm32wb0x/drivers/include/stm32wb0x_hal_usart.h index 535d0db66..d531b6e33 100644 --- a/stm32cube/stm32wb0x/drivers/include/stm32wb0x_hal_usart.h +++ b/stm32cube/stm32wb0x/drivers/include/stm32wb0x_hal_usart.h @@ -537,10 +537,10 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin */ #define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)\ (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\ - ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR1 |= (1UL << ((__INTERRUPT__) & USART_IT_MASK))): \ ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\ - ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK)))) + ((__HANDLE__)->Instance->CR2 |= (1UL << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1UL << ((__INTERRUPT__) & USART_IT_MASK)))) /** @brief Disable the specified USART interrupt. * @param __HANDLE__ specifies the USART Handle. @@ -562,10 +562,10 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin */ #define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)\ (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\ - ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR1 &= ~ (1UL << ((__INTERRUPT__) & USART_IT_MASK))): \ ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\ - ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK)))) + ((__HANDLE__)->Instance->CR2 &= ~ (1UL << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1UL << ((__INTERRUPT__) & USART_IT_MASK)))) /** @brief Check whether the specified USART interrupt has occurred or not. * @param __HANDLE__ specifies the USART Handle. @@ -695,8 +695,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16) ? 16U : \ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32) ? 32U : \ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64) ? 64U : \ - ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) ? 128U : \ - ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256) ? 256U : 1U) + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) ? 128U : 256U) /** @brief BRR division operation to set BRR register in 8-bit oversampling mode. * @param __PCLK__ USART clock. diff --git a/stm32cube/stm32wb0x/drivers/include/stm32wb0x_ll_adc.h b/stm32cube/stm32wb0x/drivers/include/stm32wb0x_ll_adc.h index 4235ecede..58da97cd7 100644 --- a/stm32cube/stm32wb0x/drivers/include/stm32wb0x_ll_adc.h +++ b/stm32cube/stm32wb0x/drivers/include/stm32wb0x_ll_adc.h @@ -348,8 +348,14 @@ typedef struct * @{ */ -#define LL_ADC_SAMPLING_AT_START (0x00000000UL) /*!< Sampling only at conversion start */ -#define LL_ADC_SAMPLING_AT_END (ADC_CONF_ADC_CONT_1V2) /*!< Sampling starts at the end of conversion (default)*/ +#define LL_ADC_SAMPLING_AT_START (0x00000000UL) /*!< Sampling phase starts only at conversion start and + sampling time is 125ns regardless of the sampling + period (default). */ +#define LL_ADC_SAMPLING_AT_END (ADC_CONF_ADC_CONT_1V2) /*!< Sampling phase starts after end of + conversion, and stops upon trigger event (Also known + as Bulb sampling mode). + Sampling time is a function of the sampling period + (Sample rate). */ /** * @} @@ -2070,8 +2076,6 @@ __STATIC_INLINE uint32_t LL_ADC_GetMicrophonePGAGain(const ADC_TypeDef *ADCx) * @arg @ref LL_ADC_CHANNEL_VINP1_VINM1 * @arg @ref LL_ADC_CHANNEL_VINP2_VINM2 * @arg @ref LL_ADC_CHANNEL_VINP3_VINM3 - * @arg @ref LL_ADC_CHANNEL_VBAT - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR * @param Range This parameter can be one of the following values: * @arg @ref LL_ADC_VIN_RANGE_1V2 * @arg @ref LL_ADC_VIN_RANGE_2V4 @@ -2108,8 +2112,6 @@ __STATIC_INLINE void LL_ADC_SetChannelVoltageRange(ADC_TypeDef *ADCx, uint32_t C * @arg @ref LL_ADC_CHANNEL_VINP1_VINM1 * @arg @ref LL_ADC_CHANNEL_VINP2_VINM2 * @arg @ref LL_ADC_CHANNEL_VINP3_VINM3 - * @arg @ref LL_ADC_CHANNEL_VBAT - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_VIN_RANGE_1V2 * @arg @ref LL_ADC_VIN_RANGE_2V4 @@ -2773,7 +2775,7 @@ __STATIC_INLINE void LL_ADC_SetCalibPointGain(ADC_TypeDef *ADCx, uint32_t Point, /** * @brief Get the gain of the calibration point 1. - * @rmtoll COMP_1 GAIN1 LL_ADC_GetCalibPoint1Gain + * @rmtoll COMP_1 GAIN1 LL_ADC_GetCalibPointGain * @param ADCx ADC instance * @param Point This parameter can be one of the following values: * @arg @ref LL_ADC_CALIB_POINT_1 @@ -2792,7 +2794,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetCalibPointGain(const ADC_TypeDef *ADCx, uint3 /** * @brief Set the offset of the calibration point 1. - * @rmtoll COMP_1 OFFSET1 LL_ADC_SetCalibPoint1Offset + * @rmtoll COMP_1 OFFSET1 LL_ADC_SetCalibPointOffset * @param ADCx ADC instance * @param Offset the signed offset of the first calibration point. * @param Point This parameter can be one of the following values: @@ -2812,7 +2814,7 @@ __STATIC_INLINE void LL_ADC_SetCalibPointOffset(ADC_TypeDef *ADCx, uint32_t Poin /** * @brief Get the offset of the calibration point 1. - * @rmtoll COMP_1 OFFSET1 LL_ADC_GetCalibPoint1Offset + * @rmtoll COMP_1 OFFSET1 LL_ADC_GetCalibPointOffset * @param ADCx ADC instance * @param Point This parameter can be one of the following values: * @arg @ref LL_ADC_CALIB_POINT_1 @@ -2899,7 +2901,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetCalibPointForDiff(const ADC_TypeDef *ADCx, ui /** * @brief Set the use of a specific calibration point for * ADC single positive mode - * @rmtoll COMP_SEL ADC_COMP_SEL_OFFSET_GAIN7 LL_ADC_SetCalibPointForSinglePos3V6 + * @rmtoll COMP_SEL ADC_COMP_SEL_OFFSET_GAIN7 LL_ADC_SetCalibPointForSinglePos * @param ADCx ADC instance * @param Point This parameter can be one of the following values: * @arg @ref LL_ADC_CALIB_POINT_1 @@ -2935,7 +2937,7 @@ __STATIC_INLINE void LL_ADC_SetCalibPointForSinglePos(ADC_TypeDef *ADCx, uint32_ /** * @brief Get what calibration point is used for * ADC single positive mode - * @rmtoll COMP_SEL ADC_COMP_SEL_OFFSET_GAIN7 LL_ADC_GetCalibPointForSinglePos3V6 + * @rmtoll COMP_SEL ADC_COMP_SEL_OFFSET_GAIN7 LL_ADC_GetCalibPointForSinglePos * @param ADCx ADC instance * @param Range This parameter can be one of the following values: * @arg @ref LL_ADC_VIN_RANGE_1V2 @@ -3047,6 +3049,8 @@ __STATIC_INLINE uint32_t LL_ADC_GetCalibPointForSingleNeg(const ADC_TypeDef *ADC /** * @brief Configure the WatchDoG threshold low and high. + * @rmtoll WD_TH ADC_WD_TH_WD_LT LL_ADC_ConfigureAWDThresholds\n + * WD_TH ADC_WD_TH_WD_HT LL_ADC_ConfigureAWDThresholds * @param ADCx ADC instance * @param LowThreshold This parameter is a 12-bit value. * @param HighThreshold This parameter is a 12-bit value. diff --git a/stm32cube/stm32wb0x/drivers/include/stm32wb0x_ll_lpuart.h b/stm32cube/stm32wb0x/drivers/include/stm32wb0x_ll_lpuart.h index 87c7c67e9..77eb1e67f 100644 --- a/stm32cube/stm32wb0x/drivers/include/stm32wb0x_ll_lpuart.h +++ b/stm32cube/stm32wb0x/drivers/include/stm32wb0x_ll_lpuart.h @@ -56,6 +56,10 @@ static const uint16_t LPUART_PRESCALER_TAB[] = (uint16_t)32, (uint16_t)64, (uint16_t)128, + (uint16_t)256, + (uint16_t)256, + (uint16_t)256, + (uint16_t)256, (uint16_t)256 }; /** diff --git a/stm32cube/stm32wb0x/drivers/include/stm32wb0x_ll_pka.h b/stm32cube/stm32wb0x/drivers/include/stm32wb0x_ll_pka.h index 047db024e..d5eea192d 100644 --- a/stm32cube/stm32wb0x/drivers/include/stm32wb0x_ll_pka.h +++ b/stm32cube/stm32wb0x/drivers/include/stm32wb0x_ll_pka.h @@ -1,6 +1,6 @@ /** ****************************************************************************** - * @filestm32wb0x_ll_pka.h + * @file stm32wb0x_ll_pka.h * @author MCD Application Team * @brief Header file of PKA LL module. ****************************************************************************** diff --git a/stm32cube/stm32wb0x/drivers/include/stm32wb0x_ll_rcc.h b/stm32cube/stm32wb0x/drivers/include/stm32wb0x_ll_rcc.h index b41529d4d..1a7987cf4 100644 --- a/stm32cube/stm32wb0x/drivers/include/stm32wb0x_ll_rcc.h +++ b/stm32cube/stm32wb0x/drivers/include/stm32wb0x_ll_rcc.h @@ -1459,6 +1459,43 @@ __STATIC_INLINE uint32_t LL_RCC_GetSPI3I2SClockSource(void) * @} */ +/** @defgroup RCC_LL_EF_RTC RTC + * @{ + */ + +/** + * @brief Enable RTC + * @rmtoll APB0ENR RTCEN LL_RCC_EnableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableRTC(void) +{ + SET_BIT(RCC->APB0ENR, RCC_APB0ENR_RTCEN); +} + +/** + * @brief Disable RTC + * @rmtoll APB0ENR RTCEN LL_RCC_DisableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableRTC(void) +{ + CLEAR_BIT(RCC->APB0ENR, RCC_APB0ENR_RTCEN); +} + +/** + * @brief Check if RTC has been enabled or not + * @rmtoll APB0ENR RTCEN LL_RCC_IsEnabledRTC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) +{ + return ((READ_BIT(RCC->APB0ENR, RCC_APB0ENR_RTCEN) == (RCC_APB0ENR_RTCEN)) ? 1UL : 0UL); +} + +/** + * @} + */ /** @defgroup RCC_LL_EF_PLL PLL * @{ @@ -1787,7 +1824,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPURSTREL(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LOCKUPRST(void) { - return ((READ_BIT(RCC->CSR, RCC_CSR_LOCKUPRSTF) == (RCC_CSR_LOCKUPRSTF)) ? 1UL : 0UL); + return (((RAM_VR.ResetReason & LL_RCC_CSR_LOCKUPRSTF) == LL_RCC_CSR_LOCKUPRSTF) ? 1UL : 0UL); } /** @@ -1797,7 +1834,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LOCKUPRST(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WDGRST(void) { - return ((READ_BIT(RCC->CSR, RCC_CSR_WDGRSTF) == (RCC_CSR_WDGRSTF)) ? 1UL : 0UL); + return (((RAM_VR.ResetReason & LL_RCC_CSR_WDGRSTF) == LL_RCC_CSR_WDGRSTF) ? 1UL : 0UL); } /** @@ -1807,7 +1844,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WDGRST(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) { - return ((READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)) ? 1UL : 0UL); + return (((RAM_VR.ResetReason & LL_RCC_CSR_SFTRSTF) == LL_RCC_CSR_SFTRSTF) ? 1UL : 0UL); } /** @@ -1817,7 +1854,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void) { - return ((READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF)) ? 1UL : 0UL); + return (((RAM_VR.ResetReason & LL_RCC_CSR_PORRSTF) == LL_RCC_CSR_PORRSTF) ? 1UL : 0UL); } /** @@ -1827,17 +1864,16 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PADRST(void) { - return ((READ_BIT(RCC->CSR, RCC_CSR_PADRSTF) == (RCC_CSR_PADRSTF)) ? 1UL : 0UL); + return (((RAM_VR.ResetReason & LL_RCC_CSR_PADRSTF) == LL_RCC_CSR_PADRSTF) ? 1UL : 0UL); } /** - * @brief Set RMVF bit to clear the reset flags. - * @rmtoll CSR RMVF LL_RCC_ClearResetFlags + * @brief Clear all reset flags. * @retval None */ __STATIC_INLINE void LL_RCC_ClearResetFlags(void) { - WRITE_REG(RCC->CSR, RCC_CSR_RMVF); + RAM_VR.ResetReason = 0; } /** diff --git a/stm32cube/stm32wb0x/drivers/include/stm32wb0x_ll_rng.h b/stm32cube/stm32wb0x/drivers/include/stm32wb0x_ll_rng.h index e4ad0cb44..379539ff0 100644 --- a/stm32cube/stm32wb0x/drivers/include/stm32wb0x_ll_rng.h +++ b/stm32cube/stm32wb0x/drivers/include/stm32wb0x_ll_rng.h @@ -677,35 +677,6 @@ __STATIC_INLINE uint32_t LL_RNG_GetSamplingClockEnableDivider(RNG_TypeDef *RNGx) return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_CLKDIV_15_0) >> RNG_CR_CLKDIV_15_0_Pos); } -/** - * @brief Set the random raw values from the random sources - * @note Available only in test mode for analog characterization where tst_bypass_ana_i input of the IP is - set to 10x0 Post processing is used0x1 Post processing is bypassed - * @rmtoll CR BP_POSTP LL_RNG_SetBypassOfPostProcessing - * @param RNGx RNG Instance - * @param value can be one of the following values: - * @arg LL_RNG_CR_BP_POSTP_0 - * @arg LL_RNG_CR_BP_POSTP_1 - * @retval None - */ -__STATIC_INLINE void LL_RNG_SetBypassOfPostProcessing(RNG_TypeDef *RNGx, uint32_t value) -{ - MODIFY_REG(RNGx->CR, RNG_CR_BP_POSTP, value); -} - -/** - * @brief Get the random raw values from the random sources - * @note Available only in test mode for analog characterization where tst_bypass_ana_i input of the IP is - set to 10x0 Post processing is used0x1 Post processing is bypassed - * @rmtoll CR BP_POSTP LL_RNG_GetBypassOfPostProcessing - * @retval can be one of the following values - * @arg LL_RNG_CR_BP_POSTP_0 - * @arg LL_RNG_CR_BP_POSTP_1 - */ -__STATIC_INLINE uint32_t LL_RNG_GetBypassOfPostProcessing(RNG_TypeDef *RNGx) -{ - return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_BP_POSTP)); -} /** * @brief Indicate if DISABLED value Flag is set or not. @@ -1870,6 +1841,39 @@ __STATIC_INLINE uint32_t LL_RNG_GetErrorIrq(RNG_TypeDef *RNGx) return (uint32_t)(READ_BIT(RNGx->IRQ_SR, RNG_IRQ_SR_ERROR_IRQ)); } +/** + * @brief Clear the FF_FULL_IRQ flag + * @note Flag is cleared by writing a 1 + * @rmtoll IRQ_SR FF_FULL_IRQ LL_RNG_ClearFfFullIrq + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_ClearFfFullIrq(RNG_TypeDef *RNGx) +{ + SET_BIT(RNGx->IRQ_SR, RNG_IRQ_SR_FF_FULL_IRQ); +} +/** + * @brief Clear the ERROR_IRQ flag + * @note Flag is cleared by writing a 1 + * @rmtoll IRQ_SR ERROR_IRQ LL_RNG_ClearErrorIrq + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_ClearErrorIrq(RNG_TypeDef *RNGx) +{ + SET_BIT(RNGx->IRQ_SR, RNG_IRQ_SR_ERROR_IRQ); +} +/** + * @brief Check if Random Number Generator is enabled + * @rmtoll CR RNG_DIS LL_RNG_IsEnabled + * @param RNGx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsEnabled(RNG_TypeDef *RNGx) +{ + return ((READ_BIT(RNGx->CR, RNG_CR_DISABLE) != (RNG_CR_DISABLE)) ? 1UL : 0UL); +} + #if defined(USE_FULL_LL_DRIVER) /** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions * @{ diff --git a/stm32cube/stm32wb0x/drivers/include/stm32wb0x_ll_spi.h b/stm32cube/stm32wb0x/drivers/include/stm32wb0x_ll_spi.h index 322db50e6..bc72f8c0b 100644 --- a/stm32cube/stm32wb0x/drivers/include/stm32wb0x_ll_spi.h +++ b/stm32cube/stm32wb0x/drivers/include/stm32wb0x_ll_spi.h @@ -55,53 +55,66 @@ typedef struct uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode. This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetTransferDirection().*/ uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave). This parameter can be a value of @ref SPI_LL_EC_MODE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetMode().*/ uint32_t DataWidth; /*!< Specifies the SPI data width. This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetDataWidth().*/ uint32_t ClockPolarity; /*!< Specifies the serial clock steady state. This parameter can be a value of @ref SPI_LL_EC_POLARITY. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetClockPolarity().*/ uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture. This parameter can be a value of @ref SPI_LL_EC_PHASE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetClockPhase().*/ - uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. + uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) + or by software using the SSI bit. This parameter can be a value of @ref SPI_LL_EC_NSS_MODE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetNSSMode().*/ - uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock. + uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used + to configure the transmit and receive SCK clock. This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER. - @note The communication clock is derived from the master clock. The slave clock does not need to be set. + @note The communication clock is derived from the master clock. + The slave clock does not need to be set. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetBaudRatePrescaler().*/ uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit. This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetTransferBitOrder().*/ uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION. - This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/ + This feature can be modified afterwards using unitary + functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/ uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetCRCPolynomial().*/ } LL_SPI_InitTypeDef; @@ -378,7 +391,7 @@ __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabled(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL); } @@ -408,7 +421,7 @@ __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode) * @arg @ref LL_SPI_MODE_MASTER * @arg @ref LL_SPI_MODE_SLAVE */ -__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetMode(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI)); } @@ -436,7 +449,7 @@ __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) * @arg @ref LL_SPI_PROTOCOL_MOTOROLA * @arg @ref LL_SPI_PROTOCOL_TI */ -__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetStandard(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF)); } @@ -465,7 +478,7 @@ __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase * @arg @ref LL_SPI_PHASE_1EDGE * @arg @ref LL_SPI_PHASE_2EDGE */ -__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA)); } @@ -494,7 +507,7 @@ __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPo * @arg @ref LL_SPI_POLARITY_LOW * @arg @ref LL_SPI_POLARITY_HIGH */ -__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL)); } @@ -534,7 +547,7 @@ __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t Bau * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 */ -__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR)); } @@ -562,7 +575,7 @@ __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitO * @arg @ref LL_SPI_LSB_FIRST * @arg @ref LL_SPI_MSB_FIRST */ -__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST)); } @@ -599,7 +612,7 @@ __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t Tra * @arg @ref LL_SPI_HALF_DUPLEX_RX * @arg @ref LL_SPI_HALF_DUPLEX_TX */ -__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)); } @@ -648,7 +661,7 @@ __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth) * @arg @ref LL_SPI_DATAWIDTH_15BIT * @arg @ref LL_SPI_DATAWIDTH_16BIT */ -__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS)); } @@ -675,7 +688,7 @@ __STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Thres * @arg @ref LL_SPI_RX_FIFO_TH_HALF * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER */ -__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH)); } @@ -719,7 +732,7 @@ __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL); } @@ -747,7 +760,7 @@ __STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength) * @arg @ref LL_SPI_CRC_8BIT * @arg @ref LL_SPI_CRC_16BIT */ -__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL)); } @@ -782,7 +795,7 @@ __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly * @param SPIx SPI Instance * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF */ -__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_REG(SPIx->CRCPR)); } @@ -793,7 +806,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF */ -__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_REG(SPIx->RXCRCR)); } @@ -804,7 +817,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF */ -__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_REG(SPIx->TXCRCR)); } @@ -845,7 +858,7 @@ __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS) * @arg @ref LL_SPI_NSS_HARD_INPUT * @arg @ref LL_SPI_NSS_HARD_OUTPUT */ -__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(const SPI_TypeDef *SPIx) { uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM)); uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U); @@ -883,7 +896,7 @@ __STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP)) ? 1UL : 0UL); } @@ -902,7 +915,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL); } @@ -913,7 +926,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL); } @@ -924,7 +937,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL); } @@ -935,7 +948,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL); } @@ -946,7 +959,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL); } @@ -964,7 +977,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL); } @@ -975,7 +988,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL); } @@ -990,7 +1003,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx) * @arg @ref LL_SPI_RX_FIFO_HALF_FULL * @arg @ref LL_SPI_RX_FIFO_FULL */ -__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL)); } @@ -1005,7 +1018,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx) * @arg @ref LL_SPI_TX_FIFO_HALF_FULL * @arg @ref LL_SPI_TX_FIFO_FULL */ -__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL)); } @@ -1045,7 +1058,7 @@ __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval None */ -__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx) +__STATIC_INLINE void LL_SPI_ClearFlag_OVR(const SPI_TypeDef *SPIx) { __IO uint32_t tmpreg; tmpreg = SPIx->DR; @@ -1061,7 +1074,7 @@ __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval None */ -__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx) +__STATIC_INLINE void LL_SPI_ClearFlag_FRE(const SPI_TypeDef *SPIx) { __IO uint32_t tmpreg; tmpreg = SPIx->SR; @@ -1078,7 +1091,8 @@ __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx) /** * @brief Enable error interrupt - * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). + * @note This bit controls the generation of an interrupt when an error condition + * occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR * @param SPIx SPI Instance * @retval None @@ -1112,7 +1126,8 @@ __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx) /** * @brief Disable error interrupt - * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). + * @note This bit controls the generation of an interrupt when an error condition + * occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR * @param SPIx SPI Instance * @retval None @@ -1150,7 +1165,7 @@ __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL); } @@ -1161,7 +1176,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL); } @@ -1172,7 +1187,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL); } @@ -1213,7 +1228,7 @@ __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL); } @@ -1246,7 +1261,7 @@ __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL); } @@ -1273,7 +1288,7 @@ __STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity) * @arg @ref LL_SPI_DMA_PARITY_ODD * @arg @ref LL_SPI_DMA_PARITY_EVEN */ -__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos); } @@ -1300,7 +1315,7 @@ __STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity) * @arg @ref LL_SPI_DMA_PARITY_ODD * @arg @ref LL_SPI_DMA_PARITY_EVEN */ -__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos); } @@ -1311,7 +1326,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval Address of data register */ -__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(const SPI_TypeDef *SPIx) { return (uint32_t) &(SPIx->DR); } @@ -1388,7 +1403,7 @@ __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) * @{ */ -ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx); +ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx); ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct); void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct); @@ -1655,7 +1670,7 @@ __STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabled(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE)) ? 1UL : 0UL); } @@ -1688,7 +1703,7 @@ __STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat * @arg @ref LL_I2S_DATAFORMAT_24B * @arg @ref LL_I2S_DATAFORMAT_32B */ -__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)); } @@ -1715,7 +1730,7 @@ __STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPo * @arg @ref LL_I2S_POLARITY_LOW * @arg @ref LL_I2S_POLARITY_HIGH */ -__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL)); } @@ -1750,7 +1765,7 @@ __STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) * @arg @ref LL_I2S_STANDARD_PCM_SHORT * @arg @ref LL_I2S_STANDARD_PCM_LONG */ -__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_GetStandard(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC)); } @@ -1781,7 +1796,7 @@ __STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode) * @arg @ref LL_I2S_MODE_MASTER_TX * @arg @ref LL_I2S_MODE_MASTER_RX */ -__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG)); } @@ -1804,7 +1819,7 @@ __STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t Presca * @param SPIx SPI Instance * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV)); } @@ -1831,7 +1846,7 @@ __STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t Presc * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN * @arg @ref LL_I2S_PRESCALER_PARITY_ODD */ -__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U); } @@ -1864,7 +1879,7 @@ __STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE)) ? 1UL : 0UL); } @@ -1898,7 +1913,7 @@ __STATIC_INLINE void LL_I2S_DisableAsyncStart(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN) == (SPI_I2SCFGR_ASTRTEN)) ? 1UL : 0UL); } @@ -1918,7 +1933,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(const SPI_TypeDef *SPIx) { return LL_SPI_IsActiveFlag_RXNE(SPIx); } @@ -1929,7 +1944,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(const SPI_TypeDef *SPIx) { return LL_SPI_IsActiveFlag_TXE(SPIx); } @@ -1940,7 +1955,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(const SPI_TypeDef *SPIx) { return LL_SPI_IsActiveFlag_BSY(SPIx); } @@ -1951,7 +1966,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(const SPI_TypeDef *SPIx) { return LL_SPI_IsActiveFlag_OVR(SPIx); } @@ -1962,7 +1977,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL); } @@ -1973,7 +1988,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(const SPI_TypeDef *SPIx) { return LL_SPI_IsActiveFlag_FRE(SPIx); } @@ -1987,7 +2002,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE)) ? 1UL : 0UL); } @@ -2009,7 +2024,7 @@ __STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval None */ -__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx) +__STATIC_INLINE void LL_I2S_ClearFlag_UDR(const SPI_TypeDef *SPIx) { __IO uint32_t tmpreg; tmpreg = SPIx->SR; @@ -2022,7 +2037,7 @@ __STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval None */ -__STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx) +__STATIC_INLINE void LL_I2S_ClearFlag_FRE(const SPI_TypeDef *SPIx) { LL_SPI_ClearFlag_FRE(SPIx); } @@ -2109,7 +2124,7 @@ __STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(const SPI_TypeDef *SPIx) { return LL_SPI_IsEnabledIT_ERR(SPIx); } @@ -2120,7 +2135,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(const SPI_TypeDef *SPIx) { return LL_SPI_IsEnabledIT_RXNE(SPIx); } @@ -2131,7 +2146,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(const SPI_TypeDef *SPIx) { return LL_SPI_IsEnabledIT_TXE(SPIx); } @@ -2172,7 +2187,7 @@ __STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx) { return LL_SPI_IsEnabledDMAReq_RX(SPIx); } @@ -2205,7 +2220,7 @@ __STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx) { return LL_SPI_IsEnabledDMAReq_TX(SPIx); } @@ -2250,7 +2265,7 @@ __STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) * @{ */ -ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx); +ErrorStatus LL_I2S_DeInit(const SPI_TypeDef *SPIx); ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct); void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct); void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity); diff --git a/stm32cube/stm32wb0x/drivers/include/stm32wb0x_ll_system.h b/stm32cube/stm32wb0x/drivers/include/stm32wb0x_ll_system.h index 0a53a5ff9..5811be123 100644 --- a/stm32cube/stm32wb0x/drivers/include/stm32wb0x_ll_system.h +++ b/stm32cube/stm32wb0x/drivers/include/stm32wb0x_ll_system.h @@ -182,6 +182,18 @@ typedef struct */ #define LL_FLASH_WAIT_STATES_0 0x00000000U /*!< FLASH Zero wait state */ #define LL_FLASH_WAIT_STATES_1 FLASH_CONFIG_WAIT_STATES_0 /*!< FLASH One wait state */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_FLASH_FLAGS FLASH Flags Definition + * @{ + */ +#define LL_FLASH_FLAG_CMDDONE FLASH_IRQRAW_CMDDONE_RIS /*!< FLASH command done flag */ +#define LL_FLASH_FLAG_CMDSTART FLASH_IRQRAW_CMDSTART_RIS /*!< FLASH command started flag */ +#define LL_FLASH_FLAG_CMDERR FLASH_IRQRAW_CMDERR_RIS /*!< FLASH command error flag */ +#define LL_FLASH_FLAG_ILLCMD FLASH_IRQRAW_ILLCMD_RIS /*!< FLASH illegal command flag */ + /** * @} */ @@ -1378,10 +1390,10 @@ __STATIC_INLINE void LL_FLASH_DisableIT(FLASH_TypeDef *FLASHx, uint32_t interrup * @param FLASHx FLASH Instance * @param interrupt FLASH interrupt * This parameter can be any combination of the following values: - * @arg @ref FLASH_IT_CMDDONE Command Done Interrupt - * @arg @ref FLASH_IT_CMDSTART Command Started Interrupt - * @arg @ref FLASH_IT_CMDERR Command Error Interrupt - * @arg @ref FLASH_IT_ILLCMD Illegal Command Interrupt + * @arg @ref LL_FLASH_IT_CMDDONE Command Done Interrupt + * @arg @ref LL_FLASH_IT_CMDSTART Command Started Interrupt + * @arg @ref LL_FLASH_IT_CMDERR Command Error Interrupt + * @arg @ref LL_FLASH_IT_ILLCMD Illegal Command Interrupt * @retval The new state of interrupt flag (SET or RESET). */ __STATIC_INLINE uint32_t LL_FLASH_GetIT(FLASH_TypeDef *FLASHx, uint32_t interrupt) @@ -1394,10 +1406,10 @@ __STATIC_INLINE uint32_t LL_FLASH_GetIT(FLASH_TypeDef *FLASHx, uint32_t interrup * @param FLASHx FLASH Instance * @param interrupt FLASH interrupt * This parameter can be any combination of the following values: - * @arg @ref FLASH_IT_CMDDONE Command Done Interrupt - * @arg @ref FLASH_IT_CMDSTART Command Started Interrupt - * @arg @ref FLASH_IT_CMDERR Command Error Interrupt - * @arg @ref FLASH_IT_ILLCMD Illegal Command Interrupt + * @arg @ref LL_FLASH_IT_CMDDONE Command Done Interrupt + * @arg @ref LL_FLASH_IT_CMDSTART Command Started Interrupt + * @arg @ref LL_FLASH_IT_CMDERR Command Error Interrupt + * @arg @ref LL_FLASH_IT_ILLCMD Illegal Command Interrupt * @retval None */ __STATIC_INLINE void LL_FLASH_ClearIT(FLASH_TypeDef *FLASHx, uint32_t interrupt) diff --git a/stm32cube/stm32wb0x/drivers/include/stm32wb0x_ll_usart.h b/stm32cube/stm32wb0x/drivers/include/stm32wb0x_ll_usart.h index e6c994f36..d21a32e86 100644 --- a/stm32cube/stm32wb0x/drivers/include/stm32wb0x_ll_usart.h +++ b/stm32cube/stm32wb0x/drivers/include/stm32wb0x_ll_usart.h @@ -56,6 +56,10 @@ static const uint32_t USART_PRESCALER_TAB[] = 32UL, 64UL, 128UL, + 256UL, + 256UL, + 256UL, + 256UL, 256UL }; /** diff --git a/stm32cube/stm32wb0x/drivers/include/stm32wb0x_ll_utils.h b/stm32cube/stm32wb0x/drivers/include/stm32wb0x_ll_utils.h index dd51863af..1f6f452a7 100644 --- a/stm32cube/stm32wb0x/drivers/include/stm32wb0x_ll_utils.h +++ b/stm32cube/stm32wb0x/drivers/include/stm32wb0x_ll_utils.h @@ -228,7 +228,7 @@ __STATIC_INLINE uint32_t LL_GetFlashSize(void) */ __STATIC_INLINE uint32_t LL_GetPackageType(void) { - return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x1FU); + return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS))); } /** diff --git a/stm32cube/stm32wb0x/drivers/src/stm32wb0x_hal_adc.c b/stm32cube/stm32wb0x/drivers/src/stm32wb0x_hal_adc.c index faa575652..670dbf16a 100644 --- a/stm32cube/stm32wb0x/drivers/src/stm32wb0x_hal_adc.c +++ b/stm32cube/stm32wb0x/drivers/src/stm32wb0x_hal_adc.c @@ -153,7 +153,7 @@ while off-loading the CPU (ratio adjustable from 1 to 128). (#) Disable the ADC interface (++) ADC clock can be hard reset and disabled at RCC top level. (++) Hard reset of ADC peripherals - using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET(). + using macro __HAL_RCC_ADC_FORCE_RESET(), __HAL_RCC_ADC_RELEASE_RESET(). (++) ADC clock disable using the equivalent macro/functions as configuration step. (+++) Example: @@ -165,13 +165,13 @@ while off-loading the CPU (ratio adjustable from 1 to 128). (#) Optionally, in case of usage of ADC with interruptions: (++) Disable the NVIC for ADC - using function HAL_NVIC_EnableIRQ(ADCx_IRQn) + using function HAL_NVIC_DisableIRQ(ADCx_IRQn) (#) Optionally, in case of usage of DMA: (++) Deinitialize the DMA - using function HAL_DMA_Init(). + using function HAL_DMA_DeInit(). (++) Disable the NVIC for DMA - using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) + using function HAL_NVIC_DisableIRQ(DMAx_Channelx_IRQn) [..] @@ -2212,7 +2212,11 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_Chann if (LL_ADC_IsConversionOngoing(hadc->Instance) == 0UL) { LL_ADC_SetSequencerRanks(hadc->Instance, sConfigChannel->Rank, sConfigChannel->Channel); - LL_ADC_SetChannelVoltageRange(hadc->Instance, sConfigChannel->Channel, sConfigChannel->VoltRange); + if ((sConfigChannel->Channel != ADC_CHANNEL_TEMPSENSOR) + && (sConfigChannel->Channel != ADC_CHANNEL_VBAT)) + { + LL_ADC_SetChannelVoltageRange(hadc->Instance, sConfigChannel->Channel, sConfigChannel->VoltRange); + } } /* If a conversion is on going no update could be done on */ /* neither of the channel configuration structure parameters. */ @@ -2233,7 +2237,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_Chann else if ((sConfigChannel->VoltRange == ADC_VIN_RANGE_1V2) || (sConfigChannel->Channel == ADC_CHANNEL_TEMPSENSOR)) { - /* 1.2V mode: [calibrated gain =0.96, gain clamped at 1] */ + /* 1.2V mode: [calibrated gain = 0.96, gain clamped at 1] */ tmp_gain = 0xFFFUL; } else if (sConfigChannel->VoltRange == ADC_VIN_RANGE_2V4) diff --git a/stm32cube/stm32wb0x/drivers/src/stm32wb0x_hal_gpio.c b/stm32cube/stm32wb0x/drivers/src/stm32wb0x_hal_gpio.c index 1023f618c..5a91ceae4 100644 --- a/stm32cube/stm32wb0x/drivers/src/stm32wb0x_hal_gpio.c +++ b/stm32cube/stm32wb0x/drivers/src/stm32wb0x_hal_gpio.c @@ -348,11 +348,11 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) tmp = SYSCFG->IO_IER; if(GPIOx == GPIOA) { - tmp = ~(1<IO_IER = tmp; @@ -360,22 +360,22 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) tmp = SYSCFG->IO_DTR; if(GPIOx == GPIOA) { - tmp = ~(1<IO_DTR = tmp; tmp = SYSCFG->IO_IBER; if(GPIOx == GPIOA) { - tmp = ~(1<IO_IBER = tmp; @@ -383,11 +383,11 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) tmp = SYSCFG->IO_IEVR; if(GPIOx == GPIOA) { - tmp = ~(1<IO_IEVR = tmp; diff --git a/stm32cube/stm32wb0x/drivers/src/stm32wb0x_hal_i2c.c b/stm32cube/stm32wb0x/drivers/src/stm32wb0x_hal_i2c.c index f0b3a666b..afb424583 100644 --- a/stm32cube/stm32wb0x/drivers/src/stm32wb0x_hal_i2c.c +++ b/stm32cube/stm32wb0x/drivers/src/stm32wb0x_hal_i2c.c @@ -3277,6 +3277,8 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd __IO uint32_t I2C_Trials = 0UL; + HAL_StatusTypeDef status = HAL_OK; + FlagStatus tmp1; FlagStatus tmp2; @@ -3334,37 +3336,64 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Wait until STOPF flag is reset */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { - return HAL_ERROR; + /* A non acknowledge appear during STOP Flag waiting process, a new trial must be performed */ + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Reset the error code for next trial */ + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } + else + { + status = HAL_ERROR; + } } + else + { + /* A acknowledge appear during STOP Flag waiting process, this mean that device respond to its address */ - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - /* Device is ready */ - hi2c->State = HAL_I2C_STATE_READY; + /* Device is ready */ + hi2c->State = HAL_I2C_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_OK; + return HAL_OK; + } } else { - /* Wait until STOPF flag is reset */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } + /* A non acknowledge is detected, this mean that device not respond to its address, + a new trial must be performed */ /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - /* Clear STOP Flag, auto generated with autoend*/ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + { + status = HAL_ERROR; + } + else + { + /* Clear STOP Flag, auto generated with autoend*/ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } } /* Increment Trials */ I2C_Trials++; + + if ((I2C_Trials < Trials) && (status == HAL_ERROR)) + { + status = HAL_OK; + } + } while (I2C_Trials < Trials); /* Update I2C state */ @@ -6377,7 +6406,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) /* Increment Buffer pointer */ hi2c->pBuffPtr++; - if ((hi2c->XferSize > 0U)) + if (hi2c->XferSize > 0U) { hi2c->XferSize--; hi2c->XferCount--; @@ -6533,7 +6562,7 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) /* Increment Buffer pointer */ hi2c->pBuffPtr++; - if ((hi2c->XferSize > 0U)) + if (hi2c->XferSize > 0U) { hi2c->XferSize--; hi2c->XferCount--; @@ -6987,7 +7016,7 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)) + if (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State = HAL_I2C_STATE_READY; @@ -7027,7 +7056,7 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State = HAL_I2C_STATE_READY; @@ -7066,7 +7095,7 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Check for the Timeout */ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State = HAL_I2C_STATE_READY; @@ -7144,7 +7173,7 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Check for the Timeout */ if ((((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) && (status == HAL_OK)) { - if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State = HAL_I2C_STATE_READY; @@ -7311,15 +7340,17 @@ static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t T static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) { + uint32_t tmp; + /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_TRANSFER_MODE(Mode)); assert_param(IS_TRANSFER_REQUEST(Request)); /* Declaration of tmp to prevent undefined behavior of volatile usage */ - uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ - (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ - (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); + tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ + (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); /* update CR2 register */ MODIFY_REG(hi2c->Instance->CR2, \ diff --git a/stm32cube/stm32wb0x/drivers/src/stm32wb0x_hal_i2s.c b/stm32cube/stm32wb0x/drivers/src/stm32wb0x_hal_i2s.c index 3f8e92701..8af7a01c2 100644 --- a/stm32cube/stm32wb0x/drivers/src/stm32wb0x_hal_i2s.c +++ b/stm32cube/stm32wb0x/drivers/src/stm32wb0x_hal_i2s.c @@ -1615,7 +1615,7 @@ __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s) * the configuration information for I2S module * @retval HAL state */ -HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s) +HAL_I2S_StateTypeDef HAL_I2S_GetState(const I2S_HandleTypeDef *hi2s) { return hi2s->State; } @@ -1626,7 +1626,7 @@ HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s) * the configuration information for I2S module * @retval I2S Error Code */ -uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s) +uint32_t HAL_I2S_GetError(const I2S_HandleTypeDef *hi2s) { return hi2s->ErrorCode; } diff --git a/stm32cube/stm32wb0x/drivers/src/stm32wb0x_hal_radio.c b/stm32cube/stm32wb0x/drivers/src/stm32wb0x_hal_radio.c index ae36e1a95..0eb261482 100644 --- a/stm32cube/stm32wb0x/drivers/src/stm32wb0x_hal_radio.c +++ b/stm32cube/stm32wb0x/drivers/src/stm32wb0x_hal_radio.c @@ -1,6 +1,6 @@ /** ****************************************************************************** - * @file stm32wb0x_hal_radio.h + * @file stm32wb0x_hal_radio.c * @author GPM WBL Application Team * @brief This file provides all the Radio Driver APIs. ****************************************************************************** @@ -70,11 +70,6 @@ * @{ */ -/* initDelay */ -#define INITDELAY_WAKEUP (0x40U) -#define INITDELAY_TIMER12_CAL (0x3FU) -#define INITDELAY_TIMER2_NOCAL (0x9U) - /* Init_radio_delay */ #if defined (STM32WB05) || defined(STM32WB09 ) #define DELAYCHK_TRANSMIT_CAL (0x5AU) @@ -102,8 +97,6 @@ #if defined (STM32WB06) || defined(STM32WB07) #define TXREADY_TIMEOUT (0x5U) #endif -#define TXDELAY_START (0x10U) -#define TXDELAY_END (0x10U) /* RX parameter init */ #define RCV_TIMEOUT (0x100) @@ -204,17 +197,11 @@ static uint8_t CondRoutineRxTrue(ActionPacket *p) /* Round up HOT_TABLE_SIZE to an integer number of words then add 4 words for table management pointers */ volatile uint32_t hot_table_radio_config_u32[((HOT_TABLE_SIZE + 3) >> 2) + 4] = {0x00}; -#if 0 /** PATCH: do not define __blue_RAM here */ +#ifndef __ZEPHYR__ /** do not define __blue_RAM here, it is defined in Zephyr wtm32wb0x/soc.c */ /* BLUE RAM, reserved for radio communication. Not usable from the application */ __SECTION(".bss.__blue_RAM") -#if defined(STM32WB05) || defined(STM32WB09) -__REQUIRED(uint8_t __blue_RAM[CFG_NUM_RADIO_TASKS * 92 + 28]) = {0,}; -#elif defined(STM32WB06) || defined (STM32WB07) -__REQUIRED(uint8_t __blue_RAM[CFG_NUM_RADIO_TASKS * 80 + 28]) = {0,}; -#else -#warning "No Blue RAM allocated" -#endif -#endif /* ENDOF PATCH */ +__REQUIRED(uint8_t __blue_RAM[CFG_NUM_RADIO_TASKS * sizeof(STATMACH_TypeDef) + sizeof(GLOBALSTATMACH_TypeDef)]) = {0,}; +#endif /* __ZEPHYR__ */ /** * @} @@ -306,9 +293,9 @@ void HAL_RADIO_Init(RADIO_HandleTypeDef *hradio) #endif /* STM32WB05 or STM32WB09 */ /*Set InitDelay*/ - LL_RADIO_SetWakeupInitDelay(INITDELAY_WAKEUP); - LL_RADIO_SetTimer12InitDelayCal(INITDELAY_TIMER12_CAL); - LL_RADIO_SetTimer12InitDelayNoCal(INITDELAY_TIMER2_NOCAL); + LL_RADIO_SetWakeupInitDelay(RADIO_INITDELAY_WAKEUP); + LL_RADIO_SetTimer12InitDelayCal(RADIO_INITDELAY_TIMER12_CAL); + LL_RADIO_SetTimer12InitDelayNoCal(RADIO_INITDELAY_TIMER2_NOCAL); /*Set Init_radio_delay*/ LL_RADIO_SetReceivedCalDelayChk(DELAYCHK_RECEIVE_CAL); @@ -319,8 +306,8 @@ void HAL_RADIO_Init(RADIO_HandleTypeDef *hradio) /* Initial and final TX delays: control the on-air start time of the TX packet * and the length of the packet "tail" after last bit is transmitted */ - LL_RADIO_SetTxDelayStart(TXDELAY_START); - LL_RADIO_SetTxDelayEnd(TXDELAY_END); + LL_RADIO_SetTxDelayStart(RADIO_TXDELAY_START); + LL_RADIO_SetTxDelayEnd(RADIO_TXDELAY_END); /* Timeout for TX ready signal from the radio FSM after the 2nd init phase * has expired @@ -344,7 +331,7 @@ void HAL_RADIO_Init(RADIO_HandleTypeDef *hradio) #endif /* The commands in the hot table start at word 4 - * The words 0 t0 2 are used to point to the command list + * The words 0 to 2 are used to point to the command list * for the various trigger events, word 3 is a null command * (see function BLEPLAT_CNTR_SetRadioConfigData) */ @@ -398,9 +385,12 @@ void HAL_RADIO_Init(RADIO_HandleTypeDef *hradio) LL_RADIO_SetRadioConfigurationAddressPointer(hot_table_radio_config_u32[0]); /* Reload radio config pointer */ - *(uint32_t *)(RRM_BASE + 0x10U) = 0x01U; + RRM->UDRA_CTRL0 = RRM_UDRA_CTRL0_RELOAD_RDCFGPTR; LL_RADIO_Active2ErrorInterrupt_Enable(); + /* Enable RRM Port Grant interrupt */ + SET_BIT(RRM->BLE_IRQ_ENABLE, RRM_BLE_IRQ_ENABLE_PORT_GRANT); + #if USE_RADIO_PROPRIETARY_DRIVER globalParameters.back2backTime = BACK_TO_BACK_TIME; globalParameters.tone_start_stop_flag = 0; @@ -548,6 +538,7 @@ static void HAL_RADIO_ActionPacketIsr(uint32_t int_flags) LL_RADIO_TIMER_DisableTimer2(BLUE); LL_RADIO_TIMER_DisableBLEWakeupTimer(WAKEUP); MODIFY_REG(BLUEGLOB->BYTE4, GLOBAL_BYTE4_ACTIVE_Msk, BLUE_IDLE_0); + HAL_RADIO_TIMER_ClearRadioTimerValue(); } else { @@ -611,39 +602,6 @@ static void HAL_RADIO_ActionPacketIsr(uint32_t int_flags) return ; } -/** - * @brief RADIO MSP Init - * @param hradio pointer to a RADIO_HandleTypeDef structure that contains - * the configuration information for RADIO module - * @retval None - */ -__weak void HAL_RADIO_MspInit(RADIO_HandleTypeDef *hradio) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hradio); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_I2S_MspInit could be implemented in the user file - */ -} - -/** - * @brief RADIO MSP DeInit - * @param hradio pointer to a RADIO_HandleTypeDef structure that contains - * the configuration information for RADIO module - * @retval None - */ -__weak void HAL_RADIO_MspDeInit(RADIO_HandleTypeDef *hradio) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hradio); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RADIO_MspDeInit could be implemented in the user file - */ -} - - /** * @brief This routine force the radio to be stopped. After calling this function, * the ISR is not triggered unless, "MakeActionPacketPending" API called again. @@ -1754,10 +1712,45 @@ uint8_t HAL_RADIO_ReceivePacketWithAck(uint8_t channel, uint32_t wakeup_time, ui #endif /* USE_RADIO_PROPRIETARY_DRIVER */ +/** + * @brief RADIO MSP Init + * @param hradio pointer to a RADIO_HandleTypeDef structure that contains + * the configuration information for RADIO module + * @retval None + */ +__weak void HAL_RADIO_MspInit(RADIO_HandleTypeDef *hradio) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hradio); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RADIO_MspInit could be implemented in the user file + */ +} + +/** + * @brief RADIO MSP DeInit + * @param hradio pointer to a RADIO_HandleTypeDef structure that contains + * the configuration information for RADIO module + * @retval None + */ +__weak void HAL_RADIO_MspDeInit(RADIO_HandleTypeDef *hradio) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hradio); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RADIO_MspDeInit could be implemented in the user file + */ +} + __weak void HAL_RADIO_TxRxCallback(uint32_t flags) { } +__weak void HAL_RADIO_RRMCallback(uint32_t ble_irq_status) +{ +} __weak void HAL_RADIO_TxRxSeqCallback(void) { @@ -1768,7 +1761,7 @@ void HAL_RADIO_TXRX_IRQHandler(void) uint32_t blue_status = BLUE->STATUSREG; uint32_t blue_interrupt = BLUE->INTERRUPT1REG; - /** clear all pending interrupts */ + /* clear all pending interrupts */ BLUE->INTERRUPT1REG = blue_interrupt; HAL_RADIO_TIMER_EndOfRadioActivityIsr(); @@ -1789,6 +1782,19 @@ void HAL_RADIO_TXRX_IRQHandler(void) blue_interrupt = BLUE->INTERRUPT1REG; } +void HAL_RADIO_RRM_IRQHandler(void) +{ + uint32_t ble_irq_status = RRM->BLE_IRQ_STATUS; + + /* Clear RRM Status register */ + RRM->BLE_IRQ_STATUS = ble_irq_status; + + HAL_RADIO_RRMCallback(ble_irq_status); + + /* Ensure flag is cleared */ + ble_irq_status = RRM->BLE_IRQ_STATUS; +} + void HAL_RADIO_TXRX_SEQ_IRQHandler(void) { diff --git a/stm32cube/stm32wb0x/drivers/src/stm32wb0x_hal_radio_timer.c b/stm32cube/stm32wb0x/drivers/src/stm32wb0x_hal_radio_timer.c index ad4161b7c..f34bbafec 100644 --- a/stm32cube/stm32wb0x/drivers/src/stm32wb0x_hal_radio_timer.c +++ b/stm32cube/stm32wb0x/drivers/src/stm32wb0x_hal_radio_timer.c @@ -53,7 +53,6 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32wb0x_hal.h" - /** @addtogroup STM32WB0x_HAL_Driver * @{ */ @@ -72,6 +71,7 @@ typedef struct { uint8_t periodicCalibration; /*!< Periodic calibration enable status */ uint32_t periodicCalibrationInterval; /*!< Periodic calibration interval in ms, to disable set to 0 */ + uint32_t periodicCalibrationIntervalMTU; /*!< Periodic calibration interval in Machine Time Unit, to disable set to 0 */ bool calibration_in_progress; /*!< Flag to indicate that a periodic calibration has been started */ } CalibrationSettingsTypeDef; @@ -82,8 +82,7 @@ typedef struct int32_t freq1; /** Round(((freq/64)*0x753)/256) */ int32_t period1; /** Round (( ((period /256) * 0x8BCF6) + (((period % 256)* 0x8BCF6)/256)) / 32) */ int32_t last_period1; /** Period global in last calibration */ - uint64_t last_calibration_time; /** Absolute system time when last calibration was performed */ - uint32_t calibration_machine_interval; /** Calibration Interval MTU */ + uint64_t nextCalibrationEvent; /** Absolute system time when next calibration will be performed */ uint8_t calibration_data_available; /** Flag to signal if a new calibration data is available or not */ } CalibrationDataTypeDef; @@ -115,9 +114,10 @@ typedef struct VTIMER_HandleType calibrationTimer; RADIO_TIMER_RadioHandleTypeDef radioTimer; uint32_t hs_startup_time; /*!< HS startup time */ - uint64_t cumulative_time; /** Absolute system time since power up */ - uint64_t last_system_time; /** Last System Time */ - uint32_t last_machine_time; /** Last machine time used to update cumulative time */ + uint64_t last_calib_system_time; /** Absolute system time of last calibration since power up */ + uint32_t last_calib_machine_time; /** Last calibration machine time used to update cumulative time */ + uint64_t last_system_time; /** Last System Time since power up*/ + uint32_t last_machine_time; /** Last Machine Time used paired with last_system_time */ uint8_t last_setup_time; /**setup time of last timer programmed*/ uint32_t last_anchor_mt; VTIMER_HandleType *rootNode; /*!< First timer of the host timer queue */ @@ -149,7 +149,13 @@ typedef struct * It is expressed in STU. */ #define RADIO_ACTIVITY_MARGIN (204800) +/* Time after that calibration should be completed + * It is expressed in STU.*/ + +#define CALIBRATION_CHECK_DURATION (100) + /* Threshold to take into account the calibration duration. */ + #define CALIB_SAFE_THR (370) /* Minimum threshold to safely program the radio timer (expressed in STU) */ @@ -184,6 +190,9 @@ it is not sure the timer can be cleared properly */ #define RADIO_TX_RX_EXCEPTION_NUMBER 18 #endif +/* This is the maximum timeout that can be used to program a timer with 32 bits */ +#define HAL_RADIO_TIMER_MAX_32BIT_TIMEOUT (0xFFFFFFFF - 410) + /** * @} */ @@ -258,19 +267,19 @@ static void _updateCalibrationData(void); static uint32_t _us_to_systime(uint32_t time); static uint32_t _us_to_machinetime(uint32_t time); -static void _configureTxRxDelay(RADIO_TIMER_ContextTypeDef *context, uint8_t calculate_st); +static void _configureTxRxDelay(uint8_t calculate_st); static void _update_xtal_startup_time(uint16_t hs_startup_time, int32_t freq1); uint32_t blue_unit_conversion(uint32_t time, uint32_t period_freq, uint32_t thr); /* Translate MTU to STU and vice-versa. It is implemented using integer operation. */ -static uint64_t _get_system_time_and_machine(RADIO_TIMER_ContextTypeDef *context, uint32_t *current_machine_time); +static void _update_calibration_time(void); +static void _update_system_and_machine_time(void); static int32_t _start_timer(VTIMER_HandleType *timerHandle, uint64_t time); static VTIMER_HandleType *_update_user_timeout(VTIMER_HandleType *rootNode, uint8_t *expired); static VTIMER_HandleType *_insert_timer_in_queue(VTIMER_HandleType *rootNode, VTIMER_HandleType *handle); static void _virtualTimeBaseEnable(FunctionalState state); static VTIMER_HandleType *_remove_timer_in_queue(VTIMER_HandleType *rootNode, VTIMER_HandleType *handle); static VTIMER_HandleType *_check_callbacks(VTIMER_HandleType *rootNode, VTIMER_HandleType **expiredList); -static void _update_system_time(RADIO_TIMER_ContextTypeDef *context); -static void _check_radio_activity(RADIO_TIMER_RadioHandleTypeDef *timerHandle, uint8_t *expired); +static uint8_t _check_radio_activity(uint8_t update_sys_time); #if defined (STM32WB06) || defined (STM32WB07) static uint32_t TIMER_SetRadioHostWakeupTime(uint32_t delay, bool *share); static void _set_controller_as_host(void); @@ -278,7 +287,7 @@ static void _check_host_activity(void); #else static uint32_t VTIMER_SetWakeupTime(uint32_t delay, bool allow_sleep); #endif -static uint8_t TIMER_SetRadioTimerValue(uint32_t timeout, bool event_type, bool cal_req); +static uint8_t TIMER_SetRadioTimerValue(void); static uint64_t TIMER_GetPastSysTime(uint32_t time, uint64_t *current_system_time); static bool TIMER_SleepCheck(void); static uint8_t TIMER_GetRadioTimerValue(uint32_t *time); @@ -347,12 +356,11 @@ void HAL_RADIO_TIMER_Init(RADIO_TIMER_InitTypeDef *RADIO_TIMER_InitStruct) /* Init Radio Timer Context */ RADIO_TIMER_Context.last_setup_time = 0; - RADIO_TIMER_Context.cumulative_time = 0; - RADIO_TIMER_Context.last_machine_time = LL_RADIO_TIMER_GetAbsoluteTime(WAKEUP); + RADIO_TIMER_Context.last_calib_system_time = 0; + RADIO_TIMER_Context.last_calib_machine_time = LL_RADIO_TIMER_GetAbsoluteTime(WAKEUP); RADIO_TIMER_Context.last_system_time = 0; - RADIO_TIMER_Context.calibrationData.last_calibration_time = 0; RADIO_TIMER_Context.calibrationData.calibration_data_available = 0; - RADIO_TIMER_Context.calibrationData.calibration_machine_interval = blue_unit_conversion(RADIO_TIMER_Context.calibrationSettings.periodicCalibrationInterval, + RADIO_TIMER_Context.calibrationSettings.periodicCalibrationIntervalMTU = blue_unit_conversion(RADIO_TIMER_Context.calibrationSettings.periodicCalibrationInterval, RADIO_TIMER_Context.calibrationData.freq1, MULT64_THR_FREQ); RADIO_TIMER_Context.wakeup_calibration = RADIO_TIMER_Context.calibrationSettings.periodicCalibration; @@ -374,9 +382,8 @@ void HAL_RADIO_TIMER_Init(RADIO_TIMER_InitTypeDef *RADIO_TIMER_InitStruct) RADIO_TIMER_Context.calibrationTimer.userData = NULL; _start_timer(&RADIO_TIMER_Context.calibrationTimer, HAL_RADIO_TIMER_GetCurrentSysTime() + RADIO_TIMER_Context.calibrationSettings.periodicCalibrationInterval); - /* Tx & Rx delay configuration */ - _configureTxRxDelay(&RADIO_TIMER_Context, TRUE); + _configureTxRxDelay(TRUE); } /** @@ -389,16 +396,6 @@ void HAL_RADIO_TIMER_Tick(void) { uint8_t expired = 0; - ATOMIC_SECTION_BEGIN(); - if (RADIO_TIMER_Context.radioTimer.active) - { - if (RADIO_TIMER_Context.radioTimer.expiryTime < HAL_RADIO_TIMER_GetCurrentSysTime()) - { - RADIO_TIMER_Context.radioTimer.active = FALSE; - } - } - ATOMIC_SECTION_END(); - /* Check for expired timers */ while (DIFF8(RADIO_TIMER_Context.expired_count, RADIO_TIMER_Context.served_count)) { @@ -452,15 +449,12 @@ void HAL_RADIO_TIMER_Tick(void) { RADIO_TIMER_Context.waitCal = 0; RADIO_TIMER_Context.radioTimer.pending = TRUE; - _check_radio_activity(&RADIO_TIMER_Context.radioTimer, &expired); - RADIO_TIMER_Context.rootNode = _update_user_timeout(RADIO_TIMER_Context.rootNode, &expired); } -#else - _check_radio_activity(&RADIO_TIMER_Context.radioTimer, &expired); #endif + _check_radio_activity(TRUE); //Start Radio Timer after calibration - HAL_RADIO_TIMER_StopVirtualTimer(&RADIO_TIMER_Context.calibrationTimer); /* Schedule next calibration event */ + HAL_RADIO_TIMER_StopVirtualTimer(&RADIO_TIMER_Context.calibrationTimer); _start_timer(&RADIO_TIMER_Context.calibrationTimer, HAL_RADIO_TIMER_GetCurrentSysTime() + RADIO_TIMER_Context.calibrationSettings.periodicCalibrationInterval); } @@ -470,9 +464,10 @@ void HAL_RADIO_TIMER_Tick(void) { if (RADIO_TIMER_Context.calibrationSettings.periodicCalibration) { - if (HAL_RADIO_TIMER_GetCurrentSysTime() > (RADIO_TIMER_Context.calibrationData.last_calibration_time + + if (HAL_RADIO_TIMER_GetCurrentSysTime() > (RADIO_TIMER_Context.last_calib_system_time + TIMER_SYSTICK_PER_FIVE_SECONDS)) { + HAL_RADIO_TIMER_StopVirtualTimer(&RADIO_TIMER_Context.calibrationTimer); _calibration_callback(&RADIO_TIMER_Context.calibrationTimer); } } @@ -591,37 +586,40 @@ PowerSaveLevels HAL_RADIO_TIMER_PowerSaveLevelCheck(void) * @param event_type: Specify if it is a TX (1) or RX (0) event. * @param cal_req: Specify if PLL calibration is requested (1) or not (0). * @retval 0 if radio activity has been scheduled successfully. - * @retval 1 if radio activity has been rejected (it is too close or in the past). + * @retval 1 if radio activity has been rejected. */ uint32_t HAL_RADIO_TIMER_SetRadioTimerValue(uint32_t time, uint8_t event_type, uint8_t cal_req) { uint8_t retVal = 0; -#if defined (STM32WB06) || defined (STM32WB07) - uint64_t current_time; -#endif RADIO_TIMER_Context.radioTimer.event_type = event_type; RADIO_TIMER_Context.radioTimer.cal_req = cal_req; - RADIO_TIMER_Context.radioTimer.expiryTime = RADIO_TIMER_Context.calibrationData.last_calibration_time + (uint32_t)(time - (uint32_t)RADIO_TIMER_Context.calibrationData.last_calibration_time); RADIO_TIMER_Context.radioTimer.active = FALSE; RADIO_TIMER_Context.radioTimer.intTxRx_to_be_served = FALSE; RADIO_TIMER_Context.radioTimer.pending = TRUE; + ATOMIC_SECTION_BEGIN(); + RADIO_TIMER_Context.radioTimer.expiryTime = HAL_RADIO_TIMER_GetFutureSysTime64(time); + if(RADIO_TIMER_Context.radioTimer.expiryTime - RADIO_TIMER_Context.last_system_time > HAL_RADIO_TIMER_MAX_32BIT_TIMEOUT) + { + RADIO_TIMER_Context.radioTimer.pending = FALSE; + ATOMIC_SECTION_END(); + return 1; + } #if defined (STM32WB06) || defined (STM32WB07) - current_time = HAL_RADIO_TIMER_GetCurrentSysTime(); if (RADIO_TIMER_Context.rootNode == NULL) { - _check_radio_activity(&RADIO_TIMER_Context.radioTimer, &retVal); + retVal = _check_radio_activity(FALSE); } else { - if (RADIO_TIMER_Context.rootNode->expiryTime < current_time || + if (RADIO_TIMER_Context.rootNode->expiryTime < RADIO_TIMER_Context.last_system_time || ((RADIO_TIMER_Context.radioTimer.expiryTime < (RADIO_TIMER_Context.rootNode->expiryTime + RADIO_TIMER_Context.hostMargin)) && RADIO_TIMER_Context.rootNode->active) || !RADIO_TIMER_Context.rootNode->active) { /* Program the radio timer */ - _check_radio_activity(&RADIO_TIMER_Context.radioTimer, &retVal); + retVal = _check_radio_activity(FALSE); if ((RADIO_TIMER_Context.radioTimer.expiryTime >= RADIO_TIMER_Context.rootNode->expiryTime) && RADIO_TIMER_Context.rootNode->active) { @@ -635,14 +633,15 @@ uint32_t HAL_RADIO_TIMER_SetRadioTimerValue(uint32_t time, uint8_t event_type, u Make sure radio errors are disabled. This call is not needed if radio errors are not enabled by the BLE stack. */ _set_controller_as_host(); + _check_host_activity(); } } #else - _check_radio_activity(&RADIO_TIMER_Context.radioTimer, &retVal); + retVal = _check_radio_activity(FALSE); #endif + ATOMIC_SECTION_END(); _virtualTimeBaseEnable(ENABLE); - return retVal; } @@ -786,9 +785,9 @@ uint32_t HAL_RADIO_TIMER_ClearRadioTimerValue(void) /** * @brief Program the radio timer (a.k.a Timer1) as close as possible. - * The current time is sampled and increased by two. + * The current time is sampled and increased by 4. * It means that the timer is going to trigger in a timer interval that goes - * from one to two machine time units. + * from three to four time units. */ void HAL_RADIO_TIMER_SetRadioCloseTimeout(void) { @@ -796,7 +795,7 @@ void HAL_RADIO_TIMER_SetRadioCloseTimeout(void) ATOMIC_SECTION_BEGIN(); current_time = LL_RADIO_TIMER_GetAbsoluteTime(WAKEUP); - LL_RADIO_TIMER_SetTimeout(BLUE, ((current_time + 2) & TIMER_MAX_VALUE)); + LL_RADIO_TIMER_SetTimeout(BLUE, ((current_time + 4) & TIMER_MAX_VALUE)); LL_RADIO_TIMER_EnableTimer1(BLUE); ATOMIC_SECTION_END(); } @@ -821,7 +820,12 @@ void HAL_RADIO_TIMER_RadioTimerIsr(void) */ void HAL_RADIO_TIMER_EndOfRadioActivityIsr(void) { + if (RADIO_TIMER_Context.radioTimer.active) + { + RADIO_TIMER_Context.radioTimer.active = FALSE; + } RADIO_TIMER_Context.radioTimer.intTxRx_to_be_served = FALSE; + } /* ----------------------- Radio Timer time unit APIs ------------------------*/ @@ -857,8 +861,8 @@ uint32_t HAL_RADIO_TIMER_MachineTimeToSysTime(uint32_t time) */ uint64_t HAL_RADIO_TIMER_GetCurrentSysTime(void) { - uint32_t current_machine_time; - return _get_system_time_and_machine(&RADIO_TIMER_Context, ¤t_machine_time); + _update_system_and_machine_time(); + return RADIO_TIMER_Context.last_system_time; } /** @@ -965,9 +969,10 @@ uint64_t HAL_RADIO_TIMER_ExpiryTime(VTIMER_HandleType *timerHandle) void HAL_RADIO_TIMER_WakeUpCallback(void) { volatile uint32_t status = 0; - uint8_t expired; UNUSED(status); - _check_radio_activity(&RADIO_TIMER_Context.radioTimer, &expired); + + _check_radio_activity(TRUE); + if (RADIO_TIMER_Context.hostIsRadioPending) { RADIO_TIMER_Context.hostIsRadioPending = 0; @@ -1027,7 +1032,7 @@ uint64_t HAL_RADIO_TIMER_GetSysTime64(uint32_t sys_time) { uint64_t time; - time = RADIO_TIMER_Context.calibrationData.last_calibration_time + (uint32_t)(sys_time - (uint32_t)RADIO_TIMER_Context.calibrationData.last_calibration_time); + time = RADIO_TIMER_Context.last_calib_system_time + (uint32_t)(sys_time - (uint32_t)RADIO_TIMER_Context.last_calib_system_time); return time; } @@ -1041,13 +1046,11 @@ uint64_t HAL_RADIO_TIMER_GetSysTime64(uint32_t sys_time) */ uint64_t HAL_RADIO_TIMER_GetFutureSysTime64(uint32_t sys_time) { - uint64_t current_time; uint32_t sysTime_ms32b; + _update_system_and_machine_time(); + sysTime_ms32b = RADIO_TIMER_Context.last_system_time >> 32; /* Most significant 32 bits of sysTime64 */ - current_time = HAL_RADIO_TIMER_GetCurrentSysTime(); - sysTime_ms32b = current_time >> 32; /* Most significant 32 bits of sysTime64 */ - - if (sys_time < (uint32_t)current_time) + if (sys_time < (uint32_t)RADIO_TIMER_Context.last_system_time) { /* Need to get most signicant 32 bits of current time increased by one */ sysTime_ms32b++; @@ -1133,22 +1136,22 @@ static void _get_calibration_data(CalibrationDataTypeDef *calibrationData) calibrationData->freq = freq; } -static void _configureTxRxDelay(RADIO_TIMER_ContextTypeDef *context, uint8_t calculate_st) +static void _configureTxRxDelay(uint8_t calculate_st) { uint8_t tx_delay_start; tx_delay_start = (BLUEGLOB->TXDELAYSTART * 125 / 1000) + 1; - BLUEGLOB->WAKEUPINITDELAY = blue_unit_conversion(WAKEUP_INIT_DELAY, context->calibrationData.freq1, MULT64_THR_FREQ); - context->TxRxDelay.tim12_delay_mt = _us_to_machinetime(BLUEGLOB->TIMER12INITDELAYCAL); - context->TxRxDelay.tx_cal_delay = _us_to_machinetime(BLUEGLOB->TRANSMITCALDELAYCHK + tx_delay_start); - context->TxRxDelay.tx_no_cal_delay = _us_to_machinetime(BLUEGLOB->TRANSMITNOCALDELAYCHK + tx_delay_start); - context->TxRxDelay.rx_cal_delay = _us_to_machinetime(BLUEGLOB->RECEIVECALDELAYCHK); - context->TxRxDelay.rx_no_cal_delay = _us_to_machinetime(BLUEGLOB->RECEIVENOCALDELAYCHK); + BLUEGLOB->WAKEUPINITDELAY = blue_unit_conversion(WAKEUP_INIT_DELAY, RADIO_TIMER_Context.calibrationData.freq1, MULT64_THR_FREQ); + RADIO_TIMER_Context.TxRxDelay.tim12_delay_mt = _us_to_machinetime(BLUEGLOB->TIMER12INITDELAYCAL); + RADIO_TIMER_Context.TxRxDelay.tx_cal_delay = _us_to_machinetime(BLUEGLOB->TRANSMITCALDELAYCHK + tx_delay_start); + RADIO_TIMER_Context.TxRxDelay.tx_no_cal_delay = _us_to_machinetime(BLUEGLOB->TRANSMITNOCALDELAYCHK + tx_delay_start); + RADIO_TIMER_Context.TxRxDelay.rx_cal_delay = _us_to_machinetime(BLUEGLOB->RECEIVECALDELAYCHK); + RADIO_TIMER_Context.TxRxDelay.rx_no_cal_delay = _us_to_machinetime(BLUEGLOB->RECEIVENOCALDELAYCHK); if (calculate_st) { - context->TxRxDelay.tx_cal_delay_st = _us_to_systime(BLUEGLOB->TRANSMITCALDELAYCHK + tx_delay_start) + WAKEUP_INIT_DELAY; + RADIO_TIMER_Context.TxRxDelay.tx_cal_delay_st = _us_to_systime(BLUEGLOB->TRANSMITCALDELAYCHK + tx_delay_start) + WAKEUP_INIT_DELAY; } } @@ -1187,11 +1190,15 @@ static void _update_xtal_startup_time(uint16_t hs_startup_time, int32_t freq1) static void _calibration_callback(void *handle) { - if (RADIO_TIMER_Context.calibrationSettings.periodicCalibration) + if(RADIO_TIMER_Context.calibrationSettings.calibration_in_progress == FALSE) { - _timer_start_calibration(); + if (RADIO_TIMER_Context.calibrationSettings.periodicCalibration) + { + _timer_start_calibration(); + } + RADIO_TIMER_Context.calibrationSettings.calibration_in_progress = TRUE; } - RADIO_TIMER_Context.calibrationSettings.calibration_in_progress = TRUE; + _start_timer(&RADIO_TIMER_Context.calibrationTimer, HAL_RADIO_TIMER_GetCurrentSysTime() + CALIBRATION_CHECK_DURATION); } static int32_t _start_timer(VTIMER_HandleType *timerHandle, uint64_t time) @@ -1215,27 +1222,33 @@ static int32_t _start_timer(VTIMER_HandleType *timerHandle, uint64_t time) INCREMENT_EXPIRE_COUNT; } } + #if defined (STM32WB06) || defined (STM32WB07) + else + { + _check_host_activity(); + } + #endif + return expired; } -static uint64_t _get_system_time_and_machine(RADIO_TIMER_ContextTypeDef *context, uint32_t *current_machine_time) +static void _update_system_and_machine_time(void) { uint32_t difftime; uint64_t new_time; ATOMIC_SECTION_BEGIN(); - new_time = context->cumulative_time; - *current_machine_time = LL_RADIO_TIMER_GetAbsoluteTime(WAKEUP); - difftime = TIME_ABSDIFF(*current_machine_time, context->last_machine_time); - new_time += blue_unit_conversion(difftime, context->calibrationData.period1, MULT64_THR_PERIOD); - if (new_time < context->last_system_time) + new_time = RADIO_TIMER_Context.last_calib_system_time; + RADIO_TIMER_Context.last_machine_time = LL_RADIO_TIMER_GetAbsoluteTime(WAKEUP); + difftime = TIME_ABSDIFF(RADIO_TIMER_Context.last_machine_time, RADIO_TIMER_Context.last_calib_machine_time); + new_time += blue_unit_conversion(difftime, RADIO_TIMER_Context.calibrationData.period1, MULT64_THR_PERIOD); + if (new_time < RADIO_TIMER_Context.last_system_time) { - new_time += blue_unit_conversion(TIMER_MAX_VALUE, context->calibrationData.period1, MULT64_THR_PERIOD); + new_time += blue_unit_conversion(TIMER_MAX_VALUE, RADIO_TIMER_Context.calibrationData.period1, MULT64_THR_PERIOD); } - context->last_system_time = new_time; + RADIO_TIMER_Context.last_system_time = new_time; ATOMIC_SECTION_END(); - return new_time; } /* Set timeout and skip non active timers */ @@ -1250,15 +1263,15 @@ static VTIMER_HandleType *_update_user_timeout(VTIMER_HandleType *rootNode, uint if (curr->active) { ATOMIC_SECTION_BEGIN(); + _update_system_and_machine_time(); #if defined (STM32WB06) || defined (STM32WB07) - uint8_t dummy; bool share = FALSE; - _check_radio_activity(&RADIO_TIMER_Context.radioTimer, &dummy); + uint8_t dummy = _check_radio_activity(FALSE); #endif - delay = curr->expiryTime - HAL_RADIO_TIMER_GetCurrentSysTime(); + delay = curr->expiryTime - RADIO_TIMER_Context.last_system_time; if (delay > 0) { - /* Protection against interrupt must be used to avoid that the called function will be interrupted + /* Protection against interrupt must be used to avoid that the called function will be interrupted and so the timer programming will happen after the target time is already passed leading to a timer expiring after timer wraps, instead of the expected delay */ #if defined (STM32WB06) || defined (STM32WB07) @@ -1443,40 +1456,51 @@ static void _updateCalibrationData(void) { if (RADIO_TIMER_Context.calibrationSettings.periodicCalibration) { - _get_calibration_data(&RADIO_TIMER_Context.calibrationData); - _update_xtal_startup_time(RADIO_TIMER_Context.hs_startup_time, RADIO_TIMER_Context.calibrationData.freq1); - _configureTxRxDelay(&RADIO_TIMER_Context, FALSE); + + CalibrationDataTypeDef updatedCalibrationData; + _get_calibration_data(&updatedCalibrationData); + _update_xtal_startup_time(RADIO_TIMER_Context.hs_startup_time, updatedCalibrationData.freq1); + + ATOMIC_SECTION_BEGIN(); RADIO_TIMER_Context.calibrationData.calibration_data_available = 1; + RADIO_TIMER_Context.calibrationData.freq = updatedCalibrationData.freq; + RADIO_TIMER_Context.calibrationData.freq1 = updatedCalibrationData.freq1; + RADIO_TIMER_Context.calibrationData.period = updatedCalibrationData.period; + RADIO_TIMER_Context.calibrationData.period1 = updatedCalibrationData.period1; + _update_calibration_time(); + ATOMIC_SECTION_END(); + + _configureTxRxDelay(FALSE); } + else + { ATOMIC_SECTION_BEGIN(); - _update_system_time(&RADIO_TIMER_Context); + _update_calibration_time(); ATOMIC_SECTION_END(); + } } -/* This function update the system time after a calibration. +/* This function update the cumulative time after a calibration. * If the user calls too often this function, you could have rounding issues in the integer maths. */ -static void _update_system_time(RADIO_TIMER_ContextTypeDef *context) +static void _update_calibration_time(void) { - uint32_t current_machine_time; - uint32_t period; - - current_machine_time = LL_RADIO_TIMER_GetAbsoluteTime(WAKEUP); - period = context->calibrationData.last_period1; - context->cumulative_time = context->calibrationData.last_calibration_time + \ - blue_unit_conversion(TIME_ABSDIFF(current_machine_time, - context->last_machine_time), - period, MULT64_THR_PERIOD); + RADIO_TIMER_Context.last_machine_time = LL_RADIO_TIMER_GetAbsoluteTime(WAKEUP); + RADIO_TIMER_Context.last_calib_system_time += blue_unit_conversion(TIME_ABSDIFF(RADIO_TIMER_Context.last_machine_time, + RADIO_TIMER_Context.last_calib_machine_time), + RADIO_TIMER_Context.calibrationData.last_period1, + MULT64_THR_PERIOD); - if ((context->calibrationSettings.periodicCalibration == 0) - && (TIME_ABSDIFF(current_machine_time, - context->last_machine_time) < context->calibrationData.calibration_machine_interval)) + if ((RADIO_TIMER_Context.calibrationSettings.periodicCalibration == 0) //LSE + && (TIME_ABSDIFF(RADIO_TIMER_Context.last_machine_time, + RADIO_TIMER_Context.last_calib_machine_time) < RADIO_TIMER_Context.calibrationSettings.periodicCalibrationIntervalMTU)) { - context->cumulative_time += blue_unit_conversion(TIMER_MAX_VALUE, period, MULT64_THR_PERIOD); + RADIO_TIMER_Context.last_calib_system_time += blue_unit_conversion(TIMER_MAX_VALUE, RADIO_TIMER_Context.calibrationData.last_period1, MULT64_THR_PERIOD); } - context->last_machine_time = current_machine_time; - context->calibrationData.last_calibration_time = context->cumulative_time; - context->calibrationData.last_period1 = context->calibrationData.period1; + RADIO_TIMER_Context.last_system_time = RADIO_TIMER_Context.last_calib_system_time; + RADIO_TIMER_Context.last_calib_machine_time = RADIO_TIMER_Context.last_machine_time; + RADIO_TIMER_Context.calibrationData.nextCalibrationEvent = RADIO_TIMER_Context.last_calib_system_time + RADIO_TIMER_Context.calibrationSettings.periodicCalibrationInterval; + RADIO_TIMER_Context.calibrationData.last_period1 = RADIO_TIMER_Context.calibrationData.period1; } /* Check if it is time to program the pending radio timer (large timeouts). @@ -1487,43 +1511,45 @@ static void _update_system_time(RADIO_TIMER_ContextTypeDef *context) The check on the next calibration event is made even though the calibration is disabled (max cal. interval) in order to avoid counter wrapping with timeouts far in the future. */ -static void _check_radio_activity(RADIO_TIMER_RadioHandleTypeDef *timerHandle, uint8_t *expired) +static uint8_t _check_radio_activity(uint8_t update_sys_time) { - uint64_t nextCalibrationEvent, currentTime; - - *expired = 0; - - if (timerHandle->pending) + uint8_t expired = 0; + if (RADIO_TIMER_Context.radioTimer.pending) { - nextCalibrationEvent = RADIO_TIMER_Context.calibrationData.last_calibration_time + \ - RADIO_TIMER_Context.calibrationSettings.periodicCalibrationInterval; ATOMIC_SECTION_BEGIN(); - currentTime = HAL_RADIO_TIMER_GetCurrentSysTime(); - if ((timerHandle->expiryTime < (nextCalibrationEvent + RADIO_ACTIVITY_MARGIN)) || \ - (currentTime > (nextCalibrationEvent + CALIB_SAFE_THR))) + if(update_sys_time == TRUE) { - if (timerHandle->expiryTime - TIMER1_INIT_DELAY > (currentTime + TIMER1_MARGIN)) + _update_system_and_machine_time(); + } + + if ((RADIO_TIMER_Context.radioTimer.expiryTime < (RADIO_TIMER_Context.calibrationData.nextCalibrationEvent + RADIO_ACTIVITY_MARGIN)) || \ + (RADIO_TIMER_Context.last_system_time > (RADIO_TIMER_Context.calibrationData.nextCalibrationEvent + CALIB_SAFE_THR))) + { + if (RADIO_TIMER_Context.radioTimer.expiryTime - TIMER1_INIT_DELAY > (RADIO_TIMER_Context.last_system_time + TIMER1_MARGIN)) { - *expired = TIMER_SetRadioTimerValue(timerHandle->expiryTime, timerHandle->event_type, timerHandle->cal_req); - timerHandle->pending = FALSE; /* timer has been served. No more pending */ - timerHandle->active = TRUE; /* timer has been programmed and it becomes ACTIVE */ - timerHandle->intTxRx_to_be_served = TRUE; + expired = TIMER_SetRadioTimerValue(); + RADIO_TIMER_Context.radioTimer.pending = FALSE; /* timer has been served. No more pending */ + RADIO_TIMER_Context.radioTimer.active = TRUE; /* timer has been programmed and it becomes ACTIVE */ + RADIO_TIMER_Context.radioTimer.intTxRx_to_be_served = TRUE; } else { + RADIO_TIMER_Context.radioTimer.pending = FALSE; - *expired = 1; + expired = 1; } } else { + #if defined (STM32WB06) || defined (STM32WB07) RADIO_TIMER_Context.waitCal = 1; #endif } ATOMIC_SECTION_END(); } + return expired; } #if defined (STM32WB06) || defined (STM32WB07) @@ -1608,15 +1634,15 @@ static void _check_host_activity(void) * @retval 0 if a correct timeout has been programmed in the timeout register * @retval 1 if a correct timeout cannot be programmed */ -static uint8_t TIMER_SetRadioTimerValue(uint32_t timeout, bool event_type, bool cal_req) +static uint8_t TIMER_SetRadioTimerValue(void) { - uint32_t current_time, delay, radio_init_delay, device_delay, rel_timeout, rel_timeout_mt; + uint32_t delay, radio_init_delay, device_delay, rel_timeout, rel_timeout_mt; uint8_t ret_val; /*choose the 2nd init duration. Check the event_type and cal. request*/ - if (event_type == TX) + if (RADIO_TIMER_Context.radioTimer.event_type == TX) { - if (cal_req) + if (RADIO_TIMER_Context.radioTimer.cal_req) { radio_init_delay = RADIO_TIMER_Context.TxRxDelay.tx_cal_delay; device_delay = RADIO_TIMER_Context.TxRxDelay.tx_cal_delay_st; @@ -1629,7 +1655,7 @@ static uint8_t TIMER_SetRadioTimerValue(uint32_t timeout, bool event_type, bool } else { - if (cal_req) + if (RADIO_TIMER_Context.radioTimer.cal_req) { radio_init_delay = RADIO_TIMER_Context.TxRxDelay.rx_cal_delay; device_delay = RADIO_TIMER_Context.TxRxDelay.tx_cal_delay_st; @@ -1642,33 +1668,34 @@ static uint8_t TIMER_SetRadioTimerValue(uint32_t timeout, bool event_type, bool } /* At this point, it is care of the upper layers to guarantee that the timeout represents an absolute time in the future */ - rel_timeout = timeout - (uint32_t)_get_system_time_and_machine(&RADIO_TIMER_Context, ¤t_time); - + rel_timeout = (uint32_t)RADIO_TIMER_Context.radioTimer.expiryTime - (uint32_t)RADIO_TIMER_Context.last_system_time; rel_timeout_mt = blue_unit_conversion(rel_timeout, RADIO_TIMER_Context.calibrationData.freq1, MULT64_THR_FREQ); /*Check if the timeout is beyond the wakeup time offset. Then program either the WakeUp timer or the Timer1*/ if (rel_timeout > (device_delay + RADIO_TIMER_Context.hs_startup_time + MARGIN_EXT)) { /*The timeout is after the wakeup_time_offset, So it is ok to program the wakeup timer*/ + delay = rel_timeout_mt - BLUEGLOB->WAKEUPINITDELAY - radio_init_delay; - LL_RADIO_TIMER_SetBLEWakeupTime(WAKEUP, ((current_time + delay) & TIMER_MAX_VALUE)); + LL_RADIO_TIMER_SetBLEWakeupTime(WAKEUP, ((RADIO_TIMER_Context.last_machine_time + delay) & TIMER_MAX_VALUE)); LL_RADIO_TIMER_SetSleepRequestMode(WAKEUP, 0); LL_RADIO_TIMER_DisableTimer1(BLUE); LL_RADIO_TIMER_DisableTimer2(BLUE); LL_RADIO_TIMER_EnableBLEWakeupTimer(WAKEUP); LL_RADIO_TIMER_EnableWakeupTimerLowPowerMode(WAKEUP); radio_init_delay += BLUEGLOB->WAKEUPINITDELAY; + } else { delay = rel_timeout_mt - RADIO_TIMER_Context.TxRxDelay.tim12_delay_mt - radio_init_delay; - LL_RADIO_TIMER_SetTimeout(BLUE, ((current_time + delay) & TIMER_MAX_VALUE)); + LL_RADIO_TIMER_SetTimeout(BLUE, ((RADIO_TIMER_Context.last_machine_time + delay) & TIMER_MAX_VALUE)); LL_RADIO_TIMER_DisableBLEWakeupTimer(WAKEUP); LL_RADIO_TIMER_EnableTimer1(BLUE); radio_init_delay += RADIO_TIMER_Context.TxRxDelay.tim12_delay_mt; } - RADIO_TIMER_Context.last_anchor_mt = (current_time + rel_timeout_mt) & TIMER_MAX_VALUE; + RADIO_TIMER_Context.last_anchor_mt = (RADIO_TIMER_Context.last_machine_time + rel_timeout_mt) & TIMER_MAX_VALUE; #if defined (STM32WB06) || defined (STM32WB07) BLUEGLOB->BYTE4 |= 1 << 7; @@ -1702,11 +1729,12 @@ static uint8_t TIMER_SetRadioTimerValue(uint32_t timeout, bool event_type, bool */ static uint64_t TIMER_GetPastSysTime(uint32_t time, uint64_t *current_system_time) { - uint32_t delta_systime, current_machine_time; - - *current_system_time = _get_system_time_and_machine(&RADIO_TIMER_Context, ¤t_machine_time); - delta_systime = blue_unit_conversion(TIME_DIFF(current_machine_time, time), RADIO_TIMER_Context.calibrationData.period1, MULT64_THR_PERIOD); - + uint32_t delta_systime; + ATOMIC_SECTION_BEGIN(); + _update_system_and_machine_time(); + *current_system_time = RADIO_TIMER_Context.last_system_time; + delta_systime = blue_unit_conversion(TIME_DIFF(RADIO_TIMER_Context.last_machine_time, time), RADIO_TIMER_Context.calibrationData.period1, MULT64_THR_PERIOD); + ATOMIC_SECTION_END(); return (*current_system_time - delta_systime); } diff --git a/stm32cube/stm32wb0x/drivers/src/stm32wb0x_hal_rcc_ex.c b/stm32cube/stm32wb0x/drivers/src/stm32wb0x_hal_rcc_ex.c index d692fbc01..aeed5b687 100644 --- a/stm32cube/stm32wb0x/drivers/src/stm32wb0x_hal_rcc_ex.c +++ b/stm32cube/stm32wb0x/drivers/src/stm32wb0x_hal_rcc_ex.c @@ -315,6 +315,8 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) frequency = LSE_VALUE; break; case RCC_LPUART1_CLKSOURCE_16M: + frequency = 16000000U; + break; default: frequency = HSE_VALUE / 2; break; diff --git a/stm32cube/stm32wb0x/drivers/src/stm32wb0x_hal_smbus.c b/stm32cube/stm32wb0x/drivers/src/stm32wb0x_hal_smbus.c index bff76c0b0..5edd3c07d 100644 --- a/stm32cube/stm32wb0x/drivers/src/stm32wb0x_hal_smbus.c +++ b/stm32cube/stm32wb0x/drivers/src/stm32wb0x_hal_smbus.c @@ -1950,7 +1950,7 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t /* Increment Buffer pointer */ hsmbus->pBuffPtr++; - if ((hsmbus->XferSize > 0U)) + if (hsmbus->XferSize > 0U) { hsmbus->XferSize--; hsmbus->XferCount--; @@ -2378,7 +2378,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t S /* Increment Buffer pointer */ hsmbus->pBuffPtr++; - if ((hsmbus->XferSize > 0U)) + if (hsmbus->XferSize > 0U) { hsmbus->XferSize--; hsmbus->XferCount--; diff --git a/stm32cube/stm32wb0x/drivers/src/stm32wb0x_hal_spi.c b/stm32cube/stm32wb0x/drivers/src/stm32wb0x_hal_spi.c index 7761fe422..d53d3c0c8 100644 --- a/stm32cube/stm32wb0x/drivers/src/stm32wb0x_hal_spi.c +++ b/stm32cube/stm32wb0x/drivers/src/stm32wb0x_hal_spi.c @@ -44,7 +44,8 @@ (+++) Configure the DMA handle parameters (+++) Configure the DMA Tx or Rx Stream/Channel (+++) Associate the initialized hdma_tx(or _rx) handle to the hspi DMA Tx or Rx handle - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx + or Rx Stream/Channel (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure. @@ -190,7 +191,8 @@ @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits), SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA). @note - (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA() + (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and + HAL_SPI_TransmitReceive_DMA() (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA() (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA() @@ -813,43 +815,40 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca * @brief Transmit an amount of data in blocking mode. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData pointer to data buffer - * @param Size amount of data to be sent - * @param Timeout Timeout duration + * @param pData pointer to data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be sent + * @param Timeout Timeout duration in ms * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint32_t tickstart; - HAL_StatusTypeDef errorcode = HAL_OK; uint16_t initial_TxXferCount; /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); - /* Process Locked */ - __HAL_LOCK(hspi); - /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); initial_TxXferCount = Size; if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } if ((pData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } + /* Process Locked */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->pTxBuffPtr = (const uint8_t *)pData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; @@ -888,7 +887,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; } @@ -898,7 +897,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Wait until TXE flag is set to send data */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; } @@ -907,9 +906,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -919,47 +918,27 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) { - if (hspi->TxXferCount > 1U) - { - /* write on the data register in packing mode */ - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount -= 2U; - } - else - { - *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); - hspi->pTxBuffPtr ++; - hspi->TxXferCount--; - } + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint8_t); + hspi->TxXferCount--; } while (hspi->TxXferCount > 0U) { /* Wait until TXE flag is set to send data */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) { - if (hspi->TxXferCount > 1U) - { - /* write on the data register in packing mode */ - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount -= 2U; - } - else - { - *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); - hspi->pTxBuffPtr++; - hspi->TxXferCount--; - } + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint8_t); + hspi->TxXferCount--; } else { /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -984,29 +963,31 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint __HAL_SPI_CLEAR_OVRFLAG(hspi); } + hspi->State = HAL_SPI_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { - errorcode = HAL_ERROR; + return HAL_ERROR; } else { - hspi->State = HAL_SPI_STATE_READY; + return HAL_OK; } - -error: - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return errorcode; } /** * @brief Receive an amount of data in blocking mode. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData pointer to data buffer - * @param Size amount of data to be received - * @param Timeout Timeout duration + * @param pData pointer to data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be received + * @param Timeout Timeout duration in ms * @retval HAL status + * @note In master mode, if the direction is set to SPI_DIRECTION_2LINES + * the receive buffer is written to data register (DR) to generate + * clock pulses and receive data */ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) { @@ -1016,12 +997,15 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 __IO uint8_t tmpreg8 = 0; #endif /* USE_SPI_CRC */ uint32_t tickstart; - HAL_StatusTypeDef errorcode = HAL_OK; if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; } if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) @@ -1031,17 +1015,11 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout); } - /* Process Locked */ - __HAL_LOCK(hspi); - /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - if ((pData == NULL) || (Size == 0U)) - { - errorcode = HAL_ERROR; - goto error; - } + /* Process Locked */ + __HAL_LOCK(hspi); /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_RX; @@ -1113,9 +1091,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -1137,9 +1115,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -1156,8 +1134,8 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) { /* the latest data has not been received */ - errorcode = HAL_TIMEOUT; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } /* Receive last data in 16 Bit mode */ @@ -1175,8 +1153,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - errorcode = HAL_TIMEOUT; - goto error; + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } /* Read CRC to Flush DR and RXNE flag */ @@ -1202,8 +1181,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 { /* Error on the CRC reception */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - errorcode = HAL_TIMEOUT; - goto error; + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ tmpreg8 = *ptmpreg8; @@ -1229,35 +1209,33 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 } #endif /* USE_SPI_CRC */ + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ + __HAL_UNLOCK(hspi); if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { - errorcode = HAL_ERROR; + return HAL_ERROR; } else { - hspi->State = HAL_SPI_STATE_READY; + return HAL_OK; } - -error : - __HAL_UNLOCK(hspi); - return errorcode; } /** * @brief Transmit and Receive an amount of data in blocking mode. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pTxData pointer to transmission data buffer - * @param pRxData pointer to reception data buffer - * @param Size amount of data to be sent and received - * @param Timeout Timeout duration + * @param pTxData pointer to transmission data buffer (u8 or u16 data elements) + * @param pRxData pointer to reception data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be sent and received + * @param Timeout Timeout duration in ms * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, - uint32_t Timeout) +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout) { uint16_t initial_TxXferCount; - uint16_t initial_RxXferCount; uint32_t tmp_mode; HAL_SPI_StateTypeDef tmp_state; uint32_t tickstart; @@ -1271,14 +1249,10 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD /* Variable used to alternate Rx and Tx during transfer */ uint32_t txallowed = 1U; - HAL_StatusTypeDef errorcode = HAL_OK; /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - /* Process Locked */ - __HAL_LOCK(hspi); - /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); @@ -1286,25 +1260,26 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD tmp_state = hspi->State; tmp_mode = hspi->Init.Mode; initial_TxXferCount = Size; - initial_RxXferCount = Size; #if (USE_SPI_CRC != 0U) spi_cr1 = READ_REG(hspi->Instance->CR1); spi_cr2 = READ_REG(hspi->Instance->CR2); #endif /* USE_SPI_CRC */ if (!((tmp_state == HAL_SPI_STATE_READY) || \ - ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && + (tmp_state == HAL_SPI_STATE_BUSY_RX)))) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } + /* Process Locked */ + __HAL_LOCK(hspi); + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ if (hspi->State != HAL_SPI_STATE_BUSY_RX) { @@ -1316,7 +1291,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD hspi->pRxBuffPtr = (uint8_t *)pRxData; hspi->RxXferCount = Size; hspi->RxXferSize = Size; - hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; hspi->TxXferCount = Size; hspi->TxXferSize = Size; @@ -1333,7 +1308,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD #endif /* USE_SPI_CRC */ /* Set the Rx Fifo threshold */ - if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (initial_RxXferCount > 1U)) + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { /* Set fiforxthreshold according the reception data length: 16bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); @@ -1356,7 +1331,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; @@ -1379,7 +1354,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD /* Check TXE flag */ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; /* Next Data is a reception (Rx). Tx not allowed */ @@ -1410,9 +1385,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD } if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -1421,49 +1396,31 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) { - if (hspi->TxXferCount > 1U) - { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount -= 2U; - } - else - { - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); - hspi->pTxBuffPtr++; - hspi->TxXferCount--; + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint8_t); + hspi->TxXferCount--; #if (USE_SPI_CRC != 0U) - /* Enable CRC Transmission */ - if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + /* Enable CRC Transmission */ + if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */ + if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP)) { - /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */ - if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP)) - { - SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM); - } - SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM); } -#endif /* USE_SPI_CRC */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } +#endif /* USE_SPI_CRC */ } while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) { /* Check TXE flag */ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) { - if (hspi->TxXferCount > 1U) - { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount -= 2U; - } - else - { - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); - hspi->pTxBuffPtr++; - hspi->TxXferCount--; - } + *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr++; + hspi->TxXferCount--; /* Next Data is a reception (Rx). Tx not allowed */ txallowed = 0U; @@ -1484,31 +1441,17 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD /* Wait until RXNE flag is reset */ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U)) { - if (hspi->RxXferCount > 1U) - { - *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; - hspi->pRxBuffPtr += sizeof(uint16_t); - hspi->RxXferCount -= 2U; - if (hspi->RxXferCount <= 1U) - { - /* Set RX Fifo threshold before to switch on 8 bit data size */ - SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); - } - } - else - { - (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR; - hspi->pRxBuffPtr++; - hspi->RxXferCount--; - } + (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR; + hspi->pRxBuffPtr++; + hspi->RxXferCount--; /* Next Data is a Transmission (Tx). Tx is allowed */ txallowed = 1U; } if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -1522,8 +1465,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { /* Error on the CRC reception */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - errorcode = HAL_TIMEOUT; - goto error; + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } /* Read CRC */ if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) @@ -1548,8 +1492,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { /* Error on the CRC reception */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - errorcode = HAL_TIMEOUT; - goto error; + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ tmpreg8 = *ptmpreg8; @@ -1565,43 +1510,44 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); /* Clear CRC Flag */ __HAL_SPI_CLEAR_CRCERRFLAG(hspi); - - errorcode = HAL_ERROR; + __HAL_UNLOCK(hspi); + return HAL_ERROR; } #endif /* USE_SPI_CRC */ /* Check the end of the transaction */ if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) { - errorcode = HAL_ERROR; hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + __HAL_UNLOCK(hspi); + return HAL_ERROR; } + + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ + __HAL_UNLOCK(hspi); + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { - errorcode = HAL_ERROR; + return HAL_ERROR; } else { - hspi->State = HAL_SPI_STATE_READY; + return HAL_OK; } - -error : - __HAL_UNLOCK(hspi); - return errorcode; } /** * @brief Transmit an amount of data in non-blocking mode with Interrupt. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData pointer to data buffer - * @param Size amount of data to be sent + * @param pData pointer to data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef errorcode = HAL_OK; /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); @@ -1609,14 +1555,12 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u if ((pData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } /* Process Locked */ @@ -1625,7 +1569,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->pTxBuffPtr = (const uint8_t *)pData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; @@ -1673,27 +1617,28 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Enable TXE and ERR interrupt */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); -error : - return errorcode; + return HAL_OK; } /** * @brief Receive an amount of data in non-blocking mode with Interrupt. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData pointer to data buffer - * @param Size amount of data to be sent + * @param pData pointer to data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be received * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef errorcode = HAL_OK; - if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; } if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) @@ -1704,12 +1649,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui } - if ((pData == NULL) || (Size == 0U)) - { - errorcode = HAL_ERROR; - goto error; - } - /* Process Locked */ __HAL_LOCK(hspi); @@ -1781,24 +1720,23 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui /* Enable RXNE and ERR interrupt */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); -error : - return errorcode; + return HAL_OK; } /** * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pTxData pointer to transmission data buffer - * @param pRxData pointer to reception data buffer - * @param Size amount of data to be sent and received + * @param pTxData pointer to transmission data buffer (u8 or u16 data elements) + * @param pRxData pointer to reception data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be sent and received * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) { uint32_t tmp_mode; HAL_SPI_StateTypeDef tmp_state; - HAL_StatusTypeDef errorcode = HAL_OK; /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); @@ -1808,16 +1746,15 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p tmp_mode = hspi->Init.Mode; if (!((tmp_state == HAL_SPI_STATE_READY) || \ - ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && + (tmp_state == HAL_SPI_STATE_BUSY_RX)))) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } /* Process locked */ @@ -1831,7 +1768,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p /* Set the transaction information */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; hspi->pRxBuffPtr = (uint8_t *)pRxData; @@ -1892,21 +1829,19 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p /* Enable TXE, RXNE and ERR interrupt */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); -error : - return errorcode; + return HAL_OK; } /** * @brief Transmit an amount of data in non-blocking mode with DMA. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData pointer to data buffer - * @param Size amount of data to be sent + * @param pData pointer to data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef errorcode = HAL_OK; /* Check tx dma handle */ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); @@ -1914,25 +1849,23 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); - /* Process Locked */ - __HAL_LOCK(hspi); - if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } if ((pData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } + /* Process Locked */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->pTxBuffPtr = (const uint8_t *)pData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; @@ -1994,9 +1927,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - errorcode = HAL_ERROR; - - goto error; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; } /* Check if the SPI is already enabled */ @@ -2006,16 +1939,16 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, __HAL_SPI_ENABLE(hspi); } + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + /* Enable the SPI Error Interrupt Bit */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); /* Enable Tx DMA Request */ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); -error : - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_OK; } /** @@ -2023,22 +1956,24 @@ error : * @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData pointer to data buffer + * @param pData pointer to data buffer (u8 or u16 data elements) * @note When the CRC feature is enabled the pData Length must be Size + 1. - * @param Size amount of data to be sent + * @param Size amount of data elements (u8 or u16) to be received * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef errorcode = HAL_OK; - /* Check rx dma handle */ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; } if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) @@ -2055,12 +1990,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Process Locked */ __HAL_LOCK(hspi); - if ((pData == NULL) || (Size == 0U)) - { - errorcode = HAL_ERROR; - goto error; - } - /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; @@ -2138,9 +2067,9 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - errorcode = HAL_ERROR; - - goto error; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; } /* Check if the SPI is already enabled */ @@ -2150,34 +2079,33 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u __HAL_SPI_ENABLE(hspi); } + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + /* Enable the SPI Error Interrupt Bit */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); /* Enable Rx DMA Request */ SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); -error: - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_OK; } /** * @brief Transmit and Receive an amount of data in non-blocking mode with DMA. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pTxData pointer to transmission data buffer - * @param pRxData pointer to reception data buffer + * @param pTxData pointer to transmission data buffer (u8 or u16 data elements) + * @param pRxData pointer to reception data buffer (u8 or u16 data elements) * @note When the CRC feature is enabled the pRxData Length must be Size + 1 - * @param Size amount of data to be sent + * @param Size amount of data elements (u8 or u16) to be sent and received * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { uint32_t tmp_mode; HAL_SPI_StateTypeDef tmp_state; - HAL_StatusTypeDef errorcode = HAL_OK; /* Check rx & tx dma handles */ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); @@ -2186,26 +2114,25 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - /* Process locked */ - __HAL_LOCK(hspi); - /* Init temporary variables */ tmp_state = hspi->State; tmp_mode = hspi->Init.Mode; if (!((tmp_state == HAL_SPI_STATE_READY) || - ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && + (tmp_state == HAL_SPI_STATE_BUSY_RX)))) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } + /* Process locked */ + __HAL_LOCK(hspi); + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ if (hspi->State != HAL_SPI_STATE_BUSY_RX) { @@ -2214,7 +2141,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * /* Set the transaction information */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; hspi->pRxBuffPtr = (uint8_t *)pRxData; @@ -2305,9 +2232,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - errorcode = HAL_ERROR; - - goto error; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; } /* Enable Rx DMA Request */ @@ -2326,9 +2253,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - errorcode = HAL_ERROR; - - goto error; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; } /* Check if the SPI is already enabled */ @@ -2337,16 +2264,17 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); } + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + /* Enable the SPI Error Interrupt Bit */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); /* Enable Tx DMA Request */ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); -error : - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_OK; } /** @@ -2439,7 +2367,8 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) __HAL_SPI_DISABLE(hspi); /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -2472,7 +2401,8 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) } /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -2727,9 +2657,11 @@ HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) { HAL_StatusTypeDef errorcode = HAL_OK; /* The Lock is not implemented on this API to allow the user application - to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback(): + to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or + HAL_SPI_TxRxCpltCallback(): when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated - and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback() + and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or + HAL_SPI_TxRxCpltCallback() */ /* Abort the SPI DMA tx Stream/Channel */ @@ -3019,7 +2951,7 @@ __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi) * the configuration information for SPI module. * @retval SPI state */ -HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) +HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi) { /* Return SPI handle state */ return hspi->State; @@ -3031,7 +2963,7 @@ HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) * the configuration information for SPI module. * @retval SPI error code in bitmap format */ -uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) +uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi) { /* Return SPI ErrorCode */ return hspi->ErrorCode; @@ -3058,7 +2990,7 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) */ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); uint32_t tickstart; /* Init tickstart for timeout management*/ @@ -3115,7 +3047,7 @@ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); uint32_t tickstart; #if (USE_SPI_CRC != 0U) __IO uint32_t tmpreg = 0U; @@ -3232,7 +3164,7 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); uint32_t tickstart; #if (USE_SPI_CRC != 0U) __IO uint32_t tmpreg = 0U; @@ -3270,7 +3202,8 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) } else { - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, + tickstart) != HAL_OK) { /* Error on the CRC reception */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); @@ -3332,7 +3265,7 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Call user Tx half complete callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) @@ -3350,7 +3283,7 @@ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Call user Rx half complete callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) @@ -3368,7 +3301,7 @@ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Call user TxRx half complete callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) @@ -3386,7 +3319,7 @@ static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAError(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Stop the disable DMA transfer on SPI side */ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); @@ -3409,7 +3342,7 @@ static void SPI_DMAError(DMA_HandleTypeDef *hdma) */ static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); hspi->RxXferCount = 0U; hspi->TxXferCount = 0U; @@ -3431,7 +3364,7 @@ static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) */ static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); hspi->hdmatx->XferAbortCallback = NULL; @@ -3447,7 +3380,8 @@ static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) __HAL_SPI_DISABLE(hspi); /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -3497,7 +3431,7 @@ static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) */ static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Disable SPI Peripheral */ __HAL_SPI_DISABLE(hspi); @@ -3514,7 +3448,8 @@ static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) } /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -3650,14 +3585,14 @@ static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) /* Transmit data in packing Bit mode */ if (hspi->TxXferCount >= 2U) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount -= 2U; } /* Transmit data in 8 Bit mode */ else { - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr++; hspi->TxXferCount--; } @@ -3751,7 +3686,7 @@ static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) { /* Transmit data in 16 Bit mode */ - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; @@ -3904,7 +3839,7 @@ static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) { - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr++; hspi->TxXferCount--; @@ -3930,7 +3865,7 @@ static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi) { /* Transmit data in 16 Bit mode */ - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; @@ -4009,7 +3944,10 @@ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, { tmp_timeout = 0U; } - count--; + else + { + count--; + } } } @@ -4032,7 +3970,7 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, __IO uint32_t count; uint32_t tmp_timeout; uint32_t tmp_tickstart; - __IO uint8_t *ptmpreg8; + __IO const uint8_t *ptmpreg8; __IO uint8_t tmpreg8 = 0; /* Adjust Timeout value in case of end of transfer */ @@ -4091,7 +4029,10 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, { tmp_timeout = 0U; } - count--; + else + { + count--; + } } } @@ -4387,7 +4328,8 @@ static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi) } /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -4430,7 +4372,8 @@ static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi) __HAL_SPI_DISABLE(hspi); /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -4459,7 +4402,8 @@ static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi) } /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } diff --git a/stm32cube/stm32wb0x/drivers/src/stm32wb0x_hal_timebase_tim_template.c b/stm32cube/stm32wb0x/drivers/src/stm32wb0x_hal_timebase_tim_template.c index d7e383784..e3bd89fa8 100644 --- a/stm32cube/stm32wb0x/drivers/src/stm32wb0x_hal_timebase_tim_template.c +++ b/stm32cube/stm32wb0x/drivers/src/stm32wb0x_hal_timebase_tim_template.c @@ -111,6 +111,11 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP; if (HAL_TIM_Base_Init(&TimHandle) == HAL_OK) { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1U) + /* Register callback */ + HAL_TIM_RegisterCallback(&TimHandle, HAL_TIM_PERIOD_ELAPSED_CB_ID, TimeBase_TIM_PeriodElapsedCallback); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /* Start the TIM time Base generation in interrupt mode */ return HAL_TIM_Base_Start_IT(&TimHandle); } diff --git a/stm32cube/stm32wb0x/drivers/src/stm32wb0x_hal_uart.c b/stm32cube/stm32wb0x/drivers/src/stm32wb0x_hal_uart.c index c6736cb77..0b595ed76 100644 --- a/stm32cube/stm32wb0x/drivers/src/stm32wb0x_hal_uart.c +++ b/stm32cube/stm32wb0x/drivers/src/stm32wb0x_hal_uart.c @@ -721,7 +721,11 @@ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID +#if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUFIE) * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID +#endif +#endif * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID @@ -854,7 +858,11 @@ HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_ * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID +#if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUFIE) * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID +#endif +#endif * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID @@ -1032,75 +1040,83 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) =============================================================================== ##### IO operation functions ##### =============================================================================== + [..] This subsection provides a set of functions allowing to manage the UART asynchronous and Half duplex data transfers. - (#) There are two mode of transfer: - (+) Blocking mode: The communication is performed in polling mode. - The HAL status of all data processing is returned by the same function - after finishing transfer. - (+) Non-Blocking mode: The communication is performed using Interrupts - or DMA, These API's return the HAL status. - The end of the data processing will be indicated through the - dedicated UART IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks - will be executed respectively at the end of the transmit or Receive process - The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (++) Non-Blocking mode: The communication is performed using Interrupts + or DMA, These API's return the HAL status. + The end of the data processing will be indicated through the + dedicated UART IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks + will be executed respectively at the end of the transmit or Receive process + The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected (#) Blocking mode API's are : - (+) HAL_UART_Transmit() - (+) HAL_UART_Receive() + (++) HAL_UART_Transmit() + (++) HAL_UART_Receive() (#) Non-Blocking mode API's with Interrupt are : - (+) HAL_UART_Transmit_IT() - (+) HAL_UART_Receive_IT() - (+) HAL_UART_IRQHandler() + (++) HAL_UART_Transmit_IT() + (++) HAL_UART_Receive_IT() + (++) HAL_UART_IRQHandler() (#) Non-Blocking mode API's with DMA are : - (+) HAL_UART_Transmit_DMA() - (+) HAL_UART_Receive_DMA() - (+) HAL_UART_DMAPause() - (+) HAL_UART_DMAResume() - (+) HAL_UART_DMAStop() + (++) HAL_UART_Transmit_DMA() + (++) HAL_UART_Receive_DMA() + (++) HAL_UART_DMAPause() + (++) HAL_UART_DMAResume() + (++) HAL_UART_DMAStop() (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode: - (+) HAL_UART_TxHalfCpltCallback() - (+) HAL_UART_TxCpltCallback() - (+) HAL_UART_RxHalfCpltCallback() - (+) HAL_UART_RxCpltCallback() - (+) HAL_UART_ErrorCallback() + (++) HAL_UART_TxHalfCpltCallback() + (++) HAL_UART_TxCpltCallback() + (++) HAL_UART_RxHalfCpltCallback() + (++) HAL_UART_RxCpltCallback() + (++) HAL_UART_ErrorCallback() (#) Non-Blocking mode transfers could be aborted using Abort API's : - (+) HAL_UART_Abort() - (+) HAL_UART_AbortTransmit() - (+) HAL_UART_AbortReceive() - (+) HAL_UART_Abort_IT() - (+) HAL_UART_AbortTransmit_IT() - (+) HAL_UART_AbortReceive_IT() + (++) HAL_UART_Abort() + (++) HAL_UART_AbortTransmit() + (++) HAL_UART_AbortReceive() + (++) HAL_UART_Abort_IT() + (++) HAL_UART_AbortTransmit_IT() + (++) HAL_UART_AbortReceive_IT() (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided: - (+) HAL_UART_AbortCpltCallback() - (+) HAL_UART_AbortTransmitCpltCallback() - (+) HAL_UART_AbortReceiveCpltCallback() + (++) HAL_UART_AbortCpltCallback() + (++) HAL_UART_AbortTransmitCpltCallback() + (++) HAL_UART_AbortReceiveCpltCallback() (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced reception services: - (+) HAL_UARTEx_RxEventCallback() + (++) HAL_UARTEx_RxEventCallback() +#if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUFIE) + + (#) Wakeup from Stop mode Callback: + (++) HAL_UARTEx_WakeupCallback() +#endif +#endif (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : - (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is - to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error - in Interrupt mode reception . - Received character is then retrieved and stored in Rx buffer, Error code is set to allow user - to identify error type, and HAL_UART_ErrorCallback() user callback is executed. - Transfer is kept ongoing on UART side. - If user wants to abort it, Abort services should be called by user. - (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted. - This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. - Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() - user callback is executed. + (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error + in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user + to identify error type, and HAL_UART_ErrorCallback() user callback is executed. + Transfer is kept ongoing on UART side. + If user wants to abort it, Abort services should be called by user. + (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() + user callback is executed. -@- In the Half duplex communication, it is forbidden to run the transmit and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful. @@ -1194,7 +1210,15 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pD huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU); pdata8bits++; } - huart->TxXferCount--; + if ((huart->gState & HAL_UART_STATE_BUSY_TX) == HAL_UART_STATE_BUSY_TX) + { + huart->TxXferCount--; + } + else + { + /* Process was aborted during the transmission */ + return HAL_ERROR; + } } if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) @@ -1306,7 +1330,15 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); pdata8bits++; } - huart->RxXferCount--; + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + huart->RxXferCount--; + } + else + { + /* Process was aborted during the reception */ + return HAL_ERROR; + } } /* At end of Rx process, restore huart->RxState to Ready */ @@ -1814,10 +1846,6 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) } #endif /* HAL_DMA_MODULE_ENABLED */ - /* Reset Tx and Rx transfer counters */ - huart->TxXferCount = 0U; - huart->RxXferCount = 0U; - /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); @@ -1886,9 +1914,6 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) } #endif /* HAL_DMA_MODULE_ENABLED */ - /* Reset Tx transfer counter */ - huart->TxXferCount = 0U; - /* Flush the whole TX FIFO (if needed) */ if (huart->FifoMode == UART_FIFOMODE_ENABLE) { @@ -1953,9 +1978,6 @@ HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) } #endif /* HAL_DMA_MODULE_ENABLED */ - /* Reset Rx transfer counter */ - huart->RxXferCount = 0U; - /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); @@ -2083,10 +2105,6 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ if (abortcplt == 1U) { - /* Reset Tx and Rx transfer counters */ - huart->TxXferCount = 0U; - huart->RxXferCount = 0U; - /* Clear ISR function pointers */ huart->RxISR = NULL; huart->TxISR = NULL; @@ -2167,8 +2185,6 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) } else { - /* Reset Tx transfer counter */ - huart->TxXferCount = 0U; /* Clear TxISR function pointers */ huart->TxISR = NULL; @@ -2189,9 +2205,6 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) else #endif /* HAL_DMA_MODULE_ENABLED */ { - /* Reset Tx transfer counter */ - huart->TxXferCount = 0U; - /* Clear TxISR function pointers */ huart->TxISR = NULL; @@ -2266,9 +2279,6 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) } else { - /* Reset Rx transfer counter */ - huart->RxXferCount = 0U; - /* Clear RxISR function pointer */ huart->pRxBuffPtr = NULL; @@ -2295,9 +2305,6 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) else #endif /* HAL_DMA_MODULE_ENABLED */ { - /* Reset Rx transfer counter */ - huart->RxXferCount = 0U; - /* Clear RxISR function pointer */ huart->pRxBuffPtr = NULL; @@ -3709,8 +3716,6 @@ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) /* DMA Normal mode */ if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC)) { - huart->TxXferCount = 0U; - /* Disable the DMA transfer for transmit request by resetting the DMAT bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); @@ -3761,8 +3766,6 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) /* DMA Normal mode */ if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC)) { - huart->RxXferCount = 0U; - /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); @@ -3789,12 +3792,22 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { + /* Check current nb of data still to be received on DMA side. + DMA Normal mode, remaining nb of data will be 0 + DMA Circular mode, remaining nb of data is reset to RxXferSize */ + uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma); + if (nb_remaining_rx_data < huart->RxXferSize) + { + /* Update nb of remaining data */ + huart->RxXferCount = nb_remaining_rx_data; + } + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ - huart->RxEventCallback(huart, huart->RxXferSize); + huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ - HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); + HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } else @@ -3827,12 +3840,22 @@ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { + huart->RxXferCount = huart->RxXferSize / 2U; + + /* Check current nb of data still to be received on DMA side. */ + uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma); + if (nb_remaining_rx_data <= huart->RxXferSize) + { + /* Update nb of remaining data */ + huart->RxXferCount = nb_remaining_rx_data; + } + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ - huart->RxEventCallback(huart, huart->RxXferSize / 2U); + huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ - HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U); + HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } else @@ -3864,7 +3887,6 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma) if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && (gstate == HAL_UART_STATE_BUSY_TX)) { - huart->TxXferCount = 0U; UART_EndTxTransfer(huart); } @@ -3872,7 +3894,6 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma) if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && (rxstate == HAL_UART_STATE_BUSY_RX)) { - huart->RxXferCount = 0U; UART_EndRxTransfer(huart); } @@ -3896,8 +3917,6 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma) static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); - huart->RxXferCount = 0U; - huart->TxXferCount = 0U; #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ @@ -3931,10 +3950,6 @@ static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) } } - /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ - huart->TxXferCount = 0U; - huart->RxXferCount = 0U; - /* Reset errorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; @@ -3986,10 +4001,6 @@ static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) } } - /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ - huart->TxXferCount = 0U; - huart->RxXferCount = 0U; - /* Reset errorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; @@ -4027,8 +4038,6 @@ static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); - huart->TxXferCount = 0U; - /* Flush the whole TX FIFO (if needed) */ if (huart->FifoMode == UART_FIFOMODE_ENABLE) { @@ -4060,8 +4069,6 @@ static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - huart->RxXferCount = 0U; - /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); diff --git a/stm32cube/stm32wb0x/drivers/src/stm32wb0x_hal_uart_ex.c b/stm32cube/stm32wb0x/drivers/src/stm32wb0x_hal_uart_ex.c index fd5d1e95d..9890d1a4a 100644 --- a/stm32cube/stm32wb0x/drivers/src/stm32wb0x_hal_uart_ex.c +++ b/stm32cube/stm32wb0x/drivers/src/stm32wb0x_hal_uart_ex.c @@ -24,7 +24,7 @@ ============================================================================== ##### UART peripheral extended features ##### ============================================================================== - + [..] (#) Declare a UART_HandleTypeDef handle structure. (#) For the UART RS485 Driver Enable mode, initialize the UART registers @@ -255,19 +255,17 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, =============================================================================== ##### IO operation functions ##### =============================================================================== + [..] This subsection provides a set of Wakeup and FIFO mode related callback functions. - #if defined(USART_CR1_UESM) #if defined(USART_CR3_WUFIE) (#) Wakeup from Stop mode Callback: - (+) HAL_UARTEx_WakeupCallback() - + (++) HAL_UARTEx_WakeupCallback() #endif #endif (#) TX/RX Fifos Callbacks: - (+) HAL_UARTEx_RxFifoFullCallback() - (+) HAL_UARTEx_TxFifoEmptyCallback() - + (++) HAL_UARTEx_RxFifoFullCallback() + (++) HAL_UARTEx_TxFifoEmptyCallback() @endverbatim * @{ */ @@ -353,19 +351,19 @@ __weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) (#) Compared to standard reception services which only consider number of received data elements as reception completion criteria, these functions also consider additional events as triggers for updating reception status to caller : - (+) Detection of inactivity period (RX line has not been active for a given period). - (++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state) + (++) Detection of inactivity period (RX line has not been active for a given period). + (+++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state) for 1 frame time, after last received byte. - (++) RX inactivity detected by RTO, i.e. line has been in idle state + (+++) RX inactivity detected by RTO, i.e. line has been in idle state for a programmable time, after last received byte. - (+) Detection that a specific character has been received. + (++) Detection that a specific character has been received. - (#) There are two mode of transfer: - (+) Blocking mode: The reception is performed in polling mode, until either expected number of data is received, + (#) There are two modes of transfer: + (++) Blocking mode: The reception is performed in polling mode, until either expected number of data is received, or till IDLE event occurs. Reception is handled only during function execution. When function exits, no data reception could occur. HAL status and number of actually received data elements, are returned by function after finishing transfer. - (+) Non-Blocking mode: The reception is performed using Interrupts or DMA. + (++) Non-Blocking mode: The reception is performed using Interrupts or DMA. These API's return the HAL status. The end of the data processing will be indicated through the dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. @@ -373,13 +371,13 @@ __weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected. (#) Blocking mode API: - (+) HAL_UARTEx_ReceiveToIdle() + (++) HAL_UARTEx_ReceiveToIdle() (#) Non-Blocking mode API with Interrupt: - (+) HAL_UARTEx_ReceiveToIdle_IT() + (++) HAL_UARTEx_ReceiveToIdle_IT() (#) Non-Blocking mode API with DMA: - (+) HAL_UARTEx_ReceiveToIdle_DMA() + (++) HAL_UARTEx_ReceiveToIdle_DMA() @endverbatim * @{ @@ -1008,17 +1006,15 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_ * Half Transfer, or Transfer Complete), this function allows to retrieve the Rx Event type that has lead * to Rx Event callback execution. * @note This function is expected to be called within the user implementation of Rx Event Callback, - * in order to provide the accurate value : - * In Interrupt Mode : - * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received) - * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of - * received data is lower than expected one) - * In DMA Mode : - * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received) - * - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received - * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of - * received data is lower than expected one). - * In DMA mode, RxEvent callback could be called several times; + * in order to provide the accurate value. + * @note In Interrupt Mode: + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received). + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed. + * @note In DMA Mode: + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received). + * - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received. + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed. + * @note In DMA mode, RxEvent callback could be called several times; * When DMA is configured in Normal Mode, HT event does not stop Reception process; * When DMA is configured in Circular Mode, HT, TC or IDLE events don't stop Reception process; * @param huart UART handle. diff --git a/stm32cube/stm32wb0x/drivers/src/stm32wb0x_ll_pka.c b/stm32cube/stm32wb0x/drivers/src/stm32wb0x_ll_pka.c index 53844fdb8..4364cf19e 100644 --- a/stm32cube/stm32wb0x/drivers/src/stm32wb0x_ll_pka.c +++ b/stm32cube/stm32wb0x/drivers/src/stm32wb0x_ll_pka.c @@ -1,6 +1,6 @@ /** ****************************************************************************** - * @filestm32wb0x_ll_pka.c + * @file stm32wb0x_ll_pka.c * @author MCD Application Team * @brief PKA LL module driver. ****************************************************************************** diff --git a/stm32cube/stm32wb0x/drivers/src/stm32wb0x_ll_spi.c b/stm32cube/stm32wb0x/drivers/src/stm32wb0x_ll_spi.c index 4130c80db..d6db5ac95 100644 --- a/stm32cube/stm32wb0x/drivers/src/stm32wb0x_ll_spi.c +++ b/stm32cube/stm32wb0x/drivers/src/stm32wb0x_ll_spi.c @@ -130,7 +130,7 @@ * - SUCCESS: SPI registers are de-initialized * - ERROR: SPI registers are not de-initialized */ -ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx) +ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx) { ErrorStatus status = ERROR; @@ -179,8 +179,9 @@ ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx) /** * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct. - * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0), - * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. + * @note As some bits in SPI configuration registers can only be written when the + * SPI is disabled (SPI_CR1_SPE bit = 0), SPI peripheral should be in disabled state prior + * calling this function. Otherwise, ERROR result will be returned. * @param SPIx SPI Instance * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure * @retval An ErrorStatus enumeration value. (Return always SUCCESS) @@ -364,7 +365,7 @@ void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct) * - SUCCESS: SPI registers are de-initialized * - ERROR: SPI registers are not de-initialized */ -ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx) +ErrorStatus LL_I2S_DeInit(const SPI_TypeDef *SPIx) { return LL_SPI_DeInit(SPIx); } diff --git a/stm32cube/stm32wb0x/soc/stm32wb05.h b/stm32cube/stm32wb0x/soc/stm32wb05.h index 759d715e0..fb3c43094 100644 --- a/stm32cube/stm32wb0x/soc/stm32wb05.h +++ b/stm32cube/stm32wb0x/soc/stm32wb05.h @@ -75,6 +75,7 @@ typedef enum DMA_IRQn = 17, /*!< 17 DMA interrupt */ RADIO_TXRX_IRQn = 18, /*!< 18 BLE Tx/Rx interrupt */ RADIO_TIMER_ERROR_IRQn = 20, /*!< 20 RADIO TIMER Error interrupt */ + RADIO_RRM_IRQn = 22, /*!< 22 RADIO Resource Manager interrupt */ RADIO_TIMER_CPU_WKUP_IRQn = 23, /*!< 23 RADIO TIMER CPU Wakeup interrupt */ RADIO_TIMER_TXRX_WKUP_IRQn = 24, /*!< 24 RADIO TIMER Tx/Rx Wakeup interrupt */ RADIO_TXRX_SEQ_IRQn = 25, /*!< 25 BLE RX/TX sequence interrupt */ diff --git a/stm32cube/stm32wb0x/soc/stm32wb06.h b/stm32cube/stm32wb0x/soc/stm32wb06.h index 8a43479ce..95bcc9543 100644 --- a/stm32cube/stm32wb0x/soc/stm32wb06.h +++ b/stm32cube/stm32wb0x/soc/stm32wb06.h @@ -78,6 +78,7 @@ typedef enum DMA_IRQn = 17, /*!< 17 DMA interrupt */ RADIO_TXRX_IRQn = 18, /*!< 18 RADIO Tx/Rx interrupt */ RADIO_TIMER_ERROR_IRQn = 20, /*!< 20 RADIO TIMER Error interrupt */ + RADIO_RRM_IRQn = 22, /*!< 22 RADIO Resource Manager interrupt */ RADIO_TIMER_CPU_WKUP_IRQn = 23, /*!< 23 RADIO TIMER CPU Wakeup interrupt */ RADIO_TIMER_TXRX_WKUP_IRQn = 24, /*!< 24 RADIO TIMER Tx/Rx Wakeup interrupt */ RADIO_TXRX_SEQ_IRQn = 25 /*!< 25 RADIO Tx/Rx sequence interrupt */ diff --git a/stm32cube/stm32wb0x/soc/stm32wb07.h b/stm32cube/stm32wb0x/soc/stm32wb07.h index 31c2bc977..9432008c5 100644 --- a/stm32cube/stm32wb0x/soc/stm32wb07.h +++ b/stm32cube/stm32wb0x/soc/stm32wb07.h @@ -78,6 +78,7 @@ typedef enum DMA_IRQn = 17, /*!< 17 DMA interrupt */ RADIO_TXRX_IRQn = 18, /*!< 18 RADIO Tx/Rx interrupt */ RADIO_TIMER_ERROR_IRQn = 20, /*!< 20 RADIO TIMER Error interrupt */ + RADIO_RRM_IRQn = 22, /*!< 22 RADIO Resource Manager interrupt */ RADIO_TIMER_CPU_WKUP_IRQn = 23, /*!< 23 RADIO TIMER CPU Wakeup interrupt */ RADIO_TIMER_TXRX_WKUP_IRQn = 24, /*!< 24 RADIO TIMER Tx/Rx Wakeup interrupt */ RADIO_TXRX_SEQ_IRQn = 25 /*!< 25 RADIO Tx/Rx sequence interrupt */ diff --git a/stm32cube/stm32wb0x/soc/stm32wb09.h b/stm32cube/stm32wb0x/soc/stm32wb09.h index ece321a75..e18e8238a 100644 --- a/stm32cube/stm32wb0x/soc/stm32wb09.h +++ b/stm32cube/stm32wb0x/soc/stm32wb09.h @@ -100,6 +100,7 @@ typedef enum DMA_IRQn = 17, /*!< 17 DMA interrupt */ RADIO_TXRX_IRQn = 18, /*!< 18 RADIO Tx/Rx interrupt */ RADIO_TIMER_ERROR_IRQn = 20, /*!< 20 RADIO TIMER Error interrupt */ + RADIO_RRM_IRQn = 22, /*!< 22 RADIO Resource Manager interrupt */ RADIO_TIMER_CPU_WKUP_IRQn = 23, /*!< 23 RADIO TIMER CPU Wakeup interrupt */ RADIO_TIMER_TXRX_WKUP_IRQn = 24, /*!< 24 RADIO TIMER Tx/Rx Wakeup interrupt */ RADIO_TXRX_SEQ_IRQn = 25, /*!< 25 RADIO Tx/Rx sequence interrupt */ @@ -4148,9 +4149,6 @@ typedef struct /*!< WAKEUP Structure */ /* ============================================================================================================================*/ /* ===================================================== CR =====================================================*/ -#define RNG_CR_BP_POSTP_Pos (24UL) /*!CR2, PWR_CR2_RAMRET2); #endif /* PWR_CR2_RAMRET2 */ -#if defined(PWR_CR2_RAMRET2) +#if defined(PWR_CR2_RAMRET3) SET_BIT(PWR->CR2, PWR_CR2_RAMRET3); #endif /* PWR_CR2_RAMRET3 */ diff --git a/stm32cube/stm32wb0x/soc/system_stm32wb0x.h b/stm32cube/stm32wb0x/soc/system_stm32wb0x.h index 949157557..eea0a6500 100644 --- a/stm32cube/stm32wb0x/soc/system_stm32wb0x.h +++ b/stm32cube/stm32wb0x/soc/system_stm32wb0x.h @@ -66,7 +66,7 @@ extern "C" { * @brief RAM base address */ #define _MEMORY_RAM_BEGIN_ 0x20000000 -#define _MEMORY_RAM_SIZE_ 0x10000 /* 32KB */ +#define _MEMORY_RAM_SIZE_ 0x8000 /* 32KB */ #define _MEMORY_RAM_END_ 0x20007FFF /** diff --git a/zephyr/module.yml b/zephyr/module.yml index 4fef1b5e3..b97986fad 100644 --- a/zephyr/module.yml +++ b/zephyr/module.yml @@ -47,11 +47,11 @@ blobs: url: https://github.com/STMicroelectronics/STM32CubeWBA/raw/v1.7.0/Middlewares/ST/STM32_WPAN/ble/stack/lib/stm32wba_ble_stack_llobasic.a description: "Binary Stack library for the STM32WBA Bluetooth subsystem" - path: stm32wb0/lib/stm32wb0x_ble_stack_controller_only.a - sha256: 54bf69acaa59afc368132f8170e9910858a2c801538494d8de96fa567c02e233 + sha256: f4d44401f8caba4d81e7c38e7549745b7525650d61f53541f5e030d1228e52b9 type: lib - version: '1.0.0' + version: '1.4.0' license-path: zephyr/blobs/stm32wb0/lib/license.md - url: https://github.com/STMicroelectronics/STM32CubeWB0/raw/v1.0.0/Middlewares/ST/STM32_BLE/stack/lib/stm32wb0x_ble_stack_controller_only.a + url: https://github.com/STMicroelectronics/STM32CubeWB0/raw/v1.4.0/Middlewares/ST/STM32_BLE/stack/lib/stm32wb0x_ble_stack_controller_only.a description: "Binary Stack library for the STM32WB0 Bluetooth subsystem" - path: stm32wba/lib/WBA6_LinkLayer15_4_Zephyr.a sha256: 189e087aef9942b6fa77e0573346cedbb1ea354ee4aa7649bfbd465779969fb3