Reduced Instruction Set Computer (RISC) Processor

This is a single cycle processor, which processes each instruction in single clock cycle, working on Instruction Set Architecture (ISA) specified in the documentation.

Arhitecture

How to use it?

• Write code in given ISA in .asm file
• Convert that code into binary instructions using formatting given in documentation
• Store instructions in .coe file
• Load .coe file in Instruction Memory
• Simulate the test bench of RISC processor

Requirements

• Xilinx ISE 14.7 (To run the code)