Created by: Angelo Jacobo
Date: November 2,2021

Materials:

• ULX3S FPGA Board
• OV7670 PMOD Connector
• OV7670 Camera
• HDMI Connector

Two ways to run this design on your ULX3S FPGA Board:

• Using Icestudio GUI
• Using the FPGA Opensource Toolchain (Yosys+Nexpnr+Fujprog)

1. Using Icestudio GUI

1. Install Icestudio
2. Clone this repository on your desired directory:
   git clone https://github.com/AngeloJacobo/ULX3S_FPGA_Sobel_Edge_Detection_OV7670.git
3. Run ULX3S_SOBEL.ice
4. Click Tools>Build
5. Click Tools>Upload
6. Done!

2. Using the FPGA OpenSource Toolchain (Yosys+Nextpnr+Fujprog)

1. Clone this repository on your desired directory:
   git clone https://github.com/AngeloJacobo/ULX3S_FPGA_Sobel_Edge_Detection_OV7670.git
2. Run make sram (or make flash if you want to download it directly to flash)
3. Done!

If you do not yet have the FPGA opensource tools installed:

1. Download the latest release of oss-cad-suite that matches your OS
2. Follow the installation guide.
3. Check if you can now call yosys , nextpnr-ecp5 , and fujprog on bash. If command not found, just add the directories of the oss-cad-suite/bin , oss-cad-suite/lib , and oss-cad-suite/py3bin to PATH.

About:

This project is ported from my previous design FPGA_RealTime_and_Static_Sobel_Edge_Detection that uses Spartan 6 FPGA Board. This design uses an HDMI interface instead of VGA. RGB pixels and processed Sobel Edge Detected pixels are both stored to SDRAM and retrieved by the HDMI which will then be displayed on the monitor.

• btn3 - switch display (RGB or edge detected image)
• btn2 - increase threshold of Sobel Edge Detection
• btn1 - decrease threshold of Sobel Edge Detection

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Inquiries

Connect with me at my linkedin: https://www.linkedin.com/in/angelo-jacobo/