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0x00 and 0xFF give IndexOutOfBounds errors

Status: Open.

#20 In CIDARLAB/NetlistSynthesizer;

· bder opened on Nov 13, 2014

two compiler warnings

Status: Open.

#18 In CIDARLAB/NetlistSynthesizer;

· bder opened on Jul 31, 2014

0x16 precompute gives 10 gates instead of 9.

bug

Status: Open.

#17 In CIDARLAB/NetlistSynthesizer;

· bder opened on Jul 23, 2014

Check espresso

Status: Open.

#16 In CIDARLAB/NetlistSynthesizer;

· PrashantVaidyanathan opened on Jul 22, 2014

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NetSynth Tests

check abc

Status: Open.

#15 In CIDARLAB/NetlistSynthesizer;

· PrashantVaidyanathan opened on Jul 22, 2014

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NetSynth Tests

Check double inverters

Status: Open.

#14 In CIDARLAB/NetlistSynthesizer;

· PrashantVaidyanathan opened on Jul 22, 2014

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NetSynth Tests

Test 2 nots to nor

Status: Open.

#13 In CIDARLAB/NetlistSynthesizer;

· PrashantVaidyanathan opened on Jul 22, 2014

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NetSynth Tests

Create a test function for all n input circuits and verify correctness

Status: Open.

#12 In CIDARLAB/NetlistSynthesizer;

· PrashantVaidyanathan opened on Jul 22, 2014

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NetSynth Tests

for precompute synthesis, a dangling OUTPUT gate exists name WireX

Status: Open.

#10 In CIDARLAB/NetlistSynthesizer;

· bder opened on Jul 22, 2014

Change runABC to accept filepath instead of file name (esp for Blif files)

enhancement

Status: Open.

#6 In CIDARLAB/NetlistSynthesizer;

· PrashantVaidyanathan opened on May 7, 2014

Parse Structural Verilog to Netlist has issues with multiple outputs.

bug

Status: Open.

#5 In CIDARLAB/NetlistSynthesizer;

· PrashantVaidyanathan opened on Apr 28, 2014