This project is my attempt to explore how computers work fundamentally at the gate level.
I aim to design and build a fully functional 8-bit CPU from scratch.
Before simulation, each module is designed conceptually using hand-drawn block diagrams and written reasoning to validate the logic flow through mental simulation and small example cases. The block diagram is then refined into a rough structural, gate-level representation before being implemented, debugged, and rigorously tested in digital logic simulators such as Logisim Evolution and Falstad. Where possible, I explore multiple design approaches to achieve the same functionality, comparing behavior, complexity, and design trade-offs before finalizing an implementation.
- Clock Module
- Registers
- Bus System
- ALU
- RAM
- Address Decode Logic
- Manually Programmable RAM
- Programmable_RAM_Stored Program Execution
- Program Counter
- Programmable ROM - Hex Display
- Programmable ROM - Decimal Display
- System Integration
- Stored Micro-Program Control
- Fetch Decode Execute Control
Each module will have its own folder containing:
- A dedicated README.md explaining design, features, and usage
- Images of schematics, simulations, and hardware builds
- Understand computation from the ground up
- Document the full design and build process
- Share schematics, notes, and experiments for others to learn from
Translating all modules into Verilog and eventually implementing the entire machine.
