revert back to runnable project

Author: outercloudstudio

src/main/scala/RISCV/Main.scala

@@ -30,21 +30,6 @@ class Main() extends Module {
 
     val memory = SRAM(1024, UInt(32.W), 2, 1, 0);
 
-    // Set up Program Counter
-
-    // Set up RAM
-    /* 
-     * 32-bit width
-     * 1024 entries
-     * 
-     */
-
-    val RAM = Module(new RAM())
-    RAM.io.enable := false.B
-    RAM.io.write := false.B
-    RAM.io.addr := 0.U(10.W)
-    RAM.io.data_in := 0.U(32.W)
-
     // Set up register file
     val registers = Module(new Registers())
     // Default connections for register file inputs
@@ -303,168 +288,6 @@ class Main() extends Module {
                 }
             }
         }
-        is ("b0000000_100_01100_11".U) {
-            // XOR instruction https://msyksphinz-self.github.io/riscv-isadoc/html/rvi.html#xor
-
-            // Get additional fields from decoder
-            val rd = decoder.io.rd
-            val rs1 = decoder.io.rs1
-            val rs2 = decoder.io.rs2
-
-            // Execute XOR: x[rd] = x[rs1] ^ x[rs2]
-            
-            // Read rs1 and rs2 values
-            regFile.io.read_addr_A := rs1
-            val rs1_value = regFile.io.out_A
-            regFile.io.read_addr_B := rs2
-            val rs2_value = regFile.io.out_B
-
-            // Set up ALU
-            alu.io.operation := "b0101".U // XOR operation
-            alu.io.signed := false.B
-            alu.io.a := rs1_value
-            alu.io.b := rs2_value
-            val alu_result = alu.io.output
-
-            // Write result to rd
-            regFile.io.write_addr := rd
-            regFile.io.write_enable := true.B
-            regFile.io.in := alu_result
-        }
-        is ("b00000_00_101_01100_11".U) {
-            // SRL instruction https://msyksphinz-self.github.io/riscv-isadoc/html/rvi.html#srl
-
-            // Get additional fields from decoder
-            val rd = decoder.io.rd
-            val rs1 = decoder.io.rs1
-            val rs2 = decoder.io.rs2
-
-            // Execute SRL: x[rd] = x[rs1] >>u x[rs2]
-
-            // Read rs1 and rs2 values
-            regFile.io.read_addr_A := rs1
-            val rs1_value = regFile.io.out_A
-            regFile.io.read_addr_B := rs2
-            val rs2_value = Cat(Fill(27,0.U), regFile.io.out_B(5,0))
-
-            // Set up ALU
-            alu.io.operation := "b1000".U // Logical right shift operation
-            alu.io.signed := false.B
-            alu.io.a := rs1_value
-            alu.io.b := rs2_value
-            val alu_result = alu.io.output
-
-            regFile.io.write_addr := rd
-            regFile.io.write_enable := true.B
-            regFile.io.in := alu_result
-        }
-        is ("b01000_00_101_01100_11".U) {
-            // SRA instruction https://msyksphinz-self.github.io/riscv-isadoc/html/rvi.html#sra
-
-            // Get additional fields from decoder
-            val rd = decoder.io.rd
-            val rs1 = decoder.io.rs1
-            val rs2 = decoder.io.rs2
-
-            // Execute SRL: x[rd] = x[rs1] >>u x[rs2]
-
-            // Read rs1 and rs2 values
-            regFile.io.read_addr_A := rs1
-            val rs1_value = regFile.io.out_A
-            regFile.io.read_addr_B := rs2
-            val rs2_value = Cat(Fill(27,0.U), regFile.io.out_B(5,0))
-
-            // Set up ALU
-            alu.io.operation := "b1001".U // Logical right shift operation
-            alu.io.signed := false.B
-            alu.io.a := rs1_value
-            alu.io.b := rs2_value
-            val alu_result = alu.io.output
-
-            regFile.io.write_addr := rd
-            regFile.io.write_enable := true.B
-            regFile.io.in := alu_result        
-        }
-        is ("b00000_00_110_01100_11".U) {
-            // OR instruction https://msyksphinz-self.github.io/riscv-isadoc/html/rvi.html#or
-
-            // Get additional fields from decoder
-            val rd = decoder.io.rd
-            val rs1 = decoder.io.rs1
-            val rs2 = decoder.io.rs2
-
-            // Execute OR: x[rd] = x[rs1] | x[rs2]
-
-            // Read rs1 and rs2 values
-            regFile.io.read_addr_A := rs1
-            val rs1_value = regFile.io.out_A
-            regFile.io.read_addr_B := rs2
-            val rs2_value = regFile.io.out_B
-
-            // Set up ALU
-            alu.io.operation := "b0100".U
-            alu.io.signed := false.B
-            alu.io.a := rs1_value
-            alu.io.b := rs2_value
-            val alu_result = alu.io.output
-
-            regFile.io.write_addr := rd
-            regFile.io.write_enable := true.B
-            regFile.io.in := alu_result
-        }
-        is ("b00000_00_111_01100_11".U) {
-            // AND instruction https://msyksphinz-self.github.io/riscv-isadoc/html/rvi.html#and
-
-            // Get additional fields from decoder
-            val rd = decoder.io.rd
-            val rs1 = decoder.io.rs1
-            val rs2 = decoder.io.rs2
-
-            // Execute AND: x[rd] = x[rs1] & x[rs2]
-
-            // Read rs1 and rs2 values
-            regFile.io.read_addr_A := rs1
-            val rs1_value = regFile.io.out_A
-            regFile.io.read_addr_B := rs2
-            val rs2_value = regFile.io.out_B
-
-            // Set up ALU
-            alu.io.operation := "b0011".U
-            alu.io.signed := false.B
-            alu.io.a := rs1_value
-            alu.io.b := rs2_value
-            val alu_result = alu.io.output
-
-            regFile.io.write_addr := rd
-            regFile.io.write_enable := true.B
-            regFile.io.in := alu_result
-        }
-        is ("b000_00000_11".U) {
-            // LB instruction https://msyksphinz-self.github.io/riscv-isadoc/html/rvi.html#lb
-
-            // Get additional fields from decoder
-            val rd = decoder.io.rd
-            val rs1 = decoder.io.rs1
-            val immediate = decoder.io.immediate
-
-            // Execute LB: x[rd] = sext(M[x[rs1] + sext(offset)][7:0])
-
-            // Read rs1 and rs2 values
-            regFile.io.read_addr_A := rs1
-            val rs1_value = regFile.io.out_A
-
-            // Sign extend offset
-            val sext_offset = Cat(Fill(20, immediate(11)), immediate) // sext(offset)
-
-            // Intermediate
-            val _sum = rs1+sext_offset
-            // Final Sign-extension
-            val result = Cat(Fill(24, _sum(7)), _sum(7,0))
-
-            regFile.io.write_addr := rd
-            regFile.io.write_enable := true.B
-            regFile.io.in := result
-        }
     }
 }
 
@@ -478,4 +301,4 @@ object Main extends App {
     ),
     args = Array("--target-dir", "generated")
   )
-}
+}

src/main/scala/RISCV/PC.scala

@@ -7,7 +7,6 @@ import scala.math._
 class PC() extends Module {
    val io = IO(new Bundle {
        val pc_in = Input(UInt(32.W))
-       val enable = Input(Bool())
        val pc_out = Output(UInt(32.W))
    })
     val pc_reg = RegInit(0.U(32.W))