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perf vendor events riscv: fix lrw core PMU event mapping #217

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perf vendor events riscv: fix lrw core PMU event mapping #217

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15 changes: 0 additions & 15 deletions tools/perf/pmu-events/arch/riscv/lrw/lrw-core/branch.json
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Original file line number Diff line number Diff line change
Expand Up @@ -49,21 +49,6 @@
"EventCode": "0x00020009",
"BriefDescription": "Fetch queue empty"
},
{
"EventName": "FETCH_MCACHE_INVALIDATE",
"EventCode": "0x00040009",
"BriefDescription": "Fetch mopcache invalidate"
},
{
"EventName": "FETCH_MCACHE_ICACHE_SWITCH",
"EventCode": "0x00080009",
"BriefDescription": "Fetch mopcache instruction cache switch"
},
{
"EventName": "FETCH_MCACHE_ICACHE_SWITCH_PENALTY",
"EventCode": "0x00100009",
"BriefDescription": "Fetch mopcache instruction cache switch penalty"
},
{
"EventName": "BR_PRED_BTB_RGN_UPDATE_NREADY",
"EventCode": "0x00200009",
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5 changes: 0 additions & 5 deletions tools/perf/pmu-events/arch/riscv/lrw/lrw-core/general_cpu.json
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Original file line number Diff line number Diff line change
@@ -1,9 +1,4 @@
[
{
"EventName": "CID_WRITE_RETIRED",
"EventCode": "0x0000020b",
"BriefDescription": "CONTEXTIDR register write"
},
{
"EventName": "CPU_CYCLES",
"EventCode": "0x0000040b",
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24 changes: 12 additions & 12 deletions tools/perf/pmu-events/arch/riscv/lrw/lrw-core/l3cache.json
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Original file line number Diff line number Diff line change
@@ -1,32 +1,32 @@
[
{
"EventName": "L3_CACHE_ALLOCATE",
"EventName": "LL_CACHE_MISS_RD",
"EventCode": "0x00000104",
"BriefDescription": "Attributable L 3 data cache allocation without refill"
"BriefDescription": "Last level cache miss, read"
},
{
"EventName": "L3_CACHE_REFILL",
"EventName": "LL_CACHE_RD",
"EventCode": "0x00000204",
"BriefDescription": "Attributable L3 unified cache refill"
"BriefDescription": "Last level cache access, read"
},
{
"EventName": "L3_CACHE",
"EventName": "L3_CACHE_REFILL",
"EventCode": "0x00000404",
"BriefDescription": "Attributable Level 3 unified cache access"
"BriefDescription": "Attributable L3 unified cache refill"
},
{
"EventName": "LL_CACHE_RD",
"EventName": "L3_CACHE_RD",
"EventCode": "0x00000804",
"BriefDescription": "Last level cache access, read"
"BriefDescription": "L3 cache read"
},
{
"EventName": "LL_CACHE_MISS_RD",
"EventName": "L3_CACHE_ALLOCATE",
"EventCode": "0x00001004",
"BriefDescription": "Last level cache miss, read"
"BriefDescription": "Attributable L3 data cache allocation without refill"
},
{
"EventName": "L3_CACHE_RD",
"EventName": "L3_CACHE",
"EventCode": "0x00002004",
"BriefDescription": "L3 cache read"
"BriefDescription": "Attributable Level 3 unified cache access"
}
]
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