Branch if equals implementation #27
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TheDeepestSpace
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Apr 5, 2025
TheDeepestSpace
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TheDeepestSpace
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TheDeepestSpace
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TheDeepestSpace
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TheDeepestSpace
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TheDeepestSpace
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src/fetch.sv
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| IDLE: pc_cur = pc_cur; | ||
| INCREMENT_PC: pc_cur = pc_cur + 32'h4; | ||
| JUMP_PC: pc_cur = pc_cur + saved_imm_reg; | ||
| default: pc_cur = 32'hxxxxxxxx; |
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note sure what our protocol is on handing there
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I think we should look into adding SVLint to our pipeline here -- https://github.com/dalance/svlint. I think it also has direct test editor support. I would really like us to have checks for exhaustive case statements especially as the codebase grows.
TheDeepestSpace
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I've rewritten fetch module into an FSM since i think it better fits into the pipelined system as opposed to the initial implementation that was tageting single-cycle processor.
TheDeepestSpace
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Jun 2, 2025
looks like i mixed up the meanings of pc_src in fetch_tb bench
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This PR contains the implementation of
beqinstruction. It is built off of the unconditional branching setup in #20 .This is a significant PR since it starts to integrate together our main modules:
InstructionDecode,ControlFSM,fetch, andALU.This is the first attempt at integration and only wires up the signals necessary for
beq.This is a pretty large PR, so I would not be opposed to breaking it up into smaller chunks, especially since there have been quite a bit of peripheral changes.
Notable changes aside from the integration in
top.v:ALUOpsignal as per the bookPCUpdateis set toTRUEunconditionallyPCSrcsignal to pick the next PC valueImmExtfrom Instruction Decode for consumption by the Fetch modulebeqcan be performed in one cycle