Synthesized VHDL code for 16-bit ALU, capable of carrying out 4 operations: addition, subtraction, bitwise-NAND, bitwise-XOR, along with carry and zero flags for two input signals. Generated Digital Waveforms of the output of RTL simulation in Quartus for a coded testbench
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UdayGohil/Arithmetic_Logic_Unit
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Synthesized VHDL code for 16-bit ALU, capable of carrying out 4 operations: addition, subtraction, bitwise-NAND, bitwise-XOR, along with carry and zero flags for two input signals
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