analogdevicesinc · AndrDragomir · Aug 25, 2025 · Aug 25, 2025
@@ -72,6 +72,7 @@ Contents
    ADRV9009 <adrv9009/index>
    ADRV9009-ZU11EG <adrv9009zu11eg/index>
    ADRV9026 <adrv9026/index>
+   ADRV903x <adrv903x/index>
    ADRV904x <adrv904x/index>
    ADRV9361Z7035 <adrv9361z7035/index>
    ADRV9364Z7020 <adrv9364z7020/index>

@@ -0,0 +1,7 @@
+####################################################################################
+## Copyright (c) 2018 - 2025 Analog Devices, Inc.
+### SPDX short identifier: BSD-1-Clause
+## Auto-generated, do not modify!
+####################################################################################
+
+include ../scripts/project-toplevel.mk
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+# ADRV903X HDL Project
+
+- Evaluation board product page: [EVAL-ADRV903x](https://www.analog.com/eval-adrv903x)
+- System documentation: https://wiki.analog.com/resources/eval/user-guides/adrv903x/quickstart/zynqmp
+- HDL project documentation: https://analogdevicesinc.github.io/hdl/projects/adrv903x/index.html
+- Evaluation board VADJ: 1.8V
+
+## Supported parts
+
+| Part name                                    | Description                             |
+|----------------------------------------------|-----------------------------------------|
+| [ADRV903x](https://www.analog.com/adrv9030)  | 8T8R2OR SoC, 400 MHz iBW RF Transceiver |
+
+## Building the project
+
+Please enter the folder for the FPGA carrier you want to use and read the README.md.
@@ -0,0 +1,41 @@
+####################################################################################
+## Copyright (c) 2018 - 2025 Analog Devices, Inc.
+### SPDX short identifier: BSD-1-Clause
+## Auto-generated, do not modify!
+####################################################################################
+
+PROJECT_NAME := adrv903x_zcu102
+
+M_DEPS += ../common/adrv903x_bd.tcl
+M_DEPS += ../../scripts/adi_pd.tcl
+M_DEPS += ../../common/zcu102/zcu102_system_constr.xdc
+M_DEPS += ../../common/zcu102/zcu102_system_bd.tcl
+M_DEPS += ../../common/xilinx/data_offload_bd.tcl
+M_DEPS += ../../common/xilinx/adi_fir_filter_constr.xdc
+M_DEPS += ../../common/xilinx/adi_fir_filter_bd.tcl
+M_DEPS += ../../../library/util_hbm/scripts/adi_util_hbm.tcl
+M_DEPS += ../../../library/util_cdc/sync_bits.v
+M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
+M_DEPS += ../../../library/common/util_pulse_gen.v
+M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/common/ad_bus_mux.v
+
+LIB_DEPS += axi_clkgen
+LIB_DEPS += axi_dmac
+LIB_DEPS += axi_sysid
+LIB_DEPS += data_offload
+LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc
+LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac
+LIB_DEPS += jesd204/axi_jesd204_rx
+LIB_DEPS += jesd204/axi_jesd204_tx
+LIB_DEPS += jesd204/jesd204_rx
+LIB_DEPS += jesd204/jesd204_tx
+LIB_DEPS += sysid_rom
+LIB_DEPS += util_do_ram
+LIB_DEPS += util_hbm
+LIB_DEPS += util_pack/util_cpack2
+LIB_DEPS += util_pack/util_upack2
+LIB_DEPS += xilinx/axi_adxcvr
+LIB_DEPS += xilinx/util_adxcvr
+
+include ../../scripts/project-xilinx.mk
@@ -0,0 +1,69 @@
+<!-- no_no_os -->
+
+# ADRV903X/ZCU102 HDL Project
+
+- VADJ with which it was tested in hardware: 1.8V
+
+## Building the project
+
+The parameters configurable through the `make` command, can be found below, as well as in the **system_project.tcl** file; it contains the default configuration.
+
+```
+cd projects/adrv903x/zcu102
+make
+```
+
+All of the RX/TX link modes can be found in the [ADRV9030 data sheet](https://www.analog.com/media/en/technical-documentation/data-sheets/adrv9030.pdf). We offer support for only a few of them.
+
+If other configurations are desired, then the parameters from the HDL project (see below) need to be changed, as well as the Linux/no-OS project configurations.
+
+**Warning**: The JESD link mode is configured using the ADRV903x plugin from [ACE](https://wiki.analog.com/resources/tools-software/ace) application. The device tree is the same, regardless of the configuration: [zynqmp-zcu102-rev10-adrv903x.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-adrv903x.dts)
+
+The overwritable parameters from the environment:
+
+- JESD_MODE - link layer encoder mode used;
+  - 8B10B - 8b10b link layer defined in JESD204B
+  - 64B66B - 64b66b link layer defined in JESD204C
+- ORX_ENABLE : Additional data path for RX-OS
+  - 0 - Disabled (used for profiles with RX-OS disabled)
+  - 1 - Enabled (used for profiles with RX-OS enabled)
+- [RX/TX]_LANE_RATE - lane rate of the [RX/TX] link
+- [RX/TX/RX_OS]_JESD_M - [RX/TX/RX_OS] number of converters per link
+- [RX/TX/RX_OS]_JESD_L - [RX/TX/RX_OS] number of lanes per link
+- [RX/TX/RX_OS]_JESD_S - [RX/TX/RX_OS] number of samples per converter per frame
+- [RX/TX/RX_OS]_JESD_NP - [RX/TX/RX_OS] number of bits per sample
+- [TX/RX/RX_OS]_TPL_WIDTH - [RX/TX/RX_OS] TPL data path width in bits
+- [RX/TX/RX_OS]_NUM_LINKS - [RX/TX/RX_OS] number of links
+
+### Example configurations
+
+#### Default configuration
+
+This specific command is equivalent to running `make` only:
+
+```
+make JESD_MODE=64B66B \
+RX_LANE_RATE=16.22 \
+TX_LANE_RATE=16.22 \
+ORX_ENABLE=1 \
+RX_NUM_LINKS=1 \
+TX_NUM_LINK=1 \
+RX_OS_NUM_LINKS=1 \
+RX_JESD_M=16 \
+RX_JESD_L=4 \
+RX_JESD_S=1 \
+RX_JESD_NP=16 \
+RX_TPL_WIDTH={} \
+RX_OS_JESD_M=8 \
+RX_OS_JESD_L=4 \
+RX_OS_JESD_S=1 \
+RX_OS_JESD_NP=16 \
+RX_OS_TPL_WIDTH={} \
+TX_JESD_M=16 \
+TX_JESD_L=8 \
+TX_JESD_S=1 \
+TX_JESD_NP=16 \
+TX_TPL_WIDTH={}
+```
+
+Corresponding device tree: [zynqmp-zcu102-rev10-adrv903x.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-adrv903x.dts)
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+###############################################################################
+## Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+## ADC FIFO depth in samples per converter
+set adc_fifo_samples_per_converter [expr 32*1024]
+## DAC FIFO depth in samples per converter
+set dac_fifo_samples_per_converter [expr 32*1024]
+
+source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl
+source $ad_hdl_dir/projects/scripts/adi_pd.tcl
+
+set mem_init_sys_path [get_env_param ADI_PROJECT_DIR ""]mem_init_sys.txt;
+
+#system ID
+ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 10
+ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/$mem_init_sys_path"
+ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 10
+
+set sys_cstring "JESD_MODE=$ad_project_params(JESD_MODE)\
+ORX_ENABLE=$ad_project_params(ORX_ENABLE)\
+RX:RATE=$ad_project_params(RX_LANE_RATE)\
+M=$ad_project_params(RX_JESD_M)\
+L=$ad_project_params(RX_JESD_L)\
+S=$ad_project_params(RX_JESD_S)\
+NP=$ad_project_params(RX_JESD_NP)\
+TPL_WIDTH=$ad_project_params(RX_TPL_WIDTH)\
+LINKS=$ad_project_params(RX_NUM_LINKS)\
+TX:RATE=$ad_project_params(TX_LANE_RATE)\
+M=$ad_project_params(TX_JESD_M)\
+L=$ad_project_params(TX_JESD_L)\
+S=$ad_project_params(TX_JESD_S)\
+NP=$ad_project_params(TX_JESD_NP)\
+TPL_WIDTH=$ad_project_params(TX_TPL_WIDTH)\
+LINKS=$ad_project_params(TX_NUM_LINKS)\
+ORX:RATE=$ad_project_params(RX_LANE_RATE)\
+M=$ad_project_params(RX_OS_JESD_M)\
+L=$ad_project_params(RX_OS_JESD_L)\
+S=$ad_project_params(RX_OS_JESD_S)\
+NP=$ad_project_params(RX_OS_JESD_NP)\
+TPL_WIDTH=$ad_project_params(RX_OS_TPL_WIDTH)\
+LINKS=$ad_project_params(RX_OS_NUM_LINKS)"
+
+sysid_gen_sys_init_file $sys_cstring 10
+
+source ../common/adrv903x_bd.tcl
+
+ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {300}