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Fixing axi_dmac and spi_engine parsing errors for Questasim. #1981

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Fixing axi_dmac and spi_engine parsing errors for Questasim. #1981

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98f0a9b
library/axi_dmac: Fix parsing error for bitfield selections.
Villyam Dec 16, 2025
bdd6258
library/spi_engine/spi_engine_execution: Fix register declaration.
Villyam Dec 16, 2025
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6 changes: 3 additions & 3 deletions library/axi_dmac/axi_dmac_regmap.v
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2014-2025 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
Expand Down Expand Up @@ -266,8 +266,8 @@ module axi_dmac_regmap #(
9'h10f: up_rdata <= DISABLE_DEBUG_REGISTERS ? 32'h00 : dbg_status;
9'h110: up_rdata <= DISABLE_DEBUG_REGISTERS ? 32'h00 : dbg_ids0;
9'h111: up_rdata <= DISABLE_DEBUG_REGISTERS ? 32'h00 : dbg_ids1;
9'h126: up_rdata <= (HAS_ADDR_HIGH && !DISABLE_DEBUG_REGISTERS) ? dbg_dest_addr[DMA_AXI_ADDR_WIDTH-1:32] : 32'h00;
9'h127: up_rdata <= (HAS_ADDR_HIGH && !DISABLE_DEBUG_REGISTERS) ? dbg_src_addr[DMA_AXI_ADDR_WIDTH-1:32] : 32'h00;
9'h126: up_rdata <= (HAS_ADDR_HIGH && !DISABLE_DEBUG_REGISTERS) ? dbg_dest_addr[DMA_AXI_ADDR_WIDTH-1:HAS_ADDR_HIGH*32] : 32'h00;
9'h127: up_rdata <= (HAS_ADDR_HIGH && !DISABLE_DEBUG_REGISTERS) ? dbg_src_addr[DMA_AXI_ADDR_WIDTH-1:HAS_ADDR_HIGH*32] : 32'h00;
default: up_rdata <= up_rdata_request;
endcase
end
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14 changes: 7 additions & 7 deletions library/axi_dmac/axi_dmac_regmap_request.v
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2018-2024 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2018-2025 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
Expand Down Expand Up @@ -194,11 +194,11 @@ module axi_dmac_regmap_request #(
9'h106: up_dma_x_length[DMA_LENGTH_WIDTH-1:DMA_LENGTH_ALIGN] <= up_wdata[DMA_LENGTH_WIDTH-1:DMA_LENGTH_ALIGN];
9'h124:
if (HAS_ADDR_HIGH) begin
up_dma_dest_address[DMA_AXI_ADDR_WIDTH-1:32] <= up_wdata[ADDR_HIGH_MSB:0];
up_dma_dest_address[DMA_AXI_ADDR_WIDTH-1:HAS_ADDR_HIGH*32] <= up_wdata[ADDR_HIGH_MSB:0];
end
9'h125:
if (HAS_ADDR_HIGH) begin
up_dma_src_address[DMA_AXI_ADDR_WIDTH-1:32] <= up_wdata[ADDR_HIGH_MSB:0];
up_dma_src_address[DMA_AXI_ADDR_WIDTH-1:HAS_ADDR_HIGH*32] <= up_wdata[ADDR_HIGH_MSB:0];
end
endcase
end
Expand Down Expand Up @@ -232,9 +232,9 @@ module axi_dmac_regmap_request #(
end
9'h117: up_rdata <= request_flock_stride;
9'h11f: up_rdata <= {request_sg_address[ADDR_LOW_MSB:BYTES_PER_BEAT_WIDTH_SG],{BYTES_PER_BEAT_WIDTH_SG{1'b0}}};
9'h124: up_rdata <= (HAS_ADDR_HIGH && HAS_DEST_ADDR) ? up_dma_dest_address[DMA_AXI_ADDR_WIDTH-1:32] : 32'h00;
9'h125: up_rdata <= (HAS_ADDR_HIGH && HAS_SRC_ADDR) ? up_dma_src_address[DMA_AXI_ADDR_WIDTH-1:32] : 32'h00;
9'h12f: up_rdata <= HAS_ADDR_HIGH ? request_sg_address[DMA_AXI_ADDR_WIDTH-1:32] : 32'h00;
9'h124: up_rdata <= (HAS_ADDR_HIGH && HAS_DEST_ADDR) ? up_dma_dest_address[DMA_AXI_ADDR_WIDTH-1:HAS_ADDR_HIGH*32] : 32'h00;
9'h125: up_rdata <= (HAS_ADDR_HIGH && HAS_SRC_ADDR) ? up_dma_src_address[DMA_AXI_ADDR_WIDTH-1:HAS_ADDR_HIGH*32] : 32'h00;
9'h12f: up_rdata <= HAS_ADDR_HIGH ? request_sg_address[DMA_AXI_ADDR_WIDTH-1:HAS_ADDR_HIGH*32] : 32'h00;
default: up_rdata <= 32'h00;
endcase
end
Expand Down Expand Up @@ -342,7 +342,7 @@ module axi_dmac_regmap_request #(
9'h11f: up_dma_sg_address[ADDR_LOW_MSB:BYTES_PER_BEAT_WIDTH_SG] <= up_wdata[ADDR_LOW_MSB:BYTES_PER_BEAT_WIDTH_SG];
9'h12f:
if (HAS_ADDR_HIGH) begin
up_dma_sg_address[DMA_AXI_ADDR_WIDTH-1:32] <= up_wdata[ADDR_HIGH_MSB:0];
up_dma_sg_address[DMA_AXI_ADDR_WIDTH-1:HAS_ADDR_HIGH*32] <= up_wdata[ADDR_HIGH_MSB:0];
end
endcase
end
Expand Down
3 changes: 2 additions & 1 deletion library/spi_engine/spi_engine_execution/spi_engine_execution_shiftreg.v
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Expand Up @@ -226,14 +226,15 @@ module spi_engine_execution_shiftreg #(

end

reg [3:0] last_sdi_bit_m = 4'b0;

assign sdi_data = sdi_data_latch;
assign last_sdi_bit = last_sdi_bit_r;
assign echo_last_bit = !last_sdi_bit_m[3] && last_sdi_bit_m[2];

// sdi_data_valid is synchronous to SPI clock, so synchronize the
// last_sdi_bit to SPI clock

reg [3:0] last_sdi_bit_m = 4'b0;
always @(posedge clk) begin
if (cs_activate) begin
last_sdi_bit_m <= 4'b0;
Expand Down
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